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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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-FL080000 -FF1HC32F460_otp -FS13000C00 -FL13FC -FP0($$Device:HC32F460KETA$FlashARM\HC32F460_512K.FLM) -FP1($$Device:HC32F460KETA$FlashARM\HC32F460_otp.FLM)) + 0 + $$Device:HC32F460KETA$Device\Include\HC32F460KETA.h + + + + + + + + + + $$Device:HC32F460KETA$SVD\HC32F460KETA.svd + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\ + GateWay + 1 + 0 + 1 + 1 + 1 + .\output\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + D:\Keil5\ARM\ARMCC\bin\fromelf.exe --bin -o .\output\app.bin .\output\GateWay.axf + fromelf --bin -o "$L@L.bin" "#L" + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 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0x00000000 + 0x1FFF8000 + + .\output\debug\GateWay.sct + + + --keep=*Handler + + + + + + + + common + + + startup_hc32f460.s + 2 + .\startup_hc32f460.s + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + system_hc32f460.c + 1 + ..\..\..\mcu\common\system_hc32f460.c + + + + + User + + + main.c + 1 + ..\source\User\Src\main.c + + + bsp.c + 1 + ..\source\User\Src\bsp.c + + + CatOneTask.c + 1 + ..\source\User\Src\CatOneTask.c + + + RS485Task.c + 1 + ..\source\User\Src\RS485Task.c + + + LoraTask.c + 1 + ..\source\User\Src\LoraTask.c + + + Public.c + 1 + ..\source\User\Src\Public.c + + + DebugCmd.c + 1 + ..\source\User\Src\DebugCmd.c + + + spiflash.c + 1 + ..\source\User\Src\spiflash.c + + + update_protocol.c + 1 + ..\source\User\Src\update_protocol.c + + + ringbuffer.c + 1 + ..\source\User\Src\ringbuffer.c + + + protocol.c + 1 + ..\source\User\Src\protocol.c + + + utils.c + 1 + ..\source\User\Src\utils.c + + + + + driver + + + hc32f460_utility.c + 1 + ..\..\..\driver\src\hc32f460_utility.c + + + hc32f460_pwc.c + 1 + ..\..\..\driver\src\hc32f460_pwc.c + + + hc32f460_interrupts.c + 1 + ..\..\..\driver\src\hc32f460_interrupts.c + + + hc32f460_clk.c + 1 + ..\..\..\driver\src\hc32f460_clk.c + + + hc32f460_icg.c + 1 + ..\..\..\driver\src\hc32f460_icg.c + + + hc32f460_efm.c + 1 + ..\..\..\driver\src\hc32f460_efm.c + + + hc32f460_sram.c + 1 + ..\..\..\driver\src\hc32f460_sram.c + + + hc32f460_gpio.c + 1 + ..\..\..\driver\src\hc32f460_gpio.c + + + hc32f460_usart.c + 1 + ..\..\..\driver\src\hc32f460_usart.c + + + hc32f460_swdt.c + 1 + ..\..\..\driver\src\hc32f460_swdt.c + + + hc32f460_ots.c + 1 + ..\..\..\driver\src\hc32f460_ots.c + + + hc32f460_spi.c + 1 + ..\..\..\driver\src\hc32f460_spi.c + + + hc32f460_exint_nmi_swi.c + 1 + ..\..\..\driver\src\hc32f460_exint_nmi_swi.c + + + hc32f460_sdioc.c + 1 + ..\..\..\driver\src\hc32f460_sdioc.c + + + hc32f460_dmac.c + 1 + ..\..\..\driver\src\hc32f460_dmac.c + + + hc32f460_rtc.c + 1 + ..\..\..\driver\src\hc32f460_rtc.c + + + hc32f460_adc.c + 1 + ..\..\..\driver\src\hc32f460_adc.c + + + + + Debug + + + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + Debug.c + 1 + ..\source\Module\Debug\Debug.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + SdCard + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + sd_card.c + 1 + ..\source\Module\SDCard\sd_card.c + + + sdmmc_cmd.c + 1 + ..\source\Module\SDCard\sdmmc_cmd.c + + + + + FatFS + + + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + sd_diskio.c + 1 + ..\source\Module\FatFS\source\sd_diskio.c + + + diskio.c + 1 + ..\source\Module\FatFS\source\diskio.c + + + ff.c + 1 + ..\source\Module\FatFS\source\ff.c + + + ffsystem.c + 1 + ..\source\Module\FatFS\source\ffsystem.c + + + + + sx127x + + + sx127x.c + 1 + ..\source\Module\SX127x\sx127x.c + + + + + Readme + + + ::CMSIS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::RTOS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_MC_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\Network\Net_Config.c + + + + + + RTE\Network\Net_Config_ETH_0.h + + + + + + RTE\Network\Net_Config_TCP.h + + + + + + RTE\RTOS\board.c + + + + + + + + + RTE\RTOS\rtconfig.h + + + + + + + + + + + + + + GateWay + 0 + 1 + + + + + diff --git a/Project/GateWay/MDK/HC32F460xE.sct b/Project/GateWay/MDK/HC32F460xE.sct new file mode 100644 index 0000000..fbe6980 --- /dev/null +++ b/Project/GateWay/MDK/HC32F460xE.sct @@ -0,0 +1,21 @@ +; **************************************************************** +; Scatter-Loading Description File +; **************************************************************** +LR_IROM1 0x00008000 0x00078000 { ; load region size_region + ER_IROM1 0x00008000 0x00078000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x1FFF8000 UNINIT 0x00000008 { ; RW data + *(.bss.noinit) + } + RW_IRAM2 0x1FFF8008 0x00026FF8 { ; RW data + .ANY (+RW +ZI) + .ANY (RAMCODE) + } + RW_IRAMB 0x200F0000 0x00001000 { ; RW data + .ANY (+RW +ZI) + } +} \ No newline at end of file diff --git a/Project/GateWay/MDK/JLinkSettings.ini b/Project/GateWay/MDK/JLinkSettings.ini new file mode 100644 index 0000000..b06dcf5 --- /dev/null +++ b/Project/GateWay/MDK/JLinkSettings.ini @@ -0,0 +1,35 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="Cortex-M4" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/Project/GateWay/MDK/RTE/File_System/FS_Config.c b/Project/GateWay/MDK/RTE/File_System/FS_Config.c new file mode 100644 index 0000000..21f42a7 --- /dev/null +++ b/Project/GateWay/MDK/RTE/File_System/FS_Config.c @@ -0,0 +1,78 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config.c + * Purpose: File System Configuration + * Rev.: V6.3.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// FAT File System +// Define FAT File System parameters + +// Number of open files <1-16> +// Define number of files that can be opened at the same time. +// Default: 4 +#define FAT_MAX_OPEN_FILES 4 + +// + +// Embedded File System +// Define Embedded File System parameters + +// Number of open files <1-16> +// Define number of files that can be opened at the same time. +// Default: 4 +#define EFS_MAX_OPEN_FILES 4 + +// + +// Initial Current Drive <0=>F0: <1=>F1: +// <2=>M0: <3=>M1: +// <4=>N0: <5=>N1: +// <6=>R0: <9=>R1: +// <7=>U0: <8=>U1: +// Set initial setting for current drive. Current drive is used for File System functions +// that are invoked with the "" string and can be altered anytime during run-time. +#define FS_INITIAL_CDRIVE 2 + +#include "RTE_Components.h" + +#ifdef RTE_FileSystem_Drive_RAM_0 +#include "FS_Config_RAM_0.h" +#endif +#ifdef RTE_FileSystem_Drive_RAM_1 +#include "FS_Config_RAM_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_NOR_0 +#include "FS_Config_NOR_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NOR_1 +#include "FS_Config_NOR_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_NAND_0 +#include "FS_Config_NAND_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NAND_1 +#include "FS_Config_NAND_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_MC_0 +#include "FS_Config_MC_0.h" +#endif +#ifdef RTE_FileSystem_Drive_MC_1 +#include "FS_Config_MC_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_USB_0 +#include "FS_Config_USB_0.h" +#endif +#ifdef RTE_FileSystem_Drive_USB_1 +#include "FS_Config_USB_1.h" +#endif + +#include "fs_config.h" diff --git a/Project/GateWay/MDK/RTE/File_System/FS_Config_MC_0.h b/Project/GateWay/MDK/RTE/File_System/FS_Config_MC_0.h new file mode 100644 index 0000000..b04116e --- /dev/null +++ b/Project/GateWay/MDK/RTE/File_System/FS_Config_MC_0.h @@ -0,0 +1,55 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System:Drive + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config_MC_0.h + * Purpose: File System Configuration for Memory Card Drive + * Rev.: V6.2.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Memory Card Drive 0 +// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" +#define MC0_ENABLE 1 + +// Connect to hardware via Driver_MCI# <0-255> +// Select driver control block for hardware interface +#define MC0_MCI_DRIVER 0 + +// Connect to hardware via Driver_SPI# <0-255> +// Select driver control block for hardware interface when in SPI mode +#define MC0_SPI_DRIVER 0 + +// Memory Card Interface Mode <0=>Native <1=>SPI +// Native uses a SD Bus with up to 8 data lines, CLK, and CMD +// SPI uses 2 data lines (MOSI and MISO), SCLK and CS +#define MC0_SPI 0 + +// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Drive Cache stores data sectors and may be increased to speed-up +// file read/write operations on this drive (default: 4 KB) +#define MC0_CACHE_SIZE 4 + +// Locate Drive Cache and Drive Buffer +// Some microcontrollers support DMA only in specific memory areas and +// require to locate the drive buffers at a fixed address. +#define MC0_CACHE_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Set buffer base address to RAM areas that support DMA with the drive. +#define MC0_CACHE_ADDR 0x7FD00000 + +// +// Filename Cache Size <0-1000000> +// Define number of cached file or directory names. +// 48 bytes of RAM is required for each cached name. +#define MC0_NAME_CACHE_SIZE 0 + +// Use FAT Journal +// Protect File Allocation Table and Directory Entries for +// fail-safe operation. +#define MC0_FAT_JOURNAL 0 + +// diff --git a/Project/GateWay/MDK/RTE/File_System/FS_Debug.c b/Project/GateWay/MDK/RTE/File_System/FS_Debug.c new file mode 100644 index 0000000..38e37f5 --- /dev/null +++ b/Project/GateWay/MDK/RTE/File_System/FS_Debug.c @@ -0,0 +1,50 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Debug.c + * Purpose: File System Debug Configuration + * Rev.: V1.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// File System Debug +// Enable File System event recording +#define FS_DEBUG_EVR_ENABLE 0 + +// Core Management <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsCore: Core Management event recording +#define FS_DEBUG_EVR_CORE 1 + +// FAT File System <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsFAT: FAT File System event recording +#define FS_DEBUG_EVR_FAT 1 + +// EFS File System <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsEFS: EFS File System event recording +#define FS_DEBUG_EVR_EFS 1 + +// I/O Control Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsIOC: I/O Control Interface event recording +#define FS_DEBUG_EVR_IOC 1 + +// NAND Flash Translation Layer <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsNFTL: NAND Flash Translation Layer event recording +#define FS_DEBUG_EVR_NFTL 1 + +// NAND Device Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsNAND: NAND Device Interface event recording +#define FS_DEBUG_EVR_NAND 1 + +// Memory Card MCI <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsMcMCI: Memory Card MCI event recording +#define FS_DEBUG_EVR_MC_MCI 1 + +// Memory Card SPI <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsMcSPI: Memory Card SPI event recording +#define FS_DEBUG_EVR_MC_SPI 1 + +// + +#include "fs_debug.h" diff --git a/Project/GateWay/MDK/RTE/Network/Net_Config.c b/Project/GateWay/MDK/RTE/Network/Net_Config.c new file mode 100644 index 0000000..f72bbaf --- /dev/null +++ b/Project/GateWay/MDK/RTE/Network/Net_Config.c @@ -0,0 +1,173 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config.c + * Purpose: Network Configuration + * Rev.: V7.1.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Network System Settings +// Global Network System definitions +// Local Host Name +// This is the name under which embedded host can be +// accessed on a local area network. +// Default: "my_host" +#define NET_HOST_NAME "my_host" + +// Memory Pool Size <1536-262144:4> +// This is the size of a memory pool in bytes. Buffers for +// network packets are allocated from this memory pool. +// Default: 12000 bytes +#define NET_MEM_POOL_SIZE 12000 + +// Start System Services +// If enabled, the system will automatically start server services +// (HTTP, FTP, TFTP server, ...) when initializing the network system. +// Default: Enabled +#define NET_START_SERVICE 1 + +// OS Resource Settings +// These settings are used to optimize usage of OS resources. +// Core Thread Stack Size <512-65535:4> +// Default: 1024 bytes +#define NET_THREAD_STACK_SIZE 1024 + +// Core Thread Priority +#define NET_THREAD_PRIORITY osPriorityNormal + +// +// + +//------------- <<< end of configuration section >>> --------------------------- + +#include "RTE_Components.h" + +#ifdef RTE_Network_Interface_ETH_0 +#include "Net_Config_ETH_0.h" +#endif +#ifdef RTE_Network_Interface_ETH_1 +#include "Net_Config_ETH_1.h" +#endif + +#ifdef RTE_Network_Interface_WiFi_0 +#include "Net_Config_WiFi_0.h" +#endif + +#ifdef RTE_Network_Interface_WiFi_1 +#include "Net_Config_WiFi_1.h" +#endif + +#ifdef RTE_Network_Interface_PPP +#include "Net_Config_PPP.h" +#endif + +#ifdef RTE_Network_Interface_SLIP +#include "Net_Config_SLIP.h" +#endif + +#ifdef RTE_Network_Socket_UDP +#include "Net_Config_UDP.h" +#endif +#ifdef RTE_Network_Socket_TCP +#include "Net_Config_TCP.h" +#endif +#ifdef RTE_Network_Socket_BSD +#include "Net_Config_BSD.h" +#endif + +#ifdef RTE_Network_Web_Server_RO +#include "Net_Config_HTTP_Server.h" +#endif +#ifdef RTE_Network_Web_Server_FS +#include "Net_Config_HTTP_Server.h" +#endif + +#ifdef RTE_Network_Telnet_Server +#include "Net_Config_Telnet_Server.h" +#endif + +#ifdef RTE_Network_TFTP_Server +#include "Net_Config_TFTP_Server.h" +#endif +#ifdef RTE_Network_TFTP_Client +#include "Net_Config_TFTP_Client.h" +#endif + +#ifdef RTE_Network_FTP_Server +#include "Net_Config_FTP_Server.h" +#endif +#ifdef RTE_Network_FTP_Client +#include "Net_Config_FTP_Client.h" +#endif + +#ifdef RTE_Network_DNS_Client +#include "Net_Config_DNS_Client.h" +#endif + +#ifdef RTE_Network_SMTP_Client +#include "Net_Config_SMTP_Client.h" +#endif + +#ifdef RTE_Network_SNMP_Agent +#include "Net_Config_SNMP_Agent.h" +#endif + +#ifdef RTE_Network_SNTP_Client +#include "Net_Config_SNTP_Client.h" +#endif + +#include "net_config.h" + +/** +\addtogroup net_genFunc +@{ +*/ +/** + \fn void net_sys_error (NET_ERROR error) + \ingroup net_cores + \brief Network system error handler. +*/ +void net_sys_error (NET_ERROR error) { + /* This function is called when a fatal error is encountered. */ + /* The normal program execution is not possible anymore. */ + + switch (error) { + case NET_ERROR_MEM_ALLOC: + /* Out of memory */ + break; + + case NET_ERROR_MEM_FREE: + /* Trying to release non existing memory block */ + break; + + case NET_ERROR_MEM_CORRUPT: + /* Memory Link pointer corrupted */ + /* More data written than the size of allocated memory block */ + break; + + case NET_ERROR_CONFIG: + /* Network configuration error detected */ + break; + + case NET_ERROR_UDP_ALLOC: + /* Out of UDP Sockets */ + break; + + case NET_ERROR_TCP_ALLOC: + /* Out of TCP Sockets */ + break; + + case NET_ERROR_TCP_STATE: + /* TCP State machine in undefined state */ + break; + } + + /* End-less loop */ + while (1); +} +/** +@} +*/ diff --git a/Project/GateWay/MDK/RTE/Network/Net_Config_ETH_0.h b/Project/GateWay/MDK/RTE/Network/Net_Config_ETH_0.h new file mode 100644 index 0000000..2fac34c --- /dev/null +++ b/Project/GateWay/MDK/RTE/Network/Net_Config_ETH_0.h @@ -0,0 +1,253 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Interface + * Copyright (c) 2004-2020 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_ETH_0.h + * Purpose: Network Configuration for ETH Interface + * Rev.: V7.3.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Ethernet Network Interface 0 +#define ETH0_ENABLE 1 + +// Connect to hardware via Driver_ETH# <0-255> +// Select driver control block for MAC and PHY interface +#define ETH0_DRIVER 0 + +// MAC Address +// Ethernet MAC Address in text representation +// Value FF-FF-FF-FF-FF-FF is not allowed, +// LSB of first byte must be 0 (an ethernet Multicast bit). +// Default: "1E-30-6C-A2-45-5E" +#define ETH0_MAC_ADDR "1E-30-6C-A2-45-5E" + +// VLAN +// Enable or disable Virtual LAN +#define ETH0_VLAN_ENABLE 0 + +// VLAN Identifier <1-4093> +// A unique 12-bit numeric value +// Default: 1 +#define ETH0_VLAN_ID 1 +// + +// IPv4 +// Enable IPv4 Protocol for Network Interface +#define ETH0_IP4_ENABLE 1 + +// IP Address +// Static IPv4 Address in text representation +// Default: "192.168.0.100" +#define ETH0_IP4_ADDR "192.168.0.100" + +// Subnet mask +// Local Subnet mask in text representation +// Default: "255.255.255.0" +#define ETH0_IP4_MASK "255.255.255.0" + +// Default Gateway +// IP Address of Default Gateway in text representation +// Default: "192.168.0.254" +#define ETH0_IP4_GATEWAY "192.168.0.254" + +// Primary DNS Server +// IP Address of Primary DNS Server in text representation +// Default: "8.8.8.8" +#define ETH0_IP4_PRIMARY_DNS "8.8.8.8" + +// Secondary DNS Server +// IP Address of Secondary DNS Server in text representation +// Default: "8.8.4.4" +#define ETH0_IP4_SECONDARY_DNS "8.8.4.4" + +// IP Fragmentation +// This option enables fragmentation of outgoing IP datagrams, +// and reassembling the fragments of incoming IP datagrams. +// Default: enabled +#define ETH0_IP4_FRAG_ENABLE 1 + +// MTU size <576-1500> +// Maximum Transmission Unit in bytes +// Default: 1500 +#define ETH0_IP4_MTU 1500 +// + +// ARP Address Resolution +// ARP cache and node address resolver settings +// Cache Table size <5-100> +// Number of cached MAC/IP addresses +// Default: 10 +#define ETH0_ARP_TAB_SIZE 10 + +// Cache Timeout in seconds <5-255> +// A timeout for cached hardware/IP addresses +// Default: 150 +#define ETH0_ARP_CACHE_TOUT 150 + +// Number of Retries <0-20> +// Number of Retries to resolve an IP address +// before ARP module gives up +// Default: 4 +#define ETH0_ARP_MAX_RETRY 4 + +// Resend Timeout in seconds <1-10> +// A timeout to resend the ARP Request +// Default: 2 +#define ETH0_ARP_RESEND_TOUT 2 + +// Send Notification on Address changes +// When this option is enabled, the embedded host +// will send a Gratuitous ARP notification at startup, +// or when the device IP address has changed. +// Default: Disabled +#define ETH0_ARP_NOTIFY 0 +// + +// IGMP Group Management +// Enable or disable Internet Group Management Protocol +#define ETH0_IGMP_ENABLE 0 + +// Membership Table size <2-50> +// Number of Groups this host can join +// Default: 5 +#define ETH0_IGMP_TAB_SIZE 5 +// + +// NetBIOS Name Service +// When this option is enabled, the embedded host can be +// accessed by its name on local LAN using NBNS protocol. +#define ETH0_NBNS_ENABLE 1 + +// Dynamic Host Configuration +// When this option is enabled, local IP address, Net Mask +// and Default Gateway are obtained automatically from +// the DHCP Server on local LAN. +#define ETH0_DHCP_ENABLE 1 + +// Vendor Class Identifier +// This value is optional. If specified, it is added +// to DHCP request message, identifying vendor type. +// Default: "" +#define ETH0_DHCP_VCID "" + +// Bootfile Name +// This value is optional. If enabled, the Bootfile Name +// (option 67) is also requested from DHCP server. +// Default: disabled +#define ETH0_DHCP_BOOTFILE 0 + +// NTP Servers +// This value is optional. If enabled, a list of NTP Servers +// (option 42) is also requested from DHCP server. +// Default: disabled +#define ETH0_DHCP_NTP_SERVERS 0 +// + +// Disable ICMP Echo response +#define ETH0_ICMP_NO_ECHO 0 +// + +// IPv6 +// Enable IPv6 Protocol for Network Interface +#define ETH0_IP6_ENABLE 1 + +// IPv6 Address +// Static IPv6 Address in text representation +// Use unspecified address "::" when static +// IPv6 address is not used. +// Default: "fec0::2" +#define ETH0_IP6_ADDR "fec0::2" + +// Subnet prefix-length <1-128> +// Number of bits that define network address +// Default: 64 +#define ETH0_IP6_PREFIX_LEN 64 + +// Default Gateway +// Default Gateway IPv6 Address in text representation +// Default: "fec0::1" +#define ETH0_IP6_GATEWAY "fec0::1" + +// Primary DNS Server +// Primary DNS Server IPv6 Address in text representation +// Default: "2001:4860:4860::8888" +#define ETH0_IP6_PRIMARY_DNS "2001:4860:4860::8888" + +// Secondary DNS Server +// Secondary DNS Server IPv6 Address in text representation +// Default: "2001:4860:4860::8844" +#define ETH0_IP6_SECONDARY_DNS "2001:4860:4860::8844" + +// Neighbor Discovery +// Neighbor cache and node address resolver settings +// Cache Table size <5-100> +// Number of cached node addresses +// Default: 5 +#define ETH0_NDP_TAB_SIZE 5 + +// Cache Timeout in seconds <5-255> +// Timeout for cached node addresses +// Default: 150 +#define ETH0_NDP_CACHE_TOUT 150 + +// Number of Retries <0-20> +// Number of retries to resolve an IP address +// before NDP module gives up +// Default: 4 +#define ETH0_NDP_MAX_RETRY 4 + +// Resend Timeout in seconds <1-10> +// A timeout to resend Neighbor Solicitation +// Default: 2 +#define ETH0_NDP_RESEND_TOUT 2 +// + +// Dynamic Host Configuration +// When this option is enabled, local IPv6 address is +// automatically configured. +#define ETH0_DHCP6_ENABLE 1 + +// DHCPv6 Client Mode <0=>Stateless Mode <1=>Statefull Mode +// Stateless DHCPv6 Client uses router advertisements +// for IPv6 address autoconfiguration (SLAAC). +// Statefull DHCPv6 Client connects to DHCPv6 server for a +// leased IPv6 address and DNS server IPv6 addresses. +#define ETH0_DHCP6_MODE 1 + +// Vendor Class Option +// If enabled, Vendor Class option is added to DHCPv6 +// request message, identifying vendor type. +// Default: disabled +#define ETH0_DHCP6_VCLASS_ENABLE 0 + +// Enterprise ID +// Enterprise-number as registered with IANA. +// Default: 0 (Reserved) +#define ETH0_DHCP6_VCLASS_EID 0 + +// Vendor Class Data +// This string identifies vendor type. +// Default: "" +#define ETH0_DHCP6_VCLASS_DATA "" +// +// + +// Disable ICMP6 Echo response +#define ETH0_ICMP6_NO_ECHO 0 +// + +// OS Resource Settings +// These settings are used to optimize usage of OS resources. +// Interface Thread Stack Size <512-65535:4> +// Default: 512 bytes +#define ETH0_THREAD_STACK_SIZE 512 + +// Interface Thread Priority +#define ETH0_THREAD_PRIORITY osPriorityAboveNormal + +// +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/Project/GateWay/MDK/RTE/Network/Net_Config_TCP.h b/Project/GateWay/MDK/RTE/Network/Net_Config_TCP.h new file mode 100644 index 0000000..79ba88c --- /dev/null +++ b/Project/GateWay/MDK/RTE/Network/Net_Config_TCP.h @@ -0,0 +1,69 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Socket + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_TCP.h + * Purpose: Network Configuration for TCP Sockets + * Rev.: V7.1.1 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// TCP Sockets +#define TCP_ENABLE 1 + +// Number of TCP Sockets <1-20> +// Number of available TCP sockets +// Default: 6 +#define TCP_NUM_SOCKS 6 + +// Number of Retries <0-20> +// How many times TCP module will try to retransmit data +// before giving up. Increase this value for high-latency +// and low throughput networks. +// Default: 5 +#define TCP_MAX_RETRY 5 + +// Retry Timeout in seconds <1-10> +// If data frame not acknowledged within this time frame, +// TCP module will try to resend the data again. +// Default: 4 +#define TCP_RETRY_TOUT 4 + +// Default Connect Timeout in seconds <1-65535> +// If no TCP data frame has been exchanged during this time, +// the TCP connection is either closed or a keep-alive frame +// is sent to verify that the connection still exists. +// Default: 120 +#define TCP_DEFAULT_TOUT 120 + +// Maximum Segment Size <536-1440> +// The Maximum Segment Size specifies the maximum +// number of bytes in the TCP segment's Data field. +// Default: 1440 +#define TCP_MAX_SEG_SIZE 1440 + +// Receive Window Size <536-65535> +// Receive Window Size specifies the size of data, +// that the socket is able to buffer in flow-control mode. +// Default: 4320 +#define TCP_RECEIVE_WIN_SIZE 4320 + +// + +// TCP Initial Retransmit period in seconds +#define TCP_INITIAL_RETRY_TOUT 1 + +// TCP SYN frame retransmit period in seconds +#define TCP_SYN_RETRY_TOUT 2 + +// Number of retries to establish a connection +#define TCP_CONNECT_RETRY 7 + +// Dynamic port start (default 49152) +#define TCP_DYN_PORT_START 49152 + +// Dynamic port end (default 65535) +#define TCP_DYN_PORT_END 65535 + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/Project/GateWay/MDK/RTE/RTOS/board.c b/Project/GateWay/MDK/RTE/RTOS/board.c new file mode 100644 index 0000000..7b3b1e8 --- /dev/null +++ b/Project/GateWay/MDK/RTE/RTOS/board.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-24 the first version + */ + +#include +#include +#include "bsp.h" + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) +/* + * Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP + * the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes + */ +#define RT_HEAP_SIZE (32*1024) +static rt_uint8_t rt_heap[RT_HEAP_SIZE]; + +RT_WEAK void *rt_heap_begin_get(void) +{ + return rt_heap; +} + +RT_WEAK void *rt_heap_end_get(void) +{ + return rt_heap + RT_HEAP_SIZE; +} +#endif + +void rt_os_tick_callback(void) +{ + rt_interrupt_enter(); + + rt_tick_increase(); + + rt_interrupt_leave(); +} + +void SysTick_IrqHandler(void) +{ + rt_os_tick_callback(); +} + +/** + * This function will initial your board. + */ +void rt_hw_board_init(void) +{ +//#error "TODO 1: OS Tick Configuration." + BSP_Init(); + /* + * TODO 1: OS Tick Configuration + * Enable the hardware timer and call the rt_os_tick_callback function + * periodically with the frequency RT_TICK_PER_SECOND. + */ + + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get()); +#endif +} + +#ifdef RT_USING_CONSOLE + +static int uart_init(void) +{ +//#error "TODO 2: Enable the hardware uart and config baudrate." + DbgUart_Config(500000); + return 0; +} +INIT_BOARD_EXPORT(uart_init); + +void rt_hw_console_output(const char *str) +{ +//#error "TODO 3: Output the string 'str' through the uart." + rt_enter_critical(); + DebugUartSend((uint8_t *)str, strlen(str)); + rt_exit_critical(); +} + +#endif + diff --git a/Project/GateWay/MDK/RTE/RTOS/board.c.base@3.1.5 b/Project/GateWay/MDK/RTE/RTOS/board.c.base@3.1.5 new file mode 100644 index 0000000..e45e75f --- /dev/null +++ b/Project/GateWay/MDK/RTE/RTOS/board.c.base@3.1.5 @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-24 the first version + */ + +#include +#include + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) +/* + * Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP + * the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes + */ +#define RT_HEAP_SIZE (15*1024) +static rt_uint8_t rt_heap[RT_HEAP_SIZE]; + +RT_WEAK void *rt_heap_begin_get(void) +{ + return rt_heap; +} + +RT_WEAK void *rt_heap_end_get(void) +{ + return rt_heap + RT_HEAP_SIZE; +} +#endif + +void rt_os_tick_callback(void) +{ + rt_interrupt_enter(); + + rt_tick_increase(); + + rt_interrupt_leave(); +} + +/** + * This function will initial your board. + */ +void rt_hw_board_init(void) +{ +#error "TODO 1: OS Tick Configuration." + /* + * TODO 1: OS Tick Configuration + * Enable the hardware timer and call the rt_os_tick_callback function + * periodically with the frequency RT_TICK_PER_SECOND. + */ + + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get()); +#endif +} + +#ifdef RT_USING_CONSOLE + +static int uart_init(void) +{ +#error "TODO 2: Enable the hardware uart and config baudrate." + return 0; +} +INIT_BOARD_EXPORT(uart_init); + +void rt_hw_console_output(const char *str) +{ +#error "TODO 3: Output the string 'str' through the uart." +} + +#endif + diff --git a/Project/GateWay/MDK/RTE/RTOS/rtconfig.h b/Project/GateWay/MDK/RTE/RTOS/rtconfig.h new file mode 100644 index 0000000..0aa25fe --- /dev/null +++ b/Project/GateWay/MDK/RTE/RTOS/rtconfig.h @@ -0,0 +1,139 @@ +/* RT-Thread config file */ + +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Configuration +// Maximal level of thread priority <8-256> +// Default: 32 +#define RT_THREAD_PRIORITY_MAX 16 +// OS tick per second +// Default: 1000 (1ms) +#define RT_TICK_PER_SECOND 1000 +// Alignment size for CPU architecture data access +// Default: 4 +#define RT_ALIGN_SIZE 4 +// the max length of object name<2-16> +// Default: 8 +#define RT_NAME_MAX 10 +// Using RT-Thread components initialization +// Using RT-Thread components initialization +#define RT_USING_COMPONENTS_INIT +// + +#define RT_USING_USER_MAIN + +// the stack size of main thread<1-4086> +// Default: 512 +#define RT_MAIN_THREAD_STACK_SIZE 512 + +// + +// Debug Configuration +// enable kernel debug configuration +// Default: enable kernel debug configuration +//#define RT_DEBUG +// +// enable components initialization debug configuration<0-1> +// Default: 0 +#define RT_DEBUG_INIT 0 +// thread stack over flow detect +// Diable Thread stack over flow detect +//#define RT_USING_OVERFLOW_CHECK +// +// + +// Hook Configuration +// using hook +// using hook +//#define RT_USING_HOOK +// +// using idle hook +// using idle hook +//#define RT_USING_IDLE_HOOK +// +// + +// Software timers Configuration +// Enables user timers +#define RT_USING_TIMER_SOFT 0 +#if RT_USING_TIMER_SOFT == 0 + #undef RT_USING_TIMER_SOFT +#endif +// The priority level of timer thread <0-31> +// Default: 4 +#define RT_TIMER_THREAD_PRIO 4 +// The stack size of timer thread <0-8192> +// Default: 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 +// + +// IPC(Inter-process communication) Configuration +// Using Semaphore +// Using Semaphore +#define RT_USING_SEMAPHORE +// +// Using Mutex +// Using Mutex +#define RT_USING_MUTEX +// +// Using Event +// Using Event +//#define RT_USING_EVENT +// +// Using MailBox +// Using MailBox +#define RT_USING_MAILBOX +// +// Using Message Queue +// Using Message Queue +#define RT_USING_MESSAGEQUEUE +// +// + +// Memory Management Configuration +// Memory Pool Management +// Memory Pool Management +//#define RT_USING_MEMPOOL +// +// Dynamic Heap Management(Algorithm: small memory ) +// Dynamic Heap Management +#define RT_USING_HEAP +#define RT_USING_SMALL_MEM +// +// using tiny size of memory +// using tiny size of memory +//#define RT_USING_TINY_SIZE +// +// + +// Console Configuration +// Using console +// Using console +#define RT_USING_CONSOLE +// +// the buffer size of console <1-1024> +// the buffer size of console +// Default: 128 (128Byte) +#define RT_CONSOLEBUF_SIZE 512 +// + +// FinSH Configuration +// include finsh config +// Select this choice if you using FinSH +//#include "finsh_config.h" +// +// + +// Device Configuration +// using device framework +// using device framework +//#define RT_USING_DEVICE +// +// + +// <<< end of configuration section >>> + +#endif diff --git a/Project/GateWay/MDK/RTE/RTOS/rtconfig.h.base@3.1.5 b/Project/GateWay/MDK/RTE/RTOS/rtconfig.h.base@3.1.5 new file mode 100644 index 0000000..5b54665 --- /dev/null +++ b/Project/GateWay/MDK/RTE/RTOS/rtconfig.h.base@3.1.5 @@ -0,0 +1,139 @@ +/* RT-Thread config file */ + +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Configuration +// Maximal level of thread priority <8-256> +// Default: 32 +#define RT_THREAD_PRIORITY_MAX 32 +// OS tick per second +// Default: 1000 (1ms) +#define RT_TICK_PER_SECOND 1000 +// Alignment size for CPU architecture data access +// Default: 4 +#define RT_ALIGN_SIZE 4 +// the max length of object name<2-16> +// Default: 8 +#define RT_NAME_MAX 8 +// Using RT-Thread components initialization +// Using RT-Thread components initialization +#define RT_USING_COMPONENTS_INIT +// + +#define RT_USING_USER_MAIN + +// the stack size of main thread<1-4086> +// Default: 512 +#define RT_MAIN_THREAD_STACK_SIZE 256 + +// + +// Debug Configuration +// enable kernel debug configuration +// Default: enable kernel debug configuration +//#define RT_DEBUG +// +// enable components initialization debug configuration<0-1> +// Default: 0 +#define RT_DEBUG_INIT 0 +// thread stack over flow detect +// Diable Thread stack over flow detect +//#define RT_USING_OVERFLOW_CHECK +// +// + +// Hook Configuration +// using hook +// using hook +//#define RT_USING_HOOK +// +// using idle hook +// using idle hook +//#define RT_USING_IDLE_HOOK +// +// + +// Software timers Configuration +// Enables user timers +#define RT_USING_TIMER_SOFT 0 +#if RT_USING_TIMER_SOFT == 0 + #undef RT_USING_TIMER_SOFT +#endif +// The priority level of timer thread <0-31> +// Default: 4 +#define RT_TIMER_THREAD_PRIO 4 +// The stack size of timer thread <0-8192> +// Default: 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 +// + +// IPC(Inter-process communication) Configuration +// Using Semaphore +// Using Semaphore +#define RT_USING_SEMAPHORE +// +// Using Mutex +// Using Mutex +//#define RT_USING_MUTEX +// +// Using Event +// Using Event +//#define RT_USING_EVENT +// +// Using MailBox +// Using MailBox +#define RT_USING_MAILBOX +// +// Using Message Queue +// Using Message Queue +//#define RT_USING_MESSAGEQUEUE +// +// + +// Memory Management Configuration +// Memory Pool Management +// Memory Pool Management +//#define RT_USING_MEMPOOL +// +// Dynamic Heap Management(Algorithm: small memory ) +// Dynamic Heap Management +#define RT_USING_HEAP +#define RT_USING_SMALL_MEM +// +// using tiny size of memory +// using tiny size of memory +//#define RT_USING_TINY_SIZE +// +// + +// Console Configuration +// Using console +// Using console +//#define RT_USING_CONSOLE +// +// the buffer size of console <1-1024> +// the buffer size of console +// Default: 128 (128Byte) +#define RT_CONSOLEBUF_SIZE 256 +// + +// FinSH Configuration +// include finsh config +// Select this choice if you using FinSH +//#include "finsh_config.h" +// +// + +// Device Configuration +// using device framework +// using device framework +//#define RT_USING_DEVICE +// +// + +// <<< end of configuration section >>> + +#endif diff --git a/Project/GateWay/MDK/RTE/_Debug/RTE_Components.h b/Project/GateWay/MDK/RTE/_Debug/RTE_Components.h new file mode 100644 index 0000000..2f4f04a --- /dev/null +++ b/Project/GateWay/MDK/RTE/_Debug/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'GateWay' + * Target: 'Debug' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460PETB.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/GateWay/MDK/RTE/_Release/RTE_Components.h b/Project/GateWay/MDK/RTE/_Release/RTE_Components.h new file mode 100644 index 0000000..b78ef95 --- /dev/null +++ b/Project/GateWay/MDK/RTE/_Release/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'GateWay' + * Target: 'Release' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460KETA.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/GateWay/MDK/RTE/_app_boot/RTE_Components.h b/Project/GateWay/MDK/RTE/_app_boot/RTE_Components.h new file mode 100644 index 0000000..06d1eb4 --- /dev/null +++ b/Project/GateWay/MDK/RTE/_app_boot/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'GateWay' + * Target: 'app_boot' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460KETA.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/GateWay/MDK/RTE/_app_dubeg/RTE_Components.h b/Project/GateWay/MDK/RTE/_app_dubeg/RTE_Components.h new file mode 100644 index 0000000..0a7a103 --- /dev/null +++ b/Project/GateWay/MDK/RTE/_app_dubeg/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'GateWay' + * Target: 'app_dubeg' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460KETA.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/GateWay/MDK/RTE/_i2c_24c256_Debug/RTE_Components.h b/Project/GateWay/MDK/RTE/_i2c_24c256_Debug/RTE_Components.h new file mode 100644 index 0000000..bf25b8a --- /dev/null +++ b/Project/GateWay/MDK/RTE/_i2c_24c256_Debug/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'DigitalModule_4Ch' + * Target: 'i2c_24c256_Debug' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460PETB.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/GateWay/MDK/RTE/_i2c_24c256_Release/RTE_Components.h b/Project/GateWay/MDK/RTE/_i2c_24c256_Release/RTE_Components.h new file mode 100644 index 0000000..b3756ae --- /dev/null +++ b/Project/GateWay/MDK/RTE/_i2c_24c256_Release/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'DigitalModule_4Ch' + * Target: 'i2c_24c256_Release' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460PETB.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/GateWay/MDK/RTE/_template_Debug/RTE_Components.h b/Project/GateWay/MDK/RTE/_template_Debug/RTE_Components.h new file mode 100644 index 0000000..114830a --- /dev/null +++ b/Project/GateWay/MDK/RTE/_template_Debug/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'DigitalModule_4Ch' + * Target: 'template_Debug' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460PETB.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/GateWay/MDK/output/GateWay.sct b/Project/GateWay/MDK/output/GateWay.sct new file mode 100644 index 0000000..f056ad7 --- /dev/null +++ b/Project/GateWay/MDK/output/GateWay.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00008000 0x0006C000 { ; load region size_region + ER_IROM1 0x00008000 0x0006C000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x1FFF8000 0x0002F000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/Project/GateWay/MDK/startup_hc32f460.s b/Project/GateWay/MDK/startup_hc32f460.s new file mode 100644 index 0000000..52a327d --- /dev/null +++ b/Project/GateWay/MDK/startup_hc32f460.s @@ -0,0 +1,621 @@ +;/****************************************************************************** +; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by HDSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2018-10-13 */ +;/* Target-mcu HC32F460 */ +;/*****************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00008000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler ; IRQ000_Handler + DCD IRQ001_Handler ; IRQ001_Handler + DCD IRQ002_Handler ; IRQ002_Handler + DCD IRQ003_Handler ; IRQ003_Handler + DCD IRQ004_Handler ; IRQ004_Handler + DCD IRQ005_Handler ; IRQ005_Handler + DCD IRQ006_Handler ; IRQ006_Handler + DCD IRQ007_Handler ; IRQ007_Handler + DCD IRQ008_Handler ; IRQ008_Handler + DCD IRQ009_Handler ; IRQ009_Handler + DCD IRQ010_Handler ; IRQ010_Handler + DCD IRQ011_Handler ; IRQ011_Handler + DCD IRQ012_Handler ; IRQ012_Handler + DCD IRQ013_Handler ; IRQ013_Handler + DCD IRQ014_Handler ; IRQ014_Handler + DCD IRQ015_Handler ; IRQ015_Handler + DCD IRQ016_Handler ; IRQ016_Handler + DCD IRQ017_Handler ; IRQ017_Handler + DCD IRQ018_Handler ; IRQ018_Handler + DCD IRQ019_Handler ; IRQ019_Handler + DCD IRQ020_Handler ; IRQ020_Handler + DCD IRQ021_Handler ; IRQ021_Handler + DCD IRQ022_Handler ; IRQ022_Handler + DCD IRQ023_Handler ; IRQ023_Handler + DCD IRQ024_Handler ; IRQ024_Handler + DCD IRQ025_Handler ; IRQ025_Handler + DCD IRQ026_Handler ; IRQ026_Handler + DCD IRQ027_Handler ; IRQ027_Handler + DCD IRQ028_Handler ; IRQ028_Handler + DCD IRQ029_Handler ; IRQ029_Handler + DCD IRQ030_Handler ; IRQ030_Handler + DCD IRQ031_Handler ; IRQ031_Handler + DCD IRQ032_Handler ; IRQ032_Handler + DCD IRQ033_Handler ; IRQ033_Handler + DCD IRQ034_Handler ; IRQ034_Handler + DCD IRQ035_Handler ; IRQ035_Handler + DCD IRQ036_Handler ; IRQ036_Handler + DCD IRQ037_Handler ; IRQ037_Handler + DCD IRQ038_Handler ; IRQ038_Handler + DCD IRQ039_Handler ; IRQ039_Handler + DCD IRQ040_Handler ; IRQ040_Handler + DCD IRQ041_Handler ; IRQ041_Handler + DCD IRQ042_Handler ; IRQ042_Handler + DCD IRQ043_Handler ; IRQ043_Handler + DCD IRQ044_Handler ; IRQ044_Handler + DCD IRQ045_Handler ; IRQ045_Handler + DCD IRQ046_Handler ; IRQ046_Handler + DCD IRQ047_Handler ; IRQ047_Handler + DCD IRQ048_Handler ; IRQ048_Handler + DCD IRQ049_Handler ; IRQ049_Handler + DCD IRQ050_Handler ; IRQ050_Handler + DCD IRQ051_Handler ; IRQ051_Handler + DCD IRQ052_Handler ; IRQ052_Handler + DCD IRQ053_Handler ; IRQ053_Handler + DCD IRQ054_Handler ; IRQ054_Handler + DCD IRQ055_Handler ; IRQ055_Handler + DCD IRQ056_Handler ; IRQ056_Handler + DCD IRQ057_Handler ; IRQ057_Handler + DCD IRQ058_Handler ; IRQ058_Handler + DCD IRQ059_Handler ; IRQ059_Handler + DCD IRQ060_Handler ; IRQ060_Handler + DCD IRQ061_Handler ; IRQ061_Handler + DCD IRQ062_Handler ; IRQ062_Handler + DCD IRQ063_Handler ; IRQ063_Handler + DCD IRQ064_Handler ; IRQ064_Handler + DCD IRQ065_Handler ; IRQ065_Handler + DCD IRQ066_Handler ; IRQ066_Handler + DCD IRQ067_Handler ; IRQ067_Handler + DCD IRQ068_Handler ; IRQ068_Handler + DCD IRQ069_Handler ; IRQ069_Handler + DCD IRQ070_Handler ; IRQ070_Handler + DCD IRQ071_Handler ; IRQ071_Handler + DCD IRQ072_Handler ; IRQ072_Handler + DCD IRQ073_Handler ; IRQ073_Handler + DCD IRQ074_Handler ; IRQ074_Handler + DCD IRQ075_Handler ; IRQ075_Handler + DCD IRQ076_Handler ; IRQ076_Handler + DCD IRQ077_Handler ; IRQ077_Handler + DCD IRQ078_Handler ; IRQ078_Handler + DCD IRQ079_Handler ; IRQ079_Handler + DCD IRQ080_Handler ; IRQ080_Handler + DCD IRQ081_Handler ; IRQ081_Handler + DCD IRQ082_Handler ; IRQ082_Handler + DCD IRQ083_Handler ; IRQ083_Handler + DCD IRQ084_Handler ; IRQ084_Handler + DCD IRQ085_Handler ; IRQ085_Handler + DCD IRQ086_Handler ; IRQ086_Handler + DCD IRQ087_Handler ; IRQ087_Handler + DCD IRQ088_Handler ; IRQ088_Handler + DCD IRQ089_Handler ; IRQ089_Handler + DCD IRQ090_Handler ; IRQ090_Handler + DCD IRQ091_Handler ; IRQ091_Handler + DCD IRQ092_Handler ; IRQ092_Handler + DCD IRQ093_Handler ; IRQ093_Handler + DCD IRQ094_Handler ; IRQ094_Handler + DCD IRQ095_Handler ; IRQ095_Handler + DCD IRQ096_Handler ; IRQ096_Handler + DCD IRQ097_Handler ; IRQ097_Handler + DCD IRQ098_Handler ; IRQ098_Handler + DCD IRQ099_Handler ; IRQ099_Handler + DCD IRQ100_Handler ; IRQ100_Handler + DCD IRQ101_Handler ; IRQ101_Handler + DCD IRQ102_Handler ; IRQ102_Handler + DCD IRQ103_Handler ; IRQ103_Handler + DCD IRQ104_Handler ; IRQ104_Handler + DCD IRQ105_Handler ; IRQ105_Handler + DCD IRQ106_Handler ; IRQ106_Handler + DCD IRQ107_Handler ; IRQ107_Handler + DCD IRQ108_Handler ; IRQ108_Handler + DCD IRQ109_Handler ; IRQ109_Handler + DCD IRQ110_Handler ; IRQ110_Handler + DCD IRQ111_Handler ; IRQ111_Handler + DCD IRQ112_Handler ; IRQ112_Handler + DCD IRQ113_Handler ; IRQ113_Handler + DCD IRQ114_Handler ; IRQ114_Handler + DCD IRQ115_Handler ; IRQ115_Handler + DCD IRQ116_Handler ; IRQ116_Handler + DCD IRQ117_Handler ; IRQ117_Handler + DCD IRQ118_Handler ; IRQ118_Handler + DCD IRQ119_Handler ; IRQ119_Handler + DCD IRQ120_Handler ; IRQ120_Handler + DCD IRQ121_Handler ; IRQ121_Handler + DCD IRQ122_Handler ; IRQ122_Handler + DCD IRQ123_Handler ; IRQ123_Handler + DCD IRQ124_Handler ; IRQ124_Handler + DCD IRQ125_Handler ; IRQ125_Handler + DCD IRQ126_Handler ; IRQ126_Handler + DCD IRQ127_Handler ; IRQ127_Handler + DCD IRQ128_Handler ; IRQ128_Handler + DCD IRQ129_Handler ; IRQ129_Handler + DCD IRQ130_Handler ; IRQ130_Handler + DCD IRQ131_Handler ; IRQ131_Handler + DCD IRQ132_Handler ; IRQ132_Handler + DCD IRQ133_Handler ; IRQ133_Handler + DCD IRQ134_Handler ; IRQ134_Handler + DCD IRQ135_Handler ; IRQ135_Handler + DCD IRQ136_Handler ; IRQ136_Handler + DCD IRQ137_Handler ; IRQ137_Handler + DCD IRQ138_Handler ; IRQ138_Handler + DCD IRQ139_Handler ; IRQ139_Handler + DCD IRQ140_Handler ; IRQ140_Handler + DCD IRQ141_Handler ; IRQ141_Handler + DCD IRQ142_Handler ; IRQ142_Handler + DCD IRQ143_Handler ; IRQ143_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main +SET_SRAM3_WAIT + LDR R0, =0x40050804 + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x40050800 + MOV R1, #0x1100 + STR R1, [R0] + + LDR R0, =0x40050804 + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + EXPORT IRQ032_Handler [WEAK] + EXPORT IRQ033_Handler [WEAK] + EXPORT IRQ034_Handler [WEAK] + EXPORT IRQ035_Handler [WEAK] + EXPORT IRQ036_Handler [WEAK] + EXPORT IRQ037_Handler [WEAK] + EXPORT IRQ038_Handler [WEAK] + EXPORT IRQ039_Handler [WEAK] + EXPORT IRQ040_Handler [WEAK] + EXPORT IRQ041_Handler [WEAK] + EXPORT IRQ042_Handler [WEAK] + EXPORT IRQ043_Handler [WEAK] + EXPORT IRQ044_Handler [WEAK] + EXPORT IRQ045_Handler [WEAK] + EXPORT IRQ046_Handler [WEAK] + EXPORT IRQ047_Handler [WEAK] + EXPORT IRQ048_Handler [WEAK] + EXPORT IRQ049_Handler [WEAK] + EXPORT IRQ050_Handler [WEAK] + EXPORT IRQ051_Handler [WEAK] + EXPORT IRQ052_Handler [WEAK] + EXPORT IRQ053_Handler [WEAK] + EXPORT IRQ054_Handler [WEAK] + EXPORT IRQ055_Handler [WEAK] + EXPORT IRQ056_Handler [WEAK] + EXPORT IRQ057_Handler [WEAK] + EXPORT IRQ058_Handler [WEAK] + EXPORT IRQ059_Handler [WEAK] + EXPORT IRQ060_Handler [WEAK] + EXPORT IRQ061_Handler [WEAK] + EXPORT IRQ062_Handler [WEAK] + EXPORT IRQ063_Handler [WEAK] + EXPORT IRQ064_Handler [WEAK] + EXPORT IRQ065_Handler [WEAK] + EXPORT IRQ066_Handler [WEAK] + EXPORT IRQ067_Handler [WEAK] + EXPORT IRQ068_Handler [WEAK] + EXPORT IRQ069_Handler [WEAK] + EXPORT IRQ070_Handler [WEAK] + EXPORT IRQ071_Handler [WEAK] + EXPORT IRQ072_Handler [WEAK] + EXPORT IRQ073_Handler [WEAK] + EXPORT IRQ074_Handler [WEAK] + EXPORT IRQ075_Handler [WEAK] + EXPORT IRQ076_Handler [WEAK] + EXPORT IRQ077_Handler [WEAK] + EXPORT IRQ078_Handler [WEAK] + EXPORT IRQ079_Handler [WEAK] + EXPORT IRQ080_Handler [WEAK] + EXPORT IRQ081_Handler [WEAK] + EXPORT IRQ082_Handler [WEAK] + EXPORT IRQ083_Handler [WEAK] + EXPORT IRQ084_Handler [WEAK] + EXPORT IRQ085_Handler [WEAK] + EXPORT IRQ086_Handler [WEAK] + EXPORT IRQ087_Handler [WEAK] + EXPORT IRQ088_Handler [WEAK] + EXPORT IRQ089_Handler [WEAK] + EXPORT IRQ090_Handler [WEAK] + EXPORT IRQ091_Handler [WEAK] + EXPORT IRQ092_Handler [WEAK] + EXPORT IRQ093_Handler [WEAK] + EXPORT IRQ094_Handler [WEAK] + EXPORT IRQ095_Handler [WEAK] + EXPORT IRQ096_Handler [WEAK] + EXPORT IRQ097_Handler [WEAK] + EXPORT IRQ098_Handler [WEAK] + EXPORT IRQ099_Handler [WEAK] + EXPORT IRQ100_Handler [WEAK] + EXPORT IRQ101_Handler [WEAK] + EXPORT IRQ102_Handler [WEAK] + EXPORT IRQ103_Handler [WEAK] + EXPORT IRQ104_Handler [WEAK] + EXPORT IRQ105_Handler [WEAK] + EXPORT IRQ106_Handler [WEAK] + EXPORT IRQ107_Handler [WEAK] + EXPORT IRQ108_Handler [WEAK] + EXPORT IRQ109_Handler [WEAK] + EXPORT IRQ110_Handler [WEAK] + EXPORT IRQ111_Handler [WEAK] + EXPORT IRQ112_Handler [WEAK] + EXPORT IRQ113_Handler [WEAK] + EXPORT IRQ114_Handler [WEAK] + EXPORT IRQ115_Handler [WEAK] + EXPORT IRQ116_Handler [WEAK] + EXPORT IRQ117_Handler [WEAK] + EXPORT IRQ118_Handler [WEAK] + EXPORT IRQ119_Handler [WEAK] + EXPORT IRQ120_Handler [WEAK] + EXPORT IRQ121_Handler [WEAK] + EXPORT IRQ122_Handler [WEAK] + EXPORT IRQ123_Handler [WEAK] + EXPORT IRQ124_Handler [WEAK] + EXPORT IRQ125_Handler [WEAK] + EXPORT IRQ126_Handler [WEAK] + EXPORT IRQ127_Handler [WEAK] + EXPORT IRQ128_Handler [WEAK] + EXPORT IRQ129_Handler [WEAK] + EXPORT IRQ130_Handler [WEAK] + EXPORT IRQ131_Handler [WEAK] + EXPORT IRQ132_Handler [WEAK] + EXPORT IRQ133_Handler [WEAK] + EXPORT IRQ134_Handler [WEAK] + EXPORT IRQ135_Handler [WEAK] + EXPORT IRQ136_Handler [WEAK] + EXPORT IRQ137_Handler [WEAK] + EXPORT IRQ138_Handler [WEAK] + EXPORT IRQ139_Handler [WEAK] + EXPORT IRQ140_Handler [WEAK] + EXPORT IRQ141_Handler [WEAK] + EXPORT IRQ142_Handler [WEAK] + EXPORT IRQ143_Handler [WEAK] +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler +IRQ032_Handler +IRQ033_Handler +IRQ034_Handler +IRQ035_Handler +IRQ036_Handler +IRQ037_Handler +IRQ038_Handler +IRQ039_Handler +IRQ040_Handler +IRQ041_Handler +IRQ042_Handler +IRQ043_Handler +IRQ044_Handler +IRQ045_Handler +IRQ046_Handler +IRQ047_Handler +IRQ048_Handler +IRQ049_Handler +IRQ050_Handler +IRQ051_Handler +IRQ052_Handler +IRQ053_Handler +IRQ054_Handler +IRQ055_Handler +IRQ056_Handler +IRQ057_Handler +IRQ058_Handler +IRQ059_Handler +IRQ060_Handler +IRQ061_Handler +IRQ062_Handler +IRQ063_Handler +IRQ064_Handler +IRQ065_Handler +IRQ066_Handler +IRQ067_Handler +IRQ068_Handler +IRQ069_Handler +IRQ070_Handler +IRQ071_Handler +IRQ072_Handler +IRQ073_Handler +IRQ074_Handler +IRQ075_Handler +IRQ076_Handler +IRQ077_Handler +IRQ078_Handler +IRQ079_Handler +IRQ080_Handler +IRQ081_Handler +IRQ082_Handler +IRQ083_Handler +IRQ084_Handler +IRQ085_Handler +IRQ086_Handler +IRQ087_Handler +IRQ088_Handler +IRQ089_Handler +IRQ090_Handler +IRQ091_Handler +IRQ092_Handler +IRQ093_Handler +IRQ094_Handler +IRQ095_Handler +IRQ096_Handler +IRQ097_Handler +IRQ098_Handler +IRQ099_Handler +IRQ100_Handler +IRQ101_Handler +IRQ102_Handler +IRQ103_Handler +IRQ104_Handler +IRQ105_Handler +IRQ106_Handler +IRQ107_Handler +IRQ108_Handler +IRQ109_Handler +IRQ110_Handler +IRQ111_Handler +IRQ112_Handler +IRQ113_Handler +IRQ114_Handler +IRQ115_Handler +IRQ116_Handler +IRQ117_Handler +IRQ118_Handler +IRQ119_Handler +IRQ120_Handler +IRQ121_Handler +IRQ122_Handler +IRQ123_Handler +IRQ124_Handler +IRQ125_Handler +IRQ126_Handler +IRQ127_Handler +IRQ128_Handler +IRQ129_Handler +IRQ130_Handler +IRQ131_Handler +IRQ132_Handler +IRQ133_Handler +IRQ134_Handler +IRQ135_Handler +IRQ136_Handler +IRQ137_Handler +IRQ138_Handler +IRQ139_Handler +IRQ140_Handler +IRQ141_Handler +IRQ142_Handler +IRQ143_Handler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Project/GateWay/source/Module/AD7924/ad7924.c b/Project/GateWay/source/Module/AD7924/ad7924.c new file mode 100644 index 0000000..e4d51f1 --- /dev/null +++ b/Project/GateWay/source/Module/AD7924/ad7924.c @@ -0,0 +1,2 @@ +#include "bps.h" + diff --git a/Project/GateWay/source/Module/FatFS/LICENSE.txt b/Project/GateWay/source/Module/FatFS/LICENSE.txt new file mode 100644 index 0000000..a9e57a9 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/LICENSE.txt @@ -0,0 +1,24 @@ +FatFs License + +FatFs has being developped as a personal project of the author, ChaN. It is free from the code anyone else wrote at current release. Following code block shows a copy of the FatFs license document that heading the source files. + +/*----------------------------------------------------------------------------/ +/ FatFs - Generic FAT Filesystem Module Rx.xx / +/-----------------------------------------------------------------------------/ +/ +/ Copyright (C) 20xx, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: +/ +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +/----------------------------------------------------------------------------*/ + +Therefore FatFs license is one of the BSD-style licenses, but there is a significant feature. FatFs is mainly intended for embedded systems. In order to extend the usability for commercial products, the redistributions of FatFs in binary form, such as embedded code, binary library and any forms without source code, do not need to include about FatFs in the documentations. This is equivalent to the 1-clause BSD license. Of course FatFs is compatible with the most of open source software licenses include GNU GPL. When you redistribute the FatFs source code with changes or create a fork, the license can also be changed to GNU GPL, BSD-style license or any open source software license that not conflict with FatFs license. diff --git a/Project/GateWay/source/Module/FatFS/documents/00index_e.html b/Project/GateWay/source/Module/FatFS/documents/00index_e.html new file mode 100644 index 0000000..eed6244 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/00index_e.html @@ -0,0 +1,149 @@ + + + + + + + + + + +FatFs - Generic FAT Filesystem Module + + + +

FatFs - Generic FAT Filesystem Module

+
+ +
+layer +

FatFs is a generic FAT/exFAT filesystem module for small embedded systems. The FatFs module is written in compliance with ANSI C (C89) and completely separated from the disk I/O layer. Therefore it is independent of the platform. It can be incorporated into small microcontrollers with limited resource, such as 8051, PIC, AVR, ARM, Z80, RX and etc. Also Petit FatFs module for tiny microcontrollers is available here.

+ +

Features

+
    +
  • DOS/Windows Compatible FAT/exFAT Filesystem.
    • +
  • Platform Independent. Easy to port.
    • +
  • Very Small Footprint for Program Code and Work Area.
    • +
  • Various Configuration Options to Support for: +
      +
    • Long File Name in ANSI/OEM or Unicode.
      • +
    • exFAT Filesystem, 64-bit LBA and GPT for Huge Storages.
      • +
    • Thread Safe for RTOS.
      • +
    • Multiple Volumes. (Physical Drives and Partitions)
      • +
    • Variable Sector Size.
      • +
    • Multiple Code Pages Including DBCS.
      • +
    • Read-only, Optional APIs, I/O Buffer and etc...
      • +
    +
    • +
+
+ + +
+

Application Interface

+layer +

FatFs provides various filesystem functions for the applications as shown below.

+
    +
  • File Access +
      +
    • f_open - Open/Create a file
      • +
    • f_close - Close an open file
      • +
    • f_read - Read data from the file
      • +
    • f_write - Write data to the file
      • +
    • f_lseek - Move read/write pointer, Expand size
      • +
    • f_truncate - Truncate file size
      • +
    • f_sync - Flush cached data
      • +
    • f_forward - Forward data to the stream
      • +
    • f_expand - Allocate a contiguous block to the file
      • +
    • f_gets - Read a string
      • +
    • f_putc - Write a character
      • +
    • f_puts - Write a string
      • +
    • f_printf - Write a formatted string
      • +
    • f_tell - Get current read/write pointer
      • +
    • f_eof - Test for end-of-file
      • +
    • f_size - Get size
      • +
    • f_error - Test for an error
      • +
    +
    • +
  • Directory Access + +
    • +
  • File and Directory Management +
      +
    • f_stat - Check existance of a file or sub-directory
      • +
    • f_unlink - Remove a file or sub-directory
      • +
    • f_rename - Rename/Move a file or sub-directory
      • +
    • f_chmod - Change attribute of a file or sub-directory
      • +
    • f_utime - Change timestamp of a file or sub-directory
      • +
    • f_mkdir - Create a sub-directory
      • +
    • f_chdir - Change current directory
      • +
    • f_chdrive - Change current drive
      • +
    • f_getcwd - Retrieve the current directory and drive
      • +
    +
    • +
  • Volume Management and System Configuration +
      +
    • f_mount - Register/Unregister the work area of the volume
      • +
    • f_mkfs - Create an FAT volume on the logical drive
      • +
    • f_fdisk - Create partitions on the physical drive
      • +
    • f_getfree - Get free space on the volume
      • +
    • f_getlabel - Get volume label
      • +
    • f_setlabel - Set volume label
      • +
    • f_setcp - Set active code page
      • +
    +
    • +
+
+ + +
+

Media Access Interface

+layer +

Since FatFs module is the Filesystem Layer independent of platforms and storage media, it is completely separated from the physical devices, such as memory card, harddisk and any type of storage device. The storage device control module is not any part of FatFs module and it needs to be provided by implementer. FatFs controls the storage devices via a simple media access interface shown below. Also sample implementations for some platforms are available in the downloads. A function checker for storage device control module is available here.

+ +
+ + +
+

Resources

+

The FatFs module is a free software opened for education, research and development. You can use, modify and/or redistribute it for any purpose without any restriction under your responsibility. For further information, refer to the application note.

+
+ + +
+

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/css_e.css b/Project/GateWay/source/Module/FatFS/documents/css_e.css new file mode 100644 index 0000000..192ce63 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/css_e.css @@ -0,0 +1,73 @@ +* {margin: 0; padding: 0; border-width: 0;} +body {margin: 8px; background-color: #e0ffff; font-color: black; font-family: serif; line-height: 133%; max-width: 1024px;} +a:link {color: blue;} +a:visited {color: darkmagenta;} +a:hover {background-color: #a0ffff;} +a:active {color: darkmagenta; overflow: hidden; outline:none; position: relative; top: 1px; left: 1px;} +abbr {border-width: 1px;} + +p {margin: 0 0 0.3em 1em;} +i {margin: 0 0.3em 0 0;} +b {margin: 0 0.1em;} +em {font-style: normal; font-weight: bold; margin: 0 0.1em;} +strong {} +pre {border: 1px dashed gray; margin: 0.5em 1em; padding: 0.5em; line-height: 1.2em; font-size: 85%; font-family: "Consolas", "Courier New", monospace; background-color: white;} +pre span.c {color: green;} +pre span.k {color: blue;} +pre span.e {color: red;} +pre span.b {font-weight: bold;} +pre span.arg {font-style: italic;} +tt {margin: 0 0.2em; font-size: 0.85em; font-family: "Consolas", "Courier New", monospace; } +tt.arg {font-style: italic;} +ol {margin: 0.5em 2.5em;} +ul {margin: 0.5em 2em;} +ul ul {margin: 0 2em 0.5em 1em;} +dl {margin: 0.5em 1em;} +dd {margin: 0 2em;} +dt {font-size: 0.85em; font-family: "Consolas", "Courier New", monospace;} +dl.par dt {margin: 0.5em 0 0 0 ; font-style: italic; } +dl.ret dt {margin: 0.5em 0 0 0 ; font-size: 0.85em; font-family: "Consolas", "Courier New", monospace; font-weight: bold; } +hr {border-width: 1px; margin: 1em;} +div.abst {font-family: sans-serif;} +div.para {clear: both; font-family: serif;} +div.ret a {font-size: 0.85em; font-family: "Consolas", "Courier New", monospace; } +.equ {text-indent: 0; margin: 1em 2em 1em;} +.indent {margin-left: 2em;} +.rset {float: right; margin: 0.3em 0 0.5em 0.5em;} +.lset {float: left; margin: 0.3em 0.5em 0.5em 0.5em;} +ul.flat li {list-style-type: none; margin: 0;} +a.imglnk img {border: 1px solid;} +.iequ {white-space: nowrap; font-weight: bold;} +.clr {clear: both;} +.it {font-style: italic;} +.mfd {font-size: 0.7em; padding: 0 1px; border: 1px solid; white-space : nowrap} +.ral {text-align: right; } +.lal {text-align: left; } +.cal {text-align: center; } + +h1 {line-height: 1em; font-size: 2em; font-family: sans-serif; padding: 0.3em 0 0.3em;} +h2 {font-size: 2em; font-family: sans-serif; background-color: #d8d8FF; padding: 0.5em 0.5em; margin: 0 0 0.5em;} +h3 {font-size: 1.5em; font-family: sans-serif; margin: 1.5em 0 0.5em;} +div.doc h3 {border-color: #b0d8d8; border-style: solid; border-width: 0px 0px 4px 12px; padding: 4px; margin-top: 3em;} +h4 {font-size: 1.2em; font-family: sans-serif; margin: 2em 0 0.2em;} +h5 {font-size: 1em; font-family: sans-serif; margin: 1em 0 0em;} +p.hdd {float: right; text-align: right; margin-top: 0.5em;} +hr.hds {clear: both; margin-bottom: 1em;} +kbd {letter-spacing: 0;} +small {font-size: 80%;} +.indent {margin-left: 2em;} + +/* Tables */ +table {margin: 0.5em 1em; border-collapse: collapse; border: 2px solid gray; } +table caption {font-family: sans-serif; font-weight: bold;} +table th {background-color: white; border-style: solid; border-width: 1px 1px 2px; border-color: gray; padding: 0 3px; vertical-align: top; white-space: nowrap;} +table td {background-color: white; border: 1px solid gray; padding: 0 3px; vertical-align: top; line-height: 1.3em;} +table.lst td:first-child {font-size: 0.85em; font-family: "Consolas", "Courier New", monospace; white-space: nowrap;} +table.lst2 td {font-size: 0.85em; font-family: "Consolas", "Courier New", monospace; white-space: nowrap;} +table.lst3 td {font-family: "Consolas", "Courier New", monospace; white-space: nowrap;} +tr.lst3 td {border-width: 2px 1px 1px; } +table.lst4 td {padding: 0.3em;} +table.lst4 td:nth-child(2) {width: 45%;} +table.lst4 td:nth-child(3) {width: 45%;} + +p.foot {clear: both; text-indent: 0; margin: 1em 0.5em 1em;} diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/appnote.html b/Project/GateWay/source/Module/FatFS/documents/doc/appnote.html new file mode 100644 index 0000000..45fd602 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/appnote.html @@ -0,0 +1,339 @@ + + + + + + + + +FatFs Module Application Note + + + +

FatFs Module Application Note

+
    +
  1. How to Port
    2. +
  2. Limits
    3. +
  3. Memory Usage
    4. +
  4. Reducing Module Size
    5. +
  5. Long File Name
    6. +
  6. Unicode API
    7. +
  7. exFAT Filesystem
    8. +
  8. 64-bit LBA
    9. +
  9. Re-entrancy
    10. +
  10. Duplicated File Access
    11. +
  11. Performance Effective File Access
    12. +
  12. Considerations on Flash Memory Media
    13. +
  13. Critical Section
    14. +
  14. Various Usable Functions for FatFs Projects
    15. +
  15. About FatFs License
    16. +
+ +
+

How to Port

+ +

Basic Considerations

+

The FatFs module assumes following conditions on portability.

+
    +
  • ANSI C
    +The FatFs module is a middleware written in ANSI C (C89). There is no platform dependence, so long as the compiler is in compliance with C89 or later. Only exFAT feature requires C99.
    • +
  • Size of integer types
    +
      +
    • Size of char must be 8-bit.
      • +
    • Size of int, as well as integer promotion, must be 16-bit or 32-bit.
      • +
    • Size of short and long must be 16-bit and 32-bit respectively. (in C89 only)
      • +
    +
  • Dependency
    +
      +
    • C89: string.h.
      • +
    • C99: string.h and stdint.h.
      • +
    • Optional: stdarg.h and math.h.
      • +
    +
+ +

Integer Types in FatFs API

+

Integer types used in FatFs are defined in ff.h as described below. It is based on Win32 API (windef.h). This will not be a problem on most platform. When a conflict with existing definitions occured, you must resolve it with care.

+
+
BYTE
8-bit unsigned integer in range of 0 to 28 - 1.
+
WORD
16-bit unsigned integer in range of 0 to 216 - 1.
+
DWORD
32-bit unsigned integer in range of 0 to 232 - 1.
+
QWORD
64-bit unsigned integer in range of 0 to 264 - 1.
+
UINT
Alias of unsigned int used to specify any number.
+
WCHAR
Alias of WORD used to specify a UTF-16 code unit.
+
TCHAR
Alias of char, WCHAR or DWORD used to specify a character encoding unit.
+
FSIZE_t
Alias of DWORD or QWORD used to address file offset and to specify file size.
+
LBA_t
Alias of DWORD or QWORD used to address sectors in LBA and to specify number of sectors.
+
+ +

System Organizations

+

The dependency diagram shown below is a typical, but not specific, configuration of the embedded system with FatFs module.

+

dependency diagram

+

(a) If a working disk module for FatFs is provided, nothing else will be needed. (b) To attach existing disk drivers with different interface, some glue functions are needed to translate the interfaces between FatFs and the driver.

+

functional diagram

+ +

Required Functions

+

You need to provide only MAI functions required by FatFs module and nothing else. If a working device control module for the target system is available, you need to write only glue functions to attach it to the FatFs module. If not, you need to port another device control module or write it from scratch. Most of MAI functions are not that always required. For instance, the write function is not required in read-only configuration. Following table shows which function is required depends on the configuration options.

+ + + + + + + + + + +
FunctionRequired when:Note
disk_status
disk_initialize
disk_read		AlwaysDisk I/O functions.
Samples available in ffsample.zip.
There are many implementations on the web.
disk_write
get_fattime
disk_ioctl (CTRL_SYNC)		FF_FS_READONLY == 0
disk_ioctl (GET_SECTOR_COUNT)
disk_ioctl (GET_BLOCK_SIZE)		FF_USE_MKFS == 1
disk_ioctl (GET_SECTOR_SIZE)FF_MAX_SS != FF_MIN_SS
disk_ioctl (CTRL_TRIM)FF_USE_TRIM == 1
ff_uni2oem
ff_oem2uni
ff_wtoupper		FF_USE_LFN != 0Unicode support functions.
Add optional module ffunicode.c to the project.
ff_mutex_create
ff_mutex_delete
ff_mutex_take
ff_mutex_give		FF_FS_REENTRANT == 1O/S dependent functions.
Sample code is available in ffsystem.c.
ff_mem_alloc
ff_mem_free		FF_USE_LFN == 3
+

FatFs cares about neither what kind of storage device is used nor how it is implemented. Only a requirement is that it is a block device read/written in fixed-size blocks that accessible via the disk I/O functions defined above.

+
+ +
+

Limits

+
    +
  • Filesystem type: FAT, FAT32(rev0.0) and exFAT(rev1.0).
    • +
  • Number of open files: Unlimited. (depends on available memory)
    • +
  • Number of volumes: Up to 10.
    • +
  • Sector size: 512, 1024, 2048 and 4096 bytes.
    • +
  • Minimum volume size: 128 sectors.
    • +
  • Maximum volume size: 232 - 1 sectors in 32-bit LBA, virtually unlimited in 64-bit LBA with exFAT.
    • +
  • Maximum file size: 232 - 1 bytes on FAT volume, virtually unlimited on exFAT volume.
    • +
  • Cluster size: Upto 128 sectors on FAT volume and up to 16 MB on exFAT volume.
    • +
+
+ +
+

Memory Usage

+

The memory usage varies depends on the configuration options.

+ + + + + + + + + + + +
ARM7
32bit		ARM7
Thumb		CM3
Thumb-2		AVRH8/300HPIC24RL78V850ESSH-2ARX600IA-32
CompilerGCCGCCGCCGCCCH38C30CC78K0RCA850SHCRXCMSC
.text (Def, R/W)10.4k6.7k6.1k12.5k11.0k11.4k13.0k8.9k9.2k6.5k8.9k
.text (Min, R/W) 7.0k4.7k4.2k 8.5k 7.6k 7.9k 9.5k6.3k6.4k4.7k6.4k
.text (Def, R/O) 4.9k3.2k2.7k 6.1k 5.2k 5.4k 6.5k4.3k4.2k3.2k4.3k
.text (Min, R/O) 3.7k2.5k2.1k 4.4k 4.0k 4.2k 5.1k3.4k3.3k2.5k3.5k
.bssV*4 + 2V*4 + 2V*4 + 2V*2 + 2V*4 + 2V*2 + 2V*2 + 2V*4 + 2V*4 + 2V*4 + 2V*4 + 2
Work area
(FF_FS_TINY == 0)		V*564
+ F*552		V*564
+ F*552		V*564
+ F*552		V*560
+ F*546		V*560
+ F*546		V*560
+ F*546		V*560
+ F*546		V*564
+ F*552		V*564
+ F*552		V*564
+ F*552		V*564
+ F*552
Work area
(FF_FS_TINY == 1)		V*564
+ F*40		V*564
+ F*40		V*564
+ F*40		V*560
+ F*34		V*560
+ F*34		V*560
+ F*34		V*560
+ F*34		V*564
+ F*40		V*564
+ F*40		V*564
+ F*40		V*564
+ F*40
+

These are the memory usage of FatFs module without lower layer on some target systems in following condition. V denotes number of mounted volumes and F denotes number of open files. Every samples here are optimezed in code size.

+
+FatFs R0.15 options:
+FF_FS_READONLY   0 (R/W, read/write) or 1 (R/O, read only)
+FF_FS_MINIMIZE   0 (Def, with all basic functions) or 3 (Min, with fully minimized)
+FF_FS_TINY       0 (Default) or 1 (Tiny file object)
+And any other options are left unchanged from original setting.
+
+
+ +
+

Reducing Module Size

+

Follwing table shows which API function is removed by configuration options to reduce the module size. To use an API function, the row of the function must be clear.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FunctionFF_FS_
MINIMIZE		FF_FS_
READONLY		FF_USE_
STRFUNC		FF_FS_
RPATH		FF_USE_
FIND		FF_USE_
CHMOD		FF_USE_
EXPAND		FF_USE_
LABEL		FF_USE_
MKFS		FF_USE_
FORWARD		FF_MULTI_
PARTITION
0123010101201010101010101
f_mount
f_open
f_close
f_read
f_write x
f_sync x
f_lseek x
f_opendir xx
f_closedir xx
f_readdir xx
f_findfirst xx x
f_findnext xx x
f_stat xxx
f_getfree xxx x
f_truncate xxx x
f_unlink xxx x
f_mkdir xxx x
f_rename xxx x
f_chdir x
f_chdrive x
f_getcwd xx
f_chmod x x
f_utime x x
f_getlabel x
f_setlabel x x
f_expand x x
f_forward x
f_mkfs x x
f_fdisk x x x
f_putc xx
f_puts xx
f_printf xx
f_gets x
+
+ +
+

Long File Name

+

FatFs module supports the long file name (LFN) extension of the FAT filesystem. The two different file names, short file name (SFN) and LFN, of a file is transparent on the API. The support for LFN feature is disabled by default. To enable the LFN, set FF_USE_LFN to 1, 2 or 3, and add ffunicode.c to the project. The LFN feature requiers a certain working buffer. The buffer size can be configured by FF_MAX_LFN according to the available memory. The length of LFN can be up to 255 characters, so that the FF_MAX_LFN should be set to 255 for any existing file names. If the size of working buffer is insufficient for the input file name, the file function fails with FR_INVALID_NAME. When use any re-entry to the API with LFN feature in RTOS environment, FF_USE_LFN must be set to 2 or 3. In this case, the file function allocates the working buffer on the stack or heap. The LFN working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.

+

Impact upon Module Size

+ + + + + + + + + +
With LFN at CM3 + gcc
FF_CODE_PAGECode size
437-869 (SBCS)+3.3k
932 (Japanese)+62k
936 (Simplified Chinese)+177k
949 (Korean)+140k
950 (Traditional Chinese)+111k
0 (All code pages)+486k
+

When the LFN is enabled, the module size will be increased depends on the configured code page. Right table shows the increment of code size in some code pages. Especially, in the CJK region, tens of thousands of characters are being used. Unfortunately, it requires a huge OEM-Unicode bidirectional conversion table and the module size will be drastically increased as shown in the table.

+

As the result, the FatFs with LFN enabled with DBCS code pages will not able to be ported on the most 8-bit MCU systems. If the target system is in legacy-free, in only Unicode and any ANSI/OEM code is not used at all, the code page setting gets meaningless. You will able to reduce the code size by configureing FatFs for Unicode API with any SBCS code page.

+

There ware some restrictions on using LFN for open source project, because the LFN extension on the FAT filesystem was a patent of Microsoft Corporation. However the related patents all have expired and using the LFN feature is free for any projects.

+
+ +
+

Unicode API

+

By default, FatFs uses ANSI/OEM code set on the API even in LFN configuration. FatFs can also switch the character encoding on the API to Unicode by configuration option FF_LFN_UNICODE. This means that FatFs is compliant with the full featured LFN specification. The data type TCHAR specifies path name strings on the API is an alias of either char(ANSI/OEM or UTF-8), WCHAR(UTF-16) or DWORD(UTF-32) depends on that option. For more information, refer to the description in the file name.

+

Note that setting of code page, FF_CODE_PAGE, has actually no meaning when FatFs is configured for the Unicode API. It should be set 437 to reduce the module size. However it still affects code conversion of string I/O functions when FF_STRF_ENCODE == 0, and also backward compatibility with legacy systems. In this case, the code page may need to be configured properly if it is considered a problem.

+
+ +
+

exFAT Filesystem

+

The exFAT (Microsoft's Extended File Allocation Table) filesystem is a succession of the FAT/FAT32 filesystem which has been widely used in embedded systems, consumer devices and portable storage media. It is adopted by SDA (SD Association) as the filesystem for SDXC card, 64 GB and larger, and they are being shipped with this format. Therefore the exFAT is one of the standard filesystems for removable media as well as FAT. The exFAT filesystem allows the file size beyond the 4 GB limit what FAT filesystem allows up to and some filesystem overhead, especially cluster allocation delay, are reduced as well. These features allow to record the large data without dividing into some files and improve the write throughput to the file.

+

Note that the exFAT filesystem is a patent of Microsoft Corporation. The exFAT feature of FatFs is an implementation based on US. Pat. App. Pub. No. 2009/0164440 A1. FatFs module can switch the exFAT on or off by a configuration option, FF_FS_EXFAT. When enable the exFAT for the commercial products, a license by Microsoft will be needed depends on the final destination of the products.

+

Remarks: Enabling exFAT discards C89 compatibility and it wants C99 because of need for 64-bit integer type.

+
+ +
+

64-bit LBA

+

LBA (Logical Block Addressing) is an addressing method to specify the location of data block, called sector, on the storage media. It is a simple linear address beginning from 0 as the first sector, 1 as the second sector and so on. The host system does not need to consider how the data block is located and managed in the storage device. FatFs supports only LBA for the media access. 32-bit LBA is a common size in the most LBA scheme. It can address up to 232 sectors, 2 TB in 512 bytes/sector. When a storage device larger than 2 TB is used, larger sector size or 64-bit LBA will be needed to address the entire sectors of the storage device.

+

By default, FatFs works in 32-bit LBA for media access. FatFs can also switch it to 64-bit LBA by a configuration option FF_LBA64. It also enables GPT (GUID Partition Table) for partiotion management on the storage device. For further information about GPT, refer to f_mkfs and f_fdisk function.

+
+ +
+

Re-entrancy

+

The file operations of two tasks to the different volumes each other is always re-entrant and it can work concurrently without any mutual exclusion regardless of the configurations except when LFN is enabled with static working buffer (FF_USE_LFN = 1).

+

The file operations of two tasks to the same volume is not thread-safe by default. FatFs can also be configured to make it thread-safe by an option FF_FS_REENTRANT. When a file function is called while the volume is being accessed by another task, the file function to the volume will be suspended until that task leaves the file function. If the wait time exceeded a period defined by FF_TIMEOUT, the file function will abort with FR_TIMEOUT. The timeout feature might not be supported on the some OSs. To enable this feature, OS dependent synchronization control functions, ff_mutex_create/ff_mutex_delete/ff_mutex_take/ff_mutex_give, need to be added to the project. There is an example code in the ffsystem.c for some OSs.

+

Note that there is an exception on the re-entrancy for f_mount and f_mkfs function. You will know why it is. These volume management functions are always not thread-safe to the volume being processed. When use these functions, other tasks need to avoid to access the corresponding volume.

+
+ + + + + + + + +
FunctionCase 1Case 2Case 3
disk_statusYesYesYes(*)
disk_initializeNoYesYes(*)
disk_readNoYesYes(*)
disk_writeNoYesYes(*)
disk_ioctlNoYesYes(*)
get_fattimeNoYesYes
+ +Case 1: Same volume.
+Case 2: Different volume on the same drive.
+Case 3: Different volume on the different drive.
+(*) In only different drive number. + +
+

Remarks: This section describes on the re-entrancy of the FatFs module itself. The FF_FS_REENTRANT option enables only exclusive use of each filesystem objects and FatFs does not that prevent to re-enter the storage device control functions. Thus the device control layer needs to be always thread-safe when FatFs API is re-entered for different volumes. Right table shows which control function can be re-entered when FatFs API is re-entered on some conditions.

+
+ +
+

Duplicated File Open

+

FatFs module does not support the read/write collision control of duplicated open to a file. The duplicated open is permitted only when each of open method to a file is read mode. The duplicated open with one or more write mode to a file is always prohibited, and also open file must not be renamed or deleted. A violation of these rules can cause data collaption.

+

The file lock control can be enabled by FF_FS_LOCK option. The value of option defines the number of open objects to manage simultaneously. In this case, if any opening, renaming or removing against the file shareing rule that described above is attempted, the file function will be rejected with FR_LOCKED. If number of open objects, files and sub-directories, is equal to FF_FS_LOCK, an extra f_open/f_opendir function will fail with FR_TOO_MANY_OPEN_FILES.

+
+ +
+

Performance Effective File Access

+

For good read/write throughput on the small embedded systems with limited size of memory, application programmer should consider what process is done in the FatFs module. The file data on the volume is transferred in following sequence by f_read function.

+

Figure 1. Sector unaligned read (short)
+ +

+

Figure 2. Sector unaligned read (long)
+ +

+

Figure 3. Fully sector aligned read
+ +

+

The file I/O buffer is a sector buffer to read/write a part of data on the sector. The sector buffer is either file private sector buffer on each file object or shared sector buffer in the filesystem object. The buffer configuration option FF_FS_TINY determins which sector buffer is used for the file data transfer. When tiny buffer configuration (1) is selected, data memory consumption is reduced FF_MAX_SS bytes each file object. In this case, FatFs module uses only a sector buffer in the filesystem object for file data transfer and FAT/directory access. The disadvantage of the tiny buffer configuration is: the FAT data cached in the sector buffer will be lost by file data transfer and it must be reloaded at every cluster boundary. However it will be suitable for most application from view point of the decent performance and low memory comsumption.

+

Figure 1 shows that a partial sector, sector unaligned part of the file, is transferred via the file I/O buffer. At long data transfer shown in Figure 2, middle of transfer data that covers one or more sector is transferred to the application buffer directly. Figure 3 shows that the case of entier transfer data is aligned to the sector boundary. In this case, file I/O buffer is not used. On the direct transfer, the maximum extent of sectors are read with disk_read function at a time but the multiple sector transfer is divided at cluster boundary even if it is contiguous.

+

Therefore taking effort to sector aligned read/write accesss eliminates buffered data transfer and the read/write performance will be improved. Besides the effect, cached FAT data will not be flushed by file data transfer at the tiny configuration, so that it can achieve same performance as non-tiny configuration with small memory footprint.

+
+ +
+

Considerations on Flash Memory Media

+

To maximize the write performance of flash memory media, such as SDC, CFC and U Disk, it must be controlled in consideration of its characteristitcs.

+

Using Mutiple-Sector Write

+
+Figure 6. Comparison between Multiple/Single Sector Write
+fig.6 +
+

The write throughput of the flash memory media becomes the worst at single sector write transaction. The write throughput increases as the number of sectors per a write transaction as shown in Figure 6. This effect more appers at faster interface speed and the performance ratio often becomes grater than ten. This result is clearly explaining how fast is multiple block write (W:16K, 32 sectors) than single block write (W:100, 1 sector), and also larger card tends to be slow at single block write. Number of write transactions also affects life time of the flash memory media. When compared at same amount of write data, the single sector write in Figure 6 above wears flash memory media 16 times more than multiple sector write in Figure 6 below. Single sector write is pretty pain for the flash memory media.

+

Therefore the application program should write the data in large block as possible. The ideal write chunk size and alighment is size of sector, and size of cluster is the best. Of course all layers between the application and the storage device must have consideration on multiple sector write, however most of open-source memory card drivers lack it. Do not split a multiple sector write request into single sector write transactions or the write throughput gets poor. Note that FatFs module and its sample disk drivers supprt multiple sector read/write operation.

+

Forcing Memory Erase

+

When remove a file with f_unlink function, the data clusters occupied by the file are marked 'free' on the FAT. But the data sectors containing the file data are not that applied any process, so that the file data left occupies a part of the flash memory array as 'live block'. If the file data can be erased on removing the file, those data blocks will be turned into the free block pool. This may skip internal block erase operation to the data block on next write operation. As the result the write performance might be improved. FatFs can manage this function by setting FF_USE_TRIM to 1. Note that because this effect is from an expectation of internal process of the storage device, it is not that always effective. Most applications will not need this function. Also f_unlink function can take a time when remove a large file.

+
+ +
+

Critical Section

+

If a write operation to the FAT volume is interrupted due to an accidental failure, such as sudden blackout, wrong media removal and unrecoverable disk error, the FAT structure on the volume can be broken. Following images shows the critical section of the FatFs module.

+
+Figure 4. Long critical section
+fig.4 +
+
+Figure 5. Minimized critical section
+fig.5 +
+
+

An interruption in the red section can cause a cross link; as a result, the object being changed can be lost. If an interruption in the yellow section is occured, there is one or more possibility listed below.

+
    +
  • The file data being rewrited is collapsed.
    • +
  • The file being appended returns initial state.
    • +
  • The file created as new is gone.
    • +
  • The file created as new or overwritten remains but no content.
    • +
  • Efficiency of disk use gets worse due to lost clusters.
    • +
+

Each case does not affect any file not opened in write mode. To minimize risk of data loss, the critical section can be minimized by minimizing the time that file is opened in write mode or using f_sync function as shown in Figure 5.

+
+ +
+

Various Usable Functions for FatFs Projects

+

These are examples of extended use of FatFs APIs. New item will be added when useful code example is found.

+
    +
  1. Open or Create File for Append (superseded by FA_OPEN_APPEND flag added at R0.12)
    2. +
  2. Delete Non-empty Sub-directory (for R0.12 and later)
    3. +
  3. Create Contiguous File (superseded by f_expand function added at R0.12)
    4. +
  4. Test if the File is Contiguous or Not
    5. +
  5. Compatibility Checker for Storage Device Control Module
    6. +
  6. Performance Checker for Storage Device Control Module
    7. +
  7. FAT Volume Image Creator (Pre-creating built-in FAT volume)
    8. +
  8. Virtual Drive Feature (refer to lpc176x/ in ffsample.zip)
    9. +
  9. Embedded Unicode String Utilities (OEMxxx→Unicode, Unicode→OEMxxx, Unicode→Unicode)
    10. +
+
+ +
+

About FatFs License

+

FatFs has being developped as a personal project of the author, ChaN. It is free from the code anyone else wrote at current release. Following code block shows a copy of the FatFs license document that included in the source files.

+
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT Filesystem Module  Rx.xx                               /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 20xx, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+
+

Therefore FatFs license is one of the BSD-style licenses but there is a significant feature. FatFs is mainly intended for embedded systems. In order to extend the usability for commercial products, the redistributions of FatFs in binary form, such as embedded code, binary library and any forms without source code, does not need to include about FatFs in the documentations. This is equivalent to the 1-clause BSD license. Of course FatFs is compatible with the most of open source software licenses includes GNU GPL. When you redistribute the FatFs source code with any changes or create a fork, the license can also be changed to GNU GPL, BSD-style license or any open source software license that compatible with FatFs license.

+
+ +

Return Home

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/chdir.html b/Project/GateWay/source/Module/FatFS/documents/doc/chdir.html new file mode 100644 index 0000000..338406e --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/chdir.html @@ -0,0 +1,88 @@ + + + + + + + + +FatFs - f_chdir + + + + +
+

f_chdir

+

The f_chdir function changes the current directory of the logical drive.

+
+FRESULT f_chdir (
+  const TCHAR* path /* [IN] Path name */
+);
+
+
+ +
+

Parameters

+
+
path
+
Pointer to the null-terminated string that specifies the directory to be set as current directory.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_NO_PATH, +FR_INVALID_NAME, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT, +FR_NOT_ENOUGH_CORE +

+
+ + +
+

Description

+

The f_chdir function changes the current directory of the logical drive. Also the current drive will be changed when in Unix style drive prefix, FF_STR_VOLUME_ID == 2. The current directory of each logical drive is initialized to the root directory on mount.

+

Note that the current directory is retained in the each file system object and the current drive is retained in a static variable, so that it also affects other tasks that use the file functions.

+
+ + +
+

QuickInfo

+

Available when FF_FS_RPATH >= 1.

+
+ + +
+

Example

+
+    /* Change current direcoty of the current drive ("dir1" under root directory) */
+    f_chdir("/dir1");
+
+    /* Change current direcoty of current drive (parent directory of drive 2) */
+    f_chdir("2:..");
+
+    /* Change current direcoty of the drive "sdcard" (at DOS/Windows style volume ID) */
+    f_chdir("sdcard:/dir1");
+
+    /* Change current direcoty of the drive "flash" and set it as current drive (at Unix style volume ID) */
+    f_chdir("/flash/dir1");
+
+
+ +
+

See Also

+

f_chdrive, f_getcwd

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/chdrive.html b/Project/GateWay/source/Module/FatFS/documents/doc/chdrive.html new file mode 100644 index 0000000..e8412b1 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/chdrive.html @@ -0,0 +1,70 @@ + + + + + + + + +FatFs - f_chdrive + + + + +
+

f_chdrive

+

The f_chdrive function changes the current drive.

+
+FRESULT f_chdrive (
+  const TCHAR* path  /* [IN] Logical drive number */
+);
+
+
+ +
+

Parameters

+
+
path
+
Specifies the logical drive number to be set as the current drive.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_INVALID_DRIVE +

+
+ + +
+

Description

+

The f_chdrive function changes only the current drive. The initial value of the current drive number is 0. In Unix style drive prefix configuration, this function will not be needed because f_chdir function changes also the current drive. Note that the current drive is retained in a static variable, so that it also affects other tasks that using the file functions.

+
+ +
+

QuickInfo

+

Available when FF_FS_RPATH >= 1.

+
+ + +
+

Example

+
+    f_chdrive("2:");  /* Set drive 2 as current drive */
+
+    f_chdrive("");    /* No effect (set current drive as current drive) */
+
+
+ + +
+

See Also

+

f_chdir, f_getcwd

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/chmod.html b/Project/GateWay/source/Module/FatFS/documents/doc/chmod.html new file mode 100644 index 0000000..0da34b2 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/chmod.html @@ -0,0 +1,89 @@ + + + + + + + + +FatFs - f_chmod + + + + +
+

f_chmod

+

The f_chmod function changes the attribute of a file or sub-directory.

+
+FRESULT f_chmod (
+  const TCHAR* path, /* [IN] Object name */
+  BYTE attr,         /* [IN] Attribute flags */
+  BYTE mask          /* [IN] Attribute masks */
+);
+
+
+ +
+

Parameters

+
+
path
+
Pointer to the null-terminated string that specifies an object to be changed
+
attr
+
Attribute flags to be set in one or more combination of the following flags. The specified flags are set and others are cleard.
+ + + + + + +
AttributeDescription
AM_RDORead only
AM_ARCArchive
AM_SYSSystem
AM_HIDHidden
+
+
mask
+
Attribute mask that specifies which attribute is changed. The specified attributes are set or cleard and others are left unchanged.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_NO_FILE, +FR_NO_PATH, +FR_INVALID_NAME, +FR_WRITE_PROTECTED, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT, +FR_NOT_ENOUGH_CORE +

+
+ + +
+

Description

+

The f_chmod function changes the attribute of a file or sub-directory.

+
+ + +
+

QuickInfo

+

Available when FF_FS_READONLY == 0 and FF_USE_CHMOD == 1.

+
+ + +
+

Example

+
+    /* Set Read-only, clear Archive and others are left unchanged. */
+    f_chmod("file.txt", AM_RDO, AM_RDO | AM_ARC);
+
+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/close.html b/Project/GateWay/source/Module/FatFS/documents/doc/close.html new file mode 100644 index 0000000..4f709af --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/close.html @@ -0,0 +1,65 @@ + + + + + + + + +FatFs - f_close + + + + +
+

f_close

+

The f_close function closes an open file.

+
+FRESULT f_close (
+  FIL* fp     /* [IN] Pointer to the file object */
+);
+
+
+ +
+

Parameter

+
+
fp
+
Pointer to the open file object structure to be closed.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_INVALID_OBJECT, +FR_TIMEOUT +

+
+ + +
+

Description

+

The f_close function closes an open file object. If the file has been changed, the cached information of the file is written back to the volume. After the function succeeded, the file object is no longer valid and it can be discarded.

+

Note that if the file object is in read-only mode and FF_FS_LOCK is not enabled, the file object can also be discarded without this procedure. However this is not recommended for future compatibility.

+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, f_read, f_write, f_sync, FIL, FATFS

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/closedir.html b/Project/GateWay/source/Module/FatFS/documents/doc/closedir.html new file mode 100644 index 0000000..79ce1ad --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/closedir.html @@ -0,0 +1,64 @@ + + + + + + + + +FatFs - f_closedir + + + + +
+

f_closedir

+

The f_closedir function closes an open directory.

+
+FRESULT f_closedir (
+  DIR* dp     /* [IN] Pointer to the directory object */
+);
+
+
+ +
+

Parameter

+
+
dp
+
Pointer to the open directory object structure to be closed.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_INT_ERR, +FR_INVALID_OBJECT, +FR_TIMEOUT +

+
+ + +
+

Description

+

The f_closedir function closes an open directory object. After the function succeeded, the directory object is no longer valid and it can be discarded.

+

Note that the directory object can also be discarded without this procedure when option FF_FS_LOCK is not enabled. However this is not recommended for future compatibility.

+
+ + +
+

QuickInfo

+

Available when FF_FS_MINIMIZE <= 1.

+
+ + +
+

See Also

+

f_opendir, f_readdir, DIR

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/config.html b/Project/GateWay/source/Module/FatFS/documents/doc/config.html new file mode 100644 index 0000000..6196fd1 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/config.html @@ -0,0 +1,304 @@ + + + + + + + + +FatFs - Configuration Options + + + +

Configuration Options

+

There are many options to configure the features of FatFs for various requirements of each project. The configuration options are defined in ffconf.h.

+ + +
+

Function Configurations

+ +

FF_FS_READONLY

+

Read/Write (0) or Read-only (1). Read-only configuration removes writing API functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, f_truncate, f_getfree and optional writing functions as well.

+ +

FF_FS_MINIMIZE

+

This option defines minimization level to remove some basic API functions as follows:

+ + + + + + +
ValueDescription
0All basic API functions are available.
1f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_utime, f_truncate and f_rename function are removed.
2f_opendir, f_readdir and f_closedir function are removed in addition to 1.
3f_lseek function is removed in addition to 2.
+ +

FF_USE_FIND

+

Disable (0) or Enable (1) filtered directory read functions, f_findfirst and f_findnext. Also FF_FS_MINIMIZE needs to be 0 or 1.

+ +

FF_USE_MKFS

+

Disable (0) or Enable (1) f_mkfs function.

+ +

FF_USE_FASTSEEK

+

Disable (0) or Enable (1) fast seek function to enable accelerated mode for f_lseek, f_read and f_write function. For more information, read here.

+ +

FF_USE_EXPAND

+

Disable (0) or Enable (1) f_expand function.

+ +

FF_USE_CHMOD

+

Disable (0) or Enable (1) metadata control functions, f_chmod and f_utime. Also FF_FS_READONLY needs to be 0.

+ +

FF_USE_LABEL

+

Disable (0) or Enable (1) API functions for volume label, f_getlabel and f_setlabel.

+ +

FF_USE_FORWARD

+

Disable (0) or Enable (1) f_forward function.

+ +

FF_USE_STRFUNC

+

This option switches string functions, f_gets, f_putc, f_puts and f_printf. These functions are equivalents of regular string stream I/O functions in POSIX. If sprintf is available and code conversion is not needed, f_write with sprintf will be efficient in code size and performance rather than f_printf. When enable this feature, stdarg.h is included in ff.c.

+ + + + + +
ValueDescription
0Disable string functions.
1Enable string functions without LF-CRLF conversion.
2Enable string functions with LF-CRLF conversion.
+ + +

This option switches support for long long integer argument in f_printf.

+

Disable (0) or Enable (1). When enable this feature, C standard needs to be C99 or later.

+ + +

This option switches support for floating point argument in f_printf. When enable this feature, C standard needs to be C99 or later and math.h is included in ff.c.

+ + + + + +
ValueDescription
0Disable floating point argument.
1Enable floating point argument in type 'f', 'e' and 'E'.
2Enable it with decimal separator ',' instead of '.'.
+ +

FF_STRF_ENCODE

+

When character encoding on the API is Unicode (FF_LFN_UNICODE >= 1), string I/O functions enabled by FF_USE_STRFUNC convert the character encoding in it. This option defines the assumption of character encoding on the file to be read/written via those functions. When LFN is not enabled or FF_LFN_UNICODE == 0, the string functions work without any code conversion and this option has no effect.

+ + + + + + +
ValueCharacter encoding on the file
0ANSI/OEM in current code page
1Unicode in UTF-16LE
2Unicode in UTF-16BE
3Unicode in UTF-8
+ +
+ + +
+

Namespace and Locale Configurations

+ +

FF_CODE_PAGE

+

This option specifies the OEM code page used on the target system. Incorrect setting of the code page can cause a file open failure. If any non-ASCII character is not used for the path name or FF_LFN_UNICODE != 0, there is no difference between any code page settings. Set it 437 anyway.

+ + + + + + + + + + + + + + + + + + + + + + + + +
ValueCode page
0Includes all code pages below and set by f_setcp()
437U.S.
720Arabic
737Greek
771KBL
775Baltic
850Latin 1
852Latin 2
855Cyrillic
857Turkish
860Portuguese
861Icelandic
862Hebrew
863Canadian French
864Arabic
865Nordic
866Russian
869Greek 2
932Japanese (DBCS)
936Simplified Chinese (DBCS)
949Korean (DBCS)
950Traditional Chinese (DBCS)
+ +

FF_USE_LFN

+

This option switches the support for long file name (LFN). When enable the LFN, Unicode support module ffunicode.c need to be added to the project. When use stack for the working buffer, take care on stack overflow. When use heap memory for the working buffer, memory management functions (ff_memalloc and ff_memfree) need to be added to the project.

+ + + + + + +
ValueDescription
0Disable LFN. Path name in only 8.3 format can be used.
1Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
2Enable LFN with dynamic working buffer on the STACK.
3Enable LFN with dynamic working buffer on the HEAP.
+ +

FF_MAX_LFN

+

LFN function requiers certain internal working buffer for the file name. This option defines size of the buffer and the value can be in range of 12 to 255 characters (actually in UTF-16 code units) of the LFN. The buffer occupies (FF_MAX_LFN + 1) * 2 bytes and additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled. It is recommended to be set 255 to fully support the LFN specification. This option has no effect when LFN is not enabled.

+ +

FF_LFN_UNICODE

+

This option switches character encoding for the file name on the API. FatFs supports the code point up to U+10FFFF. This option also affects behavior of string I/O functions (see FF_STRF_ENCODE).

+ + + + + + +
ValueCharacter EncodingTCHAR
0ANSI/OEM in current CPchar
1Unicode in UTF-16WCHAR
2Unicode in UTF-8char
3Unicode in UTF-32DWORD
+

When Unicode is selected, FF_CODE_PAGE has actually no meaning except for compatibility with legacy systems, such as MS-DOS and any system without support for LFN.

+

When LFN is not enabled, this option has no effect and FatFs works in ANSI/OEM code on the API. For more information, read here.

+ +

FF_LFN_BUF, FF_SFN_BUF

+

This set of options defines size of file name members, fname[] and altname[], in the FILINFO structure which is used to read out the directory items. These values should be suffcient for the file names to read. The maximum possible length of read file name depends on the character encoding scheme on the API as follows:

+ + + + + + +
EncodingLFN lengthSFN length
ANSI/OEM in SBCS255 items12 items
ANSI/OEM in DBCS510 items12 items
Unicode in UTF-16/32255 items12 items
Unicode in UTF-8765 items34 items
+

If the size of name member is insufficient for the LFN, the item is treated as without LFN. When LFN is not enabled, these options have no effect.

+ +

FF_FS_RPATH

+

This option configures relative path function. For more information, read here.

+ + + + + +
ValueDescription
0Disable relative path and remove related functions.
1Enable relative path. f_chdir and f_chdrive function is available.
2f_getcwd function is available in addition to 1
+ +
+ + +
+

Volume/Drive Configurations

+ +

FF_VOLUMES

+

This option configures number of volumes (logical drives up to 10) to be used.

+ +

FF_STR_VOLUME_ID

+

This option switches the support for string volume ID. When arbitrary string for the volume ID is enabled for the drive prefix, also pre-defined strings by FF_VOLUME_STRS or user defined strings can be used as drive prefix in the path name. Numeric drive number is always valid regardless of this option, and also either format of drive prefix can be enabled by this option.

+ + + + + +
ValueDescriptionExample
0Only DOS/Windows style drive prefix in numeric ID can be used.1:/filename
1Also DOS/Windows style drive prefix in string ID can be used.flash:/filename
2Also Unix style drive prefix in string ID can be used./flash/filename
+ +

FF_VOLUME_STRS

+

This option defines the volume ID strings for each logical drives. Number of items must not be less than FF_VOLUMES. Valid characters for the volume ID string are A-Z, a-z and 0-9, however, they are compared in case-insensitive. If FF_STR_VOLUME_ID == 0, this option has no effect. If FF_STR_VOLUME_ID >= 1 and this option is not defined, a user defined volume string table needs to be defined as shown below. The table should not be modified on the fly.

+
+/* User defined volume ID strings for 0: to 3: */
+const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb"};
+
+ +

FF_MULTI_PARTITION

+

Disable (0) or Enable (1). This option switches multi-partition function. By default (0), each logical drive number is bound to the same physical drive number and only a volume in the physical drive is mounted. When enabled, each logical drive is bound to the partition on the physical drive listed in the user defined partition resolution table VolToPart[]. Also f_fdisk funciton will be available. For more information, read here.

+ +

FF_MIN_SS, FF_MAX_SS

+

This set of options defines the extent of sector size used for the low level disk I/O interface, disk_read and disk_write function. Valid values are 512, 1024, 2048 and 4096. FF_MIN_SS defines minimum sector size and FF_MAX_SS defines the maximum sector size. Always set both 512 for memory card and harddisk. But a larger value may be required for on-board flash memory and some type of optical media. When FF_MAX_SS > FF_MIN_SS, support of variable sector size is enabled and GET_SECTOR_SIZE command needs to be implemented to the disk_ioctl function.

+ +

FF_LBA64

+

This option switches media access interface to 64-bit LBA and enables GUID Partition Table (GPT) for partition management, Enabled (1) or Disabled (0). exFAT filesystem needs to be enabled to enable this feature.

+ +

FF_MIN_GPT

+

This option specifies the threshold of determination of partitioning format when create patitions on the drive in f_mkfs and f_fdisk function. When number of available sectors is equal or larger than this value, the drive will be partitioned in GPT. This option has no effect when FF_LBA64 == 0.

+ +

FF_USE_TRIM

+

Disable (0) or Enable (1). This option switches ATA-TRIM function. To enable Trim function, also CTRL_TRIM command should be implemented to the disk_ioctl function.

+ +
+ + +
+

System Configurations

+ +

FF_FS_TINY

+

Normal (0) or Tiny (1). The tiny configuration reduces size of the FIL structure, file object, FF_MAX_SS bytes each. Instead of private sector buffer eliminated from the file object, common sector buffer in the FATFS structure, filesystem object, is used for the file data transfer.

+ +

FF_FS_EXFAT

+

This option switches support for exFAT filesystem in addition to the FAT/FAT32 filesystem, Enabled (1) or Disabled (0). To enable exFAT, also LFN must be enabled and configureing FF_LFN_UNICODE >= 1 and FF_MAX_LFN == 255 is recommended for full-featured exFAT function. Note that enabling exFAT discards ANSI C (C89) compatibility and wants C99 because of need for 64-bit integer type.

+ +

FF_FS_NORTC

+

Use RTC (0) or Do not use RTC (1). This option controls timestamp featuer. If the system does not have an RTC or valid timestamp is not needed, set FF_FS_NORTC to 1 to disable the timestamp function. Every objects modified by FatFs will have a constant timestamp defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR. To use the timestamp featuer, set FF_FS_NORTC == 0 and add get_fattime function to the project to get current time form the RTC. This option has no effect in read-only configuration.

+ +

FF_NORTC_MON, FF_NORTC_MDAY, FF_NORTC_YEAR

+

This set of options defines the time to be used in no RTC systems. This option has no effect in read-only configuration or FF_FS_NORTC == 0.

+ +

FF_FS_NOFSINFO

+

0 to 3. If you need to know correct free space on the FAT32 volume, set bit 0 of this option, and f_getfree function at first time after the volume mounted will force a full FAT scan. Bit 1 controls the use of last allocated cluster number for new allocation.

+ + + + + + +
ValueDescription
bit0=0Use free cluster count in the FSINFO if available.
bit0=1Do not trust free cluster count in the FSINFO.
bit1=0Use last allocated cluster number in the FSINFO to find a free cluster if available.
bit1=1Do not trust last allocated cluster number in the FSINFO.
+ +

FF_FS_LOCK

+

This option switches file lock feature to control duplicated file open and illegal operations to the open objects. Note that this feature is independent of re-entrancy. This option must be 0 in read-only configuration.

+ + + + +
ValueDescription
0Disable file lock feature. To avoid to collapse files due to wrong file operations, application program needs to avoid illegal open, remove and rename to the open objects.
>0Enable file lock feature. The value defines how many files/sub-directories can be opened simultaneously under the file lock feature. Illigal operations to the open object will be rejected with FR_LOCKED.
+ +

FF_FS_REENTRANT

+

Disable (0) or Enable (1). This option switches the re-entrancy (thread safe) of the FatFs module itself. Note that file/directory access to the different volume is always re-entrant and it can work simultaneously regardless of this option, however, volume management functions, f_mount, f_mkfs and f_fdisk, are always not re-entrant. Only file/directory access to the same volume, in other words, exclusive use of each filesystem object, is under control in this feature. To enable this feature, also user provided synchronization handlers, ff_mutex_take, ff_mutex_give, ff_mutex_create and ff_mutex_delete, need to be added to the project. Sample code is available in ffsystem.c.

+ +

FF_FS_TIMEOUT

+

Number of O/S time ticks to abort the file function with FR_TIMEOUT when the wait time exceeds this period. This option has no effect when FF_FS_REENTRANT == 0.

+ +
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/dinit.html b/Project/GateWay/source/Module/FatFS/documents/doc/dinit.html new file mode 100644 index 0000000..a5b799f --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/dinit.html @@ -0,0 +1,46 @@ + + + + + + + + +FatFs - disk_initialize + + + + +
+

disk_initialize

+

The disk_initialize function is called to initializes the storage device.

+
+DSTATUS disk_initialize (
+  BYTE pdrv           /* [IN] Physical drive number */
+);
+
+
+ +
+

Parameter

+
+
pdrv
+
Physical drive number to identify the target device. Always zero at single drive system.
+
+
+ + +
+

Return Values

+

This function returns the current drive status flags as the result. For details of the drive status, refer to the disk_status function.

+
+ +
+

Description

+

This function initializes the storage device and put it ready to generic read/write. When the function succeeded, STA_NOINIT flag in the return value is cleared.

+

Remarks: This function needs to be under control of FatFs module. Application program MUST NOT call this function while FatFs is in use, or FAT structure on the volume can be broken. To re-initialize the filesystem, use f_mount function instead.

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/dioctl.html b/Project/GateWay/source/Module/FatFS/documents/doc/dioctl.html new file mode 100644 index 0000000..8a7a394 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/dioctl.html @@ -0,0 +1,101 @@ + + + + + + + + +FatFs - disk_ioctl + + + + +
+

disk_ioctl

+

The disk_ioctl function is called to control device specific features and miscellaneous functions other than generic read/write.

+
+DRESULT disk_ioctl (
+  BYTE pdrv,     /* [IN] Drive number */
+  BYTE cmd,      /* [IN] Control command code */
+  void* buff     /* [I/O] Parameter and data buffer */
+);
+
+
+ +
+

Parameters

+
+
pdrv
+
Physical drive number to identify the target device.
+
cmd
+
Command code.
+
buff
+
Pointer to the parameter depends on the command code. Do not care if the command has no parameter to be passed.
+
+
+ + +
+

Return Value

+
+
RES_OK (0)
+
The function succeeded.
+
RES_ERROR
+
An error occured.
+
RES_PARERR
+
The command code or parameter is invalid.
+
RES_NOTRDY
+
The device has not been initialized.
+
+
+ + +
+

Description

+

The FatFs module requires only five device independent commands described below.

+ + + + + + + + +
Standard ioctl command used by FatFs
CommandDescription
CTRL_SYNCMakes sure that the device has finished pending write process. If the disk I/O layer or storage device has a write-back cache, the dirty cache data must be committed to the medium immediately. Nothing to do for this command if each write operation to the medium is completed in the disk_write function.
GET_SECTOR_COUNTRetrieves number of available sectors, the largest allowable LBA + 1, on the drive into the LBA_t variable that pointed by buff. This command is used by f_mkfs and f_fdisk function to determine the size of volume/partition to be created.
GET_SECTOR_SIZERetrieves sector size, minimum data unit for generic read/write, into the WORD variable that pointed by buff. Valid sector sizes are 512, 1024, 2048 and 4096. This command is required only if FF_MAX_SS > FF_MIN_SS. When FF_MAX_SS == FF_MIN_SS, this command will never be used and the disk_read and disk_write function must work in FF_MAX_SS bytes/sector.
GET_BLOCK_SIZERetrieves erase block size in unit of sector of the flash memory media into the DWORD variable that pointed by buff. The allowable value is 1 to 32768 in power of 2. Return 1 if it is unknown or in non flash memory media. This command is used by f_mkfs function with block size not specified and it attempts to align the data area on the suggested block boundary. Note that FatFs does not have FTL (flash translation layer), so that either disk I/O layter or storage device must have an FTL in it.
CTRL_TRIMInforms the disk I/O layter or the storage device that the data on the block of sectors is no longer needed and it can be erased. The sector block is specified in an LBA_t array {<Start LBA>, <End LBA>} that pointed by buff. This is an identical command to Trim of ATA device. Nothing to do for this command if this funcion is not supported or not a flash memory device. FatFs does not check the result code and the file function is not affected even if the sector block was not erased well. This command is called on remove a cluster chain and in the f_mkfs function. It is required when FF_USE_TRIM == 1.
+ +

FatFs will never use any device dependent command nor user defined command. Following table shows an example of non-standard commands which may be useful for some applications.

+ + + + + + + + + + + + + + + + + + + + + +
Example of optional ioctl command
CommandDescription
CTRL_FORMATCreates a physical format on the media. If buff is not null, it is pointer to the call-back function for progress notification.
CTRL_POWER_IDLEPuts the device idle state. STA_NOINIT in the current status flags may not be set if the device goes active state by generic read/write function.
CTRL_POWER_OFFPuts the device off state. Shut-down the power to the device and deinitialize the device interface if needed. STA_NOINIT in the current status flags must be set. The device goes active state by disk_initialize function.
CTRL_LOCKLocks media eject mechanism.
CTRL_UNLOCKUnlocks media eject mechanism.
CTRL_EJECTEjects media cartridge. STA_NOINIT and STA_NODISK in status flag are set after the function succeeds.
CTRL_GET_SMARTReads SMART information.
MMC_GET_TYPEGets card type. The type flags, bit0:MMCv3, bit1:SDv1, bit2:SDv2+ and bit3:LBA, is stored to a BYTE variable pointed by buff. (MMC/SDC specific command)
MMC_GET_CSDReads CSD register and sets it into a 16-byte buffer pointed by buff. (MMC/SDC specific command)
MMC_GET_CIDReads CID register and sets it into a 16-byte buffer pointed by buff. (MMC/SDC specific command)
MMC_GET_OCRReads OCR register and sets it into a 4-byte buffer pointed by buff. (MMC/SDC specific command)
MMC_GET_SDSTATReads SDSTATUS register and sets it into a 64-byte buffer pointed by buff. (SDC specific command)
ATA_GET_REVReads the revision string and sets it into a 16-byte buffer pointed by buff. (ATA/CFC specific command)
ATA_GET_MODELReads the model string and sets it into a 40-byte buffer pointed by buff. (ATA/CFC specific command)
ATA_GET_SNReads the serial number string and sets it into a 20-byte buffer pointed by buff. (ATA/CFC specific command)
ISDIO_READReads a block of iSDIO registers specified by command structure pointed by buff. (FlashAir specific command)
ISDIO_WRITEWrites a block of data to iSDIO registers specified by command structure pointed by buff. (FlashAir specific command)
ISDIO_MRITEChanges bits in an iSDIO register specified by command structure pointed by buff. (FlashAir specific command)
+
+ + +
+

QuickInfo

+

The disk_ioctl function is not needed when FF_FS_READONLY == 1 and FF_MAX_SS == FF_MIN_SS.

+
+ + +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/dread.html b/Project/GateWay/source/Module/FatFS/documents/doc/dread.html new file mode 100644 index 0000000..fa95479 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/dread.html @@ -0,0 +1,73 @@ + + + + + + + + +FatFs - disk_read + + + + +
+

disk_read

+

The disk_read function is called to read data from the storage device.

+
+DRESULT disk_read (
+  BYTE pdrv,     /* [IN] Physical drive number */
+  BYTE* buff,    /* [OUT] Pointer to the read data buffer */
+  LBA_t sector,  /* [IN] Start sector number */
+  UINT count     /* [IN] Number of sectros to read */
+);
+
+
+ +
+

Parameters

+
+
pdrv
+
Physical drive number to identify the target device.
+
buff
+
Pointer to the first item of the byte array to store read data. Size of read data will be the sector size * count bytes.
+
sector
+
Start sector number in LBA. The data type LBA_t is an alias of DWORD or QWORD depends on the configuration option.
+
count
+
Number of sectors to read.
+
+
+ + +
+

Return Value

+
+
RES_OK (0)
+
The function succeeded.
+
RES_ERROR
+
An unrecoverable hard error occured during the read operation.
+
RES_PARERR
+
Invalid parameter.
+
RES_NOTRDY
+
The device has not been initialized.
+
+
+ + +
+

Description

+

Read/write operation to the generic storage devices, such as memory card, hadddisk and optical disk, is done in unit of block of data bytes called sector. FatFs supports the sector size in range of 512 to 4096 bytes. When FatFs is configured for fixed sector size (FF_MIN_SS == FF_MAX_SS, this is the most case), the generic read/write function must work at this sector size only. When FatFs is configured for variable sector size (FF_MIN_SS < FF_MAX_SS), the sector size of medium is inquired with disk_ioctl function after disk_initialize function succeeds.

+

There are some considerations about the memory addres passed via buff. It is not that always aligned with the word boundary, because the argument is defined as BYTE*. The unaligned transfer request can occure at direct transfer. If the bus architecture, especially DMA controller, does not allow unaligned memory access, it should be solved in this function. If it is the case, there are some workarounds described below to avoid this issue.

+
    +
  • Convert word transfer to byte transfer with some trick in this function. - Recommended.
    • +
  • On the f_read() calls, avoid long read request that includes a whole of sector. - Any direct transfer never occures.
    • +
  • On the f_read(fp, data, btw, bw) calls, make sure that (((UINT)data & 3) == (f_tell(fp) & 3)) is true. - Word alignment of buff is guaranteed.
    • +
+

Also the memory area may be out of reach in DMA. This is the case if it is located on the tightly coupled memory which is usually used for stack. Use double buffered transfer, or avoid to define file I/O buffer, FATFS and FIL structure as local variables where on the stack.

+

Generally, a multiple sector read request must not be split into single sector transactions to the storage device, or read throughput gets worse.

+
+ + +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/dstat.html b/Project/GateWay/source/Module/FatFS/documents/doc/dstat.html new file mode 100644 index 0000000..1456668 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/dstat.html @@ -0,0 +1,48 @@ + + + + + + + + +FatFs - disk_status + + + + +
+

disk_status

+

The disk_status function is called to inquire the current drive status.

+
+DSTATUS disk_status (
+  BYTE pdrv     /* [IN] Physical drive number */
+);
+
+
+ +
+

Parameter

+
+
pdrv
+
Physical drive number to identify the target device. Always zero in single drive system.
+
+
+ + +
+

Return Values

+

The current drive status is returned in combination of status flags described below. FatFs refers only STA_NOINIT and STA_PROTECT.

+
+
STA_NOINIT
+
Indicates that the device has not been initialized and not ready to work. This flag is set on system reset, media removal or failure of disk_initialize function. It is cleared on disk_initialize function succeeded. Any media change that occurs asynchronously must be captured and reflect it to the status flags, or auto-mount function will not work correctly. If the system does not support media change detection, application program needs to explicitly re-mount the volume with f_mount function after each media change.
+
STA_NODISK
+
Indicates that no medium in the drive. This is always cleared when the drive is non-removable class. Note that FatFs does not refer this flag.
+
STA_PROTECT
+
Indicates that the medium is write protected. This is always cleared when the drive has no write protect function. Not valid if STA_NODISK is set.
+
+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/dwrite.html b/Project/GateWay/source/Module/FatFS/documents/doc/dwrite.html new file mode 100644 index 0000000..e449752 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/dwrite.html @@ -0,0 +1,76 @@ + + + + + + + + +FatFs - disk_write + + + + +
+

disk_write

+

The disk_write function is called to write data to the storage device.

+
+DRESULT disk_write (
+  BYTE pdrv,        /* [IN] Physical drive number */
+  const BYTE* buff, /* [IN] Pointer to the data to be written */
+  LBA_t sector,     /* [IN] Sector number to write from */
+  UINT count        /* [IN] Number of sectors to write */
+);
+
+
+ +
+

Parameters

+
+
pdrv
+
Physical drive number to identify the target device.
+
buff
+
Pointer to the first item of the byte array to be written. The size of data to be written is sector size * count bytes.
+
sector
+
Start sector number in LBA. The data type LBA_t is an alias of DWORD or QWORD depends on the configuration option.
+
count
+
Number of sectors to write.
+
+
+ + +
+

Return Values

+
+
RES_OK (0)
+
The function succeeded.
+
RES_ERROR
+
An unrecoverable hard error occured during the write operation.
+
RES_WRPRT
+
The medium is write protected.
+
RES_PARERR
+
Invalid parameter.
+
RES_NOTRDY
+
The device has not been initialized.
+
+
+ + +
+

Description

+

The specified memory address is not that always aligned to word boundary because the argument is defined as BYTE*. For more information, refer to the description of disk_read function.

+

Generally, a multiple sector write request (count > 1) must not be split into single sector transactions to the storage device, or the file write throughput will be drastically decreased.

+

FatFs expects delayed write function of the disk control layer. The write operation to the media does not need to be completed when return from this function by what write operation is in progress or data is only stored into the write-back cache. But write data on the buff is invalid after return from this function. The write completion request is done by CTRL_SYNC command of disk_ioctl function. Therefore, if a delayed write function is implemented, the write throughput of the filesystem will be improved.

+

Remarks: Application program MUST NOT call this function, or FAT structure on the volume can be collapsed.

+
+ + +
+

QuickInfo

+

This function is not needed when FF_FS_READONLY == 1.

+
+ + +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/eof.html b/Project/GateWay/source/Module/FatFS/documents/doc/eof.html new file mode 100644 index 0000000..3d4fab2 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/eof.html @@ -0,0 +1,62 @@ + + + + + + + + +FatFs - f_eof + + + + +
+

f_eof

+

The f_eof function tests for end-of-file on a file.

+
+int f_eof (
+  FIL* fp   /* [IN] File object */
+);
+
+
+ + +
+

Parameters

+
+
fp
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Values

+

The f_eof function returns a non-zero value if the read/write pointer has reached end of the file; otherwise it returns a zero.

+
+ + +
+

Description

+

In this revision, this function is implemented as a macro. It does not have any validation and mutual exclusion.

+
+#define f_eof(fp) ((int)((fp)->fptr == (fp)->fsize))
+
+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, f_lseek, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/error.html b/Project/GateWay/source/Module/FatFS/documents/doc/error.html new file mode 100644 index 0000000..685b7f2 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/error.html @@ -0,0 +1,62 @@ + + + + + + + + +FatFs - f_error + + + + +
+

f_error

+

The f_error tests for an error on a file.

+
+int f_error (
+  FIL* fp   /* [IN] File object */
+);
+
+
+ + +
+

Parameters

+
+
fp
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Values

+

Returns a non-zero value if a hard error has occured; otherwise it returns a zero.

+
+ + +
+

Description

+

In this revision, this function is implemented as a macro. It does not have any validation and mutual exclusion.

+
+#define f_error(fp) ((fp)->err)
+
+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/expand.html b/Project/GateWay/source/Module/FatFS/documents/doc/expand.html new file mode 100644 index 0000000..c753c2f --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/expand.html @@ -0,0 +1,117 @@ + + + + + + + + +FatFs - f_expand + + + + +
+

f_expand

+

The f_expand function prepares or allocates a contiguous data area to the file.

+ +
+FRESULT f_expand (
+  FIL*    fp,  /* [IN] File object */
+  FSIZE_t fsz, /* [IN] File size expanded to */
+  BYTE    opt  /* [IN] Allocation mode */
+);
+
+
+ +
+

Parameters

+
+
fp
+
Pointer to the open file object.
+
fsz
+
Number of bytes in size to prepare or allocate for the file. The data type FSIZE_t is an alias of either DWORD(32-bit) or QWORD(64-bit) depends on the configuration option FF_FS_EXFAT.
+
opt
+
Allocation mode. Prepare to allocate (0) or Allocate now (1).
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_INVALID_OBJECT, +FR_DENIED, +FR_TIMEOUT +

+
+ + +
+

Description

+

The f_expand function prepares or allocates a contiguous data area to the file. When opt is 1, the data area is allocated to the file in this function. Unlike expansion of file size by f_lseek function, the file must be truncated prior to use this function and read/write pointer of the file stays at offset 0 after the function call. The file content allocated with this function is undefined, because no data is written to the file in this process. The function can fail with FR_DENIED due to some reasons below.

+
    +
  • No free contiguous space was found.
    • +
  • Size of the file was not zero.
    • +
  • The file has been opened in read-only mode.
    • +
  • Not allowable file size. (>= 4 GB on FAT volume)
    • +
+

When opt is 0, the function finds a contiguous data area and set it as suggested point for next allocation. The subsequent cluster allocation begins at top of the contiguous area found by this function. Thus the file allocation is guaranteed be contiguous and without allocation delay until the file size reaches this size unless any other changes to the volume is performed.

+

The contiguous file has an advantage for time-critical read/write operations. It eliminates some overheads in the filesystem and the storage device caused by random access for fragmented file.

+

Also the contiguous file can be easily accessed directly via low-level disk functions. However, this is not recommended in consideration of portability and future compatibility. If the file has not been confirmed be contiguous, use this function to examine if the file is contiguous or not.

+
+ +
+

QuickInfo

+

Available when FF_USE_EXPAND == 1 and FF_FS_READONLY == 0.

+
+ + +
+

Example

+
+    /* Creating a contiguous file */
+
+    /* Create a new file */
+    res = f_open(fp = malloc(sizeof (FIL)), "file.dat", FA_WRITE|FA_CREATE_ALWAYS);
+    if (res) { /* Check if the file has been opened */
+        free(fp);
+        die("Failed to open the file.");
+    }
+
+    /* Alloacte a 100 MiB of contiguous area to the file */
+    res = f_expand(fp, 104857600, 1);
+    if (res) { /* Check if the file has been expanded */
+        f_close(fp);
+        free(fp);
+        die("Failed to allocate contiguous area.");
+    }
+
+    /* Now you have a contiguous file accessible with fp */
+
+
+
+    /* Accessing the contiguous file via low-level disk functions */
+
+    /* Get physical location of the file data */
+    drv = fp->obj.fs->pdrv;
+    lba = fp->obj.fs->database + fp->obj.fs->csize * (fp->obj.sclust - 2);
+
+    /* Write 2048 sectors from top of the file at a time */
+    res = disk_write(drv, buffer, lba, 2048);
+
+
+
+ + +
+

See Also

+

f_open, f_lseek, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/fattime.html b/Project/GateWay/source/Module/FatFS/documents/doc/fattime.html new file mode 100644 index 0000000..220f69b --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/fattime.html @@ -0,0 +1,80 @@ + + + + + + + + +FatFs - get_fattime + + + + +
+

get_fattime

+

The get_fattime function is called to get the current time.

+
+DWORD get_fattime (void);
+
+
+ + +
+

Return Value

+

Currnet local time shall be returned as bit-fields packed into a DWORD value. The bit fields are as follows:

+
+
bit31:25
+
Year origin from the 1980 (0..127, e.g. 37 for 2017)
+
bit24:21
+
Month (1..12)
+
bit20:16
+
Day of the month (1..31)
+
bit15:11
+
Hour (0..23)
+
bit10:5
+
Minute (0..59)
+
bit4:0
+
Second / 2 (0..29, e.g. 25 for 50)
+
+
+ + +
+

Description

+

The get_fattime function shall return any valid time even if the system does not support a real time clock. If a zero is returned, the file will not have a valid timestamp.

+
+ + +
+

QuickInfo

+

This function is not needed when FF_FS_READONLY == 1 or FF_FS_NORTC == 1.

+
+ + +
+

Example

+
+DWORD get_fattime (void)
+{
+    time_t t;
+    struct tm *stm;
+
+
+    t = time(0);
+    stm = localtime(&t);
+
+    return (DWORD)(stm->tm_year - 80) << 25 |
+           (DWORD)(stm->tm_mon + 1) << 21 |
+           (DWORD)stm->tm_mday << 16 |
+           (DWORD)stm->tm_hour << 11 |
+           (DWORD)stm->tm_min << 5 |
+           (DWORD)stm->tm_sec >> 1;
+}
+
+
+ + +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/fdisk.html b/Project/GateWay/source/Module/FatFS/documents/doc/fdisk.html new file mode 100644 index 0000000..d72a072 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/fdisk.html @@ -0,0 +1,95 @@ + + + + + + + + +FatFs - f_fdisk + + + + +
+

f_fdisk

+

The f_fdisk fucntion divides a physical drive.

+
+FRESULT f_fdisk (
+  BYTE  pdrv,         /* [IN] Physical drive number */
+  const LBA_t ptbl[], /* [IN] Partition map table */
+  void* work          /* [IN] Work area */
+);
+
+
+ +
+

Parameters

+
+
pdrv
+
Specifies the physical drive to be divided. This is not the logical drive number but the drive identifier passed to the low level disk functions.
+
ptbl
+
List of partition size to create on the drive. The data type LBA_t is an alias of DWORD or QWORD depends on the configuration option FF_LBA64.
+
work
+
Pointer to the function work area. The size must be at least FF_MAX_SS bytes. When a null pointer is given with FF_USE_LFN = 3, a memory block is obtained in this function for the working buffer.
+
+
+ +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_NOT_READY, +FR_WRITE_PROTECTED, +FR_INVALID_PARAMETER, +FR_NOT_ENOUGH_CORE +

+
+ +
+

Description

+

The f_fdisk function creates partitions on the physical drive. The partitioning format can be in generic MBR or GPT. The partition map table specifies how to divide the physical drive. The first item specifies the size of the first partition and the partitions are located on the drive in order of from the first item. When the value of item is less than or equal to 100, it specifies the partition size in percentage of the entire drive space. When it is larger than 100, it specifies number of sectors. The partition map table is terminated by a zero, no space is remaining for next allocation or 4th partition is created in MBR format. If the specified size is larger than remaining space on the drive, the partition is truncated at end of the drive.

+

By default, partitions are created in MBR format. It can create upto four primary partitions on a drive. GPT format is used to create the partitions when 64-bit LBA is enabled (FF_LBA64 = 1) and the drive size is equal to or larger than FF_MIN_GPT sectors. It can create over ten partitions on a drive.

+
+ +
+

QuickInfo

+

Available when FF_FS_READOLNY == 0, FF_USE_MKFS == 1 and FF_MULTI_PARTITION == 1.

+
+ +
+

Example

+
+    /* Volume mapping table defined by user (required when FF_MULTI_PARTITION == 1) */
+
+    PARTITION VolToPart[FF_VOLUMES] = {
+        {0, 1},    /* "0:" ==> 1st partition in PD#0 */
+        {0, 2},    /* "1:" ==> 2nd partition in PD#0 */
+        {1, 0}     /* "2:" ==> PD#1 as removable drive */
+    };
+
+
+    /* Initialize a brand-new disk drive mapped to physical drive 0 */
+
+    BYTE work[FF_MAX_SS];         /* Working buffer */
+    LBA_t plist[] = {50, 50, 0};  /* Divide the drive into two partitions */
+                 /* {0x10000000, 100}; 256M sectors for 1st partition and left all for 2nd partition */
+                 /* {20, 20, 20, 0}; 20% for 3 partitions each and remaing space is left not allocated */
+
+    f_fdisk(0, plist, work);                    /* Divide physical drive 0 */
+
+    f_mkfs("0:", 0, work, sizeof work); /* Create FAT volume on the logical drive 0 */
+    f_mkfs("1:", 0, work, sizeof work); /* Create FAT volume on the logical drive 1 */
+
+
+
+ +
+

See Also

+

Volume management, f_mkfs

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/filename.html b/Project/GateWay/source/Module/FatFS/documents/doc/filename.html new file mode 100644 index 0000000..8104eb0 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/filename.html @@ -0,0 +1,94 @@ + + + + + + + + +FatFs - Path Names + + + +

Path Names on the FatFs API

+ +
+

Format of the Path Names

+

The format of path name on the FatFs module is similer to the filename specs of DOS/Windos as follows:

+
[drive#:][/]directory/file
+

The FatFs module supports long file name (LFN) and 8.3 format file name (SFN). The LFN can be used when FF_USE_LFN >= 1. The sub-directories are separated with a \ or / as the same way as DOS/Windows API. Duplicated separator and terminating separator, such as "//animal///cat/", are ignored. Only a difference is that the heading drive prefix to specify the logical drive, an FAT volume, is in a digit (0-9) + a colon, while it is in an alphabet (A-Z) + a colon in DOS/Windows. The logical drive number is the identifier to specify the volume to be accessed. When drive prefix is omitted, the logical drive number is assumed as default drive.

+

Control characters (\0 to \x1F) are recognized as end of the path name. In LFN configuration, leading or embedded white spaces in the file name are valid as part of the file name, but the treminating white space and dot of the file name are ignored and truncated. In non-LFN configuration, white space is recognized as end of the path name.

+

In default configuration (FF_FS_RPATH == 0), it does not have a concept of current directory like OS oriented filesystem. Every object on the volume is always specified in full path name followed from the root directory. Dot directory names (".", "..") are not allowed. Heading separator is ignored and it can be exist or omitted. The default drive is fixed to drive 0.

+

When relative path feature is enabled (FF_FS_RPATH >= 1), specified path is followed from the root directory if a heading separator is exist. If not, it is followed from the current directory of the default drive. Dot directory name is also allowed for the path name. The current directory is set by f_chdir function and the default drive is the current drive set by f_chdrive function.

+ + + + + + + + + + + + + + +
Path nameFF_FS_RPATH == 0FF_FS_RPATH >= 1
file.txtA file in the root directory of the drive 0A file in the current directory of the current drive
/file.txtA file in the root directory of the drive 0A file in the root directory of the current drive
The root directory of the drive 0The current directory of the current drive
/The root directory of the drive 0The root directory of the current drive
2:The root directory of the drive 2The current directory of the drive 2
2:/The root directory of the drive 2The root directory of the drive 2
2:file.txtA file in the root directory of the drive 2A file in the current directory of the drive 2
../file.txtInvalid nameA file in the parent directory
.Invalid nameThis directory
..Invalid nameParent directory of the current directory (*)
dir1/..Invalid nameThe current directory
/..Invalid nameThe root directory (sticks the top level)
+

Also the drive prefix can be in pre-defined arbitrary string. When the option FF_STR_VOLUME_ID == 1, also arbitrary string volume ID can be used as drive prefix. e.g. "flash:file1.txt", "ram:temp.dat" or "sd:". If the srting does not match any volume ID, the function fails with FR_INVALID_DRIVE.

+

When FF_STR_VOLUME_ID == 2, Unix style drive prefix can be used. e.g. "/flash/file1.txt", "/ram/temp.dat" or "/sd". If a heading separator is exist, it is treated as start of drive prefix and in absolute path. Any form as "root directory in current drive" and "current directory in specified drive" cannot be used. Double dot name cannot traverse the drives such as "/flash/../ram/foo.dat".

+

Remark: In this revision, double dot name ".." cannot follow the parent directory on the exFAT volume. It will work as "." and stay there.

+
+ +
+

Legal Characters and Case Sensitivity

+

In the generic FAT filesystems, the legal characters for object name (file/directory name) are, 0-9 A-Z ! # $ % & ' ( ) - @ ^ _ ` { } ~ in ASCII and extended characters \x80 to \xFF. In the FAT filesystems with LFN extention, also + , ; = [ ], white space and extended characters U+000080 to U+10FFFF are legal for the object name. White spaces and dots can be placed anywhere in the path name except end of the name. Trailing white spaces and dots are ignored.

+

FAT filesystem is case-insensitive to the object names on the volume. Object name on the FAT volume is compared in case-insensitive. For instance, these three names, file.txt, File.Txt and FILE.TXT, are identical on the FAT filesystem. This is applied to extended charactres as well. When an object is created on the FAT volume, up converted name is recorded to the SFN entry, and the raw name is recorded to the LFN entry when LFN extension is exist.

+

As for the MS-DOS and PC DOS for CJK (DOS/DBCS), extended characters ware recorded to the SFN entry without up-case conversion and compared in case-sensitive. This causes a problem on compatibility with Windows system when the object with extended characters is created on the volume by DOS/DBCS system; therfore the object names with DBCS extended characters should not be used on the FAT volume shared by those systems. FatFs works with case-sensitive to the extended characters in only non-LFN with DBCS configuration (DOS/DBCS specs). However, FatFs works with case-insensitive to the extended character (WindowsNT specs) in LFN configuration.

+
+ +
+

Unicode API

+

The path names are input/output in either ANSI/OEM code or Unicode depends on the configuration options. The type of arguments which specifies the path names is defined as TCHAR. It is an alias of char by default and the code set used for the path name string is ANSI/OEM specifid by FF_CODE_PAGE. When FF_LFN_UNICODE is set to 1 or larger, the type of the TCHAR is switched to proper type to support the Unicode string. When Unicode API is specified by this option, the full-featured LFN specification is supported and the Unicode specific characters, such as âœâ˜ªâœ¡â˜¸â˜­ and any character not in BMP, can also be used for the path name. It also affects data types and encoding of the string I/O functions. To define literal strings, _T(s) and _TEXT(s) macro are available to specify the string in proper type. The code shown below is an example to define the literal strings.

+
+ f_open(fp, "filename.txt", FA_READ);      /* ANSI/OEM string (char) */
+ f_open(fp, L"filename.txt", FA_READ);     /* UTF-16 string (WCHAR) */
+ f_open(fp, u8"filename.txt", FA_READ);    /* UTF-8 string (char) */
+ f_open(fp, U"filename.txt", FA_READ);     /* UTF-32 string (DWORD) */
+ f_open(fp, _T("filename.txt"), FA_READ);  /* Changed by configuration (TCHAR) */
+
+
+ +
+

Volume Management

+

By default, each logical drive is associated with the physical drive in same drive number. An FAT volume on the physical drive is serched in the volume mount process. It reads boot sectors and checks it if it is an FAT VBR in order of LBA 0 as SFD format, 1st partition, 2nd partition, 3rd partition, ..., as MBR or GPT format.

+

When multiple partition feature is enabled, FF_MULTI_PARTITION = 1, each individual logical drive is associated with arbitrary partition or physical drive specified by volume management table, VolToPart[]. The table needs to be defined by user to resolve mappings of the logical drive numbers and the associated partitions or drives. Following code is an example of the volume management table.

+
+Example: "0:", "1:" and "2:" are associated with three partitions on the physical drive 0 (a non-removable drive)
+         "3:" is associated with physical drive 1 (a removable drive)
+
+PARTITION VolToPart[FF_VOLUMES] = {
+    {0, 1},     /* "0:" ==> 1st partition on the pd#0 */
+    {0, 2},     /* "1:" ==> 2nd partition on the pd#0 */
+    {0, 3},     /* "2:" ==> 3rd partition on the pd#0 */
+    {1, 0}      /* "3:" ==> pd#1 as removable drive (auto-search) */
+};
+
+
+relationship between logical drive and physical drive
+
+

There are some considerations when enable the multi-partition configuration.

+
    +
  • The physical drive that hosts two or more mounted partitions should be non-removable, or all volumes on the drive must be unmounted when remove the medium.
    • +
  • When make any change to the VolToPart[], corresponding volume should be unmounted prior to make change the item.
    • +
  • On the MBR format drive, up to four primary partitions (1-4) can be specified. The partition number 1 specifies the first item in the partition table and the partition number 2 specifies the second one, and so on. The logical patitions (5-) in the extended partition is not supported.
    • +
  • On the GPT format drive, the partition number 1 specifies the first Microsoft BDP found in the partition table and the partition number 2 specifies the second one found, and so on.
    • +
  • Windows 10 earlier than 1703 does not support multiple volumes on the physical drive with removable class. Only the first parition found on the drive will be mounted. Windows OS does not support SFD format on the physical drive with non-removable class.
    • +
  • Some systems manage the on-board storage in non-standard partition format and each partition is mapped as physical drive in disk_* functions. For such system, FF_MULTI_PARTITION should be always 0.
    • +
  • For further information about the volume management, refer to the description in f_fdisk and f_mkfs.
    • +
+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/findfirst.html b/Project/GateWay/source/Module/FatFS/documents/doc/findfirst.html new file mode 100644 index 0000000..c2df47d --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/findfirst.html @@ -0,0 +1,118 @@ + + + + + + + + +FatFs - f_findfirst + + + + +
+

f_findfirst

+

The f_findfirst function searches a directroy for an item.

+
+FRESULT f_findfirst (
+  DIR* dp,              /* [OUT] Poninter to the directory object */
+  FILINFO* fno,         /* [OUT] Pointer to the file information structure */
+  const TCHAR* path,    /* [IN] Pointer to the directory name to be opened */
+  const TCHAR* pattern  /* [IN] Pointer to the matching pattern string */
+);
+
+
+ +
+

Parameters

+
+
dp
+
Pointer to the blank directory object.
+
fno
+
Pointer to the file information structure to store the information about the found item.
+
path
+
Pointer to the null-terminated string that specifies the directory name to be opened.
+
pattern
+
Pointer to the nul-terminated string that specifies the name matching pattern to be searched for. It is referred by also subsequent f_findnext function, so that the string must be valid while the successive function calls.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_NO_PATH, +FR_INVALID_NAME, +FR_INVALID_OBJECT, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT, +FR_NOT_ENOUGH_CORE, +FR_TOO_MANY_OPEN_FILES +

+
+ + +
+

Description

+

After the directory specified by path could be opened, it starts to search the directory for items with the matching pattern specified by pattern. If the first item is found, the information about the item is stored into the file information structure fno. If not found, fno->fname[] has a null string.

+

The matching pattern string can contain wildcards. For example:

+
    +
  • ? - An any character.
    • +
  • ??? - An any string in length of three characters.
    • +
  • * - An any string in length of zero or longer.
    • +
  • ????* - An any string in length of four characters or longer.
    • +
+

Since the matching algorithm uses recursion, number of wildcards in the matching pattern is limited to four to limit the stack usage. Any pattern with too many wildcards does not match any name. In LFN configuration, only fname[] is tested when FF_USE_FIND == 1 and also altname[] is tested when FF_USE_FIND == 2. There are some differences listed below between FatFs and standard systems in matching condition.

+
    +
  • "*.*" does not match any name without extension while it matches any name with or without extension in standard systems.
    • +
  • Any pattern terminated with a dot does not match any name while it matches the name without extensiton in standard systems.
    • +
  • DBCS extended characters are compared in case-sensitive when LFN is enabled with !FF_LFN_UNICODE.
    • +
+
+ + +
+

QuickInfo

+

This is a wrapper function of f_opendir and f_readdir function. Available when FF_USE_FIND >= 1 and FF_FS_MINIMIZE <= 1.

+
+ + +
+

Examples

+
+/* Search a directory for objects and display it */
+
+void find_image_file (void)
+{
+    FRESULT fr;     /* Return value */
+    DIR dj;         /* Directory object */
+    FILINFO fno;    /* File information */
+
+    fr = f_findfirst(&dj, &fno, "", "????????.JPG"); /* Start to search for photo files */
+
+    while (fr == FR_OK && fno.fname[0]) {         /* Repeat while an item is found */
+        printf("%s\n", fno.fname);                /* Print the object name */
+        fr = f_findnext(&dj, &fno);               /* Search for next item */
+    }
+
+    f_closedir(&dj);
+}
+
+
+ + +
+

See Also

+

f_findnext, f_closedir, DIR, FILINFO

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/findnext.html b/Project/GateWay/source/Module/FatFS/documents/doc/findnext.html new file mode 100644 index 0000000..c39d3e3 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/findnext.html @@ -0,0 +1,69 @@ + + + + + + + + +FatFs - f_findnext + + + + +
+

f_findnext

+

The f_findnext function searches for a next matched object

+
+FRESULT f_findnext (
+  DIR* dp,              /* [IN] Poninter to the directory object */
+  FILINFO* fno          /* [OUT] Pointer to the file information structure */
+);
+
+
+ +
+

Parameters

+
+
dp
+
Pointer to the valid directory object created by f_findfirst function.
+
fno
+
Pointer to the file information structure to store the information about the found directory item.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_INVALID_OBJECT, +FR_TIMEOUT, +FR_NOT_ENOUGH_CORE +

+
+ + +
+

Description

+

It continues the search from a previous call to the f_findfirst or f_findnext function. If found, the information about the object is stored into the file information structure. If no item to be read, a null string will be returned into fno->fname[].

+
+ + +
+

QuickInfo

+

This is a wrapper function of f_readdir function. Available when FF_USE_FIND == 1 and FF_FS_MINIMIZE <= 1.

+
+ + +
+

See Also

+

f_findfirst, f_closedir, DIR, FILINFO

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/forward.html b/Project/GateWay/source/Module/FatFS/documents/doc/forward.html new file mode 100644 index 0000000..05d95fc --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/forward.html @@ -0,0 +1,139 @@ + + + + + + + + +FatFs - f_forward + + + + +
+

f_forward

+

The f_forward function reads the file data and forward it to the data streaming device.

+
+FRESULT f_forward (
+  FIL* fp,                        /* [IN] File object */
+  UINT (*func)(const BYTE*,UINT), /* [IN] Data streaming function */
+  UINT btf,                       /* [IN] Number of bytes to forward */
+  UINT* bf                        /* [OUT] Number of bytes forwarded */
+);
+
+
+ +
+

Parameters

+
+
fp
+
Pointer to the open file object.
+
func
+
Pointer to the user-defined data streaming function. For details, refer to the sample code.
+
btf
+
Number of bytes to forward in range of UINT.
+
bf
+
Pointer to the UINT variable to return number of bytes forwarded.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_INVALID_OBJECT, +FR_DENIED, +FR_TIMEOUT +

+
+ + +
+

Description

+

The f_forward function reads the data from the file and forward it to the outgoing stream. This function is suitable for small memory system, because it does not require any data buffer in the application module. The file pointer of the file object advances in number of bytes forwarded. In case of *bf is less than btf without error, it means the requested size of data could not be transferred due to end of file or stream goes busy during data transfer.

+
+ + +
+

QuickInfo

+

Available when FF_USE_FORWARD == 1.

+
+ + +
+

Example

+
+/*------------------------------------------------------------------------*/
+/* Sample code of data transfer function to be called back from f_forward */
+/*------------------------------------------------------------------------*/
+
+UINT out_stream (   /* Returns number of bytes sent or stream status */
+    const BYTE *p,  /* Pointer to the data block to be sent */
+    UINT btf        /* >0: Transfer call (Number of bytes to be sent). 0: Sense call */
+)
+{
+    UINT cnt = 0;
+
+
+    if (btf == 0) {     /* Sense call */
+        /* Return stream status (0: Busy, 1: Ready) */
+        /* When once it returned ready to sense call, it must accept a byte at least */
+        /* at subsequent transfer call, or f_forward will fail with FR_INT_ERR. */
+        if (FIFO_READY) cnt = 1;
+    }
+    else {              /* Transfer call */
+        do {    /* Repeat while there is any data to be sent and the stream is ready */
+            FIFO_PORT = *p++;
+            cnt++;
+        } while (cnt < btf && FIFO_READY);
+    }
+
+    return cnt;
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Sample code using f_forward function                                   */
+/*------------------------------------------------------------------------*/
+
+FRESULT play_file (
+    char *fn        /* Pointer to the audio file name to be played */
+)
+{
+    FRESULT rc;
+    FIL fil;
+    UINT dmy;
+
+    /* Open the audio file in read only mode */
+    rc = f_open(&fil, fn, FA_READ);
+    if (rc) return rc;
+
+    /* Repeat until the file pointer reaches end of the file */
+    while (rc == FR_OK && !f_eof(&fil)) {
+
+        /* some processes... */
+
+        /* Fill output stream periodicaly or on-demand */
+        rc = f_forward(&fil, out_stream, 1000, &dmy);
+    }
+
+    /* Close the file and return */
+    f_close(&fil);
+    return rc;
+}
+
+
+ + +
+

See Also

+

f_open, fgets, f_write, f_close, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/getcwd.html b/Project/GateWay/source/Module/FatFS/documents/doc/getcwd.html new file mode 100644 index 0000000..ac9a6d6 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/getcwd.html @@ -0,0 +1,83 @@ + + + + + + + + +FatFs - f_getcwd + + + + +
+

f_getcwd

+

The f_getcwd function retrieves the current directory of the current drive.

+
+FRESULT f_getcwd (
+  TCHAR* buff, /* [OUT] Buffer to return path name */
+  UINT len     /* [IN] The length of the buffer */
+);
+
+
+ +
+

Parameters

+
+
buff
+
Pointer to the buffer to receive the current directory string.
+
len
+
Size of the buffer in unit of TCHAR.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT, +FR_NOT_ENOUGH_CORE +

+
+ + +
+

Description

+

The f_getcwd function retrieves full path name of the current directory of the current drive. When FF_VOLUMES >= 2, a heading drive prefix is added to the path name. The style of drive prefix depends on FF_STR_VOLUME_ID.

+

Note: In this revision, this function cannot retrieve the current directory path on the exFAT volume. It always returns the root directory path.

+
+ + +
+

QuickInfo

+

Available when FF_FS_RPATH == 2.

+
+ + +
+

Example

+
+    FRESULT fr;
+    TCHAR str[SZ_STR];
+
+    fr = f_getcwd(str, SZ_STR);  /* Get current directory path */
+
+
+
+ + +
+

See Also

+

f_chdrive, f_chdir

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/getfree.html b/Project/GateWay/source/Module/FatFS/documents/doc/getfree.html new file mode 100644 index 0000000..bf2386c --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/getfree.html @@ -0,0 +1,94 @@ + + + + + + + + +FatFs - f_getfree + + + + +
+

f_getfree

+

The f_getfree function gets number of the free clusters on the volume.

+
+FRESULT f_getfree (
+  const TCHAR* path,  /* [IN] Logical drive number */
+  DWORD* nclst,       /* [OUT] Number of free clusters */
+  FATFS** fatfs       /* [OUT] Corresponding filesystem object */
+);
+
+
+ +
+

Parameters

+
+
path
+
Pointer to the null-terminated string that specifies the logical drive. A null-string means the default drive.
+
nclst
+
Pointer to the DWORD variable to store number of free clusters.
+
fatfs
+
Pointer to pointer that to store a pointer to the corresponding filesystem object.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT +

+
+ + +
+

Descriptions

+

The f_getfree function gets number of free clusters on the volume. The member csize in the filesystem object indicates number of sectors per cluster, so that the free space in unit of sector can be calcurated with this information. In case of FSINFO structure on the FAT32 volume is not in sync, this function can return an incorrect free cluster count. To avoid this problem, FatFs can be forced full FAT scan by FF_FS_NOFSINFO option.

+
+ + +
+

QuickInfo

+

Available when FF_FS_READONLY == 0 and FF_FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    FATFS *fs;
+    DWORD fre_clust, fre_sect, tot_sect;
+
+
+    /* Get volume information and free clusters of drive 1 */
+    res = f_getfree("1:", &fre_clust, &fs);
+    if (res) die(res);
+
+    /* Get total sectors and free sectors */
+    tot_sect = (fs->n_fatent - 2) * fs->csize;
+    fre_sect = fre_clust * fs->csize;
+
+    /* Print the free space (assuming 512 bytes/sector) */
+    printf("%10lu KiB total drive space.\n%10lu KiB available.\n", tot_sect / 2, fre_sect / 2);
+
+
+ + +
+

See Also

+

FATFS

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/getlabel.html b/Project/GateWay/source/Module/FatFS/documents/doc/getlabel.html new file mode 100644 index 0000000..ea2a016 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/getlabel.html @@ -0,0 +1,90 @@ + + + + + + + + +FatFs - f_getlabel + + + + +
+

f_getlabel

+

The f_getlabel function returns volume label and volume serial number of a volume.

+
+FRESULT f_getlabel (
+  const TCHAR* path,  /* [IN] Drive number */
+  TCHAR* label,       /* [OUT] Volume label */
+  DWORD* vsn          /* [OUT] Volume serial number */
+);
+
+
+ +
+

Parameters

+
+
path
+
Pointer to the null-terminated string that specifies the logical drive. Null-string specifies the default drive.
+
label
+
Pointer to the buffer to store the volume label. If the volume has no label, a null-string will be returned. Set null pointer if this information is not needed. The buffer size should be shown below at least to avoid buffer overflow.
+ + + + + + +
ConfigurationFF_FS_EXFAT == 0FF_FS_EXFAT == 1
FF_USE_LFN == 012 items-
FF_LFN_UNICODE == 012 items23 items
FF_LFN_UNICODE == 1,312 items12 items
FF_LFN_UNICODE == 234 items34 items
+
+
vsn
+
Pointer to the DWORD variable to store the volume serial number. Set null pointer if this information is not needed.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT +

+
+ + +
+

QuickInfo

+

Available when FF_USE_LABEL == 1.

+
+ + +
+

Example

+
+    char str[12];
+
+    /* Get volume label of the default drive */
+    f_getlabel("", str, 0);
+
+    /* Get volume label of the drive 2 */
+    f_getlabel("2:", str, 0);
+
+
+ + +
+

See Also

+f_setlabel +
+ + +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/gets.html b/Project/GateWay/source/Module/FatFS/documents/doc/gets.html new file mode 100644 index 0000000..6aee492 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/gets.html @@ -0,0 +1,65 @@ + + + + + + + + +FatFs - f_gets + + + + +
+

f_gets

+

The f_gets reads a string from the file.

+
+TCHAR* f_gets (
+  TCHAR* buff, /* [OUT] Read buffer */
+  int len,     /* [IN] Size of the read buffer */
+  FIL* fp      /* [IN] File object */
+);
+
+
+ +
+

Parameters

+
+
buff
+
Pointer to read buffer to store the read string.
+
len
+
Size of the read buffer in unit of item.
+
fp
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Values

+

When the function succeeded, buff will be returuned.

+
+ + +
+

Description

+

The read operation continues until a '\n' is stored, reached end of the file or the buffer is filled with len - 1 characters. The read string is terminated with a '\0'. When no character to read or any error occured during read operation, it returns a null pointer. The status of EOF and error can be examined with f_eof and f_error function.

+

When FatFs is configured to Unicode API (FF_LFN_UNICODE >= 1), data types on the srting fuctions, f_putc, f_puts, f_printf and f_gets, is also switched to Unicode. The character encoding on the file to be read via this function is assumed as FF_STRF_ENCODE. If the character encoding on the file differs from that on the API, it is converted in this function. In this case, input characters with wrong encoding will be lost.

+
+ + +
+

QuickInfo

+

This is a wrapper function of f_read function. Available when FF_USE_STRFUNC >= 1. When it is set to 2, '\r's contained in the file are stripped out.

+
+ + +
+

See Also

+

f_open, f_read, f_putc, f_puts, f_printf, f_close, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/lseek.html b/Project/GateWay/source/Module/FatFS/documents/doc/lseek.html new file mode 100644 index 0000000..6dd4a45 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/lseek.html @@ -0,0 +1,139 @@ + + + + + + + + +FatFs - f_lseek + + + + +
+

f_lseek

+

The f_lseek function moves the file read/write pointer of an open file object. It can also be used to expand the file size (cluster pre-allocation).

+ +
+FRESULT f_lseek (
+  FIL*    fp,  /* [IN] File object */
+  FSIZE_t ofs  /* [IN] Offset of file read/write pointer to be set */
+);
+
+
+FRESULT f_rewind (
+  FIL*    fp   /* [IN] File object */
+);
+
+
+ +
+

Parameters

+
+
fp
+
Pointer to the open file object.
+
ofs
+
Byte offset from top of the file to set read/write pointer. The data type FSIZE_t is an alias of either DWORD(32-bit) or QWORD(64-bit) depends on the configuration option FF_FS_EXFAT.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_INVALID_OBJECT, +FR_TIMEOUT +

+
+ + +
+

Description

+

File read/write ponter in the open file object points the data byte to be read/written at next read/write operation. It advances as the number of bytes read/written. The f_lseek function moves the file read/write pointer without any read/write operation to the file. The f_rewind function is impremented as a macro.

+
+#define f_rewind(fp) f_lseek((fp), 0)
+
+

If an offset beyond the file size is specified in write mode, the file size is expanded to the specified offset. The file data in the expanded part is undefined, because no data is written to the file in this process. This is suitable to pre-allocate a data area to the file quickly for fast write operation. When a contiguous data area needs to be allocated to the file, use f_expand function instead. After the f_lseek function succeeded, the current read/write pointer should be checked in order to make sure the read/write pointer has been moved correctry. In case of the read/write pointer is not pointing expected offset, either of followings has been occured.

+
    +
  • End of file. The specified ofs was clipped at end of the file in read-only mode.
    • +
  • Disk full. There is no free space on the volume to expand the file.
    • +
+

The fast seek feature enables fast backward/long seek operations without FAT access by using an on-memory CLMT (cluster link map table). It is applied to f_read and f_write function as well, however, the file size cannot be expanded by f_write, f_lseek function while the file is at fast seek mode.

+

The fast seek mode is available when FF_USE_FASTSEEK = 1. The CLMT must be created into the DWORD array prior to use the fast seek mode. To create the CLMT, set address of the DWORD array to the member cltbl in the open file object, set the size of array in unit of items to the cltbl[0] and then call f_lseek function with ofs = CREATE_LINKMAP. After the function succeeded, no FAT access is occured in subsequent f_read, f_write, f_lseek function to the file. The number of items used or required is returned into the cltbl[0]. The number of items needed is (number of the file fragments + 1) * 2. For example, 12 items in the array will be used for the file fragmented in 5 portions. If the function failed with FR_NOT_ENOUGH_CORE, the size of given array is insufficient for the file.

+
+ + +
+

QuickInfo

+

Available when FF_FS_MINIMIZE <= 2. To use fast seek function, FF_USE_FASTSEEK needs to be set 1 to enable this feature.

+
+ + +
+

Example

+
+    /* Open file */
+    fp = malloc(sizeof (FIL));
+    res = f_open(fp, "file.dat", FA_READ|FA_WRITE);
+    if (res) ...
+
+    /* Set read/write pointer to 5000 */
+    res = f_lseek(fp, 5000);
+
+    /* Set read/write pointer to end of the file to append data */
+    res = f_lseek(fp, f_size(fp));
+
+    /* Advance read/write pointer 3000 bytes */
+    res = f_lseek(fp, f_tell(fp) + 3000);
+
+    /* Rewind read/write pointer 2000 bytes (take care on wraparound) */
+    res = f_lseek(fp, f_tell(fp) - 2000);
+
+
+/* Cluster pre-allocation (to prevent buffer overrun on streaming write) */
+
+    res = f_open(fp, recfile, FA_CREATE_NEW | FA_WRITE);   /* Create a file */
+
+    res = f_lseek(fp, PRE_SIZE);             /* Expand file size (cluster pre-allocation) */
+    if (res || f_tell(fp) != PRE_SIZE) ...   /* Check if the file has been expanded successfly */
+
+    res = f_lseek(fp, OFS_DATA);             /* Record data stream with free from cluster allocation delay */
+    ...                                      /* Write operation should be aligned to sector boundary to optimize the write throughput */
+
+    res = f_truncate(fp);                    /* Truncate unused area */
+    res = f_lseek(fp, OFS_HEADER);           /* Set file header */
+    ...
+
+    res = f_close(fp);
+
+
+/* Using fast seek mode */
+
+    DWORD clmt[SZ_TBL];                    /* Cluster link map table buffer */
+
+    res = f_open(fp, fname, FA_READ | FA_WRITE);   /* Open a file */
+
+    res = f_lseek(fp, ofs1);               /* This is normal seek (cltbl is nulled on file open) */
+
+    fp->cltbl = clmt;                      /* Enable fast seek mode (cltbl != NULL) */
+    clmt[0] = SZ_TBL;                      /* Set table size */
+    res = f_lseek(fp, CREATE_LINKMAP);     /* Create CLMT */
+    ...
+
+    res = f_lseek(fp, ofs2);               /* This is fast seek */
+
+
+ + +
+

See Also

+

f_open, f_truncate, f_expand, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/mkdir.html b/Project/GateWay/source/Module/FatFS/documents/doc/mkdir.html new file mode 100644 index 0000000..905266b --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/mkdir.html @@ -0,0 +1,80 @@ + + + + + + + + +FatFs - f_mkdir + + + + +
+

f_mkdir

+

The f_mkdir function creates a new directory.

+
+FRESULT f_mkdir (
+  const TCHAR* path /* [IN] Directory name */
+);
+
+
+ +
+

Parameter

+
+
path
+
Pointer to the null-terminated string that specifies the directory name to create.
+
+
+ + +
+

Return Value

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_NO_PATH, +FR_INVALID_NAME, +FR_DENIED, +FR_EXIST, +FR_WRITE_PROTECTED, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT, +FR_NOT_ENOUGH_CORE +

+
+ + +
+

Description

+

This function creates a new directory. To remove a directory, use f_unlink function.

+
+ + +
+

QuickInfo

+

Available when FF_FS_READONLY == 0 and FF_FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    res = f_mkdir("sub1");
+    if (res) die(res);
+    res = f_mkdir("sub1/sub2");
+    if (res) die(res);
+    res = f_mkdir("sub1/sub2/sub3");
+    if (res) die(res);
+
+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/mkfs.html b/Project/GateWay/source/Module/FatFS/documents/doc/mkfs.html new file mode 100644 index 0000000..5f21154 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/mkfs.html @@ -0,0 +1,127 @@ + + + + + + + + +FatFs - f_mkfs + + + + +
+

f_mkfs

+

The f_mkfs function creates an FAT/exFAT volume on the logical drive.

+
+FRESULT f_mkfs (
+  const TCHAR* path,   /* [IN] Logical drive number */
+  const MKFS_PARM* opt,/* [IN] Format options */
+  void* work,          /* [-]  Working buffer */
+  UINT len             /* [IN] Size of working buffer */
+);
+
+
+ +
+

Parameters

+
+
path
+
Pointer to the null-terminated string specifies the logical drive to be formatted. If it does not have a drive number in it, it means to specify the default drive. The logical drive may or may not have been mounted for the format process.
+
opt
+
Specifies the format option structure MKFS_PARM holding format options. If a null pointer is given, it gives the function every option in default value. The structure has five members in order of described below:
+
+
BYTE fmt
+
Specifies a combination of FAT type flags, FM_FAT, FM_FAT32, FM_EXFAT and bitwise-or of these three, FM_ANY. FM_EXFAT is ignored when exFAT is not enabled. These flags specify which type of FAT volume to be created. If two or more types are specified, one out of them will be selected depends on the volume size and au_size. The flag FM_SFD specifies to create the volume on the drive in SFD format. The default value is FM_ANY.
+
BYTE n_fat
+
Specifies number of FAT copies on the FAT/FAT32 volume. Valid value for this member is 1 or 2. The default value (0) and any invaid value gives 1. If the FAT type is exFAT, this member has no effect.
+
UINT n_align
+
Specifies alignment of the volume data area (file allocation pool, usually erase block boundary of flash memory media) in unit of sector. The valid value for this member is between 1 and 32768 inclusive in power of 2. If a zero (the default value) or any invalid value is given, the function obtains the block size from lower layer with disk_ioctl function.
+
DWORD au_size
+
Specifies size of the allocation unit (cluter) in unit of byte. The valid value is power of 2 between sector size and 128 * sector size inclusive for FAT/FAT32 volume, or up to 16 MB for exFAT volume. If a zero (default value) or any invalid value is given, the function uses default allocation unit size depends on the volume size.
+
UINT n_root
+
Specifies number of root directory entries on the FAT volume. Valid value for this member is up to 32768 and aligned to sector size / 32. The default value (0) and any invaid value gives 512. If the FAT type is FAT32 or exFAT, this member has no effect.
+
+
work
+
Pointer to the working buffer used for the format process. If a null pointer is given with FF_USE_LFN == 3, the function uses a len bytes of heap memory in this function.
+
len
+
Size of the working buffer in unit of byte. It needs to be FF_MAX_SS at least. Plenty of working buffer reduces number of write transactions to the drive, thus the format process will finish quickly.
+
+
+ +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_NOT_READY, +FR_WRITE_PROTECTED, +FR_INVALID_DRIVE, +FR_MKFS_ABORTED, +FR_INVALID_PARAMETER, +FR_NOT_ENOUGH_CORE +

+
+ +
+

Description

+

The FAT sub-type, FAT12/FAT16/FAT32, of FAT volume except exFAT is determined by only number of clusters on the volume and nothing else, according to the FAT specification issued by Microsoft. Thus the FAT sub-type of created volume depends on the volume size and the cluster size. In case of the combination of FAT type and cluter size specified by argument is not valid for the volume size, the function will fail with FR_MKFS_ABORTED.

+

The allocation unit, also known as cluster, is a unit of disk space allocation for files. When the size of allocation unit is 32768 bytes, a file with 100 bytes in size occupies 32768 bytes of disk space. The space efficiency of disk usage gets worse as increasing size of allocation unit, but, on the other hand, the read/write performance increases. Therefore the size of allocation unit is a trade-off between space efficiency and performance. For the large volumes in GB order, 32768 bytes or larger, automatically selected by default, is recommended for most case unless extremely many small files are created in the volume.

+

When the logical drive to be formatted is associated with a physical drive (FF_MULTI_PARTITION == 0 or VolToPart[].pt == 0) and FM_SFD flag is not specified, a partition occupies entire drive space is created and then the FAT volume is created in the partition. When FM_SFD flag is specified, the FAT volume is created without any disk partitioning.

+

When the logical drive to be formatted is associated with a specific partition by multiple partition feature (FF_MULTI_PARTITION == 1 and VolToPart[].pt > 0), the FAT volume is created in the partition of the physical drive specified by volume mapping table and FM_SFD flag is ignored. The hosting physical drive needs to be partitioned with f_fdisk function or any partitioning tool prior to create the FAT volume with this function. If the partition is not exist, the function aborts with FR_MKFS_ABORTED.

+

There are three standard disk partitioning formats, MBR, GPT and SFD. The MBR format, also known as FDISK format, is usually used for harddisk, memory card and U disk. It can divide a physical drive into one or more partitions with a partition table. The GPT, GUID Partition Table, is a newly defined patitioning format for large storage devices. FatFs suppors the GPT only when 64-bit LBA is enabled. The SFD, Super-Floppy Disk, is non-partitioned disk format. The FAT volume is located at LBA 0 and occupies the entire physical drive without any disk partitioning. It is usually used for floppy disk, optical disk and most super-floppy media. Some combination of systems and media support only either partitioned format or non-partitioned format and the other is not supported.

+

Some systems manage the partitions in the on-board storage in non-standard format. The partitions are mapped as physical drives identified by pdrv in disk_* functions. For such systems, SFD format is suitable to create the FAT volume in the partition.

+
+ +
+

QuickInfo

+

Available when FF_FS_READOLNY == 0 and FF_USE_MKFS == 1.

+
+ +
+

Example

+
+/* Format default drive and create a file */
+int main (void)
+{
+    FATFS fs;           /* Filesystem object */
+    FIL fil;            /* File object */
+    FRESULT res;        /* API result code */
+    UINT bw;            /* Bytes written */
+    BYTE work[FF_MAX_SS]; /* Work area (larger is better for processing time) */
+
+
+    /* Format the default drive with default parameters */
+    res = f_mkfs("", 0, work, sizeof work);
+    if (res) ...
+
+    /* Give a work area to the default drive */
+    f_mount(&fs, "", 0);
+
+    /* Create a file as new */
+    res = f_open(&fil, "hello.txt", FA_CREATE_NEW | FA_WRITE);
+    if (res) ...
+
+    /* Write a message */
+    f_write(&fil, "Hello, World!\r\n", 15, &bw);
+    if (bw != 15) ...
+
+    /* Close the file */
+    f_close(&fil);
+
+    /* Unregister work area */
+    f_mount(0, "", 0);
+
+    ...
+
+
+ +
+

See Also

+

Example of volume size and format parameters, Volume management, f_fdisk

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/mount.html b/Project/GateWay/source/Module/FatFS/documents/doc/mount.html new file mode 100644 index 0000000..70caf65 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/mount.html @@ -0,0 +1,122 @@ + + + + + + + + +FatFs - f_mount + + + + +
+

f_mount

+

The f_mount fucntion gives work area to the FatFs module.

+
+FRESULT f_mount (
+  FATFS*       fs,    /* [IN] Filesystem object */
+  const TCHAR* path,  /* [IN] Logical drive number */
+  BYTE         opt    /* [IN] Initialization option */
+);
+
+
+FRESULT f_unmount (
+  const TCHAR* path   /* [IN] Logical drive number */
+);
+
+
+ +
+

Parameters

+
+
fs
+
Pointer to the filesystem object to be registered and cleared. Null pointer unregisters the registered filesystem object.
+
path
+
Pointer to the null-terminated string that specifies the logical drive. The string without drive number means the default drive.
+
opt
+
Mounting option. 0: Do not mount now (to be mounted on the first access to the volume), 1: Force mounted the volume to check if it is ready to work.
+
+
+ +
+

Return Values

+

+FR_OK, +FR_INVALID_DRIVE, +FR_DISK_ERR, +FR_NOT_READY, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM +

+
+ + +
+

Description

+

FatFs requires work area (filesystem object) for each logical drives (FAT volumes). Prior to perform any file/directory operations, a filesystem object needs to be registered with f_mount function for the logical drive. The file/directory API functions get ready to work after this procedure. Some volume management functions, f_mkfs, f_fdisk and f_setcp, do not want a filesystem object.

+

The f_mount function registers/unregisters a filesystem object to the FatFs module as follows:

+
    +
  1. Determines the logical drive which specified by path.
    2. +
  2. Clears and unregisters the regsitered work area of the volume if exist.
    3. +
  3. Clears and registers the new work area to the volume if fs is not NULL.
    4. +
  4. Performs volume mount process to the volume if forced mounting is specified.
    5. +
+

If there is any open object of file or directory on the logical drive, the object will be invalidated by this function.

+

If forced mounting is not specified (opt = 0), this function always succeeds regardless of the physical drive status. It only clears (de-initializes) the given work area and registers its address to the internal table and no activity of the physical drive in this function. The volume mount process will be attempted on subsequent file/directroy function if the filesystem object is not initialized. (delayed mounting) The volume mount processes, initialize the corresponding physical drive, find the FAT volume in it and then initialize the work area, is performed in the subsequent file/directory functions when either of following conditions is true.

+
    +
  • Filesystem object has not been initialized. It is de-initialized by f_mount function.
    • +
  • Physical drive is not initialized. It is de-initialized by system reset or media removal.
    • +
+

If the function with forced mounting (opt = 1) failed with FR_NOT_READY, it means that the filesystem object has been registered successfully but the volume is currently not ready to work. The volume mount process will be attempted on subsequent file/directroy function.

+

If implementation of the disk I/O layer lacks asynchronous media change detection, application program needs to perform f_mount function after each media change to force cleared the filesystem object.

+

To unregister the work area, specify a NULL to the fs, and then the work area can be discarded. f_unmount function is implemented as a macro.

+
+#define f_unmount(path) f_mount(0, path, 0)
+
+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

Example

+
+int main (void)
+{
+    FATFS *fs;     /* Ponter to the filesystem object */
+
+
+    fs = malloc(sizeof (FATFS));           /* Get work area for the volume */
+    f_mount(fs, "", 0);                    /* Mount the default drive */
+
+    f_open(...                             /* Here any file API can be used */
+
+    ...
+
+    f_mount(fs, "", 0);                    /* Re-mount the default drive to reinitialize the filesystem */
+
+    ...
+
+    f_mount(0, "", 0);                     /* Unmount the default drive */
+    free(fs);                              /* Here the work area can be discarded */
+
+    ...
+}
+
+
+ + +
+

See Also

+

f_open, FATFS

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/open.html b/Project/GateWay/source/Module/FatFS/documents/doc/open.html new file mode 100644 index 0000000..38f64e3 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/open.html @@ -0,0 +1,185 @@ + + + + + + + + +FatFs - f_open + + + + +
+

f_open

+

The f_open function opens a file.

+
+FRESULT f_open (
+  FIL* fp,           /* [OUT] Pointer to the file object structure */
+  const TCHAR* path, /* [IN] File name */
+  BYTE mode          /* [IN] Mode flags */
+);
+
+
+ +
+

Parameters

+
+
fp
+
Pointer to the blank file object structure.
+
path
+
Pointer to the null-terminated string that specifies the file name to open or create.
+
mode
+
Mode flags that specifies the type of access and open method for the file. It is specified by a combination of following flags.
+ + + + + + + + + +
FlagsMeaning
FA_READSpecifies read access to the file. Data can be read from the file.
FA_WRITESpecifies write access to the file. Data can be written to the file. Combine with FA_READ for read-write access.
FA_OPEN_EXISTINGOpens a file. The function fails if the file is not existing. (Default)
FA_CREATE_NEWCreates a new file. The function fails with FR_EXIST if the file is existing.
FA_CREATE_ALWAYSCreates a new file. If the file is existing, it will be truncated and overwritten.
FA_OPEN_ALWAYSOpens the file if it is existing. If not, a new file will be created.
FA_OPEN_APPENDSame as FA_OPEN_ALWAYS except the read/write pointer is set end of the file.
+Mode flags in POSIX fopen() function corresponds to FatFs mode flags as follows:
+ + + + + + + + + + +
POSIXFatFs
"r"FA_READ
"r+"FA_READ | FA_WRITE
"w"FA_CREATE_ALWAYS | FA_WRITE
"w+"FA_CREATE_ALWAYS | FA_WRITE | FA_READ
"a"FA_OPEN_APPEND | FA_WRITE
"a+"FA_OPEN_APPEND | FA_WRITE | FA_READ
"wx"FA_CREATE_NEW | FA_WRITE
"w+x"FA_CREATE_NEW | FA_WRITE | FA_READ
+
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_NO_FILE, +FR_NO_PATH, +FR_INVALID_NAME, +FR_DENIED, +FR_EXIST, +FR_INVALID_OBJECT, +FR_WRITE_PROTECTED, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT, +FR_LOCKED, +FR_NOT_ENOUGH_CORE, +FR_TOO_MANY_OPEN_FILES +

+
+ + +
+

Description

+

The f_open function opens a file and creates a file object. The file object is an identifier for subsequent operations to the file. Open file should be closed with f_close function after the session of the file access. If any change to the file has been made and not closed prior to power off, media removal or re-mount, or the file can be collapsed.

+

If duplicated file open is needed, read here carefully. However duplicated open of a file with any write mode flag is always prohibited.

+
+ + +
+

QuickInfo

+

Always available. Only FA_READ and FA_OPEN_EXISTING are available for the mode flags when FF_FS_READONLY == 1.

+
+ + +
+

Example

+
+/* Read a text file and display it */
+
+FATFS FatFs;   /* Work area (filesystem object) for logical drive */
+
+int main (void)
+{
+    FIL fil;        /* File object */
+    char line[100]; /* Line buffer */
+    FRESULT fr;     /* FatFs return code */
+
+
+    /* Give a work area to the default drive */
+    f_mount(&FatFs, "", 0);
+
+    /* Open a text file */
+    fr = f_open(&fil, "message.txt", FA_READ);
+    if (fr) return (int)fr;
+
+    /* Read every line and display it */
+    while (f_gets(line, sizeof line, &fil)) {
+        printf(line);
+    }
+
+    /* Close the file */
+    f_close(&fil);
+
+    return 0;
+}
+
+
+/* Copy a file "file.bin" on the drive 1 to drive 0 */
+
+int main (void)
+{
+    FATFS fs0, fs1;      /* Work area (filesystem object) for logical drives */
+    FIL fsrc, fdst;      /* File objects */
+    BYTE buffer[4096];   /* File copy buffer */
+    FRESULT fr;          /* FatFs function common result code */
+    UINT br, bw;         /* File read/write count */
+
+
+    /* Give work areas to each logical drive */
+    f_mount(&fs0, "0:", 0);
+    f_mount(&fs1, "1:", 0);
+
+    /* Open source file on the drive 1 */
+    fr = f_open(&fsrc, "1:file.bin", FA_READ);
+    if (fr) return (int)fr;
+
+    /* Create destination file on the drive 0 */
+    fr = f_open(&fdst, "0:file.bin", FA_WRITE | FA_CREATE_ALWAYS);
+    if (fr) return (int)fr;
+
+    /* Copy source to destination */
+    for (;;) {
+        fr = f_read(&fsrc, buffer, sizeof buffer, &br); /* Read a chunk of data from the source file */
+        if (br == 0) break; /* error or eof */
+        fr = f_write(&fdst, buffer, br, &bw);           /* Write it to the destination file */
+        if (bw < br) break; /* error or disk full */
+    }
+
+    /* Close open files */
+    f_close(&fsrc);
+    f_close(&fdst);
+
+    /* Unregister work area prior to discard it */
+    f_unmount("0:");
+    f_unmount("1:");
+
+    return (int)fr;
+}
+
+
+ + +
+

See Also

+

f_read, f_write, f_close, FIL, FATFS

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/opendir.html b/Project/GateWay/source/Module/FatFS/documents/doc/opendir.html new file mode 100644 index 0000000..6507249 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/opendir.html @@ -0,0 +1,75 @@ + + + + + + + + +FatFs - f_opendir + + + + +
+

f_opendir

+

The f_opendir function opens a directory.

+
+FRESULT f_opendir (
+  DIR* dp,           /* [OUT] Pointer to the directory object structure */
+  const TCHAR* path  /* [IN] Directory name */
+);
+
+
+ +
+

Parameters

+
+
dp
+
Pointer to the blank directory object to create a new one.
+
path
+
Pointer to the null-terminated string that specifies the directory name to be opened.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_NO_PATH, +FR_INVALID_NAME, +FR_INVALID_OBJECT, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT, +FR_NOT_ENOUGH_CORE, +FR_TOO_MANY_OPEN_FILES +

+
+ + +
+

Description

+

The f_opendir function opens an exsisting directory and creates a directory object for subsequent f_readdir function.

+
+ + +
+

QuickInfo

+

Available when FF_FS_MINIMIZE <= 1.

+
+ + +
+

See Also

+

f_readdir, f_closedir, DIR

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/printf.html b/Project/GateWay/source/Module/FatFS/documents/doc/printf.html new file mode 100644 index 0000000..eb64e8d --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/printf.html @@ -0,0 +1,115 @@ + + + + + + + + +FatFs - f_printf + + + + +
+

f_printf

+

The f_printf function writes formatted string to the file.

+
+int f_printf (
+  FIL* fp,          /* [IN] File object */
+  const TCHAR* fmt, /* [IN] Format stirng */
+  ...
+);
+
+
+ +
+

Parameters

+
+
fp
+
Pointer to the open file object structure.
+
fmt
+
Pointer to the null '\0' terminated format string. The terminator character will not be output.
+
...
+
Optional arguments...
+ +
+
+ + +
+

Return Values

+

When the string was written successfuly, it returns number of character encoding units written to the file. When the function failed due to disk full or an error, a negative value will be returned.

+
+ + +
+

Description

+

The format control directive is a sub-set of standard library shown as follows:

+
+    %[flag][width][precision][size]type
+
+
+
flag
Padding option. A - specifies left-aligned. A 0 specifies zero padded. The default setting is in right-aligned and space padded.
+
width
Minimum width of the field, 1-99 or *. If the width of generated string is less than the minimum width, rest field is padded with spaces or zeros. An * specifies the value comes from an argument in int type. The default setting is zero.
+
precision
Specifies number of fractional digits or maximum width of string, .0-.99 or .*. If the number is omitted, it is same as .0. Default setting is 6 for number and no limit for string.
+
size
Specifies size of integer argument, l(long) and ll(long long). If sizeof (long) == sizeof (int) is true (this is typical of 32-bit systems), prefix l can be omitted for long integer argument. The default size is int for integer argument and floating point argument is always assumed double as the default argument promotion.
+
type
Specifies type of the output format and the argument as shown below. The length of generated string is in assumtion of int is 32-bit. + + + + + + + + + + + +
TypeFormatArgumentLength
cCharacterint,
long,
long long		1 character.
dSigned decimal1 to 11 (20 for ll) characters.
uUnsigned decimal1 to 10 (20 for ll) characters.
oUnsigned octal1 to 11 (22 for ll) characters.
x XUnsigned hexdecimal1 to 8 (16 for ll) characters.
bUnsigned binary1 to 32 characters. Limited to lower 32 digits when ll is specified.
sStringTCHAR*As input string. Null pointer generates a null string.
fFloating point
(decimal)		double1 to 31 characters. If the number of characters exceeds 31, it writes "±OV". Not a number and infinite write "NaN" and "±INF".
e EFloating point
(e notation)		4 to 31 characters. If the number of characters exceeds 31 or exponent exceeds +99, it writes "±OV".
+
+
+

When FatFs is configured for Unicode API (FF_LFN_UNICODE >= 1), character encoding on the string fuctions, f_putc, f_puts, f_printf and f_gets function, is also switched to Unicode. The Unicode characters in multiple encoding unit, such as surrogate pair and multi-byte sequence, should not be divided into two function calls, or the character will be lost. The character encoding on the file to be written via this function is selected by FF_STRF_ENCODE. The characters with wrong encoding or invalid for the output encoding will be lost.

+

If sprintf is used in the project and code conversion is not needed, f_write with sprintf will be efficient in code size and performance rather than f_printf.

+
+ + +
+

QuickInfo

+

This is a wrapper function of f_write function. Available when FF_FS_READONLY == 0 and FF_USE_STRFUNC >= 1. When FF_USE_STRFUNC == 2, '\n's in the generated string are written as '\r'+'\n' each.

+
+ + +
+

Example

+
+    f_printf(fp, "%d", 1234);             /* "1234" */
+    f_printf(fp, "%6d,%3d%%", -200, 5);   /* "  -200,  5%" */
+    f_printf(fp, "%-6u", 100);            /* "100   " */
+    f_printf(fp, "%ld", 12345678);        /* "12345678" */
+    f_printf(fp, "%llu", 0x100000000);    /* "4294967296"   (FF_PRINT_LLI) */
+    f_printf(fp, "%lld", -1LL);           /* "-1"           (FF_PRINT_LLI) */
+    f_printf(fp, "%04x", 0xA3);           /* "00a3" */
+    f_printf(fp, "%08lX", 0x123ABC);      /* "00123ABC" */
+    f_printf(fp, "%016b", 0x550F);        /* "0101010100001111" */
+    f_printf(fp, "%*d", 6, 100);          /* "   100" */
+    f_printf(fp, "%s", "abcdefg");        /* "abcdefg" */
+    f_printf(fp, "%5s", "abc");           /* "  abc" */
+    f_printf(fp, "%-5s", "abc");          /* "abc  " */
+    f_printf(fp, "%.5s", "abcdefg");      /* "abcde" */
+    f_printf(fp, "%-5.2s", "abcdefg");    /* "ab   " */
+    f_printf(fp, "%c", 'a');              /* "a" */
+    f_printf(fp, "%12f", 10.0);           /* "   10.000000" (FF_PRINT_FLOAT) */
+    f_printf(fp, "%.4E", 123.45678);      /* "1.2346E+02"   (FF_PRINT_FLOAT) */
+
+
+ + +
+

See Also

+

f_open, f_putc, f_puts, f_gets, f_close, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/putc.html b/Project/GateWay/source/Module/FatFS/documents/doc/putc.html new file mode 100644 index 0000000..1b2b26f --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/putc.html @@ -0,0 +1,60 @@ + + + + + + + + +FatFs - f_putc + + + + +
+

f_putc

+

The f_putc funciton puts a character to the file.

+
+int f_putc (
+  TCHAR chr,  /* [IN] A character to write */
+  FIL* fp     /* [IN] File object */
+);
+
+
+ +
+

Parameters

+
+
chr
+
A character to write.
+
fp
+
Pointer to the open file object structuer.
+
+
+ + +
+

Return Values

+

When the character was written successfuly, it returns number of character encoding units written to the file. When the function failed due to disk full or any error, a negative value will be returned.

+
+ + +
+

Description

+

When FatFs is configured for Unicode API (FF_LFN_UNICODE >= 1), character encoding on the string fuctions, f_putc, f_puts, f_printf and f_gets function, is also switched to Unicode. The character encoding on the file to be read/written via those functions is selected by FF_STRF_ENCODE. The Unicode characters in multiple encoding unit, such as surrogate pair and multi-byte sequence, cannot be written with this function.

+
+ +
+

QuickInfo

+

This is a wrapper function of f_write function. Available when FF_FS_READONLY == 0 and FF_USE_STRFUNC >= 1. When FF_USE_STRFUNC == 2, a '\n' is output as '\r'+'\n'.

+
+ + +
+

See Also

+

f_open, f_puts, f_printf, f_gets, f_close, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/puts.html b/Project/GateWay/source/Module/FatFS/documents/doc/puts.html new file mode 100644 index 0000000..9d79a4b --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/puts.html @@ -0,0 +1,61 @@ + + + + + + + + +FatFs - f_puts + + + + +
+

f_puts

+

The f_puts function writes a string to the file.

+
+int f_puts (
+  const TCHAR* str, /* [IN] String */
+  FIL* fp           /* [IN] File object */
+);
+
+
+ +
+

Parameters

+
+
str
+
Pointer to the null terminated string to be written. The terminator character will not be written.
+
fp
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Value

+

When the string was written successfuly, it returns number of character encoding units written to the file. When the function failed due to disk full or any error, a negative value will be returned.

+
+ + +
+

Description

+

When FatFs is configured for Unicode API (FF_LFN_UNICODE >= 1), character encoding on the string fuctions, f_putc, f_puts, f_printf and f_gets function, is also switched to Unicode. The input Unicode characters in multiple encoding unit, such as surrogate pair and multi-byte sequence, should not be divided into two function calls, or the character will be lost. The character encoding on the file to be written via this functions is selected by FF_STRF_ENCODE. The characters with wrong encoding or invalid for the output encoding will be lost.

+
+ + +
+

QuickInfo

+

This is a wrapper function of f_write function. Available when FF_FS_READONLY == 0 and FF_USE_STRFUNC >= 1. When FF_USE_STRFUNC == 2, '\n's contained in the input string are output as '\r'+'\n' each.

+
+ + +
+

See Also

+

f_open, f_putc, f_printf, f_gets, f_close, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/rc.html b/Project/GateWay/source/Module/FatFS/documents/doc/rc.html new file mode 100644 index 0000000..694f67e --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/rc.html @@ -0,0 +1,135 @@ + + + + + + + + +FatFs - API Return Code + + + +

Return Code of API Functions

+

Most of API functions return common result code in enum type FRESULT. When an API function succeeded, it returns zero (FR_OK), otherwise it returns non-zero value indicates type of error.

+ +
+ +
FR_OK (0)
+
The function succeeded.
+ +
FR_DISK_ERR
+
The lower layer, disk_read, disk_write or disk_ioctl function, reported that an unrecoverable hard error occured.
Note that if once this error occured at any operation to an open file, the file object is aborted and any operations to the file except for close will be rejected.
+ +
FR_INT_ERR
+
Assertion failed and an insanity is detected in the internal process. One of the following possibilities is suspected. +
    +
  • Work area (file system object, file object or etc...) has been broken by stack overflow or something. This is the reason in most case.
    • +
  • There is an error of the FAT structure on the volume.
    • +
  • There is a bug in the FatFs module itself.
    • +
  • Wrong lower layer implementation.
    • +
+Note that if once this error occured in the operation to an open file, the file object is aborted and any operation to the file except for close will be rejected. +
+ +
FR_NOT_READY
+
The lower layer, disk_initialize function, reported that the storage device could not be got ready to work. One of the following possibilities is suspected. +
    +
  • No medium in the drive.
    • +
  • Wrong lower layer implementation.
    • +
  • Wrong hardware configuration.
    • +
  • The storage device has broken.
    • +
+
+ +
FR_NO_FILE
+
Could not find the file in the directory.
+ +
FR_NO_PATH
+
Could not find the path. A directory in the path name could not be found.
+ +
FR_INVALID_NAME
+
The given string is invalid as a path name. One of the following possibilities is suspected. +
    +
  • There is a character not allowed for the file name.
    • +
  • The file name is out of 8.3 format. (at non-LFN cfg.)
    • +
  • FF_MAX_LFN is insufficient for the file name. (at LFN cfg.)
    • +
  • There is a character encoding error in the string.
    • +
+
+ +
FR_DENIED
+
The required access was denied due to one of the following reasons: +
    +
  • Write mode open against the read-only file. (f_open)
    • +
  • Deleting the read-only file or directory. (f_unlink)
    • +
  • Deleting the non-empty directory or current directory. (f_unlink)
    • +
  • Reading the file opened without FA_READ flag. (f_read)
    • +
  • Any modification to the file opened without FA_WRITE flag. (f_write, f_truncate, f_expand)
    • +
  • Could not create the object due to root directory full or disk full. (f_open, f_mkdir)
    • +
  • Could not find a contiguous area for the file. (f_expand)
    • +
+
+ +
FR_EXIST
+
Name collision. An object with the same name is already existing in the directory.
+ +
FR_INVALID_OBJECT
+
The file/directory object is invalid or a null pointer is given. There are some reasons as follows: +
    +
  • It has been closed, or the structure has been collapsed.
    • +
  • It has been invalidated. Open objects on the volume are invalidated by voulme mount process.
    • +
  • Physical drive is not ready to work due to a media removal.
    • +
+
+ +
FR_WRITE_PROTECTED
+
A write mode operation against the write-protected media.
+ +
FR_INVALID_DRIVE
+
Invalid drive number is specified in the path name or a null pointer is given as the path name. (Related option: FF_VOLUMES)
+ +
FR_NOT_ENABLED
+
Work area for the logical drive has not been registered by f_mount function.
+ +
FR_NO_FILESYSTEM
+
Valid FAT volume could not be found in the drive. One of the following possibilities is suspected. +
    +
  • The FAT volume on the drive is collapsed.
    • +
  • Wrong lower layer implementation.
    • +
  • Wrong VolToPart[] settings. (FF_MULTI_PARTITION = 1)
    • +
+ +
FR_MKFS_ABORTED
+
The f_mkfs function aborted before start in format due to a reason as follows: +
    +
  • It is impossible to create the volume with the given conditions.
    • +
  • The size of the volume is too small. 128 sectors minimum with FM_SFD option.
    • +
  • The partition associated with the logical drive is not exist. (Related option: FF_MULTI_PARTITION)
    • +
+
+ +
FR_TIMEOUT
+
The function was canceled due to a timeout of thread-safe control. (Related option: FF_TIMEOUT)
+ +
FR_LOCKED
+
The operation to the object was rejected by file sharing control. (Related option: FF_FS_LOCK)
+ +
FR_NOT_ENOUGH_CORE
+
Not enough memory for the operation. There is one of the following reasons: +
    +
  • Could not allocate a memory for LFN working buffer. (Related option: FF_USE_LFN)
    • +
  • Size of the given buffer is insufficient for the size required.
    • +
+
+ +
FR_TOO_MANY_OPEN_FILES
+
Number of open objects has been reached maximum value and no more object can be opened. (Related option: FF_FS_LOCK)
+ +
FR_INVALID_PARAMETER
+
The given parameter is invalid or there is an inconsistent for the volume.
+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/read.html b/Project/GateWay/source/Module/FatFS/documents/doc/read.html new file mode 100644 index 0000000..9157146 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/read.html @@ -0,0 +1,80 @@ + + + + + + + + +FatFs - f_read + + + + +
+

f_read

+

The f_read function reads data from a file.

+
+FRESULT f_read (
+  FIL* fp,     /* [IN] File object */
+  void* buff,  /* [OUT] Buffer to store read data */
+  UINT btr,    /* [IN] Number of bytes to read */
+  UINT* br     /* [OUT] Number of bytes read */
+);
+
+
+ +
+

Parameters

+
+
fp
+
Pointer to the open file object.
+
buff
+
Pointer to the buffer to store the read data.
+
btr
+
Number of bytes to read in range of UINT type. If the file needs to be read fast, it should be read in large chunk as possible.
+
br
+
Pointer to the UINT variable that receives number of bytes read. This value is always valid after the function call regardless of the function return code. If the return value is equal to btr, the function return code should be FR_OK.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_DENIED, +FR_INVALID_OBJECT, +FR_TIMEOUT +

+
+ + +
+

Description

+

The function starts to read data from the file at the file offset pointed by read/write pointer. The read/write pointer advances as number of bytes read. After the function succeeded, *br should be checked to detect end of the file. In case of *br < btr, it means the read/write pointer hit end of the file during read operation.

+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

Example

+

Refer to the example in f_open.

+
+ + +
+

See Also

+

f_open, fgets, f_write, f_close, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/readdir.html b/Project/GateWay/source/Module/FatFS/documents/doc/readdir.html new file mode 100644 index 0000000..2c4956a --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/readdir.html @@ -0,0 +1,139 @@ + + + + + + + + +FatFs - f_readdir + + + + +
+

f_readdir

+

The f_readdir function reads an item of the directory.

+
+FRESULT f_readdir (
+  DIR* dp,      /* [IN] Directory object */
+  FILINFO* fno  /* [OUT] File information structure */
+);
+
+
+FRESULT f_rewinddir (
+  DIR* dp       /* [IN] Directory object */
+);
+
+
+ +
+

Parameters

+
+
dp
+
Pointer to the open directory object.
+
fno
+
Pointer to the file information structure to store the information about read item. A null pointer rewinds the read index of the directory.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_INVALID_OBJECT, +FR_TIMEOUT, +FR_NOT_ENOUGH_CORE +

+
+ + +
+

Description

+

The f_readdir function reads a directory item, informations about the object, from the open directory. Items in the directory can be read in sequence by f_readdir function calls. When all items in the directory have been read and no item to read, a null string is stored into the fno->fname[] without any error. When a null pointer is given to the fno, the read index of the directory object is rewinded. The f_rewinddir function is implemented as a macro.

+
+#define f_rewinddir(dp) f_readdir((dp), 0)
+
+

When LFN is enabled, a member altname[] is defined in the file information structure to store the short file name of the object. If the long file name is not accessible due to a reason listed below, short file name is stored to the fname[] and the altname[] has a null string.

+
    +
  • The item has no LFN. (Not the case in exFAT volume)
    • +
  • FF_MAX_LFN is insufficient to handle the LFN. (Not the case in FF_MAX_LFN == 255)
    • +
  • FF_LFN_BUF is insufficient to store the LFN.
    • +
  • The LFN contains some character not defined in current CP. (Not the case in FF_LFN_UNICODE != 0)
    • +
+

There is an issue on read directories in exFAT volume. The exFAT does not support short file name. This means no name can be returned on the condition above. If it is the case, "?" is returned as the file name to indicate that the object is not accessible. To avoid this problem, configure FatFs FF_LFN_UNICODE != 0 and FF_MAX_LFN == 255 to support the full feature of LFN specification.

+

Dot entries ("." and "..") in the sub-directory of FAT volume are filtered out and they will never appear in the read items because exFAT lacks dot entries in the sub-directory.

+
+ + +
+

QuickInfo

+

Available when FF_FS_MINIMIZE <= 1.

+
+ + +
+

Sample Code

+
+FRESULT scan_files (
+    char* path        /* Start node to be scanned (***also used as work area***) */
+)
+{
+    FRESULT res;
+    DIR dir;
+    UINT i;
+    static FILINFO fno;
+
+
+    res = f_opendir(&dir, path);                       /* Open the directory */
+    if (res == FR_OK) {
+        for (;;) {
+            res = f_readdir(&dir, &fno);                   /* Read a directory item */
+            if (res != FR_OK || fno.fname[0] == 0) break;  /* Break on error or end of dir */
+            if (fno.fattrib & AM_DIR) {                    /* It is a directory */
+                i = strlen(path);
+                sprintf(&path[i], "/%s", fno.fname);
+                res = scan_files(path);                    /* Enter the directory */
+                if (res != FR_OK) break;
+                path[i] = 0;
+            } else {                                       /* It is a file. */
+                printf("%s/%s\n", path, fno.fname);
+            }
+        }
+        f_closedir(&dir);
+    }
+
+    return res;
+}
+
+
+int main (void)
+{
+    FATFS fs;
+    FRESULT res;
+    char buff[256];
+
+
+    res = f_mount(&fs, "", 1);
+    if (res == FR_OK) {
+        strcpy(buff, "/");
+        res = scan_files(buff);
+    }
+
+    return res;
+}
+
+
+ + +
+

See Also

+

f_opendir, f_closedir, f_stat, FILINFO, DIR

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/rename.html b/Project/GateWay/source/Module/FatFS/documents/doc/rename.html new file mode 100644 index 0000000..eb31ed2 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/rename.html @@ -0,0 +1,87 @@ + + + + + + + + +FatFs - f_rename + + + + +
+

f_rename

+

The f_rename function renames and/or moves a file or sub-directory.

+
+FRESULT f_rename (
+  const TCHAR* old_name, /* [IN] Old object name */
+  const TCHAR* new_name  /* [IN] New object name */
+);
+
+
+ +
+

Parameters

+
+
old_name
+
Pointer to a null-terminated string that specifies the existing file or sub-directory to be renamed.
+
new_name
+
Pointer to a null-terminated string that specifies the new object name. A drive number may be specified in this string but it is ignored and assumed as the same drive of the old_name. Any object with this path name except old_name must not be exist, or the function fails with FR_EXIST.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_NO_FILE, +FR_NO_PATH, +FR_INVALID_NAME, +FR_EXIST, +FR_WRITE_PROTECTED, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT, +FR_LOCKED, +FR_NOT_ENOUGH_CORE +

+
+ + +
+

Description

+

Renames a file or sub-directory and can also move it to other directory in the same volume. The object to be renamed must not be an open object, or the FAT volume can be collapsed. Such the wrong operation is rejected safely when file lock function is enabled.

+
+ + +
+

QuickInfo

+

Available when FF_FS_READONLY == 0 and FF_FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    /* Rename an object in the default drive */
+    f_rename("oldname.txt", "newname.txt");
+
+    /* Rename an object in the drive 2 */
+    f_rename("2:oldname.txt", "newname.txt");
+
+    /* Rename an object and move it to another directory in the drive */
+    f_rename("log.txt", "old/log0001.txt");
+
+
+ + +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/sdir.html b/Project/GateWay/source/Module/FatFS/documents/doc/sdir.html new file mode 100644 index 0000000..19c66ec --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/sdir.html @@ -0,0 +1,38 @@ + + + + + + + + +FatFs - DIR + + + + +
+

DIR

+

The DIR structure is used for the work area to read a directory by f_oepndir, f_readdir, f_findfirst and f_findnext function. Application program must not modify any member in this structure, or f_readdir function will not work properly.

+
+typedef struct {
+    FFOBJID obj;        /* Object identifier */
+    DWORD   dptr;       /* Current read/write offset */
+    DWORD   clust;      /* Current cluster */
+    LBA_t   sect;       /* Current sector */
+    BYTE*   dir;        /* Pointer to the current SFN entry in the win[] */
+    BYTE*   fn;         /* Pointer to the SFN buffer (in/out) {file[8],ext[3],status[1]} */
+#if FF_USE_LFN
+    DWORD   blk_ofs;    /* Offset of the entry block (0xFFFFFFFF:Invalid) */
+    WCHAR*  lfn;        /* Pointer to the LFN working buffer (in/out) */
+#endif
+#if FF_USE_FIND
+    const TCHAR*  pat;  /* Ponter to the matching pattern */
+#endif
+} DIR;
+
+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/setcp.html b/Project/GateWay/source/Module/FatFS/documents/doc/setcp.html new file mode 100644 index 0000000..480393f --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/setcp.html @@ -0,0 +1,82 @@ + + + + + + + + +FatFs - f_setcp + + + + +
+

f_setcp

+

The f_setcp function sets the active code page.

+
+FRESULT f_setcp (
+  WORD cp     /* [IN] Code page to be set */
+);
+
+
+ +
+

Parameters

+
+
cp
+
OEM code page to be used for the path name. Valid values are as follows.
+ + + + + + + + + + + + + + + + + + + + + + + + +
ValueMeaning
0Initial value (any extended character cannot be used)
437U.S.
720Arabic
737Greek
771KBL
775Baltic
850Latin 1
852Latin 2
855Cyrillic
857Turkish
860Portuguese
861Icelandic
862Hebrew
863Canadian French
864Arabic
865Nordic
866Russian
869Greek 2
932Japanese (DBCS)
936Simplified Chinese (DBCS)
949Korean (DBCS)
950Traditional Chinese (DBCS)
+
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_INVALID_PARAMETER +

+
+ + +
+

Description

+

The f_setcp function sets the active code page for the path name. Also code conversion of string functions will be affected by the setting of code page when FF_LFN_UNICODE >= 1 and FF_STRF_ENCODE == 0. Because the initial setting of the code page is 0 and API function with extended character will not work properly, a valid code page needs to be set on the system start-up and it should not be changed on the fly.

+
+ + +
+

QuickInfo

+

Available when FF_CODE_PAGE == 0.

+
+ + +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/setlabel.html b/Project/GateWay/source/Module/FatFS/documents/doc/setlabel.html new file mode 100644 index 0000000..61592e3 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/setlabel.html @@ -0,0 +1,92 @@ + + + + + + + + +FatFs - f_setlabel + + + + +
+

f_setlabel

+

The f_setlabel function sets/removes the label of a volume.

+
+FRESULT f_setlabel (
+  const TCHAR* label  /* [IN] Volume label to be set */
+);
+
+
+ +
+

Parameters

+
+
label
+
Pointer to the null-terminated string that specifies the volume label to be set.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_INVALID_NAME, +FR_WRITE_PROTECTED, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT +

+
+ + +
+

Description

+

When the string has a drive prefix, the volume label will be set to the volume specified by the drive prefix. Unix style volume ID cannot be used to specify the volume. If drive number is not specified, the volume label will be set to the default drive. If length of the given volume label is zero, the volume label on the volume will be removed. The format of the volume label is as shown below:

+
    +
  • Up to 11 bytes long as conversion of OEM code page at FAT volume.
    • +
  • Up to 11 characters long at exFAT volume.
    • +
  • Allowable characters for FAT volume are: characters allowed for SFN excludes dot. Low-case characters are up converted.
    • +
  • Allowable characters for exFAT volume are: characters allowed for LFN includes dot. Low-case characters are preserved.
    • +
  • Spaces can be embedded anywhere in the volume label. Trailing spaces are truncated off at FAT volume.
    • +
+

Remark: The standard system (Windows) has a problem at the volume label with a heading \xE5 on the FAT volume. To avoid this problem, this function rejects such volume label as invalid name.

+
+ +
+

QuickInfo

+

Available when FF_FS_READONLY == 0 and FF_USE_LABEL == 1.

+
+ + +
+

Example

+
+    /* Set volume label to the default drive */
+    f_setlabel("DATA DISK");
+
+    /* Set volume label to the drive 2 */
+    f_setlabel("2:DISK 3 OF 4");
+
+    /* Remove volume label of the drive 2 */
+    f_setlabel("2:");
+
+
+ + +
+

See Also

+f_getlabel +
+ + +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/sfatfs.html b/Project/GateWay/source/Module/FatFS/documents/doc/sfatfs.html new file mode 100644 index 0000000..79079e1 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/sfatfs.html @@ -0,0 +1,62 @@ + + + + + + + + +FatFs - FATFS + + + + +
+

FATFS

+

The FATFS structure (filesystem object) holds dynamic work area of individual logical drives. It is given by application program and registerd/unregisterd to the FatFs module with f_mount function. Initialization of the structure is done by volume mount process whenever necessary. Application program must not modify any member in this structure, or the FAT volume will be collapsed.

+
+typedef struct {
+    BYTE    fs_type;      /* FAT type (0, FS_FAT12, FS_FAT16, FS_FAT32 or FS_EXFAT) */
+    BYTE    pdrv;         /* Hosting physical drive of this volume */
+    BYTE    n_fats;       /* Number of FAT copies (1,2) */
+    BYTE    wflag;        /* win[] flag (b0:win[] is dirty) */
+    BYTE    fsi_flag;     /* FSINFO flags (b7:Disabled, b0:Dirty) */
+    WORD    id;           /* Volume mount ID */
+    WORD    n_rootdir;    /* Number of root directory entries (FAT12/16) */
+    WORD    csize;        /* Sectors per cluster */
+#if FF_MAX_SS != FF_MIN_SS
+    WORD    ssize;        /* Sector size (512,1024,2048 or 4096) */
+#endif
+#if FF_FS_EXFAT
+    BYTE*   dirbuf;       /* Directory entry block scratchpad buffer */
+#endif
+#if FF_FS_REENTRANT
+    FF_SYNC_t sobj;       /* Identifier of sync object */
+#endif
+#if !FF_FS_READONLY
+    DWORD   last_clust;   /* FSINFO: Last allocated cluster (0xFFFFFFFF if invalid) */
+    DWORD   free_clust;   /* FSINFO: Number of free clusters (0xFFFFFFFF if invalid) */
+#endif
+#if FF_FS_RPATH
+    DWORD   cdir;         /* Cluster number of current directory (0:root) */
+#if FF_FS_EXFAT
+    DWORD   cdc_scl;      /* Containing directory start cluster (invalid when cdir is 0) */
+    DWORD   cdc_size;     /* b31-b8:Size of containing directory, b7-b0: Chain status */
+    DWORD   cdc_ofs;      /* Offset in the containing directory (invalid when cdir is 0) */
+#endif
+#endif
+    DWORD   n_fatent;     /* Number of FAT entries (Number of clusters + 2) */
+    DWORD   fsize;        /* Sectors per FAT */
+    LBA_t   volbase;      /* Volume base LBA */
+    LBA_t   fatbase;      /* FAT base LBA */
+    LBA_t   dirbase;      /* Root directory base (LBA|Cluster) */
+    LBA_t   database;     /* Data base LBA */
+    LBA_t   winsect;      /* Sector LBA appearing in the win[] */
+    BYTE    win[FF_MAX_SS]; /* Disk access window for directory, FAT (and file data at tiny cfg) */
+} FATFS;
+
+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/sfile.html b/Project/GateWay/source/Module/FatFS/documents/doc/sfile.html new file mode 100644 index 0000000..4d44314 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/sfile.html @@ -0,0 +1,43 @@ + + + + + + + + +FatFs - FIL + + + + +
+

FIL

+

The FIL structure (file object) holds the state of an open file. It is created by f_open function and discarded by f_close function. Application program must not modify any member in this structure except for cltbl, or the FAT volume will be collapsed. Note that a sector buffer is defined in this structure at non-tiny configuration (FF_FS_TINY == 0), so that the FIL structures at that configuration should not be defined as auto variable.

+ +
+typedef struct {
+    FFOBJID obj;          /* Object identifier */
+    BYTE    flag;         /* File object status flags */
+    BYTE    err;          /* Abort flag (error code) */
+    FSIZE_t fptr;         /* File read/write pointer (Byte offset origin from top of the file) */
+    DWORD   clust;        /* Current cluster of fptr (One cluster behind if fptr is on the cluster boundary. Invalid if fptr == 0.) */
+    LBA_t   sect;         /* Current data sector (Can be invalid if fptr is on the cluster boundary.)*/
+#if !FF_FS_READONLY
+    LBA_t   dir_sect;     /* Sector number containing the directory entry */
+    BYTE*   dir_ptr;      /* Ponter to the directory entry in the window */
+#endif
+#if FF_USE_FASTSEEK
+    DWORD*  cltbl;        /* Pointer to the cluster link map table (Nulled on file open. Set by application.) */
+#endif
+#if !FF_FS_TINY
+    BYTE    buf[FF_MAX_SS]; /* File private data transfer buffer (Always valid if fptr is not on the sector boundary but can be invalid if fptr is on the sector boundary.) */
+#endif
+} FIL;
+
+ +
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/sfileinfo.html b/Project/GateWay/source/Module/FatFS/documents/doc/sfileinfo.html new file mode 100644 index 0000000..56fad39 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/sfileinfo.html @@ -0,0 +1,78 @@ + + + + + + + + +FatFs - FILINFO + + + + +
+

FILINFO

+

The FILINFO structure holds information about the object retrieved by f_readdir, f_findfirst, f_findnext and f_stat function. Be careful in the size of structure when LFN is enabled.

+
+typedef struct {
+    FSIZE_t fsize;               /* File size */
+    WORD    fdate;               /* Last modified date */
+    WORD    ftime;               /* Last modified time */
+    BYTE    fattrib;             /* Attribute */
+#if FF_USE_LFN
+    TCHAR   altname[FF_SFN_BUF + 1]; /* Alternative object name */
+    TCHAR   fname[FF_LFN_BUF + 1];   /* Primary object name */
+#else
+    TCHAR   fname[12 + 1];       /* Object name */
+#endif
+} FILINFO;
+
+
+ +

Members

+
+
fsize
+
Size of the file in unit of byte. FSIZE_t is an alias of integer type either DWORD(32-bit) or QWORD(64-bit) depends on the configuration option FF_FS_EXFAT. Do not care if the item is a sub-directory.
+
fdate
+
The date when the file was modified or the directory was created.
+
+
bit15:9
+
Year origin from 1980 (0..127)
+
bit8:5
+
Month (1..12)
+
bit4:0
+
Day (1..31)
+
+
+
ftime
+
The time when the file was modified or the directory was created.
+
+
bit15:11
+
Hour (0..23)
+
bit10:5
+
Minute (0..59)
+
bit4:0
+
Second / 2 (0..29)
+
+
+
fattrib
+
The attribute flags in combination of:
+ + + + + + + +
FlagMeaning
AM_RDORead-only. Write mode open and deleting is rejected.
AM_HIDHidden. Should not be shown in normal directory listing.
AM_SYSSystem. Used by system and should not be accessed.
AM_ARCArchive. Set on new creation or any modification to the file.
AM_DIRDirectory. This is not a file but a sub-directory container.
+
+
fname[]
+
Null-terminated object name. A null string is stored when no item to read and it indicates this structure is invalid. The size of fname[] and altname[] each can be configured in LFN configuration.
+
altname[]
+
Alternative object name is stored if available. This member is not available in non-LFN configuration.
+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/size.html b/Project/GateWay/source/Module/FatFS/documents/doc/size.html new file mode 100644 index 0000000..535df93 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/size.html @@ -0,0 +1,62 @@ + + + + + + + + +FatFs - f_size + + + + +
+

f_size

+

The f_size function gets the size of a file.

+
+FSIZE_t f_size (
+  FIL* fp   /* [IN] File object */
+);
+
+
+ + +
+

Parameters

+
+
fp
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Values

+

Returns the size of the file in unit of byte.

+
+ + +
+

Description

+

In this revision, the f_size function is implemented as a macro. It does not have any validation and mutual exclusion.

+
+#define f_size(fp) ((fp)->obj.objsize)
+
+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, f_lseek, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/stat.html b/Project/GateWay/source/Module/FatFS/documents/doc/stat.html new file mode 100644 index 0000000..2a27df6 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/stat.html @@ -0,0 +1,112 @@ + + + + + + + + +FatFs - f_stat + + + + +
+

f_stat

+

The f_stat function checks the existence of a file or sub-directory.

+
+FRESULT f_stat (
+  const TCHAR* path,  /* [IN] Object name */
+  FILINFO* fno        /* [OUT] FILINFO structure */
+);
+
+
+ +
+

Parameters

+
+
path
+
Pointer to the null-terminated string that specifies the object to get its information. The object must not be the root direcotry.
+
fno
+
Pointer to the blank FILINFO structure to store the information of the object. Set null pointer if this information is not needed.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_NO_FILE, +FR_NO_PATH, +FR_INVALID_NAME, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT, +FR_NOT_ENOUGH_CORE +

+
+ + +
+

Description

+

The f_stat function checks the existence of a file or sub-directory in the directory. If it is not exist, the function returns with FR_NO_FILE. If it is exist, the function returns with FR_OK and the informations about the object, size, timestamp and attribute, is stored to the file information structure. For details of the file information, refer to the FILINFO structure and f_readdir function.

+

Note that the file information comes from the meta data in the directory. If the file has been opend and modified, the file will need to be synched or closed in order to obtain the latest file information.

+
+ + +
+

QuickInfo

+

Available when FF_FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    FRESULT fr;
+    FILINFO fno;
+    const char *fname = "file.txt";
+
+
+    printf("Test for \"%s\"...\n", fname);
+
+    fr = f_stat(fname, &fno);
+    switch (fr) {
+
+    case FR_OK:
+        printf("Size: %lu\n", fno.fsize);
+        printf("Timestamp: %u-%02u-%02u, %02u:%02u\n",
+               (fno.fdate >> 9) + 1980, fno.fdate >> 5 & 15, fno.fdate & 31,
+               fno.ftime >> 11, fno.ftime >> 5 & 63);
+        printf("Attributes: %c%c%c%c%c\n",
+               (fno.fattrib & AM_DIR) ? 'D' : '-',
+               (fno.fattrib & AM_RDO) ? 'R' : '-',
+               (fno.fattrib & AM_HID) ? 'H' : '-',
+               (fno.fattrib & AM_SYS) ? 'S' : '-',
+               (fno.fattrib & AM_ARC) ? 'A' : '-');
+        break;
+
+    case FR_NO_FILE:
+        printf("\"%s\" is not exist.\n", fname);
+        break;
+
+    default:
+        printf("An error occured. (%d)\n", fr);
+    }
+
+
+ + +
+

References

+

f_opendir, f_readdir, FILINFO

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/tell.html b/Project/GateWay/source/Module/FatFS/documents/doc/tell.html new file mode 100644 index 0000000..56acb47 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/tell.html @@ -0,0 +1,62 @@ + + + + + + + + +FatFs - f_tell + + + + +
+

f_tell

+

The f_tell function gets the current read/write pointer of a file.

+
+FSIZE_t f_tell (
+  FIL* fp   /* [IN] File object */
+);
+
+
+ + +
+

Parameters

+
+
fp
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Values

+

Returns current read/write pointer of the file.

+
+ + +
+

Description

+

In this revision, the f_tell function is implemented as a macro. It does not have any validation and mutual exclusion.

+
+#define f_tell(fp) ((fp)->fptr)
+
+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, f_lseek, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/truncate.html b/Project/GateWay/source/Module/FatFS/documents/doc/truncate.html new file mode 100644 index 0000000..498949a --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/truncate.html @@ -0,0 +1,66 @@ + + + + + + + + +FatFs - f_truncate + + + + +
+

f_truncate

+

The f_truncate function truncates the file size.

+
+FRESULT f_truncate (
+  FIL* fp     /* [IN] File object */
+);
+
+
+ +
+

Parameter

+
+
fp
+
Pointer to the open file object to be truncated.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_DENIED, +FR_INVALID_OBJECT, +FR_TIMEOUT +

+
+ + +
+

Description

+

The f_truncate function truncates the file size to the current file read/write pointer. This function has no effect if the file read/write pointer is already pointing end of the file.

+
+ + +
+

QuickInfo

+

Available when FF_FS_READONLY == 0 and FF_FS_MINIMIZE == 0.

+
+ + +
+

See Also

+

f_open, f_lseek, FIL

+
+ + +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/unlink.html b/Project/GateWay/source/Module/FatFS/documents/doc/unlink.html new file mode 100644 index 0000000..08e478e --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/unlink.html @@ -0,0 +1,74 @@ + + + + + + + + +FatFs - f_unlink + + + + +
+

f_unlink

+

The f_unlink function removes a file or sub-directory from the volume.

+
+FRESULT f_unlink (
+  const TCHAR* path  /* [IN] Object name */
+);
+
+
+ +
+

Parameter

+
+
path
+
Pointer to a null-terminated string that specifies the file or sub-directory to be removed.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_NO_FILE, +FR_NO_PATH, +FR_INVALID_NAME, +FR_DENIED, +FR_WRITE_PROTECTED, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT, +FR_LOCKED, +FR_NOT_ENOUGH_CORE +

+
+ + +
+

Description

+

+If condition of the object to be removed is applicable to the following terms, the function will be rejected.

    +
  • The file/sub-directory must not have read-only attribute (AM_RDO), or the function will be rejected with FR_DENIED.
    • +
  • The sub-directory must be empty and must not be current directory, or the function will be rejected with FR_DENIED.
    • +
  • The file/sub-directory must not be opened, or the FAT volume can be collapsed. It will be rejected safely when file lock function is enabled.
    • +
+
+ + +
+

QuickInfo

+

Available when FF_FS_READONLY == 0 and FF_FS_MINIMIZE == 0.

+
+ + +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/utime.html b/Project/GateWay/source/Module/FatFS/documents/doc/utime.html new file mode 100644 index 0000000..d33ed4d --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/utime.html @@ -0,0 +1,99 @@ + + + + + + + + +FatFs - f_utime + + + + +
+

f_utime

+

The f_utime function changes the timestamp of a file or sub-directory.

+
+FRESULT f_utime (
+  const TCHAR* path,  /* [IN] Object name */
+  const FILINFO* fno  /* [IN] Time and data to be set */
+);
+
+
+ +
+

Parameters

+
+
path
+
Pointer to the null-terminated string that specifies an object to be changed.
+
fno
+
Pointer to the file information structure that has a timestamp to be set in member fdate and ftime. Do not care any other members.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_NOT_READY, +FR_NO_FILE, +FR_NO_PATH, +FR_INVALID_NAME, +FR_WRITE_PROTECTED, +FR_INVALID_DRIVE, +FR_NOT_ENABLED, +FR_NO_FILESYSTEM, +FR_TIMEOUT, +FR_NOT_ENOUGH_CORE +

+
+ + +
+

Description

+

The f_utime function changes the timestamp of a file or sub-directory

+
+ + +
+

Example

+
+FRESULT set_timestamp (
+    char *obj,     /* Pointer to the file name */
+    int year,
+    int month,
+    int mday,
+    int hour,
+    int min,
+    int sec
+)
+{
+    FILINFO fno;
+
+    fno.fdate = (WORD)(((year - 1980) * 512U) | month * 32U | mday);
+    fno.ftime = (WORD)(hour * 2048U | min * 32U | sec / 2U);
+
+    return f_utime(obj, &fno);
+}
+
+
+ + +
+

QuickInfo

+

Available when FF_FS_READONLY == 0 and FF_USE_CHMOD == 1.

+
+ + +
+

See Also

+

f_stat, FILINFO

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/doc/write.html b/Project/GateWay/source/Module/FatFS/documents/doc/write.html new file mode 100644 index 0000000..4727e62 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/doc/write.html @@ -0,0 +1,80 @@ + + + + + + + + +FatFs - f_write + + + + +
+

f_write

+

The f_write writes data to a file.

+
+FRESULT f_write (
+  FIL* fp,          /* [IN] Pointer to the file object structure */
+  const void* buff, /* [IN] Pointer to the data to be written */
+  UINT btw,         /* [IN] Number of bytes to write */
+  UINT* bw          /* [OUT] Pointer to the variable to return number of bytes written */
+);
+
+
+ +
+

Parameters

+
+
fp
+
Pointer to the open file object structure.
+
buff
+
Pointer to the data to be written.
+
btw
+
Specifies number of bytes to write in range of UINT type. If the data needs to be written fast, it should be written in large chunk as possible.
+
bw
+
Pointer to the UINT variable that receives the number of bytes written. This value is always valid after the function call regardless of the function return code. If the return value is equal to btw, the function return code should be FR_OK.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_DISK_ERR, +FR_INT_ERR, +FR_DENIED, +FR_INVALID_OBJECT, +FR_TIMEOUT +

+
+ + +
+

Description

+

The function starts to write data to the file at the file offset pointed by read/write pointer. The read/write pointer advances as number of bytes written. After the function succeeded, *bw should be checked to detect the disk full. In case of *bw < btw, it means the volume got full during the write operation. The function can take a time when the volume is full or close to full.

+
+ + +
+

QuickInfo

+

Available when FF_FS_READONLY == 0.

+
+ + +
+

Example

+

Refer to the example in f_open.

+
+ + +
+

See Also

+

f_open, f_read, fputc, fputs, fprintf, f_close, FIL

+
+ +

Return

+ + diff --git a/Project/GateWay/source/Module/FatFS/documents/res/app1.c b/Project/GateWay/source/Module/FatFS/documents/res/app1.c new file mode 100644 index 0000000..c66a447 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/res/app1.c @@ -0,0 +1,44 @@ +/*------------------------------------------------------------/ +/ Open or create a file in append mode +/ (This function was sperseded by FA_OPEN_APPEND flag at FatFs R0.12a) +/------------------------------------------------------------*/ + +FRESULT open_append ( + FIL* fp, /* [OUT] File object to create */ + const char* path /* [IN] File name to be opened */ +) +{ + FRESULT fr; + + /* Opens an existing file. If not exist, creates a new file. */ + fr = f_open(fp, path, FA_WRITE | FA_OPEN_ALWAYS); + if (fr == FR_OK) { + /* Seek to end of the file to append data */ + fr = f_lseek(fp, f_size(fp)); + if (fr != FR_OK) + f_close(fp); + } + return fr; +} + + +int main (void) +{ + FRESULT fr; + FATFS fs; + FIL fil; + + /* Open or create a log file and ready to append */ + f_mount(&fs, "", 0); + fr = open_append(&fil, "logfile.txt"); + if (fr != FR_OK) return 1; + + /* Append a line */ + f_printf(&fil, "%02u/%02u/%u, %2u:%02u\n", Mday, Mon, Year, Hour, Min); + + /* Close the file */ + f_close(&fil); + + return 0; +} + diff --git a/Project/GateWay/source/Module/FatFS/documents/res/app2.c b/Project/GateWay/source/Module/FatFS/documents/res/app2.c new file mode 100644 index 0000000..3d14709 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/res/app2.c @@ -0,0 +1,81 @@ +/*------------------------------------------------------------/ +/ Delete a sub-directory even if it contains any file +/-------------------------------------------------------------/ +/ The delete_node() function is for R0.12+. +/ It works regardless of FF_FS_RPATH. +*/ + + +FRESULT delete_node ( + TCHAR* path, /* Path name buffer with the sub-directory to delete */ + UINT sz_buff, /* Size of path name buffer (items) */ + FILINFO* fno /* Name read buffer */ +) +{ + UINT i, j; + FRESULT fr; + DIR dir; + + + fr = f_opendir(&dir, path); /* Open the sub-directory to make it empty */ + if (fr != FR_OK) return fr; + + for (i = 0; path[i]; i++) ; /* Get current path length */ + path[i++] = _T('/'); + + for (;;) { + fr = f_readdir(&dir, fno); /* Get a directory item */ + if (fr != FR_OK || !fno->fname[0]) break; /* End of directory? */ + j = 0; + do { /* Make a path name */ + if (i + j >= sz_buff) { /* Buffer over flow? */ + fr = 100; break; /* Fails with 100 when buffer overflow */ + } + path[i + j] = fno->fname[j]; + } while (fno->fname[j++]); + if (fno->fattrib & AM_DIR) { /* Item is a sub-directory */ + fr = delete_node(path, sz_buff, fno); + } else { /* Item is a file */ + fr = f_unlink(path); + } + if (fr != FR_OK) break; + } + + path[--i] = 0; /* Restore the path name */ + f_closedir(&dir); + + if (fr == FR_OK) fr = f_unlink(path); /* Delete the empty sub-directory */ + return fr; +} + + + + +int main (void) /* How to use */ +{ + FRESULT fr; + FATFS fs; + TCHAR buff[256]; + FILINFO fno; + + + f_mount(&fs, _T("5:"), 0); + + /* Directory to be deleted */ + _tcscpy(buff, _T("5:dir")); + + /* Delete the directory */ + fr = delete_node(buff, sizeof buff / sizeof buff[0], &fno); + + /* Check the result */ + if (fr) { + _tprintf(_T("Failed to delete the directory. (%u)\n"), fr); + return fr; + } else { + _tprintf(_T("The directory and the contents have successfully been deleted.\n"), buff); + return 0; + } +} + + + diff --git a/Project/GateWay/source/Module/FatFS/documents/res/app3.c b/Project/GateWay/source/Module/FatFS/documents/res/app3.c new file mode 100644 index 0000000..7f9b508 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/res/app3.c @@ -0,0 +1,109 @@ +/*----------------------------------------------------------------------/ +/ Allocate a contiguous area to the file +/-----------------------------------------------------------------------/ +/ This function checks if the file is contiguous with desired size. +/ If not, a block of contiguous sectors is allocated to the file. +/ If the file has been opened without FA_WRITE flag, it only checks if +/ the file is contiguous and returns the resulut. +/-----------------------------------------------------------------------/ +/ This function can work with FatFs R0.09 - R0.11a. +/ It is incompatible with R0.12+. Use f_expand function instead. +/----------------------------------------------------------------------*/ + +/* Declarations of FatFs internal functions accessible from applications. +/ This is intended to be used for disk checking/fixing or dirty hacks :-) */ +DWORD clust2sect (FATFS* fs, DWORD clst); +DWORD get_fat (FATFS* fs, DWORD clst); +FRESULT put_fat (FATFS* fs, DWORD clst, DWORD val); + + +DWORD allocate_contiguous_clusters ( /* Returns the first sector in LBA (0:error or not contiguous) */ + FIL* fp, /* Pointer to the open file object */ + DWORD len /* Number of bytes to allocate */ +) +{ + DWORD csz, tcl, ncl, ccl, cl; + + + if (f_lseek(fp, 0) || !len) /* Check if the given parameters are valid */ + return 0; + csz = 512UL * fp->fs->csize; /* Cluster size in unit of byte (assuming 512 bytes/sector) */ + tcl = (len + csz - 1) / csz; /* Total number of clusters required */ + len = tcl * csz; /* Round-up file size to the cluster boundary */ + + /* Check if the existing cluster chain is contiguous */ + if (len == fp->fsize) { + ncl = 0; ccl = fp->sclust; + do { + cl = get_fat(fp->fs, ccl); /* Get the cluster status */ + if (cl + 1 < 3) return 0; /* Hard error? */ + if (cl != ccl + 1 && cl < fp->fs->n_fatent) break; /* Not contiguous? */ + ccl = cl; + } while (++ncl < tcl); + if (ncl == tcl) /* Is the file contiguous? */ + return clust2sect(fp->fs, fp->sclust); /* File is contiguous. Return the start sector */ + } + + /* File is not contiguous */ +#if _FS_READONLY + return 0; /* Exit if in read-only cfg. */ +#else + if (!(fp->flag & FA_WRITE)) return 0; /* Exit if the file object is for read-only */ + + if (f_truncate(fp)) return 0; /* Remove the non-contiguous chain */ + + /* Find a free contiguous area */ + ccl = cl = 2; ncl = 0; + do { + if (cl >= fp->fs->n_fatent) return 0; /* No contiguous area is found. */ + if (get_fat(fp->fs, cl)) { /* Encounterd a cluster in use */ + do { /* Skip the block of used clusters */ + cl++; + if (cl >= fp->fs->n_fatent) return 0; /* No contiguous area is found. */ + } while (get_fat(fp->fs, cl)); + ccl = cl; ncl = 0; + } + cl++; ncl++; + } while (ncl < tcl); + + /* Create a contiguous cluster chain */ + fp->fs->last_clust = ccl - 1; + if (f_lseek(fp, len)) return 0; + + return clust2sect(fp->fs, fp->sclust); /* Return file start sector */ +#endif +} + + +int main (void) +{ + FRESULT fr; + DRESULT dr; + FATFS fs; + FIL fil; + DWORD org; + + + /* Open or create a file to write */ + f_mount(&fs, "", 0); + fr = f_open(&fil, "fastrec.log", FA_READ | FA_WRITE | FA_OPEN_ALWAYS); + if (fr) return 1; + + /* Check if the file is 256MB in size and occupies a contiguous area. + / If not, a contiguous area will be re-allocated to the file. */ + org = allocate_contiguous_clusters(&fil, 0x10000000); + if (!org) { + printf("Function failed due to any error or insufficient contiguous area.\n"); + f_close(&fil); + return 1; + } + + /* Now you can read/write the file without filesystem layer. */ + ... + dr = disk_write(fil.fs->drv, Buff, org, 1024); /* Write 512KiB from top of the file */ + ... + + f_close(&fil); + return 0; +} + diff --git a/Project/GateWay/source/Module/FatFS/documents/res/app4.c b/Project/GateWay/source/Module/FatFS/documents/res/app4.c new file mode 100644 index 0000000..656a061 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/res/app4.c @@ -0,0 +1,315 @@ +/*----------------------------------------------------------------------/ +/ Low level disk I/O module function checker / +/-----------------------------------------------------------------------/ +/ WARNING: The data on the target drive will be lost! +*/ + +#include +#include +#include "ff.h" /* Declarations of sector size */ +#include "diskio.h" /* Declarations of disk functions */ + + + +static DWORD pn ( /* Pseudo random number generator */ + DWORD pns /* 0:Initialize, !0:Read */ +) +{ + static DWORD lfsr; + UINT n; + + + if (pns) { + lfsr = pns; + for (n = 0; n < 32; n++) pn(0); + } + if (lfsr & 1) { + lfsr >>= 1; + lfsr ^= 0x80200003; + } else { + lfsr >>= 1; + } + return lfsr; +} + + +int test_diskio ( + BYTE pdrv, /* Physical drive number to be checked (all data on the drive will be lost) */ + UINT ncyc, /* Number of test cycles */ + DWORD* buff, /* Pointer to the working buffer */ + UINT sz_buff /* Size of the working buffer in unit of byte */ +) +{ + UINT n, cc, ns; + DWORD sz_drv, lba, lba2, sz_eblk, pns = 1; + WORD sz_sect; + BYTE *pbuff = (BYTE*)buff; + DSTATUS ds; + DRESULT dr; + + + printf("test_diskio(%u, %u, 0x%08X, 0x%08X)\n", pdrv, ncyc, (UINT)buff, sz_buff); + + if (sz_buff < FF_MAX_SS + 8) { + printf("Insufficient work area to run the program.\n"); + return 1; + } + + for (cc = 1; cc <= ncyc; cc++) { + printf("**** Test cycle %u of %u start ****\n", cc, ncyc); + + printf(" disk_initalize(%u)", pdrv); + ds = disk_initialize(pdrv); + if (ds & STA_NOINIT) { + printf(" - failed.\n"); + return 2; + } else { + printf(" - ok.\n"); + } + + printf("**** Get drive size ****\n"); + printf(" disk_ioctl(%u, GET_SECTOR_COUNT, 0x%08X)", pdrv, (UINT)&sz_drv); + sz_drv = 0; + dr = disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_drv); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 3; + } + if (sz_drv < 128) { + printf("Failed: Insufficient drive size to test.\n"); + return 4; + } + printf(" Number of sectors on the drive %u is %lu.\n", pdrv, sz_drv); + +#if FF_MAX_SS != FF_MIN_SS + printf("**** Get sector size ****\n"); + printf(" disk_ioctl(%u, GET_SECTOR_SIZE, 0x%X)", pdrv, (UINT)&sz_sect); + sz_sect = 0; + dr = disk_ioctl(pdrv, GET_SECTOR_SIZE, &sz_sect); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 5; + } + printf(" Size of sector is %u bytes.\n", sz_sect); +#else + sz_sect = FF_MAX_SS; +#endif + + printf("**** Get block size ****\n"); + printf(" disk_ioctl(%u, GET_BLOCK_SIZE, 0x%X)", pdrv, (UINT)&sz_eblk); + sz_eblk = 0; + dr = disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_eblk); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + } + if (dr == RES_OK || sz_eblk >= 2) { + printf(" Size of the erase block is %lu sectors.\n", sz_eblk); + } else { + printf(" Size of the erase block is unknown.\n"); + } + + /* Single sector write test */ + printf("**** Single sector write test ****\n"); + lba = 0; + for (n = 0, pn(pns); n < sz_sect; n++) pbuff[n] = (BYTE)pn(0); + printf(" disk_write(%u, 0x%X, %lu, 1)", pdrv, (UINT)pbuff, lba); + dr = disk_write(pdrv, pbuff, lba, 1); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 6; + } + printf(" disk_ioctl(%u, CTRL_SYNC, NULL)", pdrv); + dr = disk_ioctl(pdrv, CTRL_SYNC, 0); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 7; + } + memset(pbuff, 0, sz_sect); + printf(" disk_read(%u, 0x%X, %lu, 1)", pdrv, (UINT)pbuff, lba); + dr = disk_read(pdrv, pbuff, lba, 1); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 8; + } + for (n = 0, pn(pns); n < sz_sect && pbuff[n] == (BYTE)pn(0); n++) ; + if (n == sz_sect) { + printf(" Read data matched.\n"); + } else { + printf(" Read data differs from the data written.\n"); + return 10; + } + pns++; + + printf("**** Multiple sector write test ****\n"); + lba = 5; ns = sz_buff / sz_sect; + if (ns > 4) ns = 4; + if (ns > 1) { + for (n = 0, pn(pns); n < (UINT)(sz_sect * ns); n++) pbuff[n] = (BYTE)pn(0); + printf(" disk_write(%u, 0x%X, %lu, %u)", pdrv, (UINT)pbuff, lba, ns); + dr = disk_write(pdrv, pbuff, lba, ns); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 11; + } + printf(" disk_ioctl(%u, CTRL_SYNC, NULL)", pdrv); + dr = disk_ioctl(pdrv, CTRL_SYNC, 0); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 12; + } + memset(pbuff, 0, sz_sect * ns); + printf(" disk_read(%u, 0x%X, %lu, %u)", pdrv, (UINT)pbuff, lba, ns); + dr = disk_read(pdrv, pbuff, lba, ns); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 13; + } + for (n = 0, pn(pns); n < (UINT)(sz_sect * ns) && pbuff[n] == (BYTE)pn(0); n++) ; + if (n == (UINT)(sz_sect * ns)) { + printf(" Read data matched.\n"); + } else { + printf(" Read data differs from the data written.\n"); + return 14; + } + } else { + printf(" Test skipped.\n"); + } + pns++; + + printf("**** Single sector write test (unaligned buffer address) ****\n"); + lba = 5; + for (n = 0, pn(pns); n < sz_sect; n++) pbuff[n+3] = (BYTE)pn(0); + printf(" disk_write(%u, 0x%X, %lu, 1)", pdrv, (UINT)(pbuff+3), lba); + dr = disk_write(pdrv, pbuff+3, lba, 1); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 15; + } + printf(" disk_ioctl(%u, CTRL_SYNC, NULL)", pdrv); + dr = disk_ioctl(pdrv, CTRL_SYNC, 0); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 16; + } + memset(pbuff+5, 0, sz_sect); + printf(" disk_read(%u, 0x%X, %lu, 1)", pdrv, (UINT)(pbuff+5), lba); + dr = disk_read(pdrv, pbuff+5, lba, 1); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 17; + } + for (n = 0, pn(pns); n < sz_sect && pbuff[n+5] == (BYTE)pn(0); n++) ; + if (n == sz_sect) { + printf(" Read data matched.\n"); + } else { + printf(" Read data differs from the data written.\n"); + return 18; + } + pns++; + + printf("**** 4GB barrier test ****\n"); + if (sz_drv >= 128 + 0x80000000 / (sz_sect / 2)) { + lba = 6; lba2 = lba + 0x80000000 / (sz_sect / 2); + for (n = 0, pn(pns); n < (UINT)(sz_sect * 2); n++) pbuff[n] = (BYTE)pn(0); + printf(" disk_write(%u, 0x%X, %lu, 1)", pdrv, (UINT)pbuff, lba); + dr = disk_write(pdrv, pbuff, lba, 1); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 19; + } + printf(" disk_write(%u, 0x%X, %lu, 1)", pdrv, (UINT)(pbuff+sz_sect), lba2); + dr = disk_write(pdrv, pbuff+sz_sect, lba2, 1); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 20; + } + printf(" disk_ioctl(%u, CTRL_SYNC, NULL)", pdrv); + dr = disk_ioctl(pdrv, CTRL_SYNC, 0); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 21; + } + memset(pbuff, 0, sz_sect * 2); + printf(" disk_read(%u, 0x%X, %lu, 1)", pdrv, (UINT)pbuff, lba); + dr = disk_read(pdrv, pbuff, lba, 1); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 22; + } + printf(" disk_read(%u, 0x%X, %lu, 1)", pdrv, (UINT)(pbuff+sz_sect), lba2); + dr = disk_read(pdrv, pbuff+sz_sect, lba2, 1); + if (dr == RES_OK) { + printf(" - ok.\n"); + } else { + printf(" - failed.\n"); + return 23; + } + for (n = 0, pn(pns); pbuff[n] == (BYTE)pn(0) && n < (UINT)(sz_sect * 2); n++) ; + if (n == (UINT)(sz_sect * 2)) { + printf(" Read data matched.\n"); + } else { + printf(" Read data differs from the data written.\n"); + return 24; + } + } else { + printf(" Test skipped.\n"); + } + pns++; + + printf("**** Test cycle %u of %u completed ****\n\n", cc, ncyc); + } + + return 0; +} + + + +int main (int argc, char* argv[]) +{ + int rc; + DWORD buff[FF_MAX_SS]; /* Working buffer (4 sector in size) */ + + /* Check function/compatibility of the physical drive #0 */ + rc = test_diskio(0, 3, buff, sizeof buff); + + if (rc) { + printf("Sorry the function/compatibility test failed. (rc=%d)\nFatFs will not work with this disk driver.\n", rc); + } else { + printf("Congratulations! The disk driver works well.\n"); + } + + return rc; +} + diff --git a/Project/GateWay/source/Module/FatFS/documents/res/app5.c b/Project/GateWay/source/Module/FatFS/documents/res/app5.c new file mode 100644 index 0000000..989515b --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/res/app5.c @@ -0,0 +1,38 @@ +/*----------------------------------------------------------------------/ +/ Test if the file is contiguous / +/----------------------------------------------------------------------*/ + +FRESULT test_contiguous_file ( + FIL* fp, /* [IN] Open file object to be checked */ + int* cont /* [OUT] 1:Contiguous, 0:Fragmented or zero-length */ +) +{ + DWORD clst, clsz, step; + FSIZE_t fsz; + FRESULT fr; + + + *cont = 0; + fr = f_rewind(fp); /* Validates and prepares the file */ + if (fr != FR_OK) return fr; + +#if FF_MAX_SS == FF_MIN_SS + clsz = (DWORD)fp->obj.fs->csize * FF_MAX_SS; /* Cluster size */ +#else + clsz = (DWORD)fp->obj.fs->csize * fp->obj.fs->ssize; +#endif + fsz = f_size(fp); + if (fsz > 0) { + clst = fp->obj.sclust - 1; /* A cluster leading the first cluster for first test */ + while (fsz) { + step = (fsz >= clsz) ? clsz : (DWORD)fsz; + fr = f_lseek(fp, f_tell(fp) + step); /* Advances file pointer a cluster */ + if (fr != FR_OK) return fr; + if (clst + 1 != fp->clust) break; /* Is not the cluster next to previous one? */ + clst = fp->clust; fsz -= step; /* Get current cluster for next test */ + } + if (fsz == 0) *cont = 1; /* All done without fail? */ + } + + return FR_OK; +} diff --git a/Project/GateWay/source/Module/FatFS/documents/res/app6.c b/Project/GateWay/source/Module/FatFS/documents/res/app6.c new file mode 100644 index 0000000..69c065e --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/res/app6.c @@ -0,0 +1,61 @@ +/*---------------------------------------------------------------------*/ +/* Raw Read/Write Throughput Checker */ +/*---------------------------------------------------------------------*/ + +#include +#include +#include "diskio.h" +#include "ff.h" + + +int test_raw_speed ( + BYTE pdrv, /* Physical drive number */ + DWORD lba, /* Start LBA for read/write test */ + DWORD len, /* Number of bytes to read/write (must be multiple of sz_buff) */ + void* buff, /* Read/write buffer */ + UINT sz_buff /* Size of read/write buffer (must be multiple of FF_MAX_SS) */ +) +{ + WORD ss; + DWORD ofs, tmr; + + +#if FF_MIN_SS != FF_MAX_SS + if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) { + printf("\ndisk_ioctl() failed.\n"); + return 0; + } +#else + ss = FF_MAX_SS; +#endif + + printf("Starting raw write test at sector %lu in %u bytes of data chunks...", lba, sz_buff); + tmr = systimer(); + for (ofs = 0; ofs < len / ss; ofs += sz_buff / ss) { + if (disk_write(pdrv, buff, lba + ofs, sz_buff / ss) != RES_OK) { + printf("\ndisk_write() failed.\n"); + return 0; + } + } + if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) { + printf("\ndisk_ioctl() failed.\n"); + return 0; + } + tmr = systimer() - tmr; + printf("\n%lu bytes written and it took %lu timer ticks.\n", len, tmr); + + printf("Starting raw read test at sector %lu in %u bytes of data chunks...", lba, sz_buff); + tmr = systimer(); + for (ofs = 0; ofs < len / ss; ofs += sz_buff / ss) { + if (disk_read(pdrv, buff, lba + ofs, sz_buff / ss) != RES_OK) { + printf("\ndisk_read() failed.\n"); + return 0; + } + } + tmr = systimer() - tmr; + printf("\n%lu bytes read and it took %lu timer ticks.\n", len, tmr); + + printf("Test completed.\n"); + return 1; +} + diff --git a/Project/GateWay/source/Module/FatFS/documents/res/f1.png b/Project/GateWay/source/Module/FatFS/documents/res/f1.png new file mode 100644 index 0000000..5191700 Binary files /dev/null and b/Project/GateWay/source/Module/FatFS/documents/res/f1.png differ diff --git a/Project/GateWay/source/Module/FatFS/documents/res/f2.png b/Project/GateWay/source/Module/FatFS/documents/res/f2.png new file mode 100644 index 0000000..8ef0ec2 Binary files /dev/null and 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0000000..9db87b7 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/documents/updates.html @@ -0,0 +1,481 @@ + + + + + + + + +FatFs - Updates and Migration Notes + + +

Updates and Migration Notes

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RevisionUpdatesMigration Notes
R0.15
Nov 6, 2022		 +Changed user provided synchronization functions in order to completely eliminate the platform dependency from FatFs code.
+Fixed a potential error in f_mount when FF_FS_REENTRANT.
+Fixed file lock control FF_FS_LOCK is not mutal excluded when FF_FS_REENTRANT && FF_VOLUMES > 1 is true.
+Fixed f_mkfs creates broken exFAT volume when the size of volume is >= 2^32 sectors.
+Fixed string functions cannot write the unicode characters not in BMP when FF_LFN_UNICODE == 2 (UTF-8).
+Fixed a compatibility issue in identification of GPT header.
+		 +User provided synchronization functions, ff_cre_syncobj, ff_del_syncobj, ff_req_grant and ff_rel_grant, needed when FF_FS_REENTRANT are replaced with ff_mutex_create, ff_mutex_delete, ff_mutex_take and ff_mutex_give respectively. For example, see ffsystem.c.
+FF_SYNC_t is removed from the configuration options.
+
R0.14b
Apr 17, 2021		 +Made FatFs uses standard library string.h for copy, compare and search instead of built-in string functions.
+Added support for long long integer and floating point to f_printf. (FF_STRF_LLI and FF_STRF_FP)
+Made path name parser ignores the terminating separator to allow "dir/".
+Improved the compatibility in Unix style path name feature.
+Fixed the file gets dead-locked when f_open failed with certain conditions. (appeared at R0.12a)
+Fixed f_mkfs can create wrong exFAT volume due to a timing dependent error. (appeared at R0.12)
+Fixed code page 855 cannot be set by f_setcp. (appeared at R0.13)
+Fixed some compiler warnings.
+		 +From this revision, FatFs depends on string.h.
+
R0.14a
Dec 05, 2020		 +Limited number of recursive calls in f_findnext to prevent stack overflow.
+Fixed old floppy disks formatted with MS-DOS 2.x and 3.x cannot be mounted.
+Fixed some compiler warnings.
+		 +Number of wildcards in the matching pattern in f_findfirst is limited to 4.
+
R0.14
Oct 14, 2019		 +Added support for 64-bit LBA and GUID partition table (FF_LBA64)
+Changed some API functions, f_mkfs and f_fdisk.
+Fixed f_open cannot find the file with file name in length of FF_MAX_LFN characters.
+Fixed f_readdir cannot retrieve long file names in length of FF_MAX_LFN - 1 characters.
+Fixed f_readdir returns file names with wrong case conversion. (appeared at R0.12)
+Fixed f_mkfs can fail to create exFAT volume in the second partition. (appeared at R0.12)
+		 +Usage of f_mkfs and f_fdisk is changed and some features are added to these functions.
+
R0.13c
Oct 14, 2018		 +Supported stdint.h for C99 and later. (integer.h was included in ff.h)
+Fixed reading a directory gets infinite loop when the last directory entry is not empty. (appeared at R0.12)
+Fixed creating a sub-directory in the fragmented sub-directory on the exFAT volume collapses FAT chain of the parent directory. (appeared at R0.12)
+Fixed f_getcwd cause output buffer overrun when the buffer has a valid drive number. (appeared at R0.13b)
+		 +From this revision, FatFs depends on stdint.h in C99 or later.
+integer.h is removed.
+
R0.13b
Apr 07, 2018		 +Added support for UTF-32 encoding on the API. (FF_LFN_UNICODE = 3)
+Added support for Unix style volume prefix. (FF_STR_VOLUME_ID = 2)
+Fixed accesing objects in the exFAT root directory beyond the cluster boundary can fail. (appeared at R0.12c)
+Fixed f_setlabel does not reject some invalid characters. (appeared at R0.09b)
+		 +
R0.13a
Oct 14, 2017		 +Added support for UTF-8 encoding on the API. (FF_LFN_UNICODE = 2)
+Added options for file name output buffer. (FF_LFN_BUF, FF_SFN_BUF)
+Added dynamic memory allocation option for working buffer of f_mkfs and f_fdisk.
+Fixed f_fdisk and f_mkfs create the partition table with wrong CHS parameters. (appeared at R0.09)
+Fixed f_unlink can cause lost clusters at fragmented file on the exFAT volume. (appeared at R0.12c)
+Fixed f_setlabel rejects some valid characters for exFAT volume. (appeared at R0.12)
+		 +
R0.13
May 21, 2017		 +Prefix of configuration item names are changed from "_" to "FF_".
+Added f_setcp, run-time code page configuration. (FF_CODE_PAGE = 0)
+Improved cluster allocation time on stretch a deep buried cluster chain.
+Improved processing time of f_mkdir with large cluster size by using FF_USE_LFN = 3.
+Improved exFAT NoFatChain flag of the fragmented file to be set after it is truncated and got contiguous.
+Fixed archive attribute is left not set when a file on the exFAT volume is renamed. (appeared at R0.12)
+Fixed exFAT FAT entry can be collapsed when write or lseek operation to the existing file is done. (appeared at R0.12c)
+Fixed creating a file can fail when a new cluster allocation to the exFAT directory occures. (appeared at R0.12c)
+		 +ASCII only configuration, FF_CODE_PAGE = 1, is removed. Use FF_CODE_PAGE = 437 instead.
+
R0.12c
Mar 04, 2017		 +Improved write throughput at the fragmented file on the exFAT volume.
+Made memory usage for exFAT be able to be reduced as decreasing _MAX_LFN.
+Fixed successive f_getfree can return wrong count on the FAT12/16 volume. (appeared at R0.12)
+Fixed configuration option _VOLUMES cannot be set 10. (appeared at R0.10c)
+		 +
R0.12b
Sep 4, 2016		 +Made f_rename be able to rename objects with the same name but case.
+Fixed an error in the case conversion teble of code page 866. (ff.c)
+Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12)
+Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12)
+Fixed f_mkfs creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12a)
+Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12)
+Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12)
+Fixed some internal errors in f_expand and f_lseek. (appeared at R0.12)
+		 +
R0.12a
Jul 10, 2016		 +Added support for creating exFAT volume with some changes of f_mkfs.
+Added a file open method FA_OPEN_APPEND.
+f_forward is available regardless of _FS_TINY.
+Fixed f_mkfs creates broken volume. (appeared at R0.12)
+Fixed wrong memory read in create_name. (appeared at R0.12)
+Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD.
+		 +Usage of f_mkfs is changed.
+
R0.12
Apr 12, 2016		 +Added support for exFAT file system. (_FS_EXFAT)
+Added f_expand. (_USE_EXPAND)
+Changed some members in FINFO and behavior of f_readdir.
+Added a configuration option _USE_CHMOD.
+Fixed errors in the case conversion teble of Unicode (cc*.c).
+		 +Usage and members of FINFO sructure used in f_readdir is changed.
+Dot entries in the sub-directory are never appear in f_readdir.
+".." does not work as path name in exFAT volume.
+f_getcwd does not work in exFAT volume.
+Many members in FIL and DIR structure are changed.
+To use f_chmod, _USE_CHMOD needs to be set.
+_WORD_ACCESS is removed from the configuration options.
+
R0.11a
Sep 5, 2015		 +Fixed wrong media change can lead a deadlock at thread-safe configuration.
+Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE)
+Fixed errors in the case conversion teble of code page 437 and 850 (ff.c).
+Fixed errors in the case conversion teble of Unicode (cc*.c).
+		 +Removed some code pages actually not exist on the standard systems. (_CODE_PAGE)
+
R0.11
Feb 9, 2015		 +Added f_findfirst and f_findnext. (_USE_FIND)
+Fixed f_unlink does not remove cluster chain of the file. (appeared at R0.10c)
+Fixed _FS_NORTC option does not work properly. (appeared at R0.10c)
+		 +
R0.10c
Nov 9, 2014		 +Added a configuration option for the platforms without RTC. (_FS_NORTC)
+Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel. (appeared at R0.09b)
+Fixed a potential problem of FAT access that can appear on disk error.
+Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08)
+		 +
R0.10b
May 19, 2014		 +Fixed a hard error in the disk I/O layer can collapse the directory entry.
+Fixed LFN entry is not deleted on delete/rename an object with its lossy converted SFN. (appeared at R0.07)
+		 +
R0.10a
Jan 15, 2014		 +Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID)
+Added an option for minimum sector size. (_MIN_SS)
+2nd argument of f_rename can have a drive number and it will be ignored.
+Fixed f_mount with forced mount fails when drive number is larger than 0. (appeared at R0.10)
+Fixed f_close invalidates the file object without volume lock.
+Fixed volume lock is left acquired after return from f_closedir. (appeared at R0.10)
+Fixed creation of a directory entry with LFN fails on too many SFN collisions. (appeared at R0.07)
+		 +
R0.10
Oct 2, 2013		 +Added an option for character encoding on the file. (_STRF_ENCODE)
+Added f_closedir.
+Added forced full FAT scan option for f_getfree. (_FS_NOFSINFO)
+Added forced mount option with changes of f_mount.
+Improved behavior of volume auto detection.
+Improved write throughput of f_puts and f_printf.
+Changed argument of f_chdrive, f_mkfs, disk_read and disk_write.
+Fixed f_write can be truncated when the file size is close to 4 GB.
+Fixed f_open, f_mkdir and f_setlabel can return incorrect result code on error.
+		 +
R0.09b
Jan 24, 2013		 +Added f_getlabel and f_setlabel. (_USE_LABEL)
+		 +
R0.09a
Aug 27, 2012		 +Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
+Changed file functions reject null object pointer to avoid crash.
+Changed option name _FS_SHARE to _FS_LOCK.
+		 +
R0.09
Sep 6, 2011		 +f_mkfs supports multiple partition on a physical drive.
+Added f_fdisk. (_MULTI_PARTITION = 2)
+		 +
R0.08b
Jan 15, 2011		 +Fast seek function is also applied to f_read and f_write.
+f_lseek reports required table size on creating CLMP.
+Extended format syntax of f_printf.
+Ignores duplicated directory separators in given path names.
+		 +
R0.08a
Aug 16, 2010		 +Added f_getcwd. (_FS_RPATH = 2)
+Added sector erase function. (_USE_ERASE)
+Moved file lock semaphore table from fs object to the bss.
+Fixed f_mkdir creates wrong directory on non-LFN cfg when the given name contains ';'.
+Fixed f_mkfs creates wrong FAT32 volume.
+		 +
R0.08
May 15, 2010		 +Added an option to _USE_LFN
+Added support of file lock. (_FS_SHARE)
+Added fast seek function. (_USE_FASTSEEK)
+Changed a type name on the API, XCHAR to TCHAR.
+Changed member, fname, in the FILINFO on Unicode cfg.
+String functions support UTF-8 encoding files on Unicode cfg.
+		 +
R0.07e
Nov 3, 2009		 +Separated out configuration options from ff.h to ffconf.h.
+Added a configuration option, _LFN_UNICODE.
+Fixed f_unlink fails to remove a sub-dir on _FS_RPATH.
+Fixed name matching error on the 13 char boundary.
+Changed f_readdir to return the SFN with always upper case on non-LFN cfg.
+		 +
R0.07c
Jan 21, 2009		 +Fixed f_unlink may return FR_OK on error.
+Fixed wrong cache control in f_lseek.
+Added support of relative path.
+Added f_chdir.
+Added f_chdrive.
+Added proper case conversion to extended characters.
+		 +
R0.07a
Apr 14, 2009		 +Separated out OS dependent code on re-entrant configuration.
+Added multiple sector size support.
+		 +
R0.07
Apr 1, 2009		 +Merged Tiny-FatFs into FatFs as a buffer configuration option.
+Added support for long file extension.
+Added multiple code page support.
+Added re-entrancy for multitask operation.
+Added auto cluster size selection to f_mkfs.
+Added rewind option to f_readdir.
+Changed result code of critical errors.
+Renamed string functions to avoid name collision.
+		 +
R0.06
Apr 1, 2008		 +Added f_forward. (Tiny-FatFs)
+Added string functions: f_gets, f_putc, f_puts and f_printf.
+Improved performance of f_lseek on moving to the same or following cluster.
+		 +
R0.05a
Feb 3, 2008		 +Added f_truncate.
+Added f_utime.
+Fixed off by one error at FAT sub-type determination.
+Fixed btr in f_read can be mistruncated.
+Fixed cached sector is left not flushed when create and close without write.
+		 +
R0.05
Aug 26, 2007		 +Changed arguments of f_read, f_write.
+Changed arguments of f_mkfs. (FatFs)
+Fixed f_mkfs on FAT32 creates incorrect FSInfo. (FatFs)
+Fixed f_mkdir on FAT32 creates broken directory. (FatFs)
+		 +
R0.04b
May 5, 2007		 +Added _USE_NTFLAG option.
+Added support for FSInfo in FAT32 volume.
+Fixed some problems corresponds to FAT32. (Tiny-FatFs)
+Fixed DBCS name can result FR_INVALID_NAME.
+Fixed short seek (<= csize) collapses the file object.
+		 +
R0.04a
Apr 1, 2007		 +Supported multiple partitions on a plysical drive. (FatFs)
+Added minimization level 3.
+Added a capability of extending file size to f_lseek.
+Fixed an endian sensitive code in f_mkfs. (FatFs)
+Fixed a problem corresponds to FAT32 support. (Tiny-FatFs)
+		 +
R0.04
Feb 4, 2007		 +Supported multiple drive system. (FatFs)
+Changed some APIs for multiple drive system.
+Added f_mkfs. (FatFs)
+Added _USE_FAT32 option. (Tiny-FatFs)
+		 +
R0.03a
Dec 11, 2006		 +Improved cluster scan algolithm to write files fast.
+Fixed f_mkdir creates broken directory on FAT32.
+		 +
R0.03
Sep 22, 2006		 +Added f_rename. +Changed option _FS_MINIMUM to _FS_MINIMIZE.
+		 +
R0.02a
Jun 10, 2006		 +Added a configuration option _FS_MINIMUM.
+		 +
R0.02
Jun 01, 2006		 +Added FAT12.
+Removed unbuffered mode.
+Fixed a problem on small (<32M) patition.
+		 +
R0.01
Apr 29, 2006		 +First release.
+		 +
+ + diff --git a/Project/GateWay/source/Module/FatFS/ff15.zip b/Project/GateWay/source/Module/FatFS/ff15.zip new file mode 100644 index 0000000..b68391f Binary files /dev/null and b/Project/GateWay/source/Module/FatFS/ff15.zip differ diff --git a/Project/GateWay/source/Module/FatFS/source/00history.txt b/Project/GateWay/source/Module/FatFS/source/00history.txt new file mode 100644 index 0000000..7a153a2 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/source/00history.txt @@ -0,0 +1,369 @@ +---------------------------------------------------------------------------- + Revision history of FatFs module +---------------------------------------------------------------------------- + +R0.00 (February 26, 2006) + + Prototype. + + + +R0.01 (April 29, 2006) + + The first release. + + + +R0.02 (June 01, 2006) + + Added FAT12 support. + Removed unbuffered mode. + Fixed a problem on small (<32M) partition. + + + +R0.02a (June 10, 2006) + + Added a configuration option (_FS_MINIMUM). + + + +R0.03 (September 22, 2006) + + Added f_rename(). + Changed option _FS_MINIMUM to _FS_MINIMIZE. + + + +R0.03a (December 11, 2006) + + Improved cluster scan algorithm to write files fast. + Fixed f_mkdir() creates incorrect directory on FAT32. + + + +R0.04 (February 04, 2007) + + Added f_mkfs(). + Supported multiple drive system. + Changed some interfaces for multiple drive system. + Changed f_mountdrv() to f_mount(). + + + +R0.04a (April 01, 2007) + + Supported multiple partitions on a physical drive. + Added a capability of extending file size to f_lseek(). + Added minimization level 3. + Fixed an endian sensitive code in f_mkfs(). + + + +R0.04b (May 05, 2007) + + Added a configuration option _USE_NTFLAG. + Added FSINFO support. + Fixed DBCS name can result FR_INVALID_NAME. + Fixed short seek (<= csize) collapses the file object. + + + +R0.05 (August 25, 2007) + + Changed arguments of f_read(), f_write() and f_mkfs(). + Fixed f_mkfs() on FAT32 creates incorrect FSINFO. + Fixed f_mkdir() on FAT32 creates incorrect directory. + + + +R0.05a (February 03, 2008) + + Added f_truncate() and f_utime(). + Fixed off by one error at FAT sub-type determination. + Fixed btr in f_read() can be mistruncated. + Fixed cached sector is not flushed when create and close without write. + + + +R0.06 (April 01, 2008) + + Added fputc(), fputs(), fprintf() and fgets(). + Improved performance of f_lseek() on moving to the same or following cluster. + + + +R0.07 (April 01, 2009) + + Merged Tiny-FatFs as a configuration option. (_FS_TINY) + Added long file name feature. (_USE_LFN) + Added multiple code page feature. (_CODE_PAGE) + Added re-entrancy for multitask operation. (_FS_REENTRANT) + Added auto cluster size selection to f_mkfs(). + Added rewind option to f_readdir(). + Changed result code of critical errors. + Renamed string functions to avoid name collision. + + + +R0.07a (April 14, 2009) + + Septemberarated out OS dependent code on reentrant cfg. + Added multiple sector size feature. + + + +R0.07c (June 21, 2009) + + Fixed f_unlink() can return FR_OK on error. + Fixed wrong cache control in f_lseek(). + Added relative path feature. + Added f_chdir() and f_chdrive(). + Added proper case conversion to extended character. + + + +R0.07e (November 03, 2009) + + Septemberarated out configuration options from ff.h to ffconf.h. + Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH. + Fixed name matching error on the 13 character boundary. + Added a configuration option, _LFN_UNICODE. + Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. + + + +R0.08 (May 15, 2010) + + Added a memory configuration option. (_USE_LFN = 3) + Added file lock feature. (_FS_SHARE) + Added fast seek feature. (_USE_FASTSEEK) + Changed some types on the API, XCHAR->TCHAR. + Changed .fname in the FILINFO structure on Unicode cfg. + String functions support UTF-8 encoding files on Unicode cfg. + + + +R0.08a (August 16, 2010) + + Added f_getcwd(). (_FS_RPATH = 2) + Added sector erase feature. (_USE_ERASE) + Moved file lock semaphore table from fs object to the bss. + Fixed f_mkfs() creates wrong FAT32 volume. + + + +R0.08b (January 15, 2011) + + Fast seek feature is also applied to f_read() and f_write(). + f_lseek() reports required table size on creating CLMP. + Extended format syntax of f_printf(). + Ignores duplicated directory separators in given path name. + + + +R0.09 (September 06, 2011) + + f_mkfs() supports multiple partition to complete the multiple partition feature. + Added f_fdisk(). + + + +R0.09a (August 27, 2012) + + Changed f_open() and f_opendir() reject null object pointer to avoid crash. + Changed option name _FS_SHARE to _FS_LOCK. + Fixed assertion failure due to OS/2 EA on FAT12/16 volume. + + + +R0.09b (January 24, 2013) + + Added f_setlabel() and f_getlabel(). + + + +R0.10 (October 02, 2013) + + Added selection of character encoding on the file. (_STRF_ENCODE) + Added f_closedir(). + Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) + Added forced mount feature with changes of f_mount(). + Improved behavior of volume auto detection. + Improved write throughput of f_puts() and f_printf(). + Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). + Fixed f_write() can be truncated when the file size is close to 4GB. + Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error. + + + +R0.10a (January 15, 2014) + + Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID) + Added a configuration option of minimum sector size. (_MIN_SS) + 2nd argument of f_rename() can have a drive number and it will be ignored. + Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10) + Fixed f_close() invalidates the file object without volume lock. + Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10) + Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07) + + + +R0.10b (May 19, 2014) + + Fixed a hard error in the disk I/O layer can collapse the directory entry. + Fixed LFN entry is not deleted when delete/rename an object with lossy converted SFN. (appeared at R0.07) + + + +R0.10c (November 09, 2014) + + Added a configuration option for the platforms without RTC. (_FS_NORTC) + Changed option name _USE_ERASE to _USE_TRIM. + Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b) + Fixed a potential problem of FAT access that can appear on disk error. + Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08) + + + +R0.11 (February 09, 2015) + + Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND) + Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c) + Fixed _FS_NORTC option does not work properly. (appeared at R0.10c) + + + +R0.11a (September 05, 2015) + + Fixed wrong media change can lead a deadlock at thread-safe configuration. + Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE) + Removed some code pages actually not exist on the standard systems. (_CODE_PAGE) + Fixed errors in the case conversion teble of code page 437 and 850 (ff.c). + Fixed errors in the case conversion teble of Unicode (cc*.c). + + + +R0.12 (April 12, 2016) + + Added support for exFAT file system. (_FS_EXFAT) + Added f_expand(). (_USE_EXPAND) + Changed some members in FINFO structure and behavior of f_readdir(). + Added an option _USE_CHMOD. + Removed an option _WORD_ACCESS. + Fixed errors in the case conversion table of Unicode (cc*.c). + + + +R0.12a (July 10, 2016) + + Added support for creating exFAT volume with some changes of f_mkfs(). + Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed. + f_forward() is available regardless of _FS_TINY. + Fixed f_mkfs() creates wrong volume. (appeared at R0.12) + Fixed wrong memory read in create_name(). (appeared at R0.12) + Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD. + + + +R0.12b (September 04, 2016) + + Made f_rename() be able to rename objects with the same name but case. + Fixed an error in the case conversion teble of code page 866. (ff.c) + Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12) + Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12) + Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12) + Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12) + Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12) + Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12) + + + +R0.12c (March 04, 2017) + + Improved write throughput at the fragmented file on the exFAT volume. + Made memory usage for exFAT be able to be reduced as decreasing _MAX_LFN. + Fixed successive f_getfree() can return wrong count on the FAT12/16 volume. (appeared at R0.12) + Fixed configuration option _VOLUMES cannot be set 10. (appeared at R0.10c) + + + +R0.13 (May 21, 2017) + + Changed heading character of configuration keywords "_" to "FF_". + Removed ASCII-only configuration, FF_CODE_PAGE = 1. Use FF_CODE_PAGE = 437 instead. + Added f_setcp(), run-time code page configuration. (FF_CODE_PAGE = 0) + Improved cluster allocation time on stretch a deep buried cluster chain. + Improved processing time of f_mkdir() with large cluster size by using FF_USE_LFN = 3. + Improved NoFatChain flag of the fragmented file to be set after it is truncated and got contiguous. + Fixed archive attribute is left not set when a file on the exFAT volume is renamed. (appeared at R0.12) + Fixed exFAT FAT entry can be collapsed when write or lseek operation to the existing file is done. (appeared at R0.12c) + Fixed creating a file can fail when a new cluster allocation to the exFAT directory occures. (appeared at R0.12c) + + + +R0.13a (October 14, 2017) + + Added support for UTF-8 encoding on the API. (FF_LFN_UNICODE = 2) + Added options for file name output buffer. (FF_LFN_BUF, FF_SFN_BUF). + Added dynamic memory allocation option for working buffer of f_mkfs() and f_fdisk(). + Fixed f_fdisk() and f_mkfs() create the partition table with wrong CHS parameters. (appeared at R0.09) + Fixed f_unlink() can cause lost clusters at fragmented file on the exFAT volume. (appeared at R0.12c) + Fixed f_setlabel() rejects some valid characters for exFAT volume. (appeared at R0.12) + + + +R0.13b (April 07, 2018) + + Added support for UTF-32 encoding on the API. (FF_LFN_UNICODE = 3) + Added support for Unix style volume ID. (FF_STR_VOLUME_ID = 2) + Fixed accesing any object on the exFAT root directory beyond the cluster boundary can fail. (appeared at R0.12c) + Fixed f_setlabel() does not reject some invalid characters. (appeared at R0.09b) + + + +R0.13c (October 14, 2018) + Supported stdint.h for C99 and later. (integer.h was included in ff.h) + Fixed reading a directory gets infinite loop when the last directory entry is not empty. (appeared at R0.12) + Fixed creating a sub-directory in the fragmented sub-directory on the exFAT volume collapses FAT chain of the parent directory. (appeared at R0.12) + Fixed f_getcwd() cause output buffer overrun when the buffer has a valid drive number. (appeared at R0.13b) + + + +R0.14 (October 14, 2019) + Added support for 64-bit LBA and GUID partition table (FF_LBA64 = 1) + Changed some API functions, f_mkfs() and f_fdisk(). + Fixed f_open() function cannot find the file with file name in length of FF_MAX_LFN characters. + Fixed f_readdir() function cannot retrieve long file names in length of FF_MAX_LFN - 1 characters. + Fixed f_readdir() function returns file names with wrong case conversion. (appeared at R0.12) + Fixed f_mkfs() function can fail to create exFAT volume in the second partition. (appeared at R0.12) + + +R0.14a (December 5, 2020) + Limited number of recursive calls in f_findnext(). + Fixed old floppy disks formatted with MS-DOS 2.x and 3.x cannot be mounted. + Fixed some compiler warnings. + + + +R0.14b (April 17, 2021) + Made FatFs uses standard library for copy, compare and search instead of built-in string functions. + Added support for long long integer and floating point to f_printf(). (FF_STRF_LLI and FF_STRF_FP) + Made path name parser ignore the terminating separator to allow "dir/". + Improved the compatibility in Unix style path name feature. + Fixed the file gets dead-locked when f_open() failed with some conditions. (appeared at R0.12a) + Fixed f_mkfs() can create wrong exFAT volume due to a timing dependent error. (appeared at R0.12) + Fixed code page 855 cannot be set by f_setcp(). + Fixed some compiler warnings. + + + +R0.15 (November 6, 2022) + Changed user provided synchronization functions in order to completely eliminate the platform dependency from FatFs code. + FF_SYNC_t is removed from the configuration options. + Fixed a potential error in f_mount when FF_FS_REENTRANT. + Fixed file lock control FF_FS_LOCK is not mutal excluded when FF_FS_REENTRANT && FF_VOLUMES > 1 is true. + Fixed f_mkfs() creates broken exFAT volume when the size of volume is >= 2^32 sectors. + Fixed string functions cannot write the unicode characters not in BMP when FF_LFN_UNICODE == 2 (UTF-8). + Fixed a compatibility issue in identification of GPT header. + diff --git a/Project/GateWay/source/Module/FatFS/source/00readme.txt b/Project/GateWay/source/Module/FatFS/source/00readme.txt new file mode 100644 index 0000000..3de3aea --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/source/00readme.txt @@ -0,0 +1,21 @@ +FatFs Module Source Files R0.15 + + +FILES + + 00readme.txt This file. + 00history.txt Revision history. + ff.c FatFs module. + ffconf.h Configuration file of FatFs module. + ff.h Common include file for FatFs and application module. + diskio.h Common include file for FatFs and disk I/O module. + diskio.c An example of glue function to attach existing disk I/O module to FatFs. + ffunicode.c Optional Unicode utility functions. + ffsystem.c An example of optional O/S related functions. + + + Low level disk I/O module is not included in this archive because the FatFs + module is only a generic file system layer and it does not depend on any specific + storage device. You need to provide a low level disk I/O module written to + control the storage device that attached to the target system. + diff --git a/Project/GateWay/source/Module/FatFS/source/diskio.c b/Project/GateWay/source/Module/FatFS/source/diskio.c new file mode 100644 index 0000000..f6ad38a --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/source/diskio.c @@ -0,0 +1,233 @@ +/*-----------------------------------------------------------------------*/ +/* Low level disk I/O module SKELETON for FatFs (C)ChaN, 2019 */ +/*-----------------------------------------------------------------------*/ +/* If a working storage control module is available, it should be */ +/* attached to the FatFs via a glue function rather than modifying it. */ +/* This is an example of glue functions to attach various exsisting */ +/* storage control modules to the FatFs module with a defined API. */ +/*-----------------------------------------------------------------------*/ + +#include "ff.h" /* Obtains integer types */ +#include "diskio.h" /* Declarations of disk functions */ +#include "sd_diskio.h" + +/* Definitions of physical drive number for each drive */ +#define DEV_RAM 0 /* Example: Map Ramdisk to physical drive 0 */ +#define DEV_MMC 1 /* Example: Map MMC/SD card to physical drive 1 */ +#define DEV_USB 2 /* Example: Map USB MSD to physical drive 2 */ + + +/*-----------------------------------------------------------------------*/ +/* Get Drive Status */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_status ( + BYTE pdrv /* Physical drive nmuber to identify the drive */ +) +{ + DSTATUS stat = STA_NOINIT; + int result; + + switch (pdrv) { + case DEV_RAM : + //result = RAM_disk_status(); + // translate the reslut code here + + return stat; + + case DEV_MMC : + result = SD_Status(pdrv); + + // translate the reslut code here + + return result; + + case DEV_USB : + //result = USB_disk_status(); + + // translate the reslut code here + + return stat; + } + return STA_NOINIT; +} + + + +/*-----------------------------------------------------------------------*/ +/* Inidialize a Drive */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_initialize ( + BYTE pdrv /* Physical drive nmuber to identify the drive */ +) +{ + DSTATUS stat; +// int result; + + switch (pdrv) { + case DEV_RAM : + //result = RAM_disk_initialize(); + + // translate the reslut code here + + return stat; + + case DEV_MMC : + stat = SD_Initialize(pdrv); + + // translate the reslut code here + + return stat; + + case DEV_USB : + //result = USB_disk_initialize(); + + // translate the reslut code here + + return stat; + } + return STA_NOINIT; +} + + + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_read ( + BYTE pdrv, /* Physical drive nmuber to identify the drive */ + BYTE *buff, /* Data buffer to store read data */ + LBA_t sector, /* Start sector in LBA */ + UINT count /* Number of sectors to read */ +) +{ + DRESULT res; + //int result; + + switch (pdrv) { + case DEV_RAM : + // translate the arguments here + + //result = RAM_disk_read(buff, sector, count); + + // translate the reslut code here + + return res; + + case DEV_MMC : + // translate the arguments here + + res = SD_Read(pdrv, buff, sector, count); + + // translate the reslut code here + + return res; + + case DEV_USB : + // translate the arguments here + + //result = USB_disk_read(buff, sector, count); + + // translate the reslut code here + + return res; + } + + return RES_PARERR; +} + + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ +/*-----------------------------------------------------------------------*/ + +#if FF_FS_READONLY == 0 + +DRESULT disk_write ( + BYTE pdrv, /* Physical drive nmuber to identify the drive */ + const BYTE *buff, /* Data to be written */ + LBA_t sector, /* Start sector in LBA */ + UINT count /* Number of sectors to write */ +) +{ + DRESULT res; + //int result; + + switch (pdrv) { + case DEV_RAM : + // translate the arguments here + + //result = RAM_disk_write(buff, sector, count); + + // translate the reslut code here + + return res; + + case DEV_MMC : + // translate the arguments here + + res = SD_Write(pdrv, buff, sector, count); + + // translate the reslut code here + + return res; + + case DEV_USB : + // translate the arguments here + + //result = USB_disk_write(buff, sector, count); + + // translate the reslut code here + + return res; + } + + return RES_PARERR; +} + +#endif + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_ioctl ( + BYTE pdrv, /* Physical drive nmuber (0..) */ + BYTE cmd, /* Control code */ + void *buff /* Buffer to send/receive control data */ +) +{ + DRESULT res; + //int result; + + switch (pdrv) { + case DEV_RAM : + + // Process of the command for the RAM drive + + return res; + + case DEV_MMC : + + // Process of the command for the MMC/SD card + res = SD_Ioctl(pdrv, cmd, buff); + return res; + + case DEV_USB : + + // Process of the command the USB drive + + return res; + } + + return RES_PARERR; +} + +__WEAKDEF DWORD get_fattime (void) +{ + return 0; +} diff --git a/Project/GateWay/source/Module/FatFS/source/diskio.h b/Project/GateWay/source/Module/FatFS/source/diskio.h new file mode 100644 index 0000000..e4ead78 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/source/diskio.h @@ -0,0 +1,77 @@ +/*-----------------------------------------------------------------------/ +/ Low level disk interface modlue include file (C)ChaN, 2019 / +/-----------------------------------------------------------------------*/ + +#ifndef _DISKIO_DEFINED +#define _DISKIO_DEFINED + +#ifdef __cplusplus +extern "C" { +#endif + +/* Status of Disk Functions */ +typedef BYTE DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + + +DSTATUS disk_initialize (BYTE pdrv); +DSTATUS disk_status (BYTE pdrv); +DRESULT disk_read (BYTE pdrv, BYTE* buff, LBA_t sector, UINT count); +DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count); +DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff); + + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl fucntion */ + +/* Generic command (Used by FatFs) */ +#define CTRL_SYNC 0 /* Complete pending write process (needed at FF_FS_READONLY == 0) */ +#define GET_SECTOR_COUNT 1 /* Get media size (needed at FF_USE_MKFS == 1) */ +#define GET_SECTOR_SIZE 2 /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */ +#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at FF_USE_MKFS == 1) */ +#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */ + +/* Generic command (Not used by FatFs) */ +#define CTRL_POWER 5 /* Get/Set power status */ +#define CTRL_LOCK 6 /* Lock/Unlock media removal */ +#define CTRL_EJECT 7 /* Eject media */ +#define CTRL_FORMAT 8 /* Create physical format on the media */ + +/* MMC/SDC specific ioctl command */ +#define MMC_GET_TYPE 10 /* Get card type */ +#define MMC_GET_CSD 11 /* Get CSD */ +#define MMC_GET_CID 12 /* Get CID */ +#define MMC_GET_OCR 13 /* Get OCR */ +#define MMC_GET_SDSTAT 14 /* Get SD status */ +#define ISDIO_READ 55 /* Read data form SD iSDIO register */ +#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */ +#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */ + +/* ATA/CF specific ioctl command */ +#define ATA_GET_REV 20 /* Get F/W revision */ +#define ATA_GET_MODEL 21 /* Get model name */ +#define ATA_GET_SN 22 /* Get serial number */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Project/GateWay/source/Module/FatFS/source/ff.c b/Project/GateWay/source/Module/FatFS/source/ff.c new file mode 100644 index 0000000..cf00c42 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/source/ff.c @@ -0,0 +1,7085 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - Generic FAT Filesystem Module R0.15 w/patch1 / +/-----------------------------------------------------------------------------/ +/ +/ Copyright (C) 2022, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: +/ +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +/ +/----------------------------------------------------------------------------*/ + + +#include +#include "ff.h" /* Declarations of FatFs API */ +#include "diskio.h" /* Declarations of device I/O functions */ +#include "bsp.h" + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ + +#if FF_DEFINED != 80286 /* Revision ID */ +#error Wrong include file (ff.h). +#endif + + +/* Limits and boundaries */ +#define MAX_DIR 0x200000 /* Max size of FAT directory */ +#define MAX_DIR_EX 0x10000000 /* Max size of exFAT directory */ +#define MAX_FAT12 0xFF5 /* Max FAT12 clusters (differs from specs, but right for real DOS/Windows behavior) */ +#define MAX_FAT16 0xFFF5 /* Max FAT16 clusters (differs from specs, but right for real DOS/Windows behavior) */ +#define MAX_FAT32 0x0FFFFFF5 /* Max FAT32 clusters (not specified, practical limit) */ +#define MAX_EXFAT 0x7FFFFFFD /* Max exFAT clusters (differs from specs, implementation limit) */ + + +/* Character code support macros */ +#define IsUpper(c) ((c) >= 'A' && (c) <= 'Z') +#define IsLower(c) ((c) >= 'a' && (c) <= 'z') +#define IsDigit(c) ((c) >= '0' && (c) <= '9') +#define IsSeparator(c) ((c) == '/' || (c) == '\\') +#define IsTerminator(c) ((UINT)(c) < (FF_USE_LFN ? ' ' : '!')) +#define IsSurrogate(c) ((c) >= 0xD800 && (c) <= 0xDFFF) +#define IsSurrogateH(c) ((c) >= 0xD800 && (c) <= 0xDBFF) +#define IsSurrogateL(c) ((c) >= 0xDC00 && (c) <= 0xDFFF) + + +/* Additional file access control and file status flags for internal use */ +#define FA_SEEKEND 0x20 /* Seek to end of the file on file open */ +#define FA_MODIFIED 0x40 /* File has been modified */ +#define FA_DIRTY 0x80 /* FIL.buf[] needs to be written-back */ + + +/* Additional file attribute bits for internal use */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_MASK 0x3F /* Mask of defined bits in FAT */ +#define AM_MASKX 0x37 /* Mask of defined bits in exFAT */ + + +/* Name status flags in fn[11] */ +#define NSFLAG 11 /* Index of the name status byte */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ +#define NS_NOLFN 0x40 /* Do not find LFN */ +#define NS_NONAME 0x80 /* Not followed */ + + +/* exFAT directory entry types */ +#define ET_BITMAP 0x81 /* Allocation bitmap */ +#define ET_UPCASE 0x82 /* Up-case table */ +#define ET_VLABEL 0x83 /* Volume label */ +#define ET_FILEDIR 0x85 /* File and directory */ +#define ET_STREAM 0xC0 /* Stream extension */ +#define ET_FILENAME 0xC1 /* Name extension */ + + +/* FatFs refers the FAT structure as simple byte array instead of structure member +/ because the C structure is not binary compatible between different platforms */ + +#define BS_JmpBoot 0 /* x86 jump instruction (3-byte) */ +#define BS_OEMName 3 /* OEM name (8-byte) */ +#define BPB_BytsPerSec 11 /* Sector size [byte] (WORD) */ +#define BPB_SecPerClus 13 /* Cluster size [sector] (BYTE) */ +#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (WORD) */ +#define BPB_NumFATs 16 /* Number of FATs (BYTE) */ +#define BPB_RootEntCnt 17 /* Size of root directory area for FAT [entry] (WORD) */ +#define BPB_TotSec16 19 /* Volume size (16-bit) [sector] (WORD) */ +#define BPB_Media 21 /* Media descriptor byte (BYTE) */ +#define BPB_FATSz16 22 /* FAT size (16-bit) [sector] (WORD) */ +#define BPB_SecPerTrk 24 /* Number of sectors per track for int13h [sector] (WORD) */ +#define BPB_NumHeads 26 /* Number of heads for int13h (WORD) */ +#define BPB_HiddSec 28 /* Volume offset from top of the drive (DWORD) */ +#define BPB_TotSec32 32 /* Volume size (32-bit) [sector] (DWORD) */ +#define BS_DrvNum 36 /* Physical drive number for int13h (BYTE) */ +#define BS_NTres 37 /* WindowsNT error flag (BYTE) */ +#define BS_BootSig 38 /* Extended boot signature (BYTE) */ +#define BS_VolID 39 /* Volume serial number (DWORD) */ +#define BS_VolLab 43 /* Volume label string (8-byte) */ +#define BS_FilSysType 54 /* Filesystem type string (8-byte) */ +#define BS_BootCode 62 /* Boot code (448-byte) */ +#define BS_55AA 510 /* Signature word (WORD) */ + +#define BPB_FATSz32 36 /* FAT32: FAT size [sector] (DWORD) */ +#define BPB_ExtFlags32 40 /* FAT32: Extended flags (WORD) */ +#define BPB_FSVer32 42 /* FAT32: Filesystem version (WORD) */ +#define BPB_RootClus32 44 /* FAT32: Root directory cluster (DWORD) */ +#define BPB_FSInfo32 48 /* FAT32: Offset of FSINFO sector (WORD) */ +#define BPB_BkBootSec32 50 /* FAT32: Offset of backup boot sector (WORD) */ +#define BS_DrvNum32 64 /* FAT32: Physical drive number for int13h (BYTE) */ +#define BS_NTres32 65 /* FAT32: Error flag (BYTE) */ +#define BS_BootSig32 66 /* FAT32: Extended boot signature (BYTE) */ +#define BS_VolID32 67 /* FAT32: Volume serial number (DWORD) */ +#define BS_VolLab32 71 /* FAT32: Volume label string (8-byte) */ +#define BS_FilSysType32 82 /* FAT32: Filesystem type string (8-byte) */ +#define BS_BootCode32 90 /* FAT32: Boot code (420-byte) */ + +#define BPB_ZeroedEx 11 /* exFAT: MBZ field (53-byte) */ +#define BPB_VolOfsEx 64 /* exFAT: Volume offset from top of the drive [sector] (QWORD) */ +#define BPB_TotSecEx 72 /* exFAT: Volume size [sector] (QWORD) */ +#define BPB_FatOfsEx 80 /* exFAT: FAT offset from top of the volume [sector] (DWORD) */ +#define BPB_FatSzEx 84 /* exFAT: FAT size [sector] (DWORD) */ +#define BPB_DataOfsEx 88 /* exFAT: Data offset from top of the volume [sector] (DWORD) */ +#define BPB_NumClusEx 92 /* exFAT: Number of clusters (DWORD) */ +#define BPB_RootClusEx 96 /* exFAT: Root directory start cluster (DWORD) */ +#define BPB_VolIDEx 100 /* exFAT: Volume serial number (DWORD) */ +#define BPB_FSVerEx 104 /* exFAT: Filesystem version (WORD) */ +#define BPB_VolFlagEx 106 /* exFAT: Volume flags (WORD) */ +#define BPB_BytsPerSecEx 108 /* exFAT: Log2 of sector size in unit of byte (BYTE) */ +#define BPB_SecPerClusEx 109 /* exFAT: Log2 of cluster size in unit of sector (BYTE) */ +#define BPB_NumFATsEx 110 /* exFAT: Number of FATs (BYTE) */ +#define BPB_DrvNumEx 111 /* exFAT: Physical drive number for int13h (BYTE) */ +#define BPB_PercInUseEx 112 /* exFAT: Percent in use (BYTE) */ +#define BPB_RsvdEx 113 /* exFAT: Reserved (7-byte) */ +#define BS_BootCodeEx 120 /* exFAT: Boot code (390-byte) */ + +#define DIR_Name 0 /* Short file name (11-byte) */ +#define DIR_Attr 11 /* Attribute (BYTE) */ +#define DIR_NTres 12 /* Lower case flag (BYTE) */ +#define DIR_CrtTime10 13 /* Created time sub-second (BYTE) */ +#define DIR_CrtTime 14 /* Created time (DWORD) */ +#define DIR_LstAccDate 18 /* Last accessed date (WORD) */ +#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (WORD) */ +#define DIR_ModTime 22 /* Modified time (DWORD) */ +#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (WORD) */ +#define DIR_FileSize 28 /* File size (DWORD) */ +#define LDIR_Ord 0 /* LFN: LFN order and LLE flag (BYTE) */ +#define LDIR_Attr 11 /* LFN: LFN attribute (BYTE) */ +#define LDIR_Type 12 /* LFN: Entry type (BYTE) */ +#define LDIR_Chksum 13 /* LFN: Checksum of the SFN (BYTE) */ +#define LDIR_FstClusLO 26 /* LFN: MBZ field (WORD) */ +#define XDIR_Type 0 /* exFAT: Type of exFAT directory entry (BYTE) */ +#define XDIR_NumLabel 1 /* exFAT: Number of volume label characters (BYTE) */ +#define XDIR_Label 2 /* exFAT: Volume label (11-WORD) */ +#define XDIR_CaseSum 4 /* exFAT: Sum of case conversion table (DWORD) */ +#define XDIR_NumSec 1 /* exFAT: Number of secondary entries (BYTE) */ +#define XDIR_SetSum 2 /* exFAT: Sum of the set of directory entries (WORD) */ +#define XDIR_Attr 4 /* exFAT: File attribute (WORD) */ +#define XDIR_CrtTime 8 /* exFAT: Created time (DWORD) */ +#define XDIR_ModTime 12 /* exFAT: Modified time (DWORD) */ +#define XDIR_AccTime 16 /* exFAT: Last accessed time (DWORD) */ +#define XDIR_CrtTime10 20 /* exFAT: Created time subsecond (BYTE) */ +#define XDIR_ModTime10 21 /* exFAT: Modified time subsecond (BYTE) */ +#define XDIR_CrtTZ 22 /* exFAT: Created timezone (BYTE) */ +#define XDIR_ModTZ 23 /* exFAT: Modified timezone (BYTE) */ +#define XDIR_AccTZ 24 /* exFAT: Last accessed timezone (BYTE) */ +#define XDIR_GenFlags 33 /* exFAT: General secondary flags (BYTE) */ +#define XDIR_NumName 35 /* exFAT: Number of file name characters (BYTE) */ +#define XDIR_NameHash 36 /* exFAT: Hash of file name (WORD) */ +#define XDIR_ValidFileSize 40 /* exFAT: Valid file size (QWORD) */ +#define XDIR_FstClus 52 /* exFAT: First cluster of the file data (DWORD) */ +#define XDIR_FileSize 56 /* exFAT: File/Directory size (QWORD) */ + +#define SZDIRE 32 /* Size of a directory entry */ +#define DDEM 0xE5 /* Deleted directory entry mark set to DIR_Name[0] */ +#define RDDEM 0x05 /* Replacement of the character collides with DDEM */ +#define LLEF 0x40 /* Last long entry flag in LDIR_Ord */ + +#define FSI_LeadSig 0 /* FAT32 FSI: Leading signature (DWORD) */ +#define FSI_StrucSig 484 /* FAT32 FSI: Structure signature (DWORD) */ +#define FSI_Free_Count 488 /* FAT32 FSI: Number of free clusters (DWORD) */ +#define FSI_Nxt_Free 492 /* FAT32 FSI: Last allocated cluster (DWORD) */ + +#define MBR_Table 446 /* MBR: Offset of partition table in the MBR */ +#define SZ_PTE 16 /* MBR: Size of a partition table entry */ +#define PTE_Boot 0 /* MBR PTE: Boot indicator */ +#define PTE_StHead 1 /* MBR PTE: Start head */ +#define PTE_StSec 2 /* MBR PTE: Start sector */ +#define PTE_StCyl 3 /* MBR PTE: Start cylinder */ +#define PTE_System 4 /* MBR PTE: System ID */ +#define PTE_EdHead 5 /* MBR PTE: End head */ +#define PTE_EdSec 6 /* MBR PTE: End sector */ +#define PTE_EdCyl 7 /* MBR PTE: End cylinder */ +#define PTE_StLba 8 /* MBR PTE: Start in LBA */ +#define PTE_SizLba 12 /* MBR PTE: Size in LBA */ + +#define GPTH_Sign 0 /* GPT HDR: Signature (8-byte) */ +#define GPTH_Rev 8 /* GPT HDR: Revision (DWORD) */ +#define GPTH_Size 12 /* GPT HDR: Header size (DWORD) */ +#define GPTH_Bcc 16 /* GPT HDR: Header BCC (DWORD) */ +#define GPTH_CurLba 24 /* GPT HDR: This header LBA (QWORD) */ +#define GPTH_BakLba 32 /* GPT HDR: Another header LBA (QWORD) */ +#define GPTH_FstLba 40 /* GPT HDR: First LBA for partition data (QWORD) */ +#define GPTH_LstLba 48 /* GPT HDR: Last LBA for partition data (QWORD) */ +#define GPTH_DskGuid 56 /* GPT HDR: Disk GUID (16-byte) */ +#define GPTH_PtOfs 72 /* GPT HDR: Partition table LBA (QWORD) */ +#define GPTH_PtNum 80 /* GPT HDR: Number of table entries (DWORD) */ +#define GPTH_PteSize 84 /* GPT HDR: Size of table entry (DWORD) */ +#define GPTH_PtBcc 88 /* GPT HDR: Partition table BCC (DWORD) */ +#define SZ_GPTE 128 /* GPT PTE: Size of partition table entry */ +#define GPTE_PtGuid 0 /* GPT PTE: Partition type GUID (16-byte) */ +#define GPTE_UpGuid 16 /* GPT PTE: Partition unique GUID (16-byte) */ +#define GPTE_FstLba 32 /* GPT PTE: First LBA of partition (QWORD) */ +#define GPTE_LstLba 40 /* GPT PTE: Last LBA of partition (QWORD) */ +#define GPTE_Flags 48 /* GPT PTE: Partition flags (QWORD) */ +#define GPTE_Name 56 /* GPT PTE: Partition name */ + + +/* Post process on fatal error in the file operations */ +#define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); } + + +/* Re-entrancy related */ +#if FF_FS_REENTRANT +#if FF_USE_LFN == 1 +#error Static LFN work area cannot be used in thread-safe configuration +#endif +#define LEAVE_FF(fs, res) { unlock_volume(fs, res); return res; } +#else +#define LEAVE_FF(fs, res) return res +#endif + + +/* Definitions of logical drive - physical location conversion */ +#if FF_MULTI_PARTITION +#define LD2PD(vol) VolToPart[vol].pd /* Get physical drive number */ +#define LD2PT(vol) VolToPart[vol].pt /* Get partition number (0:auto search, 1..:forced partition number) */ +#else +#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is associated with the same physical drive number */ +#define LD2PT(vol) 0 /* Auto partition search */ +#endif + + +/* Definitions of sector size */ +#if (FF_MAX_SS < FF_MIN_SS) || (FF_MAX_SS != 512 && FF_MAX_SS != 1024 && FF_MAX_SS != 2048 && FF_MAX_SS != 4096) || (FF_MIN_SS != 512 && FF_MIN_SS != 1024 && FF_MIN_SS != 2048 && FF_MIN_SS != 4096) +#error Wrong sector size configuration +#endif +#if FF_MAX_SS == FF_MIN_SS +#define SS(fs) ((UINT)FF_MAX_SS) /* Fixed sector size */ +#else +#define SS(fs) ((fs)->ssize) /* Variable sector size */ +#endif + + +/* Timestamp */ +#if FF_FS_NORTC == 1 +#if FF_NORTC_YEAR < 1980 || FF_NORTC_YEAR > 2107 || FF_NORTC_MON < 1 || FF_NORTC_MON > 12 || FF_NORTC_MDAY < 1 || FF_NORTC_MDAY > 31 +#error Invalid FF_FS_NORTC settings +#endif +#define GET_FATTIME() ((DWORD)(FF_NORTC_YEAR - 1980) << 25 | (DWORD)FF_NORTC_MON << 21 | (DWORD)FF_NORTC_MDAY << 16) +#else +#define GET_FATTIME() get_fattime() +#endif + + +/* File lock controls */ +#if FF_FS_LOCK +#if FF_FS_READONLY +#error FF_FS_LOCK must be 0 at read-only configuration +#endif +typedef struct { + FATFS* fs; /* Object ID 1, volume (NULL:blank entry) */ + DWORD clu; /* Object ID 2, containing directory (0:root) */ + DWORD ofs; /* Object ID 3, offset in the directory */ + UINT ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ +} FILESEM; +#endif + + +/* SBCS up-case tables (\x80-\xFF) */ +#define TBL_CT437 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT720 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT737 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT771 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF} +#define TBL_CT775 {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT850 {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \ + 0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \ + 0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT852 {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} +#define TBL_CT855 {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \ + 0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \ + 0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT857 {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT860 {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \ + 0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT861 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT862 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT863 {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \ + 0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \ + 0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT864 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT865 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT866 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT869 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \ + 0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \ + 0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \ + 0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF} + + +/* DBCS code range |----- 1st byte -----| |----------- 2nd byte -----------| */ +/* <------> <------> <------> <------> <------> */ +#define TBL_DC932 {0x81, 0x9F, 0xE0, 0xFC, 0x40, 0x7E, 0x80, 0xFC, 0x00, 0x00} +#define TBL_DC936 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0x80, 0xFE, 0x00, 0x00} +#define TBL_DC949 {0x81, 0xFE, 0x00, 0x00, 0x41, 0x5A, 0x61, 0x7A, 0x81, 0xFE} +#define TBL_DC950 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0xA1, 0xFE, 0x00, 0x00} + + +/* Macros for table definitions */ +#define MERGE_2STR(a, b) a ## b +#define MKCVTBL(hd, cp) MERGE_2STR(hd, cp) + + + + +/*-------------------------------------------------------------------------- + + Module Private Work Area + +---------------------------------------------------------------------------*/ +/* Remark: Variables defined here without initial value shall be guaranteed +/ zero/null at start-up. If not, the linker option or start-up routine is +/ not compliance with C standard. */ + +/*--------------------------------*/ +/* File/Volume controls */ +/*--------------------------------*/ + +#if FF_VOLUMES < 1 || FF_VOLUMES > 10 +#error Wrong FF_VOLUMES setting +#endif +static FATFS *FatFs[FF_VOLUMES]; /* Pointer to the filesystem objects (logical drives) */ +static WORD Fsid; /* Filesystem mount ID */ + +#if FF_FS_RPATH != 0 +static BYTE CurrVol; /* Current drive set by f_chdrive() */ +#endif + +#if FF_FS_LOCK != 0 +static FILESEM Files[FF_FS_LOCK]; /* Open object lock semaphores */ +#if FF_FS_REENTRANT +static BYTE SysLock; /* System lock flag (0:no mutex, 1:unlocked, 2:locked) */ +#endif +#endif + +#if FF_STR_VOLUME_ID +#ifdef FF_VOLUME_STRS +static const char *const VolumeStr[FF_VOLUMES] = {FF_VOLUME_STRS}; /* Pre-defined volume ID */ +#endif +#endif + +#if FF_LBA64 +#if FF_MIN_GPT > 0x100000000 +#error Wrong FF_MIN_GPT setting +#endif +static const BYTE GUID_MS_Basic[16] = {0xA2,0xA0,0xD0,0xEB,0xE5,0xB9,0x33,0x44,0x87,0xC0,0x68,0xB6,0xB7,0x26,0x99,0xC7}; +#endif + + + +/*--------------------------------*/ +/* LFN/Directory working buffer */ +/*--------------------------------*/ + +#if FF_USE_LFN == 0 /* Non-LFN configuration */ +#if FF_FS_EXFAT +#error LFN must be enabled when enable exFAT +#endif +#define DEF_NAMBUF +#define INIT_NAMBUF(fs) +#define FREE_NAMBUF() +#define LEAVE_MKFS(res) return res + +#else /* LFN configurations */ +#if FF_MAX_LFN < 12 || FF_MAX_LFN > 255 +#error Wrong setting of FF_MAX_LFN +#endif +#if FF_LFN_BUF < FF_SFN_BUF || FF_SFN_BUF < 12 +#error Wrong setting of FF_LFN_BUF or FF_SFN_BUF +#endif +#if FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3 +#error Wrong setting of FF_LFN_UNICODE +#endif +static const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* FAT: Offset of LFN characters in the directory entry */ +#define MAXDIRB(nc) ((nc + 44U) / 15 * SZDIRE) /* exFAT: Size of directory entry block scratchpad buffer needed for the name length */ + +#if FF_USE_LFN == 1 /* LFN enabled with static working buffer */ +#if FF_FS_EXFAT +static BYTE DirBuf[MAXDIRB(FF_MAX_LFN)]; /* Directory entry block scratchpad buffer */ +#endif +static WCHAR LfnBuf[FF_MAX_LFN + 1]; /* LFN working buffer */ +#define DEF_NAMBUF +#define INIT_NAMBUF(fs) +#define FREE_NAMBUF() +#define LEAVE_MKFS(res) return res + +#elif FF_USE_LFN == 2 /* LFN enabled with dynamic working buffer on the stack */ +#if FF_FS_EXFAT +#define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; BYTE dbuf[MAXDIRB(FF_MAX_LFN)]; /* LFN working buffer and directory entry block scratchpad buffer */ +#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; } +#define FREE_NAMBUF() +#else +#define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; /* LFN working buffer */ +#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; } +#define FREE_NAMBUF() +#endif +#define LEAVE_MKFS(res) return res + +#elif FF_USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */ +#if FF_FS_EXFAT +#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer and directory entry block scratchpad buffer */ +#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); } +#define FREE_NAMBUF() ff_memfree(lfn) +#else +#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer */ +#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; } +#define FREE_NAMBUF() ff_memfree(lfn) +#endif +#define LEAVE_MKFS(res) { if (!work) ff_memfree(buf); return res; } +#define MAX_MALLOC 0x8000 /* Must be >=FF_MAX_SS */ + +#else +#error Wrong setting of FF_USE_LFN + +#endif /* FF_USE_LFN == 1 */ +#endif /* FF_USE_LFN == 0 */ + + + +/*--------------------------------*/ +/* Code conversion tables */ +/*--------------------------------*/ + +#if FF_CODE_PAGE == 0 /* Run-time code page configuration */ +#define CODEPAGE CodePage +static WORD CodePage; /* Current code page */ +static const BYTE* ExCvt; /* Ptr to SBCS up-case table Ct???[] (null:not used) */ +static const BYTE* DbcTbl; /* Ptr to DBCS code range table Dc???[] (null:not used) */ + +static const BYTE Ct437[] = TBL_CT437; +static const BYTE Ct720[] = TBL_CT720; +static const BYTE Ct737[] = TBL_CT737; +static const BYTE Ct771[] = TBL_CT771; +static const BYTE Ct775[] = TBL_CT775; +static const BYTE Ct850[] = TBL_CT850; +static const BYTE Ct852[] = TBL_CT852; +static const BYTE Ct855[] = TBL_CT855; +static const BYTE Ct857[] = TBL_CT857; +static const BYTE Ct860[] = TBL_CT860; +static const BYTE Ct861[] = TBL_CT861; +static const BYTE Ct862[] = TBL_CT862; +static const BYTE Ct863[] = TBL_CT863; +static const BYTE Ct864[] = TBL_CT864; +static const BYTE Ct865[] = TBL_CT865; +static const BYTE Ct866[] = TBL_CT866; +static const BYTE Ct869[] = TBL_CT869; +static const BYTE Dc932[] = TBL_DC932; +static const BYTE Dc936[] = TBL_DC936; +static const BYTE Dc949[] = TBL_DC949; +static const BYTE Dc950[] = TBL_DC950; + +#elif FF_CODE_PAGE < 900 /* Static code page configuration (SBCS) */ +#define CODEPAGE FF_CODE_PAGE +static const BYTE ExCvt[] = MKCVTBL(TBL_CT, FF_CODE_PAGE); + +#else /* Static code page configuration (DBCS) */ +#define CODEPAGE FF_CODE_PAGE +static const BYTE DbcTbl[] = MKCVTBL(TBL_DC, FF_CODE_PAGE); + +#endif + + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* Load/Store multi-byte word in the FAT structure */ +/*-----------------------------------------------------------------------*/ + +static WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */ +{ + WORD rv; + + rv = ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} + +static DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */ +{ + DWORD rv; + + rv = ptr[3]; + rv = rv << 8 | ptr[2]; + rv = rv << 8 | ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} + +#if FF_FS_EXFAT +static QWORD ld_qword (const BYTE* ptr) /* Load an 8-byte little-endian word */ +{ + QWORD rv; + + rv = ptr[7]; + rv = rv << 8 | ptr[6]; + rv = rv << 8 | ptr[5]; + rv = rv << 8 | ptr[4]; + rv = rv << 8 | ptr[3]; + rv = rv << 8 | ptr[2]; + rv = rv << 8 | ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} +#endif + +#if !FF_FS_READONLY +static void st_word (BYTE* ptr, WORD val) /* Store a 2-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} + +static void st_dword (BYTE* ptr, DWORD val) /* Store a 4-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} + +#if FF_FS_EXFAT +static void st_qword (BYTE* ptr, QWORD val) /* Store an 8-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} +#endif +#endif /* !FF_FS_READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* String functions */ +/*-----------------------------------------------------------------------*/ + +/* Test if the byte is DBC 1st byte */ +static int dbc_1st (BYTE c) +{ +#if FF_CODE_PAGE == 0 /* Variable code page */ + if (DbcTbl && c >= DbcTbl[0]) { + if (c <= DbcTbl[1]) return 1; /* 1st byte range 1 */ + if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; /* 1st byte range 2 */ + } +#elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */ + if (c >= DbcTbl[0]) { + if (c <= DbcTbl[1]) return 1; + if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; + } +#else /* SBCS fixed code page */ + if (c != 0) return 0; /* Always false */ +#endif + return 0; +} + + +/* Test if the byte is DBC 2nd byte */ +static int dbc_2nd (BYTE c) +{ +#if FF_CODE_PAGE == 0 /* Variable code page */ + if (DbcTbl && c >= DbcTbl[4]) { + if (c <= DbcTbl[5]) return 1; /* 2nd byte range 1 */ + if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; /* 2nd byte range 2 */ + if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; /* 2nd byte range 3 */ + } +#elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */ + if (c >= DbcTbl[4]) { + if (c <= DbcTbl[5]) return 1; + if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; + if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; + } +#else /* SBCS fixed code page */ + if (c != 0) return 0; /* Always false */ +#endif + return 0; +} + + +#if FF_USE_LFN + +/* Get a Unicode code point from the TCHAR string in defined API encodeing */ +static DWORD tchar2uni ( /* Returns a character in UTF-16 encoding (>=0x10000 on surrogate pair, 0xFFFFFFFF on decode error) */ + const TCHAR** str /* Pointer to pointer to TCHAR string in configured encoding */ +) +{ + DWORD uc; + const TCHAR *p = *str; + +#if FF_LFN_UNICODE == 1 /* UTF-16 input */ + WCHAR wc; + + uc = *p++; /* Get a unit */ + if (IsSurrogate(uc)) { /* Surrogate? */ + wc = *p++; /* Get low surrogate */ + if (!IsSurrogateH(uc) || !IsSurrogateL(wc)) return 0xFFFFFFFF; /* Wrong surrogate? */ + uc = uc << 16 | wc; + } + +#elif FF_LFN_UNICODE == 2 /* UTF-8 input */ + BYTE b; + int nf; + + uc = (BYTE)*p++; /* Get an encoding unit */ + if (uc & 0x80) { /* Multiple byte code? */ + if ((uc & 0xE0) == 0xC0) { /* 2-byte sequence? */ + uc &= 0x1F; nf = 1; + } else if ((uc & 0xF0) == 0xE0) { /* 3-byte sequence? */ + uc &= 0x0F; nf = 2; + } else if ((uc & 0xF8) == 0xF0) { /* 4-byte sequence? */ + uc &= 0x07; nf = 3; + } else { /* Wrong sequence */ + return 0xFFFFFFFF; + } + do { /* Get trailing bytes */ + b = (BYTE)*p++; + if ((b & 0xC0) != 0x80) return 0xFFFFFFFF; /* Wrong sequence? */ + uc = uc << 6 | (b & 0x3F); + } while (--nf != 0); + if (uc < 0x80 || IsSurrogate(uc) || uc >= 0x110000) return 0xFFFFFFFF; /* Wrong code? */ + if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ + } + +#elif FF_LFN_UNICODE == 3 /* UTF-32 input */ + uc = (TCHAR)*p++; /* Get a unit */ + if (uc >= 0x110000 || IsSurrogate(uc)) return 0xFFFFFFFF; /* Wrong code? */ + if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ + +#else /* ANSI/OEM input */ + BYTE b; + WCHAR wc; + + wc = (BYTE)*p++; /* Get a byte */ + if (dbc_1st((BYTE)wc)) { /* Is it a DBC 1st byte? */ + b = (BYTE)*p++; /* Get 2nd byte */ + if (!dbc_2nd(b)) return 0xFFFFFFFF; /* Invalid code? */ + wc = (wc << 8) + b; /* Make a DBC */ + } + if (wc != 0) { + wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM ==> Unicode */ + if (wc == 0) return 0xFFFFFFFF; /* Invalid code? */ + } + uc = wc; + +#endif + *str = p; /* Next read pointer */ + return uc; +} + + +/* Store a Unicode char in defined API encoding */ +static UINT put_utf ( /* Returns number of encoding units written (0:buffer overflow or wrong encoding) */ + DWORD chr, /* UTF-16 encoded character (Surrogate pair if >=0x10000) */ + TCHAR* buf, /* Output buffer */ + UINT szb /* Size of the buffer */ +) +{ +#if FF_LFN_UNICODE == 1 /* UTF-16 output */ + WCHAR hs, wc; + + hs = (WCHAR)(chr >> 16); + wc = (WCHAR)chr; + if (hs == 0) { /* Single encoding unit? */ + if (szb < 1 || IsSurrogate(wc)) return 0; /* Buffer overflow or wrong code? */ + *buf = wc; + return 1; + } + if (szb < 2 || !IsSurrogateH(hs) || !IsSurrogateL(wc)) return 0; /* Buffer overflow or wrong surrogate? */ + *buf++ = hs; + *buf++ = wc; + return 2; + +#elif FF_LFN_UNICODE == 2 /* UTF-8 output */ + DWORD hc; + + if (chr < 0x80) { /* Single byte code? */ + if (szb < 1) return 0; /* Buffer overflow? */ + *buf = (TCHAR)chr; + return 1; + } + if (chr < 0x800) { /* 2-byte sequence? */ + if (szb < 2) return 0; /* Buffer overflow? */ + *buf++ = (TCHAR)(0xC0 | (chr >> 6 & 0x1F)); + *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); + return 2; + } + if (chr < 0x10000) { /* 3-byte sequence? */ + if (szb < 3 || IsSurrogate(chr)) return 0; /* Buffer overflow or wrong code? */ + *buf++ = (TCHAR)(0xE0 | (chr >> 12 & 0x0F)); + *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F)); + *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); + return 3; + } + /* 4-byte sequence */ + if (szb < 4) return 0; /* Buffer overflow? */ + hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */ + chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */ + if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */ + chr = (hc | chr) + 0x10000; + *buf++ = (TCHAR)(0xF0 | (chr >> 18 & 0x07)); + *buf++ = (TCHAR)(0x80 | (chr >> 12 & 0x3F)); + *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F)); + *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); + return 4; + +#elif FF_LFN_UNICODE == 3 /* UTF-32 output */ + DWORD hc; + + if (szb < 1) return 0; /* Buffer overflow? */ + if (chr >= 0x10000) { /* Out of BMP? */ + hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */ + chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */ + if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */ + chr = (hc | chr) + 0x10000; + } + *buf++ = (TCHAR)chr; + return 1; + +#else /* ANSI/OEM output */ + WCHAR wc; + + wc = ff_uni2oem(chr, CODEPAGE); + if (wc >= 0x100) { /* Is this a DBC? */ + if (szb < 2) return 0; + *buf++ = (char)(wc >> 8); /* Store DBC 1st byte */ + *buf++ = (TCHAR)wc; /* Store DBC 2nd byte */ + return 2; + } + if (wc == 0 || szb < 1) return 0; /* Invalid char or buffer overflow? */ + *buf++ = (TCHAR)wc; /* Store the character */ + return 1; +#endif +} +#endif /* FF_USE_LFN */ + + +#if FF_FS_REENTRANT +/*-----------------------------------------------------------------------*/ +/* Request/Release grant to access the volume */ +/*-----------------------------------------------------------------------*/ + +static int lock_volume ( /* 1:Ok, 0:timeout */ + FATFS* fs, /* Filesystem object to lock */ + int syslock /* System lock required */ +) +{ + int rv; + + +#if FF_FS_LOCK + rv = ff_mutex_take(fs->ldrv); /* Lock the volume */ + if (rv && syslock) { /* System lock reqiered? */ + rv = ff_mutex_take(FF_VOLUMES); /* Lock the system */ + if (rv) { + SysLock = 2; /* System lock succeeded */ + } else { + ff_mutex_give(fs->ldrv); /* Failed system lock */ + } + } +#else + rv = syslock ? ff_mutex_take(fs->ldrv) : ff_mutex_take(fs->ldrv); /* Lock the volume (this is to prevent compiler warning) */ +#endif + return rv; +} + + +static void unlock_volume ( + FATFS* fs, /* Filesystem object */ + FRESULT res /* Result code to be returned */ +) +{ + if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) { +#if FF_FS_LOCK + if (SysLock == 2) { /* Is the system locked? */ + SysLock = 1; + ff_mutex_give(FF_VOLUMES); + } +#endif + ff_mutex_give(fs->ldrv); /* Unlock the volume */ + } +} + +#endif + + + +#if FF_FS_LOCK +/*-----------------------------------------------------------------------*/ +/* File shareing control functions */ +/*-----------------------------------------------------------------------*/ + +static FRESULT chk_share ( /* Check if the file can be accessed */ + DIR* dp, /* Directory object pointing the file to be checked */ + int acc /* Desired access type (0:Read mode open, 1:Write mode open, 2:Delete or rename) */ +) +{ + UINT i, be; + + /* Search open object table for the object */ + be = 0; + for (i = 0; i < FF_FS_LOCK; i++) { + if (Files[i].fs) { /* Existing entry */ + if (Files[i].fs == dp->obj.fs && /* Check if the object matches with an open object */ + Files[i].clu == dp->obj.sclust && + Files[i].ofs == dp->dptr) break; + } else { /* Blank entry */ + be = 1; + } + } + if (i == FF_FS_LOCK) { /* The object has not been opened */ + return (!be && acc != 2) ? FR_TOO_MANY_OPEN_FILES : FR_OK; /* Is there a blank entry for new object? */ + } + + /* The object was opened. Reject any open against writing file and all write mode open */ + return (acc != 0 || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; +} + + +static int enq_share (void) /* Check if an entry is available for a new object */ +{ + UINT i; + + for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ; /* Find a free entry */ + return (i == FF_FS_LOCK) ? 0 : 1; +} + + +static UINT inc_share ( /* Increment object open counter and returns its index (0:Internal error) */ + DIR* dp, /* Directory object pointing the file to register or increment */ + int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i; + + + for (i = 0; i < FF_FS_LOCK; i++) { /* Find the object */ + if (Files[i].fs == dp->obj.fs + && Files[i].clu == dp->obj.sclust + && Files[i].ofs == dp->dptr) break; + } + + if (i == FF_FS_LOCK) { /* Not opened. Register it as new. */ + for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ; /* Find a free entry */ + if (i == FF_FS_LOCK) return 0; /* No free entry to register (int err) */ + Files[i].fs = dp->obj.fs; + Files[i].clu = dp->obj.sclust; + Files[i].ofs = dp->dptr; + Files[i].ctr = 0; + } + + if (acc >= 1 && Files[i].ctr) return 0; /* Access violation (int err) */ + + Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ + + return i + 1; /* Index number origin from 1 */ +} + + +static FRESULT dec_share ( /* Decrement object open counter */ + UINT i /* Semaphore index (1..) */ +) +{ + UINT n; + FRESULT res; + + + if (--i < FF_FS_LOCK) { /* Index number origin from 0 */ + n = Files[i].ctr; + if (n == 0x100) n = 0; /* If write mode open, delete the object semaphore */ + if (n > 0) n--; /* Decrement read mode open count */ + Files[i].ctr = n; + if (n == 0) { /* Delete the object semaphore if open count becomes zero */ + Files[i].fs = 0; /* Free the entry << 1, there is a potential error in this process >>> */ + } + res = FR_OK; + } else { + res = FR_INT_ERR; /* Invalid index number */ + } + return res; +} + + +static void clear_share ( /* Clear all lock entries of the volume */ + FATFS* fs +) +{ + UINT i; + + for (i = 0; i < FF_FS_LOCK; i++) { + if (Files[i].fs == fs) Files[i].fs = 0; + } +} + +#endif /* FF_FS_LOCK */ + + + +/*-----------------------------------------------------------------------*/ +/* Move/Flush disk access window in the filesystem object */ +/*-----------------------------------------------------------------------*/ +#if !FF_FS_READONLY +static FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS* fs /* Filesystem object */ +) +{ + FRESULT res = FR_OK; + + + if (fs->wflag) { /* Is the disk access window dirty? */ + if (disk_write(fs->pdrv, fs->win, fs->winsect, 1) == RES_OK) { /* Write it back into the volume */ + fs->wflag = 0; /* Clear window dirty flag */ + if (fs->winsect - fs->fatbase < fs->fsize) { /* Is it in the 1st FAT? */ + if (fs->n_fats == 2) disk_write(fs->pdrv, fs->win, fs->winsect + fs->fsize, 1); /* Reflect it to 2nd FAT if needed */ + } + } else { + res = FR_DISK_ERR; + } + } + return res; +} +#endif + + +static FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS* fs, /* Filesystem object */ + LBA_t sect /* Sector LBA to make appearance in the fs->win[] */ +) +{ + FRESULT res = FR_OK; + + + if (sect != fs->winsect) { /* Window offset changed? */ +#if !FF_FS_READONLY + res = sync_window(fs); /* Flush the window */ +#endif + if (res == FR_OK) { /* Fill sector window with new data */ + if (disk_read(fs->pdrv, fs->win, sect, 1) != RES_OK) { + sect = (LBA_t)0 - 1; /* Invalidate window if read data is not valid */ + res = FR_DISK_ERR; + } + fs->winsect = sect; + } + } + return res; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Synchronize filesystem and data on the storage */ +/*-----------------------------------------------------------------------*/ + +static FRESULT sync_fs ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS* fs /* Filesystem object */ +) +{ + FRESULT res; + + + res = sync_window(fs); + if (res == FR_OK) { + if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { /* FAT32: Update FSInfo sector if needed */ + /* Create FSInfo structure */ + memset(fs->win, 0, sizeof fs->win); + st_word(fs->win + BS_55AA, 0xAA55); /* Boot signature */ + st_dword(fs->win + FSI_LeadSig, 0x41615252); /* Leading signature */ + st_dword(fs->win + FSI_StrucSig, 0x61417272); /* Structure signature */ + st_dword(fs->win + FSI_Free_Count, fs->free_clst); /* Number of free clusters */ + st_dword(fs->win + FSI_Nxt_Free, fs->last_clst); /* Last allocated culuster */ + fs->winsect = fs->volbase + 1; /* Write it into the FSInfo sector (Next to VBR) */ + disk_write(fs->pdrv, fs->win, fs->winsect, 1); + fs->fsi_flag = 0; + } + /* Make sure that no pending write process in the lower layer */ + if (disk_ioctl(fs->pdrv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR; + } + + return res; +} + +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Get physical sector number from cluster number */ +/*-----------------------------------------------------------------------*/ + +static LBA_t clst2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */ + FATFS* fs, /* Filesystem object */ + DWORD clst /* Cluster# to be converted */ +) +{ + clst -= 2; /* Cluster number is origin from 2 */ + if (clst >= fs->n_fatent - 2) return 0; /* Is it invalid cluster number? */ + return fs->database + (LBA_t)fs->csize * clst; /* Start sector number of the cluster */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Read value of an FAT entry */ +/*-----------------------------------------------------------------------*/ + +static DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */ + FFOBJID* obj, /* Corresponding object */ + DWORD clst /* Cluster number to get the value */ +) +{ + UINT wc, bc; + DWORD val; + FATFS *fs = obj->fs; + + + if (clst < 2 || clst >= fs->n_fatent) { /* Check if in valid range */ + val = 1; /* Internal error */ + + } else { + val = 0xFFFFFFFF; /* Default value falls on disk error */ + + switch (fs->fs_type) { + case FS_FAT12 : + bc = (UINT)clst; bc += bc / 2; + if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + wc = fs->win[bc++ % SS(fs)]; /* Get 1st byte of the entry */ + if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + wc |= fs->win[bc % SS(fs)] << 8; /* Merge 2nd byte of the entry */ + val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); /* Adjust bit position */ + break; + + case FS_FAT16 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break; + val = ld_word(fs->win + clst * 2 % SS(fs)); /* Simple WORD array */ + break; + + case FS_FAT32 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; + val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; /* Simple DWORD array but mask out upper 4 bits */ + break; +#if FF_FS_EXFAT + case FS_EXFAT : + if ((obj->objsize != 0 && obj->sclust != 0) || obj->stat == 0) { /* Object except root dir must have valid data length */ + DWORD cofs = clst - obj->sclust; /* Offset from start cluster */ + DWORD clen = (DWORD)((LBA_t)((obj->objsize - 1) / SS(fs)) / fs->csize); /* Number of clusters - 1 */ + + if (obj->stat == 2 && cofs <= clen) { /* Is it a contiguous chain? */ + val = (cofs == clen) ? 0x7FFFFFFF : clst + 1; /* No data on the FAT, generate the value */ + break; + } + if (obj->stat == 3 && cofs < obj->n_cont) { /* Is it in the 1st fragment? */ + val = clst + 1; /* Generate the value */ + break; + } + if (obj->stat != 2) { /* Get value from FAT if FAT chain is valid */ + if (obj->n_frag != 0) { /* Is it on the growing edge? */ + val = 0x7FFFFFFF; /* Generate EOC */ + } else { + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; + val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF; + } + break; + } + } + val = 1; /* Internal error */ + break; +#endif + default: + val = 1; /* Internal error */ + } + } + + return val; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT access - Change value of an FAT entry */ +/*-----------------------------------------------------------------------*/ + +static FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */ + FATFS* fs, /* Corresponding filesystem object */ + DWORD clst, /* FAT index number (cluster number) to be changed */ + DWORD val /* New value to be set to the entry */ +) +{ + UINT bc; + BYTE *p; + FRESULT res = FR_INT_ERR; + + + if (clst >= 2 && clst < fs->n_fatent) { /* Check if in valid range */ + switch (fs->fs_type) { + case FS_FAT12: + bc = (UINT)clst; bc += bc / 2; /* bc: byte offset of the entry */ + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = fs->win + bc++ % SS(fs); + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; /* Update 1st byte */ + fs->wflag = 1; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = fs->win + bc % SS(fs); + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); /* Update 2nd byte */ + fs->wflag = 1; + break; + + case FS_FAT16: + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); + if (res != FR_OK) break; + st_word(fs->win + clst * 2 % SS(fs), (WORD)val); /* Simple WORD array */ + fs->wflag = 1; + break; + + case FS_FAT32: +#if FF_FS_EXFAT + case FS_EXFAT: +#endif + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); + if (res != FR_OK) break; + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { + val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000); + } + st_dword(fs->win + clst * 4 % SS(fs), val); + fs->wflag = 1; + break; + } + } + return res; +} + +#endif /* !FF_FS_READONLY */ + + + + +#if FF_FS_EXFAT && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* exFAT: Accessing FAT and Allocation Bitmap */ +/*-----------------------------------------------------------------------*/ + +/*--------------------------------------*/ +/* Find a contiguous free cluster block */ +/*--------------------------------------*/ + +static DWORD find_bitmap ( /* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */ + FATFS* fs, /* Filesystem object */ + DWORD clst, /* Cluster number to scan from */ + DWORD ncl /* Number of contiguous clusters to find (1..) */ +) +{ + BYTE bm, bv; + UINT i; + DWORD val, scl, ctr; + + + clst -= 2; /* The first bit in the bitmap corresponds to cluster #2 */ + if (clst >= fs->n_fatent - 2) clst = 0; + scl = val = clst; ctr = 0; + for (;;) { + if (move_window(fs, fs->bitbase + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF; + i = val / 8 % SS(fs); bm = 1 << (val % 8); + do { + do { + bv = fs->win[i] & bm; bm <<= 1; /* Get bit value */ + if (++val >= fs->n_fatent - 2) { /* Next cluster (with wrap-around) */ + val = 0; bm = 0; i = SS(fs); + } + if (bv == 0) { /* Is it a free cluster? */ + if (++ctr == ncl) return scl + 2; /* Check if run length is sufficient for required */ + } else { + scl = val; ctr = 0; /* Encountered a cluster in-use, restart to scan */ + } + if (val == clst) return 0; /* All cluster scanned? */ + } while (bm != 0); + bm = 1; + } while (++i < SS(fs)); + } +} + + +/*----------------------------------------*/ +/* Set/Clear a block of allocation bitmap */ +/*----------------------------------------*/ + +static FRESULT change_bitmap ( + FATFS* fs, /* Filesystem object */ + DWORD clst, /* Cluster number to change from */ + DWORD ncl, /* Number of clusters to be changed */ + int bv /* bit value to be set (0 or 1) */ +) +{ + BYTE bm; + UINT i; + LBA_t sect; + + + clst -= 2; /* The first bit corresponds to cluster #2 */ + sect = fs->bitbase + clst / 8 / SS(fs); /* Sector address */ + i = clst / 8 % SS(fs); /* Byte offset in the sector */ + bm = 1 << (clst % 8); /* Bit mask in the byte */ + for (;;) { + if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR; + do { + do { + if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR; /* Is the bit expected value? */ + fs->win[i] ^= bm; /* Flip the bit */ + fs->wflag = 1; + if (--ncl == 0) return FR_OK; /* All bits processed? */ + } while (bm <<= 1); /* Next bit */ + bm = 1; + } while (++i < SS(fs)); /* Next byte */ + i = 0; + } +} + + +/*---------------------------------------------*/ +/* Fill the first fragment of the FAT chain */ +/*---------------------------------------------*/ + +static FRESULT fill_first_frag ( + FFOBJID* obj /* Pointer to the corresponding object */ +) +{ + FRESULT res; + DWORD cl, n; + + + if (obj->stat == 3) { /* Has the object been changed 'fragmented' in this session? */ + for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) { /* Create cluster chain on the FAT */ + res = put_fat(obj->fs, cl, cl + 1); + if (res != FR_OK) return res; + } + obj->stat = 0; /* Change status 'FAT chain is valid' */ + } + return FR_OK; +} + + +/*---------------------------------------------*/ +/* Fill the last fragment of the FAT chain */ +/*---------------------------------------------*/ + +static FRESULT fill_last_frag ( + FFOBJID* obj, /* Pointer to the corresponding object */ + DWORD lcl, /* Last cluster of the fragment */ + DWORD term /* Value to set the last FAT entry */ +) +{ + FRESULT res; + + + while (obj->n_frag > 0) { /* Create the chain of last fragment */ + res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term); + if (res != FR_OK) return res; + obj->n_frag--; + } + return FR_OK; +} + +#endif /* FF_FS_EXFAT && !FF_FS_READONLY */ + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT handling - Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ + +static FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ + FFOBJID* obj, /* Corresponding object */ + DWORD clst, /* Cluster to remove a chain from */ + DWORD pclst /* Previous cluster of clst (0 if entire chain) */ +) +{ + FRESULT res = FR_OK; + DWORD nxt; + FATFS *fs = obj->fs; +#if FF_FS_EXFAT || FF_USE_TRIM + DWORD scl = clst, ecl = clst; +#endif +#if FF_USE_TRIM + LBA_t rt[2]; +#endif + + if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Check if in valid range */ + + /* Mark the previous cluster 'EOC' on the FAT if it exists */ + if (pclst != 0 && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) { + res = put_fat(fs, pclst, 0xFFFFFFFF); + if (res != FR_OK) return res; + } + + /* Remove the chain */ + do { + nxt = get_fat(obj, clst); /* Get cluster status */ + if (nxt == 0) break; /* Empty cluster? */ + if (nxt == 1) return FR_INT_ERR; /* Internal error? */ + if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { + res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */ + if (res != FR_OK) return res; + } + if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */ + fs->free_clst++; + fs->fsi_flag |= 1; + } +#if FF_FS_EXFAT || FF_USE_TRIM + if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ + ecl = nxt; + } else { /* End of contiguous cluster block */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + res = change_bitmap(fs, scl, ecl - scl + 1, 0); /* Mark the cluster block 'free' on the bitmap */ + if (res != FR_OK) return res; + } +#endif +#if FF_USE_TRIM + rt[0] = clst2sect(fs, scl); /* Start of data area to be freed */ + rt[1] = clst2sect(fs, ecl) + fs->csize - 1; /* End of data area to be freed */ + disk_ioctl(fs->pdrv, CTRL_TRIM, rt); /* Inform storage device that the data in the block may be erased */ +#endif + scl = ecl = nxt; + } +#endif + clst = nxt; /* Next cluster */ + } while (clst < fs->n_fatent); /* Repeat while not the last link */ + +#if FF_FS_EXFAT + /* Some post processes for chain status */ + if (fs->fs_type == FS_EXFAT) { + if (pclst == 0) { /* Has the entire chain been removed? */ + obj->stat = 0; /* Change the chain status 'initial' */ + } else { + if (obj->stat == 0) { /* Is it a fragmented chain from the beginning of this session? */ + clst = obj->sclust; /* Follow the chain to check if it gets contiguous */ + while (clst != pclst) { + nxt = get_fat(obj, clst); + if (nxt < 2) return FR_INT_ERR; + if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; + if (nxt != clst + 1) break; /* Not contiguous? */ + clst++; + } + if (clst == pclst) { /* Has the chain got contiguous again? */ + obj->stat = 2; /* Change the chain status 'contiguous' */ + } + } else { + if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) { /* Was the chain fragmented in this session and got contiguous again? */ + obj->stat = 2; /* Change the chain status 'contiguous' */ + } + } + } + } +#endif + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Stretch a chain or Create a new chain */ +/*-----------------------------------------------------------------------*/ + +static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + FFOBJID* obj, /* Corresponding object */ + DWORD clst /* Cluster# to stretch, 0:Create a new chain */ +) +{ + DWORD cs, ncl, scl; + FRESULT res; + FATFS *fs = obj->fs; + + + if (clst == 0) { /* Create a new chain */ + scl = fs->last_clst; /* Suggested cluster to start to find */ + if (scl == 0 || scl >= fs->n_fatent) scl = 1; + } + else { /* Stretch a chain */ + cs = get_fat(obj, clst); /* Check the cluster status */ + if (cs < 2) return 1; /* Test for insanity */ + if (cs == 0xFFFFFFFF) return cs; /* Test for disk error */ + if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + scl = clst; /* Cluster to start to find */ + } + if (fs->free_clst == 0) return 0; /* No free cluster */ + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + ncl = find_bitmap(fs, scl, 1); /* Find a free cluster */ + if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl; /* No free cluster or hard error? */ + res = change_bitmap(fs, ncl, 1, 1); /* Mark the cluster 'in use' */ + if (res == FR_INT_ERR) return 1; + if (res == FR_DISK_ERR) return 0xFFFFFFFF; + if (clst == 0) { /* Is it a new chain? */ + obj->stat = 2; /* Set status 'contiguous' */ + } else { /* It is a stretched chain */ + if (obj->stat == 2 && ncl != scl + 1) { /* Is the chain got fragmented? */ + obj->n_cont = scl - obj->sclust; /* Set size of the contiguous part */ + obj->stat = 3; /* Change status 'just fragmented' */ + } + } + if (obj->stat != 2) { /* Is the file non-contiguous? */ + if (ncl == clst + 1) { /* Is the cluster next to previous one? */ + obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2; /* Increment size of last framgent */ + } else { /* New fragment */ + if (obj->n_frag == 0) obj->n_frag = 1; + res = fill_last_frag(obj, clst, ncl); /* Fill last fragment on the FAT and link it to new one */ + if (res == FR_OK) obj->n_frag = 1; + } + } + } else +#endif + { /* On the FAT/FAT32 volume */ + ncl = 0; + if (scl == clst) { /* Stretching an existing chain? */ + ncl = scl + 1; /* Test if next cluster is free */ + if (ncl >= fs->n_fatent) ncl = 2; + cs = get_fat(obj, ncl); /* Get next cluster status */ + if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */ + if (cs != 0) { /* Not free? */ + cs = fs->last_clst; /* Start at suggested cluster if it is valid */ + if (cs >= 2 && cs < fs->n_fatent) scl = cs; + ncl = 0; + } + } + if (ncl == 0) { /* The new cluster cannot be contiguous and find another fragment */ + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= fs->n_fatent) { /* Check wrap-around */ + ncl = 2; + if (ncl > scl) return 0; /* No free cluster found? */ + } + cs = get_fat(obj, ncl); /* Get the cluster status */ + if (cs == 0) break; /* Found a free cluster? */ + if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */ + if (ncl == scl) return 0; /* No free cluster found? */ + } + } + res = put_fat(fs, ncl, 0xFFFFFFFF); /* Mark the new cluster 'EOC' */ + if (res == FR_OK && clst != 0) { + res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ + } + } + + if (res == FR_OK) { /* Update FSINFO if function succeeded. */ + fs->last_clst = ncl; + if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--; + fs->fsi_flag |= 1; + } else { + ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; /* Failed. Generate error status */ + } + + return ncl; /* Return new cluster number or error status */ +} + +#endif /* !FF_FS_READONLY */ + + + + +#if FF_USE_FASTSEEK +/*-----------------------------------------------------------------------*/ +/* FAT handling - Convert offset into cluster with link map table */ +/*-----------------------------------------------------------------------*/ + +static DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ + FIL* fp, /* Pointer to the file object */ + FSIZE_t ofs /* File offset to be converted to cluster# */ +) +{ + DWORD cl, ncl; + DWORD *tbl; + FATFS *fs = fp->obj.fs; + + + tbl = fp->cltbl + 1; /* Top of CLMT */ + cl = (DWORD)(ofs / SS(fs) / fs->csize); /* Cluster order from top of the file */ + for (;;) { + ncl = *tbl++; /* Number of cluters in the fragment */ + if (ncl == 0) return 0; /* End of table? (error) */ + if (cl < ncl) break; /* In this fragment? */ + cl -= ncl; tbl++; /* Next fragment */ + } + return cl + *tbl; /* Return the cluster number */ +} + +#endif /* FF_USE_FASTSEEK */ + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Fill a cluster with zeros */ +/*-----------------------------------------------------------------------*/ + +#if !FF_FS_READONLY +static FRESULT dir_clear ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS *fs, /* Filesystem object */ + DWORD clst /* Directory table to clear */ +) +{ + LBA_t sect; + UINT n, szb; + BYTE *ibuf; + + + if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */ + sect = clst2sect(fs, clst); /* Top of the cluster */ + fs->winsect = sect; /* Set window to top of the cluster */ + memset(fs->win, 0, sizeof fs->win); /* Clear window buffer */ +#if FF_USE_LFN == 3 /* Quick table clear by using multi-secter write */ + /* Allocate a temporary buffer */ + for (szb = ((DWORD)fs->csize * SS(fs) >= MAX_MALLOC) ? MAX_MALLOC : fs->csize * SS(fs), ibuf = 0; szb > SS(fs) && (ibuf = ff_memalloc(szb)) == 0; szb /= 2) ; + if (szb > SS(fs)) { /* Buffer allocated? */ + memset(ibuf, 0, szb); + szb /= SS(fs); /* Bytes -> Sectors */ + for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ + ff_memfree(ibuf); + } else +#endif + { + ibuf = fs->win; szb = 1; /* Use window buffer (many single-sector writes may take a time) */ + for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ + } + return (n == fs->csize) ? FR_OK : FR_DISK_ERR; +} +#endif /* !FF_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Set directory index */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp, /* Pointer to directory object */ + DWORD ofs /* Offset of directory table */ +) +{ + DWORD csz, clst; + FATFS *fs = dp->obj.fs; + + + if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) { /* Check range of offset and alignment */ + return FR_INT_ERR; + } + dp->dptr = ofs; /* Set current offset */ + clst = dp->obj.sclust; /* Table start cluster (0:root) */ + if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */ + clst = (DWORD)fs->dirbase; + if (FF_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */ + } + + if (clst == 0) { /* Static table (root-directory on the FAT volume) */ + if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */ + dp->sect = fs->dirbase; + + } else { /* Dynamic table (sub-directory or root-directory on the FAT32/exFAT volume) */ + csz = (DWORD)fs->csize * SS(fs); /* Bytes per cluster */ + while (ofs >= csz) { /* Follow cluster chain */ + clst = get_fat(&dp->obj, clst); /* Get next cluster */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal error */ + ofs -= csz; + } + dp->sect = clst2sect(fs, clst); + } + dp->clust = clst; /* Current cluster# */ + if (dp->sect == 0) return FR_INT_ERR; + dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ + dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Move directory table index next */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ + DIR* dp, /* Pointer to the directory object */ + int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ +) +{ + DWORD ofs, clst; + FATFS *fs = dp->obj.fs; + + + ofs = dp->dptr + SZDIRE; /* Next entry */ + if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) dp->sect = 0; /* Disable it if the offset reached the max value */ + if (dp->sect == 0) return FR_NO_FILE; /* Report EOT if it has been disabled */ + + if (ofs % SS(fs) == 0) { /* Sector changed? */ + dp->sect++; /* Next sector */ + + if (dp->clust == 0) { /* Static table */ + if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */ + dp->sect = 0; return FR_NO_FILE; + } + } + else { /* Dynamic table */ + if ((ofs / SS(fs) & (fs->csize - 1)) == 0) { /* Cluster changed? */ + clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ + if (clst <= 1) return FR_INT_ERR; /* Internal error */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst >= fs->n_fatent) { /* It reached end of dynamic table */ +#if !FF_FS_READONLY + if (!stretch) { /* If no stretch, report EOT */ + dp->sect = 0; return FR_NO_FILE; + } + clst = create_chain(&dp->obj, dp->clust); /* Allocate a cluster */ + if (clst == 0) return FR_DENIED; /* No free cluster */ + if (clst == 1) return FR_INT_ERR; /* Internal error */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (dir_clear(fs, clst) != FR_OK) return FR_DISK_ERR; /* Clean up the stretched table */ + if (FF_FS_EXFAT) dp->obj.stat |= 4; /* exFAT: The directory has been stretched */ +#else + if (!stretch) dp->sect = 0; /* (this line is to suppress compiler warning) */ + dp->sect = 0; return FR_NO_FILE; /* Report EOT */ +#endif + } + dp->clust = clst; /* Initialize data for new cluster */ + dp->sect = clst2sect(fs, clst); + } + } + } + dp->dptr = ofs; /* Current entry */ + dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */ + + return FR_OK; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Directory handling - Reserve a block of directory entries */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp, /* Pointer to the directory object */ + UINT n_ent /* Number of contiguous entries to allocate */ +) +{ + FRESULT res; + UINT n; + FATFS *fs = dp->obj.fs; + + + res = dir_sdi(dp, 0); + if (res == FR_OK) { + n = 0; + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; +#if FF_FS_EXFAT + if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) { /* Is the entry free? */ +#else + if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) { /* Is the entry free? */ +#endif + if (++n == n_ent) break; /* Is a block of contiguous free entries found? */ + } else { + n = 0; /* Not a free entry, restart to search */ + } + res = dir_next(dp, 1); /* Next entry with table stretch enabled */ + } while (res == FR_OK); + } + + if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ + return res; +} + +#endif /* !FF_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT: Directory handling - Load/Store start cluster number */ +/*-----------------------------------------------------------------------*/ + +static DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */ + FATFS* fs, /* Pointer to the fs object */ + const BYTE* dir /* Pointer to the key entry */ +) +{ + DWORD cl; + + cl = ld_word(dir + DIR_FstClusLO); + if (fs->fs_type == FS_FAT32) { + cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16; + } + + return cl; +} + + +#if !FF_FS_READONLY +static void st_clust ( + FATFS* fs, /* Pointer to the fs object */ + BYTE* dir, /* Pointer to the key entry */ + DWORD cl /* Value to be set */ +) +{ + st_word(dir + DIR_FstClusLO, (WORD)cl); + if (fs->fs_type == FS_FAT32) { + st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16)); + } +} +#endif + + + +#if FF_USE_LFN +/*--------------------------------------------------------*/ +/* FAT-LFN: Compare a part of file name with an LFN entry */ +/*--------------------------------------------------------*/ + +static int cmp_lfn ( /* 1:matched, 0:not matched */ + const WCHAR* lfnbuf, /* Pointer to the LFN working buffer to be compared */ + BYTE* dir /* Pointer to the directory entry containing the part of LFN */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */ + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ + uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ + if (wc != 0) { + if (i >= FF_MAX_LFN + 1 || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) { /* Compare it */ + return 0; /* Not matched */ + } + wc = uc; + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } + + if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0; /* Last segment matched but different length */ + + return 1; /* The part of LFN matched */ +} + + +#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT +/*-----------------------------------------------------*/ +/* FAT-LFN: Pick a part of file name from an LFN entry */ +/*-----------------------------------------------------*/ + +static int pick_lfn ( /* 1:succeeded, 0:buffer overflow or invalid LFN entry */ + WCHAR* lfnbuf, /* Pointer to the LFN working buffer */ + BYTE* dir /* Pointer to the LFN entry */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO is 0 */ + + i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13; /* Offset in the LFN buffer */ + + for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ + uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ + if (wc != 0) { + if (i >= FF_MAX_LFN + 1) return 0; /* Buffer overflow? */ + lfnbuf[i++] = wc = uc; /* Store it */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } + + if (dir[LDIR_Ord] & LLEF && wc != 0) { /* Put terminator if it is the last LFN part and not terminated */ + if (i >= FF_MAX_LFN + 1) return 0; /* Buffer overflow? */ + lfnbuf[i] = 0; + } + + return 1; /* The part of LFN is valid */ +} +#endif + + +#if !FF_FS_READONLY +/*-----------------------------------------*/ +/* FAT-LFN: Create an entry of LFN entries */ +/*-----------------------------------------*/ + +static void put_lfn ( + const WCHAR* lfn, /* Pointer to the LFN */ + BYTE* dir, /* Pointer to the LFN entry to be created */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* Checksum of the corresponding SFN */ +) +{ + UINT i, s; + WCHAR wc; + + + dir[LDIR_Chksum] = sum; /* Set checksum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + st_word(dir + LDIR_FstClusLO, 0); + + i = (ord - 1) * 13; /* Get offset in the LFN working buffer */ + s = wc = 0; + do { + if (wc != 0xFFFF) wc = lfn[i++]; /* Get an effective character */ + st_word(dir + LfnOfs[s], wc); /* Put it */ + if (wc == 0) wc = 0xFFFF; /* Padding characters for following items */ + } while (++s < 13); + if (wc == 0xFFFF || !lfn[i]) ord |= LLEF; /* Last LFN part is the start of LFN sequence */ + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_USE_LFN */ + + + +#if FF_USE_LFN && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT-LFN: Create a Numbered SFN */ +/*-----------------------------------------------------------------------*/ + +static void gen_numname ( + BYTE* dst, /* Pointer to the buffer to store numbered SFN */ + const BYTE* src, /* Pointer to SFN in directory form */ + const WCHAR* lfn, /* Pointer to LFN */ + UINT seq /* Sequence number */ +) +{ + BYTE ns[8], c; + UINT i, j; + WCHAR wc; + DWORD sreg; + + + memcpy(dst, src, 11); /* Prepare the SFN to be modified */ + + if (seq > 5) { /* In case of many collisions, generate a hash number instead of sequential number */ + sreg = seq; + while (*lfn) { /* Create a CRC as hash value */ + wc = *lfn++; + for (i = 0; i < 16; i++) { + sreg = (sreg << 1) + (wc & 1); + wc >>= 1; + if (sreg & 0x10000) sreg ^= 0x11021; + } + } + seq = (UINT)sreg; + } + + /* Make suffix (~ + hexadecimal) */ + i = 7; + do { + c = (BYTE)((seq % 16) + '0'); seq /= 16; + if (c > '9') c += 7; + ns[i--] = c; + } while (i && seq); + ns[i] = '~'; + + /* Append the suffix to the SFN body */ + for (j = 0; j < i && dst[j] != ' '; j++) { /* Find the offset to append */ + if (dbc_1st(dst[j])) { /* To avoid DBC break up */ + if (j == i - 1) break; + j++; + } + } + do { /* Append the suffix */ + dst[j++] = (i < 8) ? ns[i++] : ' '; + } while (j < 8); +} +#endif /* FF_USE_LFN && !FF_FS_READONLY */ + + + +#if FF_USE_LFN +/*-----------------------------------------------------------------------*/ +/* FAT-LFN: Calculate checksum of an SFN entry */ +/*-----------------------------------------------------------------------*/ + +static BYTE sum_sfn ( + const BYTE* dir /* Pointer to the SFN entry */ +) +{ + BYTE sum = 0; + UINT n = 11; + + do { + sum = (sum >> 1) + (sum << 7) + *dir++; + } while (--n); + return sum; +} + +#endif /* FF_USE_LFN */ + + + +#if FF_FS_EXFAT +/*-----------------------------------------------------------------------*/ +/* exFAT: Checksum */ +/*-----------------------------------------------------------------------*/ + +static WORD xdir_sum ( /* Get checksum of the directoly entry block */ + const BYTE* dir /* Directory entry block to be calculated */ +) +{ + UINT i, szblk; + WORD sum; + + + szblk = (dir[XDIR_NumSec] + 1) * SZDIRE; /* Number of bytes of the entry block */ + for (i = sum = 0; i < szblk; i++) { + if (i == XDIR_SetSum) { /* Skip 2-byte sum field */ + i++; + } else { + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i]; + } + } + return sum; +} + + + +static WORD xname_sum ( /* Get check sum (to be used as hash) of the file name */ + const WCHAR* name /* File name to be calculated */ +) +{ + WCHAR chr; + WORD sum = 0; + + + while ((chr = *name++) != 0) { + chr = (WCHAR)ff_wtoupper(chr); /* File name needs to be up-case converted */ + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF); + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8); + } + return sum; +} + + +#if !FF_FS_READONLY && FF_USE_MKFS +static DWORD xsum32 ( /* Returns 32-bit checksum */ + BYTE dat, /* Byte to be calculated (byte-by-byte processing) */ + DWORD sum /* Previous sum value */ +) +{ + sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat; + return sum; +} +#endif + + + +/*------------------------------------*/ +/* exFAT: Get a directory entry block */ +/*------------------------------------*/ + +static FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */ + DIR* dp /* Reading directory object pointing top of the entry block to load */ +) +{ + FRESULT res; + UINT i, sz_ent; + BYTE *dirb = dp->obj.fs->dirbuf; /* Pointer to the on-memory directory entry block 85+C0+C1s */ + + + /* Load file directory entry */ + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != ET_FILEDIR) return FR_INT_ERR; /* Invalid order */ + memcpy(dirb + 0 * SZDIRE, dp->dir, SZDIRE); + sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE; + if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR; + + /* Load stream extension entry */ + res = dir_next(dp, 0); + if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */ + if (res != FR_OK) return res; + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != ET_STREAM) return FR_INT_ERR; /* Invalid order */ + memcpy(dirb + 1 * SZDIRE, dp->dir, SZDIRE); + if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR; + + /* Load file name entries */ + i = 2 * SZDIRE; /* Name offset to load */ + do { + res = dir_next(dp, 0); + if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */ + if (res != FR_OK) return res; + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != ET_FILENAME) return FR_INT_ERR; /* Invalid order */ + if (i < MAXDIRB(FF_MAX_LFN)) memcpy(dirb + i, dp->dir, SZDIRE); + } while ((i += SZDIRE) < sz_ent); + + /* Sanity check (do it for only accessible object) */ + if (i <= MAXDIRB(FF_MAX_LFN)) { + if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR; + } + return FR_OK; +} + + +/*------------------------------------------------------------------*/ +/* exFAT: Initialize object allocation info with loaded entry block */ +/*------------------------------------------------------------------*/ + +static void init_alloc_info ( + FATFS* fs, /* Filesystem object */ + FFOBJID* obj /* Object allocation information to be initialized */ +) +{ + obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Start cluster */ + obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); /* Size */ + obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; /* Allocation status */ + obj->n_frag = 0; /* No last fragment info */ +} + + + +#if !FF_FS_READONLY || FF_FS_RPATH != 0 +/*------------------------------------------------*/ +/* exFAT: Load the object's directory entry block */ +/*------------------------------------------------*/ + +static FRESULT load_obj_xdir ( + DIR* dp, /* Blank directory object to be used to access containing directory */ + const FFOBJID* obj /* Object with its containing directory information */ +) +{ + FRESULT res; + + /* Open object containing directory */ + dp->obj.fs = obj->fs; + dp->obj.sclust = obj->c_scl; + dp->obj.stat = (BYTE)obj->c_size; + dp->obj.objsize = obj->c_size & 0xFFFFFF00; + dp->obj.n_frag = 0; + dp->blk_ofs = obj->c_ofs; + + res = dir_sdi(dp, dp->blk_ofs); /* Goto object's entry block */ + if (res == FR_OK) { + res = load_xdir(dp); /* Load the object's entry block */ + } + return res; +} +#endif + + +#if !FF_FS_READONLY +/*----------------------------------------*/ +/* exFAT: Store the directory entry block */ +/*----------------------------------------*/ + +static FRESULT store_xdir ( + DIR* dp /* Pointer to the directory object */ +) +{ + FRESULT res; + UINT nent; + BYTE *dirb = dp->obj.fs->dirbuf; /* Pointer to the directory entry block 85+C0+C1s */ + + /* Create set sum */ + st_word(dirb + XDIR_SetSum, xdir_sum(dirb)); + nent = dirb[XDIR_NumSec] + 1; + + /* Store the directory entry block to the directory */ + res = dir_sdi(dp, dp->blk_ofs); + while (res == FR_OK) { + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) break; + memcpy(dp->dir, dirb, SZDIRE); + dp->obj.fs->wflag = 1; + if (--nent == 0) break; + dirb += SZDIRE; + res = dir_next(dp, 0); + } + return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR; +} + + + +/*-------------------------------------------*/ +/* exFAT: Create a new directory entry block */ +/*-------------------------------------------*/ + +static void create_xdir ( + BYTE* dirb, /* Pointer to the directory entry block buffer */ + const WCHAR* lfn /* Pointer to the object name */ +) +{ + UINT i; + BYTE nc1, nlen; + WCHAR wc; + + + /* Create file-directory and stream-extension entry */ + memset(dirb, 0, 2 * SZDIRE); + dirb[0 * SZDIRE + XDIR_Type] = ET_FILEDIR; + dirb[1 * SZDIRE + XDIR_Type] = ET_STREAM; + + /* Create file-name entries */ + i = SZDIRE * 2; /* Top of file_name entries */ + nlen = nc1 = 0; wc = 1; + do { + dirb[i++] = ET_FILENAME; dirb[i++] = 0; + do { /* Fill name field */ + if (wc != 0 && (wc = lfn[nlen]) != 0) nlen++; /* Get a character if exist */ + st_word(dirb + i, wc); /* Store it */ + i += 2; + } while (i % SZDIRE != 0); + nc1++; + } while (lfn[nlen]); /* Fill next entry if any char follows */ + + dirb[XDIR_NumName] = nlen; /* Set name length */ + dirb[XDIR_NumSec] = 1 + nc1; /* Set secondary count (C0 + C1s) */ + st_word(dirb + XDIR_NameHash, xname_sum(lfn)); /* Set name hash */ +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_FS_EXFAT */ + + + +#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT +/*-----------------------------------------------------------------------*/ +/* Read an object from the directory */ +/*-----------------------------------------------------------------------*/ + +#define DIR_READ_FILE(dp) dir_read(dp, 0) +#define DIR_READ_LABEL(dp) dir_read(dp, 1) + +static FRESULT dir_read ( + DIR* dp, /* Pointer to the directory object */ + int vol /* Filtered by 0:file/directory or 1:volume label */ +) +{ + FRESULT res = FR_NO_FILE; + FATFS *fs = dp->obj.fs; + BYTE attr, b; +#if FF_USE_LFN + BYTE ord = 0xFF, sum = 0xFF; +#endif + + while (dp->sect) { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + b = dp->dir[DIR_Name]; /* Test for the entry type */ + if (b == 0) { + res = FR_NO_FILE; break; /* Reached to end of the directory */ + } +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + if (FF_USE_LABEL && vol) { + if (b == ET_VLABEL) break; /* Volume label entry? */ + } else { + if (b == ET_FILEDIR) { /* Start of the file entry block? */ + dp->blk_ofs = dp->dptr; /* Get location of the block */ + res = load_xdir(dp); /* Load the entry block */ + if (res == FR_OK) { + dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK; /* Get attribute */ + } + break; + } + } + } else +#endif + { /* On the FAT/FAT32 volume */ + dp->obj.attr = attr = dp->dir[DIR_Attr] & AM_MASK; /* Get attribute */ +#if FF_USE_LFN /* LFN configuration */ + if (b == DDEM || b == '.' || (int)((attr & ~AM_ARC) == AM_VOL) != vol) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (attr == AM_LFN) { /* An LFN entry is found */ + if (b & LLEF) { /* Is it start of an LFN sequence? */ + sum = dp->dir[LDIR_Chksum]; + b &= (BYTE)~LLEF; ord = b; + dp->blk_ofs = dp->dptr; + } + /* Check LFN validity and capture it */ + ord = (b == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; + } else { /* An SFN entry is found */ + if (ord != 0 || sum != sum_sfn(dp->dir)) { /* Is there a valid LFN? */ + dp->blk_ofs = 0xFFFFFFFF; /* It has no LFN. */ + } + break; + } + } +#else /* Non LFN configuration */ + if (b != DDEM && b != '.' && attr != AM_LFN && (int)((attr & ~AM_ARC) == AM_VOL) == vol) { /* Is it a valid entry? */ + break; + } +#endif + } + res = dir_next(dp, 0); /* Next entry */ + if (res != FR_OK) break; + } + + if (res != FR_OK) dp->sect = 0; /* Terminate the read operation on error or EOT */ + return res; +} + +#endif /* FF_FS_MINIMIZE <= 1 || FF_USE_LABEL || FF_FS_RPATH >= 2 */ + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Find an object in the directory */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp /* Pointer to the directory object with the file name */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; + BYTE c; +#if FF_USE_LFN + BYTE a, ord, sum; +#endif + + res = dir_sdi(dp, 0); /* Rewind directory object */ + if (res != FR_OK) return res; +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + BYTE nc; + UINT di, ni; + WORD hash = xname_sum(fs->lfnbuf); /* Hash value of the name to find */ + + while ((res = DIR_READ_FILE(dp)) == FR_OK) { /* Read an item */ +#if FF_MAX_LFN < 255 + if (fs->dirbuf[XDIR_NumName] > FF_MAX_LFN) continue; /* Skip comparison if inaccessible object name */ +#endif + if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue; /* Skip comparison if hash mismatched */ + for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) { /* Compare the name */ + if ((di % SZDIRE) == 0) di += 2; + if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break; + } + if (nc == 0 && !fs->lfnbuf[ni]) break; /* Name matched? */ + } + return res; + } +#endif + /* On the FAT/FAT32 volume */ +#if FF_USE_LFN + ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ +#endif + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + c = dp->dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if FF_USE_LFN /* LFN configuration */ + dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; + if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (!(dp->fn[NSFLAG] & NS_NOLFN)) { + if (c & LLEF) { /* Is it start of LFN sequence? */ + sum = dp->dir[LDIR_Chksum]; + c &= (BYTE)~LLEF; ord = c; /* LFN start order */ + dp->blk_ofs = dp->dptr; /* Start offset of LFN */ + } + /* Check validity of the LFN entry and compare it with given name */ + ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; + } + } else { /* An SFN entry is found */ + if (ord == 0 && sum == sum_sfn(dp->dir)) break; /* LFN matched? */ + if (!(dp->fn[NSFLAG] & NS_LOSS) && !memcmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */ + ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ + } + } +#else /* Non LFN configuration */ + dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK; + if (!(dp->dir[DIR_Attr] & AM_VOL) && !memcmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry? */ +#endif + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + + return res; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Register an object to the directory */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */ + DIR* dp /* Target directory with object name to be created */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; +#if FF_USE_LFN /* LFN configuration */ + UINT n, len, n_ent; + BYTE sn[12], sum; + + + if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME; /* Check name validity */ + for (len = 0; fs->lfnbuf[len]; len++) ; /* Get lfn length */ + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + n_ent = (len + 14) / 15 + 2; /* Number of entries to allocate (85+C0+C1s) */ + res = dir_alloc(dp, n_ent); /* Allocate directory entries */ + if (res != FR_OK) return res; + dp->blk_ofs = dp->dptr - SZDIRE * (n_ent - 1); /* Set the allocated entry block offset */ + + if (dp->obj.stat & 4) { /* Has the directory been stretched by new allocation? */ + dp->obj.stat &= ~4; + res = fill_first_frag(&dp->obj); /* Fill the first fragment on the FAT if needed */ + if (res != FR_OK) return res; + res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF); /* Fill the last fragment on the FAT if needed */ + if (res != FR_OK) return res; + if (dp->obj.sclust != 0) { /* Is it a sub-directory? */ + DIR dj; + + res = load_obj_xdir(&dj, &dp->obj); /* Load the object status */ + if (res != FR_OK) return res; + dp->obj.objsize += (DWORD)fs->csize * SS(fs); /* Increase the directory size by cluster size */ + st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize); + st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize); + fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1; /* Update the allocation status */ + res = store_xdir(&dj); /* Store the object status */ + if (res != FR_OK) return res; + } + } + + create_xdir(fs->dirbuf, fs->lfnbuf); /* Create on-memory directory block to be written later */ + return FR_OK; + } +#endif + /* On the FAT/FAT32 volume */ + memcpy(sn, dp->fn, 12); + if (sn[NSFLAG] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ + dp->fn[NSFLAG] = NS_NOLFN; /* Find only SFN */ + for (n = 1; n < 100; n++) { + gen_numname(dp->fn, sn, fs->lfnbuf, n); /* Generate a numbered name */ + res = dir_find(dp); /* Check if the name collides with existing SFN */ + if (res != FR_OK) break; + } + if (n == 100) return FR_DENIED; /* Abort if too many collisions */ + if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ + dp->fn[NSFLAG] = sn[NSFLAG]; + } + + /* Create an SFN with/without LFNs. */ + n_ent = (sn[NSFLAG] & NS_LFN) ? (len + 12) / 13 + 1 : 1; /* Number of entries to allocate */ + res = dir_alloc(dp, n_ent); /* Allocate entries */ + if (res == FR_OK && --n_ent) { /* Set LFN entry if needed */ + res = dir_sdi(dp, dp->dptr - n_ent * SZDIRE); + if (res == FR_OK) { + sum = sum_sfn(dp->fn); /* Checksum value of the SFN tied to the LFN */ + do { /* Store LFN entries in bottom first */ + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + put_lfn(fs->lfnbuf, dp->dir, (BYTE)n_ent, sum); + fs->wflag = 1; + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK && --n_ent); + } + } + +#else /* Non LFN configuration */ + res = dir_alloc(dp, 1); /* Allocate an entry for SFN */ + +#endif + + /* Set SFN entry */ + if (res == FR_OK) { + res = move_window(fs, dp->sect); + if (res == FR_OK) { + memset(dp->dir, 0, SZDIRE); /* Clean the entry */ + memcpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */ +#if FF_USE_LFN + dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT); /* Put NT flag */ +#endif + fs->wflag = 1; + } + } + + return res; +} + +#endif /* !FF_FS_READONLY */ + + + +#if !FF_FS_READONLY && FF_FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Remove an object from the directory */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */ + DIR* dp /* Directory object pointing the entry to be removed */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; +#if FF_USE_LFN /* LFN configuration */ + DWORD last = dp->dptr; + + res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs); /* Goto top of the entry block if LFN is exist */ + if (res == FR_OK) { + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + dp->dir[XDIR_Type] &= 0x7F; /* Clear the entry InUse flag. */ + } else { /* On the FAT/FAT32 volume */ + dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'. */ + } + fs->wflag = 1; + if (dp->dptr >= last) break; /* If reached last entry then all entries of the object has been deleted. */ + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR; + } +#else /* Non LFN configuration */ + + res = move_window(fs, dp->sect); + if (res == FR_OK) { + dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'.*/ + fs->wflag = 1; + } +#endif + + return res; +} + +#endif /* !FF_FS_READONLY && FF_FS_MINIMIZE == 0 */ + + + +#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 +/*-----------------------------------------------------------------------*/ +/* Get file information from directory entry */ +/*-----------------------------------------------------------------------*/ + +static void get_fileinfo ( + DIR* dp, /* Pointer to the directory object */ + FILINFO* fno /* Pointer to the file information to be filled */ +) +{ + UINT si, di; +#if FF_USE_LFN + BYTE lcf; + WCHAR wc, hs; + FATFS *fs = dp->obj.fs; + UINT nw; +#else + TCHAR c; +#endif + + + fno->fname[0] = 0; /* Invaidate file info */ + if (dp->sect == 0) return; /* Exit if read pointer has reached end of directory */ + +#if FF_USE_LFN /* LFN configuration */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* exFAT volume */ + UINT nc = 0; + + si = SZDIRE * 2; di = 0; /* 1st C1 entry in the entry block */ + hs = 0; + while (nc < fs->dirbuf[XDIR_NumName]) { + if (si >= MAXDIRB(FF_MAX_LFN)) { /* Truncated directory block? */ + di = 0; break; + } + if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */ + wc = ld_word(fs->dirbuf + si); si += 2; nc++; /* Get a character */ + if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */ + hs = wc; continue; /* Get low surrogate */ + } + nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in API encoding */ + if (nw == 0) { /* Buffer overflow or wrong char? */ + di = 0; break; + } + di += nw; + hs = 0; + } + if (hs != 0) di = 0; /* Broken surrogate pair? */ + if (di == 0) fno->fname[di++] = '\?'; /* Inaccessible object name? */ + fno->fname[di] = 0; /* Terminate the name */ + fno->altname[0] = 0; /* exFAT does not support SFN */ + + fno->fattrib = fs->dirbuf[XDIR_Attr] & AM_MASKX; /* Attribute */ + fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(fs->dirbuf + XDIR_FileSize); /* Size */ + fno->ftime = ld_word(fs->dirbuf + XDIR_ModTime + 0); /* Time */ + fno->fdate = ld_word(fs->dirbuf + XDIR_ModTime + 2); /* Date */ + return; + } else +#endif + { /* FAT/FAT32 volume */ + if (dp->blk_ofs != 0xFFFFFFFF) { /* Get LFN if available */ + si = di = 0; + hs = 0; + while (fs->lfnbuf[si] != 0) { + wc = fs->lfnbuf[si++]; /* Get an LFN character (UTF-16) */ + if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */ + hs = wc; continue; /* Get low surrogate */ + } + nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in API encoding */ + if (nw == 0) { /* Buffer overflow or wrong char? */ + di = 0; break; + } + di += nw; + hs = 0; + } + if (hs != 0) di = 0; /* Broken surrogate pair? */ + fno->fname[di] = 0; /* Terminate the LFN (null string means LFN is invalid) */ + } + } + + si = di = 0; + while (si < 11) { /* Get SFN from SFN entry */ + wc = dp->dir[si++]; /* Get a char */ + if (wc == ' ') continue; /* Skip padding spaces */ + if (wc == RDDEM) wc = DDEM; /* Restore replaced DDEM character */ + if (si == 9 && di < FF_SFN_BUF) fno->altname[di++] = '.'; /* Insert a . if extension is exist */ +#if FF_LFN_UNICODE >= 1 /* Unicode output */ + if (dbc_1st((BYTE)wc) && si != 8 && si != 11 && dbc_2nd(dp->dir[si])) { /* Make a DBC if needed */ + wc = wc << 8 | dp->dir[si++]; + } + wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM -> Unicode */ + if (wc == 0) { /* Wrong char in the current code page? */ + di = 0; break; + } + nw = put_utf(wc, &fno->altname[di], FF_SFN_BUF - di); /* Store it in API encoding */ + if (nw == 0) { /* Buffer overflow? */ + di = 0; break; + } + di += nw; +#else /* ANSI/OEM output */ + fno->altname[di++] = (TCHAR)wc; /* Store it without any conversion */ +#endif + } + fno->altname[di] = 0; /* Terminate the SFN (null string means SFN is invalid) */ + + if (fno->fname[0] == 0) { /* If LFN is invalid, altname[] needs to be copied to fname[] */ + if (di == 0) { /* If LFN and SFN both are invalid, this object is inaccessible */ + fno->fname[di++] = '\?'; + } else { + for (si = di = 0, lcf = NS_BODY; fno->altname[si]; si++, di++) { /* Copy altname[] to fname[] with case information */ + wc = (WCHAR)fno->altname[si]; + if (wc == '.') lcf = NS_EXT; + if (IsUpper(wc) && (dp->dir[DIR_NTres] & lcf)) wc += 0x20; + fno->fname[di] = (TCHAR)wc; + } + } + fno->fname[di] = 0; /* Terminate the LFN */ + if (!dp->dir[DIR_NTres]) fno->altname[0] = 0; /* Altname is not needed if neither LFN nor case info is exist. */ + } + +#else /* Non-LFN configuration */ + si = di = 0; + while (si < 11) { /* Copy name body and extension */ + c = (TCHAR)dp->dir[si++]; + if (c == ' ') continue; /* Skip padding spaces */ + if (c == RDDEM) c = DDEM; /* Restore replaced DDEM character */ + if (si == 9) fno->fname[di++] = '.';/* Insert a . if extension is exist */ + fno->fname[di++] = c; + } + fno->fname[di] = 0; /* Terminate the SFN */ +#endif + + fno->fattrib = dp->dir[DIR_Attr] & AM_MASK; /* Attribute */ + fno->fsize = ld_dword(dp->dir + DIR_FileSize); /* Size */ + fno->ftime = ld_word(dp->dir + DIR_ModTime + 0); /* Time */ + fno->fdate = ld_word(dp->dir + DIR_ModTime + 2); /* Date */ +} + +#endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */ + + + +#if FF_USE_FIND && FF_FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Pattern matching */ +/*-----------------------------------------------------------------------*/ + +#define FIND_RECURS 4 /* Maximum number of wildcard terms in the pattern to limit recursion */ + + +static DWORD get_achar ( /* Get a character and advance ptr */ + const TCHAR** ptr /* Pointer to pointer to the ANSI/OEM or Unicode string */ +) +{ + DWORD chr; + + +#if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode input */ + chr = tchar2uni(ptr); + if (chr == 0xFFFFFFFF) chr = 0; /* Wrong UTF encoding is recognized as end of the string */ + chr = ff_wtoupper(chr); + +#else /* ANSI/OEM input */ + chr = (BYTE)*(*ptr)++; /* Get a byte */ + if (IsLower(chr)) chr -= 0x20; /* To upper ASCII char */ +#if FF_CODE_PAGE == 0 + if (ExCvt && chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ +#elif FF_CODE_PAGE < 900 + if (chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ +#endif +#if FF_CODE_PAGE == 0 || FF_CODE_PAGE >= 900 + if (dbc_1st((BYTE)chr)) { /* Get DBC 2nd byte if needed */ + chr = dbc_2nd((BYTE)**ptr) ? chr << 8 | (BYTE)*(*ptr)++ : 0; + } +#endif + +#endif + return chr; +} + + +static int pattern_match ( /* 0:mismatched, 1:matched */ + const TCHAR* pat, /* Matching pattern */ + const TCHAR* nam, /* String to be tested */ + UINT skip, /* Number of pre-skip chars (number of ?s, b8:infinite (* specified)) */ + UINT recur /* Recursion count */ +) +{ + const TCHAR *pptr; + const TCHAR *nptr; + DWORD pchr, nchr; + UINT sk; + + + while ((skip & 0xFF) != 0) { /* Pre-skip name chars */ + if (!get_achar(&nam)) return 0; /* Branch mismatched if less name chars */ + skip--; + } + if (*pat == 0 && skip) return 1; /* Matched? (short circuit) */ + + do { + pptr = pat; nptr = nam; /* Top of pattern and name to match */ + for (;;) { + if (*pptr == '\?' || *pptr == '*') { /* Wildcard term? */ + if (recur == 0) return 0; /* Too many wildcard terms? */ + sk = 0; + do { /* Analyze the wildcard term */ + if (*pptr++ == '\?') { + sk++; + } else { + sk |= 0x100; + } + } while (*pptr == '\?' || *pptr == '*'); + if (pattern_match(pptr, nptr, sk, recur - 1)) return 1; /* Test new branch (recursive call) */ + nchr = *nptr; break; /* Branch mismatched */ + } + pchr = get_achar(&pptr); /* Get a pattern char */ + nchr = get_achar(&nptr); /* Get a name char */ + if (pchr != nchr) break; /* Branch mismatched? */ + if (pchr == 0) return 1; /* Branch matched? (matched at end of both strings) */ + } + get_achar(&nam); /* nam++ */ + } while (skip && nchr); /* Retry until end of name if infinite search is specified */ + + return 0; +} + +#endif /* FF_USE_FIND && FF_FS_MINIMIZE <= 1 */ + + + +/*-----------------------------------------------------------------------*/ +/* Pick a top segment and create the object name in directory form */ +/*-----------------------------------------------------------------------*/ + +static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not create */ + DIR* dp, /* Pointer to the directory object */ + const TCHAR** path /* Pointer to pointer to the segment in the path string */ +) +{ +#if FF_USE_LFN /* LFN configuration */ + BYTE b, cf; + WCHAR wc; + WCHAR *lfn; + const TCHAR* p; + DWORD uc; + UINT i, ni, si, di; + + + /* Create LFN into LFN working buffer */ + p = *path; lfn = dp->obj.fs->lfnbuf; di = 0; + for (;;) { + uc = tchar2uni(&p); /* Get a character */ + if (uc == 0xFFFFFFFF) return FR_INVALID_NAME; /* Invalid code or UTF decode error */ + if (uc >= 0x10000) lfn[di++] = (WCHAR)(uc >> 16); /* Store high surrogate if needed */ + wc = (WCHAR)uc; + if (wc < ' ' || IsSeparator(wc)) break; /* Break if end of the path or a separator is found */ + if (wc < 0x80 && strchr("*:<>|\"\?\x7F", (int)wc)) return FR_INVALID_NAME; /* Reject illegal characters for LFN */ + if (di >= FF_MAX_LFN) return FR_INVALID_NAME; /* Reject too long name */ + lfn[di++] = wc; /* Store the Unicode character */ + } + if (wc < ' ') { /* Stopped at end of the path? */ + cf = NS_LAST; /* Last segment */ + } else { /* Stopped at a separator */ + while (IsSeparator(*p)) p++; /* Skip duplicated separators if exist */ + cf = 0; /* Next segment may follow */ + if (IsTerminator(*p)) cf = NS_LAST; /* Ignore terminating separator */ + } + *path = p; /* Return pointer to the next segment */ + +#if FF_FS_RPATH != 0 + if ((di == 1 && lfn[di - 1] == '.') || + (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { /* Is this segment a dot name? */ + lfn[di] = 0; + for (i = 0; i < 11; i++) { /* Create dot name for SFN entry */ + dp->fn[i] = (i < di) ? '.' : ' '; + } + dp->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } +#endif + while (di) { /* Snip off trailing spaces and dots if exist */ + wc = lfn[di - 1]; + if (wc != ' ' && wc != '.') break; + di--; + } + lfn[di] = 0; /* LFN is created into the working buffer */ + if (di == 0) return FR_INVALID_NAME; /* Reject null name */ + + /* Create SFN in directory form */ + for (si = 0; lfn[si] == ' '; si++) ; /* Remove leading spaces */ + if (si > 0 || lfn[si] == '.') cf |= NS_LOSS | NS_LFN; /* Is there any leading space or dot? */ + while (di > 0 && lfn[di - 1] != '.') di--; /* Find last dot (di<=si: no extension) */ + + memset(dp->fn, ' ', 11); + i = b = 0; ni = 8; + for (;;) { + wc = lfn[si++]; /* Get an LFN character */ + if (wc == 0) break; /* Break on end of the LFN */ + if (wc == ' ' || (wc == '.' && si != di)) { /* Remove embedded spaces and dots */ + cf |= NS_LOSS | NS_LFN; + continue; + } + + if (i >= ni || si == di) { /* End of field? */ + if (ni == 11) { /* Name extension overflow? */ + cf |= NS_LOSS | NS_LFN; + break; + } + if (si != di) cf |= NS_LOSS | NS_LFN; /* Name body overflow? */ + if (si > di) break; /* No name extension? */ + si = di; i = 8; ni = 11; b <<= 2; /* Enter name extension */ + continue; + } + + if (wc >= 0x80) { /* Is this an extended character? */ + cf |= NS_LFN; /* LFN entry needs to be created */ +#if FF_CODE_PAGE == 0 + if (ExCvt) { /* In SBCS cfg */ + wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */ + if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ + } else { /* In DBCS cfg */ + wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Up-convert ==> ANSI/OEM code */ + } +#elif FF_CODE_PAGE < 900 /* In SBCS cfg */ + wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */ + if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ +#else /* In DBCS cfg */ + wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Up-convert ==> ANSI/OEM code */ +#endif + } + + if (wc >= 0x100) { /* Is this a DBC? */ + if (i >= ni - 1) { /* Field overflow? */ + cf |= NS_LOSS | NS_LFN; + i = ni; continue; /* Next field */ + } + dp->fn[i++] = (BYTE)(wc >> 8); /* Put 1st byte */ + } else { /* SBC */ + if (wc == 0 || strchr("+,;=[]", (int)wc)) { /* Replace illegal characters for SFN */ + wc = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ + } else { + if (IsUpper(wc)) { /* ASCII upper case? */ + b |= 2; + } + if (IsLower(wc)) { /* ASCII lower case? */ + b |= 1; wc -= 0x20; + } + } + } + dp->fn[i++] = (BYTE)wc; + } + + if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + + if (ni == 8) b <<= 2; /* Shift capital flags if no extension */ + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN; /* LFN entry needs to be created if composite capitals */ + if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */ + if (b & 0x01) cf |= NS_EXT; /* NT flag (Extension has small capital letters only) */ + if (b & 0x04) cf |= NS_BODY; /* NT flag (Body has small capital letters only) */ + } + + dp->fn[NSFLAG] = cf; /* SFN is created into dp->fn[] */ + + return FR_OK; + + +#else /* FF_USE_LFN : Non-LFN configuration */ + BYTE c, d; + BYTE *sfn; + UINT ni, si, i; + const char *p; + + /* Create file name in directory form */ + p = *path; sfn = dp->fn; + memset(sfn, ' ', 11); + si = i = 0; ni = 8; +#if FF_FS_RPATH != 0 + if (p[si] == '.') { /* Is this a dot entry? */ + for (;;) { + c = (BYTE)p[si++]; + if (c != '.' || si >= 3) break; + sfn[i++] = c; + } + if (!IsSeparator(c) && c > ' ') return FR_INVALID_NAME; + *path = p + si; /* Return pointer to the next segment */ + sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of the path */ + return FR_OK; + } +#endif + for (;;) { + c = (BYTE)p[si++]; /* Get a byte */ + if (c <= ' ') break; /* Break if end of the path name */ + if (IsSeparator(c)) { /* Break if a separator is found */ + while (IsSeparator(p[si])) si++; /* Skip duplicated separator if exist */ + break; + } + if (c == '.' || i >= ni) { /* End of body or field overflow? */ + if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Field overflow or invalid dot? */ + i = 8; ni = 11; /* Enter file extension field */ + continue; + } +#if FF_CODE_PAGE == 0 + if (ExCvt && c >= 0x80) { /* Is SBC extended character? */ + c = ExCvt[c & 0x7F]; /* To upper SBC extended character */ + } +#elif FF_CODE_PAGE < 900 + if (c >= 0x80) { /* Is SBC extended character? */ + c = ExCvt[c & 0x7F]; /* To upper SBC extended character */ + } +#endif + if (dbc_1st(c)) { /* Check if it is a DBC 1st byte */ + d = (BYTE)p[si++]; /* Get 2nd byte */ + if (!dbc_2nd(d) || i >= ni - 1) return FR_INVALID_NAME; /* Reject invalid DBC */ + sfn[i++] = c; + sfn[i++] = d; + } else { /* SBC */ + if (strchr("*+,:;<=>[]|\"\?\x7F", (int)c)) return FR_INVALID_NAME; /* Reject illegal chrs for SFN */ + if (IsLower(c)) c -= 0x20; /* To upper */ + sfn[i++] = c; + } + } + *path = &p[si]; /* Return pointer to the next segment */ + if (i == 0) return FR_INVALID_NAME; /* Reject nul string */ + + if (sfn[0] == DDEM) sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + sfn[NSFLAG] = (c <= ' ' || p[si] <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ + + return FR_OK; +#endif /* FF_USE_LFN */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Follow a file path */ +/*-----------------------------------------------------------------------*/ + +static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ + DIR* dp, /* Directory object to return last directory and found object */ + const TCHAR* path /* Full-path string to find a file or directory */ +) +{ + FRESULT res; + BYTE ns; + FATFS *fs = dp->obj.fs; + + +#if FF_FS_RPATH != 0 + if (!IsSeparator(*path) && (FF_STR_VOLUME_ID != 2 || !IsTerminator(*path))) { /* Without heading separator */ + dp->obj.sclust = fs->cdir; /* Start at the current directory */ + } else +#endif + { /* With heading separator */ + while (IsSeparator(*path)) path++; /* Strip separators */ + dp->obj.sclust = 0; /* Start from the root directory */ + } +#if FF_FS_EXFAT + dp->obj.n_frag = 0; /* Invalidate last fragment counter of the object */ +#if FF_FS_RPATH != 0 + if (fs->fs_type == FS_EXFAT && dp->obj.sclust) { /* exFAT: Retrieve the sub-directory's status */ + DIR dj; + + dp->obj.c_scl = fs->cdc_scl; + dp->obj.c_size = fs->cdc_size; + dp->obj.c_ofs = fs->cdc_ofs; + res = load_obj_xdir(&dj, &dp->obj); + if (res != FR_OK) return res; + dp->obj.objsize = ld_dword(fs->dirbuf + XDIR_FileSize); + dp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; + } +#endif +#endif + + if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */ + dp->fn[NSFLAG] = NS_NONAME; + res = dir_sdi(dp, 0); + + } else { /* Follow path */ + for (;;) { + res = create_name(dp, &path); /* Get a segment name of the path */ + if (res != FR_OK) break; + res = dir_find(dp); /* Find an object with the segment name */ + ns = dp->fn[NSFLAG]; + if (res != FR_OK) { /* Failed to find the object */ + if (res == FR_NO_FILE) { /* Object is not found */ + if (FF_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */ + if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ + dp->fn[NSFLAG] = NS_NONAME; + res = FR_OK; + } else { /* Could not find the object */ + if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ + } + } + break; + } + if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ + /* Get into the sub-directory */ + if (!(dp->obj.attr & AM_DIR)) { /* It is not a sub-directory and cannot follow */ + res = FR_NO_PATH; break; + } +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* Save containing directory information for next dir */ + dp->obj.c_scl = dp->obj.sclust; + dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat; + dp->obj.c_ofs = dp->blk_ofs; + init_alloc_info(fs, &dp->obj); /* Open next directory */ + } else +#endif + { + dp->obj.sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs)); /* Open next directory */ + } + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get logical drive number from path name */ +/*-----------------------------------------------------------------------*/ + +static int get_ldnumber ( /* Returns logical drive number (-1:invalid drive number or null pointer) */ + const TCHAR** path /* Pointer to pointer to the path name */ +) +{ + const TCHAR *tp; + const TCHAR *tt; + TCHAR tc; + int i; + int vol = -1; +#if FF_STR_VOLUME_ID /* Find string volume ID */ + const char *sp; + char c; +#endif + + tt = tp = *path; + if (!tp) return vol; /* Invalid path name? */ + do { /* Find a colon in the path */ + tc = *tt++; + } while (!IsTerminator(tc) && tc != ':'); + + if (tc == ':') { /* DOS/Windows style volume ID? */ + i = FF_VOLUMES; + if (IsDigit(*tp) && tp + 2 == tt) { /* Is there a numeric volume ID + colon? */ + i = (int)*tp - '0'; /* Get the LD number */ + } +#if FF_STR_VOLUME_ID == 1 /* Arbitrary string is enabled */ + else { + i = 0; + do { + sp = VolumeStr[i]; tp = *path; /* This string volume ID and path name */ + do { /* Compare the volume ID with path name */ + c = *sp++; tc = *tp++; + if (IsLower(c)) c -= 0x20; + if (IsLower(tc)) tc -= 0x20; + } while (c && (TCHAR)c == tc); + } while ((c || tp != tt) && ++i < FF_VOLUMES); /* Repeat for each id until pattern match */ + } +#endif + if (i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */ + vol = i; /* Drive number */ + *path = tt; /* Snip the drive prefix off */ + } + return vol; + } +#if FF_STR_VOLUME_ID == 2 /* Unix style volume ID is enabled */ + if (*tp == '/') { /* Is there a volume ID? */ + while (*(tp + 1) == '/') tp++; /* Skip duplicated separator */ + i = 0; + do { + tt = tp; sp = VolumeStr[i]; /* Path name and this string volume ID */ + do { /* Compare the volume ID with path name */ + c = *sp++; tc = *(++tt); + if (IsLower(c)) c -= 0x20; + if (IsLower(tc)) tc -= 0x20; + } while (c && (TCHAR)c == tc); + } while ((c || (tc != '/' && !IsTerminator(tc))) && ++i < FF_VOLUMES); /* Repeat for each ID until pattern match */ + if (i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */ + vol = i; /* Drive number */ + *path = tt; /* Snip the drive prefix off */ + } + return vol; + } +#endif + /* No drive prefix is found */ +#if FF_FS_RPATH != 0 + vol = CurrVol; /* Default drive is current drive */ +#else + vol = 0; /* Default drive is 0 */ +#endif + return vol; /* Return the default drive */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* GPT support functions */ +/*-----------------------------------------------------------------------*/ + +#if FF_LBA64 + +/* Calculate CRC32 in byte-by-byte */ + +static DWORD crc32 ( /* Returns next CRC value */ + DWORD crc, /* Current CRC value */ + BYTE d /* A byte to be processed */ +) +{ + BYTE b; + + + for (b = 1; b; b <<= 1) { + crc ^= (d & b) ? 1 : 0; + crc = (crc & 1) ? crc >> 1 ^ 0xEDB88320 : crc >> 1; + } + return crc; +} + + +/* Check validity of GPT header */ + +static int test_gpt_header ( /* 0:Invalid, 1:Valid */ + const BYTE* gpth /* Pointer to the GPT header */ +) +{ + UINT i; + DWORD bcc, hlen; + + + if (memcmp(gpth + GPTH_Sign, "EFI PART" "\0\0\1", 12)) return 0; /* Check signature and version (1.0) */ + hlen = ld_dword(gpth + GPTH_Size); /* Check header size */ + if (hlen < 92 || hlen > FF_MIN_SS) return 0; + for (i = 0, bcc = 0xFFFFFFFF; i < hlen; i++) { /* Check header BCC */ + bcc = crc32(bcc, i - GPTH_Bcc < 4 ? 0 : gpth[i]); + } + if (~bcc != ld_dword(gpth + GPTH_Bcc)) return 0; + if (ld_dword(gpth + GPTH_PteSize) != SZ_GPTE) return 0; /* Table entry size (must be SZ_GPTE bytes) */ + if (ld_dword(gpth + GPTH_PtNum) > 128) return 0; /* Table size (must be 128 entries or less) */ + + return 1; +} + +#if !FF_FS_READONLY && FF_USE_MKFS + +/* Generate random value */ +static DWORD make_rand ( + DWORD seed, /* Seed value */ + BYTE *buff, /* Output buffer */ + UINT n /* Data length */ +) +{ + UINT r; + + + if (seed == 0) seed = 1; + do { + for (r = 0; r < 8; r++) seed = seed & 1 ? seed >> 1 ^ 0xA3000000 : seed >> 1; /* Shift 8 bits the 32-bit LFSR */ + *buff++ = (BYTE)seed; + } while (--n); + return seed; +} + +#endif +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Load a sector and check if it is an FAT VBR */ +/*-----------------------------------------------------------------------*/ + +/* Check what the sector is */ + +static UINT check_fs ( /* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS, 3:Not FAT and invalid BS, 4:Disk error */ + FATFS* fs, /* Filesystem object */ + LBA_t sect /* Sector to load and check if it is an FAT-VBR or not */ +) +{ + WORD w, sign; + BYTE b; + + + fs->wflag = 0; fs->winsect = (LBA_t)0 - 1; /* Invaidate window */ + if (move_window(fs, sect) != FR_OK) return 4; /* Load the boot sector */ + sign = ld_word(fs->win + BS_55AA); +#if FF_FS_EXFAT + if (sign == 0xAA55 && !memcmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) return 1; /* It is an exFAT VBR */ +#endif + b = fs->win[BS_JmpBoot]; + if (b == 0xEB || b == 0xE9 || b == 0xE8) { /* Valid JumpBoot code? (short jump, near jump or near call) */ + if (sign == 0xAA55 && !memcmp(fs->win + BS_FilSysType32, "FAT32 ", 8)) { + return 0; /* It is an FAT32 VBR */ + } + /* FAT volumes formatted with early MS-DOS lack BS_55AA and BS_FilSysType, so FAT VBR needs to be identified without them. */ + w = ld_word(fs->win + BPB_BytsPerSec); + b = fs->win[BPB_SecPerClus]; + if ((w & (w - 1)) == 0 && w >= FF_MIN_SS && w <= FF_MAX_SS /* Properness of sector size (512-4096 and 2^n) */ + && b != 0 && (b & (b - 1)) == 0 /* Properness of cluster size (2^n) */ + && ld_word(fs->win + BPB_RsvdSecCnt) != 0 /* Properness of reserved sectors (MNBZ) */ + && (UINT)fs->win[BPB_NumFATs] - 1 <= 1 /* Properness of FATs (1 or 2) */ + && ld_word(fs->win + BPB_RootEntCnt) != 0 /* Properness of root dir entries (MNBZ) */ + && (ld_word(fs->win + BPB_TotSec16) >= 128 || ld_dword(fs->win + BPB_TotSec32) >= 0x10000) /* Properness of volume sectors (>=128) */ + && ld_word(fs->win + BPB_FATSz16) != 0) { /* Properness of FAT size (MNBZ) */ + return 0; /* It can be presumed an FAT VBR */ + } + } + return sign == 0xAA55 ? 2 : 3; /* Not an FAT VBR (valid or invalid BS) */ +} + + +/* Find an FAT volume */ +/* (It supports only generic partitioning rules, MBR, GPT and SFD) */ + +static UINT find_volume ( /* Returns BS status found in the hosting drive */ + FATFS* fs, /* Filesystem object */ + UINT part /* Partition to fined = 0:find as SFD and partitions, >0:forced partition number */ +) +{ + UINT fmt, i; + DWORD mbr_pt[4]; + + + fmt = check_fs(fs, 0); /* Load sector 0 and check if it is an FAT VBR as SFD format */ + if (fmt != 2 && (fmt >= 3 || part == 0)) return fmt; /* Returns if it is an FAT VBR as auto scan, not a BS or disk error */ + + /* Sector 0 is not an FAT VBR or forced partition number wants a partition */ + +#if FF_LBA64 + if (fs->win[MBR_Table + PTE_System] == 0xEE) { /* GPT protective MBR? */ + DWORD n_ent, v_ent, ofs; + QWORD pt_lba; + + if (move_window(fs, 1) != FR_OK) return 4; /* Load GPT header sector (next to MBR) */ + if (!test_gpt_header(fs->win)) return 3; /* Check if GPT header is valid */ + n_ent = ld_dword(fs->win + GPTH_PtNum); /* Number of entries */ + pt_lba = ld_qword(fs->win + GPTH_PtOfs); /* Table location */ + for (v_ent = i = 0; i < n_ent; i++) { /* Find FAT partition */ + if (move_window(fs, pt_lba + i * SZ_GPTE / SS(fs)) != FR_OK) return 4; /* PT sector */ + ofs = i * SZ_GPTE % SS(fs); /* Offset in the sector */ + if (!memcmp(fs->win + ofs + GPTE_PtGuid, GUID_MS_Basic, 16)) { /* MS basic data partition? */ + v_ent++; + fmt = check_fs(fs, ld_qword(fs->win + ofs + GPTE_FstLba)); /* Load VBR and check status */ + if (part == 0 && fmt <= 1) return fmt; /* Auto search (valid FAT volume found first) */ + if (part != 0 && v_ent == part) return fmt; /* Forced partition order (regardless of it is valid or not) */ + } + } + return 3; /* Not found */ + } +#endif + if (FF_MULTI_PARTITION && part > 4) return 3; /* MBR has 4 partitions max */ + for (i = 0; i < 4; i++) { /* Load partition offset in the MBR */ + mbr_pt[i] = ld_dword(fs->win + MBR_Table + i * SZ_PTE + PTE_StLba); + } + i = part ? part - 1 : 0; /* Table index to find first */ + do { /* Find an FAT volume */ + fmt = mbr_pt[i] ? check_fs(fs, mbr_pt[i]) : 3; /* Check if the partition is FAT */ + } while (part == 0 && fmt >= 2 && ++i < 4); + return fmt; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Determine logical drive number and mount the volume if needed */ +/*-----------------------------------------------------------------------*/ + +static FRESULT mount_volume ( /* FR_OK(0): successful, !=0: an error occurred */ + const TCHAR** path, /* Pointer to pointer to the path name (drive number) */ + FATFS** rfs, /* Pointer to pointer to the found filesystem object */ + BYTE mode /* Desiered access mode to check write protection */ +) +{ + int vol; + FATFS *fs; + DSTATUS stat; + LBA_t bsect; + DWORD tsect, sysect, fasize, nclst, szbfat; + WORD nrsv; + UINT fmt; + + + /* Get logical drive number */ + *rfs = 0; + vol = get_ldnumber(path); + if (vol < 0) return FR_INVALID_DRIVE; + + /* Check if the filesystem object is valid or not */ + fs = FatFs[vol]; /* Get pointer to the filesystem object */ + if (!fs) return FR_NOT_ENABLED; /* Is the filesystem object available? */ +#if FF_FS_REENTRANT + if (!lock_volume(fs, 1)) return FR_TIMEOUT; /* Lock the volume, and system if needed */ +#endif + *rfs = fs; /* Return pointer to the filesystem object */ + + mode &= (BYTE)~FA_READ; /* Desired access mode, write access or not */ + if (fs->fs_type != 0) { /* If the volume has been mounted */ + stat = disk_status(fs->pdrv); + if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ + if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ + return FR_WRITE_PROTECTED; + } + return FR_OK; /* The filesystem object is already valid */ + } + } + + /* The filesystem object is not valid. */ + /* Following code attempts to mount the volume. (find an FAT volume, analyze the BPB and initialize the filesystem object) */ + + fs->fs_type = 0; /* Invalidate the filesystem object */ + stat = disk_initialize(fs->pdrv); /* Initialize the volume hosting physical drive */ + if (stat & STA_NOINIT) { /* Check if the initialization succeeded */ + return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ + } + if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; + } +#if FF_MAX_SS != FF_MIN_SS /* Get sector size (multiple sector size cfg only) */ + if (disk_ioctl(fs->pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR; + if (SS(fs) > FF_MAX_SS || SS(fs) < FF_MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; +#endif + + /* Find an FAT volume on the hosting drive */ + fmt = find_volume(fs, LD2PT(vol)); + if (fmt == 4) return FR_DISK_ERR; /* An error occurred in the disk I/O layer */ + if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + bsect = fs->winsect; /* Volume offset in the hosting physical drive */ + + /* An FAT volume is found (bsect). Following code initializes the filesystem object */ + +#if FF_FS_EXFAT + if (fmt == 1) { + QWORD maxlba; + DWORD so, cv, bcl, i; + + for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ; /* Check zero filler */ + if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM; + + if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM; /* Check exFAT version (must be version 1.0) */ + + if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) { /* (BPB_BytsPerSecEx must be equal to the physical sector size) */ + return FR_NO_FILESYSTEM; + } + + maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect; /* Last LBA of the volume + 1 */ + if (!FF_LBA64 && maxlba >= 0x100000000) return FR_NO_FILESYSTEM; /* (It cannot be accessed in 32-bit LBA) */ + + fs->fsize = ld_dword(fs->win + BPB_FatSzEx); /* Number of sectors per FAT */ + + fs->n_fats = fs->win[BPB_NumFATsEx]; /* Number of FATs */ + if (fs->n_fats != 1) return FR_NO_FILESYSTEM; /* (Supports only 1 FAT) */ + + fs->csize = 1 << fs->win[BPB_SecPerClusEx]; /* Cluster size */ + if (fs->csize == 0) return FR_NO_FILESYSTEM; /* (Must be 1..32768 sectors) */ + + nclst = ld_dword(fs->win + BPB_NumClusEx); /* Number of clusters */ + if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM; /* (Too many clusters) */ + fs->n_fatent = nclst + 2; + + /* Boundaries and Limits */ + fs->volbase = bsect; + fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx); + fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx); + if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM; /* (Volume size must not be smaller than the size required) */ + fs->dirbase = ld_dword(fs->win + BPB_RootClusEx); + + /* Get bitmap location and check if it is contiguous (implementation assumption) */ + so = i = 0; + for (;;) { /* Find the bitmap entry in the root directory (in only first cluster) */ + if (i == 0) { + if (so >= fs->csize) return FR_NO_FILESYSTEM; /* Not found? */ + if (move_window(fs, clst2sect(fs, (DWORD)fs->dirbase) + so) != FR_OK) return FR_DISK_ERR; + so++; + } + if (fs->win[i] == ET_BITMAP) break; /* Is it a bitmap entry? */ + i = (i + SZDIRE) % SS(fs); /* Next entry */ + } + bcl = ld_dword(fs->win + i + 20); /* Bitmap cluster */ + if (bcl < 2 || bcl >= fs->n_fatent) return FR_NO_FILESYSTEM; /* (Wrong cluster#) */ + fs->bitbase = fs->database + fs->csize * (bcl - 2); /* Bitmap sector */ + for (;;) { /* Check if bitmap is contiguous */ + if (move_window(fs, fs->fatbase + bcl / (SS(fs) / 4)) != FR_OK) return FR_DISK_ERR; + cv = ld_dword(fs->win + bcl % (SS(fs) / 4) * 4); + if (cv == 0xFFFFFFFF) break; /* Last link? */ + if (cv != ++bcl) return FR_NO_FILESYSTEM; /* Fragmented bitmap? */ + } + +#if !FF_FS_READONLY + fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ +#endif + fmt = FS_EXFAT; /* FAT sub-type */ + } else +#endif /* FF_FS_EXFAT */ + { + if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must be equal to the physical sector size) */ + + fasize = ld_word(fs->win + BPB_FATSz16); /* Number of sectors per FAT */ + if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32); + fs->fsize = fasize; + + fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FATs */ + if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + fasize *= fs->n_fats; /* Number of sectors for FAT area */ + + fs->csize = fs->win[BPB_SecPerClus]; /* Cluster size */ + if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ + + fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt); /* Number of root directory entries */ + if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ + + tsect = ld_word(fs->win + BPB_TotSec16); /* Number of sectors on the volume */ + if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32); + + nrsv = ld_word(fs->win + BPB_RsvdSecCnt); /* Number of reserved sectors */ + if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */ + + /* Determine the FAT sub type */ + sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE); /* RSV + FAT + DIR */ + if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + fmt = 0; + if (nclst <= MAX_FAT32) fmt = FS_FAT32; + if (nclst <= MAX_FAT16) fmt = FS_FAT16; + if (nclst <= MAX_FAT12) fmt = FS_FAT12; + if (fmt == 0) return FR_NO_FILESYSTEM; + + /* Boundaries and Limits */ + fs->n_fatent = nclst + 2; /* Number of FAT entries */ + fs->volbase = bsect; /* Volume start sector */ + fs->fatbase = bsect + nrsv; /* FAT start sector */ + fs->database = bsect + sysect; /* Data start sector */ + if (fmt == FS_FAT32) { + if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0) */ + if (fs->n_rootdir != 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */ + szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ + } else { + if (fs->n_rootdir == 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ + fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ + fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + } + if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_FATSz must not be less than the size needed) */ + +#if !FF_FS_READONLY + /* Get FSInfo if available */ + fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ + fs->fsi_flag = 0x80; +#if (FF_FS_NOFSINFO & 3) != 3 + if (fmt == FS_FAT32 /* Allow to update FSInfo only if BPB_FSInfo32 == 1 */ + && ld_word(fs->win + BPB_FSInfo32) == 1 + && move_window(fs, bsect + 1) == FR_OK) + { + fs->fsi_flag = 0; + if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSInfo data if available */ + && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 + && ld_dword(fs->win + FSI_StrucSig) == 0x61417272) + { +#if (FF_FS_NOFSINFO & 1) == 0 + fs->free_clst = ld_dword(fs->win + FSI_Free_Count); +#endif +#if (FF_FS_NOFSINFO & 2) == 0 + fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free); +#endif + } + } +#endif /* (FF_FS_NOFSINFO & 3) != 3 */ +#endif /* !FF_FS_READONLY */ + } + + fs->fs_type = (BYTE)fmt;/* FAT sub-type (the filesystem object gets valid) */ + fs->id = ++Fsid; /* Volume mount ID */ +#if FF_USE_LFN == 1 + fs->lfnbuf = LfnBuf; /* Static LFN working buffer */ +#if FF_FS_EXFAT + fs->dirbuf = DirBuf; /* Static directory block scratchpad buuffer */ +#endif +#endif +#if FF_FS_RPATH != 0 + fs->cdir = 0; /* Initialize current directory */ +#endif +#if FF_FS_LOCK /* Clear file lock semaphores */ + clear_share(fs); +#endif + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/directory object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */ + FFOBJID* obj, /* Pointer to the FFOBJID, the 1st member in the FIL/DIR structure, to check validity */ + FATFS** rfs /* Pointer to pointer to the owner filesystem object to return */ +) +{ + FRESULT res = FR_INVALID_OBJECT; + + + if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) { /* Test if the object is valid */ +#if FF_FS_REENTRANT + if (lock_volume(obj->fs, 0)) { /* Take a grant to access the volume */ + if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the hosting phsical drive is kept initialized */ + res = FR_OK; + } else { + unlock_volume(obj->fs, FR_OK); /* Invalidated volume, abort to access */ + } + } else { /* Could not take */ + res = FR_TIMEOUT; + } +#else + if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the hosting phsical drive is kept initialized */ + res = FR_OK; + } +#endif + } + *rfs = (res == FR_OK) ? obj->fs : 0; /* Return corresponding filesystem object if it is valid */ + return res; +} + + + + +/*--------------------------------------------------------------------------- + + Public Functions (FatFs API) + +----------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Logical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + FATFS* fs, /* Pointer to the filesystem object to be registered (NULL:unmount)*/ + const TCHAR* path, /* Logical drive number to be mounted/unmounted */ + BYTE opt /* Mount option: 0=Do not mount (delayed mount), 1=Mount immediately */ +) +{ + FATFS *cfs; + int vol; + FRESULT res; + const TCHAR *rp = path; + + + /* Get volume ID (logical drive number) */ + vol = get_ldnumber(&rp); + if (vol < 0) return FR_INVALID_DRIVE; + cfs = FatFs[vol]; /* Pointer to the filesystem object of the volume */ + + if (cfs) { /* Unregister current filesystem object if regsitered */ + FatFs[vol] = 0; +#if FF_FS_LOCK + clear_share(cfs); +#endif +#if FF_FS_REENTRANT /* Discard mutex of the current volume */ + ff_mutex_delete(vol); +#endif + cfs->fs_type = 0; /* Invalidate the filesystem object to be unregistered */ + } + + if (fs) { /* Register new filesystem object */ + fs->pdrv = LD2PD(vol); /* Volume hosting physical drive */ +#if FF_FS_REENTRANT /* Create a volume mutex */ + fs->ldrv = (BYTE)vol; /* Owner volume ID */ + if (!ff_mutex_create(vol)) return FR_INT_ERR; +#if FF_FS_LOCK + if (SysLock == 0) { /* Create a system mutex if needed */ + if (!ff_mutex_create(FF_VOLUMES)) { + ff_mutex_delete(vol); + return FR_INT_ERR; + } + SysLock = 1; /* System mutex is ready */ + } +#endif +#endif + fs->fs_type = 0; /* Invalidate the new filesystem object */ + FatFs[vol] = fs; /* Register new fs object */ + } + + if (opt == 0) return FR_OK; /* Do not mount now, it will be mounted in subsequent file functions */ + + res = mount_volume(&path, &fs, 0); /* Force mounted the volume */ + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL* fp, /* Pointer to the blank file object */ + const TCHAR* path, /* Pointer to the file name */ + BYTE mode /* Access mode and open mode flags */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; +#if !FF_FS_READONLY + DWORD cl, bcs, clst, tm; + LBA_t sc; + FSIZE_t ofs; +#endif + DEF_NAMBUF + + + if (!fp) return FR_INVALID_OBJECT; + + /* Get logical drive number */ + mode &= FF_FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND; + res = mount_volume(&path, &fs, mode); + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ +#if !FF_FS_READONLY /* Read/Write configuration */ + if (res == FR_OK) { + if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ + res = FR_INVALID_NAME; + } +#if FF_FS_LOCK + else { + res = chk_share(&dj, (mode & ~FA_READ) ? 1 : 0); /* Check if the file can be used */ + } +#endif + } + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { + if (res != FR_OK) { /* No file, create new */ + if (res == FR_NO_FILE) { /* There is no file to open, create a new entry */ +#if FF_FS_LOCK + res = enq_share() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; +#else + res = dir_register(&dj); +#endif + } + mode |= FA_CREATE_ALWAYS; /* File is created */ + } + else { /* Any object with the same name is already existing */ + if (dj.obj.attr & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ + res = FR_DENIED; + } else { + if (mode & FA_CREATE_NEW) res = FR_EXIST; /* Cannot create as new file */ + } + } + if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate the file if overwrite mode */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + /* Get current allocation info */ + fp->obj.fs = fs; + init_alloc_info(fs, &fp->obj); + /* Set directory entry block initial state */ + memset(fs->dirbuf + 2, 0, 30); /* Clear 85 entry except for NumSec */ + memset(fs->dirbuf + 38, 0, 26); /* Clear C0 entry except for NumName and NameHash */ + fs->dirbuf[XDIR_Attr] = AM_ARC; + st_dword(fs->dirbuf + XDIR_CrtTime, GET_FATTIME()); + fs->dirbuf[XDIR_GenFlags] = 1; + res = store_xdir(&dj); + if (res == FR_OK && fp->obj.sclust != 0) { /* Remove the cluster chain if exist */ + res = remove_chain(&fp->obj, fp->obj.sclust, 0); + fs->last_clst = fp->obj.sclust - 1; /* Reuse the cluster hole */ + } + } else +#endif + { + /* Set directory entry initial state */ + tm = GET_FATTIME(); /* Set created time */ + st_dword(dj.dir + DIR_CrtTime, tm); + st_dword(dj.dir + DIR_ModTime, tm); + cl = ld_clust(fs, dj.dir); /* Get current cluster chain */ + dj.dir[DIR_Attr] = AM_ARC; /* Reset attribute */ + st_clust(fs, dj.dir, 0); /* Reset file allocation info */ + st_dword(dj.dir + DIR_FileSize, 0); + fs->wflag = 1; + if (cl != 0) { /* Remove the cluster chain if exist */ + sc = fs->winsect; + res = remove_chain(&dj.obj, cl, 0); + if (res == FR_OK) { + res = move_window(fs, sc); + fs->last_clst = cl - 1; /* Reuse the cluster hole */ + } + } + } + } + } + else { /* Open an existing file */ + if (res == FR_OK) { /* Is the object exsiting? */ + if (dj.obj.attr & AM_DIR) { /* File open against a directory */ + res = FR_NO_FILE; + } else { + if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* Write mode open against R/O file */ + res = FR_DENIED; + } + } + } + } + if (res == FR_OK) { + if (mode & FA_CREATE_ALWAYS) mode |= FA_MODIFIED; /* Set file change flag if created or overwritten */ + fp->dir_sect = fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dj.dir; +#if FF_FS_LOCK + fp->obj.lockid = inc_share(&dj, (mode & ~FA_READ) ? 1 : 0); /* Lock the file for this session */ + if (fp->obj.lockid == 0) res = FR_INT_ERR; +#endif + } +#else /* R/O configuration */ + if (res == FR_OK) { + if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it origin directory itself? */ + res = FR_INVALID_NAME; + } else { + if (dj.obj.attr & AM_DIR) { /* Is it a directory? */ + res = FR_NO_FILE; + } + } + } +#endif + + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fp->obj.c_scl = dj.obj.sclust; /* Get containing directory info */ + fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; + fp->obj.c_ofs = dj.blk_ofs; + init_alloc_info(fs, &fp->obj); + } else +#endif + { + fp->obj.sclust = ld_clust(fs, dj.dir); /* Get object allocation info */ + fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); + } +#if FF_USE_FASTSEEK + fp->cltbl = 0; /* Disable fast seek mode */ +#endif + fp->obj.fs = fs; /* Validate the file object */ + fp->obj.id = fs->id; + fp->flag = mode; /* Set file access mode */ + fp->err = 0; /* Clear error flag */ + fp->sect = 0; /* Invalidate current data sector */ + fp->fptr = 0; /* Set file pointer top of the file */ +#if !FF_FS_READONLY +#if !FF_FS_TINY + memset(fp->buf, 0, sizeof fp->buf); /* Clear sector buffer */ +#endif + if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) { /* Seek to end of file if FA_OPEN_APPEND is specified */ + fp->fptr = fp->obj.objsize; /* Offset to seek */ + bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */ + clst = fp->obj.sclust; /* Follow the cluster chain */ + for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) { + clst = get_fat(&fp->obj, clst); + if (clst <= 1) res = FR_INT_ERR; + if (clst == 0xFFFFFFFF) res = FR_DISK_ERR; + } + fp->clust = clst; + if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */ + sc = clst2sect(fs, clst); + if (sc == 0) { + res = FR_INT_ERR; + } else { + fp->sect = sc + (DWORD)(ofs / SS(fs)); +#if !FF_FS_TINY + if (disk_read(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR; +#endif + } + } +#if FF_FS_LOCK + if (res != FR_OK) dec_share(fp->obj.lockid); /* Decrement file open counter if seek failed */ +#endif + } +#endif + } + + FREE_NAMBUF(); + } + + if (res != FR_OK) fp->obj.fs = 0; /* Invalidate file object on error */ + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL* fp, /* Open file to be read */ + void* buff, /* Data buffer to store the read data */ + UINT btr, /* Number of bytes to read */ + UINT* br /* Number of bytes read */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst; + LBA_t sect; + FSIZE_t remain; + UINT rcnt, cc, csect; + BYTE *rbuff = (BYTE*)buff; + + + *br = 0; /* Clear read byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + remain = fp->obj.objsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr > 0; btr -= rcnt, *br += rcnt, rbuff += rcnt, fp->fptr += rcnt) { /* Repeat until btr bytes read */ + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + if (csect == 0) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->obj.sclust; /* Follow cluster chain from the origin */ + } else { /* Middle or end of the file */ +#if FF_USE_FASTSEEK + if (fp->cltbl) { + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + } else +#endif + { + clst = get_fat(&fp->obj, fp->clust); /* Follow cluster chain on the FAT */ + } + } + if (clst < 2) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + sect = clst2sect(fs, fp->clust); /* Get current sector */ + if (sect == 0) ABORT(fs, FR_INT_ERR); + sect += csect; + cc = btr / SS(fs); /* When remaining bytes >= sector size, */ + if (cc > 0) { /* Read maximum contiguous sectors directly */ + if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + cc = fs->csize - csect; + } + if (disk_read(fs->pdrv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); +#if !FF_FS_READONLY && FF_FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ +#if FF_FS_TINY + if (fs->wflag && fs->winsect - sect < cc) { + memcpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs)); + } +#else + if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) { + memcpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); + } +#endif +#endif + rcnt = SS(fs) * cc; /* Number of bytes transferred */ + continue; + } +#if !FF_FS_TINY + if (fp->sect != sect) { /* Load data sector if not in cache */ +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ + } +#endif + fp->sect = sect; + } + rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ + if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ +#if FF_FS_TINY + if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ + memcpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ +#else + memcpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ +#endif + } + + LEAVE_FF(fs, FR_OK); +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL* fp, /* Open file to be written */ + const void* buff, /* Data to be written */ + UINT btw, /* Number of bytes to write */ + UINT* bw /* Number of bytes written */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst; + LBA_t sect; + UINT wcnt, cc, csect; + const BYTE *wbuff = (const BYTE*)buff; + + + *bw = 0; /* Clear write byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + /* Check fptr wrap-around (file size cannot reach 4 GiB at FAT volume) */ + if ((!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) { + btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr); + } + + for ( ; btw > 0; btw -= wcnt, *bw += wcnt, wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize) { /* Repeat until all data written */ + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ + if (csect == 0) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->obj.sclust; /* Follow from the origin */ + if (clst == 0) { /* If no cluster is allocated, */ + clst = create_chain(&fp->obj, 0); /* create a new cluster chain */ + } + } else { /* On the middle or end of the file */ +#if FF_USE_FASTSEEK + if (fp->cltbl) { + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + } else +#endif + { + clst = create_chain(&fp->obj, fp->clust); /* Follow or stretch cluster chain on the FAT */ + } + } + if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clst == 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */ + } +#if FF_FS_TINY + if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Write-back sector cache */ +#else + if (fp->flag & FA_DIRTY) { /* Write-back sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + sect = clst2sect(fs, fp->clust); /* Get current sector */ + if (sect == 0) ABORT(fs, FR_INT_ERR); + sect += csect; + cc = btw / SS(fs); /* When remaining bytes >= sector size, */ + if (cc > 0) { /* Write maximum contiguous sectors directly */ + if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + cc = fs->csize - csect; + } + if (disk_write(fs->pdrv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); +#if FF_FS_MINIMIZE <= 2 +#if FF_FS_TINY + if (fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + memcpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs)); + fs->wflag = 0; + } +#else + if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + memcpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs)); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif +#endif + wcnt = SS(fs) * cc; /* Number of bytes transferred */ + continue; + } +#if FF_FS_TINY + if (fp->fptr >= fp->obj.objsize) { /* Avoid silly cache filling on the growing edge */ + if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); + fs->winsect = sect; + } +#else + if (fp->sect != sect && /* Fill sector cache with file data */ + fp->fptr < fp->obj.objsize && + disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } +#endif + fp->sect = sect; + } + wcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ + if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ +#if FF_FS_TINY + if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ + memcpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ + fs->wflag = 1; +#else + memcpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ + fp->flag |= FA_DIRTY; +#endif + } + + fp->flag |= FA_MODIFIED; /* Set file change flag */ + + LEAVE_FF(fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL* fp /* Open file to be synced */ +) +{ + FRESULT res; + FATFS *fs; + DWORD tm; + BYTE *dir; + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res == FR_OK) { + if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */ +#if !FF_FS_TINY + if (fp->flag & FA_DIRTY) { /* Write-back cached data if needed */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + /* Update the directory entry */ + tm = GET_FATTIME(); /* Modified time */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + res = fill_first_frag(&fp->obj); /* Fill first fragment on the FAT if needed */ + if (res == FR_OK) { + res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */ + } + if (res == FR_OK) { + DIR dj; + DEF_NAMBUF + + INIT_NAMBUF(fs); + res = load_obj_xdir(&dj, &fp->obj); /* Load directory entry block */ + if (res == FR_OK) { + fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */ + fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1; /* Update file allocation information */ + st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust); /* Update start cluster */ + st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize); /* Update file size */ + st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize); /* (FatFs does not support Valid File Size feature) */ + st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Update modified time */ + fs->dirbuf[XDIR_ModTime10] = 0; + st_dword(fs->dirbuf + XDIR_AccTime, 0); + res = store_xdir(&dj); /* Restore it to the directory */ + if (res == FR_OK) { + res = sync_fs(fs); + fp->flag &= (BYTE)~FA_MODIFIED; + } + } + FREE_NAMBUF(); + } + } else +#endif + { + res = move_window(fs, fp->dir_sect); + if (res == FR_OK) { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */ + st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation information */ + st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */ + st_dword(dir + DIR_ModTime, tm); /* Update modified time */ + st_word(dir + DIR_LstAccDate, 0); + fs->wflag = 1; + res = sync_fs(fs); /* Restore it to the directory */ + fp->flag &= (BYTE)~FA_MODIFIED; + } + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* !FF_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL* fp /* Open file to be closed */ +) +{ + FRESULT res; + FATFS *fs; + +#if !FF_FS_READONLY + res = f_sync(fp); /* Flush cached data */ + if (res == FR_OK) +#endif + { + res = validate(&fp->obj, &fs); /* Lock volume */ + if (res == FR_OK) { +#if FF_FS_LOCK + res = dec_share(fp->obj.lockid); /* Decrement file open counter */ + if (res == FR_OK) fp->obj.fs = 0; /* Invalidate file object */ +#else + fp->obj.fs = 0; /* Invalidate file object */ +#endif +#if FF_FS_REENTRANT + unlock_volume(fs, FR_OK); /* Unlock volume */ +#endif + } + } + return res; +} + + + + +#if FF_FS_RPATH >= 1 +/*-----------------------------------------------------------------------*/ +/* Change Current Directory or Current Drive, Get Current Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chdrive ( + const TCHAR* path /* Drive number to set */ +) +{ + int vol; + + + /* Get logical drive number */ + vol = get_ldnumber(&path); + if (vol < 0) return FR_INVALID_DRIVE; + CurrVol = (BYTE)vol; /* Set it as current volume */ + + return FR_OK; +} + + + +FRESULT f_chdir ( + const TCHAR* path /* Pointer to the directory path */ +) +{ +#if FF_STR_VOLUME_ID == 2 + UINT i; +#endif + FRESULT res; + DIR dj; + FATFS *fs; + DEF_NAMBUF + + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it the start directory itself? */ + fs->cdir = dj.obj.sclust; +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->cdc_scl = dj.obj.c_scl; + fs->cdc_size = dj.obj.c_size; + fs->cdc_ofs = dj.obj.c_ofs; + } +#endif + } else { + if (dj.obj.attr & AM_DIR) { /* It is a sub-directory */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus); /* Sub-directory cluster */ + fs->cdc_scl = dj.obj.sclust; /* Save containing directory information */ + fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; + fs->cdc_ofs = dj.blk_ofs; + } else +#endif + { + fs->cdir = ld_clust(fs, dj.dir); /* Sub-directory cluster */ + } + } else { + res = FR_NO_PATH; /* Reached but a file */ + } + } + } + FREE_NAMBUF(); + if (res == FR_NO_FILE) res = FR_NO_PATH; +#if FF_STR_VOLUME_ID == 2 /* Also current drive is changed if in Unix style volume ID */ + if (res == FR_OK) { + for (i = FF_VOLUMES - 1; i && fs != FatFs[i]; i--) ; /* Set current drive */ + CurrVol = (BYTE)i; + } +#endif + } + + LEAVE_FF(fs, res); +} + + +#if FF_FS_RPATH >= 2 +FRESULT f_getcwd ( + TCHAR* buff, /* Pointer to the directory path */ + UINT len /* Size of buff in unit of TCHAR */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + UINT i, n; + DWORD ccl; + TCHAR *tp = buff; +#if FF_VOLUMES >= 2 + UINT vl; +#if FF_STR_VOLUME_ID + const char *vp; +#endif +#endif + FILINFO fno; + DEF_NAMBUF + + + /* Get logical drive */ + buff[0] = 0; /* Set null string to get current volume */ + res = mount_volume((const TCHAR**)&buff, &fs, 0); /* Get current volume */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + + /* Follow parent directories and create the path */ + i = len; /* Bottom of buffer (directory stack base) */ + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* (Cannot do getcwd on exFAT and returns root path) */ + dj.obj.sclust = fs->cdir; /* Start to follow upper directory from current directory */ + while ((ccl = dj.obj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ + res = dir_sdi(&dj, 1 * SZDIRE); /* Get parent directory */ + if (res != FR_OK) break; + res = move_window(fs, dj.sect); + if (res != FR_OK) break; + dj.obj.sclust = ld_clust(fs, dj.dir); /* Goto parent directory */ + res = dir_sdi(&dj, 0); + if (res != FR_OK) break; + do { /* Find the entry links to the child directory */ + res = DIR_READ_FILE(&dj); + if (res != FR_OK) break; + if (ccl == ld_clust(fs, dj.dir)) break; /* Found the entry */ + res = dir_next(&dj, 0); + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ + if (res != FR_OK) break; + get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ + for (n = 0; fno.fname[n]; n++) ; /* Name length */ + if (i < n + 1) { /* Insufficient space to store the path name? */ + res = FR_NOT_ENOUGH_CORE; break; + } + while (n) buff[--i] = fno.fname[--n]; /* Stack the name */ + buff[--i] = '/'; + } + } + if (res == FR_OK) { + if (i == len) buff[--i] = '/'; /* Is it the root-directory? */ +#if FF_VOLUMES >= 2 /* Put drive prefix */ + vl = 0; +#if FF_STR_VOLUME_ID >= 1 /* String volume ID */ + for (n = 0, vp = (const char*)VolumeStr[CurrVol]; vp[n]; n++) ; + if (i >= n + 2) { + if (FF_STR_VOLUME_ID == 2) *tp++ = (TCHAR)'/'; + for (vl = 0; vl < n; *tp++ = (TCHAR)vp[vl], vl++) ; + if (FF_STR_VOLUME_ID == 1) *tp++ = (TCHAR)':'; + vl++; + } +#else /* Numeric volume ID */ + if (i >= 3) { + *tp++ = (TCHAR)'0' + CurrVol; + *tp++ = (TCHAR)':'; + vl = 2; + } +#endif + if (vl == 0) res = FR_NOT_ENOUGH_CORE; +#endif + /* Add current directory path */ + if (res == FR_OK) { + do { /* Copy stacked path string */ + *tp++ = buff[i++]; + } while (i < len); + } + } + FREE_NAMBUF(); + } + + *tp = 0; + LEAVE_FF(fs, res); +} + +#endif /* FF_FS_RPATH >= 2 */ +#endif /* FF_FS_RPATH >= 1 */ + + + +#if FF_FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File Read/Write Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL* fp, /* Pointer to the file object */ + FSIZE_t ofs /* File pointer from top of file */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst, bcs; + LBA_t nsect; + FSIZE_t ifptr; +#if FF_USE_FASTSEEK + DWORD cl, pcl, ncl, tcl, tlen, ulen; + DWORD *tbl; + LBA_t dsc; +#endif + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res == FR_OK) res = (FRESULT)fp->err; +#if FF_FS_EXFAT && !FF_FS_READONLY + if (res == FR_OK && fs->fs_type == FS_EXFAT) { + res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */ + } +#endif + if (res != FR_OK) LEAVE_FF(fs, res); + +#if FF_USE_FASTSEEK + if (fp->cltbl) { /* Fast seek */ + if (ofs == CREATE_LINKMAP) { /* Create CLMT */ + tbl = fp->cltbl; + tlen = *tbl++; ulen = 2; /* Given table size and required table size */ + cl = fp->obj.sclust; /* Origin of the chain */ + if (cl != 0) { + do { + /* Get a fragment */ + tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ + do { + pcl = cl; ncl++; + cl = get_fat(&fp->obj, cl); + if (cl <= 1) ABORT(fs, FR_INT_ERR); + if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + } while (cl == pcl + 1); + if (ulen <= tlen) { /* Store the length and top of the fragment */ + *tbl++ = ncl; *tbl++ = tcl; + } + } while (cl < fs->n_fatent); /* Repeat until end of chain */ + } + *fp->cltbl = ulen; /* Number of items used */ + if (ulen <= tlen) { + *tbl = 0; /* Terminate table */ + } else { + res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ + } + } else { /* Fast seek */ + if (ofs > fp->obj.objsize) ofs = fp->obj.objsize; /* Clip offset at the file size */ + fp->fptr = ofs; /* Set file pointer */ + if (ofs > 0) { + fp->clust = clmt_clust(fp, ofs - 1); + dsc = clst2sect(fs, fp->clust); + if (dsc == 0) ABORT(fs, FR_INT_ERR); + dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); + if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ +#if !FF_FS_TINY +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Load current sector */ +#endif + fp->sect = dsc; + } + } + } + } else +#endif + + /* Normal Seek */ + { +#if FF_FS_EXFAT + if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF; /* Clip at 4 GiB - 1 if at FATxx */ +#endif + if (ofs > fp->obj.objsize && (FF_FS_READONLY || !(fp->flag & FA_WRITE))) { /* In read-only mode, clip offset with the file size */ + ofs = fp->obj.objsize; + } + ifptr = fp->fptr; + fp->fptr = nsect = 0; + if (ofs > 0) { + bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->clust; + } else { /* When seek to back cluster, */ + clst = fp->obj.sclust; /* start from the first cluster */ +#if !FF_FS_READONLY + if (clst == 0) { /* If no cluster chain, create a new chain */ + clst = create_chain(&fp->obj, 0); + if (clst == 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->obj.sclust = clst; + } +#endif + fp->clust = clst; + } + if (clst != 0) { + while (ofs > bcs) { /* Cluster following loop */ + ofs -= bcs; fp->fptr += bcs; +#if !FF_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + if (FF_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize to generate FAT value */ + fp->obj.objsize = fp->fptr; + fp->flag |= FA_MODIFIED; + } + clst = create_chain(&fp->obj, clst); /* Follow chain with forceed stretch */ + if (clst == 0) { /* Clip file size in case of disk full */ + ofs = 0; break; + } + } else +#endif + { + clst = get_fat(&fp->obj, clst); /* Follow cluster chain if not in write mode */ + } + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + fp->clust = clst; + } + fp->fptr += ofs; + if (ofs % SS(fs)) { + nsect = clst2sect(fs, clst); /* Current sector */ + if (nsect == 0) ABORT(fs, FR_INT_ERR); + nsect += (DWORD)(ofs / SS(fs)); + } + } + } + if (!FF_FS_READONLY && fp->fptr > fp->obj.objsize) { /* Set file change flag if the file size is extended */ + fp->obj.objsize = fp->fptr; + fp->flag |= FA_MODIFIED; + } + if (fp->fptr % SS(fs) && nsect != fp->sect) { /* Fill sector cache if needed */ +#if !FF_FS_TINY +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ +#endif + fp->sect = nsect; + } + } + + LEAVE_FF(fs, res); +} + + + +#if FF_FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a Directory Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR* dp, /* Pointer to directory object to create */ + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + FATFS *fs; + DEF_NAMBUF + + + if (!dp) return FR_INVALID_OBJECT; + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + if (res == FR_OK) { + dp->obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(dp, path); /* Follow the path to the directory */ + if (res == FR_OK) { /* Follow completed */ + if (!(dp->fn[NSFLAG] & NS_NONAME)) { /* It is not the origin directory itself */ + if (dp->obj.attr & AM_DIR) { /* This object is a sub-directory */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + dp->obj.c_scl = dp->obj.sclust; /* Get containing directory inforamation */ + dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat; + dp->obj.c_ofs = dp->blk_ofs; + init_alloc_info(fs, &dp->obj); /* Get object allocation info */ + } else +#endif + { + dp->obj.sclust = ld_clust(fs, dp->dir); /* Get object allocation info */ + } + } else { /* This object is a file */ + res = FR_NO_PATH; + } + } + if (res == FR_OK) { + dp->obj.id = fs->id; + res = dir_sdi(dp, 0); /* Rewind directory */ +#if FF_FS_LOCK + if (res == FR_OK) { + if (dp->obj.sclust != 0) { + dp->obj.lockid = inc_share(dp, 0); /* Lock the sub directory */ + if (!dp->obj.lockid) res = FR_TOO_MANY_OPEN_FILES; + } else { + dp->obj.lockid = 0; /* Root directory need not to be locked */ + } + } +#endif + } + } + FREE_NAMBUF(); + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + if (res != FR_OK) dp->obj.fs = 0; /* Invalidate the directory object if function failed */ + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Close Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_closedir ( + DIR *dp /* Pointer to the directory object to be closed */ +) +{ + FRESULT res; + FATFS *fs; + + + res = validate(&dp->obj, &fs); /* Check validity of the file object */ + if (res == FR_OK) { +#if FF_FS_LOCK + if (dp->obj.lockid) res = dec_share(dp->obj.lockid); /* Decrement sub-directory open counter */ + if (res == FR_OK) dp->obj.fs = 0; /* Invalidate directory object */ +#else + dp->obj.fs = 0; /* Invalidate directory object */ +#endif +#if FF_FS_REENTRANT + unlock_volume(fs, FR_OK); /* Unlock volume */ +#endif + } + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entries in Sequence */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR* dp, /* Pointer to the open directory object */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + FATFS *fs; + DEF_NAMBUF + + + res = validate(&dp->obj, &fs); /* Check validity of the directory object */ + if (res == FR_OK) { + if (!fno) { + res = dir_sdi(dp, 0); /* Rewind the directory object */ + } else { + INIT_NAMBUF(fs); + res = DIR_READ_FILE(dp); /* Read an item */ + if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */ + if (res == FR_OK) { /* A valid entry is found */ + get_fileinfo(dp, fno); /* Get the object information */ + res = dir_next(dp, 0); /* Increment index for next */ + if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */ + } + FREE_NAMBUF(); + } + } + LEAVE_FF(fs, res); +} + + + +#if FF_USE_FIND +/*-----------------------------------------------------------------------*/ +/* Find Next File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_findnext ( + DIR* dp, /* Pointer to the open directory object */ + FILINFO* fno /* Pointer to the file information structure */ +) +{ + FRESULT res; + + + for (;;) { + res = f_readdir(dp, fno); /* Get a directory item */ + if (res != FR_OK || !fno || !fno->fname[0]) break; /* Terminate if any error or end of directory */ + if (pattern_match(dp->pat, fno->fname, 0, FIND_RECURS)) break; /* Test for the file name */ +#if FF_USE_LFN && FF_USE_FIND == 2 + if (pattern_match(dp->pat, fno->altname, 0, FIND_RECURS)) break; /* Test for alternative name if exist */ +#endif + } + return res; +} + + + +/*-----------------------------------------------------------------------*/ +/* Find First File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_findfirst ( + DIR* dp, /* Pointer to the blank directory object */ + FILINFO* fno, /* Pointer to the file information structure */ + const TCHAR* path, /* Pointer to the directory to open */ + const TCHAR* pattern /* Pointer to the matching pattern */ +) +{ + FRESULT res; + + + dp->pat = pattern; /* Save pointer to pattern string */ + res = f_opendir(dp, path); /* Open the target directory */ + if (res == FR_OK) { + res = f_findnext(dp, fno); /* Find the first item */ + } + return res; +} + +#endif /* FF_USE_FIND */ + + + +#if FF_FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const TCHAR* path, /* Pointer to the file path */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMBUF + + + /* Get logical drive */ + res = mount_volume(&path, &dj.obj.fs, 0); + if (res == FR_OK) { + INIT_NAMBUF(dj.obj.fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */ + res = FR_INVALID_NAME; + } else { /* Found an object */ + if (fno) get_fileinfo(&dj, fno); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(dj.obj.fs, res); +} + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const TCHAR* path, /* Logical drive number */ + DWORD* nclst, /* Pointer to a variable to return number of free clusters */ + FATFS** fatfs /* Pointer to return pointer to corresponding filesystem object */ +) +{ + FRESULT res; + FATFS *fs; + DWORD nfree, clst, stat; + LBA_t sect; + UINT i; + FFOBJID obj; + + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + if (res == FR_OK) { + *fatfs = fs; /* Return ptr to the fs object */ + /* If free_clst is valid, return it without full FAT scan */ + if (fs->free_clst <= fs->n_fatent - 2) { + *nclst = fs->free_clst; + } else { + /* Scan FAT to obtain number of free clusters */ + nfree = 0; + if (fs->fs_type == FS_FAT12) { /* FAT12: Scan bit field FAT entries */ + clst = 2; obj.fs = fs; + do { + stat = get_fat(&obj, clst); + if (stat == 0xFFFFFFFF) { + res = FR_DISK_ERR; break; + } + if (stat == 1) { + res = FR_INT_ERR; break; + } + if (stat == 0) nfree++; + } while (++clst < fs->n_fatent); + } else { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* exFAT: Scan allocation bitmap */ + BYTE bm; + UINT b; + + clst = fs->n_fatent - 2; /* Number of clusters */ + sect = fs->bitbase; /* Bitmap sector */ + i = 0; /* Offset in the sector */ + do { /* Counts numbuer of bits with zero in the bitmap */ + if (i == 0) { /* New sector? */ + res = move_window(fs, sect++); + if (res != FR_OK) break; + } + for (b = 8, bm = ~fs->win[i]; b && clst; b--, clst--) { + nfree += bm & 1; + bm >>= 1; + } + i = (i + 1) % SS(fs); + } while (clst); + } else +#endif + { /* FAT16/32: Scan WORD/DWORD FAT entries */ + clst = fs->n_fatent; /* Number of entries */ + sect = fs->fatbase; /* Top of the FAT */ + i = 0; /* Offset in the sector */ + do { /* Counts numbuer of entries with zero in the FAT */ + if (i == 0) { /* New sector? */ + res = move_window(fs, sect++); + if (res != FR_OK) break; + } + if (fs->fs_type == FS_FAT16) { + if (ld_word(fs->win + i) == 0) nfree++; + i += 2; + } else { + if ((ld_dword(fs->win + i) & 0x0FFFFFFF) == 0) nfree++; + i += 4; + } + i %= SS(fs); + } while (--clst); + } + } + if (res == FR_OK) { /* Update parameters if succeeded */ + *nclst = nfree; /* Return the free clusters */ + fs->free_clst = nfree; /* Now free_clst is valid */ + fs->fsi_flag |= 1; /* FAT32: FSInfo is to be updated */ + } + } + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL* fp /* Pointer to the file object */ +) +{ + FRESULT res; + FATFS *fs; + DWORD ncl; + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + if (fp->fptr < fp->obj.objsize) { /* Process when fptr is not on the eof */ + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain(&fp->obj, fp->obj.sclust, 0); + fp->obj.sclust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat(&fp->obj, fp->clust); + res = FR_OK; + if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (ncl == 1) res = FR_INT_ERR; + if (res == FR_OK && ncl < fs->n_fatent) { + res = remove_chain(&fp->obj, ncl, fp->clust); + } + } + fp->obj.objsize = fp->fptr; /* Set file size to current read/write point */ + fp->flag |= FA_MODIFIED; +#if !FF_FS_TINY + if (res == FR_OK && (fp->flag & FA_DIRTY)) { + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { + res = FR_DISK_ERR; + } else { + fp->flag &= (BYTE)~FA_DIRTY; + } + } +#endif + if (res != FR_OK) ABORT(fs, res); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const TCHAR* path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + FATFS *fs; + DIR dj, sdj; + DWORD dclst = 0; +#if FF_FS_EXFAT + FFOBJID obj; +#endif + DEF_NAMBUF + + + /* Get logical drive */ + res = mount_volume(&path, &fs, FA_WRITE); + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (FF_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) { + res = FR_INVALID_NAME; /* Cannot remove dot entry */ + } +#if FF_FS_LOCK + if (res == FR_OK) res = chk_share(&dj, 2); /* Check if it is an open object */ +#endif + if (res == FR_OK) { /* The object is accessible */ + if (dj.fn[NSFLAG] & NS_NONAME) { + res = FR_INVALID_NAME; /* Cannot remove the origin directory */ + } else { + if (dj.obj.attr & AM_RDO) { + res = FR_DENIED; /* Cannot remove R/O object */ + } + } + if (res == FR_OK) { +#if FF_FS_EXFAT + obj.fs = fs; + if (fs->fs_type == FS_EXFAT) { + init_alloc_info(fs, &obj); + dclst = obj.sclust; + } else +#endif + { + dclst = ld_clust(fs, dj.dir); + } + if (dj.obj.attr & AM_DIR) { /* Is it a sub-directory? */ +#if FF_FS_RPATH != 0 + if (dclst == fs->cdir) { /* Is it the current directory? */ + res = FR_DENIED; + } else +#endif + { + sdj.obj.fs = fs; /* Open the sub-directory */ + sdj.obj.sclust = dclst; +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + sdj.obj.objsize = obj.objsize; + sdj.obj.stat = obj.stat; + } +#endif + res = dir_sdi(&sdj, 0); + if (res == FR_OK) { + res = DIR_READ_FILE(&sdj); /* Test if the directory is empty */ + if (res == FR_OK) res = FR_DENIED; /* Not empty? */ + if (res == FR_NO_FILE) res = FR_OK; /* Empty? */ + } + } + } + } + if (res == FR_OK) { + res = dir_remove(&dj); /* Remove the directory entry */ + if (res == FR_OK && dclst != 0) { /* Remove the cluster chain if exist */ +#if FF_FS_EXFAT + res = remove_chain(&obj, dclst, 0); +#else + res = remove_chain(&dj.obj, dclst, 0); +#endif + } + if (res == FR_OK) res = sync_fs(fs); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + FATFS *fs; + DIR dj; + FFOBJID sobj; + DWORD dcl, pcl, tm; + DEF_NAMBUF + + + res = mount_volume(&path, &fs, FA_WRITE); /* Get logical drive */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) res = FR_EXIST; /* Name collision? */ + if (FF_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) { /* Invalid name? */ + res = FR_INVALID_NAME; + } + if (res == FR_NO_FILE) { /* It is clear to create a new directory */ + sobj.fs = fs; /* New object id to create a new chain */ + dcl = create_chain(&sobj, 0); /* Allocate a cluster for the new directory */ + res = FR_OK; + if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster? */ + if (dcl == 1) res = FR_INT_ERR; /* Any insanity? */ + if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; /* Disk error? */ + tm = GET_FATTIME(); + if (res == FR_OK) { + res = dir_clear(fs, dcl); /* Clean up the new table */ + if (res == FR_OK) { + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* Create dot entries (FAT only) */ + memset(fs->win + DIR_Name, ' ', 11); /* Create "." entry */ + fs->win[DIR_Name] = '.'; + fs->win[DIR_Attr] = AM_DIR; + st_dword(fs->win + DIR_ModTime, tm); + st_clust(fs, fs->win, dcl); + memcpy(fs->win + SZDIRE, fs->win, SZDIRE); /* Create ".." entry */ + fs->win[SZDIRE + 1] = '.'; pcl = dj.obj.sclust; + st_clust(fs, fs->win + SZDIRE, pcl); + fs->wflag = 1; + } + res = dir_register(&dj); /* Register the object to the parent directoy */ + } + } + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* Initialize directory entry block */ + st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Created time */ + st_dword(fs->dirbuf + XDIR_FstClus, dcl); /* Table start cluster */ + st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)fs->csize * SS(fs)); /* Directory size needs to be valid */ + st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)fs->csize * SS(fs)); + fs->dirbuf[XDIR_GenFlags] = 3; /* Initialize the object flag */ + fs->dirbuf[XDIR_Attr] = AM_DIR; /* Attribute */ + res = store_xdir(&dj); + } else +#endif + { + st_dword(dj.dir + DIR_ModTime, tm); /* Created time */ + st_clust(fs, dj.dir, dcl); /* Table start cluster */ + dj.dir[DIR_Attr] = AM_DIR; /* Attribute */ + fs->wflag = 1; + } + if (res == FR_OK) { + res = sync_fs(fs); + } + } else { + remove_chain(&sobj, dcl, 0); /* Could not register, remove the allocated cluster */ + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename a File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const TCHAR* path_old, /* Pointer to the object name to be renamed */ + const TCHAR* path_new /* Pointer to the new name */ +) +{ + FRESULT res; + FATFS *fs; + DIR djo, djn; + BYTE buf[FF_FS_EXFAT ? SZDIRE * 2 : SZDIRE], *dir; + LBA_t sect; + DEF_NAMBUF + + + get_ldnumber(&path_new); /* Snip the drive number of new name off */ + res = mount_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */ + if (res == FR_OK) { + djo.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&djo, path_old); /* Check old object */ + if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check validity of name */ +#if FF_FS_LOCK + if (res == FR_OK) { + res = chk_share(&djo, 2); + } +#endif + if (res == FR_OK) { /* Object to be renamed is found */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* At exFAT volume */ + BYTE nf, nn; + WORD nh; + + memcpy(buf, fs->dirbuf, SZDIRE * 2); /* Save 85+C0 entry of old object */ + memcpy(&djn, &djo, sizeof djo); + res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ + if (res == FR_OK) { /* Is new name already in use by any other object? */ + res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; + } + if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName]; + nh = ld_word(fs->dirbuf + XDIR_NameHash); + memcpy(fs->dirbuf, buf, SZDIRE * 2); /* Restore 85+C0 entry */ + fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn; + st_word(fs->dirbuf + XDIR_NameHash, nh); + if (!(fs->dirbuf[XDIR_Attr] & AM_DIR)) fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ +/* Start of critical section where an interruption can cause a cross-link */ + res = store_xdir(&djn); + } + } + } else +#endif + { /* At FAT/FAT32 volume */ + memcpy(buf, djo.dir, SZDIRE); /* Save directory entry of the object */ + memcpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */ + res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ + if (res == FR_OK) { /* Is new name already in use by any other object? */ + res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; + } + if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + dir = djn.dir; /* Copy directory entry of the object except name */ + memcpy(dir + 13, buf + 13, SZDIRE - 13); + dir[DIR_Attr] = buf[DIR_Attr]; + if (!(dir[DIR_Attr] & AM_DIR)) dir[DIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ + fs->wflag = 1; + if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the sub-directory if needed */ + sect = clst2sect(fs, ld_clust(fs, dir)); + if (sect == 0) { + res = FR_INT_ERR; + } else { +/* Start of critical section where an interruption can cause a cross-link */ + res = move_window(fs, sect); + dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */ + if (res == FR_OK && dir[1] == '.') { + st_clust(fs, dir, djn.obj.sclust); + fs->wflag = 1; + } + } + } + } + } + } + if (res == FR_OK) { + res = dir_remove(&djo); /* Remove old entry */ + if (res == FR_OK) { + res = sync_fs(fs); + } + } +/* End of the critical section */ + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_FS_MINIMIZE == 0 */ +#endif /* FF_FS_MINIMIZE <= 1 */ +#endif /* FF_FS_MINIMIZE <= 2 */ + + + +#if FF_USE_CHMOD && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Change Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const TCHAR* path, /* Pointer to the file path */ + BYTE attr, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + FATFS *fs; + DIR dj; + DEF_NAMBUF + + + res = mount_volume(&path, &fs, FA_WRITE); /* Get logical drive */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ + if (res == FR_OK) { + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + res = store_xdir(&dj); + } else +#endif + { + dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + fs->wflag = 1; + } + if (res == FR_OK) { + res = sync_fs(fs); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const TCHAR* path, /* Pointer to the file/directory name */ + const FILINFO* fno /* Pointer to the timestamp to be set */ +) +{ + FRESULT res; + FATFS *fs; + DIR dj; + DEF_NAMBUF + + + res = mount_volume(&path, &fs, FA_WRITE); /* Get logical drive */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); + res = store_xdir(&dj); + } else +#endif + { + st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); + fs->wflag = 1; + } + if (res == FR_OK) { + res = sync_fs(fs); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + +#endif /* FF_USE_CHMOD && !FF_FS_READONLY */ + + + +#if FF_USE_LABEL +/*-----------------------------------------------------------------------*/ +/* Get Volume Label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getlabel ( + const TCHAR* path, /* Logical drive number */ + TCHAR* label, /* Buffer to store the volume label */ + DWORD* vsn /* Variable to store the volume serial number */ +) +{ + FRESULT res; + FATFS *fs; + DIR dj; + UINT si, di; + WCHAR wc; + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + + /* Get volume label */ + if (res == FR_OK && label) { + dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = DIR_READ_LABEL(&dj); /* Find a volume label entry */ + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + WCHAR hs; + UINT nw; + + for (si = di = hs = 0; si < dj.dir[XDIR_NumLabel]; si++) { /* Extract volume label from 83 entry */ + wc = ld_word(dj.dir + XDIR_Label + si * 2); + if (hs == 0 && IsSurrogate(wc)) { /* Is the code a surrogate? */ + hs = wc; continue; + } + nw = put_utf((DWORD)hs << 16 | wc, &label[di], 4); /* Store it in API encoding */ + if (nw == 0) { /* Encode error? */ + di = 0; break; + } + di += nw; + hs = 0; + } + if (hs != 0) di = 0; /* Broken surrogate pair? */ + label[di] = 0; + } else +#endif + { + si = di = 0; /* Extract volume label from AM_VOL entry */ + while (si < 11) { + wc = dj.dir[si++]; +#if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode output */ + if (dbc_1st((BYTE)wc) && si < 11) wc = wc << 8 | dj.dir[si++]; /* Is it a DBC? */ + wc = ff_oem2uni(wc, CODEPAGE); /* Convert it into Unicode */ + if (wc == 0) { /* Invalid char in current code page? */ + di = 0; break; + } + di += put_utf(wc, &label[di], 4); /* Store it in Unicode */ +#else /* ANSI/OEM output */ + label[di++] = (TCHAR)wc; +#endif + } + do { /* Truncate trailing spaces */ + label[di] = 0; + if (di == 0) break; + } while (label[--di] == ' '); + } + } + } + if (res == FR_NO_FILE) { /* No label entry and return nul string */ + label[0] = 0; + res = FR_OK; + } + } + + /* Get volume serial number */ + if (res == FR_OK && vsn) { + res = move_window(fs, fs->volbase); + if (res == FR_OK) { + switch (fs->fs_type) { + case FS_EXFAT: + di = BPB_VolIDEx; + break; + + case FS_FAT32: + di = BS_VolID32; + break; + + default: + di = BS_VolID; + } + *vsn = ld_dword(fs->win + di); + } + } + + LEAVE_FF(fs, res); +} + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Set Volume Label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_setlabel ( + const TCHAR* label /* Volume label to set with heading logical drive number */ +) +{ + FRESULT res; + FATFS *fs; + DIR dj; + BYTE dirvn[22]; + UINT di; + WCHAR wc; + static const char badchr[18] = "+.,;=[]" "/*:<>|\\\"\?\x7F"; /* [0..16] for FAT, [7..16] for exFAT */ +#if FF_USE_LFN + DWORD dc; +#endif + + /* Get logical drive */ + res = mount_volume(&label, &fs, FA_WRITE); + if (res != FR_OK) LEAVE_FF(fs, res); + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + memset(dirvn, 0, 22); + di = 0; + while ((UINT)*label >= ' ') { /* Create volume label */ + dc = tchar2uni(&label); /* Get a Unicode character */ + if (dc >= 0x10000) { + if (dc == 0xFFFFFFFF || di >= 10) { /* Wrong surrogate or buffer overflow */ + dc = 0; + } else { + st_word(dirvn + di * 2, (WCHAR)(dc >> 16)); di++; + } + } + if (dc == 0 || strchr(&badchr[7], (int)dc) || di >= 11) { /* Check validity of the volume label */ + LEAVE_FF(fs, FR_INVALID_NAME); + } + st_word(dirvn + di * 2, (WCHAR)dc); di++; + } + } else +#endif + { /* On the FAT/FAT32 volume */ + memset(dirvn, ' ', 11); + di = 0; + while ((UINT)*label >= ' ') { /* Create volume label */ +#if FF_USE_LFN + dc = tchar2uni(&label); + wc = (dc < 0x10000) ? ff_uni2oem(ff_wtoupper(dc), CODEPAGE) : 0; +#else /* ANSI/OEM input */ + wc = (BYTE)*label++; + if (dbc_1st((BYTE)wc)) wc = dbc_2nd((BYTE)*label) ? wc << 8 | (BYTE)*label++ : 0; + if (IsLower(wc)) wc -= 0x20; /* To upper ASCII characters */ +#if FF_CODE_PAGE == 0 + if (ExCvt && wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ +#elif FF_CODE_PAGE < 900 + if (wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ +#endif +#endif + if (wc == 0 || strchr(&badchr[0], (int)wc) || di >= (UINT)((wc >= 0x100) ? 10 : 11)) { /* Reject invalid characters for volume label */ + LEAVE_FF(fs, FR_INVALID_NAME); + } + if (wc >= 0x100) dirvn[di++] = (BYTE)(wc >> 8); + dirvn[di++] = (BYTE)wc; + } + if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME); /* Reject illegal name (heading DDEM) */ + while (di && dirvn[di - 1] == ' ') di--; /* Snip trailing spaces */ + } + + /* Set volume label */ + dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = DIR_READ_LABEL(&dj); /* Get volume label entry */ + if (res == FR_OK) { + if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { + dj.dir[XDIR_NumLabel] = (BYTE)di; /* Change the volume label */ + memcpy(dj.dir + XDIR_Label, dirvn, 22); + } else { + if (di != 0) { + memcpy(dj.dir, dirvn, 11); /* Change the volume label */ + } else { + dj.dir[DIR_Name] = DDEM; /* Remove the volume label */ + } + } + fs->wflag = 1; + res = sync_fs(fs); + } else { /* No volume label entry or an error */ + if (res == FR_NO_FILE) { + res = FR_OK; + if (di != 0) { /* Create a volume label entry */ + res = dir_alloc(&dj, 1); /* Allocate an entry */ + if (res == FR_OK) { + memset(dj.dir, 0, SZDIRE); /* Clean the entry */ + if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { + dj.dir[XDIR_Type] = ET_VLABEL; /* Create volume label entry */ + dj.dir[XDIR_NumLabel] = (BYTE)di; + memcpy(dj.dir + XDIR_Label, dirvn, 22); + } else { + dj.dir[DIR_Attr] = AM_VOL; /* Create volume label entry */ + memcpy(dj.dir, dirvn, 11); + } + fs->wflag = 1; + res = sync_fs(fs); + } + } + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_USE_LABEL */ + + + +#if FF_USE_EXPAND && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Allocate a Contiguous Blocks to the File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_expand ( + FIL* fp, /* Pointer to the file object */ + FSIZE_t fsz, /* File size to be expanded to */ + BYTE opt /* Operation mode 0:Find and prepare or 1:Find and allocate */ +) +{ + FRESULT res; + FATFS *fs; + DWORD n, clst, stcl, scl, ncl, tcl, lclst; + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); +#if FF_FS_EXFAT + if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED); /* Check if in size limit */ +#endif + n = (DWORD)fs->csize * SS(fs); /* Cluster size */ + tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0); /* Number of clusters required */ + stcl = fs->last_clst; lclst = 0; + if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2; + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + scl = find_bitmap(fs, stcl, tcl); /* Find a contiguous cluster block */ + if (scl == 0) res = FR_DENIED; /* No contiguous cluster block was found */ + if (scl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) { /* A contiguous free area is found */ + if (opt) { /* Allocate it now */ + res = change_bitmap(fs, scl, tcl, 1); /* Mark the cluster block 'in use' */ + lclst = scl + tcl - 1; + } else { /* Set it as suggested point for next allocation */ + lclst = scl - 1; + } + } + } else +#endif + { + scl = clst = stcl; ncl = 0; + for (;;) { /* Find a contiguous cluster block */ + n = get_fat(&fp->obj, clst); + if (++clst >= fs->n_fatent) clst = 2; + if (n == 1) { + res = FR_INT_ERR; break; + } + if (n == 0xFFFFFFFF) { + res = FR_DISK_ERR; break; + } + if (n == 0) { /* Is it a free cluster? */ + if (++ncl == tcl) break; /* Break if a contiguous cluster block is found */ + } else { + scl = clst; ncl = 0; /* Not a free cluster */ + } + if (clst == stcl) { /* No contiguous cluster? */ + res = FR_DENIED; break; + } + } + if (res == FR_OK) { /* A contiguous free area is found */ + if (opt) { /* Allocate it now */ + for (clst = scl, n = tcl; n; clst++, n--) { /* Create a cluster chain on the FAT */ + res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1); + if (res != FR_OK) break; + lclst = clst; + } + } else { /* Set it as suggested point for next allocation */ + lclst = scl - 1; + } + } + } + + if (res == FR_OK) { + fs->last_clst = lclst; /* Set suggested start cluster to start next */ + if (opt) { /* Is it allocated now? */ + fp->obj.sclust = scl; /* Update object allocation information */ + fp->obj.objsize = fsz; + if (FF_FS_EXFAT) fp->obj.stat = 2; /* Set status 'contiguous chain' */ + fp->flag |= FA_MODIFIED; + if (fs->free_clst <= fs->n_fatent - 2) { /* Update FSINFO */ + fs->free_clst -= tcl; + fs->fsi_flag |= 1; + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* FF_USE_EXPAND && !FF_FS_READONLY */ + + + +#if FF_USE_FORWARD +/*-----------------------------------------------------------------------*/ +/* Forward Data to the Stream Directly */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_forward ( + FIL* fp, /* Pointer to the file object */ + UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + UINT btf, /* Number of bytes to forward */ + UINT* bf /* Pointer to number of bytes forwarded */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst; + LBA_t sect; + FSIZE_t remain; + UINT rcnt, csect; + BYTE *dbuf; + + + *bf = 0; /* Clear transfer byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + remain = fp->obj.objsize - fp->fptr; + if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ + + for ( ; btf > 0 && (*func)(0, 0); fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { /* Repeat until all data transferred or stream goes busy */ + csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + if (csect == 0) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->obj.sclust : get_fat(&fp->obj, fp->clust); + if (clst <= 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + } + sect = clst2sect(fs, fp->clust); /* Get current data sector */ + if (sect == 0) ABORT(fs, FR_INT_ERR); + sect += csect; +#if FF_FS_TINY + if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window to the file data */ + dbuf = fs->win; +#else + if (fp->sect != sect) { /* Fill sector cache with file data */ +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + } + dbuf = fp->buf; +#endif + fp->sect = sect; + rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ + if (rcnt > btf) rcnt = btf; /* Clip it by btr if needed */ + rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt); /* Forward the file data */ + if (rcnt == 0) ABORT(fs, FR_INT_ERR); + } + + LEAVE_FF(fs, FR_OK); +} +#endif /* FF_USE_FORWARD */ + + + +#if !FF_FS_READONLY && FF_USE_MKFS +/*-----------------------------------------------------------------------*/ +/* Create FAT/exFAT volume (with sub-functions) */ +/*-----------------------------------------------------------------------*/ + +#define N_SEC_TRACK 63 /* Sectors per track for determination of drive CHS */ +#define GPT_ALIGN 0x100000 /* Alignment of partitions in GPT [byte] (>=128KB) */ +#define GPT_ITEMS 128 /* Number of GPT table size (>=128, sector aligned) */ + + +/* Create partitions on the physical drive in format of MBR or GPT */ + +static FRESULT create_partition ( + BYTE drv, /* Physical drive number */ + const LBA_t plst[], /* Partition list */ + BYTE sys, /* System ID for each partition (for only MBR) */ + BYTE *buf /* Working buffer for a sector */ +) +{ + UINT i, cy; + LBA_t sz_drv; + DWORD sz_drv32, nxt_alloc32, sz_part32; + BYTE *pte; + BYTE hd, n_hd, sc, n_sc; + + /* Get physical drive size */ + if (disk_ioctl(drv, GET_SECTOR_COUNT, &sz_drv) != RES_OK) return FR_DISK_ERR; + +#if FF_LBA64 + if (sz_drv >= FF_MIN_GPT) { /* Create partitions in GPT format */ + WORD ss; + UINT sz_ptbl, pi, si, ofs; + DWORD bcc, rnd, align; + QWORD nxt_alloc, sz_part, sz_pool, top_bpt; + static const BYTE gpt_mbr[16] = {0x00, 0x00, 0x02, 0x00, 0xEE, 0xFE, 0xFF, 0x00, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF}; + +#if FF_MAX_SS != FF_MIN_SS + if (disk_ioctl(drv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; /* Get sector size */ + if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; +#else + ss = FF_MAX_SS; +#endif + rnd = (DWORD)sz_drv + GET_FATTIME(); /* Random seed */ + align = GPT_ALIGN / ss; /* Partition alignment for GPT [sector] */ + sz_ptbl = GPT_ITEMS * SZ_GPTE / ss; /* Size of partition table [sector] */ + top_bpt = sz_drv - sz_ptbl - 1; /* Backup partition table start sector */ + nxt_alloc = 2 + sz_ptbl; /* First allocatable sector */ + sz_pool = top_bpt - nxt_alloc; /* Size of allocatable area */ + bcc = 0xFFFFFFFF; sz_part = 1; + pi = si = 0; /* partition table index, size table index */ + do { + if (pi * SZ_GPTE % ss == 0) memset(buf, 0, ss); /* Clean the buffer if needed */ + if (sz_part != 0) { /* Is the size table not termintated? */ + nxt_alloc = (nxt_alloc + align - 1) & ((QWORD)0 - align); /* Align partition start */ + sz_part = plst[si++]; /* Get a partition size */ + if (sz_part <= 100) { /* Is the size in percentage? */ + sz_part = sz_pool * sz_part / 100; + sz_part = (sz_part + align - 1) & ((QWORD)0 - align); /* Align partition end (only if in percentage) */ + } + if (nxt_alloc + sz_part > top_bpt) { /* Clip the size at end of the pool */ + sz_part = (nxt_alloc < top_bpt) ? top_bpt - nxt_alloc : 0; + } + } + if (sz_part != 0) { /* Add a partition? */ + ofs = pi * SZ_GPTE % ss; + memcpy(buf + ofs + GPTE_PtGuid, GUID_MS_Basic, 16); /* Set partition GUID (Microsoft Basic Data) */ + rnd = make_rand(rnd, buf + ofs + GPTE_UpGuid, 16); /* Set unique partition GUID */ + st_qword(buf + ofs + GPTE_FstLba, nxt_alloc); /* Set partition start sector */ + st_qword(buf + ofs + GPTE_LstLba, nxt_alloc + sz_part - 1); /* Set partition end sector */ + nxt_alloc += sz_part; /* Next allocatable sector */ + } + if ((pi + 1) * SZ_GPTE % ss == 0) { /* Write the buffer if it is filled up */ + for (i = 0; i < ss; bcc = crc32(bcc, buf[i++])) ; /* Calculate table check sum */ + if (disk_write(drv, buf, 2 + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR; /* Write to primary table */ + if (disk_write(drv, buf, top_bpt + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR; /* Write to secondary table */ + } + } while (++pi < GPT_ITEMS); + + /* Create primary GPT header */ + memset(buf, 0, ss); + memcpy(buf + GPTH_Sign, "EFI PART" "\0\0\1\0" "\x5C\0\0", 16); /* Signature, version (1.0) and size (92) */ + st_dword(buf + GPTH_PtBcc, ~bcc); /* Table check sum */ + st_qword(buf + GPTH_CurLba, 1); /* LBA of this header */ + st_qword(buf + GPTH_BakLba, sz_drv - 1); /* LBA of secondary header */ + st_qword(buf + GPTH_FstLba, 2 + sz_ptbl); /* LBA of first allocatable sector */ + st_qword(buf + GPTH_LstLba, top_bpt - 1); /* LBA of last allocatable sector */ + st_dword(buf + GPTH_PteSize, SZ_GPTE); /* Size of a table entry */ + st_dword(buf + GPTH_PtNum, GPT_ITEMS); /* Number of table entries */ + st_dword(buf + GPTH_PtOfs, 2); /* LBA of this table */ + rnd = make_rand(rnd, buf + GPTH_DskGuid, 16); /* Disk GUID */ + for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ; /* Calculate header check sum */ + st_dword(buf + GPTH_Bcc, ~bcc); /* Header check sum */ + if (disk_write(drv, buf, 1, 1) != RES_OK) return FR_DISK_ERR; + + /* Create secondary GPT header */ + st_qword(buf + GPTH_CurLba, sz_drv - 1); /* LBA of this header */ + st_qword(buf + GPTH_BakLba, 1); /* LBA of primary header */ + st_qword(buf + GPTH_PtOfs, top_bpt); /* LBA of this table */ + st_dword(buf + GPTH_Bcc, 0); + for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ; /* Calculate header check sum */ + st_dword(buf + GPTH_Bcc, ~bcc); /* Header check sum */ + if (disk_write(drv, buf, sz_drv - 1, 1) != RES_OK) return FR_DISK_ERR; + + /* Create protective MBR */ + memset(buf, 0, ss); + memcpy(buf + MBR_Table, gpt_mbr, 16); /* Create a GPT partition */ + st_word(buf + BS_55AA, 0xAA55); + if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; + + } else +#endif + { /* Create partitions in MBR format */ + sz_drv32 = (DWORD)sz_drv; + n_sc = N_SEC_TRACK; /* Determine drive CHS without any consideration of the drive geometry */ + for (n_hd = 8; n_hd != 0 && sz_drv32 / n_hd / n_sc > 1024; n_hd *= 2) ; + if (n_hd == 0) n_hd = 255; /* Number of heads needs to be <256 */ + + memset(buf, 0, FF_MAX_SS); /* Clear MBR */ + pte = buf + MBR_Table; /* Partition table in the MBR */ + for (i = 0, nxt_alloc32 = n_sc; i < 4 && nxt_alloc32 != 0 && nxt_alloc32 < sz_drv32; i++, nxt_alloc32 += sz_part32) { + sz_part32 = (DWORD)plst[i]; /* Get partition size */ + if (sz_part32 <= 100) sz_part32 = (sz_part32 == 100) ? sz_drv32 : sz_drv32 / 100 * sz_part32; /* Size in percentage? */ + if (nxt_alloc32 + sz_part32 > sz_drv32 || nxt_alloc32 + sz_part32 < nxt_alloc32) sz_part32 = sz_drv32 - nxt_alloc32; /* Clip at drive size */ + if (sz_part32 == 0) break; /* End of table or no sector to allocate? */ + + st_dword(pte + PTE_StLba, nxt_alloc32); /* Start LBA */ + st_dword(pte + PTE_SizLba, sz_part32); /* Number of sectors */ + pte[PTE_System] = sys; /* System type */ + + cy = (UINT)(nxt_alloc32 / n_sc / n_hd); /* Start cylinder */ + hd = (BYTE)(nxt_alloc32 / n_sc % n_hd); /* Start head */ + sc = (BYTE)(nxt_alloc32 % n_sc + 1); /* Start sector */ + pte[PTE_StHead] = hd; + pte[PTE_StSec] = (BYTE)((cy >> 2 & 0xC0) | sc); + pte[PTE_StCyl] = (BYTE)cy; + + cy = (UINT)((nxt_alloc32 + sz_part32 - 1) / n_sc / n_hd); /* End cylinder */ + hd = (BYTE)((nxt_alloc32 + sz_part32 - 1) / n_sc % n_hd); /* End head */ + sc = (BYTE)((nxt_alloc32 + sz_part32 - 1) % n_sc + 1); /* End sector */ + pte[PTE_EdHead] = hd; + pte[PTE_EdSec] = (BYTE)((cy >> 2 & 0xC0) | sc); + pte[PTE_EdCyl] = (BYTE)cy; + + pte += SZ_PTE; /* Next entry */ + } + + st_word(buf + BS_55AA, 0xAA55); /* MBR signature */ + if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the MBR */ + } + + return FR_OK; +} + + + +FRESULT f_mkfs ( + const TCHAR* path, /* Logical drive number */ + const MKFS_PARM* opt, /* Format options */ + void* work, /* Pointer to working buffer (null: use len bytes of heap memory) */ + UINT len /* Size of working buffer [byte] */ +) +{ + static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0}; /* Cluster size boundary for FAT volume (4Ks unit) */ + static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0}; /* Cluster size boundary for FAT32 volume (128Ks unit) */ + static const MKFS_PARM defopt = {FM_ANY, 0, 0, 0, 0}; /* Default parameter */ + BYTE fsopt, fsty, sys, pdrv, ipart; + BYTE *buf; + BYTE *pte; + WORD ss; /* Sector size */ + DWORD sz_buf, sz_blk, n_clst, pau, nsect, n, vsn; + LBA_t sz_vol, b_vol, b_fat, b_data; /* Size of volume, Base LBA of volume, fat, data */ + LBA_t sect, lba[2]; + DWORD sz_rsv, sz_fat, sz_dir, sz_au; /* Size of reserved, fat, dir, data, cluster */ + UINT n_fat, n_root, i; /* Index, Number of FATs and Number of roor dir entries */ + int vol; + DSTATUS ds; + FRESULT res; + + + /* Check mounted drive and clear work area */ + vol = get_ldnumber(&path); /* Get target logical drive */ + if (vol < 0) return FR_INVALID_DRIVE; + if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the fs object if mounted */ + pdrv = LD2PD(vol); /* Hosting physical drive */ + ipart = LD2PT(vol); /* Hosting partition (0:create as new, 1..:existing partition) */ + + /* Initialize the hosting physical drive */ + ds = disk_initialize(pdrv); + if (ds & STA_NOINIT) return FR_NOT_READY; + if (ds & STA_PROTECT) return FR_WRITE_PROTECTED; + + /* Get physical drive parameters (sz_drv, sz_blk and ss) */ + if (!opt) opt = &defopt; /* Use default parameter if it is not given */ + sz_blk = opt->align; + if (sz_blk == 0) disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk); /* Block size from the paramter or lower layer */ + if (sz_blk == 0 || sz_blk > 0x8000 || (sz_blk & (sz_blk - 1))) sz_blk = 1; /* Use default if the block size is invalid */ +#if FF_MAX_SS != FF_MIN_SS + if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; + if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; +#else + ss = FF_MAX_SS; +#endif + + /* Options for FAT sub-type and FAT parameters */ + fsopt = opt->fmt & (FM_ANY | FM_SFD); + n_fat = (opt->n_fat >= 1 && opt->n_fat <= 2) ? opt->n_fat : 1; + n_root = (opt->n_root >= 1 && opt->n_root <= 32768 && (opt->n_root % (ss / SZDIRE)) == 0) ? opt->n_root : 512; + sz_au = (opt->au_size <= 0x1000000 && (opt->au_size & (opt->au_size - 1)) == 0) ? opt->au_size : 0; + sz_au /= ss; /* Byte --> Sector */ + + /* Get working buffer */ + sz_buf = len / ss; /* Size of working buffer [sector] */ + if (sz_buf == 0) return FR_NOT_ENOUGH_CORE; + buf = (BYTE*)work; /* Working buffer */ +#if FF_USE_LFN == 3 + if (!buf) buf = ff_memalloc(sz_buf * ss); /* Use heap memory for working buffer */ +#endif + if (!buf) return FR_NOT_ENOUGH_CORE; + + /* Determine where the volume to be located (b_vol, sz_vol) */ + b_vol = sz_vol = 0; + if (FF_MULTI_PARTITION && ipart != 0) { /* Is the volume associated with any specific partition? */ + /* Get partition location from the existing partition table */ + if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Load MBR */ + if (ld_word(buf + BS_55AA) != 0xAA55) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if MBR is valid */ +#if FF_LBA64 + if (buf[MBR_Table + PTE_System] == 0xEE) { /* GPT protective MBR? */ + DWORD n_ent, ofs; + QWORD pt_lba; + + /* Get the partition location from GPT */ + if (disk_read(pdrv, buf, 1, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Load GPT header sector (next to MBR) */ + if (!test_gpt_header(buf)) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if GPT header is valid */ + n_ent = ld_dword(buf + GPTH_PtNum); /* Number of entries */ + pt_lba = ld_qword(buf + GPTH_PtOfs); /* Table start sector */ + ofs = i = 0; + while (n_ent) { /* Find MS Basic partition with order of ipart */ + if (ofs == 0 && disk_read(pdrv, buf, pt_lba++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Get PT sector */ + if (!memcmp(buf + ofs + GPTE_PtGuid, GUID_MS_Basic, 16) && ++i == ipart) { /* MS basic data partition? */ + b_vol = ld_qword(buf + ofs + GPTE_FstLba); + sz_vol = ld_qword(buf + ofs + GPTE_LstLba) - b_vol + 1; + break; + } + n_ent--; ofs = (ofs + SZ_GPTE) % ss; /* Next entry */ + } + if (n_ent == 0) LEAVE_MKFS(FR_MKFS_ABORTED); /* Partition not found */ + fsopt |= 0x80; /* Partitioning is in GPT */ + } else +#endif + { /* Get the partition location from MBR partition table */ + pte = buf + (MBR_Table + (ipart - 1) * SZ_PTE); + if (ipart > 4 || pte[PTE_System] == 0) LEAVE_MKFS(FR_MKFS_ABORTED); /* No partition? */ + b_vol = ld_dword(pte + PTE_StLba); /* Get volume start sector */ + sz_vol = ld_dword(pte + PTE_SizLba); /* Get volume size */ + } + } else { /* The volume is associated with a physical drive */ + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + if (!(fsopt & FM_SFD)) { /* To be partitioned? */ + /* Create a single-partition on the drive in this function */ +#if FF_LBA64 + if (sz_vol >= FF_MIN_GPT) { /* Which partition type to create, MBR or GPT? */ + fsopt |= 0x80; /* Partitioning is in GPT */ + b_vol = GPT_ALIGN / ss; sz_vol -= b_vol + GPT_ITEMS * SZ_GPTE / ss + 1; /* Estimated partition offset and size */ + } else +#endif + { /* Partitioning is in MBR */ + if (sz_vol > N_SEC_TRACK) { + b_vol = N_SEC_TRACK; sz_vol -= b_vol; /* Estimated partition offset and size */ + } + } + } + } + if (sz_vol < 128) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >=128s */ + + /* Now start to create an FAT volume at b_vol and sz_vol */ + + do { /* Pre-determine the FAT type */ + if (FF_FS_EXFAT && (fsopt & FM_EXFAT)) { /* exFAT possible? */ + if ((fsopt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || sz_au > 128) { /* exFAT only, vol >= 64MS or sz_au > 128S ? */ + fsty = FS_EXFAT; break; + } + } +#if FF_LBA64 + if (sz_vol >= 0x100000000) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too large volume for FAT/FAT32 */ +#endif + if (sz_au > 128) sz_au = 128; /* Invalid AU for FAT/FAT32? */ + if (fsopt & FM_FAT32) { /* FAT32 possible? */ + if (!(fsopt & FM_FAT)) { /* no-FAT? */ + fsty = FS_FAT32; break; + } + } + if (!(fsopt & FM_FAT)) LEAVE_MKFS(FR_INVALID_PARAMETER); /* no-FAT? */ + fsty = FS_FAT16; + } while (0); + + vsn = (DWORD)sz_vol + GET_FATTIME(); /* VSN generated from current time and partitiion size */ + +#if FF_FS_EXFAT + if (fsty == FS_EXFAT) { /* Create an exFAT volume */ + DWORD szb_bit, szb_case, sum, nbit, clu, clen[3]; + WCHAR ch, si; + UINT j, st; + + if (sz_vol < 0x1000) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume for exFAT? */ +#if FF_USE_TRIM + lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1; /* Inform storage device that the volume area may be erased */ + disk_ioctl(pdrv, CTRL_TRIM, lba); +#endif + /* Determine FAT location, data location and number of clusters */ + if (sz_au == 0) { /* AU auto-selection */ + sz_au = 8; + if (sz_vol >= 0x80000) sz_au = 64; /* >= 512Ks */ + if (sz_vol >= 0x4000000) sz_au = 256; /* >= 64Ms */ + } + b_fat = b_vol + 32; /* FAT start at offset 32 */ + sz_fat = (DWORD)((sz_vol / sz_au + 2) * 4 + ss - 1) / ss; /* Number of FAT sectors */ + b_data = (b_fat + sz_fat + sz_blk - 1) & ~((LBA_t)sz_blk - 1); /* Align data area to the erase block boundary */ + if (b_data - b_vol >= sz_vol / 2) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ + n_clst = (DWORD)((sz_vol - (b_data - b_vol)) / sz_au); /* Number of clusters */ + if (n_clst <16) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too few clusters? */ + if (n_clst > MAX_EXFAT) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters? */ + + szb_bit = (n_clst + 7) / 8; /* Size of allocation bitmap */ + clen[0] = (szb_bit + sz_au * ss - 1) / (sz_au * ss); /* Number of allocation bitmap clusters */ + + /* Create a compressed up-case table */ + sect = b_data + sz_au * clen[0]; /* Table start sector */ + sum = 0; /* Table checksum to be stored in the 82 entry */ + st = 0; si = 0; i = 0; j = 0; szb_case = 0; + do { + switch (st) { + case 0: + ch = (WCHAR)ff_wtoupper(si); /* Get an up-case char */ + if (ch != si) { + si++; break; /* Store the up-case char if exist */ + } + for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ; /* Get run length of no-case block */ + if (j >= 128) { + ch = 0xFFFF; st = 2; break; /* Compress the no-case block if run is >= 128 chars */ + } + st = 1; /* Do not compress short run */ + /* FALLTHROUGH */ + case 1: + ch = si++; /* Fill the short run */ + if (--j == 0) st = 0; + break; + + default: + ch = (WCHAR)j; si += (WCHAR)j; /* Number of chars to skip */ + st = 0; + } + sum = xsum32(buf[i + 0] = (BYTE)ch, sum); /* Put it into the write buffer */ + sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum); + i += 2; szb_case += 2; + if (si == 0 || i == sz_buf * ss) { /* Write buffered data when buffer full or end of process */ + n = (i + ss - 1) / ss; + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; i = 0; + } + } while (si); + clen[1] = (szb_case + sz_au * ss - 1) / (sz_au * ss); /* Number of up-case table clusters */ + clen[2] = 1; /* Number of root dir clusters */ + + /* Initialize the allocation bitmap */ + sect = b_data; nsect = (szb_bit + ss - 1) / ss; /* Start of bitmap and number of bitmap sectors */ + nbit = clen[0] + clen[1] + clen[2]; /* Number of clusters in-use by system (bitmap, up-case and root-dir) */ + do { + memset(buf, 0, sz_buf * ss); /* Initialize bitmap buffer */ + for (i = 0; nbit != 0 && i / 8 < sz_buf * ss; buf[i / 8] |= 1 << (i % 8), i++, nbit--) ; /* Mark used clusters */ + n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; nsect -= n; + } while (nsect); + + /* Initialize the FAT */ + sect = b_fat; nsect = sz_fat; /* Start of FAT and number of FAT sectors */ + j = nbit = clu = 0; + do { + memset(buf, 0, sz_buf * ss); i = 0; /* Clear work area and reset write offset */ + if (clu == 0) { /* Initialize FAT [0] and FAT[1] */ + st_dword(buf + i, 0xFFFFFFF8); i += 4; clu++; + st_dword(buf + i, 0xFFFFFFFF); i += 4; clu++; + } + do { /* Create chains of bitmap, up-case and root dir */ + while (nbit != 0 && i < sz_buf * ss) { /* Create a chain */ + st_dword(buf + i, (nbit > 1) ? clu + 1 : 0xFFFFFFFF); + i += 4; clu++; nbit--; + } + if (nbit == 0 && j < 3) nbit = clen[j++]; /* Get next chain length */ + } while (nbit != 0 && i < sz_buf * ss); + n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; nsect -= n; + } while (nsect); + + /* Initialize the root directory */ + memset(buf, 0, sz_buf * ss); + buf[SZDIRE * 0 + 0] = ET_VLABEL; /* Volume label entry (no label) */ + buf[SZDIRE * 1 + 0] = ET_BITMAP; /* Bitmap entry */ + st_dword(buf + SZDIRE * 1 + 20, 2); /* cluster */ + st_dword(buf + SZDIRE * 1 + 24, szb_bit); /* size */ + buf[SZDIRE * 2 + 0] = ET_UPCASE; /* Up-case table entry */ + st_dword(buf + SZDIRE * 2 + 4, sum); /* sum */ + st_dword(buf + SZDIRE * 2 + 20, 2 + clen[0]); /* cluster */ + st_dword(buf + SZDIRE * 2 + 24, szb_case); /* size */ + sect = b_data + sz_au * (clen[0] + clen[1]); nsect = sz_au; /* Start of the root directory and number of sectors */ + do { /* Fill root directory sectors */ + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + memset(buf, 0, ss); /* Rest of entries are filled with zero */ + sect += n; nsect -= n; + } while (nsect); + + /* Create two set of the exFAT VBR blocks */ + sect = b_vol; + for (n = 0; n < 2; n++) { + /* Main record (+0) */ + memset(buf, 0, ss); + memcpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11); /* Boot jump code (x86), OEM name */ + st_qword(buf + BPB_VolOfsEx, b_vol); /* Volume offset in the physical drive [sector] */ + st_qword(buf + BPB_TotSecEx, sz_vol); /* Volume size [sector] */ + st_dword(buf + BPB_FatOfsEx, (DWORD)(b_fat - b_vol)); /* FAT offset [sector] */ + st_dword(buf + BPB_FatSzEx, sz_fat); /* FAT size [sector] */ + st_dword(buf + BPB_DataOfsEx, (DWORD)(b_data - b_vol)); /* Data offset [sector] */ + st_dword(buf + BPB_NumClusEx, n_clst); /* Number of clusters */ + st_dword(buf + BPB_RootClusEx, 2 + clen[0] + clen[1]); /* Root dir cluster # */ + st_dword(buf + BPB_VolIDEx, vsn); /* VSN */ + st_word(buf + BPB_FSVerEx, 0x100); /* Filesystem version (1.00) */ + for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ; /* Log2 of sector size [byte] */ + for (buf[BPB_SecPerClusEx] = 0, i = sz_au; i >>= 1; buf[BPB_SecPerClusEx]++) ; /* Log2 of cluster size [sector] */ + buf[BPB_NumFATsEx] = 1; /* Number of FATs */ + buf[BPB_DrvNumEx] = 0x80; /* Drive number (for int13) */ + st_word(buf + BS_BootCodeEx, 0xFEEB); /* Boot code (x86) */ + st_word(buf + BS_55AA, 0xAA55); /* Signature (placed here regardless of sector size) */ + for (i = sum = 0; i < ss; i++) { /* VBR checksum */ + if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum); + } + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + /* Extended bootstrap record (+1..+8) */ + memset(buf, 0, ss); + st_word(buf + ss - 2, 0xAA55); /* Signature (placed at end of sector) */ + for (j = 1; j < 9; j++) { + for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + } + /* OEM/Reserved record (+9..+10) */ + memset(buf, 0, ss); + for ( ; j < 11; j++) { + for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + } + /* Sum record (+11) */ + for (i = 0; i < ss; i += 4) st_dword(buf + i, sum); /* Fill with checksum value */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + } + + } else +#endif /* FF_FS_EXFAT */ + { /* Create an FAT/FAT32 volume */ + do { + pau = sz_au; + /* Pre-determine number of clusters and FAT sub-type */ + if (fsty == FS_FAT32) { /* FAT32 volume */ + if (pau == 0) { /* AU auto-selection */ + n = (DWORD)sz_vol / 0x20000; /* Volume size in unit of 128KS */ + for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ; /* Get from table */ + } + n_clst = (DWORD)sz_vol / pau; /* Number of clusters */ + sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */ + sz_rsv = 32; /* Number of reserved sectors */ + sz_dir = 0; /* No static directory */ + if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) LEAVE_MKFS(FR_MKFS_ABORTED); + } else { /* FAT volume */ + if (pau == 0) { /* au auto-selection */ + n = (DWORD)sz_vol / 0x1000; /* Volume size in unit of 4KS */ + for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */ + } + n_clst = (DWORD)sz_vol / pau; + if (n_clst > MAX_FAT12) { + n = n_clst * 2 + 4; /* FAT size [byte] */ + } else { + fsty = FS_FAT12; + n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */ + } + sz_fat = (n + ss - 1) / ss; /* FAT size [sector] */ + sz_rsv = 1; /* Number of reserved sectors */ + sz_dir = (DWORD)n_root * SZDIRE / ss; /* Root dir size [sector] */ + } + b_fat = b_vol + sz_rsv; /* FAT base */ + b_data = b_fat + sz_fat * n_fat + sz_dir; /* Data base */ + + /* Align data area to erase block boundary (for flash memory media) */ + n = (DWORD)(((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data); /* Sectors to next nearest from current data base */ + if (fsty == FS_FAT32) { /* FAT32: Move FAT */ + sz_rsv += n; b_fat += n; + } else { /* FAT: Expand FAT */ + if (n % n_fat) { /* Adjust fractional error if needed */ + n--; sz_rsv++; b_fat++; + } + sz_fat += n / n_fat; + } + + /* Determine number of clusters and final check of validity of the FAT sub-type */ + if (sz_vol < b_data + pau * 16 - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ + n_clst = ((DWORD)sz_vol - sz_rsv - sz_fat * n_fat - sz_dir) / pau; + if (fsty == FS_FAT32) { + if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32? */ + if (sz_au == 0 && (sz_au = pau / 2) != 0) continue; /* Adjust cluster size and retry */ + LEAVE_MKFS(FR_MKFS_ABORTED); + } + } + if (fsty == FS_FAT16) { + if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */ + if (sz_au == 0 && (pau * 2) <= 64) { + sz_au = pau * 2; continue; /* Adjust cluster size and retry */ + } + if ((fsopt & FM_FAT32)) { + fsty = FS_FAT32; continue; /* Switch type to FAT32 and retry */ + } + if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ + LEAVE_MKFS(FR_MKFS_ABORTED); + } + if (n_clst <= MAX_FAT12) { /* Too few clusters for FAT16 */ + if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ + LEAVE_MKFS(FR_MKFS_ABORTED); + } + } + if (fsty == FS_FAT12 && n_clst > MAX_FAT12) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters for FAT12 */ + + /* Ok, it is the valid cluster configuration */ + break; + } while (1); + +#if FF_USE_TRIM + lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1; /* Inform storage device that the volume area may be erased */ + disk_ioctl(pdrv, CTRL_TRIM, lba); +#endif + /* Create FAT VBR */ + memset(buf, 0, ss); + memcpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11); /* Boot jump code (x86), OEM name */ + st_word(buf + BPB_BytsPerSec, ss); /* Sector size [byte] */ + buf[BPB_SecPerClus] = (BYTE)pau; /* Cluster size [sector] */ + st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv); /* Size of reserved area */ + buf[BPB_NumFATs] = (BYTE)n_fat; /* Number of FATs */ + st_word(buf + BPB_RootEntCnt, (WORD)((fsty == FS_FAT32) ? 0 : n_root)); /* Number of root directory entries */ + if (sz_vol < 0x10000) { + st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */ + } else { + st_dword(buf + BPB_TotSec32, (DWORD)sz_vol); /* Volume size in 32-bit LBA */ + } + buf[BPB_Media] = 0xF8; /* Media descriptor byte */ + st_word(buf + BPB_SecPerTrk, 63); /* Number of sectors per track (for int13) */ + st_word(buf + BPB_NumHeads, 255); /* Number of heads (for int13) */ + st_dword(buf + BPB_HiddSec, (DWORD)b_vol); /* Volume offset in the physical drive [sector] */ + if (fsty == FS_FAT32) { + st_dword(buf + BS_VolID32, vsn); /* VSN */ + st_dword(buf + BPB_FATSz32, sz_fat); /* FAT size [sector] */ + st_dword(buf + BPB_RootClus32, 2); /* Root directory cluster # (2) */ + st_word(buf + BPB_FSInfo32, 1); /* Offset of FSINFO sector (VBR + 1) */ + st_word(buf + BPB_BkBootSec32, 6); /* Offset of backup VBR (VBR + 6) */ + buf[BS_DrvNum32] = 0x80; /* Drive number (for int13) */ + buf[BS_BootSig32] = 0x29; /* Extended boot signature */ + memcpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ + } else { + st_dword(buf + BS_VolID, vsn); /* VSN */ + st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */ + buf[BS_DrvNum] = 0x80; /* Drive number (for int13) */ + buf[BS_BootSig] = 0x29; /* Extended boot signature */ + memcpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ + } + st_word(buf + BS_55AA, 0xAA55); /* Signature (offset is fixed here regardless of sector size) */ + if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it to the VBR sector */ + + /* Create FSINFO record if needed */ + if (fsty == FS_FAT32) { + disk_write(pdrv, buf, b_vol + 6, 1); /* Write backup VBR (VBR + 6) */ + memset(buf, 0, ss); + st_dword(buf + FSI_LeadSig, 0x41615252); + st_dword(buf + FSI_StrucSig, 0x61417272); + st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */ + st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */ + st_word(buf + BS_55AA, 0xAA55); + disk_write(pdrv, buf, b_vol + 7, 1); /* Write backup FSINFO (VBR + 7) */ + disk_write(pdrv, buf, b_vol + 1, 1); /* Write original FSINFO (VBR + 1) */ + } + + /* Initialize FAT area */ + memset(buf, 0, sz_buf * ss); + sect = b_fat; /* FAT start sector */ + for (i = 0; i < n_fat; i++) { /* Initialize FATs each */ + if (fsty == FS_FAT32) { + st_dword(buf + 0, 0xFFFFFFF8); /* FAT[0] */ + st_dword(buf + 4, 0xFFFFFFFF); /* FAT[1] */ + st_dword(buf + 8, 0x0FFFFFFF); /* FAT[2] (root directory) */ + } else { + st_dword(buf + 0, (fsty == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8); /* FAT[0] and FAT[1] */ + } + nsect = sz_fat; /* Number of FAT sectors */ + do { /* Fill FAT sectors */ + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) + LEAVE_MKFS(FR_DISK_ERR); + memset(buf, 0, ss); /* Rest of FAT all are cleared */ + sect += n; nsect -= n; + } while (nsect); + } + + /* Initialize root directory (fill with zero) */ + nsect = (fsty == FS_FAT32) ? pau : sz_dir; /* Number of root directory sectors */ + do { + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; nsect -= n; + } while (nsect); + } + + /* A FAT volume has been created here */ + + /* Determine system ID in the MBR partition table */ + if (FF_FS_EXFAT && fsty == FS_EXFAT) { + sys = 0x07; /* exFAT */ + } else if (fsty == FS_FAT32) { + sys = 0x0C; /* FAT32X */ + } else if (sz_vol >= 0x10000) { + sys = 0x06; /* FAT12/16 (large) */ + } else if (fsty == FS_FAT16) { + sys = 0x04; /* FAT16 */ + } else { + sys = 0x01; /* FAT12 */ + } + + /* Update partition information */ + if (FF_MULTI_PARTITION && ipart != 0) { /* Volume is in the existing partition */ + if (!FF_LBA64 || !(fsopt & 0x80)) { /* Is the partition in MBR? */ + /* Update system ID in the partition table */ + if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Read the MBR */ + buf[MBR_Table + (ipart - 1) * SZ_PTE + PTE_System] = sys; /* Set system ID */ + if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it back to the MBR */ + } + } else { /* Volume as a new single partition */ + if (!(fsopt & FM_SFD)) { /* Create partition table if not in SFD format */ + lba[0] = sz_vol; lba[1] = 0; + res = create_partition(pdrv, lba, sys, buf); + if (res != FR_OK) LEAVE_MKFS(res); + } + } + + if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + + LEAVE_MKFS(FR_OK); +} + + + + +#if FF_MULTI_PARTITION +/*-----------------------------------------------------------------------*/ +/* Create Partition Table on the Physical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_fdisk ( + BYTE pdrv, /* Physical drive number */ + const LBA_t ptbl[], /* Pointer to the size table for each partitions */ + void* work /* Pointer to the working buffer (null: use heap memory) */ +) +{ + BYTE *buf = (BYTE*)work; + DSTATUS stat; + FRESULT res; + + + /* Initialize the physical drive */ + stat = disk_initialize(pdrv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + +#if FF_USE_LFN == 3 + if (!buf) buf = ff_memalloc(FF_MAX_SS); /* Use heap memory for working buffer */ +#endif + if (!buf) return FR_NOT_ENOUGH_CORE; + + res = create_partition(pdrv, ptbl, 0x07, buf); /* Create partitions (system ID is temporary setting and determined by f_mkfs) */ + + LEAVE_MKFS(res); +} + +#endif /* FF_MULTI_PARTITION */ +#endif /* !FF_FS_READONLY && FF_USE_MKFS */ + + + + +#if FF_USE_STRFUNC +#if FF_USE_LFN && FF_LFN_UNICODE && (FF_STRF_ENCODE < 0 || FF_STRF_ENCODE > 3) +#error Wrong FF_STRF_ENCODE setting +#endif +/*-----------------------------------------------------------------------*/ +/* Get a String from the File */ +/*-----------------------------------------------------------------------*/ + +TCHAR* f_gets ( + TCHAR* buff, /* Pointer to the buffer to store read string */ + int len, /* Size of string buffer (items) */ + FIL* fp /* Pointer to the file object */ +) +{ + int nc = 0; + TCHAR *p = buff; + BYTE s[4]; + UINT rc; + DWORD dc; +#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE <= 2 + WCHAR wc; +#endif +#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE == 3 + UINT ct; +#endif + +#if FF_USE_LFN && FF_LFN_UNICODE /* With code conversion (Unicode API) */ + /* Make a room for the character and terminator */ + if (FF_LFN_UNICODE == 1) len -= (FF_STRF_ENCODE == 0) ? 1 : 2; + if (FF_LFN_UNICODE == 2) len -= (FF_STRF_ENCODE == 0) ? 3 : 4; + if (FF_LFN_UNICODE == 3) len -= 1; + while (nc < len) { +#if FF_STRF_ENCODE == 0 /* Read a character in ANSI/OEM */ + f_read(fp, s, 1, &rc); /* Get a code unit */ + if (rc != 1) break; /* EOF? */ + wc = s[0]; + if (dbc_1st((BYTE)wc)) { /* DBC 1st byte? */ + f_read(fp, s, 1, &rc); /* Get 2nd byte */ + if (rc != 1 || !dbc_2nd(s[0])) continue; /* Wrong code? */ + wc = wc << 8 | s[0]; + } + dc = ff_oem2uni(wc, CODEPAGE); /* Convert ANSI/OEM into Unicode */ + if (dc == 0) continue; /* Conversion error? */ +#elif FF_STRF_ENCODE == 1 || FF_STRF_ENCODE == 2 /* Read a character in UTF-16LE/BE */ + f_read(fp, s, 2, &rc); /* Get a code unit */ + if (rc != 2) break; /* EOF? */ + dc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1]; + if (IsSurrogateL(dc)) continue; /* Broken surrogate pair? */ + if (IsSurrogateH(dc)) { /* High surrogate? */ + f_read(fp, s, 2, &rc); /* Get low surrogate */ + if (rc != 2) break; /* EOF? */ + wc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1]; + if (!IsSurrogateL(wc)) continue; /* Broken surrogate pair? */ + dc = ((dc & 0x3FF) + 0x40) << 10 | (wc & 0x3FF); /* Merge surrogate pair */ + } +#else /* Read a character in UTF-8 */ + f_read(fp, s, 1, &rc); /* Get a code unit */ + if (rc != 1) break; /* EOF? */ + dc = s[0]; + if (dc >= 0x80) { /* Multi-byte sequence? */ + ct = 0; + if ((dc & 0xE0) == 0xC0) { /* 2-byte sequence? */ + dc &= 0x1F; ct = 1; + } + if ((dc & 0xF0) == 0xE0) { /* 3-byte sequence? */ + dc &= 0x0F; ct = 2; + } + if ((dc & 0xF8) == 0xF0) { /* 4-byte sequence? */ + dc &= 0x07; ct = 3; + } + if (ct == 0) continue; + f_read(fp, s, ct, &rc); /* Get trailing bytes */ + if (rc != ct) break; + rc = 0; + do { /* Merge the byte sequence */ + if ((s[rc] & 0xC0) != 0x80) break; + dc = dc << 6 | (s[rc] & 0x3F); + } while (++rc < ct); + if (rc != ct || dc < 0x80 || IsSurrogate(dc) || dc >= 0x110000) continue; /* Wrong encoding? */ + } +#endif + /* A code point is avaialble in dc to be output */ + + if (FF_USE_STRFUNC == 2 && dc == '\r') continue; /* Strip \r off if needed */ +#if FF_LFN_UNICODE == 1 || FF_LFN_UNICODE == 3 /* Output it in UTF-16/32 encoding */ + if (FF_LFN_UNICODE == 1 && dc >= 0x10000) { /* Out of BMP at UTF-16? */ + *p++ = (TCHAR)(0xD800 | ((dc >> 10) - 0x40)); nc++; /* Make and output high surrogate */ + dc = 0xDC00 | (dc & 0x3FF); /* Make low surrogate */ + } + *p++ = (TCHAR)dc; nc++; + if (dc == '\n') break; /* End of line? */ +#elif FF_LFN_UNICODE == 2 /* Output it in UTF-8 encoding */ + if (dc < 0x80) { /* Single byte? */ + *p++ = (TCHAR)dc; + nc++; + if (dc == '\n') break; /* End of line? */ + } else if (dc < 0x800) { /* 2-byte sequence? */ + *p++ = (TCHAR)(0xC0 | (dc >> 6 & 0x1F)); + *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); + nc += 2; + } else if (dc < 0x10000) { /* 3-byte sequence? */ + *p++ = (TCHAR)(0xE0 | (dc >> 12 & 0x0F)); + *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F)); + *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); + nc += 3; + } else { /* 4-byte sequence */ + *p++ = (TCHAR)(0xF0 | (dc >> 18 & 0x07)); + *p++ = (TCHAR)(0x80 | (dc >> 12 & 0x3F)); + *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F)); + *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); + nc += 4; + } +#endif + } + +#else /* Byte-by-byte read without any conversion (ANSI/OEM API) */ + len -= 1; /* Make a room for the terminator */ + while (nc < len) { + f_read(fp, s, 1, &rc); /* Get a byte */ + if (rc != 1) break; /* EOF? */ + dc = s[0]; + if (FF_USE_STRFUNC == 2 && dc == '\r') continue; + *p++ = (TCHAR)dc; nc++; + if (dc == '\n') break; + } +#endif + + *p = 0; /* Terminate the string */ + return nc ? buff : 0; /* When no data read due to EOF or error, return with error. */ +} + + + + +#if !FF_FS_READONLY +#include +#define SZ_PUTC_BUF 64 +#define SZ_NUM_BUF 32 + +/*-----------------------------------------------------------------------*/ +/* Put a Character to the File (with sub-functions) */ +/*-----------------------------------------------------------------------*/ + +/* Output buffer and work area */ + +typedef struct { + FIL *fp; /* Ptr to the writing file */ + int idx, nchr; /* Write index of buf[] (-1:error), number of encoding units written */ +#if FF_USE_LFN && FF_LFN_UNICODE == 1 + WCHAR hs; +#elif FF_USE_LFN && FF_LFN_UNICODE == 2 + BYTE bs[4]; + UINT wi, ct; +#endif + BYTE buf[SZ_PUTC_BUF]; /* Write buffer */ +} putbuff; + + +/* Buffered file write with code conversion */ + +static void putc_bfd (putbuff* pb, TCHAR c) +{ + UINT n; + int i, nc; +#if FF_USE_LFN && FF_LFN_UNICODE + WCHAR hs, wc; +#if FF_LFN_UNICODE == 2 + DWORD dc; + const TCHAR* tp; +#endif +#endif + + if (FF_USE_STRFUNC == 2 && c == '\n') { /* LF -> CRLF conversion */ + putc_bfd(pb, '\r'); + } + + i = pb->idx; /* Write index of pb->buf[] */ + if (i < 0) return; /* In write error? */ + nc = pb->nchr; /* Write unit counter */ + +#if FF_USE_LFN && FF_LFN_UNICODE +#if FF_LFN_UNICODE == 1 /* UTF-16 input */ + if (IsSurrogateH(c)) { /* Is this a high-surrogate? */ + pb->hs = c; return; /* Save it for next */ + } + hs = pb->hs; pb->hs = 0; + if (hs != 0) { /* Is there a leading high-surrogate? */ + if (!IsSurrogateL(c)) hs = 0; /* Discard high-surrogate if not a surrogate pair */ + } else { + if (IsSurrogateL(c)) return; /* Discard stray low-surrogate */ + } + wc = c; +#elif FF_LFN_UNICODE == 2 /* UTF-8 input */ + for (;;) { + if (pb->ct == 0) { /* Out of multi-byte sequence? */ + pb->bs[pb->wi = 0] = (BYTE)c; /* Save 1st byte */ + if ((BYTE)c < 0x80) break; /* Single byte code? */ + if (((BYTE)c & 0xE0) == 0xC0) pb->ct = 1; /* 2-byte sequence? */ + if (((BYTE)c & 0xF0) == 0xE0) pb->ct = 2; /* 3-byte sequence? */ + if (((BYTE)c & 0xF8) == 0xF0) pb->ct = 3; /* 4-byte sequence? */ + return; /* Wrong leading byte (discard it) */ + } else { /* In the multi-byte sequence */ + if (((BYTE)c & 0xC0) != 0x80) { /* Broken sequence? */ + pb->ct = 0; continue; /* Discard the sequense */ + } + pb->bs[++pb->wi] = (BYTE)c; /* Save the trailing byte */ + if (--pb->ct == 0) break; /* End of the sequence? */ + return; + } + } + tp = (const TCHAR*)pb->bs; + dc = tchar2uni(&tp); /* UTF-8 ==> UTF-16 */ + if (dc == 0xFFFFFFFF) return; /* Wrong code? */ + hs = (WCHAR)(dc >> 16); + wc = (WCHAR)dc; +#elif FF_LFN_UNICODE == 3 /* UTF-32 input */ + if (IsSurrogate(c) || c >= 0x110000) return; /* Discard invalid code */ + if (c >= 0x10000) { /* Out of BMP? */ + hs = (WCHAR)(0xD800 | ((c >> 10) - 0x40)); /* Make high surrogate */ + wc = 0xDC00 | (c & 0x3FF); /* Make low surrogate */ + } else { + hs = 0; + wc = (WCHAR)c; + } +#endif + /* A code point in UTF-16 is available in hs and wc */ + +#if FF_STRF_ENCODE == 1 /* Write a code point in UTF-16LE */ + if (hs != 0) { /* Surrogate pair? */ + st_word(&pb->buf[i], hs); + i += 2; + nc++; + } + st_word(&pb->buf[i], wc); + i += 2; +#elif FF_STRF_ENCODE == 2 /* Write a code point in UTF-16BE */ + if (hs != 0) { /* Surrogate pair? */ + pb->buf[i++] = (BYTE)(hs >> 8); + pb->buf[i++] = (BYTE)hs; + nc++; + } + pb->buf[i++] = (BYTE)(wc >> 8); + pb->buf[i++] = (BYTE)wc; +#elif FF_STRF_ENCODE == 3 /* Write a code point in UTF-8 */ + if (hs != 0) { /* 4-byte sequence? */ + nc += 3; + hs = (hs & 0x3FF) + 0x40; + pb->buf[i++] = (BYTE)(0xF0 | hs >> 8); + pb->buf[i++] = (BYTE)(0x80 | (hs >> 2 & 0x3F)); + pb->buf[i++] = (BYTE)(0x80 | (hs & 3) << 4 | (wc >> 6 & 0x0F)); + pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F)); + } else { + if (wc < 0x80) { /* Single byte? */ + pb->buf[i++] = (BYTE)wc; + } else { + if (wc < 0x800) { /* 2-byte sequence? */ + nc += 1; + pb->buf[i++] = (BYTE)(0xC0 | wc >> 6); + } else { /* 3-byte sequence */ + nc += 2; + pb->buf[i++] = (BYTE)(0xE0 | wc >> 12); + pb->buf[i++] = (BYTE)(0x80 | (wc >> 6 & 0x3F)); + } + pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F)); + } + } +#else /* Write a code point in ANSI/OEM */ + if (hs != 0) return; + wc = ff_uni2oem(wc, CODEPAGE); /* UTF-16 ==> ANSI/OEM */ + if (wc == 0) return; + if (wc >= 0x100) { + pb->buf[i++] = (BYTE)(wc >> 8); nc++; + } + pb->buf[i++] = (BYTE)wc; +#endif + +#else /* ANSI/OEM input (without re-encoding) */ + pb->buf[i++] = (BYTE)c; +#endif + + if (i >= (int)(sizeof pb->buf) - 4) { /* Write buffered characters to the file */ + f_write(pb->fp, pb->buf, (UINT)i, &n); + i = (n == (UINT)i) ? 0 : -1; + } + pb->idx = i; + pb->nchr = nc + 1; +} + + +/* Flush remaining characters in the buffer */ + +static int putc_flush (putbuff* pb) +{ + UINT nw; + + if ( pb->idx >= 0 /* Flush buffered characters to the file */ + && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK + && (UINT)pb->idx == nw) return pb->nchr; + return -1; +} + + +/* Initialize write buffer */ + +static void putc_init (putbuff* pb, FIL* fp) +{ + memset(pb, 0, sizeof (putbuff)); + pb->fp = fp; +} + + + +int f_putc ( + TCHAR c, /* A character to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + + + putc_init(&pb, fp); + putc_bfd(&pb, c); /* Put the character */ + return putc_flush(&pb); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a String to the File */ +/*-----------------------------------------------------------------------*/ + +int f_puts ( + const TCHAR* str, /* Pointer to the string to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + + + putc_init(&pb, fp); + while (*str) putc_bfd(&pb, *str++); /* Put the string */ + return putc_flush(&pb); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a Formatted String to the File (with sub-functions) */ +/*-----------------------------------------------------------------------*/ +#if FF_PRINT_FLOAT && FF_INTDEF == 2 +#include + +static int ilog10 (double n) /* Calculate log10(n) in integer output */ +{ + int rv = 0; + + while (n >= 10) { /* Decimate digit in right shift */ + if (n >= 100000) { + n /= 100000; rv += 5; + } else { + n /= 10; rv++; + } + } + while (n < 1) { /* Decimate digit in left shift */ + if (n < 0.00001) { + n *= 100000; rv -= 5; + } else { + n *= 10; rv--; + } + } + return rv; +} + + +static double i10x (int n) /* Calculate 10^n in integer input */ +{ + double rv = 1; + + while (n > 0) { /* Left shift */ + if (n >= 5) { + rv *= 100000; n -= 5; + } else { + rv *= 10; n--; + } + } + while (n < 0) { /* Right shift */ + if (n <= -5) { + rv /= 100000; n += 5; + } else { + rv /= 10; n++; + } + } + return rv; +} + + +static void ftoa ( + char* buf, /* Buffer to output the floating point string */ + double val, /* Value to output */ + int prec, /* Number of fractional digits */ + TCHAR fmt /* Notation */ +) +{ + int d; + int e = 0, m = 0; + char sign = 0; + double w; + const char *er = 0; + const char ds = FF_PRINT_FLOAT == 2 ? ',' : '.'; + + + if (isnan(val)) { /* Not a number? */ + er = "NaN"; + } else { + if (prec < 0) prec = 6; /* Default precision? (6 fractional digits) */ + if (val < 0) { /* Negative? */ + val = 0 - val; sign = '-'; + } else { + sign = '+'; + } + if (isinf(val)) { /* Infinite? */ + er = "INF"; + } else { + if (fmt == 'f') { /* Decimal notation? */ + val += i10x(0 - prec) / 2; /* Round (nearest) */ + m = ilog10(val); + if (m < 0) m = 0; + if (m + prec + 3 >= SZ_NUM_BUF) er = "OV"; /* Buffer overflow? */ + } else { /* E notation */ + if (val != 0) { /* Not a true zero? */ + val += i10x(ilog10(val) - prec) / 2; /* Round (nearest) */ + e = ilog10(val); + if (e > 99 || prec + 7 >= SZ_NUM_BUF) { /* Buffer overflow or E > +99? */ + er = "OV"; + } else { + if (e < -99) e = -99; + val /= i10x(e); /* Normalize */ + } + } + } + } + if (!er) { /* Not error condition */ + if (sign == '-') *buf++ = sign; /* Add a - if negative value */ + do { /* Put decimal number */ + if (m == -1) *buf++ = ds; /* Insert a decimal separator when get into fractional part */ + w = i10x(m); /* Snip the highest digit d */ + d = (int)(val / w); val -= d * w; + *buf++ = (char)('0' + d); /* Put the digit */ + } while (--m >= -prec); /* Output all digits specified by prec */ + if (fmt != 'f') { /* Put exponent if needed */ + *buf++ = (char)fmt; + if (e < 0) { + e = 0 - e; *buf++ = '-'; + } else { + *buf++ = '+'; + } + *buf++ = (char)('0' + e / 10); + *buf++ = (char)('0' + e % 10); + } + } + } + if (er) { /* Error condition */ + if (sign) *buf++ = sign; /* Add sign if needed */ + do { /* Put error symbol */ + *buf++ = *er++; + } while (*er); + } + *buf = 0; /* Term */ +} +#endif /* FF_PRINT_FLOAT && FF_INTDEF == 2 */ + + + +int f_printf ( + FIL* fp, /* Pointer to the file object */ + const TCHAR* fmt, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + putbuff pb; + UINT i, j, w, f, r; + int prec; +#if FF_PRINT_LLI && FF_INTDEF == 2 + QWORD v; +#else + DWORD v; +#endif + TCHAR *tp; + TCHAR tc, pad; + TCHAR nul = 0; + char d, str[SZ_NUM_BUF]; + + + putc_init(&pb, fp); + + va_start(arp, fmt); + + for (;;) { + tc = *fmt++; + if (tc == 0) break; /* End of format string */ + if (tc != '%') { /* Not an escape character (pass-through) */ + putc_bfd(&pb, tc); + continue; + } + f = w = 0; pad = ' '; prec = -1; /* Initialize parms */ + tc = *fmt++; + if (tc == '0') { /* Flag: '0' padded */ + pad = '0'; tc = *fmt++; + } else if (tc == '-') { /* Flag: Left aligned */ + f = 2; tc = *fmt++; + } + if (tc == '*') { /* Minimum width from an argument */ + w = va_arg(arp, int); + tc = *fmt++; + } else { + while (IsDigit(tc)) { /* Minimum width */ + w = w * 10 + tc - '0'; + tc = *fmt++; + } + } + if (tc == '.') { /* Precision */ + tc = *fmt++; + if (tc == '*') { /* Precision from an argument */ + prec = va_arg(arp, int); + tc = *fmt++; + } else { + prec = 0; + while (IsDigit(tc)) { /* Precision */ + prec = prec * 10 + tc - '0'; + tc = *fmt++; + } + } + } + if (tc == 'l') { /* Size: long int */ + f |= 4; tc = *fmt++; +#if FF_PRINT_LLI && FF_INTDEF == 2 + if (tc == 'l') { /* Size: long long int */ + f |= 8; tc = *fmt++; + } +#endif + } + if (tc == 0) break; /* End of format string */ + switch (tc) { /* Atgument type is... */ + case 'b': /* Unsigned binary */ + r = 2; break; + + case 'o': /* Unsigned octal */ + r = 8; break; + + case 'd': /* Signed decimal */ + case 'u': /* Unsigned decimal */ + r = 10; break; + + case 'x': /* Unsigned hexadecimal (lower case) */ + case 'X': /* Unsigned hexadecimal (upper case) */ + r = 16; break; + + case 'c': /* Character */ + putc_bfd(&pb, (TCHAR)va_arg(arp, int)); + continue; + + case 's': /* String */ + tp = va_arg(arp, TCHAR*); /* Get a pointer argument */ + if (!tp) tp = &nul; /* Null ptr generates a null string */ + for (j = 0; tp[j]; j++) ; /* j = tcslen(tp) */ + if (prec >= 0 && j > (UINT)prec) j = prec; /* Limited length of string body */ + for ( ; !(f & 2) && j < w; j++) putc_bfd(&pb, pad); /* Left pads */ + while (*tp && prec--) putc_bfd(&pb, *tp++); /* Body */ + while (j++ < w) putc_bfd(&pb, ' '); /* Right pads */ + continue; +#if FF_PRINT_FLOAT && FF_INTDEF == 2 + case 'f': /* Floating point (decimal) */ + case 'e': /* Floating point (e) */ + case 'E': /* Floating point (E) */ + ftoa(str, va_arg(arp, double), prec, tc); /* Make a floating point string */ + for (j = strlen(str); !(f & 2) && j < w; j++) putc_bfd(&pb, pad); /* Left pads */ + for (i = 0; str[i]; putc_bfd(&pb, str[i++])) ; /* Body */ + while (j++ < w) putc_bfd(&pb, ' '); /* Right pads */ + continue; +#endif + default: /* Unknown type (pass-through) */ + putc_bfd(&pb, tc); continue; + } + + /* Get an integer argument and put it in numeral */ +#if FF_PRINT_LLI && FF_INTDEF == 2 + if (f & 8) { /* long long argument? */ + v = (QWORD)va_arg(arp, long long); + } else if (f & 4) { /* long argument? */ + v = (tc == 'd') ? (QWORD)(long long)va_arg(arp, long) : (QWORD)va_arg(arp, unsigned long); + } else { /* int/short/char argument */ + v = (tc == 'd') ? (QWORD)(long long)va_arg(arp, int) : (QWORD)va_arg(arp, unsigned int); + } + if (tc == 'd' && (v & 0x8000000000000000)) { /* Negative value? */ + v = 0 - v; f |= 1; + } +#else + if (f & 4) { /* long argument? */ + v = (DWORD)va_arg(arp, long); + } else { /* int/short/char argument */ + v = (tc == 'd') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int); + } + if (tc == 'd' && (v & 0x80000000)) { /* Negative value? */ + v = 0 - v; f |= 1; + } +#endif + i = 0; + do { /* Make an integer number string */ + d = (char)(v % r); v /= r; + if (d > 9) d += (tc == 'x') ? 0x27 : 0x07; + str[i++] = d + '0'; + } while (v && i < SZ_NUM_BUF); + if (f & 1) str[i++] = '-'; /* Sign */ + /* Write it */ + for (j = i; !(f & 2) && j < w; j++) { /* Left pads */ + putc_bfd(&pb, pad); + } + do { /* Body */ + putc_bfd(&pb, (TCHAR)str[--i]); + } while (i); + while (j++ < w) { /* Right pads */ + putc_bfd(&pb, ' '); + } + } + + va_end(arp); + + return putc_flush(&pb); +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_USE_STRFUNC */ + + + +#if FF_CODE_PAGE == 0 +/*-----------------------------------------------------------------------*/ +/* Set Active Codepage for the Path Name */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_setcp ( + WORD cp /* Value to be set as active code page */ +) +{ + static const WORD validcp[22] = { 437, 720, 737, 771, 775, 850, 852, 855, 857, 860, 861, 862, 863, 864, 865, 866, 869, 932, 936, 949, 950, 0}; + static const BYTE *const tables[22] = {Ct437, Ct720, Ct737, Ct771, Ct775, Ct850, Ct852, Ct855, Ct857, Ct860, Ct861, Ct862, Ct863, Ct864, Ct865, Ct866, Ct869, Dc932, Dc936, Dc949, Dc950, 0}; + UINT i; + + + for (i = 0; validcp[i] != 0 && validcp[i] != cp; i++) ; /* Find the code page */ + if (validcp[i] != cp) return FR_INVALID_PARAMETER; /* Not found? */ + + CodePage = cp; + if (cp >= 900) { /* DBCS */ + ExCvt = 0; + DbcTbl = tables[i]; + } else { /* SBCS */ + ExCvt = tables[i]; + DbcTbl = 0; + } + return FR_OK; +} +#endif /* FF_CODE_PAGE == 0 */ + diff --git a/Project/GateWay/source/Module/FatFS/source/ff.h b/Project/GateWay/source/Module/FatFS/source/ff.h new file mode 100644 index 0000000..e0a7712 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/source/ff.h @@ -0,0 +1,429 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - Generic FAT Filesystem module R0.15 / +/-----------------------------------------------------------------------------/ +/ +/ Copyright (C) 2022, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: + +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +/ +/----------------------------------------------------------------------------*/ + + +#ifndef FF_DEFINED +#define FF_DEFINED 80286 /* Revision ID */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ffconf.h" /* FatFs configuration options */ + +#if FF_DEFINED != FFCONF_DEF +#error Wrong configuration file (ffconf.h). +#endif + + +/* Integer types used for FatFs API */ + +#if defined(_WIN32) /* Windows VC++ (for development only) */ +#define FF_INTDEF 2 +#include +typedef unsigned __int64 QWORD; +#include +#define isnan(v) _isnan(v) +#define isinf(v) (!_finite(v)) + +#elif (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__cplusplus) /* C99 or later */ +#define FF_INTDEF 2 +#include +typedef unsigned int UINT; /* int must be 16-bit or 32-bit */ +typedef unsigned char BYTE; /* char must be 8-bit */ +typedef uint16_t WORD; /* 16-bit unsigned integer */ +typedef uint32_t DWORD; /* 32-bit unsigned integer */ +typedef uint64_t QWORD; /* 64-bit unsigned integer */ +typedef WORD WCHAR; /* UTF-16 character type */ + +#else /* Earlier than C99 */ +#define FF_INTDEF 1 +typedef unsigned int UINT; /* int must be 16-bit or 32-bit */ +typedef unsigned char BYTE; /* char must be 8-bit */ +typedef unsigned short WORD; /* 16-bit unsigned integer */ +typedef unsigned long DWORD; /* 32-bit unsigned integer */ +typedef WORD WCHAR; /* UTF-16 character type */ +#endif + + +/* Type of file size and LBA variables */ + +#if FF_FS_EXFAT +#if FF_INTDEF != 2 +#error exFAT feature wants C99 or later +#endif +typedef QWORD FSIZE_t; +#if FF_LBA64 +typedef QWORD LBA_t; +#else +typedef DWORD LBA_t; +#endif +#else +#if FF_LBA64 +#error exFAT needs to be enabled when enable 64-bit LBA +#endif +typedef DWORD FSIZE_t; +typedef DWORD LBA_t; +#endif + + + +/* Type of path name strings on FatFs API (TCHAR) */ + +#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */ +typedef WCHAR TCHAR; +#define _T(x) L ## x +#define _TEXT(x) L ## x +#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */ +typedef char TCHAR; +#define _T(x) u8 ## x +#define _TEXT(x) u8 ## x +#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */ +typedef DWORD TCHAR; +#define _T(x) U ## x +#define _TEXT(x) U ## x +#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3) +#error Wrong FF_LFN_UNICODE setting +#else /* ANSI/OEM code in SBCS/DBCS */ +typedef char TCHAR; +#define _T(x) x +#define _TEXT(x) x +#endif + + + +/* Definitions of volume management */ + +#if FF_MULTI_PARTITION /* Multiple partition configuration */ +typedef struct { + BYTE pd; /* Physical drive number */ + BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */ +} PARTITION; +extern PARTITION VolToPart[]; /* Volume - Partition mapping table */ +#endif + +#if FF_STR_VOLUME_ID +#ifndef FF_VOLUME_STRS +extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */ +#endif +#endif + + + +/* Filesystem object structure (FATFS) */ + +typedef struct { + BYTE fs_type; /* Filesystem type (0:not mounted) */ + BYTE pdrv; /* Volume hosting physical drive */ + BYTE ldrv; /* Logical drive number (used only when FF_FS_REENTRANT) */ + BYTE n_fats; /* Number of FATs (1 or 2) */ + BYTE wflag; /* win[] status (b0:dirty) */ + BYTE fsi_flag; /* FSINFO status (b7:disabled, b0:dirty) */ + WORD id; /* Volume mount ID */ + WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ + WORD csize; /* Cluster size [sectors] */ +#if FF_MAX_SS != FF_MIN_SS + WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */ +#endif +#if FF_USE_LFN + WCHAR* lfnbuf; /* LFN working buffer */ +#endif +#if FF_FS_EXFAT + BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */ +#endif +#if !FF_FS_READONLY + DWORD last_clst; /* Last allocated cluster */ + DWORD free_clst; /* Number of free clusters */ +#endif +#if FF_FS_RPATH + DWORD cdir; /* Current directory start cluster (0:root) */ +#if FF_FS_EXFAT + DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */ + DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */ + DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */ +#endif +#endif + DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */ + DWORD fsize; /* Number of sectors per FAT */ + LBA_t volbase; /* Volume base sector */ + LBA_t fatbase; /* FAT base sector */ + LBA_t dirbase; /* Root directory base sector (FAT12/16) or cluster (FAT32/exFAT) */ + LBA_t database; /* Data base sector */ +#if FF_FS_EXFAT + LBA_t bitbase; /* Allocation bitmap base sector */ +#endif + LBA_t winsect; /* Current sector appearing in the win[] */ + BYTE win[FF_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */ +} FATFS; + + + +/* Object ID and allocation information (FFOBJID) */ + +typedef struct { + FATFS* fs; /* Pointer to the hosting volume of this object */ + WORD id; /* Hosting volume's mount ID */ + BYTE attr; /* Object attribute */ + BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:fragmented in this session, b2:sub-directory stretched) */ + DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */ + FSIZE_t objsize; /* Object size (valid when sclust != 0) */ +#if FF_FS_EXFAT + DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */ + DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */ + DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */ + DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */ + DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */ +#endif +#if FF_FS_LOCK + UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */ +#endif +} FFOBJID; + + + +/* File object structure (FIL) */ + +typedef struct { + FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */ + BYTE flag; /* File status flags */ + BYTE err; /* Abort flag (error code) */ + FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */ + DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */ + LBA_t sect; /* Sector number appearing in buf[] (0:invalid) */ +#if !FF_FS_READONLY + LBA_t dir_sect; /* Sector number containing the directory entry (not used at exFAT) */ + BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */ +#endif +#if FF_USE_FASTSEEK + DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */ +#endif +#if !FF_FS_TINY + BYTE buf[FF_MAX_SS]; /* File private data read/write window */ +#endif +} FIL; + + + +/* Directory object structure (DIR) */ + +typedef struct { + FFOBJID obj; /* Object identifier */ + DWORD dptr; /* Current read/write offset */ + DWORD clust; /* Current cluster */ + LBA_t sect; /* Current sector (0:Read operation has terminated) */ + BYTE* dir; /* Pointer to the directory item in the win[] */ + BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */ +#if FF_USE_LFN + DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */ +#endif +#if FF_USE_FIND + const TCHAR* pat; /* Pointer to the name matching pattern */ +#endif +} DIR; + + + +/* File information structure (FILINFO) */ + +typedef struct { + FSIZE_t fsize; /* File size */ + WORD fdate; /* Modified date */ + WORD ftime; /* Modified time */ + BYTE fattrib; /* File attribute */ +#if FF_USE_LFN + TCHAR altname[FF_SFN_BUF + 1];/* Alternative file name */ + TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */ +#else + TCHAR fname[12 + 1]; /* File name */ +#endif +} FILINFO; + + + +/* Format parameter structure (MKFS_PARM) */ + +typedef struct { + BYTE fmt; /* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */ + BYTE n_fat; /* Number of FATs */ + UINT align; /* Data area alignment (sector) */ + UINT n_root; /* Number of root directory entries */ + DWORD au_size; /* Cluster size (byte) */ +} MKFS_PARM; + + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* (0) Succeeded */ + FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */ + FR_INT_ERR, /* (2) Assertion failed */ + FR_NOT_READY, /* (3) The physical drive cannot work */ + FR_NO_FILE, /* (4) Could not find the file */ + FR_NO_PATH, /* (5) Could not find the path */ + FR_INVALID_NAME, /* (6) The path name format is invalid */ + FR_DENIED, /* (7) Access denied due to prohibited access or directory full */ + FR_EXIST, /* (8) Access denied due to prohibited access */ + FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ + FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ + FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ + FR_NOT_ENABLED, /* (12) The volume has no work area */ + FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */ + FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */ + FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ + FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */ + FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ + FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */ + FR_INVALID_PARAMETER /* (19) Given parameter is invalid */ +} FRESULT; + + + + +/*--------------------------------------------------------------*/ +/* FatFs Module Application Interface */ +/*--------------------------------------------------------------*/ + +FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */ +FRESULT f_close (FIL* fp); /* Close an open file object */ +FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */ +FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */ +FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */ +FRESULT f_truncate (FIL* fp); /* Truncate the file */ +FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */ +FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */ +FRESULT f_closedir (DIR* dp); /* Close an open directory */ +FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */ +FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */ +FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */ +FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */ +FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */ +FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */ +FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */ +FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */ +FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */ +FRESULT f_chdir (const TCHAR* path); /* Change current directory */ +FRESULT f_chdrive (const TCHAR* path); /* Change current drive */ +FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */ +FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */ +FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */ +FRESULT f_setlabel (const TCHAR* label); /* Set volume label */ +FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */ +FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt); /* Allocate a contiguous block to the file */ +FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */ +FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len); /* Create a FAT volume */ +FRESULT f_fdisk (BYTE pdrv, const LBA_t ptbl[], void* work); /* Divide a physical drive into some partitions */ +FRESULT f_setcp (WORD cp); /* Set current code page */ +int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */ +int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ +int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ +TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ + +/* Some API fucntions are implemented as macro */ + +#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize)) +#define f_error(fp) ((fp)->err) +#define f_tell(fp) ((fp)->fptr) +#define f_size(fp) ((fp)->obj.objsize) +#define f_rewind(fp) f_lseek((fp), 0) +#define f_rewinddir(dp) f_readdir((dp), 0) +#define f_rmdir(path) f_unlink(path) +#define f_unmount(path) f_mount(0, path, 0) + + + + +/*--------------------------------------------------------------*/ +/* Additional Functions */ +/*--------------------------------------------------------------*/ + +/* RTC function (provided by user) */ +#if !FF_FS_READONLY && !FF_FS_NORTC +DWORD get_fattime (void); /* Get current time */ +#endif + + +/* LFN support functions (defined in ffunicode.c) */ + +#if FF_USE_LFN >= 1 +WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */ +WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */ +DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */ +#endif + + +/* O/S dependent functions (samples available in ffsystem.c) */ + +#if FF_USE_LFN == 3 /* Dynamic memory allocation */ +void* ff_memalloc (UINT msize); /* Allocate memory block */ +void ff_memfree (void* mblock); /* Free memory block */ +#endif +#if FF_FS_REENTRANT /* Sync functions */ +int ff_mutex_create (int vol); /* Create a sync object */ +void ff_mutex_delete (int vol); /* Delete a sync object */ +int ff_mutex_take (int vol); /* Lock sync object */ +void ff_mutex_give (int vol); /* Unlock sync object */ +#endif + + + + +/*--------------------------------------------------------------*/ +/* Flags and Offset Address */ +/*--------------------------------------------------------------*/ + +/* File access mode and open method flags (3rd argument of f_open) */ +#define FA_READ 0x01 +#define FA_WRITE 0x02 +#define FA_OPEN_EXISTING 0x00 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA_OPEN_APPEND 0x30 + +/* Fast seek controls (2nd argument of f_lseek) */ +#define CREATE_LINKMAP ((FSIZE_t)0 - 1) + +/* Format options (2nd argument of f_mkfs) */ +#define FM_FAT 0x01 +#define FM_FAT32 0x02 +#define FM_EXFAT 0x04 +#define FM_ANY 0x07 +#define FM_SFD 0x08 + +/* Filesystem type (FATFS.fs_type) */ +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 +#define FS_EXFAT 4 + +/* File attribute bits for directory entry (FILINFO.fattrib) */ +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ + + +#ifdef __cplusplus +} +#endif + +#endif /* FF_DEFINED */ diff --git a/Project/GateWay/source/Module/FatFS/source/ffconf.h b/Project/GateWay/source/Module/FatFS/source/ffconf.h new file mode 100644 index 0000000..156deec --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/source/ffconf.h @@ -0,0 +1,296 @@ +/*---------------------------------------------------------------------------/ +/ Configurations of FatFs Module +/---------------------------------------------------------------------------*/ + +#define FFCONF_DEF 80286 /* Revision ID */ + +/*---------------------------------------------------------------------------/ +/ Function Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_READONLY 0 +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + + +#define FF_FS_MINIMIZE 0 +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: Basic functions are fully enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#define FF_USE_FIND 0 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + + +#define FF_USE_MKFS 1 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + + +#define FF_USE_FASTSEEK 1 +/* This option switches fast seek function. (0:Disable or 1:Enable) */ + + +#define FF_USE_EXPAND 0 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + + +#define FF_USE_CHMOD 0 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ + + +#define FF_USE_LABEL 0 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + + +#define FF_USE_FORWARD 0 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + + +#define FF_USE_STRFUNC 0 +#define FF_PRINT_LLI 1 +#define FF_PRINT_FLOAT 1 +#define FF_STRF_ENCODE 3 +/* FF_USE_STRFUNC switches string functions, f_gets(), f_putc(), f_puts() and +/ f_printf(). +/ +/ 0: Disable. FF_PRINT_LLI, FF_PRINT_FLOAT and FF_STRF_ENCODE have no effect. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. +/ +/ FF_PRINT_LLI = 1 makes f_printf() support long long argument and FF_PRINT_FLOAT = 1/2 +/ makes f_printf() support floating point argument. These features want C99 or later. +/ When FF_LFN_UNICODE >= 1 with LFN enabled, string functions convert the character +/ encoding in it. FF_STRF_ENCODE selects assumption of character encoding ON THE FILE +/ to be read/written via those functions. +/ +/ 0: ANSI/OEM in current CP +/ 1: Unicode in UTF-16LE +/ 2: Unicode in UTF-16BE +/ 3: Unicode in UTF-8 +*/ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define FF_CODE_PAGE 437 +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect code page setting can cause a file open failure. +/ +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +/ 0 - Include all code pages above and configured by f_setcp() +*/ + + +#define FF_USE_LFN 0 +#define FF_MAX_LFN 255 +/* The FF_USE_LFN switches the support for LFN (long file name). +/ +/ 0: Disable LFN. FF_MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function +/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and +/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled. +/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can +/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN +/ specification. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */ + + +#define FF_LFN_UNICODE 0 +/* This option switches the character encoding on the API when LFN is enabled. +/ +/ 0: ANSI/OEM in current CP (TCHAR = char) +/ 1: Unicode in UTF-16 (TCHAR = WCHAR) +/ 2: Unicode in UTF-8 (TCHAR = char) +/ 3: Unicode in UTF-32 (TCHAR = DWORD) +/ +/ Also behavior of string I/O functions will be affected by this option. +/ When LFN is not enabled, this option has no effect. */ + + +#define FF_LFN_BUF 255 +#define FF_SFN_BUF 12 +/* This set of options defines size of file name members in the FILINFO structure +/ which is used to read out directory items. These values should be suffcient for +/ the file names to read. The maximum possible length of the read file name depends +/ on character encoding. When LFN is not enabled, these options have no effect. */ + + +#define FF_FS_RPATH 0 +/* This option configures support for relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define FF_VOLUMES 3 +/* Number of volumes (logical drives) to be used. (1-10) */ + + +#define FF_STR_VOLUME_ID 0 +#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3" +/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings. +/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive +/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each +/ logical drives. Number of items must not be less than FF_VOLUMES. Valid +/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are +/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is +/ not defined, a user defined volume string table is needed as: +/ +/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",... +*/ + + +#define FF_MULTI_PARTITION 0 +/* This option switches support for multiple volumes on the physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When this function is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ function will be available. */ + + +#define FF_MIN_SS 512 +#define FF_MAX_SS 512 +/* This set of options configures the range of sector size to be supported. (512, +/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and +/ harddisk, but a larger value may be required for on-board flash memory and some +/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured +/ for variable sector size mode and disk_ioctl() function needs to implement +/ GET_SECTOR_SIZE command. */ + + +#define FF_LBA64 0 +/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable) +/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */ + + +#define FF_MIN_GPT 0x10000000 +/* Minimum number of sectors to switch GPT as partitioning format in f_mkfs and +/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */ + + +#define FF_USE_TRIM 0 +/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_TINY 0 +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the filesystem object (FATFS) is used for the file data transfer. */ + + +#define FF_FS_EXFAT 0 +/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable) +/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1) +/ Note that enabling exFAT discards ANSI C (C89) compatibility. */ + + +#define FF_FS_NORTC 0 +#define FF_NORTC_MON 1 +#define FF_NORTC_MDAY 1 +#define FF_NORTC_YEAR 2022 +/* The option FF_FS_NORTC switches timestamp feature. If the system does not have +/ an RTC or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable the +/ timestamp feature. Every object modified by FatFs will have a fixed timestamp +/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time. +/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to read current time form real-time clock. FF_NORTC_MON, +/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. +/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */ + + +#define FF_FS_NOFSINFO 0 +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at the first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + +#define FF_FS_LOCK 1 +/* The option FF_FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + + +#define FF_FS_REENTRANT 1 +#define FF_FS_TIMEOUT 1000 +/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this featuer. +/ +/ 0: Disable re-entrancy. FF_FS_TIMEOUT have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_mutex_create(), ff_mutex_delete(), ff_mutex_take() and ff_mutex_give() +/ function, must be added to the project. Samples are available in ffsystem.c. +/ +/ The FF_FS_TIMEOUT defines timeout period in unit of O/S time tick. +*/ + + + +/*--- End of configuration options ---*/ diff --git a/Project/GateWay/source/Module/FatFS/source/ffsystem.c b/Project/GateWay/source/Module/FatFS/source/ffsystem.c new file mode 100644 index 0000000..9f2f813 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/source/ffsystem.c @@ -0,0 +1,223 @@ +/*------------------------------------------------------------------------*/ +/* A Sample Code of User Provided OS Dependent Functions for FatFs */ +/*------------------------------------------------------------------------*/ + +#include "ff.h" + + +#if FF_USE_LFN == 3 /* Use dynamic memory allocation */ + +/*------------------------------------------------------------------------*/ +/* Allocate/Free a Memory Block */ +/*------------------------------------------------------------------------*/ + +#include /* with POSIX API */ + + +void* ff_memalloc ( /* Returns pointer to the allocated memory block (null if not enough core) */ + UINT msize /* Number of bytes to allocate */ +) +{ + return malloc((size_t)msize); /* Allocate a new memory block */ +} + + +void ff_memfree ( + void* mblock /* Pointer to the memory block to free (no effect if null) */ +) +{ + free(mblock); /* Free the memory block */ +} + +#endif + + + + +#if FF_FS_REENTRANT /* Mutal exclusion */ +/*------------------------------------------------------------------------*/ +/* Definitions of Mutex */ +/*------------------------------------------------------------------------*/ + +#define OS_TYPE 5 /* 0:Win32, 1:uITRON4.0, 2:uC/OS-II, 3:FreeRTOS, 4:CMSIS-RTOS ,5:RT-Thread*/ + + +#if OS_TYPE == 0 /* Win32 */ +#include +static HANDLE Mutex[FF_VOLUMES + 1]; /* Table of mutex handle */ + +#elif OS_TYPE == 1 /* uITRON */ +#include "itron.h" +#include "kernel.h" +static mtxid Mutex[FF_VOLUMES + 1]; /* Table of mutex ID */ + +#elif OS_TYPE == 2 /* uc/OS-II */ +#include "includes.h" +static OS_EVENT *Mutex[FF_VOLUMES + 1]; /* Table of mutex pinter */ + +#elif OS_TYPE == 3 /* FreeRTOS */ +#include "FreeRTOS.h" +#include "semphr.h" +static SemaphoreHandle_t Mutex[FF_VOLUMES + 1]; /* Table of mutex handle */ + +#elif OS_TYPE == 4 /* CMSIS-RTOS */ +#include "cmsis_os.h" +static osMutexId Mutex[FF_VOLUMES + 1]; /* Table of mutex ID */ + +#elif OS_TYPE == 5 /* RT-Thread */ +#include "rtthread.h" +static rt_mutex_t Mutex[FF_VOLUMES + 1]; /* Table of mutex ID */ + +#endif + + + +/*------------------------------------------------------------------------*/ +/* Create a Mutex */ +/*------------------------------------------------------------------------*/ +/* This function is called in f_mount function to create a new mutex +/ or semaphore for the volume. When a 0 is returned, the f_mount function +/ fails with FR_INT_ERR. +*/ + +int ff_mutex_create ( /* Returns 1:Function succeeded or 0:Could not create the mutex */ + int vol /* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */ +) +{ +#if OS_TYPE == 0 /* Win32 */ + Mutex[vol] = CreateMutex(NULL, FALSE, NULL); + return (int)(Mutex[vol] != INVALID_HANDLE_VALUE); + +#elif OS_TYPE == 1 /* uITRON */ + T_CMTX cmtx = {TA_TPRI,1}; + + Mutex[vol] = acre_mtx(&cmtx); + return (int)(Mutex[vol] > 0); + +#elif OS_TYPE == 2 /* uC/OS-II */ + OS_ERR err; + + Mutex[vol] = OSMutexCreate(0, &err); + return (int)(err == OS_NO_ERR); + +#elif OS_TYPE == 3 /* FreeRTOS */ + Mutex[vol] = xSemaphoreCreateMutex(); + return (int)(Mutex[vol] != NULL); + +#elif OS_TYPE == 4 /* CMSIS-RTOS */ + osMutexDef(cmsis_os_mutex); + + Mutex[vol] = osMutexCreate(osMutex(cmsis_os_mutex)); + return (int)(Mutex[vol] != NULL); + +#elif OS_TYPE == 5 /* RT-Thread */ + Mutex[vol] = rt_mutex_create("FatFs", RT_IPC_FLAG_FIFO); + return (int)(Mutex[vol] != RT_NULL); +#endif +} + + +/*------------------------------------------------------------------------*/ +/* Delete a Mutex */ +/*------------------------------------------------------------------------*/ +/* This function is called in f_mount function to delete a mutex or +/ semaphore of the volume created with ff_mutex_create function. +*/ + +void ff_mutex_delete ( /* Returns 1:Function succeeded or 0:Could not delete due to an error */ + int vol /* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */ +) +{ +#if OS_TYPE == 0 /* Win32 */ + CloseHandle(Mutex[vol]); + +#elif OS_TYPE == 1 /* uITRON */ + del_mtx(Mutex[vol]); + +#elif OS_TYPE == 2 /* uC/OS-II */ + OS_ERR err; + + OSMutexDel(Mutex[vol], OS_DEL_ALWAYS, &err); + +#elif OS_TYPE == 3 /* FreeRTOS */ + vSemaphoreDelete(Mutex[vol]); + +#elif OS_TYPE == 4 /* CMSIS-RTOS */ + osMutexDelete(Mutex[vol]); + +#elif OS_TYPE == 5 /* RT-Thread */ + rt_mutex_delete(Mutex[vol]); + +#endif +} + + +/*------------------------------------------------------------------------*/ +/* Request a Grant to Access the Volume */ +/*------------------------------------------------------------------------*/ +/* This function is called on enter file functions to lock the volume. +/ When a 0 is returned, the file function fails with FR_TIMEOUT. +*/ + +int ff_mutex_take ( /* Returns 1:Succeeded or 0:Timeout */ + int vol /* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */ +) +{ +#if OS_TYPE == 0 /* Win32 */ + return (int)(WaitForSingleObject(Mutex[vol], FF_FS_TIMEOUT) == WAIT_OBJECT_0); + +#elif OS_TYPE == 1 /* uITRON */ + return (int)(tloc_mtx(Mutex[vol], FF_FS_TIMEOUT) == E_OK); + +#elif OS_TYPE == 2 /* uC/OS-II */ + OS_ERR err; + + OSMutexPend(Mutex[vol], FF_FS_TIMEOUT, &err)); + return (int)(err == OS_NO_ERR); + +#elif OS_TYPE == 3 /* FreeRTOS */ + return (int)(xSemaphoreTake(Mutex[vol], FF_FS_TIMEOUT) == pdTRUE); + +#elif OS_TYPE == 4 /* CMSIS-RTOS */ + return (int)(osMutexWait(Mutex[vol], FF_FS_TIMEOUT) == osOK); + +#elif OS_TYPE == 5 /* RT-Thread */ + return (int)(rt_mutex_take(Mutex[vol], FF_FS_TIMEOUT) == RT_EOK); + +#endif +} + + + +/*------------------------------------------------------------------------*/ +/* Release a Grant to Access the Volume */ +/*------------------------------------------------------------------------*/ +/* This function is called on leave file functions to unlock the volume. +*/ + +void ff_mutex_give ( + int vol /* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */ +) +{ +#if OS_TYPE == 0 /* Win32 */ + ReleaseMutex(Mutex[vol]); + +#elif OS_TYPE == 1 /* uITRON */ + unl_mtx(Mutex[vol]); + +#elif OS_TYPE == 2 /* uC/OS-II */ + OSMutexPost(Mutex[vol]); + +#elif OS_TYPE == 3 /* FreeRTOS */ + xSemaphoreGive(Mutex[vol]); + +#elif OS_TYPE == 4 /* CMSIS-RTOS */ + osMutexRelease(Mutex[vol]); + +#elif OS_TYPE == 5 /* RT-Thread */ + rt_mutex_release(Mutex[vol]); +#endif +} + +#endif /* FF_FS_REENTRANT */ + diff --git a/Project/GateWay/source/Module/FatFS/source/ffunicode.c b/Project/GateWay/source/Module/FatFS/source/ffunicode.c new file mode 100644 index 0000000..e6bcaca --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/source/ffunicode.c @@ -0,0 +1,15593 @@ +/*------------------------------------------------------------------------*/ +/* Unicode Handling Functions for FatFs R0.13 and Later */ +/*------------------------------------------------------------------------*/ +/* This module will occupy a huge memory in the .rodata section when the */ +/* FatFs is configured for LFN with DBCS. If the system has a Unicode */ +/* library for the code conversion, this module should be modified to use */ +/* it to avoid silly memory consumption. */ +/*------------------------------------------------------------------------*/ +/* +/ Copyright (C) 2022, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: +/ +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +*/ + + +#include "ff.h" + +#if FF_USE_LFN != 0 /* This module will be blanked if in non-LFN configuration */ + +#define MERGE2(a, b) a ## b +#define CVTBL(tbl, cp) MERGE2(tbl, cp) + + +/*------------------------------------------------------------------------*/ +/* Code Conversion Tables */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE == 932 || FF_CODE_PAGE == 0 /* Japanese */ +static const WCHAR uni2oem932[] = { /* Unicode --> Shift_JIS pairs */ + 0x00A7, 0x8198, 0x00A8, 0x814E, 0x00B0, 0x818B, 0x00B1, 0x817D, 0x00B4, 0x814C, 0x00B6, 0x81F7, 0x00D7, 0x817E, 0x00F7, 0x8180, + 0x0391, 0x839F, 0x0392, 0x83A0, 0x0393, 0x83A1, 0x0394, 0x83A2, 0x0395, 0x83A3, 0x0396, 0x83A4, 0x0397, 0x83A5, 0x0398, 0x83A6, + 0x0399, 0x83A7, 0x039A, 0x83A8, 0x039B, 0x83A9, 0x039C, 0x83AA, 0x039D, 0x83AB, 0x039E, 0x83AC, 0x039F, 0x83AD, 0x03A0, 0x83AE, + 0x03A1, 0x83AF, 0x03A3, 0x83B0, 0x03A4, 0x83B1, 0x03A5, 0x83B2, 0x03A6, 0x83B3, 0x03A7, 0x83B4, 0x03A8, 0x83B5, 0x03A9, 0x83B6, + 0x03B1, 0x83BF, 0x03B2, 0x83C0, 0x03B3, 0x83C1, 0x03B4, 0x83C2, 0x03B5, 0x83C3, 0x03B6, 0x83C4, 0x03B7, 0x83C5, 0x03B8, 0x83C6, + 0x03B9, 0x83C7, 0x03BA, 0x83C8, 0x03BB, 0x83C9, 0x03BC, 0x83CA, 0x03BD, 0x83CB, 0x03BE, 0x83CC, 0x03BF, 0x83CD, 0x03C0, 0x83CE, + 0x03C1, 0x83CF, 0x03C3, 0x83D0, 0x03C4, 0x83D1, 0x03C5, 0x83D2, 0x03C6, 0x83D3, 0x03C7, 0x83D4, 0x03C8, 0x83D5, 0x03C9, 0x83D6, + 0x0401, 0x8446, 0x0410, 0x8440, 0x0411, 0x8441, 0x0412, 0x8442, 0x0413, 0x8443, 0x0414, 0x8444, 0x0415, 0x8445, 0x0416, 0x8447, + 0x0417, 0x8448, 0x0418, 0x8449, 0x0419, 0x844A, 0x041A, 0x844B, 0x041B, 0x844C, 0x041C, 0x844D, 0x041D, 0x844E, 0x041E, 0x844F, + 0x041F, 0x8450, 0x0420, 0x8451, 0x0421, 0x8452, 0x0422, 0x8453, 0x0423, 0x8454, 0x0424, 0x8455, 0x0425, 0x8456, 0x0426, 0x8457, + 0x0427, 0x8458, 0x0428, 0x8459, 0x0429, 0x845A, 0x042A, 0x845B, 0x042B, 0x845C, 0x042C, 0x845D, 0x042D, 0x845E, 0x042E, 0x845F, + 0x042F, 0x8460, 0x0430, 0x8470, 0x0431, 0x8471, 0x0432, 0x8472, 0x0433, 0x8473, 0x0434, 0x8474, 0x0435, 0x8475, 0x0436, 0x8477, + 0x0437, 0x8478, 0x0438, 0x8479, 0x0439, 0x847A, 0x043A, 0x847B, 0x043B, 0x847C, 0x043C, 0x847D, 0x043D, 0x847E, 0x043E, 0x8480, + 0x043F, 0x8481, 0x0440, 0x8482, 0x0441, 0x8483, 0x0442, 0x8484, 0x0443, 0x8485, 0x0444, 0x8486, 0x0445, 0x8487, 0x0446, 0x8488, + 0x0447, 0x8489, 0x0448, 0x848A, 0x0449, 0x848B, 0x044A, 0x848C, 0x044B, 0x848D, 0x044C, 0x848E, 0x044D, 0x848F, 0x044E, 0x8490, + 0x044F, 0x8491, 0x0451, 0x8476, 0x2010, 0x815D, 0x2015, 0x815C, 0x2018, 0x8165, 0x2019, 0x8166, 0x201C, 0x8167, 0x201D, 0x8168, + 0x2020, 0x81F5, 0x2021, 0x81F6, 0x2025, 0x8164, 0x2026, 0x8163, 0x2030, 0x81F1, 0x2032, 0x818C, 0x2033, 0x818D, 0x203B, 0x81A6, + 0x2103, 0x818E, 0x2116, 0x8782, 0x2121, 0x8784, 0x212B, 0x81F0, 0x2160, 0x8754, 0x2161, 0x8755, 0x2162, 0x8756, 0x2163, 0x8757, + 0x2164, 0x8758, 0x2165, 0x8759, 0x2166, 0x875A, 0x2167, 0x875B, 0x2168, 0x875C, 0x2169, 0x875D, 0x2170, 0xFA40, 0x2171, 0xFA41, + 0x2172, 0xFA42, 0x2173, 0xFA43, 0x2174, 0xFA44, 0x2175, 0xFA45, 0x2176, 0xFA46, 0x2177, 0xFA47, 0x2178, 0xFA48, 0x2179, 0xFA49, + 0x2190, 0x81A9, 0x2191, 0x81AA, 0x2192, 0x81A8, 0x2193, 0x81AB, 0x21D2, 0x81CB, 0x21D4, 0x81CC, 0x2200, 0x81CD, 0x2202, 0x81DD, + 0x2203, 0x81CE, 0x2207, 0x81DE, 0x2208, 0x81B8, 0x220B, 0x81B9, 0x2211, 0x8794, 0x221A, 0x81E3, 0x221D, 0x81E5, 0x221E, 0x8187, + 0x221F, 0x8798, 0x2220, 0x81DA, 0x2225, 0x8161, 0x2227, 0x81C8, 0x2228, 0x81C9, 0x2229, 0x81BF, 0x222A, 0x81BE, 0x222B, 0x81E7, + 0x222C, 0x81E8, 0x222E, 0x8793, 0x2234, 0x8188, 0x2235, 0x81E6, 0x223D, 0x81E4, 0x2252, 0x81E0, 0x2260, 0x8182, 0x2261, 0x81DF, + 0x2266, 0x8185, 0x2267, 0x8186, 0x226A, 0x81E1, 0x226B, 0x81E2, 0x2282, 0x81BC, 0x2283, 0x81BD, 0x2286, 0x81BA, 0x2287, 0x81BB, + 0x22A5, 0x81DB, 0x22BF, 0x8799, 0x2312, 0x81DC, 0x2460, 0x8740, 0x2461, 0x8741, 0x2462, 0x8742, 0x2463, 0x8743, 0x2464, 0x8744, + 0x2465, 0x8745, 0x2466, 0x8746, 0x2467, 0x8747, 0x2468, 0x8748, 0x2469, 0x8749, 0x246A, 0x874A, 0x246B, 0x874B, 0x246C, 0x874C, + 0x246D, 0x874D, 0x246E, 0x874E, 0x246F, 0x874F, 0x2470, 0x8750, 0x2471, 0x8751, 0x2472, 0x8752, 0x2473, 0x8753, 0x2500, 0x849F, + 0x2501, 0x84AA, 0x2502, 0x84A0, 0x2503, 0x84AB, 0x250C, 0x84A1, 0x250F, 0x84AC, 0x2510, 0x84A2, 0x2513, 0x84AD, 0x2514, 0x84A4, + 0x2517, 0x84AF, 0x2518, 0x84A3, 0x251B, 0x84AE, 0x251C, 0x84A5, 0x251D, 0x84BA, 0x2520, 0x84B5, 0x2523, 0x84B0, 0x2524, 0x84A7, + 0x2525, 0x84BC, 0x2528, 0x84B7, 0x252B, 0x84B2, 0x252C, 0x84A6, 0x252F, 0x84B6, 0x2530, 0x84BB, 0x2533, 0x84B1, 0x2534, 0x84A8, + 0x2537, 0x84B8, 0x2538, 0x84BD, 0x253B, 0x84B3, 0x253C, 0x84A9, 0x253F, 0x84B9, 0x2542, 0x84BE, 0x254B, 0x84B4, 0x25A0, 0x81A1, + 0x25A1, 0x81A0, 0x25B2, 0x81A3, 0x25B3, 0x81A2, 0x25BC, 0x81A5, 0x25BD, 0x81A4, 0x25C6, 0x819F, 0x25C7, 0x819E, 0x25CB, 0x819B, + 0x25CE, 0x819D, 0x25CF, 0x819C, 0x25EF, 0x81FC, 0x2605, 0x819A, 0x2606, 0x8199, 0x2640, 0x818A, 0x2642, 0x8189, 0x266A, 0x81F4, + 0x266D, 0x81F3, 0x266F, 0x81F2, 0x3000, 0x8140, 0x3001, 0x8141, 0x3002, 0x8142, 0x3003, 0x8156, 0x3005, 0x8158, 0x3006, 0x8159, + 0x3007, 0x815A, 0x3008, 0x8171, 0x3009, 0x8172, 0x300A, 0x8173, 0x300B, 0x8174, 0x300C, 0x8175, 0x300D, 0x8176, 0x300E, 0x8177, + 0x300F, 0x8178, 0x3010, 0x8179, 0x3011, 0x817A, 0x3012, 0x81A7, 0x3013, 0x81AC, 0x3014, 0x816B, 0x3015, 0x816C, 0x301D, 0x8780, + 0x301F, 0x8781, 0x3041, 0x829F, 0x3042, 0x82A0, 0x3043, 0x82A1, 0x3044, 0x82A2, 0x3045, 0x82A3, 0x3046, 0x82A4, 0x3047, 0x82A5, + 0x3048, 0x82A6, 0x3049, 0x82A7, 0x304A, 0x82A8, 0x304B, 0x82A9, 0x304C, 0x82AA, 0x304D, 0x82AB, 0x304E, 0x82AC, 0x304F, 0x82AD, + 0x3050, 0x82AE, 0x3051, 0x82AF, 0x3052, 0x82B0, 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0x8266, 0xFF28, 0x8267, 0xFF29, 0x8268, 0xFF2A, 0x8269, 0xFF2B, 0x826A, 0xFF2C, 0x826B, 0xFF2D, 0x826C, 0xFF2E, 0x826D, + 0xFF2F, 0x826E, 0xFF30, 0x826F, 0xFF31, 0x8270, 0xFF32, 0x8271, 0xFF33, 0x8272, 0xFF34, 0x8273, 0xFF35, 0x8274, 0xFF36, 0x8275, + 0xFF37, 0x8276, 0xFF38, 0x8277, 0xFF39, 0x8278, 0xFF3A, 0x8279, 0xFF3B, 0x816D, 0xFF3C, 0x815F, 0xFF3D, 0x816E, 0xFF3E, 0x814F, + 0xFF3F, 0x8151, 0xFF40, 0x814D, 0xFF41, 0x8281, 0xFF42, 0x8282, 0xFF43, 0x8283, 0xFF44, 0x8284, 0xFF45, 0x8285, 0xFF46, 0x8286, + 0xFF47, 0x8287, 0xFF48, 0x8288, 0xFF49, 0x8289, 0xFF4A, 0x828A, 0xFF4B, 0x828B, 0xFF4C, 0x828C, 0xFF4D, 0x828D, 0xFF4E, 0x828E, + 0xFF4F, 0x828F, 0xFF50, 0x8290, 0xFF51, 0x8291, 0xFF52, 0x8292, 0xFF53, 0x8293, 0xFF54, 0x8294, 0xFF55, 0x8295, 0xFF56, 0x8296, + 0xFF57, 0x8297, 0xFF58, 0x8298, 0xFF59, 0x8299, 0xFF5A, 0x829A, 0xFF5B, 0x816F, 0xFF5C, 0x8162, 0xFF5D, 0x8170, 0xFF5E, 0x8160, + 0xFF61, 0x00A1, 0xFF62, 0x00A2, 0xFF63, 0x00A3, 0xFF64, 0x00A4, 0xFF65, 0x00A5, 0xFF66, 0x00A6, 0xFF67, 0x00A7, 0xFF68, 0x00A8, + 0xFF69, 0x00A9, 0xFF6A, 0x00AA, 0xFF6B, 0x00AB, 0xFF6C, 0x00AC, 0xFF6D, 0x00AD, 0xFF6E, 0x00AE, 0xFF6F, 0x00AF, 0xFF70, 0x00B0, + 0xFF71, 0x00B1, 0xFF72, 0x00B2, 0xFF73, 0x00B3, 0xFF74, 0x00B4, 0xFF75, 0x00B5, 0xFF76, 0x00B6, 0xFF77, 0x00B7, 0xFF78, 0x00B8, + 0xFF79, 0x00B9, 0xFF7A, 0x00BA, 0xFF7B, 0x00BB, 0xFF7C, 0x00BC, 0xFF7D, 0x00BD, 0xFF7E, 0x00BE, 0xFF7F, 0x00BF, 0xFF80, 0x00C0, + 0xFF81, 0x00C1, 0xFF82, 0x00C2, 0xFF83, 0x00C3, 0xFF84, 0x00C4, 0xFF85, 0x00C5, 0xFF86, 0x00C6, 0xFF87, 0x00C7, 0xFF88, 0x00C8, + 0xFF89, 0x00C9, 0xFF8A, 0x00CA, 0xFF8B, 0x00CB, 0xFF8C, 0x00CC, 0xFF8D, 0x00CD, 0xFF8E, 0x00CE, 0xFF8F, 0x00CF, 0xFF90, 0x00D0, + 0xFF91, 0x00D1, 0xFF92, 0x00D2, 0xFF93, 0x00D3, 0xFF94, 0x00D4, 0xFF95, 0x00D5, 0xFF96, 0x00D6, 0xFF97, 0x00D7, 0xFF98, 0x00D8, + 0xFF99, 0x00D9, 0xFF9A, 0x00DA, 0xFF9B, 0x00DB, 0xFF9C, 0x00DC, 0xFF9D, 0x00DD, 0xFF9E, 0x00DE, 0xFF9F, 0x00DF, 0xFFE0, 0x8191, + 0xFFE1, 0x8192, 0xFFE2, 0x81CA, 0xFFE3, 0x8150, 0xFFE4, 0xFA55, 0xFFE5, 0x818F, 0, 0 +}; + +static const WCHAR oem2uni932[] = { /* Shift_JIS --> Unicode pairs */ + 0x00A1, 0xFF61, 0x00A2, 0xFF62, 0x00A3, 0xFF63, 0x00A4, 0xFF64, 0x00A5, 0xFF65, 0x00A6, 0xFF66, 0x00A7, 0xFF67, 0x00A8, 0xFF68, + 0x00A9, 0xFF69, 0x00AA, 0xFF6A, 0x00AB, 0xFF6B, 0x00AC, 0xFF6C, 0x00AD, 0xFF6D, 0x00AE, 0xFF6E, 0x00AF, 0xFF6F, 0x00B0, 0xFF70, + 0x00B1, 0xFF71, 0x00B2, 0xFF72, 0x00B3, 0xFF73, 0x00B4, 0xFF74, 0x00B5, 0xFF75, 0x00B6, 0xFF76, 0x00B7, 0xFF77, 0x00B8, 0xFF78, + 0x00B9, 0xFF79, 0x00BA, 0xFF7A, 0x00BB, 0xFF7B, 0x00BC, 0xFF7C, 0x00BD, 0xFF7D, 0x00BE, 0xFF7E, 0x00BF, 0xFF7F, 0x00C0, 0xFF80, + 0x00C1, 0xFF81, 0x00C2, 0xFF82, 0x00C3, 0xFF83, 0x00C4, 0xFF84, 0x00C5, 0xFF85, 0x00C6, 0xFF86, 0x00C7, 0xFF87, 0x00C8, 0xFF88, + 0x00C9, 0xFF89, 0x00CA, 0xFF8A, 0x00CB, 0xFF8B, 0x00CC, 0xFF8C, 0x00CD, 0xFF8D, 0x00CE, 0xFF8E, 0x00CF, 0xFF8F, 0x00D0, 0xFF90, + 0x00D1, 0xFF91, 0x00D2, 0xFF92, 0x00D3, 0xFF93, 0x00D4, 0xFF94, 0x00D5, 0xFF95, 0x00D6, 0xFF96, 0x00D7, 0xFF97, 0x00D8, 0xFF98, + 0x00D9, 0xFF99, 0x00DA, 0xFF9A, 0x00DB, 0xFF9B, 0x00DC, 0xFF9C, 0x00DD, 0xFF9D, 0x00DE, 0xFF9E, 0x00DF, 0xFF9F, 0x8140, 0x3000, + 0x8141, 0x3001, 0x8142, 0x3002, 0x8143, 0xFF0C, 0x8144, 0xFF0E, 0x8145, 0x30FB, 0x8146, 0xFF1A, 0x8147, 0xFF1B, 0x8148, 0xFF1F, + 0x8149, 0xFF01, 0x814A, 0x309B, 0x814B, 0x309C, 0x814C, 0x00B4, 0x814D, 0xFF40, 0x814E, 0x00A8, 0x814F, 0xFF3E, 0x8150, 0xFFE3, + 0x8151, 0xFF3F, 0x8152, 0x30FD, 0x8153, 0x30FE, 0x8154, 0x309D, 0x8155, 0x309E, 0x8156, 0x3003, 0x8157, 0x4EDD, 0x8158, 0x3005, + 0x8159, 0x3006, 0x815A, 0x3007, 0x815B, 0x30FC, 0x815C, 0x2015, 0x815D, 0x2010, 0x815E, 0xFF0F, 0x815F, 0xFF3C, 0x8160, 0xFF5E, + 0x8161, 0x2225, 0x8162, 0xFF5C, 0x8163, 0x2026, 0x8164, 0x2025, 0x8165, 0x2018, 0x8166, 0x2019, 0x8167, 0x201C, 0x8168, 0x201D, + 0x8169, 0xFF08, 0x816A, 0xFF09, 0x816B, 0x3014, 0x816C, 0x3015, 0x816D, 0xFF3B, 0x816E, 0xFF3D, 0x816F, 0xFF5B, 0x8170, 0xFF5D, + 0x8171, 0x3008, 0x8172, 0x3009, 0x8173, 0x300A, 0x8174, 0x300B, 0x8175, 0x300C, 0x8176, 0x300D, 0x8177, 0x300E, 0x8178, 0x300F, + 0x8179, 0x3010, 0x817A, 0x3011, 0x817B, 0xFF0B, 0x817C, 0xFF0D, 0x817D, 0x00B1, 0x817E, 0x00D7, 0x8180, 0x00F7, 0x8181, 0xFF1D, + 0x8182, 0x2260, 0x8183, 0xFF1C, 0x8184, 0xFF1E, 0x8185, 0x2266, 0x8186, 0x2267, 0x8187, 0x221E, 0x8188, 0x2234, 0x8189, 0x2642, + 0x818A, 0x2640, 0x818B, 0x00B0, 0x818C, 0x2032, 0x818D, 0x2033, 0x818E, 0x2103, 0x818F, 0xFFE5, 0x8190, 0xFF04, 0x8191, 0xFFE0, + 0x8192, 0xFFE1, 0x8193, 0xFF05, 0x8194, 0xFF03, 0x8195, 0xFF06, 0x8196, 0xFF0A, 0x8197, 0xFF20, 0x8198, 0x00A7, 0x8199, 0x2606, + 0x819A, 0x2605, 0x819B, 0x25CB, 0x819C, 0x25CF, 0x819D, 0x25CE, 0x819E, 0x25C7, 0x819F, 0x25C6, 0x81A0, 0x25A1, 0x81A1, 0x25A0, + 0x81A2, 0x25B3, 0x81A3, 0x25B2, 0x81A4, 0x25BD, 0x81A5, 0x25BC, 0x81A6, 0x203B, 0x81A7, 0x3012, 0x81A8, 0x2192, 0x81A9, 0x2190, + 0x81AA, 0x2191, 0x81AB, 0x2193, 0x81AC, 0x3013, 0x81B8, 0x2208, 0x81B9, 0x220B, 0x81BA, 0x2286, 0x81BB, 0x2287, 0x81BC, 0x2282, + 0x81BD, 0x2283, 0x81BE, 0x222A, 0x81BF, 0x2229, 0x81C8, 0x2227, 0x81C9, 0x2228, 0x81CA, 0xFFE2, 0x81CB, 0x21D2, 0x81CC, 0x21D4, + 0x81CD, 0x2200, 0x81CE, 0x2203, 0x81DA, 0x2220, 0x81DB, 0x22A5, 0x81DC, 0x2312, 0x81DD, 0x2202, 0x81DE, 0x2207, 0x81DF, 0x2261, + 0x81E0, 0x2252, 0x81E1, 0x226A, 0x81E2, 0x226B, 0x81E3, 0x221A, 0x81E4, 0x223D, 0x81E5, 0x221D, 0x81E6, 0x2235, 0x81E7, 0x222B, + 0x81E8, 0x222C, 0x81F0, 0x212B, 0x81F1, 0x2030, 0x81F2, 0x266F, 0x81F3, 0x266D, 0x81F4, 0x266A, 0x81F5, 0x2020, 0x81F6, 0x2021, + 0x81F7, 0x00B6, 0x81FC, 0x25EF, 0x824F, 0xFF10, 0x8250, 0xFF11, 0x8251, 0xFF12, 0x8252, 0xFF13, 0x8253, 0xFF14, 0x8254, 0xFF15, + 0x8255, 0xFF16, 0x8256, 0xFF17, 0x8257, 0xFF18, 0x8258, 0xFF19, 0x8260, 0xFF21, 0x8261, 0xFF22, 0x8262, 0xFF23, 0x8263, 0xFF24, + 0x8264, 0xFF25, 0x8265, 0xFF26, 0x8266, 0xFF27, 0x8267, 0xFF28, 0x8268, 0xFF29, 0x8269, 0xFF2A, 0x826A, 0xFF2B, 0x826B, 0xFF2C, + 0x826C, 0xFF2D, 0x826D, 0xFF2E, 0x826E, 0xFF2F, 0x826F, 0xFF30, 0x8270, 0xFF31, 0x8271, 0xFF32, 0x8272, 0xFF33, 0x8273, 0xFF34, + 0x8274, 0xFF35, 0x8275, 0xFF36, 0x8276, 0xFF37, 0x8277, 0xFF38, 0x8278, 0xFF39, 0x8279, 0xFF3A, 0x8281, 0xFF41, 0x8282, 0xFF42, + 0x8283, 0xFF43, 0x8284, 0xFF44, 0x8285, 0xFF45, 0x8286, 0xFF46, 0x8287, 0xFF47, 0x8288, 0xFF48, 0x8289, 0xFF49, 0x828A, 0xFF4A, + 0x828B, 0xFF4B, 0x828C, 0xFF4C, 0x828D, 0xFF4D, 0x828E, 0xFF4E, 0x828F, 0xFF4F, 0x8290, 0xFF50, 0x8291, 0xFF51, 0x8292, 0xFF52, + 0x8293, 0xFF53, 0x8294, 0xFF54, 0x8295, 0xFF55, 0x8296, 0xFF56, 0x8297, 0xFF57, 0x8298, 0xFF58, 0x8299, 0xFF59, 0x829A, 0xFF5A, + 0x829F, 0x3041, 0x82A0, 0x3042, 0x82A1, 0x3043, 0x82A2, 0x3044, 0x82A3, 0x3045, 0x82A4, 0x3046, 0x82A5, 0x3047, 0x82A6, 0x3048, + 0x82A7, 0x3049, 0x82A8, 0x304A, 0x82A9, 0x304B, 0x82AA, 0x304C, 0x82AB, 0x304D, 0x82AC, 0x304E, 0x82AD, 0x304F, 0x82AE, 0x3050, + 0x82AF, 0x3051, 0x82B0, 0x3052, 0x82B1, 0x3053, 0x82B2, 0x3054, 0x82B3, 0x3055, 0x82B4, 0x3056, 0x82B5, 0x3057, 0x82B6, 0x3058, + 0x82B7, 0x3059, 0x82B8, 0x305A, 0x82B9, 0x305B, 0x82BA, 0x305C, 0x82BB, 0x305D, 0x82BC, 0x305E, 0x82BD, 0x305F, 0x82BE, 0x3060, + 0x82BF, 0x3061, 0x82C0, 0x3062, 0x82C1, 0x3063, 0x82C2, 0x3064, 0x82C3, 0x3065, 0x82C4, 0x3066, 0x82C5, 0x3067, 0x82C6, 0x3068, + 0x82C7, 0x3069, 0x82C8, 0x306A, 0x82C9, 0x306B, 0x82CA, 0x306C, 0x82CB, 0x306D, 0x82CC, 0x306E, 0x82CD, 0x306F, 0x82CE, 0x3070, + 0x82CF, 0x3071, 0x82D0, 0x3072, 0x82D1, 0x3073, 0x82D2, 0x3074, 0x82D3, 0x3075, 0x82D4, 0x3076, 0x82D5, 0x3077, 0x82D6, 0x3078, + 0x82D7, 0x3079, 0x82D8, 0x307A, 0x82D9, 0x307B, 0x82DA, 0x307C, 0x82DB, 0x307D, 0x82DC, 0x307E, 0x82DD, 0x307F, 0x82DE, 0x3080, + 0x82DF, 0x3081, 0x82E0, 0x3082, 0x82E1, 0x3083, 0x82E2, 0x3084, 0x82E3, 0x3085, 0x82E4, 0x3086, 0x82E5, 0x3087, 0x82E6, 0x3088, + 0x82E7, 0x3089, 0x82E8, 0x308A, 0x82E9, 0x308B, 0x82EA, 0x308C, 0x82EB, 0x308D, 0x82EC, 0x308E, 0x82ED, 0x308F, 0x82EE, 0x3090, + 0x82EF, 0x3091, 0x82F0, 0x3092, 0x82F1, 0x3093, 0x8340, 0x30A1, 0x8341, 0x30A2, 0x8342, 0x30A3, 0x8343, 0x30A4, 0x8344, 0x30A5, + 0x8345, 0x30A6, 0x8346, 0x30A7, 0x8347, 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0xFBBC, 0x91DE, 0xFBBD, 0x91ED, 0xFBBE, 0x91EE, 0xFBBF, 0x91E4, 0xFBC0, 0x91E5, 0xFBC1, 0x9206, 0xFBC2, 0x9210, 0xFBC3, 0x920A, + 0xFBC4, 0x923A, 0xFBC5, 0x9240, 0xFBC6, 0x923C, 0xFBC7, 0x924E, 0xFBC8, 0x9259, 0xFBC9, 0x9251, 0xFBCA, 0x9239, 0xFBCB, 0x9267, + 0xFBCC, 0x92A7, 0xFBCD, 0x9277, 0xFBCE, 0x9278, 0xFBCF, 0x92E7, 0xFBD0, 0x92D7, 0xFBD1, 0x92D9, 0xFBD2, 0x92D0, 0xFBD3, 0xFA27, + 0xFBD4, 0x92D5, 0xFBD5, 0x92E0, 0xFBD6, 0x92D3, 0xFBD7, 0x9325, 0xFBD8, 0x9321, 0xFBD9, 0x92FB, 0xFBDA, 0xFA28, 0xFBDB, 0x931E, + 0xFBDC, 0x92FF, 0xFBDD, 0x931D, 0xFBDE, 0x9302, 0xFBDF, 0x9370, 0xFBE0, 0x9357, 0xFBE1, 0x93A4, 0xFBE2, 0x93C6, 0xFBE3, 0x93DE, + 0xFBE4, 0x93F8, 0xFBE5, 0x9431, 0xFBE6, 0x9445, 0xFBE7, 0x9448, 0xFBE8, 0x9592, 0xFBE9, 0xF9DC, 0xFBEA, 0xFA29, 0xFBEB, 0x969D, + 0xFBEC, 0x96AF, 0xFBED, 0x9733, 0xFBEE, 0x973B, 0xFBEF, 0x9743, 0xFBF0, 0x974D, 0xFBF1, 0x974F, 0xFBF2, 0x9751, 0xFBF3, 0x9755, + 0xFBF4, 0x9857, 0xFBF5, 0x9865, 0xFBF6, 0xFA2A, 0xFBF7, 0xFA2B, 0xFBF8, 0x9927, 0xFBF9, 0xFA2C, 0xFBFA, 0x999E, 0xFBFB, 0x9A4E, + 0xFBFC, 0x9AD9, 0xFC40, 0x9ADC, 0xFC41, 0x9B75, 0xFC42, 0x9B72, 0xFC43, 0x9B8F, 0xFC44, 0x9BB1, 0xFC45, 0x9BBB, 0xFC46, 0x9C00, + 0xFC47, 0x9D70, 0xFC48, 0x9D6B, 0xFC49, 0xFA2D, 0xFC4A, 0x9E19, 0xFC4B, 0x9ED1, 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 936 || FF_CODE_PAGE == 0 /* Simplified Chinese */ +static const WCHAR uni2oem936[] = { /* Unicode --> GBK pairs */ + 0x00A4, 0xA1E8, 0x00A7, 0xA1EC, 0x00A8, 0xA1A7, 0x00B0, 0xA1E3, 0x00B1, 0xA1C0, 0x00B7, 0xA1A4, 0x00D7, 0xA1C1, 0x00E0, 0xA8A4, + 0x00E1, 0xA8A2, 0x00E8, 0xA8A8, 0x00E9, 0xA8A6, 0x00EA, 0xA8BA, 0x00EC, 0xA8AC, 0x00ED, 0xA8AA, 0x00F2, 0xA8B0, 0x00F3, 0xA8AE, + 0x00F7, 0xA1C2, 0x00F9, 0xA8B4, 0x00FA, 0xA8B2, 0x00FC, 0xA8B9, 0x0101, 0xA8A1, 0x0113, 0xA8A5, 0x011B, 0xA8A7, 0x012B, 0xA8A9, + 0x0144, 0xA8BD, 0x0148, 0xA8BE, 0x014D, 0xA8AD, 0x016B, 0xA8B1, 0x01CE, 0xA8A3, 0x01D0, 0xA8AB, 0x01D2, 0xA8AF, 0x01D4, 0xA8B3, + 0x01D6, 0xA8B5, 0x01D8, 0xA8B6, 0x01DA, 0xA8B7, 0x01DC, 0xA8B8, 0x0251, 0xA8BB, 0x0261, 0xA8C0, 0x02C7, 0xA1A6, 0x02C9, 0xA1A5, + 0x02CA, 0xA840, 0x02CB, 0xA841, 0x02D9, 0xA842, 0x0391, 0xA6A1, 0x0392, 0xA6A2, 0x0393, 0xA6A3, 0x0394, 0xA6A4, 0x0395, 0xA6A5, + 0x0396, 0xA6A6, 0x0397, 0xA6A7, 0x0398, 0xA6A8, 0x0399, 0xA6A9, 0x039A, 0xA6AA, 0x039B, 0xA6AB, 0x039C, 0xA6AC, 0x039D, 0xA6AD, + 0x039E, 0xA6AE, 0x039F, 0xA6AF, 0x03A0, 0xA6B0, 0x03A1, 0xA6B1, 0x03A3, 0xA6B2, 0x03A4, 0xA6B3, 0x03A5, 0xA6B4, 0x03A6, 0xA6B5, + 0x03A7, 0xA6B6, 0x03A8, 0xA6B7, 0x03A9, 0xA6B8, 0x03B1, 0xA6C1, 0x03B2, 0xA6C2, 0x03B3, 0xA6C3, 0x03B4, 0xA6C4, 0x03B5, 0xA6C5, + 0x03B6, 0xA6C6, 0x03B7, 0xA6C7, 0x03B8, 0xA6C8, 0x03B9, 0xA6C9, 0x03BA, 0xA6CA, 0x03BB, 0xA6CB, 0x03BC, 0xA6CC, 0x03BD, 0xA6CD, + 0x03BE, 0xA6CE, 0x03BF, 0xA6CF, 0x03C0, 0xA6D0, 0x03C1, 0xA6D1, 0x03C3, 0xA6D2, 0x03C4, 0xA6D3, 0x03C5, 0xA6D4, 0x03C6, 0xA6D5, + 0x03C7, 0xA6D6, 0x03C8, 0xA6D7, 0x03C9, 0xA6D8, 0x0401, 0xA7A7, 0x0410, 0xA7A1, 0x0411, 0xA7A2, 0x0412, 0xA7A3, 0x0413, 0xA7A4, + 0x0414, 0xA7A5, 0x0415, 0xA7A6, 0x0416, 0xA7A8, 0x0417, 0xA7A9, 0x0418, 0xA7AA, 0x0419, 0xA7AB, 0x041A, 0xA7AC, 0x041B, 0xA7AD, + 0x041C, 0xA7AE, 0x041D, 0xA7AF, 0x041E, 0xA7B0, 0x041F, 0xA7B1, 0x0420, 0xA7B2, 0x0421, 0xA7B3, 0x0422, 0xA7B4, 0x0423, 0xA7B5, + 0x0424, 0xA7B6, 0x0425, 0xA7B7, 0x0426, 0xA7B8, 0x0427, 0xA7B9, 0x0428, 0xA7BA, 0x0429, 0xA7BB, 0x042A, 0xA7BC, 0x042B, 0xA7BD, + 0x042C, 0xA7BE, 0x042D, 0xA7BF, 0x042E, 0xA7C0, 0x042F, 0xA7C1, 0x0430, 0xA7D1, 0x0431, 0xA7D2, 0x0432, 0xA7D3, 0x0433, 0xA7D4, + 0x0434, 0xA7D5, 0x0435, 0xA7D6, 0x0436, 0xA7D8, 0x0437, 0xA7D9, 0x0438, 0xA7DA, 0x0439, 0xA7DB, 0x043A, 0xA7DC, 0x043B, 0xA7DD, + 0x043C, 0xA7DE, 0x043D, 0xA7DF, 0x043E, 0xA7E0, 0x043F, 0xA7E1, 0x0440, 0xA7E2, 0x0441, 0xA7E3, 0x0442, 0xA7E4, 0x0443, 0xA7E5, + 0x0444, 0xA7E6, 0x0445, 0xA7E7, 0x0446, 0xA7E8, 0x0447, 0xA7E9, 0x0448, 0xA7EA, 0x0449, 0xA7EB, 0x044A, 0xA7EC, 0x044B, 0xA7ED, + 0x044C, 0xA7EE, 0x044D, 0xA7EF, 0x044E, 0xA7F0, 0x044F, 0xA7F1, 0x0451, 0xA7D7, 0x2010, 0xA95C, 0x2013, 0xA843, 0x2014, 0xA1AA, + 0x2015, 0xA844, 0x2016, 0xA1AC, 0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1, 0x2025, 0xA845, 0x2026, 0xA1AD, + 0x2030, 0xA1EB, 0x2032, 0xA1E4, 0x2033, 0xA1E5, 0x2035, 0xA846, 0x203B, 0xA1F9, 0x20AC, 0x0080, 0x2103, 0xA1E6, 0x2105, 0xA847, + 0x2109, 0xA848, 0x2116, 0xA1ED, 0x2121, 0xA959, 0x2160, 0xA2F1, 0x2161, 0xA2F2, 0x2162, 0xA2F3, 0x2163, 0xA2F4, 0x2164, 0xA2F5, + 0x2165, 0xA2F6, 0x2166, 0xA2F7, 0x2167, 0xA2F8, 0x2168, 0xA2F9, 0x2169, 0xA2FA, 0x216A, 0xA2FB, 0x216B, 0xA2FC, 0x2170, 0xA2A1, + 0x2171, 0xA2A2, 0x2172, 0xA2A3, 0x2173, 0xA2A4, 0x2174, 0xA2A5, 0x2175, 0xA2A6, 0x2176, 0xA2A7, 0x2177, 0xA2A8, 0x2178, 0xA2A9, + 0x2179, 0xA2AA, 0x2190, 0xA1FB, 0x2191, 0xA1FC, 0x2192, 0xA1FA, 0x2193, 0xA1FD, 0x2196, 0xA849, 0x2197, 0xA84A, 0x2198, 0xA84B, + 0x2199, 0xA84C, 0x2208, 0xA1CA, 0x220F, 0xA1C7, 0x2211, 0xA1C6, 0x2215, 0xA84D, 0x221A, 0xA1CC, 0x221D, 0xA1D8, 0x221E, 0xA1DE, + 0x221F, 0xA84E, 0x2220, 0xA1CF, 0x2223, 0xA84F, 0x2225, 0xA1CE, 0x2227, 0xA1C4, 0x2228, 0xA1C5, 0x2229, 0xA1C9, 0x222A, 0xA1C8, + 0x222B, 0xA1D2, 0x222E, 0xA1D3, 0x2234, 0xA1E0, 0x2235, 0xA1DF, 0x2236, 0xA1C3, 0x2237, 0xA1CB, 0x223D, 0xA1D7, 0x2248, 0xA1D6, + 0x224C, 0xA1D5, 0x2252, 0xA850, 0x2260, 0xA1D9, 0x2261, 0xA1D4, 0x2264, 0xA1DC, 0x2265, 0xA1DD, 0x2266, 0xA851, 0x2267, 0xA852, + 0x226E, 0xA1DA, 0x226F, 0xA1DB, 0x2295, 0xA892, 0x2299, 0xA1D1, 0x22A5, 0xA1CD, 0x22BF, 0xA853, 0x2312, 0xA1D0, 0x2460, 0xA2D9, + 0x2461, 0xA2DA, 0x2462, 0xA2DB, 0x2463, 0xA2DC, 0x2464, 0xA2DD, 0x2465, 0xA2DE, 0x2466, 0xA2DF, 0x2467, 0xA2E0, 0x2468, 0xA2E1, + 0x2469, 0xA2E2, 0x2474, 0xA2C5, 0x2475, 0xA2C6, 0x2476, 0xA2C7, 0x2477, 0xA2C8, 0x2478, 0xA2C9, 0x2479, 0xA2CA, 0x247A, 0xA2CB, + 0x247B, 0xA2CC, 0x247C, 0xA2CD, 0x247D, 0xA2CE, 0x247E, 0xA2CF, 0x247F, 0xA2D0, 0x2480, 0xA2D1, 0x2481, 0xA2D2, 0x2482, 0xA2D3, + 0x2483, 0xA2D4, 0x2484, 0xA2D5, 0x2485, 0xA2D6, 0x2486, 0xA2D7, 0x2487, 0xA2D8, 0x2488, 0xA2B1, 0x2489, 0xA2B2, 0x248A, 0xA2B3, + 0x248B, 0xA2B4, 0x248C, 0xA2B5, 0x248D, 0xA2B6, 0x248E, 0xA2B7, 0x248F, 0xA2B8, 0x2490, 0xA2B9, 0x2491, 0xA2BA, 0x2492, 0xA2BB, + 0x2493, 0xA2BC, 0x2494, 0xA2BD, 0x2495, 0xA2BE, 0x2496, 0xA2BF, 0x2497, 0xA2C0, 0x2498, 0xA2C1, 0x2499, 0xA2C2, 0x249A, 0xA2C3, + 0x249B, 0xA2C4, 0x2500, 0xA9A4, 0x2501, 0xA9A5, 0x2502, 0xA9A6, 0x2503, 0xA9A7, 0x2504, 0xA9A8, 0x2505, 0xA9A9, 0x2506, 0xA9AA, + 0x2507, 0xA9AB, 0x2508, 0xA9AC, 0x2509, 0xA9AD, 0x250A, 0xA9AE, 0x250B, 0xA9AF, 0x250C, 0xA9B0, 0x250D, 0xA9B1, 0x250E, 0xA9B2, + 0x250F, 0xA9B3, 0x2510, 0xA9B4, 0x2511, 0xA9B5, 0x2512, 0xA9B6, 0x2513, 0xA9B7, 0x2514, 0xA9B8, 0x2515, 0xA9B9, 0x2516, 0xA9BA, + 0x2517, 0xA9BB, 0x2518, 0xA9BC, 0x2519, 0xA9BD, 0x251A, 0xA9BE, 0x251B, 0xA9BF, 0x251C, 0xA9C0, 0x251D, 0xA9C1, 0x251E, 0xA9C2, + 0x251F, 0xA9C3, 0x2520, 0xA9C4, 0x2521, 0xA9C5, 0x2522, 0xA9C6, 0x2523, 0xA9C7, 0x2524, 0xA9C8, 0x2525, 0xA9C9, 0x2526, 0xA9CA, + 0x2527, 0xA9CB, 0x2528, 0xA9CC, 0x2529, 0xA9CD, 0x252A, 0xA9CE, 0x252B, 0xA9CF, 0x252C, 0xA9D0, 0x252D, 0xA9D1, 0x252E, 0xA9D2, + 0x252F, 0xA9D3, 0x2530, 0xA9D4, 0x2531, 0xA9D5, 0x2532, 0xA9D6, 0x2533, 0xA9D7, 0x2534, 0xA9D8, 0x2535, 0xA9D9, 0x2536, 0xA9DA, + 0x2537, 0xA9DB, 0x2538, 0xA9DC, 0x2539, 0xA9DD, 0x253A, 0xA9DE, 0x253B, 0xA9DF, 0x253C, 0xA9E0, 0x253D, 0xA9E1, 0x253E, 0xA9E2, + 0x253F, 0xA9E3, 0x2540, 0xA9E4, 0x2541, 0xA9E5, 0x2542, 0xA9E6, 0x2543, 0xA9E7, 0x2544, 0xA9E8, 0x2545, 0xA9E9, 0x2546, 0xA9EA, + 0x2547, 0xA9EB, 0x2548, 0xA9EC, 0x2549, 0xA9ED, 0x254A, 0xA9EE, 0x254B, 0xA9EF, 0x2550, 0xA854, 0x2551, 0xA855, 0x2552, 0xA856, + 0x2553, 0xA857, 0x2554, 0xA858, 0x2555, 0xA859, 0x2556, 0xA85A, 0x2557, 0xA85B, 0x2558, 0xA85C, 0x2559, 0xA85D, 0x255A, 0xA85E, + 0x255B, 0xA85F, 0x255C, 0xA860, 0x255D, 0xA861, 0x255E, 0xA862, 0x255F, 0xA863, 0x2560, 0xA864, 0x2561, 0xA865, 0x2562, 0xA866, + 0x2563, 0xA867, 0x2564, 0xA868, 0x2565, 0xA869, 0x2566, 0xA86A, 0x2567, 0xA86B, 0x2568, 0xA86C, 0x2569, 0xA86D, 0x256A, 0xA86E, + 0x256B, 0xA86F, 0x256C, 0xA870, 0x256D, 0xA871, 0x256E, 0xA872, 0x256F, 0xA873, 0x2570, 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0x9F2F, 0xF7F9, 0x9F30, 0xFC9F, 0x9F31, 0xFCA0, 0x9F32, 0xFD40, + 0x9F33, 0xFD41, 0x9F34, 0xFD42, 0x9F35, 0xFD43, 0x9F36, 0xFD44, 0x9F37, 0xF7FB, 0x9F38, 0xFD45, 0x9F39, 0xF7FA, 0x9F3A, 0xFD46, + 0x9F3B, 0xB1C7, 0x9F3C, 0xFD47, 0x9F3D, 0xF7FC, 0x9F3E, 0xF7FD, 0x9F3F, 0xFD48, 0x9F40, 0xFD49, 0x9F41, 0xFD4A, 0x9F42, 0xFD4B, + 0x9F43, 0xFD4C, 0x9F44, 0xF7FE, 0x9F45, 0xFD4D, 0x9F46, 0xFD4E, 0x9F47, 0xFD4F, 0x9F48, 0xFD50, 0x9F49, 0xFD51, 0x9F4A, 0xFD52, + 0x9F4B, 0xFD53, 0x9F4C, 0xFD54, 0x9F4D, 0xFD55, 0x9F4E, 0xFD56, 0x9F4F, 0xFD57, 0x9F50, 0xC6EB, 0x9F51, 0xECB4, 0x9F52, 0xFD58, + 0x9F53, 0xFD59, 0x9F54, 0xFD5A, 0x9F55, 0xFD5B, 0x9F56, 0xFD5C, 0x9F57, 0xFD5D, 0x9F58, 0xFD5E, 0x9F59, 0xFD5F, 0x9F5A, 0xFD60, + 0x9F5B, 0xFD61, 0x9F5C, 0xFD62, 0x9F5D, 0xFD63, 0x9F5E, 0xFD64, 0x9F5F, 0xFD65, 0x9F60, 0xFD66, 0x9F61, 0xFD67, 0x9F62, 0xFD68, + 0x9F63, 0xFD69, 0x9F64, 0xFD6A, 0x9F65, 0xFD6B, 0x9F66, 0xFD6C, 0x9F67, 0xFD6D, 0x9F68, 0xFD6E, 0x9F69, 0xFD6F, 0x9F6A, 0xFD70, + 0x9F6B, 0xFD71, 0x9F6C, 0xFD72, 0x9F6D, 0xFD73, 0x9F6E, 0xFD74, 0x9F6F, 0xFD75, 0x9F70, 0xFD76, 0x9F71, 0xFD77, 0x9F72, 0xFD78, + 0x9F73, 0xFD79, 0x9F74, 0xFD7A, 0x9F75, 0xFD7B, 0x9F76, 0xFD7C, 0x9F77, 0xFD7D, 0x9F78, 0xFD7E, 0x9F79, 0xFD80, 0x9F7A, 0xFD81, + 0x9F7B, 0xFD82, 0x9F7C, 0xFD83, 0x9F7D, 0xFD84, 0x9F7E, 0xFD85, 0x9F7F, 0xB3DD, 0x9F80, 0xF6B3, 0x9F81, 0xFD86, 0x9F82, 0xFD87, + 0x9F83, 0xF6B4, 0x9F84, 0xC1E4, 0x9F85, 0xF6B5, 0x9F86, 0xF6B6, 0x9F87, 0xF6B7, 0x9F88, 0xF6B8, 0x9F89, 0xF6B9, 0x9F8A, 0xF6BA, + 0x9F8B, 0xC8A3, 0x9F8C, 0xF6BB, 0x9F8D, 0xFD88, 0x9F8E, 0xFD89, 0x9F8F, 0xFD8A, 0x9F90, 0xFD8B, 0x9F91, 0xFD8C, 0x9F92, 0xFD8D, + 0x9F93, 0xFD8E, 0x9F94, 0xFD8F, 0x9F95, 0xFD90, 0x9F96, 0xFD91, 0x9F97, 0xFD92, 0x9F98, 0xFD93, 0x9F99, 0xC1FA, 0x9F9A, 0xB9A8, + 0x9F9B, 0xEDE8, 0x9F9C, 0xFD94, 0x9F9D, 0xFD95, 0x9F9E, 0xFD96, 0x9F9F, 0xB9EA, 0x9FA0, 0xD9DF, 0x9FA1, 0xFD97, 0x9FA2, 0xFD98, + 0x9FA3, 0xFD99, 0x9FA4, 0xFD9A, 0x9FA5, 0xFD9B, 0xF92C, 0xFD9C, 0xF979, 0xFD9D, 0xF995, 0xFD9E, 0xF9E7, 0xFD9F, 0xF9F1, 0xFDA0, + 0xFA0C, 0xFE40, 0xFA0D, 0xFE41, 0xFA0E, 0xFE42, 0xFA0F, 0xFE43, 0xFA11, 0xFE44, 0xFA13, 0xFE45, 0xFA14, 0xFE46, 0xFA18, 0xFE47, + 0xFA1F, 0xFE48, 0xFA20, 0xFE49, 0xFA21, 0xFE4A, 0xFA23, 0xFE4B, 0xFA24, 0xFE4C, 0xFA27, 0xFE4D, 0xFA28, 0xFE4E, 0xFA29, 0xFE4F, + 0xFE30, 0xA955, 0xFE31, 0xA6F2, 0xFE33, 0xA6F4, 0xFE34, 0xA6F5, 0xFE35, 0xA6E0, 0xFE36, 0xA6E1, 0xFE37, 0xA6F0, 0xFE38, 0xA6F1, + 0xFE39, 0xA6E2, 0xFE3A, 0xA6E3, 0xFE3B, 0xA6EE, 0xFE3C, 0xA6EF, 0xFE3D, 0xA6E6, 0xFE3E, 0xA6E7, 0xFE3F, 0xA6E4, 0xFE40, 0xA6E5, + 0xFE41, 0xA6E8, 0xFE42, 0xA6E9, 0xFE43, 0xA6EA, 0xFE44, 0xA6EB, 0xFE49, 0xA968, 0xFE4A, 0xA969, 0xFE4B, 0xA96A, 0xFE4C, 0xA96B, + 0xFE4D, 0xA96C, 0xFE4E, 0xA96D, 0xFE4F, 0xA96E, 0xFE50, 0xA96F, 0xFE51, 0xA970, 0xFE52, 0xA971, 0xFE54, 0xA972, 0xFE55, 0xA973, + 0xFE56, 0xA974, 0xFE57, 0xA975, 0xFE59, 0xA976, 0xFE5A, 0xA977, 0xFE5B, 0xA978, 0xFE5C, 0xA979, 0xFE5D, 0xA97A, 0xFE5E, 0xA97B, + 0xFE5F, 0xA97C, 0xFE60, 0xA97D, 0xFE61, 0xA97E, 0xFE62, 0xA980, 0xFE63, 0xA981, 0xFE64, 0xA982, 0xFE65, 0xA983, 0xFE66, 0xA984, + 0xFE68, 0xA985, 0xFE69, 0xA986, 0xFE6A, 0xA987, 0xFE6B, 0xA988, 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA1E7, + 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, + 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, + 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, + 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, + 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, + 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, + 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA3DC, + 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, + 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, + 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, + 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, + 0xFF5D, 0xA3FD, 0xFF5E, 0xA1AB, 0xFFE0, 0xA1E9, 0xFFE1, 0xA1EA, 0xFFE2, 0xA956, 0xFFE3, 0xA3FE, 0xFFE4, 0xA957, 0xFFE5, 0xA3A4, + 0, 0 +}; + +static const WCHAR oem2uni936[] = { /* GBK --> Unicode pairs */ + 0x0080, 0x20AC, 0x8140, 0x4E02, 0x8141, 0x4E04, 0x8142, 0x4E05, 0x8143, 0x4E06, 0x8144, 0x4E0F, 0x8145, 0x4E12, 0x8146, 0x4E17, + 0x8147, 0x4E1F, 0x8148, 0x4E20, 0x8149, 0x4E21, 0x814A, 0x4E23, 0x814B, 0x4E26, 0x814C, 0x4E29, 0x814D, 0x4E2E, 0x814E, 0x4E2F, + 0x814F, 0x4E31, 0x8150, 0x4E33, 0x8151, 0x4E35, 0x8152, 0x4E37, 0x8153, 0x4E3C, 0x8154, 0x4E40, 0x8155, 0x4E41, 0x8156, 0x4E42, + 0x8157, 0x4E44, 0x8158, 0x4E46, 0x8159, 0x4E4A, 0x815A, 0x4E51, 0x815B, 0x4E55, 0x815C, 0x4E57, 0x815D, 0x4E5A, 0x815E, 0x4E5B, + 0x815F, 0x4E62, 0x8160, 0x4E63, 0x8161, 0x4E64, 0x8162, 0x4E65, 0x8163, 0x4E67, 0x8164, 0x4E68, 0x8165, 0x4E6A, 0x8166, 0x4E6B, + 0x8167, 0x4E6C, 0x8168, 0x4E6D, 0x8169, 0x4E6E, 0x816A, 0x4E6F, 0x816B, 0x4E72, 0x816C, 0x4E74, 0x816D, 0x4E75, 0x816E, 0x4E76, + 0x816F, 0x4E77, 0x8170, 0x4E78, 0x8171, 0x4E79, 0x8172, 0x4E7A, 0x8173, 0x4E7B, 0x8174, 0x4E7C, 0x8175, 0x4E7D, 0x8176, 0x4E7F, + 0x8177, 0x4E80, 0x8178, 0x4E81, 0x8179, 0x4E82, 0x817A, 0x4E83, 0x817B, 0x4E84, 0x817C, 0x4E85, 0x817D, 0x4E87, 0x817E, 0x4E8A, + 0x8180, 0x4E90, 0x8181, 0x4E96, 0x8182, 0x4E97, 0x8183, 0x4E99, 0x8184, 0x4E9C, 0x8185, 0x4E9D, 0x8186, 0x4E9E, 0x8187, 0x4EA3, + 0x8188, 0x4EAA, 0x8189, 0x4EAF, 0x818A, 0x4EB0, 0x818B, 0x4EB1, 0x818C, 0x4EB4, 0x818D, 0x4EB6, 0x818E, 0x4EB7, 0x818F, 0x4EB8, + 0x8190, 0x4EB9, 0x8191, 0x4EBC, 0x8192, 0x4EBD, 0x8193, 0x4EBE, 0x8194, 0x4EC8, 0x8195, 0x4ECC, 0x8196, 0x4ECF, 0x8197, 0x4ED0, + 0x8198, 0x4ED2, 0x8199, 0x4EDA, 0x819A, 0x4EDB, 0x819B, 0x4EDC, 0x819C, 0x4EE0, 0x819D, 0x4EE2, 0x819E, 0x4EE6, 0x819F, 0x4EE7, + 0x81A0, 0x4EE9, 0x81A1, 0x4EED, 0x81A2, 0x4EEE, 0x81A3, 0x4EEF, 0x81A4, 0x4EF1, 0x81A5, 0x4EF4, 0x81A6, 0x4EF8, 0x81A7, 0x4EF9, + 0x81A8, 0x4EFA, 0x81A9, 0x4EFC, 0x81AA, 0x4EFE, 0x81AB, 0x4F00, 0x81AC, 0x4F02, 0x81AD, 0x4F03, 0x81AE, 0x4F04, 0x81AF, 0x4F05, + 0x81B0, 0x4F06, 0x81B1, 0x4F07, 0x81B2, 0x4F08, 0x81B3, 0x4F0B, 0x81B4, 0x4F0C, 0x81B5, 0x4F12, 0x81B6, 0x4F13, 0x81B7, 0x4F14, + 0x81B8, 0x4F15, 0x81B9, 0x4F16, 0x81BA, 0x4F1C, 0x81BB, 0x4F1D, 0x81BC, 0x4F21, 0x81BD, 0x4F23, 0x81BE, 0x4F28, 0x81BF, 0x4F29, + 0x81C0, 0x4F2C, 0x81C1, 0x4F2D, 0x81C2, 0x4F2E, 0x81C3, 0x4F31, 0x81C4, 0x4F33, 0x81C5, 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0x9DB7, 0xFA55, 0x9DB8, 0xFA56, 0x9DB9, 0xFA57, 0x9DBA, + 0xFA58, 0x9DBB, 0xFA59, 0x9DBC, 0xFA5A, 0x9DBD, 0xFA5B, 0x9DBE, 0xFA5C, 0x9DBF, 0xFA5D, 0x9DC0, 0xFA5E, 0x9DC1, 0xFA5F, 0x9DC2, + 0xFA60, 0x9DC3, 0xFA61, 0x9DC4, 0xFA62, 0x9DC5, 0xFA63, 0x9DC6, 0xFA64, 0x9DC7, 0xFA65, 0x9DC8, 0xFA66, 0x9DC9, 0xFA67, 0x9DCA, + 0xFA68, 0x9DCB, 0xFA69, 0x9DCC, 0xFA6A, 0x9DCD, 0xFA6B, 0x9DCE, 0xFA6C, 0x9DCF, 0xFA6D, 0x9DD0, 0xFA6E, 0x9DD1, 0xFA6F, 0x9DD2, + 0xFA70, 0x9DD3, 0xFA71, 0x9DD4, 0xFA72, 0x9DD5, 0xFA73, 0x9DD6, 0xFA74, 0x9DD7, 0xFA75, 0x9DD8, 0xFA76, 0x9DD9, 0xFA77, 0x9DDA, + 0xFA78, 0x9DDB, 0xFA79, 0x9DDC, 0xFA7A, 0x9DDD, 0xFA7B, 0x9DDE, 0xFA7C, 0x9DDF, 0xFA7D, 0x9DE0, 0xFA7E, 0x9DE1, 0xFA80, 0x9DE2, + 0xFA81, 0x9DE3, 0xFA82, 0x9DE4, 0xFA83, 0x9DE5, 0xFA84, 0x9DE6, 0xFA85, 0x9DE7, 0xFA86, 0x9DE8, 0xFA87, 0x9DE9, 0xFA88, 0x9DEA, + 0xFA89, 0x9DEB, 0xFA8A, 0x9DEC, 0xFA8B, 0x9DED, 0xFA8C, 0x9DEE, 0xFA8D, 0x9DEF, 0xFA8E, 0x9DF0, 0xFA8F, 0x9DF1, 0xFA90, 0x9DF2, + 0xFA91, 0x9DF3, 0xFA92, 0x9DF4, 0xFA93, 0x9DF5, 0xFA94, 0x9DF6, 0xFA95, 0x9DF7, 0xFA96, 0x9DF8, 0xFA97, 0x9DF9, 0xFA98, 0x9DFA, + 0xFA99, 0x9DFB, 0xFA9A, 0x9DFC, 0xFA9B, 0x9DFD, 0xFA9C, 0x9DFE, 0xFA9D, 0x9DFF, 0xFA9E, 0x9E00, 0xFA9F, 0x9E01, 0xFAA0, 0x9E02, + 0xFB40, 0x9E03, 0xFB41, 0x9E04, 0xFB42, 0x9E05, 0xFB43, 0x9E06, 0xFB44, 0x9E07, 0xFB45, 0x9E08, 0xFB46, 0x9E09, 0xFB47, 0x9E0A, + 0xFB48, 0x9E0B, 0xFB49, 0x9E0C, 0xFB4A, 0x9E0D, 0xFB4B, 0x9E0E, 0xFB4C, 0x9E0F, 0xFB4D, 0x9E10, 0xFB4E, 0x9E11, 0xFB4F, 0x9E12, + 0xFB50, 0x9E13, 0xFB51, 0x9E14, 0xFB52, 0x9E15, 0xFB53, 0x9E16, 0xFB54, 0x9E17, 0xFB55, 0x9E18, 0xFB56, 0x9E19, 0xFB57, 0x9E1A, + 0xFB58, 0x9E1B, 0xFB59, 0x9E1C, 0xFB5A, 0x9E1D, 0xFB5B, 0x9E1E, 0xFB5C, 0x9E24, 0xFB5D, 0x9E27, 0xFB5E, 0x9E2E, 0xFB5F, 0x9E30, + 0xFB60, 0x9E34, 0xFB61, 0x9E3B, 0xFB62, 0x9E3C, 0xFB63, 0x9E40, 0xFB64, 0x9E4D, 0xFB65, 0x9E50, 0xFB66, 0x9E52, 0xFB67, 0x9E53, + 0xFB68, 0x9E54, 0xFB69, 0x9E56, 0xFB6A, 0x9E59, 0xFB6B, 0x9E5D, 0xFB6C, 0x9E5F, 0xFB6D, 0x9E60, 0xFB6E, 0x9E61, 0xFB6F, 0x9E62, + 0xFB70, 0x9E65, 0xFB71, 0x9E6E, 0xFB72, 0x9E6F, 0xFB73, 0x9E72, 0xFB74, 0x9E74, 0xFB75, 0x9E75, 0xFB76, 0x9E76, 0xFB77, 0x9E77, + 0xFB78, 0x9E78, 0xFB79, 0x9E79, 0xFB7A, 0x9E7A, 0xFB7B, 0x9E7B, 0xFB7C, 0x9E7C, 0xFB7D, 0x9E7D, 0xFB7E, 0x9E80, 0xFB80, 0x9E81, + 0xFB81, 0x9E83, 0xFB82, 0x9E84, 0xFB83, 0x9E85, 0xFB84, 0x9E86, 0xFB85, 0x9E89, 0xFB86, 0x9E8A, 0xFB87, 0x9E8C, 0xFB88, 0x9E8D, + 0xFB89, 0x9E8E, 0xFB8A, 0x9E8F, 0xFB8B, 0x9E90, 0xFB8C, 0x9E91, 0xFB8D, 0x9E94, 0xFB8E, 0x9E95, 0xFB8F, 0x9E96, 0xFB90, 0x9E97, + 0xFB91, 0x9E98, 0xFB92, 0x9E99, 0xFB93, 0x9E9A, 0xFB94, 0x9E9B, 0xFB95, 0x9E9C, 0xFB96, 0x9E9E, 0xFB97, 0x9EA0, 0xFB98, 0x9EA1, + 0xFB99, 0x9EA2, 0xFB9A, 0x9EA3, 0xFB9B, 0x9EA4, 0xFB9C, 0x9EA5, 0xFB9D, 0x9EA7, 0xFB9E, 0x9EA8, 0xFB9F, 0x9EA9, 0xFBA0, 0x9EAA, + 0xFC40, 0x9EAB, 0xFC41, 0x9EAC, 0xFC42, 0x9EAD, 0xFC43, 0x9EAE, 0xFC44, 0x9EAF, 0xFC45, 0x9EB0, 0xFC46, 0x9EB1, 0xFC47, 0x9EB2, + 0xFC48, 0x9EB3, 0xFC49, 0x9EB5, 0xFC4A, 0x9EB6, 0xFC4B, 0x9EB7, 0xFC4C, 0x9EB9, 0xFC4D, 0x9EBA, 0xFC4E, 0x9EBC, 0xFC4F, 0x9EBF, + 0xFC50, 0x9EC0, 0xFC51, 0x9EC1, 0xFC52, 0x9EC2, 0xFC53, 0x9EC3, 0xFC54, 0x9EC5, 0xFC55, 0x9EC6, 0xFC56, 0x9EC7, 0xFC57, 0x9EC8, + 0xFC58, 0x9ECA, 0xFC59, 0x9ECB, 0xFC5A, 0x9ECC, 0xFC5B, 0x9ED0, 0xFC5C, 0x9ED2, 0xFC5D, 0x9ED3, 0xFC5E, 0x9ED5, 0xFC5F, 0x9ED6, + 0xFC60, 0x9ED7, 0xFC61, 0x9ED9, 0xFC62, 0x9EDA, 0xFC63, 0x9EDE, 0xFC64, 0x9EE1, 0xFC65, 0x9EE3, 0xFC66, 0x9EE4, 0xFC67, 0x9EE6, + 0xFC68, 0x9EE8, 0xFC69, 0x9EEB, 0xFC6A, 0x9EEC, 0xFC6B, 0x9EED, 0xFC6C, 0x9EEE, 0xFC6D, 0x9EF0, 0xFC6E, 0x9EF1, 0xFC6F, 0x9EF2, + 0xFC70, 0x9EF3, 0xFC71, 0x9EF4, 0xFC72, 0x9EF5, 0xFC73, 0x9EF6, 0xFC74, 0x9EF7, 0xFC75, 0x9EF8, 0xFC76, 0x9EFA, 0xFC77, 0x9EFD, + 0xFC78, 0x9EFF, 0xFC79, 0x9F00, 0xFC7A, 0x9F01, 0xFC7B, 0x9F02, 0xFC7C, 0x9F03, 0xFC7D, 0x9F04, 0xFC7E, 0x9F05, 0xFC80, 0x9F06, + 0xFC81, 0x9F07, 0xFC82, 0x9F08, 0xFC83, 0x9F09, 0xFC84, 0x9F0A, 0xFC85, 0x9F0C, 0xFC86, 0x9F0F, 0xFC87, 0x9F11, 0xFC88, 0x9F12, + 0xFC89, 0x9F14, 0xFC8A, 0x9F15, 0xFC8B, 0x9F16, 0xFC8C, 0x9F18, 0xFC8D, 0x9F1A, 0xFC8E, 0x9F1B, 0xFC8F, 0x9F1C, 0xFC90, 0x9F1D, + 0xFC91, 0x9F1E, 0xFC92, 0x9F1F, 0xFC93, 0x9F21, 0xFC94, 0x9F23, 0xFC95, 0x9F24, 0xFC96, 0x9F25, 0xFC97, 0x9F26, 0xFC98, 0x9F27, + 0xFC99, 0x9F28, 0xFC9A, 0x9F29, 0xFC9B, 0x9F2A, 0xFC9C, 0x9F2B, 0xFC9D, 0x9F2D, 0xFC9E, 0x9F2E, 0xFC9F, 0x9F30, 0xFCA0, 0x9F31, + 0xFD40, 0x9F32, 0xFD41, 0x9F33, 0xFD42, 0x9F34, 0xFD43, 0x9F35, 0xFD44, 0x9F36, 0xFD45, 0x9F38, 0xFD46, 0x9F3A, 0xFD47, 0x9F3C, + 0xFD48, 0x9F3F, 0xFD49, 0x9F40, 0xFD4A, 0x9F41, 0xFD4B, 0x9F42, 0xFD4C, 0x9F43, 0xFD4D, 0x9F45, 0xFD4E, 0x9F46, 0xFD4F, 0x9F47, + 0xFD50, 0x9F48, 0xFD51, 0x9F49, 0xFD52, 0x9F4A, 0xFD53, 0x9F4B, 0xFD54, 0x9F4C, 0xFD55, 0x9F4D, 0xFD56, 0x9F4E, 0xFD57, 0x9F4F, + 0xFD58, 0x9F52, 0xFD59, 0x9F53, 0xFD5A, 0x9F54, 0xFD5B, 0x9F55, 0xFD5C, 0x9F56, 0xFD5D, 0x9F57, 0xFD5E, 0x9F58, 0xFD5F, 0x9F59, + 0xFD60, 0x9F5A, 0xFD61, 0x9F5B, 0xFD62, 0x9F5C, 0xFD63, 0x9F5D, 0xFD64, 0x9F5E, 0xFD65, 0x9F5F, 0xFD66, 0x9F60, 0xFD67, 0x9F61, + 0xFD68, 0x9F62, 0xFD69, 0x9F63, 0xFD6A, 0x9F64, 0xFD6B, 0x9F65, 0xFD6C, 0x9F66, 0xFD6D, 0x9F67, 0xFD6E, 0x9F68, 0xFD6F, 0x9F69, + 0xFD70, 0x9F6A, 0xFD71, 0x9F6B, 0xFD72, 0x9F6C, 0xFD73, 0x9F6D, 0xFD74, 0x9F6E, 0xFD75, 0x9F6F, 0xFD76, 0x9F70, 0xFD77, 0x9F71, + 0xFD78, 0x9F72, 0xFD79, 0x9F73, 0xFD7A, 0x9F74, 0xFD7B, 0x9F75, 0xFD7C, 0x9F76, 0xFD7D, 0x9F77, 0xFD7E, 0x9F78, 0xFD80, 0x9F79, + 0xFD81, 0x9F7A, 0xFD82, 0x9F7B, 0xFD83, 0x9F7C, 0xFD84, 0x9F7D, 0xFD85, 0x9F7E, 0xFD86, 0x9F81, 0xFD87, 0x9F82, 0xFD88, 0x9F8D, + 0xFD89, 0x9F8E, 0xFD8A, 0x9F8F, 0xFD8B, 0x9F90, 0xFD8C, 0x9F91, 0xFD8D, 0x9F92, 0xFD8E, 0x9F93, 0xFD8F, 0x9F94, 0xFD90, 0x9F95, + 0xFD91, 0x9F96, 0xFD92, 0x9F97, 0xFD93, 0x9F98, 0xFD94, 0x9F9C, 0xFD95, 0x9F9D, 0xFD96, 0x9F9E, 0xFD97, 0x9FA1, 0xFD98, 0x9FA2, + 0xFD99, 0x9FA3, 0xFD9A, 0x9FA4, 0xFD9B, 0x9FA5, 0xFD9C, 0xF92C, 0xFD9D, 0xF979, 0xFD9E, 0xF995, 0xFD9F, 0xF9E7, 0xFDA0, 0xF9F1, + 0xFE40, 0xFA0C, 0xFE41, 0xFA0D, 0xFE42, 0xFA0E, 0xFE43, 0xFA0F, 0xFE44, 0xFA11, 0xFE45, 0xFA13, 0xFE46, 0xFA14, 0xFE47, 0xFA18, + 0xFE48, 0xFA1F, 0xFE49, 0xFA20, 0xFE4A, 0xFA21, 0xFE4B, 0xFA23, 0xFE4C, 0xFA24, 0xFE4D, 0xFA27, 0xFE4E, 0xFA28, 0xFE4F, 0xFA29, + 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 949 || FF_CODE_PAGE == 0 /* Korean */ +static const WCHAR uni2oem949[] = { /* Unicode --> Korean pairs */ + 0x00A1, 0xA2AE, 0x00A4, 0xA2B4, 0x00A7, 0xA1D7, 0x00A8, 0xA1A7, 0x00AA, 0xA8A3, 0x00AD, 0xA1A9, 0x00AE, 0xA2E7, 0x00B0, 0xA1C6, + 0x00B1, 0xA1BE, 0x00B2, 0xA9F7, 0x00B3, 0xA9F8, 0x00B4, 0xA2A5, 0x00B6, 0xA2D2, 0x00B7, 0xA1A4, 0x00B8, 0xA2AC, 0x00B9, 0xA9F6, + 0x00BA, 0xA8AC, 0x00BC, 0xA8F9, 0x00BD, 0xA8F6, 0x00BE, 0xA8FA, 0x00BF, 0xA2AF, 0x00C6, 0xA8A1, 0x00D0, 0xA8A2, 0x00D7, 0xA1BF, + 0x00D8, 0xA8AA, 0x00DE, 0xA8AD, 0x00DF, 0xA9AC, 0x00E6, 0xA9A1, 0x00F0, 0xA9A3, 0x00F7, 0xA1C0, 0x00F8, 0xA9AA, 0x00FE, 0xA9AD, + 0x0111, 0xA9A2, 0x0126, 0xA8A4, 0x0127, 0xA9A4, 0x0131, 0xA9A5, 0x0132, 0xA8A6, 0x0133, 0xA9A6, 0x0138, 0xA9A7, 0x013F, 0xA8A8, + 0x0140, 0xA9A8, 0x0141, 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0xD6CA, 0xC459, 0xD6CB, 0xC45A, + 0xD6CC, 0xC8C7, 0xD6CD, 0xC461, 0xD6CE, 0xC462, 0xD6CF, 0xC463, 0xD6D0, 0xC464, 0xD6D1, 0xC8C8, 0xD6D2, 0xC465, 0xD6D3, 0xC466, + 0xD6D4, 0xC8C9, 0xD6D5, 0xC467, 0xD6D6, 0xC468, 0xD6D7, 0xC8CA, 0xD6D8, 0xC469, 0xD6D9, 0xC8CB, 0xD6DA, 0xC46A, 0xD6DB, 0xC46B, + 0xD6DC, 0xC46C, 0xD6DD, 0xC46D, 0xD6DE, 0xC46E, 0xD6DF, 0xC46F, 0xD6E0, 0xC8CC, 0xD6E1, 0xC470, 0xD6E2, 0xC471, 0xD6E3, 0xC472, + 0xD6E4, 0xC8CD, 0xD6E5, 0xC473, 0xD6E6, 0xC474, 0xD6E7, 0xC475, 0xD6E8, 0xC8CE, 0xD6E9, 0xC476, 0xD6EA, 0xC477, 0xD6EB, 0xC478, + 0xD6EC, 0xC479, 0xD6ED, 0xC47A, 0xD6EE, 0xC481, 0xD6EF, 0xC482, 0xD6F0, 0xC8CF, 0xD6F1, 0xC483, 0xD6F2, 0xC484, 0xD6F3, 0xC485, + 0xD6F4, 0xC486, 0xD6F5, 0xC8D0, 0xD6F6, 0xC487, 0xD6F7, 0xC488, 0xD6F8, 0xC489, 0xD6F9, 0xC48A, 0xD6FA, 0xC48B, 0xD6FB, 0xC48C, + 0xD6FC, 0xC8D1, 0xD6FD, 0xC8D2, 0xD6FE, 0xC48D, 0xD6FF, 0xC48E, 0xD700, 0xC8D3, 0xD701, 0xC48F, 0xD702, 0xC490, 0xD703, 0xC491, + 0xD704, 0xC8D4, 0xD705, 0xC492, 0xD706, 0xC493, 0xD707, 0xC494, 0xD708, 0xC495, 0xD709, 0xC496, 0xD70A, 0xC497, 0xD70B, 0xC498, + 0xD70C, 0xC499, 0xD70D, 0xC49A, 0xD70E, 0xC49B, 0xD70F, 0xC49C, 0xD710, 0xC49D, 0xD711, 0xC8D5, 0xD712, 0xC49E, 0xD713, 0xC49F, + 0xD714, 0xC4A0, 0xD715, 0xC541, 0xD716, 0xC542, 0xD717, 0xC543, 0xD718, 0xC8D6, 0xD719, 0xC8D7, 0xD71A, 0xC544, 0xD71B, 0xC545, + 0xD71C, 0xC8D8, 0xD71D, 0xC546, 0xD71E, 0xC547, 0xD71F, 0xC548, 0xD720, 0xC8D9, 0xD721, 0xC549, 0xD722, 0xC54A, 0xD723, 0xC54B, + 0xD724, 0xC54C, 0xD725, 0xC54D, 0xD726, 0xC54E, 0xD727, 0xC54F, 0xD728, 0xC8DA, 0xD729, 0xC8DB, 0xD72A, 0xC550, 0xD72B, 0xC8DC, + 0xD72C, 0xC551, 0xD72D, 0xC8DD, 0xD72E, 0xC552, 0xD72F, 0xC553, 0xD730, 0xC554, 0xD731, 0xC555, 0xD732, 0xC556, 0xD733, 0xC557, + 0xD734, 0xC8DE, 0xD735, 0xC8DF, 0xD736, 0xC558, 0xD737, 0xC559, 0xD738, 0xC8E0, 0xD739, 0xC55A, 0xD73A, 0xC561, 0xD73B, 0xC562, + 0xD73C, 0xC8E1, 0xD73D, 0xC563, 0xD73E, 0xC564, 0xD73F, 0xC565, 0xD740, 0xC566, 0xD741, 0xC567, 0xD742, 0xC568, 0xD743, 0xC569, + 0xD744, 0xC8E2, 0xD745, 0xC56A, 0xD746, 0xC56B, 0xD747, 0xC8E3, 0xD748, 0xC56C, 0xD749, 0xC8E4, 0xD74A, 0xC56D, 0xD74B, 0xC56E, + 0xD74C, 0xC56F, 0xD74D, 0xC570, 0xD74E, 0xC571, 0xD74F, 0xC572, 0xD750, 0xC8E5, 0xD751, 0xC8E6, 0xD752, 0xC573, 0xD753, 0xC574, + 0xD754, 0xC8E7, 0xD755, 0xC575, 0xD756, 0xC8E8, 0xD757, 0xC8E9, 0xD758, 0xC8EA, 0xD759, 0xC8EB, 0xD75A, 0xC576, 0xD75B, 0xC577, + 0xD75C, 0xC578, 0xD75D, 0xC579, 0xD75E, 0xC57A, 0xD75F, 0xC581, 0xD760, 0xC8EC, 0xD761, 0xC8ED, 0xD762, 0xC582, 0xD763, 0xC8EE, + 0xD764, 0xC583, 0xD765, 0xC8EF, 0xD766, 0xC584, 0xD767, 0xC585, 0xD768, 0xC586, 0xD769, 0xC8F0, 0xD76A, 0xC587, 0xD76B, 0xC588, + 0xD76C, 0xC8F1, 0xD76D, 0xC589, 0xD76E, 0xC58A, 0xD76F, 0xC58B, 0xD770, 0xC8F2, 0xD771, 0xC58C, 0xD772, 0xC58D, 0xD773, 0xC58E, + 0xD774, 0xC8F3, 0xD775, 0xC58F, 0xD776, 0xC590, 0xD777, 0xC591, 0xD778, 0xC592, 0xD779, 0xC593, 0xD77A, 0xC594, 0xD77B, 0xC595, + 0xD77C, 0xC8F4, 0xD77D, 0xC8F5, 0xD77E, 0xC596, 0xD77F, 0xC597, 0xD780, 0xC598, 0xD781, 0xC8F6, 0xD782, 0xC599, 0xD783, 0xC59A, + 0xD784, 0xC59B, 0xD785, 0xC59C, 0xD786, 0xC59D, 0xD787, 0xC59E, 0xD788, 0xC8F7, 0xD789, 0xC8F8, 0xD78A, 0xC59F, 0xD78B, 0xC5A0, + 0xD78C, 0xC8F9, 0xD78D, 0xC641, 0xD78E, 0xC642, 0xD78F, 0xC643, 0xD790, 0xC8FA, 0xD791, 0xC644, 0xD792, 0xC645, 0xD793, 0xC646, + 0xD794, 0xC647, 0xD795, 0xC648, 0xD796, 0xC649, 0xD797, 0xC64A, 0xD798, 0xC8FB, 0xD799, 0xC8FC, 0xD79A, 0xC64B, 0xD79B, 0xC8FD, + 0xD79C, 0xC64C, 0xD79D, 0xC8FE, 0xD79E, 0xC64D, 0xD79F, 0xC64E, 0xD7A0, 0xC64F, 0xD7A1, 0xC650, 0xD7A2, 0xC651, 0xD7A3, 0xC652, + 0xF900, 0xCBD0, 0xF901, 0xCBD6, 0xF902, 0xCBE7, 0xF903, 0xCDCF, 0xF904, 0xCDE8, 0xF905, 0xCEAD, 0xF906, 0xCFFB, 0xF907, 0xD0A2, + 0xF908, 0xD0B8, 0xF909, 0xD0D0, 0xF90A, 0xD0DD, 0xF90B, 0xD1D4, 0xF90C, 0xD1D5, 0xF90D, 0xD1D8, 0xF90E, 0xD1DB, 0xF90F, 0xD1DC, + 0xF910, 0xD1DD, 0xF911, 0xD1DE, 0xF912, 0xD1DF, 0xF913, 0xD1E0, 0xF914, 0xD1E2, 0xF915, 0xD1E3, 0xF916, 0xD1E4, 0xF917, 0xD1E5, + 0xF918, 0xD1E6, 0xF919, 0xD1E8, 0xF91A, 0xD1E9, 0xF91B, 0xD1EA, 0xF91C, 0xD1EB, 0xF91D, 0xD1ED, 0xF91E, 0xD1EF, 0xF91F, 0xD1F0, + 0xF920, 0xD1F2, 0xF921, 0xD1F6, 0xF922, 0xD1FA, 0xF923, 0xD1FC, 0xF924, 0xD1FD, 0xF925, 0xD1FE, 0xF926, 0xD2A2, 0xF927, 0xD2A3, + 0xF928, 0xD2A7, 0xF929, 0xD2A8, 0xF92A, 0xD2A9, 0xF92B, 0xD2AA, 0xF92C, 0xD2AB, 0xF92D, 0xD2AD, 0xF92E, 0xD2B2, 0xF92F, 0xD2BE, + 0xF930, 0xD2C2, 0xF931, 0xD2C3, 0xF932, 0xD2C4, 0xF933, 0xD2C6, 0xF934, 0xD2C7, 0xF935, 0xD2C8, 0xF936, 0xD2C9, 0xF937, 0xD2CA, + 0xF938, 0xD2CB, 0xF939, 0xD2CD, 0xF93A, 0xD2CE, 0xF93B, 0xD2CF, 0xF93C, 0xD2D0, 0xF93D, 0xD2D1, 0xF93E, 0xD2D2, 0xF93F, 0xD2D3, + 0xF940, 0xD2D4, 0xF941, 0xD2D5, 0xF942, 0xD2D6, 0xF943, 0xD2D7, 0xF944, 0xD2D9, 0xF945, 0xD2DA, 0xF946, 0xD2DE, 0xF947, 0xD2DF, + 0xF948, 0xD2E1, 0xF949, 0xD2E2, 0xF94A, 0xD2E4, 0xF94B, 0xD2E5, 0xF94C, 0xD2E6, 0xF94D, 0xD2E7, 0xF94E, 0xD2E8, 0xF94F, 0xD2E9, + 0xF950, 0xD2EA, 0xF951, 0xD2EB, 0xF952, 0xD2F0, 0xF953, 0xD2F1, 0xF954, 0xD2F2, 0xF955, 0xD2F3, 0xF956, 0xD2F4, 0xF957, 0xD2F5, + 0xF958, 0xD2F7, 0xF959, 0xD2F8, 0xF95A, 0xD4E6, 0xF95B, 0xD4FC, 0xF95C, 0xD5A5, 0xF95D, 0xD5AB, 0xF95E, 0xD5AE, 0xF95F, 0xD6B8, + 0xF960, 0xD6CD, 0xF961, 0xD7CB, 0xF962, 0xD7E4, 0xF963, 0xDBC5, 0xF964, 0xDBE4, 0xF965, 0xDCA5, 0xF966, 0xDDA5, 0xF967, 0xDDD5, + 0xF968, 0xDDF4, 0xF969, 0xDEFC, 0xF96A, 0xDEFE, 0xF96B, 0xDFB3, 0xF96C, 0xDFE1, 0xF96D, 0xDFE8, 0xF96E, 0xE0F1, 0xF96F, 0xE1AD, + 0xF970, 0xE1ED, 0xF971, 0xE3F5, 0xF972, 0xE4A1, 0xF973, 0xE4A9, 0xF974, 0xE5AE, 0xF975, 0xE5B1, 0xF976, 0xE5B2, 0xF977, 0xE5B9, + 0xF978, 0xE5BB, 0xF979, 0xE5BC, 0xF97A, 0xE5C4, 0xF97B, 0xE5CE, 0xF97C, 0xE5D0, 0xF97D, 0xE5D2, 0xF97E, 0xE5D6, 0xF97F, 0xE5FA, + 0xF980, 0xE5FB, 0xF981, 0xE5FC, 0xF982, 0xE5FE, 0xF983, 0xE6A1, 0xF984, 0xE6A4, 0xF985, 0xE6A7, 0xF986, 0xE6AD, 0xF987, 0xE6AF, + 0xF988, 0xE6B0, 0xF989, 0xE6B1, 0xF98A, 0xE6B3, 0xF98B, 0xE6B7, 0xF98C, 0xE6B8, 0xF98D, 0xE6BC, 0xF98E, 0xE6C4, 0xF98F, 0xE6C6, + 0xF990, 0xE6C7, 0xF991, 0xE6CA, 0xF992, 0xE6D2, 0xF993, 0xE6D6, 0xF994, 0xE6D9, 0xF995, 0xE6DC, 0xF996, 0xE6DF, 0xF997, 0xE6E1, + 0xF998, 0xE6E4, 0xF999, 0xE6E5, 0xF99A, 0xE6E6, 0xF99B, 0xE6E8, 0xF99C, 0xE6EA, 0xF99D, 0xE6EB, 0xF99E, 0xE6EC, 0xF99F, 0xE6EF, + 0xF9A0, 0xE6F1, 0xF9A1, 0xE6F2, 0xF9A2, 0xE6F5, 0xF9A3, 0xE6F6, 0xF9A4, 0xE6F7, 0xF9A5, 0xE6F9, 0xF9A6, 0xE7A1, 0xF9A7, 0xE7A6, + 0xF9A8, 0xE7A9, 0xF9A9, 0xE7AA, 0xF9AA, 0xE7AC, 0xF9AB, 0xE7AD, 0xF9AC, 0xE7B0, 0xF9AD, 0xE7BF, 0xF9AE, 0xE7C1, 0xF9AF, 0xE7C6, + 0xF9B0, 0xE7C7, 0xF9B1, 0xE7CB, 0xF9B2, 0xE7CD, 0xF9B3, 0xE7CF, 0xF9B4, 0xE7D0, 0xF9B5, 0xE7D3, 0xF9B6, 0xE7DF, 0xF9B7, 0xE7E4, + 0xF9B8, 0xE7E6, 0xF9B9, 0xE7F7, 0xF9BA, 0xE8E7, 0xF9BB, 0xE8E8, 0xF9BC, 0xE8F0, 0xF9BD, 0xE8F1, 0xF9BE, 0xE8F7, 0xF9BF, 0xE8F9, + 0xF9C0, 0xE8FB, 0xF9C1, 0xE8FE, 0xF9C2, 0xE9A7, 0xF9C3, 0xE9AC, 0xF9C4, 0xE9CC, 0xF9C5, 0xE9F7, 0xF9C6, 0xEAC1, 0xF9C7, 0xEAE5, + 0xF9C8, 0xEAF4, 0xF9C9, 0xEAF7, 0xF9CA, 0xEAFC, 0xF9CB, 0xEAFE, 0xF9CC, 0xEBA4, 0xF9CD, 0xEBA7, 0xF9CE, 0xEBA9, 0xF9CF, 0xEBAA, + 0xF9D0, 0xEBBA, 0xF9D1, 0xEBBB, 0xF9D2, 0xEBBD, 0xF9D3, 0xEBC1, 0xF9D4, 0xEBC2, 0xF9D5, 0xEBC6, 0xF9D6, 0xEBC7, 0xF9D7, 0xEBCC, + 0xF9D8, 0xEBCF, 0xF9D9, 0xEBD0, 0xF9DA, 0xEBD1, 0xF9DB, 0xEBD2, 0xF9DC, 0xEBD8, 0xF9DD, 0xECA6, 0xF9DE, 0xECA7, 0xF9DF, 0xECAA, + 0xF9E0, 0xECAF, 0xF9E1, 0xECB0, 0xF9E2, 0xECB1, 0xF9E3, 0xECB2, 0xF9E4, 0xECB5, 0xF9E5, 0xECB8, 0xF9E6, 0xECBA, 0xF9E7, 0xECC0, + 0xF9E8, 0xECC1, 0xF9E9, 0xECC5, 0xF9EA, 0xECC6, 0xF9EB, 0xECC9, 0xF9EC, 0xECCA, 0xF9ED, 0xECD5, 0xF9EE, 0xECDD, 0xF9EF, 0xECDE, + 0xF9F0, 0xECE1, 0xF9F1, 0xECE4, 0xF9F2, 0xECE7, 0xF9F3, 0xECE8, 0xF9F4, 0xECF7, 0xF9F5, 0xECF8, 0xF9F6, 0xECFA, 0xF9F7, 0xEDA1, + 0xF9F8, 0xEDA2, 0xF9F9, 0xEDA3, 0xF9FA, 0xEDEE, 0xF9FB, 0xEEDB, 0xF9FC, 0xF2BD, 0xF9FD, 0xF2FA, 0xF9FE, 0xF3B1, 0xF9FF, 0xF4A7, + 0xFA00, 0xF4EE, 0xFA01, 0xF6F4, 0xFA02, 0xF6F6, 0xFA03, 0xF7B8, 0xFA04, 0xF7C8, 0xFA05, 0xF7D3, 0xFA06, 0xF8DB, 0xFA07, 0xF8F0, + 0xFA08, 0xFAA1, 0xFA09, 0xFAA2, 0xFA0A, 0xFAE6, 0xFA0B, 0xFCA9, 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA3A4, + 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, + 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, + 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, + 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, + 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, + 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, + 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA1AC, + 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, + 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, + 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, + 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, + 0xFF5D, 0xA3FD, 0xFF5E, 0xA2A6, 0xFFE0, 0xA1CB, 0xFFE1, 0xA1CC, 0xFFE2, 0xA1FE, 0xFFE3, 0xA3FE, 0xFFE5, 0xA1CD, 0xFFE6, 0xA3DC, + 0, 0 +}; + +static const WCHAR oem2uni949[] = { /* Korean --> Unicode pairs */ + 0x8141, 0xAC02, 0x8142, 0xAC03, 0x8143, 0xAC05, 0x8144, 0xAC06, 0x8145, 0xAC0B, 0x8146, 0xAC0C, 0x8147, 0xAC0D, 0x8148, 0xAC0E, + 0x8149, 0xAC0F, 0x814A, 0xAC18, 0x814B, 0xAC1E, 0x814C, 0xAC1F, 0x814D, 0xAC21, 0x814E, 0xAC22, 0x814F, 0xAC23, 0x8150, 0xAC25, + 0x8151, 0xAC26, 0x8152, 0xAC27, 0x8153, 0xAC28, 0x8154, 0xAC29, 0x8155, 0xAC2A, 0x8156, 0xAC2B, 0x8157, 0xAC2E, 0x8158, 0xAC32, + 0x8159, 0xAC33, 0x815A, 0xAC34, 0x8161, 0xAC35, 0x8162, 0xAC36, 0x8163, 0xAC37, 0x8164, 0xAC3A, 0x8165, 0xAC3B, 0x8166, 0xAC3D, + 0x8167, 0xAC3E, 0x8168, 0xAC3F, 0x8169, 0xAC41, 0x816A, 0xAC42, 0x816B, 0xAC43, 0x816C, 0xAC44, 0x816D, 0xAC45, 0x816E, 0xAC46, + 0x816F, 0xAC47, 0x8170, 0xAC48, 0x8171, 0xAC49, 0x8172, 0xAC4A, 0x8173, 0xAC4C, 0x8174, 0xAC4E, 0x8175, 0xAC4F, 0x8176, 0xAC50, + 0x8177, 0xAC51, 0x8178, 0xAC52, 0x8179, 0xAC53, 0x817A, 0xAC55, 0x8181, 0xAC56, 0x8182, 0xAC57, 0x8183, 0xAC59, 0x8184, 0xAC5A, + 0x8185, 0xAC5B, 0x8186, 0xAC5D, 0x8187, 0xAC5E, 0x8188, 0xAC5F, 0x8189, 0xAC60, 0x818A, 0xAC61, 0x818B, 0xAC62, 0x818C, 0xAC63, + 0x818D, 0xAC64, 0x818E, 0xAC65, 0x818F, 0xAC66, 0x8190, 0xAC67, 0x8191, 0xAC68, 0x8192, 0xAC69, 0x8193, 0xAC6A, 0x8194, 0xAC6B, + 0x8195, 0xAC6C, 0x8196, 0xAC6D, 0x8197, 0xAC6E, 0x8198, 0xAC6F, 0x8199, 0xAC72, 0x819A, 0xAC73, 0x819B, 0xAC75, 0x819C, 0xAC76, + 0x819D, 0xAC79, 0x819E, 0xAC7B, 0x819F, 0xAC7C, 0x81A0, 0xAC7D, 0x81A1, 0xAC7E, 0x81A2, 0xAC7F, 0x81A3, 0xAC82, 0x81A4, 0xAC87, + 0x81A5, 0xAC88, 0x81A6, 0xAC8D, 0x81A7, 0xAC8E, 0x81A8, 0xAC8F, 0x81A9, 0xAC91, 0x81AA, 0xAC92, 0x81AB, 0xAC93, 0x81AC, 0xAC95, + 0x81AD, 0xAC96, 0x81AE, 0xAC97, 0x81AF, 0xAC98, 0x81B0, 0xAC99, 0x81B1, 0xAC9A, 0x81B2, 0xAC9B, 0x81B3, 0xAC9E, 0x81B4, 0xACA2, + 0x81B5, 0xACA3, 0x81B6, 0xACA4, 0x81B7, 0xACA5, 0x81B8, 0xACA6, 0x81B9, 0xACA7, 0x81BA, 0xACAB, 0x81BB, 0xACAD, 0x81BC, 0xACAE, + 0x81BD, 0xACB1, 0x81BE, 0xACB2, 0x81BF, 0xACB3, 0x81C0, 0xACB4, 0x81C1, 0xACB5, 0x81C2, 0xACB6, 0x81C3, 0xACB7, 0x81C4, 0xACBA, + 0x81C5, 0xACBE, 0x81C6, 0xACBF, 0x81C7, 0xACC0, 0x81C8, 0xACC2, 0x81C9, 0xACC3, 0x81CA, 0xACC5, 0x81CB, 0xACC6, 0x81CC, 0xACC7, + 0x81CD, 0xACC9, 0x81CE, 0xACCA, 0x81CF, 0xACCB, 0x81D0, 0xACCD, 0x81D1, 0xACCE, 0x81D2, 0xACCF, 0x81D3, 0xACD0, 0x81D4, 0xACD1, + 0x81D5, 0xACD2, 0x81D6, 0xACD3, 0x81D7, 0xACD4, 0x81D8, 0xACD6, 0x81D9, 0xACD8, 0x81DA, 0xACD9, 0x81DB, 0xACDA, 0x81DC, 0xACDB, + 0x81DD, 0xACDC, 0x81DE, 0xACDD, 0x81DF, 0xACDE, 0x81E0, 0xACDF, 0x81E1, 0xACE2, 0x81E2, 0xACE3, 0x81E3, 0xACE5, 0x81E4, 0xACE6, + 0x81E5, 0xACE9, 0x81E6, 0xACEB, 0x81E7, 0xACED, 0x81E8, 0xACEE, 0x81E9, 0xACF2, 0x81EA, 0xACF4, 0x81EB, 0xACF7, 0x81EC, 0xACF8, + 0x81ED, 0xACF9, 0x81EE, 0xACFA, 0x81EF, 0xACFB, 0x81F0, 0xACFE, 0x81F1, 0xACFF, 0x81F2, 0xAD01, 0x81F3, 0xAD02, 0x81F4, 0xAD03, + 0x81F5, 0xAD05, 0x81F6, 0xAD07, 0x81F7, 0xAD08, 0x81F8, 0xAD09, 0x81F9, 0xAD0A, 0x81FA, 0xAD0B, 0x81FB, 0xAD0E, 0x81FC, 0xAD10, + 0x81FD, 0xAD12, 0x81FE, 0xAD13, 0x8241, 0xAD14, 0x8242, 0xAD15, 0x8243, 0xAD16, 0x8244, 0xAD17, 0x8245, 0xAD19, 0x8246, 0xAD1A, + 0x8247, 0xAD1B, 0x8248, 0xAD1D, 0x8249, 0xAD1E, 0x824A, 0xAD1F, 0x824B, 0xAD21, 0x824C, 0xAD22, 0x824D, 0xAD23, 0x824E, 0xAD24, + 0x824F, 0xAD25, 0x8250, 0xAD26, 0x8251, 0xAD27, 0x8252, 0xAD28, 0x8253, 0xAD2A, 0x8254, 0xAD2B, 0x8255, 0xAD2E, 0x8256, 0xAD2F, + 0x8257, 0xAD30, 0x8258, 0xAD31, 0x8259, 0xAD32, 0x825A, 0xAD33, 0x8261, 0xAD36, 0x8262, 0xAD37, 0x8263, 0xAD39, 0x8264, 0xAD3A, + 0x8265, 0xAD3B, 0x8266, 0xAD3D, 0x8267, 0xAD3E, 0x8268, 0xAD3F, 0x8269, 0xAD40, 0x826A, 0xAD41, 0x826B, 0xAD42, 0x826C, 0xAD43, + 0x826D, 0xAD46, 0x826E, 0xAD48, 0x826F, 0xAD4A, 0x8270, 0xAD4B, 0x8271, 0xAD4C, 0x8272, 0xAD4D, 0x8273, 0xAD4E, 0x8274, 0xAD4F, + 0x8275, 0xAD51, 0x8276, 0xAD52, 0x8277, 0xAD53, 0x8278, 0xAD55, 0x8279, 0xAD56, 0x827A, 0xAD57, 0x8281, 0xAD59, 0x8282, 0xAD5A, + 0x8283, 0xAD5B, 0x8284, 0xAD5C, 0x8285, 0xAD5D, 0x8286, 0xAD5E, 0x8287, 0xAD5F, 0x8288, 0xAD60, 0x8289, 0xAD62, 0x828A, 0xAD64, + 0x828B, 0xAD65, 0x828C, 0xAD66, 0x828D, 0xAD67, 0x828E, 0xAD68, 0x828F, 0xAD69, 0x8290, 0xAD6A, 0x8291, 0xAD6B, 0x8292, 0xAD6E, + 0x8293, 0xAD6F, 0x8294, 0xAD71, 0x8295, 0xAD72, 0x8296, 0xAD77, 0x8297, 0xAD78, 0x8298, 0xAD79, 0x8299, 0xAD7A, 0x829A, 0xAD7E, + 0x829B, 0xAD80, 0x829C, 0xAD83, 0x829D, 0xAD84, 0x829E, 0xAD85, 0x829F, 0xAD86, 0x82A0, 0xAD87, 0x82A1, 0xAD8A, 0x82A2, 0xAD8B, + 0x82A3, 0xAD8D, 0x82A4, 0xAD8E, 0x82A5, 0xAD8F, 0x82A6, 0xAD91, 0x82A7, 0xAD92, 0x82A8, 0xAD93, 0x82A9, 0xAD94, 0x82AA, 0xAD95, + 0x82AB, 0xAD96, 0x82AC, 0xAD97, 0x82AD, 0xAD98, 0x82AE, 0xAD99, 0x82AF, 0xAD9A, 0x82B0, 0xAD9B, 0x82B1, 0xAD9E, 0x82B2, 0xAD9F, + 0x82B3, 0xADA0, 0x82B4, 0xADA1, 0x82B5, 0xADA2, 0x82B6, 0xADA3, 0x82B7, 0xADA5, 0x82B8, 0xADA6, 0x82B9, 0xADA7, 0x82BA, 0xADA8, + 0x82BB, 0xADA9, 0x82BC, 0xADAA, 0x82BD, 0xADAB, 0x82BE, 0xADAC, 0x82BF, 0xADAD, 0x82C0, 0xADAE, 0x82C1, 0xADAF, 0x82C2, 0xADB0, + 0x82C3, 0xADB1, 0x82C4, 0xADB2, 0x82C5, 0xADB3, 0x82C6, 0xADB4, 0x82C7, 0xADB5, 0x82C8, 0xADB6, 0x82C9, 0xADB8, 0x82CA, 0xADB9, + 0x82CB, 0xADBA, 0x82CC, 0xADBB, 0x82CD, 0xADBC, 0x82CE, 0xADBD, 0x82CF, 0xADBE, 0x82D0, 0xADBF, 0x82D1, 0xADC2, 0x82D2, 0xADC3, + 0x82D3, 0xADC5, 0x82D4, 0xADC6, 0x82D5, 0xADC7, 0x82D6, 0xADC9, 0x82D7, 0xADCA, 0x82D8, 0xADCB, 0x82D9, 0xADCC, 0x82DA, 0xADCD, + 0x82DB, 0xADCE, 0x82DC, 0xADCF, 0x82DD, 0xADD2, 0x82DE, 0xADD4, 0x82DF, 0xADD5, 0x82E0, 0xADD6, 0x82E1, 0xADD7, 0x82E2, 0xADD8, + 0x82E3, 0xADD9, 0x82E4, 0xADDA, 0x82E5, 0xADDB, 0x82E6, 0xADDD, 0x82E7, 0xADDE, 0x82E8, 0xADDF, 0x82E9, 0xADE1, 0x82EA, 0xADE2, + 0x82EB, 0xADE3, 0x82EC, 0xADE5, 0x82ED, 0xADE6, 0x82EE, 0xADE7, 0x82EF, 0xADE8, 0x82F0, 0xADE9, 0x82F1, 0xADEA, 0x82F2, 0xADEB, + 0x82F3, 0xADEC, 0x82F4, 0xADED, 0x82F5, 0xADEE, 0x82F6, 0xADEF, 0x82F7, 0xADF0, 0x82F8, 0xADF1, 0x82F9, 0xADF2, 0x82FA, 0xADF3, + 0x82FB, 0xADF4, 0x82FC, 0xADF5, 0x82FD, 0xADF6, 0x82FE, 0xADF7, 0x8341, 0xADFA, 0x8342, 0xADFB, 0x8343, 0xADFD, 0x8344, 0xADFE, + 0x8345, 0xAE02, 0x8346, 0xAE03, 0x8347, 0xAE04, 0x8348, 0xAE05, 0x8349, 0xAE06, 0x834A, 0xAE07, 0x834B, 0xAE0A, 0x834C, 0xAE0C, + 0x834D, 0xAE0E, 0x834E, 0xAE0F, 0x834F, 0xAE10, 0x8350, 0xAE11, 0x8351, 0xAE12, 0x8352, 0xAE13, 0x8353, 0xAE15, 0x8354, 0xAE16, + 0x8355, 0xAE17, 0x8356, 0xAE18, 0x8357, 0xAE19, 0x8358, 0xAE1A, 0x8359, 0xAE1B, 0x835A, 0xAE1C, 0x8361, 0xAE1D, 0x8362, 0xAE1E, + 0x8363, 0xAE1F, 0x8364, 0xAE20, 0x8365, 0xAE21, 0x8366, 0xAE22, 0x8367, 0xAE23, 0x8368, 0xAE24, 0x8369, 0xAE25, 0x836A, 0xAE26, + 0x836B, 0xAE27, 0x836C, 0xAE28, 0x836D, 0xAE29, 0x836E, 0xAE2A, 0x836F, 0xAE2B, 0x8370, 0xAE2C, 0x8371, 0xAE2D, 0x8372, 0xAE2E, + 0x8373, 0xAE2F, 0x8374, 0xAE32, 0x8375, 0xAE33, 0x8376, 0xAE35, 0x8377, 0xAE36, 0x8378, 0xAE39, 0x8379, 0xAE3B, 0x837A, 0xAE3C, + 0x8381, 0xAE3D, 0x8382, 0xAE3E, 0x8383, 0xAE3F, 0x8384, 0xAE42, 0x8385, 0xAE44, 0x8386, 0xAE47, 0x8387, 0xAE48, 0x8388, 0xAE49, + 0x8389, 0xAE4B, 0x838A, 0xAE4F, 0x838B, 0xAE51, 0x838C, 0xAE52, 0x838D, 0xAE53, 0x838E, 0xAE55, 0x838F, 0xAE57, 0x8390, 0xAE58, + 0x8391, 0xAE59, 0x8392, 0xAE5A, 0x8393, 0xAE5B, 0x8394, 0xAE5E, 0x8395, 0xAE62, 0x8396, 0xAE63, 0x8397, 0xAE64, 0x8398, 0xAE66, + 0x8399, 0xAE67, 0x839A, 0xAE6A, 0x839B, 0xAE6B, 0x839C, 0xAE6D, 0x839D, 0xAE6E, 0x839E, 0xAE6F, 0x839F, 0xAE71, 0x83A0, 0xAE72, + 0x83A1, 0xAE73, 0x83A2, 0xAE74, 0x83A3, 0xAE75, 0x83A4, 0xAE76, 0x83A5, 0xAE77, 0x83A6, 0xAE7A, 0x83A7, 0xAE7E, 0x83A8, 0xAE7F, + 0x83A9, 0xAE80, 0x83AA, 0xAE81, 0x83AB, 0xAE82, 0x83AC, 0xAE83, 0x83AD, 0xAE86, 0x83AE, 0xAE87, 0x83AF, 0xAE88, 0x83B0, 0xAE89, + 0x83B1, 0xAE8A, 0x83B2, 0xAE8B, 0x83B3, 0xAE8D, 0x83B4, 0xAE8E, 0x83B5, 0xAE8F, 0x83B6, 0xAE90, 0x83B7, 0xAE91, 0x83B8, 0xAE92, + 0x83B9, 0xAE93, 0x83BA, 0xAE94, 0x83BB, 0xAE95, 0x83BC, 0xAE96, 0x83BD, 0xAE97, 0x83BE, 0xAE98, 0x83BF, 0xAE99, 0x83C0, 0xAE9A, + 0x83C1, 0xAE9B, 0x83C2, 0xAE9C, 0x83C3, 0xAE9D, 0x83C4, 0xAE9E, 0x83C5, 0xAE9F, 0x83C6, 0xAEA0, 0x83C7, 0xAEA1, 0x83C8, 0xAEA2, + 0x83C9, 0xAEA3, 0x83CA, 0xAEA4, 0x83CB, 0xAEA5, 0x83CC, 0xAEA6, 0x83CD, 0xAEA7, 0x83CE, 0xAEA8, 0x83CF, 0xAEA9, 0x83D0, 0xAEAA, + 0x83D1, 0xAEAB, 0x83D2, 0xAEAC, 0x83D3, 0xAEAD, 0x83D4, 0xAEAE, 0x83D5, 0xAEAF, 0x83D6, 0xAEB0, 0x83D7, 0xAEB1, 0x83D8, 0xAEB2, + 0x83D9, 0xAEB3, 0x83DA, 0xAEB4, 0x83DB, 0xAEB5, 0x83DC, 0xAEB6, 0x83DD, 0xAEB7, 0x83DE, 0xAEB8, 0x83DF, 0xAEB9, 0x83E0, 0xAEBA, + 0x83E1, 0xAEBB, 0x83E2, 0xAEBF, 0x83E3, 0xAEC1, 0x83E4, 0xAEC2, 0x83E5, 0xAEC3, 0x83E6, 0xAEC5, 0x83E7, 0xAEC6, 0x83E8, 0xAEC7, + 0x83E9, 0xAEC8, 0x83EA, 0xAEC9, 0x83EB, 0xAECA, 0x83EC, 0xAECB, 0x83ED, 0xAECE, 0x83EE, 0xAED2, 0x83EF, 0xAED3, 0x83F0, 0xAED4, + 0x83F1, 0xAED5, 0x83F2, 0xAED6, 0x83F3, 0xAED7, 0x83F4, 0xAEDA, 0x83F5, 0xAEDB, 0x83F6, 0xAEDD, 0x83F7, 0xAEDE, 0x83F8, 0xAEDF, + 0x83F9, 0xAEE0, 0x83FA, 0xAEE1, 0x83FB, 0xAEE2, 0x83FC, 0xAEE3, 0x83FD, 0xAEE4, 0x83FE, 0xAEE5, 0x8441, 0xAEE6, 0x8442, 0xAEE7, + 0x8443, 0xAEE9, 0x8444, 0xAEEA, 0x8445, 0xAEEC, 0x8446, 0xAEEE, 0x8447, 0xAEEF, 0x8448, 0xAEF0, 0x8449, 0xAEF1, 0x844A, 0xAEF2, + 0x844B, 0xAEF3, 0x844C, 0xAEF5, 0x844D, 0xAEF6, 0x844E, 0xAEF7, 0x844F, 0xAEF9, 0x8450, 0xAEFA, 0x8451, 0xAEFB, 0x8452, 0xAEFD, + 0x8453, 0xAEFE, 0x8454, 0xAEFF, 0x8455, 0xAF00, 0x8456, 0xAF01, 0x8457, 0xAF02, 0x8458, 0xAF03, 0x8459, 0xAF04, 0x845A, 0xAF05, + 0x8461, 0xAF06, 0x8462, 0xAF09, 0x8463, 0xAF0A, 0x8464, 0xAF0B, 0x8465, 0xAF0C, 0x8466, 0xAF0E, 0x8467, 0xAF0F, 0x8468, 0xAF11, + 0x8469, 0xAF12, 0x846A, 0xAF13, 0x846B, 0xAF14, 0x846C, 0xAF15, 0x846D, 0xAF16, 0x846E, 0xAF17, 0x846F, 0xAF18, 0x8470, 0xAF19, + 0x8471, 0xAF1A, 0x8472, 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0xB4B2, 0xB220, 0xB4B3, 0xB234, 0xB4B4, 0xB23C, + 0xB4B5, 0xB258, 0xB4B6, 0xB25C, 0xB4B7, 0xB260, 0xB4B8, 0xB268, 0xB4B9, 0xB269, 0xB4BA, 0xB274, 0xB4BB, 0xB275, 0xB4BC, 0xB27C, + 0xB4BD, 0xB284, 0xB4BE, 0xB285, 0xB4BF, 0xB289, 0xB4C0, 0xB290, 0xB4C1, 0xB291, 0xB4C2, 0xB294, 0xB4C3, 0xB298, 0xB4C4, 0xB299, + 0xB4C5, 0xB29A, 0xB4C6, 0xB2A0, 0xB4C7, 0xB2A1, 0xB4C8, 0xB2A3, 0xB4C9, 0xB2A5, 0xB4CA, 0xB2A6, 0xB4CB, 0xB2AA, 0xB4CC, 0xB2AC, + 0xB4CD, 0xB2B0, 0xB4CE, 0xB2B4, 0xB4CF, 0xB2C8, 0xB4D0, 0xB2C9, 0xB4D1, 0xB2CC, 0xB4D2, 0xB2D0, 0xB4D3, 0xB2D2, 0xB4D4, 0xB2D8, + 0xB4D5, 0xB2D9, 0xB4D6, 0xB2DB, 0xB4D7, 0xB2DD, 0xB4D8, 0xB2E2, 0xB4D9, 0xB2E4, 0xB4DA, 0xB2E5, 0xB4DB, 0xB2E6, 0xB4DC, 0xB2E8, + 0xB4DD, 0xB2EB, 0xB4DE, 0xB2EC, 0xB4DF, 0xB2ED, 0xB4E0, 0xB2EE, 0xB4E1, 0xB2EF, 0xB4E2, 0xB2F3, 0xB4E3, 0xB2F4, 0xB4E4, 0xB2F5, + 0xB4E5, 0xB2F7, 0xB4E6, 0xB2F8, 0xB4E7, 0xB2F9, 0xB4E8, 0xB2FA, 0xB4E9, 0xB2FB, 0xB4EA, 0xB2FF, 0xB4EB, 0xB300, 0xB4EC, 0xB301, + 0xB4ED, 0xB304, 0xB4EE, 0xB308, 0xB4EF, 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0xF8B7, 0x6241, 0xF8B8, 0x7247, 0xF8B9, 0x7BC7, 0xF8BA, 0x7DE8, 0xF8BB, 0x7FE9, 0xF8BC, 0x904D, + 0xF8BD, 0x97AD, 0xF8BE, 0x9A19, 0xF8BF, 0x8CB6, 0xF8C0, 0x576A, 0xF8C1, 0x5E73, 0xF8C2, 0x67B0, 0xF8C3, 0x840D, 0xF8C4, 0x8A55, + 0xF8C5, 0x5420, 0xF8C6, 0x5B16, 0xF8C7, 0x5E63, 0xF8C8, 0x5EE2, 0xF8C9, 0x5F0A, 0xF8CA, 0x6583, 0xF8CB, 0x80BA, 0xF8CC, 0x853D, + 0xF8CD, 0x9589, 0xF8CE, 0x965B, 0xF8CF, 0x4F48, 0xF8D0, 0x5305, 0xF8D1, 0x530D, 0xF8D2, 0x530F, 0xF8D3, 0x5486, 0xF8D4, 0x54FA, + 0xF8D5, 0x5703, 0xF8D6, 0x5E03, 0xF8D7, 0x6016, 0xF8D8, 0x629B, 0xF8D9, 0x62B1, 0xF8DA, 0x6355, 0xF8DB, 0xFA06, 0xF8DC, 0x6CE1, + 0xF8DD, 0x6D66, 0xF8DE, 0x75B1, 0xF8DF, 0x7832, 0xF8E0, 0x80DE, 0xF8E1, 0x812F, 0xF8E2, 0x82DE, 0xF8E3, 0x8461, 0xF8E4, 0x84B2, + 0xF8E5, 0x888D, 0xF8E6, 0x8912, 0xF8E7, 0x900B, 0xF8E8, 0x92EA, 0xF8E9, 0x98FD, 0xF8EA, 0x9B91, 0xF8EB, 0x5E45, 0xF8EC, 0x66B4, + 0xF8ED, 0x66DD, 0xF8EE, 0x7011, 0xF8EF, 0x7206, 0xF8F0, 0xFA07, 0xF8F1, 0x4FF5, 0xF8F2, 0x527D, 0xF8F3, 0x5F6A, 0xF8F4, 0x6153, + 0xF8F5, 0x6753, 0xF8F6, 0x6A19, 0xF8F7, 0x6F02, 0xF8F8, 0x74E2, 0xF8F9, 0x7968, 0xF8FA, 0x8868, 0xF8FB, 0x8C79, 0xF8FC, 0x98C7, + 0xF8FD, 0x98C4, 0xF8FE, 0x9A43, 0xF9A1, 0x54C1, 0xF9A2, 0x7A1F, 0xF9A3, 0x6953, 0xF9A4, 0x8AF7, 0xF9A5, 0x8C4A, 0xF9A6, 0x98A8, + 0xF9A7, 0x99AE, 0xF9A8, 0x5F7C, 0xF9A9, 0x62AB, 0xF9AA, 0x75B2, 0xF9AB, 0x76AE, 0xF9AC, 0x88AB, 0xF9AD, 0x907F, 0xF9AE, 0x9642, + 0xF9AF, 0x5339, 0xF9B0, 0x5F3C, 0xF9B1, 0x5FC5, 0xF9B2, 0x6CCC, 0xF9B3, 0x73CC, 0xF9B4, 0x7562, 0xF9B5, 0x758B, 0xF9B6, 0x7B46, + 0xF9B7, 0x82FE, 0xF9B8, 0x999D, 0xF9B9, 0x4E4F, 0xF9BA, 0x903C, 0xF9BB, 0x4E0B, 0xF9BC, 0x4F55, 0xF9BD, 0x53A6, 0xF9BE, 0x590F, + 0xF9BF, 0x5EC8, 0xF9C0, 0x6630, 0xF9C1, 0x6CB3, 0xF9C2, 0x7455, 0xF9C3, 0x8377, 0xF9C4, 0x8766, 0xF9C5, 0x8CC0, 0xF9C6, 0x9050, + 0xF9C7, 0x971E, 0xF9C8, 0x9C15, 0xF9C9, 0x58D1, 0xF9CA, 0x5B78, 0xF9CB, 0x8650, 0xF9CC, 0x8B14, 0xF9CD, 0x9DB4, 0xF9CE, 0x5BD2, + 0xF9CF, 0x6068, 0xF9D0, 0x608D, 0xF9D1, 0x65F1, 0xF9D2, 0x6C57, 0xF9D3, 0x6F22, 0xF9D4, 0x6FA3, 0xF9D5, 0x701A, 0xF9D6, 0x7F55, + 0xF9D7, 0x7FF0, 0xF9D8, 0x9591, 0xF9D9, 0x9592, 0xF9DA, 0x9650, 0xF9DB, 0x97D3, 0xF9DC, 0x5272, 0xF9DD, 0x8F44, 0xF9DE, 0x51FD, + 0xF9DF, 0x542B, 0xF9E0, 0x54B8, 0xF9E1, 0x5563, 0xF9E2, 0x558A, 0xF9E3, 0x6ABB, 0xF9E4, 0x6DB5, 0xF9E5, 0x7DD8, 0xF9E6, 0x8266, + 0xF9E7, 0x929C, 0xF9E8, 0x9677, 0xF9E9, 0x9E79, 0xF9EA, 0x5408, 0xF9EB, 0x54C8, 0xF9EC, 0x76D2, 0xF9ED, 0x86E4, 0xF9EE, 0x95A4, + 0xF9EF, 0x95D4, 0xF9F0, 0x965C, 0xF9F1, 0x4EA2, 0xF9F2, 0x4F09, 0xF9F3, 0x59EE, 0xF9F4, 0x5AE6, 0xF9F5, 0x5DF7, 0xF9F6, 0x6052, + 0xF9F7, 0x6297, 0xF9F8, 0x676D, 0xF9F9, 0x6841, 0xF9FA, 0x6C86, 0xF9FB, 0x6E2F, 0xF9FC, 0x7F38, 0xF9FD, 0x809B, 0xF9FE, 0x822A, + 0xFAA1, 0xFA08, 0xFAA2, 0xFA09, 0xFAA3, 0x9805, 0xFAA4, 0x4EA5, 0xFAA5, 0x5055, 0xFAA6, 0x54B3, 0xFAA7, 0x5793, 0xFAA8, 0x595A, + 0xFAA9, 0x5B69, 0xFAAA, 0x5BB3, 0xFAAB, 0x61C8, 0xFAAC, 0x6977, 0xFAAD, 0x6D77, 0xFAAE, 0x7023, 0xFAAF, 0x87F9, 0xFAB0, 0x89E3, + 0xFAB1, 0x8A72, 0xFAB2, 0x8AE7, 0xFAB3, 0x9082, 0xFAB4, 0x99ED, 0xFAB5, 0x9AB8, 0xFAB6, 0x52BE, 0xFAB7, 0x6838, 0xFAB8, 0x5016, + 0xFAB9, 0x5E78, 0xFABA, 0x674F, 0xFABB, 0x8347, 0xFABC, 0x884C, 0xFABD, 0x4EAB, 0xFABE, 0x5411, 0xFABF, 0x56AE, 0xFAC0, 0x73E6, + 0xFAC1, 0x9115, 0xFAC2, 0x97FF, 0xFAC3, 0x9909, 0xFAC4, 0x9957, 0xFAC5, 0x9999, 0xFAC6, 0x5653, 0xFAC7, 0x589F, 0xFAC8, 0x865B, + 0xFAC9, 0x8A31, 0xFACA, 0x61B2, 0xFACB, 0x6AF6, 0xFACC, 0x737B, 0xFACD, 0x8ED2, 0xFACE, 0x6B47, 0xFACF, 0x96AA, 0xFAD0, 0x9A57, + 0xFAD1, 0x5955, 0xFAD2, 0x7200, 0xFAD3, 0x8D6B, 0xFAD4, 0x9769, 0xFAD5, 0x4FD4, 0xFAD6, 0x5CF4, 0xFAD7, 0x5F26, 0xFAD8, 0x61F8, + 0xFAD9, 0x665B, 0xFADA, 0x6CEB, 0xFADB, 0x70AB, 0xFADC, 0x7384, 0xFADD, 0x73B9, 0xFADE, 0x73FE, 0xFADF, 0x7729, 0xFAE0, 0x774D, + 0xFAE1, 0x7D43, 0xFAE2, 0x7D62, 0xFAE3, 0x7E23, 0xFAE4, 0x8237, 0xFAE5, 0x8852, 0xFAE6, 0xFA0A, 0xFAE7, 0x8CE2, 0xFAE8, 0x9249, + 0xFAE9, 0x986F, 0xFAEA, 0x5B51, 0xFAEB, 0x7A74, 0xFAEC, 0x8840, 0xFAED, 0x9801, 0xFAEE, 0x5ACC, 0xFAEF, 0x4FE0, 0xFAF0, 0x5354, + 0xFAF1, 0x593E, 0xFAF2, 0x5CFD, 0xFAF3, 0x633E, 0xFAF4, 0x6D79, 0xFAF5, 0x72F9, 0xFAF6, 0x8105, 0xFAF7, 0x8107, 0xFAF8, 0x83A2, + 0xFAF9, 0x92CF, 0xFAFA, 0x9830, 0xFAFB, 0x4EA8, 0xFAFC, 0x5144, 0xFAFD, 0x5211, 0xFAFE, 0x578B, 0xFBA1, 0x5F62, 0xFBA2, 0x6CC2, + 0xFBA3, 0x6ECE, 0xFBA4, 0x7005, 0xFBA5, 0x7050, 0xFBA6, 0x70AF, 0xFBA7, 0x7192, 0xFBA8, 0x73E9, 0xFBA9, 0x7469, 0xFBAA, 0x834A, + 0xFBAB, 0x87A2, 0xFBAC, 0x8861, 0xFBAD, 0x9008, 0xFBAE, 0x90A2, 0xFBAF, 0x93A3, 0xFBB0, 0x99A8, 0xFBB1, 0x516E, 0xFBB2, 0x5F57, + 0xFBB3, 0x60E0, 0xFBB4, 0x6167, 0xFBB5, 0x66B3, 0xFBB6, 0x8559, 0xFBB7, 0x8E4A, 0xFBB8, 0x91AF, 0xFBB9, 0x978B, 0xFBBA, 0x4E4E, + 0xFBBB, 0x4E92, 0xFBBC, 0x547C, 0xFBBD, 0x58D5, 0xFBBE, 0x58FA, 0xFBBF, 0x597D, 0xFBC0, 0x5CB5, 0xFBC1, 0x5F27, 0xFBC2, 0x6236, + 0xFBC3, 0x6248, 0xFBC4, 0x660A, 0xFBC5, 0x6667, 0xFBC6, 0x6BEB, 0xFBC7, 0x6D69, 0xFBC8, 0x6DCF, 0xFBC9, 0x6E56, 0xFBCA, 0x6EF8, + 0xFBCB, 0x6F94, 0xFBCC, 0x6FE0, 0xFBCD, 0x6FE9, 0xFBCE, 0x705D, 0xFBCF, 0x72D0, 0xFBD0, 0x7425, 0xFBD1, 0x745A, 0xFBD2, 0x74E0, + 0xFBD3, 0x7693, 0xFBD4, 0x795C, 0xFBD5, 0x7CCA, 0xFBD6, 0x7E1E, 0xFBD7, 0x80E1, 0xFBD8, 0x82A6, 0xFBD9, 0x846B, 0xFBDA, 0x84BF, + 0xFBDB, 0x864E, 0xFBDC, 0x865F, 0xFBDD, 0x8774, 0xFBDE, 0x8B77, 0xFBDF, 0x8C6A, 0xFBE0, 0x93AC, 0xFBE1, 0x9800, 0xFBE2, 0x9865, + 0xFBE3, 0x60D1, 0xFBE4, 0x6216, 0xFBE5, 0x9177, 0xFBE6, 0x5A5A, 0xFBE7, 0x660F, 0xFBE8, 0x6DF7, 0xFBE9, 0x6E3E, 0xFBEA, 0x743F, + 0xFBEB, 0x9B42, 0xFBEC, 0x5FFD, 0xFBED, 0x60DA, 0xFBEE, 0x7B0F, 0xFBEF, 0x54C4, 0xFBF0, 0x5F18, 0xFBF1, 0x6C5E, 0xFBF2, 0x6CD3, + 0xFBF3, 0x6D2A, 0xFBF4, 0x70D8, 0xFBF5, 0x7D05, 0xFBF6, 0x8679, 0xFBF7, 0x8A0C, 0xFBF8, 0x9D3B, 0xFBF9, 0x5316, 0xFBFA, 0x548C, + 0xFBFB, 0x5B05, 0xFBFC, 0x6A3A, 0xFBFD, 0x706B, 0xFBFE, 0x7575, 0xFCA1, 0x798D, 0xFCA2, 0x79BE, 0xFCA3, 0x82B1, 0xFCA4, 0x83EF, + 0xFCA5, 0x8A71, 0xFCA6, 0x8B41, 0xFCA7, 0x8CA8, 0xFCA8, 0x9774, 0xFCA9, 0xFA0B, 0xFCAA, 0x64F4, 0xFCAB, 0x652B, 0xFCAC, 0x78BA, + 0xFCAD, 0x78BB, 0xFCAE, 0x7A6B, 0xFCAF, 0x4E38, 0xFCB0, 0x559A, 0xFCB1, 0x5950, 0xFCB2, 0x5BA6, 0xFCB3, 0x5E7B, 0xFCB4, 0x60A3, + 0xFCB5, 0x63DB, 0xFCB6, 0x6B61, 0xFCB7, 0x6665, 0xFCB8, 0x6853, 0xFCB9, 0x6E19, 0xFCBA, 0x7165, 0xFCBB, 0x74B0, 0xFCBC, 0x7D08, + 0xFCBD, 0x9084, 0xFCBE, 0x9A69, 0xFCBF, 0x9C25, 0xFCC0, 0x6D3B, 0xFCC1, 0x6ED1, 0xFCC2, 0x733E, 0xFCC3, 0x8C41, 0xFCC4, 0x95CA, + 0xFCC5, 0x51F0, 0xFCC6, 0x5E4C, 0xFCC7, 0x5FA8, 0xFCC8, 0x604D, 0xFCC9, 0x60F6, 0xFCCA, 0x6130, 0xFCCB, 0x614C, 0xFCCC, 0x6643, + 0xFCCD, 0x6644, 0xFCCE, 0x69A5, 0xFCCF, 0x6CC1, 0xFCD0, 0x6E5F, 0xFCD1, 0x6EC9, 0xFCD2, 0x6F62, 0xFCD3, 0x714C, 0xFCD4, 0x749C, + 0xFCD5, 0x7687, 0xFCD6, 0x7BC1, 0xFCD7, 0x7C27, 0xFCD8, 0x8352, 0xFCD9, 0x8757, 0xFCDA, 0x9051, 0xFCDB, 0x968D, 0xFCDC, 0x9EC3, + 0xFCDD, 0x532F, 0xFCDE, 0x56DE, 0xFCDF, 0x5EFB, 0xFCE0, 0x5F8A, 0xFCE1, 0x6062, 0xFCE2, 0x6094, 0xFCE3, 0x61F7, 0xFCE4, 0x6666, + 0xFCE5, 0x6703, 0xFCE6, 0x6A9C, 0xFCE7, 0x6DEE, 0xFCE8, 0x6FAE, 0xFCE9, 0x7070, 0xFCEA, 0x736A, 0xFCEB, 0x7E6A, 0xFCEC, 0x81BE, + 0xFCED, 0x8334, 0xFCEE, 0x86D4, 0xFCEF, 0x8AA8, 0xFCF0, 0x8CC4, 0xFCF1, 0x5283, 0xFCF2, 0x7372, 0xFCF3, 0x5B96, 0xFCF4, 0x6A6B, + 0xFCF5, 0x9404, 0xFCF6, 0x54EE, 0xFCF7, 0x5686, 0xFCF8, 0x5B5D, 0xFCF9, 0x6548, 0xFCFA, 0x6585, 0xFCFB, 0x66C9, 0xFCFC, 0x689F, + 0xFCFD, 0x6D8D, 0xFCFE, 0x6DC6, 0xFDA1, 0x723B, 0xFDA2, 0x80B4, 0xFDA3, 0x9175, 0xFDA4, 0x9A4D, 0xFDA5, 0x4FAF, 0xFDA6, 0x5019, + 0xFDA7, 0x539A, 0xFDA8, 0x540E, 0xFDA9, 0x543C, 0xFDAA, 0x5589, 0xFDAB, 0x55C5, 0xFDAC, 0x5E3F, 0xFDAD, 0x5F8C, 0xFDAE, 0x673D, + 0xFDAF, 0x7166, 0xFDB0, 0x73DD, 0xFDB1, 0x9005, 0xFDB2, 0x52DB, 0xFDB3, 0x52F3, 0xFDB4, 0x5864, 0xFDB5, 0x58CE, 0xFDB6, 0x7104, + 0xFDB7, 0x718F, 0xFDB8, 0x71FB, 0xFDB9, 0x85B0, 0xFDBA, 0x8A13, 0xFDBB, 0x6688, 0xFDBC, 0x85A8, 0xFDBD, 0x55A7, 0xFDBE, 0x6684, + 0xFDBF, 0x714A, 0xFDC0, 0x8431, 0xFDC1, 0x5349, 0xFDC2, 0x5599, 0xFDC3, 0x6BC1, 0xFDC4, 0x5F59, 0xFDC5, 0x5FBD, 0xFDC6, 0x63EE, + 0xFDC7, 0x6689, 0xFDC8, 0x7147, 0xFDC9, 0x8AF1, 0xFDCA, 0x8F1D, 0xFDCB, 0x9EBE, 0xFDCC, 0x4F11, 0xFDCD, 0x643A, 0xFDCE, 0x70CB, + 0xFDCF, 0x7566, 0xFDD0, 0x8667, 0xFDD1, 0x6064, 0xFDD2, 0x8B4E, 0xFDD3, 0x9DF8, 0xFDD4, 0x5147, 0xFDD5, 0x51F6, 0xFDD6, 0x5308, + 0xFDD7, 0x6D36, 0xFDD8, 0x80F8, 0xFDD9, 0x9ED1, 0xFDDA, 0x6615, 0xFDDB, 0x6B23, 0xFDDC, 0x7098, 0xFDDD, 0x75D5, 0xFDDE, 0x5403, + 0xFDDF, 0x5C79, 0xFDE0, 0x7D07, 0xFDE1, 0x8A16, 0xFDE2, 0x6B20, 0xFDE3, 0x6B3D, 0xFDE4, 0x6B46, 0xFDE5, 0x5438, 0xFDE6, 0x6070, + 0xFDE7, 0x6D3D, 0xFDE8, 0x7FD5, 0xFDE9, 0x8208, 0xFDEA, 0x50D6, 0xFDEB, 0x51DE, 0xFDEC, 0x559C, 0xFDED, 0x566B, 0xFDEE, 0x56CD, + 0xFDEF, 0x59EC, 0xFDF0, 0x5B09, 0xFDF1, 0x5E0C, 0xFDF2, 0x6199, 0xFDF3, 0x6198, 0xFDF4, 0x6231, 0xFDF5, 0x665E, 0xFDF6, 0x66E6, + 0xFDF7, 0x7199, 0xFDF8, 0x71B9, 0xFDF9, 0x71BA, 0xFDFA, 0x72A7, 0xFDFB, 0x79A7, 0xFDFC, 0x7A00, 0xFDFD, 0x7FB2, 0xFDFE, 0x8A70, + 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 950 || FF_CODE_PAGE == 0 /* Traditional Chinese */ +static const WCHAR uni2oem950[] = { /* Unicode --> Big5 pairs */ + 0x00A7, 0xA1B1, 0x00AF, 0xA1C2, 0x00B0, 0xA258, 0x00B1, 0xA1D3, 0x00B7, 0xA150, 0x00D7, 0xA1D1, 0x00F7, 0xA1D2, 0x02C7, 0xA3BE, + 0x02C9, 0xA3BC, 0x02CA, 0xA3BD, 0x02CB, 0xA3BF, 0x02CD, 0xA1C5, 0x02D9, 0xA3BB, 0x0391, 0xA344, 0x0392, 0xA345, 0x0393, 0xA346, + 0x0394, 0xA347, 0x0395, 0xA348, 0x0396, 0xA349, 0x0397, 0xA34A, 0x0398, 0xA34B, 0x0399, 0xA34C, 0x039A, 0xA34D, 0x039B, 0xA34E, + 0x039C, 0xA34F, 0x039D, 0xA350, 0x039E, 0xA351, 0x039F, 0xA352, 0x03A0, 0xA353, 0x03A1, 0xA354, 0x03A3, 0xA355, 0x03A4, 0xA356, + 0x03A5, 0xA357, 0x03A6, 0xA358, 0x03A7, 0xA359, 0x03A8, 0xA35A, 0x03A9, 0xA35B, 0x03B1, 0xA35C, 0x03B2, 0xA35D, 0x03B3, 0xA35E, + 0x03B4, 0xA35F, 0x03B5, 0xA360, 0x03B6, 0xA361, 0x03B7, 0xA362, 0x03B8, 0xA363, 0x03B9, 0xA364, 0x03BA, 0xA365, 0x03BB, 0xA366, + 0x03BC, 0xA367, 0x03BD, 0xA368, 0x03BE, 0xA369, 0x03BF, 0xA36A, 0x03C0, 0xA36B, 0x03C1, 0xA36C, 0x03C3, 0xA36D, 0x03C4, 0xA36E, + 0x03C5, 0xA36F, 0x03C6, 0xA370, 0x03C7, 0xA371, 0x03C8, 0xA372, 0x03C9, 0xA373, 0x2013, 0xA156, 0x2014, 0xA158, 0x2018, 0xA1A5, + 0x2019, 0xA1A6, 0x201C, 0xA1A7, 0x201D, 0xA1A8, 0x2025, 0xA14C, 0x2026, 0xA14B, 0x2027, 0xA145, 0x2032, 0xA1AC, 0x2035, 0xA1AB, + 0x203B, 0xA1B0, 0x20AC, 0xA3E1, 0x2103, 0xA24A, 0x2105, 0xA1C1, 0x2109, 0xA24B, 0x2160, 0xA2B9, 0x2161, 0xA2BA, 0x2162, 0xA2BB, + 0x2163, 0xA2BC, 0x2164, 0xA2BD, 0x2165, 0xA2BE, 0x2166, 0xA2BF, 0x2167, 0xA2C0, 0x2168, 0xA2C1, 0x2169, 0xA2C2, 0x2190, 0xA1F6, + 0x2191, 0xA1F4, 0x2192, 0xA1F7, 0x2193, 0xA1F5, 0x2196, 0xA1F8, 0x2197, 0xA1F9, 0x2198, 0xA1FB, 0x2199, 0xA1FA, 0x2215, 0xA241, + 0x221A, 0xA1D4, 0x221E, 0xA1DB, 0x221F, 0xA1E8, 0x2220, 0xA1E7, 0x2223, 0xA1FD, 0x2225, 0xA1FC, 0x2229, 0xA1E4, 0x222A, 0xA1E5, + 0x222B, 0xA1EC, 0x222E, 0xA1ED, 0x2234, 0xA1EF, 0x2235, 0xA1EE, 0x2252, 0xA1DC, 0x2260, 0xA1DA, 0x2261, 0xA1DD, 0x2266, 0xA1D8, + 0x2267, 0xA1D9, 0x2295, 0xA1F2, 0x2299, 0xA1F3, 0x22A5, 0xA1E6, 0x22BF, 0xA1E9, 0x2500, 0xA277, 0x2502, 0xA278, 0x250C, 0xA27A, + 0x2510, 0xA27B, 0x2514, 0xA27C, 0x2518, 0xA27D, 0x251C, 0xA275, 0x2524, 0xA274, 0x252C, 0xA273, 0x2534, 0xA272, 0x253C, 0xA271, + 0x2550, 0xA2A4, 0x2550, 0xF9F9, 0x2551, 0xF9F8, 0x2552, 0xF9E6, 0x2553, 0xF9EF, 0x2554, 0xF9DD, 0x2555, 0xF9E8, 0x2556, 0xF9F1, + 0x2557, 0xF9DF, 0x2558, 0xF9EC, 0x2559, 0xF9F5, 0x255A, 0xF9E3, 0x255B, 0xF9EE, 0x255C, 0xF9F7, 0x255D, 0xF9E5, 0x255E, 0xA2A5, + 0x255E, 0xF9E9, 0x255F, 0xF9F2, 0x2560, 0xF9E0, 0x2561, 0xA2A7, 0x2561, 0xF9EB, 0x2562, 0xF9F4, 0x2563, 0xF9E2, 0x2564, 0xF9E7, + 0x2565, 0xF9F0, 0x2566, 0xF9DE, 0x2567, 0xF9ED, 0x2568, 0xF9F6, 0x2569, 0xF9E4, 0x256A, 0xA2A6, 0x256A, 0xF9EA, 0x256B, 0xF9F3, + 0x256C, 0xF9E1, 0x256D, 0xA27E, 0x256D, 0xF9FA, 0x256E, 0xA2A1, 0x256E, 0xF9FB, 0x256F, 0xA2A3, 0x256F, 0xF9FD, 0x2570, 0xA2A2, + 0x2570, 0xF9FC, 0x2571, 0xA2AC, 0x2572, 0xA2AD, 0x2573, 0xA2AE, 0x2574, 0xA15A, 0x2581, 0xA262, 0x2582, 0xA263, 0x2583, 0xA264, + 0x2584, 0xA265, 0x2585, 0xA266, 0x2586, 0xA267, 0x2587, 0xA268, 0x2588, 0xA269, 0x2589, 0xA270, 0x258A, 0xA26F, 0x258B, 0xA26E, + 0x258C, 0xA26D, 0x258D, 0xA26C, 0x258E, 0xA26B, 0x258F, 0xA26A, 0x2593, 0xF9FE, 0x2594, 0xA276, 0x2595, 0xA279, 0x25A0, 0xA1BD, + 0x25A1, 0xA1BC, 0x25B2, 0xA1B6, 0x25B3, 0xA1B5, 0x25BC, 0xA1BF, 0x25BD, 0xA1BE, 0x25C6, 0xA1BB, 0x25C7, 0xA1BA, 0x25CB, 0xA1B3, + 0x25CE, 0xA1B7, 0x25CF, 0xA1B4, 0x25E2, 0xA2A8, 0x25E3, 0xA2A9, 0x25E4, 0xA2AB, 0x25E5, 0xA2AA, 0x2605, 0xA1B9, 0x2606, 0xA1B8, + 0x2640, 0xA1F0, 0x2642, 0xA1F1, 0x3000, 0xA140, 0x3001, 0xA142, 0x3002, 0xA143, 0x3003, 0xA1B2, 0x3008, 0xA171, 0x3009, 0xA172, + 0x300A, 0xA16D, 0x300B, 0xA16E, 0x300C, 0xA175, 0x300D, 0xA176, 0x300E, 0xA179, 0x300F, 0xA17A, 0x3010, 0xA169, 0x3011, 0xA16A, + 0x3012, 0xA245, 0x3014, 0xA165, 0x3015, 0xA166, 0x301D, 0xA1A9, 0x301E, 0xA1AA, 0x3021, 0xA2C3, 0x3022, 0xA2C4, 0x3023, 0xA2C5, + 0x3024, 0xA2C6, 0x3025, 0xA2C7, 0x3026, 0xA2C8, 0x3027, 0xA2C9, 0x3028, 0xA2CA, 0x3029, 0xA2CB, 0x3105, 0xA374, 0x3106, 0xA375, + 0x3107, 0xA376, 0x3108, 0xA377, 0x3109, 0xA378, 0x310A, 0xA379, 0x310B, 0xA37A, 0x310C, 0xA37B, 0x310D, 0xA37C, 0x310E, 0xA37D, + 0x310F, 0xA37E, 0x3110, 0xA3A1, 0x3111, 0xA3A2, 0x3112, 0xA3A3, 0x3113, 0xA3A4, 0x3114, 0xA3A5, 0x3115, 0xA3A6, 0x3116, 0xA3A7, + 0x3117, 0xA3A8, 0x3118, 0xA3A9, 0x3119, 0xA3AA, 0x311A, 0xA3AB, 0x311B, 0xA3AC, 0x311C, 0xA3AD, 0x311D, 0xA3AE, 0x311E, 0xA3AF, + 0x311F, 0xA3B0, 0x3120, 0xA3B1, 0x3121, 0xA3B2, 0x3122, 0xA3B3, 0x3123, 0xA3B4, 0x3124, 0xA3B5, 0x3125, 0xA3B6, 0x3126, 0xA3B7, + 0x3127, 0xA3B8, 0x3128, 0xA3B9, 0x3129, 0xA3BA, 0x32A3, 0xA1C0, 0x338E, 0xA255, 0x338F, 0xA256, 0x339C, 0xA250, 0x339D, 0xA251, + 0x339E, 0xA252, 0x33A1, 0xA254, 0x33C4, 0xA257, 0x33CE, 0xA253, 0x33D1, 0xA1EB, 0x33D2, 0xA1EA, 0x33D5, 0xA24F, 0x4E00, 0xA440, + 0x4E01, 0xA442, 0x4E03, 0xA443, 0x4E07, 0xC945, 0x4E08, 0xA456, 0x4E09, 0xA454, 0x4E0A, 0xA457, 0x4E0B, 0xA455, 0x4E0C, 0xC946, + 0x4E0D, 0xA4A3, 0x4E0E, 0xC94F, 0x4E0F, 0xC94D, 0x4E10, 0xA4A2, 0x4E11, 0xA4A1, 0x4E14, 0xA542, 0x4E15, 0xA541, 0x4E16, 0xA540, + 0x4E18, 0xA543, 0x4E19, 0xA4FE, 0x4E1E, 0xA5E0, 0x4E1F, 0xA5E1, 0x4E26, 0xA8C3, 0x4E2B, 0xA458, 0x4E2D, 0xA4A4, 0x4E2E, 0xC950, + 0x4E30, 0xA4A5, 0x4E31, 0xC963, 0x4E32, 0xA6EA, 0x4E33, 0xCBB1, 0x4E38, 0xA459, 0x4E39, 0xA4A6, 0x4E3B, 0xA544, 0x4E3C, 0xC964, + 0x4E42, 0xC940, 0x4E43, 0xA444, 0x4E45, 0xA45B, 0x4E47, 0xC947, 0x4E48, 0xA45C, 0x4E4B, 0xA4A7, 0x4E4D, 0xA545, 0x4E4E, 0xA547, + 0x4E4F, 0xA546, 0x4E52, 0xA5E2, 0x4E53, 0xA5E3, 0x4E56, 0xA8C4, 0x4E58, 0xADBC, 0x4E59, 0xA441, 0x4E5C, 0xC941, 0x4E5D, 0xA445, + 0x4E5E, 0xA45E, 0x4E5F, 0xA45D, 0x4E69, 0xA5E4, 0x4E73, 0xA8C5, 0x4E7E, 0xB0AE, 0x4E7F, 0xD44B, 0x4E82, 0xB6C3, 0x4E83, 0xDCB1, + 0x4E84, 0xDCB2, 0x4E86, 0xA446, 0x4E88, 0xA4A9, 0x4E8B, 0xA8C6, 0x4E8C, 0xA447, 0x4E8D, 0xC948, 0x4E8E, 0xA45F, 0x4E91, 0xA4AA, + 0x4E92, 0xA4AC, 0x4E93, 0xC951, 0x4E94, 0xA4AD, 0x4E95, 0xA4AB, 0x4E99, 0xA5E5, 0x4E9B, 0xA8C7, 0x4E9E, 0xA8C8, 0x4E9F, 0xAB45, + 0x4EA1, 0xA460, 0x4EA2, 0xA4AE, 0x4EA4, 0xA5E6, 0x4EA5, 0xA5E8, 0x4EA6, 0xA5E7, 0x4EA8, 0xA6EB, 0x4EAB, 0xA8C9, 0x4EAC, 0xA8CA, + 0x4EAD, 0xAB46, 0x4EAE, 0xAB47, 0x4EB3, 0xADBD, 0x4EB6, 0xDCB3, 0x4EB9, 0xF6D6, 0x4EBA, 0xA448, 0x4EC0, 0xA4B0, 0x4EC1, 0xA4AF, + 0x4EC2, 0xC952, 0x4EC3, 0xA4B1, 0x4EC4, 0xA4B7, 0x4EC6, 0xA4B2, 0x4EC7, 0xA4B3, 0x4EC8, 0xC954, 0x4EC9, 0xC953, 0x4ECA, 0xA4B5, + 0x4ECB, 0xA4B6, 0x4ECD, 0xA4B4, 0x4ED4, 0xA54A, 0x4ED5, 0xA54B, 0x4ED6, 0xA54C, 0x4ED7, 0xA54D, 0x4ED8, 0xA549, 0x4ED9, 0xA550, + 0x4EDA, 0xC96A, 0x4EDC, 0xC966, 0x4EDD, 0xC969, 0x4EDE, 0xA551, 0x4EDF, 0xA561, 0x4EE1, 0xC968, 0x4EE3, 0xA54E, 0x4EE4, 0xA54F, + 0x4EE5, 0xA548, 0x4EE8, 0xC965, 0x4EE9, 0xC967, 0x4EF0, 0xA5F5, 0x4EF1, 0xC9B0, 0x4EF2, 0xA5F2, 0x4EF3, 0xA5F6, 0x4EF4, 0xC9BA, + 0x4EF5, 0xC9AE, 0x4EF6, 0xA5F3, 0x4EF7, 0xC9B2, 0x4EFB, 0xA5F4, 0x4EFD, 0xA5F7, 0x4EFF, 0xA5E9, 0x4F00, 0xC9B1, 0x4F01, 0xA5F8, + 0x4F02, 0xC9B5, 0x4F04, 0xC9B9, 0x4F05, 0xC9B6, 0x4F08, 0xC9B3, 0x4F09, 0xA5EA, 0x4F0A, 0xA5EC, 0x4F0B, 0xA5F9, 0x4F0D, 0xA5EE, + 0x4F0E, 0xC9AB, 0x4F0F, 0xA5F1, 0x4F10, 0xA5EF, 0x4F11, 0xA5F0, 0x4F12, 0xC9BB, 0x4F13, 0xC9B8, 0x4F14, 0xC9AF, 0x4F15, 0xA5ED, + 0x4F18, 0xC9AC, 0x4F19, 0xA5EB, 0x4F1D, 0xC9B4, 0x4F22, 0xC9B7, 0x4F2C, 0xC9AD, 0x4F2D, 0xCA66, 0x4F2F, 0xA742, 0x4F30, 0xA6F4, + 0x4F33, 0xCA67, 0x4F34, 0xA6F1, 0x4F36, 0xA744, 0x4F38, 0xA6F9, 0x4F3A, 0xA6F8, 0x4F3B, 0xCA5B, 0x4F3C, 0xA6FC, 0x4F3D, 0xA6F7, + 0x4F3E, 0xCA60, 0x4F3F, 0xCA68, 0x4F41, 0xCA64, 0x4F43, 0xA6FA, 0x4F46, 0xA6FD, 0x4F47, 0xA6EE, 0x4F48, 0xA747, 0x4F49, 0xCA5D, + 0x4F4C, 0xCBBD, 0x4F4D, 0xA6EC, 0x4F4E, 0xA743, 0x4F4F, 0xA6ED, 0x4F50, 0xA6F5, 0x4F51, 0xA6F6, 0x4F52, 0xCA62, 0x4F53, 0xCA5E, + 0x4F54, 0xA6FB, 0x4F55, 0xA6F3, 0x4F56, 0xCA5A, 0x4F57, 0xA6EF, 0x4F58, 0xCA65, 0x4F59, 0xA745, 0x4F5A, 0xA748, 0x4F5B, 0xA6F2, + 0x4F5C, 0xA740, 0x4F5D, 0xA746, 0x4F5E, 0xA6F0, 0x4F5F, 0xCA63, 0x4F60, 0xA741, 0x4F61, 0xCA69, 0x4F62, 0xCA5C, 0x4F63, 0xA6FE, + 0x4F64, 0xCA5F, 0x4F67, 0xCA61, 0x4F69, 0xA8D8, 0x4F6A, 0xCBBF, 0x4F6B, 0xCBCB, 0x4F6C, 0xA8D0, 0x4F6E, 0xCBCC, 0x4F6F, 0xA8CB, + 0x4F70, 0xA8D5, 0x4F73, 0xA8CE, 0x4F74, 0xCBB9, 0x4F75, 0xA8D6, 0x4F76, 0xCBB8, 0x4F77, 0xCBBC, 0x4F78, 0xCBC3, 0x4F79, 0xCBC1, + 0x4F7A, 0xA8DE, 0x4F7B, 0xA8D9, 0x4F7C, 0xCBB3, 0x4F7D, 0xCBB5, 0x4F7E, 0xA8DB, 0x4F7F, 0xA8CF, 0x4F80, 0xCBB6, 0x4F81, 0xCBC2, + 0x4F82, 0xCBC9, 0x4F83, 0xA8D4, 0x4F84, 0xCBBB, 0x4F85, 0xCBB4, 0x4F86, 0xA8D3, 0x4F87, 0xCBB7, 0x4F88, 0xA8D7, 0x4F89, 0xCBBA, + 0x4F8B, 0xA8D2, 0x4F8D, 0xA8CD, 0x4F8F, 0xA8DC, 0x4F90, 0xCBC4, 0x4F91, 0xA8DD, 0x4F92, 0xCBC8, 0x4F94, 0xCBC6, 0x4F95, 0xCBCA, + 0x4F96, 0xA8DA, 0x4F97, 0xCBBE, 0x4F98, 0xCBB2, 0x4F9A, 0xCBC0, 0x4F9B, 0xA8D1, 0x4F9C, 0xCBC5, 0x4F9D, 0xA8CC, 0x4F9E, 0xCBC7, + 0x4FAE, 0xAB56, 0x4FAF, 0xAB4A, 0x4FB2, 0xCDE0, 0x4FB3, 0xCDE8, 0x4FB5, 0xAB49, 0x4FB6, 0xAB51, 0x4FB7, 0xAB5D, 0x4FB9, 0xCDEE, + 0x4FBA, 0xCDEC, 0x4FBB, 0xCDE7, 0x4FBF, 0xAB4B, 0x4FC0, 0xCDED, 0x4FC1, 0xCDE3, 0x4FC2, 0xAB59, 0x4FC3, 0xAB50, 0x4FC4, 0xAB58, + 0x4FC5, 0xCDDE, 0x4FC7, 0xCDEA, 0x4FC9, 0xCDE1, 0x4FCA, 0xAB54, 0x4FCB, 0xCDE2, 0x4FCD, 0xCDDD, 0x4FCE, 0xAB5B, 0x4FCF, 0xAB4E, + 0x4FD0, 0xAB57, 0x4FD1, 0xAB4D, 0x4FD3, 0xCDDF, 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0xF3F0, + 0x9D88, 0xF3DC, 0x9D89, 0xC44C, 0x9D8A, 0xF3DA, 0x9D8B, 0xF3E1, 0x9D8C, 0xF3E2, 0x9D90, 0xF57D, 0x9D92, 0xF57B, 0x9D94, 0xF5A2, + 0x9D96, 0xF5AE, 0x9D97, 0xF5A5, 0x9D98, 0xF57C, 0x9D99, 0xF578, 0x9D9A, 0xF5A7, 0x9D9B, 0xF57E, 0x9D9C, 0xF5A3, 0x9D9D, 0xF57A, + 0x9D9E, 0xF5AA, 0x9D9F, 0xF577, 0x9DA0, 0xF5A1, 0x9DA1, 0xF5A6, 0x9DA2, 0xF5A8, 0x9DA3, 0xF5AB, 0x9DA4, 0xF579, 0x9DA6, 0xF5AF, + 0x9DA7, 0xF5B0, 0x9DA8, 0xF5A9, 0x9DA9, 0xF5AD, 0x9DAA, 0xF5A4, 0x9DAC, 0xF6C1, 0x9DAD, 0xF6C4, 0x9DAF, 0xC561, 0x9DB1, 0xF6C3, + 0x9DB2, 0xF6C8, 0x9DB3, 0xF6C6, 0x9DB4, 0xC562, 0x9DB5, 0xF6BD, 0x9DB6, 0xF6B3, 0x9DB7, 0xF6B2, 0x9DB8, 0xC564, 0x9DB9, 0xF6BF, + 0x9DBA, 0xF6C0, 0x9DBB, 0xF6BC, 0x9DBC, 0xF6B4, 0x9DBE, 0xF6B9, 0x9DBF, 0xF5AC, 0x9DC1, 0xF6B5, 0x9DC2, 0xC563, 0x9DC3, 0xF6BB, + 0x9DC5, 0xF6BA, 0x9DC7, 0xF6B6, 0x9DC8, 0xF6C2, 0x9DCA, 0xF6B7, 0x9DCB, 0xF7BB, 0x9DCC, 0xF6C5, 0x9DCD, 0xF6C7, 0x9DCE, 0xF6BE, + 0x9DCF, 0xF6B8, 0x9DD0, 0xF7BC, 0x9DD1, 0xF7BE, 0x9DD2, 0xF7B8, 0x9DD3, 0xC5C2, 0x9DD5, 0xF7C5, 0x9DD6, 0xF7C3, 0x9DD7, 0xC5C3, + 0x9DD8, 0xF7C2, 0x9DD9, 0xF7C1, 0x9DDA, 0xF7BA, 0x9DDB, 0xF7B7, 0x9DDC, 0xF7BD, 0x9DDD, 0xF7C6, 0x9DDE, 0xF7B9, 0x9DDF, 0xF7BF, + 0x9DE1, 0xF869, 0x9DE2, 0xF86E, 0x9DE3, 0xF864, 0x9DE4, 0xF867, 0x9DE5, 0xC5EE, 0x9DE6, 0xF86B, 0x9DE8, 0xF872, 0x9DE9, 0xF7C0, + 0x9DEB, 0xF865, 0x9DEC, 0xF86F, 0x9DED, 0xF873, 0x9DEE, 0xF86A, 0x9DEF, 0xF863, 0x9DF0, 0xF86D, 0x9DF2, 0xF86C, 0x9DF3, 0xF871, + 0x9DF4, 0xF870, 0x9DF5, 0xF7C4, 0x9DF6, 0xF868, 0x9DF7, 0xF862, 0x9DF8, 0xF866, 0x9DF9, 0xC64E, 0x9DFA, 0xC64F, 0x9DFB, 0xF861, + 0x9DFD, 0xF8E6, 0x9DFE, 0xF8DD, 0x9DFF, 0xF8E5, 0x9E00, 0xF8E2, 0x9E01, 0xF8E3, 0x9E02, 0xF8DC, 0x9E03, 0xF8DF, 0x9E04, 0xF8E7, + 0x9E05, 0xF8E1, 0x9E06, 0xF8E0, 0x9E07, 0xF8DE, 0x9E09, 0xF8E4, 0x9E0B, 0xF95D, 0x9E0D, 0xF95E, 0x9E0F, 0xF960, 0x9E10, 0xF95F, + 0x9E11, 0xF962, 0x9E12, 0xF961, 0x9E13, 0xF97C, 0x9E14, 0xF97B, 0x9E15, 0xF9B7, 0x9E17, 0xF9B8, 0x9E19, 0xF9C5, 0x9E1A, 0xC678, + 0x9E1B, 0xC67C, 0x9E1D, 0xF9CF, 0x9E1E, 0xC67D, 0x9E75, 0xB3BF, 0x9E79, 0xC4D0, 0x9E7A, 0xF6C9, 0x9E7C, 0xC650, 0x9E7D, 0xC651, + 0x9E7F, 0xB3C0, 0x9E80, 0xE0EE, 0x9E82, 0xB9A8, 0x9E83, 0xE8F0, 0x9E86, 0xECB0, 0x9E87, 0xECB1, 0x9E88, 0xECAF, 0x9E89, 0xEFAB, + 0x9E8A, 0xEFAA, 0x9E8B, 0xC247, 0x9E8C, 0xF1DF, 0x9E8D, 0xEFAC, 0x9E8E, 0xF1DE, 0x9E91, 0xF3F3, 0x9E92, 0xC451, 0x9E93, 0xC453, + 0x9E94, 0xF3F2, 0x9E97, 0xC452, 0x9E99, 0xF5B1, 0x9E9A, 0xF5B3, 0x9E9B, 0xF5B2, 0x9E9C, 0xF6CA, 0x9E9D, 0xC565, 0x9E9F, 0xC5EF, + 0x9EA0, 0xF8E8, 0x9EA1, 0xF963, 0x9EA4, 0xF9D2, 0x9EA5, 0xB3C1, 0x9EA7, 0xE4E5, 0x9EA9, 0xBEA2, 0x9EAD, 0xECB3, 0x9EAE, 0xECB2, + 0x9EB0, 0xEFAD, 0x9EB4, 0xC454, 0x9EB5, 0xC4D1, 0x9EB6, 0xF7C7, 0x9EB7, 0xF9CB, 0x9EBB, 0xB3C2, 0x9EBC, 0xBBF2, 0x9EBE, 0xBEA3, + 0x9EC0, 0xF3F4, 0x9EC2, 0xF874, 0x9EC3, 0xB6C0, 0x9EC8, 0xEFAE, 0x9ECC, 0xC664, 0x9ECD, 0xB6C1, 0x9ECE, 0xBEA4, 0x9ECF, 0xC248, + 0x9ED0, 0xF875, 0x9ED1, 0xB6C2, 0x9ED3, 0xE8F1, 0x9ED4, 0xC072, 0x9ED5, 0xECB4, 0x9ED6, 0xECB5, 0x9ED8, 0xC071, 0x9EDA, 0xEFAF, + 0x9EDB, 0xC24C, 0x9EDC, 0xC24A, 0x9EDD, 0xC24B, 0x9EDE, 0xC249, 0x9EDF, 0xF1E0, 0x9EE0, 0xC35C, 0x9EE4, 0xF5B5, 0x9EE5, 0xF5B4, + 0x9EE6, 0xF5B7, 0x9EE7, 0xF5B6, 0x9EE8, 0xC4D2, 0x9EEB, 0xF6CB, 0x9EED, 0xF6CD, 0x9EEE, 0xF6CC, 0x9EEF, 0xC566, 0x9EF0, 0xF7C8, + 0x9EF2, 0xF876, 0x9EF3, 0xF877, 0x9EF4, 0xC5F0, 0x9EF5, 0xF964, 0x9EF6, 0xF97D, 0x9EF7, 0xC675, 0x9EF9, 0xDCB0, 0x9EFA, 0xECB6, + 0x9EFB, 0xEFB0, 0x9EFC, 0xF3F5, 0x9EFD, 0xE0EF, 0x9EFF, 0xEFB1, 0x9F00, 0xF1E2, 0x9F01, 0xF1E1, 0x9F06, 0xF878, 0x9F07, 0xC652, + 0x9F09, 0xF965, 0x9F0A, 0xF97E, 0x9F0E, 0xB9A9, 0x9F0F, 0xE8F2, 0x9F10, 0xE8F3, 0x9F12, 0xECB7, 0x9F13, 0xB9AA, 0x9F15, 0xC35D, + 0x9F16, 0xF1E3, 0x9F18, 0xF6CF, 0x9F19, 0xC567, 0x9F1A, 0xF6D0, 0x9F1B, 0xF6CE, 0x9F1C, 0xF879, 0x9F1E, 0xF8E9, 0x9F20, 0xB9AB, + 0x9F22, 0xEFB4, 0x9F23, 0xEFB3, 0x9F24, 0xEFB2, 0x9F25, 0xF1E4, 0x9F28, 0xF1E8, 0x9F29, 0xF1E7, 0x9F2A, 0xF1E6, 0x9F2B, 0xF1E5, + 0x9F2C, 0xC35E, 0x9F2D, 0xF3F6, 0x9F2E, 0xF5B9, 0x9F2F, 0xC4D3, 0x9F30, 0xF5B8, 0x9F31, 0xF6D1, 0x9F32, 0xF7CB, 0x9F33, 0xF7CA, + 0x9F34, 0xC5C4, 0x9F35, 0xF7C9, 0x9F36, 0xF87C, 0x9F37, 0xF87B, 0x9F38, 0xF87A, 0x9F3B, 0xBBF3, 0x9F3D, 0xECB8, 0x9F3E, 0xC24D, + 0x9F40, 0xF3F7, 0x9F41, 0xF3F8, 0x9F42, 0xF7CC, 0x9F43, 0xF87D, 0x9F46, 0xF8EA, 0x9F47, 0xF966, 0x9F48, 0xF9B9, 0x9F49, 0xF9D4, + 0x9F4A, 0xBBF4, 0x9F4B, 0xC24E, 0x9F4C, 0xF1E9, 0x9F4D, 0xF3F9, 0x9F4E, 0xF6D2, 0x9F4F, 0xF87E, 0x9F52, 0xBEA6, 0x9F54, 0xEFB5, + 0x9F55, 0xF1EA, 0x9F56, 0xF3FA, 0x9F57, 0xF3FB, 0x9F58, 0xF3FC, 0x9F59, 0xF5BE, 0x9F5B, 0xF5BA, 0x9F5C, 0xC568, 0x9F5D, 0xF5BD, + 0x9F5E, 0xF5BC, 0x9F5F, 0xC4D4, 0x9F60, 0xF5BB, 0x9F61, 0xC4D6, 0x9F63, 0xC4D5, 0x9F64, 0xF6D4, 0x9F65, 0xF6D3, 0x9F66, 0xC569, + 0x9F67, 0xC56A, 0x9F6A, 0xC5C6, 0x9F6B, 0xF7CD, 0x9F6C, 0xC5C5, 0x9F6E, 0xF8A3, 0x9F6F, 0xF8A4, 0x9F70, 0xF8A2, 0x9F71, 0xF8A1, + 0x9F72, 0xC654, 0x9F74, 0xF8EB, 0x9F75, 0xF8EC, 0x9F76, 0xF8ED, 0x9F77, 0xC653, 0x9F78, 0xF967, 0x9F79, 0xF96A, 0x9F7A, 0xF969, + 0x9F7B, 0xF968, 0x9F7E, 0xF9D3, 0x9F8D, 0xC073, 0x9F90, 0xC365, 0x9F91, 0xF5BF, 0x9F92, 0xF6D5, 0x9F94, 0xC5C7, 0x9F95, 0xF7CE, + 0x9F98, 0xF9D5, 0x9F9C, 0xC074, 0x9FA0, 0xEFB6, 0x9FA2, 0xF7CF, 0x9FA4, 0xF9A1, 0xFA0C, 0xC94A, 0xFA0D, 0xDDFC, 0xFE30, 0xA14A, + 0xFE31, 0xA157, 0xFE33, 0xA159, 0xFE34, 0xA15B, 0xFE35, 0xA15F, 0xFE36, 0xA160, 0xFE37, 0xA163, 0xFE38, 0xA164, 0xFE39, 0xA167, + 0xFE3A, 0xA168, 0xFE3B, 0xA16B, 0xFE3C, 0xA16C, 0xFE3D, 0xA16F, 0xFE3E, 0xA170, 0xFE3F, 0xA173, 0xFE40, 0xA174, 0xFE41, 0xA177, + 0xFE42, 0xA178, 0xFE43, 0xA17B, 0xFE44, 0xA17C, 0xFE49, 0xA1C6, 0xFE4A, 0xA1C7, 0xFE4B, 0xA1CA, 0xFE4C, 0xA1CB, 0xFE4D, 0xA1C8, + 0xFE4E, 0xA1C9, 0xFE4F, 0xA15C, 0xFE50, 0xA14D, 0xFE51, 0xA14E, 0xFE52, 0xA14F, 0xFE54, 0xA151, 0xFE55, 0xA152, 0xFE56, 0xA153, + 0xFE57, 0xA154, 0xFE59, 0xA17D, 0xFE5A, 0xA17E, 0xFE5B, 0xA1A1, 0xFE5C, 0xA1A2, 0xFE5D, 0xA1A3, 0xFE5E, 0xA1A4, 0xFE5F, 0xA1CC, + 0xFE60, 0xA1CD, 0xFE61, 0xA1CE, 0xFE62, 0xA1DE, 0xFE63, 0xA1DF, 0xFE64, 0xA1E0, 0xFE65, 0xA1E1, 0xFE66, 0xA1E2, 0xFE68, 0xA242, + 0xFE69, 0xA24C, 0xFE6A, 0xA24D, 0xFE6B, 0xA24E, 0xFF01, 0xA149, 0xFF03, 0xA1AD, 0xFF04, 0xA243, 0xFF05, 0xA248, 0xFF06, 0xA1AE, + 0xFF08, 0xA15D, 0xFF09, 0xA15E, 0xFF0A, 0xA1AF, 0xFF0B, 0xA1CF, 0xFF0C, 0xA141, 0xFF0D, 0xA1D0, 0xFF0E, 0xA144, 0xFF0F, 0xA1FE, + 0xFF10, 0xA2AF, 0xFF11, 0xA2B0, 0xFF12, 0xA2B1, 0xFF13, 0xA2B2, 0xFF14, 0xA2B3, 0xFF15, 0xA2B4, 0xFF16, 0xA2B5, 0xFF17, 0xA2B6, + 0xFF18, 0xA2B7, 0xFF19, 0xA2B8, 0xFF1A, 0xA147, 0xFF1B, 0xA146, 0xFF1C, 0xA1D5, 0xFF1D, 0xA1D7, 0xFF1E, 0xA1D6, 0xFF1F, 0xA148, + 0xFF20, 0xA249, 0xFF21, 0xA2CF, 0xFF22, 0xA2D0, 0xFF23, 0xA2D1, 0xFF24, 0xA2D2, 0xFF25, 0xA2D3, 0xFF26, 0xA2D4, 0xFF27, 0xA2D5, + 0xFF28, 0xA2D6, 0xFF29, 0xA2D7, 0xFF2A, 0xA2D8, 0xFF2B, 0xA2D9, 0xFF2C, 0xA2DA, 0xFF2D, 0xA2DB, 0xFF2E, 0xA2DC, 0xFF2F, 0xA2DD, + 0xFF30, 0xA2DE, 0xFF31, 0xA2DF, 0xFF32, 0xA2E0, 0xFF33, 0xA2E1, 0xFF34, 0xA2E2, 0xFF35, 0xA2E3, 0xFF36, 0xA2E4, 0xFF37, 0xA2E5, + 0xFF38, 0xA2E6, 0xFF39, 0xA2E7, 0xFF3A, 0xA2E8, 0xFF3C, 0xA240, 0xFF3F, 0xA1C4, 0xFF41, 0xA2E9, 0xFF42, 0xA2EA, 0xFF43, 0xA2EB, + 0xFF44, 0xA2EC, 0xFF45, 0xA2ED, 0xFF46, 0xA2EE, 0xFF47, 0xA2EF, 0xFF48, 0xA2F0, 0xFF49, 0xA2F1, 0xFF4A, 0xA2F2, 0xFF4B, 0xA2F3, + 0xFF4C, 0xA2F4, 0xFF4D, 0xA2F5, 0xFF4E, 0xA2F6, 0xFF4F, 0xA2F7, 0xFF50, 0xA2F8, 0xFF51, 0xA2F9, 0xFF52, 0xA2FA, 0xFF53, 0xA2FB, + 0xFF54, 0xA2FC, 0xFF55, 0xA2FD, 0xFF56, 0xA2FE, 0xFF57, 0xA340, 0xFF58, 0xA341, 0xFF59, 0xA342, 0xFF5A, 0xA343, 0xFF5B, 0xA161, + 0xFF5C, 0xA155, 0xFF5D, 0xA162, 0xFF5E, 0xA1E3, 0xFFE0, 0xA246, 0xFFE1, 0xA247, 0xFFE3, 0xA1C3, 0xFFE5, 0xA244, 0, 0 +}; + +static const WCHAR oem2uni950[] = { /* Big5 --> Unicode pairs */ + 0xA140, 0x3000, 0xA141, 0xFF0C, 0xA142, 0x3001, 0xA143, 0x3002, 0xA144, 0xFF0E, 0xA145, 0x2027, 0xA146, 0xFF1B, 0xA147, 0xFF1A, + 0xA148, 0xFF1F, 0xA149, 0xFF01, 0xA14A, 0xFE30, 0xA14B, 0x2026, 0xA14C, 0x2025, 0xA14D, 0xFE50, 0xA14E, 0xFE51, 0xA14F, 0xFE52, + 0xA150, 0x00B7, 0xA151, 0xFE54, 0xA152, 0xFE55, 0xA153, 0xFE56, 0xA154, 0xFE57, 0xA155, 0xFF5C, 0xA156, 0x2013, 0xA157, 0xFE31, + 0xA158, 0x2014, 0xA159, 0xFE33, 0xA15A, 0x2574, 0xA15B, 0xFE34, 0xA15C, 0xFE4F, 0xA15D, 0xFF08, 0xA15E, 0xFF09, 0xA15F, 0xFE35, + 0xA160, 0xFE36, 0xA161, 0xFF5B, 0xA162, 0xFF5D, 0xA163, 0xFE37, 0xA164, 0xFE38, 0xA165, 0x3014, 0xA166, 0x3015, 0xA167, 0xFE39, + 0xA168, 0xFE3A, 0xA169, 0x3010, 0xA16A, 0x3011, 0xA16B, 0xFE3B, 0xA16C, 0xFE3C, 0xA16D, 0x300A, 0xA16E, 0x300B, 0xA16F, 0xFE3D, + 0xA170, 0xFE3E, 0xA171, 0x3008, 0xA172, 0x3009, 0xA173, 0xFE3F, 0xA174, 0xFE40, 0xA175, 0x300C, 0xA176, 0x300D, 0xA177, 0xFE41, + 0xA178, 0xFE42, 0xA179, 0x300E, 0xA17A, 0x300F, 0xA17B, 0xFE43, 0xA17C, 0xFE44, 0xA17D, 0xFE59, 0xA17E, 0xFE5A, 0xA1A1, 0xFE5B, + 0xA1A2, 0xFE5C, 0xA1A3, 0xFE5D, 0xA1A4, 0xFE5E, 0xA1A5, 0x2018, 0xA1A6, 0x2019, 0xA1A7, 0x201C, 0xA1A8, 0x201D, 0xA1A9, 0x301D, + 0xA1AA, 0x301E, 0xA1AB, 0x2035, 0xA1AC, 0x2032, 0xA1AD, 0xFF03, 0xA1AE, 0xFF06, 0xA1AF, 0xFF0A, 0xA1B0, 0x203B, 0xA1B1, 0x00A7, + 0xA1B2, 0x3003, 0xA1B3, 0x25CB, 0xA1B4, 0x25CF, 0xA1B5, 0x25B3, 0xA1B6, 0x25B2, 0xA1B7, 0x25CE, 0xA1B8, 0x2606, 0xA1B9, 0x2605, + 0xA1BA, 0x25C7, 0xA1BB, 0x25C6, 0xA1BC, 0x25A1, 0xA1BD, 0x25A0, 0xA1BE, 0x25BD, 0xA1BF, 0x25BC, 0xA1C0, 0x32A3, 0xA1C1, 0x2105, + 0xA1C2, 0x00AF, 0xA1C3, 0xFFE3, 0xA1C4, 0xFF3F, 0xA1C5, 0x02CD, 0xA1C6, 0xFE49, 0xA1C7, 0xFE4A, 0xA1C8, 0xFE4D, 0xA1C9, 0xFE4E, + 0xA1CA, 0xFE4B, 0xA1CB, 0xFE4C, 0xA1CC, 0xFE5F, 0xA1CD, 0xFE60, 0xA1CE, 0xFE61, 0xA1CF, 0xFF0B, 0xA1D0, 0xFF0D, 0xA1D1, 0x00D7, + 0xA1D2, 0x00F7, 0xA1D3, 0x00B1, 0xA1D4, 0x221A, 0xA1D5, 0xFF1C, 0xA1D6, 0xFF1E, 0xA1D7, 0xFF1D, 0xA1D8, 0x2266, 0xA1D9, 0x2267, + 0xA1DA, 0x2260, 0xA1DB, 0x221E, 0xA1DC, 0x2252, 0xA1DD, 0x2261, 0xA1DE, 0xFE62, 0xA1DF, 0xFE63, 0xA1E0, 0xFE64, 0xA1E1, 0xFE65, + 0xA1E2, 0xFE66, 0xA1E3, 0xFF5E, 0xA1E4, 0x2229, 0xA1E5, 0x222A, 0xA1E6, 0x22A5, 0xA1E7, 0x2220, 0xA1E8, 0x221F, 0xA1E9, 0x22BF, + 0xA1EA, 0x33D2, 0xA1EB, 0x33D1, 0xA1EC, 0x222B, 0xA1ED, 0x222E, 0xA1EE, 0x2235, 0xA1EF, 0x2234, 0xA1F0, 0x2640, 0xA1F1, 0x2642, + 0xA1F2, 0x2295, 0xA1F3, 0x2299, 0xA1F4, 0x2191, 0xA1F5, 0x2193, 0xA1F6, 0x2190, 0xA1F7, 0x2192, 0xA1F8, 0x2196, 0xA1F9, 0x2197, + 0xA1FA, 0x2199, 0xA1FB, 0x2198, 0xA1FC, 0x2225, 0xA1FD, 0x2223, 0xA1FE, 0xFF0F, 0xA240, 0xFF3C, 0xA241, 0x2215, 0xA242, 0xFE68, + 0xA243, 0xFF04, 0xA244, 0xFFE5, 0xA245, 0x3012, 0xA246, 0xFFE0, 0xA247, 0xFFE1, 0xA248, 0xFF05, 0xA249, 0xFF20, 0xA24A, 0x2103, + 0xA24B, 0x2109, 0xA24C, 0xFE69, 0xA24D, 0xFE6A, 0xA24E, 0xFE6B, 0xA24F, 0x33D5, 0xA250, 0x339C, 0xA251, 0x339D, 0xA252, 0x339E, + 0xA253, 0x33CE, 0xA254, 0x33A1, 0xA255, 0x338E, 0xA256, 0x338F, 0xA257, 0x33C4, 0xA258, 0x00B0, 0xA259, 0x5159, 0xA25A, 0x515B, + 0xA25B, 0x515E, 0xA25C, 0x515D, 0xA25D, 0x5161, 0xA25E, 0x5163, 0xA25F, 0x55E7, 0xA260, 0x74E9, 0xA261, 0x7CCE, 0xA262, 0x2581, + 0xA263, 0x2582, 0xA264, 0x2583, 0xA265, 0x2584, 0xA266, 0x2585, 0xA267, 0x2586, 0xA268, 0x2587, 0xA269, 0x2588, 0xA26A, 0x258F, + 0xA26B, 0x258E, 0xA26C, 0x258D, 0xA26D, 0x258C, 0xA26E, 0x258B, 0xA26F, 0x258A, 0xA270, 0x2589, 0xA271, 0x253C, 0xA272, 0x2534, + 0xA273, 0x252C, 0xA274, 0x2524, 0xA275, 0x251C, 0xA276, 0x2594, 0xA277, 0x2500, 0xA278, 0x2502, 0xA279, 0x2595, 0xA27A, 0x250C, + 0xA27B, 0x2510, 0xA27C, 0x2514, 0xA27D, 0x2518, 0xA27E, 0x256D, 0xA2A1, 0x256E, 0xA2A2, 0x2570, 0xA2A3, 0x256F, 0xA2A4, 0x2550, + 0xA2A5, 0x255E, 0xA2A6, 0x256A, 0xA2A7, 0x2561, 0xA2A8, 0x25E2, 0xA2A9, 0x25E3, 0xA2AA, 0x25E5, 0xA2AB, 0x25E4, 0xA2AC, 0x2571, + 0xA2AD, 0x2572, 0xA2AE, 0x2573, 0xA2AF, 0xFF10, 0xA2B0, 0xFF11, 0xA2B1, 0xFF12, 0xA2B2, 0xFF13, 0xA2B3, 0xFF14, 0xA2B4, 0xFF15, + 0xA2B5, 0xFF16, 0xA2B6, 0xFF17, 0xA2B7, 0xFF18, 0xA2B8, 0xFF19, 0xA2B9, 0x2160, 0xA2BA, 0x2161, 0xA2BB, 0x2162, 0xA2BC, 0x2163, + 0xA2BD, 0x2164, 0xA2BE, 0x2165, 0xA2BF, 0x2166, 0xA2C0, 0x2167, 0xA2C1, 0x2168, 0xA2C2, 0x2169, 0xA2C3, 0x3021, 0xA2C4, 0x3022, + 0xA2C5, 0x3023, 0xA2C6, 0x3024, 0xA2C7, 0x3025, 0xA2C8, 0x3026, 0xA2C9, 0x3027, 0xA2CA, 0x3028, 0xA2CB, 0x3029, 0xA2CC, 0x5341, + 0xA2CD, 0x5344, 0xA2CE, 0x5345, 0xA2CF, 0xFF21, 0xA2D0, 0xFF22, 0xA2D1, 0xFF23, 0xA2D2, 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0xF6DF, 0x5EF2, 0xF6E0, 0x6521, 0xF6E1, 0x6520, 0xF6E2, 0x6526, 0xF6E3, 0x6522, 0xF6E4, 0x6B0B, 0xF6E5, 0x6B08, 0xF6E6, 0x6B09, + 0xF6E7, 0x6C0D, 0xF6E8, 0x7055, 0xF6E9, 0x7056, 0xF6EA, 0x7057, 0xF6EB, 0x7052, 0xF6EC, 0x721E, 0xF6ED, 0x721F, 0xF6EE, 0x72A9, + 0xF6EF, 0x737F, 0xF6F0, 0x74D8, 0xF6F1, 0x74D5, 0xF6F2, 0x74D9, 0xF6F3, 0x74D7, 0xF6F4, 0x766D, 0xF6F5, 0x76AD, 0xF6F6, 0x7935, + 0xF6F7, 0x79B4, 0xF6F8, 0x7A70, 0xF6F9, 0x7A71, 0xF6FA, 0x7C57, 0xF6FB, 0x7C5C, 0xF6FC, 0x7C59, 0xF6FD, 0x7C5B, 0xF6FE, 0x7C5A, + 0xF740, 0x7CF4, 0xF741, 0x7CF1, 0xF742, 0x7E91, 0xF743, 0x7F4F, 0xF744, 0x7F87, 0xF745, 0x81DE, 0xF746, 0x826B, 0xF747, 0x8634, + 0xF748, 0x8635, 0xF749, 0x8633, 0xF74A, 0x862C, 0xF74B, 0x8632, 0xF74C, 0x8636, 0xF74D, 0x882C, 0xF74E, 0x8828, 0xF74F, 0x8826, + 0xF750, 0x882A, 0xF751, 0x8825, 0xF752, 0x8971, 0xF753, 0x89BF, 0xF754, 0x89BE, 0xF755, 0x89FB, 0xF756, 0x8B7E, 0xF757, 0x8B84, + 0xF758, 0x8B82, 0xF759, 0x8B86, 0xF75A, 0x8B85, 0xF75B, 0x8B7F, 0xF75C, 0x8D15, 0xF75D, 0x8E95, 0xF75E, 0x8E94, 0xF75F, 0x8E9A, + 0xF760, 0x8E92, 0xF761, 0x8E90, 0xF762, 0x8E96, 0xF763, 0x8E97, 0xF764, 0x8F60, 0xF765, 0x8F62, 0xF766, 0x9147, 0xF767, 0x944C, + 0xF768, 0x9450, 0xF769, 0x944A, 0xF76A, 0x944B, 0xF76B, 0x944F, 0xF76C, 0x9447, 0xF76D, 0x9445, 0xF76E, 0x9448, 0xF76F, 0x9449, + 0xF770, 0x9446, 0xF771, 0x973F, 0xF772, 0x97E3, 0xF773, 0x986A, 0xF774, 0x9869, 0xF775, 0x98CB, 0xF776, 0x9954, 0xF777, 0x995B, + 0xF778, 0x9A4E, 0xF779, 0x9A53, 0xF77A, 0x9A54, 0xF77B, 0x9A4C, 0xF77C, 0x9A4F, 0xF77D, 0x9A48, 0xF77E, 0x9A4A, 0xF7A1, 0x9A49, + 0xF7A2, 0x9A52, 0xF7A3, 0x9A50, 0xF7A4, 0x9AD0, 0xF7A5, 0x9B19, 0xF7A6, 0x9B2B, 0xF7A7, 0x9B3B, 0xF7A8, 0x9B56, 0xF7A9, 0x9B55, + 0xF7AA, 0x9C46, 0xF7AB, 0x9C48, 0xF7AC, 0x9C3F, 0xF7AD, 0x9C44, 0xF7AE, 0x9C39, 0xF7AF, 0x9C33, 0xF7B0, 0x9C41, 0xF7B1, 0x9C3C, + 0xF7B2, 0x9C37, 0xF7B3, 0x9C34, 0xF7B4, 0x9C32, 0xF7B5, 0x9C3D, 0xF7B6, 0x9C36, 0xF7B7, 0x9DDB, 0xF7B8, 0x9DD2, 0xF7B9, 0x9DDE, + 0xF7BA, 0x9DDA, 0xF7BB, 0x9DCB, 0xF7BC, 0x9DD0, 0xF7BD, 0x9DDC, 0xF7BE, 0x9DD1, 0xF7BF, 0x9DDF, 0xF7C0, 0x9DE9, 0xF7C1, 0x9DD9, + 0xF7C2, 0x9DD8, 0xF7C3, 0x9DD6, 0xF7C4, 0x9DF5, 0xF7C5, 0x9DD5, 0xF7C6, 0x9DDD, 0xF7C7, 0x9EB6, 0xF7C8, 0x9EF0, 0xF7C9, 0x9F35, + 0xF7CA, 0x9F33, 0xF7CB, 0x9F32, 0xF7CC, 0x9F42, 0xF7CD, 0x9F6B, 0xF7CE, 0x9F95, 0xF7CF, 0x9FA2, 0xF7D0, 0x513D, 0xF7D1, 0x5299, + 0xF7D2, 0x58E8, 0xF7D3, 0x58E7, 0xF7D4, 0x5972, 0xF7D5, 0x5B4D, 0xF7D6, 0x5DD8, 0xF7D7, 0x882F, 0xF7D8, 0x5F4F, 0xF7D9, 0x6201, + 0xF7DA, 0x6203, 0xF7DB, 0x6204, 0xF7DC, 0x6529, 0xF7DD, 0x6525, 0xF7DE, 0x6596, 0xF7DF, 0x66EB, 0xF7E0, 0x6B11, 0xF7E1, 0x6B12, + 0xF7E2, 0x6B0F, 0xF7E3, 0x6BCA, 0xF7E4, 0x705B, 0xF7E5, 0x705A, 0xF7E6, 0x7222, 0xF7E7, 0x7382, 0xF7E8, 0x7381, 0xF7E9, 0x7383, + 0xF7EA, 0x7670, 0xF7EB, 0x77D4, 0xF7EC, 0x7C67, 0xF7ED, 0x7C66, 0xF7EE, 0x7E95, 0xF7EF, 0x826C, 0xF7F0, 0x863A, 0xF7F1, 0x8640, + 0xF7F2, 0x8639, 0xF7F3, 0x863C, 0xF7F4, 0x8631, 0xF7F5, 0x863B, 0xF7F6, 0x863E, 0xF7F7, 0x8830, 0xF7F8, 0x8832, 0xF7F9, 0x882E, + 0xF7FA, 0x8833, 0xF7FB, 0x8976, 0xF7FC, 0x8974, 0xF7FD, 0x8973, 0xF7FE, 0x89FE, 0xF840, 0x8B8C, 0xF841, 0x8B8E, 0xF842, 0x8B8B, + 0xF843, 0x8B88, 0xF844, 0x8C45, 0xF845, 0x8D19, 0xF846, 0x8E98, 0xF847, 0x8F64, 0xF848, 0x8F63, 0xF849, 0x91BC, 0xF84A, 0x9462, + 0xF84B, 0x9455, 0xF84C, 0x945D, 0xF84D, 0x9457, 0xF84E, 0x945E, 0xF84F, 0x97C4, 0xF850, 0x97C5, 0xF851, 0x9800, 0xF852, 0x9A56, + 0xF853, 0x9A59, 0xF854, 0x9B1E, 0xF855, 0x9B1F, 0xF856, 0x9B20, 0xF857, 0x9C52, 0xF858, 0x9C58, 0xF859, 0x9C50, 0xF85A, 0x9C4A, + 0xF85B, 0x9C4D, 0xF85C, 0x9C4B, 0xF85D, 0x9C55, 0xF85E, 0x9C59, 0xF85F, 0x9C4C, 0xF860, 0x9C4E, 0xF861, 0x9DFB, 0xF862, 0x9DF7, + 0xF863, 0x9DEF, 0xF864, 0x9DE3, 0xF865, 0x9DEB, 0xF866, 0x9DF8, 0xF867, 0x9DE4, 0xF868, 0x9DF6, 0xF869, 0x9DE1, 0xF86A, 0x9DEE, + 0xF86B, 0x9DE6, 0xF86C, 0x9DF2, 0xF86D, 0x9DF0, 0xF86E, 0x9DE2, 0xF86F, 0x9DEC, 0xF870, 0x9DF4, 0xF871, 0x9DF3, 0xF872, 0x9DE8, + 0xF873, 0x9DED, 0xF874, 0x9EC2, 0xF875, 0x9ED0, 0xF876, 0x9EF2, 0xF877, 0x9EF3, 0xF878, 0x9F06, 0xF879, 0x9F1C, 0xF87A, 0x9F38, + 0xF87B, 0x9F37, 0xF87C, 0x9F36, 0xF87D, 0x9F43, 0xF87E, 0x9F4F, 0xF8A1, 0x9F71, 0xF8A2, 0x9F70, 0xF8A3, 0x9F6E, 0xF8A4, 0x9F6F, + 0xF8A5, 0x56D3, 0xF8A6, 0x56CD, 0xF8A7, 0x5B4E, 0xF8A8, 0x5C6D, 0xF8A9, 0x652D, 0xF8AA, 0x66ED, 0xF8AB, 0x66EE, 0xF8AC, 0x6B13, + 0xF8AD, 0x705F, 0xF8AE, 0x7061, 0xF8AF, 0x705D, 0xF8B0, 0x7060, 0xF8B1, 0x7223, 0xF8B2, 0x74DB, 0xF8B3, 0x74E5, 0xF8B4, 0x77D5, + 0xF8B5, 0x7938, 0xF8B6, 0x79B7, 0xF8B7, 0x79B6, 0xF8B8, 0x7C6A, 0xF8B9, 0x7E97, 0xF8BA, 0x7F89, 0xF8BB, 0x826D, 0xF8BC, 0x8643, + 0xF8BD, 0x8838, 0xF8BE, 0x8837, 0xF8BF, 0x8835, 0xF8C0, 0x884B, 0xF8C1, 0x8B94, 0xF8C2, 0x8B95, 0xF8C3, 0x8E9E, 0xF8C4, 0x8E9F, + 0xF8C5, 0x8EA0, 0xF8C6, 0x8E9D, 0xF8C7, 0x91BE, 0xF8C8, 0x91BD, 0xF8C9, 0x91C2, 0xF8CA, 0x946B, 0xF8CB, 0x9468, 0xF8CC, 0x9469, + 0xF8CD, 0x96E5, 0xF8CE, 0x9746, 0xF8CF, 0x9743, 0xF8D0, 0x9747, 0xF8D1, 0x97C7, 0xF8D2, 0x97E5, 0xF8D3, 0x9A5E, 0xF8D4, 0x9AD5, + 0xF8D5, 0x9B59, 0xF8D6, 0x9C63, 0xF8D7, 0x9C67, 0xF8D8, 0x9C66, 0xF8D9, 0x9C62, 0xF8DA, 0x9C5E, 0xF8DB, 0x9C60, 0xF8DC, 0x9E02, + 0xF8DD, 0x9DFE, 0xF8DE, 0x9E07, 0xF8DF, 0x9E03, 0xF8E0, 0x9E06, 0xF8E1, 0x9E05, 0xF8E2, 0x9E00, 0xF8E3, 0x9E01, 0xF8E4, 0x9E09, + 0xF8E5, 0x9DFF, 0xF8E6, 0x9DFD, 0xF8E7, 0x9E04, 0xF8E8, 0x9EA0, 0xF8E9, 0x9F1E, 0xF8EA, 0x9F46, 0xF8EB, 0x9F74, 0xF8EC, 0x9F75, + 0xF8ED, 0x9F76, 0xF8EE, 0x56D4, 0xF8EF, 0x652E, 0xF8F0, 0x65B8, 0xF8F1, 0x6B18, 0xF8F2, 0x6B19, 0xF8F3, 0x6B17, 0xF8F4, 0x6B1A, + 0xF8F5, 0x7062, 0xF8F6, 0x7226, 0xF8F7, 0x72AA, 0xF8F8, 0x77D8, 0xF8F9, 0x77D9, 0xF8FA, 0x7939, 0xF8FB, 0x7C69, 0xF8FC, 0x7C6B, + 0xF8FD, 0x7CF6, 0xF8FE, 0x7E9A, 0xF940, 0x7E98, 0xF941, 0x7E9B, 0xF942, 0x7E99, 0xF943, 0x81E0, 0xF944, 0x81E1, 0xF945, 0x8646, + 0xF946, 0x8647, 0xF947, 0x8648, 0xF948, 0x8979, 0xF949, 0x897A, 0xF94A, 0x897C, 0xF94B, 0x897B, 0xF94C, 0x89FF, 0xF94D, 0x8B98, + 0xF94E, 0x8B99, 0xF94F, 0x8EA5, 0xF950, 0x8EA4, 0xF951, 0x8EA3, 0xF952, 0x946E, 0xF953, 0x946D, 0xF954, 0x946F, 0xF955, 0x9471, + 0xF956, 0x9473, 0xF957, 0x9749, 0xF958, 0x9872, 0xF959, 0x995F, 0xF95A, 0x9C68, 0xF95B, 0x9C6E, 0xF95C, 0x9C6D, 0xF95D, 0x9E0B, + 0xF95E, 0x9E0D, 0xF95F, 0x9E10, 0xF960, 0x9E0F, 0xF961, 0x9E12, 0xF962, 0x9E11, 0xF963, 0x9EA1, 0xF964, 0x9EF5, 0xF965, 0x9F09, + 0xF966, 0x9F47, 0xF967, 0x9F78, 0xF968, 0x9F7B, 0xF969, 0x9F7A, 0xF96A, 0x9F79, 0xF96B, 0x571E, 0xF96C, 0x7066, 0xF96D, 0x7C6F, + 0xF96E, 0x883C, 0xF96F, 0x8DB2, 0xF970, 0x8EA6, 0xF971, 0x91C3, 0xF972, 0x9474, 0xF973, 0x9478, 0xF974, 0x9476, 0xF975, 0x9475, + 0xF976, 0x9A60, 0xF977, 0x9C74, 0xF978, 0x9C73, 0xF979, 0x9C71, 0xF97A, 0x9C75, 0xF97B, 0x9E14, 0xF97C, 0x9E13, 0xF97D, 0x9EF6, + 0xF97E, 0x9F0A, 0xF9A1, 0x9FA4, 0xF9A2, 0x7068, 0xF9A3, 0x7065, 0xF9A4, 0x7CF7, 0xF9A5, 0x866A, 0xF9A6, 0x883E, 0xF9A7, 0x883D, + 0xF9A8, 0x883F, 0xF9A9, 0x8B9E, 0xF9AA, 0x8C9C, 0xF9AB, 0x8EA9, 0xF9AC, 0x8EC9, 0xF9AD, 0x974B, 0xF9AE, 0x9873, 0xF9AF, 0x9874, + 0xF9B0, 0x98CC, 0xF9B1, 0x9961, 0xF9B2, 0x99AB, 0xF9B3, 0x9A64, 0xF9B4, 0x9A66, 0xF9B5, 0x9A67, 0xF9B6, 0x9B24, 0xF9B7, 0x9E15, + 0xF9B8, 0x9E17, 0xF9B9, 0x9F48, 0xF9BA, 0x6207, 0xF9BB, 0x6B1E, 0xF9BC, 0x7227, 0xF9BD, 0x864C, 0xF9BE, 0x8EA8, 0xF9BF, 0x9482, + 0xF9C0, 0x9480, 0xF9C1, 0x9481, 0xF9C2, 0x9A69, 0xF9C3, 0x9A68, 0xF9C4, 0x9B2E, 0xF9C5, 0x9E19, 0xF9C6, 0x7229, 0xF9C7, 0x864B, + 0xF9C8, 0x8B9F, 0xF9C9, 0x9483, 0xF9CA, 0x9C79, 0xF9CB, 0x9EB7, 0xF9CC, 0x7675, 0xF9CD, 0x9A6B, 0xF9CE, 0x9C7A, 0xF9CF, 0x9E1D, + 0xF9D0, 0x7069, 0xF9D1, 0x706A, 0xF9D2, 0x9EA4, 0xF9D3, 0x9F7E, 0xF9D4, 0x9F49, 0xF9D5, 0x9F98, 0xF9D6, 0x7881, 0xF9D7, 0x92B9, + 0xF9D8, 0x88CF, 0xF9D9, 0x58BB, 0xF9DA, 0x6052, 0xF9DB, 0x7CA7, 0xF9DC, 0x5AFA, 0xF9DD, 0x2554, 0xF9DE, 0x2566, 0xF9DF, 0x2557, + 0xF9E0, 0x2560, 0xF9E1, 0x256C, 0xF9E2, 0x2563, 0xF9E3, 0x255A, 0xF9E4, 0x2569, 0xF9E5, 0x255D, 0xF9E6, 0x2552, 0xF9E7, 0x2564, + 0xF9E8, 0x2555, 0xF9E9, 0x255E, 0xF9EA, 0x256A, 0xF9EB, 0x2561, 0xF9EC, 0x2558, 0xF9ED, 0x2567, 0xF9EE, 0x255B, 0xF9EF, 0x2553, + 0xF9F0, 0x2565, 0xF9F1, 0x2556, 0xF9F2, 0x255F, 0xF9F3, 0x256B, 0xF9F4, 0x2562, 0xF9F5, 0x2559, 0xF9F6, 0x2568, 0xF9F7, 0x255C, + 0xF9F8, 0x2551, 0xF9F9, 0x2550, 0xF9FA, 0x256D, 0xF9FB, 0x256E, 0xF9FC, 0x2570, 0xF9FD, 0x256F, 0xF9FE, 0x2593, 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 437 || FF_CODE_PAGE == 0 +static const WCHAR uc437[] = { /* CP437(U.S.) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 720 || FF_CODE_PAGE == 0 +static const WCHAR uc720[] = { /* CP720(Arabic) to Unicode conversion table */ + 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, + 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 737 || FF_CODE_PAGE == 0 +static const WCHAR uc737[] = { /* CP737(Greek) to Unicode conversion table */ + 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, + 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, + 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, + 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 771 || FF_CODE_PAGE == 0 +static const WCHAR uc771[] = { /* CP771(KBL) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x0104, 0x0105, 0x010C, 0x010D, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0118, 0x0119, 0x0116, 0x0117, 0x012E, 0x012F, 0x0160, 0x0161, 0x0172, 0x0173, 0x016A, 0x016B, 0x017D, 0x017E, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 775 || FF_CODE_PAGE == 0 +static const WCHAR uc775[] = { /* CP775(Baltic) to Unicode conversion table */ + 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, + 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, + 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, + 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 850 || FF_CODE_PAGE == 0 +static const WCHAR uc850[] = { /* CP850(Latin 1) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 852 || FF_CODE_PAGE == 0 +static const WCHAR uc852[] = { /* CP852(Latin 2) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, + 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, + 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 855 || FF_CODE_PAGE == 0 +static const WCHAR uc855[] = { /* CP855(Cyrillic) to Unicode conversion table */ + 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, + 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, + 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, + 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, + 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 857 || FF_CODE_PAGE == 0 +static const WCHAR uc857[] = { /* CP857(Turkish) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 860 || FF_CODE_PAGE == 0 +static const WCHAR uc860[] = { /* CP860(Portuguese) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E3, 0x00E0, 0x00C1, 0x00E7, 0x00EA, 0x00CA, 0x00E8, 0x00CD, 0x00D4, 0x00EC, 0x00C3, 0x00C2, + 0x00C9, 0x00C0, 0x00C8, 0x00F4, 0x00F5, 0x00F2, 0x00DA, 0x00F9, 0x00CC, 0x00D5, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x20A7, 0x00D3, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00D2, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 861 || FF_CODE_PAGE == 0 +static const WCHAR uc861[] = { /* CP861(Icelandic) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00D0, 0x00F0, 0x00DE, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00FE, 0x00FB, 0x00DD, 0x00FD, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00C1, 0x00CD, 0x00D3, 0x00DA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 862 || FF_CODE_PAGE == 0 +static const WCHAR uc862[] = { /* CP862(Hebrew) to Unicode conversion table */ + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 863 || FF_CODE_PAGE == 0 +static const WCHAR uc863[] = { /* CP863(Canadian French) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00C2, 0x00E0, 0x00B6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x2017, 0x00C0, + 0x00C9, 0x00C8, 0x00CA, 0x00F4, 0x00CB, 0x00CF, 0x00FB, 0x00F9, 0x00A4, 0x00D4, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x00DB, 0x0192, + 0x00A6, 0x00B4, 0x00F3, 0x00FA, 0x00A8, 0x00BB, 0x00B3, 0x00AF, 0x00CE, 0x3210, 0x00AC, 0x00BD, 0x00BC, 0x00BE, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2219, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 864 || FF_CODE_PAGE == 0 +static const WCHAR uc864[] = { /* CP864(Arabic) to Unicode conversion table */ + 0x00B0, 0x00B7, 0x2219, 0x221A, 0x2592, 0x2500, 0x2502, 0x253C, 0x2524, 0x252C, 0x251C, 0x2534, 0x2510, 0x250C, 0x2514, 0x2518, + 0x03B2, 0x221E, 0x03C6, 0x00B1, 0x00BD, 0x00BC, 0x2248, 0x00AB, 0x00BB, 0xFEF7, 0xFEF8, 0x0000, 0x0000, 0xFEFB, 0xFEFC, 0x0000, + 0x00A0, 0x00AD, 0xFE82, 0x00A3, 0x00A4, 0xFE84, 0x0000, 0x20AC, 0xFE8E, 0xFE8F, 0xFE95, 0xFE99, 0x060C, 0xFE9D, 0xFEA1, 0xFEA5, + 0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667, 0x0668, 0x0669, 0xFED1, 0x061B, 0xFEB1, 0xFEB5, 0xFEB9, 0x061F, + 0x00A2, 0xFE80, 0xFE81, 0xFE83, 0xFE85, 0xFECA, 0xFE8B, 0xFE8D, 0xFE91, 0xFE93, 0xFE97, 0xFE9B, 0xFE9F, 0xFEA3, 0xFEA7, 0xFEA9, + 0xFEAB, 0xFEAD, 0xFEAF, 0xFEB3, 0xFEB7, 0xFEBB, 0xFEBF, 0xFEC1, 0xFEC5, 0xFECB, 0xFECF, 0x00A6, 0x00AC, 0x00F7, 0x00D7, 0xFEC9, + 0x0640, 0xFED3, 0xFED7, 0xFEDB, 0xFEDF, 0xFEE3, 0xFEE7, 0xFEEB, 0xFEED, 0xFEEF, 0xFEF3, 0xFEBD, 0xFECC, 0xFECE, 0xFECD, 0xFEE1, + 0xFE7D, 0x0651, 0xFEE5, 0xFEE9, 0xFEEC, 0xFEF0, 0xFEF2, 0xFED0, 0xFED5, 0xFEF5, 0xFEF6, 0xFEDD, 0xFED9, 0xFEF1, 0x25A0, 0x0000 +}; +#endif +#if FF_CODE_PAGE == 865 || FF_CODE_PAGE == 0 +static const WCHAR uc865[] = { /* CP865(Nordic) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C5, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00A4, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 866 || FF_CODE_PAGE == 0 +static const WCHAR uc866[] = { /* CP866(Russian) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 869 || FF_CODE_PAGE == 0 +static const WCHAR uc869[] = { /* CP869(Greek 2) to Unicode conversion table */ + 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x0386, 0x00B7, 0x00B7, 0x00AC, 0x00A6, 0x2018, 0x2019, 0x0388, 0x2015, 0x0389, + 0x038A, 0x03AA, 0x038C, 0x00B7, 0x00B7, 0x038E, 0x03AB, 0x00A9, 0x038F, 0x00B2, 0x00B3, 0x03AC, 0x00A3, 0x03AD, 0x03AE, 0x03AF, + 0x03CA, 0x0390, 0x03CC, 0x03CD, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x00BD, 0x0398, 0x0399, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x039A, 0x039B, 0x039C, 0x039D, 0x2563, 0x2551, 0x2557, 0x255D, 0x039E, 0x039F, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0A30, 0x03A1, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x03A3, + 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x2518, 0x250C, 0x2588, 0x2584, 0x03B4, 0x03B5, 0x2580, + 0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x0384, + 0x00AD, 0x00B1, 0x03C5, 0x03C6, 0x03C7, 0x00A7, 0x03C8, 0x0385, 0x00B0, 0x00A8, 0x03C9, 0x03CB, 0x03B0, 0x03CE, 0x25A0, 0x00A0 +}; +#endif + + + + +/*------------------------------------------------------------------------*/ +/* OEM <==> Unicode Conversions for Static Code Page Configuration with */ +/* SBCS Fixed Code Page */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE != 0 && FF_CODE_PAGE < 900 +WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ + DWORD uni, /* UTF-16 encoded character to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + WCHAR c = 0; + const WCHAR* p = CVTBL(uc, FF_CODE_PAGE); + + + if (uni < 0x80) { /* ASCII? */ + c = (WCHAR)uni; + + } else { /* Non-ASCII */ + if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */ + for (c = 0; c < 0x80 && uni != p[c]; c++) ; + c = (c + 0x80) & 0xFF; + } + } + + return c; +} + +WCHAR ff_oem2uni ( /* Returns Unicode character in UTF-16, zero on error */ + WCHAR oem, /* OEM code to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + WCHAR c = 0; + const WCHAR* p = CVTBL(uc, FF_CODE_PAGE); + + + if (oem < 0x80) { /* ASCII? */ + c = oem; + + } else { /* Extended char */ + if (cp == FF_CODE_PAGE) { /* Is it a valid code page? */ + if (oem < 0x100) c = p[oem - 0x80]; + } + } + + return c; +} + +#endif + + + +/*------------------------------------------------------------------------*/ +/* OEM <==> Unicode Conversions for Static Code Page Configuration with */ +/* DBCS Fixed Code Page */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE >= 900 +WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ + DWORD uni, /* UTF-16 encoded character to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR* p; + WCHAR c = 0, uc; + UINT i = 0, n, li, hi; + + + if (uni < 0x80) { /* ASCII? */ + c = (WCHAR)uni; + + } else { /* Non-ASCII */ + if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */ + uc = (WCHAR)uni; + p = CVTBL(uni2oem, FF_CODE_PAGE); + hi = sizeof CVTBL(uni2oem, FF_CODE_PAGE) / 4 - 1; + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (uc == p[i * 2]) break; + if (uc > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + + return c; +} + + +WCHAR ff_oem2uni ( /* Returns Unicode character in UTF-16, zero on error */ + WCHAR oem, /* OEM code to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR* p; + WCHAR c = 0; + UINT i = 0, n, li, hi; + + + if (oem < 0x80) { /* ASCII? */ + c = oem; + + } else { /* Extended char */ + if (cp == FF_CODE_PAGE) { /* Is it valid code page? */ + p = CVTBL(oem2uni, FF_CODE_PAGE); + hi = sizeof CVTBL(oem2uni, FF_CODE_PAGE) / 4 - 1; + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (oem == p[i * 2]) break; + if (oem > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + + return c; +} +#endif + + + +/*------------------------------------------------------------------------*/ +/* OEM <==> Unicode Conversions for Dynamic Code Page Configuration */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE == 0 + +static const WORD cp_code[] = { 437, 720, 737, 771, 775, 850, 852, 855, 857, 860, 861, 862, 863, 864, 865, 866, 869, 0}; +static const WCHAR* const cp_table[] = {uc437, uc720, uc737, uc771, uc775, uc850, uc852, uc855, uc857, uc860, uc861, uc862, uc863, uc864, uc865, uc866, uc869, 0}; + + +WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ + DWORD uni, /* UTF-16 encoded character to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR* p; + WCHAR c = 0, uc; + UINT i, n, li, hi; + + + if (uni < 0x80) { /* ASCII? */ + c = (WCHAR)uni; + + } else { /* Non-ASCII */ + if (uni < 0x10000) { /* Is it in BMP? */ + uc = (WCHAR)uni; + p = 0; + if (cp < 900) { /* SBCS */ + for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get conversion table */ + p = cp_table[i]; + if (p) { /* Is it valid code page ? */ + for (c = 0; c < 0x80 && uc != p[c]; c++) ; /* Find OEM code in the table */ + c = (c + 0x80) & 0xFF; + } + } else { /* DBCS */ + switch (cp) { /* Get conversion table */ + case 932 : p = uni2oem932; hi = sizeof uni2oem932 / 4 - 1; break; + case 936 : p = uni2oem936; hi = sizeof uni2oem936 / 4 - 1; break; + case 949 : p = uni2oem949; hi = sizeof uni2oem949 / 4 - 1; break; + case 950 : p = uni2oem950; hi = sizeof uni2oem950 / 4 - 1; break; + } + if (p) { /* Is it valid code page? */ + li = 0; + for (n = 16; n; n--) { /* Find OEM code */ + i = li + (hi - li) / 2; + if (uc == p[i * 2]) break; + if (uc > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + } + } + + return c; +} + + +WCHAR ff_oem2uni ( /* Returns Unicode character in UTF-16, zero on error */ + WCHAR oem, /* OEM code to be converted (DBC if >=0x100) */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR* p; + WCHAR c = 0; + UINT i, n, li, hi; + + + if (oem < 0x80) { /* ASCII? */ + c = oem; + + } else { /* Extended char */ + p = 0; + if (cp < 900) { /* SBCS */ + for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get table */ + p = cp_table[i]; + if (p) { /* Is it a valid CP ? */ + if (oem < 0x100) c = p[oem - 0x80]; + } + } else { /* DBCS */ + switch (cp) { + case 932 : p = oem2uni932; hi = sizeof oem2uni932 / 4 - 1; break; + case 936 : p = oem2uni936; hi = sizeof oem2uni936 / 4 - 1; break; + case 949 : p = oem2uni949; hi = sizeof oem2uni949 / 4 - 1; break; + case 950 : p = oem2uni950; hi = sizeof oem2uni950 / 4 - 1; break; + } + if (p) { + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (oem == p[i * 2]) break; + if (oem > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + } + + return c; +} +#endif + + + +/*------------------------------------------------------------------------*/ +/* Unicode Up-case Conversion */ +/*------------------------------------------------------------------------*/ + +DWORD ff_wtoupper ( /* Returns up-converted code point */ + DWORD uni /* Unicode code point to be up-converted */ +) +{ + const WORD* p; + WORD uc, bc, nc, cmd; + static const WORD cvt1[] = { /* Compressed up conversion table for U+0000 - U+0FFF */ + /* Basic Latin */ + 0x0061,0x031A, + /* Latin-1 Supplement */ + 0x00E0,0x0317, + 0x00F8,0x0307, + 0x00FF,0x0001,0x0178, + /* Latin Extended-A */ + 0x0100,0x0130, + 0x0132,0x0106, + 0x0139,0x0110, + 0x014A,0x012E, + 0x0179,0x0106, + /* Latin Extended-B */ + 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, + 0x01CD,0x0110, + 0x01DD,0x0001,0x018E, + 0x01DE,0x0112, + 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, + 0x01F8,0x0128, + 0x0222,0x0112, + 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, + 0x0246,0x010A, + /* IPA Extensions */ + 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, + /* Greek, Coptic */ + 0x037B,0x0003,0x03FD,0x03FE,0x03FF, + 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, + 0x03B1,0x0311, + 0x03C2,0x0002,0x03A3,0x03A3, + 0x03C4,0x0308, + 0x03CC,0x0003,0x038C,0x038E,0x038F, + 0x03D8,0x0118, + 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, + /* Cyrillic */ + 0x0430,0x0320, + 0x0450,0x0710, + 0x0460,0x0122, + 0x048A,0x0136, + 0x04C1,0x010E, + 0x04CF,0x0001,0x04C0, + 0x04D0,0x0144, + /* Armenian */ + 0x0561,0x0426, + + 0x0000 /* EOT */ + }; + static const WORD cvt2[] = { /* Compressed up conversion table for U+1000 - U+FFFF */ + /* Phonetic Extensions */ + 0x1D7D,0x0001,0x2C63, + /* Latin Extended Additional */ + 0x1E00,0x0196, + 0x1EA0,0x015A, + /* Greek Extended */ + 0x1F00,0x0608, + 0x1F10,0x0606, + 0x1F20,0x0608, + 0x1F30,0x0608, + 0x1F40,0x0606, + 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, + 0x1F60,0x0608, + 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, + 0x1F80,0x0608, + 0x1F90,0x0608, + 0x1FA0,0x0608, + 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, + 0x1FCC,0x0001,0x1FC3, + 0x1FD0,0x0602, + 0x1FE0,0x0602, + 0x1FE5,0x0001,0x1FEC, + 0x1FF3,0x0001,0x1FFC, + /* Letterlike Symbols */ + 0x214E,0x0001,0x2132, + /* Number forms */ + 0x2170,0x0210, + 0x2184,0x0001,0x2183, + /* Enclosed Alphanumerics */ + 0x24D0,0x051A, + 0x2C30,0x042F, + /* Latin Extended-C */ + 0x2C60,0x0102, + 0x2C67,0x0106, 0x2C75,0x0102, + /* Coptic */ + 0x2C80,0x0164, + /* Georgian Supplement */ + 0x2D00,0x0826, + /* Full-width */ + 0xFF41,0x031A, + + 0x0000 /* EOT */ + }; + + + if (uni < 0x10000) { /* Is it in BMP? */ + uc = (WORD)uni; + p = uc < 0x1000 ? cvt1 : cvt2; + for (;;) { + bc = *p++; /* Get the block base */ + if (bc == 0 || uc < bc) break; /* Not matched? */ + nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ + if (uc < bc + nc) { /* In the block? */ + switch (cmd) { + case 0: uc = p[uc - bc]; break; /* Table conversion */ + case 1: uc -= (uc - bc) & 1; break; /* Case pairs */ + case 2: uc -= 16; break; /* Shift -16 */ + case 3: uc -= 32; break; /* Shift -32 */ + case 4: uc -= 48; break; /* Shift -48 */ + case 5: uc -= 26; break; /* Shift -26 */ + case 6: uc += 8; break; /* Shift +8 */ + case 7: uc -= 80; break; /* Shift -80 */ + case 8: uc -= 0x1C60; break; /* Shift -0x1C60 */ + } + break; + } + if (cmd == 0) p += nc; /* Skip table if needed */ + } + uni = uc; + } + + return uni; +} + + +#endif /* #if FF_USE_LFN != 0 */ diff --git a/Project/GateWay/source/Module/FatFS/source/sd_diskio.c b/Project/GateWay/source/Module/FatFS/source/sd_diskio.c new file mode 100644 index 0000000..eb5a639 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/source/sd_diskio.c @@ -0,0 +1,204 @@ +#include "bsp.h" +#include "sd_diskio.h" + + +#define SDIOC_SD_UINT SDIOC_UNIT +#define SDIOC_SD_CLK (PWC_FCG1_SDIOC1) +/* Local pre-processor symbols/macros ('#define') */ + + +/* Block size is 512 bytes */ +#define SD_DEFAULT_BLOCK_SIZE (512U) +/* SD read/write timeout time */ +#define SD_RW_TIMEOUT_TIME (30000UL) +/* Local variable definitions ('static') */ + +static volatile DSTATUS SdStat = (DSTATUS)STA_NOINIT; + +/** +* @brief Get SD card insert status. +* @param None +* @retval An en_flag_status_t enumeration value: +* - Set: SD card inserted +* - Reset: No SD card insert +*/ +//static en_flag_status_t SDCard_GetInsertStatus(void) +//{ +//// en_flag_status_t enFlagSta = Set; +//// /* Check SD card detect pin */ +//// if (0U != BSP_IO_ReadPortPin(EIO_PORT0, EIO_SDIC1_CD)) +//// { +//// enFlagSta = Reset; +//// } +//// return enFlagSta; +// return Set; +//} + +/** +* @brief SD card configuration. +* @param None +* @retval An en_result_t enumeration value: +* - Ok: Configuration success +* - Error: Configuration failed +*/ +static en_result_t SDCard_Config(void) +{ + return SdioInit(); +} + +/** +* @brief Get SD card state. +* @param None +* @retval An en_result_t enumeration value: +* - Ok: Data transfer is acting +* - Error: No data transfer is acting +*/ +static en_result_t SDCard_GetCardTransState(void) +{ + en_result_t enRet; + en_sd_card_state_t enCardState; + + enRet = SD_GetCardState(&stcSdhandle, &enCardState); + + if (Ok == enRet) { + if (SD_CARD_STAT_TRANS == enCardState) { + enRet = Ok; + } + } + + return enRet; +} + +/** +* @brief Check the SD card status. +* @param lun: Not used +* @retval DSTATUS: Operation status +*/ +static DSTATUS SD_CheckStatus(BYTE lun) +{ + SdStat = (DSTATUS)STA_NOINIT; + en_result_t enRet; + + enRet = SDCard_GetCardTransState(); + if (Ok == enRet) { + SdStat &= (DSTATUS)(~(DSTATUS)STA_NOINIT); + } + return SdStat; +} + +/** +* @brief Gets Disk Status +* @param lun: Not used +* @retval DSTATUS: Operation status +*/ +DSTATUS SD_Status(BYTE lun) +{ + return SD_CheckStatus(lun); +} + +/** +* @brief Initializes a Drive + * @param lun: Not used +* @retval DSTATUS: Operation status +*/ +DSTATUS SD_Initialize(BYTE lun) +{ + SdStat = (DSTATUS)STA_NOINIT; + if (Ok == SDCard_Config()) { + SdStat = SD_CheckStatus(lun); + } + return SdStat; +} + +/** +* @brief Reads Sector(s) +* @param lun: Not used +* @param buff: Pointer to data buffer used to store read data +* @param sector: Sector address (LBA) +* @param count: Number of sectors to read (1..128) +* @retval DRESULT: Operation result +*/ +DRESULT SD_Read(BYTE lun, BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + + if (Ok == SDCARD_ReadBlocks(&stcSdhandle, (uint32_t)sector, (uint16_t)count, (uint8_t *)buff, SD_RW_TIMEOUT_TIME)) { + /* Wait until the read operation is finished */ + while (Ok != SDCard_GetCardTransState()){ + } + res = RES_OK; + } + + return res; +} + +/** +* @brief Writes Sector(s) +* @param lun: Not used +* @param buff: Pointer to data to be written +* @param sector: Sector address (LBA) + * @param count: Number of sectors to write (1..128) +* @retval DRESULT: Operation result +*/ +DRESULT SD_Write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + if (Ok == SDCARD_WriteBlocks(&stcSdhandle, (uint32_t)sector, (uint16_t)count, (uint8_t *)buff, SD_RW_TIMEOUT_TIME)) { + /* Wait until the Write operation is finished */ + while (Ok != SDCard_GetCardTransState()) { + } + res = RES_OK; + } + return res; +} + +/** +* @brief I/O control operation +* @param lun: Not used +* @param cmd: Control code +* @param buff: Pointer to buffer used to send/receive data +* @retval DRESULT: Operation result +*/ +DRESULT SD_Ioctl(BYTE lun, BYTE cmd, void *buff) +{ + DRESULT res; + //stc_sd_card_info_t stcCardInfo; + if (0U != (SdStat & (DSTATUS)STA_NOINIT)) { + res = RES_NOTRDY; + } + else + { + switch (cmd) { + /* Make sure that no pending write process */ + case CTRL_SYNC : + res = RES_OK; + break; + + /* Get number of sectors on the disk (DWORD) */ + case GET_SECTOR_COUNT : + SDCARD_GetCardCSD(&stcSdhandle); + *(DWORD*)buff =stcSdhandle.stcSdCardInfo.u32LogBlockNbr; + res = RES_OK; + break; + + /* Get R/W sector size (WORD) */ + case GET_SECTOR_SIZE : + SDCARD_GetCardCSD(&stcSdhandle); + *(WORD*)buff = (uint16_t)stcSdhandle.stcSdCardInfo.u32LogBlockSize; + res = RES_OK; + break; + + /* Get erase block size in unit of sector (DWORD) */ + case GET_BLOCK_SIZE : + SDCARD_GetCardCSD(&stcSdhandle); + *(DWORD*)buff = stcSdhandle.stcSdCardInfo.u32LogBlockSize / SD_DEFAULT_BLOCK_SIZE; + res = RES_OK; + break; + + default: + res = RES_PARERR; + break; + } + } + return res; +} diff --git a/Project/GateWay/source/Module/FatFS/source/sd_diskio.h b/Project/GateWay/source/Module/FatFS/source/sd_diskio.h new file mode 100644 index 0000000..0aec272 --- /dev/null +++ b/Project/GateWay/source/Module/FatFS/source/sd_diskio.h @@ -0,0 +1,26 @@ +#ifndef __SD_DISKIO__ +#define __SD_DISKIO__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Include files */ +#include "hc32_common.h" +#include "ff.h" +#include "diskio.h" + +/* Global function prototypes (definition in C source) */ +DSTATUS SD_Status (BYTE); +DSTATUS SD_Initialize (BYTE); +DRESULT SD_Read (BYTE, BYTE*, DWORD, UINT); +DRESULT SD_Write (BYTE, const BYTE*, DWORD, UINT); +DRESULT SD_Ioctl (BYTE, BYTE, void*); + +#ifdef __cplusplus +} +#endif + +#endif /* __SD_DISKIO__ */ diff --git a/Project/GateWay/source/Module/SDCard/sd_card.c b/Project/GateWay/source/Module/SDCard/sd_card.c new file mode 100644 index 0000000..02945a0 --- /dev/null +++ b/Project/GateWay/source/Module/SDCard/sd_card.c @@ -0,0 +1,1319 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file sd_card.c + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-15 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "sdmmc_cmd.h" +#include "sd_card.h" + +/** + ******************************************************************************* + ** \addtogroup SdiocGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +typedef enum en_sd_card_type +{ + SdCardSdsc = 0u, + SdCardSdhcSdxc = 1u, + SdCardSecured = 3u, +} en_sd_card_type_t; + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Card Command Class supported. */ +#define SDMMC_CARD_CCCC_ERASE (0x00000020u) + +/*!< Card locked */ +#define SDMMC_CARD_LOCKED (0x02000000u) + +/*!< Voltage trial times */ +#define SD_CARD_MAX_VOLT_TRIAL (0x0000FFFFu) + +/*!< High speed */ +#define SD_CHECK_FUNCTION_HIGH_SPEED (0x00FFFF01u) +#define SD_SET_FUNCTION_HIGH_SPEED (0x80FFFF01u) + +/*!< Block size is 512 bytes */ +#define SD_CARD_BLOCK_SIZE (512u) + +/*!< SDIOC buffer align size */ +#define SDIOC_BUF_ALIGN_SIZE (4ul) + +/*!< Log Block Number for 2G bytes Cards */ +#define SD_CARD_CAPACITY (0x400000u) + +/*!< Card power up status bit (busy) */ +#define SD_CARD_OCR_BUSY (0x80000000ul) + +#define SD_CARD_OP_NONE (0x00000000u) /*!< None */ +#define SD_CARD_OP_READ_SINGLE_BLOCK (0x00000001u) /*!< Read single block operation */ +#define SD_CARD_OP_READ_MULTIPLE_BLOCK (0x00000002u) /*!< Read multiple blocks operation */ +#define SD_CARD_OP_WRITE_SINGLE_BLOCK (0x00000010u) /*!< Write single block operation */ +#define SD_CARD_OP_WRITE_MULTIPLE_BLOCK (0x00000020u) /*!< Write multiple blocks operation */ +#define SD_CARD_OP_IT (0x00000008u) /*!< Process in Interrupt mode */ +#define SD_CARD_OP_DMA (0x00000080u) /*!< Process in DMA mode */ + +/*!< the SD card relative card address. */ +#define RelCardAddress(handle) ((handle)->stcSdCardInfo.u32RelCardAddr) +#define IsCardProgramming(handle) ((SdmmcCardStatePgm == (handle)->stcCardStatus.CURRENT_STATE) ? true : false) +#define IsCardReadyForData(handle) ((1u == (handle)->stcCardStatus.READY_FOR_DATA) ? true : false) + +#define IS_DMA_CFG_VALID(handle) \ +( (NULL != (handle)->pstcDmaInitCfg) && \ + (NULL != (handle)->pstcDmaInitCfg->DMAx)) + +/*!< the SD card use DMA unit && channel. */ +#define DMA_Unit(handle) ((handle)->pstcDmaInitCfg->DMAx) +#define DMA_CH(handle) ((handle)->pstcDmaInitCfg->enDmaCh) + +/*!< Parameter valid check for buffer address. */ +#define IS_VALID_TRANSFER_BUF_ALIGN(x) (!((SDIOC_BUF_ALIGN_SIZE-1ul) & ((uint32_t)(x)))) + +/*!< Parameter valid check for SDIOC command value. */ +#define IS_VALID_TRANSFER_BUF_LEN(x) (!((SD_CARD_BLOCK_SIZE - 1u) & (x))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static en_result_t SdCardInitSd(stc_sd_handle_t *handle); +static en_result_t SdCardPowerON(stc_sd_handle_t *handle); +static en_result_t SdCardInitHost(const stc_sd_handle_t *handle); +static en_result_t SdCardSetSpeed(stc_sd_handle_t *handle); +static en_result_t SdCardSetBusWidth(stc_sd_handle_t *handle); +static en_result_t SdCardCheckReayForData(stc_sd_handle_t *handle, + uint32_t u32Timeout); +static en_result_t DmaSdiocTxConfig(M4_DMA_TypeDef* DMAx, + en_dma_channel_t enCh, + M4_SDIOC_TypeDef *SDIOCx, + uint8_t *pu8TxBuf, + uint16_t u16len); +static en_result_t DmaSdiocRxConfig(M4_DMA_TypeDef* DMAx, + en_dma_channel_t enCh, + M4_SDIOC_TypeDef *SDIOCx, + uint8_t *pu8RxBuf, + uint16_t u16len); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize SD. + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] pstcInitCfg The pointer of SD configure structure + ** \arg This parameter detail refer @ref stc_sdcard_init_t + ** + ** \retval Ok Initialize SD successfully. + ** \retval Error Initialize SD unsuccessfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - handle == NULL + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t SDCARD_Init(stc_sd_handle_t *handle, + const stc_sdcard_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != handle) && (NULL != pstcInitCfg)) + { + handle->pstcCardInitCfg = pstcInitCfg; + + enRet = SdCardInitHost(handle); + if (enRet != Ok) + { + return enRet; + } + + enRet = SdCardPowerON(handle); + if (enRet != Ok) + { + return enRet; + } + + enRet = SdCardInitSd(handle); + if (enRet != Ok) + { + return enRet; + } + + enRet = SdCardSetBusWidth(handle); + if (enRet != Ok) + { + return enRet; + } + + enRet = SdCardSetSpeed(handle); + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set SD Card device Read/Write mode. + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] enDevMode Read/Write mode + ** \arg SdCardDmaMode DMA mode transfer + ** \arg SdCardPollingMode Polling mode transfer + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter handle pointer is NULL. + ** + ******************************************************************************/ +en_result_t SDCARD_SetDeviceMode(stc_sd_handle_t *handle, + en_sd_card_device_mode_t enDevMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != handle) + { + handle->enDevMode = enDevMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get SD Card device Read/Write mode. + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval SdCardDmaMode DMA mode transfer + ** \retval SdCardPollingMode Polling mode transfer + ** + ******************************************************************************/ +en_sd_card_device_mode_t SDCARD_GetDeviceMode(const stc_sd_handle_t *handle) +{ + DDL_ASSERT(NULL != handle); + + return handle->enDevMode; +} + +/** + ******************************************************************************* + ** \brief Get Card specified Data information. + ** + ** \param [in] handle Pointer to SD Card handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok Get successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - handle == NULL + ** + ******************************************************************************/ +en_result_t SDCARD_GetCardCSD(stc_sd_handle_t *handle) +{ + uint32_t u32Csize = 0ul; + uint32_t u32NumSector = 0ul; + uint32_t u32CsizeMulti = 0ul; + stc_sdcard_csd_v1_t *pstcCsdSd = NULL; + stc_sdcard_csd_v2_t *pstcCsdSdHc = NULL; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != handle) + { + /* High Capacity CSD Version 2.0*/ + if ((handle->CSD[3] & 0x00FF0000ul) == 0x00400000ul) + { + pstcCsdSdHc = (stc_sdcard_csd_v2_t *)&handle->CSD[0]; + u32Csize = ((unsigned int)pstcCsdSdHc->C_SIZE3 << 16ul) + + ((unsigned int)pstcCsdSdHc->C_SIZE2 << 8ul) + + pstcCsdSdHc->C_SIZE1; + + u32NumSector = (u32Csize + 1ul) << 10ul; + + handle->stcSdCardInfo.u32Class = (((uint32_t)pstcCsdSdHc->CCC2) << 4u) | ((uint32_t)pstcCsdSdHc->CCC1); + handle->stcSdCardInfo.u32BlockSize = 1ul << (pstcCsdSdHc->READ_BL_LEN); + } + else /* Standard Capacity CSD Version 1.xx */ + { + pstcCsdSd = (stc_sdcard_csd_v1_t *)&handle->CSD[0]; + + u32Csize = ((unsigned int)pstcCsdSd->C_SIZE3 << 10) + + ((unsigned int)pstcCsdSd->C_SIZE2 << 2) + + pstcCsdSd->C_SIZE1; + + u32CsizeMulti = ((uint32_t)(pstcCsdSd->C_SIZE_MULTI2) << 1) + (uint32_t)pstcCsdSd->C_SIZE_MULTI1; + u32NumSector = (u32Csize + 1ul) << (u32CsizeMulti + 2ul); + + if (pstcCsdSd->READ_BL_LEN == 0x0Au) + { + u32NumSector *= 2ul; + } + else if (pstcCsdSd->READ_BL_LEN == 0x0Bu) + { + u32NumSector *= 4ul; + } + else + { + /* Do nothing: only avoid MISRA warning */ + } + + handle->stcSdCardInfo.u32Class = ((uint32_t)pstcCsdSd->CCC2 << 4) | (uint32_t)pstcCsdSd->CCC1; + handle->stcSdCardInfo.u32BlockSize = 1ul << (pstcCsdSd->READ_BL_LEN); + } + + handle->stcSdCardInfo.u32BlockNbr = u32NumSector; + handle->stcSdCardInfo.u32LogBlockNbr = (handle->stcSdCardInfo.u32BlockNbr) * ((handle->stcSdCardInfo.u32BlockSize) / SD_CARD_BLOCK_SIZE); + handle->stcSdCardInfo.u32LogBlockSize = SD_CARD_BLOCK_SIZE; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Erase SD card blocks. + ** + ** \param [in] handle Pointer to SD Card handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] u32BlkStartAddr Block start address + ** \param [in] u32BlkEndAddr Block end address + ** \param [in] u32Timeout Erase timeout value + ** + ** \retval Ok Erase successfully. + ** \retval Error Erase unsuccessfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - handle == NULL + ** - u32BlkStartAddr out of range + ** - u32BlkEndAddr out of range + ** + ******************************************************************************/ +en_result_t SDCARD_Erase(stc_sd_handle_t *handle, + uint32_t u32BlkStartAddr, + uint32_t u32BlkEndAddr, + uint32_t u32Timeout) +{ + en_result_t enCmdRet = Error; + __IO uint32_t u32TimeCount = u32Timeout * (SystemCoreClock / 8u / 1000u); + + if ((NULL == handle) || + (u32BlkStartAddr > u32BlkEndAddr) || + (u32BlkEndAddr > handle->stcSdCardInfo.u32BlockNbr)) + { + return ErrorInvalidParameter; + } + + /* Check if the card command class supports erase command */ + if (!(handle->stcSdCardInfo.u32Class & SDMMC_CARD_CCCC_ERASE)) + { + return ErrorAccessRights; + } + + if ((SDIOC_GetResponse(handle->SDIOCx, SdiocRegResp01) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + return ErrorAccessRights; + } + + /* Check the Card capacity in term of Logical number of blocks */ + if (handle->stcSdCardInfo.u32CardType != SdCardSdhcSdxc) + { + u32BlkStartAddr *= SD_CARD_BLOCK_SIZE; + u32BlkEndAddr *= SD_CARD_BLOCK_SIZE; + } + + /* Send CMD35 ERASE_GRP_START with argument as address */ + enCmdRet = SDMMC_Cmd32_EraseWrBlkStart(handle->SDIOCx, u32BlkStartAddr, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + /* Send CMD36 ERASE_GRP_END with argument as address */ + enCmdRet = SDMMC_Cmd33_EraseWrBlkEnd(handle->SDIOCx, u32BlkEndAddr, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + enCmdRet = SDMMC_Cmd38_Erase(handle->SDIOCx, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + enCmdRet = SdCardCheckReayForData(handle, u32TimeCount); + + return enCmdRet; +} + +/** + ******************************************************************************* + ** \brief Read block data from SD card + ** + ** \param [in] handle Pointer to SD Card handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] u32BlockAddr Block address + ** \param [in] u16BlockCnt Block Count + ** \param [in] pu8Data Pointer to buffer which will store SD Card data. + ** \param [in] u32Timeout Transfer timeout + ** + ** \retval Ok Read successfully. + ** \retval Error Read unsuccessfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - handle == NULL + ** - pu8Data == NULL + ** - u16BlockCnt == 0 + ** - (u32BlockAddr + u16BlockCnt) out of range + ** + ******************************************************************************/ +en_result_t SDCARD_ReadBlocks(stc_sd_handle_t *handle, + uint32_t u32BlockAddr, + uint16_t u16BlockCnt, + uint8_t *pu8Data, + uint32_t u32Timeout) +{ + en_result_t enCmdRet; + stc_sdioc_data_cfg_t stcDataCfg; + uint8_t *pu8TempBuf = (uint8_t *)pu8Data; + uint32_t u32TimeCount = u32Timeout * (SystemCoreClock / 8u / 1000u); + __IO uint32_t u32Count = u32TimeCount; + en_sd_card_device_mode_t enDeviceMode = SDCARD_GetDeviceMode(handle); + en_flag_status_t enStatus = Reset; + en_flag_status_t enIrqFlag = Reset; + + if (NULL == handle) + { + return ErrorInvalidParameter; + } + + if ((NULL == pu8Data) || (0u == u16BlockCnt)) + { + handle->u32ErrorCode |= SD_CARD_ERROR_PARAM; + return ErrorInvalidParameter; + } + + handle->u32ErrorCode = SD_CARD_ERROR_NONE; + + if ((u32BlockAddr + u16BlockCnt) > (handle->stcSdCardInfo.u32LogBlockNbr)) + { + handle->u32ErrorCode |= SD_CARD_ERROR_ADDR_OUT_OF_RANGE; + return ErrorInvalidParameter; + } + + if (handle->stcSdCardInfo.u32CardType != SdCardSdhcSdxc) + { + u32BlockAddr *= SD_CARD_BLOCK_SIZE; + } + + /* Set Block Size for Card */ + enCmdRet = SDMMC_Cmd16_SetBlockLength(handle->SDIOCx, SD_CARD_BLOCK_SIZE, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + stcDataCfg.u16BlkCnt = u16BlockCnt; + stcDataCfg.u16BlkSize = SD_CARD_BLOCK_SIZE; + stcDataCfg.enDataTimeOut = SdiocDtoSdclk_2_27; + stcDataCfg.enTransferDir = SdiocTransferToHost; + stcDataCfg.enAutoCmd12Enable = (u16BlockCnt > 1u) ? Enable:Disable; + stcDataCfg.enTransferMode = (u16BlockCnt > 1u) ? SdiocTransferMultiple:SdiocTransferSingle; + enCmdRet = SDIOC_ConfigData(handle->SDIOCx, &stcDataCfg); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + if (enDeviceMode == SdCardDmaMode) + { + if (IS_DMA_CFG_VALID(handle)) + { + DmaSdiocRxConfig(DMA_Unit(handle), DMA_CH(handle), handle->SDIOCx, pu8TempBuf, u16BlockCnt * SD_CARD_BLOCK_SIZE); + } + } + + /* Read block(s) in polling mode */ + if (1u == u16BlockCnt) + { + handle->Context = SD_CARD_OP_READ_SINGLE_BLOCK; + /* Read Single Block command */ + enCmdRet = SDMMC_Cmd17_ReadSingleBlock(handle->SDIOCx, u32BlockAddr, (uint32_t *)(&handle->stcCardStatus)); + } + else + { + handle->Context = SD_CARD_OP_READ_MULTIPLE_BLOCK; + /* Read Multi Block command */ + enCmdRet = SDMMC_Cmd18_ReadMultipleBlock(handle->SDIOCx, u32BlockAddr, (uint32_t *)(&handle->stcCardStatus)); + } + + if (enCmdRet != Ok) + { + return enCmdRet; + } + + if (SdCardPollingMode == enDeviceMode) + { + /* Poll on SDIO flags */ + while (u16BlockCnt) + { + enStatus = SDIOC_GetStatus(handle->SDIOCx, SdiocBufferReadEnble); + enIrqFlag = SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocBufferReadReady); + if ((Set == enStatus) && (Set == enIrqFlag)) + { + SDIOC_ReadBuffer(handle->SDIOCx, pu8TempBuf, SD_CARD_BLOCK_SIZE); + + u16BlockCnt--; + u32Count = u32TimeCount; + pu8TempBuf += SD_CARD_BLOCK_SIZE; + } + + if (0ul == u32Count--) + { + return ErrorTimeout; + } + } + } + + for (u32Count = u32TimeCount; u32Count > 0ul; u32Count--) + { + if (Set == SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete)) + { + break; + } + } + + if (0ul == u32Count) + { + return ErrorTimeout; + } + else + { + SDIOC_ClearNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete); + } + + /* check whether Data transfer stops */ + if (Set == SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocErrorInt)) + { + enCmdRet = Error; + } + + return enCmdRet; +} + +/** + ******************************************************************************* + ** \brief Write block data to SD card + ** + ** \param [in] handle Pointer to SD Card handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] u32BlockAddr Block address + ** \param [in] u16BlockCnt Block Count + ** \param [in] pu8Data Pointer to buffer which contains data to be send to SD Card. + ** \param [in] u32Timeout Transfer timeout + ** + ** \retval Ok Write successfully. + ** \retval Error Write unsuccessfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - handle == NULL + ** - pu8Data == NULL + ** - u16BlockCnt == 0 + ** - (u32BlockAddr + u16BlockCnt) out of range + ** + ******************************************************************************/ +en_result_t SDCARD_WriteBlocks(stc_sd_handle_t *handle, + uint32_t u32BlockAddr, + uint16_t u16BlockCnt, + uint8_t *pu8Data, + uint32_t u32Timeout) +{ + en_result_t enCmdRet; + stc_sdioc_data_cfg_t stcDataCfg; + uint8_t *pu8TempBuf = (uint8_t *)pu8Data; + uint32_t u32TimeCount = u32Timeout * (SystemCoreClock / 50ul / 1000ul); + __IO uint32_t u32Count = u32TimeCount; + en_sd_card_device_mode_t enDeviceMode = SDCARD_GetDeviceMode(handle); + en_flag_status_t enStatus = Reset; + en_flag_status_t enIrqFlag = Reset; + + if (NULL == handle) + { + return ErrorInvalidParameter; + } + + if ((NULL == pu8Data) || (0u == u16BlockCnt)) + { + handle->u32ErrorCode |= SD_CARD_ERROR_PARAM; + return ErrorInvalidParameter; + } + + handle->u32ErrorCode = SD_CARD_ERROR_NONE; + + if ((u32BlockAddr + u16BlockCnt) > (handle->stcSdCardInfo.u32LogBlockNbr)) + { + handle->u32ErrorCode |= SD_CARD_ERROR_ADDR_OUT_OF_RANGE; + return ErrorInvalidParameter; + } + + /* Set Block Size for Card */ + enCmdRet = SDMMC_Cmd16_SetBlockLength(handle->SDIOCx, SD_CARD_BLOCK_SIZE, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + stcDataCfg.u16BlkCnt = u16BlockCnt; + stcDataCfg.u16BlkSize = SD_CARD_BLOCK_SIZE; + stcDataCfg.enDataTimeOut = SdiocDtoSdclk_2_27; + stcDataCfg.enTransferDir = SdiocTransferToCard; + stcDataCfg.enAutoCmd12Enable = (u16BlockCnt > 1u) ? Enable:Disable; + stcDataCfg.enTransferMode = (u16BlockCnt > 1u) ? SdiocTransferMultiple:SdiocTransferSingle; + enCmdRet = SDIOC_ConfigData(handle->SDIOCx, &stcDataCfg); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + if (handle->stcSdCardInfo.u32CardType != SdCardSdhcSdxc) + { + u32BlockAddr *= SD_CARD_BLOCK_SIZE; + } + + if (enDeviceMode == SdCardDmaMode) + { + if (IS_DMA_CFG_VALID(handle)) + { + DmaSdiocTxConfig(DMA_Unit(handle), DMA_CH(handle), handle->SDIOCx, pu8TempBuf, u16BlockCnt * SD_CARD_BLOCK_SIZE); + } + } + + /* Write block(s) in polling mode */ + if (1u == u16BlockCnt) + { + /* Read Single Block command */ + enCmdRet = SDMMC_Cmd24_WriteSingleBlock(handle->SDIOCx, u32BlockAddr, (uint32_t *)(&handle->stcCardStatus)); + } + else + { + /* Read Multi Block command */ + enCmdRet = SDMMC_Cmd25_WriteMultipleBlock(handle->SDIOCx, u32BlockAddr, (uint32_t *)(&handle->stcCardStatus)); + } + + if (enCmdRet != Ok) + { + return enCmdRet; + } + + if (SdCardPollingMode == enDeviceMode) + { + /* Poll on SDIO flags */ + while (u16BlockCnt) + { + enStatus = SDIOC_GetStatus(handle->SDIOCx, SdiocBufferWriteEnble); + enIrqFlag = SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocBufferWriteReady); + if ((Set == enStatus) && (Set == enIrqFlag)) + { + /* Write data to SDIO Tx Buffer */ + SDIOC_WriteBuffer(handle->SDIOCx, pu8TempBuf, SD_CARD_BLOCK_SIZE); + + u16BlockCnt--; + u32Count = u32TimeCount; + pu8TempBuf += SD_CARD_BLOCK_SIZE; + } + + if (u32Count-- == 0ul) + { + return ErrorTimeout; + } + } + } + + for (u32Count = u32TimeCount; u32Count > 0ul; u32Count--) + { + enStatus = SDIOC_GetStatus(handle->SDIOCx, SdiocData0PinLvl); + enIrqFlag = SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete); + if ((Set == enStatus) && (Set == enIrqFlag)) + { + break; + } + } + + if (0u == u32Count) + { + return ErrorTimeout; + } + else + { + SDIOC_ClearNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete); + } + + enCmdRet = SdCardCheckReayForData(handle, u32TimeCount); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + /* check whether Data transfer stops */ + if(Set == SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocErrorInt)) + { + return Error; + } + + SDIOC_ClearNormalIrqFlag(handle->SDIOCx, SdiocBufferWriteReady); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set SD bus width. + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok Set SD bus width successfully. + ** \retval Error Set SD bus width unsuccessfully. + ** \retval ErrorInvalidParameter If one of following conditions matches: + ** - NULL == pstcCfg + ** - enBusWidth is invalid. + ** - Other invalid configuration + ** + ******************************************************************************/ +static en_result_t SdCardSetBusWidth(stc_sd_handle_t *handle) +{ + uint32_t u32CmdArg = 0ul; + en_result_t enCmdRet = Ok; + + if ((NULL == handle) || (NULL == handle->pstcCardInitCfg)) + { + return ErrorInvalidParameter; + } + + switch (handle->pstcCardInitCfg->enBusWidth) + { + case SdiocBusWidth1Bit: + u32CmdArg = 0u; + break; + case SdiocBusWidth4Bit: + u32CmdArg = 2u; + break; + default: + enCmdRet = ErrorInvalidParameter; + break; + } + + if (Ok != enCmdRet) + { + return enCmdRet; + } + + enCmdRet = SDMMC_Cmd55_AppCmd(handle->SDIOCx, (RelCardAddress(handle) << 16u), (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + enCmdRet = SDMMC_Acmd6_SetBusWidth(handle->SDIOCx, u32CmdArg, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + enCmdRet = SDIOC_SetBusWidth(handle->SDIOCx, handle->pstcCardInitCfg->enBusWidth); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set SD high speed mode. + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok Set SD bus width successfully. + ** \retval Ok Set SD bus width unsuccessfully. + ** \retval ErrorInvalidParameter If one of following conditions matches: + ** - NULL == pstcCfg + ** - u32Freq is invalid. + ** + ******************************************************************************/ +static en_result_t SdCardSetSpeed(stc_sd_handle_t *handle) +{ + uint8_t au8TempBuf[64] = {0}; + uint32_t u32TimeCount = 2000 * (SystemCoreClock / 8u / 1000u); + __IO uint32_t u32Count = u32TimeCount; + en_flag_status_t enStatus = Reset; + en_flag_status_t enIrqFlag = Reset; + + en_result_t enCmdRet = ErrorInvalidParameter; + stc_sdioc_data_cfg_t stcDataCfg; + uint32_t u32Arg = SD_SET_FUNCTION_HIGH_SPEED; + + if ((NULL != handle) && (NULL != handle->pstcCardInitCfg)) + { + enCmdRet = Ok; + if (SdiocHighSpeedMode == handle->pstcCardInitCfg->enSpeedMode) + { + /* Set Block Size for Card */ + enCmdRet = SDMMC_Cmd16_SetBlockLength(handle->SDIOCx, 64u, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet == Ok) + { + stcDataCfg.u16BlkCnt = 1u; + stcDataCfg.u16BlkSize = 64u; + stcDataCfg.enDataTimeOut = SdiocDtoSdclk_2_27; + stcDataCfg.enTransferDir = SdiocTransferToHost; + stcDataCfg.enAutoCmd12Enable = Disable; + stcDataCfg.enTransferMode = SdiocTransferSingle; + enCmdRet = SDIOC_ConfigData(handle->SDIOCx, &stcDataCfg); + if (enCmdRet == Ok) + { + enCmdRet = SDMMC_Cmd6_SwitchFunc(handle->SDIOCx, u32Arg, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet == Ok) + { + while (u32Count--) + { + enStatus = SDIOC_GetStatus(handle->SDIOCx, SdiocBufferReadEnble); + enIrqFlag = SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocBufferReadReady); + if ((Set == enStatus) && (Set == enIrqFlag)) + { + SDIOC_ReadBuffer(handle->SDIOCx, au8TempBuf, sizeof(au8TempBuf)); + break; + } + } + + if (0ul == u32Count) + { + return ErrorTimeout; + } + + u32Count = u32TimeCount; + while (u32Count--) + { + if (Set == SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete)) + { + SDIOC_ClearNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete); + break; + } + } + + if (0ul == u32Count) + { + return ErrorTimeout; + } + + /* Check whether switch function with error or transfer error occur */ + if ((!(au8TempBuf[16] & 0x01)) || + (Set == SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocErrorInt))) + { + enCmdRet = Error; + } + } + } + } + } + + if (enCmdRet == Ok) + { + SDIOC_SetSpeedMode(handle->SDIOCx, handle->pstcCardInitCfg->enSpeedMode); + + enCmdRet = SDIOC_SetClk(handle->SDIOCx, handle->pstcCardInitCfg->enClkFreq); + } + } + + return enCmdRet; +} + +/** + ******************************************************************************* + ** \brief Initialize SDIO Host + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok SDIO host initialized successfully + ** \retval ErrorInvalidParameter If one of following conditions matches: + ** - NULL == pstcInitCfg + ** - Other invalid configuration + ** + ******************************************************************************/ +static en_result_t SdCardInitHost(const stc_sd_handle_t *handle) +{ + en_result_t enRet = Ok; + + if ((NULL == handle) || (NULL == handle->pstcCardInitCfg)) + { + return ErrorInvalidParameter; + } + + /* Enable SD clock supply */ + if (M4_SDIOC1 == handle->SDIOCx) + { + PWC_Fcg1PeriphClockCmd(PWC_FCG1_PERIPH_SDIOC1, Enable); + } + else if (M4_SDIOC2 == handle->SDIOCx) + { + PWC_Fcg1PeriphClockCmd(PWC_FCG1_PERIPH_SDIOC2, Enable); + } + else + { + return ErrorInvalidParameter; + } + + /* Set mode: SD */ + SDIOC_SetMode(handle->SDIOCx, SdiocModeSD); + + enRet = SDIOC_Init(handle->SDIOCx, handle->pstcCardInitCfg->pstcInitCfg); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize SD bus + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok SDIO bus cmd operate successfully. + ** \retval Error SDIO bus cmd operate unsuccessfully. + ** \retval ErrorInvalidParameter If one of following conditions matches: + ** - NULL == pstcCfg + ** - Other invalid configuration + ** + ******************************************************************************/ +static en_result_t SdCardInitSd(stc_sd_handle_t *handle) +{ + en_result_t enCmdRet = Ok; + + if(NULL == handle) + { + return ErrorInvalidParameter; + } + + if (handle->stcSdCardInfo.u32CardType != SdCardSecured) + { + /* Send CMD2 ALL_SEND_CID */ + enCmdRet = SDMMC_Cmd2_AllSendCID(handle->SDIOCx, handle->CID); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* SD Card publishes its RCA. */ + enCmdRet = SDMMC_Cmd3_SendRelativeAddr(handle->SDIOCx, &(handle->RCA)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + /* Get the SD card RCA */ + RelCardAddress(handle) = handle->RCA; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + enCmdRet = SDMMC_Cmd9_SendCSD(handle->SDIOCx, RelCardAddress(handle), handle->CSD); + if (enCmdRet != Ok) + { + return enCmdRet; + } + } + + /* Get CSD parameters */ + enCmdRet = SDCARD_GetCardCSD(handle); + if (enCmdRet == Ok) + { + /* Select the Card */ + enCmdRet = SDMMC_Cmd7_SelectDeselectCard(handle->SDIOCx, RelCardAddress(handle), (uint32_t *)(&handle->stcCardStatus)); + } + + return enCmdRet; +} + +/** + ******************************************************************************* + ** \brief Activate SD in power-on stage + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok Activate successfully. + ** \retval Error Activate unsuccessfully. + ** \retval ErrorInvalidParameter If one of following conditions matches: + ** - NULL == handle + ** - Other invalid configuration + ** + ******************************************************************************/ +static en_result_t SdCardPowerON(stc_sd_handle_t *handle) +{ + uint32_t u32IfCond = 0u; + __IO uint32_t u32Count = 0ul; + en_result_t enCmdRet = Error; + + if (NULL == handle) + { + return ErrorInvalidParameter; + } + + handle->u32ErrorCode = SD_CARD_ERROR_NONE; + + /* CMD0: GO_IDLE_STATE */ + enCmdRet = SDMMC_Cmd0_GoIdleState(handle->SDIOCx); + if (enCmdRet != Ok) + { + handle->u32ErrorCode |= SD_CARD_ERROR_GENERAL_UNKNOWN_ERR; + return enCmdRet; + } + + /* Reset OCR valude */ + handle->OCR = 0ul; + + /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ + enCmdRet = SDMMC_Cmd8_SendIfCond(handle->SDIOCx, &u32IfCond); + if (enCmdRet != Ok) + { + handle->stcSdCardInfo.u32CardVersion = SdCardVer1x; + + /* Send ACMD41 SD_APP_OP_COND with Argument 0x00100000 */ + while (SD_CARD_OCR_BUSY != (handle->OCR & SD_CARD_OCR_BUSY)) + { + if (SD_CARD_MAX_VOLT_TRIAL == u32Count++) + { + handle->u32ErrorCode |= SD_CARD_ERROR_INVALID_VOLTRANGE; + return enCmdRet; + } + + /* SEND CMD55 APP_CMD with RCA as 0 */ + enCmdRet = SDMMC_Cmd55_AppCmd(handle->SDIOCx, 0u, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + continue; + } + + /* Send CMD41 */ + enCmdRet = SDMMC_Acmd41_SdSendOpCond(handle->SDIOCx, SdmmcStanderdCapacity, &handle->OCR); + if (enCmdRet == Error) + { + handle->u32ErrorCode |= SD_CARD_ERROR_UNSUPPORTED_FEATURE; + return enCmdRet; + } + } + + /* Card type is SDSC */ + handle->stcSdCardInfo.u32CardType = SdCardSdsc; + } + else + { + handle->stcSdCardInfo.u32CardVersion = SdCardVer2x; + + /* Send ACMD41 SD_APP_OP_COND with Argument 0x40100000 */ + while (SD_CARD_OCR_BUSY != (handle->OCR & SD_CARD_OCR_BUSY)) + { + if (SD_CARD_MAX_VOLT_TRIAL == u32Count++) + { + handle->u32ErrorCode |= SD_CARD_ERROR_INVALID_VOLTRANGE; + return Error; + } + + /* SEND CMD55 APP_CMD with RCA as 0 */ + enCmdRet = SDMMC_Cmd55_AppCmd(handle->SDIOCx, 0u, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + continue; + } + + /* Send CMD41 */ + enCmdRet = SDMMC_Acmd41_SdSendOpCond(handle->SDIOCx, SdmmcHighCapacity, &handle->OCR); + if (enCmdRet == Error) + { + handle->u32ErrorCode |= SD_CARD_ERROR_UNSUPPORTED_FEATURE; + return enCmdRet; + } + } + + if ((handle->OCR & SdmmcHighCapacity) == SdmmcHighCapacity) + { + handle->stcSdCardInfo.u32CardType = SdCardSdhcSdxc; + } + else + { + handle->stcSdCardInfo.u32CardType = SdCardSdsc; + } + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Checks if the SD card is ready for data. + ** + ** \param [in] handle Pointer to SD Card handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] u32Timeout Retry to get card status time + ** + ** \retval Ok Card is ready for data + ** \retval Error Card is not ready for data + ** \retval ErrorInvalidParameter NULL == handle + ** + ******************************************************************************/ +static en_result_t SdCardCheckReayForData(stc_sd_handle_t *handle, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != handle) + { + do + { + enRet = SDMMC_Cmd13_SendStatus(handle->SDIOCx, RelCardAddress(handle), (uint32_t *)(&handle->stcCardStatus)); + if (Ok != enRet) + { + break; + } + } while ((--u32Timeout) && (false == IsCardReadyForData(handle))); + + if (0u == u32Timeout) + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the DMA Channel for SDIO Tx request. + ** + ** \param [in] DMAx The pointer to DMAC register base + ** \arg M4_DMA1 DMAC unit 1 instance register base + ** \arg M4_DMA2 DMAC unit 2 instance register base + ** \param [in] enCh The specified DMAC channel. + ** \arg DmaCh0 DMAC channel 0 + ** \arg DmaCh1 DMAC channel 1 + ** \arg DmaCh2 DMAC channel 2 + ** \arg DmaCh3 DMAC channel 3 + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu8TxBuf Pointer to the Tx buffer + ** \param [in] u16len Tx buffer size + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter Set unsuccessfully. + ** + ******************************************************************************/ +static en_result_t DmaSdiocTxConfig(M4_DMA_TypeDef* DMAx, + en_dma_channel_t enCh, + M4_SDIOC_TypeDef *SDIOCx, + uint8_t *pu8TxBuf, + uint16_t u16len) +{ + stc_dma_config_t stcDmaInit; + uint32_t u32Fcg0Periph = (M4_DMA1 == DMAx) ? PWC_FCG0_PERIPH_DMA1 : PWC_FCG0_PERIPH_DMA2; + en_event_src_t enEvtSrc = (M4_SDIOC1 == SDIOCx) ? EVT_SDIOC1_DMAW : EVT_SDIOC2_DMAW; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu8TxBuf) && \ + (IS_VALID_TRANSFER_BUF_LEN(u16len)) && \ + (IS_VALID_TRANSFER_BUF_ALIGN(pu8TxBuf))) + { + /* Enable peripheral clock */ + PWC_Fcg0PeriphClockCmd(u32Fcg0Periph, Enable); + + /* Enable DMA. */ + DMA_Cmd(DMAx, Enable); + + /* Initialize DMA. */ + MEM_ZERO_STRUCT(stcDmaInit); + stcDmaInit.u16BlockSize = SD_CARD_BLOCK_SIZE/4u; /* Set data block size. */ + stcDmaInit.u16TransferCnt = u16len/SD_CARD_BLOCK_SIZE; /* Set transfer count. */ + stcDmaInit.u32SrcAddr = (uint32_t)(&pu8TxBuf[0]); /* Set source address. */ + stcDmaInit.u32DesAddr = (uint32_t)(&SDIOCx->BUF0); /* Set destination address. */ + stcDmaInit.stcDmaChCfg.enSrcInc = AddressIncrease; /* Set source address mode. */ + stcDmaInit.stcDmaChCfg.enDesInc = AddressFix; /* Set destination address mode. */ + stcDmaInit.stcDmaChCfg.enTrnWidth = Dma32Bit; /* Set data width 8bit. */ + DMA_InitChannel(DMAx, enCh, &stcDmaInit); + + /* Enable the specified DMA channel. */ + DMA_ChannelCmd(DMAx, enCh, Enable); + + /* Clear DMA flag. */ + DMA_ClearIrqFlag(DMAx, enCh, TrnCpltIrq); + DMA_ClearIrqFlag(DMAx, enCh, BlkTrnCpltIrq); + + /* Enable peripheral circuit trigger function. */ + PWC_Fcg0PeriphClockCmd(PWC_FCG0_PERIPH_AOS, Enable); + + /* Set DMA trigger source. */ + DMA_SetTriggerSrc(DMAx, enCh, enEvtSrc); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the DMA Channel for SDIO Rx request. + ** + ** \param [in] DMAx The pointer to DMAC register base + ** \arg M4_DMA1 DMAC unit 1 instance register base + ** \arg M4_DMA2 DMAC unit 2 instance register base + ** \param [in] enCh The specified DMAC channel. + ** \arg DmaCh0 DMAC channel 0 + ** \arg DmaCh1 DMAC channel 1 + ** \arg DmaCh2 DMAC channel 2 + ** \arg DmaCh3 DMAC channel 3 + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu8RxBuf Pointer to the Rx buffer + ** \param [in] u16len Rx buffer size + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter Set unsuccessfully. + ** + ******************************************************************************/ +static en_result_t DmaSdiocRxConfig(M4_DMA_TypeDef* DMAx, + en_dma_channel_t enCh, + M4_SDIOC_TypeDef *SDIOCx, + uint8_t *pu8RxBuf, + uint16_t u16len) +{ + stc_dma_config_t stcDmaInit; + uint32_t u32Fcg0Periph = (M4_DMA1 == DMAx) ? PWC_FCG0_PERIPH_DMA1 : PWC_FCG0_PERIPH_DMA2; + en_event_src_t enEvtSrc = (M4_SDIOC1 == SDIOCx) ? EVT_SDIOC1_DMAR : EVT_SDIOC2_DMAR; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu8RxBuf) && \ + (IS_VALID_TRANSFER_BUF_LEN(u16len)) && \ + (IS_VALID_TRANSFER_BUF_ALIGN(pu8RxBuf))) + { + /* Enable peripheral clock */ + PWC_Fcg0PeriphClockCmd(u32Fcg0Periph,Enable); + + /* Enable DMA. */ + DMA_Cmd(DMAx, Enable); + + /* Initialize DMA. */ + MEM_ZERO_STRUCT(stcDmaInit); + stcDmaInit.u16BlockSize = SD_CARD_BLOCK_SIZE/4u; /* Set data block size. */ + stcDmaInit.u16TransferCnt = u16len/SD_CARD_BLOCK_SIZE; /* Set transfer count. */ + stcDmaInit.u32SrcAddr = (uint32_t)(&SDIOCx->BUF0); /* Set source address. */ + stcDmaInit.u32DesAddr = (uint32_t)(&pu8RxBuf[0]); /* Set destination address. */ + stcDmaInit.stcDmaChCfg.enSrcInc = AddressFix; /* Set source address mode. */ + stcDmaInit.stcDmaChCfg.enDesInc = AddressIncrease; /* Set destination address mode. */ + stcDmaInit.stcDmaChCfg.enTrnWidth = Dma32Bit; /* Set data width 8bit. */ + DMA_InitChannel(DMAx, enCh, &stcDmaInit); + + /* Enable the specified DMA channel. */ + DMA_ChannelCmd(DMAx, enCh, Enable); + + /* Clear DMA flag. */ + DMA_ClearIrqFlag(DMAx, enCh, TrnCpltIrq); + DMA_ClearIrqFlag(DMAx, enCh, BlkTrnCpltIrq); + + /* Enable peripheral circuit trigger function. */ + PWC_Fcg0PeriphClockCmd(PWC_FCG0_PERIPH_AOS, Enable); + + /* Set DMA trigger source. */ + DMA_SetTriggerSrc(DMAx, enCh, enEvtSrc); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Get the current card status. + * @param [in] handle Pointer to a @ref stc_sd_handle_t structure + * @param [out] pu32CardStatus Pointer to the value of current card status + * @retval int32_t: + * - LL_OK: Get card status success + * - LL_ERR: Refer to u32ErrorCode for the reason of error + * - LL_ERR_INVD_PARAM: An invalid parameter was write to the send command + * - LL_ERR_TIMEOUT: Send command timeout + */ +static en_result_t SD_GetCurrCardStatus(stc_sd_handle_t *handle, uint32_t *pu32CardStatus) +{ + en_result_t i32Ret; + + /* Send Status command */ + i32Ret = SDMMC_Cmd13_SendStatus(handle->SDIOCx, (uint32_t)(handle->stcSdCardInfo.u32RelCardAddr), (uint32_t *)&handle->u32ErrorCode); + if (Ok != i32Ret) { + return i32Ret; + } + /* Get SD card status */ + *pu32CardStatus = SDIOC_GetResponse(handle->SDIOCx, SdiocRegResp01); + + return i32Ret; +} + +/** + * @brief Get the current sd card state. + * @param [in] handle Pointer to a @ref stc_sd_handle_t structure + * @param [out] peCardState Pointer to a @ref en_sd_card_state_t enumeration + * @retval int32_t: + * - LL_OK: Get sd card state success + * - LL_ERR: Refer to u32ErrorCode for the reason of error + * - LL_ERR_INVD_PARAM: handle == NULL or peCardState == NULL or + * An invalid parameter was write to the send command + * - LL_ERR_TIMEOUT: Send command timeout + */ +en_result_t SD_GetCardState(stc_sd_handle_t *handle, en_sd_card_state_t *peCardState) +{ + en_result_t i32Ret; + uint32_t u32Response = 0UL; + + if ((NULL == peCardState) || (NULL == handle)) { + i32Ret = ErrorInvalidParameter; + } else { + i32Ret = SD_GetCurrCardStatus(handle, &u32Response); + *peCardState = (en_sd_card_state_t)(uint32_t)((u32Response >> 9) & 0x0FU); + } + + return i32Ret; +} + +//@} // SdiocGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Project/GateWay/source/Module/SDCard/sd_card.h b/Project/GateWay/source/Module/SDCard/sd_card.h new file mode 100644 index 0000000..93eb041 --- /dev/null +++ b/Project/GateWay/source/Module/SDCard/sd_card.h @@ -0,0 +1,404 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file sd_card.h + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-15 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ +#ifndef __SD_CARD_H__ +#define __SD_CARD_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "sdmmc_cmd.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SdiocGroup Secure Digital Input and Output Controller(SDIOC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief SD Card version definition + ** + ******************************************************************************/ + /** + * @brief SD Card State enumeration structure definition + */ +typedef enum { + SD_CARD_STAT_IDLE = 0x00U, /*!< Card state is idle */ + SD_CARD_STAT_RDY = 0x01U, /*!< Card state is ready */ + SD_CARD_STAT_IDENTIFY = 0x02U, /*!< Card is in identification state */ + SD_CARD_STAT_STANDBY = 0x03U, /*!< Card is in standby state */ + SD_CARD_STAT_TRANS = 0x04U, /*!< Card is in transfer state */ + SD_CARD_STAT_TX_DATA = 0x05U, /*!< Card is sending an operation */ + SD_CARD_STAT_RX_DATA = 0x06U, /*!< Card is receiving operation information */ + SD_CARD_STAT_PGM = 0x07U, /*!< Card is in programming state */ + SD_CARD_STAT_DISCONNECT = 0x08U /*!< Card is disconnected */ +} en_sd_card_state_t; + + +typedef enum en_sd_card_version +{ + SdCardVer1x = 0u, ///< SD Card version: 1.x + SdCardVer2x = 1u, ///< SD Card version: 2.x +} en_sd_card_version_t; + +/** + ******************************************************************************* + ** \brief SD Card device Read/Write mode + ** + ******************************************************************************/ +typedef enum en_sd_card_device_mode +{ + SdCardPollingMode = 0u, ///< Polling mode transfer + SdCardDmaMode = 1u, ///< DMA mode transfer +} en_sd_card_device_mode_t; + +/** + ******************************************************************************* + ** \brief SD Card Information Structure definition + ** + ******************************************************************************/ +typedef struct stc_sd_card_info +{ + uint32_t u32CardType; ///< Specifies the card Type + + uint32_t u32CardVersion; ///< Specifies the card version + + uint32_t u32Class; ///< Specifies the class of the card class + + uint32_t u32RelCardAddr; ///< Specifies the Relative Card Address + + uint32_t u32BlockNbr; ///< Specifies the Card Capacity in blocks + + uint32_t u32BlockSize; ///< Specifies one block size in bytes + + uint32_t u32LogBlockNbr; ///< Specifies the Card logical Capacity in blocks + + uint32_t u32LogBlockSize; ///< Specifies logical block size in bytes + +} stc_sd_card_info_t; + +/** + ******************************************************************************* + ** \brief CSD Register ver1.0(for Standard Capacity Card) + ** + ******************************************************************************/ +typedef struct stc_sdcard_csd_v1 +{ + /* Byte 1 */ + uint8_t RESERVE1 : 2; + uint8_t FILE_FORMAT : 2; + uint8_t TMP_WRITE_PROTECT : 1; + uint8_t PERM_WRITE_PROTECT : 1; + uint8_t COPY : 1; + uint8_t FILE_FORMAT_GRP : 1; + + /* Byte 2 */ + uint8_t RESERVE2 : 5; + uint8_t WRITE_BL_PARTIAL : 1; + uint8_t WRITE_BL_LEN1 : 2; + /* Byte 3 */ + uint8_t WRITE_BL_LEN2 : 2; + uint8_t R2W_FACTOR : 3; + uint8_t RESERVE3 : 2; + uint8_t WP_GRP_ENABLE : 1; + + /* Byte 4 */ + uint8_t WP_GRP_SIZE : 7; + uint8_t SECTOR_SIZE1 : 1; + /* Byte 5 */ + uint8_t SECTOR_SIZE2 : 6; + uint8_t ERASE_BLK_EN : 1; + uint8_t C_SIZE_MULTI1 : 1; + /* Byte 6 */ + uint8_t C_SIZE_MULTI2 : 2; + uint8_t CDD_W_CURR_MAX : 3; + uint8_t CDD_W_CURR_MIN : 3; + + /* Byte 7 */ + uint8_t VDD_R_CURR_MAX : 3; + uint8_t VDD_R_CURR_MIN : 3; + uint8_t C_SIZE1 : 2; + /* Byte 8 */ + uint8_t C_SIZE2 : 8; + /* Byte 9 */ + uint8_t C_SIZE3 : 2; + uint8_t RESERVED4 : 2; + uint8_t DSR_IMP : 1; + uint8_t READ_BLK_MISALIGH : 1; + uint8_t WRITE_BLK_MISALIGN : 1; + uint8_t READ_BL_PARTIAL : 1; + + /* Byte 10 */ + uint8_t READ_BL_LEN : 4; + uint8_t CCC1 : 4; + /* Byte 11 */ + uint8_t CCC2 : 8; + + /* Byte 12 */ + uint8_t TRAN_SPEED : 8; + + /* Byte 13 */ + uint8_t NSAC : 8; + + /* Byte 14 */ + uint8_t TAAC : 8; + + /* Byte 15 */ + uint8_t RESERVE5 : 6; + uint8_t CSD_STRUCTURE : 2; +}stc_sdcard_csd_v1_t; + +/** + ******************************************************************************* + ** \brief CSD Register ver2.0(for High Capacity Card) + ** + ******************************************************************************/ +typedef struct stc_sdcard_csd_v2 +{ + /* Byte 1 */ + uint8_t RESERVED1 : 2; + uint8_t FILE_FORMAT : 2; + uint8_t TMP_WRITE_PROTECT : 1; + uint8_t PERM_WRITE_PROTECT : 1; + uint8_t COPY : 1; + uint8_t FILE_FORMAT_GRP : 1; + + /* Byte 2 */ + uint8_t RESERVED2 : 5; + uint8_t WRITE_BL_PARTIAL : 1; + uint8_t WRITE_BL_LEN1 : 2; + /* Byte 3 */ + uint8_t WRITE_BL_LEN2 : 2; + uint8_t R2W_FACTOR : 3; + uint8_t RESERVED3 : 2; + uint8_t WP_GRP_ENABLE : 1; + + /* Byte 4 */ + uint8_t WP_GRP_SIZE : 7; + uint8_t SECTOR_SIZE1 : 1; + /* Byte 5 */ + uint8_t SECTOR_SIZE2 : 6; + uint8_t ERASE_BLK_EN : 1; + uint8_t RESERVED4 : 1; + + /* Byte 6 */ + uint8_t C_SIZE1 : 8; + /* Byte 7 */ + uint8_t C_SIZE2 : 8; + /* Byte 8 */ + uint8_t C_SIZE3 : 6; + uint8_t RESERVED5 : 2; + + /* Byte 9 */ + uint8_t RESERVED6 : 4; + uint8_t DSR_IMP : 1; + uint8_t READ_BLK_MISALIGH : 1; + uint8_t WRITE_BLK_MISALIGN : 1; + uint8_t READ_BL_PARTIAL : 1; + + /* Byte 10 */ + uint8_t READ_BL_LEN : 4; + uint8_t CCC1 : 4; + + /* Byte 11 */ + uint8_t CCC2 : 8; + + /* Byte 12 */ + uint8_t TRAN_SPEED : 8; + + /* Byte 13 */ + uint8_t NSAC : 8; + + /* Byte 14 */ + uint8_t TAAC : 8; + + /* Byte 15 */ + uint8_t RESERVED7 : 6; + uint8_t CSD_STRUCTURE : 2; +} stc_sdcard_csd_v2_t; + +/** + ******************************************************************************* + ** \brief SD Card initilization parameters + ** + ******************************************************************************/ +typedef struct stc_sdcard_init +{ + en_sdioc_bus_width_t enBusWidth; ///< Specifies the SDIOC bus width. + ///< This parameter can be a value of @ref en_sdioc_bus_width_t + + en_sdioc_clk_freq_t enClkFreq; ///< Specifies the SDIOC clock frequency. + ///< This parameter can be a value of @ref en_sdioc_clk_freq_t + + en_sdioc_speed_mode_t enSpeedMode; ///< Specifies the SDIOC speed mode. + ///< This parameter can be a value of @ref en_sdioc_speed_mode_t + + const stc_sdioc_init_t *pstcInitCfg; ///< SD required parameters + ///< and this structure detail refer @ref stc_sdioc_init_t +} stc_sdcard_init_t; + +/** + ******************************************************************************* + ** \brief SD Card use DMA unit/channel parameters + ** + ******************************************************************************/ +typedef struct stc_sdcard_dma_init +{ + M4_DMA_TypeDef *DMAx; ///< Pointer to DMA registers base address + ///< and this structure detail refer @ref M4_DMA_TypeDef + + en_dma_channel_t enDmaCh; ///< Specifies the DMA channel. + ///< This parameter can be a value of @ref en_dma_channel_t +} stc_sdcard_dma_init_t; + +/** + ******************************************************************************* + ** \brief SD handle Structure definition + ** + ******************************************************************************/ +typedef struct stc_sd_handle +{ + M4_SDIOC_TypeDef *SDIOCx; ///< Pointer to SD registers base address + ///< and this structure detail refer @ref M4_SDIOC_TypeDef + + en_sd_card_device_mode_t enDevMode; ///< SD Card Write/Read mode and this parameter can be a value of @ref en_sd_card_device_mode_t + + const stc_sdcard_dma_init_t *pstcDmaInitCfg; ///< Pointer to SD Card initialization parameters + ///< and this structure detail refer @ref stc_sdcard_init_t + + const stc_sdcard_init_t *pstcCardInitCfg; ///< Pointer to SD Card initialization parameters + ///< and this structure detail refer @ref stc_sdcard_init_t + + __IO uint32_t Context; ///< SD transfer context + + __IO uint32_t u32ErrorCode; ///< SD Card Error codes + + stc_sd_card_info_t stcSdCardInfo; ///< SD Card information + ///< and this structure detail refer @ref stc_sd_card_info_t + + stc_sdmmc_resp_card_status_t stcCardStatus; ///< SD Card status + ///< and this structure detail refer @ref stc_sdmmc_resp_card_status_t + + uint32_t OCR; ///< SD Card Operation Condition Register + + uint32_t CID[4]; ///< SD Card IDentification + + uint32_t CSD[4]; ///< SD Card Specific Data + + uint32_t DSR; ///< DSR value + + uint32_t RCA; ///< RCA value + + uint32_t SCR[2]; ///< SD Card Configuration Register + + uint32_t CSR; ///< SD Card Status Register +}stc_sd_handle_t; + + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define SD_CARD_ERROR_NONE (SDMMC_ERROR_NONE) /*!< No error */ +#define SD_CARD_ERROR_CMD_CRC_FAIL (SDMMC_ERROR_CMD_CRC_FAIL) /*!< Command response received (but CRC check failed) */ +#define SD_CARD_ERROR_DATA_CRC_FAIL (SDMMC_ERROR_DATA_CRC_FAIL) /*!< Data block sent/received (CRC check failed) */ +#define SD_CARD_ERROR_CMD_RSP_TIMEOUT (SDMMC_ERROR_CMD_RSP_TIMEOUT) /*!< Command response timeout */ +#define SD_CARD_ERROR_DATA_TIMEOUT (SDMMC_ERROR_DATA_TIMEOUT) /*!< Data timeout */ +#define SD_CARD_ERROR_TX_UNDERRUN (SDMMC_ERROR_TX_UNDERRUN) /*!< Transmit FIFO underrun */ +#define SD_CARD_ERROR_RX_OVERRUN (SDMMC_ERROR_RX_OVERRUN) /*!< Receive FIFO overrun */ +#define SD_CARD_ERROR_ADDR_MISALIGNED (SDMMC_ERROR_ADDR_MISALIGNED) /*!< Misaligned address */ +#define SD_CARD_ERROR_BLOCK_LEN_ERR (SDMMC_ERROR_BLOCK_LEN_ERR) /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define SD_CARD_ERROR_ERASE_SEQ_ERR (SDMMC_ERROR_ERASE_SEQ_ERR) /*!< An error in the sequence of erase command occurs */ +#define SD_CARD_ERROR_BAD_ERASE_PARAM (SDMMC_ERROR_BAD_ERASE_PARAM) /*!< An invalid selection for erase groups */ +#define SD_CARD_ERROR_WRITE_PROT_VIOLATION (SDMMC_ERROR_WRITE_PROT_VIOLATION) /*!< Attempt to program a write protect block */ +#define SD_CARD_ERROR_LOCK_UNLOCK_FAILED (SDMMC_ERROR_LOCK_UNLOCK_FAILED) /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define SD_CARD_ERROR_COM_CRC_FAILED (SDMMC_ERROR_COM_CRC_FAILED) /*!< CRC check of the previous command failed */ +#define SD_CARD_ERROR_ILLEGAL_CMD (SDMMC_ERROR_ILLEGAL_CMD) /*!< Command is not legal for the card state */ +#define SD_CARD_ERROR_CARD_ECC_FAILED (SDMMC_ERROR_CARD_ECC_FAILED) /*!< Card internal ECC was applied but failed to correct the data */ +#define SD_CARD_ERROR_CC_ERR (SDMMC_ERROR_CC_ERR) /*!< Internal card controller error */ +#define SD_CARD_ERROR_GENERAL_UNKNOWN_ERR (SDMMC_ERROR_GENERAL_UNKNOWN_ERR) /*!< General or unknown error */ +#define SD_CARD_ERROR_STREAM_READ_UNDERRUN (SDMMC_ERROR_STREAM_READ_UNDERRUN) /*!< The card could not sustain data reading in stream rmode */ +#define SD_CARD_ERROR_STREAM_WRITE_OVERRUN (SDMMC_ERROR_STREAM_WRITE_OVERRUN) /*!< The card could not sustain data programming in stream mode */ +#define SD_CARD_ERROR_CID_CSD_OVERWRITE (SDMMC_ERROR_CID_CSD_OVERWRITE) /*!< CID/CSD overwrite error */ +#define SD_CARD_ERROR_WP_ERASE_SKIP (SDMMC_ERROR_WP_ERASE_SKIP) /*!< Only partial address space was erased */ +#define SD_CARD_ERROR_CARD_ECC_DISABLED (SDMMC_ERROR_CARD_ECC_DISABLED) /*!< Command has been executed without using internal ECC */ +#define SD_CARD_ERROR_ERASE_RESET (SDMMC_ERROR_ERASE_RESET) /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define SD_CARD_ERROR_AKE_SEQ_ERR (SDMMC_ERROR_AKE_SEQ_ERR) /*!< Error in sequence of authentication */ +#define SD_CARD_ERROR_INVALID_VOLTRANGE (SDMMC_ERROR_INVALID_VOLTRANGE) /*!< Error in case of invalid voltage range */ +#define SD_CARD_ERROR_ADDR_OUT_OF_RANGE (SDMMC_ERROR_ADDR_OUT_OF_RANGE) /*!< Error when addressed block is out of range */ +#define SD_CARD_ERROR_REQUEST_NOT_APPLICABLE (SDMMC_ERROR_REQUEST_NOT_APPLICABLE)/*!< Error when command request is not applicable */ +#define SD_CARD_ERROR_PARAM (SDMMC_ERROR_INVALID_PARAMETER) /*!< the used parameter is not valid */ +#define SD_CARD_ERROR_UNSUPPORTED_FEATURE (SDMMC_ERROR_UNSUPPORTED_FEATURE) /*!< Error when feature is not insupported */ +#define SD_CARD_ERROR_BUSY (SDMMC_ERROR_BUSY) /*!< Error when transfer process is busy */ +#define SD_CARD_ERROR_DMA (SDMMC_ERROR_DMA) /*!< Error while DMA transfer */ +#define SD_CARD_ERROR_TIMEOUT (SDMMC_ERROR_TIMEOUT) /*!< Timeout error */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +en_result_t SDCARD_Init(stc_sd_handle_t *handle, + const stc_sdcard_init_t *pstcInitCfg); +en_result_t SDCARD_SetDeviceMode(stc_sd_handle_t *handle, + en_sd_card_device_mode_t enDevMode); +en_sd_card_device_mode_t SDCARD_GetDeviceMode(const stc_sd_handle_t *handle); +en_result_t SDCARD_GetCardCSD(stc_sd_handle_t *handle); +en_result_t SDCARD_Erase(stc_sd_handle_t *handle, + uint32_t u32BlkStartAddr, + uint32_t u32BlkEndAddr, + uint32_t u32Timeout); +en_result_t SDCARD_ReadBlocks( stc_sd_handle_t *handle, + uint32_t u32BlockAddr, + uint16_t u16BlockCnt, + uint8_t *pu8Data, + uint32_t u32Timeout); +en_result_t SDCARD_WriteBlocks( stc_sd_handle_t *handle, + uint32_t u32BlockAddr, + uint16_t u16BlockCnt, + uint8_t *pu8Data, + uint32_t u32Timeout); +en_result_t SD_GetCardState(stc_sd_handle_t *handle, en_sd_card_state_t *peCardState); +//@} // SdiocGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __SD_CARD_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Project/GateWay/source/Module/SDCard/sd_card_1.c b/Project/GateWay/source/Module/SDCard/sd_card_1.c new file mode 100644 index 0000000..568cb05 --- /dev/null +++ b/Project/GateWay/source/Module/SDCard/sd_card_1.c @@ -0,0 +1,1268 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file sd_card.c + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-15 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "sdmmc_cmd.h" +#include "sd_card.h" + +/** + ******************************************************************************* + ** \addtogroup SdiocGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +typedef enum en_sd_card_type +{ + SdCardSdsc = 0u, + SdCardSdhcSdxc = 1u, + SdCardSecured = 3u, +} en_sd_card_type_t; + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Card Command Class supported. */ +#define SDMMC_CARD_CCCC_ERASE (0x00000020u) + +/*!< Card locked */ +#define SDMMC_CARD_LOCKED (0x02000000u) + +/*!< Voltage trial times */ +#define SD_CARD_MAX_VOLT_TRIAL (0x0000FFFFu) + +/*!< High speed */ +#define SD_CHECK_FUNCTION_HIGH_SPEED (0x00FFFF01u) +#define SD_SET_FUNCTION_HIGH_SPEED (0x80FFFF01u) + +/*!< Block size is 512 bytes */ +#define SD_CARD_BLOCK_SIZE (512u) + +/*!< SDIOC buffer align size */ +#define SDIOC_BUF_ALIGN_SIZE (4ul) + +/*!< Log Block Number for 2G bytes Cards */ +#define SD_CARD_CAPACITY (0x400000u) + +/*!< Card power up status bit (busy) */ +#define SD_CARD_OCR_BUSY (0x80000000ul) + +#define SD_CARD_OP_NONE (0x00000000u) /*!< None */ +#define SD_CARD_OP_READ_SINGLE_BLOCK (0x00000001u) /*!< Read single block operation */ +#define SD_CARD_OP_READ_MULTIPLE_BLOCK (0x00000002u) /*!< Read multiple blocks operation */ +#define SD_CARD_OP_WRITE_SINGLE_BLOCK (0x00000010u) /*!< Write single block operation */ +#define SD_CARD_OP_WRITE_MULTIPLE_BLOCK (0x00000020u) /*!< Write multiple blocks operation */ +#define SD_CARD_OP_IT (0x00000008u) /*!< Process in Interrupt mode */ +#define SD_CARD_OP_DMA (0x00000080u) /*!< Process in DMA mode */ + +/*!< the SD card relative card address. */ +#define RelCardAddress(handle) ((handle)->stcSdCardInfo.u32RelCardAddr) +#define IsCardProgramming(handle) ((SdmmcCardStatePgm == (handle)->stcCardStatus.CURRENT_STATE) ? true : false) +#define IsCardReadyForData(handle) ((1u == (handle)->stcCardStatus.READY_FOR_DATA) ? true : false) + +#define IS_DMA_CFG_VALID(handle) \ +( (NULL != (handle)->pstcDmaInitCfg) && \ + (NULL != (handle)->pstcDmaInitCfg->DMAx)) + +/*!< the SD card use DMA unit && channel. */ +#define DMA_Unit(handle) ((handle)->pstcDmaInitCfg->DMAx) +#define DMA_CH(handle) ((handle)->pstcDmaInitCfg->enDmaCh) + +/*!< Parameter valid check for buffer address. */ +#define IS_VALID_TRANSFER_BUF_ALIGN(x) (!((SDIOC_BUF_ALIGN_SIZE-1ul) & ((uint32_t)(x)))) + +/*!< Parameter valid check for SDIOC command value. */ +#define IS_VALID_TRANSFER_BUF_LEN(x) (!((SD_CARD_BLOCK_SIZE - 1u) & (x))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static en_result_t SdCardInitSd(stc_sd_handle_t *handle); +static en_result_t SdCardPowerON(stc_sd_handle_t *handle); +static en_result_t SdCardInitHost(const stc_sd_handle_t *handle); +static en_result_t SdCardSetSpeed(stc_sd_handle_t *handle); +static en_result_t SdCardSetBusWidth(stc_sd_handle_t *handle); +static en_result_t SdCardCheckReayForData(stc_sd_handle_t *handle, + uint32_t u32Timeout); +static en_result_t DmaSdiocTxConfig(M4_DMA_TypeDef* DMAx, + en_dma_channel_t enCh, + M4_SDIOC_TypeDef *SDIOCx, + uint8_t *pu8TxBuf, + uint16_t u16len); +static en_result_t DmaSdiocRxConfig(M4_DMA_TypeDef* DMAx, + en_dma_channel_t enCh, + M4_SDIOC_TypeDef *SDIOCx, + uint8_t *pu8RxBuf, + uint16_t u16len); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize SD. + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] pstcInitCfg The pointer of SD configure structure + ** \arg This parameter detail refer @ref stc_sdcard_init_t + ** + ** \retval Ok Initialize SD successfully. + ** \retval Error Initialize SD unsuccessfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - handle == NULL + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t SDCARD_Init(stc_sd_handle_t *handle, + const stc_sdcard_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != handle) && (NULL != pstcInitCfg)) + { + handle->pstcCardInitCfg = pstcInitCfg; + + enRet = SdCardInitHost(handle); + if (enRet != Ok) + { + return enRet; + } + + enRet = SdCardPowerON(handle); + if (enRet != Ok) + { + return enRet; + } + + enRet = SdCardInitSd(handle); + if (enRet != Ok) + { + return enRet; + } + + enRet = SdCardSetBusWidth(handle); + if (enRet != Ok) + { + return enRet; + } + + enRet = SdCardSetSpeed(handle); + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set SD Card device Read/Write mode. + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] enDevMode Read/Write mode + ** \arg SdCardDmaMode DMA mode transfer + ** \arg SdCardPollingMode Polling mode transfer + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter handle pointer is NULL. + ** + ******************************************************************************/ +en_result_t SDCARD_SetDeviceMode(stc_sd_handle_t *handle, + en_sd_card_device_mode_t enDevMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != handle) + { + handle->enDevMode = enDevMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get SD Card device Read/Write mode. + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval SdCardDmaMode DMA mode transfer + ** \retval SdCardPollingMode Polling mode transfer + ** + ******************************************************************************/ +en_sd_card_device_mode_t SDCARD_GetDeviceMode(const stc_sd_handle_t *handle) +{ + DDL_ASSERT(NULL != handle); + + return handle->enDevMode; +} + +/** + ******************************************************************************* + ** \brief Get Card specified Data information. + ** + ** \param [in] handle Pointer to SD Card handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok Get successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - handle == NULL + ** + ******************************************************************************/ +en_result_t SDCARD_GetCardCSD(stc_sd_handle_t *handle) +{ + uint32_t u32Csize = 0ul; + uint32_t u32NumSector = 0ul; + uint32_t u32CsizeMulti = 0ul; + stc_sdcard_csd_v1_t *pstcCsdSd = NULL; + stc_sdcard_csd_v2_t *pstcCsdSdHc = NULL; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != handle) + { + /* High Capacity CSD Version 2.0*/ + if ((handle->CSD[3] & 0x00FF0000ul) == 0x00400000ul) + { + pstcCsdSdHc = (stc_sdcard_csd_v2_t *)&handle->CSD[0]; + u32Csize = ((unsigned int)pstcCsdSdHc->C_SIZE3 << 16ul) + + ((unsigned int)pstcCsdSdHc->C_SIZE2 << 8ul) + + pstcCsdSdHc->C_SIZE1; + + u32NumSector = (u32Csize + 1ul) << 10ul; + + handle->stcSdCardInfo.u32Class = (((uint32_t)pstcCsdSdHc->CCC2) << 4u) | ((uint32_t)pstcCsdSdHc->CCC1); + handle->stcSdCardInfo.u32BlockSize = 1ul << (pstcCsdSdHc->READ_BL_LEN); + } + else /* Standard Capacity CSD Version 1.xx */ + { + pstcCsdSd = (stc_sdcard_csd_v1_t *)&handle->CSD[0]; + + u32Csize = ((unsigned int)pstcCsdSd->C_SIZE3 << 10) + + ((unsigned int)pstcCsdSd->C_SIZE2 << 2) + + pstcCsdSd->C_SIZE1; + + u32CsizeMulti = ((uint32_t)(pstcCsdSd->C_SIZE_MULTI2) << 1) + (uint32_t)pstcCsdSd->C_SIZE_MULTI1; + u32NumSector = (u32Csize + 1ul) << (u32CsizeMulti + 2ul); + + if (pstcCsdSd->READ_BL_LEN == 0x0Au) + { + u32NumSector *= 2ul; + } + else if (pstcCsdSd->READ_BL_LEN == 0x0Bu) + { + u32NumSector *= 4ul; + } + else + { + /* Do nothing: only avoid MISRA warning */ + } + + handle->stcSdCardInfo.u32Class = ((uint32_t)pstcCsdSd->CCC2 << 4) | (uint32_t)pstcCsdSd->CCC1; + handle->stcSdCardInfo.u32BlockSize = 1ul << (pstcCsdSd->READ_BL_LEN); + } + + handle->stcSdCardInfo.u32BlockNbr = u32NumSector; + handle->stcSdCardInfo.u32LogBlockNbr = (handle->stcSdCardInfo.u32BlockNbr) * ((handle->stcSdCardInfo.u32BlockSize) / SD_CARD_BLOCK_SIZE); + handle->stcSdCardInfo.u32LogBlockSize = SD_CARD_BLOCK_SIZE; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Erase SD card blocks. + ** + ** \param [in] handle Pointer to SD Card handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] u32BlkStartAddr Block start address + ** \param [in] u32BlkEndAddr Block end address + ** \param [in] u32Timeout Erase timeout value + ** + ** \retval Ok Erase successfully. + ** \retval Error Erase unsuccessfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - handle == NULL + ** - u32BlkStartAddr out of range + ** - u32BlkEndAddr out of range + ** + ******************************************************************************/ +en_result_t SDCARD_Erase(stc_sd_handle_t *handle, + uint32_t u32BlkStartAddr, + uint32_t u32BlkEndAddr, + uint32_t u32Timeout) +{ + en_result_t enCmdRet = Error; + __IO uint32_t u32TimeCount = u32Timeout * (SystemCoreClock / 8u / 1000u); + + if ((NULL == handle) || + (u32BlkStartAddr > u32BlkEndAddr) || + (u32BlkEndAddr > handle->stcSdCardInfo.u32BlockNbr)) + { + return ErrorInvalidParameter; + } + + /* Check if the card command class supports erase command */ + if (!(handle->stcSdCardInfo.u32Class & SDMMC_CARD_CCCC_ERASE)) + { + return ErrorAccessRights; + } + + if ((SDIOC_GetResponse(handle->SDIOCx, SdiocRegResp01) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + return ErrorAccessRights; + } + + /* Check the Card capacity in term of Logical number of blocks */ + if (handle->stcSdCardInfo.u32CardType != SdCardSdhcSdxc) + { + u32BlkStartAddr *= SD_CARD_BLOCK_SIZE; + u32BlkEndAddr *= SD_CARD_BLOCK_SIZE; + } + + /* Send CMD35 ERASE_GRP_START with argument as address */ + enCmdRet = SDMMC_Cmd32_EraseWrBlkStart(handle->SDIOCx, u32BlkStartAddr, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + /* Send CMD36 ERASE_GRP_END with argument as address */ + enCmdRet = SDMMC_Cmd33_EraseWrBlkEnd(handle->SDIOCx, u32BlkEndAddr, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + enCmdRet = SDMMC_Cmd38_Erase(handle->SDIOCx, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + enCmdRet = SdCardCheckReayForData(handle, u32TimeCount); + + return enCmdRet; +} + +/** + ******************************************************************************* + ** \brief Read block data from SD card + ** + ** \param [in] handle Pointer to SD Card handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] u32BlockAddr Block address + ** \param [in] u16BlockCnt Block Count + ** \param [in] pu8Data Pointer to buffer which will store SD Card data. + ** \param [in] u32Timeout Transfer timeout + ** + ** \retval Ok Read successfully. + ** \retval Error Read unsuccessfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - handle == NULL + ** - pu8Data == NULL + ** - u16BlockCnt == 0 + ** - (u32BlockAddr + u16BlockCnt) out of range + ** + ******************************************************************************/ +en_result_t SDCARD_ReadBlocks(stc_sd_handle_t *handle, + uint32_t u32BlockAddr, + uint16_t u16BlockCnt, + uint8_t *pu8Data, + uint32_t u32Timeout) +{ + en_result_t enCmdRet; + stc_sdioc_data_cfg_t stcDataCfg; + uint8_t *pu8TempBuf = (uint8_t *)pu8Data; + uint32_t u32TimeCount = u32Timeout * (SystemCoreClock / 8u / 1000u); + __IO uint32_t u32Count = u32TimeCount; + en_sd_card_device_mode_t enDeviceMode = SDCARD_GetDeviceMode(handle); + en_flag_status_t enStatus = Reset; + en_flag_status_t enIrqFlag = Reset; + + if (NULL == handle) + { + return ErrorInvalidParameter; + } + + if ((NULL == pu8Data) || (0u == u16BlockCnt)) + { + handle->u32ErrorCode |= SD_CARD_ERROR_PARAM; + return ErrorInvalidParameter; + } + + handle->u32ErrorCode = SD_CARD_ERROR_NONE; + + if ((u32BlockAddr + u16BlockCnt) > (handle->stcSdCardInfo.u32LogBlockNbr)) + { + handle->u32ErrorCode |= SD_CARD_ERROR_ADDR_OUT_OF_RANGE; + return ErrorInvalidParameter; + } + + if (handle->stcSdCardInfo.u32CardType != SdCardSdhcSdxc) + { + u32BlockAddr *= SD_CARD_BLOCK_SIZE; + } + + /* Set Block Size for Card */ + enCmdRet = SDMMC_Cmd16_SetBlockLength(handle->SDIOCx, SD_CARD_BLOCK_SIZE, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + stcDataCfg.u16BlkCnt = u16BlockCnt; + stcDataCfg.u16BlkSize = SD_CARD_BLOCK_SIZE; + stcDataCfg.enDataTimeOut = SdiocDtoSdclk_2_27; + stcDataCfg.enTransferDir = SdiocTransferToHost; + stcDataCfg.enAutoCmd12Enable = (u16BlockCnt > 1u) ? Enable:Disable; + stcDataCfg.enTransferMode = (u16BlockCnt > 1u) ? SdiocTransferMultiple:SdiocTransferSingle; + enCmdRet = SDIOC_ConfigData(handle->SDIOCx, &stcDataCfg); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + if (enDeviceMode == SdCardDmaMode) + { + if (IS_DMA_CFG_VALID(handle)) + { + DmaSdiocRxConfig(DMA_Unit(handle), DMA_CH(handle), handle->SDIOCx, pu8TempBuf, u16BlockCnt * SD_CARD_BLOCK_SIZE); + } + } + + /* Read block(s) in polling mode */ + if (1u == u16BlockCnt) + { + handle->Context = SD_CARD_OP_READ_SINGLE_BLOCK; + /* Read Single Block command */ + enCmdRet = SDMMC_Cmd17_ReadSingleBlock(handle->SDIOCx, u32BlockAddr, (uint32_t *)(&handle->stcCardStatus)); + } + else + { + handle->Context = SD_CARD_OP_READ_MULTIPLE_BLOCK; + /* Read Multi Block command */ + enCmdRet = SDMMC_Cmd18_ReadMultipleBlock(handle->SDIOCx, u32BlockAddr, (uint32_t *)(&handle->stcCardStatus)); + } + + if (enCmdRet != Ok) + { + return enCmdRet; + } + + if (SdCardPollingMode == enDeviceMode) + { + /* Poll on SDIO flags */ + while (u16BlockCnt) + { + enStatus = SDIOC_GetStatus(handle->SDIOCx, SdiocBufferReadEnble); + enIrqFlag = SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocBufferReadReady); + if ((Set == enStatus) && (Set == enIrqFlag)) + { + SDIOC_ReadBuffer(handle->SDIOCx, pu8TempBuf, SD_CARD_BLOCK_SIZE); + + u16BlockCnt--; + u32Count = u32TimeCount; + pu8TempBuf += SD_CARD_BLOCK_SIZE; + } + + if (0ul == u32Count--) + { + return ErrorTimeout; + } + } + } + + for (u32Count = u32TimeCount; u32Count > 0ul; u32Count--) + { + if (Set == SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete)) + { + break; + } + } + + if (0ul == u32Count) + { + return ErrorTimeout; + } + else + { + SDIOC_ClearNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete); + } + + /* check whether Data transfer stops */ + if (Set == SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocErrorInt)) + { + enCmdRet = Error; + } + + return enCmdRet; +} + +/** + ******************************************************************************* + ** \brief Write block data to SD card + ** + ** \param [in] handle Pointer to SD Card handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] u32BlockAddr Block address + ** \param [in] u16BlockCnt Block Count + ** \param [in] pu8Data Pointer to buffer which contains data to be send to SD Card. + ** \param [in] u32Timeout Transfer timeout + ** + ** \retval Ok Write successfully. + ** \retval Error Write unsuccessfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - handle == NULL + ** - pu8Data == NULL + ** - u16BlockCnt == 0 + ** - (u32BlockAddr + u16BlockCnt) out of range + ** + ******************************************************************************/ +en_result_t SDCARD_WriteBlocks(stc_sd_handle_t *handle, + uint32_t u32BlockAddr, + uint16_t u16BlockCnt, + uint8_t *pu8Data, + uint32_t u32Timeout) +{ + en_result_t enCmdRet; + stc_sdioc_data_cfg_t stcDataCfg; + uint8_t *pu8TempBuf = (uint8_t *)pu8Data; + uint32_t u32TimeCount = u32Timeout * (SystemCoreClock / 50ul / 1000ul); + __IO uint32_t u32Count = u32TimeCount; + en_sd_card_device_mode_t enDeviceMode = SDCARD_GetDeviceMode(handle); + en_flag_status_t enStatus = Reset; + en_flag_status_t enIrqFlag = Reset; + + if (NULL == handle) + { + return ErrorInvalidParameter; + } + + if ((NULL == pu8Data) || (0u == u16BlockCnt)) + { + handle->u32ErrorCode |= SD_CARD_ERROR_PARAM; + return ErrorInvalidParameter; + } + + handle->u32ErrorCode = SD_CARD_ERROR_NONE; + + if ((u32BlockAddr + u16BlockCnt) > (handle->stcSdCardInfo.u32LogBlockNbr)) + { + handle->u32ErrorCode |= SD_CARD_ERROR_ADDR_OUT_OF_RANGE; + return ErrorInvalidParameter; + } + + /* Set Block Size for Card */ + enCmdRet = SDMMC_Cmd16_SetBlockLength(handle->SDIOCx, SD_CARD_BLOCK_SIZE, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + stcDataCfg.u16BlkCnt = u16BlockCnt; + stcDataCfg.u16BlkSize = SD_CARD_BLOCK_SIZE; + stcDataCfg.enDataTimeOut = SdiocDtoSdclk_2_27; + stcDataCfg.enTransferDir = SdiocTransferToCard; + stcDataCfg.enAutoCmd12Enable = (u16BlockCnt > 1u) ? Enable:Disable; + stcDataCfg.enTransferMode = (u16BlockCnt > 1u) ? SdiocTransferMultiple:SdiocTransferSingle; + enCmdRet = SDIOC_ConfigData(handle->SDIOCx, &stcDataCfg); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + if (handle->stcSdCardInfo.u32CardType != SdCardSdhcSdxc) + { + u32BlockAddr *= SD_CARD_BLOCK_SIZE; + } + + if (enDeviceMode == SdCardDmaMode) + { + if (IS_DMA_CFG_VALID(handle)) + { + DmaSdiocTxConfig(DMA_Unit(handle), DMA_CH(handle), handle->SDIOCx, pu8TempBuf, u16BlockCnt * SD_CARD_BLOCK_SIZE); + } + } + + /* Write block(s) in polling mode */ + if (1u == u16BlockCnt) + { + /* Read Single Block command */ + enCmdRet = SDMMC_Cmd24_WriteSingleBlock(handle->SDIOCx, u32BlockAddr, (uint32_t *)(&handle->stcCardStatus)); + } + else + { + /* Read Multi Block command */ + enCmdRet = SDMMC_Cmd25_WriteMultipleBlock(handle->SDIOCx, u32BlockAddr, (uint32_t *)(&handle->stcCardStatus)); + } + + if (enCmdRet != Ok) + { + return enCmdRet; + } + + if (SdCardPollingMode == enDeviceMode) + { + /* Poll on SDIO flags */ + while (u16BlockCnt) + { + enStatus = SDIOC_GetStatus(handle->SDIOCx, SdiocBufferWriteEnble); + enIrqFlag = SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocBufferWriteReady); + if ((Set == enStatus) && (Set == enIrqFlag)) + { + /* Write data to SDIO Tx Buffer */ + SDIOC_WriteBuffer(handle->SDIOCx, pu8TempBuf, SD_CARD_BLOCK_SIZE); + + u16BlockCnt--; + u32Count = u32TimeCount; + pu8TempBuf += SD_CARD_BLOCK_SIZE; + } + + if (u32Count-- == 0ul) + { + return ErrorTimeout; + } + } + } + + for (u32Count = u32TimeCount; u32Count > 0ul; u32Count--) + { + enStatus = SDIOC_GetStatus(handle->SDIOCx, SdiocData0PinLvl); + enIrqFlag = SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete); + if ((Set == enStatus) && (Set == enIrqFlag)) + { + break; + } + } + + if (0u == u32Count) + { + return ErrorTimeout; + } + else + { + SDIOC_ClearNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete); + } + + enCmdRet = SdCardCheckReayForData(handle, u32TimeCount); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + /* check whether Data transfer stops */ + if(Set == SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocErrorInt)) + { + return Error; + } + + SDIOC_ClearNormalIrqFlag(handle->SDIOCx, SdiocBufferWriteReady); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set SD bus width. + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok Set SD bus width successfully. + ** \retval Error Set SD bus width unsuccessfully. + ** \retval ErrorInvalidParameter If one of following conditions matches: + ** - NULL == pstcCfg + ** - enBusWidth is invalid. + ** - Other invalid configuration + ** + ******************************************************************************/ +static en_result_t SdCardSetBusWidth(stc_sd_handle_t *handle) +{ + uint32_t u32CmdArg = 0ul; + en_result_t enCmdRet = Ok; + + if ((NULL == handle) || (NULL == handle->pstcCardInitCfg)) + { + return ErrorInvalidParameter; + } + + switch (handle->pstcCardInitCfg->enBusWidth) + { + case SdiocBusWidth1Bit: + u32CmdArg = 0u; + break; + case SdiocBusWidth4Bit: + u32CmdArg = 2u; + break; + default: + enCmdRet = ErrorInvalidParameter; + break; + } + + if (Ok != enCmdRet) + { + return enCmdRet; + } + + enCmdRet = SDMMC_Cmd55_AppCmd(handle->SDIOCx, (RelCardAddress(handle) << 16u), (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + enCmdRet = SDMMC_Acmd6_SetBusWidth(handle->SDIOCx, u32CmdArg, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + enCmdRet = SDIOC_SetBusWidth(handle->SDIOCx, handle->pstcCardInitCfg->enBusWidth); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set SD high speed mode. + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok Set SD bus width successfully. + ** \retval Ok Set SD bus width unsuccessfully. + ** \retval ErrorInvalidParameter If one of following conditions matches: + ** - NULL == pstcCfg + ** - u32Freq is invalid. + ** + ******************************************************************************/ +static en_result_t SdCardSetSpeed(stc_sd_handle_t *handle) +{ + uint8_t au8TempBuf[64] = {0}; + uint32_t u32TimeCount = 2000 * (SystemCoreClock / 8u / 1000u); + __IO uint32_t u32Count = u32TimeCount; + en_flag_status_t enStatus = Reset; + en_flag_status_t enIrqFlag = Reset; + + en_result_t enCmdRet = ErrorInvalidParameter; + stc_sdioc_data_cfg_t stcDataCfg; + uint32_t u32Arg = SD_SET_FUNCTION_HIGH_SPEED; + + if ((NULL != handle) && (NULL != handle->pstcCardInitCfg)) + { + enCmdRet = Ok; + if (SdiocHighSpeedMode == handle->pstcCardInitCfg->enSpeedMode) + { + /* Set Block Size for Card */ + enCmdRet = SDMMC_Cmd16_SetBlockLength(handle->SDIOCx, 64u, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet == Ok) + { + stcDataCfg.u16BlkCnt = 1u; + stcDataCfg.u16BlkSize = 64u; + stcDataCfg.enDataTimeOut = SdiocDtoSdclk_2_27; + stcDataCfg.enTransferDir = SdiocTransferToHost; + stcDataCfg.enAutoCmd12Enable = Disable; + stcDataCfg.enTransferMode = SdiocTransferSingle; + enCmdRet = SDIOC_ConfigData(handle->SDIOCx, &stcDataCfg); + if (enCmdRet == Ok) + { + enCmdRet = SDMMC_Cmd6_SwitchFunc(handle->SDIOCx, u32Arg, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet == Ok) + { + while (u32Count--) + { + enStatus = SDIOC_GetStatus(handle->SDIOCx, SdiocBufferReadEnble); + enIrqFlag = SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocBufferReadReady); + if ((Set == enStatus) && (Set == enIrqFlag)) + { + SDIOC_ReadBuffer(handle->SDIOCx, au8TempBuf, sizeof(au8TempBuf)); + break; + } + } + + if (0ul == u32Count) + { + return ErrorTimeout; + } + + u32Count = u32TimeCount; + while (u32Count--) + { + if (Set == SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete)) + { + SDIOC_ClearNormalIrqFlag(handle->SDIOCx, SdiocTransferComplete); + break; + } + } + + if (0ul == u32Count) + { + return ErrorTimeout; + } + + /* Check whether switch function with error or transfer error occur */ + if ((!(au8TempBuf[16] & 0x01)) || + (Set == SDIOC_GetNormalIrqFlag(handle->SDIOCx, SdiocErrorInt))) + { + enCmdRet = Error; + } + } + } + } + } + + if (enCmdRet == Ok) + { + SDIOC_SetSpeedMode(handle->SDIOCx, handle->pstcCardInitCfg->enSpeedMode); + + enCmdRet = SDIOC_SetClk(handle->SDIOCx, handle->pstcCardInitCfg->enClkFreq); + } + } + + return enCmdRet; +} + +/** + ******************************************************************************* + ** \brief Initialize SDIO Host + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok SDIO host initialized successfully + ** \retval ErrorInvalidParameter If one of following conditions matches: + ** - NULL == pstcInitCfg + ** - Other invalid configuration + ** + ******************************************************************************/ +static en_result_t SdCardInitHost(const stc_sd_handle_t *handle) +{ + en_result_t enRet = Ok; + + if ((NULL == handle) || (NULL == handle->pstcCardInitCfg)) + { + return ErrorInvalidParameter; + } + + /* Enable SD clock supply */ + if (M4_SDIOC1 == handle->SDIOCx) + { + PWC_Fcg1PeriphClockCmd(PWC_FCG1_PERIPH_SDIOC1, Enable); + } + else if (M4_SDIOC2 == handle->SDIOCx) + { + PWC_Fcg1PeriphClockCmd(PWC_FCG1_PERIPH_SDIOC2, Enable); + } + else + { + return ErrorInvalidParameter; + } + + /* Set mode: SD */ + SDIOC_SetMode(handle->SDIOCx, SdiocModeSD); + + enRet = SDIOC_Init(handle->SDIOCx, handle->pstcCardInitCfg->pstcInitCfg); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize SD bus + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok SDIO bus cmd operate successfully. + ** \retval Error SDIO bus cmd operate unsuccessfully. + ** \retval ErrorInvalidParameter If one of following conditions matches: + ** - NULL == pstcCfg + ** - Other invalid configuration + ** + ******************************************************************************/ +static en_result_t SdCardInitSd(stc_sd_handle_t *handle) +{ + en_result_t enCmdRet = Ok; + + if(NULL == handle) + { + return ErrorInvalidParameter; + } + + if (handle->stcSdCardInfo.u32CardType != SdCardSecured) + { + /* Send CMD2 ALL_SEND_CID */ + enCmdRet = SDMMC_Cmd2_AllSendCID(handle->SDIOCx, handle->CID); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* SD Card publishes its RCA. */ + enCmdRet = SDMMC_Cmd3_SendRelativeAddr(handle->SDIOCx, &(handle->RCA)); + if (enCmdRet != Ok) + { + return enCmdRet; + } + + /* Get the SD card RCA */ + RelCardAddress(handle) = handle->RCA; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + enCmdRet = SDMMC_Cmd9_SendCSD(handle->SDIOCx, RelCardAddress(handle), handle->CSD); + if (enCmdRet != Ok) + { + return enCmdRet; + } + } + + /* Get CSD parameters */ + enCmdRet = SDCARD_GetCardCSD(handle); + if (enCmdRet == Ok) + { + /* Select the Card */ + enCmdRet = SDMMC_Cmd7_SelectDeselectCard(handle->SDIOCx, RelCardAddress(handle), (uint32_t *)(&handle->stcCardStatus)); + } + + return enCmdRet; +} + +/** + ******************************************************************************* + ** \brief Activate SD in power-on stage + ** + ** \param [in] handle Pointer to SD handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** + ** \retval Ok Activate successfully. + ** \retval Error Activate unsuccessfully. + ** \retval ErrorInvalidParameter If one of following conditions matches: + ** - NULL == handle + ** - Other invalid configuration + ** + ******************************************************************************/ +static en_result_t SdCardPowerON(stc_sd_handle_t *handle) +{ + uint32_t u32IfCond = 0u; + __IO uint32_t u32Count = 0ul; + en_result_t enCmdRet = Error; + + if (NULL == handle) + { + return ErrorInvalidParameter; + } + + handle->u32ErrorCode = SD_CARD_ERROR_NONE; + + /* CMD0: GO_IDLE_STATE */ + enCmdRet = SDMMC_Cmd0_GoIdleState(handle->SDIOCx); + if (enCmdRet != Ok) + { + handle->u32ErrorCode |= SD_CARD_ERROR_GENERAL_UNKNOWN_ERR; + return enCmdRet; + } + + /* Reset OCR valude */ + handle->OCR = 0ul; + + /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ + enCmdRet = SDMMC_Cmd8_SendIfCond(handle->SDIOCx, &u32IfCond); + if (enCmdRet != Ok) + { + handle->stcSdCardInfo.u32CardVersion = SdCardVer1x; + + /* Send ACMD41 SD_APP_OP_COND with Argument 0x00100000 */ + while (SD_CARD_OCR_BUSY != (handle->OCR & SD_CARD_OCR_BUSY)) + { + if (SD_CARD_MAX_VOLT_TRIAL == u32Count++) + { + handle->u32ErrorCode |= SD_CARD_ERROR_INVALID_VOLTRANGE; + return enCmdRet; + } + + /* SEND CMD55 APP_CMD with RCA as 0 */ + enCmdRet = SDMMC_Cmd55_AppCmd(handle->SDIOCx, 0u, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + continue; + } + + /* Send CMD41 */ + enCmdRet = SDMMC_Acmd41_SdSendOpCond(handle->SDIOCx, SdmmcStanderdCapacity, &handle->OCR); + if (enCmdRet == Error) + { + handle->u32ErrorCode |= SD_CARD_ERROR_UNSUPPORTED_FEATURE; + return enCmdRet; + } + } + + /* Card type is SDSC */ + handle->stcSdCardInfo.u32CardType = SdCardSdsc; + } + else + { + handle->stcSdCardInfo.u32CardVersion = SdCardVer2x; + + /* Send ACMD41 SD_APP_OP_COND with Argument 0x40100000 */ + while (SD_CARD_OCR_BUSY != (handle->OCR & SD_CARD_OCR_BUSY)) + { + if (SD_CARD_MAX_VOLT_TRIAL == u32Count++) + { + handle->u32ErrorCode |= SD_CARD_ERROR_INVALID_VOLTRANGE; + return Error; + } + + /* SEND CMD55 APP_CMD with RCA as 0 */ + enCmdRet = SDMMC_Cmd55_AppCmd(handle->SDIOCx, 0u, (uint32_t *)(&handle->stcCardStatus)); + if (enCmdRet != Ok) + { + continue; + } + + /* Send CMD41 */ + enCmdRet = SDMMC_Acmd41_SdSendOpCond(handle->SDIOCx, SdmmcHighCapacity, &handle->OCR); + if (enCmdRet == Error) + { + handle->u32ErrorCode |= SD_CARD_ERROR_UNSUPPORTED_FEATURE; + return enCmdRet; + } + } + + if ((handle->OCR & SdmmcHighCapacity) == SdmmcHighCapacity) + { + handle->stcSdCardInfo.u32CardType = SdCardSdhcSdxc; + } + else + { + handle->stcSdCardInfo.u32CardType = SdCardSdsc; + } + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Checks if the SD card is ready for data. + ** + ** \param [in] handle Pointer to SD Card handle + ** \arg This parameter detail refer @ref stc_sd_handle_t + ** \param [in] u32Timeout Retry to get card status time + ** + ** \retval Ok Card is ready for data + ** \retval Error Card is not ready for data + ** \retval ErrorInvalidParameter NULL == handle + ** + ******************************************************************************/ +static en_result_t SdCardCheckReayForData(stc_sd_handle_t *handle, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != handle) + { + do + { + enRet = SDMMC_Cmd13_SendStatus(handle->SDIOCx, RelCardAddress(handle), (uint32_t *)(&handle->stcCardStatus)); + if (Ok != enRet) + { + break; + } + } while ((--u32Timeout) && (false == IsCardReadyForData(handle))); + + if (0u == u32Timeout) + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the DMA Channel for SDIO Tx request. + ** + ** \param [in] DMAx The pointer to DMAC register base + ** \arg M4_DMA1 DMAC unit 1 instance register base + ** \arg M4_DMA2 DMAC unit 2 instance register base + ** \param [in] enCh The specified DMAC channel. + ** \arg DmaCh0 DMAC channel 0 + ** \arg DmaCh1 DMAC channel 1 + ** \arg DmaCh2 DMAC channel 2 + ** \arg DmaCh3 DMAC channel 3 + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu8TxBuf Pointer to the Tx buffer + ** \param [in] u16len Tx buffer size + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter Set unsuccessfully. + ** + ******************************************************************************/ +static en_result_t DmaSdiocTxConfig(M4_DMA_TypeDef* DMAx, + en_dma_channel_t enCh, + M4_SDIOC_TypeDef *SDIOCx, + uint8_t *pu8TxBuf, + uint16_t u16len) +{ + stc_dma_config_t stcDmaInit; + uint32_t u32Fcg0Periph = (M4_DMA1 == DMAx) ? PWC_FCG0_PERIPH_DMA1 : PWC_FCG0_PERIPH_DMA2; + en_event_src_t enEvtSrc = (M4_SDIOC1 == SDIOCx) ? EVT_SDIOC1_DMAW : EVT_SDIOC2_DMAW; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu8TxBuf) && \ + (IS_VALID_TRANSFER_BUF_LEN(u16len)) && \ + (IS_VALID_TRANSFER_BUF_ALIGN(pu8TxBuf))) + { + /* Enable peripheral clock */ + PWC_Fcg0PeriphClockCmd(u32Fcg0Periph, Enable); + + /* Enable DMA. */ + DMA_Cmd(DMAx, Enable); + + /* Initialize DMA. */ + MEM_ZERO_STRUCT(stcDmaInit); + stcDmaInit.u16BlockSize = SD_CARD_BLOCK_SIZE/4u; /* Set data block size. */ + stcDmaInit.u16TransferCnt = u16len/SD_CARD_BLOCK_SIZE; /* Set transfer count. */ + stcDmaInit.u32SrcAddr = (uint32_t)(&pu8TxBuf[0]); /* Set source address. */ + stcDmaInit.u32DesAddr = (uint32_t)(&SDIOCx->BUF0); /* Set destination address. */ + stcDmaInit.stcDmaChCfg.enSrcInc = AddressIncrease; /* Set source address mode. */ + stcDmaInit.stcDmaChCfg.enDesInc = AddressFix; /* Set destination address mode. */ + stcDmaInit.stcDmaChCfg.enTrnWidth = Dma32Bit; /* Set data width 8bit. */ + DMA_InitChannel(DMAx, enCh, &stcDmaInit); + + /* Enable the specified DMA channel. */ + DMA_ChannelCmd(DMAx, enCh, Enable); + + /* Clear DMA flag. */ + DMA_ClearIrqFlag(DMAx, enCh, TrnCpltIrq); + DMA_ClearIrqFlag(DMAx, enCh, BlkTrnCpltIrq); + + /* Enable peripheral circuit trigger function. */ + PWC_Fcg0PeriphClockCmd(PWC_FCG0_PERIPH_AOS, Enable); + + /* Set DMA trigger source. */ + DMA_SetTriggerSrc(DMAx, enCh, enEvtSrc); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the DMA Channel for SDIO Rx request. + ** + ** \param [in] DMAx The pointer to DMAC register base + ** \arg M4_DMA1 DMAC unit 1 instance register base + ** \arg M4_DMA2 DMAC unit 2 instance register base + ** \param [in] enCh The specified DMAC channel. + ** \arg DmaCh0 DMAC channel 0 + ** \arg DmaCh1 DMAC channel 1 + ** \arg DmaCh2 DMAC channel 2 + ** \arg DmaCh3 DMAC channel 3 + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu8RxBuf Pointer to the Rx buffer + ** \param [in] u16len Rx buffer size + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter Set unsuccessfully. + ** + ******************************************************************************/ +static en_result_t DmaSdiocRxConfig(M4_DMA_TypeDef* DMAx, + en_dma_channel_t enCh, + M4_SDIOC_TypeDef *SDIOCx, + uint8_t *pu8RxBuf, + uint16_t u16len) +{ + stc_dma_config_t stcDmaInit; + uint32_t u32Fcg0Periph = (M4_DMA1 == DMAx) ? PWC_FCG0_PERIPH_DMA1 : PWC_FCG0_PERIPH_DMA2; + en_event_src_t enEvtSrc = (M4_SDIOC1 == SDIOCx) ? EVT_SDIOC1_DMAR : EVT_SDIOC2_DMAR; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu8RxBuf) && \ + (IS_VALID_TRANSFER_BUF_LEN(u16len)) && \ + (IS_VALID_TRANSFER_BUF_ALIGN(pu8RxBuf))) + { + /* Enable peripheral clock */ + PWC_Fcg0PeriphClockCmd(u32Fcg0Periph,Enable); + + /* Enable DMA. */ + DMA_Cmd(DMAx, Enable); + + /* Initialize DMA. */ + MEM_ZERO_STRUCT(stcDmaInit); + stcDmaInit.u16BlockSize = SD_CARD_BLOCK_SIZE/4u; /* Set data block size. */ + stcDmaInit.u16TransferCnt = u16len/SD_CARD_BLOCK_SIZE; /* Set transfer count. */ + stcDmaInit.u32SrcAddr = (uint32_t)(&SDIOCx->BUF0); /* Set source address. */ + stcDmaInit.u32DesAddr = (uint32_t)(&pu8RxBuf[0]); /* Set destination address. */ + stcDmaInit.stcDmaChCfg.enSrcInc = AddressFix; /* Set source address mode. */ + stcDmaInit.stcDmaChCfg.enDesInc = AddressIncrease; /* Set destination address mode. */ + stcDmaInit.stcDmaChCfg.enTrnWidth = Dma32Bit; /* Set data width 8bit. */ + DMA_InitChannel(DMAx, enCh, &stcDmaInit); + + /* Enable the specified DMA channel. */ + DMA_ChannelCmd(DMAx, enCh, Enable); + + /* Clear DMA flag. */ + DMA_ClearIrqFlag(DMAx, enCh, TrnCpltIrq); + DMA_ClearIrqFlag(DMAx, enCh, BlkTrnCpltIrq); + + /* Enable peripheral circuit trigger function. */ + PWC_Fcg0PeriphClockCmd(PWC_FCG0_PERIPH_AOS, Enable); + + /* Set DMA trigger source. */ + DMA_SetTriggerSrc(DMAx, enCh, enEvtSrc); + + enRet = Ok; + } + + return enRet; +} + +//@} // SdiocGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Project/GateWay/source/Module/SDCard/sdmmc_cmd.c b/Project/GateWay/source/Module/SDCard/sdmmc_cmd.c new file mode 100644 index 0000000..2bdaa1b --- /dev/null +++ b/Project/GateWay/source/Module/SDCard/sdmmc_cmd.c @@ -0,0 +1,1641 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file sdmmc_cmd.c + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-15 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "sdmmc_cmd.h" + +/** + ******************************************************************************* + ** \addtogroup SdiocGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for SDIOC Instances. */ +#define IS_VALID_SDIOC(__SDIOCx__) \ +( (M4_SDIOC1 == (__SDIOCx__)) || \ + (M4_SDIOC2 == (__SDIOCx__))) + +/*!< Parameter valid check for SDIOC Instances. */ +#define IS_VALID_SD_TYPE(x) \ +( (SdmmcHighCapacity == (x)) || \ + (SdmmcStanderdCapacity == (x))) + +/*!< CMDBSY bit loop count */ +#define SDIOC_FLAG_CMDBUSY_LOOPS (200000ul) + +/*!< Command send and response timeout */ +#define SDMMC_CMD_TIMEOUT (10000ul) + +/*!< OCR register bit */ +#define SDMMC_SD_OCR_HCS (0x40000000ul) /* High Capacity Support */ +#define SDMMC_SD_OCR_BUSY (0x80000000ul) /* Card power up status bit (busy) */ + + +#define SDMMC_BUS_WIDTH_1BIT (0x00000000ul) +#define SDMMC_BUS_WIDTH_4BIT (0x00000002ul) + +#define SDMMC_CMD8_CHECK_PATTERN (0x000000AAul) +#define SDMMC_CMD8_VOLTAGE_SUPPLIED (0x00000100ul) /* 2.7 - 3.6v*/ +#define SDMMC_CMD8_ARGUEMENT (SDMMC_CMD8_VOLTAGE_SUPPLIED | SDMMC_CMD8_CHECK_PATTERN) +#define SDMMC_ACMD41_VOLTAGE (SDMMC_SD_VOLT_3_3) +#define SDMMC_ACMD41_HCS (1ul << 30u) + +/*!< Masks for R1 Response (SD Card Status Register) */ +#define SDMMC_R1_AKE_SEQ_ERROR (0x1ul << 3u ) +#define SDMMC_R1_ERASE_RESET (0x1ul << 13u) +#define SDMMC_R1_CARD_ECC_DISABLED (0x1ul << 14u) +#define SDMMC_R1_WP_ERASE_SKIP (0x1ul << 15u) +#define SDMMC_R1_CID_CSD_OVERWRITE (0x1ul << 16u) +#define SDMMC_R1_STREAM_WRITE_OVERRUN (0x1ul << 17u) +#define SDMMC_R1_STREAM_READ_UNDERRUN (0x1ul << 18u) +#define SDMMC_R1_GENERAL_UNKNOWN_ERROR (0x1ul << 19u) +#define SDMMC_R1_CC_ERROR (0x1ul << 20u) +#define SDMMC_R1_CARD_ECC_FAILED (0x1ul << 21u) +#define SDMMC_R1_ILLEGAL_COMMAND (0x1ul << 22u) +#define SDMMC_R1_COM_CRC_ERROR (0x1ul << 23u) +#define SDMMC_R1_LOCK_UNLOCK_FAILED (0x1ul << 24u) +#define SDMMC_R1_WP_VIOLATION (0x1ul << 26u) +#define SDMMC_R1_ERASE_PARAM_ERROR (0x1ul << 27u) +#define SDMMC_R1_ERASE_SEQ_ERROR (0x1ul << 28u) +#define SDMMC_R1_BLOCK_LEN_ERROR (0x1ul << 29u) +#define SDMMC_R1_ADDRESS_ERROR (0x1ul << 30u) +#define SDMMC_R1_OUT_OF_RANGE (0x1ul << 31u) +#define SDMMC_R1_ERRORS (0xFDFFE008ul) + +/*!< Masks for R6 Response. */ +#define SDMMC_R6_GENERAL_UNKNOWN_ERROR (0x1ul << 13u) +#define SDMMC_R6_ILLEGAL_CMD (0x1ul << 14u) +#define SDMMC_R6_COM_CRC_ERROR (0x1ul << 15u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp1(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32CmdResp1, + uint32_t u32Timeout); +static en_result_t SDMMC_GetCmdResp1b(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32CmdResp1, + uint32_t u32Timeout); +static en_result_t SDMMC_GetCmdResp2(M4_SDIOC_TypeDef *SDIOCx, + uint32_t u32CID_CSD[4]); +static en_result_t SDMMC_GetCmdResp3(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32OCR); +static en_result_t SDMMC_GetCmdResp6(M4_SDIOC_TypeDef *SDIOx, + uint32_t *pu32RCA); +static en_result_t SDMMC_GetCmdResp7(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32IfCond); +static en_result_t SDMMC_WaitBusIdle(M4_SDIOC_TypeDef *SDIOCx); +static en_result_t SDMMC_WaitResponse(M4_SDIOC_TypeDef *SDIOCx, + uint32_t u32Timeout); +static bool SDMMC_GetCardDetection(M4_SDIOC_TypeDef *SDIOCx); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Send the GO_IDLE_STATE command which will reset all cards to idle state + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd0_GoIdleState(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + stcCmdCfg.u8CmdIndex = CMD0_GO_IDLE_STATE; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdNoRsp; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + /* Set command and argument. */ + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_WaitResponse(SDIOCx, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_OP_COND command. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32Argument Argument used for the command. + ** \param [in] pu32OCR Pointer to buffer which will store OCR content. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd1_SendOpCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32OCR) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + stcCmdCfg.u8CmdIndex = CMD1_SEND_OP_COND; + stcCmdCfg.u32Argument = u32Argument; + stcCmdCfg.enRspIndex = SdiocCmdRspR3; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + + /* Set command and argument. */ + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp3(SDIOCx, pu32OCR); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ALL_SEND_CID command for asking any card to send the CID numbers + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32CID Pointer to buffer which will store CID content. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd2_AllSendCID(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32CID[4]) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + stcCmdCfg.u8CmdIndex = CMD2_ALL_SEND_CID; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR2; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + + /* Set command and argument. */ + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp2(SDIOCx, u32CID); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_RELATIVE_ADDR command for asking the card to publish a + ** new relative address(RCA) + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu32RCA Pointer to buffer which will store RCA. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd3_SendRelativeAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32RCA) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + stcCmdCfg.u8CmdIndex = CMD3_SEND_RELATIVE_ADDR; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR6; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + + /* Set command and argument. */ + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp6(SDIOCx, pu32RCA); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SWITCH_FUNC command. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32Argument Argument used for the command. + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd6_SwitchFunc(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + stcCmdCfg.u8CmdIndex = CMD6_SWITCH_FUNC; + stcCmdCfg.u32Argument = u32Argument; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + + /* Set command and argument. */ + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SELECT/DESELECT_CARD command for toggling a card between the + ** stand-by and transfer states or between the programming and disconnect states. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32RCA Relative Sdcard Address. + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd7_SelectDeselectCard(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD7_SEL_DESEL_CARD; + stcCmdCfg.u32Argument = (u32RCA << 16u); + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_IF_COND command. Sends SD Memory Card interface + ** condition, which includes host supply voltage information and asks + ** the card whether card supports voltage + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu32IfCond Pointer to buffers for storing interface condition. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd8_SendIfCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32IfCond) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Send CMD8 to verify SD card interface operating condition */ + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /* CMD Response: R7 */ + stcCmdCfg.u8CmdIndex = CMD8_SEND_IF_COND; + stcCmdCfg.u32Argument = SDMMC_CMD8_ARGUEMENT; + stcCmdCfg.enRspIndex = SdiocCmdRspR7; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); /* Set command and argument. */ + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp7(SDIOCx, pu32IfCond); + if (enRet == Ok) + { + if((*pu32IfCond & 0xFFu) != SDMMC_CMD8_CHECK_PATTERN) + { + enRet = Error; + } + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_CSD command to addressed card which will sends its + ** card-specificdata (CSD). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32RCA Relative Card Address + ** \param [in] u32CSD Pointer to buffers for storing CSD contents. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd9_SendCSD(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t u32CSD[4]) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD9_SEND_CSD; + stcCmdCfg.u32Argument = (u32RCA << 16u); + stcCmdCfg.enRspIndex = SdiocCmdRspR2; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp2(SDIOCx, u32CSD); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_CID command to addressed card which will sends its card + ** identification(CID). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32RCA Relative Card Address + ** \param [in] u32CID Pointer to buffers for storing CID contents. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd10_SendCID(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t u32CID[4]) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD10_SEND_CID; + stcCmdCfg.u32Argument = (u32RCA << 16u); + stcCmdCfg.enRspIndex = SdiocCmdRspR2; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp2(SDIOCx, u32CID); + } + } + } + + return enRet; +} + +/******************************************************************************* +** \brief Send the STOP_TRANSMISSION command to force the card to stop transmission. +** +** \param [in] SDIOCx Pointer to SDIOC instance register base +** \arg M4_SDIOC1 SDIOC unit 1 instance register base +** \arg M4_SDIOC2 SDIOC unit 2 instance register base +** +** \retval Ok Send successfully. +** \retval Error Send unsuccessfully. +** +*******************************************************************************/ +en_result_t SDMMC_Cmd12_StopTransmission(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD12_STOP_TRANSMISSION; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_STATUS to addressed card which will send its status + ** register contents + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32RCA Relative Card Address + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd13_SendStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD13_SEND_STATUS; + stcCmdCfg.u32Argument = (u32RCA << 16u); + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SET_BLOCKLEN command and check the response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32BlockLen Block length + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd16_SetBlockLength(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD16_SET_BLOCKLEN; + stcCmdCfg.u32Argument = u32BlockLen; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the READ_SINGLE_BLOCK command and check the response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32ReadAddr Data address + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd17_ReadSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD17_READ_SINGLE_BLOCK; + stcCmdCfg.u32Argument = u32ReadAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Enable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the READ_MULTIPLE_BLOCK command and check the response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32ReadAddr Data address + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd18_ReadMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD18_READ_MULTIPLE_BLOCK; + stcCmdCfg.u32Argument = u32ReadAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Enable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the WRITE_BLOCK command and check the response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32WriteAddr Data address + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd24_WriteSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD24_WRITE_SINGLE_BLOCK; + stcCmdCfg.u32Argument = u32WriteAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Enable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the WRITE_MULTIPLE_BLOCK command and check the response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32WriteAddr Data address + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd25_WriteMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD25_WRITE_MULTIPLE_BLOCK; + stcCmdCfg.u32Argument = u32WriteAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Enable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ERASE_WR_BLK_START command for setting the address of the + ** first write block to be erased. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32StartAddr The start address will be erased + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd32_EraseWrBlkStart(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD32_ERASE_WR_BLK_START; + stcCmdCfg.u32Argument = u32StartAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ERASE_WR_BLK_END command for setting the address of the + ** last write block of the continuous range to be erased. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32EndAddr The last address will be erased + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd33_EraseWrBlkEnd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD33_ERASE_WR_BLK_END; + stcCmdCfg.u32Argument = u32EndAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ERASE_GRP_START command and check the response. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32StartAddr The start address will be erased + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd35_SetEraseStartAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD35_ERASE_GRP_START; + stcCmdCfg.u32Argument = u32StartAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ERASE_GRP_END command and check the response. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32EndAddr The end address will be erased + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd36_SetEraseEndAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD36_ERASE_GRP_END; + stcCmdCfg.u32Argument = u32EndAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ERASE command for erasing all previously selected write blocks. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd38_Erase(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + SDIOC_SetDataTimeout(SDIOCx, SdiocDtoSdclk_2_27); + + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD38_ERASE; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR1b; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1b(SDIOCx, pu32Resp1, 50u * SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the APP_CMD Command to interpret the following command as an + ** application-specific command(ACMD). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32Argument Command argument(RCA) + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd55_AppCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD55_APP_CMD; + stcCmdCfg.u32Argument = u32Argument; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SET_BUS_WIDTH(ACMD6) Command to set bus width. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32BusWidth The data bus width, '00'= 1bit or '10' = 4bits bus + ** \arg SDMMC_BUS_WIDTH_1BIT 1 bits bus + ** \arg SDMMC_BUS_WIDTH_4BIT 4 bits bus + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Acmd6_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = ACMD6_APP_SD_SET_BUSWIDTH; + stcCmdCfg.u32Argument = u32BusWidth; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SD_STATUS(ACMD13) Command to ask the Status Register. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Acmd13_SdStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = ACMD13_SD_APP_STATUS; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SD_SEND_OP_COND(ACMD41) command to negotiate the operation + ** voltage range and get OCR. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32SdType Sdcard type + ** \arg SdmmcHighCapacity SD memory card: Standard capacity + ** \arg SdmmcHighCapacity SD memory card: High capacity + ** \param [in] pu32OCR Pointer to the variable that will contain + ** the OCR register contents. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Acmd41_SdSendOpCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32SdType, uint32_t *pu32OCR) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pu32OCR)) + { + DDL_ASSERT(IS_VALID_SD_TYPE(u32SdType)); + + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = ACMD41_SD_SEND_OP_COND; + stcCmdCfg.u32Argument = SDMMC_ACMD41_VOLTAGE | u32SdType; + stcCmdCfg.enRspIndex = SdiocCmdRspR3; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp3(SDIOCx, pu32OCR); + if (enRet == Ok) + { + if (!(*pu32OCR & SDMMC_SD_OCR_BUSY)) + { + enRet = ErrorOperationInProgress; + } + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_SCR(ACMD51) command to read the SD Configuration Register(SCR). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Acmd51_SendSCR(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = ACMD51_SD_APP_SEND_SCR; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R1(normal response command). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [out] pu32CmdResp1 received response value + ** \param [in] u32Timeout timeout for waiting SDIOC idle + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter pu32CmdResp1 == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp1(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32CmdResp1, + uint32_t u32Timeout) +{ + uint32_t u32R1 = 0u; + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitResponse(SDIOCx, u32Timeout); + if (enRet == Ok) + { + /* received response, retrieve it for analysis */ + u32R1 = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + if (u32R1 & SDMMC_R1_ERRORS) + { + enRet = Error; + } + + if (pu32CmdResp1 != NULL) + { + *pu32CmdResp1 = u32R1; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R1(normal response command) with busy signal. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [out] pu32CmdResp1 received response value + ** \param [in] u32Timeout timeout for waiting SDIOC idle + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter pu32CmdResp1 == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp1b(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32CmdResp1, + uint32_t u32Timeout) +{ + uint32_t u32R1 = 0u; + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t u32TmpCnt = u32Timeout; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitResponse(SDIOCx, u32Timeout); + if (enRet == Ok) + { + do + { + if (u32TmpCnt-- == 0u) + { + enRet = ErrorTimeout; + } + } while (Reset == SDIOC_GetStatus(SDIOCx, SdiocData0PinLvl)); + + if (enRet == Ok) + { + /* received response, retrieve it for analysis */ + u32R1 = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + if (u32R1 & SDMMC_R1_ERRORS) + { + enRet = Error; + } + + if (pu32CmdResp1 != NULL) + { + *pu32CmdResp1 = u32R1; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R2(CID, CSD register). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32CID_CSD Pointer to the variable that will contain the + ** CID or CSD register contents + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter u32CID_CSD == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp2(M4_SDIOC_TypeDef *SDIOCx, + uint32_t u32CID_CSD[4]) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != u32CID_CSD)) + { + enRet = SDMMC_WaitResponse(SDIOCx, SDMMC_CMD_TIMEOUT); + if (enRet == Ok) + { + /* received response */ + u32CID_CSD[0] = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + u32CID_CSD[1] = SDIOC_GetResponse(SDIOCx, SdiocRegResp23); + u32CID_CSD[2] = SDIOC_GetResponse(SDIOCx, SdiocRegResp45); + u32CID_CSD[3] = SDIOC_GetResponse(SDIOCx, SdiocRegResp67); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R3(OCR register). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu32OCR Pointer to the variable that will contain + ** the OCR register contents. + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter pu32OCR == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp3(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32OCR) +{ + en_result_t enRet = ErrorInvalidParameter; + + if((IS_VALID_SDIOC(SDIOCx)) && (NULL != pu32OCR)) + { + enRet = SDMMC_WaitResponse(SDIOCx, SDMMC_CMD_TIMEOUT); + if (enRet == Ok) + { + /* received response, retrieve it for analysis */ + *pu32OCR = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R6(Published RCA response). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu32RCA Pointer to the variable that will contain + ** published RCA number + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter pu32RCA == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp6(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32RCA) +{ + uint32_t u32R6 = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pu32RCA)) + { + enRet = SDMMC_WaitResponse(SDIOCx, SDMMC_CMD_TIMEOUT); + if (enRet == Ok) + { + /* received response, retrieve it. */ + u32R6 = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + if (!(u32R6 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_ERROR))) + { + *pu32RCA = (u32R6 >> 16); + } + else + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R7. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu32IfCond Pointer to the variable that will contain + ** interface condition. + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter pu32IfCond == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp7(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32IfCond) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pu32IfCond)) + { + enRet = SDMMC_WaitResponse(SDIOCx, SDMMC_CMD_TIMEOUT); + if (enRet == Ok) + { + *pu32IfCond = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Wait for bus line idle + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Command&Data line is free within a certain time + ** \retval ErrorTimeout Command&Data line is still busy after a certain time. + ** \retval ErrorInvalidParameter SDIOCx == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_WaitBusIdle(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32Retry = SDIOC_FLAG_CMDBUSY_LOOPS; + en_flag_status_t enInhibitCmdStatus = Set; + en_flag_status_t enInhibitDataStatus = Set; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = ErrorTimeout; + while (u32Retry-- > 0ul) + { + enInhibitCmdStatus = SDIOC_GetStatus(SDIOCx, SdiocCommandInhibitCmd); + enInhibitDataStatus = SDIOC_GetStatus(SDIOCx, SdiocCommandInhibitData); + if ((Reset == enInhibitCmdStatus) || (Reset == enInhibitDataStatus)) + { + enRet = Ok; + break; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Wait response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32Timeout timeout times + ** + ** \retval Ok Respond normal + ** \retval ErrorTimeout Respond timeout. + ** \retval ErrorInvalidParameter SDIOCx == NULL + ** \retval ErrorAccessRights Card is removed. + ** + ******************************************************************************/ +static en_result_t SDMMC_WaitResponse(M4_SDIOC_TypeDef *SDIOCx, + uint32_t u32Timeout) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The Timeout is expressed in ms */ + __IO uint32_t u32Count = u32Timeout * (SystemCoreClock / 8u /1000u); + en_flag_status_t enErrorInt = Set; + en_flag_status_t enCommandComplete = Set; + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = Ok; + do + { + if (u32Count-- == 0u) + { + enRet = ErrorTimeout; + break; + } + enErrorInt = SDIOC_GetNormalIrqFlag(SDIOCx, SdiocErrorInt); + enCommandComplete = SDIOC_GetNormalIrqFlag(SDIOCx, SdiocCommandComplete); + } while ((Reset == enErrorInt) && (Reset == enCommandComplete)); + + if (enRet == Ok) + { + if (Set == SDIOC_GetNormalIrqFlag(SDIOCx, SdiocErrorInt)) + { + enRet = Error; + } + else + { + if (false == SDMMC_GetCardDetection(SDIOCx)) + { + enRet = ErrorAccessRights; + } + else + { + if (Set == SDIOC_GetNormalIrqFlag(SDIOCx, SdiocCommandComplete)) + { + SDIOC_ClearNormalIrqFlag(SDIOCx, SdiocCommandComplete); + } + + if (Set == SDIOC_GetNormalIrqFlag(SDIOCx, SdiocTransferComplete)) + { + SDIOC_ClearNormalIrqFlag(SDIOCx, SdiocTransferComplete); + } + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get card insertion status + ** + ** This function checks card is inserted or not. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval true Card is inserted + ** \retval false Card is removed + ** + ******************************************************************************/ +static bool SDMMC_GetCardDetection(M4_SDIOC_TypeDef *SDIOCx) +{ + bool bRet = false; + __IO uint32_t u32Count = 5000ul * (SystemCoreClock / 8ul /1000ul); + + /* Wait until card is stable */ + do + { + if (Set == SDIOC_GetStatus(SDIOCx, SdiocCardStateStable)) + { + break; + } + } while (u32Count--); + + if (u32Count != 0ul) + { + bRet = true;//(Set == SDIOC_GetStatus(SDIOCx, SdiocCardInserted)) ? true : false; + } + + return bRet; +} + +//@} // SdiocGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Project/GateWay/source/Module/SDCard/sdmmc_cmd.h b/Project/GateWay/source/Module/SDCard/sdmmc_cmd.h new file mode 100644 index 0000000..9890e53 --- /dev/null +++ b/Project/GateWay/source/Module/SDCard/sdmmc_cmd.h @@ -0,0 +1,311 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file sdmmc_cmd.h + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-15 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ +#ifndef __SDMMC_CMD_H__ +#define __SDMMC_CMD_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ddl.h" +#include "hc32f460_utility.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SdiocGroup Secure Digital Input and Output Controller(SDIOC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SD/eMMC/SDIO card status + ** + ******************************************************************************/ +typedef enum en_sdmmc_card_state +{ + SdmmcCardStateIdle = 0u, ///< Card state: Idle State + SdmmcCardStateReady = 1u, ///< Card state: Ready State + SdmmcCardStateIdent = 2u, ///< Card state: Identification State + SdmmcCardStateStby = 3u, ///< Card state: Stand-by State + SdmmcCardStateTran = 4u, ///< Card state: Transfer State + SdmmcCardStateSendData = 5u, ///< Card state: Sending-data State + SdmmcCardStateRcvData = 6u, ///< Card state: Receive-data State + SdmmcCardStatePgm = 7u, ///< Card state: Programming State + SdmmcCardStateDis = 8u, ///< Card state: Disconnect State +} en_sdmmc_card_state_t; + +/** + ******************************************************************************* + ** \brief SD/eMMC/SDIO card capacity. + ** + ******************************************************************************/ +typedef enum sdmmc_capacity +{ + SdmmcStanderdCapacity = 0x00000000u, ///< Card capacity: Standard Capacity + SdmmcHighCapacity = 0x40000000u, ///< Card capacity: High Capacity +} sdmmc_capacity_t; + +/** + ******************************************************************************* + ** \brief SD/eMMC/SDIO card response data structure. + ** + ******************************************************************************/ +typedef struct stc_sdmmc_resp_card_status +{ + uint32_t RESERVE1 :3; ///< RESERVE + uint32_t AKE_SEQ_ERROR :1; ///< Error in the sequence of the authentication process + uint32_t RESERVE2 :1; ///< RESERVE + uint32_t APP_CMD :1; ///< The card will expect ACMD, or an indication that the command has been interpreted as ACMD + uint32_t RESERVE3 :2; ///< RESERVE + uint32_t READY_FOR_DATA :1; ///< Corresponds to buffer empty signaling on the bus + uint32_t CURRENT_STATE :4; ///< The state of the card when receiving the command. + + uint32_t ERASE_RESET :1; ///< An erase sequence was cleared before executing because an out of erase sequence command was received + uint32_t CARD_ECC_DISABLE :1; ///< The command has been executed without using the internal ECC. + uint32_t WP_ERASE_SKIP :1; ///< Set when only partial address space was erased due to existing write protected blocks or the temporary or permanent write protected card was erased. + uint32_t CSD_OVERWRITE :1; ///< - The read only section of the CSD does not match the card content. + ///< - An attempt to reverse the copy (set as original) or permanent WP (unprotected) bits was made. + uint32_t RESERVE4 :2; ///< RESERVE + uint32_t ERRORR :1; ///< A general or an unknown error occurred during the operation. + uint32_t CC_ERROR :1; ///< Internal card controller error + uint32_t CARD_ECC_FAIL :1; ///< Card internal ECC was applied but failed to correct the data. + uint32_t ILLEGAL_CMD :1; ///< Command not legal for the card state + uint32_t COM_CRC_ERROR :1; ///< The CRC check of the previous command failed. + uint32_t LOCK_UNLOCK_FAIL :1; ///< Set when a sequence or password error has been detected in lock/unlock card command. + uint32_t CARD_IS_LOCKED :1; ///< When set, signals that the card is locked by the host + uint32_t WP_VIOLATION :1; ///< Set when the host attempts to write to a protected block or to the temporary or permanent write protected card. + uint32_t ERASE_PARAM :1; ///< An invalid selection of write-blocks for erase occurred. + uint32_t ERASE_SEQ_ERR :1; ///< An error in the sequence of erase commands occurred. + uint32_t BLOCK_LEN_ERR :1; ///< The transferred block length is not allowed for this card, or the number of transferred bytes does not match the block length. + uint32_t ADDRESS_ERROR :1; ///< A misaligned address which did not match the block length was used in the command. + uint32_t OUT_OF_RANGE :1; ///< The command’s argument was out of the allowed range for this card. +} stc_sdmmc_resp_card_status_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SDMMC Commands Index + ** + ******************************************************************************/ +#define CMD0_GO_IDLE_STATE (0u) /*!< Resets the SD memory card. */ +#define CMD1_SEND_OP_COND (1u) /*!< Sends host capacity support information and activates the card's initialization process. */ +#define CMD2_ALL_SEND_CID (2u) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define CMD3_SEND_RELATIVE_ADDR (3u) /*!< Asks the card to publish a new relative address (RCA). */ +#define CMD_SET_DSR (4u) /*!< Programs the DSR of all cards. */ +#define CMD_SDMMC_SEN_OP_COND (5u) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its + operating condition register (OCR) content in the response on the CMD line. */ +#define CMD6_SWITCH_FUNC (6u) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define CMD7_SEL_DESEL_CARD (7u) /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define CMD8_SEND_IF_COND (8u) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information + and asks the card whether card supports voltage. */ +#define CMD9_SEND_CSD (9u) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define CMD10_SEND_CID (10u) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define CMD11_READ_DAT_UNTIL_STOP (11u) /*!< SD card doesn't support it. */ +#define CMD12_STOP_TRANSMISSION (12u) /*!< Forces the card to stop transmission. */ +#define CMD13_SEND_STATUS (13u) /*!< Addressed card sends its status register. */ +#define CMD14_HS_BUSTEST_READ (14u) /*!< Reserved */ +#define CMD15_GO_INACTIVE_STATE (15u) /*!< Sends an addressed card into the inactive state. */ +#define CMD16_SET_BLOCKLEN (16u) /*!< Sets the block length (in bytes for SDSC) for all following block commands + (read, write, lock). Default block length is fixed to 512 Bytes. Not effective + for SDHS and SDXC. */ +#define CMD17_READ_SINGLE_BLOCK (17u) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define CMD18_READ_MULTIPLE_BLOCK (18u) /*!< Continuously transfers data blocks from card to host until interrupted by + STOP_TRANSMISSION command. */ +#define CMD19_HS_BUSTEST_WRITE (19u) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define CMD20_WRITE_DAT_UNTIL_STOP (20u) /*!< Speed class control command. */ +#define CMD23_SET_BLOCK_COUNT (23u) /*!< Specify block count for CMD18 and CMD25. */ +#define CMD24_WRITE_SINGLE_BLOCK (24u) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define CMD25_WRITE_MULTIPLE_BLOCK (25u) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define CMD26_PROG_CID (26u) /*!< Reserved for manufacturers. */ +#define CMD27_PROG_CSD (27u) /*!< Programming of the programmable bits of the CSD. */ +#define CMD28_SET_WRITE_PROT (28u) /*!< Sets the write protection bit of the addressed group. */ +#define CMD29_CLR_WRITE_PROT (29u) /*!< Clears the write protection bit of the addressed group. */ +#define CMD30_SEND_WRITE_PROT (30u) /*!< Asks the card to send the status of the write protection bits. */ +#define CMD32_ERASE_WR_BLK_START (32u) /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define CMD33_ERASE_WR_BLK_END (33u) /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define CMD35_ERASE_GRP_START (35u) /*!< Sets the address of the first write block to be erased. Reserved for each command + system set by switch function command (CMD6). */ +#define CMD36_ERASE_GRP_END (36u) /*!< Sets the address of the last write block of the continuous range to be erased. + Reserved for each command system set by switch function command (CMD6). */ +#define CMD38_ERASE (38u) /*!< Reserved for SD security applications. */ +#define CMD39_FAST_IO (39u) /*!< SD card doesn't support it (Reserved). */ +#define CMD40_GO_IRQ_STATE (40u) /*!< SD card doesn't support it (Reserved). */ +#define CMD42_LOCK_UNLOCK (42u) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by + the SET_BLOCK_LEN command. */ +#define CMD55_APP_CMD (55u) /*!< Indicates to the card that the next command is an application specific command rather + than a standard command. */ +#define CMD56_GEN_CMD (56u) /*!< Used either to transfer a data block to the card or to get a data block from the card + for general purpose/application specific commands. */ +#define CMD64_NO_CMD (64u) /*!< No command */ + +/** + ******************************************************************************* + ** \brief SDMMC_APP_CMD Commands Index + ** + ******************************************************************************/ +#define ACMD6_APP_SD_SET_BUSWIDTH (6u) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus + widths are given in SCR register. */ +#define ACMD13_SD_APP_STATUS (13u) /*!< (ACMD13) Sends the SD status. */ +#define ACMD22_SD_APP_SEND_NUM_WRITE_BLOCKS (22u) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with + 32bit+CRC data block. */ +#define ACMD41_SD_SEND_OP_COND (41u) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to + send its operating condition register (OCR) content in the response on the CMD line. */ +#define ACMD42_SET_CLR_CARD_DETECT (42u) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define ACMD51_SD_APP_SEND_SCR (51u) /*!< Reads the SD Configuration Register (SCR). */ +#define ACMD52_RW_DIRECT (52u) /*!< For SD I/O card only, reserved for security specification. */ +#define ACMD53_RW_EXTENDED (53u) /*!< For SD I/O card only, reserved for security specification. */ + +/** + ******************************************************************************* + ** \brief SD Card Specific security commands Commands Index + ** + ******************************************************************************/ +#define ACMD43_GET_MKB (43u) +#define ACMD44_GET_MID (44u) +#define ACMD45_SET_CER_RN1 (45u) +#define ACMD46_GET_CER_RN2 (46u) +#define ACMD47_SET_CER_RES2 (47u) +#define ACMD48_GET_CER_RES1 (48u) +#define ACMD18_SECURE_READ_MULTIPLE_BLOCK (18u) +#define ACMD25_SECURE_WRITE_MULTIPLE_BLOCK (25u) +#define ACMD38_SECURE_ERASE (38u) +#define ACMD49_CHANGE_SECURE_AREA (49u) +#define ACMD48_SECURE_WRITE_MKB (48u) + +/** + ******************************************************************************* + ** \brief Media voltage supported. + ** + ******************************************************************************/ +#define SDMMC_SD_VOLT_1_7 (0x00000010ul) /* Low voltage card minimum */ +#define SDMMC_SD_VOLT_1_8 (0x00000020ul) +#define SDMMC_SD_VOLT_1_9 (0x00000040ul) +#define SDMMC_SD_VOLT_2_0 (0x00000080ul) +#define SDMMC_SD_VOLT_2_1 (0x00000100ul) /* Basic communication minimum */ +#define SDMMC_SD_VOLT_2_2 (0x00000200ul) +#define SDMMC_SD_VOLT_2_3 (0x00000400ul) +#define SDMMC_SD_VOLT_2_4 (0x00000800ul) +#define SDMMC_SD_VOLT_2_5 (0x00001000ul) +#define SDMMC_SD_VOLT_2_6 (0x00002000ul) +#define SDMMC_SD_VOLT_2_7 (0x00004000ul) +#define SDMMC_SD_VOLT_2_8 (0x00008000ul) /* Memory access minimum */ +#define SDMMC_SD_VOLT_2_9 (0x00010000ul) +#define SDMMC_SD_VOLT_3_0 (0x00020000ul) +#define SDMMC_SD_VOLT_3_1 (0x00040000ul) +#define SDMMC_SD_VOLT_3_2 (0x00080000ul) +#define SDMMC_SD_VOLT_3_3 (0x00100000ul) +#define SDMMC_SD_VOLT_3_4 (0x00200000ul) +#define SDMMC_SD_VOLT_3_5 (0x00400000ul) +#define SDMMC_SD_VOLT_3_6 (0x00800000ul) + + +#define SDMMC_ERROR_NONE (0x00000000ul) /*!< No error */ +#define SDMMC_ERROR_CMD_CRC_FAIL (0x00000001ul) /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERROR_DATA_CRC_FAIL (0x00000002ul) /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERROR_CMD_RSP_TIMEOUT (0x00000004ul) /*!< Command response timeout */ +#define SDMMC_ERROR_DATA_TIMEOUT (0x00000008ul) /*!< Data timeout */ +#define SDMMC_ERROR_TX_UNDERRUN (0x00000010ul) /*!< Transmit FIFO underrun */ +#define SDMMC_ERROR_RX_OVERRUN (0x00000020ul) /*!< Receive FIFO overrun */ +#define SDMMC_ERROR_ADDR_MISALIGNED (0x00000040ul) /*!< Misaligned address */ +#define SDMMC_ERROR_BLOCK_LEN_ERR (0x00000080ul) /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_ERASE_SEQ_ERR (0x00000100ul) /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERROR_BAD_ERASE_PARAM (0x00000200ul) /*!< An invalid selection for erase groups */ +#define SDMMC_ERROR_WRITE_PROT_VIOLATION (0x00000400ul) /*!< Attempt to program a write protect block */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED (0x00000800ul) /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_COM_CRC_FAILED (0x00001000ul) /*!< CRC check of the previous command failed */ +#define SDMMC_ERROR_ILLEGAL_CMD (0x00002000ul) /*!< Command is not legal for the card state */ +#define SDMMC_ERROR_CARD_ECC_FAILED (0x00004000ul) /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERROR_CC_ERR (0x00008000ul) /*!< Internal card controller error */ +#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR (0x00010000ul) /*!< General or unknown error */ +#define SDMMC_ERROR_STREAM_READ_UNDERRUN (0x00020000ul) /*!< The card could not sustain data reading in stream rmode */ +#define SDMMC_ERROR_STREAM_WRITE_OVERRUN (0x00040000ul) /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERROR_CID_CSD_OVERWRITE (0x00080000ul) /*!< CID/CSD overwrite error */ +#define SDMMC_ERROR_WP_ERASE_SKIP (0x00100000ul) /*!< Only partial address space was erased */ +#define SDMMC_ERROR_CARD_ECC_DISABLED (0x00200000ul) /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERROR_ERASE_RESET (0x00400000ul) /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define SDMMC_ERROR_AKE_SEQ_ERR (0x00800000ul) /*!< Error in sequence of authentication */ +#define SDMMC_ERROR_INVALID_VOLTRANGE (0x01000000ul) /*!< Error in case of invalid voltage range */ +#define SDMMC_ERROR_ADDR_OUT_OF_RANGE (0x02000000ul) /*!< Error when addressed block is out of range */ +#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE (0x04000000ul) /*!< Error when command request is not applicable */ +#define SDMMC_ERROR_INVALID_PARAMETER (0x08000000ul) /*!< the used parameter is not valid */ +#define SDMMC_ERROR_UNSUPPORTED_FEATURE (0x10000000ul) /*!< Error when feature is not insupported */ +#define SDMMC_ERROR_BUSY (0x20000000ul) /*!< Error when transfer process is busy */ +#define SDMMC_ERROR_DMA (0x40000000ul) /*!< Error while DMA transfer */ +#define SDMMC_ERROR_TIMEOUT (0x80000000ul) /*!< Timeout error */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t SDMMC_Cmd0_GoIdleState(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDMMC_Cmd1_SendOpCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32OCR); +en_result_t SDMMC_Cmd2_AllSendCID(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32CID[4]); +en_result_t SDMMC_Cmd3_SendRelativeAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32RCA); +en_result_t SDMMC_Cmd6_SwitchFunc(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd7_SelectDeselectCard(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd8_SendIfCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32IfCond); +en_result_t SDMMC_Cmd9_SendCSD(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t u32CSD[4]); +en_result_t SDMMC_Cmd10_SendCID(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t u32CID[4]); +en_result_t SDMMC_Cmd12_StopTransmission(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd13_SendStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd16_SetBlockLength(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd17_ReadSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd18_ReadMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd24_WriteSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd25_WriteMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd32_EraseWrBlkStart(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd33_EraseWrBlkEnd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd35_SetEraseStartAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd36_SetEraseEndAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd38_Erase(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1); +en_result_t SDMMC_Cmd55_AppCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32Resp1); +en_result_t SDMMC_Acmd6_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32Resp1); +en_result_t SDMMC_Acmd13_SdStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1); +en_result_t SDMMC_Acmd41_SdSendOpCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32SdType, uint32_t *pu32OCR); +en_result_t SDMMC_Acmd51_SendSCR(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1); + +//@} // SdiocGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __SDMMC_CMD_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Project/GateWay/source/Module/SDCard/sdmmc_cmd_1.c b/Project/GateWay/source/Module/SDCard/sdmmc_cmd_1.c new file mode 100644 index 0000000..6b0d673 --- /dev/null +++ b/Project/GateWay/source/Module/SDCard/sdmmc_cmd_1.c @@ -0,0 +1,1641 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file sdmmc_cmd.c + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-15 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "sdmmc_cmd.h" + +/** + ******************************************************************************* + ** \addtogroup SdiocGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for SDIOC Instances. */ +#define IS_VALID_SDIOC(__SDIOCx__) \ +( (M4_SDIOC1 == (__SDIOCx__)) || \ + (M4_SDIOC2 == (__SDIOCx__))) + +/*!< Parameter valid check for SDIOC Instances. */ +#define IS_VALID_SD_TYPE(x) \ +( (SdmmcHighCapacity == (x)) || \ + (SdmmcStanderdCapacity == (x))) + +/*!< CMDBSY bit loop count */ +#define SDIOC_FLAG_CMDBUSY_LOOPS (200000ul) + +/*!< Command send and response timeout */ +#define SDMMC_CMD_TIMEOUT (10000ul) + +/*!< OCR register bit */ +#define SDMMC_SD_OCR_HCS (0x40000000ul) /* High Capacity Support */ +#define SDMMC_SD_OCR_BUSY (0x80000000ul) /* Card power up status bit (busy) */ + + +#define SDMMC_BUS_WIDTH_1BIT (0x00000000ul) +#define SDMMC_BUS_WIDTH_4BIT (0x00000002ul) + +#define SDMMC_CMD8_CHECK_PATTERN (0x000000AAul) +#define SDMMC_CMD8_VOLTAGE_SUPPLIED (0x00000100ul) /* 2.7 - 3.6v*/ +#define SDMMC_CMD8_ARGUEMENT (SDMMC_CMD8_VOLTAGE_SUPPLIED | SDMMC_CMD8_CHECK_PATTERN) +#define SDMMC_ACMD41_VOLTAGE (SDMMC_SD_VOLT_3_3) +#define SDMMC_ACMD41_HCS (1ul << 30u) + +/*!< Masks for R1 Response (SD Card Status Register) */ +#define SDMMC_R1_AKE_SEQ_ERROR (0x1ul << 3u ) +#define SDMMC_R1_ERASE_RESET (0x1ul << 13u) +#define SDMMC_R1_CARD_ECC_DISABLED (0x1ul << 14u) +#define SDMMC_R1_WP_ERASE_SKIP (0x1ul << 15u) +#define SDMMC_R1_CID_CSD_OVERWRITE (0x1ul << 16u) +#define SDMMC_R1_STREAM_WRITE_OVERRUN (0x1ul << 17u) +#define SDMMC_R1_STREAM_READ_UNDERRUN (0x1ul << 18u) +#define SDMMC_R1_GENERAL_UNKNOWN_ERROR (0x1ul << 19u) +#define SDMMC_R1_CC_ERROR (0x1ul << 20u) +#define SDMMC_R1_CARD_ECC_FAILED (0x1ul << 21u) +#define SDMMC_R1_ILLEGAL_COMMAND (0x1ul << 22u) +#define SDMMC_R1_COM_CRC_ERROR (0x1ul << 23u) +#define SDMMC_R1_LOCK_UNLOCK_FAILED (0x1ul << 24u) +#define SDMMC_R1_WP_VIOLATION (0x1ul << 26u) +#define SDMMC_R1_ERASE_PARAM_ERROR (0x1ul << 27u) +#define SDMMC_R1_ERASE_SEQ_ERROR (0x1ul << 28u) +#define SDMMC_R1_BLOCK_LEN_ERROR (0x1ul << 29u) +#define SDMMC_R1_ADDRESS_ERROR (0x1ul << 30u) +#define SDMMC_R1_OUT_OF_RANGE (0x1ul << 31u) +#define SDMMC_R1_ERRORS (0xFDFFE008ul) + +/*!< Masks for R6 Response. */ +#define SDMMC_R6_GENERAL_UNKNOWN_ERROR (0x1ul << 13u) +#define SDMMC_R6_ILLEGAL_CMD (0x1ul << 14u) +#define SDMMC_R6_COM_CRC_ERROR (0x1ul << 15u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp1(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32CmdResp1, + uint32_t u32Timeout); +static en_result_t SDMMC_GetCmdResp1b(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32CmdResp1, + uint32_t u32Timeout); +static en_result_t SDMMC_GetCmdResp2(M4_SDIOC_TypeDef *SDIOCx, + uint32_t u32CID_CSD[4]); +static en_result_t SDMMC_GetCmdResp3(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32OCR); +static en_result_t SDMMC_GetCmdResp6(M4_SDIOC_TypeDef *SDIOx, + uint32_t *pu32RCA); +static en_result_t SDMMC_GetCmdResp7(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32IfCond); +static en_result_t SDMMC_WaitBusIdle(M4_SDIOC_TypeDef *SDIOCx); +static en_result_t SDMMC_WaitResponse(M4_SDIOC_TypeDef *SDIOCx, + uint32_t u32Timeout); +static bool SDMMC_GetCardDetection(M4_SDIOC_TypeDef *SDIOCx); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Send the GO_IDLE_STATE command which will reset all cards to idle state + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd0_GoIdleState(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + stcCmdCfg.u8CmdIndex = CMD0_GO_IDLE_STATE; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdNoRsp; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + /* Set command and argument. */ + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_WaitResponse(SDIOCx, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_OP_COND command. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32Argument Argument used for the command. + ** \param [in] pu32OCR Pointer to buffer which will store OCR content. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd1_SendOpCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32OCR) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + stcCmdCfg.u8CmdIndex = CMD1_SEND_OP_COND; + stcCmdCfg.u32Argument = u32Argument; + stcCmdCfg.enRspIndex = SdiocCmdRspR3; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + + /* Set command and argument. */ + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp3(SDIOCx, pu32OCR); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ALL_SEND_CID command for asking any card to send the CID numbers + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32CID Pointer to buffer which will store CID content. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd2_AllSendCID(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32CID[4]) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + stcCmdCfg.u8CmdIndex = CMD2_ALL_SEND_CID; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR2; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + + /* Set command and argument. */ + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp2(SDIOCx, u32CID); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_RELATIVE_ADDR command for asking the card to publish a + ** new relative address(RCA) + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu32RCA Pointer to buffer which will store RCA. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd3_SendRelativeAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32RCA) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + stcCmdCfg.u8CmdIndex = CMD3_SEND_RELATIVE_ADDR; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR6; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + + /* Set command and argument. */ + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp6(SDIOCx, pu32RCA); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SWITCH_FUNC command. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32Argument Argument used for the command. + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd6_SwitchFunc(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + stcCmdCfg.u8CmdIndex = CMD6_SWITCH_FUNC; + stcCmdCfg.u32Argument = u32Argument; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + + /* Set command and argument. */ + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SELECT/DESELECT_CARD command for toggling a card between the + ** stand-by and transfer states or between the programming and disconnect states. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32RCA Relative Sdcard Address. + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd7_SelectDeselectCard(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD7_SEL_DESEL_CARD; + stcCmdCfg.u32Argument = (u32RCA << 16u); + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_IF_COND command. Sends SD Memory Card interface + ** condition, which includes host supply voltage information and asks + ** the card whether card supports voltage + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu32IfCond Pointer to buffers for storing interface condition. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd8_SendIfCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32IfCond) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Send CMD8 to verify SD card interface operating condition */ + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /* CMD Response: R7 */ + stcCmdCfg.u8CmdIndex = CMD8_SEND_IF_COND; + stcCmdCfg.u32Argument = SDMMC_CMD8_ARGUEMENT; + stcCmdCfg.enRspIndex = SdiocCmdRspR7; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); /* Set command and argument. */ + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp7(SDIOCx, pu32IfCond); + if (enRet == Ok) + { + if((*pu32IfCond & 0xFFu) != SDMMC_CMD8_CHECK_PATTERN) + { + enRet = Error; + } + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_CSD command to addressed card which will sends its + ** card-specificdata (CSD). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32RCA Relative Card Address + ** \param [in] u32CSD Pointer to buffers for storing CSD contents. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd9_SendCSD(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t u32CSD[4]) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD9_SEND_CSD; + stcCmdCfg.u32Argument = (u32RCA << 16u); + stcCmdCfg.enRspIndex = SdiocCmdRspR2; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp2(SDIOCx, u32CSD); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_CID command to addressed card which will sends its card + ** identification(CID). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32RCA Relative Card Address + ** \param [in] u32CID Pointer to buffers for storing CID contents. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd10_SendCID(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t u32CID[4]) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD10_SEND_CID; + stcCmdCfg.u32Argument = (u32RCA << 16u); + stcCmdCfg.enRspIndex = SdiocCmdRspR2; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp2(SDIOCx, u32CID); + } + } + } + + return enRet; +} + +/******************************************************************************* +** \brief Send the STOP_TRANSMISSION command to force the card to stop transmission. +** +** \param [in] SDIOCx Pointer to SDIOC instance register base +** \arg M4_SDIOC1 SDIOC unit 1 instance register base +** \arg M4_SDIOC2 SDIOC unit 2 instance register base +** +** \retval Ok Send successfully. +** \retval Error Send unsuccessfully. +** +*******************************************************************************/ +en_result_t SDMMC_Cmd12_StopTransmission(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD12_STOP_TRANSMISSION; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_STATUS to addressed card which will send its status + ** register contents + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32RCA Relative Card Address + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd13_SendStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD13_SEND_STATUS; + stcCmdCfg.u32Argument = (u32RCA << 16u); + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SET_BLOCKLEN command and check the response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32BlockLen Block length + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd16_SetBlockLength(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD16_SET_BLOCKLEN; + stcCmdCfg.u32Argument = u32BlockLen; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the READ_SINGLE_BLOCK command and check the response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32ReadAddr Data address + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd17_ReadSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD17_READ_SINGLE_BLOCK; + stcCmdCfg.u32Argument = u32ReadAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Enable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the READ_MULTIPLE_BLOCK command and check the response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32ReadAddr Data address + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd18_ReadMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD18_READ_MULTIPLE_BLOCK; + stcCmdCfg.u32Argument = u32ReadAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Enable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the WRITE_BLOCK command and check the response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32WriteAddr Data address + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd24_WriteSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD24_WRITE_SINGLE_BLOCK; + stcCmdCfg.u32Argument = u32WriteAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Enable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the WRITE_MULTIPLE_BLOCK command and check the response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32WriteAddr Data address + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd25_WriteMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD25_WRITE_MULTIPLE_BLOCK; + stcCmdCfg.u32Argument = u32WriteAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Enable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ERASE_WR_BLK_START command for setting the address of the + ** first write block to be erased. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32StartAddr The start address will be erased + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd32_EraseWrBlkStart(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD32_ERASE_WR_BLK_START; + stcCmdCfg.u32Argument = u32StartAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ERASE_WR_BLK_END command for setting the address of the + ** last write block of the continuous range to be erased. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32EndAddr The last address will be erased + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd33_EraseWrBlkEnd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD33_ERASE_WR_BLK_END; + stcCmdCfg.u32Argument = u32EndAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ERASE_GRP_START command and check the response. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32StartAddr The start address will be erased + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd35_SetEraseStartAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD35_ERASE_GRP_START; + stcCmdCfg.u32Argument = u32StartAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ERASE_GRP_END command and check the response. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32EndAddr The end address will be erased + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd36_SetEraseEndAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD36_ERASE_GRP_END; + stcCmdCfg.u32Argument = u32EndAddr; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the ERASE command for erasing all previously selected write blocks. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd38_Erase(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + SDIOC_SetDataTimeout(SDIOCx, SdiocDtoSdclk_2_27); + + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD38_ERASE; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR1b; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1b(SDIOCx, pu32Resp1, 50u * SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the APP_CMD Command to interpret the following command as an + ** application-specific command(ACMD). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32Argument Command argument(RCA) + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Cmd55_AppCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = CMD55_APP_CMD; + stcCmdCfg.u32Argument = u32Argument; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SET_BUS_WIDTH(ACMD6) Command to set bus width. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32BusWidth The data bus width, '00'= 1bit or '10' = 4bits bus + ** \arg SDMMC_BUS_WIDTH_1BIT 1 bits bus + ** \arg SDMMC_BUS_WIDTH_4BIT 4 bits bus + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Acmd6_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = ACMD6_APP_SD_SET_BUSWIDTH; + stcCmdCfg.u32Argument = u32BusWidth; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SD_STATUS(ACMD13) Command to ask the Status Register. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Acmd13_SdStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = ACMD13_SD_APP_STATUS; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SD_SEND_OP_COND(ACMD41) command to negotiate the operation + ** voltage range and get OCR. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32SdType Sdcard type + ** \arg SdmmcHighCapacity SD memory card: Standard capacity + ** \arg SdmmcHighCapacity SD memory card: High capacity + ** \param [in] pu32OCR Pointer to the variable that will contain + ** the OCR register contents. + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Acmd41_SdSendOpCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32SdType, uint32_t *pu32OCR) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pu32OCR)) + { + DDL_ASSERT(IS_VALID_SD_TYPE(u32SdType)); + + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = ACMD41_SD_SEND_OP_COND; + stcCmdCfg.u32Argument = SDMMC_ACMD41_VOLTAGE | u32SdType; + stcCmdCfg.enRspIndex = SdiocCmdRspR3; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp3(SDIOCx, pu32OCR); + if (enRet == Ok) + { + if (!(*pu32OCR & SDMMC_SD_OCR_BUSY)) + { + enRet = ErrorOperationInProgress; + } + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Send the SEND_SCR(ACMD51) command to read the SD Configuration Register(SCR). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [out] pu32Resp1 Pointer to response data buffer + ** + ** \retval Ok Send successfully. + ** \retval Error Send unsuccessfully. + ** + ******************************************************************************/ +en_result_t SDMMC_Acmd51_SendSCR(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32Resp1) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_cmd_cfg_t stcCmdCfg = {0}; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitBusIdle(SDIOCx); + if (enRet == Ok) + { + /* Set command and argument. */ + stcCmdCfg.u8CmdIndex = ACMD51_SD_APP_SEND_SCR; + stcCmdCfg.u32Argument = 0u; + stcCmdCfg.enRspIndex = SdiocCmdRspR1; + stcCmdCfg.enDataPresentEnable = Disable; + stcCmdCfg.enCmdType = SdiocCmdNormal; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdCfg); + if (enRet == Ok) + { + /* Check for error conditions */ + enRet = SDMMC_GetCmdResp1(SDIOCx, pu32Resp1, SDMMC_CMD_TIMEOUT); + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R1(normal response command). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [out] pu32CmdResp1 received response value + ** \param [in] u32Timeout timeout for waiting SDIOC idle + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter pu32CmdResp1 == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp1(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32CmdResp1, + uint32_t u32Timeout) +{ + uint32_t u32R1 = 0u; + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitResponse(SDIOCx, u32Timeout); + if (enRet == Ok) + { + /* received response, retrieve it for analysis */ + u32R1 = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + if (u32R1 & SDMMC_R1_ERRORS) + { + enRet = Error; + } + + if (pu32CmdResp1 != NULL) + { + *pu32CmdResp1 = u32R1; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R1(normal response command) with busy signal. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [out] pu32CmdResp1 received response value + ** \param [in] u32Timeout timeout for waiting SDIOC idle + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter pu32CmdResp1 == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp1b(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32CmdResp1, + uint32_t u32Timeout) +{ + uint32_t u32R1 = 0u; + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t u32TmpCnt = u32Timeout; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = SDMMC_WaitResponse(SDIOCx, u32Timeout); + if (enRet == Ok) + { + do + { + if (u32TmpCnt-- == 0u) + { + enRet = ErrorTimeout; + } + } while (Reset == SDIOC_GetStatus(SDIOCx, SdiocData0PinLvl)); + + if (enRet == Ok) + { + /* received response, retrieve it for analysis */ + u32R1 = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + if (u32R1 & SDMMC_R1_ERRORS) + { + enRet = Error; + } + + if (pu32CmdResp1 != NULL) + { + *pu32CmdResp1 = u32R1; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R2(CID, CSD register). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32CID_CSD Pointer to the variable that will contain the + ** CID or CSD register contents + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter u32CID_CSD == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp2(M4_SDIOC_TypeDef *SDIOCx, + uint32_t u32CID_CSD[4]) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != u32CID_CSD)) + { + enRet = SDMMC_WaitResponse(SDIOCx, SDMMC_CMD_TIMEOUT); + if (enRet == Ok) + { + /* received response */ + u32CID_CSD[0] = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + u32CID_CSD[1] = SDIOC_GetResponse(SDIOCx, SdiocRegResp23); + u32CID_CSD[2] = SDIOC_GetResponse(SDIOCx, SdiocRegResp45); + u32CID_CSD[3] = SDIOC_GetResponse(SDIOCx, SdiocRegResp67); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R3(OCR register). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu32OCR Pointer to the variable that will contain + ** the OCR register contents. + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter pu32OCR == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp3(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32OCR) +{ + en_result_t enRet = ErrorInvalidParameter; + + if((IS_VALID_SDIOC(SDIOCx)) && (NULL != pu32OCR)) + { + enRet = SDMMC_WaitResponse(SDIOCx, SDMMC_CMD_TIMEOUT); + if (enRet == Ok) + { + /* received response, retrieve it for analysis */ + *pu32OCR = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R6(Published RCA response). + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu32RCA Pointer to the variable that will contain + ** published RCA number + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter pu32RCA == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp6(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32RCA) +{ + uint32_t u32R6 = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pu32RCA)) + { + enRet = SDMMC_WaitResponse(SDIOCx, SDMMC_CMD_TIMEOUT); + if (enRet == Ok) + { + /* received response, retrieve it. */ + u32R6 = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + if (!(u32R6 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_ERROR))) + { + *pu32RCA = (u32R6 >> 16); + } + else + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Response R7. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pu32IfCond Pointer to the variable that will contain + ** interface condition. + ** + ** \retval Ok Get successfully. + ** \retval Error Get unsuccessfully. + ** \retval ErrorInvalidParameter pu32IfCond == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_GetCmdResp7(M4_SDIOC_TypeDef *SDIOCx, + uint32_t *pu32IfCond) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pu32IfCond)) + { + enRet = SDMMC_WaitResponse(SDIOCx, SDMMC_CMD_TIMEOUT); + if (enRet == Ok) + { + *pu32IfCond = SDIOC_GetResponse(SDIOCx, SdiocRegResp01); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Wait for bus line idle + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Command&Data line is free within a certain time + ** \retval ErrorTimeout Command&Data line is still busy after a certain time. + ** \retval ErrorInvalidParameter SDIOCx == NULL + ** + ******************************************************************************/ +static en_result_t SDMMC_WaitBusIdle(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32Retry = SDIOC_FLAG_CMDBUSY_LOOPS; + en_flag_status_t enInhibitCmdStatus = Set; + en_flag_status_t enInhibitDataStatus = Set; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = ErrorTimeout; + while (u32Retry-- > 0ul) + { + enInhibitCmdStatus = SDIOC_GetStatus(SDIOCx, SdiocCommandInhibitCmd); + enInhibitDataStatus = SDIOC_GetStatus(SDIOCx, SdiocCommandInhibitData); + if ((Reset == enInhibitCmdStatus) || (Reset == enInhibitDataStatus)) + { + enRet = Ok; + break; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Wait response + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32Timeout timeout times + ** + ** \retval Ok Respond normal + ** \retval ErrorTimeout Respond timeout. + ** \retval ErrorInvalidParameter SDIOCx == NULL + ** \retval ErrorAccessRights Card is removed. + ** + ******************************************************************************/ +static en_result_t SDMMC_WaitResponse(M4_SDIOC_TypeDef *SDIOCx, + uint32_t u32Timeout) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The Timeout is expressed in ms */ + __IO uint32_t u32Count = u32Timeout * (SystemCoreClock / 8u /1000u); + en_flag_status_t enErrorInt = Set; + en_flag_status_t enCommandComplete = Set; + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_SDIOC(SDIOCx)) + { + enRet = Ok; + do + { + if (u32Count-- == 0u) + { + enRet = ErrorTimeout; + break; + } + enErrorInt = SDIOC_GetNormalIrqFlag(SDIOCx, SdiocErrorInt); + enCommandComplete = SDIOC_GetNormalIrqFlag(SDIOCx, SdiocCommandComplete); + } while ((Reset == enErrorInt) && (Reset == enCommandComplete)); + + if (enRet == Ok) + { + if (Set == SDIOC_GetNormalIrqFlag(SDIOCx, SdiocErrorInt)) + { + enRet = Error; + } + else + { + if (false == SDMMC_GetCardDetection(SDIOCx)) + { + enRet = ErrorAccessRights; + } + else + { + if (Set == SDIOC_GetNormalIrqFlag(SDIOCx, SdiocCommandComplete)) + { + SDIOC_ClearNormalIrqFlag(SDIOCx, SdiocCommandComplete); + } + + if (Set == SDIOC_GetNormalIrqFlag(SDIOCx, SdiocTransferComplete)) + { + SDIOC_ClearNormalIrqFlag(SDIOCx, SdiocTransferComplete); + } + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get card insertion status + ** + ** This function checks card is inserted or not. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval true Card is inserted + ** \retval false Card is removed + ** + ******************************************************************************/ +static bool SDMMC_GetCardDetection(M4_SDIOC_TypeDef *SDIOCx) +{ + bool bRet = false; + __IO uint32_t u32Count = 5000ul * (SystemCoreClock / 8ul /1000ul); + + /* Wait until card is stable */ + do + { + if (Set == SDIOC_GetStatus(SDIOCx, SdiocCardStateStable)) + { + break; + } + } while (u32Count--); + + if (u32Count != 0ul) + { + bRet = (Set == SDIOC_GetStatus(SDIOCx, SdiocCardInserted)) ? true : false; + } + + return bRet; +} + +//@} // SdiocGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Project/GateWay/source/Module/SHT20/SHT20.C b/Project/GateWay/source/Module/SHT20/SHT20.C new file mode 100644 index 0000000..a5193e4 --- /dev/null +++ b/Project/GateWay/source/Module/SHT20/SHT20.C @@ -0,0 +1,615 @@ +#include "SHT20.h" + + +SHT20Var_t SHT20; + +//---------- Defines ----------------------------------------------------------- +// CRC ÀÛ¼ÓºÍУÑé³£Á¿ +const uint32_t POLYNOMIAL = 0x131; //P(x)=x^8+x^5+x^4+1 = 100110001 + +/* +************************************************************ +* º¯ÊýÃû³Æ£º SHT2x_CheckCrc +* +* º¯Êý¹¦ÄÜ£º ¼ì²éÊý¾ÝÕýÈ·ÐÔ +* +* Èë¿Ú²ÎÊý£º data£º¶ÁÈ¡µ½µÄÊý¾Ý +* nbrOfBytes£ºÐèҪУÑéµÄÊýÁ¿ +* checksum£º¶ÁÈ¡µ½µÄУ¶Ô±ÈÑéÖµ +* +* ·µ»Ø²ÎÊý£º УÑé½á¹û +* +* ˵Ã÷£º 0-³É¹¦ 1-ʧ°Ü +************************************************************ +*/ +uint8_t SHT2x_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum) +{ + uint8_t crc = 0; + uint8_t bit = 0; + uint8_t byteCtr = 0; + + //calculates 8-Bit checksum with given polynomial + for(byteCtr = 0; byteCtr < nbrOfBytes; ++byteCtr) { + crc ^= (data[byteCtr]); + for ( bit = 8; bit > 0; --bit) { + if (crc & 0x80) + crc = (crc << 1) ^ POLYNOMIAL; + else + crc = (crc << 1); + } + } + + if(crc != checksum) + return 1; + return 0; + +} + +void delay_us(int dlycnt) +{ + for(int i = 0; i < dlycnt; i++) { + uint8_t temp = 10; + while(temp--); + } +} + +#ifdef I2C_SOFTWARE +#define ACK 0 //Ó¦´ðÐźŠ+#define NACK 1 //·ÇÓ¦´ðÐźŠ+#define SHT20_IN_SDA SHT20_I2C_SDA_Read() //¶ÁÈ¡SDAÖµ +#define IIC_Delay() delay_us(10) //ʱÖÓÑÓʱ + +/*================================================================ +[ Name ]void IO_I2CInit(void) +[Function]I2C³õʼ»¯ ¿ÕÏÐ״̬ +[ Notes ] +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +void IO_I2CInit(void) +{ + // +} + +// +/*================================================================ +[ Name ]SHT20_I2C_SDA_Read +[Function]¶ÁÈ¡SDAÊý¾ÝÏßÉÏÖµ +[ Notes ] +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +uint8_t SHT20_I2C_SDA_Read(void) +{ + SHT20_SDA_IN(); + if(SHT20_SDA_GET()) + return 1; + else + return 0; +} + +/*================================================================ +[ Name ]I2CStart +[Function]¿ªÊ¼ +[ Notes ] +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +void I2CStart(void) +{ + //uint8_t retval; + SHT20_SDA_OUT(); //ÉèÖóÉÊä³ö + //SHT20_SCL_OUT(); + SHT20_I2C_SDA_HIGH(); //ΪSDAϽµÆô¶¯×ö×¼±¸ + SHT20_I2C_SCL_HIGH(); //ÔÚSCL¸ßµçƽʱ£¬SDAΪϽµÑØʱºò×ÜÏßÆô¶¯ + + IIC_Delay(); + SHT20_I2C_SDA_LOW(); //Í»±ä£¬×ÜÏßÆô¶¯ + IIC_Delay(); + SHT20_I2C_SCL_LOW(); + IIC_Delay(); + +//SHT20_SDA_IN(); //ÉèÖóÉÊäÈë +// if(SHT20_IN_SDA) +// { +// retval= NACK; +// } +// else +// { +// retval= ACK; +// } +// retval=retval; +} + +/*================================================================ +[ Name ]I2CStop +[Function]½áÊø +[ Notes ] +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +void I2CStop(void) +{ + SHT20_SDA_OUT(); //ÉèÖóÉÊä³ö + SHT20_I2C_SDA_LOW(); //ΪSDAÉÏÉý×ö×¼±¸ + SHT20_I2C_SCL_LOW(); + + IIC_Delay(); + SHT20_I2C_SCL_HIGH(); //ÔÚSCL¸ßµçƽʱ£¬SDAΪÉÏÉýÑØʱºò×ÜÏßÍ£Ö¹ + IIC_Delay(); + SHT20_I2C_SDA_HIGH(); //Í»±ä£¬×ÜÏßÍ£Ö¹ + IIC_Delay(); +} + +/*================================================================ +[ Name ]I2C_Write_Byte +[Function]дһ¸ö×Ö½Ú ·µ»ØACK»òNACK +[ Notes ]´Ó¸ßµ½µÍ·¢ +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +uint8_t I2C_Write_Byte(uint8_t Write_Byte) //Sendbyte +{ + uint8_t i,retval=3; + + SHT20_SDA_OUT(); //ÉèÖóÉÊä³ö + //SHT20_SCL_OUT() ; + for(i = 0;i < 8;i++) { + if(Write_Byte & 0x80) + SHT20_I2C_SDA_HIGH(); //ÅжϷ¢ËÍ룬ÏÈ·¢Ë͸ßλ + else + SHT20_I2C_SDA_LOW(); + + //IIC_Delay(); + SHT20_I2C_SCL_HIGH(); //ΪSCLϽµ×ö×¼±¸ + IIC_Delay(); + SHT20_I2C_SCL_LOW(); //Í»±ä£¬½«Êý¾Ýλ·¢Ë͹ýÈ¥ + IIC_Delay(); + Write_Byte<<=1; //Êý¾Ý×óÒÆһλ + } //×Ö½Ú·¢ËÍÍê³É£¬¿ªÊ¼½ÓÊÕÓ¦´ðÐźŠ+ IIC_Delay(); + SHT20_I2C_SDA_HIGH(); //ÊÍ·ÅÊý¾ÝÏß + IIC_Delay(); + SHT20_SDA_IN(); //ÉèÖóÉÊäÈë + //IIC_Delay(); + SHT20_I2C_SCL_HIGH(); //ΪSCLϽµ×ö×¼±¸ + IIC_Delay(); + + if(SHT20_IN_SDA) + retval= NACK; + else + retval= ACK; + + SHT20_I2C_SCL_LOW(); + IIC_Delay(); + return retval; +} +// +/*================================================================ +[ Name ]I2C_Read_Byte +[Function]¶ÁÒ»¸ö×Ö½Ú£¬Èë¿â²ÎÊýÓÃÓÚ¿ØÖÆÓ¦´ð״̬ ACK»òNAC +[ Notes ]´Ó¸ßµ½µÍ +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +uint8_t I2C_Read_Byte(uint8_t AckValue)//receivebyte +{ + uint8_t i; + uint8_t RXDATA=0; +// SHT20_SDA_OUT(); //ÉèÖóÉÊä³ö +// SHT20_I2C_SDA_HIGH(); //Ê×ÏÈÖÃÊý¾ÝÏßΪ¸ßµçƽ +// SHT20_I2C_SCL_LOW(); + SHT20_SDA_IN(); //ÉèÖóÉÊäÈë + + for(i = 0;i < 8;i++) { + SHT20_I2C_SCL_HIGH(); //Í»±ä + IIC_Delay(); + RXDATA <<= 1; //¶ÁÈëÊý¾Ý£¬¸ßλÔÚÇ° + if(SHT20_IN_SDA) RXDATA |= 0x01; //ÊÕµ½¸ßµçƽ + else RXDATA &= 0xfe; + IIC_Delay(); + SHT20_I2C_SCL_LOW(); + IIC_Delay(); + } //Êý¾Ý½ÓÊÕÍê³É + + SHT20_SDA_OUT(); + if(AckValue) + SHT20_I2C_SDA_HIGH(); + else + SHT20_I2C_SDA_LOW(); + + IIC_Delay(); + SHT20_I2C_SCL_HIGH(); + IIC_Delay(); + SHT20_I2C_SCL_LOW(); + IIC_Delay(); + + return RXDATA; //·µ»Ø¶ÁÈ¡µ½µÄÊý¾Ý +} + +/*================================================================ +[ Name ]SHT20_SoftReset +[Function]SHT20Èí¼þ¸´Î» +[ Notes ]´Ó¸ßµ½µÍ +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +void SHT20_Reset(void) +{ + // IO_I2CInit(); //I2C initialize + I2CStart(); //start I2C + I2C_Write_Byte(SHT20_ADDRESS&0xfe); //I2C address + write + I2C_Write_Byte(0xfe); //soft reset + I2CStop(); //stop I2C +} + +/*================================================================ +[ Name ]SET_Resolution +[Function]д¼Ä´æÆ÷ ÉèÖ÷ֱæÂÊ +[ Notes ]´Ó¸ßµ½µÍ +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +void SET_Resolution(void) +{ + I2CStart(); //Start I2C + if(I2C_Write_Byte(SHT20_ADDRESS&0xfe) == ACK) { //I2C address + write + ACK + if(I2C_Write_Byte(0xe6) == ACK) { //дÓû§¼Ä´æÆ÷ + if(I2C_Write_Byte(0x83) == ACK) + __NOP(); //ÉèÖ÷ֱæÂÊ 11bit RH% ²âÁ¿Ê±¼ä:12ms(typ.) & 11bit T²âÁ¿Ê±¼ä:9ms(typ.) + } + } + I2CStop(); //Stop I2C +} + +/*================================================================ +[ Name ]ReadSht20 +[Function]·ÇÖ÷»úģʽ£¬¶ÁÈ¡ÎÂʪ¶ÈÖµ +[ Notes ]Èë¿Ú¿ØÖƶÁȡζȻòʪ¶È ¸´Î»ÐèÒª15ms ζÈת»»×î´óÐèÒª85ms +[ Author ]LZH SHT20ÉϵçºóµÈ´ý20ms ÔÙ¶ÁÈ¡sht20 +[ Data ]2016.06.22 +================================================================*/ +float SHT2x_MeasureHM(uint8_t whatdo) +{ + float temp; + uint8_t MSB,LSB,checksum=0,checktemp[2]; + float Humidity,Temperature; + uint32_t waitt= 1000; + //SET_Resolution(); //´Ë´¦Ö®Ç°³ö¹ýÎÊÌâ ËùÒÔÆÁ±Îµô + + I2CStart(); + if(I2C_Write_Byte(SHT20_ADDRESS&0xfe)==ACK) { //I2C address + write + ACK + if(I2C_Write_Byte(whatdo)==ACK) { //Command + do{ + delay_us(100); //¼ÓÈ볬ʱ + I2CStart(); + if(--waitt==0) + break; + } while(I2C_Write_Byte(SHT20_ADDRESS|0x01) == NACK); //I2C address + read + NACK + + if(waitt != 0) { + MSB = I2C_Read_Byte(ACK); //Data(MSB) + LSB = I2C_Read_Byte(ACK); //Data(LSB) + checksum=I2C_Read_Byte(NACK); //Checksum + NACK ÀÛ¼ÓºÍУÑéÖµ + I2CStop(); //Stop I2C + checktemp[0]=MSB; + checktemp[1]=LSB; + if(SHT2x_CheckCrc(checktemp,2,checksum)) { //ÀÛ¼ÓºÍУÑé³É¹¦ + LSB &= 0xfc; //Data (LSB) ºóÁ½Î»ÇåÁã + temp = MSB*256 + LSB; //Ê®Áù½øÖÆתʮ½øÖÆ + if (whatdo==((uint8_t)0xf5)) { //No Hold Master Mode,read humidity + /*-- calculate relative humidity [%RH] --*/ + Humidity =(temp*125)/65536-6; //¹«Ê½: RH%= -6 + 125 * SRH/2^16 + return Humidity; //·µ»Ø:humidity + } + else{ //No Hold Master Mode,read temperature + /*-- calculate temperature [¡æ] --*/ + Temperature = (temp*175.72)/65536-46.85; //¹«Ê½:T= -46.85 + 175.72 * ST/2^16 + return Temperature; //·µ»Ø:temperature + } + } + } + } + } + I2CStop(); //CT add + return 0; +} +// +/******************************************************** +[ Name ]GetMiddleNum +[Function] ÖÐÖµÂ˲¨ +[ Notes ] ´«ÈëÊý¾Ýbuf bArray, iFilterLenÂ˲¨Êý¾Ý³¤¶È +[ Author ] CSDN +[ Data ]2018.10.25 + +**********************************************************/ + +float GetMiddleNum(float * bArray, uint8_t iFilterLen) +{ + uint8_t i,j;// Ñ­»·±äÁ¿ + float bTemp; + + if(iFilterLen>100) + return 0; + // ÓÃðÅÝ·¨¶ÔÊý×é½øÐÐÅÅÐò + for (j = 0; j < iFilterLen - 1; j ++) { + for (i = 0; i < iFilterLen - j - 1; i ++) { + if (bArray[i] > bArray[i + 1]) { + // »¥»» + bTemp = bArray[i]; + bArray[i] = bArray[i + 1]; + bArray[i + 1] = bTemp; + } + } + } + // ¼ÆËãÖÐÖµ + if ((iFilterLen & 1) > 0) { + // Êý×éÓÐÆæÊý¸öÔªËØ£¬·µ»ØÖмäÒ»¸öÔªËØ + bTemp = bArray[(iFilterLen -1) / 2]; + } + else { + // Êý×éÓÐżÊý¸öÔªËØ£¬·µ»ØÖмäÁ½¸öÔªËØƽ¾ùÖµ + bTemp = (bArray[iFilterLen / 2-1] + bArray[iFilterLen / 2 ]) / 2; + } + return bTemp; +} +// +/******************************************************** +[ Name ]ReadSht20_Medium +[Function] »ñÈ¡ÖÐÖµ +[ Notes ] ¶ÁÈ¡Íêºó¹Ø±ÕÉÏÀ­ ÉèΪµÍ (½â¾ö¸ÉÈÅÎÊÌâ) +[ Author ] +[ Data ]2018.10.25 + +**********************************************************/ +float ReadSht20_Medium (void) +{ + float arry3[3]; + //SHT20_I2C_SET_PULL_UP(); //¿ªÆôÒý½ÅÉÏÀ­ + for(uint8_t ui=0; ui<3; ui++) { + arry3[ui]= SHT2x_MeasureHM(SHT20_Measurement_T_HM); + delay_us(20); + //printf("sht origin %.2f \r\n",arry3[ui]); + } + float retv = GetMiddleNum(arry3, 3); + +#ifdef I2C_SOFTWARE + //SHT20_I2C_SET_PULL_NO(); //¹Ø±ÕÉÏÀ­ + SHT20_I2C_LOW(); //¶ÁÈ¡ÍêζȺóÀ­µÍ +#endif + return retv; +} + +#else + +/* +************************************************************ +* º¯ÊýÃû³Æ£º SHT20_reset +* +* º¯Êý¹¦ÄÜ£º SHT20¸´Î» +* +* Èë¿Ú²ÎÊý£º ÎÞ +* +* ·µ»Ø²ÎÊý£º ÎÞ +* +* ˵Ã÷£º +************************************************************ +*/ +void SHT20_Reset(void) +{ + uint8_t Data = SHT20_SOFT_RESET; + Sht20_Reg_Write(SHT20_ADDRESS, &Data, 1); + Sht20_Delay(15); +} + +/* +************************************************************ +* º¯ÊýÃû³Æ£º SHT20_read_user_reg +* +* º¯Êý¹¦ÄÜ£º SHT20¶ÁÈ¡Óû§¼Ä´æÆ÷ +* +* Èë¿Ú²ÎÊý£º ÎÞ +* +* ·µ»Ø²ÎÊý£º ¶ÁÈ¡µ½µÄÓû§¼Ä´æÆ÷µÄÖµ +* +* ˵Ã÷£º +************************************************************ +*/ +uint8_t SHT20_read_user_reg(void) +{ + uint8_t val = 0; + uint8_t reg = SHT20_READ_REG; + Sht20_Read(SHT20_ADDRESS, ®, &val, 1); + return val; +} + +/* +************************************************************ +* º¯ÊýÃû³Æ£º SHT2x_CalcTemperatureC +* +* º¯Êý¹¦ÄÜ£º ζȼÆËã +* +* Èë¿Ú²ÎÊý£º u16sT£º¶ÁÈ¡µ½µÄζÈԭʼÊý¾Ý +* +* ·µ»Ø²ÎÊý£º ¼ÆËãºóµÄζÈÊý¾Ý +* +* ˵Ã÷£º +************************************************************ +*/ +float SHT2x_CalcTemperatureC(uint16_t u16sT) +{ + float temperatureC = 0; // variable for result + + u16sT &= ~0x0003; // clear bits [1..0] (status bits) + //-- calculate temperature [¡æ] -- + temperatureC = -46.85 + 175.72 / 65536 * (float)u16sT; //T= -46.85 + 175.72 * ST/2^16 + + return temperatureC; +} + +/* +************************************************************ +* º¯ÊýÃû³Æ£º SHT2x_CalcRH +* +* º¯Êý¹¦ÄÜ£º ʪ¶È¼ÆËã +* +* Èë¿Ú²ÎÊý£º u16sRH£º¶ÁÈ¡µ½µÄʪ¶ÈԭʼÊý¾Ý +* +* ·µ»Ø²ÎÊý£º ¼ÆËãºóµÄʪ¶ÈÊý¾Ý +* +* ˵Ã÷£º +************************************************************ +*/ +float SHT2x_CalcRH(uint16_t u16sRH) +{ + float humidityRH = 0; // variable for result + + u16sRH &= ~0x0003; // clear bits [1..0] (status bits) + //-- calculate relative humidity [%RH] -- + //humidityRH = -6.0 + 125.0/65536 * (float)u16sRH; // RH= -6 + 125 * SRH/2^16 + humidityRH = ((float)u16sRH * 0.00190735) - 6; + + return humidityRH; +} + +/* +************************************************************ +* º¯ÊýÃû³Æ£º SHT2x_MeasureHM +* +* º¯Êý¹¦ÄÜ£º ²âÁ¿ÎÂʪ¶È +* +* Èë¿Ú²ÎÊý£º cmd£º²âÁ¿Î¶Ȼ¹ÊÇʪ¶È +* +* ·µ»Ø²ÎÊý£º ²âÁ¿½á¹û +* +* ˵Ã÷£º +************************************************************ +*/ +float SHT2x_MeasureHM(uint8_t cmd) +{ + uint8_t checksum = 0; //checksum + uint8_t data[3]; //data array for checksum verification + uint16_t tmp = 0; + float t = 0; + + Sht20_Read(SHT20_ADDRESS, &cmd, data, 3); + checksum = data[2]; + if(SHT2x_CheckCrc(data, 2, checksum) == 0) { + tmp = (data[0] << 8) + data[1]; + if(cmd == SHT20_Measurement_T_NHM) + t = SHT2x_CalcTemperatureC(tmp); + else + t = SHT2x_CalcRH(tmp); + } + + return t; +} + + +#endif + +/* +************************************************************ +* º¯ÊýÃû³Æ£º SHT20_GetValue +* +* º¯Êý¹¦ÄÜ£º »ñÈ¡ÎÂʪ¶ÈÊý¾Ý +* +* Èë¿Ú²ÎÊý£º ÎÞ +* +* ·µ»Ø²ÎÊý£º ÎÞ +* +* ˵Ã÷£º ÎÂʪ¶È½á¹û±£´æÔÚSHT20½á¹¹ÌåÀï +************************************************************ +*/ +void SHT20_GetValue(float *Tempreture, float *Humidity) +{ + if(Tempreture != NULL) { + *Tempreture = SHT20.Tempreture; + } + if(Humidity != NULL) { + *Humidity = SHT20.Humidity; + } + //SHT20_reset(); +} + +void SHT20Start(void) +{ + memset(&SHT20, 0x00, sizeof(SHT20)); + SHT20.Sht20Status = SHT20_INIT; +} +void SHT20LoopHandler(void) +{ + uint8_t ret; + uint8_t rData[3]; + + switch(SHT20.Sht20Status) { + case SHT20_IDLE: + break; + + case SHT20_INIT: + SHT20_Reset(); + SHT20.Sht201mSDelayCnt = 200; + SHT20.Sht20Status = SHT20_READ_HUMI; + break; + + case SHT20_READ_TEMPR: + if(SHT20.Sht201mSDelayCnt > 0) + break; + SHT20.Cmd = SHT20_Measurement_T_NHM; + ret = SHT20_StartMeas(SHT20_ADDRESS, &SHT20.Cmd); + if(ret == true) { + SHT20.Sht201mSDelayCnt = 90; + SHT20.Sht20Status = SHT20_READ_DATA; + } + else { + SHT20.Sht201mSDelayCnt = 1000; + SHT20.Sht20Status = SHT20_INIT; + } + break; + + case SHT20_READ_HUMI: + if(SHT20.Sht201mSDelayCnt > 0) + break; + SHT20.Cmd = SHT20_Measurement_RH_NHM; + ret = SHT20_StartMeas(SHT20_ADDRESS, &SHT20.Cmd); + if(ret == true) { + SHT20.Sht201mSDelayCnt = 90; + SHT20.Sht20Status = SHT20_READ_DATA; + } + else { + SHT20.Sht201mSDelayCnt = 1000; + SHT20.Sht20Status = SHT20_INIT; + } + break; + + case SHT20_READ_DATA: + if(SHT20.Sht201mSDelayCnt > 0) + break; + ret = SHT20_Readata(SHT20_ADDRESS, rData, 3); + if(ret == true) { + if(SHT2x_CheckCrc(rData, 2, rData[2]) == 0) { + uint16_t tmp = (rData[0] << 8) + rData[1]; + if(SHT20.Cmd == SHT20_Measurement_T_NHM) { + SHT20.Tempreture = SHT2x_CalcTemperatureC(tmp); + SHT20.Sht20Status = SHT20_READ_HUMI; + } + else { + SHT20.Humidity = SHT2x_CalcRH(tmp); + SHT20.Sht20Status = SHT20_READ_TEMPR; + } + SHT20.Sht201mSDelayCnt = 5; + } + } + else { + SHT20.Sht201mSDelayCnt = 1000; + SHT20.Sht20Status = SHT20_INIT; + } + } +} + +void SHT201mSRoutine(void) +{ + if(SHT20.Sht201mSDelayCnt > 0) + SHT20.Sht201mSDelayCnt--; +} + diff --git a/Project/GateWay/source/Module/SHT20/SHT20.H b/Project/GateWay/source/Module/SHT20/SHT20.H new file mode 100644 index 0000000..b62142b --- /dev/null +++ b/Project/GateWay/source/Module/SHT20/SHT20.H @@ -0,0 +1,156 @@ +/*************************************************************** +* File name : SHT20.h +* Description : SHT20 Humidity and Temperature Sensors +* M C U : STM32L051XX +* Compiler : Keil uVision V5.00a +* Created by : +* Copyright : Copyright(c) 2018 +* Created data : 2018.03.16 +* Modified data: 2018.03.16 +* Vision : V1.0 +*****************************************************************/ + +/*****************Function Declaration*************************/ +/*----define to easier to use-----*/ +#include +#include "bsp.h" + +typedef enum { + SHT20_IDLE, + SHT20_INIT, + SHT20_READ_TEMPR, + SHT20_READ_HUMI, + SHT20_READ_DATA +}SHT20Status_m; + +typedef struct { + SHT20Status_m Sht20Status; + int Sht201mSDelayCnt; + float Tempreture; + float Humidity; + uint8_t Cmd; +}SHT20Var_t; + +#define SHT20_Write_Add 0x80 +#define SHT20_Read_Add 0x81 +#define SHT20_Measurement_RH_HM 0XE5 +#define SHT20_Measurement_T_HM 0XE3 +#define SHT20_Measurement_RH_NHM 0XF5 //·ÇÖ÷»úģʽµØÖ· +#define SHT20_Measurement_T_NHM 0XF3 //·ÇÖ÷»úģʽµØÖ· +#define SHT20_READ_REG 0XE7 +#define SHT20_WRITE_REG 0XE6 +#define SHT20_SOFT_RESET 0XFE + +//#define I2C_SOFTWARE + +#ifdef I2C_SOFTWARE + +#define SHT20_ADDRESS 0X80 + +#define SHT20_SDA_IN() I2C_SDA_IN() //ÉèÖÃÒý½ÅÊäÈëģʽ +#define SHT20_SDA_OUT() I2C_SDA_OUT() //ÉèÖÃÒý½ÅÊä³öģʽ +#define SHT20_SDA_GET() I2C_SDA_GET() + +#define SHT20_I2C_SDA_LOW() I2C_SDA_LOW() +#define SHT20_I2C_SCL_LOW() I2C_SCL_LOW() +#define SHT20_I2C_SDA_HIGH() I2C_SDA_HIGH() +#define SHT20_I2C_SCL_HIGH() I2C_SCL_HIGH() + + +#define SHT20_I2C_LOW() {SHT20_I2C_SDA_LOW();SHT20_I2C_SCL_LOW();} + +/*================================================================ +[ Name ]void IO_I2CInit(void) +[Function]I2C³õʼ»¯ ¿ÕÏÐ״̬ +[ Notes ] +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +void IO_I2CInit(void); + +/*================================================================ +[ Name ]I2CStart +[Function]¿ªÊ¼ +[ Notes ] +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +void I2CStart(void); + +/*================================================================ +[ Name ]I2CStop +[Function]½áÊø +[ Notes ] +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +void I2CStop(void); + +/*================================================================ +[ Name ]I2C_Write_Byte +[Function]дһ¸ö×Ö½Ú ·µ»ØACK»òNACK +[ Notes ]´Ó¸ßµ½µÍ·¢ +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +uint8_t I2C_Write_Byte(uint8_t Write_Byte); + +/*================================================================ +[ Name ]I2C_Read_Byte +[Function]¶ÁÒ»¸ö×Ö½Ú£¬Èë¿â²ÎÊýÓÃÓÚ¿ØÖÆÓ¦´ð״̬ ACK»òNAC +[ Notes ]´Ó¸ßµ½µÍ +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +uint8_t I2C_Read_Byte(uint8_t AckValue); + + +/*================================================================ +[ Name ]SHT20_SoftReset +[Function]SHT20Èí¼þ¸´Î» +[ Notes ]´Ó¸ßµ½µÍ +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +void SHT20_SoftReset(void); + +/*================================================================ +[ Name ]SET_Resolution +[Function]д¼Ä´æÆ÷ ÉèÖ÷ֱæÂÊ +[ Notes ]´Ó¸ßµ½µÍ +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +void SET_Resolution(void); + +/*================================================================ +[ Name ]ReadSht20 +[Function]·ÇÖ÷»úģʽ£¬¶ÁÈ¡ÎÂʪ¶ÈÖµ +[ Notes ]Èë¿Ú¿ØÖƶÁȡζȻòʪ¶È +[ Author ]LZH +[ Data ]2016.06.22 +================================================================*/ +float ReadSht20(char whatdo); + +float ReadSht20_Medium (void); + +#else + +#define SHT20_ADDRESS 0X40 + +#define Sht20_Reg_Write(DevAddr, RegData, rLen) I2C_Write(DevAddr, NULL, RegData, rLen) +#define Sht20_Read(DevAddr, RegAddr, rData, rLen) I2C_Read(DevAddr, RegAddr, rData, rLen) +#define Sht20_Delay(x) + +void SHT20_reset(void); + + +#endif +void SHT20_GetValue(float *Tempreture, float *Humidity); +void SHT20Start(void); +void SHT20LoopHandler(void); +void SHT201mSRoutine(void); + + + + diff --git a/Project/GateWay/source/Module/SX127x/sx127x.c b/Project/GateWay/source/Module/SX127x/sx127x.c new file mode 100644 index 0000000..5735d58 --- /dev/null +++ b/Project/GateWay/source/Module/SX127x/sx127x.c @@ -0,0 +1,659 @@ +#include "sx127x.h" +#include "DebugCmd.h" + +#if (LORA_MODULE == SX1278W1) +static Sx1276Type_t LoRaPara = { + .ucChannel = 4, + .dwFreqHz = FREQ_CENT, + .ucPower = 20, + .SignalBw = SX1276_BW_250K, + .SpreadFactor = SX1276_SF_512, + .ErrorCoding = SX1276_EC_4_6, + .RegPreamble = 10, + .ucOpModePrev = RFLR_OPMODE_STANDBY, + .bAntSwPrev = RF_ANT_RECEIVER, + .RegBuff = 0, + .State = SX1276_IDLE, + .ucRxPacketSize = 0, + .ucTxPacketSize = 0, + .RxCallBack = NULL, +}; + +void LoraReset(void) +{ + LORA_RESET_CLR(); + Ddl_Delay1ms(1); + LORA_RESET_SET(); +} + +///////////////////////////////////////////////// +void SX1276SetAntSw(Sx1276AntStatus_m Status) +{ + switch(Status){ + case RF_ANT_TRANSMITTER: + LORA_ANTTXEN(); + break; + case RF_ANT_RECEIVER: + LORA_ANTRXEN(); + break; + case RF_ANT_CLOSE: + LORA_ANTCLOSE(); + break; + } +} + +void SX1276ReadBuffer(uint8_t ucAddr, uint8_t *pucBuff, uint8_t ucLen) +{ + uint8_t ucCnt; + LORA_SPI_NSS_CLR(); + LORA_SPI_READ_WRITE(ucAddr & 0x7F); + for( ucCnt = 0; ucCnt < ucLen; ucCnt++ ){ + pucBuff[ucCnt] = LORA_SPI_READ_WRITE(0); + } + LORA_SPI_NSS_SET(); +} + +void SX1276WriteBuffer(uint8_t ucAddr, uint8_t *pucBuff, uint8_t ucLen) +{ + uint8_t ucCnt; + LORA_SPI_NSS_CLR(); + LORA_SPI_READ_WRITE(ucAddr | 0x80); + for( ucCnt = 0; ucCnt < ucLen; ucCnt++ ){ + LORA_SPI_READ_WRITE(pucBuff[ucCnt]); + } + LORA_SPI_NSS_SET(); + } + +void SX1276Write(uint8_t ucAddr, uint8_t ucData) +{ + SX1276WriteBuffer(ucAddr, &ucData, 1); +} + +void SX1276Read(uint8_t ucAddr, uint8_t * pucData) +{ + SX1276ReadBuffer(ucAddr, pucData, 1); +} + +void SX1276WriteFifo(uint8_t *pucBuff, uint8_t ucLen) +{ + SX1276WriteBuffer(0, pucBuff, ucLen); +} + +void SX1276ReadFifo(uint8_t *pucBuff, uint8_t ucLen) +{ + SX1276ReadBuffer(0, pucBuff, ucLen); +} + +///////////////////////////////////////////////// +void SX1276LoRaSetNbTrigPeaks(uint8_t ucValue) +{ + SX1276Read(0x31, &(LoRaPara.RegBuff.RegTestReserved31)); + LoRaPara.RegBuff.RegTestReserved31 = (LoRaPara.RegBuff.RegTestReserved31 & 0xF8) | ucValue; + SX1276Write(0x31, LoRaPara.RegBuff.RegTestReserved31 ); +} + +void SX1276LoRaSetSignalBandwidth(Sx1276BwType Bw) +{ + SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1)); + LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_BW_MASK) | Bw; + SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1); + LoRaPara.SignalBw = Bw; +} + +void SX1276LoRaSetSpreadingFactor(Sx1276SpreadFactorType Factor) +{ + if (Factor > SX1276_SF_4096){ + Factor = SX1276_SF_4096; + } + else if (Factor < SX1276_SF_64){ + Factor = SX1276_SF_64; + } + if (Factor == SX1276_SF_64){ + SX1276LoRaSetNbTrigPeaks(5); + } + else{ + SX1276LoRaSetNbTrigPeaks(3); + } + SX1276Read(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2)); + LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SF_MASK ) | Factor; + SX1276Write(REG_LR_MODEMCONFIG2, LoRaPara.RegBuff.RegModemConfig2); + LoRaPara.SpreadFactor = Factor; +} + +void SX1276LoRaSetErrorCoding(Sx1276ErrorCodingType Value){ + SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1)); + LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_CODINGRATE_MASK ) | Value; + SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1 ); + LoRaPara.ErrorCoding = Value; +} + +void SX1276LoRaSetFreqHz(uint32_t dwFreqHz) +{ + LoRaPara.dwFreqHz = dwFreqHz; + dwFreqHz = ( uint32_t )( ( double )dwFreqHz / ( double )FREQ_STEP ); + LoRaPara.RegBuff.RegFrfMsb = ( uint8_t )( ( dwFreqHz >> 16 ) & 0xFF ); + LoRaPara.RegBuff.RegFrfMid = ( uint8_t )( ( dwFreqHz >> 8 ) & 0xFF ); + LoRaPara.RegBuff.RegFrfLsb = ( uint8_t )( dwFreqHz & 0xFF ); + SX1276WriteBuffer(REG_LR_FRFMSB, &(LoRaPara.RegBuff.RegFrfMsb), 3); +} + +void SX1276LoRaSetSymbTimeout(uint16_t ucValue) +{ + SX1276ReadBuffer(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2), 2); + LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK) | (( ucValue >> 8) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ); + LoRaPara.RegBuff.RegSymbTimeoutLsb = ucValue & 0xFF; + SX1276WriteBuffer(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2), 2); +} + +void SX1276LoRaSetLowDatarateOptimize(bool bEnable) +{ + SX1276Read(REG_LR_MODEMCONFIG3, &(LoRaPara.RegBuff.RegModemConfig3)); + LoRaPara.RegBuff.RegModemConfig3 = (LoRaPara.RegBuff.RegModemConfig3 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) | ( bEnable << 3 ); + SX1276Write(REG_LR_MODEMCONFIG3, LoRaPara.RegBuff.RegModemConfig3); +} + +void SX1276LoRaSetPAOutput(uint8_t ucOutputPin) +{ + SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig)); + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_MASK ) | ucOutputPin; + SX1276Write(REG_LR_PACONFIG, LoRaPara.RegBuff.RegPaConfig ); +} + +void SX1276LoRaSetPa20dBm(bool bEnable) +{ + SX1276Read(REG_LR_PADAC, &(LoRaPara.RegBuff.RegPaDac)); + SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig)); + if ((LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST ) { + if( bEnable == true ){ + LoRaPara.RegBuff.RegPaDac = 0x87; + } + } + else{ + LoRaPara.RegBuff.RegPaDac = 0x84; + } + SX1276Write(REG_LR_PADAC, LoRaPara.RegBuff.RegPaDac ); +} + +void SX1276LoRaSetRfPower(int8_t sbPower) +{ + SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig)); + SX1276Read(REG_LR_PADAC, &(LoRaPara.RegBuff.RegPaDac)); + if ((LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST ) { + if ((LoRaPara.RegBuff.RegPaDac & 0x87) == 0x87){ + if( sbPower < 5 ){ + sbPower = 5; + } + if( sbPower > 20){ + sbPower = 20; + } + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70; + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | + ( uint8_t )( ( uint16_t )( sbPower - 5 ) & 0x0F ); + } + else{ + if( sbPower < 2){ + sbPower = 2; + } + if( sbPower > 17){ + sbPower = 17; + } + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70; + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | + ( uint8_t )( ( uint16_t )( sbPower - 2 ) & 0x0F ); + } + } + else{ + if( sbPower < -1){ + sbPower = -1; + } + if( sbPower > 14){ + sbPower = 14; + } + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70; + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | + ( uint8_t )( ( uint16_t )( sbPower + 1 ) & 0x0F ); + } + SX1276Write(REG_LR_PACONFIG, LoRaPara.RegBuff.RegPaConfig); + LoRaPara.ucPower = sbPower; +} + +void SX1276LoRaSetOpMode(Sx1276OpModeType ucOpMode) +{ + Sx1276AntStatus_m bAntSwStatus = RF_ANT_RECEIVER; + LoRaPara.ucOpModePrev = LoRaPara.RegBuff.RegOpMode & ~RFLR_OPMODE_MASK; + if( ucOpMode != LoRaPara.ucOpModePrev){ + if(ucOpMode == RFLR_OPMODE_TRANSMITTER){ + LORA_RXEN_CLR(); + LORA_TXEN_SET(); + bAntSwStatus = RF_ANT_TRANSMITTER; + } + else if(ucOpMode == RFLR_OPMODE_RECEIVER){ + LORA_TXEN_CLR(); + LORA_RXEN_SET(); + bAntSwStatus = RF_ANT_RECEIVER; + } + else { + LORA_TXEN_CLR(); + LORA_RXEN_CLR(); + bAntSwStatus = RF_ANT_CLOSE; + } + if( bAntSwStatus != LoRaPara.bAntSwPrev ){ + LoRaPara.bAntSwPrev = bAntSwStatus; + SX1276SetAntSw(bAntSwStatus); + } + LoRaPara.RegBuff.RegOpMode = (LoRaPara.RegBuff.RegOpMode & RFLR_OPMODE_MASK ) | ucOpMode; + SX1276Write( REG_LR_OPMODE, LoRaPara.RegBuff.RegOpMode); + } +} +//////////////////////////////////////////////////////////////// + +void Sx1276LoRaEnterRx(void) +{ + uint8_t ucCnt; + SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY); + LoRaPara.RegBuff.RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | RFLR_IRQFLAGS_VALIDHEADER | RFLR_IRQFLAGS_TXDONE; + SX1276Write(REG_LR_IRQFLAGSMASK, LoRaPara.RegBuff.RegIrqFlagsMask); + LoRaPara.RegBuff.RegHopPeriod = 255; + SX1276Write(REG_LR_HOPPERIOD, LoRaPara.RegBuff.RegHopPeriod ); + // RxDone RxTimeout FhssChangeChannel ValidHeader + LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_01 | RFLR_DIOMAPPING1_DIO3_01; + // CadDetected ModeReady + LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00; + SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2); + LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoRxBaseAddr; + SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr); + SX1276LoRaSetOpMode(RFLR_OPMODE_RECEIVER); + for (ucCnt=0; ucCnt< LORA_BUFF_SIZE; ucCnt++){ + LoRaPara.RxTxBuff[ucCnt] = 0; + } + LoRaPara.State = SX1276_IDLE;//COMST_RX + uint8_t temp; + SX1276Read(REG_LR_IRQFLAGS, &temp); +} + +///////////////////////////////////////////////// +void Sx1276LoRaInit(DataRevCallBack RxCallBack) +{ + if(RxCallBack != NULL) { + LoRaPara.RxCallBack = RxCallBack; + } + LoraReset(); + SX1276LoRaSetOpMode(RFLR_OPMODE_SLEEP); + LoRaPara.RegBuff.RegOpMode = (LoRaPara.RegBuff.RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON; + SX1276Write(REG_LR_OPMODE, LoRaPara.RegBuff.RegOpMode ); + SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY); + // RxDone RxTimeout FhssChangeChannel ValidHeader + LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_01; + // CadDetected ModeReady + LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00; + SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2 ); + SX1276ReadBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS); + LoRaPara.State = SX1276_BUSY; + SX1276Read(REG_LR_VERSION, &(LoRaPara.RegBuff.RegVersion)); + SX1276ReadBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS); + LoRaPara.RegBuff.RegLna = RFLR_LNA_GAIN_G1; + SX1276WriteBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS); + + // set the RF settings + SX1276LoRaWriteChannel(LoRaPara.ucChannel); + //SX1276LoRaSetFreqHz(LoRaPara.dwFreqHz); + //REG_LR_MODEMCONFIG1 + SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1)); + //SignalBandwidth + LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_BW_MASK ) | LoRaPara.SignalBw; + //ErrorCoding + LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_CODINGRATE_MASK ) | LoRaPara.ErrorCoding; + //IMPLICITHEADER + LoRaPara.RegBuff.RegModemConfig1 = LoRaPara.RegBuff.RegModemConfig1 | RFLR_MODEMCONFIG1_IMPLICITHEADER_ON; + SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1); + //REG_LR_MODEMCONFIG2 + SX1276Read(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2)); + //SpreadingFactor + if( LoRaPara.SpreadFactor == SX1276_SF_64){ + SX1276LoRaSetNbTrigPeaks(5); + SX1276LoRaSetLowDatarateOptimize(true); + } + else{ + SX1276LoRaSetNbTrigPeaks(3); + SX1276LoRaSetLowDatarateOptimize(false); //µÍÊý¾ÝËÙÂÊÉèÖà + } + LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SF_MASK ) | LoRaPara.SpreadFactor; + //PacketCrcOn + LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) | SX1276_CRC_ON; //SX1276_CRC_OFF + SX1276Write(REG_LR_MODEMCONFIG2, LoRaPara.RegBuff.RegModemConfig2); + uint8_t Config2 = 0; + SX1276Read(REG_LR_MODEMCONFIG2, &Config2); + if(LoRaPara.RegBuff.RegModemConfig2 == Config2) { + Debug_Printf("Lora OK!\r\n"); + } + else { + Debug_Printf("Lora Error!\r\n"); + } + SX1276LoRaSetSymbTimeout(0x3FF); + LoRaPara.RegBuff.RegPreambleMsb= (LoRaPara.RegPreamble >> 8) & 0x00ff; + LoRaPara.RegBuff.RegPreambleLsb= LoRaPara.RegPreamble & 0x00ff; + SX1276Write(REG_LR_PREAMBLEMSB, LoRaPara.RegBuff.RegPreambleMsb); + SX1276Write(REG_LR_PREAMBLELSB, LoRaPara.RegBuff.RegPreambleLsb); + SX1276Write(REG_LR_PAYLOADLENGTH, LORA_BUFF_SIZE); + SX1276Write(REG_LR_PAYLOADMAXLENGTH, LORA_BUFF_SIZE); + LoRaPara.RegBuff.RegPayloadLength = LORA_BUFF_SIZE; + + #ifndef USE_LORA_860_PA + if(LoRaPara.dwFreqHz > 860000000 ){ + SX1276LoRaSetPAOutput(RFLR_PACONFIG_PASELECT_RFO); + SX1276LoRaSetPa20dBm(false); + LoRaPara.ucPower = 14; + } + else + #endif + { + SX1276LoRaSetPAOutput(RFLR_PACONFIG_PASELECT_PABOOST); + SX1276LoRaSetPa20dBm(true); + LoRaPara.ucPower = 20; + } + SX1276LoRaSetRfPower(LoRaPara.ucPower); + SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY); + Sx1276LoRaEnterRx(); +} + +void IsrSx1276LoRaTxRx(GateWayPara GateWay) +{ + switch (LoRaPara.State){ + case SX1276_IDLE: + case SX1276_RX: + // Clear Irq + LORA_RXLED_ON(); + do { + SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE); + SX1276Read(REG_LR_IRQFLAGS, &(LoRaPara.RegBuff.RegIrqFlags)); + if((LoRaPara.RegBuff.RegIrqFlags & RFLR_IRQFLAGS_RXDONE) != RFLR_IRQFLAGS_RXDONE) + break; + }while(1); + if((LoRaPara.RegBuff.RegIrqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR ) == RFLR_IRQFLAGS_PAYLOADCRCERROR) { + // Clear Irq + SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR); + LoRaPara.State = SX1276_IDLE; + break; + } + SX1276Read(REG_LR_PKTSNRVALUE, &(LoRaPara.RegBuff.RegPktSnrValue)); + SX1276Read(REG_LR_RSSIVALUE, &(LoRaPara.RegBuff.RegRssiValue)); + SX1276Read(REG_LR_PKTRSSIVALUE, &(LoRaPara.RegBuff.RegPktRssiValue)); + SX1276Read(REG_LR_FIFORXCURRENTADDR, &(LoRaPara.RegBuff.RegFifoRxCurrentAddr)); + SX1276Read(REG_LR_NBRXBYTES, &(LoRaPara.RegBuff.RegNbRxBytes)); + LoRaPara.ucRxPacketSize = LoRaPara.RegBuff.RegNbRxBytes; + LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoRxCurrentAddr; + SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr); + SX1276ReadFifo(LoRaPara.RxTxBuff, (LoRaPara.ucRxPacketSize > LORA_BUFF_SIZE) ? LORA_BUFF_SIZE : LoRaPara.ucRxPacketSize); + uint8_t ucLen; + if(LoRaPara.ucRxPacketSize < LORA_BUFF_SIZE) { + ucLen= LoRaPara.ucRxPacketSize; + } + else { + ucLen= LORA_BUFF_SIZE; + } + LoRaPara.RxTxBuff[ucLen] = 0; + if(LoRaPara.RxCallBack != NULL) + LoRaPara.RxRet = LoRaPara.RxCallBack(GateWay, LoRaPara.RxTxBuff, ucLen); + + LoRaPara.ucRxPacketSize = 0; + LoRaPara.State = SX1276_IDLE; + LORA_RXLED_OFF(); + break; + case SX1276_TX: + // Clear Irq + SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE); + LORA_TXLED_OFF(); + Sx1276LoRaEnterRx(); + break; + default: + break; + } +} + +void Sx1276LoRaLoopHandler(GateWayPara GateWay) +{ + if(LORA_GETDIO0() > 0){ // RxDone or TxDone + IsrSx1276LoRaTxRx(GateWay); + } +} +void Sx1276LoRaSendBuffer(uint8_t* pucBuff, uint16_t ucLen) +{ + LoRaPara.State = SX1276_BUSY; + if (ucLen > LORA_BUFF_SIZE){ + ucLen = LORA_BUFF_SIZE; + } + LoRaPara.ucTxPacketSize = ucLen; + while(ucLen--){ + LoRaPara.RxTxBuff[ucLen] = pucBuff[ucLen]; + }; + SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY); + LoRaPara.RegBuff.RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | RFLR_IRQFLAGS_RXDONE | RFLR_IRQFLAGS_PAYLOADCRCERROR | RFLR_IRQFLAGS_VALIDHEADER; + //LoRaPara.RegBuff.RegHopPeriod = 0; + //SX1276Write(REG_LR_HOPPERIOD, LoRaPara.RegBuff.RegHopPeriod); + SX1276Write(REG_LR_IRQFLAGSMASK, LoRaPara.RegBuff.RegIrqFlagsMask); + // Initializes the payload size + LoRaPara.RegBuff.RegPayloadLength = LoRaPara.ucTxPacketSize; + SX1276Write(REG_LR_PAYLOADLENGTH, LoRaPara.RegBuff.RegPayloadLength); + LoRaPara.RegBuff.RegFifoTxBaseAddr = 0x00; // Full buffer used for Tx + SX1276Write(REG_LR_FIFOTXBASEADDR, LoRaPara.RegBuff.RegFifoTxBaseAddr); + LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoTxBaseAddr; + SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr); + // Write payload buffer to LORA modem + SX1276WriteFifo(LoRaPara.RxTxBuff, LoRaPara.RegBuff.RegPayloadLength); + // TxDone RxTimeout FhssChangeChannel ValidHeader + LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_01; + // PllLock Mode Ready + LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_01 | RFLR_DIOMAPPING2_DIO5_00; + SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2); + SX1276LoRaSetOpMode(RFLR_OPMODE_TRANSMITTER); + uint8_t temp; + SX1276Read(REG_LR_IRQFLAGS, &temp); + LORA_TXLED_ON(); + LoRaPara.State = SX1276_TX; +} + +void Sx1276LoRaSleep(void) +{ + SX1276LoRaSetOpMode(RFLR_OPMODE_SLEEP);//RFLR_OPMODE_STANDBY +} + +void Sx1276LoRaWakeup(void) +{ + Sx1276LoRaEnterRx(); +} + +//////////////////////////////////////// +//ÅäÖñ¾²ã²ÎÊýµÄº¯Êý +//ƵµÀ±í +const uint32_t gdwSx1276ChannelTbl[SX1276_CHANNEL_MAX]={ + FREQ_CENT-FREQ_DEV*8, FREQ_CENT-FREQ_DEV*7, FREQ_CENT-FREQ_DEV*6, FREQ_CENT-FREQ_DEV*5, + FREQ_CENT-FREQ_DEV*4, FREQ_CENT-FREQ_DEV*3, FREQ_CENT-FREQ_DEV*2, FREQ_CENT-FREQ_DEV*1, + FREQ_CENT+FREQ_DEV*0, FREQ_CENT+FREQ_DEV*1, FREQ_CENT+FREQ_DEV*2, FREQ_CENT+FREQ_DEV*3, + FREQ_CENT+FREQ_DEV*4, FREQ_CENT+FREQ_DEV*5, FREQ_CENT+FREQ_DEV*6, FREQ_CENT+FREQ_DEV*7, + FREQ_CENT+FREQ_DEV*8 +}; + +//LORAPT_CHANNEL +uint8_t SX1276LoRaReadChannel(void) +{ + return LoRaPara.ucChannel; +} + +bool SX1276LoRaWriteChannel(uint8_t Channel) +{ + if(Channel > SX1276_CHANNEL_MAX) { + return false; + } + + LoRaPara.dwFreqHz = gdwSx1276ChannelTbl[Channel]; + SX1276LoRaSetFreqHz(LoRaPara.dwFreqHz); + + return true; +} + +//LORAPT_FREQ, +uint32_t SX1276LoRaReadFreq(void) +{ + return LoRaPara.dwFreqHz; +} + +void SX1276LoRaWriteFreq(uint32_t Freq) +{ + SX1276LoRaSetFreqHz(Freq); +} + +//LORAPT_BW, +uint32_t SX1276LoRaReadBw(void) +{ + return LoRaPara.SignalBw; +} + +void SX1276LoRaWriteBw(Sx1276BwType SignalBw) +{ + LoRaPara.SignalBw = SignalBw; + SX1276LoRaSetSignalBandwidth(SignalBw); +} + +//LORAPT_SF, +uint8_t SX1276LoRaReadSf(void) +{ + return LoRaPara.SpreadFactor; +} + +void SX1276LoRaWriteSf(Sx1276SpreadFactorType SpreadFactor) +{ + LoRaPara.SpreadFactor = SpreadFactor; + SX1276LoRaSetSpreadingFactor(LoRaPara.SpreadFactor); +} + +//LORAPT_EC, +uint8_t SX1276LoRaReadEc(void) +{ + return LoRaPara.ErrorCoding; +} + +void SX1276LoRaWriteEc(Sx1276ErrorCodingType ErrorCoding) +{ + LoRaPara.ErrorCoding = ErrorCoding; + SX1276LoRaSetErrorCoding(ErrorCoding); +} + +//LORAPT_RSSI, +uint32_t SX1276LoRaParaReadRssi(void) +{ + uint32_t rssi; + + SX1276Read(REG_LR_PKTRSSIVALUE, &(LoRaPara.RegBuff.RegPktRssiValue)); + SX1276Read(REG_LR_RSSIVALUE, &(LoRaPara.RegBuff.RegRssiValue)); + rssi = (uint16_t)(LoRaPara.RegBuff.RegPktSnrValue)<<16; + rssi |= (uint16_t)(LoRaPara.RegBuff.RegRssiValue)<<8; + rssi |= LoRaPara.RegBuff.RegPktRssiValue; + return rssi; +} + +uint8_t SX1276LoRaReadRssiPkt(void) +{ + uint8_t RssiPkt; + + SX1276Read(REG_LR_PKTRSSIVALUE, &LoRaPara.RegBuff.RegPktRssiValue); + RssiPkt = LoRaPara.RegBuff.RegPktRssiValue; + return RssiPkt; +} + +//LORAPT_POWER, +void SX1276LoRaWritePwr(int8_t Pwr) +{ + SX1276LoRaSetRfPower(Pwr); +} + +//LORAPT_SET_RX, +void SX1276LoRaWriteRx(void) +{ + Sx1276LoRaEnterRx(); +} + +//LORAPT_SET_SLEEP,true-Sleep, false-Wakeup +void SX1276LoRaWriteSleep(bool Sleep) +{ + if(Sleep){ + Sx1276LoRaSleep(); + } + else { + Sx1276LoRaWakeup(); + } +} + +Sx1276StateType_t SX1276LoRaReadStatus(void) +{ + return LoRaPara.State; +} + +///////////////RSSI Calc/////////////// +void SX1276LoCalcRssiSnr(int16_t *pswRssi, int8_t *psbSnr) +{ + int8_t sbSnr= LoRaPara.RegBuff.RegPktSnrValue & 0x80 ? (-1)*((int8_t)(((~LoRaPara.RegBuff.RegPktSnrValue+ 1)& 0xFF)/4)): (~LoRaPara.RegBuff.RegPktSnrValue& 0xFF)/4; + if (sbSnr > 0) { + *pswRssi= RSSI_OFFSET_LF+ LoRaPara.RegBuff.RegPktRssiValue; + } + else { + *pswRssi= NOISE_ABSOLUTE_ZERO + 10 + SIGNAL_BW_LOG_125KHZ + NOISE_FIGURE_LF + sbSnr; + } + *psbSnr= sbSnr; +} + +int GetSx1276RxRetValue(void) +{ + return LoRaPara.RxRet; +} + +void Sx1276RxRetValue(void) +{ + LoRaPara.RxRet = -1; +} + +bool LoraSetChannel(uint8_t Channel) +{ + if(Channel > 16) + return false; + LoRaPara.ucChannel = Channel; + return true; +} + +bool LoraSetPower(uint8_t Power) +{ + if(Power > 20) + return false; + LoRaPara.ucPower = Power; + return true; +} + +bool LoraSetSignalBw(uint8_t SignalBw) +{ + if(SignalBw > 9) + return false; + LoRaPara.SignalBw = (SignalBw << 4); + return true; +} + +bool LoraSetSpreadFactor(uint8_t SpreadFactor) +{ + if(SpreadFactor < 4 || SpreadFactor > 12) + return false; + LoRaPara.SpreadFactor = (SpreadFactor << 4); + return true; +} + +bool LoraSetErrorCoding(uint8_t ErrorCoding) +{ + if(ErrorCoding == 0 || ErrorCoding > 4) + return false; + LoRaPara.ErrorCoding = ErrorCoding << 1; + return true; +} + +bool LoraSetRegPreamble(uint8_t RegPreamble) +{ + LoRaPara.RegPreamble = RegPreamble; + return true; +} +#endif diff --git a/Project/GateWay/source/Module/SX127x/sx127x.h b/Project/GateWay/source/Module/SX127x/sx127x.h new file mode 100644 index 0000000..2683723 --- /dev/null +++ b/Project/GateWay/source/Module/SX127x/sx127x.h @@ -0,0 +1,840 @@ +#ifndef __SX127X_H +#define __SX127X_H + +#include "bsp.h" +#include "Public.h" +#include "main.h" + +//Constant values need to compute the RSSI value +#define RSSI_OFFSET_LF -164 +#define RSSI_OFFSET_HF -157 +#define NOISE_ABSOLUTE_ZERO -174 +#define NOISE_FIGURE_LF 4 +#define NOISE_FIGURE_HF 6 +#define SIGNAL_BW_LOG_125KHZ 5 + +//SX1276 definitions +#define XTAL_FREQ 32000000 +#define FREQ_STEP 61.03515625 + +//SX1276 Internal registers Address +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +#define REG_LR_BANDSETTING 0x04 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_NBRXBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_MODEMCONFIG3 0x26 +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_PLLHOP 0x44 +#define REG_LR_TCXO 0x4B +#define REG_LR_PADAC 0x4D +#define REG_LR_FORMERTEMP 0x5B +#define REG_LR_BITRATEFRAC 0x5D +#define REG_LR_AGCREF 0x61 +#define REG_LR_AGCTHRESH1 0x62 +#define REG_LR_AGCTHRESH2 0x63 +#define REG_LR_AGCTHRESH3 0x64 + +//RegOpMode +typedef enum{ + RFLR_OPMODE_LONGRANGEMODE_MASK =0x7F, + RFLR_OPMODE_LONGRANGEMODE_OFF =0x00, // Default + RFLR_OPMODE_LONGRANGEMODE_ON =0x80, + RFLR_OPMODE_ACCESSSHAREDREG_MASK =0xBF, + RFLR_OPMODE_ACCESSSHAREDREG_ENABLE =0x40, + RFLR_OPMODE_ACCESSSHAREDREG_DISABLE =0x00, // Default + RFLR_OPMODE_FREQMODE_ACCESS_MASK =0xF7, + RFLR_OPMODE_FREQMODE_ACCESS_LF =0x08, // Default + RFLR_OPMODE_FREQMODE_ACCESS_HF =0x00, + RFLR_OPMODE_MASK =0xF8, + RFLR_OPMODE_SLEEP =0x00, + RFLR_OPMODE_STANDBY =0x01, // Default + RFLR_OPMODE_SYNTHESIZER_TX =0x02, + RFLR_OPMODE_TRANSMITTER =0x03, + RFLR_OPMODE_SYNTHESIZER_RX =0x04, + RFLR_OPMODE_RECEIVER =0x05, + // LoRa specific modes + RFLR_OPMODE_RECEIVER_SINGLE =0x06, + RFLR_OPMODE_CAD =0x07 +}Sx1276OpModeType; + +//RegBandSetting +#define RFLR_BANDSETTING_MASK 0x3F +#define RFLR_BANDSETTING_AUTO 0x00 // Default +#define RFLR_BANDSETTING_DIV_BY_1 0x40 +#define RFLR_BANDSETTING_DIV_BY_2 0x80 +#define RFLR_BANDSETTING_DIV_BY_6 0xC0 + +//RegFrf (MHz) +#define RFLR_FRFMSB_434_MHZ 0x6C // Default +#define RFLR_FRFMID_434_MHZ 0x80 // Default +#define RFLR_FRFLSB_434_MHZ 0x00 // Default +#define RFLR_FRFMSB_863_MHZ 0xD7 +#define RFLR_FRFMID_863_MHZ 0xC0 +#define RFLR_FRFLSB_863_MHZ 0x00 +#define RFLR_FRFMSB_864_MHZ 0xD8 +#define RFLR_FRFMID_864_MHZ 0x00 +#define RFLR_FRFLSB_864_MHZ 0x00 +#define RFLR_FRFMSB_865_MHZ 0xD8 +#define RFLR_FRFMID_865_MHZ 0x40 +#define RFLR_FRFLSB_865_MHZ 0x00 +#define RFLR_FRFMSB_866_MHZ 0xD8 +#define RFLR_FRFMID_866_MHZ 0x80 +#define RFLR_FRFLSB_866_MHZ 0x00 +#define RFLR_FRFMSB_867_MHZ 0xD8 +#define RFLR_FRFMID_867_MHZ 0xC0 +#define RFLR_FRFLSB_867_MHZ 0x00 +#define RFLR_FRFMSB_868_MHZ 0xD9 +#define RFLR_FRFMID_868_MHZ 0x00 +#define RFLR_FRFLSB_868_MHZ 0x00 +#define RFLR_FRFMSB_869_MHZ 0xD9 +#define RFLR_FRFMID_869_MHZ 0x40 +#define RFLR_FRFLSB_869_MHZ 0x00 +#define RFLR_FRFMSB_870_MHZ 0xD9 +#define RFLR_FRFMID_870_MHZ 0x80 +#define RFLR_FRFLSB_870_MHZ 0x00 +#define RFLR_FRFMSB_902_MHZ 0xE1 +#define RFLR_FRFMID_902_MHZ 0x80 +#define RFLR_FRFLSB_902_MHZ 0x00 +#define RFLR_FRFMSB_903_MHZ 0xE1 +#define RFLR_FRFMID_903_MHZ 0xC0 +#define RFLR_FRFLSB_903_MHZ 0x00 +#define RFLR_FRFMSB_904_MHZ 0xE2 +#define RFLR_FRFMID_904_MHZ 0x00 +#define RFLR_FRFLSB_904_MHZ 0x00 +#define RFLR_FRFMSB_905_MHZ 0xE2 +#define RFLR_FRFMID_905_MHZ 0x40 +#define RFLR_FRFLSB_905_MHZ 0x00 +#define RFLR_FRFMSB_906_MHZ 0xE2 +#define RFLR_FRFMID_906_MHZ 0x80 +#define RFLR_FRFLSB_906_MHZ 0x00 +#define RFLR_FRFMSB_907_MHZ 0xE2 +#define RFLR_FRFMID_907_MHZ 0xC0 +#define RFLR_FRFLSB_907_MHZ 0x00 +#define RFLR_FRFMSB_908_MHZ 0xE3 +#define RFLR_FRFMID_908_MHZ 0x00 +#define RFLR_FRFLSB_908_MHZ 0x00 +#define RFLR_FRFMSB_909_MHZ 0xE3 +#define RFLR_FRFMID_909_MHZ 0x40 +#define RFLR_FRFLSB_909_MHZ 0x00 +#define RFLR_FRFMSB_910_MHZ 0xE3 +#define RFLR_FRFMID_910_MHZ 0x80 +#define RFLR_FRFLSB_910_MHZ 0x00 +#define RFLR_FRFMSB_911_MHZ 0xE3 +#define RFLR_FRFMID_911_MHZ 0xC0 +#define RFLR_FRFLSB_911_MHZ 0x00 +#define RFLR_FRFMSB_912_MHZ 0xE4 +#define RFLR_FRFMID_912_MHZ 0x00 +#define RFLR_FRFLSB_912_MHZ 0x00 +#define RFLR_FRFMSB_913_MHZ 0xE4 +#define RFLR_FRFMID_913_MHZ 0x40 +#define RFLR_FRFLSB_913_MHZ 0x00 +#define RFLR_FRFMSB_914_MHZ 0xE4 +#define RFLR_FRFMID_914_MHZ 0x80 +#define RFLR_FRFLSB_914_MHZ 0x00 +#define RFLR_FRFMSB_915_MHZ 0xE4 // Default +#define RFLR_FRFMID_915_MHZ 0xC0 // Default +#define RFLR_FRFLSB_915_MHZ 0x00 // Default +#define RFLR_FRFMSB_916_MHZ 0xE5 +#define RFLR_FRFMID_916_MHZ 0x00 +#define RFLR_FRFLSB_916_MHZ 0x00 +#define RFLR_FRFMSB_917_MHZ 0xE5 +#define RFLR_FRFMID_917_MHZ 0x40 +#define RFLR_FRFLSB_917_MHZ 0x00 +#define RFLR_FRFMSB_918_MHZ 0xE5 +#define RFLR_FRFMID_918_MHZ 0x80 +#define RFLR_FRFLSB_918_MHZ 0x00 +#define RFLR_FRFMSB_919_MHZ 0xE5 +#define RFLR_FRFMID_919_MHZ 0xC0 +#define RFLR_FRFLSB_919_MHZ 0x00 +#define RFLR_FRFMSB_920_MHZ 0xE6 +#define RFLR_FRFMID_920_MHZ 0x00 +#define RFLR_FRFLSB_920_MHZ 0x00 +#define RFLR_FRFMSB_921_MHZ 0xE6 +#define RFLR_FRFMID_921_MHZ 0x40 +#define RFLR_FRFLSB_921_MHZ 0x00 +#define RFLR_FRFMSB_922_MHZ 0xE6 +#define RFLR_FRFMID_922_MHZ 0x80 +#define RFLR_FRFLSB_922_MHZ 0x00 +#define RFLR_FRFMSB_923_MHZ 0xE6 +#define RFLR_FRFMID_923_MHZ 0xC0 +#define RFLR_FRFLSB_923_MHZ 0x00 +#define RFLR_FRFMSB_924_MHZ 0xE7 +#define RFLR_FRFMID_924_MHZ 0x00 +#define RFLR_FRFLSB_924_MHZ 0x00 +#define RFLR_FRFMSB_925_MHZ 0xE7 +#define RFLR_FRFMID_925_MHZ 0x40 +#define RFLR_FRFLSB_925_MHZ 0x00 +#define RFLR_FRFMSB_926_MHZ 0xE7 +#define RFLR_FRFMID_926_MHZ 0x80 +#define RFLR_FRFLSB_926_MHZ 0x00 +#define RFLR_FRFMSB_927_MHZ 0xE7 +#define RFLR_FRFMID_927_MHZ 0xC0 +#define RFLR_FRFLSB_927_MHZ 0x00 +#define RFLR_FRFMSB_928_MHZ 0xE8 +#define RFLR_FRFMID_928_MHZ 0x00 +#define RFLR_FRFLSB_928_MHZ 0x00 + +//RegPaConfig +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default +#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +//RegPaRamp +#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF +#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 +#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +//RegOcp +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +//RegLna +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 +#define RFLR_LNA_BOOST_LF_MASK 0xE7 +#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default +#define RFLR_LNA_BOOST_LF_GAIN 0x08 +#define RFLR_LNA_BOOST_LF_IP3 0x10 +#define RFLR_LNA_BOOST_LF_BOOST 0x18 +#define RFLR_LNA_RXBANDFORCE_MASK 0xFB +#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04 +#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default +#define RFLR_LNA_BOOST_HF_MASK 0xFC +#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default +#define RFLR_LNA_BOOST_HF_ON 0x03 + +//RegFifoAddrPtr +#define RFLR_FIFOADDRPTR 0x00 // Default + +//RegFifoTxBaseAddr +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +//RegFifoTxBaseAddr +#define RFLR_FIFORXBASEADDR 0x00 // Default + +//RegFifoRxCurrentAddr (Read Only) + +//RegIrqFlagsMask +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +//RegIrqFlags +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + + //RegModemStat (Read Only) +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +//RegModemConfig1 +#define RFLR_MODEMCONFIG1_BW_MASK 0x0F +#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 +#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 +#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 +#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 +#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 +#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x00 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x01 // Default + + //RegModemConfig2 +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 + +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 + +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + + +//RegHopChannel (Read Only) +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40 +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + + +//RegSymbTimeoutLsb +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +//RegPreambleLengthMsb +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +//RegPreambleLengthLsb +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +//RegPayloadLength +#define RFLR_PAYLOADLENGTH 0x0E // Default + +//RegPayloadMaxLength +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +//RegHopPeriod +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + + +//RegDioMapping1 +//DIO0 +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 +//DIO1 +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 +//DIO2 +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C +//DIO3 +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +//RegDioMapping2 +//DIO4 +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 +//DIO5 +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 +//MAP +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +// RegPllHop +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +//RegTcxo +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +//RegPaDac +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +//RegPll +#define RFLR_PLL_BANDWIDTH_MASK 0x3F +#define RFLR_PLL_BANDWIDTH_75 0x00 +#define RFLR_PLL_BANDWIDTH_150 0x40 +#define RFLR_PLL_BANDWIDTH_225 0x80 +#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default + +//RegPllLowPn +#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 +#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 +#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 +#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +//RegModemConfig3 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 + +//REGISTER +typedef struct _Sx1276RegType{ + uint8_t RegFifo; // 0x00 + // Common settings + uint8_t RegOpMode; // 0x01 + uint8_t RegRes02; // 0x02 + uint8_t RegRes03; // 0x03 + uint8_t RegBandSetting; // 0x04 + uint8_t RegRes05; // 0x05 + uint8_t RegFrfMsb; // 0x06 + uint8_t RegFrfMid; // 0x07 + uint8_t RegFrfLsb; // 0x08 + // Tx settings + uint8_t RegPaConfig; // 0x09 + uint8_t RegPaRamp; // 0x0A + uint8_t RegOcp; // 0x0B + // Rx settings + uint8_t RegLna; // 0x0C + // LoRa registers + uint8_t RegFifoAddrPtr; // 0x0D + uint8_t RegFifoTxBaseAddr; // 0x0E + uint8_t RegFifoRxBaseAddr; // 0x0F + uint8_t RegFifoRxCurrentAddr; // 0x10 + uint8_t RegIrqFlagsMask; // 0x11 + uint8_t RegIrqFlags; // 0x12 + uint8_t RegNbRxBytes; // 0x13 + uint8_t RegRxHeaderCntValueMsb; // 0x14 + uint8_t RegRxHeaderCntValueLsb; // 0x15 + uint8_t RegRxPacketCntValueMsb; // 0x16 + uint8_t RegRxPacketCntValueLsb; // 0x17 + uint8_t RegModemStat; // 0x18 + uint8_t RegPktSnrValue; // 0x19 + uint8_t RegPktRssiValue; // 0x1A + uint8_t RegRssiValue; // 0x1B + uint8_t RegHopChannel; // 0x1C + uint8_t RegModemConfig1; // 0x1D + uint8_t RegModemConfig2; // 0x1E + uint8_t RegSymbTimeoutLsb; // 0x1F + uint8_t RegPreambleMsb; // 0x20 + uint8_t RegPreambleLsb; // 0x21 + uint8_t RegPayloadLength; // 0x22 + uint8_t RegMaxPayloadLength; // 0x23 + uint8_t RegHopPeriod; // 0x24 + uint8_t RegFifoRxByteAddr; // 0x25 + uint8_t RegModemConfig3; // 0x26 + uint8_t RegTestReserved27[0x30 - 0x27]; // 0x27-0x30 + uint8_t RegTestReserved31; // 0x31 + uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x40 + // I/O settings + uint8_t RegDioMapping1; // 0x40 + uint8_t RegDioMapping2; // 0x41 + // Version + uint8_t RegVersion; // 0x42 + // Additional settings + uint8_t RegAgcRef; // 0x43 + uint8_t RegAgcThresh1; // 0x44 + uint8_t RegAgcThresh2; // 0x45 + uint8_t RegAgcThresh3; // 0x46 + // Test + uint8_t RegTestReserved47[0x4B - 0x47]; // 0x47-0x4A + // Additional settings + uint8_t RegPllHop; // 0x4B + uint8_t RegTestReserved4C; // 0x4C + uint8_t RegPaDac; // 0x4D + // Test + //uint8_t RegTestReserved4E[0x58-0x4E]; // 0x4E-0x57 + // Additional settings + //uint8_t RegTcxo; // 0x58 + // Test + //uint8_t RegTestReserved59; // 0x59 + // Test + //uint8_t RegTestReserved5B; // 0x5B + // Additional settings + //uint8_t RegPll; // 0x5C + // Test + //uint8_t RegTestReserved5D; // 0x5D + // Additional settings + //uint8_t RegPllLowPn; // 0x5E + // Test + //uint8_t RegTestReserved5F[0x6C - 0x5F]; // 0x5F-0x6B + // Additional settings + //uint8_t RegFormerTemp; // 0x6C + // Test + //uint8_t RegTestReserved6D[0x71 - 0x6D]; // 0x6D-0x70 +}Sx1276RegType; + +#define SIZE_OF_REGISTERS (sizeof(Sx1276RegType)) + +//RF state machine +typedef enum{ + RFLR_STATE_IDLE, + RFLR_STATE_RX_RUNNING, + RFLR_STATE_TX_RUNNING, +}LRStateType; + +typedef enum{ + RADIO_RESET_OFF, + RADIO_RESET_ON, +}tRadioResetState; + +typedef enum{ + RF_IDLE, + RF_BUSY, + RF_RX_DONE, + RF_RX_TIMEOUT, + RF_TX_DONE, + RF_TX_TIMEOUT, + RF_LEN_ERROR, + RF_CHANNEL_EMPTY, + RF_CHANNEL_ACTIVITY_DETECTED, +}Sx1276RetType; + +typedef enum{ + SX1276_BW_7K8= (0), + SX1276_BW_10K4= (1<<4), + SX1276_BW_15K6= (2<<4), + SX1276_BW_20K8= (3<<4), + SX1276_BW_31K2= (4<<4), + SX1276_BW_41K6= (5<<4), + SX1276_BW_62K5= (6<<4), + SX1276_BW_125K= (7<<4), + SX1276_BW_250K= (8<<4), + SX1276_BW_500K= (9<<4) +}Sx1276BwType; + +typedef enum{ + SX1276_SF_64= (6<<4), + SX1276_SF_128= (7<<4), + SX1276_SF_256= (8<<4), + SX1276_SF_512= (9<<4), + SX1276_SF_1024= (10<<4), + SX1276_SF_2048= (11<<4), + SX1276_SF_4096= (12<<4) +}Sx1276SpreadFactorType; + +typedef enum{ + SX1276_EC_4_5= (1<<1), + SX1276_EC_4_6= (2<<1), + SX1276_EC_4_7= (3<<1), + SX1276_EC_4_8= (4<<1) +}Sx1276ErrorCodingType; + +typedef enum{ + SX1276_CRC_OFF= (0), + SX1276_CRC_ON= (1<<2) +}Sx1276CrcOnType; + +typedef enum{ + SX1276_IH_OFF= (0), + SX1276_IH_ON= (1) +}Sx1276ImplicitHeaderOnType; + +//¿É±äËÙÂÊ +typedef struct _AutoSfType{ + Sx1276SpreadFactorType Sf; + uint8_t ucRssiMin, ucRssiMax; + uint16_t wTimeout; +}AutoSfType, *PAutoSf; + +//Parameter +typedef enum{ + LORAPT_STATUS, + LORAPT_CHANNEL, + LORAPT_FREQ, + LORAPT_BW, + LORAPT_SF, + LORAPT_EC, + LORAPT_RSSI, + LORAPT_POWER, + LORAPT_SET_RX, + LORAPT_SET_SLEEP, + LORAPT_MAX +}Sx1276LoraParaType; + +#define SX1276_CHANNEL_MAX 17 + +#define LORA_SPI_NSS_SET() SPI2_NSS_SET() +#define LORA_SPI_NSS_CLR() SPI2_NSS_CLR() +#define LORA_SPI_READ_WRITE(x) Spi2SendReceive(x) +#define LORA_GETDIO0() LORA_DIO_GET() +//#define LORA_GETDIO1() GET_LORA_DIO1() + +#define USE_RF_SW 0 +#define USE_LORA_LED 1 +#if USE_RF_SW == 1 +#define LORA_ANTTXEN() { \ + SET_LORA_TXEN_PIN();\ + CLR_LORA_RXEN_PIN();\ + } + +#define LORA_ANTRXEN() { \ + SET_LORA_RXEN_PIN();\ + CLR_LORA_TXEN_PIN();\ + } + +#define LORA_ANTCLOSE() { \ + CLR_LORA_RXEN_PIN();\ + CLR_LORA_TXEN_PIN();\ + } +#else +#define LORA_ANTTXEN() +#define LORA_ANTRXEN() +#define LORA_ANTCLOSE() +#endif + +#if USE_LORA_LED == 1 +#define LORA_TXLED_ON() POWER_LED_ON() +#define LORA_TXLED_OFF() POWER_LED_OFF() +#define LORA_RXLED_ON() POWER_LED_ON() +#define LORA_RXLED_OFF() POWER_LED_OFF() +#else +#define LORA_TXLED_ON() +#define LORA_TXLED_OFF() +#endif + +#define LORA_BUFF_SIZE 255 + +typedef enum { + RF_ANT_TRANSMITTER, + RF_ANT_RECEIVER, + RF_ANT_CLOSE, +}Sx1276AntStatus_m; + +typedef enum { + SX1276_SLEEP, + SX1276_IDLE, + SX1276_RX, + SX1276_TX, + SX1276_BUSY, + SX1276_ERROR, + SX1276_MAX +}Sx1276StateType_t; + +typedef struct { + uint8_t ucChannel; + uint32_t dwFreqHz; + int8_t ucPower; + Sx1276BwType SignalBw; + Sx1276SpreadFactorType SpreadFactor; + Sx1276ErrorCodingType ErrorCoding; + uint8_t RegPreamble; + uint8_t ucOpModePrev; + Sx1276AntStatus_m bAntSwPrev; + Sx1276RegType RegBuff; + Sx1276StateType_t State; + uint8_t ucRxPacketSize; + uint8_t ucTxPacketSize; + uint8_t RxTxBuff[LORA_BUFF_SIZE]; + DataRevCallBack RxCallBack; + int RxRet; +}Sx1276Type_t, *pSx1276Type; + + +//ISM Freq In China +//Up Link: +//CH0-5: 470.3-471.3MHz +//CH39-44:478.1-479.1MHz +//CH78-95:485.9-489.3MHz +//Down Link: +//CH0-47:500.3-509.7MHz + +#define USE_915MHZ 0//=1ʹÓÃ915 =0ʹÓÃ433 + +#if (USE_915MHZ == 1) + //ÖÐÐÄƵÂÊ£¬²»¶¨ÒåÔòĬÈÏΪ449000000Hz + #define FREQ_CENT 915000000ul + //860MHz-1GHzʹÓÃPA¹¦·Å£¬²»¶¨ÒåÔòĬÈϲ»Ê¹Óà + //SX127x²»¶¨Ò壬HOPERFÄ£¿éÐèÒª¶¨Òå + #define USE_LORA_860_PA +#endif + +/* +ÖÐÐÄƵÂÊÅäÖãº433100000ul + 200000*N +*/ +#define CH0 (433100000ul + 0) //²âÊÔƵÂÊ +#define CH1 (433100000ul + 200000) +#define CH2 (433100000ul + 400000) +#define CH3 (433100000ul + 600000) +#define CH4 (433100000ul + 800000) +#define CH5 (433100000ul + 1000000) +#define CH6 (433100000ul + 1200000) +#define CH7 (433100000ul + 1400000) +#define CH8 (433100000ul + 1600000) +#define CH9 (433100000ul + 1800000) +#define CH10 (433100000ul + 2000000) + +#if (MAC_ADDR_TYPE == 0) +#define FREQ_CENT CH0 +#elif (MAC_ADDR_TYPE == 1) +#define FREQ_CENT CH1 +#elif (MAC_ADDR_TYPE == 2) +#define FREQ_CENT CH2 +#elif (MAC_ADDR_TYPE == 3) +#define FREQ_CENT CH3 +#elif (MAC_ADDR_TYPE == 4) +#define FREQ_CENT CH4 +#elif (MAC_ADDR_TYPE == 5) +#define FREQ_CENT CH5 +#elif (MAC_ADDR_TYPE == 6) +#define FREQ_CENT CH6 +#elif (MAC_ADDR_TYPE == 7) +#define FREQ_CENT CH7 +#elif (MAC_ADDR_TYPE == 8) +#define FREQ_CENT CH8 +#elif (MAC_ADDR_TYPE == 9) +#define FREQ_CENT CH9 +#elif (MAC_ADDR_TYPE == 10) +#define FREQ_CENT CH10 +#endif + +#if !defined FREQ_CENT +#define FREQ_CENT (433100000ul + 0)//200000 +#endif +#if !defined FREQ_DEV +#define FREQ_DEV 1000000ul +#endif + +////////////////////////////////////////////////////////////////////// +void Sx1276LoRaLoopHandler(GateWayPara GateWay); +void IsrSx1276LoRaTxRx(GateWayPara GateWay); +void Sx1276LoRaInit(DataRevCallBack RxCallBack); +void Sx1276LoRaSendBuffer(uint8_t* pucBuff, uint16_t ucLen); +uint8_t SX1276LoRaReadChannel(void); +bool SX1276LoRaWriteChannel(uint8_t Channel); +uint32_t SX1276LoRaReadFreq(void); +void SX1276LoRaWriteFreq(uint32_t Freq); +void SX1276LoRaWriteBw(Sx1276BwType SignalBw); +uint32_t SX1276LoRaReadBw(void); +uint8_t SX1276LoRaReadSf(void); +void SX1276LoRaWriteSf(Sx1276SpreadFactorType SpreadFactor); +void SX1276LoRaWriteEc(Sx1276ErrorCodingType ErrorCoding); +uint8_t SX1276LoRaReadEc(void); +uint32_t SX1276LoRaParaReadRssi(void); +uint8_t SX1276LoRaReadRssiPkt(void); +void SX1276LoRaWritePwr(int8_t Pwr); +void SX1276LoRaWriteRx(void); +void SX1276LoRaWriteSleep(bool Sleep); +Sx1276StateType_t SX1276LoRaReadStatus(void); +void SX1276LoCalcRssiSnr(int16_t *pswRssi, int8_t *psbSnr); +void Sx1276LoRaSleep(void); +void Sx1276LoRaWakeup(void); +int GetSx1276RxRetValue(void); +void Sx1276RxRetValue(void); + +bool LoraSetChannel(uint8_t Channel); +bool LoraSetPower(uint8_t Power); +bool LoraSetSignalBw(uint8_t SignalBw); +bool LoraSetSpreadFactor(uint8_t SpreadFactor); +bool LoraSetErrorCoding(uint8_t ErrorCoding); +bool LoraSetRegPreamble(uint8_t RegPreamble); +#endif + diff --git a/Project/GateWay/source/User/Inc/ADS1231.h b/Project/GateWay/source/User/Inc/ADS1231.h new file mode 100644 index 0000000..1fe2617 --- /dev/null +++ b/Project/GateWay/source/User/Inc/ADS1231.h @@ -0,0 +1,13 @@ +#ifndef __ADS1231__ +#define __ADS1231__ + +#include "bsp.h" + +void ADS1231_Open(void); +void ADS1231_SpeedSet(void); +bool ADS1231_Read(uint32_t *r_data, uint8_t channel); +void ADS1231_HighSpeedSet(void); +void ADS1231_LowSpeedSet(void); + +#endif + diff --git a/Project/GateWay/source/User/Inc/AppTask.h b/Project/GateWay/source/User/Inc/AppTask.h new file mode 100644 index 0000000..e69de29 diff --git a/Project/GateWay/source/User/Inc/CatOneTask.h b/Project/GateWay/source/User/Inc/CatOneTask.h new file mode 100644 index 0000000..60482ac --- /dev/null +++ b/Project/GateWay/source/User/Inc/CatOneTask.h @@ -0,0 +1,107 @@ +#ifndef __CAT_ONE_TASK_H +#define __CAT_ONE_TASK_H +#include "main.h" +#include "Public.h" + +#define CAT_ONE_REV_TIMEOUT_MAX (10 * 60 * 1000) +#define CAT_ONE_REV_LEN_MAX 512 + +#define CAT_ONE_POW_ON() CAT1_POW_ON() +#define CAT_ONE_POW_OFF() CAT1_POW_OFF() + +#define CAT_ONE_LINKA_GET() CAT1_LINKA_GET() +#define CAT_ONE_LINKB_GET() CAT1_LINKB_GET() + +#define CAT_ONE_DELAY_1MS(X) + +typedef enum { + CAT_ONE_AT_NULL, + CAT_ONE_AT, //¿ª»ú¼ì²â + CAT_ONE_ATE0, //¹Ø»ØÏÔ + CAT_ONE_CPIN, //ʶ¿¨ + CAT_ONE_IMEI, + CAT_ONE_LCCID, //¶Á¿¨ + CAT_ONE_CEREG, //²éѯע²á״̬ + CAT_ONE_CGPADDR, //²éѯIPµØÖ· + CAT_ONE_CSQ, //²éѯÐźÅÇ¿¶È + CAT_ONE_LDNSGIP, //ÓòÃû½âÎö + CAT_ONE_LBS, //»ñÈ¡»ùÕ¾¶¨Î»ÐÅÏ¢ + CAT_ONE_LIPOPEN, //ÉèÖÃTCP·þÎñÆ÷µØÖ·ºÍ¶Ë¿Ú + CAT_ONE_LIPSEND, //·¢ËÍÊý¾Ý + CAT_ONE_LTPCLOSE, //¶Ï¿ªÁ¬½Ó + CAT_ONE_LBSPARA, + CAT_ONE_CCLK, //»ñȡʱ¼ä + CAT_ONE_AT_CMD_END, +}CatOneATCMD_m; + +typedef enum { + CAT_ONE_IDEL, + CAT_ONE_INIT, + CAT_ONE_TCP_CONN, + CAT_ONE_WAIT_CONN, + CAT_ONE_SEND_DATA, + CAT_ONE_WAIT_SEND, + CAT_ONE_REV_DATA, + CAT_ONE_REG_SVR, + CAT_ONE_WAIT_REV, + CAT_ONE_RESET, + CAT_ONE_OFF, + CAT_ONE_CLOSE_TCP, +}CatOneStatus_m; + +typedef enum { + CAT_ONE_RET_NULL, + CAT_ONE_RET_OK, + CAT_ONE_RET_ERR, + CAT_ONE_RET_TIMEOUT, +}CatOneRetStatus_m; + +typedef enum { + CAT_ONE_CMD_MODE, + CAT_ONE_PT_MODE, +}CatOneMode_m; + +typedef enum { + CAT_ONE_2G, + CAT_ONE_ATE, +}CatOneNetType_m; + +typedef struct { + CatOneStatus_m Status; + CatOneStatus_m NextStatus; + CatOneRetStatus_m ATCmdRet; + uint32_t CatOne1mSDelayCnt; + uint32_t ResetDelayCnt; + uint32_t RegisterDelayCnt; + uint8_t AtCmdResendCnt; + uint8_t AtCmdIdx; + CatOneATCMD_m AtCmd; + bool RxFlag; + uint16_t CSQ; + char IMEI[20]; + char SIM[32]; + CatOneNetType_m NetType; + bool TcpConnFlag; + + bool LBSFlag; + int Longitude; + int Latitude; + char CatOneSendBuff[1024]; + + GateWayPara GateWay; + DataRevCallBack CatOneRevCallBack; +}CatOne_t, *pCatOne_t; + +CatOneRetStatus_m CatOneSend(uint8_t *sData, uint16_t sLen); +void CatOneStart(void); +void CatOneStop(void); +void CatOneReset(void); +void Cat1DBGOnOff(bool OnOff); +void CatOneGetLocationInfo(int *Longitude, int *Latitude); +void CatOneGetIMEIAndSIM(char *Imei, char *Sim); +bool CatOneGetStatus(void); +bool CatOneEthSendQueue(uint8_t *sData, uint16_t sLen); +void CatOne_Eth_Thread_Entry(void *parameter); +void EthRxOverhandler(void); +void CatReadImeiOrSim(char *Imei, char *Sim); +#endif diff --git a/Project/GateWay/source/User/Inc/DebugCmd.h b/Project/GateWay/source/User/Inc/DebugCmd.h new file mode 100644 index 0000000..1dd66bd --- /dev/null +++ b/Project/GateWay/source/User/Inc/DebugCmd.h @@ -0,0 +1,7 @@ +#ifndef __DEBUG_CMD_H +#define __DEBUG_CMD_H + +void Debug_Thread_Entry(void *parameter); +void DebugRxOverhandler(void); +void Debug_Printf(char *format, ...); +#endif diff --git a/Project/GateWay/source/User/Inc/Encryption.h b/Project/GateWay/source/User/Inc/Encryption.h new file mode 100644 index 0000000..7067945 --- /dev/null +++ b/Project/GateWay/source/User/Inc/Encryption.h @@ -0,0 +1,7 @@ +#ifndef __EPT__ +#define __EPT__ + +void Encrypt_Code(unsigned char *data, unsigned char *EPT_data); +void Decrypt_Code(unsigned char *EPT_data,unsigned char *DPT_data); + +#endif diff --git a/Project/GateWay/source/User/Inc/LoraTask.h b/Project/GateWay/source/User/Inc/LoraTask.h new file mode 100644 index 0000000..e0bb72f --- /dev/null +++ b/Project/GateWay/source/User/Inc/LoraTask.h @@ -0,0 +1,11 @@ +#ifndef __LORA_TASK_H +#define __LORA_TASK_H + +#include "bsp.h" +#include "sx127x.h" + +void Lora_Thread_Entry(void *parameter); +int LoraRevCallBack(GateWayPara GateWay, uint8_t *rData, uint16_t rLen); +void LoraInit(void); +#endif + diff --git a/Project/GateWay/source/User/Inc/Public.h b/Project/GateWay/source/User/Inc/Public.h new file mode 100644 index 0000000..0d2e06a --- /dev/null +++ b/Project/GateWay/source/User/Inc/Public.h @@ -0,0 +1,283 @@ +#ifndef __PUBLIC_H +#define __PUBLIC_H + +#include "bsp.h" + +#define LORA_LOWPOWER //LORAµÍ¹¦ºÄÉ豸£¬²ÉÓÃÖ÷¶¯Éϱ¨·½Ê½ + +#define SENSOR_DATA_LEN_MAX 50 +#define SENSOR_NUM_MAX 16 +#define COMMUNIT_NUM_MAX 32 + +#define REGISTER_INTERVAL_MAX (2 * 60) +#define COMMUNIT_READ_SENSOR_INTERVAL_MAX (1 * 60) + +#define LORA_ERR_RESET_DLY_MAX (10 * 60) //LORA½ÓÊÕ³¬Ê±¸´Î»ÑÓʱ£¬µ¥Î»Ãë +#define CAT1_ERR_RESET_DLY_MAX (60 * 60) //CAT1½ÓÊÕ³¬Ê±¸´Î»ÑÓʱ£¬µ¥Î»Ãë + +typedef struct GateWay_t GateWayPara_t, *GateWayPara; + +typedef void (*SendData)(uint8_t *sData, uint16_t sLen); +typedef int (*DataRevCallBack)(GateWayPara GateWay, uint8_t *rData, uint16_t rLen); +typedef int (*DataRevResCallBack)(GateWayPara GateWay, uint8_t *rData, uint16_t rLen, SendData Response); +typedef int (*SendDataOrg)(uint8_t *sData); + +typedef enum { + DEBUG_CH_DBG, + DEBUG_CH_RS485_1, + DEBUG_CH_RS485_2, +}DebugChannel_m; + + +typedef enum { + DEV_TYPE_BROADCAST, + DEV_TYPE_INC_COMMUNIT = 0x8001, + DEV_TYPE_EXT_COMMUNIT, + DEV_TYPE_ICE_SENSOR, + DEV_TYPE_CRACK_SENSOR, + DEV_TYPE_PRESSURE_SENSOR, + DEV_TYPE_RAIN_SENSOR, +}DevType_m; + +typedef enum { + CATONE_COMM, + ETH_COMM, +}CommType_m; + +typedef enum { + LORA_COMM, + RS485CH1_COMM, + RS485CH2_COMM +}SensorComm_m; + +typedef enum { + COMM_UNIT_CMD_REG, + COMM_UNIT_CMD_CAIL, + COMM_UNIT_CMD_READ, + COMM_UNIT_CMD_SET_SENSOR_COLL_TIME = 5, + COMM_UNIT_CMD_TIME_SYNC, + COMM_UNIT_CMD_CONT_LASER = 8,//¼¤¹â¶ÀÓÐÖ¸Áî + COMM_UNIT_CMD_END, +}CommUnitCmd_m; + +typedef enum { + NET_COMM_CMD_REG, + NET_COMM_CMD_CAIL, + NET_COMM_CMD_UPDATE, + NET_COMM_CMD_READ_GW_INFO, + //NET_COMM_CMD_READ_UNIT_INFO, + NET_COMM_CMD_GW_PARA_CONFIG, + NET_COMM_CMD_HIS_DATA, + NET_COMM_CMD_ADD_UNIT, + NET_COMM_CMD_LP_DEV_CONFIG, + NET_COMM_CMD_ALARM, + NET_COMM_CMD_CONT_LASER,//¼¤¹â¶ÀÓÐÖ¸Áî + NET_COMM_CMD_END, +}NetCommCmd_m; + +typedef enum { + SENSOR_TYPE_NULL, //0x0000 ¿ÕÉ豸 + FORCE_6D, //0x0001 ÁùάӦÁ¦ + OSMOTIC_PRESSURE, //0x0002 Éø͸ѹ + ELASTIC_WAVEGUIDE, //0x0003 µ¯ÐÔ²¨µ¼ + DIELECTRIC_MASS, //0x0004 ½éµçÖÊÆÕ + VIBRATE_SENSOR, //0x0005 ΢Õñ¶¯´«¸ÐÆ÷ + CONT_DEFOR_3D, //0x0006 ÈýάÁ¬Ðø±äÐÎ + COMM_UNIT, //0x0007 ͨѶµ¥Ôª + FORCE_3D, //0x0008 ÈýάӦÁ¦ + LASER_TRACING, //0x0009 ¼¤¹âʾ×Ù + WATER_LEVEL, //0x000A ˮλ¼Æ + _0x000B, //0x000B ±£Áô + _0x000C, //0x000C ±£Áô + MULTI_PARAMETER_FUSION, //0x000D ¶à²ÎÊýÈÚºÏ + CRACK_DETECTION, //0x000E ÁÑ·ìÒÇ + _0x000F, //0x000F ±£Áô + ATTITUDE_MONITOR, //0x0010 ×Ë̬¼ì²â + LASER_DISPLACE, //0x0011 ¼¤¹âλÒÆ + REBAR_STRESS, //0x0012 ¸Ö½îÓ¦Á¦ + ANCHOR_ROD_STRESS, //0x0013 ê¸ËÖáÁ¦ + SURFACE_STRESS, //0x0014 ±íÃæÓ¦Á¦ + PRESSURE, //0x0015 ѹÁ¦ + MICROWAVE_DISPLACE, //0x0016 ΢²¨Î»ÒÆ +}SensorType_m; + +typedef struct {//Ö÷É豸¹Ì¶¨°üÍ· + uint8_t BatLevel; //µç³ØµçÁ¿ + int8_t RSSI; //ÐźÅÇ¿¶È + int8_t Nsr; //ÐÅÔë±È +}__attribute__ ((packed))MasterDev_T,*MasterDevDp; + +typedef struct { + int16_t AccX; + int16_t AccY; + int16_t AccZ; + int32_t Strain1; + int32_t Strain2; + int32_t Strain3; + int32_t Strain4; + int32_t Strain5; + int32_t Strain6; +}__attribute__((packed))Force6D_T; + +typedef struct { + MasterDev_T MasterDev; + int16_t PitchAngle; //¸©Ñö½Çƫб £¨·¶Î§¡À900£©µ¥Î»0.1¡ã + int16_t RollAngle; //ºá¹ö½Çƫб £¨·¶Î§¡À900£©µ¥Î»0.1¡ã + int16_t YawAngle; //Æ«º½½Çƫб £¨·¶Î§0~3600£©µ¥Î»0.1¡ã +}__attribute__((packed))LaserTracingType_t; + +typedef struct { + uint8_t CommDevAddr[6]; //ͨѶµ¥ÔªµØÖ· + uint16_t CollectInterval; //²É¼¯Ê±¼ä¼ä¸ô + uint16_t ReportInterval; //Éϱ¨Ê±¼ä¼ä¸ô + uint8_t ERInterval; //½ô¼±Éϱ¨Ê±¼ä¼ä¸ô + uint8_t ERTime; //½ô¼±Éϱ¨Ê±³¤ +}__attribute__((packed))SvrDownLPDevConfigPara_t; + +typedef struct { + int Distance; +}__attribute__((packed))LaserDistanceSensorType_t; + +typedef struct { + uint8_t AlarmType; + uint8_t AlarmState; + uint8_t AlarmPara; +}__attribute__((packed))GateWayAlarmType_t; + +#define LW_DEV_COLLECT_INTERVAL_MAX 300//ĬÈÏ300Ãë +#define LW_DEV_REPORT_INTERVAL_MAX 20//20·ÖÖÓ +#define LW_DEV_ER_INTERVAL_MAX 2//2·ÖÖÓ +#define LW_DEV_ER_TIME_MAX 20//20·ÖÖÓ + +typedef struct { + uint16_t CollectInterval; //²É¼¯Ê±¼ä¼ä¸ô + uint16_t ReportInterval; //Éϱ¨Ê±¼ä¼ä¸ô + uint8_t ERInterval; //½ô¼±Éϱ¨Ê±¼ä¼ä¸ô + uint8_t ERTime; //½ô¼±Éϱ¨Ê±³¤ + uint32_t TimeStamp; //ʱ¼ä´Á +}__attribute__((packed))LPDevConfigPara_t; + +typedef struct { + bool RegFlag; + bool RevNewDataFlag; + bool CommStatus; //ͨѶ״̬£¬1-ÔÚÏߣ¬0-ÀëÏß + bool CailFlag; //У׼±êÖ¾£¨µÍ¹¦ºÄ£© + bool TimeSyncFlag; //ʱ¼äͬ²½±êÖ¾£¨µÍ¹¦ºÄ£© + bool ContLaser; //¼¤¹â¿ØÖƱêÖ¾£¨µÍ¹¦ºÄ£© + bool LaserOnOff; //¼¤¹â״̬£¨µÍ¹¦ºÄ£© + uint32_t CommErrCnt; + uint8_t MasterMac[6]; + uint8_t Mac[SENSOR_NUM_MAX][6];//µÚһλÊÇÖ÷É豸£¬ºóÃæÈ«ÊÇ×ÓÉ豸 + uint8_t BatLevel; + int8_t RSSI; //ÐźÅÇ¿¶È + int8_t Nsr; //ÐÅÔë±È + uint16_t CUType; + uint8_t SensorN; + uint16_t SensorType[SENSOR_NUM_MAX]; + //µÍ¹¦ºÄÉ豸ÅäÖÃÐÅÏ¢ + bool ConfigFlag; //ÅäÖñêÖ¾£¬Îª1±íʾÓÐÐÂÅäÖã¬Ó¦´ðµÍ¹¦ºÄÉ豸ʱÐèÒª¸½´ø·¢ËÍ + uint16_t CollectInterval; //²É¼¯Ê±¼ä¼ä¸ô + uint16_t ReportInterval; //Éϱ¨Ê±¼ä¼ä¸ô + uint8_t ERInterval; //½ô¼±Éϱ¨Ê±¼ä¼ä¸ô + uint8_t ERTime; //½ô¼±Éϱ¨Ê±³¤ +}CommUnitPara_t, *CommUnitPara; + +typedef struct { + uint8_t Data[SENSOR_NUM_MAX][SENSOR_DATA_LEN_MAX]; +}CommUnitData_t, *CommUnitData; + +typedef struct { + CommUnitPara_t Para; +}CommUnit_t, *CommUnit; + +typedef struct { + bool Enable; //´®¿ÚʹÄÜ + bool CommUnitEnable; //ͨѶµ¥ÔªÊ¹ÄÜ£¬¿ªÆô£¨Ê¹ÓÃÄÚ²¿Í¨Ñ¶µ¥Ôª¹¦ÄÜ£¬Ö±½ÓºÍ´«¸ÐÆ÷ͨѶ£©£¬¹Ø±Õ£¨Ö±½ÓºÍRS485ÀàÐ͵ÄͨѶµ¥ÔªÍ¨Ñ¶£© + bool QuerySensorFlag; //²éѯ´«¸ÐÆ÷±êÖ¾ + bool UpgradeEnable;//Éý¼¶¹¦ÄÜʹÄÜ + uint8_t Power; + uint32_t BaudRate; + SendData RS485Send; + CommUnit_t CUData; +}RS485Para_t, *RS485Para; + +typedef struct { + uint8_t Header; + uint8_t GWMac[6]; + uint8_t DevMac[6]; + uint8_t Cmd; + //uint16_t DevType; + uint16_t PayloadLen; +}__attribute__((packed))CommUnitFrameHeader_t, *CommUnitFrameHeader; + +typedef struct { + uint8_t Header; + uint8_t GWMac[6]; + //uint8_t SvrMac[6]; + uint8_t Cmd; + uint8_t BatLevel; + uint32_t Timestamp; + uint8_t PacketNum; + uint8_t PacketIdx; + uint16_t PayloadLen; +}__attribute__((packed))NetCommFrameHeader_t, *NetCommFrameHeader; + +typedef struct { + bool OnOff; + SendData LoraSend; + uint8_t ucChannel; + int8_t ucPower; + uint8_t SignalBw; + uint8_t SpreadFactor; + uint8_t ErrorCoding; + uint8_t RegPreamble; + uint32_t FreqCent; +}LoraPara_t, *pLoraPara; + +typedef struct { + uint32_t SavFlag; //´æ´¢±êÖ¾ + CommType_m Comm; //Íø¹ØͨѶ·½Ê½ + uint8_t GwMac[6]; //Íø¹Ømac + char SvrAddr[4]; //·þÎñÆ÷µØÖ· + uint32_t SvrPort; //·þÎñÆ÷¶Ë¿Ú + uint32_t CommUnitReadInterval; //ͨѶµ¥Ôª¶Áȡʱ¼ä¼ä¸ô,µ¥Î»S + CommUnitPara_t CommUnitArray[COMMUNIT_NUM_MAX]; //×¢²áµÄͨѶµ¥ÔªÐÅÏ¢ + RS485Para_t Rs485Ch1; //RS485ͨµÀ1ÅäÖà + RS485Para_t Rs485Ch2; //RS485ͨµÀ2ÅäÖà + uint8_t DebugChannel; //µ÷ÊÔͨµÀ + LoraPara_t Lora; //LoraÅäÖà + bool OutageFlag; //¶Ïµç±¨¾¯±êÖ¾ + uint16_t crc16; +}__attribute__((packed))GWConfigPara_t, *GWConfigPara; + +struct GateWay_t{ + bool TimeSyncFlag; //ʱ¼äͬ²½±êÖ¾ + bool SvrRegFlag; //·þÎñÆ÷×¢²á±êÖ¾ + uint8_t SvrMac[6]; //·þÎñÆ÷mac + GWConfigPara_t ConfigPara; //ÅäÖòÎÊý + CommUnitData_t CUDataArray[COMMUNIT_NUM_MAX]; + uint8_t Battery; //µç³ØµçÁ¿ + uint16_t UploadInterval; //ÉÏ´«¼ä¸ô + uint32_t HistoryNum; //ÀúÊ·Êý¾ÝÊýÁ¿ + DataRevCallBack SvrRevCallBack; //½ÓÊÕµ½·þÎñÆ÷»Øµ÷ + DataRevResCallBack CommUnitRevCallBack; //ͨѶµ¥Ôª½ÓÊջص÷ + rt_mq_t NetSendData_MQ; //ÍøÂç·¢ËÍÊý¾Ý¶ÓÁУ¬µÚÒ»¸ö×Ö½ÚÓÃÓÚ´æ´¢ÏûÏ¢³¤¶È, µÚ¶þ×Ö½Ú´æ´¢ÃüÁî×Ö£¬ºóΪÊý¾Ý + rt_mq_t LoraRev_MQ; //Lora½ÓÊÕÏûÏ¢¶ÓÁУ¬µÚÒ»¸ö×Ö½ÚÓÃÓÚ´æ´¢ÏûÏ¢³¤¶È£¬ºóΪÊý¾Ý + rt_mutex_t UartRevMutex; + + uint8_t BatteryReadDlyCnt; //¶ÁÈ¡µçѹÑÓʱ£¬µ¥Î»Ã룬·ÀÖ¹4G·¢ËÍÀ­µÍµç³Øµçѹ£¬Ôì³É¶ÏµçÎó±¨ +}; + +int Cat1EthRevCallBack(GateWayPara GateWay, uint8_t *rData, uint16_t rLen); +uint16_t CRC_Modbus(uint16_t wBase, __IO uint8_t *para, uint16_t length); +uint8_t AsciiToHex(char *ASCData, uint8_t *HexData, uint8_t sLen); +void HexToAscii(uint8_t *HexData, char *ASCData, uint8_t sLen); +int NetCommOrgData(GateWayPara GateWay, uint8_t *MegData, uint8_t *OutData); +int CommUnitAnalyze(GateWayPara GateWay, uint8_t *rData, uint16_t rLen, SendData Response); +void DebugAnalyze(GateWayPara GateWay, uint8_t *rData, uint16_t rLen); +void CommUnitCmdSend(GateWayPara GateWay, uint8_t *CommUnitMac, CommUnitCmd_m Cmd, uint8_t *Payload, uint16_t PayloadLen, SendData Send); +int CheckCommUnitReg(GateWayPara GateWay, uint8_t *CommUnitMac); +int CommUintOrgData(GateWayPara GateWay, CommUnitPara CUPara, CommUnitData CUData, uint8_t *sData); +void DebugDisplaySensorData(int SensorIdx, uint16_t SensorType, uint8_t *SensorData); +#endif + diff --git a/Project/GateWay/source/User/Inc/PublicTypes.h b/Project/GateWay/source/User/Inc/PublicTypes.h new file mode 100644 index 0000000..5edbd94 --- /dev/null +++ b/Project/GateWay/source/User/Inc/PublicTypes.h @@ -0,0 +1,14 @@ +#ifndef __PUBLIC_TYPES_H +#define __PUBLIC_TYPES_H + +#include +#include + +typedef void (*ReadPara)(pSFBTPara rPara); +typedef void (*SavPara)(pSFBTPara wPara); +typedef void (*UartSend)(uint8_t *sData, int sLen); +typedef void (*DataRevCallBack)(uint8_t *rData, uint8_t rLen); +typedef int (*SendDataOrg)(uint8_t *sData); + +#endif + diff --git a/Project/GateWay/source/User/Inc/RS485Task.h b/Project/GateWay/source/User/Inc/RS485Task.h new file mode 100644 index 0000000..46b7c1c --- /dev/null +++ b/Project/GateWay/source/User/Inc/RS485Task.h @@ -0,0 +1,70 @@ +#ifndef __RS485_TASK_H +#define __RS485_TASK_H + +#include "bsp.h" +#include "Public.h" + +#define RS485_RX_BUFF_LEN_MAX 64 + +typedef struct { + SensorComm_m Com; + uint16_t SensorType; +}SensorTypes_t; + +typedef enum { + RS485_OUT_VOLTAGE_OV, + RS485_OUT_VOLTAGE_5V, + RS485_OUT_VOLTAGE_12V, +}RS485Vol_m; + +typedef struct { + uint8_t Header; + uint8_t SlvAddr; + uint8_t Cmd; + //uint16_t DevType; + uint8_t PayloadLen; +}__attribute__((packed))FrameHeader_t, *FrameHeader; + +typedef enum { + RS485_SENSOR_CMD_NULL, + RS485_SENSOR_CMD_CAIL, + RS485_SENSOR_CMD_READ, + RS485_SENSOR_CMD_QUERY, + RS485_SENSOR_CMD_SET_ADDR, + RS485_SENSOR_CMD_SET_INV_TIME, + RS485_SENSOR_CMD_TIME_SYNC, + RS485_SENSOR_CMD_END, +}RS485SensorCmd_m; + +//´«¸ÐÆ÷Êý¾Ý·¢ËͽṹÌå +typedef struct { + bool SendFlag; + uint8_t SensorCnt; + uint8_t SensorErrCnt[SENSOR_NUM_MAX]; + uint8_t ReadSensorCnt; + int32_t ReadSensorInterval; + RS485SensorCmd_m Cmd; + uint8_t SensorAddr; + uint16_t SensorType; + uint8_t CmdParaLen; + uint8_t *CmdPara; + uint8_t RS485RxBuff[RS485_RX_BUFF_LEN_MAX]; + uint8_t RS485RxLen; + uint8_t RS485TimeOutCnt; + uint32_t RS485CommUnitReadTimeDelay; + uint8_t SendUnitCommIdx; + rt_sem_t RS485Rev_Sem; + bool InitOverFlag; + CommUnitData_t SensorData; +}SensorCommPara_t, *SensorCommPara; + +void RS485CmdSend(GateWayPara GateWay, uint8_t CommUintAddr, SensorCommPara SensorComm); +void RS485Ch1_Thread_Entry(void *parameter); +void RS485Ch2_Thread_Entry(void *parameter); +void RS485RxOverhandler(void); + +extern SensorCommPara_t SComm1Para; +extern SensorCommPara_t SComm2Para; +#endif + + diff --git a/Project/GateWay/source/User/Inc/app_comm.h b/Project/GateWay/source/User/Inc/app_comm.h new file mode 100644 index 0000000..f00913b --- /dev/null +++ b/Project/GateWay/source/User/Inc/app_comm.h @@ -0,0 +1,10 @@ +#ifndef _APP_COMM_H_ +#define _APP_COMM_H_ + +#include "rtthread.h" + +#define BSP_LOG(format,...) do { \ + rt_kprintf(format, ##__VA_ARGS__); \ +} while (0) + +#endif diff --git a/Project/GateWay/source/User/Inc/bsp.h b/Project/GateWay/source/User/Inc/bsp.h new file mode 100644 index 0000000..3458932 --- /dev/null +++ b/Project/GateWay/source/User/Inc/bsp.h @@ -0,0 +1,414 @@ +#ifndef __BSP_H +#define __BSP_H + +#include +#include +#include +#include +#include +#include "hc32_ddl.h" +#include "rtthread.h" +#include "ff.h" + +//#define USE_BOOTLOADER + +//#define FLASH_SECTOR_SIZE 0x2000ul +//#define FLASH_BASE ((uint32_t)0x00000000) +//#define FLASH_SIZE (64u * FLASH_SECTOR_SIZE) + + +//#define SRAM_BASE ((uint32_t)0x1FFF8000) +//#define RAM_SIZE 0x2F000ul + + +//#define BOOT_SIZE (4 * FLASH_SECTOR_SIZE) +//#define APP_ADDRESS (FLASH_BASE + BOOT_SIZE) + +//#define BOOT_PARA_ADDRESS (FLASH_SIZE - FLASH_SECTOR_SIZE) +//#define BOOT_PARA_SIZE (FLASH_SECTOR_SIZE) + +/* flash rom map ´æ´¢·ÖÇø*/ +//boot 16k +#define FLASH_BASE ((uint32_t)0x00000000) +#define FLASH_SECTOR_SIZE 0x2000ul + +#define FLASH_BOOT_BASE (FLASH_BASE) +#define FLASH_BOOT_SIZE (4*FLASH_SECTOR_SIZE) +//app +#define FLASH_APP_BASE (FLASH_BOOT_BASE+ FLASH_BOOT_SIZE) +#define FLASH_APP_SIZE (58*FLASH_SECTOR_SIZE) + +//boot info +#define FLASH_BINFO_BASE (FLASH_APP_BASE + FLASH_APP_SIZE) +#define FLASH_BINFO_SIZE (1*FLASH_SECTOR_SIZE) + +//user config +#define FLASH_CFG_BASE (FLASH_BINFO_BASE + FLASH_BINFO_SIZE) +#define FLASH_CFG_SIZE (1*FLASH_SECTOR_SIZE) + +#define FLASH_CFG_MAGIC (0xa5) + +#define APP_START_FLAG 0x55AA5A5A +#define APP_UPDATE_FLAG 0xA5A5AA55 + + +#define WATCH_DOG 1 + +#define DEBUG 1 +#define USE_SD_CARD 0 + +#define RTC_IRQn Int001_IRQn + +#define LORA_DIO0_IRQn Int005_IRQn + +#define DBGUART_IRQn Int006_IRQn +#define DBGUART_EI_IRQn Int007_IRQn + +#define RS485CH1_UART_IRQn Int008_IRQn +#define RS485CH1_UART_EI_IRQn Int009_IRQn + +#define RS485CH2_UART_IRQn Int010_IRQn +#define RS485CH2_UART_EI_IRQn Int011_IRQn + +#define ETH_OR_CAT1_UART_IRQn Int012_IRQn +#define ETH_OR_CAT1_UART_EI_IRQn Int013_IRQn + +#define DBG_RXPIN_IRQn Int002_IRQn + + +//DEBUG +#define DBG_USART_CH (M4_USART1) +#define DBG_USART_RX_PORT (PortA) +#define DBG_USART_RX_PIN (Pin11) +#define DBG_USART_TX_PORT (PortA) +#define DBG_USART_TX_PIN (Pin12) +#define DBG_USART_RX_FUNC (Func_Usart1_Rx) +#define DBG_USART_TX_FUNC (Func_Usart1_Tx) +#define DBG_USART_RI_NUM (INT_USART1_RI) +#define DBG_USART_EI_NUM (INT_USART1_EI) +#define DBG_USART_TI_NUM (INT_USART1_TI) +#define DBG_USART_TCI_NUM (INT_USART1_TCI) +#define DBG_FCG1_PERIPH (PWC_FCG1_PERIPH_USART1) + +//RS485 Ch1 +#define RS485_CH1_USART_CH (M4_USART2) +#define RS485_CH1_USART_RX_PORT (PortA) +#define RS485_CH1_USART_RX_PIN (Pin10) +#define RS485_CH1_USART_TX_PORT (PortA) +#define RS485_CH1_USART_TX_PIN (Pin08) +#define RS485_CH1_USART_RX_FUNC (Func_Usart2_Rx) +#define RS485_CH1_USART_TX_FUNC (Func_Usart2_Tx) +#define RS485_CH1_USART_RI_NUM (INT_USART2_RI) +#define RS485_CH1_USART_EI_NUM (INT_USART2_EI) +#define RS485_CH1_USART_TI_NUM (INT_USART2_TI) +#define RS485_CH1_USART_TCI_NUM (INT_USART2_TCI) +#define RS485_CH1_FCG1_PERIPH (PWC_FCG1_PERIPH_USART2) + +#define RS485_CH1_CTRL_PORT (PortC) +#define RS485_CH1_CTRL_PIN (Pin07) +#define RS485_CH1_TX() PORT_SetBits(RS485_CH1_CTRL_PORT, RS485_CH1_CTRL_PIN) +#define RS485_CH1_RX() PORT_ResetBits(RS485_CH1_CTRL_PORT, RS485_CH1_CTRL_PIN) + +#define RS485_CH1_POW_PORT (PortC) +#define RS485_CH1_POW_PIN (Pin10) +#define RS485_CH1_POW_ON() PORT_SetBits(RS485_CH1_POW_PORT, RS485_CH1_POW_PIN) +#define RS485_CH1_POW_OFF() PORT_ResetBits(RS485_CH1_POW_PORT, RS485_CH1_POW_PIN) + +//#define RS485_CH1_VOL_CTRL_PORT (PortA) +//#define RS485_CH1_VOL_CTRL_PIN (Pin15) +//#define RS485_CH1_VOL_5V() PORT_SetBits(RS485_CH1_VOL_CTRL_PORT, RS485_CH1_VOL_CTRL_PIN) +//#define RS485_CH1_VOL_12V() PORT_ResetBits(RS485_CH1_VOL_CTRL_PORT, RS485_CH1_VOL_CTRL_PIN) + +//RS485 Ch2 +#define RS485_CH2_USART_CH (M4_USART3) +#define RS485_CH2_USART_RX_PORT (PortB) +#define RS485_CH2_USART_RX_PIN (Pin14) +#define RS485_CH2_USART_TX_PORT (PortB) +#define RS485_CH2_USART_TX_PIN (Pin12) +#define RS485_CH2_USART_RX_FUNC (Func_Usart3_Rx) +#define RS485_CH2_USART_TX_FUNC (Func_Usart3_Tx) +#define RS485_CH2_USART_RI_NUM (INT_USART3_RI) +#define RS485_CH2_USART_EI_NUM (INT_USART3_EI) +#define RS485_CH2_USART_TI_NUM (INT_USART3_TI) +#define RS485_CH2_USART_TCI_NUM (INT_USART3_TCI) +#define RS485_CH2_FCG1_PERIPH (PWC_FCG1_PERIPH_USART3) + +#define RS485_CH2_CTRL_PORT (PortB) +#define RS485_CH2_CTRL_PIN (Pin13) +#define RS485_CH2_TX() PORT_SetBits(RS485_CH2_CTRL_PORT, RS485_CH2_CTRL_PIN) +#define RS485_CH2_RX() PORT_ResetBits(RS485_CH2_CTRL_PORT, RS485_CH2_CTRL_PIN) + +#define RS485_CH2_POW_PORT (PortB) +#define RS485_CH2_POW_PIN (Pin02) +#define RS485_CH2_POW_ON() PORT_SetBits(RS485_CH2_POW_PORT, RS485_CH2_POW_PIN) +#define RS485_CH2_POW_OFF() PORT_ResetBits(RS485_CH2_POW_PORT, RS485_CH2_POW_PIN) + +//#define RS485_CH2_VOL_CTRL_PORT (PortB) +//#define RS485_CH2_VOL_CTRL_PIN (Pin10) +//#define RS485_CH2_VOL_5V() PORT_SetBits(RS485_CH2_VOL_CTRL_PORT, RS485_CH2_VOL_CTRL_PIN) +//#define RS485_CH2_VOL_12V() PORT_ResetBits(RS485_CH2_VOL_CTRL_PORT, RS485_CH2_VOL_CTRL_PIN) + +//ETH OR CAT1 +#define ETH_OR_CAT1_USART_CH (M4_USART4) +#define ETH_OR_CAT1_USART_RX_PORT (PortB) +#define ETH_OR_CAT1_USART_RX_PIN (Pin09) +#define ETH_OR_CAT1_USART_TX_PORT (PortC) +#define ETH_OR_CAT1_USART_TX_PIN (Pin13) +#define ETH_OR_CAT1_USART_RX_FUNC (Func_Usart4_Rx) +#define ETH_OR_CAT1_USART_TX_FUNC (Func_Usart4_Tx) +#define ETH_OR_CAT1_USART_RI_NUM (INT_USART4_RI) +#define ETH_OR_CAT1_USART_EI_NUM (INT_USART4_EI) +#define ETH_OR_CAT1_USART_TI_NUM (INT_USART4_TI) +#define ETH_OR_CAT1_USART_TCI_NUM (INT_USART4_TCI) +#define ETH_OR_CAT1_FCG1_PERIPH (PWC_FCG1_PERIPH_USART4) + +#define ETH_OR_CAT1_CTRL_PORT (PortB) +#define ETH_OR_CAT1_CTRL_PIN (Pin08) +#define ETH_ON() PORT_SetBits(ETH_OR_CAT1_CTRL_PORT, ETH_OR_CAT1_CTRL_PIN) +#define CAT1_ON() PORT_ResetBits(ETH_OR_CAT1_CTRL_PORT, ETH_OR_CAT1_CTRL_PIN) + +//#define ETH_OR_CAT1_TX_CTRL_PORT (PortH) +//#define ETH_OR_CAT1_TX_CTRL_PIN (Pin02) +//#define ETH_ON() { PORT_SetBits(ETH_OR_CAT1_CTRL_PORT, ETH_OR_CAT1_CTRL_PIN); PORT_SetBits(ETH_OR_CAT1_TX_CTRL_PORT, ETH_OR_CAT1_TX_CTRL_PIN); } +//#define CAT1_ON() { PORT_ResetBits(ETH_OR_CAT1_CTRL_PORT, ETH_OR_CAT1_CTRL_PIN); PORT_ResetBits(ETH_OR_CAT1_TX_CTRL_PORT, ETH_OR_CAT1_TX_CTRL_PIN);} + +#define CAT1_PWR_KEY_PORT (PortA) +#define CAT1_PWR_KEY_PIN (Pin03) +#define CAT1_PWR_KEY_CLR() PORT_SetBits(CAT1_PWR_KEY_PORT, CAT1_PWR_KEY_PIN) +#define CAT1_PWR_KEY_SET() PORT_ResetBits(CAT1_PWR_KEY_PORT, CAT1_PWR_KEY_PIN) + +#define CAT1_RESET_PORT (PortA) +#define CAT1_RESET_PIN (Pin00) +#define CAT1_RESET_CLR() PORT_SetBits(CAT1_RESET_PORT, CAT1_RESET_PIN) +#define CAT1_RESET_SET() PORT_ResetBits(CAT1_RESET_PORT, CAT1_RESET_PIN) + +//#define CAT1_POW_PORT (PortA) +//#define CAT1_POW_PIN (Pin00) +//#define CAT1_POW_ON() PORT_SetBits(CAT1_POW_PORT, CAT1_POW_PIN) +//#define CAT1_POW_OFF() PORT_ResetBits(CAT1_POW_PORT, CAT1_POW_PIN) + +#define ETH_RESET_PORT (PortB) +#define ETH_RESET_PIN (Pin05) +#define ETH_RESET_SET() PORT_SetBits(ETH_RESET_PORT, ETH_RESET_PIN) +#define ETH_RESET_CLR() PORT_ResetBits(ETH_RESET_PORT, ETH_RESET_PIN) + +#define ETH_DEF_PORT (PortB) +#define ETH_DEF_PIN (Pin07) +#define ETH_DEF_SET() PORT_SetBits(ETH_DEF_PORT, ETH_DEF_PIN) +#define ETH_DEF_CLR() PORT_ResetBits(ETH_DEF_PORT, ETH_DEF_PIN) + +#define ETH_LINK_PORT (PortB) +#define ETH_LINK_PIN (Pin06) +#define ETH_LINK_GET() PORT_GetBit(ETH_LINK_PORT, ETH_LINK_PIN) + +/* SPI_MOSI Port/Pin definition */ +#define SPI_NSS_PORT (PortC) +#define SPI_NSS_PIN (Pin00) +#define SPI_NSS_FUNC (Func_Spi1_Nss0) +#define SPI_NSS_SET() PORT_SetBits(SPI_NSS_PORT, SPI_NSS_PIN) +#define SPI_NSS_CLR() PORT_ResetBits(SPI_NSS_PORT, SPI_NSS_PIN) + +/* SPI_SCK Port/Pin definition */ +#define SPI_SCK_PORT (PortC) +#define SPI_SCK_PIN (Pin02) +#define SPI_SCK_FUNC (Func_Spi1_Sck) + +/* SPI_MOSI Port/Pin definition */ +#define SPI_MOSI_PORT (PortC) +#define SPI_MOSI_PIN (Pin03) +#define SPI_MOSI_FUNC (Func_Spi1_Mosi) + +/* SPI_MISO Port/Pin definition */ +#define SPI_MISO_PORT (PortC) +#define SPI_MISO_PIN (Pin01) +#define SPI_MISO_FUNC (Func_Spi1_Miso) + +/* SPI unit and clock definition */ +#define SPI_UNIT (M4_SPI1) +#define SPI_UNIT_CLOCK (PWC_FCG1_PERIPH_SPI1) + + +//LORA IO +/* SPI_SCK Port/Pin definition */ +#define SPI2_SCK_PORT (PortC) +#define SPI2_SCK_PIN (Pin04) +#define SPI2_SCK_FUNC (Func_Spi2_Sck) + +/* SPI_MOSI Port/Pin definition */ +#define SPI2_MOSI_PORT (PortA) +#define SPI2_MOSI_PIN (Pin07) +#define SPI2_MOSI_FUNC (Func_Spi2_Mosi) + +/* SPI_MISO Port/Pin definition */ +#define SPI2_MISO_PORT (PortA) +#define SPI2_MISO_PIN (Pin06) +#define SPI2_MISO_FUNC (Func_Spi2_Miso) + +/* SPI_MOSI Port/Pin definition */ +#define SPI2_NSS_PORT (PortC) +#define SPI2_NSS_PIN (Pin05) +#define SPI2_NSS_FUNC (Func_Spi2_Nss0) +#define SPI2_NSS_SET() PORT_SetBits(SPI2_NSS_PORT, SPI2_NSS_PIN) +#define SPI2_NSS_CLR() PORT_ResetBits(SPI2_NSS_PORT, SPI2_NSS_PIN) + +/* SPI unit and clock definition */ +#define SPI2_UNIT (M4_SPI2) +#define SPI2_UNIT_CLOCK (PWC_FCG1_PERIPH_SPI2) + +#define LORA_DIO_PORT (PortA) +#define LORA_DIO_PIN (Pin04) +#define LORA_DIO_GET() PORT_GetBit(LORA_DIO_PORT, LORA_DIO_PIN) +#define LORA_DIO_EXIT_CH (ExtiCh04) +#define LORA_DIO_EXIT_SRC (INT_PORT_EIRQ4) + +#define LORA_RESET_PORT (PortA) +#define LORA_RESET_PIN (Pin05) +#define LORA_RESET_SET() PORT_SetBits(LORA_RESET_PORT, LORA_RESET_PIN) +#define LORA_RESET_CLR() PORT_ResetBits(LORA_RESET_PORT, LORA_RESET_PIN) + +#define LORA_RXEN_PORT (PortB) +#define LORA_RXEN_PIN (Pin00) +#define LORA_RXEN_SET() PORT_SetBits(LORA_RXEN_PORT, LORA_RXEN_PIN) +#define LORA_RXEN_CLR() PORT_ResetBits(LORA_RXEN_PORT, LORA_RXEN_PIN) + +#define LORA_TXEN_PORT (PortB) +#define LORA_TXEN_PIN (Pin01) +#define LORA_TXEN_SET() PORT_SetBits(LORA_TXEN_PORT, LORA_TXEN_PIN) +#define LORA_TXEN_CLR() PORT_ResetBits(LORA_TXEN_PORT, LORA_TXEN_PIN) + +#define LORA_RX_LED_PORT (PortB) +#define LORA_RX_LED_PIN (Pin03) +#define LORA_RX_LED_SET() PORT_SetBits(LORA_RX_LED_PORT, LORA_RX_LED_PIN) +#define LORA_RX_LED_CLR() PORT_ResetBits(LORA_RX_LED_PORT, LORA_RX_LED_PIN) +#define LORA_RX_TOGGLE() PORT_Toggle(LORA_RX_LED_PORT, LORA_RX_LED_PIN) + +#define LORA_POW_PORT (PortC) +#define LORA_POW_PIN (Pin06) +#define LORA_POW_ON() PORT_SetBits(LORA_POW_PORT, LORA_POW_PIN) +#define LORA_POW_OFF() PORT_ResetBits(LORA_POW_PORT, LORA_POW_PIN) + +#define POWER_LED_PORT (PortB) +#define POWER_LED_PIN (Pin04) +#define POWER_LED_ON() PORT_SetBits(POWER_LED_PORT, POWER_LED_PIN) +#define POWER_LED_OFF() PORT_ResetBits(POWER_LED_PORT, POWER_LED_PIN) +#define POWER_TOGGLE() PORT_Toggle(POWER_LED_PORT, POWER_LED_PIN) + +#if USE_SD_CARD +#include "sd_card.h" +/* SDIOC Port/Pin definition */ +#define SDIOC_CD_PORT (PortA) +#define SDIOC_CD_PIN (Pin10) + +#define SDIOC_CK_PORT (PortC) +#define SDIOC_CK_PIN (Pin12) + +#define SDIOC_CMD_PORT (PortD) +#define SDIOC_CMD_PIN (Pin02) + +#define SDIOC_D0_PORT (PortC) +#define SDIOC_D0_PIN (Pin08) + +#define SDIOC_D1_PORT (PortC) +#define SDIOC_D1_PIN (Pin09) + +#define SDIOC_D2_PORT (PortA) +#define SDIOC_D2_PIN (Pin09) + +#define SDIOC_D3_PORT (PortC) +#define SDIOC_D3_PIN (Pin11) + +/* SD sector && count */ +#define SD_SECTOR_START (0u) +#define SD_SECTOR_COUNT (4u) + +/* SDIOC unit */ +#define SDIOC_UNIT (M4_SDIOC1) + +en_result_t SdioInit(void); +bool SDCardErase(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr); +bool SDCardReadBlocks(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr, uint8_t *ReadBuff); +bool SDCardWriteBlocks(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr, uint8_t *WriteBuff); +#endif + +#define BAT_COLL_ADC_CH (ADC1_CH1) + +//Ö¡Í·½á¹¹Ìå +typedef struct { + uint8_t Header; + uint8_t SlvAddr; + uint8_t Cmd; + uint8_t PayloadLen; +}update_protocol_hd_t; + +//Ö÷»úÏ·¢Éý¼¶ÇëÇóÔغɽṹÌå +typedef struct { + uint16_t PackageNum; + uint32_t AppSize; + uint32_t AppCrc32; +}__attribute__ ((packed))update_protocol_req_t; + +//´Ó»úÇëÇóÏ·¢½á¹¹Ìå +typedef struct { + uint16_t PackageIndex; + uint32_t PackageNum; +}__attribute__ ((packed))update_protocol_get_t; + +//Ö÷»úÓ¦´ðÏ·¢Êý¾Ý½á¹¹Ìå +typedef struct { + uint16_t PackageIndex; + uint16_t PackageNum; + uint8_t DataLen; +}__attribute__ ((packed))update_protocol_rsp_t; + +typedef struct { + uint32_t AppFlag; + uint32_t DevType; + uint32_t DevAddr; + uint32_t UpdateFlag; + uint32_t PackageNum; + uint32_t AppSize; + uint32_t Crc32Check; +}boot_para_t; + +void BSP_Init(void); + +void DbgUart_Config(uint32_t BaudRate); +void DebugUartSend(uint8_t *sData, uint16_t sLen); +void DbgRxIrqCallback(uint8_t rData); + +void RS485Ch1_Config(uint32_t BaudRate); +void RS485Ch1UartSend(uint8_t *sData, uint16_t sLen); +void RS485Ch1RxIrqCallback(uint8_t rData); + +void RS485Ch2_Config(uint32_t BaudRate); +void RS485Ch2UartSend(uint8_t *sData, uint16_t sLen); +void RS485Ch2RxIrqCallback(uint8_t rData); + +void EthOrCat1UartSend(uint8_t *sData, uint16_t sLen); +void EthOrCat1RxIrqCallback(uint8_t rData); + +void LoraTxRxIrqCallback(void); + +uint16_t Spi1SendReceive(uint16_t sData); +uint16_t Spi2SendReceive(uint16_t sData); + +//void ReadAdcValue(uint16_t *ADValue); +uint16_t GetADCBuffPoint(void); +void ADC_Start(void) ; + +void FeedDog(void); +void Error_Handler(void); + +int TimeTs(void); +void TimeShow(uint32_t dwStamp); +void TimeSync(time_t ts) ; +void TimeGet(struct tm *cTime); +void TimeSync2(uint8_t Year, uint8_t Month, uint8_t Day, uint8_t Hour, uint8_t Min, uint8_t Sec); + +void FlashWrite(uint32_t Addr, uint32_t *wData, uint8_t wLen); +void FlashRead(uint32_t Addr,uint32_t *rData, uint8_t rLen); +void dev_boot_read_param(boot_para_t *pParam); +int dev_boot_write_param(boot_para_t Param); +//extern stc_sd_handle_t stcSdhandle; +#endif + diff --git a/Project/GateWay/source/User/Inc/ddl_config.h b/Project/GateWay/source/User/Inc/ddl_config.h new file mode 100644 index 0000000..47ebdca --- /dev/null +++ b/Project/GateWay/source/User/Inc/ddl_config.h @@ -0,0 +1,164 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file ddl_config.h + ** + ** A detailed description is available at + ** @link DdlConfigGroup Ddl Config description @endlink + ** + ** - 2021-04-16 CDT First version for Device Driver Library config. + ** + ******************************************************************************/ +#ifndef __DDL_CONFIG_H__ +#define __DDL_CONFIG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DdlConfigGroup Device Driver Library config(DDLCONFIG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Chip module on-off define */ +#define DDL_ON (1u) +#define DDL_OFF (0u) + +/** + ******************************************************************************* + ** \brief This is the list of modules to be used in the device driver library + ** Select the modules you need to use to DDL_ON. + ** + ** \note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + ** properly. + ** + ** \note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + ** Library. + ** + ** \note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + ******************************************************************************/ +#ifndef BOOT_ENABLE +#define DDL_ICG_ENABLE (DDL_ON) +#endif + +//#define DDL_ICG_ENABLE (DDL_ON) +#define DDL_UTILITY_ENABLE (DDL_ON) +#define DDL_PRINT_ENABLE (DDL_OFF) + +#define DDL_ADC_ENABLE (DDL_ON) +#define DDL_AES_ENABLE (DDL_OFF) +#define DDL_CAN_ENABLE (DDL_OFF) +#define DDL_CLK_ENABLE (DDL_ON) +#define DDL_CMP_ENABLE (DDL_OFF) +#define DDL_CRC_ENABLE (DDL_OFF) +#define DDL_DCU_ENABLE (DDL_OFF) +#define DDL_DMAC_ENABLE (DDL_ON) +#define DDL_EFM_ENABLE (DDL_ON) +#define DDL_EMB_ENABLE (DDL_OFF) +#define DDL_EVENT_PORT_ENABLE (DDL_OFF) +#define DDL_EXINT_NMI_SWI_ENABLE (DDL_ON) +#define DDL_GPIO_ENABLE (DDL_ON) +#define DDL_HASH_ENABLE (DDL_OFF) +#define DDL_I2C_ENABLE (DDL_OFF) +#define DDL_I2S_ENABLE (DDL_OFF) +#define DDL_INTERRUPTS_ENABLE (DDL_ON) +#define DDL_INTERRUPTS_SHARE_ENABLE (DDL_OFF) +#define DDL_KEYSCAN_ENABLE (DDL_OFF) +#define DDL_MPU_ENABLE (DDL_OFF) +#define DDL_OTS_ENABLE (DDL_OFF) +#define DDL_PWC_ENABLE (DDL_ON) +#define DDL_QSPI_ENABLE (DDL_OFF) +#define DDL_RMU_ENABLE (DDL_OFF) +#define DDL_RTC_ENABLE (DDL_ON) +#define DDL_SDIOC_ENABLE (DDL_ON) +#define DDL_SPI_ENABLE (DDL_ON) +#define DDL_SRAM_ENABLE (DDL_ON) +#define DDL_SWDT_ENABLE (DDL_ON) +#define DDL_TIMER0_ENABLE (DDL_OFF) +#define DDL_TIMER4_CNT_ENABLE (DDL_OFF) +#define DDL_TIMER4_EMB_ENABLE (DDL_OFF) +#define DDL_TIMER4_OCO_ENABLE (DDL_OFF) +#define DDL_TIMER4_PWM_ENABLE (DDL_OFF) +#define DDL_TIMER4_SEVT_ENABLE (DDL_OFF) +#define DDL_TIMER6_ENABLE (DDL_OFF) +#define DDL_TIMERA_ENABLE (DDL_OFF) +#define DDL_TRNG_ENABLE (DDL_OFF) +#define DDL_USART_ENABLE (DDL_ON) +#define DDL_USBFS_ENABLE (DDL_OFF) +#define DDL_WDT_ENABLE (DDL_OFF) + + +/*! Midware module on-off define */ +#define MW_ON (1u) +#define MW_OFF (0u) + +/** + ******************************************************************************* + ** \brief This is the list of Midware modules to use + ** Select the modules you need to use to MW_ON. + ******************************************************************************/ +#define MW_FS_ENABLE (MW_OFF) +#define MW_SD_CARD_ENABLE (MW_OFF) +#define MW_W25QXX_ENABLE (MW_OFF) +#define MW_WM8731_ENABLE (MW_OFF) + +/* BSP on-off define */ +#define BSP_ON (1u) +#define BSP_OFF (0u) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F460_LQFP100_V1 (1u) +#define BSP_EV_HC32F460_LQFP100_V2 (2u) + +/** + * @brief The macro BSP_EV_HC32F460 is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to BSP_EV_HC32F460. + */ +#define BSP_EV_HC32F460 (BSP_EV_HC32F460_LQFP100_V2) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // DdlConfigGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __DDL_CONFIG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Project/GateWay/source/User/Inc/main.h b/Project/GateWay/source/User/Inc/main.h new file mode 100644 index 0000000..1741e94 --- /dev/null +++ b/Project/GateWay/source/User/Inc/main.h @@ -0,0 +1,16 @@ +#ifndef __MAIN__H +#define __MAIN__H +#include "bsp.h" +#include "Public.h" +#include "DebugCmd.h" + +#define SOFTWARE_VERSION 12 +#define HARDWARE_VERSION 12 + +#define MAC_ADDR_TYPE 1//0Ϊ²âÊÔ·þÎñÆ÷ + +extern bool MainDispEn; +#define MAIN_DBG_LOG(...) { if(MainDispEn) Debug_Printf(__VA_ARGS__);} + +void MainDBGOnOff(bool OnOff); +#endif diff --git a/Project/GateWay/source/User/Inc/protocol.h b/Project/GateWay/source/User/Inc/protocol.h new file mode 100644 index 0000000..168205a --- /dev/null +++ b/Project/GateWay/source/User/Inc/protocol.h @@ -0,0 +1,96 @@ +#ifndef _PROTOCOL_H_ +#define _PROTOCOL_H_ + + +#include "stdint.h" + +#define PROTOCOL_BUF_MAX (512) + +#define PROTOCOL_HEAD (0x527A) + +#define PROTOCOL_FRAME_HEAD_SIZE (7) // ×îС֡³¤£ºÍ·(2) + µØÖ·(2) + ÃüÁî(1) + ³¤¶È(2) + CRC(2) + +#define PROTOCOL_FRAME_MIN_SIZE (9) // ×îС֡³¤£ºÍ·(2) + µØÖ·(2) + ÃüÁî(1) + ³¤¶È(2) + CRC(2) +// ´íÎóÂ붨Òå +typedef enum { + PROTOCOL_SUCCESS = 0, + PROTOCOL_ERR_INVALID_PARAM, + PROTOCOL_ERR_BUFFER_OVERFLOW, + PROTOCOL_ERR_CRC +}protocol_err_t; + +typedef enum +{ + PROTOCOL_CMD_GET_AD =0x81, + PROTOCOL_CMD_GET_TP =0x82, + + PROTOCOL_CMD_SET_ID =0x83, + PROTOCOL_CMD_GET_ID =0x84, + + PROTOCOL_CMD_SET_TP_OFFSET =0x8A, + PROTOCOL_CMD_GET_TP_OFFSET =0x8B, + + PROTOCOL_CMD_RESET_CHANNEL =0x8F, + +}protocol_cmd_t; + +typedef struct __attribute__((packed)) { + uint8_t status; + float value; +} ch_data_t; + +typedef struct __attribute__((packed)) { + uint8_t dev_status; + ch_data_t channels[8]; + uint8_t reserved[7]; +} ad_datas_t; + +typedef struct __attribute__((packed)) { + uint8_t dev_status; + ch_data_t channels[8]; + uint8_t reserved[7]; +} tp_datas_t; + +typedef struct __attribute__((packed)) { + uint8_t id; + uint8_t reserved[3]; +} id_data_t; + +typedef struct __attribute__((packed)) { + uint8_t id; + union{ + uint8_t bytes[4]; + float value; + }prams; + +} offset_set_data_t,offset_get_data_t; + +typedef struct __attribute__((packed)) { + uint8_t id; +}offset_get_param_t; + +extern int protocol_pack_frame( + uint16_t slave_addr, + uint8_t command,const + uint8_t *payload, + uint16_t payload_len, + uint8_t *buffer,uint16_t buffer_size, + uint16_t *packed_len +); + +extern int protocol_unpack_frame( + const uint8_t *frame, + uint16_t frame_len, + uint16_t *slave_addr, + uint8_t *command, + uint8_t *payload, + uint16_t *payload_len); + +#endif + + + + + + + diff --git a/Project/GateWay/source/User/Inc/ringbuffer.h b/Project/GateWay/source/User/Inc/ringbuffer.h new file mode 100644 index 0000000..b517e6c --- /dev/null +++ b/Project/GateWay/source/User/Inc/ringbuffer.h @@ -0,0 +1,45 @@ +/****************************************************************************** + * @brief »·Ðλº³åÇø¹ÜÀí(²Î¿¼linux/kfifo) + * + * Copyright (c) 2016~2020, + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2016-05-30 Morro ³õ°æÍê³É + ******************************************************************************/ + +#ifndef _RING_BUF_H_ +#define _RING_BUF_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*»·Ðλº³åÇø¹ÜÀíÆ÷*/ +typedef struct { + unsigned char *buf; /*»·Ðλº³åÇø */ + unsigned int size; /*»·Ðλº³åÇø */ + unsigned int front; /*Í·Ö¸Õë */ + unsigned int rear; /*βָÕë */ +}ring_buf_t; + +bool ring_buf_init(ring_buf_t *r,unsigned char *buf,unsigned int size); + +void ring_buf_clr(ring_buf_t *r); + +int ring_buf_len(ring_buf_t *r); + +int ring_buf_put(ring_buf_t *r,unsigned char *buf,unsigned int len); + +int ring_buf_get(ring_buf_t *r,unsigned char *buf,unsigned int len); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Project/GateWay/source/User/Inc/spiflash.h b/Project/GateWay/source/User/Inc/spiflash.h new file mode 100644 index 0000000..48cd15b --- /dev/null +++ b/Project/GateWay/source/User/Inc/spiflash.h @@ -0,0 +1,76 @@ +#ifndef __SPI_FLASH_H +#define __SPI_FLASH_H + +#include "bsp.h" + +#define LOG_SAV_FLAG (0xAA5555AA) +#define LOG_INFO_SAV_FLAG (0xA55A) + +#define SpiFlashClrNss() SPI_NSS_CLR() +#define SpiFlashSetNss() SPI_NSS_SET() + +#define SPIFLASH_CMD_WRITE 0x02 /* Write to Memory instruction */ +#define SPIFLASH_CMD_WRSR 0x01 /* Write Status Register instruction */ +#define SPIFLASH_CMD_WREN 0x06 /* Write enable instruction */ +#define SPIFLASH_CMD_READ 0x03 /* Read from Memory instruction */ +#define SPIFLASH_CMD_RDSR 0x05 /* Read Status Register instruction */ +#define SPIFLASH_CMD_RDID 0x9F /* Read identification */ +#define SPIFLASH_CMD_SE 0x20 /* 4KSector Erase instruction */ +#define SPIFLASH_CMD_BE 0xC7 /* Bulk Erase instruction */ +#define SPIFLASH_WIP_FLAG 0x01 /* Write In Progress (WIP) flag */ +#define SPIFLASH_DUMMY_BYTE 0xA5 +#define SPIFLASH_PAGESIZE 0x100 +#define SPIFLASH_SECTORSIZE 4096 +#define SPIFLASH_M25P128_ID 0x202018 +#define SPIFLASH_M25P64_ID 0x202017 + +void SpiFlashEraseChip(void); +void SpiFlashEraseSector(uint32_t SectorAddr); +void SpiFlashWriteAnyLengthData(uint8_t* wData, uint32_t wAddr, uint16_t wLen); +void SpiFlashReadAnyLengthData(uint8_t* rData, uint32_t rAddr, uint16_t rLen); +uint32_t SpiFlashReadId(void); + +/* USER CODE BEGIN */ +#define SPIFLASH_SIZE 16777216 +#define SPIFLASH_SECTOR_NUM 4096 + +#define GATEWEY_PARA_SAV_ADDR 0x00 +#define GATEWEY_PARA_SAV_SECTOR 0x00 + +#define LOG_INFO_START_SECTOR 0x01 +#define LOG_SAV_START_SECTOR 0x02 + +//#if (LORA_MODULE == WH_LR36_L) +//#define LOG_SAV_SIZE 78 +//#define LOG_SAV_NUM_SECTOR 52 //ÿÉÈÇø´æ´¢ÊýÁ¿ +//#else +//#define LOG_SAV_SIZE 78 //150 +//#define LOG_SAV_NUM_SECTOR 52 //27 //ÿÉÈÇø´æ´¢ÊýÁ¿ +//#endif + +#define LOG_SAV_SIZE_MAX 256 +#define LOG_SAV_NUM_MAX ((SPIFLASH_SECTOR_NUM - LOG_SAV_START_SECTOR) * LOG_SAV_NUM_SECTOR) + +typedef struct { + uint32_t LogSavFlag; //ÈÕÖ¾´æ´¢±êÖ¾ + uint32_t LogIdx; //ÈÕÖ¾ÐòºÅ + uint32_t LogEndAddr; //ÈÕÖ¾½áÊøµØÖ· + uint32_t TimeStamp; //´æ´¢Ê±¼ä +}LogHeader_t, *LogHeader; + +void SavMMC5983Calib(uint8_t *wData, uint32_t wLen); +void ReadMMC5983Calib(uint8_t *rData, uint32_t rLen); + +void LogInit(void); +uint32_t ReadLogNum(void); +uint32_t ReadLastLogEndAddr(void); +uint32_t ReadFirstLogStartAddr(void); +void SavLogNum(uint32_t LogNum); +void AddLog(uint8_t *wData, uint32_t wLen); +int ReadLog(LogHeader Header, uint8_t **wData, uint32_t LogIdx); +int ReadPara(uint8_t *Para, uint32_t ParaLen); +int WritePara(uint8_t *Para, uint32_t ParaLen); + +/* USER CODE END */ + +#endif diff --git a/Project/GateWay/source/User/Inc/update_protocol.h b/Project/GateWay/source/User/Inc/update_protocol.h new file mode 100644 index 0000000..dfe4aba --- /dev/null +++ b/Project/GateWay/source/User/Inc/update_protocol.h @@ -0,0 +1,20 @@ +#ifndef _UPDATE_PROTOCOL_H_ +#define _UPDATE_PROTOCOL_H_ + +#include "stdint.h" + +#define CRC16_BASE 0xA001 + +typedef void (*update_send_t)(uint8_t *pBuf,uint16_t len); + +void update_init(update_send_t pCbs); + +int update_unpack(uint8_t* rxData, int rLen,uint8_t *cmd, uint8_t* dev_addr, void *pUser, int *pLen); + +void update_send_cmd(uint8_t Cmd, uint16_t Indx, int PageNum); + +#endif + + + + diff --git a/Project/GateWay/source/User/Inc/utils.h b/Project/GateWay/source/User/Inc/utils.h new file mode 100644 index 0000000..a0ed99d --- /dev/null +++ b/Project/GateWay/source/User/Inc/utils.h @@ -0,0 +1,8 @@ +#ifndef _UTILS_H_ +#define _UTILS_H_ + +#include "stdint.h" + +extern uint16_t modbus_crc16(uint8_t *buf, int len); + +#endif diff --git a/Project/GateWay/source/User/Src/ADS1231.c b/Project/GateWay/source/User/Src/ADS1231.c new file mode 100644 index 0000000..24265ad --- /dev/null +++ b/Project/GateWay/source/User/Src/ADS1231.c @@ -0,0 +1,126 @@ +#include "ADS1231.h" + +extern float Temperature; + + +void ADS1231_Open(void) +{ + PDWN1_SET(); + PDWN2_SET(); + PDWN3_SET(); + PDWN4_SET(); +} + +void ADS1231_HighSpeedSet(void) +{ + SPEED1_SET(); + SPEED2_SET(); + SPEED3_SET(); + SPEED4_SET(); +} + +void ADS1231_LowSpeedSet(void) +{ + SPEED1_RESET(); + SPEED2_RESET(); + SPEED3_RESET(); + SPEED4_RESET(); +} + +uint32_t GpioAGetDout(en_pin_t enPin) +{ + return *(uint32_t *)((uint32_t)(&M4_PORT->PIDRA)) & (enPin); +} + +uint32_t GpioBGetDout(en_pin_t enPin) +{ + return *(uint32_t *)((uint32_t)(&M4_PORT->PIDRB)) & (enPin); +} + +bool ADS1231_Read(uint32_t *r_data, uint8_t channel) { + uint8_t i; + uint32_t data = 0; + + switch(channel) { + case 0: + if(GpioAGetDout(DRDY_DOUT1_PIN) != 0) + return false; + + for(i = 0; i < 24; i++) { + SCLK1_SET(); + data <<= 0x01; + __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); + SCLK1_RESET(); + + if(GpioAGetDout(DRDY_DOUT1_PIN) != 0) + data |= 0x01; + } + SCLK1_SET(); + __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); + SCLK1_RESET(); + break; + case 1: + if(GpioAGetDout(DRDY_DOUT2_PIN) != 0) + return false; + + for(i = 0; i < 24; i++) { + SCLK2_SET(); + data <<= 0x01; + __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); + SCLK2_RESET(); + __NOP(); __NOP(); + if(GpioAGetDout(DRDY_DOUT2_PIN) != 0) + data |= 0x01; + } + SCLK2_SET(); + __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); + SCLK2_RESET(); + break; + case 2: + if(GpioBGetDout(DRDY_DOUT3_PIN) != 0) + return false; + + for(i = 0; i < 24; i++) { + SCLK3_SET(); + data <<= 0x01; + __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); + SCLK3_RESET(); + if(GpioBGetDout(DRDY_DOUT3_PIN) != 0 ) + data |= 0x01; + } + SCLK3_SET(); + __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); + SCLK3_RESET(); + break; + case 3: + if(GpioBGetDout(DRDY_DOUT4_PIN) != 0 ) + return false; + + for(i = 0; i < 24; i++) { + SCLK4_SET(); + data <<= 0x01; + __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); + SCLK4_RESET(); + if(GpioBGetDout(DRDY_DOUT4_PIN) != 0 ) + data |= 0x01; + } + SCLK4_SET(); + __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); + SCLK4_RESET(); + break; + default: + return false; + + } + + if(data <= 0x00ffffff) { + if(data > 0x007fffff) + *r_data = data|0xff000000; + else + *r_data = data; + } + else + return false; + + return true; +} diff --git a/Project/GateWay/source/User/Src/AppTask.c b/Project/GateWay/source/User/Src/AppTask.c new file mode 100644 index 0000000..e69de29 diff --git a/Project/GateWay/source/User/Src/CatOneTask.c b/Project/GateWay/source/User/Src/CatOneTask.c new file mode 100644 index 0000000..0a272d9 --- /dev/null +++ b/Project/GateWay/source/User/Src/CatOneTask.c @@ -0,0 +1,730 @@ +#include "CatOneTask.h" +#include "Public.h" +#include "DebugCmd.h" + +static rt_sem_t CatOneRev_Sem = RT_NULL; +static rt_sem_t CatOneIRQ_Sem = RT_NULL; +static rt_sem_t EthIRQ_Sem = RT_NULL; +static rt_thread_t Cat1Rev_Thread = RT_NULL; + +static uint8_t CAT1DispEn = false; +static CatOne_t CatOne; + +static char CatOneEthRxBuff[CAT_ONE_REV_LEN_MAX]; +static uint16_t CatOneEthRxLen; + +static uint8_t CatOneEthTxBuff[CAT_ONE_REV_LEN_MAX]; +static uint16_t CatOneEthTxLen; + +static uint8_t Payload[CAT_ONE_REV_LEN_MAX]; +static char CommUnitSendASCII[CAT_ONE_REV_LEN_MAX * 2]; + +static uint8_t EthRevTimeOutCnt; + +static uint16_t CatSendErrCnt = 0; + +#define CAT1_DBG_LOG(...) { if(CAT1DispEn) Debug_Printf(__VA_ARGS__);} +//#define CAT1_DBG_ARRAY(ARRAY, SIZE) { if(CAT1DispEn) {DBG_ARRAY(ARRAY,SIZE)}} + +#define CATONE_RESET_DELAY_TIME_MAX (5 * 60 * 1000) + +const char *CatOneATCmdStr[16] = { + "NULL", + "AT\r\n", //¿ª»ú¼ì²â + "ATE0\r\n", //¹Ø»ØÏÔ + "AT+CPIN?\r\n", //ʶ¿¨ +// "AT+CIMI\r\n", //IMEI + "AT+CGSN=1\r\n", + "AT+LCCID\r\n", //¶Á¿¨ºÅ + "AT+CEREG?\r\n", //²éѯע²á״̬ + "AT+CGPADDR=1\r\n", //²éѯIPµØÖ· + "AT+CSQ\r\n", //²éѯÐźÅÇ¿¶È + "AT+LDNSGIP=gxjt.cui635.cn\r\n", + "AT+LBS=0\r\n", //»ñÈ¡»ùÕ¾¶¨Î»ÐÅÏ¢ + "AT+LIPOPEN=", //ÉèÖÃTCP·þÎñÆ÷µØÖ·ºÍ¶Ë¿Ú£¬AT+LIPOPEN="TCP","114.55.52.96",6803 + "AT+LIPSEND=", //·¢ËÍÊý¾Ý, AT+LIPSEND=0,1,20,"31313131313131323232323232" + "AT+LIPCLOSE=0\r\n",//¶Ï¿ªÁ¬½Ó + "AT+LBSPARA=http://locator-aep.xiot.senthink.com:80/locator/v0.1/locate,B84E427D95B1DF4A3F49B18DDF714C72\r\n", + "AT+CCLK?\r\n", //»ñȡʱ¼ä +}; + +void Cat1DBGOnOff(bool OnOff) +{ + CAT1DispEn = OnOff; + if(OnOff) + Debug_Printf("\r\nCat1 Display Enable!\r\n\r\n"); + else + Debug_Printf("\r\nCat1 Display Disable!\r\n\r\n"); +} + +const CatOneATCMD_m CatOneModeSetCmdArray[] = { + CAT_ONE_AT_NULL, + CAT_ONE_AT, + CAT_ONE_ATE0, + //CAT_ONE_LBSPARA, + CAT_ONE_LCCID, + CAT_ONE_IMEI, + CAT_ONE_CPIN, + CAT_ONE_CEREG, + CAT_ONE_CSQ, + //CAT_ONE_LDNSGIP, + //CAT_ONE_LBS, + CAT_ONE_CCLK, + CAT_ONE_AT_CMD_END +}; + +//CatOneRetStatus_m CatOneSend(uint8_t *sData, uint16_t sLen) +//{ +// rt_err_t result; +// +// if(CatOne.Status != CAT_ONE_IDEL && CatOne.Status != CAT_ONE_WAIT_SEND) +// return CAT_ONE_RET_ERR; +// +// //CatOne.Status = CAT_ONE_RESET; +// result = rt_mq_send(CatOneRev_MQ, sData, sLen); +// if(result != RT_EOK) { +// CAT1_DBG_LOG("CatOne MQ Send ERR...\r\n"); +// return CAT_ONE_RET_ERR; +// } +// CAT1_DBG_LOG("CatOne Send Message: \r\n", sData); +// return CAT_ONE_RET_OK; +//} + +void CatOneStop(void) +{ + CatOne.Status = CAT_ONE_OFF; +} + +void CatOneGetLocationInfo(int *Longitude, int *Latitude) +{ + if(CatOne.LBSFlag) { + *Longitude = CatOne.Longitude; + *Latitude = CatOne.Latitude; + } + else { + *Longitude = 0; + *Latitude = 0; + } +} + +void CatOneGetIMEIAndSIM(char *Imei, char *Sim) +{ + memcpy(Imei, CatOne.IMEI, 15); + memcpy(Sim, CatOne.SIM, 20); +} + +//·µ»Øtrue-busy, false-Idle +bool CatOneGetStatus(void) +{ + if(CatOne.Status == CAT_ONE_IDEL) + return false; + return true; +} + +void CatOneReset(void) +{ + CatOne.Status = CAT_ONE_RESET; +} + +void CatTimeSync(char *Data) +{ + struct tm sTimet; + time_t sTime; + char *p; + + p = strchr(Data, '\"'); + if(p == NULL) + return; + + int ret = sscanf(p, "\"%d/%d/%d,%d:%d:%d+", + &sTimet.tm_year, &sTimet.tm_mon, &sTimet.tm_mday, + &sTimet.tm_hour, &sTimet.tm_min, & sTimet.tm_sec); + if(ret != 6) { + int ret = sscanf(p, "\"%d/%d/%d,%d:%d:%d-", + &sTimet.tm_year, &sTimet.tm_mon, &sTimet.tm_mday, + &sTimet.tm_hour, &sTimet.tm_min, & sTimet.tm_sec); + if(ret != 6) + return; + } + + sTimet.tm_isdst = 0; + if(sTimet.tm_year < 24 || sTimet.tm_year > 50) + return; + sTimet.tm_year += 100; + + if(sTimet.tm_mon > 12 || sTimet.tm_mon == 0) + return; + sTimet.tm_mon--; + + sTime = mktime(&sTimet); + TimeSync(sTime); + CAT1_DBG_LOG("Set Time:"); + TimeShow(TimeTs()); +} + +void CatOneAtCmdAnalyze(char *RxBuff) +{ + char *p; + int ret; + + CatOne.ATCmdRet = CAT_ONE_RET_OK; + CAT1_DBG_LOG(RxBuff); + + switch(CatOne.AtCmd) { + case CAT_ONE_AT: + case CAT_ONE_ATE0: + case CAT_ONE_LIPSEND: + case CAT_ONE_LDNSGIP: + case CAT_ONE_LBSPARA: + if(strstr(RxBuff, "OK") == NULL) { + CatOne.ATCmdRet = CAT_ONE_RET_ERR; + } + break; + + case CAT_ONE_IMEI: + if(strstr(RxBuff, "OK") == NULL) { + CatOne.ATCmdRet = CAT_ONE_RET_ERR; + } + p = strstr(RxBuff, "+CGSN"); + if(p == NULL) { + CatOne.ATCmdRet = CAT_ONE_RET_ERR; + } + p = strchr(p, '"'); + if(p != NULL) { + memcpy(CatOne.IMEI, p+1, 15); + } + else { + memset(CatOne.IMEI, 0, 15); + } +// ret = sscanf(p, "+CGSN: \"%s\"\r\n", CatOne.IMEI); +// if(ret != 1) { +// memset(CatOne.IMEI, 0, 15); +// } + CatOne.IMEI[15] = 0; + break; + + case CAT_ONE_CCLK: + if(strstr(RxBuff, "+CCLK") != NULL) { + CatTimeSync(RxBuff); + } + break; + + case CAT_ONE_LCCID: + if(strstr(RxBuff, "OK") == NULL) { + CatOne.ATCmdRet = CAT_ONE_RET_ERR; + } + p = strstr(RxBuff, "+LCCID"); + if(p == NULL) { + CatOne.ATCmdRet = CAT_ONE_RET_ERR; + } + memset(CatOne.SIM, 0, 32); + ret = sscanf(p, "+LCCID: %s\r\n", CatOne.SIM); + if(ret != 1) { + memset(CatOne.SIM, 0, 32); + } + break; + + case CAT_ONE_LBS: + p = strstr(RxBuff, "+LBS"); + if(p != NULL) { + double Longitude, Latitude; + int ret = sscanf(p, "+LBS: %lf,%lf\r\n", &Longitude, &Latitude); + if(ret == 2) { + CatOne.LBSFlag = true; + CatOne.Longitude = Longitude * 100000; + CatOne.Latitude = Latitude * 100000; + } + } + break; + + case CAT_ONE_LIPOPEN: + if(strstr(RxBuff, "OK") != NULL) { + CatOne.Status = CatOne.NextStatus; + CatOne.CatOne1mSDelayCnt = 10 * 1000; + return; + } + else { + if(strstr(RxBuff, "LIPOPEN: 0,1") != NULL) { + CAT1_DBG_LOG("Cat1 successfully to connect to the server.\r\n\r\n"); + CatOne.TcpConnFlag = true; + CatOne.Status = CatOne.NextStatus; + rt_sem_release(CatOneRev_Sem); + } + else if(strstr(RxBuff, "LIPOPEN: 0,0") != NULL) { + CAT1_DBG_LOG("Cat1 failed to connect to the server.\r\n\r\n"); + CatOne.TcpConnFlag = false; + CatOne.Status = CAT_ONE_OFF; + } + return; + } + + case CAT_ONE_CPIN: + if(strstr(RxBuff, "READY") == NULL) { + CatOne.ATCmdRet = CAT_ONE_RET_ERR; + } + break; + + case CAT_ONE_CEREG: + if(strstr(RxBuff, "CEREG: 0,1") == NULL) { + CatOne.CatOne1mSDelayCnt = 3000; + CatOne.ATCmdRet = CAT_ONE_RET_ERR; + } + break; + + case CAT_ONE_CGPADDR: + if(strstr(RxBuff, "+CGPADDR") == NULL) { + CatOne.ATCmdRet = CAT_ONE_RET_ERR; + } + break; + + case CAT_ONE_CSQ: + if(strstr(RxBuff, "+CSQ") == NULL) { + CatOne.ATCmdRet = CAT_ONE_RET_ERR; + } + break; + + case CAT_ONE_LTPCLOSE: + if(strstr(RxBuff, "CLOSE OK") != NULL) { + break; + } + else if(strstr(RxBuff, "ERROR") != NULL) { + break; + } + else if(strstr(RxBuff, "OK") != NULL){ + break; + } + CatOne.ATCmdRet = CAT_ONE_RET_ERR; + break; + case CAT_ONE_AT_NULL: + p = strstr(RxBuff, "+LIPURC"); + if(p != NULL) { + char rData[120]; + uint8_t hData[60]; + int rLen, hLen, ret; + + if(strstr(p, "+LIPURC: 0,0") != NULL) { + CAT1_DBG_LOG("TCP connection disconnected.\r\n\r\n"); + CatOne.TcpConnFlag = false; + CatOne.Status = CAT_ONE_OFF; + return; + } + + ret = sscanf(p, "+LIPURC: 0,1,%d,%s\r\n", &rLen, rData); + if(ret == 2) { + if(rLen < 24) + return; + memset(hData, 0x00, 60); + hLen = AsciiToHex(rData, hData, rLen); + CatSendErrCnt = 0; + CatOne.GateWay->SvrRevCallBack(CatOne.GateWay, hData, hLen); + } + else { + return; + } + //CatOne.Status = CAT_ONE_CLOSE_TCP; + rt_sem_release(CatOneRev_Sem);//½ÓÊÕÈÎÎñ + return; + } + default: + CatOne.ATCmdRet = CAT_ONE_RET_ERR; + + } + if(CatOne.ATCmdRet == CAT_ONE_RET_OK) { + CatOne.Status = CatOne.NextStatus; + if(CatOne.AtCmd == CAT_ONE_LIPSEND) + CatOne.CatOne1mSDelayCnt = 5 * 1000; + else + CatOne.CatOne1mSDelayCnt = 10; + CatOne.AtCmd = CAT_ONE_AT_NULL; + rt_sem_release(CatOneRev_Sem); + } +} + +void CatOneAtCmdSend(CatOneATCMD_m Cmd, uint32_t Dly, CatOneStatus_m NextStatus) +{ + CatOne.AtCmd = Cmd; + if(CatOne.AtCmd == CAT_ONE_LIPSEND) { + HexToAscii(CatOneEthTxBuff, CommUnitSendASCII, CatOneEthTxLen); + sprintf(CatOne.CatOneSendBuff,"AT+LIPSEND=0,1,%d,\"%s\"\r\n",CatOneEthTxLen * 2, CommUnitSendASCII); + CatOne.GateWay->BatteryReadDlyCnt = 30; + } + else if(CatOne.AtCmd == CAT_ONE_LIPOPEN) { + sprintf(CatOne.CatOneSendBuff,"AT+LIPOPEN=\"TCP\",\"%d.%d.%d.%d\",%d\r\n", + CatOne.GateWay->ConfigPara.SvrAddr[0], + CatOne.GateWay->ConfigPara.SvrAddr[1], + CatOne.GateWay->ConfigPara.SvrAddr[2], + CatOne.GateWay->ConfigPara.SvrAddr[3], + CatOne.GateWay->ConfigPara.SvrPort); + } + else { + strcpy(CatOne.CatOneSendBuff, CatOneATCmdStr[CatOne.AtCmd]); + } + CAT1_DBG_LOG(CatOne.CatOneSendBuff); + EthRevTimeOutCnt = 0; + EthOrCat1UartSend((uint8_t *)CatOne.CatOneSendBuff, strlen(CatOne.CatOneSendBuff)); + CatOne.CatOne1mSDelayCnt = Dly; + CatOne.Status = CAT_ONE_WAIT_REV; + CatOne.NextStatus = NextStatus; +} + +int GateWayRegister(uint8_t *TxBuff) +{ + uint16_t UnitCommCnt = 0; + uint8_t *p = &TxBuff[0]; + uint16_t len = 5; + + if(CatOne.GateWay->ConfigPara.Rs485Ch1.CommUnitEnable == true && CatOne.GateWay->ConfigPara.Rs485Ch1.Enable == true) { + UnitCommCnt++; + memcpy(&p[len], CatOne.GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0], 6); + len += 6; + } + if(CatOne.GateWay->ConfigPara.Rs485Ch2.CommUnitEnable == true && CatOne.GateWay->ConfigPara.Rs485Ch2.Enable == true) { + UnitCommCnt++; + memcpy(&p[len], CatOne.GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0], 6); + len += 6; + } + for(int i = 0; i < COMMUNIT_NUM_MAX; i++) { + if(CatOne.GateWay->ConfigPara.CommUnitArray[i].RegFlag == true) { + for(int j = 0; j < CatOne.GateWay->ConfigPara.CommUnitArray[i].SensorN; j++) + { + memcpy(&p[len], CatOne.GateWay->ConfigPara.CommUnitArray[i].Mac[j], 6); + len += 6; + UnitCommCnt++; + } + } + } + TxBuff[0] = (len - 3) & 0x00ff; + TxBuff[1] = ((len - 3) >> 8) & 0x00ff; + TxBuff[2] = NET_COMM_CMD_REG; + TxBuff[3] = UnitCommCnt & 0x00ff; + TxBuff[4] = (UnitCommCnt >> 8) & 0x00ff; + return len; +} + +void CatOneLoopHandler(void) +{ + static rt_err_t result; + uint16_t ret; + static uint8_t Cat1RevErrCnt = 0; + + switch(CatOne.Status){ + case CAT_ONE_IDEL: + rt_thread_delay(1); + if(CatOne.ResetDelayCnt > 0) { + CatOne.ResetDelayCnt--; + } + else { + CatOne.Status = CAT_ONE_RESET; + } + break; + + case CAT_ONE_WAIT_REV: + result = rt_sem_take(CatOneRev_Sem, CatOne.CatOne1mSDelayCnt); + if(result != RT_EOK) { + if(CatOne.AtCmdResendCnt > 0) { + CatOne.AtCmdResendCnt--; + CatOneAtCmdSend(CatOne.AtCmd, 2000, CatOne.NextStatus); + CAT1_DBG_LOG("Cat1 Ret TimeOut, ReSend(%d)...\r\n", CatOne.AtCmdResendCnt); + } + else { //3´Î´íÎ󣬹ػú + CAT1_DBG_LOG("Cat1 error, Close!\r\n"); + if(CatOne.AtCmd == CAT_ONE_LIPSEND) + CatOne.Status = CAT_ONE_CLOSE_TCP; + else + CatOne.Status = CAT_ONE_OFF; + } + } + break; + + case CAT_ONE_INIT: + CatOne.AtCmdIdx++; + if(CatOneModeSetCmdArray[CatOne.AtCmdIdx] != CAT_ONE_AT_CMD_END) { + if(CatOneModeSetCmdArray[CatOne.AtCmdIdx] == CAT_ONE_CEREG) + CatOne.AtCmdResendCnt = 30; + else + CatOne.AtCmdResendCnt = 3; + CatOneAtCmdSend(CatOneModeSetCmdArray[CatOne.AtCmdIdx], 1000, CAT_ONE_INIT); + } + else { + CatOne.Status = CAT_ONE_TCP_CONN; + CatOne.CatOne1mSDelayCnt = 0; + CatOne.AtCmdIdx = 0; + CatOne.AtCmd = CAT_ONE_AT_NULL; + } + break; + + case CAT_ONE_TCP_CONN: + CatOneAtCmdSend(CAT_ONE_LIPOPEN, 2000, CAT_ONE_WAIT_CONN); + break; + + case CAT_ONE_WAIT_CONN: + if(CatOne.TcpConnFlag) { + if(CatOne.GateWay->SvrRegFlag == false) + CatOne.Status = CAT_ONE_REG_SVR; + else + CatOne.Status = CAT_ONE_WAIT_SEND; + } + break; + + case CAT_ONE_REG_SVR: //×¢²á·þÎñÆ÷ + ret = GateWayRegister(CatOneEthTxBuff); + rt_mq_send(CatOne.GateWay->NetSendData_MQ, CatOneEthTxBuff, ret); + CatOne.Status = CAT_ONE_WAIT_SEND; + break; + + case CAT_ONE_WAIT_SEND: + result = rt_mq_recv(CatOne.GateWay->NetSendData_MQ, Payload, CAT_ONE_REV_LEN_MAX, 1000); + if(result == RT_EOK) { + CatOneEthTxLen = NetCommOrgData(CatOne.GateWay, Payload, CatOneEthTxBuff); + CatOne.Status = CAT_ONE_SEND_DATA; + } + else { + if(CatOne.Status == CAT_ONE_RESET || CatOne.Status == CAT_ONE_OFF) //ÍⲿÃüÁîÖ´ÐУ¬×´Ì¬¸Ä±ä + return; + if(!CatOne.TcpConnFlag) { + CatOne.Status = CAT_ONE_OFF; + } + else { + CatSendErrCnt++; + if(CatSendErrCnt > CAT1_ERR_RESET_DLY_MAX) { + CatOne.Status = CAT_ONE_RESET; + CAT1_DBG_LOG("Cat1 has no data for a long time, Reset!\r\n"); + CatSendErrCnt = 0; + break; + } + CatOne.Status = CAT_ONE_WAIT_SEND; + } + } + break; + + case CAT_ONE_SEND_DATA: + CatOne.AtCmdResendCnt = 3; + Cat1RevErrCnt++; + if(Cat1RevErrCnt > 10) { + CatOne.Status = CAT_ONE_RESET; + CAT1_DBG_LOG("Cat1 has no receive data for a long time, Reset!\r\n"); + Cat1RevErrCnt = 0; + break; + } + CatOneAtCmdSend(CAT_ONE_LIPSEND, 5000, CAT_ONE_REV_DATA); + break; + + case CAT_ONE_REV_DATA: + result = rt_sem_take(CatOneRev_Sem, CatOne.CatOne1mSDelayCnt); + if(result != RT_EOK) { + if(CatOne.TcpConnFlag == false) { + CAT1_DBG_LOG("Cat1 Rec Server Data Timeout!\r\n"); + break; + } + } + else { + Cat1RevErrCnt = 0; + } + if(CatOne.GateWay->SvrRegFlag == false) //É豸ûע²á£¬¹Ø±Õ4G£¬µÈ´ýÏÂÒ»´ÎÖØÐÂ×¢²á + CatOne.Status = CAT_ONE_OFF; + else + CatOne.Status = CAT_ONE_WAIT_SEND; + break; + + case CAT_ONE_CLOSE_TCP: + CatOne.AtCmdResendCnt = 3; + CatOneAtCmdSend(CAT_ONE_LTPCLOSE, 1000, CAT_ONE_OFF); + break; + + case CAT_ONE_OFF: + //CAT1_POW_OFF(); + CAT1_RESET_SET(); + CAT1_PWR_KEY_CLR(); + rt_thread_delay(3000); + CAT1_PWR_KEY_SET(); + CatSendErrCnt = 0; + CAT1_DBG_LOG("Cat1 Power Off!\r\n"); + CatOne.Status = CAT_ONE_IDEL; + CatOne.ResetDelayCnt = CATONE_RESET_DELAY_TIME_MAX; + break; + + case CAT_ONE_RESET: + CatSendErrCnt = 0; + CAT1_DBG_LOG("Cat1 Reset!\r\n"); + CAT1_RESET_CLR(); + CAT1_PWR_KEY_SET(); + //CAT1_POW_ON(); + rt_thread_delay(50); + CAT1_RESET_SET(); + CAT1_PWR_KEY_CLR(); + rt_thread_delay(1000); + CAT1_PWR_KEY_SET(); + CatOne.Status = CAT_ONE_INIT; + CatOne.AtCmdIdx = 0; + rt_thread_delay(1000); + CatOne.GateWay->BatteryReadDlyCnt = 60; + break; + } +} + +void EthLoopHandler(void) +{ + rt_err_t result; + + if(CatOne.GateWay->SvrRegFlag == false) { + if(CatOne.RegisterDelayCnt == 0) { + if(ETH_LINK_GET() == Reset) { + CatOne.RegisterDelayCnt = REGISTER_INTERVAL_MAX * 10; + uint8_t ret = GateWayRegister(CatOneEthTxBuff); + rt_mq_send(CatOne.GateWay->NetSendData_MQ, CatOneEthTxBuff, ret); + } + } + else { + CatOne.RegisterDelayCnt--; + } + } + result = rt_mq_recv(CatOne.GateWay->NetSendData_MQ, Payload, CAT_ONE_REV_LEN_MAX, 100); + if(result == RT_EOK) { + CatOneEthTxLen = NetCommOrgData(CatOne.GateWay, Payload, CatOneEthTxBuff); + HexToAscii(CatOneEthTxBuff, CommUnitSendASCII, CatOneEthTxLen); + EthRevTimeOutCnt = 0; + EthOrCat1UartSend((uint8_t *)CommUnitSendASCII, CatOneEthTxLen * 2); + CommUnitSendASCII[CatOneEthTxLen * 2] = 0; + CAT1_DBG_LOG("Eth Send: %s\r\n",CommUnitSendASCII); + } +} + +bool CatOneEthSendQueue(uint8_t *sData, uint16_t sLen) +{ + if(CatOne.GateWay->SvrRegFlag == false) + return false; + rt_mq_send(CatOne.GateWay->NetSendData_MQ, sData, sLen); + return true; +} + +static void CatOneInit(GateWayPara GateWay) +{ + memset(&CatOne, 0x00, sizeof(CatOne_t)); + CatOne.Status = CAT_ONE_RESET; + CatOne.GateWay = GateWay; + CatOne.CatOneRevCallBack = GateWay->SvrRevCallBack; +} + +void CatOneEthRev_Thread_Entry(void *parameter) +{ + rt_err_t result; + char RxBuffTemp[CAT_ONE_REV_LEN_MAX]; + uint8_t HexData[CAT_ONE_REV_LEN_MAX / 2]; + + GateWayPara GateWay = (GateWayPara)parameter; + + rt_kprintf("CatOneTthRev Thread is running!\r\n"); + + while(1) { + if(GateWay->ConfigPara.Comm == CATONE_COMM) { + result = rt_sem_take(CatOneIRQ_Sem, 500); + if(result == RT_EOK) { + memcpy(RxBuffTemp, CatOneEthRxBuff, CatOneEthRxLen); + RxBuffTemp[CatOneEthRxLen] = 0; + CatOneAtCmdAnalyze(RxBuffTemp); + memset(CatOneEthRxBuff, 0x00, CAT_ONE_REV_LEN_MAX); + CatOneEthRxLen = 0; + } + //CatOneEthRxLen = 0; + } + else if(GateWay->ConfigPara.Comm == ETH_COMM) { + result = rt_sem_take(EthIRQ_Sem, 500); + if(result == RT_EOK) { + memcpy(RxBuffTemp, CatOneEthRxBuff, CatOneEthRxLen); + RxBuffTemp[CatOneEthRxLen] = 0; + CAT1_DBG_LOG("Eth Rev: %s\r\n",RxBuffTemp); + memset(HexData, 0x00, CatOneEthRxLen / 2); + uint8_t ret = AsciiToHex(RxBuffTemp, HexData, CatOneEthRxLen); + if(ret > 0) + GateWay->SvrRevCallBack(GateWay, HexData, ret); + memset(CatOneEthRxBuff, 0x00, CAT_ONE_REV_LEN_MAX); + CatOneEthRxLen = 0; + } + //CatOneEthRxLen = 0; + } + } +} + +void CatOne_Eth_Thread_Entry(void *parameter) +{ + GateWayPara GateWay = (GateWayPara)parameter; + + CatOneRev_Sem = rt_sem_create("cat1r_sem", 0, RT_IPC_FLAG_FIFO); + if(CatOneRev_Sem == RT_NULL) { + rt_kprintf("CatOne Sem Create Failed!\r\n"); + } + + EthIRQ_Sem = rt_sem_create("eth_sem", 0, RT_IPC_FLAG_FIFO); + if(EthIRQ_Sem == RT_NULL) { + rt_kprintf("Eth Sem Create Failed!\r\n"); + } + + CatOneIRQ_Sem = rt_sem_create("cat1_sem", 0, RT_IPC_FLAG_FIFO); + if(CatOneIRQ_Sem == RT_NULL) { + rt_kprintf("CatOneIRQ Sem Create Failed!\r\n"); + } + + CatOneInit(GateWay); + ETH_RESET_CLR(); + rt_thread_delay(10); + ETH_RESET_SET(); + Cat1Rev_Thread = rt_thread_create("Cat1Rev", CatOneEthRev_Thread_Entry, parameter, 3000, 3, 20); + if (Cat1Rev_Thread != RT_NULL) { + rt_thread_startup(Cat1Rev_Thread); + } + else { + rt_kprintf("CatOneRev Thread Create Failed! Exit...\r\n"); + return; + } + rt_kprintf("CatOne Thread is running£¡\r\n"); + + while(1) { + //rt_mutex_take(GateWay->UartRevMutex, RT_WAITING_FOREVER); + if(GateWay->ConfigPara.Comm == CATONE_COMM) + CatOneLoopHandler(); + else if(GateWay->ConfigPara.Comm == ETH_COMM) + EthLoopHandler(); + else + rt_thread_delay(1); + //rt_mutex_release(GateWay->UartRevMutex); + } +} + + +void EthOrCat1RxIrqCallback(uint8_t rData) +{ + if(EthRevTimeOutCnt == 0) + CatOneEthRxLen = 0; + + if(CatOneEthRxLen < CAT_ONE_REV_LEN_MAX) { + CatOneEthRxBuff[CatOneEthRxLen++] = rData; + } + + EthRevTimeOutCnt = 3; +} + +void EthRxOverhandler(void) +{ + if(EthRevTimeOutCnt > 0) + EthRevTimeOutCnt--; + + if(CatOneEthRxLen > 5 && EthRevTimeOutCnt == 0) { + EthRevTimeOutCnt = 20; + if(CatOne.GateWay->ConfigPara.Comm == CATONE_COMM) + rt_sem_release(CatOneIRQ_Sem); + else + rt_sem_release(EthIRQ_Sem); + } +} + +void CatReadImeiOrSim(char *Imei, char *Sim) +{ + if(Imei != NULL) { + memcpy(Imei, CatOne.IMEI, 15); + Imei[15] = 0x00; + } + if(Sim != NULL) { + memcpy(Sim, CatOne.SIM, 20); + Sim[20] = 0x00; + } +} diff --git a/Project/GateWay/source/User/Src/DebugCmd.c b/Project/GateWay/source/User/Src/DebugCmd.c new file mode 100644 index 0000000..39da31c --- /dev/null +++ b/Project/GateWay/source/User/Src/DebugCmd.c @@ -0,0 +1,1686 @@ +#include "main.h" +#include "CatOneTask.h" +#include "RS485Task.h" +#include "Public.h" +#include +#include "spiflash.h" +#include "LoraTask.h" + +#define DBG_RX_LEN_MAX 128 +//#define DBG_LOG(...) rt_kprintf(__VA_ARGS__) +#define DEBUG_CMD_CNT 22 +#define DEBUG_BUFF_SIZE_MAX 512 + +#define DEBUG_BUFSIZE 200 +#define DEBUG_BUFF_MAX 1024 + +void Debug_Printf(char *format, ...); + +#define DBG_LOG(...) Debug_Printf(__VA_ARGS__) + +typedef void (*DebugExec)(int argc, char *argv[]); + +typedef struct{ + char *DBGCmd; + DebugExec DBGExec; +}DBGFunType; + +const DBGFunType DebugFun[DEBUG_CMD_CNT]; + +static GateWayPara GateWay; +static char buff[DBG_RX_LEN_MAX]; +static uint8_t DebugRxLen; +static uint8_t DebugRxBuff[DBG_RX_LEN_MAX]; +static uint8_t DebugRxTimeOut1mSCnt; +static rt_sem_t DebugRev_Sem; +static uint16_t ir=0; /* buffer read index*/ +static char tempBuff[DEBUG_BUFF_MAX]; + +void vcom_Print(uint8_t sLen) +{ + char* CurChar; + ir = 0; + while(ir < sLen) + { + CurChar = &buff[ir++]; + if(GateWay->ConfigPara.DebugChannel == DEBUG_CH_RS485_1) + RS485Ch1UartSend((uint8_t*)CurChar, 1); + else if(GateWay->ConfigPara.DebugChannel == DEBUG_CH_RS485_2) + RS485Ch2UartSend((uint8_t*)CurChar, 1); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: Debug_Printf +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1ÈÎÎñº¯Êý +* ²Î Êý: ÈÎÎñ²ÎÊýÈë¿Ú +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void Debug_Printf(char *format, ...) +{ + va_list args; + va_start(args, format); + uint16_t len; + //uint32_t primask_bit; + uint16_t offset = 0; + //primask_bit = __get_PRIMASK(); + //__disable_irq(); + + /*convert into string at buff[0] of length iw*/ + len = vsprintf(&tempBuff[0], format, args); + if(GateWay->ConfigPara.DebugChannel == DEBUG_CH_DBG) { + rt_kprintf(tempBuff); + } + else { + while(offset < len) { + if((len - offset) < DEBUG_BUFSIZE) { + memcpy(&buff[0], &tempBuff[offset], len - offset); + vcom_Print(len - offset); + offset = len; + } + else { + memcpy(&buff[0], &tempBuff[offset], DEBUG_BUFSIZE); + offset += DEBUG_BUFSIZE; + vcom_Print(DEBUG_BUFSIZE); + } + } + } + //__set_PRIMASK(primask_bit); + //__enable_irq(); + + va_end(args); +} +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch2_Thread_Entry +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1ÈÎÎñº¯Êý +* ²Î Êý: ÈÎÎñ²ÎÊýÈë¿Ú +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void Debug_Thread_Entry(void *parameter) +{ + GateWay = (GateWayPara)parameter; + rt_err_t result; + + DebugRev_Sem = rt_sem_create("debug_sem", 0, RT_IPC_FLAG_FIFO); + if(DebugRev_Sem == RT_NULL) { + rt_kprintf("DebugRev Sem Create Failed!\r\n"); + } + rt_kprintf("DebugRev Thread is running£¡\r\n"); + + while(1) { + result = rt_sem_take(DebugRev_Sem, RT_WAITING_FOREVER); + if(result == RT_EOK) { + DebugAnalyze(GateWay, DebugRxBuff, DebugRxLen); + DebugRxTimeOut1mSCnt = 0; + DebugRxLen = 0; + } + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch2RxIrqCallback +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1Öжϴ¦Àí»Øµ÷º¯Êý +* ²Î Êý: rData ½ÓÊÕµ½µÄÊý¾Ý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DbgRxIrqCallback(uint8_t rData) +{ + if(DebugRxTimeOut1mSCnt == 0) + DebugRxLen = 0; + + DebugRxTimeOut1mSCnt = 3; + if(DebugRxLen < DBG_RX_LEN_MAX) { + DebugRxBuff[DebugRxLen++] = rData; + } +} + + +void DebugRxOverhandler(void) +{ + if(DebugRxTimeOut1mSCnt > 0) + DebugRxTimeOut1mSCnt--; + + if(DebugRxLen > 2 && DebugRxTimeOut1mSCnt == 0) { + DebugRxTimeOut1mSCnt = 20; + rt_sem_release(DebugRev_Sem); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugAnalyze +* ¹¦ÄÜÃèÊö: µ÷ÊÔÖ¸Áî½âÎö +* ²Î Êý: GateWay, Íø¹Ø²ÎÊý¾ä±ú + rData,ÊäÈëÊý¾Ý + rLen, ÊäÈëÊý¾Ý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugAnalyze(GateWayPara GateWay, uint8_t *rData, uint16_t rLen) +{ + int argc = 0; + char *argv[10], *argp; + + for(int i = 0; i < 10; i++) { + argv[i] = 0; + } + if(rLen == 0) + return; + //for(argv[argc] = strtok(RxBuff, " "); argv[argc] != NULL; argv[++argc] = strtok(NULL, " ")); + argp = strtok((char *)rData, " "); + for(int i = 0; i < 10; i++) { + if(argp != NULL) { + argv[argc++] = argp; + argp = strtok(NULL, " "); + } + else if(argc > 0){ + argc--; + break; + } + } + + argp = strtok(argv[argc], "'\r'"); + if(argp != NULL) { + argv[argc++] = argp; + } + + for(int i = 0; i < DEBUG_CMD_CNT; i++) { + if(strcmp(argv[0], DebugFun[i].DBGCmd) == 0) + DebugFun[i].DBGExec(argc, argv); + } + memset(rData, 0x00, rLen); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdMainOnOff +* ¹¦ÄÜÃèÊö: Ö÷µ÷ÊÔÐÅÏ¢¿ª¹Ø +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdMainOnOff(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: main arg1\r\n"); + DBG_LOG(" brief --> Turn the Main_DBG on or off.\r\n"); + DBG_LOG(" arg1 --> on/off\r\n\r\n"); + return; + } + + if(strcmp(argv[1], "on") == 0) { + MainDBGOnOff(true); + } + else if(strcmp(argv[1], "off") == 0) { + MainDBGOnOff(false); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdCat1OnOff +* ¹¦ÄÜÃèÊö: CAT1µ÷ÊÔÐÅÏ¢¿ª¹Ø +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdCat1OnOff(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: cat1 arg1\r\n"); + DBG_LOG(" brief --> Turn the Cat1_DBG on or off.\r\n"); + DBG_LOG(" arg1 --> on/off\r\n\r\n"); + return; + } + + if(strcmp(argv[1], "on") == 0) { + Cat1DBGOnOff(true); + } + else if(strcmp(argv[1], "off") == 0) { + Cat1DBGOnOff(false); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdCat1OnOff +* ¹¦ÄÜÃèÊö: CAT1µ÷ÊÔÐÅÏ¢¿ª¹Ø +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdRS485Ctrl(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: rs485 arg1 arg2 arg3 arg4\r\n"); + DBG_LOG(" brief --> RS485 control command.\r\n"); + DBG_LOG(" arg1 --> idx: (1, 2) RS485 channel selection.\r\n"); + DBG_LOG(" arg2 --> scmd:(o, c, v, b)Rs485 subcommand.\r\n"); + DBG_LOG(" scmd = o, arg3 = (on, off) RS485 Channel On-OFF.\r\n"); + DBG_LOG(" scmd = c, arg3 = (on, off) Enable the internal communication unit function.\r\n"); + DBG_LOG(" scmd = v, arg3 = (on, off) Set output voltage.\r\n"); + DBG_LOG(" scmd = b, arg3 = (2400~500000) Set baud rate.\r\n\r\n"); + DBG_LOG(" scmd = u, arg4 = (on, off) Set Upgrade symbol.\r\n\r\n"); + return; + } + + int idx = atoi(argv[1]); + if(idx < 1 || idx > 2) { + DBG_LOG("RS485 Cmd Para Error!\r\n"); + return; + } + + char scmd = argv[2][0]; + switch(scmd) { + case 'o': + if(strstr(argv[3], "on") != NULL) { + if(idx == 1) + GateWay->ConfigPara.Rs485Ch1.Enable = true; + else if(idx == 2) + GateWay->ConfigPara.Rs485Ch2.Enable = true; + DBG_LOG("RS485Ch%d Enable!\r\n", idx); + } + else if(strstr(argv[3], "off") != NULL){ + if(idx == 1) + GateWay->ConfigPara.Rs485Ch1.Enable = false; + else if(idx == 2) + GateWay->ConfigPara.Rs485Ch2.Enable = false; + DBG_LOG("RS485Ch%d Disable!\r\n", idx); + } + break; + + case 'c': + if(strstr(argv[3], "on") != NULL) { + if(idx == 1) { + GateWay->ConfigPara.Rs485Ch1.CommUnitEnable = true; + GateWay->ConfigPara.Rs485Ch1.QuerySensorFlag = true; + GateWay->ConfigPara.Rs485Ch1.CUData.Para.SensorN = 0; + memset(GateWay->ConfigPara.Rs485Ch1.CUData.Para.SensorType, 0x00, SENSOR_NUM_MAX * 2); + GateWay->ConfigPara.Rs485Ch1.CUData.Para.CommStatus = true; + RS485Ch1_Config(9600); + GateWay->ConfigPara.Rs485Ch1.BaudRate = 9600; + SComm1Para.SensorCnt = 0; + } + else if(idx == 2) { + GateWay->ConfigPara.Rs485Ch2.CommUnitEnable = true; + GateWay->ConfigPara.Rs485Ch2.QuerySensorFlag = true; + GateWay->ConfigPara.Rs485Ch2.CUData.Para.SensorN = 0; + memset(GateWay->ConfigPara.Rs485Ch2.CUData.Para.SensorType, 0x00, SENSOR_NUM_MAX * 2); + GateWay->ConfigPara.Rs485Ch2.CUData.Para.CommStatus = true; + RS485Ch2_Config(9600); + GateWay->ConfigPara.Rs485Ch2.BaudRate = 9600; + SComm2Para.SensorCnt = 0; + } + DBG_LOG("RS485Ch%d Enable!\r\n", idx); + } + else if(strstr(argv[3], "off") != NULL){ + if(idx == 1) { + GateWay->ConfigPara.Rs485Ch1.CommUnitEnable = false; + GateWay->ConfigPara.Rs485Ch1.CUData.Para.CommStatus = false; + } + else if(idx == 2) { + GateWay->ConfigPara.Rs485Ch2.CommUnitEnable = false; + GateWay->ConfigPara.Rs485Ch2.CUData.Para.CommStatus = false; + } + DBG_LOG("RS485Ch%d Disable!\r\n", idx); + } + break; + + case 'v': + if(strstr(argv[3], "on") != NULL) { + if(idx == 1) { + GateWay->ConfigPara.Rs485Ch1.Power = 1; + RS485_CH1_POW_ON(); + DBG_LOG("RS485Ch%d Power On!\r\n", idx); + } + else if(idx == 2) { + GateWay->ConfigPara.Rs485Ch2.Power = 1; + RS485_CH2_POW_ON(); + DBG_LOG("RS485Ch%d Power On!\r\n", idx); + } + } + else if(strstr(argv[3], "off") != NULL) { + if(idx == 1) { + GateWay->ConfigPara.Rs485Ch1.Power = 0; + RS485_CH1_POW_OFF(); + DBG_LOG("RS485Ch%d Power Off!\r\n", idx); + } + else if(idx == 2) { + GateWay->ConfigPara.Rs485Ch2.Power = 0; + RS485_CH2_POW_OFF(); + DBG_LOG("RS485Ch%d Power Off!\r\n", idx); + } + } + break; + + case 'b': { + int BaudRate = atoi(argv[3]); + if(idx == 1) { + GateWay->ConfigPara.Rs485Ch1.BaudRate = BaudRate; + RS485Ch1_Config(BaudRate); + DBG_LOG("RS485Ch%d Set BaudRate %d!\r\n", idx, GateWay->ConfigPara.Rs485Ch1.BaudRate); + } + else if(idx == 2) { + GateWay->ConfigPara.Rs485Ch2.BaudRate = BaudRate; + RS485Ch2_Config(BaudRate); + DBG_LOG("RS485Ch%d Set BaudRate %d!\r\n", idx, GateWay->ConfigPara.Rs485Ch2.BaudRate); + } + } + break; + + case 'u': + if(strstr(argv[3], "on") != NULL) { + if(idx == 1) { + GateWay->ConfigPara.Rs485Ch1.UpgradeEnable = true; + DBG_LOG("RS485Ch%d Upgrade On!\r\n", idx); + } + else if(idx == 2) { + GateWay->ConfigPara.Rs485Ch2.UpgradeEnable = true; + DBG_LOG("RS485Ch%d Upgrade On!\r\n", idx); + } + } + else if(strstr(argv[3], "off") != NULL){ + if(idx == 1) { + GateWay->ConfigPara.Rs485Ch2.UpgradeEnable = false; + DBG_LOG("RS485Ch%d Upgrade Off!\r\n", idx); + } + else if(idx == 2) { + GateWay->ConfigPara.Rs485Ch2.UpgradeEnable = false; + DBG_LOG("RS485Ch%d Upgrade Off!\r\n", idx); + } + } + break; + + default: + DBG_LOG("RS485 Cmd Para Error!\r\n"); + return; + } + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdDelCommUnit +* ¹¦ÄÜÃèÊö: ɾ³ýÒÑ×¢²áµÄͨѶµ¥Ôª +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdDelCommUnit(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + uint8_t mac[6]; + + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: cudel arg1\r\n"); + DBG_LOG(" brief --> Delete communication unit.\r\n"); + DBG_LOG(" arg1 --> mac: communication unit Mac address.\r\n"); + DBG_LOG(" mac = (XX-XX-XX-XX-XX-XX), Delete specified MAC communication unit.\r\n"); + DBG_LOG(" mac = (all), Delete all communication units.\r\n\r\n"); + return; + } + + if(strcmp(argv[1], "all") == 0) { + for(uint8_t i = 0; i < COMMUNIT_NUM_MAX; i++) + { + GateWay->ConfigPara.CommUnitArray[i].RegFlag = false; + } + DBG_LOG("All devices have been deleted!\r\n"); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + return; + } + + int ret = sscanf(argv[1], "%x-%x-%x-%x-%x-%x", + (int *)&mac[0], (int *)&mac[1], (int *)&mac[2], (int *)&mac[3], (int *)&mac[4], (int *)&mac[5]); + if(ret != 6) { + DBG_LOG("cudel Cmd Para Error!\r\n"); + return; + } + + ret = CheckCommUnitReg(GateWay, mac); + if(ret < 0) { + DBG_LOG("The device is not registered with this gateway!\r\n"); + return; + } + GateWay->ConfigPara.CommUnitArray[ret].RegFlag = false; + //memset(&GateWay->ConfigPara.CommUnitArray[ret], 0x00, sizeof(CommUnitData_t)); + DBG_LOG("Device has been deleted!\r\n"); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdLsCommUnit +* ¹¦ÄÜÃèÊö: ²é¿´Í¨Ñ¶µ¥ÔªÐÅÏ¢ +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdLsCommUnit(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: culs\r\n\ + brief --> Viewing Communication Unit Information.\r\n\r\n"); + return; + } + + if(GateWay->ConfigPara.Rs485Ch1.CommUnitEnable == true) { + DBG_LOG("DevType: 8001\r\n"); + DBG_LOG("DevMac: 01-80-02-00-00-01\r\n"); + DBG_LOG("SensorNum: %d\r\n", GateWay->ConfigPara.Rs485Ch1.CUData.Para.SensorN); + DBG_LOG("SensorType: "); + for(int i = 0; i < GateWay->ConfigPara.Rs485Ch1.CUData.Para.SensorN; i++) { + DBG_LOG("%04X ", GateWay->ConfigPara.Rs485Ch1.CUData.Para.SensorType[i]); + } + DBG_LOG("\r\n\r\n"); + } + + if(GateWay->ConfigPara.Rs485Ch2.CommUnitEnable == true) { + DBG_LOG("DevType: 8002\r\n"); + DBG_LOG("DevMac: 01-80-02-00-00-02\r\n"); + DBG_LOG("SensorNum: %d\r\n", GateWay->ConfigPara.Rs485Ch2.CUData.Para.SensorN); + DBG_LOG("SensorType: "); + for(int i = 0; i < GateWay->ConfigPara.Rs485Ch2.CUData.Para.SensorN; i++) { + DBG_LOG("%04X ", GateWay->ConfigPara.Rs485Ch2.CUData.Para.SensorType[i]); + } + DBG_LOG("\r\n\r\n"); + } + + int CUCnt = 0; + for(int i = 0; i < COMMUNIT_NUM_MAX; i++) { + if(GateWay->ConfigPara.CommUnitArray[i].RegFlag == true) { + CUCnt++; + CommUnitPara_t CU; + memcpy(&CU, &GateWay->ConfigPara.CommUnitArray[i], sizeof(CommUnitPara_t)); + DBG_LOG("DevType: %04X\r\n", GateWay->ConfigPara.CommUnitArray[i].CUType); + DBG_LOG("DevMac: %02X-%02X-%02X-%02X-%02X-%02X\r\n", + GateWay->ConfigPara.CommUnitArray[i].Mac[0][0], + GateWay->ConfigPara.CommUnitArray[i].Mac[0][1], + GateWay->ConfigPara.CommUnitArray[i].Mac[0][2], + GateWay->ConfigPara.CommUnitArray[i].Mac[0][3], + GateWay->ConfigPara.CommUnitArray[i].Mac[0][4], + GateWay->ConfigPara.CommUnitArray[i].Mac[0][5]); + DBG_LOG("SensorNum: %d\r\n", GateWay->ConfigPara.CommUnitArray[i].SensorN); + DBG_LOG("SensorType: "); + for(int j = 0; j < GateWay->ConfigPara.CommUnitArray[i].SensorN; j++) { + DBG_LOG("%04X ", GateWay->ConfigPara.CommUnitArray[i].SensorType[j]); + } + DBG_LOG("\r\n\r\n"); + } + } + if(CUCnt ==0) { + DBG_LOG("No device is registered.\r\n"); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdSetComm +* ¹¦ÄÜÃèÊö: ÉèÖÃÍø¹ØÓë·þÎñͨѶ·½Ê½ +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdSetComm(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: comm arg1\r\n"); + DBG_LOG(" brief --> Set gateway and service communication methods.\r\n"); + DBG_LOG(" arg1 --> para: (cat1, eth),Cat1 or ETH communication.\r\n\r\n"); + return; + } + + if(strcmp(argv[1], "cat1") == 0) { + GateWay->ConfigPara.Comm = CATONE_COMM; + CAT1_ON(); + CatOneReset(); + DBG_LOG("Set the communication method to Cat1.\r\n"); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + } + else if(strcmp(argv[1], "eth") == 0) { + DBG_LOG("Set the communication method to Eth.\r\n"); + if(GateWay->ConfigPara.Comm == CATONE_COMM) { + CAT1_PWR_KEY_CLR(); + CatOneStop(); + rt_thread_delay(3000); + CAT1_PWR_KEY_SET(); + } + + GateWay->ConfigPara.Comm = ETH_COMM; + ETH_ON(); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + } + +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdSetCollTime +* ¹¦ÄÜÃèÊö: ÉèÖÃÊý¾Ý²É¼¯¼ä¸ô +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdSetCollTime(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: sct para\r\n"); + DBG_LOG(" brief --> Set the data collection interval.\r\n"); + DBG_LOG(" arg1 --> para: (10~3600),Set the range from 10 to 3600 seconds.\r\n\r\n"); + return; + } + + int time = atoi(argv[1]); + if(time < 10 && time > 7200) { + DBG_LOG("RS485 Cmd Para Error!\r\n"); + return; + } + GateWay->ConfigPara.CommUnitReadInterval = time; + DBG_LOG("Set the collection time interval to %d seconds.\r\n", time); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdReadHisData +* ¹¦ÄÜÃèÊö: ¶ÁÈ¡ÀúÊ·Êý¾Ý +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdReadHisData(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + int StartIdx; + int ReadNum; + LogHeader_t Header; + uint8_t *Data; + char *AsciiData; + int ret; + int LogIdx; + + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: his arg1 arg2\r\n"); + DBG_LOG(" brief --> Read historical data.\r\n"); + DBG_LOG(" arg1 --> start_num: The starting number of historical data.\r\n"); + DBG_LOG(" start_num = (all),Read all historical data.\r\n"); + DBG_LOG(" arg2 --> read_num: The number of historical data.\r\n\r\n"); + return; + } + + if(strcmp(argv[1], "all") == 0) { + StartIdx = 1; + ReadNum = 0xffffffff; + } + StartIdx = atoi(argv[1]); + ReadNum = atoi(argv[2]); + if(StartIdx <= 0 || ReadNum <= 0) { + DBG_LOG("His Cmd Para Error!\r\n"); + return; + } + + if(StartIdx > 1) { + ret = ReadLog(&Header, &Data, 1); + if(ret == 0) { + DBG_LOG("His Cmd Read Error!\r\n"); + return; + } + rt_free(Data); + if(Header.LogIdx > StartIdx) { + DBG_LOG("His Cmd StartIdx Error, Read First Log, StartIdx = %d!\r\n, Header.LogIdx"); + LogIdx = Header.LogIdx; + } + else { + if(Header.LogIdx == StartIdx) { + Header.LogEndAddr = 0; + } + LogIdx = StartIdx; + } + + } + else { + LogIdx = 1; + } + while(ReadNum > 0) { + ret = ReadLog(&Header, &Data, LogIdx); + if(ret == 0) + return; + + LogIdx++; + ReadNum--; + AsciiData = rt_malloc(ret * 2 + 2); + HexToAscii(Data, AsciiData, ret); + AsciiData[2 * ret] = 0; + DBG_LOG("LogIdx: %d, Data %s\r\n", Header.LogIdx, AsciiData); + rt_free(AsciiData); + rt_free(Data); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdDelHisData +* ¹¦ÄÜÃèÊö: ɾ³ýÀúÊ·Êý¾Ý +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdDelHisData(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: fmt\r\n\ + brief --> Delete historical data.\r\n\r\n"); + return; + } + + SavLogNum(0); + DBG_LOG("The historical data has been deleted.\r\n"); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdGetHisInfo +* ¹¦ÄÜÃèÊö: »ñÈ¡ÀúÊ·Êý¾ÝÐÅÏ¢ +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdGetHisInfo(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + uint32_t LogN; + LogHeader_t Header; + uint8_t *Data; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: hinf\r\n\ + brief --> Obtain historical data information.\r\n\r\n"); + return; + } + + LogN = ReadLogNum(); + if(LogN == 0) { + DBG_LOG("LogN: 0\r\n"); + DBG_LOG("FirstLogIdx: 0\r\n"); + DBG_LOG("FirstLogAddr: %d\r\n", ReadFirstLogStartAddr()); + DBG_LOG("LastLogEndAddr: %d\r\n", ReadLastLogEndAddr()); + return; + } + Header.LogEndAddr = 0; + int ret = ReadLog(&Header, &Data, 0); + if(ret == 0) { + DBG_LOG("Read log information error.\r\n"); + return; + } + rt_free(Data); + DBG_LOG("LogN: %d\r\n", LogN - Header.LogIdx + 1); + DBG_LOG("FirstLogIdx: %d\r\n", Header.LogIdx); + DBG_LOG("FirstLogAddr: %d\r\n", ReadFirstLogStartAddr()); + DBG_LOG("LastLogEndAddr: %d\r\n", ReadLastLogEndAddr()); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdRestoreFactory +* ¹¦ÄÜÃèÊö: »Ö¸´³ö³§ÉèÖà +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdRestoreFactory(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: res\r\n\ + brief --> Restore to factory.\r\n\r\n"); + return; + } + + memset((uint8_t *)&GateWay->ConfigPara, 0x00, sizeof(GWConfigPara_t)); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + DBG_LOG("Restore factory settings, GateWay Restart...\r\n"); + rt_thread_delay(1000); + NVIC_SystemReset(); + while(1); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdRestoreFactory +* ¹¦ÄÜÃèÊö: »Ö¸´³ö³§ÉèÖà +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdReboot(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: reboot\r\n\ + brief --> System Reboot.\r\n\r\n"); + return; + } + + DBG_LOG("GateWay Reboot...\r\n"); + rt_thread_delay(1000); + NVIC_SystemReset(); + while(1); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdSetSensorCollectTime +* ¹¦ÄÜÃèÊö: ÉèÖòɼ¯Ê±¼ä +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdSetCollectTime(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + uint8_t sData[50]; + uint8_t sLen; + + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: sct arg1 arg2\r\n"); + DBG_LOG(" brief --> Set the sensor collection time.\r\n"); + DBG_LOG(" arg1 --> (cu, se)cu: CommUnit, Se: Sensor\r\n"); + DBG_LOG(" arg1 --> (10--7200)Second.\r\n\r\n"); + return; + } + + int IntervalTime = atoi(argv[2]); + + if(IntervalTime < 10 && IntervalTime > 7200) { + DBG_LOG("SCT Cmd Para Error!\r\n"); + return; + } + + if(strcmp(argv[1], "cu") == 0) { + GateWay->ConfigPara.CommUnitReadInterval = IntervalTime; + DBG_LOG(" Set the CommUnit collect time to %d seconds\r\n", IntervalTime); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + } + else if(strcmp(argv[1], "se") == 0) { + FrameHeader Header = (FrameHeader)sData; + Header->Header = 0x7C; + Header->SlvAddr = 00; + Header->Cmd = RS485_SENSOR_CMD_SET_INV_TIME; + //Header->DevType = 0; + Header->PayloadLen = 2; + + sLen = sizeof(FrameHeader_t); + + sData[sLen++] = IntervalTime & 0x00ff; + sData[sLen++] = (IntervalTime >> 8) & 0x00ff; + + uint16_t Check = CRC_Modbus(0xA001, sData, sLen); + + sData[sLen++] = Check & 0xff; + sData[sLen++] = (Check >> 0x08) & 0x00ff; + + if(GateWay->ConfigPara.Rs485Ch1.Enable == true && GateWay->ConfigPara.Rs485Ch1.CommUnitEnable == true) + GateWay->ConfigPara.Rs485Ch1.RS485Send(sData, sLen); + if(GateWay->ConfigPara.Rs485Ch2.Enable == true && GateWay->ConfigPara.Rs485Ch2.CommUnitEnable == true) + GateWay->ConfigPara.Rs485Ch2.RS485Send(sData, sLen); + + DBG_LOG("Set the Sensor collect time to %d seconds\r\n", IntervalTime); + } + else { + DBG_LOG("SCT Cmd Para Error!\r\n"); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdTimeSync +* ¹¦ÄÜÃèÊö: ʱ¼äͬ²½ +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdTimeSync(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + uint32_t year, month, day, hour, min, sec; + uint8_t ret; + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: time\r\n"); + DBG_LOG(" brief --> Time synchronization.\r\n"); + DBG_LOG(" args --> (time YYYY-MM-DD,hh:mm:ss)Set system time.\r\n\r\n"); + return; + } + + ret = sscanf(argv[1], "%d-%d-%d,%d:%d:%d\r\n", &year, &month, &day, &hour, &min, &sec); + if(ret != 6 || year < 2022 || year > 2099 || month > 12 || day > 31 || hour > 60 || min > 60 || sec > 60) { + DBG_LOG("Parameter error.\r\n"); + return; + } + else + TimeSync2(year - 2000, month, day, hour, min, sec); + + DBG_LOG("Time Sync: "); + uint32_t ctime = TimeTs(); + struct tm *stime; + stime = localtime(&ctime); + DBG_LOG("%d/",stime->tm_year + 1900); + DBG_LOG("%d/",stime->tm_mon + 1); + DBG_LOG("%d-",stime->tm_mday); + DBG_LOG("%d:",stime->tm_hour); + DBG_LOG("%d:",stime->tm_min); + DBG_LOG("%d\r\n",stime->tm_sec); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdTimeSync +* ¹¦ÄÜÃèÊö: ²éѯÄÚÖÃͨѶµ¥Ôª´«¸ÐÆ÷ +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +extern SensorCommPara_t SComm1Para; +extern SensorCommPara_t SComm2Para; +void DebugCmdQuerySensor(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: qs\r\n"); + DBG_LOG(" brief --> Query the sensors of the internal CommUnit.\r\n\r\n"); + return; + } + + if(GateWay->ConfigPara.Rs485Ch1.Enable == true && GateWay->ConfigPara.Rs485Ch1.CommUnitEnable == true) { + DBG_LOG("Query Rs485Ch1...\r\n"); + GateWay->ConfigPara.Rs485Ch1.QuerySensorFlag = true; + GateWay->ConfigPara.Rs485Ch1.CUData.Para.SensorN = 0; + memset(GateWay->ConfigPara.Rs485Ch1.CUData.Para.SensorType, 0x00, sizeof(GateWay->ConfigPara.Rs485Ch1.CUData.Para.SensorType)); + SComm1Para.SensorCnt = 0; + } + if(GateWay->ConfigPara.Rs485Ch2.Enable == true && GateWay->ConfigPara.Rs485Ch2.CommUnitEnable == true) { + DBG_LOG("Query Rs485Ch2...\r\n"); + GateWay->ConfigPara.Rs485Ch2.QuerySensorFlag = true; + GateWay->ConfigPara.Rs485Ch2.CUData.Para.SensorN = 0; + memset(GateWay->ConfigPara.Rs485Ch2.CUData.Para.SensorType, 0x00, sizeof(GateWay->ConfigPara.Rs485Ch2.CUData.Para.SensorType)); + SComm2Para.SensorCnt = 0; + } +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdSelDebugChannel +* ¹¦ÄÜÃèÊö: Ñ¡Ôñµ÷ÊÔÐÅÏ¢Êä³öͨµÀ£¬ +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdSelDebugChannel(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: dch\r\n"); + DBG_LOG(" brief --> Debug information output channel selection.\r\n"); + DBG_LOG(" args --> (dbg|ch1|ch2) default: dbg\r\n"); + DBG_LOG(" dbg: On board debugging serial port.\r\n"); + DBG_LOG(" ch1: RS485 channel 1 serial port.\r\n"); + DBG_LOG(" ch2: RS485 channel 2 serial port.\r\n"); + DBG_LOG(" note --> When selecting ch1 or ch2, the channel must enable an disable internal CommUnit function before it can be used.\r\n\r\n"); + return; + } + + if(strcmp(argv[1], "dbg") == 0) { + DBG_LOG("Select Debug Channel is dbg\r\n"); + GateWay->ConfigPara.DebugChannel = DEBUG_CH_DBG; + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + } + else if(strcmp(argv[1], "ch1") == 0) { + if (GateWay->ConfigPara.Rs485Ch1.CommUnitEnable == true){ + DBG_LOG("RS485 channel 1 CommUnit function is not disabled\r\n"); + return; + } + DBG_LOG("Select Debug Channel is RS485_CH1\r\n"); + GateWay->ConfigPara.Rs485Ch1.BaudRate = 500000; + GateWay->ConfigPara.Rs485Ch1.Enable = true; + RS485Ch1_Config(GateWay->ConfigPara.Rs485Ch1.BaudRate); + GateWay->ConfigPara.DebugChannel = DEBUG_CH_RS485_1; + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + } + + else if(strcmp(argv[1], "ch2") == 0) { + if (GateWay->ConfigPara.Rs485Ch2.CommUnitEnable == true){ + DBG_LOG("RS485 channel 2 CommUnit function is not disabled\r\n"); + return; + } + DBG_LOG("Select Debug Channel is RS485_CH2\r\n"); + GateWay->ConfigPara.Rs485Ch2.BaudRate = 500000; + GateWay->ConfigPara.Rs485Ch2.Enable = true; + RS485Ch2_Config(GateWay->ConfigPara.Rs485Ch2.BaudRate); + GateWay->ConfigPara.DebugChannel = DEBUG_CH_RS485_2; + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdSetSvr +* ¹¦ÄÜÃèÊö: ÉèÖ÷þÎñÆ÷µØÖ·¡¢¶Ë¿Ú +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void DebugCmdSetSvr(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + int IP[4]; + int port; + + if(argc < 3) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: arg1 arg2\r\n"); + DBG_LOG(" brief --> Set the server IP address and port for 4G communication.\r\n"); + DBG_LOG(" arg1 --> (xx.xx.xx.xx) ip\r\n"); + DBG_LOG(" arg2 --> port\r\n\r\n"); + return; + } + + char *IpStr = argv[1]; + + int ret = sscanf(IpStr, "%d.%d.%d.%d", &IP[0], &IP[1], &IP[2], &IP[3]); + if(ret != 4) + return; + if(IP[0] > 0xff || IP[1] > 0xff || IP[2] > 0xff || IP[3] > 0xff) + return; + + port = atoi(argv[2]); + if(port > 0xffff) + return; + + GateWay->ConfigPara.SvrAddr[0] = IP[0]; + GateWay->ConfigPara.SvrAddr[1] = IP[1]; + GateWay->ConfigPara.SvrAddr[2] = IP[2]; + GateWay->ConfigPara.SvrAddr[3] = IP[3]; + GateWay->ConfigPara.SvrPort = port; + + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + DBG_LOG("Set server ip and port completed.\r\n"); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdSetMac +* ¹¦ÄÜÃèÊö: ÉèÖÃMACµØÖ· +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void DebugCmdSetMac(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + uint8_t mac[6]; + + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: mac arg1 arg2\r\n"); + DBG_LOG(" brief --> Set the server IP address and port for 4G communication.\r\n"); + DBG_LOG(" arg1 --> psw\r\n"); + DBG_LOG(" arg2 --> mac(xx-xx-xx-xx-xx-xx)\r\n\r\n"); + return; + } + + if(strcmp(argv[1], "gxjt") != 0) { + DBG_LOG("Password Error\r\n"); + return; + } + + int ret = sscanf(argv[2], "%02X-%02X-%02X-%02X-%02X-%02X", + (int *)&mac[0], (int *)&mac[1], (int *)&mac[2], (int *)&mac[3], (int *)&mac[4], (int *)&mac[5]); + if(ret != 6) + return; + + memcpy(GateWay->ConfigPara.GwMac, mac, 6); +// GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0][3] = GateWay->ConfigPara.GwMac[4]; +// GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0][4] = GateWay->ConfigPara.GwMac[5]; +// GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0][3] = GateWay->ConfigPara.GwMac[4]; +// GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0][4] = GateWay->ConfigPara.GwMac[5]; + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + DBG_LOG("Set gateway mac Address completed.\r\n"); +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdGetPara +* ¹¦ÄÜÃèÊö: ²é¿´²ÎÊý +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void DebugCmdGetPara(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(argc > 1) { + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: para\r\n"); + DBG_LOG(" brief --> View gateway parameters.\r\n\r\n"); + return; + } + } + DBG_LOG("\r\n**********************************************************\r\n"); + DBG_LOG("SoftWare V:%d.%d, HardWare V:%d.%d\r\n", SOFTWARE_VERSION / 10, SOFTWARE_VERSION % 10, HARDWARE_VERSION / 10, HARDWARE_VERSION % 10); + DBG_LOG("GateWay MAC: %02X-%02X-%02X-%02X-%02X-%02X\r\n", + GateWay->ConfigPara.GwMac[0], GateWay->ConfigPara.GwMac[1], GateWay->ConfigPara.GwMac[2], GateWay->ConfigPara.GwMac[3], GateWay->ConfigPara.GwMac[4], GateWay->ConfigPara.GwMac[5]); + DBG_LOG("Battery: %d%\r\n", GateWay->Battery); + DBG_LOG("CommInf: %s\r\n", (GateWay->ConfigPara.Comm == CATONE_COMM) ? "Cat1" : "Eth"); + if(GateWay->ConfigPara.Comm == CATONE_COMM) { + char Imei[20], Sim[32]; + CatReadImeiOrSim(Imei, Sim); + DBG_LOG("Cat1 IMEI: %s\r\n", Imei); + DBG_LOG("Cat1 SIM: %s\r\n", Sim); + } + DBG_LOG("CommUnitReadInterval: %d\r\n", GateWay->ConfigPara.CommUnitReadInterval); + DBG_LOG("Svr MAC: %02X-%02X-%02X-%02X-%02X-%02X\r\n", + GateWay->SvrMac[0], GateWay->SvrMac[1], GateWay->SvrMac[2], GateWay->SvrMac[3], GateWay->SvrMac[4], GateWay->SvrMac[5]); + DBG_LOG("Svr IP: %d.%d.%d.%d\r\n", + GateWay->ConfigPara.SvrAddr[0], GateWay->ConfigPara.SvrAddr[1], GateWay->ConfigPara.SvrAddr[2], GateWay->ConfigPara.SvrAddr[3]); + DBG_LOG("Svr Port: %d\r\n", GateWay->ConfigPara.SvrPort); + DBG_LOG("Register Status: %d\r\n", GateWay->SvrRegFlag); + DBG_LOG("RS485Ch1 Mac: %02X-%02X-%02X-%02X-%02X-%02X\r\n", + GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0][0],GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0][1], + GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0][2],GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0][3], + GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0][4],GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0][5]); + DBG_LOG("RS485Ch1: %s, ", (GateWay->ConfigPara.Rs485Ch1.Enable == true) ? "Enable" : "Disable"); + DBG_LOG("InCommUnit %s, ", (GateWay->ConfigPara.Rs485Ch1.CommUnitEnable == true) ? "Enable" : "Disable"); + DBG_LOG("Vout %s, ", (GateWay->ConfigPara.Rs485Ch1.Power == true) ? "Enable" : "Disable"); + DBG_LOG("Baudrate %d\r\n", GateWay->ConfigPara.Rs485Ch1.BaudRate); + DBG_LOG("RS485Ch2 Mac: %02X-%02X-%02X-%02X-%02X-%02X\r\n", + GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0][0],GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0][1], + GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0][2],GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0][3], + GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0][4],GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0][5]); + DBG_LOG("RS485Ch2: %s, ", (GateWay->ConfigPara.Rs485Ch2.Enable == true) ? "Enable" : "Disable"); + DBG_LOG("InCommUnit %s, ", (GateWay->ConfigPara.Rs485Ch2.CommUnitEnable == true) ? "Enable" : "Disable"); + DBG_LOG("Vout %s, ", (GateWay->ConfigPara.Rs485Ch2.Power == true) ? "Enable" : "Disable"); + DBG_LOG("Baudrate %d\r\n", GateWay->ConfigPara.Rs485Ch2.BaudRate); + + DBG_LOG("Lora: ch %d, rp %d, fc %d\r\n", GateWay->ConfigPara.Lora.ucChannel, GateWay->ConfigPara.Lora.RegPreamble, GateWay->ConfigPara.Lora.FreqCent); + + struct tm *stime; + uint32_t dwStamp = TimeTs(); + stime = localtime(&dwStamp); + DBG_LOG("%d/",stime->tm_year + 1900); + DBG_LOG("%d/",stime->tm_mon + 1); + DBG_LOG("%d-",stime->tm_mday); + DBG_LOG("%d:",stime->tm_hour); + DBG_LOG("%d:",stime->tm_min); + DBG_LOG("%d\r\n",stime->tm_sec); + DBG_LOG("**********************************************************\r\n"); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdCali +* ¹¦ÄÜÃèÊö: У׼´«¸ÐÆ÷ +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void DebugCmdCali(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + uint8_t mac[6]; + uint8_t Rs485Cmd[8] = {0x7a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0a, 0x7d}; + uint8_t CommUnitCmd[20]; + CommUnitFrameHeader CUFrame; + + if(argc < 2) + return; + + if(argc > 1) { + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: cali\r\n"); + DBG_LOG(" brief --> Calibrate the sensor.\r\n\r\n"); + DBG_LOG(" arg1 --> mac: communication unit Mac address.\r\n"); + DBG_LOG(" mac = (XX-XX-XX-XX-XX-XX), Calibrate specified MAC communication unit.\r\n"); + DBG_LOG(" mac = (all), Calibrate all communication units.\r\n\r\n"); + return; + } + } + + CUFrame = (CommUnitFrameHeader)CommUnitCmd; + CUFrame->Header = 0x7B; + memcpy(CUFrame->GWMac, GateWay->ConfigPara.GwMac, 6); + memset(CUFrame->DevMac, 0x00, 6); + CUFrame->Cmd = 0x01; + //CUFrame->DevType = 0x8002; + CUFrame->PayloadLen = 0; + uint16_t crc16 = CRC_Modbus(0xA001, CommUnitCmd, sizeof(CommUnitFrameHeader_t)); + CommUnitCmd[sizeof(CommUnitFrameHeader_t)] = crc16 & 0x00ff; + CommUnitCmd[sizeof(CommUnitFrameHeader_t) + 1] = (crc16 >> 8) & 0x00ff; + + if(strcmp(argv[1], "all") == 0) { + if(GateWay->ConfigPara.Rs485Ch1.Enable == true) { + if(GateWay->ConfigPara.Rs485Ch1.CommUnitEnable == true) { + GateWay->ConfigPara.Rs485Ch1.RS485Send(Rs485Cmd, 8); + } + else { + GateWay->ConfigPara.Rs485Ch1.RS485Send(CommUnitCmd, sizeof(CommUnitFrameHeader_t) + 2); + } + } + if(GateWay->ConfigPara.Rs485Ch2.Enable == true) { + if(GateWay->ConfigPara.Rs485Ch2.CommUnitEnable == true) { + GateWay->ConfigPara.Rs485Ch2.RS485Send(Rs485Cmd, 8); + } + else { + GateWay->ConfigPara.Rs485Ch2.RS485Send(CommUnitCmd, sizeof(CommUnitFrameHeader_t) + 2); + } + } + + for(int i = 0; i < COMMUNIT_NUM_MAX; i++)//²ÎÊý±éÀú + { + if(GateWay->ConfigPara.CommUnitArray[i].RegFlag == true) + GateWay->ConfigPara.CommUnitArray[i].CailFlag = true;//У׼ÖÃ룬µÈ´ýÏ´δËMACÖ÷É豸ÉÏ´«Êý¾ÝʱÏ·¢Ð£×¼Ö¸ÁµÍ¹¦ºÄ£© + } + //Sx1276LoRaSendBuffer(CommUnitCmd, sizeof(CommUnitFrameHeader_t) + 2);//µÍ¹¦ºÄģʽϲ»ÓÃÏ·¢ + + DBG_LOG("Calibrate all communication units.\r\n"); + return; + } + + int ret = sscanf(argv[1], "%x-%x-%x-%x-%x-%x", + (int *)&mac[0], (int *)&mac[1], (int *)&mac[2], (int *)&mac[3], (int *)&mac[4], (int *)&mac[5]); + if(ret != 6) { + DBG_LOG("Cali Cmd Para Error!\r\n"); + return; + } + + if(memcmp(mac, GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0], 6) == 0) { + if(!GateWay->ConfigPara.Rs485Ch1.Enable || !GateWay->ConfigPara.Rs485Ch1.CommUnitEnable) { + DBG_LOG("Internal communication unit 1 is turned off!\r\n"); + return; + } + GateWay->ConfigPara.Rs485Ch1.RS485Send(Rs485Cmd, 8); + DBG_LOG("Calibrate internal communication unit 1!\r\n"); + return; + } + + if(memcmp(mac, GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0], 6) == 0) { + if(!GateWay->ConfigPara.Rs485Ch2.Enable || !GateWay->ConfigPara.Rs485Ch2.CommUnitEnable) { + DBG_LOG("Internal communication unit 2 is turned off!\r\n"); + return; + } + GateWay->ConfigPara.Rs485Ch2.RS485Send(Rs485Cmd, 8); + DBG_LOG("Calibrate internal communication unit 2!\r\n"); + } + + ret = CheckCommUnitReg(GateWay, mac); + if(ret < 0) { + DBG_LOG("The CommUnit was not found!\r\n"); + return; + } + + memcpy(CUFrame->DevMac, mac, 6); + crc16 = CRC_Modbus(0xA001, CommUnitCmd, sizeof(CommUnitFrameHeader_t)); + CommUnitCmd[sizeof(CommUnitFrameHeader_t)] = crc16 & 0x00ff; + CommUnitCmd[sizeof(CommUnitFrameHeader_t) + 1] = (crc16 >> 8) & 0x00ff; + + if(mac[2] == 0x01) { //LORAͨѶ + if(GateWay->ConfigPara.CommUnitArray[ret].RegFlag == true) + GateWay->ConfigPara.CommUnitArray[ret].CailFlag = true;//У׼ÖÃ룬µÈ´ýÏ´δËMACÖ÷É豸ÉÏ´«Êý¾ÝʱÏ·¢Ð£×¼Ö¸ÁµÍ¹¦ºÄ£© + DBG_LOG("Wait for the device to respond. Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CUFrame->DevMac[0], CUFrame->DevMac[1], CUFrame->DevMac[2], CUFrame->DevMac[3], CUFrame->DevMac[4], CUFrame->DevMac[5]); + //Sx1276LoRaSendBuffer(CommUnitCmd, sizeof(CommUnitFrameHeader_t) + 2); + } + else if(mac[2] == 0x02) { //RS485ͨѶ + if(GateWay->ConfigPara.Rs485Ch1.Enable == true && !GateWay->ConfigPara.Rs485Ch1.CommUnitEnable) { + GateWay->ConfigPara.Rs485Ch1.RS485Send(Rs485Cmd, sizeof(CommUnitFrameHeader_t) + 2); + DBG_LOG("Calibrate CommUnit: %s!\r\n", argv[1]); + } + else if(GateWay->ConfigPara.Rs485Ch2.Enable == true && !GateWay->ConfigPara.Rs485Ch2.CommUnitEnable) { + GateWay->ConfigPara.Rs485Ch2.RS485Send(Rs485Cmd, sizeof(CommUnitFrameHeader_t) + 2); + DBG_LOG("Calibrate CommUnit: %s!\r\n", argv[1]); + } + else { + DBG_LOG("Communication unit type error.\r\n"); + } + } +} +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugLaserConfig +* ¹¦ÄÜÃèÊö: ¼¤¹â¿ØÖÆ +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void DebugLaserConfig(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + uint8_t mac[6]; + uint8_t Rs485Cmd[8] = {0x7a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0a, 0x7d}; + uint8_t CommUnitCmd[20]; + uint8_t len; + uint16_t crc16; + CommUnitFrameHeader CUFrame; + + if(argc < 2) + return; + + if(argc > 1) { + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: laser\r\n"); + DBG_LOG(" brief --> Control laser cutting.\r\n\r\n"); + DBG_LOG(" arg1 --> mac: communication unit Mac address.\r\n"); + DBG_LOG(" mac = (XX-XX-XX-XX-XX-XX), Control specified MAC communication unit.\r\n"); + DBG_LOG(" arg2 --> state: on/off, Turn on or off the laser.\r\n\r\n"); + return; + } + } + + int ret = sscanf(argv[1], "%x-%x-%x-%x-%x-%x", + (int *)&mac[0], (int *)&mac[1], (int *)&mac[2], (int *)&mac[3], (int *)&mac[4], (int *)&mac[5]); + if(ret != 6) { + DBG_LOG("Control laser Cmd Para Error!\r\n"); + return; + } + + CUFrame = (CommUnitFrameHeader)CommUnitCmd; + CUFrame->Header = 0x7B; + memcpy(CUFrame->GWMac, GateWay->ConfigPara.GwMac, 6); + memcpy(CUFrame->DevMac, mac, 6); + CUFrame->Cmd = COMM_UNIT_CMD_CONT_LASER; + //CUFrame->DevType = 0x8002; + CUFrame->PayloadLen = 1; + + if(strcmp(argv[2], "on") == 0 || strcmp(argv[2], "off") == 0) + { + if(memcmp(mac, GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0], 6) == 0) { + if(!GateWay->ConfigPara.Rs485Ch1.Enable || !GateWay->ConfigPara.Rs485Ch1.CommUnitEnable) { + DBG_LOG("Internal communication unit 1 is turned off!\r\n"); + return; + } + GateWay->ConfigPara.Rs485Ch1.RS485Send(Rs485Cmd, 8); + DBG_LOG("Control internal communication unit 1!\r\n"); + return; + } + + if(memcmp(mac, GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0], 6) == 0) { + if(!GateWay->ConfigPara.Rs485Ch2.Enable || !GateWay->ConfigPara.Rs485Ch2.CommUnitEnable) { + DBG_LOG("Internal communication unit 2 is turned off!\r\n"); + return; + } + GateWay->ConfigPara.Rs485Ch2.RS485Send(Rs485Cmd, 8); + DBG_LOG("Control internal communication unit 2!\r\n"); + } + + ret = CheckCommUnitReg(GateWay, mac); + if(ret < 0) { + DBG_LOG("The CommUnit was not found!\r\n"); + + } + } + else + { + DBG_LOG("Parameter error!\r\n"); + return; + } + + + len = sizeof(CommUnitFrameHeader_t); + bool onoff; + if(strcmp(argv[2], "on") == 0) + { + onoff = true; + CommUnitCmd[len++] = onoff; + } + else if(strcmp(argv[2], "off") == 0) + { + onoff = false; + CommUnitCmd[len++] = onoff; + } + crc16 = CRC_Modbus(0xA001, CommUnitCmd, len); + CommUnitCmd[len++] = crc16 & 0x00ff; + CommUnitCmd[len++] = (crc16 >> 8) & 0x00ff; + + if(mac[2] == 0x01) { //LORAͨѶ£¬µÍ¹¦ºÄģʽ²»ÓÃÖ÷¶¯Ï·¢ + if(GateWay->ConfigPara.CommUnitArray[ret].RegFlag == true) + { + if(onoff == true) + { + GateWay->ConfigPara.CommUnitArray[ret].ContLaser = true;//¿ØÖÆÖÃ룬µÈ´ýÏ´δËMACÖ÷É豸ÉÏ´«Êý¾ÝʱÏ·¢Ð£×¼Ö¸ÁµÍ¹¦ºÄ£© + DBG_LOG("Wait for the device to respond. Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CUFrame->DevMac[0], CUFrame->DevMac[1], CUFrame->DevMac[2], CUFrame->DevMac[3], CUFrame->DevMac[4], CUFrame->DevMac[5]); + GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff = onoff; + } + else if(onoff == false) + { + GateWay->ConfigPara.CommUnitArray[ret].ContLaser = false; + GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff = onoff; + Sx1276LoRaSendBuffer(CommUnitCmd, len);//Ö±½Ó·¢ + } + } + } + else if(mac[2] == 0x02) { //RS485ͨѶ + if(GateWay->ConfigPara.Rs485Ch1.Enable == true && !GateWay->ConfigPara.Rs485Ch1.CommUnitEnable) { + GateWay->ConfigPara.Rs485Ch1.RS485Send(Rs485Cmd, len); + DBG_LOG("Control RS485 laser CommUnit: %s!\r\n", argv[1]); + } + else if(GateWay->ConfigPara.Rs485Ch2.Enable == true && !GateWay->ConfigPara.Rs485Ch2.CommUnitEnable) { + GateWay->ConfigPara.Rs485Ch2.RS485Send(Rs485Cmd, len); + DBG_LOG("Control RS485 laser CommUnit: %s!\r\n", argv[1]); + } + else { + DBG_LOG("Communication unit type error.\r\n"); + } + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdLPConfig +* ¹¦ÄÜÃèÊö: µÍ¹¦ºÄ²ÎÊýÅäÖà +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void DebugCmdLPConfig(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + uint16_t CollectInterval; //²É¼¯Ê±¼ä¼ä¸ô + uint16_t ReportInterval; //Éϱ¨Ê±¼ä¼ä¸ô + uint8_t ERInterval; //½ô¼±Éϱ¨Ê±¼ä¼ä¸ô + uint8_t ERTime; //½ô¼±Éϱ¨Ê±³¤ + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: lpcfg arg1 arg2 arg3 arg4\r\n"); + DBG_LOG(" brief --> Configure low-power device parameters.\r\n"); + DBG_LOG(" arg1 --> Collect interval\r\n"); + DBG_LOG(" arg2 --> Report interval\r\n"); + DBG_LOG(" arg3 --> Emergency reporting interval\r\n"); + DBG_LOG(" arg4 --> Emergency reporting time\r\n\r\n"); + return; + } + + if(argc < 5) + return; + + + CollectInterval = atoi(argv[1]); + if(CollectInterval < 30 || CollectInterval > 7200) { + DBG_LOG("CollectInterval Para Error!\r\n"); + return; + } + + ReportInterval = atoi(argv[2]); + if(ReportInterval < 5 || ReportInterval > 720) { + DBG_LOG("ReportInterval Para Error!\r\n"); + return; + } + + ERInterval = atoi(argv[3]); + if(ERInterval < 1 || ERInterval > 5) { + DBG_LOG("ERInterval Para Error!\r\n"); + return; + } + + ERTime = atoi(argv[4]); + if(ERTime < 10 || ERTime > 120) { + DBG_LOG("ERTime Para Error!\r\n"); + return; + } + + for(int i = 0; i < COMMUNIT_NUM_MAX; i++) { + if(GateWay->ConfigPara.CommUnitArray[i].RegFlag) { + GateWay->ConfigPara.CommUnitArray[i].CollectInterval = CollectInterval; + GateWay->ConfigPara.CommUnitArray[i].ReportInterval = ReportInterval; + GateWay->ConfigPara.CommUnitArray[i].ERInterval = ERInterval; + GateWay->ConfigPara.CommUnitArray[i].ERTime = ERTime; + GateWay->ConfigPara.CommUnitArray[i].ConfigFlag = true; + } + } + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + DBG_LOG("The low-power device is configured.\r\n"); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdLPConfig +* ¹¦ÄÜÃèÊö: µÍ¹¦ºÄ²ÎÊýÅäÖà +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void DebugLoraConfig(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + if(argc < 2) + return; + + if(strcmp(argv[1], "?") == 0) { + DBG_LOG("Debug Cmd: Lora arg1 arg2\r\n"); + DBG_LOG(" brief --> Configure Lora parameters.\r\n"); + DBG_LOG(" arg1 --> ch: Channel--para=(0~16)\r\n"); + DBG_LOG(" pw: Power--para=(0~20)\r\n"); + DBG_LOG(" bw: SignalBw--para=(0~9)\r\n"); + DBG_LOG(" sf: SpreadFactor--para=(6~12)\r\n"); + DBG_LOG(" ec: ErrorCoding--para=(1~4)\r\n"); + DBG_LOG(" rp: RegPreamble--para=(1~32)\r\n"); + DBG_LOG(" o: on/off\r\n"); + DBG_LOG(" arg2 --> para\r\n"); + + return; + } + + if(strcmp(argv[1], "o") == 0) { + if(strcmp(argv[2], "on") == 0) { + GateWay->ConfigPara.Lora.OnOff = true; + LORA_POW_ON(); + DBG_LOG(" Lora Power On!\r\n"); + } + else if(strcmp(argv[2], "off") == 0) { + GateWay->ConfigPara.Lora.OnOff = false; + LORA_POW_OFF(); + DBG_LOG(" Lora Power Off!\r\n"); + } + } + + if(strcmp(argv[1], "ch") == 0) { + int ch = atoi(argv[2]); + if(LoraSetChannel(ch)) { + GateWay->ConfigPara.Lora.ucChannel = ch; + DBG_LOG(" Lora Channel is configured successfully!\r\n"); + } + else { + DBG_LOG("Lora Para Error!\r\n"); + return; + } + } + + if(strcmp(argv[1], "pw") == 0) { + int pow = atoi(argv[2]); + if(LoraSetPower(pow)) { + GateWay->ConfigPara.Lora.ucPower = pow; + DBG_LOG(" Lora Power is configured successfully!\r\n"); + } + else { + DBG_LOG("Lora Para Error!\r\n"); + return; + } + } + + if(strcmp(argv[1], "bw") == 0) { + int bw = atoi(argv[2]); + if(LoraSetSignalBw(bw)) { + GateWay->ConfigPara.Lora.SignalBw = bw; + DBG_LOG(" Lora SignalBw is configured successfully!\r\n"); + } + else { + DBG_LOG("Lora Para Error!\r\n"); + return; + } + } + + if(strcmp(argv[1], "sf") == 0) { + int sf = atoi(argv[2]); + if(LoraSetSpreadFactor(sf)) { + GateWay->ConfigPara.Lora.SpreadFactor = sf; + DBG_LOG(" Lora SpreadFactor is configured successfully!\r\n"); + } + else { + DBG_LOG("Lora Para Error!\r\n"); + return; + } + } + + if(strcmp(argv[1], "ec") == 0) { + int ec = atoi(argv[2]); + if(LoraSetErrorCoding(ec)) { + GateWay->ConfigPara.Lora.ErrorCoding = ec; + DBG_LOG(" Lora ErrorCoding is configured successfully!\r\n"); + } + else { + DBG_LOG("Lora Para Error!\r\n"); + return; + } + } + + if(strcmp(argv[1], "rp") == 0) { + int rp = atoi(argv[2]); + if(LoraSetRegPreamble(rp)) { + GateWay->ConfigPara.Lora.RegPreamble = rp; + DBG_LOG(" Lora RegPreamble is configured successfully!\r\n"); + } + else { + DBG_LOG("Lora Para Error!\r\n"); + return; + } + } + if(GateWay->ConfigPara.Lora.OnOff) + LoraInit(); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + DBG_LOG("Lora reinitializes.\r\n"); +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugCmdHelp +* ¹¦ÄÜÃèÊö: µ÷ÊÔÃüÁî°ïÖúÐÅÏ¢ +* ²Î Êý: argc, ÊäÈë²ÎÊýÊýÁ¿ + argv, ÊäÈë²ÎÊý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugCmdHelp(int argc, char *argv[]) +{ + DBG_LOG("\r\n"); + uint8_t Data[100]; + uint8_t len; + + len = strlen("main ?\r\n"); + memcpy(Data, "main ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("cat1 ?\r\n"); + memcpy(Data, "cat1 ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("rs485 ?\r\n"); + memcpy(Data, "rs485 ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("cudel ?\r\n"); + memcpy(Data, "cudel ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("culs ?\r\n"); + memcpy(Data, "culs ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("comm ?\r\n"); + memcpy(Data, "comm ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("sct ?\r\n"); + memcpy(Data, "sct ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("his ?\r\n"); + memcpy(Data, "his ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("fmt ?\r\n"); + memcpy(Data, "fmt ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("hinf ?\r\n"); + memcpy(Data, "hinf ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + +// len = strlen("res ?\r\n"); +// memcpy(Data, "res ?\r\n", len); +// DebugAnalyze(GateWay, Data, len); + + len = strlen("sct ?\r\n"); + memcpy(Data, "sct ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("time ?\r\n"); + memcpy(Data, "time ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("svr ?\r\n"); + memcpy(Data, "svr ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("qs ?\r\n"); + memcpy(Data, "qs ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("dch ?\r\n"); + memcpy(Data, "dch ?\r\n", len); + DebugAnalyze(GateWay, Data, len); + + len = strlen("para ?\r\n"); + memcpy(Data, "para ?\r\n", len); + DebugAnalyze(GateWay, Data, len); +} + +const DBGFunType DebugFun[DEBUG_CMD_CNT] = { + "help", DebugCmdHelp, + "main", DebugCmdMainOnOff, + "cat1", DebugCmdCat1OnOff, + "rs485", DebugCmdRS485Ctrl, + "cudel", DebugCmdDelCommUnit, + "culs", DebugCmdLsCommUnit, + "comm", DebugCmdSetComm, + "sct", DebugCmdSetCollectTime, +// "his", DebugCmdReadHisData, + "fmt", DebugCmdDelHisData, + "hinf", DebugCmdGetHisInfo, +// "res", DebugCmdRestoreFactory, + "time", DebugCmdTimeSync, + "qs", DebugCmdQuerySensor, + "dch", DebugCmdSelDebugChannel, + "svr", DebugCmdSetSvr, + "mac", DebugCmdSetMac, + "para", DebugCmdGetPara, + "cali", DebugCmdCali, + "laser", DebugLaserConfig, + "lpcfg", DebugCmdLPConfig, + "lora", DebugLoraConfig, + "reboot", DebugCmdReboot, +}; diff --git a/Project/GateWay/source/User/Src/Encryption.c b/Project/GateWay/source/User/Src/Encryption.c new file mode 100644 index 0000000..daca8b5 --- /dev/null +++ b/Project/GateWay/source/User/Src/Encryption.c @@ -0,0 +1,87 @@ +#include "encryption.h" + +//´Ó»ú¼ÓÃܱí +const unsigned char EPT_Table[32][6] = { + {1, 6, 4, 2, 3, 5}, {2, 4, 6, 3, 5, 1}, {3, 5, 6, 2, 1, 4}, {5, 3, 2, 1, 4, 6}, + {4, 2, 3, 1, 5, 6}, {6, 3, 5, 1, 4, 2}, {3, 5, 2, 6, 4, 1}, {2, 5, 4, 3, 1, 6}, + {2, 4, 1, 5, 3, 6}, {4, 6, 1, 3, 2, 5}, {4, 2, 1, 5, 6, 3}, {3, 2, 6, 5, 1, 4}, + {2, 6, 5, 1, 4, 3}, {6, 4, 3, 1, 2, 5}, {1, 6, 3, 2, 4, 5}, {5, 3, 4, 6, 2, 1}, + {5, 3, 1, 2, 6, 4}, {1, 4, 2, 6, 5, 3}, {3, 5, 2, 1, 4, 6}, {6, 1, 4, 2, 3, 5}, + {4, 1, 2, 5, 3, 6}, {4, 2, 6, 3, 5, 1}, {2, 6, 1, 4, 3, 5}, {4, 3, 1, 5, 6, 2}, + {5, 1, 2, 4, 6, 3}, {6, 5, 1, 3, 4, 2}, {2, 1, 6, 3, 5, 4}, {1, 5, 6, 3, 4, 2}, + {3, 6, 5, 4, 2, 1}, {1, 2, 6, 3, 5, 4}, {4, 6, 5, 3, 2, 1}, {5, 3, 4, 2, 6, 1} +}; + +//´Ó»ú½âÃÜ±í£º +const unsigned char DPT_Table[32][5] ={ + {1, 4, 2, 3, 5}, {2, 4, 3, 5, 1}, {3, 5, 2, 1, 4}, {5, 3, 2, 1, 4}, + {4, 2, 3, 1, 5}, {3, 5, 1, 4, 2}, {3, 5, 2, 4, 1}, {2, 5, 4, 3, 1}, + {2, 4, 1, 5, 3}, {4, 1, 3, 2, 5}, {4, 2, 1, 5, 3}, {3, 2, 5, 1, 4}, + {2, 5, 1, 4, 3}, {4, 3, 1, 2, 5}, {1, 3, 2, 4, 5}, {5, 3, 4, 2, 1}, + {5, 3, 1, 2, 4}, {1, 4, 2, 5, 3}, {3, 2, 1, 4, 5}, {1, 4, 5, 2, 3}, + {4, 1, 2, 5, 3}, {4, 2, 3, 5, 1}, {2, 1, 4, 3, 5}, {4, 3, 1, 5, 2}, + {5, 1, 2, 4, 3}, {5, 1, 3, 4, 2}, {2, 1, 3, 5, 4}, {1, 5, 3, 4, 2}, + {3, 5, 4, 2, 1}, {1, 2, 3, 5, 4}, {4, 5, 3, 2, 1}, {5, 3, 4, 2, 1} +}; + +//Êý¾Ýλ¼ÓÃÜ±í£º +const unsigned char EPT_D[32] = { + 0x23, 0x4c, 0x92, 0x38, 0x52, 0xa4, 0x9a, 0x61, + 0x86, 0xc8, 0x70, 0x16, 0x32, 0x58, 0x62, 0x83, + 0xa5, 0x16, 0x1c, 0x49, 0x48, 0xc1, 0x8c, 0x91, + 0xd0, 0x2c, 0x49, 0x42, 0xc1, 0x8c, 0x98, 0xd0 +}; + +/****************************************************************/ +/* ¼ÓÃܺ¯Êý */ +/* */ +/*º¯ÊýÈë¿Ú: *data,δ¼ÓÃܵÄÆÕͨЭÒéÊý¾Ý */ +/* */ +/*º¯Êý³ö¿Ú: *EPT_data£¬Éú³ÉµÄ¼ÓÃÜЭÒé */ +/****************************************************************/ +void Encrypt_Code(unsigned char *data, unsigned char *EPT_data) { + unsigned char Edata[6]; + unsigned char i = 0; + unsigned char check; + unsigned char ept_byte; + + check = (data[0]+data[1]+data[2]+data[3]+data[4]+data[5]) % 0xff; + ept_byte = check % 32; + + for (i = 0; i < 6; i++) { + Edata[i] = ((~(data[i] & EPT_D[ept_byte])) & EPT_D[ept_byte]) | (data[i] & (~EPT_D[ept_byte])); + } + + for (i = 0; i < 6; i++) { + EPT_data[i] = Edata[EPT_Table[ept_byte][i]-1]; + } + + EPT_data[6] = ((~(check & 0xaa)) & 0xaa) | (check & 0x55); +} + +/****************************************************************/ +/* ½âÃܺ¯Êý */ +/* */ +/*º¯ÊýÈë¿Ú£º *EPT_data£¬ÐèÒª½âÃܵļÓÃÜЭÒé */ +/* */ +/*º¯Êý³ö¿Ú£º *DPT_data£¬Éú³ÉµÄÆÕͨЭÒé */ +/****************************************************************/ +void Decrypt_Code(unsigned char *EPT_data,unsigned char *DPT_data) { + unsigned char data[5]; + unsigned char i = 0; + unsigned char check; + unsigned char ept_byte; + + check = ((~(EPT_data[5]&0xaa))&0xaa)|(EPT_data[5]&0x55); + ept_byte = check % 32; + + for(i=0;i<5;i++) { + data[i] = ((~(EPT_data[i]&EPT_D[ept_byte]))&EPT_D[ept_byte])|(EPT_data[i]&(~EPT_D[ept_byte])); + } + for(i=0;i<5;i++) { + DPT_data[DPT_Table[ept_byte][i]-1] = data[i]; + } + DPT_data[5] = check; +} + + diff --git a/Project/GateWay/source/User/Src/LoraTask.c b/Project/GateWay/source/User/Src/LoraTask.c new file mode 100644 index 0000000..9a6ae81 --- /dev/null +++ b/Project/GateWay/source/User/Src/LoraTask.c @@ -0,0 +1,212 @@ +#include "LoraTask.h" +#include "main.h" +#include "CatOneTask.h" +#include "DebugCmd.h" + +#define UC_OFFLINE_TIME_INTERVAL_MAX (2 * 60 * 60)//ÀëÏßÅжÏ×î´óʱ¼ä¼ä¸ô£¬µ¥Î»Ãë + +static rt_sem_t LoraDioIRQ_Sem = RT_NULL; +static rt_thread_t LoraIRQ_Thread = RT_NULL; +static GateWayPara GateWay; + +void LoraSend(uint8_t* pucBuff, uint8_t ucLen) +{ + Sx1276LoRaSendBuffer(pucBuff, ucLen); +} + +//Lora½ÓÊÕÏûϢͳһ·Åµ½ÏûÏ¢¶ÓÁУ¬ÓɽÓÊÕÈÎÎñ´¦Àí +int LoraRevCallBack(GateWayPara GateWay, uint8_t *rData, uint16_t rLen) +{ + uint8_t *sData; + if(rLen > 255) + return -1; + + sData = rt_malloc(rLen + 5); + sData[0] = rLen; + +// Debug_Printf("Lora Rev: "); +// for(int i = 0; i < rLen; i++) { +// Debug_Printf("%02x ", rData[i]); +// } +// Debug_Printf("\r\n"); + + memcpy(&sData[1], rData, rLen); + rt_mq_send(GateWay->LoraRev_MQ, sData, rLen + 1); + rt_free(sData); + return 0; +} + +void LoraIRQ_Thread_Entry(void *parameter) +{ + rt_err_t result; + static uint16_t LoraErrCnt = 0; + + Debug_Printf("LoraRev Thread is running£¡\r\n"); + while(1) { + if(GateWay->ConfigPara.Lora.OnOff == false) { + rt_thread_delay(100); + continue; + } + + result = rt_sem_take(LoraDioIRQ_Sem, 1000); + if(result == RT_EOK) { + IsrSx1276LoRaTxRx(GateWay); + LoraErrCnt = 0; + } + else { + LoraErrCnt++; + if(LoraErrCnt > LORA_ERR_RESET_DLY_MAX) { //15·ÖÖÓÄÚûÓÐÊÕµ½loraÊý¾ÝÖØÆôloraÄ£¿é + LoraErrCnt = 0; + Debug_Printf("Lora Reset£¡\r\n"); + Sx1276LoRaInit(LoraRevCallBack); + } + } + } +} + +static void LoRaSendBuffer(uint8_t* pucBuff, uint16_t ucLen) +{ + if(GateWay->ConfigPara.Lora.OnOff) + Sx1276LoRaSendBuffer(pucBuff, ucLen); +} + +void Lora_Thread_Entry(void *parameter) +{ + rt_err_t result; +#ifndef LORA_LOWPOWER + bool UnitCommSendFlag = false; + uint8_t SendUnitCommIdx = 0; + uint16_t UnitCommReadDelayCnt = 0; +#endif + uint8_t Payload[256]; + uint8_t MegData[9]; + + GateWay = (GateWayPara)parameter; + + while(GateWay->ConfigPara.Lora.OnOff == false) { + rt_thread_delay(100); + } + + LoraDioIRQ_Sem = rt_sem_create("loradioirq_sem", 0, RT_IPC_FLAG_FIFO); + if(LoraDioIRQ_Sem == RT_NULL) { + Debug_Printf("CatOneIRQ Sem Create Failed!\r\n"); + } + + LoraIRQ_Thread = rt_thread_create("LoraIRQ", LoraIRQ_Thread_Entry, NULL, 512, 3, 20); + if (LoraIRQ_Thread != RT_NULL) + rt_thread_startup(LoraIRQ_Thread); + + Sx1276LoRaInit(LoraRevCallBack); + Debug_Printf("Lora Thread is running£¡\r\n"); +#ifdef LORA_LOWPOWER + while(1) { + if(GateWay->ConfigPara.Lora.OnOff == false) { + rt_thread_delay(100); + continue; + } + + result = rt_mq_recv(GateWay->LoraRev_MQ, Payload, 256, 1000); + if(result == RT_EOK) { + int ret = GateWay->CommUnitRevCallBack(GateWay, &Payload[1], Payload[0], LoRaSendBuffer); + if(ret == 0xff) //×¢²áÐÅÏ¢ + continue; + } + else { //ÀëÏßÅÐ¶Ï + for(int i = 0; i < COMMUNIT_NUM_MAX; i++) { + if(GateWay->ConfigPara.CommUnitArray[i].RegFlag == true) { + if(GateWay->ConfigPara.CommUnitArray[i].CommErrCnt < UC_OFFLINE_TIME_INTERVAL_MAX) { + GateWay->ConfigPara.CommUnitArray[i].CommErrCnt++; + } + else if(GateWay->ConfigPara.CommUnitArray[i].CommStatus) { + GateWay->ConfigPara.CommUnitArray[i].CommStatus = 0; + MegData[0] = 7; + MegData[1] = 0; + MegData[2] = COMM_UNIT_CMD_READ; + memcpy(&MegData[3], GateWay->ConfigPara.CommUnitArray[i].Mac[0], 6); + MegData[9] = GateWay->ConfigPara.CommUnitArray[i].CommStatus; + Debug_Printf("The CommUnit is offline.Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + GateWay->ConfigPara.CommUnitArray[i].Mac[0][0], + GateWay->ConfigPara.CommUnitArray[i].Mac[0][1], + GateWay->ConfigPara.CommUnitArray[i].Mac[0][2], + GateWay->ConfigPara.CommUnitArray[i].Mac[0][3], + GateWay->ConfigPara.CommUnitArray[i].Mac[0][4], + GateWay->ConfigPara.CommUnitArray[i].Mac[0][5]); + CatOneEthSendQueue(MegData, 10); //·¢ËÍÀëÏßÏûÏ¢ + } + } + } + } + } +#else + while(1) { + if(UnitCommSendFlag == false && UnitCommReadDelayCnt >= GateWay->ConfigPara.CommUnitReadInterval) { + if(SendUnitCommIdx < COMMUNIT_NUM_MAX) { + if(GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].RegFlag && + GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[2] == 0x01) { + GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].RevNewDataFlag = false; + Debug_Printf("Lora Read CommUnit: %02X:%02X:%02X:%02X:%02X:%02X\r\n", + GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[0], + GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[1], + GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[2], + GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[3], + GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[4], + GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[5]); + CommUnitCmdSend(GateWay, GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[0], COMM_UNIT_CMD_READ, NULL, 0, Sx1276LoRaSendBuffer); + UnitCommSendFlag = true; + } + else { + SendUnitCommIdx++; + continue; + } + } + else { + SendUnitCommIdx = 0; + UnitCommReadDelayCnt = 0; + } + } + + if(UnitCommReadDelayCnt < GateWay->ConfigPara.CommUnitReadInterval) + UnitCommReadDelayCnt++; + + result = rt_mq_recv(GateWay->LoraRev_MQ, Payload, 256, 1000); + if(result == RT_EOK) { + int ret = GateWay->CommUnitRevCallBack(GateWay, &Payload[1], Payload[0], Sx1276LoRaSendBuffer); + if(ret == 0xff) //×¢²áÐÅÏ¢ + continue; + + if(UnitCommSendFlag && GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].RevNewDataFlag) { + UnitCommSendFlag = false; + SendUnitCommIdx++; + } + } + else if(UnitCommSendFlag) { //ÀëÏßÅÐ¶Ï + GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommErrCnt++; + if(GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommErrCnt == 10) { + GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommErrCnt = 0; + if(GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommStatus) { + GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommStatus = 0; + MegData[0] = 7; + MegData[1] = 0; + MegData[2] = COMM_UNIT_CMD_READ; + memcpy(&MegData[3], GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[0], 6); + MegData[9] = GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommStatus; + CatOneEthSendQueue(MegData, 10); //·¢ËÍÀëÏßÏûÏ¢ + } + } + UnitCommSendFlag = false; + SendUnitCommIdx++; + } + } +#endif +} + + +void LoraTxRxIrqCallback(void) +{ + rt_sem_release(LoraDioIRQ_Sem); +} + +void LoraInit(void) +{ + Sx1276LoRaInit(LoraRevCallBack); +} diff --git a/Project/GateWay/source/User/Src/Public.c b/Project/GateWay/source/User/Src/Public.c new file mode 100644 index 0000000..4642dcd --- /dev/null +++ b/Project/GateWay/source/User/Src/Public.c @@ -0,0 +1,1165 @@ +#include "main.h" +#include "Public.h" +#include "RS485Task.h" +#include "LoraTask.h" +#include "spiflash.h" +#include "CatOneTask.h" +#include + +//´«¸ÐÆ÷¶ÔÓ¦µÄÊý¾Ý³¤¶È +const uint8_t SensorTypeDataLen[] = { + 0, //0x0000-±£Áô + 30, //0x0001-Ó¦Á¦³¡¼ì²âµ¥Ôª + 12, //0x0002-Éø͸ѹ¼ì²âµ¥Ôª + 14, //0x0003-µ¯ÐÔ²¨µ¼¼ì²âµ¥Ôª + 10, //0x0004-½éµçÖÊÆÕ¼ì²âµ¥Ôª + 6, //0x0005-΢Õñ¶¯ + 6, //0x0006-ÈýάÁ¬Ðø±äÐμì²âµ¥Ôª + 3, //0x0007-ͨѶµ¥Ôª + 18, //0x0008-ÈýάӦÁ¦¼ì²âµ¥Ôª + 9, //0x0009-¼¤¹âʾ×Ù(Ö÷É豸) + 12, //0x000A-ˮλ¼Æ + 0, //0x000B-±£Áô + 0, //0x000C-±£Áô + 14, //0x000D-¶þάӦÁ¦³¡¼ì²âµ¥Ôª + 9, //0x000E-ÁÑ·ì¼ì²âµ¥Ôª + 8, //0x0010-×Ë̬¼ì²âµ¥Ôª + 4, //0x0011-¼¤¹âλÒƼì²âµ¥Ôª +}; + +/***************************************************************************************** +* º¯ÊýÃû³Æ: CRC_Modbus +* ¹¦ÄÜÃèÊö: CRC16¼ÆË㺯Êý +* ²Î Êý: wBase, ¶àÏîʽ + Para£¬Ð£ÑéÊý¾ÝÈë¿Ú + Data, УÑéÊý¾Ý³¤¶ÈÈë¿Ú +* ·µ »Ø Öµ: crc16УÑéÖµ +*****************************************************************************************/ +uint16_t CRC_Modbus(uint16_t wBase, __IO uint8_t *para, uint16_t length) +{ + uint16_t crc = 0xffff; + + uint16_t index,i; + + for(index = 0 ; index < length;index++) { + crc ^= para[index]; + for(i = 0; i < 8; i++) { + if(crc & 1) { + crc >>= 1; + crc ^= wBase; + } + else + crc >>= 1; + } + } + return crc; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: HexToAscii +* ¹¦ÄÜÃèÊö: HEXת»»ÎªASCII×Ö·û´®º¯Êý +* ²Î Êý: HexData, 16½øÖÆÊý¾ÝÈë¿Ú + ASCData£¬×ª»»ºóµÄASCIIÊý¾Ý + sLen, ÐèҪתµÄ16½øÖÆÊý¾Ý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void HexToAscii(uint8_t *HexData, char *ASCData, uint8_t sLen) +{ + uint8_t temp; + + for(int i = 0; i < sLen; i++) { + temp = (HexData[i] >> 4) & 0x0f; + if(temp < 10) + temp += '0'; + else + temp = (temp - 10) + 'A'; + + ASCData[i * 2] = temp; + + temp = HexData[i] & 0x0f; + if(temp < 10) + temp += '0'; + else + temp = (temp - 10) + 'A'; + + ASCData[i * 2 + 1] = temp; + } + ASCData[sLen * 2] = 0; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: AsciiToHex +* ¹¦ÄÜÃèÊö: AscII×Ö·û´®×ª»»Îª16½øÖÆÊý×é +* ²Î Êý: ASCData, AscII×Ö·û´®Èë¿Ú + HexData£¬×ª»»ºóµÄÊý¾Ý + sLen, ÐèҪתµÄ×Ö·û´®³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +uint8_t AsciiToHex(char *ASCData, uint8_t *HexData, uint8_t sLen) +{ + char chr; + uint8_t HexLen = 0; + + if(sLen % 2 == 1) + return 0; + + for(int i = 0; i < sLen; i++) { + chr = ASCData[i]; + if(chr >= '0' && chr <= '9') { + HexData[HexLen] |= chr - '0'; + } + else if(chr >= 'A' && chr <= 'F') { + HexData[HexLen] |= chr - 'A' + 0x0A; + } + else if(chr >= 'a' && chr <= 'f') { + HexData[HexLen] |= chr - 'a' + 0x0A; + } + if(i % 2 == 0) { + HexData[HexLen] <<= 4; + } + else { + HexLen++; + } + } + return HexLen; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: ReadHistoryData +* ¹¦ÄÜÃèÊö: ¶ÁÈ¡ÀúÊ·Êý¾Ý +* ²Î Êý: rData,ÊäÈëÊý¾Ý + rLen, ÊäÈëÊý¾Ý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +int ReadHistoryData(LogHeader LogH, uint8_t **Data, int Idx) +{ + return ReadLog(LogH, Data, Idx); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: NetCommOrgData +* ¹¦ÄÜÃèÊö: Éϱ¨Êý¾Ý×éÖ¯ +* ²Î Êý: MegData, ÏûÏ¢¶ÓÁÐÊý¾Ý + OutData, Êä³öÊý¾Ý³ö¿Ú +* ·µ »Ø Öµ: Êý¾Ý³¤¶È +*****************************************************************************************/ +int NetCommOrgData(GateWayPara GateWay, uint8_t *MegData, uint8_t *OutData) +{ + uint8_t Cmd, *Meg; + uint16_t check; + uint16_t Len; + uint16_t PayloadLen; + + PayloadLen = MegData[0] | (MegData[1] << 8); + Cmd = MegData[2]; + Meg = &MegData[3]; + + NetCommFrameHeader NCHeader = (NetCommFrameHeader)OutData; + + NCHeader->Header = 0x7A; + memcpy(NCHeader->GWMac, GateWay->ConfigPara.GwMac, 6); + //memcpy(NCHeader->SvrMac, GateWay->SvrMac, 6); + NCHeader->Cmd = Cmd; + NCHeader->BatLevel = GateWay->Battery; + NCHeader->Timestamp = TimeTs(); + + NCHeader->PacketNum = 1; + NCHeader->PacketIdx = 1; + NCHeader->PayloadLen = PayloadLen; + + Len = sizeof(NetCommFrameHeader_t); + + memcpy(&OutData[Len], Meg, NCHeader->PayloadLen); + Len += NCHeader->PayloadLen; + + check = CRC_Modbus(0xA001, OutData, Len); + OutData[Len++] = check & 0x00ff; + OutData[Len++] = (check >> 8) & 0x00ff; + + return Len; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: CheckCommUnitReg +* ¹¦ÄÜÃèÊö: ¼ì²éÉ豸ÊÇ·ñ×¢²á +* ²Î Êý: GateWay,Íø¹Ø¾ä±ú + CommUnitMac, ´ý¼ì²éµÄÉ豸MAC +* ·µ »Ø Öµ: ÒÑ×¢²á·µ»Øtrue,ûע²á·µ»Øfalse +*****************************************************************************************/ +int CheckCommUnitReg(GateWayPara GateWay, uint8_t *CommUnitMac) +{ + for(int i = 0; i < COMMUNIT_NUM_MAX; i++) { + if(memcmp(GateWay->ConfigPara.CommUnitArray[i].Mac[0], CommUnitMac, 6) == 0) { + if(GateWay->ConfigPara.CommUnitArray[i].RegFlag == true) + return i; + } + } + return -1; +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: CommUnitSendCmd +* ¹¦ÄÜÃèÊö: Íø¹ØÏ·¢Í¨Ñ¶µ¥ÔªÖ¸ÁÊý +* ²Î Êý: GateWay, Íø¹Ø¾ä±ú + CommUnitMac£¬Í¨Ñ¶µ¥ÔªMACµØÖ· + Cmd, ÃüÁî×Ö + Payload, Ï·¢Êý¾Ý + PayloadLen£¬ Ï·¢Êý¾Ý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void CommUnitCmdSend(GateWayPara GateWay, uint8_t *CommUnitMac, CommUnitCmd_m Cmd, uint8_t *Payload, uint16_t PayloadLen, SendData Send) +{ + uint8_t SendBuff[50]; + uint8_t SendLen; + + if(PayloadLen > 10) + return; + CommUnitFrameHeader CUHeader = (CommUnitFrameHeader)SendBuff; + + CUHeader->Header = 0x7B; + memcpy(CUHeader->GWMac, GateWay->ConfigPara.GwMac, 6); + if(CommUnitMac == NULL) { + memset(CUHeader->DevMac, 0x00, 6); + //CUHeader->DevType = 0x0000; + } + else { + int ret = CheckCommUnitReg(GateWay, CommUnitMac); + if(ret < 0) + return; + memcpy(CUHeader->DevMac, CommUnitMac, 6); + //CUHeader->DevType = GateWay->ConfigPara.CommUnitArray[ret].CUType; + } + CUHeader->Cmd = Cmd; + CUHeader->PayloadLen = PayloadLen; + SendLen = sizeof(CommUnitFrameHeader_t); + if(PayloadLen > 0) { + memcpy(&SendBuff[SendLen], Payload, PayloadLen); + SendLen += PayloadLen; + } + uint16_t crc16 = CRC_Modbus(0xA001, SendBuff, SendLen); + SendBuff[SendLen++] = crc16 & 0x00ff; + SendBuff[SendLen++] = (crc16 >> 8) & 0x00ff; + + if(Send != NULL) { + Send(SendBuff, SendLen); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: CommUintOrgData +* ¹¦ÄÜÃèÊö: ÉÏ´«´«¸ÐÆ÷Êý¾Ýº¯Êý +* ²Î Êý: GWMac,Íø¹ØmacµØÖ· + CUPara, ͨѶµ¥Ôª²ÎÊý + sData, Êý¾ÝÈë¿Ú +* ·µ »Ø Öµ: Êý¾Ý³¤¶È +*****************************************************************************************/ +int CommUintOrgData(GateWayPara GateWay, CommUnitPara CUPara, CommUnitData CUData, uint8_t *sData) +{ + uint16_t Len = 0; + uint8_t SensorN = 0; + + Len = 3; + memcpy(&sData[3], CUPara->Mac[0], 6); + Len += 6; + sData[Len++] = CUPara->CommStatus; +// sData[Len++] = CUPara->BatLevel; +// sData[Len++] = CUPara->SensorN; + +// for(int i = 0; i < SENSOR_NUM_MAX; i++) { +// if(CUPara->SensorType[i] != 0x0000) { +// sData[Len++] = CUPara->SensorType[i] & 0x00ff; +// sData[Len++] = (CUPara->SensorType[i] >> 8) & 0x00ff; +// SensorN++; +// } +// if(SensorN >= CUPara->SensorN) +// break; +// } +// SensorN = 0; + for(int i = 0; i < SENSOR_NUM_MAX; i++) { + if(CUPara->SensorType[i] != 0x0000) { + switch(CUPara->SensorType[i]) { + case FORCE_6D: + memcpy(&sData[Len], CUData->Data[i], sizeof(Force6D_T)); + Len += sizeof(Force6D_T); + break; + case OSMOTIC_PRESSURE: + break; + case ELASTIC_WAVEGUIDE: + break; + case DIELECTRIC_MASS: + break; + case VIBRATE_SENSOR: + break; + case CONT_DEFOR_3D: + break; + case COMM_UNIT: + break; + case FORCE_3D: + break; + case LASER_TRACING: + memcpy(&sData[Len], CUData->Data[i], sizeof(LaserTracingType_t)); + Len += sizeof(LaserTracingType_t); + break; + case WATER_LEVEL: + break; + case _0x000B: + break; + case _0x000C: + break; + case MULTI_PARAMETER_FUSION: + break; + case CRACK_DETECTION: + break; + case _0x000F: + break; + case ATTITUDE_MONITOR: + break; + case LASER_DISPLACE: + break; + case REBAR_STRESS: + break; + case ANCHOR_ROD_STRESS: + break; + case SURFACE_STRESS: + break; + case PRESSURE: + break; + case MICROWAVE_DISPLACE: + break; + } + SensorN++; + } + if(SensorN >= CUPara->SensorN) + break; + } + sData[0] = (Len - 3) & 0x00ff; + sData[1] = ((Len - 3) >> 8) & 0x00ff; + sData[2] = NET_COMM_CMD_UPDATE; + return Len; +} + +void DebugDisplaySensorData(int SensorIdx, uint16_t SensorType, uint8_t *SensorData) +{ + switch(SensorType) { + case SENSOR_TYPE_NULL: { + break; + } + case FORCE_6D: { + Force6D_T Sensor; + memcpy((uint8_t *)&Sensor, SensorData, sizeof(Force6D_T)); + MAIN_DBG_LOG("Sensor%d Type %04x: Accx=%d, Accy=%d, Accz=%d, Strain1=%d, Strain2=%d, Strain3=%d, Strain4=%d, Strain5=%d, Strain6=%d\r\n", + SensorIdx, SensorType, Sensor.AccX, Sensor.AccY, Sensor.AccZ, + Sensor.Strain1, Sensor.Strain2, Sensor.Strain3, Sensor.Strain4, Sensor.Strain5, Sensor.Strain6); + break; + } + case OSMOTIC_PRESSURE: { + break; + } + case ELASTIC_WAVEGUIDE:{ + break; + } + case DIELECTRIC_MASS:{ + break; + } + case VIBRATE_SENSOR:{ + break; + } + case CONT_DEFOR_3D:{ + break;} + case COMM_UNIT:{ + break; + } + case FORCE_3D: { + break; + } + case LASER_TRACING: { + LaserTracingType_t Sensor; + memcpy((uint8_t *)&Sensor, SensorData, sizeof(LaserTracingType_t)); + MAIN_DBG_LOG("Sensor%d Type %04x: PitchAngle=%04d, RollAngle=%04d, YawAngle=%04d\r\n", + SensorIdx, SensorType, Sensor.PitchAngle, Sensor.RollAngle, Sensor.YawAngle); + break; + } + case WATER_LEVEL: { + break; + } + case _0x000B: { + break; + } + case _0x000C: { + break; + } + case MULTI_PARAMETER_FUSION: { + break; + } + case CRACK_DETECTION: { + break; + } + case _0x000F: { + break; + } + case ATTITUDE_MONITOR: { + break; + } + case LASER_DISPLACE: { + break; + } + case REBAR_STRESS: { + break; + } + case ANCHOR_ROD_STRESS: { + break; + } + case SURFACE_STRESS: { + break; + } + case PRESSURE: { + break; + } + case MICROWAVE_DISPLACE: { + break; + } + default: + break; + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: CommUnitAnalyze +* ¹¦ÄÜÃèÊö: ͨѶµ¥ÔªÊý¾Ý½âÎö£¬Ê¹ÓÃÓÚLORAºÍRS485ͨѶ +* ²Î Êý: rData,ÊäÈëÊý¾Ý + rLen, ÊäÈëÊý¾Ý³¤¶È +* ·µ »Ø Öµ: ·µ»Ø½ÓÊÕµ½µÄͨѶµ¥ÔªÐòºÅ£¬´íÎó·µ»Ø-1 +*****************************************************************************************/ +int CommUnitAnalyze(GateWayPara GateWay, uint8_t *rData, uint16_t rLen, SendData Response) +{ + uint16_t check, crc16; + int CommUnitIdx; + uint16_t PayLoadLen; + uint8_t *PayLoad; + uint8_t *MegData; + uint16_t len; + //uint8_t *Data; + uint16_t CommUintLen; + + CommUnitFrameHeader CUHeader = (CommUnitFrameHeader)rData; + PayLoad = &rData[sizeof(CommUnitFrameHeader_t)]; + + if(CUHeader->Header != 0x7B) + return -1; + + check = CRC_Modbus(0xA001, rData, rLen - 2); + crc16 = rData[rLen - 2] | (rData[rLen - 1] << 8); + + if(check != crc16) + return -1; + + if((CUHeader->Cmd != COMM_UNIT_CMD_REG) && (memcmp(GateWay->ConfigPara.GwMac, CUHeader->GWMac, 6) != 0)) + return -1; + + CommUnitIdx = CheckCommUnitReg(GateWay, CUHeader->DevMac); + if(CommUnitIdx < 0) { + if(CUHeader->Cmd != COMM_UNIT_CMD_REG) + return -1; + } + + switch(CUHeader->Cmd) { + case COMM_UNIT_CMD_REG:{ + if(PayLoad[0] > SENSOR_NUM_MAX) { + return -1; + } + +// if(CUHeader->PayloadLen < 2) +// return -1; + + if(CommUnitIdx >= 0) { //É豸´æÔÚ + MAIN_DBG_LOG("\r\nCommUnit has already been registered! Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CUHeader->DevMac[0], CUHeader->DevMac[1], CUHeader->DevMac[2], CUHeader->DevMac[3], CUHeader->DevMac[4], CUHeader->DevMac[5]); + uint8_t ret = 1; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CommErrCnt = 0; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag = true; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CailFlag = false; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].TimeSyncFlag = false; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ContLaser = false; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].LaserOnOff = false; + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_REG, &ret, 1, Response); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + return CommUnitIdx; + } + for(int i = 0; i < COMMUNIT_NUM_MAX; i++) { + if(GateWay->ConfigPara.CommUnitArray[i].RegFlag == false) { + CommUnitIdx = i; + GateWay->ConfigPara.CommUnitArray[i].RegFlag = true; + GateWay->ConfigPara.CommUnitArray[i].CommStatus = true; + GateWay->ConfigPara.CommUnitArray[i].CailFlag = false; + GateWay->ConfigPara.CommUnitArray[i].TimeSyncFlag = false; + GateWay->ConfigPara.CommUnitArray[i].ContLaser = false; + GateWay->ConfigPara.CommUnitArray[i].LaserOnOff = false; + + GateWay->ConfigPara.CommUnitArray[i].CUType = DEV_TYPE_EXT_COMMUNIT;//ÍâÖÃͨѶµ¥Ôª + MAIN_DBG_LOG("\r\nCommUnit register succeed!\r\n"); + + memcpy(GateWay->ConfigPara.CommUnitArray[i].MasterMac, &PayLoad[1], 6); + MAIN_DBG_LOG("Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n",CUHeader->DevMac[0], CUHeader->DevMac[1], CUHeader->DevMac[2], CUHeader->DevMac[3], CUHeader->DevMac[4], CUHeader->DevMac[5]); + + GateWay->ConfigPara.CommUnitArray[i].SensorN = PayLoad[0]; + MAIN_DBG_LOG("SensorN: %d ", GateWay->ConfigPara.CommUnitArray[i].SensorN); + //memcpy(GateWay->ConfigPara.CommUnitArray[i].SensorType, &PayLoad[1], CUHeader->PayloadLen-1); + MAIN_DBG_LOG("Sensor Type: "); + for(int j = 0; j < GateWay->ConfigPara.CommUnitArray[i].SensorN; j++) { + memcpy(GateWay->ConfigPara.CommUnitArray[i].Mac[j], &PayLoad[(j*6)+1], 6); + GateWay->ConfigPara.CommUnitArray[i].SensorType[j] = PayLoad[(j*6)+1] | (PayLoad[(j*6)+2] << 8); + MAIN_DBG_LOG("0x%04x, ", GateWay->ConfigPara.CommUnitArray[i].SensorType[j]); + } + MAIN_DBG_LOG("\r\n"); + GateWay->ConfigPara.CommUnitArray[i].CommErrCnt = 0; + GateWay->ConfigPara.CommUnitArray[i].ConfigFlag = true; + GateWay->ConfigPara.CommUnitArray[i].CollectInterval = LW_DEV_COLLECT_INTERVAL_MAX; + GateWay->ConfigPara.CommUnitArray[i].ReportInterval = LW_DEV_REPORT_INTERVAL_MAX; + GateWay->ConfigPara.CommUnitArray[i].ERInterval = LW_DEV_ER_INTERVAL_MAX; + GateWay->ConfigPara.CommUnitArray[i].ERTime = LW_DEV_ER_TIME_MAX; + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + uint8_t ret = 1; + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_REG, &ret, 1, Response); + + if(GateWay->SvrRegFlag) { //Íø¹ØÒÑ×¢²á£¬Ïò·þÎñ·¢ËÍÐÂÉ豸Ìí¼ÓÖ¸Áî + PayLoadLen = (GateWay->ConfigPara.CommUnitArray[i].SensorN * 6) + 2; + MegData = rt_malloc(PayLoadLen + 3); + MegData[0] = PayLoadLen & 0x00ff;; + MegData[1] = (PayLoadLen >> 8) & 0x00ff; + MegData[2] = NET_COMM_CMD_ADD_UNIT; + for(uint8_t i = 0; i < GateWay->ConfigPara.CommUnitArray[i].SensorN; i++) + { + memcpy(&MegData[3], GateWay->ConfigPara.CommUnitArray[i].Mac[i], 6); + } + CatOneEthSendQueue(MegData, PayLoadLen+3); + rt_free(MegData); + } + return 0xff; + } + } + MAIN_DBG_LOG("\r\nCommUnit register failed! Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CUHeader->DevMac[0], CUHeader->DevMac[1], CUHeader->DevMac[2], CUHeader->DevMac[3], CUHeader->DevMac[4], CUHeader->DevMac[5]); + break;} + + case COMM_UNIT_CMD_CAIL:{ + if(PayLoad[0] == 0) { + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CailFlag = true; + MAIN_DBG_LOG("CommUnit calibrate failed! Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CUHeader->DevMac[0], CUHeader->DevMac[1], CUHeader->DevMac[2], CUHeader->DevMac[3], CUHeader->DevMac[4], CUHeader->DevMac[5]); + } + else if(PayLoad[0] == 1){ + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CailFlag = false; + MAIN_DBG_LOG("CommUnit calibrate succeed! Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CUHeader->DevMac[0], CUHeader->DevMac[1], CUHeader->DevMac[2], CUHeader->DevMac[3], CUHeader->DevMac[4], CUHeader->DevMac[5]); + } + uint32_t ctime = TimeTs(); + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag == true) { + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag = false; + LPDevConfigPara_t Config; + Config.CollectInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CollectInterval; + Config.ReportInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ReportInterval; + Config.ERInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERInterval; + Config.ERTime = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERTime; + Config.TimeStamp = ctime; + MAIN_DBG_LOG("CI:%d, RI:%d, EI:%d, ET:%d\r\n", Config.CollectInterval, Config.ReportInterval, Config.ERInterval, Config.ERTime); + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_READ, (uint8_t *)&Config, sizeof(LPDevConfigPara_t), Response); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ContLaser == true) + { + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].LaserOnOff == true) + {//´ò¿ª¼¤¹â + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_CONT_LASER, (uint8_t *)&GateWay->ConfigPara.CommUnitArray[CommUnitIdx].LaserOnOff, 1, Response); + } + MAIN_DBG_LOG("Issue laser control commands.\r\n"); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CailFlag == true) + { + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_CAIL, 0, 0, Response); + MAIN_DBG_LOG("Issue calibration instructions.\r\n"); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].TimeSyncFlag == true) + { + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_TIME_SYNC, (uint8_t *)&ctime, 4, Response); + MAIN_DBG_LOG("Issue a time synchronization command.\r\n"); + } + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + break;} + + case COMM_UNIT_CMD_READ:{ +// if(PayLoad[1] > SENSOR_NUM_MAX) { +// return CommUnitIdx; +// } + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CommStatus = true; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].RevNewDataFlag = true; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CommErrCnt = 0; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].BatLevel = PayLoad[0]; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].RSSI = PayLoad[1]; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].Nsr = PayLoad[2]; +// memset(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].SensorType, 0x00, sizeof(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].SensorType)); +// memcpy(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].SensorType, &PayLoad[2], GateWay->ConfigPara.CommUnitArray[CommUnitIdx].SensorN * 2); +// len = 0; +// Data = &PayLoad[GateWay->ConfigPara.CommUnitArray[CommUnitIdx].SensorN * 2 + 2]; +// int16_t Rssi; +// int8_t Snr; +// SX1276LoCalcRssiSnr(&Rssi, &Snr); + MAIN_DBG_LOG("\r\nCUMac:%02X-%02X-%02X-%02X-%02X-%02X, Bat: %d%, SN: %d£¬Rssi:%d, Snr:%d\r\n", + CUHeader->DevMac[0], CUHeader->DevMac[1], CUHeader->DevMac[2], CUHeader->DevMac[3], CUHeader->DevMac[4], CUHeader->DevMac[5], + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].BatLevel, + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].SensorN, + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].RSSI, + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].Nsr); + for(int i = 0; i < GateWay->ConfigPara.CommUnitArray[CommUnitIdx].SensorN; i++) { + memcpy(GateWay->CUDataArray[CommUnitIdx].Data[i], &PayLoad[0], SensorTypeDataLen[GateWay->ConfigPara.CommUnitArray[CommUnitIdx].SensorType[i]]); + //ÏÔʾ´«¸ÐÆ÷Êý¾Ý + DebugDisplaySensorData(i, GateWay->ConfigPara.CommUnitArray[CommUnitIdx].SensorType[i], GateWay->CUDataArray[CommUnitIdx].Data[i]); + len += SensorTypeDataLen[GateWay->ConfigPara.CommUnitArray[CommUnitIdx].SensorType[i]]; + } +#ifdef LORA_LOWPOWER + uint32_t ctime = TimeTs(); + LPDevConfigPara_t Config; + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CollectInterval > 7200 || GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CollectInterval < 30) + { + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CollectInterval = 300; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag = true; + } + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ReportInterval > 720 || GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ReportInterval < 5) + { + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ReportInterval = 20; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag = true; + } + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERInterval > 5 || GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERInterval < 1) + { + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERInterval = 2; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag = true; + } + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERTime > 120 || GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERTime < 10) + { + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERTime = 20; + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag = true; + } + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag == true) { + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag = false; + Config.CollectInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CollectInterval; + Config.ReportInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ReportInterval; + Config.ERInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERInterval; + Config.ERTime = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERTime; + Config.TimeStamp = ctime; + MAIN_DBG_LOG("CI:%d, RI:%d, EI:%d, ET:%d\r\n", Config.CollectInterval, Config.ReportInterval, Config.ERInterval, Config.ERTime); + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_READ, (uint8_t *)&Config, sizeof(LPDevConfigPara_t), Response); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ContLaser == true) + { + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].LaserOnOff == true) + {//´ò¿ª¼¤¹â + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_CONT_LASER, (uint8_t *)&GateWay->ConfigPara.CommUnitArray[CommUnitIdx].LaserOnOff, 1, Response); + } + MAIN_DBG_LOG("Issue laser control commands.\r\n"); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CailFlag == true) + { + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_CAIL, 0, 0, Response); + MAIN_DBG_LOG("Issue calibration instructions.\r\n"); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].TimeSyncFlag == true) + { + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_TIME_SYNC, (uint8_t *)&ctime, 4, Response); + MAIN_DBG_LOG("Issue a time synchronization command.\r\n"); + } + else + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_READ, (uint8_t *)&ctime, 4, Response); +#endif + MegData = rt_malloc(512); + CommUintLen = CommUintOrgData(GateWay, &GateWay->ConfigPara.CommUnitArray[CommUnitIdx], &GateWay->CUDataArray[CommUnitIdx], MegData); + //AddLog(&MegData[2], CommUintLen); + CatOneEthSendQueue(MegData, CommUintLen); + rt_free(MegData); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + break;} + + case COMM_UNIT_CMD_TIME_SYNC:{ + if(PayLoad[0] == 0) { + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].TimeSyncFlag = true; + MAIN_DBG_LOG("CommUnit time synchronization failed! Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CUHeader->DevMac[0], CUHeader->DevMac[1], CUHeader->DevMac[2], CUHeader->DevMac[3], CUHeader->DevMac[4], CUHeader->DevMac[5]); + } + else if(PayLoad[0] == 1){ + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].TimeSyncFlag = false; + MAIN_DBG_LOG("CommUnit time synchronization succeed! Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CUHeader->DevMac[0], CUHeader->DevMac[1], CUHeader->DevMac[2], CUHeader->DevMac[3], CUHeader->DevMac[4], CUHeader->DevMac[5]); + } + uint32_t ctime = TimeTs(); + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag == true) { + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag = false; + LPDevConfigPara_t Config; + Config.CollectInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CollectInterval; + Config.ReportInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ReportInterval; + Config.ERInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERInterval; + Config.ERTime = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERTime; + Config.TimeStamp = ctime; + MAIN_DBG_LOG("CI:%d, RI:%d, EI:%d, ET:%d\r\n", Config.CollectInterval, Config.ReportInterval, Config.ERInterval, Config.ERTime); + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_READ, (uint8_t *)&Config, sizeof(LPDevConfigPara_t), Response); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ContLaser == true) + { + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].LaserOnOff == true) + {//´ò¿ª¼¤¹â + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_CONT_LASER, (uint8_t *)&GateWay->ConfigPara.CommUnitArray[CommUnitIdx].LaserOnOff, 1, Response); + } + MAIN_DBG_LOG("Issue laser control commands.\r\n"); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CailFlag == true) + { + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_CAIL, 0, 0, Response); + MAIN_DBG_LOG("Issue calibration instructions.\r\n"); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].TimeSyncFlag == true) + { + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_TIME_SYNC, (uint8_t *)&ctime, 4, Response); + MAIN_DBG_LOG("Issue a time synchronization command.\r\n"); + } + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + break;} + + case COMM_UNIT_CMD_CONT_LASER:{ + if(PayLoad[0] == 0) { + //Ó¦´ð·þÎñÆ÷ + MegData = rt_malloc(10); + MegData[0] = 7; + MegData[1] = 0; + MegData[2] = NET_COMM_CMD_CONT_LASER; + MegData[3] = CUHeader->DevMac[0]; + MegData[4] = CUHeader->DevMac[1]; + MegData[5] = CUHeader->DevMac[2]; + MegData[6] = CUHeader->DevMac[3]; + MegData[7] = CUHeader->DevMac[4]; + MegData[8] = CUHeader->DevMac[5]; + MegData[9] = PayLoad[0]; + CatOneEthSendQueue(MegData, 10); + rt_free(MegData); + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ContLaser = false; + MAIN_DBG_LOG("CommUnit The laser has been turned off! Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CUHeader->DevMac[0], CUHeader->DevMac[1], CUHeader->DevMac[2], CUHeader->DevMac[3], CUHeader->DevMac[4], CUHeader->DevMac[5]); + } + else if(PayLoad[0] == 1){ + //Ó¦´ð·þÎñÆ÷ + MegData = rt_malloc(10); + MegData[0] = 7; + MegData[1] = 0; + MegData[2] = NET_COMM_CMD_CONT_LASER; + MegData[3] = CUHeader->DevMac[0]; + MegData[4] = CUHeader->DevMac[1]; + MegData[5] = CUHeader->DevMac[2]; + MegData[6] = CUHeader->DevMac[3]; + MegData[7] = CUHeader->DevMac[4]; + MegData[8] = CUHeader->DevMac[5]; + MegData[9] = PayLoad[0]; + CatOneEthSendQueue(MegData, 10); + rt_free(MegData); + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ContLaser = false; + MAIN_DBG_LOG("CommUnit The laser has been activated! Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CUHeader->DevMac[0], CUHeader->DevMac[1], CUHeader->DevMac[2], CUHeader->DevMac[3], CUHeader->DevMac[4], CUHeader->DevMac[5]); + } + uint32_t ctime = TimeTs(); + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag == true) { + GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ConfigFlag = false; + LPDevConfigPara_t Config; + Config.CollectInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CollectInterval; + Config.ReportInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ReportInterval; + Config.ERInterval = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERInterval; + Config.ERTime = GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ERTime; + Config.TimeStamp = ctime; + MAIN_DBG_LOG("CI:%d, RI:%d, EI:%d, ET:%d\r\n", Config.CollectInterval, Config.ReportInterval, Config.ERInterval, Config.ERTime); + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_READ, (uint8_t *)&Config, sizeof(LPDevConfigPara_t), Response); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].ContLaser == true) + { + if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].LaserOnOff == true) + {//´ò¿ª¼¤¹â + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_CONT_LASER, (uint8_t *)&GateWay->ConfigPara.CommUnitArray[CommUnitIdx].LaserOnOff, 1, Response); + } + MAIN_DBG_LOG("Issue laser control commands.\r\n"); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].CailFlag == true) + { + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_CAIL, 0, 0, Response); + MAIN_DBG_LOG("Issue calibration instructions.\r\n"); + } + else if(GateWay->ConfigPara.CommUnitArray[CommUnitIdx].TimeSyncFlag == true) + { + CommUnitCmdSend(GateWay, CUHeader->DevMac, COMM_UNIT_CMD_TIME_SYNC, (uint8_t *)&ctime, 4, Response); + MAIN_DBG_LOG("Issue a time synchronization command.\r\n"); + } + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + break;} + + default: + break; + } + return CommUnitIdx; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: Cat1RevCallBack +* ¹¦ÄÜÃèÊö: 4G½ÓÊջص÷º¯Êý +* ²Î Êý: rData£¬Êý¾ÝÊäÈë½Ó¿Ú + rLen, Êý¾Ý³¤¶ÈÊäÈë½Ó¿Ú +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +int Cat1EthRevCallBack(GateWayPara GateWay, uint8_t *rData, uint16_t rLen) +{ + uint16_t check,crc16; + uint8_t *Data; + uint8_t *MegData; + uint8_t sLen; + + uint8_t CommUintMac[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + NetCommFrameHeader NCHeader = (NetCommFrameHeader)rData; + + uint16_t FrameLen = sizeof(NetCommFrameHeader_t) + NCHeader->PayloadLen; + if(FrameLen > CAT_ONE_REV_LEN_MAX) + return -1; + if(NCHeader->Header != 0x7A) + return -1; + if(memcmp(NCHeader->GWMac, GateWay->ConfigPara.GwMac, 6) != 0x00) + return -1; + + + check = CRC_Modbus(0xA001, rData, FrameLen); + crc16 = rData[FrameLen] | (rData[FrameLen + 1] << 8); + Data = &rData[sizeof(NetCommFrameHeader_t)]; + + if(check != crc16) + return -1; + + uint32_t cTime = TimeTs(); + if(abs((int)(NCHeader->Timestamp - cTime)) > 2) { + TimeSync(NCHeader->Timestamp); + GateWay->TimeSyncFlag = true; + SensorCommPara_t SCPara; + SCPara.Cmd = RS485_SENSOR_CMD_TIME_SYNC; + SCPara.SensorAddr = 0x00; + SCPara.SensorType = 0x00; + SCPara.CmdParaLen = 4; + SCPara.CmdPara = (uint8_t *)&NCHeader->Timestamp; + + memcpy(&CommUintMac[0], Data, 6); + + if(GateWay->ConfigPara.Rs485Ch1.Enable == true) { //ÄÚ²¿Í¨Ñ¶µ¥Ôª´¦Àí + if(GateWay->ConfigPara.Rs485Ch1.CommUnitEnable == true) + CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_TIME_SYNC, &rData[14], 4, GateWay->ConfigPara.Rs485Ch1.RS485Send); + else + RS485CmdSend(GateWay, 1, &SCPara); + } + if(GateWay->ConfigPara.Rs485Ch2.Enable == true) { + if(GateWay->ConfigPara.Rs485Ch2.CommUnitEnable == true) + CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_TIME_SYNC, &rData[14], 4, GateWay->ConfigPara.Rs485Ch2.RS485Send); + else + RS485CmdSend(GateWay, 2, &SCPara); + } + for(int i = 0; i < COMMUNIT_NUM_MAX; i++)//²ÎÊý±éÀú + { + if(GateWay->ConfigPara.CommUnitArray[i].RegFlag == true) + GateWay->ConfigPara.CommUnitArray[i].TimeSyncFlag = true;//УʱÖÃ룬µÈ´ýÏ´δËMACÖ÷É豸ÉÏ´«Êý¾ÝʱÏ·¢Ð£×¼Ö¸ÁµÍ¹¦ºÄ£© + } + //У׼ÆäËûͨѶÍø¹Ø + //CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_TIME_SYNC, &rData[14], 4, Sx1276LoRaSendBuffer); + } + + switch(NCHeader->Cmd) { + case NET_COMM_CMD_REG:{ + if(*Data == 1) { //×¢²á³É¹¦ + GateWay->SvrRegFlag = true; + //memcpy(GateWay->SvrMac, NCHeader->SvrMac, 6); + memset(GateWay->SvrMac, 0x00, 6); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + MAIN_DBG_LOG("Gateway Registered...\r\n"); + } + else { + GateWay->SvrRegFlag = false; + memset(GateWay->SvrMac, 0x00, 6); + MAIN_DBG_LOG("Gateway Register Failed....\r\n"); + } + break;} + + case NET_COMM_CMD_CAIL:{ + //Ó¦´ð·þÎñÆ÷ + MegData = rt_malloc(4); + MegData[0] = 1; + MegData[1] = 0; + MegData[2] = NET_COMM_CMD_CAIL; + MegData[3] = 1; + sLen = 4; + CatOneEthSendQueue(MegData, sLen); + rt_free(MegData); + //¿ªÊ¼Ð£×¼ + memcpy(&CommUintMac[0], Data, 6); + if(memcmp(CommUintMac, Data, 6) == 0) { //У׼ËùÓд«¸ÐÆ÷ + SensorCommPara_t SCPara; + SCPara.Cmd = RS485_SENSOR_CMD_CAIL; + SCPara.SensorAddr = 0x00; + //SCPara.SensorType = 0x00; + SCPara.CmdParaLen = 0; + SCPara.CmdPara = NULL; + if(GateWay->ConfigPara.Rs485Ch1.Enable == true) { //ÄÚ²¿Í¨Ñ¶µ¥Ôª´¦Àí + if(GateWay->ConfigPara.Rs485Ch1.CommUnitEnable == true) + RS485CmdSend(GateWay, 1, &SCPara); + else + CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_CAIL, NULL, 0, GateWay->ConfigPara.Rs485Ch1.RS485Send); + } + if(GateWay->ConfigPara.Rs485Ch2.Enable == true) { + if(GateWay->ConfigPara.Rs485Ch1.CommUnitEnable == true) + RS485CmdSend(GateWay, 2, &SCPara); + else + CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_CAIL, NULL, 0, GateWay->ConfigPara.Rs485Ch2.RS485Send); + } + + for(int i = 0; i < COMMUNIT_NUM_MAX; i++)//²ÎÊý±éÀú + { + if(GateWay->ConfigPara.CommUnitArray[i].RegFlag == true) + GateWay->ConfigPara.CommUnitArray[i].CailFlag = true;//У׼ÖÃ룬µÈ´ýÏ´δËMACÖ÷É豸ÉÏ´«Êý¾ÝʱÏ·¢Ð£×¼Ö¸ÁµÍ¹¦ºÄ£© + } + //У׼ÆäËûͨѶÍø¹Ø + //CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_CAIL, NULL, 0, Sx1276LoRaSendBuffer); + MAIN_DBG_LOG("Calibrate all device.\r\n"); + } + else { + int ret = CheckCommUnitReg(GateWay, CommUintMac); + if(ret < 0) + return -1; + if(GateWay->ConfigPara.CommUnitArray[ret].CUType != DEV_TYPE_EXT_COMMUNIT) + return -1; + if((GateWay->ConfigPara.CommUnitArray[ret].Mac[0][3] / 0x80) != 1) {//ÅжÏÊÇ·ñΪͨѶµ¥Ôª£¨Ö÷É豸£© + if(GateWay->ConfigPara.CommUnitArray[ret].Mac[0][2] == 1)//ÅжÏͨѶÀàÐÍ + { + GateWay->ConfigPara.CommUnitArray[ret].CailFlag = true;//У׼ÖÃ룬µÈ´ýÏ´δËMACÖ÷É豸ÉÏ´«Êý¾ÝʱÏ·¢Ð£×¼Ö¸ÁµÍ¹¦ºÄ£© + //CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_CAIL, NULL, 0, Sx1276LoRaSendBuffer);//²éѯģʽ + MAIN_DBG_LOG("Calibrate Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CommUintMac[0], CommUintMac[1], CommUintMac[2], CommUintMac[3], CommUintMac[4], CommUintMac[5]); + } + else if(GateWay->ConfigPara.CommUnitArray[ret].Mac[0][2] == 2)//ÅжÏͨѶÀàÐÍ + { + if(GateWay->ConfigPara.Rs485Ch1.Enable == true && !GateWay->ConfigPara.Rs485Ch1.CommUnitEnable) + { + CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_CAIL, NULL, 0, GateWay->ConfigPara.Rs485Ch1.RS485Send); + } + else if(GateWay->ConfigPara.Rs485Ch2.Enable == true && !GateWay->ConfigPara.Rs485Ch2.CommUnitEnable) + { + CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_CAIL, NULL, 0, GateWay->ConfigPara.Rs485Ch2.RS485Send); + } + } + } + } + break;} + + case NET_COMM_CMD_UPDATE:{ + MAIN_DBG_LOG("Received server response.....\r\n"); + break;} + + case NET_COMM_CMD_READ_GW_INFO: { + MegData = rt_malloc(512); + uint16_t SensorCnt = 0; + sLen = 5; + if(GateWay->ConfigPara.Rs485Ch1.Enable == true) { //ÄÚ²¿Í¨Ñ¶µ¥Ôª´¦Àí + if(GateWay->ConfigPara.Rs485Ch1.CommUnitEnable == true) { + SensorCnt++; + memcpy(&MegData[sLen], GateWay->ConfigPara.Rs485Ch1.CUData.Para.Mac[0], 6); + sLen += 6; + } + } + if(GateWay->ConfigPara.Rs485Ch2.Enable == true) { + if(GateWay->ConfigPara.Rs485Ch2.CommUnitEnable == true) { + SensorCnt++; + memcpy(&MegData[sLen], GateWay->ConfigPara.Rs485Ch2.CUData.Para.Mac[0], 6); + sLen += 6; + } + } + for(int i = 0; i < COMMUNIT_NUM_MAX; i++) { + if(GateWay->ConfigPara.CommUnitArray[i].RegFlag) { + for(int j = 0; j < GateWay->ConfigPara.CommUnitArray[i].SensorN; j++) + { + SensorCnt++; + memcpy(&MegData[sLen], GateWay->ConfigPara.CommUnitArray[i].Mac[j], 6); + sLen += 6; + } + } + } + MegData[sLen++] = GateWay->Battery; + MegData[sLen++] = GateWay->UploadInterval & 0x00ff; + MegData[sLen++] = (GateWay->UploadInterval >> 8) & 0x00ff; + MegData[sLen++] = GateWay->HistoryNum & 0x00ff; + MegData[sLen++] = (GateWay->HistoryNum >> 8) & 0x00ff; + MegData[sLen++] = (GateWay->HistoryNum >> 16) & 0x00ff; + MegData[sLen++] = (GateWay->HistoryNum >> 24) & 0x00ff; + MegData[0] = (sLen - 3) & 0x00ff;//Êý¾ÝÌ峤¶È + MegData[1] = ((sLen - 3) >> 8) & 0x00ff;//Êý¾ÝÌ峤¶È + MegData[2] = NET_COMM_CMD_READ_GW_INFO;//Ö¸Áî + MegData[3] = SensorCnt&0xFF; + MegData[4] = (SensorCnt >> 8)&0xFF; + CatOneEthSendQueue(MegData, sLen); + rt_free(MegData); + break; + } + + case NET_COMM_CMD_GW_PARA_CONFIG:{ + //Ó¦´ð·þÎñÆ÷ + MegData = rt_malloc(4); + MegData[0] = 1; + MegData[1] = 0; + MegData[2] = NET_COMM_CMD_GW_PARA_CONFIG; + MegData[3] = 1; + sLen = 4; + CatOneEthSendQueue(MegData, sLen); + rt_free(MegData); + MAIN_DBG_LOG("AThe server sends down the gateway parameter configuration...\r\n"); + break;} + + case NET_COMM_CMD_HIS_DATA: { + uint32_t *StartIdx, *EndIdx; + StartIdx = (uint32_t *)Data; + EndIdx = (uint32_t *)&Data[4]; + if(*StartIdx > GateWay->HistoryNum) + return -1; + + if(*EndIdx == 0) { + *EndIdx = GateWay->HistoryNum; + } + LogHeader_t LogH; + LogH.LogEndAddr = 0; + for(int i = *StartIdx; i < *EndIdx; i++) { + uint8_t *HisData; + int ret = ReadHistoryData(&LogH, &HisData, i); + if(HisData != NULL) { + MegData = rt_malloc(ret + 15); + MegData[0] = ret - 1 + 4; + MegData[1] = NET_COMM_CMD_HIS_DATA; + memcpy(&MegData[2], (uint8_t *)&LogH.LogIdx, 4); + sLen = 6; + memcpy(&MegData[sLen], HisData, 6); + sLen += 6; + memcpy(&MegData[sLen], &HisData[7], ret - 7); + sLen += ret - 7; + CatOneEthSendQueue(MegData, sLen); + rt_free(MegData); + rt_free(HisData); + rt_thread_delay(10); + } + else { + continue; + } + } + } + + case NET_COMM_CMD_ADD_UNIT:{ + if(*Data == 1) { //¼Èë³É¹¦ + MAIN_DBG_LOG("Adding CommUnit succeeded...\r\n"); + } + else { + MAIN_DBG_LOG("Adding CommUnit Failed...\r\n"); + } + break;} + + case NET_COMM_CMD_LP_DEV_CONFIG: { + //¿ªÊ¼ÅäÖà + SvrDownLPDevConfigPara_t *LPDevConfig; + LPDevConfig = (SvrDownLPDevConfigPara_t *)Data; + int ret = memcmp(CommUintMac, LPDevConfig->CommDevAddr, 6); + if(ret == 0) { + for(int i = 0; i < COMMUNIT_NUM_MAX; i++) { + if(GateWay->ConfigPara.CommUnitArray[i].RegFlag) { + GateWay->ConfigPara.CommUnitArray[i].CollectInterval = LPDevConfig->CollectInterval; + GateWay->ConfigPara.CommUnitArray[i].ReportInterval = LPDevConfig->ReportInterval; + GateWay->ConfigPara.CommUnitArray[i].ERInterval = LPDevConfig->ERInterval; + GateWay->ConfigPara.CommUnitArray[i].ERTime = LPDevConfig->ERTime; + GateWay->ConfigPara.CommUnitArray[i].ConfigFlag = true; + } + } + MAIN_DBG_LOG("Configure all the parameters of the main devices.\r\n"); + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + } + else { + memcpy(&CommUintMac[0], Data, 6); + int ret = CheckCommUnitReg(GateWay, CommUintMac); + if(ret < 0) + return -1; + GateWay->ConfigPara.CommUnitArray[ret].CollectInterval = LPDevConfig->CollectInterval; + GateWay->ConfigPara.CommUnitArray[ret].ReportInterval = LPDevConfig->ReportInterval; + GateWay->ConfigPara.CommUnitArray[ret].ERInterval = LPDevConfig->ERInterval; + GateWay->ConfigPara.CommUnitArray[ret].ERTime = LPDevConfig->ERTime; + GateWay->ConfigPara.CommUnitArray[ret].ConfigFlag = true; + WritePara((uint8_t *)&GateWay->ConfigPara, sizeof(GWConfigPara_t)); + MAIN_DBG_LOG("Main equipment parameter configuration. Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CommUintMac[0], CommUintMac[1], CommUintMac[2], CommUintMac[3], CommUintMac[4], CommUintMac[5]); + } + //Ó¦´ð·þÎñÆ÷ + MegData = rt_malloc(4); + MegData[0] = 1; + MegData[1] = 0; + MegData[2] = NET_COMM_CMD_LP_DEV_CONFIG; + MegData[3] = 1; + sLen = 4; + CatOneEthSendQueue(MegData, sLen); + rt_free(MegData); + break;} + + case NET_COMM_CMD_CONT_LASER:{ + memcpy(&CommUintMac[0], Data, 6); + int ret = CheckCommUnitReg(GateWay, CommUintMac); + if(ret < 0) + return -1; + if(GateWay->ConfigPara.CommUnitArray[ret].CUType != DEV_TYPE_EXT_COMMUNIT) + return -1; + if((GateWay->ConfigPara.CommUnitArray[ret].Mac[0][3] / 0x80) != 1) {//ÅжÏÊÇ·ñΪͨѶµ¥Ôª£¨Ö÷É豸£© + if(GateWay->ConfigPara.CommUnitArray[ret].Mac[0][2] == 1)//ÅжÏͨѶÀàÐÍ + { + GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff = Data[6];//·þÎñÆ÷Ï·¢´ò¿ª»òÕ߹رռ¤¹â + if(GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff == true) + { + GateWay->ConfigPara.CommUnitArray[ret].ContLaser = true;//¿ØÖƼ¤¹â£¬µÈ´ýÏ´δËMACÖ÷É豸ÉÏ´«Êý¾ÝʱÏ·¢´ò¿ª¼¤¹âÖ¸ÁµÍ¹¦ºÄ£© + MAIN_DBG_LOG("Waiting for the laser response. Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CommUintMac[0], CommUintMac[1], CommUintMac[2], CommUintMac[3], CommUintMac[4], CommUintMac[5]); + } + else if(GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff == false) + {//Ö±½Ó·¢ËÍ + MAIN_DBG_LOG("Waiting for the laser response. Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n", + CommUintMac[0], CommUintMac[1], CommUintMac[2], CommUintMac[3], CommUintMac[4], CommUintMac[5]); + GateWay->ConfigPara.CommUnitArray[ret].ContLaser = false; + CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_CONT_LASER, (uint8_t *)&GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff, 1, Sx1276LoRaSendBuffer);//²éѯģʽ + } + } + else if(GateWay->ConfigPara.CommUnitArray[ret].Mac[0][2] == 2)//ÅжÏͨѶÀàÐÍ + { + if(GateWay->ConfigPara.Rs485Ch1.Enable == true && !GateWay->ConfigPara.Rs485Ch1.CommUnitEnable) + { + GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff = Data[6];//·þÎñÆ÷Ï·¢´ò¿ª»òÕ߹رռ¤¹â + if(GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff == true) + { + GateWay->ConfigPara.CommUnitArray[ret].ContLaser = true;//¿ØÖƼ¤¹â£¬µÈ´ýÏ´δËMACÖ÷É豸ÉÏ´«Êý¾ÝʱÏ·¢´ò¿ª¼¤¹âÖ¸ÁµÍ¹¦ºÄ£© + } + else if(GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff == false) + { + CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_CONT_LASER, &Data[6], 1, GateWay->ConfigPara.Rs485Ch1.RS485Send); + } + } + else if(GateWay->ConfigPara.Rs485Ch2.Enable == true && !GateWay->ConfigPara.Rs485Ch2.CommUnitEnable) + { + GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff = Data[6];//·þÎñÆ÷Ï·¢´ò¿ª»òÕ߹رռ¤¹â + if(GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff == true) + { + GateWay->ConfigPara.CommUnitArray[ret].ContLaser = true;//¿ØÖƼ¤¹â£¬µÈ´ýÏ´δËMACÖ÷É豸ÉÏ´«Êý¾ÝʱÏ·¢´ò¿ª¼¤¹âÖ¸ÁµÍ¹¦ºÄ£© + } + else if(GateWay->ConfigPara.CommUnitArray[ret].LaserOnOff == false) + { + CommUnitCmdSend(GateWay, CommUintMac, COMM_UNIT_CMD_CONT_LASER, &Data[6], 1, GateWay->ConfigPara.Rs485Ch2.RS485Send); + } + } + } + } + break;} + + default: + break; + } + return 0; +} diff --git a/Project/GateWay/source/User/Src/RS485Task.c b/Project/GateWay/source/User/Src/RS485Task.c new file mode 100644 index 0000000..997b512 --- /dev/null +++ b/Project/GateWay/source/User/Src/RS485Task.c @@ -0,0 +1,623 @@ +#include "main.h" +#include "RS485Task.h" +#include "Public.h" +#include "spiflash.h" +#include "CatOneTask.h" +#include "DebugCmd.h" +#include "update_protocol.h" +#include "bsp.h" + +//#define RS485_DBG_LOG(...) { if(RS485DispEn) Debug_Printf(__VA_ARGS__);} + +//static uint8_t RS485DispEn = false; + +SensorCommPara_t SComm1Para; +SensorCommPara_t SComm2Para; + +const uint8_t RS485SensorCmdPayLoadLen[RS485_SENSOR_CMD_END] = {0, 0, 0, 1, 0}; + +/***************************************************************************************** +* º¯ÊýÃû³Æ: SavSensorData +* ¹¦ÄÜÃèÊö: ¼Ç¼´«¸ÐÆ÷Êý¾Ý +* ²Î Êý: SensorIdx, ´«¸ÐÆ÷ÐòºÅ + Para£¬´«¸ÐÆ÷½á¹¹Ö¸Õë + Data, ´«¸ÐÆ÷Êý¾Ý + Len, ´«¸ÐÆ÷Êý¾Ý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void SavSensorData(uint8_t SensorIdx, CommUnitData CUData, uint8_t *Data, uint8_t Len) +{ + if(Data == NULL) { + memset(CUData->Data[SensorIdx], 0x00, SENSOR_DATA_LEN_MAX); + } + else { + memcpy(CUData->Data[SensorIdx], Data, Len); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Analyze +* ¹¦ÄÜÃèÊö: 485Êý¾Ý½âÎö +* ²Î Êý: SCPara, ´«¸ÐÆ÷·¢ËͲÎÊý + Para, ´«¸ÐÆ÷½á¹¹Ö¸Õë + rData, ´«¸ÐÆ÷Êý¾ÝÈë¿Ú + rLen, ´«¸ÐÆ÷Êý¾Ý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void RS485Analyze(GateWayPara GateWay, SensorCommPara SCPara, CommUnit Para, uint8_t *rData, uint8_t rLen) +{ + uint16_t crc16; + uint8_t *Payload; + + crc16 = (rData[rLen - 1] << 8)|rData[rLen - 2]; + uint16_t Check = CRC_Modbus(0xA001, rData, rLen - 2); + if(crc16 != Check) + return; + + FrameHeader Header = (FrameHeader)rData; + if(Header->Cmd != RS485_SENSOR_CMD_QUERY) { + if(Header->SlvAddr != SCPara->SensorAddr) + return; + } + + Payload = &rData[sizeof(FrameHeader)]; + if(Header->PayloadLen == 0) + return; + + if(Header->SlvAddr == 0 || Header->SlvAddr > SENSOR_NUM_MAX) + return; + + SCPara->SensorErrCnt[Header->SlvAddr - 1] = 0; + switch(Header->Cmd) { + case RS485_SENSOR_CMD_SET_ADDR: + if(*Payload == 1) { + MAIN_DBG_LOG("Sensor%d Addr Set succeed!\r\n", Header->SlvAddr); + } + else { + MAIN_DBG_LOG("Sensor%d Addr Set failed!\r\n", Header->SlvAddr); + } + break; + + case RS485_SENSOR_CMD_CAIL: + if(*Payload == 1) { + MAIN_DBG_LOG("Sensor%d calibration succeeded!\r\n", Header->SlvAddr); + } + else { + MAIN_DBG_LOG("Sensor%d calibration succeeded!\r\n", Header->SlvAddr); + } + break; + + case RS485_SENSOR_CMD_QUERY: + if(Para->Para.SensorN < 16) { + Para->Para.SensorN++; + Para->Para.SensorType[SCPara->SensorAddr - 1] = rData[6] | (rData[7] << 8); + MAIN_DBG_LOG("Found Sensor%d, Type: %d!\r\n", Header->SlvAddr, Para->Para.SensorType[SCPara->SensorAddr - 1]); + } + break; + + case RS485_SENSOR_CMD_READ: { + memcpy(SCPara->SensorData.Data[SCPara->SensorAddr - 1], &rData[sizeof(FrameHeader_t)], Header->PayloadLen); + if(SCPara->SendFlag) + SCPara->ReadSensorCnt++; + DebugDisplaySensorData(Header->SlvAddr, 0, &rData[sizeof(FrameHeader_t)]); + } + + default: + break; + } +} + +static void update_on_start(uint8_t* frame, int len, uint8_t* pload, int size) +{ + update_protocol_req_t* pReq = (void*)&frame[sizeof(update_protocol_hd_t)]; + + //TODO: + + boot_para_t cfg = {0}; + + cfg.AppFlag = 0; + cfg.UpdateFlag = APP_UPDATE_FLAG; + cfg.Crc32Check = pReq->AppCrc32; + cfg.PackageNum = pReq->PackageNum; + cfg.AppSize = pReq->AppSize; + /** + ²Ù×÷FALSH £¬Ð´Éý¼¶²ÎÊý + **/ + dev_boot_write_param(cfg); + + update_send_cmd(0x01, 1, pReq->PackageNum); + + //ÖØÆô½øÈëBOOT + NVIC_SystemReset(); +} + +static int update_cmd_process(uint8_t cmd, void* frame, int len, void* pload, int size) +{ + int res = -1; + + switch (cmd) { + case 0x81: { + update_on_start(frame, len, pload, size); + + res = 0; + } + break; + + default: + break; + + } + + return res; +} + +static int update_process(void* frame, int len) +{ + uint8_t cmd = 0; + + uint8_t slave_addr = 0; + + uint8_t user_data[256] = {0}; + + int user_data_len = 0; + + int res = update_unpack(frame, len, &cmd, &slave_addr, user_data, &user_data_len); + + if (res != 0) + return -1; + + if (slave_addr != 0x01) + return -2; + + res = update_cmd_process(cmd, frame, len, user_data, user_data_len); + + if (res != 0) + return -3; + + return 0; +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485SensorCmdSend +* ¹¦ÄÜÃèÊö: Ï·¢´«¸ÐÆ÷Ö¸ÁÊý +* ²Î Êý: Para,ͨѶ²ÎÊýÈë¿Ú +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void RS485SensorCmdSend(GateWayPara GateWay, SensorCommPara SensorComm) +{ + uint8_t sData[50]; + uint8_t sLen; + + if(SensorComm->Cmd >= RS485_SENSOR_CMD_END) + return; + + FrameHeader Header = (FrameHeader)sData; + + Header->Header = 0x7C; + Header->SlvAddr = SensorComm->SensorAddr; + Header->Cmd = SensorComm->Cmd; + //Header->DevType = SensorComm->SensorType; + Header->PayloadLen = SensorComm->CmdParaLen; + + sLen = sizeof(FrameHeader_t); + if(SensorComm->CmdParaLen > 0) { + memcpy(&sData[sLen], SensorComm->CmdPara, SensorComm->CmdParaLen); + sLen += SensorComm->CmdParaLen; + } + uint16_t Check = CRC_Modbus(0xA001, sData, sLen); + + sData[sLen++] = Check & 0xff; + sData[sLen++] = (Check >> 0x08) & 0x00ff; + + if(SensorComm == &SComm1Para) + GateWay->ConfigPara.Rs485Ch1.RS485Send(sData, sLen); + else + GateWay->ConfigPara.Rs485Ch2.RS485Send(sData, sLen); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485SensorCmdSend +* ¹¦ÄÜÃèÊö: Ï·¢´«¸ÐÆ÷Ö¸ÁÊý +* ²Î Êý: CommUintAddr£¬ ͨѶµ¥ÔªµØÖ· + Para,ͨѶ²ÎÊýÈë¿Ú +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void RS485CmdSend(GateWayPara GateWay, uint8_t CommUintAddr, SensorCommPara SensorComm) +{ + SensorCommPara SC; + + if(CommUintAddr) + SC = &SComm1Para; + else + SC = &SComm2Para; + + SC->Cmd = SensorComm->Cmd; + SC->CmdPara = SensorComm->CmdPara; + SC->CmdParaLen = SensorComm->CmdParaLen; + SC->SensorAddr = SensorComm->SensorAddr; + //SC->SensorType = SensorComm->SensorType; + + RS485SensorCmdSend(GateWay, SC); +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485LoopHandler +* ¹¦ÄÜÃèÊö: RS485Ñ­»·´¦Àíº¯Êý +* ²Î Êý: GateWay, Íø¹Ø²ÎÊý¾ä±ú + RS485Ch, RS485ͨµÀ¾ä±ú + SCPara£¬ RS485ͨѶ¾ä±ú +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static uint8_t CommUintData[512]; +int test = 0; +void RS485LoopHandler(GateWayPara GateWay, RS485Para RS485Ch, SensorCommPara SCPara) +{ + uint8_t RxBuffTemp[RS485_RX_BUFF_LEN_MAX]; + uint8_t RxLenTemp; + uint16_t CommUintLen; + rt_err_t result; + uint8_t MegData[9]; + int ret; + + if(RS485Ch->Enable == false) { + rt_thread_delay(10); + return; + } + + if(RS485Ch->CommUnitEnable == true) { //ʹÓÃÄÚÖÃͨѶµ¥Ôª + if(RS485Ch->QuerySensorFlag == true) { //¿ª»ú²éÕÒ´«¸ÐÆ÷ + if(SCPara->SensorCnt < SENSOR_NUM_MAX) { + rt_thread_delay(50); + SCPara->Cmd = RS485_SENSOR_CMD_QUERY; + SCPara->SensorAddr = SCPara->SensorCnt + 1; + SCPara->SensorType = 0; + SCPara->CmdParaLen = RS485SensorCmdPayLoadLen[RS485_SENSOR_CMD_QUERY]; + SCPara->CmdPara = NULL; + //rt_mutex_take(GateWay->UartRevMutex, RT_WAITING_FOREVER); + SCPara->RS485TimeOutCnt = 0; + SCPara->RS485RxLen = 0; + RS485SensorCmdSend(GateWay, SCPara); + SCPara->SendFlag = true; + SCPara->SensorCnt++; + if(SCPara->SensorCnt >= SENSOR_NUM_MAX) { + SCPara->ReadSensorInterval = 2; + SCPara->SensorCnt = 0; + SCPara->ReadSensorCnt = 0; + RS485Ch->QuerySensorFlag = false; + } + } + } + else if(RS485Ch->CUData.Para.SensorN > 0){ + SCPara->SendFlag = false; + if(SCPara->ReadSensorInterval > 0) { + SCPara->ReadSensorInterval--; + } + else { + if(SCPara->ReadSensorCnt >= RS485Ch->CUData.Para.SensorN || SCPara->SensorCnt >= SENSOR_NUM_MAX) { + SCPara->SensorCnt = 0; + SCPara->ReadSensorCnt = 0; + SCPara->ReadSensorInterval = GateWay->ConfigPara.CommUnitReadInterval * 5; + RS485Ch->CUData.Para.BatLevel = GateWay->Battery; + CommUintLen = CommUintOrgData(GateWay, &RS485Ch->CUData.Para, &SCPara->SensorData, CommUintData); + //AddLog(&CommUintData[2], CommUintLen - 2); + CatOneEthSendQueue(CommUintData, CommUintLen); + if(RS485Ch == &GateWay->ConfigPara.Rs485Ch1) { + MAIN_DBG_LOG("InCommUint1 Send Meg...\r\n"); + } + else { + MAIN_DBG_LOG("InCommUint2 Send Meg...\r\n"); + } + SCPara->SensorCnt = 0; + } + else { + if(RS485Ch->CUData.Para.SensorType[SCPara->SensorCnt] != 0) { + rt_thread_delay(50); + SCPara->Cmd = RS485_SENSOR_CMD_READ; + SCPara->SensorAddr = SCPara->SensorCnt + 1; + SCPara->SensorType = RS485Ch->CUData.Para.SensorType[SCPara->SensorCnt]; + SCPara->CmdParaLen = RS485SensorCmdPayLoadLen[RS485_SENSOR_CMD_READ]; + SCPara->CmdPara = NULL; + //rt_mutex_take(GateWay->UartRevMutex, RT_WAITING_FOREVER); + RS485SensorCmdSend(GateWay, SCPara); + SCPara->SendFlag = true; + } + SCPara->SensorCnt++; + } + } + } + } + else { //¶ÁÈ¡ÍâÖÃͨѶµ¥Ôª + if(SCPara->RS485CommUnitReadTimeDelay >= (GateWay->ConfigPara.CommUnitReadInterval * 5) && SCPara->SendFlag == false) { + if(SCPara->SendUnitCommIdx < COMMUNIT_NUM_MAX) { + if(GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].RegFlag && + GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][2] == 0x02) { + Debug_Printf("RS485Ch%d Read CommUnit: %02X:%02X:%02X:%02X:%02X:%02X\r\n", + ((SCPara == &SComm1Para) ? 1 : 2), + GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][0], + GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][1], + GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][2], + GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][3], + GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][4], + GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][5]); + CommUnitCmdSend(GateWay, GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0], COMM_UNIT_CMD_READ, NULL, 0, RS485Ch->RS485Send); + SCPara->SendFlag = true; + } + else { + SCPara->SendUnitCommIdx++; + return; + } + } + else { + SCPara->SendUnitCommIdx = 0; + SCPara->RS485CommUnitReadTimeDelay = 0; + } + } + } + + if(SCPara->RS485CommUnitReadTimeDelay < (GateWay->ConfigPara.CommUnitReadInterval * 5)) + SCPara->RS485CommUnitReadTimeDelay++; + + result = rt_sem_take(SCPara->RS485Rev_Sem, 200); + if(result == RT_EOK) { + memcpy(RxBuffTemp, SCPara->RS485RxBuff, SCPara->RS485RxLen); + RxLenTemp = SCPara->RS485RxLen; +// memset(SCPara->RS485RxBuff, 0x00, RS485_RX_BUFF_LEN_MAX); + SCPara->RS485RxLen = 0; + if(RxBuffTemp[0] == 0x7A && RS485Ch->UpgradeEnable == true) { //Éý¼¶ + update_process(RxBuffTemp,RxLenTemp); + } + else if(RxBuffTemp[0] == 0x7A && RS485Ch->CommUnitEnable == true) { //ÄÚÖÃͨѶµ¥ÔªÊý¾Ý½âÎö + if(SCPara->SendFlag == false) { + SCPara->RS485RxLen = 0; + return; + } + RS485Analyze(GateWay, SCPara, &RS485Ch->CUData, RxBuffTemp, RxLenTemp); + //rt_mutex_release(GateWay->UartRevMutex); + } + else if(RxBuffTemp[0] == 0x7B && RS485Ch->CommUnitEnable == false){ //¶ÁÈ¡ÍⲿͨѶµ¥ÔªÊý¾Ý½âÎö + if(SCPara == &SComm1Para) + ret = GateWay->CommUnitRevCallBack(GateWay, RxBuffTemp, RxLenTemp, GateWay->ConfigPara.Rs485Ch1.RS485Send); + else + ret = GateWay->CommUnitRevCallBack(GateWay, RxBuffTemp, RxLenTemp, GateWay->ConfigPara.Rs485Ch2.RS485Send); + if(ret == 0xff) { //×¢²áÐÅÏ¢ + SCPara->RS485RxLen = 0; + return; + } + if(SCPara->SendFlag && GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].RevNewDataFlag) { + SCPara->SendUnitCommIdx++; + } + else { + SCPara->RS485RxLen = 0; + return; + } + } + else { //µ÷ÊÔÃüÁî½âÎö + DebugAnalyze(GateWay, RxBuffTemp, RxLenTemp); + } + SCPara->RS485RxLen = 0; + SCPara->SendFlag = false; + } + else { + if(RS485Ch->CommUnitEnable == true) { + //rt_mutex_release(GateWay->UartRevMutex); + if(SCPara->SendFlag == true) { //&& RS485Ch->CUData.Para.SensorN > 0 && RS485Ch->QuerySensorFlag == false){ + if(RS485Ch == &GateWay->ConfigPara.Rs485Ch1) { + test++; + MAIN_DBG_LOG("InCommUint1, Sensor %d Comm Error, Cmd %d...\r\n", SCPara->SensorAddr, SCPara->Cmd); + } + else { + MAIN_DBG_LOG("InCommUint2, Sensor %d Comm Error, Cmd %d...\r\n", SCPara->SensorAddr, SCPara->Cmd); + } + SCPara->SensorErrCnt[SCPara->SensorAddr - 1]++; + if(SCPara->SensorErrCnt[SCPara->SensorAddr - 1] >= 5) + SavSensorData(SCPara->SensorAddr - 1, &SCPara->SensorData, NULL, 0); + } + } + else if(SCPara->SendFlag){ + GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommErrCnt++; + if(GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommErrCnt == 10) { + GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommErrCnt = 0; + if(GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommStatus) { + GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommStatus = 0; + MegData[0] = 7; + MegData[1] = COMM_UNIT_CMD_READ; + memcpy(&MegData[2], GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0], 6); + MegData[8] = GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommStatus; + CatOneEthSendQueue(MegData, 9); //·¢ËÍÀëÏßÏûÏ¢ + } + } + SCPara->SendUnitCommIdx++; + } + SCPara->SendFlag = false; + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1_Thread_Entry +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1ÈÎÎñº¯Êý +* ²Î Êý: ÈÎÎñ²ÎÊýÈë¿Ú +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void RS485Ch1_Thread_Entry(void *parameter) +{ + uint8_t InCommUnitMac[6] = {0x01, 0x80, 0x02, 0x00, 0x00, 0x01}; + GateWayPara GateWay; + SensorCommPara SCPara; + RS485Para RS485Ch; + + SCPara = &SComm1Para; + SCPara->SensorCnt = 0; + SCPara->InitOverFlag = false; + SCPara->ReadSensorInterval = 300; + GateWay = (GateWayPara)parameter; + InCommUnitMac[3] = GateWay->ConfigPara.GwMac[4]; + InCommUnitMac[4] = GateWay->ConfigPara.GwMac[5]; + RS485Ch = &GateWay->ConfigPara.Rs485Ch1; + memcpy(RS485Ch->CUData.Para.Mac, InCommUnitMac, 6); + if(RS485Ch->CommUnitEnable == true) { + RS485_CH1_POW_ON(); + RS485Ch->CUData.Para.SensorN = 0; + memset(RS485Ch->CUData.Para.SensorType, 0x00, sizeof(SENSOR_NUM_MAX * 2)); + RS485Ch->QuerySensorFlag = true; + RS485Ch->CUData.Para.CommStatus = true; + } + SCPara->RS485CommUnitReadTimeDelay = 100; + SCPara->RS485Rev_Sem = rt_sem_create("rsch1sem", 0, RT_IPC_FLAG_FIFO); + if(SCPara->RS485Rev_Sem == RT_NULL) { + Debug_Printf("RS485Ch1Rev Sem Create Failed!\r\n"); + } + Debug_Printf("RS485Ch1Rev Thread is running£¡\r\n"); + + rt_thread_delay(3000); + SCPara->InitOverFlag = true; + + + update_init(RS485Ch1UartSend); + while(1) { + RS485LoopHandler(GateWay, RS485Ch, SCPara); + //rt_thread_delay(10); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1RxIrqCallback +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1Öжϴ¦Àí»Øµ÷º¯Êý +* ²Î Êý: rData ½ÓÊÕµ½µÄÊý¾Ý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void RS485Ch1RxIrqCallback(uint8_t rData) +{ + if(SComm1Para.RS485TimeOutCnt == 0) { + SComm1Para.RS485RxLen = 0; + } + if(SComm1Para.RS485RxLen < RS485_RX_BUFF_LEN_MAX) + SComm1Para.RS485RxBuff[SComm1Para.RS485RxLen++] = rData; + + SComm1Para.RS485TimeOutCnt = 3; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch2_Thread_Entry +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1ÈÎÎñº¯Êý +* ²Î Êý: ÈÎÎñ²ÎÊýÈë¿Ú +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void RS485Ch2_Thread_Entry(void *parameter) +{ + uint8_t InCommUnitMac[6] = {0x01, 0x80, 0x02, 0x00, 0x00, 0x02}; + GateWayPara GateWay; + SensorCommPara SCPara; + RS485Para RS485Ch; + + SCPara = &SComm2Para; + SCPara->SensorCnt = 0; + SCPara->InitOverFlag = false; + SCPara->ReadSensorInterval = 0; + GateWay = (GateWayPara)parameter; + InCommUnitMac[3] = GateWay->ConfigPara.GwMac[4]; + InCommUnitMac[4] = GateWay->ConfigPara.GwMac[5]; + RS485Ch = &GateWay->ConfigPara.Rs485Ch2; + memcpy(RS485Ch->CUData.Para.Mac, InCommUnitMac, 6); + if(RS485Ch->CommUnitEnable == true) { + RS485_CH2_POW_ON(); + RS485Ch->CUData.Para.SensorN = 0; + memset(RS485Ch->CUData.Para.SensorType, 0x00, sizeof(SENSOR_NUM_MAX * 2)); + RS485Ch->QuerySensorFlag = true; + RS485Ch->CUData.Para.CommStatus = 1; + } + SCPara->RS485CommUnitReadTimeDelay = 100; + SCPara->RS485Rev_Sem = rt_sem_create("rsch2sem", 0, RT_IPC_FLAG_FIFO); + if(SCPara->RS485Rev_Sem == RT_NULL) { + Debug_Printf("RS485Ch2Rev Sem Create Failed!\r\n"); + } + Debug_Printf("RS485Ch2Rev Thread is running£¡\r\n"); + rt_thread_delay(3000); + SCPara->InitOverFlag = true; + while(1) { + RS485LoopHandler(GateWay, RS485Ch, SCPara); + //rt_thread_delay(10); + } +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch2RxIrqCallback +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1Öжϴ¦Àí»Øµ÷º¯Êý +* ²Î Êý: rData ½ÓÊÕµ½µÄÊý¾Ý +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void RS485Ch2RxIrqCallback(uint8_t rData) +{ + if(SComm2Para.RS485TimeOutCnt == 0) { + SComm2Para.RS485RxLen = 0; + } + + if(SComm2Para.RS485RxLen < RS485_RX_BUFF_LEN_MAX) + SComm2Para.RS485RxBuff[SComm2Para.RS485RxLen++] = rData; + + SComm2Para.RS485TimeOutCnt = 3; +} + + +void RS485RxOverhandler(void) +{ + if(SComm1Para.RS485TimeOutCnt > 0) + SComm1Para.RS485TimeOutCnt--; + + if(SComm1Para.RS485RxLen > 5 && SComm1Para.RS485TimeOutCnt == 0) { + if(SComm1Para.InitOverFlag == true) { + rt_sem_release(SComm1Para.RS485Rev_Sem); + SComm1Para.RS485TimeOutCnt = 20; + } + else { + SComm1Para.RS485RxLen = 0; + SComm1Para.RS485TimeOutCnt = 0; + } + } + + if(SComm2Para.RS485TimeOutCnt > 0) + SComm2Para.RS485TimeOutCnt--; + + if(SComm2Para.RS485RxLen > 5 && SComm2Para.RS485TimeOutCnt == 0) { + if(SComm2Para.InitOverFlag == true) { + SComm2Para.RS485TimeOutCnt = 20; + rt_sem_release(SComm2Para.RS485Rev_Sem); + } + else { + SComm2Para.RS485RxLen = 0; + SComm2Para.RS485TimeOutCnt = 0; + } + } +} +#if 0 +void RS485Ch2RxIrqCallback(uint8_t rData) +{ + static bool FrameHeader = false; + static uint8_t rLen = 0; + + if(FrameHeader == false) { + if(rData == 0x7a || rData == 0x7b) { + FrameHeader = true; + RS485Chr2RxLen = 0; + } + } + if(RS485Chr2RxLen < RS485_RX_BUFF_LEN_MAX) { + RS485Chr2RxBuff[RS485Chr2RxLen++] = rData; + } + else { + FrameHeader = false; + RS485Chr2RxLen = 0; + } + + if(RS485Chr2RxLen == 6) { + rLen = rData + 8; + } + else if(RS485Chr2RxLen > 6) { + if(RS485Chr2RxLen >= rLen) { + rt_sem_release(RS485Ch2Rev_Sem); + FrameHeader = false; + } + } +} +#endif diff --git a/Project/GateWay/source/User/Src/app_comm.c b/Project/GateWay/source/User/Src/app_comm.c new file mode 100644 index 0000000..eb391f2 --- /dev/null +++ b/Project/GateWay/source/User/Src/app_comm.c @@ -0,0 +1,420 @@ +/* +Êý¾ÝͨÐÅÈÎÎñ +*/ +#include "bsp.h" + +#include "ringbuffer.h" +#include "protocol.h" +#include "update_protocol.h" + +#include "app_comm.h" +#include "app_tp_collect.h" +#include "app_ad_collect.h" + +#define USING_SIMULATOR ( 0 ) + +#define COMM_RECV_OUTTIME (20) + +static struct { + ring_buf_t rb; + uint8_t rb_pool[128]; +} g_comm; + +static struct { + uint8_t rxbuf[256]; + int rxbytes; +} g_frame; + +static void rs485_rx_cb(uint8_t data) +{ + ring_buf_put(&g_comm.rb, &data, 1); +} + +/** +·µ»ØÖµ:³É¹¦:len,ʧ°Ü: 0 +***/ +static int recive_frame(void) +{ + uint8_t data = 0; + + int len = ring_buf_len(&g_comm.rb); + + if (len == 0) + return 0; + + for (int i = 0; i < len; i++) { + + if (g_frame.rxbytes < sizeof(g_frame.rxbuf)) { + + int byte = ring_buf_get(&g_comm.rb, &data, 1); + + if (byte > 0) { + + g_frame.rxbuf[ g_frame.rxbytes] = data; + + g_frame.rxbytes++; + } + } + } + + return len; +} + +static void update_on_start(uint8_t* frame, int len, uint8_t* pload, int size) +{ + update_protocol_req_t* pReq = (void*)&frame[sizeof(update_protocol_hd_t)]; + + boot_para_t cfg = {0}; + + cfg.AppFlag = 0; + cfg.UpdateFlag = APP_UPDATE_FLAG; + cfg.Crc32Check = pReq->AppCrc32; + cfg.PackageNum = pReq->PackageNum; + cfg.AppSize = pReq->AppSize; + + dev_boot_write_param(cfg); + + update_send_cmd(0x01, 1, pReq->PackageNum); + + //ÖØÆô½øÈëBOOT + NVIC_SystemReset(); +} + +static int update_cmd_process(uint8_t cmd, void* frame, int len, void* pload, int size) +{ + int res = -1; + + switch (cmd) { + case 0x81: { + update_on_start(frame, len, pload, size); + + res = 0; + } + break; + + default: + break; + + } + + return res; +} + +static int update_process(void* frame, int len) +{ + uint8_t cmd = 0; + + uint8_t slave_addr = 0; + + uint8_t user_data[256] = {0}; + + int user_data_len = 0; + + int res = update_unpack(frame, len, &cmd, &slave_addr, user_data, &user_data_len); + + if (res != 0) + return -1; + + if (slave_addr != 0x01) + return -2; + + res = update_cmd_process(cmd, frame, len, user_data, user_data_len); + + if (res != 0) + return -3; + + return 0; +} + +static void comm_rsp(uint8_t slave_addr,uint8_t frame_cmd,void *pay, int len) +{ + uint8_t frame_ack[128] = {0}; + + uint16_t frame_ack_len = 0; + + protocol_pack_frame(slave_addr, frame_cmd - 0x80, pay, len, frame_ack, sizeof(frame_ack), &frame_ack_len); + + dev_rs485_send(frame_ack, frame_ack_len); +} + +static void comm_process(uint8_t* frame, int len) +{ + uint16_t slave_addr = 0; + uint8_t frame_cmd = 0; + uint8_t frame_data[64] = {0}; + uint16_t frame_data_len = 0; + + /***Êý¾Ý½âÂë***/ + int err = -1; + + err= protocol_unpack_frame(frame, len, &slave_addr, &frame_cmd, frame_data, &frame_data_len); + + if (err != PROTOCOL_SUCCESS) + return ; + + //TODO:»ñÈ¡±¾»úµØÖ· + uint8_t local_addr = 0; + dev_cfg_get_devid(&local_addr); + + + uint8_t rsp_data[64] = {0}; + void* payload = rsp_data; + uint16_t payload_len = 0; + + uint8_t is_match =1; + + switch (frame_cmd) { + + case PROTOCOL_CMD_SET_ID: { + + // + if (slave_addr != local_addr) + return ; + + id_data_t data = {0}; + + memcpy(&data, &frame_data, sizeof(data)); + + dev_cfg_set_devid(data.id); + + BSP_LOG("set: device id =[%d] =[0x%x] \n", data.id,data.id); + } + break; + + case PROTOCOL_CMD_GET_ID:{ + + id_data_t id_data = {0}; + + id_data.id = local_addr; + + payload_len = sizeof(id_data); + + memcpy(payload ,&id_data,payload_len); + + BSP_LOG("get: device id =[%d] =[0x%x] \n", id_data.id,id_data.id); + + }break; + + + case PROTOCOL_CMD_GET_TP: { + //TODO: get tp datas + if (slave_addr != local_addr) + return ; + + tp_datas_t tp_data = {0}; + + collect_tp_info_t tp_info={0}; + + app_collect_tp_get(&tp_info); + + memcpy( &tp_data,&tp_info.tp_datas,sizeof(tp_data)); + + //¼æÈݾÉЭÒé,ûÓÐÓõ½µÄͨµÀ£¬Ìî³äÎÞЧÊý¾Ý + for(int i=0; i <8-TP_SENSOR_NUM; i++){ + + tp_data.channels[i+TP_SENSOR_NUM].status =1; + tp_data.channels[i+TP_SENSOR_NUM].value =0; + } + + for (int i = 0; i < TP_SENSOR_NUM ; i++) { + + char strbuf[128]={0}; + + snprintf(strbuf,sizeof(strbuf)," comm ad ch[%d] %08.4f \r\n", i, tp_data.channels[i].value); + + BSP_LOG("%s",strbuf); + } + + BSP_LOG("\r\n"); + + payload_len = sizeof(tp_data); + + memcpy(payload, &tp_data, payload_len); + + }break; + + case PROTOCOL_CMD_GET_AD: { + + // + if (slave_addr != local_addr) + return ; + + //TODO: get ad datas + ad_datas_t ad_data = {0}; + + app_collect_ad_get(&ad_data); + + //¼æÈݾÉЭÒé,ûÓÐÓõ½µÄͨµÀ£¬Ìî³äÎÞЧÊý¾Ý + for(int i=0; i <8-YB_SENSOR_NUM; i++){ + + ad_data.channels[i+5].status =1; + } + + BSP_LOG("\r\n"); + + for (int i = 0; i < YB_SENSOR_NUM ; i++) { + + char strbuf[128] = {0}; + + snprintf(strbuf, sizeof(strbuf), " comm ad ch[%d] %08.4f \r\n", i, ad_data.channels[i].value); + + BSP_LOG("%s", strbuf); + } + + BSP_LOG("\r\n"); + + payload_len = sizeof(ad_data); + + memcpy(payload, &ad_data, payload_len); + + } + break; + + case PROTOCOL_CMD_SET_TP_OFFSET:{ + + if (slave_addr != local_addr) + return ; + + offset_set_data_t offset_data={0}; + + memcpy( &offset_data,frame_data,sizeof(offset_data)); + + dev_cfg_set_temp_offset(offset_data.id, offset_data.prams.value); + + char strbuf[128]={0}; + + snprintf(strbuf,sizeof(strbuf)," set[%d] offset %.2f \r\n", offset_data.id , offset_data.prams.value); + + BSP_LOG("%s",strbuf); + + }break; + + + case PROTOCOL_CMD_GET_TP_OFFSET:{ + + // + if (slave_addr != local_addr) + return ; + + offset_get_param_t *param = (void *)frame_data; + + offset_get_data_t offset_data={0}; + + float val = 200; + + dev_cfg_get_temp_offset( param->id,&val); + + offset_data.id = param->id; + + offset_data.prams.value = val; + + payload_len = sizeof(offset_data); + + memcpy(payload,&offset_data,payload_len); + + char strbuf[128]={0}; + + snprintf(strbuf,sizeof(strbuf)," get[%d] offset %.2f \r\n", offset_data.id , offset_data.prams.value); + + BSP_LOG("%s",strbuf); + + + }break; + + case PROTOCOL_CMD_RESET_CHANNEL: { + // + if (slave_addr != local_addr) + return ; + + app_collect_ad_reset_offset(); + + BSP_LOG("reset offset start"); + + } + break; + + default: + is_match =0; + break; + } + + if(is_match ==0) + return; + + comm_rsp(slave_addr,frame_cmd, payload, payload_len); +} + + +void app_comm_entry(void *param) +{ + int len = 0; + + dev_rs485_init(); + + dev_rs485_rx_register(rs485_rx_cb); + + ring_buf_init(&g_comm.rb, g_comm.rb_pool, sizeof(g_comm.rb_pool)); + + /***/ + update_init(dev_rs485_send); + + while (1) { + + rt_thread_mdelay(1); + + len = recive_frame(); + + if (len == 0) { + + rt_thread_mdelay(5); + + len = recive_frame(); + + if (len == 0) { + + if (g_frame.rxbytes > 0) { + + update_process(g_frame.rxbuf, g_frame.rxbytes); + + comm_process(g_frame.rxbuf, g_frame.rxbytes); + + g_frame.rxbytes = 0; + } + } + } + } +} + + +ALIGN(RT_ALIGN_SIZE) +static uint8_t comm_thd_stack[4096]; +static struct rt_thread comm_thd; + +int app_comm_init(void) +{ + +#if USING_SIMULATOR + BSP_LOG("comm data using simulator \n"); +#endif + + int ret = rt_thread_init(&comm_thd, + "app_comm", + app_comm_entry, + RT_NULL, + comm_thd_stack, + sizeof(comm_thd_stack), + 10, + 20 + ); + + + if(ret == RT_EOK){ + + rt_thread_startup(&comm_thd); + } + + return 0; +} +INIT_APP_EXPORT(app_comm_init); + + diff --git a/Project/GateWay/source/User/Src/bsp.c b/Project/GateWay/source/User/Src/bsp.c new file mode 100644 index 0000000..1de06a4 --- /dev/null +++ b/Project/GateWay/source/User/Src/bsp.c @@ -0,0 +1,1812 @@ +#include +#include "bsp.h" +#include "rtthread.h" +#include "ff.h" + +#define SPI_MASTER_MODE + +//stc_sd_handle_t stcSdhandle; +static uint16_t m_au16Adc1SaValue; + +#if USE_SD_CARD +#include "sd_card.h" +/***************************************************************************************** + * MMC or SD + ****************************************************************************************/ +static stc_sdcard_init_t stcCardInitCfg; +static stc_sdcard_dma_init_t stcDmaInitCfg; +/***************************************************************************************** +* º¯ÊýÃû³Æ: SdioInit +* ¹¦ÄÜÃèÊö: Sdio³õʼ»¯º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +en_result_t SdioInit(void) +{ + en_result_t result; + + PORT_SetFunc(SDIOC_D0_PORT, SDIOC_D0_PIN, Func_Sdio, Disable); + PORT_SetFunc(SDIOC_D1_PORT, SDIOC_D1_PIN, Func_Sdio, Disable); + PORT_SetFunc(SDIOC_D2_PORT, SDIOC_D2_PIN, Func_Sdio, Disable); + PORT_SetFunc(SDIOC_D3_PORT, SDIOC_D3_PIN, Func_Sdio, Disable); + //PORT_SetFunc(SDIOC_CD_PORT, SDIOC_CD_PIN, Func_Sdio, Disable); + PORT_SetFunc(SDIOC_CK_PORT, SDIOC_CK_PIN, Func_Sdio, Disable); + PORT_SetFunc(SDIOC_CMD_PORT, SDIOC_CMD_PIN, Func_Sdio, Disable); + + stcCardInitCfg.enBusWidth = SdiocBusWidth4Bit; + stcCardInitCfg.enClkFreq = SdiocClk50M; + stcCardInitCfg.enSpeedMode = SdiocHighSpeedMode; + stcCardInitCfg.pstcInitCfg = NULL; + + stcDmaInitCfg.DMAx = M4_DMA2; + stcDmaInitCfg.enDmaCh = DmaCh1; + + stcSdhandle.SDIOCx = SDIOC_UNIT; + stcSdhandle.enDevMode = SdCardDmaMode; + stcSdhandle.pstcDmaInitCfg = &stcDmaInitCfg; + result = SDCARD_Init(&stcSdhandle, &stcCardInitCfg); + + return result; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: SDCardErase +* ¹¦ÄÜÃèÊö: SDCardÉÈÇø²Á³ýº¯Êý£¬×î´ó²Á³ýÉÈÇøÊý10 +* ²Î Êý: u32BlkStartAddr ÆðʼÉÈÇø + u32BlkEndAddr ½áÊøÉÈÇø +* ·µ »Ø Öµ: ²Ù×÷³É¹¦·µ»Øtrue£¬Ê§°Ü·µ»Øfalse +*****************************************************************************************/ +bool SDCardErase(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr) +{ + if(u32BlkEndAddr - u32BlkStartAddr > 10) + return false; + if(Ok != SDCARD_Erase(&stcSdhandle, u32BlkStartAddr, u32BlkEndAddr, 2000u)) { + return false; + } + return true; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: SDCardReadBlocks +* ¹¦ÄÜÃèÊö: SDCardÉÈÇø¶ÁÈ¡º¯Êý£¬×î´ó¶ÁÈ¡ÉÈÇøÊý10 +* ²Î Êý: u32BlkStartAddr ÆðʼÉÈÇø + u32BlkEndAddr ½áÊøÉÈÇø +* ·µ »Ø Öµ: ²Ù×÷³É¹¦·µ»Øtrue£¬Ê§°Ü·µ»Øfalse +*****************************************************************************************/ +bool SDCardReadBlocks(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr, uint8_t *ReadBuff) +{ + if(u32BlkEndAddr - u32BlkStartAddr > 10) + return false; + if (Ok != SDCARD_ReadBlocks(&stcSdhandle, u32BlkStartAddr, u32BlkEndAddr, ReadBuff, 2000u)) { + return false; + } + return true; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: SDCardWriteBlocks +* ¹¦ÄÜÃèÊö: SDCardÉÈÇøдÈ뺯Êý£¬×î´óдÈëÉÈÇøÊý10 +* ²Î Êý: u32BlkStartAddr ÆðʼÉÈÇø + u32BlkEndAddr ½áÊøÉÈÇø +* ·µ »Ø Öµ: ²Ù×÷³É¹¦·µ»Øtrue£¬Ê§°Ü·µ»Øfalse +*****************************************************************************************/ +bool SDCardWriteBlocks(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr, uint8_t *WriteBuff) +{ + if(u32BlkEndAddr - u32BlkStartAddr > 10) + return false; + if (Ok != SDCARD_WriteBlocks(&stcSdhandle, u32BlkStartAddr, u32BlkEndAddr, WriteBuff, 2000u)) { + return false; + } + return true; +} +#endif + +/***************************************************************************************** + * System Clock + ****************************************************************************************/ + +/***************************************************************************************** +* º¯ÊýÃû³Æ: SystemClockConfig +* ¹¦ÄÜÃèÊö: ϵͳʱÖÓÉèÖà +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void SystemClockConfig(void) +{ + stc_clk_sysclk_cfg_t stcSysClkCfg; + stc_clk_xtal_cfg_t stcXtalCfg; + stc_clk_mpll_cfg_t stcMpllCfg; + stc_sram_config_t stcSramConfig; + + MEM_ZERO_STRUCT(stcSysClkCfg); + MEM_ZERO_STRUCT(stcXtalCfg); + MEM_ZERO_STRUCT(stcMpllCfg); + MEM_ZERO_STRUCT(stcSramConfig); + + /* Set bus clk div. */ + stcSysClkCfg.enHclkDiv = ClkSysclkDiv1; + stcSysClkCfg.enExclkDiv = ClkSysclkDiv2; + stcSysClkCfg.enPclk0Div = ClkSysclkDiv1; + stcSysClkCfg.enPclk1Div = ClkSysclkDiv2; + stcSysClkCfg.enPclk2Div = ClkSysclkDiv4; + stcSysClkCfg.enPclk3Div = ClkSysclkDiv4; + stcSysClkCfg.enPclk4Div = ClkSysclkDiv2; + CLK_SysClkConfig(&stcSysClkCfg); + + /* Config Xtal and Enable Xtal */ + stcXtalCfg.enMode = ClkXtalModeOsc; + stcXtalCfg.enDrv = ClkXtalLowDrv; + stcXtalCfg.enFastStartup = Enable; + CLK_XtalConfig(&stcXtalCfg); + CLK_XtalCmd(Enable); + +// /* Config Hrc and enable HRC */ +// CLK_HrcTrim(SystemCoreClock); +// CLK_HrcCmd(Enable); + + /* sram init include read/write wait cycle setting */ + stcSramConfig.u8SramIdx = Sram12Idx | Sram3Idx | SramHsIdx | SramRetIdx; + stcSramConfig.enSramRC = SramCycle2; + stcSramConfig.enSramWC = SramCycle2; + SRAM_Init(&stcSramConfig); + + /* flash read wait cycle setting */ + EFM_Unlock(); + EFM_SetLatency(EFM_LATENCY_5); + EFM_Lock(); + + /* MPLL config (XTAL / pllmDiv * plln / PllpDiv = 200M). */ + stcMpllCfg.pllmDiv = 2ul; + stcMpllCfg.plln = 50ul; + stcMpllCfg.PllpDiv = 2ul; + stcMpllCfg.PllqDiv = 2ul; + stcMpllCfg.PllrDiv = 2ul; + CLK_SetPllSource(ClkPllSrcXTAL); + CLK_MpllConfig(&stcMpllCfg); + + /* Enable MPLL. */ + CLK_MpllCmd(Enable); + /* Wait MPLL ready. */ + while(Set != CLK_GetFlagStatus(ClkFlagMPLLRdy)) + { + ; + } + /* Switch driver ability */ + PWC_HS2HP(); + /* Switch system clock source to MPLL. */ + CLK_SetSysClkSource(CLKSysSrcMPLL); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: Xtal32_ClockConfig +* ¹¦ÄÜÃèÊö: ϵͳµÍËÙʱÖÓÅäÖà +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void Xtal32_ClockConfig(void) +{ + stc_clk_xtal32_cfg_t stcXtal32Cfg; + + /* configure structure initialization */ + MEM_ZERO_STRUCT(stcXtal32Cfg); + + /* Stop xtal32 */ + CLK_Xtal32Cmd(Disable); + Ddl_Delay1ms(100u); + /* Configuration xtal32 structure */ + stcXtal32Cfg.enDrv = ClkXtal32HighDrv; + stcXtal32Cfg.enFilterMode = ClkXtal32FilterModeFull; + CLK_Xtal32Config(&stcXtal32Cfg); + /* Startup xtal32 */ + CLK_Xtal32Cmd(Enable); + /* wait for xtal32 running */ + Ddl_Delay1ms(100u); +} + + +/***************************************************************************************** + * Debug Uart + ****************************************************************************************/ + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DbgUartRec +* ¹¦ÄÜÃèÊö: µ÷ÊÔ´®¿Ú½ÓÊÕº¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ·µ»ØÊÕµ½µÄ×Ö·û +*****************************************************************************************/ +static uint8_t DbgUartRec(void) +{ + uint16_t u16Data = USART_RecData(DBG_USART_CH); + return (uint8_t)u16Data; +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DBGUsartErrIrqCallback +* ¹¦ÄÜÃèÊö: µ÷ÊÔ´®¿Ú´íÎóÖжϻص÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void DBGUsartErrIrqCallback(void) +{ + if(DBG_USART_CH->SR_f.ORE) { + DBG_USART_CH->CR1_f.CORE = 1; + USART_RecData(DBG_USART_CH); + } + + if(DBG_USART_CH->SR_f.PE) + DBG_USART_CH->CR1_f.CPE = 1; + + if(DBG_USART_CH->SR_f.FE) + DBG_USART_CH->CR1_f.CFE = 1; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DbgUsartRxIrqCallback +* ¹¦ÄÜÃèÊö: µ÷ÊÔ´®¿Ú½ÓÊÕÖжϻص÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void DbgUsartRxIrqCallback(void) +{ + uint8_t rData = DbgUartRec(); + DbgRxIrqCallback(rData); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DbgUart_Config +* ¹¦ÄÜÃèÊö: µ÷ÊÔ´®¿ÚÅäÖú¯Êý +* ²Î Êý: BaudRate ´®¿Ú²¨ÌØÂÊ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DbgUart_Config(uint32_t BaudRate) +{ + stc_usart_uart_init_t stcInitCfg; + stc_irq_regi_conf_t stcIrqRegiCfg; + en_result_t enRet; + stc_port_init_t stcPortInit; + + MEM_ZERO_STRUCT(stcPortInit); + + stcPortInit.enPinOType = Pin_OType_Cmos; + PORT_Init(DBG_USART_RX_PORT, DBG_USART_RX_PIN, &stcPortInit); + PORT_Init(DBG_USART_TX_PORT, DBG_USART_TX_PIN, &stcPortInit); + + stcInitCfg.enClkMode = UsartIntClkCkNoOutput; + stcInitCfg.enClkDiv = UsartClkDiv_1; + stcInitCfg.enDataLength = UsartDataBits8; + stcInitCfg.enDirection = UsartDataLsbFirst; + stcInitCfg.enStopBit = UsartOneStopBit; + stcInitCfg.enParity = UsartParityNone; + stcInitCfg.enSampleMode = UsartSampleBit8; + stcInitCfg.enDetectMode = UsartStartBitFallEdge; + stcInitCfg.enHwFlow = UsartRtsEnable; + + PWC_Fcg1PeriphClockCmd(DBG_FCG1_PERIPH, Enable); + + PORT_SetFunc(DBG_USART_RX_PORT, DBG_USART_RX_PIN, DBG_USART_RX_FUNC, Disable); + PORT_SetFunc(DBG_USART_TX_PORT, DBG_USART_TX_PIN, DBG_USART_TX_FUNC, Disable); + + enRet = USART_UART_Init(DBG_USART_CH, &stcInitCfg); + if(enRet != Ok) { + Error_Handler(); + } + enRet = USART_SetBaudrate(DBG_USART_CH, BaudRate); + if(enRet != Ok) { + Error_Handler(); + } + + stcIrqRegiCfg.enIRQn = DBGUART_IRQn; + stcIrqRegiCfg.pfnCallback = &DbgUsartRxIrqCallback; + stcIrqRegiCfg.enIntSrc = DBG_USART_RI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + + + /* Set USART RX error IRQ */ + stcIrqRegiCfg.enIRQn = DBGUART_EI_IRQn; + stcIrqRegiCfg.pfnCallback = &DBGUsartErrIrqCallback; + stcIrqRegiCfg.enIntSrc = DBG_USART_EI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + +#if 0 + /* Set USART TX IRQ */ + stcIrqRegiCfg.enIRQn = Int002_IRQn; + stcIrqRegiCfg.pfnCallback = &UsartTxIrqCallback; + stcIrqRegiCfg.enIntSrc = USART_TI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + + /* Set USART TX complete IRQ */ + stcIrqRegiCfg.enIRQn = Int003_IRQn; + stcIrqRegiCfg.pfnCallback = &UsartTxCmpltIrqCallback; + stcIrqRegiCfg.enIntSrc = USART_TCI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); +#endif + USART_FuncCmd(DBG_USART_CH, UsartTx, Enable); + USART_FuncCmd(DBG_USART_CH, UsartRx, Enable); + USART_FuncCmd(DBG_USART_CH, UsartRxInt, Enable); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DebugUartSend +* ¹¦ÄÜÃèÊö: µ÷ÊÔ´®¿Ú·¢Ëͺ¯Êý +* ²Î Êý: sData ·¢ËÍÊý¾ÝÈë¿ÚÖ¸Õë + sLen ·¢ËÍÊý¾Ý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void DebugUartSend(uint8_t *sData, uint16_t sLen) +{ + for(int i = 0; i < sLen; i++) { + USART_SendData(DBG_USART_CH, sData[i]); + while(USART_GetStatus(DBG_USART_CH, UsartTxComplete) == Reset); + } +} + + +/***************************************************************************************** + * RS485Ch1 Uart + ****************************************************************************************/ + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1UartRec +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1´®¿Ú½ÓÊÕº¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ·µ»ØÊÕµ½µÄ×Ö·û +*****************************************************************************************/ +static uint8_t RS485Ch1UartRec(void) +{ + uint16_t u16Data = USART_RecData(RS485_CH1_USART_CH); + return (uint8_t)u16Data; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1UsartErrIrqCallback +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1´®¿Ú´íÎóÖжϻص÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void RS485Ch1UsartErrIrqCallback(void) +{ + if(RS485_CH1_USART_CH->SR_f.ORE) { + RS485_CH1_USART_CH->CR1_f.CORE = 1; + USART_RecData(RS485_CH1_USART_CH); + } + + if(RS485_CH1_USART_CH->SR_f.PE) + RS485_CH1_USART_CH->CR1_f.CPE = 1; + + if(RS485_CH1_USART_CH->SR_f.FE) + RS485_CH1_USART_CH->CR1_f.CFE = 1; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1UsartRxIrqCallback +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1´®¿Ú½ÓÊÕÖжϻص÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void RS485Ch1UsartRxIrqCallback(void) +{ + uint8_t rData = RS485Ch1UartRec(); + RS485Ch1RxIrqCallback(rData); +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1_Config +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1ÅäÖú¯Êý +* ²Î Êý: BaudRate ´®¿Ú²¨ÌØÂÊ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void RS485Ch1_Config(uint32_t BaudRate) +{ + stc_usart_uart_init_t stcInitCfg; + stc_irq_regi_conf_t stcIrqRegiCfg; + en_result_t enRet; + stc_port_init_t stcPortInit; + + MEM_ZERO_STRUCT(stcPortInit); + + stcPortInit.enPinOType = Pin_OType_Cmos; + PORT_Init(RS485_CH1_USART_RX_PORT, RS485_CH1_USART_RX_PIN, &stcPortInit); + PORT_Init(RS485_CH1_USART_TX_PORT, RS485_CH1_USART_TX_PIN, &stcPortInit); + + stcInitCfg.enClkMode = UsartIntClkCkNoOutput; + stcInitCfg.enClkDiv = UsartClkDiv_16; + stcInitCfg.enDataLength = UsartDataBits8; + stcInitCfg.enDirection = UsartDataLsbFirst; + stcInitCfg.enStopBit = UsartOneStopBit; + stcInitCfg.enParity = UsartParityNone; + stcInitCfg.enSampleMode = UsartSampleBit8; + stcInitCfg.enDetectMode = UsartStartBitFallEdge; + stcInitCfg.enHwFlow = UsartRtsEnable; + + PWC_Fcg1PeriphClockCmd(RS485_CH1_FCG1_PERIPH, Enable); + + PORT_SetFunc(RS485_CH1_USART_RX_PORT, RS485_CH1_USART_RX_PIN, RS485_CH1_USART_RX_FUNC, Disable); + PORT_SetFunc(RS485_CH1_USART_TX_PORT, RS485_CH1_USART_TX_PIN, RS485_CH1_USART_TX_FUNC, Disable); + + enRet = USART_UART_Init(RS485_CH1_USART_CH, &stcInitCfg); + if(enRet != Ok) { + Error_Handler(); + } + enRet = USART_SetBaudrate(RS485_CH1_USART_CH, BaudRate); + if(enRet != Ok) { + Error_Handler(); + } + + stcIrqRegiCfg.enIRQn = RS485CH1_UART_IRQn; + stcIrqRegiCfg.pfnCallback = &RS485Ch1UsartRxIrqCallback; + stcIrqRegiCfg.enIntSrc = RS485_CH1_USART_RI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + + + /* Set USART RX error IRQ */ + stcIrqRegiCfg.enIRQn = RS485CH1_UART_EI_IRQn; + stcIrqRegiCfg.pfnCallback = &RS485Ch1UsartErrIrqCallback; + stcIrqRegiCfg.enIntSrc = RS485_CH1_USART_EI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + +#if 0 + /* Set USART TX IRQ */ + stcIrqRegiCfg.enIRQn = Int002_IRQn; + stcIrqRegiCfg.pfnCallback = &UsartTxIrqCallback; + stcIrqRegiCfg.enIntSrc = USART_TI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + + /* Set USART TX complete IRQ */ + stcIrqRegiCfg.enIRQn = Int003_IRQn; + stcIrqRegiCfg.pfnCallback = &UsartTxCmpltIrqCallback; + stcIrqRegiCfg.enIntSrc = USART_TCI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); +#endif + USART_FuncCmd(RS485_CH1_USART_CH, UsartTx, Enable); + USART_FuncCmd(RS485_CH1_USART_CH, UsartRx, Enable); + USART_FuncCmd(RS485_CH1_USART_CH, UsartRxInt, Enable); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1UartSend +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1´®¿Ú·¢Ëͺ¯Êý +* ²Î Êý: sData ·¢ËÍÊý¾ÝÈë¿ÚÖ¸Õë + sLen ·¢ËÍÊý¾Ý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void RS485Ch1UartSend(uint8_t *sData, uint16_t sLen) +{ + RS485_CH1_TX(); + for(int i = 0; i < sLen; i++) { + USART_SendData(RS485_CH1_USART_CH, sData[i]); + while(USART_GetStatus(RS485_CH1_USART_CH, UsartTxComplete) == Reset); + } + RS485_CH1_RX(); +} + +/***************************************************************************************** + * RS485Ch2 Uart + ****************************************************************************************/ + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1UartRec +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1´®¿Ú½ÓÊÕº¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ·µ»ØÊÕµ½µÄ×Ö·û +*****************************************************************************************/ +static uint8_t RS485Ch2UartRec(void) +{ + uint16_t u16Data = USART_RecData(RS485_CH2_USART_CH); + return (uint8_t)u16Data; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1UsartErrIrqCallback +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1´®¿Ú´íÎóÖжϻص÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void RS485Ch2UsartErrIrqCallback(void) +{ + if(RS485_CH2_USART_CH->SR_f.ORE) { + RS485_CH2_USART_CH->CR1_f.CORE = 1; + USART_RecData(RS485_CH2_USART_CH); + } + + if(RS485_CH2_USART_CH->SR_f.PE) + RS485_CH2_USART_CH->CR1_f.CPE = 1; + + if(RS485_CH2_USART_CH->SR_f.FE) + RS485_CH2_USART_CH->CR1_f.CFE = 1; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1UsartRxIrqCallback +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1´®¿Ú½ÓÊÕÖжϻص÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void RS485Ch2UsartRxIrqCallback(void) +{ + uint8_t rData = RS485Ch2UartRec(); + RS485Ch2RxIrqCallback(rData); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1_Config +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1ÅäÖú¯Êý +* ²Î Êý: BaudRate ´®¿Ú²¨ÌØÂÊ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void RS485Ch2_Config(uint32_t BaudRate) +{ + stc_usart_uart_init_t stcInitCfg; + stc_irq_regi_conf_t stcIrqRegiCfg; + en_result_t enRet; + stc_port_init_t stcPortInit; + + MEM_ZERO_STRUCT(stcPortInit); + + stcPortInit.enPinOType = Pin_OType_Cmos; + PORT_Init(RS485_CH2_USART_RX_PORT, RS485_CH2_USART_RX_PIN, &stcPortInit); + PORT_Init(RS485_CH2_USART_TX_PORT, RS485_CH2_USART_TX_PIN, &stcPortInit); + + stcInitCfg.enClkMode = UsartIntClkCkNoOutput; + stcInitCfg.enClkDiv = UsartClkDiv_16; + stcInitCfg.enDataLength = UsartDataBits8; + stcInitCfg.enDirection = UsartDataLsbFirst; + stcInitCfg.enStopBit = UsartOneStopBit; + stcInitCfg.enParity = UsartParityNone; + stcInitCfg.enSampleMode = UsartSampleBit8; + stcInitCfg.enDetectMode = UsartStartBitFallEdge; + stcInitCfg.enHwFlow = UsartRtsEnable; + + PWC_Fcg1PeriphClockCmd(RS485_CH2_FCG1_PERIPH, Enable); + + PORT_SetFunc(RS485_CH2_USART_RX_PORT, RS485_CH2_USART_RX_PIN, RS485_CH2_USART_RX_FUNC, Disable); + PORT_SetFunc(RS485_CH2_USART_TX_PORT, RS485_CH2_USART_TX_PIN, RS485_CH2_USART_TX_FUNC, Disable); + + enRet = USART_UART_Init(RS485_CH2_USART_CH, &stcInitCfg); + if(enRet != Ok) { + Error_Handler(); + } + enRet = USART_SetBaudrate(RS485_CH2_USART_CH, BaudRate); + if(enRet != Ok) { + Error_Handler(); + } + + stcIrqRegiCfg.enIRQn = RS485CH2_UART_IRQn; + stcIrqRegiCfg.pfnCallback = &RS485Ch2UsartRxIrqCallback; + stcIrqRegiCfg.enIntSrc = RS485_CH2_USART_RI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + + + /* Set USART RX error IRQ */ + stcIrqRegiCfg.enIRQn = RS485CH2_UART_EI_IRQn; + stcIrqRegiCfg.pfnCallback = &RS485Ch2UsartErrIrqCallback; + stcIrqRegiCfg.enIntSrc = RS485_CH2_USART_EI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + +#if 0 + /* Set USART TX IRQ */ + stcIrqRegiCfg.enIRQn = Int002_IRQn; + stcIrqRegiCfg.pfnCallback = &UsartTxIrqCallback; + stcIrqRegiCfg.enIntSrc = USART_TI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + + /* Set USART TX complete IRQ */ + stcIrqRegiCfg.enIRQn = Int003_IRQn; + stcIrqRegiCfg.pfnCallback = &UsartTxCmpltIrqCallback; + stcIrqRegiCfg.enIntSrc = USART_TCI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); +#endif + USART_FuncCmd(RS485_CH2_USART_CH, UsartTx, Enable); + USART_FuncCmd(RS485_CH2_USART_CH, UsartRx, Enable); + USART_FuncCmd(RS485_CH2_USART_CH, UsartRxInt, Enable); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1UartSend +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1´®¿Ú·¢Ëͺ¯Êý +* ²Î Êý: sData ·¢ËÍÊý¾ÝÈë¿ÚÖ¸Õë + sLen ·¢ËÍÊý¾Ý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void RS485Ch2UartSend(uint8_t *sData, uint16_t sLen) +{ + RS485_CH2_TX(); + for(int i = 0; i < sLen; i++) { + USART_SendData(RS485_CH2_USART_CH, sData[i]); + while(USART_GetStatus(RS485_CH2_USART_CH, UsartTxComplete) == Reset); + } + RS485_CH2_RX(); +} + + + +/***************************************************************************************** + * Eth Or Cat1 Uart + ****************************************************************************************/ + +/***************************************************************************************** +* º¯ÊýÃû³Æ: EthOrCat1UartRec +* ¹¦ÄÜÃèÊö: cat1ºÍeth´®¿Ú½ÓÊÕº¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ·µ»ØÊÕµ½µÄ×Ö·û +*****************************************************************************************/ +static uint8_t EthOrCat1UartRec(void) +{ + uint16_t u16Data = USART_RecData(ETH_OR_CAT1_USART_CH); + return (uint8_t)u16Data; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1UsartErrIrqCallback +* ¹¦ÄÜÃèÊö: cat1ºÍeth´®¿Ú´íÎóÖжϻص÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void EthOrCat1UsartErrIrqCallback(void) +{ + if(ETH_OR_CAT1_USART_CH->SR_f.ORE) { + ETH_OR_CAT1_USART_CH->CR1_f.CORE = 1; + USART_RecData(ETH_OR_CAT1_USART_CH); + } + + if(ETH_OR_CAT1_USART_CH->SR_f.PE) + ETH_OR_CAT1_USART_CH->CR1_f.CPE = 1; + + if(ETH_OR_CAT1_USART_CH->SR_f.FE) + ETH_OR_CAT1_USART_CH->CR1_f.CFE = 1; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1UsartRxIrqCallback +* ¹¦ÄÜÃèÊö: cat1ºÍeth´®¿Ú½ÓÊÕÖжϻص÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void EthOrCat1UsartRxIrqCallback(void) +{ + uint8_t rData =EthOrCat1UartRec(); + EthOrCat1RxIrqCallback(rData); +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1_Config +* ¹¦ÄÜÃèÊö: cat1ºÍeth´®¿ÚÅäÖú¯Êý +* ²Î Êý: BaudRate ´®¿Ú²¨ÌØÂÊ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void EthOrCat1_Config(uint32_t BaudRate) +{ + stc_usart_uart_init_t stcInitCfg; + stc_irq_regi_conf_t stcIrqRegiCfg; + en_result_t enRet; + stc_port_init_t stcPortInit; + + MEM_ZERO_STRUCT(stcPortInit); + + stcPortInit.enPinOType = Pin_OType_Cmos; + PORT_Init(ETH_OR_CAT1_USART_RX_PORT, ETH_OR_CAT1_USART_RX_PIN, &stcPortInit); + PORT_Init(ETH_OR_CAT1_USART_TX_PORT, ETH_OR_CAT1_USART_TX_PIN, &stcPortInit); + + stcInitCfg.enClkMode = UsartIntClkCkNoOutput; + stcInitCfg.enClkDiv = UsartClkDiv_1; + stcInitCfg.enDataLength = UsartDataBits8; + stcInitCfg.enDirection = UsartDataLsbFirst; + stcInitCfg.enStopBit = UsartOneStopBit; + stcInitCfg.enParity = UsartParityNone; + stcInitCfg.enSampleMode = UsartSampleBit8; + stcInitCfg.enDetectMode = UsartStartBitFallEdge; + stcInitCfg.enHwFlow = UsartRtsEnable; + + PWC_Fcg1PeriphClockCmd(ETH_OR_CAT1_FCG1_PERIPH, Enable); + + PORT_SetFunc(ETH_OR_CAT1_USART_RX_PORT, ETH_OR_CAT1_USART_RX_PIN, ETH_OR_CAT1_USART_RX_FUNC, Disable); + PORT_SetFunc(ETH_OR_CAT1_USART_TX_PORT, ETH_OR_CAT1_USART_TX_PIN, ETH_OR_CAT1_USART_TX_FUNC, Disable); + + enRet = USART_UART_Init(ETH_OR_CAT1_USART_CH, &stcInitCfg); + if(enRet != Ok) { + Error_Handler(); + } + enRet = USART_SetBaudrate(ETH_OR_CAT1_USART_CH, BaudRate); + if(enRet != Ok) { + Error_Handler(); + } + + stcIrqRegiCfg.enIRQn = ETH_OR_CAT1_UART_IRQn; + stcIrqRegiCfg.pfnCallback = &EthOrCat1UsartRxIrqCallback; + stcIrqRegiCfg.enIntSrc = ETH_OR_CAT1_USART_RI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + + + /* Set USART RX error IRQ */ + stcIrqRegiCfg.enIRQn = ETH_OR_CAT1_UART_EI_IRQn; + stcIrqRegiCfg.pfnCallback = &EthOrCat1UsartErrIrqCallback; + stcIrqRegiCfg.enIntSrc = ETH_OR_CAT1_USART_EI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + +#if 0 + /* Set USART TX IRQ */ + stcIrqRegiCfg.enIRQn = Int002_IRQn; + stcIrqRegiCfg.pfnCallback = &UsartTxIrqCallback; + stcIrqRegiCfg.enIntSrc = USART_TI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); + + /* Set USART TX complete IRQ */ + stcIrqRegiCfg.enIRQn = Int003_IRQn; + stcIrqRegiCfg.pfnCallback = &UsartTxCmpltIrqCallback; + stcIrqRegiCfg.enIntSrc = USART_TCI_NUM; + enIrqRegistration(&stcIrqRegiCfg); + NVIC_SetPriority(stcIrqRegiCfg.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(stcIrqRegiCfg.enIRQn); + NVIC_EnableIRQ(stcIrqRegiCfg.enIRQn); +#endif + USART_FuncCmd(ETH_OR_CAT1_USART_CH, UsartTx, Enable); + USART_FuncCmd(ETH_OR_CAT1_USART_CH, UsartRx, Enable); + USART_FuncCmd(ETH_OR_CAT1_USART_CH, UsartRxInt, Enable); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: EthOrCat1UartSend +* ¹¦ÄÜÃèÊö: cat1ºÍeth´®¿Ú·¢Ëͺ¯Êý +* ²Î Êý: sData ·¢ËÍÊý¾ÝÈë¿ÚÖ¸Õë + sLen ·¢ËÍÊý¾Ý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void EthOrCat1UartSend(uint8_t *sData, uint16_t sLen) +{ + for(int i = 0; i < sLen; i++) { + USART_SendData(ETH_OR_CAT1_USART_CH, sData[i]); + while(USART_GetStatus(ETH_OR_CAT1_USART_CH, UsartTxComplete) == Reset); + } +} + + + +/***************************************************************************************** + * GPIO + ****************************************************************************************/ + +/***************************************************************************************** +* º¯ÊýÃû³Æ: LoraDio0IrqCallback +* ¹¦ÄÜÃèÊö: LORA DIO0Öжϻص÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void LoraDio0IrqCallback(void) +{ + EXINT_IrqFlgClr(LORA_DIO_EXIT_CH); + LoraTxRxIrqCallback(); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: GPIO_Config +* ¹¦ÄÜÃèÊö: GPIOÅäÖú¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void GPIO_Config(void) +{ + stc_port_init_t stcPortInit; + stc_port_pub_set_t stcPortPub; + stc_exint_config_t stcExtiConfig; + stc_irq_regi_conf_t stcIrqRegiConf; + + PORT_DebugPortSetting(TDO_SWO, Disable); + PORT_DebugPortSetting(TDI, Disable); + PORT_DebugPortSetting(TRST, Disable); + + MEM_ZERO_STRUCT(stcPortInit); + MEM_ZERO_STRUCT(stcPortPub); + + stcPortPub.enReadWait = WaitCycle3; + PORT_PubSetting(&stcPortPub); + + stcPortInit.enPinMode = Pin_Mode_Out; + stcPortInit.enPinOType = Pin_OType_Cmos; + stcPortInit.enPinDrv = Pin_Drv_H; + stcPortInit.enPullUp = Disable; + PORT_Init(RS485_CH1_CTRL_PORT, RS485_CH1_CTRL_PIN, &stcPortInit); + RS485_CH1_RX(); + + PORT_Init(RS485_CH1_POW_PORT, RS485_CH1_POW_PIN, &stcPortInit); + RS485_CH1_POW_OFF(); + +// PORT_Init(RS485_CH1_VOL_CTRL_PORT, RS485_CH1_VOL_CTRL_PIN, &stcPortInit); +// RS485_CH1_VOL_5V(); + + PORT_Init(RS485_CH2_CTRL_PORT, RS485_CH2_CTRL_PIN, &stcPortInit); + RS485_CH2_RX(); + + PORT_Init(RS485_CH2_POW_PORT, RS485_CH2_POW_PIN, &stcPortInit); + RS485_CH2_POW_OFF(); + +// PORT_Init(RS485_CH2_VOL_CTRL_PORT, RS485_CH2_VOL_CTRL_PIN, &stcPortInit); +// RS485_CH1_VOL_5V(); + + PORT_Init(ETH_OR_CAT1_CTRL_PORT, ETH_OR_CAT1_CTRL_PIN, &stcPortInit); +// PORT_Init(ETH_OR_CAT1_TX_CTRL_PORT, ETH_OR_CAT1_TX_CTRL_PIN, &stcPortInit); + ETH_ON(); + + PORT_Init(CAT1_PWR_KEY_PORT, CAT1_PWR_KEY_PIN, &stcPortInit); + CAT1_PWR_KEY_SET(); + + PORT_Init(CAT1_RESET_PORT, CAT1_RESET_PIN, &stcPortInit); + CAT1_RESET_CLR(); + +// PORT_Init(CAT1_POW_PORT, CAT1_POW_PIN, &stcPortInit); +// CAT1_POW_OFF(); + + PORT_Init(ETH_RESET_PORT, ETH_RESET_PIN, &stcPortInit); + ETH_RESET_CLR(); + + PORT_Init(ETH_DEF_PORT, ETH_DEF_PIN, &stcPortInit); + ETH_DEF_SET(); + +// PORT_Init(SPI_NSS_PORT, SPI_NSS_PIN, &stcPortInit); +// SPI_NSS_SET(); + +// PORT_Init(SPI2_NSS_PORT, SPI2_NSS_PIN, &stcPortInit); +// SPI2_NSS_SET(); + + PORT_Init(LORA_RESET_PORT, LORA_RESET_PIN, &stcPortInit); + LORA_RESET_SET(); + + PORT_Init(LORA_RXEN_PORT, LORA_RXEN_PIN, &stcPortInit); + LORA_RXEN_SET(); + + PORT_Init(LORA_TXEN_PORT, LORA_TXEN_PIN, &stcPortInit); + LORA_TXEN_CLR(); + + PORT_Init(POWER_LED_PORT, POWER_LED_PIN, &stcPortInit); + POWER_LED_OFF(); + + PORT_Init(LORA_RX_LED_PORT, LORA_RX_LED_PIN, &stcPortInit); + LORA_RX_LED_CLR(); + + PORT_Init(LORA_POW_PORT, LORA_POW_PIN, &stcPortInit); + LORA_POW_OFF(); + + stcPortInit.enPinMode = Pin_Mode_In; + PORT_Init(ETH_LINK_PORT, ETH_LINK_PIN, &stcPortInit); + + stcPortInit.enExInt = Enable; + stcPortInit.enPullUp = Enable; + PORT_Init(LORA_DIO_PORT, LORA_DIO_PIN, &stcPortInit); + + stcExtiConfig.enExitCh = LORA_DIO_EXIT_CH; + stcExtiConfig.enFilterEn = Enable; + stcExtiConfig.enFltClk = Pclk3Div8; + stcExtiConfig.enExtiLvl = ExIntRisingEdge; + EXINT_Init(&stcExtiConfig); + + stcIrqRegiConf.enIntSrc = LORA_DIO_EXIT_SRC; /* Select External Int Ch.1 */ + stcIrqRegiConf.enIRQn = LORA_DIO0_IRQn; /* Register External Int to Vect.No.000 */ + stcIrqRegiConf.pfnCallback = &LoraDio0IrqCallback; /* Callback function */ + enIrqRegistration(&stcIrqRegiConf); /* Registration IRQ */ + NVIC_ClearPendingIRQ(stcIrqRegiConf.enIRQn); /* Clear pending */ + NVIC_SetPriority(stcIrqRegiConf.enIRQn, DDL_IRQ_PRIORITY_00); /* Set priority */ + NVIC_EnableIRQ(stcIrqRegiConf.enIRQn); /* Enable NVIC */ + //enIntWakeupEnable(Extint2WU); +} + + +/***************************************************************************************** + * SPI1 spiflash + ****************************************************************************************/ + +/***************************************************************************************** +* º¯ÊýÃû³Æ: Spi1_Config +* ¹¦ÄÜÃèÊö: SPI1ÅäÖú¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void Spi1_Config(void) +{ + stc_spi_init_t stcSpiInit; + stc_port_init_t stcPortInit; + + MEM_ZERO_STRUCT(stcPortInit); + + stcPortInit.enPinOType = Pin_OType_Cmos; + PORT_Init(SPI_SCK_PORT, SPI_SCK_PIN, &stcPortInit); + PORT_Init(SPI_MOSI_PORT, SPI_MOSI_PIN, &stcPortInit); + PORT_Init(SPI_MISO_PORT, SPI_MISO_PIN, &stcPortInit); + stcPortInit.enPinMode = Pin_Mode_Out; + stcPortInit.enPinOType = Pin_OType_Cmos; + stcPortInit.enPinDrv = Pin_Drv_H; + stcPortInit.enPullUp = Disable; + PORT_Init(SPI_NSS_PORT, SPI_NSS_PIN, &stcPortInit); + SPI_NSS_SET(); + /* configuration structure initialization */ + MEM_ZERO_STRUCT(stcSpiInit); + + /* Configuration peripheral clock */ + PWC_Fcg1PeriphClockCmd(SPI_UNIT_CLOCK, Enable); + + /* Configuration SPI pin */ + PORT_SetFunc(SPI_SCK_PORT, SPI_SCK_PIN, SPI_SCK_FUNC, Disable); + PORT_SetFunc(SPI_MOSI_PORT, SPI_MOSI_PIN, SPI_MOSI_FUNC, Disable); + PORT_SetFunc(SPI_MISO_PORT, SPI_MISO_PIN, SPI_MISO_FUNC, Disable); + + /* Configuration SPI structure */ + stcSpiInit.enClkDiv = SpiClkDiv16; + stcSpiInit.enFrameNumber = SpiFrameNumber1; + stcSpiInit.enDataLength = SpiDataLengthBit8; + stcSpiInit.enFirstBitPosition = SpiFirstBitPositionMSB; + stcSpiInit.enSckPolarity = SpiSckIdleLevelHigh; + stcSpiInit.enSckPhase = SpiSckOddChangeEvenSample; + stcSpiInit.enReadBufferObject = SpiReadReceiverBuffer; + stcSpiInit.enWorkMode = SpiWorkMode4Line; + stcSpiInit.enTransMode = SpiTransFullDuplex; + stcSpiInit.enCommAutoSuspendEn = Disable; + stcSpiInit.enModeFaultErrorDetectEn = Disable; + stcSpiInit.enParitySelfDetectEn = Disable; + stcSpiInit.enParityEn = Disable; + stcSpiInit.enParity = SpiParityEven; + +#ifdef SPI_MASTER_MODE + stcSpiInit.enMasterSlaveMode = SpiModeMaster; + stcSpiInit.stcDelayConfig.enSsSetupDelayOption = SpiSsSetupDelayCustomValue; + stcSpiInit.stcDelayConfig.enSsSetupDelayTime = SpiSsSetupDelaySck1; + stcSpiInit.stcDelayConfig.enSsHoldDelayOption = SpiSsHoldDelayCustomValue; + stcSpiInit.stcDelayConfig.enSsHoldDelayTime = SpiSsHoldDelaySck1; + stcSpiInit.stcDelayConfig.enSsIntervalTimeOption = SpiSsIntervalCustomValue; + stcSpiInit.stcDelayConfig.enSsIntervalTime = SpiSsIntervalSck6PlusPck2; + stcSpiInit.stcSsConfig.enSsValidBit = SpiSsValidChannel0; + stcSpiInit.stcSsConfig.enSs0Polarity = SpiSsLowValid; +#endif + +#ifdef SPI_SLAVE_MODE + stcSpiInit.enMasterSlaveMode = SpiModeSlave; + stcSpiInit.stcSsConfig.enSsValidBit = SpiSsValidChannel0; + stcSpiInit.stcSsConfig.enSs0Polarity = SpiSsLowValid; +#endif + + SPI_Init(SPI_UNIT, &stcSpiInit); + SPI_Cmd(SPI_UNIT, Enable); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: Spi1SendReceive +* ¹¦ÄÜÃèÊö: SPI1·¢ËͽÓÊÕº¯Êý +* ²Î Êý: sData ·¢Ë͵ÄÊý¾ÝÈë¿âŶ +* ·µ »Ø Öµ: ½ÓÊÕµ½µÄÊý¾Ý +*****************************************************************************************/ +uint16_t Spi1SendReceive(uint16_t sData) +{ + uint16_t retry = 0; + uint16_t rData; + + /* Wait tx buffer empty */ + while (Reset == SPI_GetFlag(SPI_UNIT, SpiFlagSendBufferEmpty)) { + retry++; + if(retry > 0x4000) + return 0; + } + + /* Send data */ + SPI_SendData8(SPI_UNIT, sData); + + /* Wait rx buffer full */ + retry = 0; + while (Reset == SPI_GetFlag(SPI_UNIT, SpiFlagReceiveBufferFull)) { + retry++; + if(retry > 0x4000) + return 0; + } + /* Receive data */ + rData = SPI_ReceiveData8(SPI_UNIT); + + return rData; +} + + +/***************************************************************************************** + * SPI2 spiflash + ****************************************************************************************/ + +/***************************************************************************************** +* º¯ÊýÃû³Æ: Spi2_Config +* ¹¦ÄÜÃèÊö: SPI2ÅäÖú¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void Spi2_Config(void) +{ + stc_spi_init_t stcSpiInit; + stc_port_init_t stcPortInit; + + MEM_ZERO_STRUCT(stcPortInit); + + stcPortInit.enPinOType = Pin_OType_Cmos; + PORT_Init(SPI2_SCK_PORT, SPI2_SCK_PIN, &stcPortInit); + PORT_Init(SPI2_MOSI_PORT, SPI2_MOSI_PIN, &stcPortInit); + PORT_Init(SPI2_MISO_PORT, SPI2_MISO_PIN, &stcPortInit); + //PORT_Init(SPI2_NSS_PORT, SPI2_NSS_PIN, &stcPortInit); + stcPortInit.enPinMode = Pin_Mode_Out; + stcPortInit.enPinOType = Pin_OType_Cmos; + stcPortInit.enPinDrv = Pin_Drv_H; + stcPortInit.enPullUp = Disable; + PORT_Init(SPI2_NSS_PORT, SPI2_NSS_PIN, &stcPortInit); + SPI2_NSS_SET(); + /* configuration structure initialization */ + MEM_ZERO_STRUCT(stcSpiInit); + + /* Configuration peripheral clock */ + PWC_Fcg1PeriphClockCmd(SPI2_UNIT_CLOCK, Enable); + + /* Configuration SPI pin */ + PORT_SetFunc(SPI2_SCK_PORT, SPI2_SCK_PIN, SPI2_SCK_FUNC, Disable); + PORT_SetFunc(SPI2_MOSI_PORT, SPI2_MOSI_PIN, SPI2_MOSI_FUNC, Disable); + PORT_SetFunc(SPI2_MISO_PORT, SPI2_MISO_PIN, SPI2_MISO_FUNC, Disable); + //PORT_SetFunc(SPI2_NSS_PORT, SPI2_NSS_PIN, SPI2_NSS_FUNC, Disable); + + /* Configuration SPI structure */ + stcSpiInit.enClkDiv = SpiClkDiv16; + stcSpiInit.enFrameNumber = SpiFrameNumber1; + stcSpiInit.enDataLength = SpiDataLengthBit8; + stcSpiInit.enFirstBitPosition = SpiFirstBitPositionMSB; + stcSpiInit.enSckPolarity = SpiSckIdleLevelHigh; + stcSpiInit.enSckPhase = SpiSckOddChangeEvenSample; + stcSpiInit.enReadBufferObject = SpiReadReceiverBuffer; + stcSpiInit.enWorkMode = SpiWorkMode4Line; + stcSpiInit.enTransMode = SpiTransFullDuplex; + stcSpiInit.enCommAutoSuspendEn = Disable; + stcSpiInit.enModeFaultErrorDetectEn = Disable; + stcSpiInit.enParitySelfDetectEn = Disable; + stcSpiInit.enParityEn = Disable; + stcSpiInit.enParity = SpiParityEven; + +#ifdef SPI_MASTER_MODE + stcSpiInit.enMasterSlaveMode = SpiModeMaster; + stcSpiInit.stcDelayConfig.enSsSetupDelayOption = SpiSsSetupDelayCustomValue; + stcSpiInit.stcDelayConfig.enSsSetupDelayTime = SpiSsSetupDelaySck1; + stcSpiInit.stcDelayConfig.enSsHoldDelayOption = SpiSsHoldDelayCustomValue; + stcSpiInit.stcDelayConfig.enSsHoldDelayTime = SpiSsHoldDelaySck1; + stcSpiInit.stcDelayConfig.enSsIntervalTimeOption = SpiSsIntervalCustomValue; + stcSpiInit.stcDelayConfig.enSsIntervalTime = SpiSsIntervalSck8PlusPck2; + stcSpiInit.stcSsConfig.enSsValidBit = SpiSsValidChannel0; + stcSpiInit.stcSsConfig.enSs0Polarity = SpiSsLowValid; +#endif + +#ifdef SPI_SLAVE_MODE + stcSpiInit.enMasterSlaveMode = SpiModeSlave; + stcSpiInit.stcSsConfig.enSsValidBit = SpiSsValidChannel0; + stcSpiInit.stcSsConfig.enSs0Polarity = SpiSsLowValid; +#endif + + SPI_Init(SPI2_UNIT, &stcSpiInit); + SPI_Cmd(SPI2_UNIT, Enable); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: Spi2SendReceive +* ¹¦ÄÜÃèÊö: SPI2·¢ËͽÓÊÕº¯Êý +* ²Î Êý: sData ·¢Ë͵ÄÊý¾ÝÈë¿âŶ +* ·µ »Ø Öµ: ½ÓÊÕµ½µÄÊý¾Ý +*****************************************************************************************/ +uint16_t Spi2SendReceive(uint16_t sData) +{ + uint16_t retry = 0; + uint16_t rData; + + /* Wait tx buffer empty */ + while (Reset == SPI_GetFlag(SPI2_UNIT, SpiFlagSendBufferEmpty)) { + retry++; + if(retry > 0x4000) + return 0; + } + + /* Send data */ + SPI_SendData8(SPI2_UNIT, sData); + + /* Wait rx buffer full */ + retry = 0; + while (Reset == SPI_GetFlag(SPI2_UNIT, SpiFlagReceiveBufferFull)) { + retry++; + if(retry > 0x4000) + return 0; + } + /* Receive data */ + rData = SPI_ReceiveData8(SPI2_UNIT); + + return rData; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: Rtc_Config +* ¹¦ÄÜÃèÊö: RTCÅäÖà +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void Rtc_Config(void) +{ + stc_rtc_init_t stcRtcInit; + stc_irq_regi_conf_t stcIrqRegiConf; + + /* configuration structure initialization */ + MEM_ZERO_STRUCT(stcRtcInit); + MEM_ZERO_STRUCT(stcIrqRegiConf); + + /* Reset rtc counter */ + if (RTC_DeInit() == ErrorTimeout) { + //DBG_LOG("Reset RTC Failed!\r\n"); + } + else { + /* Configuration rtc structure */ + stcRtcInit.enClkSource = RtcClkXtal32; + stcRtcInit.enPeriodInt = RtcPeriodIntInvalid; + stcRtcInit.enTimeFormat = RtcTimeFormat24Hour; + stcRtcInit.enCompenWay = RtcOutputCompenDistributed; + stcRtcInit.enCompenEn = Disable; + stcRtcInit.u16CompenVal = 0u; + RTC_Init(&stcRtcInit); + +// /* Configure interrupt of rtc period */ +// stcIrqRegiConf.enIntSrc = INT_RTC_PRD; +// stcIrqRegiConf.enIRQn = RTC_IRQn; +// stcIrqRegiConf.pfnCallback = &RtcPeriod_IrqCallback; +// enIrqRegistration(&stcIrqRegiConf); +// NVIC_ClearPendingIRQ(stcIrqRegiConf.enIRQn); +// NVIC_SetPriority(stcIrqRegiConf.enIRQn, DDL_IRQ_PRIORITY_DEFAULT); +// NVIC_EnableIRQ(stcIrqRegiConf.enIRQn); +// enIntWakeupEnable(RtcPeriodWU); +// /* Enable period interrupt */ +// RTC_IrqCmd(RtcIrqPeriod, Enable); + /* Startup rtc count */ + RTC_Cmd(Enable); + } +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: AdcInitConfig +* ¹¦ÄÜÃèÊö: ADC³õʼ»¯ÅäÖà +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void AdcInitConfig(void) +{ + stc_adc_init_t stcAdcInit; + + MEM_ZERO_STRUCT(stcAdcInit); + + stcAdcInit.enResolution = AdcResolution_12Bit; + stcAdcInit.enDataAlign = AdcDataAlign_Right; + stcAdcInit.enAutoClear = AdcClren_Enable; + stcAdcInit.enScanMode = AdcMode_SAOnce; + stcAdcInit.enRschsel = AdcRschsel_Restart; + /* 1. Enable ADC1. */ + PWC_Fcg3PeriphClockCmd(PWC_FCG3_PERIPH_ADC1, Enable); + /* 2. Initialize ADC1. */ + ADC_Init(M4_ADC1, &stcAdcInit); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: AdcSetChannelPinMode +* ¹¦ÄÜÃèÊö: ADCͨµÀÒý½ÅÅäÖà +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void AdcSetChannelPinMode(uint32_t u32Channel) +{ + en_port_t enPort; + en_pin_t enPin; + stc_port_init_t stcPortInit; + + MEM_ZERO_STRUCT(stcPortInit); + stcPortInit.enPinMode = Pin_Mode_Ana; + stcPortInit.enPullUp = Disable; + + switch (u32Channel) { + case ADC1_CH0: enPort = PortA; enPin = Pin00; break; + case ADC1_CH1: enPort = PortA; enPin = Pin01; break; + case ADC1_CH2: enPort = PortA; enPin = Pin02; break; + case ADC1_CH3: enPort = PortA; enPin = Pin03; break; + case ADC1_CH4: enPort = PortA; enPin = Pin04; break; + case ADC1_CH5: enPort = PortA; enPin = Pin05; break; + case ADC1_CH6: enPort = PortA; enPin = Pin06; break; + case ADC1_CH7: enPort = PortA; enPin = Pin07; break; + case ADC1_CH8: enPort = PortB; enPin = Pin00; break; + case ADC1_CH9: enPort = PortB; enPin = Pin01; break; + case ADC1_CH10: enPort = PortC; enPin = Pin00; break; + case ADC1_CH11: enPort = PortC; enPin = Pin01; break; + case ADC1_CH12: enPort = PortC; enPin = Pin02; break; + case ADC1_CH13: enPort = PortC; enPin = Pin03; break; + case ADC1_CH14: enPort = PortC; enPin = Pin04; break; + case ADC1_CH15: enPort = PortC; enPin = Pin05; break; + default: + return; + } + PORT_Init(enPort, enPin, &stcPortInit); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: AdcChannelConfig +* ¹¦ÄÜÃèÊö: ADCͨµÀÅäÖà +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void AdcChannelConfig(void) +{ + stc_adc_ch_cfg_t stcChCfg; + uint8_t au8Adc1SaSampTime[1] = {255}; + + MEM_ZERO_STRUCT(stcChCfg); + + stcChCfg.u32Channel = BAT_COLL_ADC_CH; + stcChCfg.u8Sequence = ADC_SEQ_A; + stcChCfg.pu8SampTime = au8Adc1SaSampTime; + + AdcSetChannelPinMode(BAT_COLL_ADC_CH); + + /* 2. Add ADC channel. */ + ADC_AddAdcChannel(M4_ADC1, &stcChCfg); + + /* 3. Configure the average channel if you need. */ + ADC_ConfigAvg(M4_ADC1, AdcAvcnt_256); //ƽ¾ùͨµÀÅäÖ㬶à´Î²ÉÑùºóÊä³öƽ¾ùÖµ + + /* 4. Add average channel if you need. */ + ADC_AddAvgChannel(M4_ADC1, BAT_COLL_ADC_CH); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: Adc1_Config +* ¹¦ÄÜÃèÊö: ADC1ÅäÖà +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void Adc1_Config(void) +{ + CLK_SetPeriClkSource(ClkPeriSrcPclk); + AdcInitConfig(); + AdcChannelConfig(); +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: AdcDmaConfig +* ¹¦ÄÜÃèÊö: ADC DMAÅäÖà +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void AdcDmaConfig(void) +{ + stc_dma_config_t stcDmaCfg; + + MEM_ZERO_STRUCT(stcDmaCfg); + + stcDmaCfg.u16BlockSize = 1; + stcDmaCfg.u16TransferCnt = 0u; + stcDmaCfg.u32SrcAddr = (uint32_t)(&M4_ADC1->DR1); + stcDmaCfg.u32DesAddr = (uint32_t)(&m_au16Adc1SaValue); + stcDmaCfg.u16DesRptSize = 1; + stcDmaCfg.u16SrcRptSize = 1; + stcDmaCfg.u32DmaLlp = 0u; + stcDmaCfg.stcSrcNseqCfg.u16Cnt = 0u; + stcDmaCfg.stcSrcNseqCfg.u32Offset = 0u; + stcDmaCfg.stcDesNseqCfg.u16Cnt = 0u; + stcDmaCfg.stcDesNseqCfg.u32Offset = 0u; + stcDmaCfg.stcDmaChCfg.enSrcInc = AddressIncrease; + stcDmaCfg.stcDmaChCfg.enDesInc = AddressIncrease; + stcDmaCfg.stcDmaChCfg.enSrcRptEn = Enable; + stcDmaCfg.stcDmaChCfg.enDesRptEn = Enable; + stcDmaCfg.stcDmaChCfg.enSrcNseqEn = Disable; + stcDmaCfg.stcDmaChCfg.enDesNseqEn = Disable; + stcDmaCfg.stcDmaChCfg.enTrnWidth = Dma16Bit; + stcDmaCfg.stcDmaChCfg.enLlpEn = Disable; + /* Enable DMA interrupt. */ + stcDmaCfg.stcDmaChCfg.enIntEn = Enable; + + PWC_Fcg0PeriphClockCmd(PWC_FCG0_PERIPH_DMA1, Enable); + DMA_InitChannel(M4_DMA1, DmaCh0, &stcDmaCfg); + DMA_Cmd(M4_DMA1, Enable); + DMA_ChannelCmd(M4_DMA1, DmaCh0, Enable); + DMA_ClearIrqFlag(M4_DMA1, DmaCh0, TrnCpltIrq); + /* AOS must be enabled to use DMA */ + /* AOS enabled at first. */ + /* If you have enabled AOS before, then the following statement is not needed. */ + PWC_Fcg0PeriphClockCmd(PWC_FCG0_PERIPH_AOS, Enable); + DMA_SetTriggerSrc(M4_DMA1, DmaCh0, EVT_ADC1_EOCA); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DmaIrqRegister +* ¹¦ÄÜÃèÊö: DMAÖжϼĴæÆ÷ÅäÖà +* ²Î Êý: pstcCfg£¬ ÖжϲÎÊý + u32Priority£¬ ÖжÏÓÅÏȼ¶ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void DmaIrqRegister(stc_irq_regi_conf_t *pstcCfg, uint32_t u32Priority) +{ + int16_t s16Vnum = pstcCfg->enIRQn; + + if (((s16Vnum >= Int000_IRQn) && (s16Vnum <= Int031_IRQn)) || + ((s16Vnum >= Int038_IRQn) && (s16Vnum <= Int043_IRQn))) { + if (Ok != enIrqRegistration(pstcCfg)) + return; + } + else if (Int129_IRQn == s16Vnum) + enShareIrqEnable(pstcCfg->enIntSrc); + else + return; + + NVIC_ClearPendingIRQ(pstcCfg->enIRQn); + NVIC_SetPriority(pstcCfg->enIRQn, u32Priority); + NVIC_EnableIRQ(pstcCfg->enIRQn); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DmaIrqRegister +* ¹¦ÄÜÃèÊö: DMAÖжÏÅäÖà +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void DmaIrqConfig(void) +{ + stc_irq_regi_conf_t stcAdcIrqCfg; + + stcAdcIrqCfg.enIntSrc = INT_DMA1_BTC0; + stcAdcIrqCfg.enIRQn = Int030_IRQn; + stcAdcIrqCfg.pfnCallback = Dma1Btc0_IrqHandler; + + DmaIrqRegister(&stcAdcIrqCfg, DDL_IRQ_PRIORITY_03); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: DmaIrqRegister +* ¹¦ÄÜÃèÊö: DMAÅäÖà +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +static void Dma_Config(void) +{ + AdcDmaConfig(); + DmaIrqConfig(); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: ReadAdcValue +* ¹¦ÄÜÃèÊö: ¶ÁÈ¡ADÖµ +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ADÖµ +*****************************************************************************************/ +uint16_t GetADCBuffPoint(void) +{ + return m_au16Adc1SaValue; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: ADC_Start +* ¹¦ÄÜÃèÊö: Æô¶¯ADCת»» +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ADÖµ +*****************************************************************************************/ +void ADC_Start(void) +{ + ADC_StartConvert(M4_ADC1); +} +//void ReadAdcValue(uint16_t *ADValue) +//{ +// ADC_PollingSa(M4_ADC1, ADValue, 1, 100); +//} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: TimeGet +* ¹¦ÄÜÃèÊö: »ñȡϵͳʱ¼ä +* ²Î Êý: tm ¶Áȡʱ¼äÈë¿Ú +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void TimeGet(struct tm *cTime) +{ + stc_rtc_date_time_t RtcDateTime; + + RTC_GetDateTime(RtcDataFormatDec, &RtcDateTime); + cTime->tm_year = RtcDateTime.u8Year + 100; + cTime->tm_mon = RtcDateTime.u8Month - 1; + cTime->tm_mday = RtcDateTime.u8Day; + cTime->tm_hour = RtcDateTime.u8Hour; + cTime->tm_min = RtcDateTime.u8Minute; + cTime->tm_sec = RtcDateTime.u8Second; + cTime->tm_isdst = 0; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: TimeTs +* ¹¦ÄÜÃèÊö: ϵͳʱ¼äת»»Ê±¼ä´Á +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ·µ»Øʱ¼ä´Á +*****************************************************************************************/ +int TimeTs(void) +{ + struct tm cTime; + + TimeGet(&cTime); + time_t cTimet = mktime(&cTime); + + return cTimet; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: TimeShow +* ¹¦ÄÜÃèÊö: ½«Ê±¼äÊä³öµ½DBG´®¿Ú +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void TimeShow(uint32_t dwStamp) +{ + struct tm *stime; + stime = localtime(&dwStamp); + rt_kprintf("%d/",stime->tm_year + 1900); + rt_kprintf("%d/",stime->tm_mon + 1); + rt_kprintf("%d-",stime->tm_mday); + rt_kprintf("%d:",stime->tm_hour); + rt_kprintf("%d:",stime->tm_min); + rt_kprintf("%d\r\n",stime->tm_sec); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: TimeSync +* ¹¦ÄÜÃèÊö: ͨ¹ýʱ¼ä´Áͬ²½ +* ²Î Êý: ts ʱ¼äÈë¿Ú +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void TimeSync(time_t ts) +{ + struct tm *td; + stc_rtc_date_time_t RtcDateTime; + + td = localtime(&ts); + + RtcDateTime.u8Year = td->tm_year - 100; + RtcDateTime.u8Month = td->tm_mon + 1; + RtcDateTime.u8Day = td->tm_mday; + RtcDateTime.u8Weekday = td->tm_wday; + RtcDateTime.u8Hour = td->tm_hour; + RtcDateTime.u8Minute = td->tm_min; + RtcDateTime.u8Second = td->tm_sec; + + RTC_SetDateTime(RtcDataFormatDec, &RtcDateTime, Enable, Enable); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: TimeSync2 +* ¹¦ÄÜÃèÊö: ͨ¹ýÄêÔÂÈÕͬ²½ +* ²Î Êý: Year Äê + Month Ô + Day ÈÕ + Hour ʱ + Min ·Ö + Sec Ãë +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void TimeSync2(uint8_t Year, uint8_t Month, uint8_t Day, uint8_t Hour, uint8_t Min, uint8_t Sec) +{ + stc_rtc_date_time_t RtcDateTime; + + if(Year > 99 || Month < 1 || Month > 12 || Day < 1 || Day > 31 || Hour > 23 || Min > 59 || Sec > 59) + return; + + RtcDateTime.u8Year = Year; + RtcDateTime.u8Month = Month; + RtcDateTime.u8Day = Day; + RtcDateTime.u8Hour = Hour; + RtcDateTime.u8Minute = Min; + RtcDateTime.u8Second = Sec; + RTC_SetDateTime(RtcDataFormatDec, &RtcDateTime, Enable, Enable); +} +void FlashWrite(uint32_t Addr, uint32_t *wData, uint8_t wLen) +{ +// while(Ok != Flash_SectorErase(BOOT_PARA_ADDRESS)); +// for(int i = 0; i < wLen / 4; i++) { +// Flash_WriteWord(BOOT_PARA_ADDRESS + i * 4, wData[i]); +// } + + EFM_Unlock(); + + /* Enable flash. */ + EFM_FlashCmd(Enable); + /* Wait flash ready. */ + while(Set != EFM_GetFlagStatus(EFM_FLAG_RDY)) { ; } + /* Sequence program. */ + //EFM_SequenceProgram(FLASH_WRITE_ADDR, wLen, wData); + for(int i = 0; i < wLen; i++) { + EFM_SingleProgram(Addr + i * 4, wData[i]); + } + + EFM_Lock(); +} + +void FlashRead(uint32_t Addr,uint32_t *rData, uint8_t rLen) +{ + for(int i = 0; i < rLen / 4; i++) { + rData[i] = *((volatile uint32_t*)(Addr + i * 4)); + } +} +void dev_boot_read_param(boot_para_t *pParam) +{ + FlashRead(FLASH_BINFO_BASE,(uint8_t *)pParam,sizeof(boot_para_t)); +} +int dev_boot_write_param(boot_para_t Param) +{ + int wLen; + uint32_t *pData; + + pData= (uint32_t *)&Param; + + wLen = sizeof(boot_para_t)/4; + + EFM_Unlock(); + + /* Enable flash. */ + EFM_FlashCmd(Enable); + /* Wait flash ready. */ + while(Set != EFM_GetFlagStatus(EFM_FLAG_RDY)) { ; } + /* Erase sector. */ + EFM_SectorErase(FLASH_BINFO_BASE); + + for(int i = 0; i < wLen; i++) { + EFM_SingleProgram(FLASH_BINFO_BASE + i * 4, pData[i]); + } + /* Lock EFM. */ + EFM_Lock(); +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: EnterStop +* ¹¦ÄÜÃèÊö: ½øÈëµÍ¹¦ºÄ״̬ +* ²Î Êý: SleepStatus É豸µÍ¹¦ºÄ״̬ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +//void EnterStop(void) +//{ +// stc_pwc_stop_mode_cfg_t stcPwcStopCfg; +// stc_port_init_t stcPortInit; +// uint16_t AnaPin; +// +// PWC_Fcg1PeriphClockCmd(SPI_UNIT_CLOCK, Disable); +// PWC_Fcg1PeriphClockCmd(DBG_FCG1_PERIPH, Disable); +// DBGRxWakeupInit(); +// +// MEM_ZERO_STRUCT(stcPortInit); +// stcPortInit.enPinMode = Pin_Mode_Ana; +// AnaPin = PinAll & (~(Pin13|Pin14)); +// PORT_Init(PortA, AnaPin, &stcPortInit); +// +// AnaPin = PinAll & (~Pin02); +// PORT_Init(PortB, AnaPin, &stcPortInit); +// +// AnaPin = PinAll & (~(Pin03)); +// PORT_Init(PortC, AnaPin, &stcPortInit); +// +// AnaPin = Pin02; +// PORT_Init(PortH, AnaPin, &stcPortInit); +// +// SysTick_Suspend(); +// +// stcPwcStopCfg.enStpDrvAbi = StopUlowspeed; +// stcPwcStopCfg.enStopClk = ClkFix; +// stcPwcStopCfg.enStopFlash = Wait; +// stcPwcStopCfg.enPll = Enable; +// +// while(Ok != PWC_StopModeCfg(&stcPwcStopCfg)){;} +// while(1ul != M4_EFM->FSR_f.RDY){;} +// PWC_EnterStopMd(); +//} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: Wakeup +* ¹¦ÄÜÃèÊö: É豸»½ÐÑ +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +//void Wakeup(void) +//{ +// NVIC_DisableIRQ(DBG_RXPIN_IRQn); +// PWC_ClkRecover(); +// //SystemClockConfig(); +// Spi_Config(); +// DbgUart_Config(500000); +// //GPIO_Config(); +// //SysTick_Resume(); +// SysTick_Init(1000); +//} + +void Error_Handler(void) +{ + while(1){ ; } +} + +/***************************************************************************************** + * Watch Dog + ****************************************************************************************/ + +/***************************************************************************************** +* º¯ÊýÃû³Æ: FeedDog +* ¹¦ÄÜÃèÊö: ¿´ÃŹ·Î¹¹·º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +void FeedDog(void) +{ +#if (WATCH_DOG == 1) + SWDT_RefreshCounter(); +#endif +} + +void DelaymS(int Dly) +{ + int j; + for(int i = 0; i < Dly; i++){ + j = 350; + while(j > 0) j--; + } +} + +void BSP_Init(void) +{ + stc_clk_freq_t Freq; + + GPIO_Config(); + + POWER_LED_ON(); + LORA_POW_OFF(); + CAT1_RESET_CLR(); + ETH_RESET_CLR(); + FeedDog(); + for(int i = 0; i < 6; i++) { + DelaymS(6000); + FeedDog(); + + } + POWER_LED_OFF(); + + SystemClockConfig(); + Xtal32_ClockConfig(); + + DbgUart_Config(500000); + EthOrCat1_Config(115200); +// RS485Ch1_Config(9600); +// RS485Ch2_Config(9600); +#if USE_SD_CARD + SdioInit(); +#endif + Rtc_Config(); + Spi1_Config(); + Spi2_Config(); + Adc1_Config(); + Dma_Config(); + FeedDog(); + ADC_Start(); + CLK_GetClockFreq(&Freq); + SysTick_Init(1000); + FeedDog(); + //DBG_LOG("SysFreq = %d\r\n", Freq.sysclkFreq); +} + +/***************************************************************************************** + * User Irq CallBack + ****************************************************************************************/ + +/***************************************************************************************** +* º¯ÊýÃû³Æ: LoraTxRxIrqCallback +* ¹¦ÄÜÃèÊö: LORAÊÕ·¢ÖжÏÍⲿÖض¨Ïò»Øµ÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +__weak void LoraTxRxIrqCallback(void) +{ + +} +/***************************************************************************************** +* º¯ÊýÃû³Æ: DbgRxIrqCallback +* ¹¦ÄÜÃèÊö: µ÷ÊÔ´®¿Ú½ÓÊÕÖжÏÍⲿÖض¨Ïò»Øµ÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +__weak void DbgRxIrqCallback(uint8_t rData) +{ + +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch1RxIrqCallback +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1´®¿Ú½ÓÊÕÖжÏÍⲿÖض¨Ïò»Øµ÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +__weak void RS485Ch1RxIrqCallback(uint8_t rData) +{ + +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RS485Ch2RxIrqCallback +* ¹¦ÄÜÃèÊö: RS485ͨµÀ1´®¿Ú½ÓÊÕÖжÏÍⲿÖض¨Ïò»Øµ÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +__weak void RS485Ch2RxIrqCallback(uint8_t rData) +{ + +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: EthOrCat1RxIrqCallback +* ¹¦ÄÜÃèÊö: EthºÍCat1´®¿Ú½ÓÊÕÖжÏÍⲿÖض¨Ïò»Øµ÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +__weak void EthOrCat1RxIrqCallback(uint8_t rData) +{ + +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: RtcPeriod_IrqCallback +* ¹¦ÄÜÃèÊö: RTCÖжϻص÷ +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +//__weak void RtcPeriod_IrqCallback(void) +//{ + +//} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: Dma1Btc0_IrqHandler +* ¹¦ÄÜÃèÊö: DMAÖжÏÍⲿÖض¨Ïò»Øµ÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +__weak void Dma1Btc0_IrqHandler(void) +{ + DMA_ClearIrqFlag(M4_DMA1, DmaCh0, BlkTrnCpltIrq); + ADC_Start(); +} diff --git a/Project/GateWay/source/User/Src/main.c b/Project/GateWay/source/User/Src/main.c new file mode 100644 index 0000000..c6df189 --- /dev/null +++ b/Project/GateWay/source/User/Src/main.c @@ -0,0 +1,645 @@ +#include +#include +#include "main.h" +#include "CatOneTask.h" +#include "LoraTask.h" +#include "CatOneTask.h" +#include "RS485Task.h" +#include "DebugCmd.h" +#include "spiflash.h" + + +//ÑÅÏ£º 81-00-00-06-00-01 +// 81-00-00-06-00-02 +// 81-00-00-06-00-03 +// 81-00-00-06-00-04 +// 81-00-00-06-00-05 +// 81-00-00-06-00-06 +// 81-00-00-06-00-07 +// 81-00-00-06-00-08 +// 81-00-00-06-00-09 +// 81-00-00-06-00-0A + +static const uint8_t GateWayMac_Test[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x00}; +static const uint8_t GateWayMac_BL1[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x01}; +static const uint8_t GateWayMac_BL2[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x02}; +static const uint8_t GateWayMac_BL3[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x03}; +static const uint8_t GateWayMac_BL4[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x04}; +static const uint8_t GateWayMac_BL5[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x05}; +static const uint8_t GateWayMac_BL6[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x06}; +static const uint8_t GateWayMac_BL7[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x07}; +static const uint8_t GateWayMac_BL8[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x08}; +static const uint8_t GateWayMac_BL9[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x09}; +static const uint8_t GateWayMac_BL10[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x0A}; +bool MainDispEn = true; + +static rt_thread_t Lora_Thread = RT_NULL; +static rt_thread_t Cat1Eth_Thread = RT_NULL; +static rt_thread_t RS485Ch1_Thread = RT_NULL; +static rt_thread_t RS485Ch2_Thread = RT_NULL; +static rt_thread_t Debug_Thread = RT_NULL; + +GateWayPara_t GateWay; + +#define ARRAY_DIM(a) (sizeof(a) / sizeof((a)[0])) +//static int Battery_Level_Percent_Table[11] = {3000, 3650, 3700, 3740, 3760, 3795, 3840, 3910, 3980, 4070, 4150}; +static int Battery_Level_Percent_Table[11] = {6000, 7300, 7400, 7480, 7520, 7590, 7680, 7820, 7960, 8140, 8300}; +int toPercentage(int voltage) +{ + int i; + if(voltage < Battery_Level_Percent_Table[0]) + return 0; + + for(i = 0; i 0 +// GateWay.ConfigPara.SvrAddr[0] = 39; +// GateWay.ConfigPara.SvrAddr[1] = 106; +// GateWay.ConfigPara.SvrAddr[2] = 103; +// GateWay.ConfigPara.SvrAddr[3] = 147; +// GateWay.ConfigPara.SvrPort = 8080; + GateWay.ConfigPara.SvrAddr[0] = 103; + GateWay.ConfigPara.SvrAddr[1] = 217; + GateWay.ConfigPara.SvrAddr[2] = 192; + GateWay.ConfigPara.SvrAddr[3] = 248; + GateWay.ConfigPara.SvrPort = 12111; +#endif + + if(GateWay.ConfigPara.DebugChannel == DEBUG_CH_RS485_1) { + GateWay.ConfigPara.Rs485Ch1.Enable = true; + GateWay.ConfigPara.Rs485Ch1.BaudRate = 500000; + } + if(GateWay.ConfigPara.Rs485Ch1.BaudRate < 2400 || GateWay.ConfigPara.Rs485Ch1.BaudRate > 921600) + GateWay.ConfigPara.Rs485Ch1.BaudRate = 500000; + RS485Ch1_Config(GateWay.ConfigPara.Rs485Ch1.BaudRate); + + if(GateWay.ConfigPara.DebugChannel == DEBUG_CH_RS485_2) { + GateWay.ConfigPara.Rs485Ch2.Enable = true; + GateWay.ConfigPara.Rs485Ch2.BaudRate = 500000; + } + if(GateWay.ConfigPara.Rs485Ch2.BaudRate < 2400 || GateWay.ConfigPara.Rs485Ch2.BaudRate > 921600) + GateWay.ConfigPara.Rs485Ch2.BaudRate = 500000; + RS485Ch2_Config(GateWay.ConfigPara.Rs485Ch2.BaudRate); + + if(GateWay.ConfigPara.Rs485Ch1.Power) + RS485_CH1_POW_ON(); + else + RS485_CH1_POW_OFF(); + + if(GateWay.ConfigPara.Rs485Ch2.Power) { + RS485_CH2_POW_OFF(); + rt_thread_delay(1000); + RS485_CH2_POW_ON(); + } + else + RS485_CH2_POW_OFF(); + + if(GateWay.ConfigPara.Lora.OnOff == true) { + LORA_POW_ON(); + } + else { + LORA_POW_OFF(); + } + if(LoraSetChannel(GateWay.ConfigPara.Lora.ucChannel) == false) { + GateWay.ConfigPara.Lora.ucChannel = 8; + LoraSetChannel(GateWay.ConfigPara.Lora.ucChannel); + //WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t)); + } + if(LoraSetPower(GateWay.ConfigPara.Lora.ucPower) == false) { + GateWay.ConfigPara.Lora.ucPower = 20; + LoraSetPower(GateWay.ConfigPara.Lora.ucPower); + //WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t)); + } + if(LoraSetSignalBw(GateWay.ConfigPara.Lora.SignalBw) == false) { + GateWay.ConfigPara.Lora.SignalBw = 8; + LoraSetSignalBw(GateWay.ConfigPara.Lora.SignalBw); + //WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t)); + } + if(LoraSetSpreadFactor(GateWay.ConfigPara.Lora.SpreadFactor) == false) { + GateWay.ConfigPara.Lora.SpreadFactor = 9; + LoraSetSpreadFactor(GateWay.ConfigPara.Lora.SpreadFactor); + //WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t)); + } + if(LoraSetErrorCoding(GateWay.ConfigPara.Lora.ErrorCoding) == false) { + GateWay.ConfigPara.Lora.ErrorCoding = 2; + LoraSetErrorCoding(GateWay.ConfigPara.Lora.ErrorCoding); + //WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t)); + } + if(GateWay.ConfigPara.Lora.RegPreamble > 0xFE) { + GateWay.ConfigPara.Lora.RegPreamble = 10; + //WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t)); + } + LoraSetRegPreamble(GateWay.ConfigPara.Lora.RegPreamble); + + WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t)); + + LogInit(); + + Header.LogEndAddr = 0; + if(ReadLogNum() > 0) { + int ret = ReadLog(&Header, NULL, 0); + if(ret > 0) { + GateWay.HistoryNum = ReadLogNum() - Header.LogIdx + 1; + rt_kprintf("History Num: %d\r\n", GateWay.HistoryNum); + } + else { + rt_kprintf("History Num: 0\r\n"); + } + } + else + rt_kprintf("History Num: 0\r\n"); + if(GateWay.ConfigPara.Comm == CATONE_COMM) { + CAT1_ON(); + } + else { + ETH_ON(); + } +} + +void OutageUpdate(uint8_t AlarmType, bool AlarmState, uint8_t Batt) +{ + GateWayAlarmType_t *Alarm; + uint8_t MegData[6],len; + len = sizeof(GateWayAlarmType_t); + MegData[0] = len & 0x00ff;; + MegData[1] = (len >> 8) & 0x00ff; + MegData[2] = NET_COMM_CMD_ALARM; + + Alarm = (GateWayAlarmType_t *)&MegData[3]; + Alarm->AlarmType = AlarmType; + Alarm->AlarmState = AlarmState; + Alarm->AlarmPara = Batt; + CatOneEthSendQueue(MegData, 6); //·¢Ëͱ¨¾¯ÐÅÏ¢ +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: main +* ¹¦ÄÜÃèÊö: Ö÷º¯Êý +* ²Î Êý: ÎÞ +* ·µ »Ø Öµ: ÔËÐдíÎó·µ»Ø-1 +*****************************************************************************************/ +static uint8_t LastBattery = 0xff; //ÉÏÒ»´Îµç³Øµçѹ +int main(void) +{ + uint16_t OneSecondDlyCnt = 0; +// struct tm cTime; + uint16_t PowerONLedDly = 2000; + uint32_t SystemRseetDlyCnt = 0; + uint32_t BatteryUpdateDlyCnt = 0; + uint8_t AlarmType = 0; + + GateWayInit(); + + rt_kprintf("\r\n\r\n"); + rt_kprintf("****************************************************\r\n"); + rt_kprintf("** **\r\n"); + rt_kprintf("** GateWay **\r\n"); + rt_kprintf("** SoftWare V%d.%d **\r\n", SOFTWARE_VERSION / 10, SOFTWARE_VERSION % 10); + rt_kprintf("** HardWare V%d.%d **\r\n", HARDWARE_VERSION / 10, HARDWARE_VERSION % 10); + rt_kprintf("** Compile: %s %s **\r\n", __DATE__, __TIME__); + rt_kprintf("** **\r\n"); + rt_kprintf("****************************************************\r\n\r\n"); +// TimeGet(&cTime); +// TimeShow(TimeTs()); + FeedDog(); + //rt_thread_delay(500); + //InfTest(); + //FeedDog(); + + //Cat1DBGOnOff(true); + + + GateWay.CommUnitRevCallBack = CommUnitAnalyze; + GateWay.SvrRevCallBack = Cat1EthRevCallBack; + + GateWay.NetSendData_MQ = rt_mq_create("NetSendMQ", 512, 10, RT_IPC_FLAG_FIFO); + if(GateWay.NetSendData_MQ == RT_NULL) { + rt_kprintf("CatOne MQ Create Failed!\r\n"); + } + + GateWay.LoraRev_MQ = rt_mq_create("LoraRevMQ", 256, 10, RT_IPC_FLAG_FIFO); + if(GateWay.LoraRev_MQ == RT_NULL) { + rt_kprintf("LoraRev MQ Create Failed!\r\n"); + } + + GateWay.UartRevMutex = rt_mutex_create("urmutex", RT_IPC_FLAG_FIFO); + if(GateWay.UartRevMutex == RT_NULL) { + rt_kprintf("UR Mutex Create Failed!\r\n"); + } + + GateWay.SvrRevCallBack = Cat1EthRevCallBack; + + RS485Ch1_Thread = rt_thread_create("RS485Ch1", RS485Ch1_Thread_Entry, &GateWay, 2048, 3, 20); + if (RS485Ch1_Thread != RT_NULL) + rt_thread_startup(RS485Ch1_Thread); + else + return -1; + + RS485Ch2_Thread = rt_thread_create("RS485Ch2", RS485Ch2_Thread_Entry, &GateWay, 2048, 3, 20); + if (RS485Ch2_Thread != RT_NULL) + rt_thread_startup(RS485Ch2_Thread); + else + return -1; + + Debug_Thread = rt_thread_create("DebugUart", Debug_Thread_Entry, &GateWay, 2048, 3, 20); + if (RS485Ch2_Thread != RT_NULL) + rt_thread_startup(Debug_Thread); + else + return -1; + + Cat1Eth_Thread = rt_thread_create("Cat1Eth", CatOne_Eth_Thread_Entry, &GateWay, 4096, 3, 20); + if (Cat1Eth_Thread != RT_NULL) + rt_thread_startup(Cat1Eth_Thread); + else + return -1; + + Lora_Thread = rt_thread_create("Lora", Lora_Thread_Entry, &GateWay, 1024, 3, 20); + if (Lora_Thread != RT_NULL) + rt_thread_startup(Lora_Thread); + else + return -1; + + while(1) { + if(PowerONLedDly > 0) { + PowerONLedDly--; + if(PowerONLedDly == 1) { + POWER_LED_OFF(); + } + } + EthRxOverhandler(); + RS485RxOverhandler(); + DebugRxOverhandler(); + if(OneSecondDlyCnt % 200 == 0) { + FeedDog(); + LORA_RX_TOGGLE(); + POWER_TOGGLE(); + } + OneSecondDlyCnt++; + if(OneSecondDlyCnt == 1000) { + OneSecondDlyCnt = 0; + + if(GateWay.BatteryReadDlyCnt > 0) { + GateWay.BatteryReadDlyCnt--; + continue; + } + + uint16_t ADValue = GetADCBuffPoint(); + //V = (AD * 3.3 / 4096) * (R1+R2) / R1; R1 = 200, R2 = 120 + //¼ÆËã³ö³£ÊýΪ0.0021484375£¬À©´ó1000±¶ + float Voltage = ADValue * 2.1484375; + GateWay.Battery = toPercentage(Voltage); + + //ÉϵçÅжϵçÁ¿ + if(LastBattery == 0xff) { + LastBattery = GateWay.Battery; + + if(GateWay.ConfigPara.OutageFlag == true) { //Óб¨¾¯ + AlarmType = 1; + } + else { + AlarmType = 0; + } + //BatteryUpdateDlyCnt = 2 * 60; + BatteryUpdateDlyCnt = 10; + } + else { + if(GateWay.ConfigPara.OutageFlag == false) { //ûÓи澯£¬Åжϵç³ØµçѹÊÇ·ñ½µµÍ + if(GateWay.Battery <= LastBattery) { + if(LastBattery <= 5) { + GateWay.ConfigPara.OutageFlag = true; + WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t)); + Debug_Printf("The power is cutted.(1) Bat = %d, LBat = %d\r\n", GateWay.Battery, LastBattery); + LastBattery = GateWay.Battery; + AlarmType = 1; + OutageUpdate(AlarmType, GateWay.ConfigPara.OutageFlag, LastBattery); + BatteryUpdateDlyCnt = 20 * 60; + } + else if((LastBattery - GateWay.Battery) > 2) { + GateWay.ConfigPara.OutageFlag = true; + WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t)); + LastBattery = GateWay.Battery; + AlarmType = 1; + Debug_Printf("The power is cutted.(2) Bat = %d, LBat = %d\r\n", GateWay.Battery, LastBattery); + OutageUpdate(AlarmType, GateWay.ConfigPara.OutageFlag, LastBattery); + BatteryUpdateDlyCnt = 20 * 60; + } + } + else { //³äµç£¬¸üÐÂÉÏÒ»´Îµç³Øµçѹ + LastBattery = GateWay.Battery; + } + } + else { + if(GateWay.Battery >= LastBattery) { + if(LastBattery > 95) { + GateWay.ConfigPara.OutageFlag = false; + WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t)); + Debug_Printf("The power is restored.(1) Bat = %d, LBat = %d\r\n", GateWay.Battery, LastBattery); + LastBattery = GateWay.Battery; + AlarmType = 1; + OutageUpdate(AlarmType, GateWay.ConfigPara.OutageFlag, LastBattery); + BatteryUpdateDlyCnt = 90 * 60; + AlarmType = 0; + } + else if(GateWay.Battery - LastBattery > 5) { + GateWay.ConfigPara.OutageFlag = false; + WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t)); + Debug_Printf("The power is restored.(2) Bat = %d, LBat = %d\r\n", GateWay.Battery, LastBattery); + LastBattery = GateWay.Battery; + AlarmType = 1; + OutageUpdate(AlarmType, GateWay.ConfigPara.OutageFlag, LastBattery); + BatteryUpdateDlyCnt = 90 * 60; + AlarmType = 0; + } + } + else { //µç³Ø¼ÌÐø·Åµç£¬¸üÐÂÉÏÒ»´Îµç³Øµçѹ + LastBattery = GateWay.Battery; + } + } + } + BatteryUpdateDlyCnt--; + if(BatteryUpdateDlyCnt == 0) { + if(GateWay.ConfigPara.OutageFlag) { //Óб¨¾¯ + BatteryUpdateDlyCnt = 20 * 60; + } + else { + BatteryUpdateDlyCnt = 90 * 60; + } + OutageUpdate(AlarmType, GateWay.ConfigPara.OutageFlag, LastBattery); + } + //ADC_Start(); + } + SystemRseetDlyCnt++; + if(SystemRseetDlyCnt > (24 * 60 * 60 * 1000)) { + SystemRseetDlyCnt = 0; + Debug_Printf("The system resets periodically.\r\n"); + rt_thread_delay(10); + NVIC_SystemReset(); + } + rt_thread_delay(1); + } +} + + + +#if 0 +static FATFS SDFatFs; +static FIL TestFile; +static uint8_t u8WorkBuffer[FF_MAX_SS]; + +void FSInit(void) +{ + FRESULT fRet; + uint32_t u32WBNbr, u32RBNbr; + char SDPath[] = "1:"; + MKFS_PARM opt; + uint8_t u8ReadText[100]; + en_result_t enTestRet = Error; + uint8_t u8WriteText[] = "This is a string used to test the FatFs"; + + if (FR_OK != f_mount(&SDFatFs, (TCHAR const*)SDPath, 0U)) { + rt_kprintf("FatFs Initialization Error!\r\n"); + } + else { + memset(&opt, 0, sizeof(MKFS_PARM)); + opt.fmt = (BYTE)FM_FAT32; + /* Create a FAT file system (format) on the logical drive */ + if (FR_OK != f_mkfs((TCHAR const*)SDPath, &opt, u8WorkBuffer, sizeof(u8WorkBuffer))) { + rt_kprintf("FatFs Format Error!\r\n"); + } + else { + /* Create and Open a new text file object with write access */ + if (FR_OK != f_open(&TestFile, "1:Test.txt", ((BYTE)FA_CREATE_ALWAYS | (BYTE)FA_WRITE))) { + rt_kprintf("\"Test.txt\" file Open for write Error!\r\n"); + } + else { + /* Write data to the text file */ + fRet = f_write(&TestFile, u8WriteText, sizeof(u8WriteText), (void *)&u32WBNbr); + if ((0UL == u32WBNbr) || (FR_OK != fRet)) { + rt_kprintf("\"Test.txt\" file Write or EOF Error!\r\n"); + else { + /* Close the open text file */ + f_close(&TestFile); + /* Open the text file object with read access */ + if (FR_OK != f_open(&TestFile, "1:Test.txt", (BYTE)FA_READ)) { + rt_kprintf("\"Test.txt\" file Open for read Error!\r\n"); + } + else { + memset(u8ReadText, 0, sizeof(u8ReadText)); + /* Read data from the text file */ + fRet = f_read(&TestFile, u8ReadText, sizeof(u8ReadText), (UINT*)(uint32_t)&u32RBNbr); + if ((0UL == u32RBNbr) || (FR_OK != fRet)) { + rt_kprintf("\"Test.txt\" file Read or EOF Error!\r\n"); + } + else { + /* Close the open text file */ + f_close(&TestFile); + /* Compare read data with the expected data */ + if (u32RBNbr == u32WBNbr) { + /* Check data value */ + if (0 == memcmp(u8WriteText, u8ReadText, u32RBNbr)) { + enTestRet = Ok; + } + } + } + } + } + } + } + } + /* Unlink the micro SD disk I/O driver */ + f_mount(NULL, (TCHAR const*)SDPath, 0U); + + if(enTestRet != Ok) { + rt_kprintf("Error!\r\n"); + } + else { + rt_kprintf("Ok!\r\n"); + } +} + +#endif + diff --git a/Project/GateWay/source/User/Src/protocol.c b/Project/GateWay/source/User/Src/protocol.c new file mode 100644 index 0000000..1ab5277 --- /dev/null +++ b/Project/GateWay/source/User/Src/protocol.c @@ -0,0 +1,120 @@ +#include "protocol.h" +#include "string.h" +#include "utils.h" + +int protocol_pack_frame( + uint16_t slave_addr, + uint8_t command,const + uint8_t *payload, + uint16_t payload_len, + uint8_t *buffer,uint16_t buffer_size, + uint16_t *packed_len) +{ + + // ¹¹½¨»ù´¡Ö¡Í· + + buffer[0] = PROTOCOL_HEAD & 0xFF; + buffer[1] = (PROTOCOL_HEAD >> 8) & 0xFF; + buffer[2] = slave_addr & 0xFF; + buffer[3] = (slave_addr >> 8) & 0xFF; + + buffer[4] = command; + + buffer[5] = payload_len & 0xFF; + buffer[6] = (payload_len >> 8) & 0xFF; + + // ¸´ÖÆÓÐЧÔغɣ¨±£³ÖС¶Ë¸ñʽ£© + if (payload_len > 0 && payload != NULL) { + memcpy(buffer + PROTOCOL_FRAME_HEAD_SIZE , payload, payload_len); + } + + // ÉèÖÃʵ¼Ê³¤¶È + int fram_len = PROTOCOL_FRAME_MIN_SIZE + payload_len; + + + // ¼ÆËãCRC£¨¸²¸ÇµØÖ·¡¢ÃüÁî¡¢³¤¶ÈºÍÓÐЧÔغɣ© + uint16_t crc = 0xFFFF; + + crc = modbus_crc16(buffer,fram_len -2); + + // дÈëCRC£¨±£³ÖС¶Ë¸ñʽ£© + + buffer[fram_len-2] = (uint8_t)(crc & 0xFF); + buffer[fram_len-1] = (uint8_t)(crc >> 8); + + *packed_len =fram_len; + + return PROTOCOL_SUCCESS; + +} + +int protocol_unpack_frame( + const uint8_t *frame, + uint16_t frame_len, + uint16_t *slave_addr, + uint8_t *command, + uint8_t *payload, + uint16_t *payload_len +) { + // ²ÎÊýУÑé + if (frame == NULL || slave_addr == NULL || command == NULL || payload_len == NULL) { + return PROTOCOL_ERR_INVALID_PARAM; + } + if (frame_len < PROTOCOL_FRAME_MIN_SIZE) { + return PROTOCOL_ERR_INVALID_PARAM; + } + + // ֡ͷУÑé + uint16_t header = (frame[0] | frame[1] <<8); + + if (header != PROTOCOL_HEAD) { + + return PROTOCOL_ERR_INVALID_PARAM; + } + + // »ù´¡×ֶνâÎö + *slave_addr = (frame[2] | frame[3] << 8); + + + *command = frame[4]; + + + *payload_len = (frame[5] | frame[6] << 8); + + // Êý¾ÝÍêÕûÐÔУÑé + if (*payload_len > (frame_len - PROTOCOL_FRAME_MIN_SIZE)) { + + return PROTOCOL_ERR_BUFFER_OVERFLOW; + } + + int frame_size = *payload_len + 9; + + uint16_t calc_crc =0xffff; + + calc_crc = modbus_crc16((uint8_t *)frame, frame_size -2 ); + + // УÑéCRC£¨±£³ÖС¶Ë¸ñʽ£© + union{ + + uint16_t value; + struct{ + uint8_t crcl; + uint8_t crch; + }bytes; + + }crc_data; + + crc_data.bytes.crcl =(frame[frame_size - 2] ) ; + crc_data.bytes.crch =(frame[frame_size - 1] ) ; + + if (calc_crc != crc_data.value) { + return PROTOCOL_ERR_CRC; + } + + // ¸´ÖÆÓÐЧÔغɣ¨±£³ÖС¶Ë¸ñʽ£© + if (*payload_len > 0 && payload != NULL) { + memcpy(payload, frame + PROTOCOL_FRAME_HEAD_SIZE, *payload_len); + } + + return PROTOCOL_SUCCESS; +} diff --git a/Project/GateWay/source/User/Src/ringbuffer.c b/Project/GateWay/source/User/Src/ringbuffer.c new file mode 100644 index 0000000..225076b --- /dev/null +++ b/Project/GateWay/source/User/Src/ringbuffer.c @@ -0,0 +1,89 @@ +/****************************************************************************** + * @brief »·Ðλº³åÇø¹ÜÀí(²Î¿¼linux/kfifo) + * + * Copyright (c) 2016~2020, + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2016-05-30 Morro ³õ°æÍê³É + ******************************************************************************/ +#include "ringbuffer.h" +#include +#include + +#define min(a,b) ( (a) < (b) )? (a):(b) + +/* + *@brief ¹¹ÔìÒ»¸ö¿Õ»·Ðλº³åÇø + *@param[in] r - »·Ðλº³åÇø¹ÜÀíÆ÷ + *@param[in] buf - Êý¾Ý»º³åÇø + *@param[in] len - buf³¤¶È(±ØÐëÊÇ2µÄN´ÎÃÝ) + *@retval bool + */ +bool ring_buf_init(ring_buf_t *r,unsigned char *buf, unsigned int len) +{ + r->buf = buf; + r->size = len; + r->front = r->rear = 0; + return (buf != NULL) && ((len & len -1) == 0); +} + +/* + *@brief Çå¿Õ»·Ðλº³åÇø + *@param[in] r - ´ýÇå¿ÕµÄ»·Ðλº³åÇø + *@retval none + */ +void ring_buf_clr(ring_buf_t *r) +{ + r->front = r->rear = 0; +} + +/* + *@brief »ñÈ¡»·Ðλº³åÇøÊý¾Ý³¤¶È + *@retval »·Ðλº³åÇøÖÐÓÐЧ×Ö½ÚÊý + */ +int ring_buf_len(ring_buf_t *r) +{ + return r->rear - r->front; +} + +/* + *@brief ½«Ö¸¶¨³¤¶ÈµÄÊý¾Ý·Åµ½»·Ðλº³åÇøÖÐ + *@param[in] buf - Êý¾Ý»º³åÇø + * len - »º³åÇø³¤¶È + *@retval ʵ¼Ê·Åµ½ÖеÄÊý¾Ý + */ +int ring_buf_put(ring_buf_t *r,unsigned char *buf,unsigned int len) +{ + unsigned int i; + unsigned int left; + left = r->size + r->front - r->rear; + len = min(len , left); + i = min(len, r->size - (r->rear & r->size - 1)); + memcpy(r->buf + (r->rear & r->size - 1), buf, i); + memcpy(r->buf, buf + i, len - i); + r->rear += len; + return len; + +} + +/* + *@brief ´Ó»·Ðλº³åÇøÖжÁÈ¡Ö¸¶¨³¤¶ÈµÄÊý¾Ý + *@param[in] len - ¶ÁÈ¡³¤¶È + *@param[out] buf - Êä³öÊý¾Ý»º³åÇø + *@retval ʵ¼Ê¶ÁÈ¡³¤¶È + */ +int ring_buf_get(ring_buf_t *r,unsigned char *buf,unsigned int len) +{ + unsigned int i; + unsigned int left; + left = r->rear - r->front; + len = min(len , left); + i = min(len, r->size - (r->front & r->size - 1)); + memcpy(buf, r->buf + (r->front & r->size - 1), i); + memcpy(buf + i, r->buf, len - i); + r->front += len; + return len; +} diff --git a/Project/GateWay/source/User/Src/spiflash.c b/Project/GateWay/source/User/Src/spiflash.c new file mode 100644 index 0000000..c22f2fe --- /dev/null +++ b/Project/GateWay/source/User/Src/spiflash.c @@ -0,0 +1,497 @@ +#include "spiflash.h" +#include "rtthread.h" +#include "DebugCmd.h" +#include "Public.h" + +//#define FLASH_TEST + +#ifdef FLASH_TEST +uint8_t flashtestbuff[SPIFLASH_SIZE]; +#endif + +static uint8_t SpiFlashReadByte(void) +{ + return Spi1SendReceive(0); +} + +static void SpiFlashSendByte(uint8_t sData) +{ + Spi1SendReceive(sData); +} + +static void SpiFlashWriteEnable(void) +{ + SpiFlashClrNss(); + SpiFlashSendByte(SPIFLASH_CMD_WREN); + SpiFlashSetNss(); +} + +static void SpiFlashWaitForWriteEnd(void) +{ + uint8_t flashstatus = 0; + SpiFlashClrNss(); + SpiFlashSendByte(SPIFLASH_CMD_RDSR); + do{ + flashstatus = SpiFlashReadByte(); + } + while ((flashstatus & SPIFLASH_WIP_FLAG) == SPIFLASH_WIP_FLAG); + SpiFlashSetNss(); +} + +//ÉÈÇø²Á³ý +void SpiFlashEraseSector(uint32_t SectorAddr) +{ +#ifdef FLASH_TEST + memset(&flashtestbuff[SectorAddr], 0xff, 4096); +#else + SpiFlashWriteEnable(); + SpiFlashWaitForWriteEnd(); + SpiFlashClrNss(); + SpiFlashSendByte(SPIFLASH_CMD_SE); + SpiFlashSendByte((SectorAddr >> 16) & 0x00FF); + SpiFlashSendByte((SectorAddr >> 8) & 0x00FF); + SpiFlashSendByte(SectorAddr & 0x00FF); + SpiFlashSetNss(); + SpiFlashWaitForWriteEnd(); +#endif +} + +//ÕûƬ²Á³ý +void SpiFlashEraseChip(void) +{ + SpiFlashWriteEnable(); + SpiFlashClrNss(); + SpiFlashSendByte(SPIFLASH_CMD_BE); + SpiFlashSetNss(); + SpiFlashWaitForWriteEnd(); +} + +//дÊý¾Ý +void SpiFlashWriteData(uint8_t* wData, uint32_t wAddr, uint16_t wLen) +{ +#ifdef FLASH_TEST + memcpy(&flashtestbuff[wAddr], wData, wLen); +#else + SpiFlashWriteEnable(); + SpiFlashClrNss(); + SpiFlashSendByte(SPIFLASH_CMD_WRITE); + SpiFlashSendByte((wAddr >> 16) & 0x00FF); + SpiFlashSendByte((wAddr >> 8) & 0x00FF); + SpiFlashSendByte(wAddr & 0x00FF); + for(int i = 0; i < wLen; i++) { + SpiFlashSendByte(wData[i]); + } + SpiFlashSetNss(); + SpiFlashWaitForWriteEnd(); +#endif +} + +void SpiFlashWriteAnyLengthData(uint8_t* wData, uint32_t wAddr, uint16_t wLen) +{ + uint16_t PageCnt; //ÐèҪдÈëÒ³Êý + uint16_t FirstPageWriteSize; //ÔÚÆðʼµØÖ·²»ÎªÒ³ÆðʼµØÖ·µÄÇé¿öÏ£¬ÏÈдÈ뵱ǰҳʣÓà¿Õ¼ä + uint16_t LastPageWriteSize; //×îºóһҳдÈ볤¶È + uint32_t AddrOffset = 0; + uint32_t WriteAddr; + LogHeader LogH; + WriteAddr = wAddr; + + //дÈëµÄ³¤¶È³¬³ö×î´ó¿Õ¼ä£¬´ÓÆðʼ¿ªÊ¼Ð´Æð + if((WriteAddr + wLen) > SPIFLASH_SIZE) { + LogH = (LogHeader)wData; + WriteAddr = LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE; + LogH->LogEndAddr = WriteAddr + wLen; + } + + uint16_t FirstPageRemainSpace = SPIFLASH_PAGESIZE - (WriteAddr % SPIFLASH_PAGESIZE); + +// //ÅжÏÊÇ·ñ¿çÉÈÇø£¬¿çÉÈÇøÐèÒªÏȲÁ³ýÏÂÒ»ÉÈÇø +// CheckDelSecter(wAddr, wLen); + + if(wLen < FirstPageRemainSpace) { + FirstPageWriteSize = wLen; //¼ÆËãÊ×ҳдÈ볤¶È + PageCnt = 0; + LastPageWriteSize = 0; + } + else { +// FirstPageWriteSize = FirstPageRemainSpace % SPIFLASH_PAGESIZE; +// PageCnt = (wLen - (FirstPageWriteSize % SPIFLASH_PAGESIZE)) / SPIFLASH_PAGESIZE; //¼ÆËãÐèҪдÈë¶àÉÙÕûÒ³ +// LastPageWriteSize = (wLen - (FirstPageWriteSize % SPIFLASH_PAGESIZE)) % SPIFLASH_PAGESIZE; //¼ÆËãÊ£ÓàÐèҪдÈëµÄ³¤¶È + FirstPageWriteSize = FirstPageRemainSpace; + PageCnt = (wLen - FirstPageWriteSize) / SPIFLASH_PAGESIZE; //¼ÆËãÐèҪдÈë¶àÉÙÕûÒ³ + LastPageWriteSize = (wLen - FirstPageWriteSize) % SPIFLASH_PAGESIZE; //¼ÆËãÊ£ÓàÐèҪдÈëµÄ³¤¶È + } + + if(FirstPageWriteSize > 0) { + SpiFlashWriteData(&wData[AddrOffset], WriteAddr, FirstPageWriteSize); + AddrOffset += FirstPageWriteSize; + WriteAddr += FirstPageWriteSize; + } + for(int i = 0; i < PageCnt; i++) { + SpiFlashWriteData(&wData[AddrOffset], WriteAddr, SPIFLASH_PAGESIZE); + AddrOffset += SPIFLASH_PAGESIZE; + WriteAddr += SPIFLASH_PAGESIZE; + } + if(LastPageWriteSize > 0) { + SpiFlashWriteData(&wData[AddrOffset], WriteAddr, LastPageWriteSize); + } +} + +void SpiFlashReadAnyLengthData(uint8_t* rData, uint32_t rAddr, uint16_t rLen) +{ +#ifdef FLASH_TEST + memcpy(rData, &flashtestbuff[rAddr], rLen); +#else + SpiFlashClrNss(); + SpiFlashSendByte(SPIFLASH_CMD_READ); + SpiFlashSendByte((rAddr >> 16) & 0x00FF); + SpiFlashSendByte((rAddr >> 8) & 0x00FF); + SpiFlashSendByte(rAddr & 0x00FF); + for(int i = 0; i < rLen; i++) { + rData[i] = SpiFlashReadByte(); + } + SpiFlashSetNss(); +#endif +} + +uint32_t SpiFlashReadId(void) +{ + uint32_t Temp = 0, Temp0 = 0, Temp1 = 0, Temp2 = 0; + SpiFlashClrNss(); + SpiFlashSendByte(0x9F); + Temp0 = SpiFlashReadByte(); + Temp1 = SpiFlashReadByte(); + Temp2 = SpiFlashReadByte(); + SpiFlashSetNss(); + Temp = (Temp0 << 16) | (Temp1 << 8) | Temp2; + return Temp; +} + +typedef struct { + uint16_t Flag; + uint16_t LoopSavFlag; //Ñ­»·´æ´¢±êÖ¾ + uint32_t LogCnt; //ÈÕÖ¾×î´óÊýÁ¿ + uint32_t FirstLogStartAddr; //µÚÒ»¸öÊý¾ÝµÄÆðʼµØÖ· + uint32_t LastLogEndAddr; //×îºóÒ»¸öÊý¾ÝµÄ½áÊøµØÖ· +}LogNumSav_t; + +static LogNumSav_t LogNumArray[256]; +static __IO uint32_t gLogCnt = 0; +static __IO uint32_t FirstLogStartAddr = 0; //µÚÒ»¸öÈÕÖ¾ÆðʼµØÖ· +static __IO uint32_t LastLogEndAddr = 0; //×îºóÒ»¸öÈÕÖ¾½áÊøµØÖ· +static __IO uint16_t LoopSavFlag = 0; //Ñ­»·´æ´¢±êÖ¾ +static uint16_t LogNumIdx; + +uint16_t ReadLoopSavFlag(void) +{ + return LoopSavFlag; +} + +void SetLoopSavFlag(uint16_t LoopFlag) +{ + LoopSavFlag = LoopFlag; +} + +uint32_t ReadLogNum(void) +{ + return gLogCnt; +} + +void SetLogNum(uint32_t LogCnt) +{ + gLogCnt = LogCnt; +} + +uint32_t ReadFirstLogStartAddr(void) +{ + return FirstLogStartAddr; +} + +void SetFirstLogStartAddr(uint32_t FLStartAddr) +{ + FirstLogStartAddr = FLStartAddr; +} + + +uint32_t ReadLastLogEndAddr(void) +{ + return LastLogEndAddr; +} + +void SetLastLogEndAddr(uint32_t LLEndAddr) +{ + LastLogEndAddr = LLEndAddr; +} + +void LogInit(void) +{ + LogNumIdx = 0xffff; + SpiFlashReadId(); + SpiFlashReadAnyLengthData((uint8_t *)&LogNumArray, LOG_INFO_START_SECTOR * SPIFLASH_SECTORSIZE, sizeof(LogNumArray)); + for(int i = 0; i < 256; i++) { + if(LogNumArray[i].Flag != LOG_INFO_SAV_FLAG) { + LogNumIdx = i; + break; + } + } + if(LogNumIdx == 0xffff) { //256Ìõ¼Ç¼Âú£¬¶Á×îºóÒ»Ìõ¼Ç¼ + LogNumIdx = 0; + SetLogNum(LogNumArray[255].LogCnt); + SetLoopSavFlag(LogNumArray[255].LoopSavFlag); + SetFirstLogStartAddr(LogNumArray[255].FirstLogStartAddr); + SetLastLogEndAddr(LogNumArray[255].LastLogEndAddr); + return; + } + if(LogNumIdx == 0) { //ûÓмǼ + LogNumIdx = 0; + SetLogNum(0); + SetLoopSavFlag(0); + SetFirstLogStartAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE); + SetLastLogEndAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE); + return; + } + SetLogNum(LogNumArray[LogNumIdx-1].LogCnt); + SetLoopSavFlag(LogNumArray[LogNumIdx-1].LoopSavFlag); + SetFirstLogStartAddr(LogNumArray[LogNumIdx-1].FirstLogStartAddr); + SetLastLogEndAddr(LogNumArray[LogNumIdx-1].LastLogEndAddr); +} + +void SavLogNum(uint32_t LogNum) +{ + LogNumSav_t CLogSav; + + if(LogNum == 0) { + LogNumIdx = 0; + SetLogNum(0); + SetLoopSavFlag(0); + SetFirstLogStartAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE); + SetLastLogEndAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE); + SpiFlashEraseSector(LOG_INFO_START_SECTOR * SPIFLASH_SECTORSIZE); + return; + } + + SetLogNum(LogNum); + CLogSav.Flag = LOG_INFO_SAV_FLAG; + CLogSav.LogCnt = LogNum; + CLogSav.FirstLogStartAddr = ReadFirstLogStartAddr(); + CLogSav.LastLogEndAddr = ReadLastLogEndAddr(); + + if(LogNumIdx == 256) { + SpiFlashEraseSector(LOG_INFO_START_SECTOR * SPIFLASH_SECTORSIZE); + LogNumIdx = 0; + } + SpiFlashWriteData((uint8_t *)&CLogSav, LogNumIdx * sizeof(LogNumSav_t) + LOG_INFO_START_SECTOR * SPIFLASH_SECTORSIZE, sizeof(LogNumSav_t)); + LogNumIdx++; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: CheckDelSecter +* ¹¦ÄÜÃèÊö: ¼ì²éÐèҪɾ³ýµÄÉÈÇø£¬¿çÉÈÇøɾ³ýÏÂÒ»ÉÈÇø£¬Èç¹ûµ½ÁËɾ³ý×îºóÒ»¸öÉÈÇø£¬Ñ­»·µ½ÆðʼÉÈÇø +* ²Î Êý: wAddr, дÈëµØÖ· + wLen, дÈ볤¶È +* ·µ »Ø Öµ: ·µ»ØдÈëÆðʼµØÖ· +*****************************************************************************************/ +uint8_t LogBuff[LOG_SAV_SIZE_MAX]; +const uint8_t SavFlag[4] ={0xAA, 0x55, 0x55, 0xAA}; +void CheckDelSecter(uint32_t wAddr, uint16_t wLen) +{ + uint32_t DelOffsetAddr, FindFirstLogAddr; //´æ´¢ÆðʼµØÖ· + uint32_t DelSectorNum = 0; + uint32_t SurplusSpace = SPIFLASH_SECTORSIZE - (wAddr % SPIFLASH_SECTORSIZE); + + if((wAddr + wLen) > SPIFLASH_SIZE) { + DelOffsetAddr = LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE; + SetLastLogEndAddr(DelOffsetAddr + wLen); + SetLoopSavFlag(1); + SpiFlashEraseSector(DelOffsetAddr); + FindFirstLogAddr = DelOffsetAddr + SPIFLASH_SECTORSIZE; + } + else { + if(wLen < SurplusSpace) { //³¤¶ÈûÓг¬¹ýÉÈÇøÊ£ÓàÈÝÁ¿ + SetLastLogEndAddr(wAddr + wLen); + return; + } + DelOffsetAddr = (wAddr / SPIFLASH_SECTORSIZE + 1) * SPIFLASH_SECTORSIZE; + DelSectorNum = (wLen - SurplusSpace) / SPIFLASH_SECTORSIZE + 1; + SetLastLogEndAddr(wAddr + wLen); + for(int i = 0; i < DelSectorNum; i++) { + SpiFlashEraseSector(DelOffsetAddr); + DelOffsetAddr += SPIFLASH_SECTORSIZE; + } + if(DelOffsetAddr == SPIFLASH_SIZE) { + DelOffsetAddr = LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE; + } + FindFirstLogAddr = DelOffsetAddr; + } + + if(!ReadLoopSavFlag()) + return; + + uint32_t ReadAddr = FindFirstLogAddr; + while(1) { + SpiFlashReadAnyLengthData(LogBuff, ReadAddr, LOG_SAV_SIZE_MAX); + int i; + for(i = 0; i < LOG_SAV_SIZE_MAX; i++) { + if(memcmp(&LogBuff[i], SavFlag, 4) == 0) { + SetFirstLogStartAddr(ReadAddr + i); + return;; + } + } + if(i == LOG_SAV_SIZE_MAX) { + ReadAddr += LOG_SAV_SIZE_MAX; + if(ReadAddr >= SPIFLASH_SIZE) { //ÕÒ²»µ½ÏÂÒ»ÌõÊý¾Ý£¬ÖØÖÃflash + Debug_Printf("Add LOG Error, Next Data No Find!\r\n"); + SetLogNum(0); + SetLoopSavFlag(0); + SetFirstLogStartAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE); + SetLastLogEndAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE); + return; + } + } + } +} + +uint8_t LogBuffTemp[LOG_SAV_SIZE_MAX]; +void AddLog(uint8_t *wData, uint32_t wLen) +{ + //const uint8_t SavFlag[4] ={0xAA, 0x55, 0x55, 0xAA}; + uint32_t LogNum; + uint32_t LogSize; + //uint32_t FLStartAddr; + uint32_t LLEndAddr; +// uint32_t SectorN; + LogHeader LogH; + + LogH = (LogHeader)LogBuffTemp; + + LogNum = ReadLogNum(); + if(LogNum == 0) { + SetFirstLogStartAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE); + SetLastLogEndAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE); + SpiFlashEraseSector(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE); + } + //FLStartAddr = ReadFirstLogStartAddr(); + LLEndAddr = ReadLastLogEndAddr(); + LogNum++; + LogH->LogSavFlag = LOG_SAV_FLAG; + LogH->LogIdx = LogNum; + LogSize = wLen + sizeof(LogHeader_t); + LogH->LogEndAddr = LLEndAddr + LogSize; + LogH->TimeStamp = TimeTs(); + memcpy(&LogBuffTemp[sizeof(LogHeader_t)], wData, wLen); + + //ÅжÏÊÇ·ñ¿çÉÈÇø£¬¿çÉÈÇøÐèÒªÏȲÁ³ýÏÂÒ»ÉÈÇø + CheckDelSecter(LLEndAddr, LogSize); + if(LogH->LogEndAddr > SPIFLASH_SIZE) { + LLEndAddr = LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE; + LogH->LogEndAddr = ReadLastLogEndAddr(); + } + SpiFlashWriteAnyLengthData(LogBuffTemp, LLEndAddr, LogSize); + + SavLogNum(LogNum); + //Debug_Printf("Add LOG: %d,endaddr = %d\r\n", LogNum, ReadLastLogEndAddr()); +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: ReadLog +* ¹¦ÄÜÃèÊö: ¶ÁÈ¡ÈÕÖ¾ +* ²Î Êý: Header, ÉÏÒ»°üÈÕ־ͷÐÅÏ¢£¬Á¬Ðø¶Áȡʱ´«ÈëÉÏÒ»°üÊý¾ÝÐÅÏ¢£¬Ëõ¶ÌÈÕÖ¾±éÀúʱ¼ä£¬ + Header->LogEndAddrΪ0¶ÁÈ¡µÚÒ»°üÊý¾Ý,LogIdxÊý¾ÝÎÞЧ + rData, ÈÕÖ¾³ö¿Ú£¬ÐèÒªÊÍ·Å + LogIdx, ¶ÁÈ¡µÄÈÕÖ¾µÄÐòºÅ£¬Îª0¶ÁÈ¡Header->LogEndAddr¶ÔÓ¦ÈÕÖ¾ +* ·µ »Ø Öµ: ·µ»ØÊý¾Ý³¤¶È +*****************************************************************************************/ +int ReadLog(LogHeader Header, uint8_t **rData, uint32_t LogIdx) +{ + uint32_t FSAddr; + int LogLen = 0; + //bool FirstIdx = false; + + if(Header == NULL) + return 0; + + if(Header->LogEndAddr == 0) { + Header->LogEndAddr = ReadFirstLogStartAddr(); + LogIdx = 0; + } + + if(LogIdx == 1) { + FSAddr = ReadFirstLogStartAddr(); + } + else + FSAddr = Header->LogEndAddr; + + while(1) { + SpiFlashReadAnyLengthData((uint8_t *)Header, FSAddr, sizeof(LogHeader_t)); + if(Header->LogSavFlag != LOG_SAV_FLAG) { + if((SPIFLASH_SIZE - FSAddr) < LOG_SAV_SIZE_MAX) { //ÅжÏÊÇ·ñµ½Æ¬Î² + FSAddr = LOG_SAV_START_SECTOR * SPIFLASH_SECTOR_NUM; + continue; + } + else + return 0; + } + if(LogIdx == 0) { + LogIdx = Header->LogIdx; + } + else if(Header->LogIdx != LogIdx) { + FSAddr = Header->LogEndAddr; + continue; + } + + if(Header->LogIdx == LogIdx) { + if(*rData == NULL) + return sizeof(LogHeader_t); + + SpiFlashReadAnyLengthData(LogBuffTemp, FSAddr, Header->LogEndAddr - FSAddr); + LogLen = Header->LogEndAddr - FSAddr - sizeof(LogHeader_t); + void *pTemp = rt_malloc(LogLen); + if(pTemp == NULL) + return 0; + + *rData =pTemp; + memcpy(*rData, &LogBuffTemp[sizeof(LogHeader_t)], LogLen); + break; + } + } + return LogLen; +} + + +/***************************************************************************************** +* º¯ÊýÃû³Æ: ReadPara +* ¹¦ÄÜÃèÊö: ¶ÁÈ¡²ÎÊý +* ²Î Êý: Para, Íø¹Ø²ÎÊý + ParaLen, ²ÎÊý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +int ReadPara(uint8_t *Para, uint32_t ParaLen) +{ + SpiFlashReadAnyLengthData(Para, GATEWEY_PARA_SAV_ADDR, ParaLen); //¶ÁȡƬβÊý¾Ý + uint16_t Check = CRC_Modbus(0xA001, Para, ParaLen - 2); + GWConfigPara CfgPara = (GWConfigPara)Para; + if(CfgPara->crc16 != Check) + return -1; + return 0; +} + +/***************************************************************************************** +* º¯ÊýÃû³Æ: WritePara +* ¹¦ÄÜÃèÊö: дÈë²ÎÊý +* ²Î Êý: Para, Íø¹Ø²ÎÊý + ParaLen, ²ÎÊý³¤¶È +* ·µ »Ø Öµ: ÎÞ +*****************************************************************************************/ +int WritePara(uint8_t *Para, uint32_t ParaLen) +{ + SpiFlashEraseSector(GATEWEY_PARA_SAV_ADDR); + + uint16_t Check = CRC_Modbus(0xA001, Para, ParaLen - 2); + GWConfigPara CfgPara = (GWConfigPara)Para; + CfgPara->crc16 = Check; + SpiFlashWriteAnyLengthData(Para, GATEWEY_PARA_SAV_ADDR, ParaLen); //¶ÁȡƬβÊý¾Ý + return 0; +} + +/* USER CODE END */ diff --git a/Project/GateWay/source/User/Src/update_protocol.c b/Project/GateWay/source/User/Src/update_protocol.c new file mode 100644 index 0000000..3bff818 --- /dev/null +++ b/Project/GateWay/source/User/Src/update_protocol.c @@ -0,0 +1,95 @@ +#include "update_protocol.h" +#include "string.h" +#include "public.h" + +static struct +{ + update_send_t pfnSend; + +}g_update_protoc; + + +void update_send_cmd(uint8_t Cmd, uint16_t Indx, int PageNum) +{ + uint8_t sData[24]={0}; + uint8_t sLen =0; + uint16_t crc16; + + update_protocol_hd_t *Frame = (update_protocol_hd_t*)sData; + + Frame->Header = 0x7a; + Frame->SlvAddr = 0x01; + Frame->Cmd = Cmd; + + if (Cmd == 0x01) + { + Frame->PayloadLen = 1; + sData[sizeof(update_protocol_hd_t)] = Indx; + } + else if (Cmd == 0x02) + { + Frame->PayloadLen = 4; + update_protocol_get_t *GDData = (update_protocol_get_t*)&sData[sizeof(update_protocol_hd_t)]; + GDData->PackageIndex = Indx; + GDData->PackageNum = PageNum; + } + + sLen = sizeof(update_protocol_hd_t) + Frame->PayloadLen; + crc16 = CRC_Modbus(CRC16_BASE, sData, sLen); + sData[sLen++] = crc16; + sData[sLen++] = (crc16 >> 8) & 0x00ff; + + g_update_protoc.pfnSend(sData, sLen); +} + +void update_init(update_send_t pCbs) +{ + g_update_protoc.pfnSend =pCbs; +} + + +int update_unpack(uint8_t* rxData, int rLen,uint8_t *cmd, uint8_t* dev_addr, void *pload, int *pLen){ + + uint16_t crc16; + + uint16_t check; + + check = CRC_Modbus(CRC16_BASE, rxData, rLen - 2); + + crc16 = (rxData[rLen - 1] << 8) | rxData[rLen - 2]; + + if (check != crc16 || rxData[0] !=0x7a || pload ==0) + { + return -1; + } + + update_protocol_hd_t *Frame = (update_protocol_hd_t*)rxData; + + *dev_addr = Frame->SlvAddr; + + *cmd = Frame->Cmd; + + if (Frame->Cmd == 0x81){ + + //update_protocol_req_t *UpData = (update_protocol_req_t*)&rxData[sizeof(update_protocol_hd_t)]; + + pload = 0; + + *pLen = 0; + + + }else if (Frame->Cmd == 0x82){ + + update_protocol_rsp_t *DownData = (update_protocol_rsp_t *)&rxData[sizeof(update_protocol_hd_t)]; + + memcpy(pload , &rxData[sizeof(update_protocol_hd_t) + sizeof(update_protocol_rsp_t)],DownData->DataLen); + + *pLen = DownData->DataLen; + + }else{ + + return -2; + } + + return 0; +} diff --git a/Project/GateWay/source/User/Src/utils.c b/Project/GateWay/source/User/Src/utils.c new file mode 100644 index 0000000..c04477f --- /dev/null +++ b/Project/GateWay/source/User/Src/utils.c @@ -0,0 +1,43 @@ +#include "utils.h" + +/* +生æˆå¤šé¡¹å¼ (x^16 + x^15 + x^2 + 1） +*/ +uint16_t modbus_crc16(uint8_t* data, int length) +{ + + uint16_t crc = 0xFFFF; // åˆå§‹å€¼FFFF + uint16_t polynomial = 0x8005; // 多项å¼8005 + + for (int i = 0; i < length; i++) { + // 输入å转(REFIN)：对æ¯ä¸ªå­—节进行ä½å转 + uint8_t byte = data[i]; + uint8_t reversed_byte = 0; + + for (int j = 0; j < 8; j++) { + reversed_byte = (reversed_byte << 1) | (byte & 0x01); + byte >>= 1; + } + + crc ^= (reversed_byte << 8); // 与高字节异或 + + for (int j = 0; j < 8; j++) { + if (crc & 0x8000) { // æ£€æŸ¥æœ€é«˜ä½ + crc = (crc << 1) ^ polynomial; + } else { + crc <<= 1; + } + } + } + + // 输出å转(REFOUT)：对16ä½CRC结果进行ä½å转 + uint16_t reversed_crc = 0; + + for (int i = 0; i < 16; i++) { + reversed_crc = (reversed_crc << 1) | (crc & 0x0001); + crc >>= 1; + } + + // 结果异或值(XOROUT)：0000（实际ä¸å˜ï¼‰ + return reversed_crc ^ 0x0000; +} diff --git a/README.md b/README.md index e0d5a97..4db8152 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,3 @@ # GateWay +一代网关 \ No newline at end of file diff --git a/driver/inc/hc32f460_adc.h b/driver/inc/hc32f460_adc.h new file mode 100644 index 0000000..edaf0b9 --- /dev/null +++ b/driver/inc/hc32f460_adc.h @@ -0,0 +1,509 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_adc.h + ** + ** A detailed description is available at + ** @link AdcGroup Adc description @endlink + ** + ** - 2018-11-30 CDT First version for Device Driver Library of Adc. + ** + ******************************************************************************/ +#ifndef __HC32F460_ADC_H__ +#define __HC32F460_ADC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_ADC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup AdcGroup Analog-to-Digital Converter(ADC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief ADC average count. + ** + ******************************************************************************/ +typedef enum en_adc_avcnt +{ + AdcAvcnt_2 = 0x0, ///< Average after 2 conversions. + AdcAvcnt_4 = 0x1, ///< Average after 4 conversions. + AdcAvcnt_8 = 0x2, ///< Average after 8 conversions. + AdcAvcnt_16 = 0x3, ///< Average after 16 conversions. + AdcAvcnt_32 = 0x4, ///< Average after 32 conversions. + AdcAvcnt_64 = 0x5, ///< Average after 64 conversions. + AdcAvcnt_128 = 0x6, ///< Average after 128 conversions. + AdcAvcnt_256 = 0x7, ///< Average after 256 conversions. +} en_adc_avcnt_t; + +/** + ******************************************************************************* + ** \brief ADC data alignment + ** + ******************************************************************************/ +typedef enum en_adc_data_align +{ + AdcDataAlign_Right = 0x0, ///< Data right alignment. + AdcDataAlign_Left = 0x1, ///< Data left alignment. +} en_adc_data_align_t; + +/** + ******************************************************************************* + ** \brief Automatically clear data registers after reading data. + ** The auto clear function is mainly used to detect whether the data register + ** is updated. + ** + ******************************************************************************/ +typedef enum en_adc_clren +{ + AdcClren_Disable = 0x0, ///< Automatic clear function disable. + AdcClren_Enable = 0x1, ///< Automatic clear function enable. +} en_adc_clren_t; + +/** + ******************************************************************************* + ** \brief ADC resolution. + ** + ******************************************************************************/ +typedef enum en_adc_resolution +{ + AdcResolution_12Bit = 0x0, ///< Resolution is 12 bit. + AdcResolution_10Bit = 0x1, ///< Resolution is 10 bit. + AdcResolution_8Bit = 0x2, ///< Resolution is 8 bit. +} en_adc_resolution_t; + +/** + ******************************************************************************* + ** \brief ADC scan mode. + ** + ******************************************************************************/ +typedef enum en_adc_scan_mode +{ + AdcMode_SAOnce = 0x0, ///< Sequence A works once. + AdcMode_SAContinuous = 0x1, ///< Sequence A works always. + AdcMode_SAOnceSBOnce = 0x2, ///< Sequence A and sequence B work once. + AdcMode_SAContinuousSBOnce = 0x3, ///< Sequence A works always, sequence works once. +} en_adc_scan_mode_t; + +/** + ******************************************************************************* + ** \brief ADC sequence A restart position. + ** + ******************************************************************************/ +typedef enum en_adc_rschsel +{ + AdcRschsel_Continue = 0x0, ///< After sequence A is interrupted by sequence B, + ///< sequence A continues to scan from the interrupt + ///< when it restarts. + + AdcRschsel_Restart = 0x1, ///< After sequence A is interrupted by sequence B, + ///< sequence A restarts scanning from the first channel + ///< when it restarts. +} en_adc_rschsel_t; + +/** + ******************************************************************************* + ** \brief ADC external or internal trigger source enable/disable . + ** + ******************************************************************************/ +typedef enum en_adc_trgen +{ + AdcTrgen_Disable = 0x0, ///< External or internal trigger source disable. + AdcTrgen_Enable = 0x1, ///< External or internal trigger source enable. +} en_adc_trgen_t; + +/** + ******************************************************************************* + ** \brief ADC sequence trigger source selection. + ** + ******************************************************************************/ +typedef enum en_adc_trgsel +{ + AdcTrgsel_ADTRGX = 0x0, ///< X = 1(use ADC1) / 2(use ADC2), same as below. + AdcTrgsel_TRGX0 = 0x1, ///< Pin IN_TRG10 / IN_TRG20. + AdcTrgsel_TRGX1 = 0x2, ///< Pin IN_TRG11 / IN_TRG21. + AdcTrgsel_TRGX0_TRGX1 = 0x3, ///< Pin IN_TRG10 + IN_TRG11 / IN_TRG20 + IN_TRG21. +} en_adc_trgsel_t; + +/** + ******************************************************************************* + ** \brief Sequence A/B conversion completion interrupt enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_eocien +{ + AdcEocien_Disable = 0x0, ///< Conversion completion interrupt disable. + AdcEocien_Enable = 0x1, ///< Conversion completion interrupt enable. +} en_adc_eocien_t; + +/** + ******************************************************************************* + ** \brief ADC sync mode. + ** + ******************************************************************************/ +typedef enum en_adc_sync_mode +{ + AdcSync_SingleSerial = 0x0u, ///< Single: ADC1 and ADC2 only sample and convert once after triggering. + ///< Serial: ADC2 start after ADC1 N PCLK4 cycles. + AdcSync_SingleParallel = 0x2u, ///< Parallel: ADC1 and ADC2 start at the same time. + AdcSync_ContinuousSerial = 0x4u, ///< Continuous: ADC1 and ADC2 continuously sample and convert after triggering. + AdcSync_ContinuousParallel = 0x6u, +} en_adc_sync_mode_t; + +/** + ******************************************************************************* + ** \brief ADC sync enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_syncen +{ + AdcSync_Disable = 0x0, ///< Disable sync mode. + AdcSync_Enable = 0x1, ///< Enable sync mode. +} en_adc_syncen_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog interrupt enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_awdien +{ + AdcAwdInt_Disable = 0x0, ///< Disable AWD interrupt. + AdcAwdInt_Enable = 0x1, ///< Enable AWD interrupt. +} en_adc_awdien_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog interrupt event sequence selection. + ** + ******************************************************************************/ +typedef enum en_adc_awdss +{ + AdcAwdSel_SA_SB = 0x0, ///< Sequence A and B output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SA = 0x1, ///< Sequence A output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SB = 0x2, ///< Sequence B output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SB_SA = 0x3, ///< Same as AdcAwdSel_SA_SB. +} en_adc_awdss_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog comparison mode selection. + ** + ******************************************************************************/ +typedef enum en_adc_awdmd +{ + AdcAwdCmpMode_0 = 0x0, ///< Upper limit is AWDDR0, lower limit is AWDDR1. + ///< If AWDDR0 > result or result > AWDDR1, + ///< the interrupt will be occur. + + AdcAwdCmpMode_1 = 0x1, ///< The range is [AWDDR0, AWDDR1]. + ///< If AWDDR0 <= result <= AWDDR1, the interrupt will be occur. +} en_adc_awdmd_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_awden +{ + AdcAwd_Disable = 0x0, ///< Disable AWD. + AdcAwd_Enable = 0x1, ///< Enable AWD. +} en_adc_awden_t; + +/** + ******************************************************************************* + ** \brief PGA control. + ** + ******************************************************************************/ +typedef enum en_adc_pga_ctl +{ + AdcPgaCtl_Invalid = 0x0, ///< Amplifier is invalid. + AdcPgaCtl_Amplify = 0xE, ///< Amplifier effective. +} en_adc_pga_ctl_t; + +/** + ******************************************************************************* + ** \brief The amplification factor of the amplifier is as follows. + ** + ******************************************************************************/ +typedef enum en_adc_pga_factor +{ + AdcPgaFactor_2 = 0x0, ///< PGA magnification 2. + AdcPgaFactor_2P133 = 0x1, ///< PGA magnification 2.133. + AdcPgaFactor_2P286 = 0x2, ///< PGA magnification 2.286. + AdcPgaFactor_2P667 = 0x3, ///< PGA magnification 2.667. + AdcPgaFactor_2P909 = 0x4, ///< PGA magnification 2.909. + AdcPgaFactor_3P2 = 0x5, ///< PGA magnification 3.2. + AdcPgaFactor_3P556 = 0x6, ///< PGA magnification 3.556. + AdcPgaFactor_4 = 0x7, ///< PGA magnification 4. + AdcPgaFactor_4P571 = 0x8, ///< PGA magnification 4.571. + AdcPgaFactor_5P333 = 0x9, ///< PGA magnification 5.333. + AdcPgaFactor_6P4 = 0xA, ///< PGA magnification 6.4. + AdcPgaFactor_8 = 0xB, ///< PGA magnification 8. + AdcPgaFactor_10P667 = 0xC, ///< PGA magnification 10.667. + AdcPgaFactor_16 = 0xD, ///< PGA magnification 16. + AdcPgaFactor_32 = 0xE, ///< PGA magnification 32. +} en_adc_pga_factor_t; + +/** + ******************************************************************************* + ** \brief Negative phase input selection + ** + ******************************************************************************/ +typedef enum en_adc_pga_negative +{ + AdcPgaNegative_PGAVSS = 0x0, ///< Use external port PGAVSS as PGA negative input. + AdcPgaNegative_VSSA = 0x1, ///< Use internal analog ground VSSA as PGA negative input. +} en_adc_pga_negative_t; + +/** + ******************************************************************************* + ** \brief ADC common trigger source select + ** + ******************************************************************************/ +typedef enum en_adc_com_trigger +{ + AdcComTrigger_1 = 0x1, ///< Select common trigger 1. + AdcComTrigger_2 = 0x2, ///< Select common trigger 2. + AdcComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_adc_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Structure definition of ADC + ** + ******************************************************************************/ +typedef struct stc_adc_ch_cfg +{ + uint32_t u32Channel; ///< ADC channels mask. + uint8_t u8Sequence; ///< The sequence which the channel(s) belong to. + uint8_t *pu8SampTime; ///< Pointer to sampling time. +} stc_adc_ch_cfg_t; + +typedef struct stc_adc_awd_cfg +{ + en_adc_awdmd_t enAwdmd; ///< Comparison mode of the values. + en_adc_awdss_t enAwdss; ///< Interrupt output select. + uint16_t u16AwdDr0; ///< Your range DR0. + uint16_t u16AwdDr1; ///< Your range DR1. +} stc_adc_awd_cfg_t; + +typedef struct stc_adc_trg_cfg +{ + uint8_t u8Sequence; ///< The sequence will be configured trigger source. + en_adc_trgsel_t enTrgSel; ///< Trigger source type. + en_event_src_t enInTrg0; ///< Internal trigger 0 source number + ///< (event number @ref en_event_src_t). + en_event_src_t enInTrg1; ///< Internal trigger 1 source number + ///< (event number @ref en_event_src_t). +} stc_adc_trg_cfg_t; + +typedef struct stc_adc_init +{ + en_adc_resolution_t enResolution; ///< ADC resolution 12bit/10bit/8bit. + en_adc_data_align_t enDataAlign; ///< ADC data alignment. + en_adc_clren_t enAutoClear; ///< Automatically clear data register. + ///< after reading data register(enable/disable). + en_adc_scan_mode_t enScanMode; ///< ADC scan mode. + en_adc_rschsel_t enRschsel; ///< Restart or continue. +} stc_adc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief ADC sequence definition. + ** + ******************************************************************************/ +/* ADC sequence definition */ +#define ADC_SEQ_A ((uint8_t)0) +#define ADC_SEQ_B ((uint8_t)1) + +/* ADC pin definition */ +#define ADC1_IN0 ((uint8_t)0) +#define ADC1_IN1 ((uint8_t)1) +#define ADC1_IN2 ((uint8_t)2) +#define ADC1_IN3 ((uint8_t)3) +#define ADC12_IN4 ((uint8_t)4) +#define ADC12_IN5 ((uint8_t)5) +#define ADC12_IN6 ((uint8_t)6) +#define ADC12_IN7 ((uint8_t)7) +#define ADC12_IN8 ((uint8_t)8) +#define ADC12_IN9 ((uint8_t)9) +#define ADC12_IN10 ((uint8_t)10) +#define ADC12_IN11 ((uint8_t)11) +#define ADC1_IN12 ((uint8_t)12) +#define ADC1_IN13 ((uint8_t)13) +#define ADC1_IN14 ((uint8_t)14) +#define ADC1_IN15 ((uint8_t)15) +#define ADC_PIN_INVALID ((uint8_t)0xFF) + +/* ADC channel index definition */ +#define ADC_CH_IDX0 (0u) +#define ADC_CH_IDX1 (1u) +#define ADC_CH_IDX2 (2u) +#define ADC_CH_IDX3 (3u) +#define ADC_CH_IDX4 (4u) +#define ADC_CH_IDX5 (5u) +#define ADC_CH_IDX6 (6u) +#define ADC_CH_IDX7 (7u) +#define ADC_CH_IDX8 (8u) +#define ADC_CH_IDX9 (9u) +#define ADC_CH_IDX10 (10u) +#define ADC_CH_IDX11 (11u) +#define ADC_CH_IDX12 (12u) +#define ADC_CH_IDX13 (13u) +#define ADC_CH_IDX14 (14u) +#define ADC_CH_IDX15 (15u) +#define ADC_CH_IDX16 (16u) + +/* ADC1 channel mask definition */ +#define ADC1_CH0 (0x1ul << 0u) ///< Default mapping pin ADC1_IN0 +#define ADC1_CH1 (0x1ul << 1u) ///< Default mapping pin ADC1_IN1 +#define ADC1_CH2 (0x1ul << 2u) ///< Default mapping pin ADC1_IN2 +#define ADC1_CH3 (0x1ul << 3u) ///< Default mapping pin ADC1_IN3 +#define ADC1_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN4 +#define ADC1_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN5 +#define ADC1_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN6 +#define ADC1_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN7 +#define ADC1_CH8 (0x1ul << 8u) ///< Default mapping pin ADC12_IN8 +#define ADC1_CH9 (0x1ul << 9u) ///< Default mapping pin ADC12_IN9 +#define ADC1_CH10 (0x1ul << 10u) ///< Default mapping pin ADC12_IN10 +#define ADC1_CH11 (0x1ul << 11u) ///< Default mapping pin ADC12_IN11 +#define ADC1_CH12 (0x1ul << 12u) ///< Default mapping pin ADC12_IN12 +#define ADC1_CH13 (0x1ul << 13u) ///< Default mapping pin ADC12_IN13 +#define ADC1_CH14 (0x1ul << 14u) ///< Default mapping pin ADC12_IN14 +#define ADC1_CH15 (0x1ul << 15u) ///< Default mapping pin ADC12_IN15 +#define ADC1_CH16 (0x1ul << 16u) +#define ADC1_CH_INTERNAL (ADC1_CH16) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC +#define ADC1_CH_ALL (0x0001FFFFul) +#define ADC1_PIN_MASK_ALL (ADC1_CH_ALL & ~ADC1_CH_INTERNAL) + +/* ADC2 channel definition */ +#define ADC2_CH0 (0x1ul << 0u) ///< Default mapping pin ADC12_IN4 +#define ADC2_CH1 (0x1ul << 1u) ///< Default mapping pin ADC12_IN5 +#define ADC2_CH2 (0x1ul << 2u) ///< Default mapping pin ADC12_IN6 +#define ADC2_CH3 (0x1ul << 3u) ///< Default mapping pin ADC12_IN7 +#define ADC2_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN8 +#define ADC2_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN9 +#define ADC2_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN10 +#define ADC2_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN11 +#define ADC2_CH8 (0x1ul << 8u) +#define ADC2_CH_INTERNAL (ADC2_CH8) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC +#define ADC2_CH_ALL (0x000001FFul) +#define ADC2_PIN_MASK_ALL (ADC2_CH_ALL & ~ADC2_CH_INTERNAL) + +/* +* PGA channel definition. +* NOTE: The PGA channel directly maps external pins and does not correspond to the ADC channel. +*/ +#define PGA_CH0 (0x1ul << ADC1_IN0) ///< Mapping pin ADC1_IN0 +#define PGA_CH1 (0x1ul << ADC1_IN1) ///< Mapping pin ADC1_IN1 +#define PGA_CH2 (0x1ul << ADC1_IN2) ///< Mapping pin ADC1_IN2 +#define PGA_CH3 (0x1ul << ADC1_IN3) ///< Mapping pin ADC1_IN3 +#define PGA_CH4 (0x1ul << ADC12_IN4) ///< Mapping pin ADC12_IN4 +#define PGA_CH5 (0x1ul << ADC12_IN5) ///< Mapping pin ADC12_IN5 +#define PGA_CH6 (0x1ul << ADC12_IN6) ///< Mapping pin ADC12_IN6 +#define PGA_CH7 (0x1ul << ADC12_IN7) ///< Mapping pin ADC12_IN7 +#define PGA_CH8 (0x1ul << ADC12_IN8) ///< Mapping internal 8bit DAC1 output +#define PGA_CH_ALL (0x000001FFul) + +/* ADC1 has up to 17 channels */ +#define ADC1_CH_COUNT (17u) + +/* ADC2 has up to 9 channels */ +#define ADC2_CH_COUNT (9u) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit); +en_result_t ADC_DeInit(M4_ADC_TypeDef *ADCx); + +en_result_t ADC_SetScanMode(M4_ADC_TypeDef *ADCx, en_adc_scan_mode_t enMode); +en_result_t ADC_ConfigTriggerSrc(M4_ADC_TypeDef *ADCx, const stc_adc_trg_cfg_t *pstcTrgCfg); +en_result_t ADC_TriggerSrcCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState); +void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, en_adc_trgsel_t enTrgSel, \ + en_adc_com_trigger_t enComTrigger, en_functional_state_t enState); + +en_result_t ADC_AddAdcChannel(M4_ADC_TypeDef *ADCx, const stc_adc_ch_cfg_t *pstcChCfg); +en_result_t ADC_DelAdcChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_SeqITCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState); + +en_result_t ADC_ConfigAvg(M4_ADC_TypeDef *ADCx, en_adc_avcnt_t enAvgCnt); +en_result_t ADC_AddAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_DelAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); + +en_result_t ADC_ConfigAwd(M4_ADC_TypeDef *ADCx, const stc_adc_awd_cfg_t *pstcAwdCfg); +en_result_t ADC_AwdCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState); +en_result_t ADC_AwdITCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState); +en_result_t ADC_AddAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_DelAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); + +void ADC_ConfigPga(en_adc_pga_factor_t enFactor, en_adc_pga_negative_t enNegativeIn); +void ADC_PgaCmd(en_functional_state_t enState); +void ADC_AddPgaChannel(uint32_t u32Channel); +void ADC_DelPgaChannel(uint32_t u32Channel); + +void ADC_ConfigSync(en_adc_sync_mode_t enMode, uint8_t u8TrgDelay); +void ADC_SyncCmd(en_functional_state_t enState); + +en_result_t ADC_StartConvert(M4_ADC_TypeDef *ADCx); +en_result_t ADC_StopConvert(M4_ADC_TypeDef *ADCx); +en_flag_status_t ADC_GetEocFlag(const M4_ADC_TypeDef *ADCx, uint8_t u8Seq); +void ADC_ClrEocFlag(M4_ADC_TypeDef *ADCx, uint8_t u8Seq); +en_result_t ADC_PollingSa(M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length, uint32_t u32Timeout); + +en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length); +en_result_t ADC_GetChData(const M4_ADC_TypeDef *ADCx, uint32_t u32TargetCh, uint16_t *pu16AdcData, uint8_t u8Length); +uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex); + +uint32_t ADC_GetAwdFlag(const M4_ADC_TypeDef *ADCx); +void ADC_ClrAwdFlag(M4_ADC_TypeDef *ADCx); +void ADC_ClrAwdChFlag(M4_ADC_TypeDef *ADCx, uint32_t u32AwdCh); + +en_result_t ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, uint32_t u32DestChannel, uint8_t u8AdcPin); +uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex); + +//@} // AdcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_ADC_ENABLE */ + +#endif /* __HC32F460_ADC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_aes.h b/driver/inc/hc32f460_aes.h new file mode 100644 index 0000000..eca2f48 --- /dev/null +++ b/driver/inc/hc32f460_aes.h @@ -0,0 +1,81 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_aes.h + ** + ** A detailed description is available at + ** @link AesGroup Aes description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Aes. + ** + ******************************************************************************/ +#ifndef __HC32F460_AES_H__ +#define __HC32F460_AES_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_AES_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup AesGroup Advanced Encryption Standard(AES) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + /* AES key length in bytes is 16. */ +#define AES_KEYLEN ((uint8_t)16) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t AES_Encrypt(const uint8_t *pu8Plaintext, + uint32_t u32PlaintextSize, + const uint8_t *pu8Key, + uint8_t *pu8Ciphertext); + +en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext, + uint32_t u32CiphertextSize, + const uint8_t *pu8Key, + uint8_t *pu8Plaintext); + +//@} // AesGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_AES_ENABLE */ + +#endif /* __HC32F460_AES_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_can.h b/driver/inc/hc32f460_can.h new file mode 100644 index 0000000..34e689a --- /dev/null +++ b/driver/inc/hc32f460_can.h @@ -0,0 +1,518 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_can.h + ** + ** A detailed description is available at + ** @link CanGroup CAN description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of CAN + ** + ******************************************************************************/ +#ifndef __HC32F460_CAN_H__ +#define __HC32F460_CAN_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CAN_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CanGroup Controller Area Network(CAN) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief The Can error types. + ******************************************************************************/ +typedef enum +{ + NO_ERROR = 0U, + BIT_ERROR = 1U, + FORM_ERROR = 2U, + STUFF_ERROR = 3U, + ACK_ERROR = 4U, + CRC_ERROR = 5U, + UNKOWN_ERROR = 6U, +}en_can_error_t; + +/** + ******************************************************************************* + ** \brief The Can transmit buffer select.(TCMD) + ******************************************************************************/ +typedef enum +{ + CanPTBSel = 0U, ///< high-priority buffer + CanSTBSel = 1U, ///< secondary buffer +}en_can_buffer_sel_t; + +/** + ******************************************************************************* + ** \brief The Can warning limits.(AFWL) + ******************************************************************************/ +typedef struct stc_can_warning_limit +{ + uint8_t CanWarningLimitVal; ///< Receive buffer almost full warning limit + uint8_t CanErrorWarningLimitVal; ///< Programmable error warning limit +}stc_can_warning_limit_t; + +/** + ******************************************************************************* + ** \brief The Acceptance Filters Frame Format Check.(ACF) + ******************************************************************************/ +typedef enum en_can_acf_format_en +{ + CanStdFrames = 0x02u, ///< Accepts only Standard frames + CanExtFrames = 0x03u, ///< Accepts only Extended frames + CanAllFrames = 0x00u, ///< Accepts both standard or extended frames +}en_can_acf_format_en_t; + +/** + ******************************************************************************* + ** \brief The Acceptance Filters Enable.(ACFEN) + ******************************************************************************/ +typedef enum en_can_filter_sel +{ + CanFilterSel1 = 0u, ///< The Acceptance Filter 1 Enable + CanFilterSel2 = 1u, ///< The Acceptance Filter 2 Enable + CanFilterSel3 = 2u, ///< The Acceptance Filter 3 Enable + CanFilterSel4 = 3u, ///< The Acceptance Filter 4 Enable + CanFilterSel5 = 4u, ///< The Acceptance Filter 5 Enable + CanFilterSel6 = 5u, ///< The Acceptance Filter 6 Enable + CanFilterSel7 = 6u, ///< The Acceptance Filter 7 Enable + CanFilterSel8 = 7u, ///< The Acceptance Filter 8 Enable +}en_can_filter_sel_t; + +/** + ******************************************************************************* + ** \brief The can interrupt enable.(IE) + ******************************************************************************/ +typedef enum +{ + //<empty and =almost full, but not full and no overflow + CanRxBufFull = 3, ///< full +}en_can_rx_buf_status_t; + +/** + ******************************************************************************* + ** \brief The Can Transmission secondary Status.(TSSTAT) + ******************************************************************************/ +typedef enum +{ + CanTxBufEmpty = 0, ///< TTEN=0 or TTTBM=0: STB is empty + ///< TTEN=1 and TTTBM=1: PTB and STB are empty + CanTxBufnotHalfFull = 1, ///< TTEN=0 or TTTBM=0: STB is less than or equal to half full + ///< TTEN=1 and TTTBM=1: PTB and STB are not empty and not full + CanTxBufHalfFull = 2, ///< TTEN=0 or TTTBM=0: STB is more than half full + ///< TTEN=1 and TTTBM=1: None + CanTxBufFull = 3, ///< TTEN=0 or TTTBM=0: STB is full + ///< TTEN=1 and TTTBM=1: PTB and STB are full +}en_can_tx_buf_status_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Acceptance Filter Code and Mask. + ******************************************************************************/ +typedef struct stc_can_filter +{ + uint32_t u32CODE; ///< Acceptance CODE + uint32_t u32MASK; ///< Acceptance MASK + en_can_filter_sel_t enFilterSel; ///< The Acceptance Filters Enable + en_can_acf_format_en_t enAcfFormat; ///< The Acceptance Filters Frame Format Check. +}stc_can_filter_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Bit Timing. + ******************************************************************************/ +typedef struct stc_can_bt +{ + uint8_t SEG_1; ///< Bit timing segment 1(Tseg_1 = (SEG_1 + 2)*TQ) + uint8_t SEG_2; ///< Bit timing segment 2(Tseg_2 = (SEG_2 + 1)*TQ) + uint8_t SJW; ///< Synchronization jump width(Tsjw = (SJW + 1)*TQ) + uint8_t PRESC; ///< The Prescaler divides the system clock to get the time quanta clock tq_clk(TQ) +}stc_can_bt_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Control Frame. + ******************************************************************************/ +typedef struct +{ + uint32_t DLC : 4; ///< Data length code + uint32_t RESERVED0 : 2; ///< Ignore + uint32_t RTR : 1; ///< Remote transmission request + uint32_t IDE : 1; ///< IDentifier extension + uint32_t RESERVED1 : 24; ///< Ignore +}stc_can_txcontrol_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Tx Frame. + ******************************************************************************/ +typedef struct stc_can_txframe +{ + union + { + uint32_t TBUF32_0; ///< Ignore + uint32_t StdID; ///< Standard ID + uint32_t ExtID; ///< Extended ID + }; + union + { + uint32_t TBUF32_1; ///< Ignore + stc_can_txcontrol_t Control_f; ///< CAN Tx Control + }; + union + { + uint32_t TBUF32_2[2]; ///< Ignore + uint8_t Data[8]; ///< CAN data + }; + en_can_buffer_sel_t enBufferSel; ///< CAN Tx buffer select +}stc_can_txframe_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx Ctrl. + ******************************************************************************/ +typedef struct +{ + uint8_t DLC : 4; ///< Data length code + uint8_t RESERVED0 : 2; ///< Ignore + uint8_t RTR : 1; ///< Remote transmission request + uint8_t IDE : 1; ///< IDentifier extension +}stc_can_rxcontrol_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN status. + ******************************************************************************/ +typedef struct +{ + uint8_t RESERVED0 : 4; ///< Ignore + uint8_t TX : 1; ///< TX is set to 1 if the loop back mode is activated + uint8_t KOER : 3; ///< Kind of error +}stc_can_status_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN control, status and cycletime. + ******************************************************************************/ +typedef struct +{ + stc_can_rxcontrol_t Control_f; ///< @ref stc_can_rxcontrol_t + stc_can_status_t Status_f; ///< @ref stc_can_status_t + uint16_t CycleTime; ///< TTCAN cycletime +}stc_can_cst_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx frame. + ******************************************************************************/ +typedef struct stc_can_rxframe +{ + union + { + uint32_t RBUF32_0; ///< Ignore + uint32_t StdID; ///< Standard ID + uint32_t ExtID; ///< Extended ID + }; + union + { + uint32_t RBUF32_1; ///< Ignore + stc_can_cst_t Cst; ///< @ref stc_can_cst_t + }; + union + { + uint32_t RBUF32_2[2]; ///< Ignore + uint8_t Data[8]; ///< CAN data + }; +}stc_can_rxframe_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx frame. + ******************************************************************************/ +typedef struct stc_can_init_config +{ + en_can_rx_buf_all_t enCanRxBufAll; ///< @ref en_can_rx_buf_all_t + en_can_rx_buf_mode_en_t enCanRxBufMode; ///< @ref en_can_rx_buf_mode_en_t + en_can_self_ack_en_t enCanSAck; ///< @ref en_can_self_ack_en_t + en_can_stb_mode_t enCanSTBMode; ///< @ref en_can_stb_mode_t + stc_can_bt_t stcCanBt; ///< @ref stc_can_bt_t + stc_can_warning_limit_t stcWarningLimit; ///< @ref stc_can_warning_limit_t + stc_can_filter_t *pstcFilter; ///< @ref stc_can_filter_t Pointer to a stc_can_filter_t type array that \ + ///< contains the configuration informations of the acceptance filters. + uint8_t u8FilterCount; ///< Number of filters that to to initialized. +}stc_can_init_config_t; + +/** + ******************************************************************************* + ** \brief CAN TTCAN + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN pointer to a TB message slot + ******************************************************************************/ +typedef enum +{ + CanTTcanPTBSel = 0x00u, ///< PTB + CanTTcanSTB1Sel = 0x01u, ///< STB1 + CanTTcanSTB2Sel = 0x02u, ///< STB2 + CanTTcanSTB3Sel = 0x03u, ///< STB3 + CanTTcanSTB4Sel = 0x04u, ///< STB4 +}en_can_ttcan_tbslot_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN Timer prescaler + ******************************************************************************/ +typedef enum +{ + CanTTcanTprescDiv1 = 0x00u, ///< Div1 + CanTTcanTprescDiv2 = 0x01u, ///< Div2 + CanTTcanTprescDiv3 = 0x02u, ///< Div3 + CanTTcanTprescDiv4 = 0x03u, ///< Div4 +}en_can_ttcan_Tpresc_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN Trigger type + ******************************************************************************/ +typedef enum +{ + CanTTcanImmediate = 0x00, ///< Immediate trigger for immediate transmission + CanTTcanTime = 0x01, ///< Time trigger for receive trigger + CanTTcanSingle = 0x02, ///< Single shot transmit trigger for exclusive time windows + CanTTcanTransStart = 0x03, ///< Transmit start trigger for merged arbitrating time windows + CanTTcanTransStop = 0x04, ///< Transmit stop trigger for merged arbitrating time windows +}en_can_ttcan_trigger_type_t; + +typedef enum +{ + CanTTcanWdtTriggerIrq = 0x80, ///< Watch trigger interrupt + CanTTcanTimTriggerIrq = 0x10, ///< Time trigger interrupt +}en_can_ttcan_irq_type_t; + + +typedef struct stc_can_ttcan_ref_msg +{ + uint8_t u8IDE; ///< Reference message IDE:1-Extended; 0-Standard; + union ///< Reference message ID + { + uint32_t RefStdID; ///< Reference standard ID + uint32_t RefExtID; ///< Reference Extended ID + }; +}stc_can_ttcan_ref_msg_t; + +typedef struct stc_can_ttcan_trigger_config +{ + en_can_ttcan_tbslot_t enTbSlot; ///< Transmit trigger TB slot pointer + en_can_ttcan_trigger_type_t enTrigType; ///< Trigger type + en_can_ttcan_Tpresc_t enTpresc; ///< Timer prescaler + uint8_t u8Tew; ///< Transmit enable window + uint16_t u16TrigTime; ///< TTCAN trigger time + uint16_t u16WatchTrigTime; ///< TTCAN watch trigger time register +}stc_can_ttcan_trigger_config_t; + + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CAN_Init(const stc_can_init_config_t *pstcCanInitCfg); +void CAN_DeInit(void); +void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState); +bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType); +void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType); +void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState); +en_can_error_t CAN_ErrorStatusGet(void); +bool CAN_StatusGet(en_can_status_t enCanStatus); + +void CAN_FilterConfig(const stc_can_filter_t pstcFilter[], uint8_t u8FilterCount); +void CAN_FilterCmd(en_can_filter_sel_t enFilter, en_functional_state_t enNewState); + +void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame); +en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd); +en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame); + +uint8_t CAN_ArbitrationLostCap(void); +uint8_t CAN_RxErrorCntGet(void); +uint8_t CAN_TxErrorCntGet(void); + + +//<< void CAN_TTCAN_Enable(void); +//<< void CAN_TTCAN_Disable(void); +//<< void CAN_TTCAN_IrqCmd(void); +//<< void CAN_TTCAN_ReferenceMsgSet(stc_can_ttcan_ref_msg_t *pstcRefMsg); +//<< void CAN_TTCAN_TriggerConfig(stc_can_ttcan_trigger_config_t *pstcTriggerCfg); + +//@} // CanGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CAN_ENABLE */ + +#endif /* __HC32F460_CAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/inc/hc32f460_can1.h b/driver/inc/hc32f460_can1.h new file mode 100644 index 0000000..9bba878 --- /dev/null +++ b/driver/inc/hc32f460_can1.h @@ -0,0 +1,514 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_can.h + ** + ** A detailed description is available at + ** @link CanGroup CAN description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of CAN + ** + ******************************************************************************/ +#ifndef __HC32F460_CAN_H__ +#define __HC32F460_CAN_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CAN_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CanGroup Controller Area Network(CAN) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief The Can error types. + ******************************************************************************/ +typedef enum +{ + NO_ERROR = 0U, + BIT_ERROR = 1U, + FORM_ERROR = 2U, + STUFF_ERROR = 3U, + ACK_ERROR = 4U, + CRC_ERROR = 5U, + UNKOWN_ERROR = 6U, +}en_can_error_t; + +/** + ******************************************************************************* + ** \brief The Can transmit buffer select.(TCMD) + ******************************************************************************/ +typedef enum +{ + CanPTBSel = 0U, ///< high-priority buffer + CanSTBSel = 1U, ///< secondary buffer +}en_can_buffer_sel_t; + +/** + ******************************************************************************* + ** \brief The Can warning limits.(AFWL) + ******************************************************************************/ +typedef struct stc_can_warning_limit +{ + uint8_t CanWarningLimitVal; ///< Receive buffer almost full warning limit + uint8_t CanErrorWarningLimitVal; ///< Programmable error warning limit +}stc_can_warning_limit_t; + +/** + ******************************************************************************* + ** \brief The Acceptance Filters Frame Format Check.(ACF) + ******************************************************************************/ +typedef enum en_can_acf_format_en +{ + CanStdFrames = 0x02u, ///< Accepts only Standard frames + CanExtFrames = 0x03u, ///< Accepts only Extended frames + CanAllFrames = 0x00u, ///< Accepts both standard or extended frames +}en_can_acf_format_en_t; + +/** + ******************************************************************************* + ** \brief The Acceptance Filters Enable.(ACFEN) + ******************************************************************************/ +typedef enum en_can_filter_sel +{ + CanFilterSel1 = 0u, ///< The Acceptance Filter 1 Enable + CanFilterSel2 = 1u, ///< The Acceptance Filter 2 Enable + CanFilterSel3 = 2u, ///< The Acceptance Filter 3 Enable + CanFilterSel4 = 3u, ///< The Acceptance Filter 4 Enable + CanFilterSel5 = 4u, ///< The Acceptance Filter 5 Enable + CanFilterSel6 = 5u, ///< The Acceptance Filter 6 Enable + CanFilterSel7 = 6u, ///< The Acceptance Filter 7 Enable + CanFilterSel8 = 7u, ///< The Acceptance Filter 8 Enable +}en_can_filter_sel_t; + +/** + ******************************************************************************* + ** \brief The can interrupt enable.(IE) + ******************************************************************************/ +typedef enum +{ + //<empty and =almost full, but not full and no overflow + CanRxBufFull = 3, ///< full +}en_can_rx_buf_status_t; + +/** + ******************************************************************************* + ** \brief The Can Transmission secondary Status.(TSSTAT) + ******************************************************************************/ +typedef enum +{ + CanTxBufEmpty = 0, ///< TTEN=0 or TTTBM=0: STB is empty + ///< TTEN=1 and TTTBM=1: PTB and STB are empty + CanTxBufnotHalfFull = 1, ///< TTEN=0 or TTTBM=0: STB is less than or equal to half full + ///< TTEN=1 and TTTBM=1: PTB and STB are not empty and not full + CanTxBufHalfFull = 2, ///< TTEN=0 or TTTBM=0: STB is more than half full + ///< TTEN=1 and TTTBM=1: None + CanTxBufFull = 3, ///< TTEN=0 or TTTBM=0: STB is full + ///< TTEN=1 and TTTBM=1: PTB and STB are full +}en_can_tx_buf_status_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Acceptance Filter Code and Mask. + ******************************************************************************/ +typedef struct stc_can_filter +{ + uint32_t u32CODE; ///< Acceptance CODE + uint32_t u32MASK; ///< Acceptance MASK + en_can_filter_sel_t enFilterSel; ///< The Acceptance Filters Enable + en_can_acf_format_en_t enAcfFormat; ///< The Acceptance Filters Frame Format Check. +}stc_can_filter_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Bit Timing. + ******************************************************************************/ +typedef struct stc_can_bt +{ + uint8_t SEG_1; ///< Bit timing segment 1(Tseg_1 = (SEG_1 + 2)*TQ) + uint8_t SEG_2; ///< Bit timing segment 2(Tseg_2 = (SEG_2 + 1)*TQ) + uint8_t SJW; ///< Synchronization jump width(Tsjw = (SJW + 1)*TQ) + uint8_t PRESC; ///< The Prescaler divides the system clock to get the time quanta clock tq_clk(TQ) +}stc_can_bt_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Control Frame. + ******************************************************************************/ +typedef struct +{ + uint32_t DLC : 4; ///< Data length code + uint32_t RESERVED0 : 2; ///< Ignore + uint32_t RTR : 1; ///< Remote transmission request + uint32_t IDE : 1; ///< IDentifier extension + uint32_t RESERVED1 : 24; ///< Ignore +}stc_can_txcontrol_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Tx Frame. + ******************************************************************************/ +typedef struct stc_can_txframe +{ + union + { + uint32_t TBUF32_0; ///< Ignore + uint32_t StdID; ///< Standard ID + uint32_t ExtID; ///< Extended ID + }; + union + { + uint32_t TBUF32_1; ///< Ignore + stc_can_txcontrol_t Control_f; ///< CAN Tx Control + }; + union + { + uint32_t TBUF32_2[2]; ///< Ignore + uint8_t Data[8]; ///< CAN data + }; + en_can_buffer_sel_t enBufferSel; ///< CAN Tx buffer select +}stc_can_txframe_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx Ctrl. + ******************************************************************************/ +typedef struct +{ + uint8_t DLC : 4; ///< Data length code + uint8_t RESERVED0 : 2; ///< Ignore + uint8_t RTR : 1; ///< Remote transmission request + uint8_t IDE : 1; ///< IDentifier extension +}stc_can_rxcontrol_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN status. + ******************************************************************************/ +typedef struct +{ + uint8_t RESERVED0 : 4; ///< Ignore + uint8_t TX : 1; ///< TX is set to 1 if the loop back mode is activated + uint8_t KOER : 3; ///< Kind of error +}stc_can_status_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN control, status and cycletime. + ******************************************************************************/ +typedef struct +{ + stc_can_rxcontrol_t Control_f; ///< @ref stc_can_rxcontrol_t + stc_can_status_t Status_f; ///< @ref stc_can_status_t + uint16_t CycleTime; ///< TTCAN cycletime +}stc_can_cst_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx frame. + ******************************************************************************/ +typedef struct stc_can_rxframe +{ + union + { + uint32_t RBUF32_0; ///< Ignore + uint32_t StdID; ///< Standard ID + uint32_t ExtID; ///< Extended ID + }; + union + { + uint32_t RBUF32_1; ///< Ignore + stc_can_cst_t Cst; ///< @ref stc_can_cst_t + }; + union + { + uint32_t RBUF32_2[2]; ///< Ignore + uint8_t Data[8]; ///< CAN data + }; +}stc_can_rxframe_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx frame. + ******************************************************************************/ +typedef struct stc_can_init_config +{ + en_can_rx_buf_all_t enCanRxBufAll; ///< @ref en_can_rx_buf_all_t + en_can_rx_buf_mode_en_t enCanRxBufMode; ///< @ref en_can_rx_buf_mode_en_t + en_can_self_ack_en_t enCanSAck; ///< @ref en_can_self_ack_en_t + en_can_stb_mode_t enCanSTBMode; ///< @ref en_can_stb_mode_t + stc_can_bt_t stcCanBt; ///< @ref stc_can_bt_t + stc_can_warning_limit_t stcWarningLimit; ///< @ref stc_can_warning_limit_t +}stc_can_init_config_t; + +/** + ******************************************************************************* + ** \brief CAN TTCAN + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN pointer to a TB message slot + ******************************************************************************/ +typedef enum +{ + CanTTcanPTBSel = 0x00u, ///< PTB + CanTTcanSTB1Sel = 0x01u, ///< STB1 + CanTTcanSTB2Sel = 0x02u, ///< STB2 + CanTTcanSTB3Sel = 0x03u, ///< STB3 + CanTTcanSTB4Sel = 0x04u, ///< STB4 +}en_can_ttcan_tbslot_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN Timer prescaler + ******************************************************************************/ +typedef enum +{ + CanTTcanTprescDiv1 = 0x00u, ///< Div1 + CanTTcanTprescDiv2 = 0x01u, ///< Div2 + CanTTcanTprescDiv3 = 0x02u, ///< Div3 + CanTTcanTprescDiv4 = 0x03u, ///< Div4 +}en_can_ttcan_Tpresc_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN Trigger type + ******************************************************************************/ +typedef enum +{ + CanTTcanImmediate = 0x00, ///< Immediate trigger for immediate transmission + CanTTcanTime = 0x01, ///< Time trigger for receive trigger + CanTTcanSingle = 0x02, ///< Single shot transmit trigger for exclusive time windows + CanTTcanTransStart = 0x03, ///< Transmit start trigger for merged arbitrating time windows + CanTTcanTransStop = 0x04, ///< Transmit stop trigger for merged arbitrating time windows +}en_can_ttcan_trigger_type_t; + +typedef enum +{ + CanTTcanWdtTriggerIrq = 0x80, ///< Watch trigger interrupt + CanTTcanTimTriggerIrq = 0x10, ///< Time trigger interrupt +}en_can_ttcan_irq_type_t; + + +typedef struct stc_can_ttcan_ref_msg +{ + uint8_t u8IDE; ///< Reference message IDE:1-Extended; 0-Standard; + union ///< Reference message ID + { + uint32_t RefStdID; ///< Reference standard ID + uint32_t RefExtID; ///< Reference Extended ID + }; +}stc_can_ttcan_ref_msg_t; + +typedef struct stc_can_ttcan_trigger_config +{ + en_can_ttcan_tbslot_t enTbSlot; ///< Transmit trigger TB slot pointer + en_can_ttcan_trigger_type_t enTrigType; ///< Trigger type + en_can_ttcan_Tpresc_t enTpresc; ///< Timer prescaler + uint8_t u8Tew; ///< Transmit enable window + uint16_t u16TrigTime; ///< TTCAN trigger time + uint16_t u16WatchTrigTime; ///< TTCAN watch trigger time register +}stc_can_ttcan_trigger_config_t; + + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CAN_Init(stc_can_init_config_t *pstcCanInitCfg); +void CAN_DeInit(void); +void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState); +bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType); +void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType); +void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState); +en_can_error_t CAN_ErrorStatusGet(void); +bool CAN_StatusGet(en_can_status_t enCanStatus); + +void CAN_FilterConfig(const stc_can_filter_t *pstcFilter, en_functional_state_t enNewState); +void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame); +en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd); +en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame); + +uint8_t CAN_ArbitrationLostCap(void); +uint8_t CAN_RxErrorCntGet(void); +uint8_t CAN_TxErrorCntGet(void); + + +//<< void CAN_TTCAN_Enable(void); +//<< void CAN_TTCAN_Disable(void); +//<< void CAN_TTCAN_IrqCmd(void); +//<< void CAN_TTCAN_ReferenceMsgSet(stc_can_ttcan_ref_msg_t *pstcRefMsg); +//<< void CAN_TTCAN_TriggerConfig(stc_can_ttcan_trigger_config_t *pstcTriggerCfg); + +//@} // CanGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CAN_ENABLE */ + +#endif /* __HC32F460_CAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/inc/hc32f460_clk.h b/driver/inc/hc32f460_clk.h new file mode 100644 index 0000000..84c555d --- /dev/null +++ b/driver/inc/hc32f460_clk.h @@ -0,0 +1,647 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_clk.h + ** + ** A detailed description is available at + ** @link CmuGroup Clock description @endlink + ** + ** - 2018-10-13 CDT First version for Device Driver Library of CMU. + ** + ******************************************************************************/ +#ifndef __HC32F460_CLK_H__ +#define __HC32F460_CLK_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CLK_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CmuGroup Clock Manage Unit(CMU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief The system clock source. + ** + ******************************************************************************/ + typedef enum en_clk_sys_source + { + ClkSysSrcHRC = 0u, ///< The system clock source is HRC. + ClkSysSrcMRC = 1u, ///< The system clock source is MRC. + ClkSysSrcLRC = 2u, ///< The system clock source is LRC. + ClkSysSrcXTAL = 3u, ///< The system clock source is XTAL. + ClkSysSrcXTAL32 = 4u, ///< The system clock source is XTAL32. + CLKSysSrcMPLL = 5u, ///< The system clock source is MPLL. + }en_clk_sys_source_t; + +/** + ******************************************************************************* + ** \brief The pll clock source. + ** + ******************************************************************************/ + typedef enum en_clk_pll_source + { + ClkPllSrcXTAL = 0u, ///< The pll clock source is XTAL. + ClkPllSrcHRC = 1u, ///< The pll clock source is HRC. + }en_clk_pll_source_t; + +/** + ******************************************************************************* + ** \brief The usb clock source. + ** + ******************************************************************************/ +typedef enum en_clk_usb_source +{ + ClkUsbSrcSysDiv2 = 2u, ///< The usb clock source is 1/2 system clock. + ClkUsbSrcSysDiv3 = 3u, ///< The usb clock source is 1/3 system clock. + ClkUsbSrcSysDiv4 = 4u, ///< The usb clock source is 1/4 system clock. + ClkUsbSrcMpllp = 8u, ///< The usb clock source is MPLLP. + ClkUsbSrcMpllq = 9u, ///< The usb clock source is MPLLQ. + ClkUsbSrcMpllr = 10u, ///< The usb clock source is MPLLR. + ClkUsbSrcUpllp = 11u, ///< The usb clock source is UPLLP. + ClkUsbSrcUpllq = 12u, ///< The usb clock source is UPLLQ. + ClkUsbSrcUpllr = 13u, ///< The usb clock source is UPLLR. +}en_clk_usb_source_t; + +/** + ******************************************************************************* + ** \brief The peripheral(adc/trng/I2S) clock source. + ** + ******************************************************************************/ +typedef enum en_clk_peri_source +{ + ClkPeriSrcPclk = 0u, ///< The peripheral(adc/trng/I2S) clock source is division from system clock. + ClkPeriSrcMpllp = 8u, ///< The peripheral(adc/trng/I2S) clock source is MPLLP. + ClkPeriSrcMpllq = 9u, ///< The peripheral(adc/trng/I2S) clock source is MPLLQ. + ClkPeriSrcMpllr = 10u, ///< The peripheral(adc/trng/I2S) clock source is MPLLR. + ClkPeriSrcUpllp = 11u, ///< The peripheral(adc/trng/I2S) clock source is UPLLP. + ClkPeriSrcUpllq = 12u, ///< The peripheral(adc/trng/I2S) clock source is UPLLQ. + ClkPeriSrcUpllr = 13u, ///< The peripheral(adc/trng/I2S) clock source is UPLLR. +}en_clk_peri_source_t; + +/** + ******************************************************************************* + ** \brief The clock output source. + ** + ******************************************************************************/ +typedef enum en_clk_output_source +{ + ClkOutputSrcHrc = 0u, ///< The clock output source is HRC + ClkOutputSrcMrc = 1u, ///< The clock output source is MRC. + ClkOutputSrcLrc = 2u, ///< The clock output source is LRC. + ClkOutputSrcXtal = 3u, ///< The clock output source is XTAL. + ClkOutputSrcXtal32 = 4u, ///< The clock output source is XTAL32 + ClkOutputSrcMpllp = 6u, ///< The clock output source is MPLLP. + ClkOutputSrcUpllp = 7u, ///< The clock output source is UPLLP. + ClkOutputSrcMpllq = 8u, ///< The clock output source is MPLLQ. + ClkOutputSrcUpllq = 9u, ///< The clock output source is UPLLQ. + ClkOutputSrcSysclk = 11u, ///< The clock output source is system clock. +}en_clk_output_source_t; + +/** + ******************************************************************************* + ** \brief The clock frequency source for measure or reference. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_source +{ + ClkFcmSrcXtal = 0u, ///< The clock frequency measure or reference source is XTAL + ClkFcmSrcXtal32 = 1u, ///< The clock frequency measure or reference source is XTAL32. + ClkFcmSrcHrc = 2u, ///< The clock frequency measure or reference source is HRC. + ClkFcmSrcLrc = 3u, ///< The clock frequency measure or reference source is LRC. + ClkFcmSrcSwdtrc = 4u, ///< The clock frequency measure or reference source is SWDTRC + ClkFcmSrcPclk1 = 5u, ///< The clock frequency measure or reference source is PCLK1. + ClkFcmSrcUpllp = 6u, ///< The clock frequency measure or reference source is UPLLP. + ClkFcmSrcMrc = 7u, ///< The clock frequency measure or reference source is MRC. + ClkFcmSrcMpllp = 8u, ///< The clock frequency measure or reference source is MPLLP. + ClkFcmSrcRtcLrc = 9u, ///< The clock frequency measure or reference source is RTCLRC. +}en_clk_fcm_intref_source_t,en_clk_fcm_measure_source_t; + +/** + ******************************************************************************* + ** \brief The clock flag status. + ** + ******************************************************************************/ +typedef enum en_clk_flag +{ + ClkFlagHRCRdy = 0u, ///< The clock flag is HRC ready. + ClkFlagXTALRdy = 1u, ///< The clock flag is XTAL ready. + ClkFlagMPLLRdy = 2u, ///< The clock flag is MPLL ready. + ClkFlagUPLLRdy = 3u, ///< The clock flag is UPLL ready. + ClkFlagXTALStoppage = 4u, ///< The clock flag is XTAL stoppage. +}en_clk_flag_t; + +/** + ******************************************************************************* + ** \brief The clock frequency measure flag status. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_flag +{ + ClkFcmFlagErrf = 0u, ///< The clock frequency flag is frequency abnormal. + ClkFcmFlagMendf = 1u, ///< The clock frequency flag is end of measurement. + ClkFcmFlagOvf = 2u, ///< The clock frequency flag is counter overflow. +}en_clk_fcm_flag_t; + +/** + ******************************************************************************* + ** \brief The source of xtal. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_mode +{ + ClkXtalModeOsc = 0u, ///< Use external high speed osc as source. + ClkXtalModeExtClk = 1u, ///< Use external clk as source. +}en_clk_xtal_mode_t; + +/** + ******************************************************************************* + ** \brief The drive capability of xtal. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_drv +{ + ClkXtalHighDrv = 0u, ///< High drive capability.20MHz~24MHz. + ClkXtalMidDrv = 1u, ///< Middle drive capability.16MHz~20MHz. + ClkXtalLowDrv = 2u, ///< Low drive capability.8MHz~16MHz. + ClkXtalTinyDrv = 3u, ///< Tiny drive capability.8MHz. +}en_clk_xtal_drv_t; + +/** + ******************************************************************************* + ** \brief The stable time of XTAL. + ** + ** \note It depends on SUPDRV bit. + ******************************************************************************/ +typedef enum en_clk_xtal_stb_cycle +{ + ClkXtalStbCycle35 = 1u, ///< stable time is 35(36) cycle. + ClkXtalStbCycle67 = 2u, ///< stable time is 67(68) cycle. + ClkXtalStbCycle131 = 3u, ///< stable time is 131(132) cycle. + ClkXtalStbCycle259 = 4u, ///< stable time is 259(260) cycle. + ClkXtalStbCycle547 = 5u, ///< stable time is 547(548) cycle. + ClkXtalStbCycle1059 = 6u, ///< stable time is 1059(1060) cycle. + ClkXtalStbCycle2147 = 7u, ///< stable time is 2147(2148) cycle. + ClkXtalStbCycle4291 = 8u, ///< stable time is 4291(4292) cycle. + ClkXtalStbCycle8163 = 9u, ///< stable time is 8163(8164) cycle. +}en_clk_xtal_stb_cycle_t; + +/** + ******************************************************************************* + ** \brief The handle of xtal stoppage. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_stp_mode +{ + ClkXtalStpModeInt = 0u, ///< The handle of stoppage is interrupt. + ClkXtalStpModeReset = 1u, ///< The handle of stoppage is reset. +}en_clk_xtal_stp_mode_t; + +/** + ******************************************************************************* + ** \brief The drive capability of xtal32. + ** + ******************************************************************************/ +typedef enum en_clk_xtal32_drv +{ + ClkXtal32MidDrv = 0u, ///< Middle drive capability.32.768KHz. + ClkXtal32HighDrv = 1u, ///< High drive capability.32.768KHz. +}en_clk_xtal32_drv_t; + +/** + ******************************************************************************* + ** \brief The filter mode of xtal32. + ** + ******************************************************************************/ +typedef enum en_clk_xtal32_filter_mode +{ + ClkXtal32FilterModeFull = 0u, ///< Valid in run,stop,power down mode. + ClkXtal32FilterModePart = 2u, ///< Valid in run mode. + ClkXtal32FilterModeNone = 3u, ///< Invalid in run,stop,power down mode. +}en_clk_xtal32_filter_mode_t; + +/** + ******************************************************************************* + ** \brief The division factor of system clock. + ** + ******************************************************************************/ +typedef enum en_clk_sysclk_div_factor +{ + ClkSysclkDiv1 = 0u, ///< 1 division. + ClkSysclkDiv2 = 1u, ///< 2 division. + ClkSysclkDiv4 = 2u, ///< 4 division. + ClkSysclkDiv8 = 3u, ///< 8 division. + ClkSysclkDiv16 = 4u, ///< 16 division. + ClkSysclkDiv32 = 5u, ///< 32 division. + ClkSysclkDiv64 = 6u, ///< 64 division. +}en_clk_sysclk_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of system clock.It will be used for debug clock. + ** + ******************************************************************************/ +typedef enum en_clk_tpiuclk_div_factor +{ + ClkTpiuclkDiv1 = 0u, ///< 1 division. + ClkTpiuclkDiv2 = 1u, ///< 2 division. + ClkTpiuclkDiv4 = 2u, ///< 4 division. +}en_clk_tpiuclk_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of clock output. + ** + ******************************************************************************/ +typedef enum en_clk_output_div_factor +{ + ClkOutputDiv1 = 0u, ///< 1 division. + ClkOutputDiv2 = 1u, ///< 2 division. + ClkOutputDiv4 = 2u, ///< 4 division. + ClkOutputDiv8 = 3u, ///< 8 division. + ClkOutputDiv16 = 4u, ///< 16 division. + ClkOutputDiv32 = 5u, ///< 32 division. + ClkOutputDiv64 = 6u, ///< 64 division. + ClkOutputDiv128 = 7u, ///< 128 division. +}en_clk_output_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of fcm measure source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_measure_div_factor +{ + ClkFcmMeaDiv1 = 0u, ///< 1 division. + ClkFcmMeaDiv4 = 1u, ///< 4 division. + ClkFcmMeaDiv8 = 2u, ///< 8 division. + ClkFcmMeaDiv32 = 3u, ///< 32 division. +}en_clk_fcm_measure_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_intref_div_factor +{ + ClkFcmIntrefDiv32 = 0u, ///< 32 division. + ClkFcmIntrefDiv128 = 1u, ///< 128 division. + ClkFcmIntrefDiv1024 = 2u, ///< 1024 division. + ClkFcmIntrefDiv8192 = 3u, ///< 8192 division. +}en_clk_fcm_intref_div_factor_t; + +/** + ******************************************************************************* + ** \brief The edge of the fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_edge +{ + ClkFcmEdgeRising = 0u, ///< Rising edge. + ClkFcmEdgeFalling = 1u, ///< Falling edge. + ClkFcmEdgeBoth = 2u, ///< Both edge. +}en_clk_fcm_edge_t; + +/** + ******************************************************************************* + ** \brief The filter clock of the fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_filter_clk +{ + ClkFcmFilterClkNone = 0u, ///< None filter. + ClkFcmFilterClkFcmSrc = 1u, ///< Use fcm measurement source as filter clock. + ClkFcmFilterClkFcmSrcDiv4 = 2u, ///< Use 1/4 fcm measurement source as filter clock. + ClkFcmFilterClkFcmSrcDiv16 = 3u, ///< Use 1/16 fcm measurement source as filter clock. +}en_clk_fcm_filter_clk_t; + +/** + ******************************************************************************* + ** \brief The fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_refer +{ + ClkFcmExtRef = 0u, ///< Use external reference. + ClkFcmInterRef = 1u, ///< Use internal reference. +}en_clk_fcm_refer_t; + +/** + ******************************************************************************* + ** \brief The handle of fcm abnormal. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_abnormal_handle +{ + ClkFcmHandleInterrupt = 0u, ///< The handle of fcm abnormal is interrupt. + ClkFcmHandleReset = 1u, ///< The handle of fcm abnormal is reset. +}en_clk_fcm_abnormal_handle_t; + +/** + ******************************************************************************* + ** \brief The channel of clock output. + ** + ******************************************************************************/ +typedef enum en_clk_output_ch +{ + ClkOutputCh1 = 1u, ///< The output of clk is MCO_1. + ClkOutputCh2 = 2u, ///< The output of clk is MCO_2. +}en_clk_output_ch_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL. + ** + ** \note Configures the XTAL if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal_cfg +{ + en_functional_state_t enFastStartup; ///< Enable fast start up or not. + en_clk_xtal_mode_t enMode; ///< Select xtal mode. + en_clk_xtal_drv_t enDrv; ///< Select xtal drive capability. +}stc_clk_xtal_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL stoppage. + ** + ** \note Configures the XTAL stoppage if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal_stp_cfg +{ + en_functional_state_t enDetect; ///< Enable detect stoppage or not. + en_clk_xtal_stp_mode_t enMode; ///< Select the handle of xtal stoppage. + en_functional_state_t enModeReset; ///< Enable reset for handle the xtal stoppage. + en_functional_state_t enModeInt; ///< Enable interrupt for handle the xtal stoppage. +}stc_clk_xtal_stp_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL32. + ** + ** \note Configures the XTAL32 if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal32_cfg +{ + en_clk_xtal32_drv_t enDrv; ///< Select xtal32 drive capability. + en_clk_xtal32_filter_mode_t enFilterMode; ///< The filter mode of xtal32. +}stc_clk_xtal32_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of PLL. + ** + ** \note Configures the PLL if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_pll_cfg +{ + uint32_t PllpDiv; ///< Pllp clk, division factor of VCO out. + uint32_t PllqDiv; ///< Pllq clk, division factor of VCO out. + uint32_t PllrDiv; ///< Pllr clk, division factor of VCO out. + uint32_t plln; ///< Multiplication factor of vco out, ensure between 240M~480M + uint32_t pllmDiv; ///< Division factor of VCO in, ensure between 1M~12M. +}stc_clk_mpll_cfg_t, stc_clk_upll_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of system clock. + ** + ** \note Configures the system clock if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_sysclk_cfg +{ + en_clk_sysclk_div_factor_t enHclkDiv; ///< Division for hclk. + en_clk_sysclk_div_factor_t enExclkDiv; ///< Division for exclk. + en_clk_sysclk_div_factor_t enPclk0Div; ///< Division for pclk0. + en_clk_sysclk_div_factor_t enPclk1Div; ///< Division for pclk1. + en_clk_sysclk_div_factor_t enPclk2Div; ///< Division for pclk2. + en_clk_sysclk_div_factor_t enPclk3Div; ///< Division for pclk3. + en_clk_sysclk_div_factor_t enPclk4Div; ///< Division for pclk4. +}stc_clk_sysclk_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of clock output. + ** + ** \note Configures the clock output if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_output_cfg +{ + en_clk_output_source_t enOutputSrc; ///< The clock output source. + en_clk_output_div_factor_t enOutputDiv; ///< The division factor of clock output source. +}stc_clk_output_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm window. + ** + ** \note Configures the fcm window if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_window_cfg +{ + uint16_t windowLower; ///< The lower value of the window. + uint16_t windowUpper; ///< The upper value of the window. +}stc_clk_fcm_window_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm measurement. + ** + ** \note Configures the fcm measurement if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_measure_cfg +{ + en_clk_fcm_measure_source_t enSrc; ///< The measurement source. + en_clk_fcm_measure_div_factor_t enSrcDiv; ///< The division factor of measurement source. +}stc_clk_fcm_measure_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm reference. + ** + ** \note Configures the fcm reference if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_reference_cfg +{ + en_functional_state_t enExtRef; ///< Enable external reference or not. + en_clk_fcm_edge_t enEdge; ///< The edge of internal reference. + en_clk_fcm_filter_clk_t enFilterClk; ///< The filter clock of internal reference. + en_clk_fcm_refer_t enRefSel; ///< Select reference. + en_clk_fcm_intref_source_t enIntRefSrc; ///< Select internal reference. + en_clk_fcm_intref_div_factor_t enIntRefDiv; ///< The division factor of internal reference. +}stc_clk_fcm_reference_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm interrupt. + ** + ** \note Configures the fcm interrupt if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_interrupt_cfg +{ + en_clk_fcm_abnormal_handle_t enHandleSel; ///< Use interrupt or reset. + en_functional_state_t enHandleReset; ///< Enable reset or not. + en_functional_state_t enHandleInterrupt; ///< Enable interrupt or not. + en_functional_state_t enOvfInterrupt; ///< Enable overflow interrupt or not. + en_functional_state_t enEndInterrupt; ///< Enable measurement end interrupt or not. +}stc_clk_fcm_interrupt_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm. + ** + ** \note Configures the fcm if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_cfg +{ + stc_clk_fcm_window_cfg_t *pstcFcmWindowCfg; ///< Window configuration struct. + stc_clk_fcm_measure_cfg_t *pstcFcmMeaCfg; ///< Measurement configuration struct. + stc_clk_fcm_reference_cfg_t *pstcFcmRefCfg; ///< Reference configuration struct. + stc_clk_fcm_interrupt_cfg_t *pstcFcmIntCfg; ///< Interrupt configuration struct. +}stc_clk_fcm_cfg_t; + +/** + ******************************************************************************* + ** \brief Clock frequency structure. + ** + ******************************************************************************/ +typedef struct stc_clk_freq +{ + uint32_t sysclkFreq; ///< System clock frequency. + uint32_t hclkFreq; ///< Hclk frequency. + uint32_t exckFreq; ///< Exclk frequency. + uint32_t pclk0Freq; ///< Pclk0 frequency. + uint32_t pclk1Freq; ///< Pclk1 frequency. + uint32_t pclk2Freq; ///< Pclk2 frequency. + uint32_t pclk3Freq; ///< Pclk3 frequency. + uint32_t pclk4Freq; ///< Pclk4 frequency. +}stc_clk_freq_t; + +/** + ******************************************************************************* + ** \brief PLL Clock frequency structure. + ** + ******************************************************************************/ +typedef struct stc_pll_clk_freq +{ + uint32_t mpllp; ///< mpllp clock frequency. + uint32_t mpllq; ///< mpllq clock frequency. + uint32_t mpllr; ///< mpllr clock frequency. + uint32_t upllp; ///< upllp clock frequency. + uint32_t upllq; ///< upllq clock frequency. + uint32_t upllr; ///< upllr clock frequency. +}stc_pll_clk_freq_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CLK_XtalConfig(const stc_clk_xtal_cfg_t *pstcXtalCfg); +void CLK_XtalStbConfig(const en_clk_xtal_stb_cycle_t enXtalStb); +void CLK_XtalStpConfig(const stc_clk_xtal_stp_cfg_t *pstcXtalStpCfg); +en_result_t CLK_XtalCmd(en_functional_state_t enNewState); + +void CLK_Xtal32Config(const stc_clk_xtal32_cfg_t *pstcXtal32Cfg); +en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState); + +void CLK_HrcTrim(int8_t trimValue); +en_result_t CLK_HrcCmd(en_functional_state_t enNewState); + +void CLK_MrcTrim(int8_t trimValue); +en_result_t CLK_MrcCmd(en_functional_state_t enNewState); + +void CLK_LrcTrim(int8_t trimValue); +en_result_t CLK_LrcCmd(en_functional_state_t enNewState); + +void CLK_SetPllSource(en_clk_pll_source_t enPllSrc); +void CLK_MpllConfig(const stc_clk_mpll_cfg_t *pstcMpllCfg); +en_result_t CLK_MpllCmd(en_functional_state_t enNewState); + +void CLK_UpllConfig(const stc_clk_upll_cfg_t *pstcUpllCfg); +en_result_t CLK_UpllCmd(en_functional_state_t enNewState); + +void CLK_SetSysClkSource(en_clk_sys_source_t enTargetSysSrc); +en_clk_sys_source_t CLK_GetSysClkSource(void); + +void CLK_SysClkConfig(const stc_clk_sysclk_cfg_t *pstcSysclkCfg); +void CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq); +void CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq); + +void CLK_SetUsbClkSource(en_clk_usb_source_t enTargetUsbSrc); +void CLK_SetPeriClkSource(en_clk_peri_source_t enTargetPeriSrc); +void CLK_SetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg, en_clk_peri_source_t enTargetPeriSrc); +en_clk_peri_source_t CLK_GetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg); + +void CLK_TpiuClkConfig(const en_clk_tpiuclk_div_factor_t enTpiuDiv); +void CLK_TpiuClkCmd(en_functional_state_t enNewState); + +void CLK_OutputClkConfig(en_clk_output_ch_t enCh, const stc_clk_output_cfg_t *pstcOutputCfg); +void CLK_OutputClkCmd(en_clk_output_ch_t enCh, en_functional_state_t enNewState); +en_flag_status_t CLK_GetFlagStatus(en_clk_flag_t enClkFlag); + +void CLK_FcmConfig(const stc_clk_fcm_cfg_t *pstcClkFcmCfg); +void CLK_FcmCmd(en_functional_state_t enNewState); + +uint16_t CLK_GetFcmCounter(void); +en_flag_status_t CLK_GetFcmFlag(en_clk_fcm_flag_t enFcmFlag); +void CLK_ClearFcmFlag(en_clk_fcm_flag_t enFcmFlag); + +void CLK_ClearXtalStdFlag(void); + +//@} // CmuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CLK_ENABLE */ + +#endif /* __HC32F460_CLK_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_cmp.h b/driver/inc/hc32f460_cmp.h new file mode 100644 index 0000000..19d4b63 --- /dev/null +++ b/driver/inc/hc32f460_cmp.h @@ -0,0 +1,279 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_cmp.h + ** + ** A detailed description is available at + ** @link CmpGroup CMP @endlink + ** + ** - 2018-10-22 CDT First version for Device Driver Library of CMP. + ** + ******************************************************************************/ +#ifndef __HC32F460_CMP_H__ +#define __HC32F460_CMP_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CMP_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CmpGroup Comparator(CMP) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief CMP function enumeration + ******************************************************************************/ +typedef enum en_cmp_func +{ + CmpVcoutOutput = (1u << 12), ///< CMP vcout output enable function + CmpOutpuInv = (1u << 13), ///< CMP output invert enable function + CmpOutput = (1u << 14), ///< CMP output enable function +} en_cmp_func_t; + +/** + ******************************************************************************* + ** \brief CMP edge selection enumeration + ******************************************************************************/ +typedef enum en_cmp_edge_sel +{ + CmpNoneEdge = 0u, ///< None edge detection + CmpRisingEdge = 1u, ///< Rising edge detection + CmpFaillingEdge = 2u, ///< Falling edge detection + CmpBothEdge = 3u, ///< Falling or Rising edge detection +} en_cmp_edge_sel_t; + +/** + ******************************************************************************* + ** \brief CMP filter sample clock division enumeration + ******************************************************************************/ +typedef enum en_cmp_fltclk_div +{ + CmpNoneFlt = 0u, ///< Unuse filter + CmpFltPclk3Div1 = 1u, ///< PCLK3/1 + CmpFltPclk3Div2 = 2u, ///< PCLK3/2 + CmpFltPclk3Div4 = 3u, ///< PCLK3/4 + CmpFltPclk3Div8 = 4u, ///< PCLK3/8 + CmpFltPclk3Div16 = 5u, ///< PCLK3/16 + CmpFltPclk3Div32 = 6u, ///< PCLK3/32 + CmpFltPclk3Div64 = 7u, ///< PCLK3/64 +} en_cmp_fltclk_div_t; + +/** + ******************************************************************************* + ** \brief CMP INP4 input enumeration + ******************************************************************************/ +typedef enum en_cmp_inp4_sel +{ + CmpInp4None = 0u, ///< None input + CmpInp4PGAO = 1u, ///< PGAO output + CmpInp4PGAO_BP = 2u, ///< PGAO_BP output + CmpInp4CMP1_INP4 = 4u, ///< CMP1_INP4 +} en_cmp_inp4_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INP input enumeration + ******************************************************************************/ +typedef enum en_cmp_inp_sel +{ + CmpInpNone = 0u, ///< None input + CmpInp1 = 1u, ///< INP1 input + CmpInp2 = 2u, ///< INP2 input + CmpInp1_Inp2 = 3u, ///< INP1 INP2 input + CmpInp3 = 4u, ///< INP3 input + CmpInp1_Inp3 = 5u, ///< INP1 INP3 input + CmpInp2_Inp3 = 6u, ///< INP2 INP3 input + CmpInp1_Inp2_Inp3 = 7u, ///< INP1 INP2 INP3 input + CmpInp4 = 8u, ///< INP4 input + CmpInp1_Inp4 = 9u, ///< INP1 INP4 input + CmpInp2_Inp4 = 10u, ///< INP2 INP4 input + CmpInp1_Inp2_Inp4 = 11u, ///< INP1 INP2 INP4 input + CmpInp3_Inp4 = 12u, ///< INP3 INP4 input + CmpInp1_Inp3_Inp4 = 13u, ///< INP1 INP3 INP4 input + CmpInp2_Inp3_Inp4 = 14u, ///< INP2 INP3 INP4 input + CmpInp1_Inp2_Inp3_Inp4 = 15u, ///< INP1 INP2 INP3 INP4 input +} en_cmp_inp_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INM input enumeration + ******************************************************************************/ +typedef enum en_cmp_inm_sel +{ + CmpInmNone = 0u, ///< None input + CmpInm1 = 1u, ///< INM1 input + CmpInm2 = 2u, ///< INM2 input + CmpInm3 = 4u, ///< INM3 input + CmpInm4 = 8u, ///< INM4 input +} en_cmp_inm_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INP State enumeration (read only) + ******************************************************************************/ +typedef enum en_cmp_inp_state +{ + CmpInpNoneState = 0u, ///< none input state + CmpInp1State = 1u, ///< INP1 input state + CmpInp2State = 2u, ///< INP2 input state + CmpInp3State = 4u, ///< INP3 input state + CmpInp4State = 8u, ///< INP4 input state +} en_cmp_inp_state_t; + +/** + ******************************************************************************* + ** \brief CMP Output State enumeration (read only) + ******************************************************************************/ +typedef enum en_cmp_output_state +{ + CmpOutputLow = 0u, ///< Compare output Low "0" + CmpOutputHigh = 1u, ///< Compare output High "1" +} en_cmp_output_state_t; + +/** + ******************************************************************************* + ** \brief CMP input selection + ******************************************************************************/ +typedef struct stc_cmp_input_sel +{ + en_cmp_inm_sel_t enInmSel; ///< CMP INM sel + + en_cmp_inp_sel_t enInpSel; ///< CMP INP sel + + en_cmp_inp4_sel_t enInp4Sel; ///< CMP INP4 sel +} stc_cmp_input_sel_t; + +/** + ****************************************************************************** + ** \brief DAC channel + ******************************************************************************/ +typedef enum en_cmp_dac_ch +{ + CmpDac1 = 0u, ///< DAC1 + CmpDac2 = 1u, ///< DAC2 +} en_cmp_dac_ch_t; + +/** + ****************************************************************************** + ** \brief ADC internal reference voltage path + ******************************************************************************/ +typedef enum en_cmp_adc_int_ref_volt_path +{ + CmpAdcRefVoltPathDac1 = (1u << 0u), ///< ADC internal reference voltage path: DAC1 + CmpAdcRefVoltPathDac2 = (1u << 1u), ///< ADC internal reference voltage path: DAC2 + CmpAdcRefVoltPathVref = (1u << 4u), ///< ADC internal reference voltage path: VREF +} en_cmp_adc_int_ref_volt_path_t; + +/** + ******************************************************************************* + ** \brief CMP initialization structure definition + ******************************************************************************/ +typedef struct stc_cmp_init +{ + en_cmp_edge_sel_t enEdgeSel; ///< CMP edge sel + + en_cmp_fltclk_div_t enFltClkDiv; ///< CMP FLTclock division + + en_functional_state_t enCmpOutputEn; ///< CMP Output enable + + en_functional_state_t enCmpVcoutOutputEn; ///< CMP output result enable + + en_functional_state_t enCmpInvEn; ///< CMP INV sel for output + + en_functional_state_t enCmpIntEN; ///< CMP interrupt enable +} stc_cmp_init_t; + +/** + ******************************************************************************* + ** \brief CMP DAC initialization structure definition + ******************************************************************************/ +typedef struct stc_cmp_dac_init +{ + uint8_t u8DacData; ///< CMP DAC Data register value + + en_functional_state_t enCmpDacEN; ///< CMP DAC enable +} stc_cmp_dac_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t CMP_Init(M4_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcInitCfg); +en_result_t CMP_DeInit(M4_CMP_TypeDef *CMPx); +en_result_t CMP_Cmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd); +en_result_t CMP_IrqCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd); +en_result_t CMP_SetScanTime(M4_CMP_TypeDef *CMPx, + uint8_t u8ScanStable, + uint8_t u8ScanPeriod); +en_result_t CMP_FuncCmd(M4_CMP_TypeDef *CMPx, + en_cmp_func_t enFunc, + en_functional_state_t enCmd); +en_result_t CMP_StartScan(M4_CMP_TypeDef *CMPx); +en_result_t CMP_StopScan(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetFilterClkDiv(M4_CMP_TypeDef *CMPx, + en_cmp_fltclk_div_t enFltClkDiv); +en_cmp_fltclk_div_t CMP_GetFilterClkDiv(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetEdgeSel(M4_CMP_TypeDef *CMPx, + en_cmp_edge_sel_t enEdgeSel); +en_cmp_edge_sel_t CMP_GetEdgeSel(M4_CMP_TypeDef *CMPx); +en_result_t CMP_InputSel(M4_CMP_TypeDef *CMPx, + const stc_cmp_input_sel_t *pstcInputSel); +en_result_t CMP_SetInp(M4_CMP_TypeDef *CMPx, en_cmp_inp_sel_t enInputSel); +en_cmp_inp_sel_t CMP_GetInp(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetInm(M4_CMP_TypeDef *CMPx, en_cmp_inm_sel_t enInputSel); +en_cmp_inm_sel_t CMP_GetInm(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetInp4(M4_CMP_TypeDef *CMPx,en_cmp_inp4_sel_t enInputSel); +en_cmp_inp4_sel_t CMP_GetInp4(M4_CMP_TypeDef *CMPx); +en_cmp_output_state_t CMP_GetOutputState(M4_CMP_TypeDef *CMPx); +en_cmp_inp_state_t CMP_GetInpState(M4_CMP_TypeDef *CMPx); +en_result_t CMP_DAC_Init(en_cmp_dac_ch_t enCh, + const stc_cmp_dac_init_t *pstcInitCfg); +en_result_t CMP_DAC_DeInit(en_cmp_dac_ch_t enCh); +en_result_t CMP_DAC_Cmd(en_cmp_dac_ch_t enCh, en_functional_state_t enCmd); +en_result_t CMP_DAC_SetData(en_cmp_dac_ch_t enCh, uint8_t u8DacData); +uint8_t CMP_DAC_GetData(en_cmp_dac_ch_t enCh); +en_result_t CMP_ADC_SetRefVoltPath(en_cmp_adc_int_ref_volt_path_t enRefVoltPath); + +//@} // CmpGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CMP_ENABLE */ + +#endif /* __HC32F460_CMP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_crc.h b/driver/inc/hc32f460_crc.h new file mode 100644 index 0000000..756d249 --- /dev/null +++ b/driver/inc/hc32f460_crc.h @@ -0,0 +1,118 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_crc.h + ** + ** A detailed description is available at + ** @link CrcGroup Crc description @endlink + ** + ** - 2019-03-07 CDT First version for Device Driver Library of Crc. + ** + ******************************************************************************/ +#ifndef __HC32F460_CRC_H__ +#define __HC32F460_CRC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CRC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CrcGroup Cyclic Redundancy Check(CRC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* Bits definitions of CRC control register(CRC_CR). */ +/* + * Definitions of CRC protocol. + * NOTE: CRC16 polynomial is X16 + X12 + X5 + 1 + * CRC32 polynomial is X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + \ + * X8 + X7 + X5 + X4 + X2 + X + 1 + */ +#define CRC_SEL_16B ((uint32_t)0x0) +#define CRC_SEL_32B ((uint32_t)(0x1ul << 1u)) + +/* + * Identifies the transpose configuration of the source data. + * If this function is enabled, the source data's bits in bytes are transposed. + * e.g. There's a source data 0x1234 which will be calculated checksum and this + * function is enabled, the final data be calculated is 0x482C. + * 0x12: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x48. + * 0x48: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x2C. + * The same to 32 bit data while using CRC32. + */ +#define CRC_REFIN_DISABLE ((uint32_t)0x0) +#define CRC_REFIN_ENABLE ((uint32_t)(0x1ul << 2u)) + +/* + * Identifies the transpose configuration of the checksum. + * If this function is enabled, bits of the checksum will be transposed. + * e.g. There is a CRC16 checksum is 0x5678 before this function enabled, then + * this function is enabled, the checksum will be 0x1E6A. + * 0x5678: bit0->bit15, bit1->bit14, ..., bit15->bit0, the final data is 0x1E6A. + * The same to CRC32 checksum while using CRC32. + */ +#define CRC_REFOUT_DISABLE ((uint32_t)0x0) +#define CRC_REFOUT_ENABLE ((uint32_t)(0x1ul << 3u)) + +/* + * XORs the CRC checksum with 0xFFFF(CRC16) or 0xFFFFFFFF(CRC32). + * e.g. There is a CRC16 checksum is 0x5678 before this function enabled. + * If this function enabled, the checksum will be 0xA987. + * The same to CRC32 checksum while using CRC32. + */ +#define CRC_XOROUT_DISABLE ((uint32_t)0x0) +#define CRC_XOROUT_ENABLE ((uint32_t)(0x1ul << 4u)) + +#define CRC_CONFIG_MASK ((uint32_t)(0x1Eu)) + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CRC_Init(uint32_t u32Config); +uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length); +uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length); +bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16CheckSum, const uint16_t *pu16Data, uint32_t u32Length); +bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32CheckSum, const uint32_t *pu32Data, uint32_t u32Length); + +//@} // CrcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CRC_ENABLE */ + +#endif /* __HC32F460_CRC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_dcu.h b/driver/inc/hc32f460_dcu.h new file mode 100644 index 0000000..21bce80 --- /dev/null +++ b/driver/inc/hc32f460_dcu.h @@ -0,0 +1,216 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dcu.h + ** + ** A detailed description is available at + ** @link DcuGroup DCU description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of DCU. + ** + ******************************************************************************/ +#ifndef __HC32F460_DCU_H__ +#define __HC32F460_DCU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_DCU_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DcuGroup Data Computing Unit(DCU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief DCU register data enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_data_register +{ + DcuRegisterData0 = 0u, ///< DCU DATA0 + DcuRegisterData1 = 1u, ///< DCU DATA1 + DcuRegisterData2 = 2u, ///< DCU DATA2 +} en_dcu_data_register_t; + +/** + ******************************************************************************* + ** \brief DCU operation enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_operation_mode +{ + DcuInvalid = 0u, ///< DCU Invalid + DcuOpAdd = 1u, ///< DCU operation: Add + DcuOpSub = 2u, ///< DCU operation: Sub + DcuHwTrigOpAdd = 3u, ///< DCU operation: Hardware trigger Add + DcuHwTrigOpSub = 4u, ///< DCU operation: Hardware trigger Sub + DcuOpCompare = 5u, ///< DCU operation: Compare +} en_dcu_operation_mode_t; + +/** + ******************************************************************************* + ** \brief DCU data size enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_data_size +{ + DcuDataBit8 = 0u, ///< DCU data size: 8 bit + DcuDataBit16 = 1u, ///< DCU data size: 16 bit + DcuDataBit32 = 2u, ///< DCU data size: 32 bit +} en_dcu_data_size_t; + +/** + ******************************************************************************* + ** \brief DCU compare operation trigger mode enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_cmp_trigger_mode +{ + DcuCmpTrigbyData0 = 0u, ///< DCU compare triggered by DATA0 + DcuCmpTrigbyData012 = 1u, ///< DCU compare triggered by DATA0 or DATA1 or DATA2 +} en_dcu_cmp_trigger_mode_t; + +/** + ******************************************************************************* + ** \brief DCU interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_int_sel +{ + DcuIntOp = (1ul << 0), ///< DCU overflow or underflow interrupt + DcuIntLs2 = (1ul << 1), ///< DCU DATA0 < DATA2 interrupt + DcuIntEq2 = (1ul << 2), ///< DCU DATA0 = DATA2 interrupt + DcuIntGt2 = (1ul << 3), ///< DCU DATA0 > DATA2 interrupt + DcuIntLs1 = (1ul << 4), ///< DCU DATA0 < DATA1 interrupt + DcuIntEq1 = (1ul << 5), ///< DCU DATA0 = DATA1 interrupt + DcuIntGt1 = (1ul << 6), ///< DCU DATA0 > DATA1 interrupt +} en_dcu_int_sel_t, en_dcu_flag_t; + +/** + ******************************************************************************* + ** \brief DCU window interrupt mode enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_int_win_mode +{ + DcuIntInvalid = 0u, ///< DCU don't occur interrupt + DcuWinIntInvalid = 1u, ///< DCU window interrupt is invalid. + DcuInsideWinCmpInt = 2u, ///< DCU occur interrupt when DATA2 ¡Ü DATA0 ¡Ü DATA2 + DcuOutsideWinCmpInt = 3u, ///< DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 +} en_dcu_int_win_mode_t; + +/* DCU common trigger source select */ +typedef enum en_dcu_com_trigger +{ + DcuComTrigger_1 = 1u, ///< Select common trigger 1. + DcuComTrigger_2 = 2u, ///< Select common trigger 2. + DcuComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_dcu_com_trigger_t; + +/** + ******************************************************************************* + ** \brief DCU initialization configuration + ** + ******************************************************************************/ +typedef struct stc_dcu_init +{ + uint32_t u32IntSel; ///< Specifies interrupt selection and This parameter can be a value of @ref en_dcu_int_sel_t + + en_functional_state_t enIntCmd; ///< Select DCU interrupt function. Enable:Enable DCU interrupt function; Disable:Disable DCU interrupt function + + en_dcu_int_win_mode_t enIntWinMode; ///< Specifies interrupt window mode and This parameter can be a value of @ref en_dcu_int_win_mode_t + + en_dcu_data_size_t enDataSize; ///< Specifies DCU data size and This parameter can be a value of @ref en_dcu_data_size_t + + en_dcu_operation_mode_t enOperation; ///< Specifies DCU operation and This parameter can be a value of @ref en_dcu_operation_mode_t + + en_dcu_cmp_trigger_mode_t enCmpTriggerMode; ///< Specifies DCU compare operation trigger mode size and This parameter can be a value of @ref en_dcu_cmp_trigger_mode_t + +} stc_dcu_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg); +en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx, + en_dcu_operation_mode_t enMode); +en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize); +en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx, + en_dcu_int_win_mode_t enIntWinMode); +en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx, + en_dcu_cmp_trigger_mode_t enTriggerMode); +en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_EnableInterrupt(M4_DCU_TypeDef *DCUx); +en_result_t DCU_DisableInterrupt(M4_DCU_TypeDef *DCUx); +en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag); +en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag); +en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx, + en_dcu_int_sel_t enIntSel, + en_functional_state_t enCmd); +uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, uint8_t u8Data); +uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint16_t u16Data); +uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint32_t u32Data); +en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx, + en_event_src_t enTriggerSrc); +void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx, + en_dcu_com_trigger_t enComTrigger, + en_functional_state_t enState); + +//@} // DcuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_DCU_ENABLE */ + +#endif /* __HC32F460_DCU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_dmac.h b/driver/inc/hc32f460_dmac.h new file mode 100644 index 0000000..6a75373 --- /dev/null +++ b/driver/inc/hc32f460_dmac.h @@ -0,0 +1,363 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dmac.h + ** + ** A detailed description is available at + ** @link DmacGroup DMAC description @endlink + ** + ** - 2018-11-18 CDT First version for Device Driver Library of DMAC. + ** + ******************************************************************************/ +#ifndef __HC32F460_DMAC_H__ +#define __HC32F460_DMAC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_DMAC_ENABLE == DDL_ON) + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DmacGroup Direct Memory Access Control(DMAC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief DMA Channel + ** + ******************************************************************************/ +typedef enum en_dma_channel +{ + DmaCh0 = 0u, ///< DMA channel 0 + DmaCh1 = 1u, ///< DMA channel 1 + DmaCh2 = 2u, ///< DMA channel 2 + DmaCh3 = 3u, ///< DMA channel 3 + DmaChMax = 4u ///< DMA channel max +}en_dma_channel_t; + +/** + ******************************************************************************* + ** \brief DMA transfer data width + ** + ******************************************************************************/ +typedef enum en_dma_transfer_width +{ + Dma8Bit = 0u, ///< 8 bit transfer via DMA + Dma16Bit = 1u, ///< 16 bit transfer via DMA + Dma32Bit = 2u ///< 32 bit transfer via DMA +}en_dma_transfer_width_t; + +/** + ******************************************************************************* + ** \brief DMA flag + ** + ******************************************************************************/ +typedef enum en_dma_flag +{ + DmaTransferComplete = 0u, ///< DMA transfer complete + DmaBlockComplete = 1u, ///< DMA block transfer complete + DmaTransferErr = 2u, ///< DMA transfer error + DmaReqErr = 3u, ///< DMA transfer request error + DmaFlagMax = 4u +}en_dma_flag_t; + +/** + ******************************************************************************* + ** \brief DMA address mode + ** + ******************************************************************************/ +typedef enum en_dma_address_mode +{ + AddressFix = 0u, ///< Address fixed + AddressIncrease = 1u, ///< Address increased + AddressDecrease = 2u, ///< Address decreased +}en_dma_address_mode_t; + +/** + ******************************************************************************* + ** \brief DMA link list pointer mode + ** + ******************************************************************************/ +typedef enum en_dma_llp_mode +{ + LlpWaitNextReq = 0u, ///< DMA trigger transfer after wait next request + LlpRunNow = 1u, ///< DMA trigger transfer now +}en_dma_llp_mode_t; + +/** + ******************************************************************************* + ** \brief DMA interrupt selection + ** + ******************************************************************************/ +typedef enum en_dma_irq_sel +{ + TrnErrIrq = 0u, ///< Select DMA transfer error interrupt + TrnReqErrIrq = 1u, ///< Select DMA transfer req over error interrupt + TrnCpltIrq = 2u, ///< Select DMA transfer completion interrupt + BlkTrnCpltIrq = 3u, ///< Select DMA block completion interrupt + DmaIrqSelMax = 4u +}en_dma_irq_sel_t; + +/** + ******************************************************************************* + ** \brief DMA re_config count mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_cnt_mode +{ + CntFix = 0u, ///< Fix + CntSrcAddr = 1u, ///< Source address mode + CntDesAddr = 2u, ///< Destination address mode +}en_dma_recfg_cnt_mode_t; + +/** + ******************************************************************************* + ** \brief DMA re_config destination address mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_daddr_mode +{ + DaddrFix = 0u, ///< Fix + DaddrNseq = 1u, ///< No_sequence address + DaddrRep = 2u, ///< Repeat address +}en_dma_recfg_daddr_mode_t; + +/** + ******************************************************************************* + ** \brief DMA re_config source address mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_saddr_mode +{ + SaddrFix = 0u, ///< Fix + SaddrNseq = 1u, ///< No_sequence address + SaddrRep = 2u, ///< Repeat address +}en_dma_recfg_saddr_mode_t; + +/** + ******************************************************************************* + ** \brief DMA channel status + ** + ******************************************************************************/ +typedef enum en_dma_ch_flag +{ + DmaSta = 0u, ///< DMA status. + ReCfgSta = 1u, ///< DMA re_configuration status. + DmaCh0Sta = 2u, ///< DMA channel 0 status. + DmaCh1Sta = 3u, ///< DMA channel 1 status. + DmaCh2Sta = 4u, ///< DMA channel 2 status. + DmaCh3Sta = 5u, ///< DMA channel 3 status. +}en_dma_ch_flag_t; + +/** + ******************************************************************************* + ** \brief DMA common trigger source select + ** + ******************************************************************************/ +typedef enum en_dma_com_trigger +{ + DmaComTrigger_1 = 0x1, ///< Select common trigger 1. + DmaComTrigger_2 = 0x2, ///< Select common trigger 2. + DmaComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_dma_com_trigger_t; + +/** + ******************************************************************************* + ** \brief DMA llp descriptor + ** + ******************************************************************************/ +typedef struct stc_dma_llp_descriptor +{ + uint32_t SARx; ///< DMA source address register + uint32_t DARx; ///< DMA destination address register + union + { + uint32_t DTCTLx; + stc_dma_dtctl_field_t DTCTLx_f; ///< DMA data control register + }; + union + { + uint32_t RPTx; + stc_dma_rpt_field_t RPTx_f; ///< DMA repeat control register + }; + union + { + uint32_t SNSEQCTLx; + stc_dma_snseqctl_field_t SNSEQCTLx_f; ///< DMA source no-sequence control register + }; + union + { + __IO uint32_t DNSEQCTLx; + stc_dma_dnseqctl_field_t DNSEQCTLx_f; ///< DMA destination no-sequence control register + }; + union + { + uint32_t LLPx; + stc_dma_llp_field_t LLPx_f; ///< DMA link-list-pointer register + }; + union + { + uint32_t CHxCTL; + stc_dma_ch0ctl_field_t CHxCTL_f; ///< DMA channel control register + }; +}stc_dma_llp_descriptor_t; + +/** + ******************************************************************************* + ** \brief DMA no-sequence function configuration + ** + ******************************************************************************/ +typedef struct stc_dma_nseq_cfg +{ + uint32_t u32Offset; ///< DMA no-sequence offset. + uint16_t u16Cnt; ///< DMA no-sequence count. +}stc_dma_nseq_cfg_t; + +/** + ******************************************************************************* + ** \brief DMA no-sequence function configuration + ** + ******************************************************************************/ +typedef struct stc_dma_nseqb_cfg +{ + uint32_t u32NseqDist; ///< DMA no-sequence district interval. + uint16_t u16CntB; ///< DMA no-sequence count. +}stc_dma_nseqb_cfg_t; + +/** + ******************************************************************************* + ** \brief DMA re_config configuration + ** + ******************************************************************************/ +typedef struct stc_dma_recfg_ctl +{ + uint16_t u16SrcRptBSize; ///< The source repeat size. + uint16_t u16DesRptBSize; ///< The destination repeat size. + en_dma_recfg_saddr_mode_t enSaddrMd; ///< DMA re_config source address mode. + en_dma_recfg_daddr_mode_t enDaddrMd; ///< DMA re_config destination address mode. + en_dma_recfg_cnt_mode_t enCntMd; ///< DMA re_config count mode. + stc_dma_nseq_cfg_t stcSrcNseqBCfg; ///< The source no_sequence re_config. + stc_dma_nseq_cfg_t stcDesNseqBCfg; ///< The destination no_sequence re_config. +}stc_dma_recfg_ctl_t; + +/** + ******************************************************************************* + ** \brief DMA channel configuration + ** + ******************************************************************************/ +typedef struct stc_dma_ch_cfg +{ + en_dma_address_mode_t enSrcInc; ///< DMA source address update mode. + en_dma_address_mode_t enDesInc; ///< DMA destination address update mode. + en_functional_state_t enSrcRptEn; ///< Enable source repeat function or not. + en_functional_state_t enDesRptEn; ///< Enable destination repeat function or not. + en_functional_state_t enSrcNseqEn; ///< Enable source no_sequence function or not. + en_functional_state_t enDesNseqEn; ///< Enable destination no_sequence function or not. + en_dma_transfer_width_t enTrnWidth; ///< DMA transfer data width. + en_functional_state_t enLlpEn; ///< Enable linked list pointer function or not. + en_dma_llp_mode_t enLlpMd; ///< Dma linked list pointer mode. + en_functional_state_t enIntEn; ///< Enable interrupt function or not. +}stc_dma_ch_cfg_t; + + +/** + ******************************************************************************* + ** \brief DMA configuration + ** + ******************************************************************************/ +typedef struct stc_dma_config +{ + uint16_t u16BlockSize; ///< Transfer block size = 1024, when 0 is set. + uint16_t u16TransferCnt; ///< Transfer counter. + uint32_t u32SrcAddr; ///< The source address. + uint32_t u32DesAddr; ///< The destination address. + uint16_t u16SrcRptSize; ///< The source repeat size. + uint16_t u16DesRptSize; ///< The destination repeat size. + uint32_t u32DmaLlp; ///< The Dma linked list pointer address + stc_dma_nseq_cfg_t stcSrcNseqCfg; ///< The source no_sequence configuration. + stc_dma_nseq_cfg_t stcDesNseqCfg; ///< The destination no_sequence configuration. + stc_dma_ch_cfg_t stcDmaChCfg; ///< The Dma channel configuration. +}stc_dma_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState); +en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState); +void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_recfg_ctl_t* pstcDmaReCfg); +void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg,en_functional_state_t enNewState); +en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag); + +en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address); +en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address); +en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize); +en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt); +en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetDesRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstcSrcNseqCfg); +en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg); +en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstDesNseqCfg); +en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstDesNseqBCfg); +en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer); + +void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc); +void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc); +void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState); +void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState); + +void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_ch_cfg_t* pstcChCfg); +void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_config_t* pstcDmaCfg); +void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); + + + +//@} // DmacGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_DMAC_ENABLE */ + +#endif /* __HC32F460_DMAC_H__*/ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_efm.h b/driver/inc/hc32f460_efm.h new file mode 100644 index 0000000..a6185bb --- /dev/null +++ b/driver/inc/hc32f460_efm.h @@ -0,0 +1,209 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_efm.h + ** + ** A detailed description is available at + ** @link EfmGroup EFM description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of EFM. + ** + ******************************************************************************/ +#ifndef __HC32F460_EFM_H__ +#define __HC32F460_EFM_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EFM_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup EfmGroup Embedded Flash Management unit(EFM) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The flash status. + ** + ******************************************************************************/ +typedef enum en_efm_flash_status +{ + FlashReady = 1u, ///< The flash ready flag. + FlashRWErr = 2u, ///< The flash read/write error flag. + FlashEOP = 3u, ///< The flash end of operation flag. + FlashPgMissMatch = 4u, ///< The flash program miss match flag. + FlashPgSizeErr = 5u, ///< The flash program size error flag. + FlashPgareaPErr = 6u, ///< The flash program protect area error flag. + FlashWRPErr = 7u, ///< The flash write protect error flag. +}en_efm_flash_status_t; + +/** + ******************************************************************************* + ** \brief The flash read mode. + ** + ******************************************************************************/ +typedef enum en_efm_read_md +{ + NormalRead = 0u, ///< The flash normal read mode. + UltraPowerRead = 1u, ///< The flash ultra power read mode. +}en_efm_read_md_t; + +/** + ******************************************************************************* + ** \brief The flash interrupt select. + ** + ******************************************************************************/ +typedef enum en_efm_int_sel +{ + PgmErsErrInt = 0u, ///< The flash program / erase error interrupt. + EndPgmInt = 1u, ///< The flash end of program interrupt. + ColErrInt = 2u, ///< The flash read collided error interrupt. +}en_efm_int_sel_t; + +/** + ******************************************************************************* + ** \brief The bus state while flash program & erase. + ** + ******************************************************************************/ +typedef enum en_efm_bus_sta +{ + BusBusy = 0u, ///< The bus busy while flash program & erase. + BusRelease = 1u, ///< The bus release while flash program & erase. +}en_efm_bus_sta_t; + +/** + ******************************************************************************* + ** \brief Structure of windows protect address. + ** + ** \note None. + ** + ******************************************************************************/ +typedef struct stc_efm_win_protect_addr +{ + uint32_t StartAddr; ///< The protect start address. + uint32_t EndAddr; ///< The protect end address. +}stc_efm_win_protect_addr_t; + +/** + ******************************************************************************* + ** \brief Structure of unique ID. + ** + ** \note None. + ** + ******************************************************************************/ +typedef struct stc_efm_unique_id +{ + uint32_t uniqueID1; ///< unique ID 1. + uint32_t uniqueID2; ///< unique ID 2. + uint32_t uniqueID3; ///< unique ID 3. +}stc_efm_unique_id_t; +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + /* Flach latency cycle (0~15) */ +#define EFM_LATENCY_0 (0ul) +#define EFM_LATENCY_1 (1ul) +#define EFM_LATENCY_2 (2ul) +#define EFM_LATENCY_3 (3ul) +#define EFM_LATENCY_4 (4ul) +#define EFM_LATENCY_5 (5ul) +#define EFM_LATENCY_6 (6ul) +#define EFM_LATENCY_7 (7ul) +#define EFM_LATENCY_8 (8ul) +#define EFM_LATENCY_9 (9ul) +#define EFM_LATENCY_10 (10ul) +#define EFM_LATENCY_11 (11ul) +#define EFM_LATENCY_12 (12ul) +#define EFM_LATENCY_13 (13ul) +#define EFM_LATENCY_14 (14ul) +#define EFM_LATENCY_15 (15ul) + +/* Flash flag */ +#define EFM_FLAG_WRPERR (0x00000001ul) +#define EFM_FLAG_PEPRTERR (0x00000002ul) +#define EFM_FLAG_PGSZERR (0x00000004ul) +#define EFM_FLAG_PGMISMTCH (0x00000008ul) +#define EFM_FLAG_EOP (0x00000010ul) +#define EFM_FLAG_COLERR (0x00000020ul) +#define EFM_FLAG_RDY (0x00000100ul) + +/* Flash operate mode */ +#define EFM_MODE_READONLY (0ul) +#define EFM_MODE_SINGLEPROGRAM (1ul) +#define EFM_MODE_SINGLEPROGRAMRB (2ul) +#define EFM_MODE_SEQUENCEPROGRAM (3ul) +#define EFM_MODE_SECTORERASE (4ul) +#define EFM_MODE_CHIPERASE (5ul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void EFM_Unlock(void); +void EFM_Lock(void); + +void EFM_FlashCmd(en_functional_state_t enNewState); +void EFM_SetLatency(uint32_t u32Latency); +void EFM_InstructionCacheCmd(en_functional_state_t enNewState); +void EFM_DataCacheRstCmd(en_functional_state_t enNewState); +void EFM_SetReadMode(en_efm_read_md_t enReadMD); +void EFM_ErasePgmCmd(en_functional_state_t enNewState); +en_result_t EFM_SetErasePgmMode(uint32_t u32Mode); +void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState); + +en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag); +en_flag_status_t EFM_GetSwitchStatus(void); +void EFM_ClearFlag(uint32_t u32flag); +en_efm_flash_status_t EFM_GetStatus(void); +void EFM_SetBusState(en_efm_bus_sta_t enState); + +void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr); + +en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data); +en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data); +en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf); +en_result_t EFM_SectorErase(uint32_t u32Addr); +en_result_t EFM_MassErase(uint32_t u32Addr); + +en_result_t EFM_OtpLock(uint32_t u32Addr); +stc_efm_unique_id_t EFM_ReadUID(void); + + +//@} // EfmGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EFM_ENABLE */ + +#endif /* __HC32F460_EFM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/inc/hc32f460_emb.h b/driver/inc/hc32f460_emb.h new file mode 100644 index 0000000..0820870 --- /dev/null +++ b/driver/inc/hc32f460_emb.h @@ -0,0 +1,205 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_emb.h + ** + ** A detailed description is available at + ** @link EMBGroup EMB description @endlink + ** + ** - 2018-11-24 CDT First version for Device Driver Library of EMB. + ** + ******************************************************************************/ +#ifndef __HC32F460_EMB_H__ +#define __HC32F460_EMB_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EMB_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + ******************************************************************************* + ** \defgroup EMBGroup Emergency Brake(EMB) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief EMB status enumeration + ******************************************************************************/ +typedef enum en_emb_status +{ + EMBFlagPortIn = 0u, ///< EMB port in brake flag + EMBFlagPWMSame = 1u, ///< EMB PWM same brake flag + EMBFlagCmp = 2u, ///< EMB CMP brake flag + EMBFlagOSCFail = 3u, ///< EMB oscillator fail brake flag + EMBPortInState = 4u, ///< EMB port in state + EMBPWMState = 5u, ///< EMB PWM same state +} en_emb_status_t; + +/** + ******************************************************************************* + ** \brief EMB status clear(recover) enumeration + ******************************************************************************/ +typedef enum en_emb_status_clr +{ + EMBPortInFlagClr = 0u, ///< EMB port in brake flag clear + EMBPWMSameFlagCLr = 1u, ///< EMB PWM same brake flag clear + EMBCmpFlagClr = 2u, ///< EMB CMP brake flag clear + EMBOSCFailFlagCLr = 3u, ///< EMB oscillator fail brake flag clear +} en_emb_status_clr_t; + +/** + ******************************************************************************* + ** \brief EMB irq enumeration + ******************************************************************************/ +typedef enum en_emb_irq_type +{ + PORTBrkIrq = 0u, ///< EMB port brake interrupt + PWMSmBrkIrq = 1u, ///< EMB PWM same brake interrupt + CMPBrkIrq = 2u, ///< EMB CMP brake interrupt + OSCFailBrkIrq = 3u, ///< EMB oscillator fail brake interrupt +} en_emb_irq_type_t; + +/** + ******************************************************************************* + ** \brief EMB port in filter enumeration + ******************************************************************************/ +typedef enum en_emb_port_filter +{ + EMBPortFltDiv0 = 0u, ///< EMB port in filter with PCLK clock + EMBPortFltDiv8 = 1u, ///< EMB port in filter with PCLK/8 clock + EMBPortFltDiv32 = 2u, ///< EMB port in filter with PCLK/32 clock + EMBPortFltDiv128 = 3u, ///< EMB port in filter with PCLK/128 clock +} en_emb_port_filter_t; + +/** + ******************************************************************************* + ** \brief EMB CR0 for timer6 config + ** \note + ******************************************************************************/ +typedef struct stc_emb_ctrl_timer6 +{ + bool bEnPortBrake; ///< Enable port brake + bool bEnCmp1Brake; ///< Enable CMP1 brake + bool bEnCmp2Brake; ///< Enable CMP2 brake + bool bEnCmp3Brake; ///< Enable CMP3 brake + bool bEnOSCFailBrake; ///< Enable OSC fail brake + bool bEnTimer61PWMSBrake; ///< Enable tiemr61 PWM same brake + bool bEnTimer62PWMSBrake; ///< Enable tiemr62 PWM same brake + bool bEnTimer63PWMSBrake; ///< Enable tiemr63 PWM same brake + en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection + bool bEnPorInFlt; ///< Enable port in filter + bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel +}stc_emb_ctrl_timer6_t; + +/** + ******************************************************************************* + ** \brief EMB CR1~3 for timer4x config + ** \note + ******************************************************************************/ +typedef struct stc_emb_ctrl_timer4 +{ + bool bEnPortBrake; ///< Enable port brake + bool bEnCmp1Brake; ///< Enable CMP1 brake + bool bEnCmp2Brake; ///< Enable CMP2 brake + bool bEnCmp3Brake; ///< Enable CMP3 brake + bool bEnOSCFailBrake; ///< Enable OS fail brake + bool bEnTimer4xWHLSammeBrake; ///< Enable tiemr4x PWM WH WL same brake + bool bEnTimer4xVHLSammeBrake; ///< Enable tiemr4x PWM VH VL same brake + bool bEnTimer4xUHLSammeBrake; ///< Enable tiemr4x PWM UH UL same brake + en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection + bool bEnPorInFlt; ///< Enable port in filter + bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel +}stc_emb_ctrl_timer4_t; + + +/** + ******************************************************************************* + ** \brief EMB PWM level detect timer6 config + ** \note + ******************************************************************************/ +typedef struct stc_emb_pwm_level_timer6 +{ + bool bEnTimer61HighLevelDect; ///< Enable tiemr61 active detected level 1:HighLevel 0:LowLevel + bool bEnTimer62HighLevelDect; ///< Enable tiemr62 active detected level 1:HighLevel 0:LowLevel + bool bEnTimer63HighLevelDect; ///< Enable tiemr63 active detected level 1:HighLevel 0:LowLevel +}stc_emb_pwm_level_timer6_t; + +/** + ******************************************************************************* + ** \brief EMB PWM level detect timer4x config + ** \note + ******************************************************************************/ +typedef struct stc_emb_pwm_level_timer4 +{ + bool bEnUHLPhaseHighLevelDect; ///< Enable tiemr4x UH UL active detected level 1:HighLevel 0:LowLevel + bool bEnVHLPhaseHighLevelDect; ///< Enable tiemr4x VH VL active detected level 1:HighLevel 0:LowLevel + bool bEnWHLphaseHighLevelDect; ///< Enable tiemr4x WH WL active detected level 1:HighLevel 0:LowLevel +}stc_emb_pwm_level_timer4_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* IRQ config */ +en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx, + en_emb_irq_type_t enEMBIrq, + bool bEn); +/* Get status(flag) */ +bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus); +/* Status(flag) clear (recover) */ +en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx, + en_emb_status_clr_t enStatusClr); +/* Control Register(CTL) config for timer6 */ +en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR); +/* Control Register(CTL) config for timer4 */ +en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_ctrl_timer4_t* pstcEMBConfigCR); +/* PWM level detect (short detection) selection config for timer6 */ +en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv); +/* PWM level detect (short detection) selection config for timer4 */ +en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv); +/* Software brake */ +en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn); + +//@} // EMBGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EMB_ENABLE */ + +#endif /* __HC32F460_EMB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_event_port.h b/driver/inc/hc32f460_event_port.h new file mode 100644 index 0000000..8833829 --- /dev/null +++ b/driver/inc/hc32f460_event_port.h @@ -0,0 +1,176 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_event_port.h + ** + ** A detailed description is available at + ** @link EventPortGroup EventPort description @endlink + ** + ** - 2018-12-07 CDT First version for Device Driver Library of EventPort. + ** + ******************************************************************************/ + +#ifndef __HC32F460_EVENT_PORT_H__ +#define __HC32F460_EVENT_PORT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EVENT_PORT_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup EventPortGroup Event Port (EventPort) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Event Port Index enumeration + ** + ******************************************************************************/ +typedef enum en_event_port +{ + EventPort1 = 0, ///< Event port 1 + EventPort2 = 1, ///< Event port 2 + EventPort3 = 2, ///< Event port 3 + EventPort4 = 3, ///< Event port 4 +}en_event_port_t; + +/** + ******************************************************************************* + ** \brief Event Port Pin enumeration + ** + ******************************************************************************/ +typedef enum en_event_pin +{ + EventPin00 = 1u << 0, ///< Event port Pin 00 + EventPin01 = 1u << 1, ///< Event port Pin 01 + EventPin02 = 1u << 2, ///< Event port Pin 02 + EventPin03 = 1u << 3, ///< Event port Pin 03 + EventPin04 = 1u << 4, ///< Event port Pin 04 + EventPin05 = 1u << 5, ///< Event port Pin 05 + EventPin06 = 1u << 6, ///< Event port Pin 06 + EventPin07 = 1u << 7, ///< Event port Pin 07 + EventPin08 = 1u << 8, ///< Event port Pin 08 + EventPin09 = 1u << 9, ///< Event port Pin 09 + EventPin10 = 1u << 10, ///< Event port Pin 10 + EventPin11 = 1u << 11, ///< Event port Pin 11 + EventPin12 = 1u << 12, ///< Event port Pin 12 + EventPin13 = 1u << 13, ///< Event port Pin 13 + EventPin14 = 1u << 14, ///< Event port Pin 14 + EventPin15 = 1u << 15, ///< Event port Pin 15 + EventPinAll= 0xFFFF, ///< All event pins are selected +}en_event_pin_t; + +/** + ******************************************************************************* + ** \brief Event Port common trigger source select + ** + ******************************************************************************/ +typedef enum en_event_port_com_trigger +{ + EpComTrigger_1 = 0x1, ///< Select common trigger 1. + EpComTrigger_2 = 0x2, ///< Select common trigger 2. + EpComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_event_port_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Event Port direction enumeration + ** + ******************************************************************************/ +typedef enum en_event_port_dir +{ + EventPortIn = 0, ///< Event Port direction 'IN' + EventPortOut = 1, ///< Event Port direction 'OUT' +}en_event_port_dir_t; + +/** + ******************************************************************************* + ** \brief Enumeration to filter clock setting for Event port detect + ** + ** \note + ******************************************************************************/ +typedef enum en_ep_flt_clk +{ + Pclk1Div1 = 0u, ///< PCLK1 as EP filter clock source + Pclk1Div8 = 1u, ///< PCLK1 div8 as EP filter clock source + Pclk1Div32 = 2u, ///< PCLK1 div32 as EP filter clock source + Pclk1Div64 = 3u, ///< PCLK1 div64 as EP filter clock source +}en_ep_flt_clk_t; + +/** + ******************************************************************************* + ** \brief Event port init structure definition + ******************************************************************************/ +typedef struct stc_event_port_init +{ + en_event_port_dir_t enDirection; ///< Input/Output setting + en_functional_state_t enReset; ///< Corresponding pin reset after triggered + en_functional_state_t enSet; ///< Corresponding pin set after triggered + en_functional_state_t enRisingDetect; ///< Rising edge detect enable + en_functional_state_t enFallingDetect;///< Falling edge detect enable + en_functional_state_t enFilter; ///< Filter clock source select + en_ep_flt_clk_t enFilterClk; ///< Filter clock, ref@ en_ep_flt_clk_t for details +}stc_event_port_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t EVENTPORT_Init(en_event_port_t enEventPort, \ + uint16_t u16EventPin, const stc_event_port_init_t *pstcEventPortInit); +extern en_result_t EVENTPORT_DeInit(void); +extern en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort, \ + en_event_src_t enTriggerSrc); +void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort, \ + en_event_port_com_trigger_t enComTrigger, \ + en_functional_state_t enState); +extern uint16_t EVENTPORT_GetData(en_event_port_t enEventPort); +extern en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort, \ + en_event_pin_t enEventPin); +extern en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort, \ + en_event_pin_t u16EventPin); +extern en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort, \ + en_event_pin_t u16EventPin); + +//@} // EventPortGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EVENT_PORT_ENABLE */ + +#endif /* __HC32F460_EVENT_PORT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_exint_nmi_swi.h b/driver/inc/hc32f460_exint_nmi_swi.h new file mode 100644 index 0000000..eeb69fc --- /dev/null +++ b/driver/inc/hc32f460_exint_nmi_swi.h @@ -0,0 +1,257 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_exint_nmi_swi.h + ** + ** A detailed description is available at + ** @link ExintNmiSwiGroup Exint/Nmi/Swi description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of exint, Nmi, SW interrupt. + ** + ******************************************************************************/ + +#ifndef __HC32F460_EXINT_NMI_SWI_H__ +#define __HC32F460_EXINT_NMI_SWI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup ExintNmiSwiGroup External Interrupts (External Interrupt), \ + ** NMI (Non-Maskable Interrupt), SWI (Software Interrupt) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Enumeration to filter clock setting for EXINT and NMI + ** + ** \note + ******************************************************************************/ +typedef enum en_ei_flt_clk +{ + Pclk3Div1 = 0u, ///< PCLK3 as EP filter clock source + Pclk3Div8 = 1u, ///< PCLK3 div8 as EP filter clock source + Pclk3Div32 = 2u, ///< PCLK3 div32 as EP filter clock source + Pclk3Div64 = 3u, ///< PCLK3 div64 as EP filter clock source +}en_ei_flt_clk_t; + +/** + ******************************************************************************* + ** \brief Enumeration to NMI detection + ** + ** \note + ******************************************************************************/ +typedef enum en_nmi_lvl +{ + NmiFallingEdge = 0u, ///< Falling edge detection + NmiRisingEdge = 1u, ///< Rising edge detection +}en_nmi_lvl_t; + +/** + ******************************************************************************* + ** \brief Enumeration to EXTI detection + ** + ** \note + ******************************************************************************/ +typedef enum en_exti_lvl +{ + ExIntFallingEdge = 0u, ///< Falling edge detection + ExIntRisingEdge = 1u, ///< Rising edge detection + ExIntBothEdge = 2u, ///< Falling or Rising edge detection + ExIntLowLevel = 3u, ///< "L" level detection +}en_exti_lvl_t; + +/** + ******************************************************************************* + ** \brief Enumeration to define an index for EXINT + ******************************************************************************/ +typedef enum en_exti_ch +{ + ExtiCh00 = 0u, + ExtiCh01 = 1u, + ExtiCh02 = 2u, + ExtiCh03 = 3u, + ExtiCh04 = 4u, + ExtiCh05 = 5u, + ExtiCh06 = 6u, + ExtiCh07 = 7u, + ExtiCh08 = 8u, + ExtiCh09 = 9u, + ExtiCh10 = 10u, + ExtiCh11 = 11u, + ExtiCh12 = 12u, + ExtiCh13 = 13u, + ExtiCh14 = 14u, + ExtiCh15 = 15u, +}en_exti_ch_t; + +/** + ******************************************************************************* + ** \brief Enumeration to define the SWI channel + ******************************************************************************/ +typedef enum en_swi_ch +{ + SwiCh00 = 1u << 0, + SwiCh01 = 1u << 1, + SwiCh02 = 1u << 2, + SwiCh03 = 1u << 3, + SwiCh04 = 1u << 4, + SwiCh05 = 1u << 5, + SwiCh06 = 1u << 6, + SwiCh07 = 1u << 7, + SwiCh08 = 1u << 8, + SwiCh09 = 1u << 9, + SwiCh10 = 1u << 10, + SwiCh11 = 1u << 11, + SwiCh12 = 1u << 12, + SwiCh13 = 1u << 13, + SwiCh14 = 1u << 14, + SwiCh15 = 1u << 15, + SwiCh16 = 1u << 16, + SwiCh17 = 1u << 17, + SwiCh18 = 1u << 18, + SwiCh19 = 1u << 19, + SwiCh20 = 1u << 20, + SwiCh21 = 1u << 21, + SwiCh22 = 1u << 22, + SwiCh23 = 1u << 23, + SwiCh24 = 1u << 24, + SwiCh25 = 1u << 25, + SwiCh26 = 1u << 26, + SwiCh27 = 1u << 27, + SwiCh28 = 1u << 28, + SwiCh29 = 1u << 29, + SwiCh30 = 1u << 30, + SwiCh31 = 1u << 31, +}en_swi_ch_t; + +/** + ******************************************************************************* + ** \brief External Interrupt configuration + ** + ** \note The EXINT configuration + ******************************************************************************/ +typedef struct stc_exint_config +{ + en_exti_ch_t enExitCh; ///< External Int CH.0~15 ref@ en_exti_ch_t + en_functional_state_t enFilterEn; ///< TRUE: Enable filter function + en_ei_flt_clk_t enFltClk; ///< Filter clock, ref@ en_ei_flt_clk_t for details + en_exti_lvl_t enExtiLvl; ///< Detection level, ref@ en_exti_lvl_t for details +}stc_exint_config_t; + +/** + ******************************************************************************* + ** \brief Enumeration to NMI Trigger source + ** + ** \note + ******************************************************************************/ +typedef enum en_nmi_src +{ + NmiSrcNmi = 1u << 0, ///< NMI pin + NmiSrcSwdt = 1u << 1, ///< Special watch dog timer + NmiSrcVdu1 = 1u << 2, ///< Voltage detect 1 + NmiSrcVdu2 = 1u << 3, ///< Voltage detect 2 + NmiSrcXtalStop = 1u << 5, ///< Xtal stop + NmiSrcSramPE = 1u << 8, ///< SRAM1/2/HS/Ret parity error + NmiSrcSramDE = 1u << 9, ///< SRAM3 ECC error + NmiSrcMpu = 1u << 10, ///< MPU error + NmiSrcWdt = 1u << 11, ///< Watch dog timer +}en_nmi_src_t; + +/** + ******************************************************************************* + ** \brief Enumeration to software interrupt or event + ** + ** \note + ******************************************************************************/ +typedef enum en_swi_type +{ + SwEvent = 0u, ///< software event + SwInt = 1u, ///< software interrupt +}en_swi_type_t; + + +/** + ******************************************************************************* + ** \brief NMI configuration + ** + ** \note The NMI configuration + ******************************************************************************/ +typedef struct stc_nmi_config +{ + en_functional_state_t enFilterEn; ///< TRUE: Enable filter function + en_ei_flt_clk_t enFilterClk; ///< Filter clock, ref@ en_flt_clk_t for details + en_nmi_lvl_t enNmiLvl; ///< Detection level, ref@ en_nmi_lvl_t for details + uint16_t u16NmiSrc; ///< NMI trigger source, ref@ en_nmi_src_t for details + func_ptr_t pfnNmiCallback; ///< Callback pointers +}stc_nmi_config_t; + +/** + ******************************************************************************* + ** \brief SWI configuration + ** + ** \note The SWI configuration + ******************************************************************************/ +typedef struct stc_swi_config +{ + en_swi_ch_t enSwiCh; ///< SWI channel + en_swi_type_t enSwiType; ///< Select software interrupt or event + func_ptr_t pfnSwiCallback; ///< Callback pointers +}stc_swi_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t EXINT_Init(const stc_exint_config_t *pstcExtiConfig); +extern en_int_status_t EXINT_IrqFlgGet(en_exti_ch_t enExint); +extern en_result_t EXINT_IrqFlgClr(en_exti_ch_t enExint); +extern en_result_t NMI_Init(const stc_nmi_config_t *pstcNmiConfig); +extern en_result_t NMI_DeInit(void); +extern en_int_status_t NMI_IrqFlgGet(en_nmi_src_t enNmiSrc); +extern en_result_t NMI_IrqFlgClr(uint16_t u16NmiSrc); +extern en_result_t SWI_Enable(uint32_t u32SwiCh); +extern en_result_t SWI_Disable(uint32_t u32SwiCh); + +//@} // ExintNmiSwiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EXINT_NMI_SWI_ENABLE */ + +#endif /* __HC32F460_EXINT_NMI_SWI_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_gpio.h b/driver/inc/hc32f460_gpio.h new file mode 100644 index 0000000..b553de1 --- /dev/null +++ b/driver/inc/hc32f460_gpio.h @@ -0,0 +1,294 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_gpio.h + ** + ** A detailed description is available at + ** @link GpioGroup Gpio description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of Gpio. + ** + ******************************************************************************/ + +#ifndef __HC32F460_GPIO_H__ +#define __HC32F460_GPIO_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_GPIO_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup GpioGroup General Purpose Input/Output(GPIO) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief GPIO Configuration Mode enumeration + ** + ******************************************************************************/ +typedef enum en_pin_mode +{ + Pin_Mode_In = 0, ///< GPIO Input mode + Pin_Mode_Out = 1, ///< GPIO Output mode + Pin_Mode_Ana = 2, ///< GPIO Analog mode +}en_pin_mode_t; + +/** + ******************************************************************************* + ** \brief GPIO Drive Capacity enumeration + ** + ******************************************************************************/ +typedef enum en_pin_drv +{ + Pin_Drv_L = 0, ///< Low Drive Capacity + Pin_Drv_M = 1, ///< Middle Drive Capacity + Pin_Drv_H = 2, ///< High Drive Capacity +}en_pin_drv_t; + +/** + ******************************************************************************* + ** \brief GPIO Output Type enumeration + ******************************************************************************/ +typedef enum en_pin_o_type +{ + Pin_OType_Cmos = 0, ///< CMOS + Pin_OType_Od = 1, ///< Open Drain +}en_pin_o_type_t; + + +typedef enum en_debug_port +{ + TCK_SWCLK = 1 << 0, ///< TCK or SWCLK + TMS_SWDIO = 1 << 1, ///< TMS or SWDIO + TDO_SWO = 1 << 2, ///< TOD or SWD + TDI = 1 << 3, ///< TDI + TRST = 1 << 4, ///< TRest + ALL_DBG_PIN = 0x1Fu ///< All above +}en_debug_port_t; +/** + ******************************************************************************* + ** \brief GPIO Port Index enumeration + ******************************************************************************/ +typedef enum en_port +{ + PortA = 0, ///< port group A + PortB = 1, ///< port group B + PortC = 2, ///< port group C + PortD = 3, ///< port group D + PortE = 4, ///< port group E + PortH = 5, ///< port group H +}en_port_t; + +/** + ******************************************************************************* + ** \brief GPIO Pin Index enumeration + ******************************************************************************/ +typedef enum en_pin +{ + Pin00 = (1 << 0), ///< Pin index 00 of each port group + Pin01 = (1 << 1), ///< Pin index 01 of each port group + Pin02 = (1 << 2), ///< Pin index 02 of each port group + Pin03 = (1 << 3), ///< Pin index 03 of each port group + Pin04 = (1 << 4), ///< Pin index 04 of each port group + Pin05 = (1 << 5), ///< Pin index 05 of each port group + Pin06 = (1 << 6), ///< Pin index 06 of each port group + Pin07 = (1 << 7), ///< Pin index 07 of each port group + Pin08 = (1 << 8), ///< Pin index 08 of each port group + Pin09 = (1 << 9), ///< Pin index 09 of each port group + Pin10 = (1 << 10), ///< Pin index 10 of each port group + Pin11 = (1 << 11), ///< Pin index 11 of each port group + Pin12 = (1 << 12), ///< Pin index 12 of each port group + Pin13 = (1 << 13), ///< Pin index 13 of each port group + Pin14 = (1 << 14), ///< Pin index 14 of each port group + Pin15 = (1 << 15), ///< Pin index 15 of each port group + PinAll= 0xFFFF, ///< All pins selected +}en_pin_t; + +/** + ******************************************************************************* + ** \brief GPIO Pin read wait cycle enumeration + ******************************************************************************/ +typedef enum en_read_wait +{ + WaitCycle0 = 0, ///< no wait cycle, operation freq. lower than 42MHz + WaitCycle1 = 1, ///< one wait cycle, operation freq. @[42~84)MHz + WaitCycle2 = 2, ///< two wait cycles, operation freq. @[84~126)MHz + WaitCycle3 = 3, ///< three wait cycles, operation freq. @[126~200)MHz +}en_read_wait_t; + +/** + ******************************************************************************* + ** \brief GPIO Function enumeration + ******************************************************************************/ +typedef enum en_port_func +{ + Func_Gpio = 0u, ///< function set to gpio + Func_Fcmref = 1u, ///< function set to fcm reference + Func_Rtcout = 1u, ///< function set to rtc output + Func_Vcout = 1u, ///< function set to vc output + Func_Adtrg = 1u, ///< function set to adc trigger + Func_Mclkout = 1u, ///< function set to mclk output + Func_Tim4 = 2u, ///< function set to timer4 + Func_Tim6 = 3u, ///< function set to timer6 + Func_Tima0 = 4u, ///< function set to timerA + Func_Tima1 = 5u, ///< function set to timerA + Func_Tima2 = 6u, ///< function set to timerA + Func_Emb = 6u, ///< function set to emb + Func_Usart_Ck = 7u, ///< function set to usart clk + Func_Spi_Nss = 7u, ///< function set to spi nss + Func_Qspi = 7u, ///< function set to qspi + Func_Key = 8u, ///< function set to key + Func_Sdio = 9u, ///< function set to sdio + Func_I2s = 10u, ///< function set to i2s + Func_UsbF = 10u, ///< function set to usb full speed + Func_Evnpt = 14u, ///< function set to event port + Func_Eventout = 15u, ///< function set to event out + Func_Usart1_Tx = 32u, ///< function set to usart tx of ch.1 + Func_Usart3_Tx = 32u, ///< function set to usart tx of ch.3 + Func_Usart1_Rx = 33u, ///< function set to usart rx of ch.1 + Func_Usart3_Rx = 33u, ///< function set to usart rx of ch.3 + Func_Usart1_Rts = 34u, ///< function set to usart rts of ch.1 + Func_Usart3_Rts = 34u, ///< function set to usart rts of ch.3 + Func_Usart1_Cts = 35u, ///< function set to usart cts of ch.1 + Func_Usart3_Cts = 35u, ///< function set to usart cts of ch.3 + Func_Usart2_Tx = 36u, ///< function set to usart tx of ch.2 + Func_Usart4_Tx = 36u, ///< function set to usart tx of ch.4 + Func_Usart2_Rx = 37u, ///< function set to usart rx of ch.2 + Func_Usart4_Rx = 37u, ///< function set to usart rx of ch.4 + Func_Usart2_Rts = 38u, ///< function set to usart rts of ch.2 + Func_Usart4_Rts = 38u, ///< function set to usart rts of ch.4 + Func_Usart2_Cts = 39u, ///< function set to usart cts of ch.2 + Func_Usart4_Cts = 39u, ///< function set to usart cts of ch.4 + Func_Spi1_Mosi = 40u, ///< function set to spi mosi of ch.1 + Func_Spi3_Mosi = 40u, ///< function set to spi mosi of ch.3 + Func_Spi1_Miso = 41u, ///< function set to spi miso of ch.1 + Func_Spi3_Miso = 41u, ///< function set to spi miso of ch.3 + Func_Spi1_Nss0 = 42u, ///< function set to spi nss0 of ch.1 + Func_Spi3_Nss0 = 42u, ///< function set to spi nss0 of ch.3 + Func_Spi1_Sck = 43u, ///< function set to spi sck of ch.1 + Func_Spi3_Sck = 43u, ///< function set to spi sck of ch.3 + Func_Spi2_Mosi = 44u, ///< function set to spi mosi of ch.2 + Func_Spi4_Mosi = 44u, ///< function set to spi mosi of ch.2 + Func_Spi2_Miso = 45u, ///< function set to spi miso of ch.4 + Func_Spi4_Miso = 45u, ///< function set to spi miso of ch.4 + Func_Spi2_Nss0 = 46u, ///< function set to spi nss0 of ch.2 + Func_Spi4_Nss0 = 46u, ///< function set to spi nss0 of ch.4 + Func_Spi2_Sck = 47u, ///< function set to spi sck of ch.2 + Func_Spi4_Sck = 47u, ///< function set to spi sck of ch.4 + Func_I2c1_Sda = 48u, ///< function set to i2c sda of ch.1 + Func_I2c3_Sda = 48u, ///< function set to i2c sda of ch.3 + Func_I2c1_Scl = 49u, ///< function set to i2c scl of ch.1 + Func_I2c3_Scl = 49u, ///< function set to i2c scl of ch.3 + Func_I2c2_Sda = 50u, ///< function set to i2c sda of ch.2 + Func_Can1_Tx = 50u, ///< function set to can tx of ch.1 + Func_I2c2_Scl = 51u, ///< function set to i2c scl of ch.2 + Func_Can1_Rx = 51u, ///< function set to can rx of ch.1 + Func_I2s1_Sd = 52u, ///< function set to i2s sd of ch.1 + Func_I2s3_Sd = 52u, ///< function set to i2s sd of ch.3 + Func_I2s1_Sdin = 53u, ///< function set to i2s sdin of ch.1 + Func_I2s3_Sdin = 53u, ///< function set to i2s sdin of ch.3 + Func_I2s1_Ws = 54u, ///< function set to i2s ws of ch.1 + Func_I2s3_Ws = 54u, ///< function set to i2s ws of ch.3 + Func_I2s1_Ck = 55u, ///< function set to i2s ck of ch.1 + Func_I2s3_Ck = 55u, ///< function set to i2s ck of ch.3 + Func_I2s2_Sd = 56u, ///< function set to i2s sd of ch.2 + Func_I2s4_Sd = 56u, ///< function set to i2s sd of ch.4 + Func_I2s2_Sdin = 57u, ///< function set to i2s sdin of ch.2 + Func_I2s4_Sdin = 57u, ///< function set to i2s sdin of ch.4 + Func_I2s2_Ws = 58u, ///< function set to i2s ws of ch.2 + Func_I2s4_Ws = 58u, ///< function set to i2s ws of ch.4 + Func_I2s2_Ck = 59u, ///< function set to i2s ck of ch.2 + Func_I2s4_Ck = 59u, ///< function set to i2s ck of ch.4 +}en_port_func_t; + +/** + ******************************************************************************* + ** \brief GPIO init structure definition + ******************************************************************************/ +typedef struct stc_port_init +{ + en_pin_mode_t enPinMode; ///< Set pin mode @ref en_pin_mode_t + en_functional_state_t enLatch; ///< Pin output latch enable + en_functional_state_t enExInt; ///< External int enable + en_functional_state_t enInvert; ///< Pin input/output invert enable + en_functional_state_t enPullUp; ///< Internal pull-up resistor enable + en_pin_drv_t enPinDrv; ///< Drive capacity setting @ref en_pin_drv_t + en_pin_o_type_t enPinOType; ///< Output mode setting @ref en_pin_o_type_t + en_functional_state_t enPinSubFunc; ///< Pin sub-function enable +}stc_port_init_t; + +/** + ******************************************************************************* + ** \brief GPIO public setting structure definition + ******************************************************************************/ +typedef struct stc_port_pub_set +{ + en_port_func_t enSubFuncSel; ///< Sub-function setting @ref en_port_func_t + en_read_wait_t enReadWait; ///< Read wait cycle setting @ref en_read_wait_t +}stc_port_pub_set_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t PORT_Init(en_port_t enPort, uint16_t u16Pin, \ + const stc_port_init_t *pstcPortInit); +extern en_result_t PORT_DeInit(void); +extern void PORT_Unlock(void); +extern void PORT_Lock(void); +extern en_result_t PORT_DebugPortSetting(uint8_t u8DebugPort, en_functional_state_t enFunc); +extern en_result_t PORT_PubSetting(const stc_port_pub_set_t *pstcPortPubSet); +extern uint16_t PORT_GetData(en_port_t enPort); +extern en_flag_status_t PORT_GetBit(en_port_t enPort, en_pin_t enPin); +extern en_result_t PORT_SetPortData(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_ResetPortData(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_OE(en_port_t enPort, uint16_t u16Pin, en_functional_state_t enNewState); +extern en_result_t PORT_SetBits(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_ResetBits(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin, \ + en_port_func_t enFuncSel, en_functional_state_t enSubFunc); +extern en_result_t PORT_SetSubFunc(en_port_func_t enFuncSel); + +//@} // GpioGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_GPIO_ENABLE */ + +#endif /* __HC32F460_GPIO_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_hash.h b/driver/inc/hc32f460_hash.h new file mode 100644 index 0000000..8ee1ce4 --- /dev/null +++ b/driver/inc/hc32f460_hash.h @@ -0,0 +1,72 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_hash.h + ** + ** A detailed description is available at + ** @link HashGroup Hash description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of Hash. + ** + ******************************************************************************/ +#ifndef __HC32F460_HASH_H__ +#define __HC32F460_HASH_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_HASH_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup HashGroup Hash(HASH) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void HASH_Init(void); +void HASH_DeInit(void); +en_result_t HASH_Start(const uint8_t *pu8SrcData, + uint32_t u32SrcDataSize, + uint8_t *pu8MsgDigest, + uint32_t u32Timeout); + +//@} // HashGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_HASH_ENABLE */ + +#endif /* __HC32F460_HASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_i2c.h b/driver/inc/hc32f460_i2c.h new file mode 100644 index 0000000..dc8ea44 --- /dev/null +++ b/driver/inc/hc32f460_i2c.h @@ -0,0 +1,270 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2c.h + ** + ** A detailed description is available at + ** @link I2cGroup Inter-Integrated Circuit(I2C) description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of I2C. + ** + ******************************************************************************/ + +#ifndef __HC32F460_I2C_H__ +#define __HC32F460_I2C_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_I2C_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup I2cGroup Inter-Integrated Circuit (I2C) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief I2c configuration structure + ** + ******************************************************************************/ +typedef struct stc_i2c_init +{ + uint32_t u32ClockDiv; ///< I2C clock division for i2c source clock + uint32_t u32Baudrate; ///< I2C baudrate config + uint32_t u32SclTime; ///< The SCL rising and falling time, count of T(i2c source clock after frequency divider) +}stc_i2c_init_t; + +/** + ******************************************************************************* + ** \brief I2c SMBUS configuration structure + ** + ******************************************************************************/ +typedef struct stc_i2c_smbus_init +{ + en_functional_state_t enHostAdrMatchFunc; ///< SMBUS host address matching function + en_functional_state_t enDefaultAdrMatchFunc; ///< SMBUS default address matching function + en_functional_state_t enAlarmAdrMatchFunc; ///< SMBUS Alarm address matching function +}stc_i2c_smbus_init_t; + +/** + ******************************************************************************* + ** \brief I2c digital filter mode enumeration + ** + ******************************************************************************/ +typedef enum en_i2c_digital_filter_mode +{ + Filter1BaseCycle = 0u, ///< I2C digital filter ability 1 base cycle + Filter2BaseCycle = 1u, ///< I2C digital filter ability 2 base cycle + Filter3BaseCycle = 2u, ///< I2C digital filter ability 3 base cycle + Filter4BaseCycle = 3u, ///< I2C digital filter ability 4 base cycle +}en_i2c_digital_filter_mode_t; + +/** + ******************************************************************************* + ** \brief I2c address bit enumeration + ** + ******************************************************************************/ +typedef enum en_address_bit +{ + Adr7bit = 0u, ///< I2C address length is 7 bits + Adr10bit = 1u, ///< I2C address length is 10 bits +}en_address_bit_t; + +/** + ******************************************************************************* + ** \brief I2c transfer direction enumeration + ** + ******************************************************************************/ +typedef enum en_trans_direction +{ + I2CDirTrans = 0u, + I2CDirReceive = 1u, +}en_trans_direction_t; + +/** + ******************************************************************************* + ** \brief I2c clock timeout switch enumeration + ** + ******************************************************************************/ +typedef enum en_clock_timeout_switch +{ + TimeoutFunOff = 0u, ///< I2C SCL pin time out function off + LowTimerOutOn = 3u, ///< I2C SCL pin high level time out function on + HighTimeOutOn = 5u, ///< I2C SCL pin low level time out function on + BothTimeOutOn = 7u, ///< I2C SCL pin both(low and high) level time out function on +}en_clock_timeout_switch_t; + +/** + ******************************************************************************* + ** \brief I2c clock timeout initialize structure + ** + ******************************************************************************/ +typedef struct stc_clock_timeout_init +{ + en_clock_timeout_switch_t enClkTimeOutSwitch; ///< I2C clock timeout function switch + uint16_t u16TimeOutHigh; ///< I2C clock timeout period for High level + uint16_t u16TimeOutLow; ///< I2C clock timeout period for Low level +}stc_clock_timeout_init_t; + +/** + ******************************************************************************* + ** \brief I2c ACK config enumeration + ** + ******************************************************************************/ +typedef enum en_i2c_ack_config +{ + I2c_ACK = 0u, + I2c_NACK = 1u, +}en_i2c_ack_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* define interrupt enable bit for I2C_CR2 register */ +#define I2C_CR2_STARTIE (0x00000001ul) +#define I2C_CR2_SLADDR0EN (0x00000002ul) +#define I2C_CR2_SLADDR1EN (0x00000004ul) +#define I2C_CR2_TENDIE (0x00000008ul) +#define I2C_CR2_STOPIE (0x00000010ul) +#define I2C_CR2_RFULLIE (0x00000040ul) +#define I2C_CR2_TEMPTYIE (0x00000080ul) +#define I2C_CR2_ARLOIE (0x00000200ul) +#define I2C_CR2_NACKIE (0x00001000ul) +#define I2C_CR2_TMOURIE (0x00004000ul) +#define I2C_CR2_GENCALLIE (0x00100000ul) +#define I2C_CR2_SMBDEFAULTIE (0x00200000ul) +#define I2C_CR2_SMBHOSTIE (0x00400000ul) +#define I2C_CR2_SMBALRTIE (0x00800000ul) + +/* define status bit for I2C_SR register */ +#define I2C_SR_STARTF (0x00000001ul) +#define I2C_SR_SLADDR0F (0x00000002ul) +#define I2C_SR_SLADDR1F (0x00000004ul) +#define I2C_SR_TENDF (0x00000008ul) +#define I2C_SR_STOPF (0x00000010ul) +#define I2C_SR_RFULLF (0x00000040ul) +#define I2C_SR_TEMPTYF (0x00000080ul) +#define I2C_SR_ARLOF (0x00000200ul) +#define I2C_SR_ACKRF (0x00000400ul) +#define I2C_SR_NACKF (0x00001000ul) +#define I2C_SR_TMOUTF (0x00004000ul) +#define I2C_SR_MSL (0x00010000ul) +#define I2C_SR_BUSY (0x00020000ul) +#define I2C_SR_TRA (0x00040000ul) +#define I2C_SR_GENCALLF (0x00100000ul) +#define I2C_SR_SMBDEFAULTF (0x00200000ul) +#define I2C_SR_SMBHOSTF (0x00400000ul) +#define I2C_SR_SMBALRTF (0x00800000ul) + +/* define status clear bit for I2C_CLR register*/ +#define I2C_CLR_STARTFCLR (0x00000001ul) +#define I2C_CLR_SLADDR0FCLR (0x00000002ul) +#define I2C_CLR_SLADDR1FCLR (0x00000004ul) +#define I2C_CLR_TENDFCLR (0x00000008ul) +#define I2C_CLR_STOPFCLR (0x00000010ul) +#define I2C_CLR_RFULLFCLR (0x00000040ul) +#define I2C_CLR_TEMPTYFCLR (0x00000080ul) +#define I2C_CLR_ARLOFCLR (0x00000200ul) +#define I2C_CLR_NACKFCLR (0x00001000ul) +#define I2C_CLR_TMOUTFCLR (0x00004000ul) +#define I2C_CLR_GENCALLFCLR (0x00100000ul) +#define I2C_CLR_SMBDEFAULTFCLR (0x00200000ul) +#define I2C_CLR_SMBHOSTFCLR (0x00400000ul) +#define I2C_CLR_SMBALRTFCLR (0x00800000ul) +#define I2C_CLR_MASK (0x00F056DFul) + +/* I2C_Clock_Division I2C clock division */ +#define I2C_CLK_DIV1 (0ul) /* I2c source clock/1 */ +#define I2C_CLK_DIV2 (1ul) /* I2c source clock/2 */ +#define I2C_CLK_DIV4 (2ul) /* I2c source clock/4 */ +#define I2C_CLK_DIV8 (3ul) /* I2c source clock/8 */ +#define I2C_CLK_DIV16 (4ul) /* I2c source clock/16 */ +#define I2C_CLK_DIV32 (5ul) /* I2c source clock/32 */ +#define I2C_CLK_DIV64 (6ul) /* I2c source clock/64 */ +#define I2C_CLK_DIV128 (7ul) /* I2c source clock/128 */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error); +en_result_t I2C_DeInit(M4_I2C_TypeDef* pstcI2Cx); +en_result_t I2C_Init(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error); +void I2C_Cmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +en_result_t I2C_SmbusConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_smbus_init_t* pstcI2C_SmbusInitStruct); +void I2C_SmBusCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_SoftwareResetCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); + +//////////////////////////////////////////////////////////////////////////////////////// +void I2C_DigitalFilterConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_digital_filter_mode_t enDigiFilterMode); +void I2C_DigitalFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_AnalogFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GeneralCallCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_SlaveAdr0Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr); +void I2C_SlaveAdr1Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr); +en_result_t I2C_ClkTimeOutConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_clock_timeout_init_t* pstcTimoutInit); +void I2C_IntCmd(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32IntEn, en_functional_state_t enNewState); +void I2C_FastAckCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_BusWaitCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); + +/////////////////////////////////////////////////////////////////////////////////////// +void I2C_GenerateStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GenerateReStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GenerateStop(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_WriteData(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Data); +uint8_t I2C_ReadData(M4_I2C_TypeDef* pstcI2Cx); +void I2C_AckConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_ack_config_t u32AckConfig); +en_flag_status_t I2C_GetStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit); +void I2C_ClearStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit); + +/* High level functions for reference ********************************/ +en_result_t I2C_Start(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_Restart(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_TransAddr(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Addr, en_trans_direction_t enDir, uint32_t u32Timeout); +en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* pstcI2Cx, uint16_t u16Addr, en_trans_direction_t enDir, uint32_t u32Timeout); +en_result_t I2C_TransData(M4_I2C_TypeDef* pstcI2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout); +en_result_t I2C_ReceiveData(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +en_result_t I2C_Stop(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *pstcI2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout); +en_result_t I2C_MasterDataReceiveAndStop(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); + +//@} // I2cGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_I2C_ENABLE */ + +#endif /* __HC32F460_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_i2s.h b/driver/inc/hc32f460_i2s.h new file mode 100644 index 0000000..210cf66 --- /dev/null +++ b/driver/inc/hc32f460_i2s.h @@ -0,0 +1,206 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2s.h + ** + ** A detailed description is available at + ** @link I2sGroup Inter-IC Sound Bus description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of I2S. + ** + ******************************************************************************/ + +#ifndef __HC32F460_I2S_H__ +#define __HC32F460_I2S_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_I2S_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup I2sGroup Inter-IC Sound(I2S) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief I2S function + ******************************************************************************/ +typedef enum en_i2s_func +{ + TxEn = 0u, ///< Transfer enable function + TxIntEn = 1u, ///< Transfer interrupt enable function + RxEn = 2u, ///< receive enable function + RxIntEn = 3u, ///< receive interrupt enable function + ErrIntEn = 4u, ///< error interrupt enable function +}en_i2s_func_t; + + +/** + ******************************************************************************* + ** \brief I2S status flag + ******************************************************************************/ +typedef enum en_i2s_std +{ + TxBufAlarmFlag = 0u, + RxBufAlarmFlag = 1u, + TxBufEmptFlag = 2u, + TxBufFullFlag = 3u, + RxBufEmptFlag = 4u, + RxBufFullFlag = 5u, +}en_i2s_std_t; + +/** + ******************************************************************************* + ** \brief I2S clr flag + ******************************************************************************/ +typedef enum en_i2s_err_flag +{ + ClrTxErrFlag = 0u, + ClrRxErrFlag = 1u, +}en_i2s_err_flag_t; +/** + ******************************************************************************* + ** \brief I2S mode + ******************************************************************************/ +typedef enum en_i2s_mode +{ + I2sMaster = 0u, ///< I2S Master mode + I2sSlave = 1u, ///< I2S Slave mode +}en_i2s_mode_t; + +/** + ******************************************************************************* + ** \brief I2S full duplex mode + ******************************************************************************/ +typedef enum en_i2s_full_duplex_mode +{ + I2s_HalfDuplex = 0u, ///< I2S half duplex + I2s_FullDuplex = 1u, ///< I2S full duplex +}en_i2s_full_duplex_mode_t; + +/** + ******************************************************************************* + ** \brief I2S standard + ******************************************************************************/ +typedef enum en_i2s_standard +{ + Std_Philips = 0u, ///< I2S Philips standard + Std_MSBJust = 1u, ///< I2S MSB justified standart + Std_LSBJust = 2u, ///< I2S LSB justified standart + Std_PCM = 3u, ///< I2S PCM standart +}en_i2s_standard_t; + +/** + ******************************************************************************* + ** \brief I2S channel data length + ******************************************************************************/ +typedef enum en_i2s_ch_len +{ + I2s_ChLen_16Bit = 0u, + I2s_ChLen_32Bit = 1u, +}en_i2s_ch_len_t; + +/** + ******************************************************************************* + ** \brief I2S data length + ******************************************************************************/ +typedef enum en_i2s_data_len +{ + I2s_DataLen_16Bit = 0u, + I2s_DataLen_24Bit = 1u, + I2s_DataLen_32Bit = 2u, +}en_i2s_data_len_t; + +/** + ******************************************************************************* + ** \brief I2S configuration structure + ******************************************************************************/ +typedef struct stc_i2s_config +{ + en_i2s_mode_t enMode; ///< I2S mode + en_i2s_full_duplex_mode_t enFullDuplexMode; ///< I2S full duplex mode + uint32_t u32I2sInterClkFreq; ///< I2S internal clock frequency + en_i2s_standard_t enStandrad; ///< I2S standard + en_i2s_data_len_t enDataBits; ///< I2S data format, data bits + en_i2s_ch_len_t enChanelLen; ///< I2S channel length + en_functional_state_t enMcoOutEn; ///< I2S MCK output config + en_functional_state_t enExckEn; ///< I2S EXCK function config + uint32_t u32AudioFreq; ///< I2S audio frequecy +}stc_i2s_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* define audio frequency */ +#define I2S_AudioFreq_192k (192000ul) +#define I2S_AudioFreq_96k (96000ul) +#define I2S_AudioFreq_48k (48000ul) +#define I2S_AudioFreq_44k (44100ul) +#define I2S_AudioFreq_32k (32000ul) +#define I2S_AudioFreq_22k (22050ul) +#define I2S_AudioFreq_16k (16000ul) +#define I2S_AudioFreq_11k (11025ul) +#define I2S_AudioFreq_8k (8000ul) +#define I2S_AudioFreq_Default (2ul) + +/* if use external clock open this define */ +#define I2S_EXTERNAL_CLOCK_VAL (12288000ul) + +/* 0,1 or 2 config for tx or tx buffer interrupt warning level */ +#define RXBUF_IRQ_WL (1ul) +#define TXBUF_IRQ_WL (1ul) + +/* 0: Short frame synchronization; 1: Long frame synchronization */ +#define PCM_SYNC_FRAME (0ul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t I2s_Init(M4_I2S_TypeDef* pstcI2sReg, const stc_i2s_config_t* pstcI2sCfg); +void I2S_SendData(M4_I2S_TypeDef* pstcI2sReg, uint32_t u32Data); +uint32_t I2S_RevData(const M4_I2S_TypeDef* pstcI2sReg); +void I2S_FuncCmd(M4_I2S_TypeDef* pstcI2sReg, en_i2s_func_t enFunc, en_functional_state_t enNewState); +en_flag_status_t I2S_GetStatus(M4_I2S_TypeDef* pstcI2sReg, en_i2s_std_t enStd); +en_flag_status_t I2S_GetErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag); +void I2S_ClrErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag); +en_result_t I2s_DeInit(M4_I2S_TypeDef* pstcI2sReg); + +//@} // I2sGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_I2S_ENABLE */ + +#endif /* __HC32F460_I2S_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_icg.h b/driver/inc/hc32f460_icg.h new file mode 100644 index 0000000..7efaa9a --- /dev/null +++ b/driver/inc/hc32f460_icg.h @@ -0,0 +1,406 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_icg.h + ** + ** A detailed description is available at + ** @link IcgGroup Initialize configure description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of ICG. + ** + ******************************************************************************/ +#ifndef __HC32F460_ICG_H__ +#define __HC32F460_ICG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_ICG_ENABLE == DDL_ON) + +#define WATCH_DOG 1 + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup IcgGroup Initialize Configure(ICG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT running state after reset + ******************************************************************************/ +#define SWDT_AUTO_START_AFTER_RESET ((uint16_t)0x0000) ///< SWDT Auto Start after reset +#define SWDT_STOP_AFTER_RESET ((uint16_t)0x0001) ///< SWDT stop after reset + +/** + ******************************************************************************* + ** \brief SWDT count underflow or refresh error trigger event type + ******************************************************************************/ +#define SWDT_INTERRUPT_REQUEST ((uint16_t)0x0000) ///< WDT trigger interrupt request +#define SWDT_RESET_REQUEST ((uint16_t)0x0002) ///< WDT trigger reset request + +/** + ******************************************************************************* + ** \brief SWDT count underflow cycle + ******************************************************************************/ +#define SWDT_COUNT_UNDERFLOW_CYCLE_256 ((uint16_t)0x0000) ///< 256 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_4096 ((uint16_t)0x0004) ///< 4096 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_16384 ((uint16_t)0x0008) ///< 16384 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_65536 ((uint16_t)0x000C) ///< 65536 clock cycle + +/** + ******************************************************************************* + ** \brief SWDT count clock division + ******************************************************************************/ +#define SWDT_COUNT_SWDTCLK_DIV1 ((uint16_t)0x0000) ///< SWDTCLK +#define SWDT_COUNT_SWDTCLK_DIV16 ((uint16_t)0x0040) ///< SWDTCLK/16 +#define SWDT_COUNT_SWDTCLK_DIV32 ((uint16_t)0x0050) ///< SWDTCLK/32 +#define SWDT_COUNT_SWDTCLK_DIV64 ((uint16_t)0x0060) ///< SWDTCLK/64 +#define SWDT_COUNT_SWDTCLK_DIV128 ((uint16_t)0x0070) ///< SWDTCLK/128 +#define SWDT_COUNT_SWDTCLK_DIV256 ((uint16_t)0x0080) ///< SWDTCLK/256 +#define SWDT_COUNT_SWDTCLK_DIV2048 ((uint16_t)0x00B0) ///< SWDTCLK/2048 + +/** + ******************************************************************************* + ** \brief SWDT allow refresh percent range + ******************************************************************************/ +#define SWDT_100PCT ((uint16_t)0x0000) ///< 100% +#define SWDT_0To25PCT ((uint16_t)0x0100) ///< 0%~25% +#define SWDT_25To50PCT ((uint16_t)0x0200) ///< 25%~50% +#define SWDT_0To50PCT ((uint16_t)0x0300) ///< 0%~50% +#define SWDT_50To75PCT ((uint16_t)0x0400) ///< 50%~75% +#define SWDT_0To25PCT_50To75PCT ((uint16_t)0x0500) ///< 0%~25% & 50%~75% +#define SWDT_25To75PCT ((uint16_t)0x0600) ///< 25%~75% +#define SWDT_0To75PCT ((uint16_t)0x0700) ///< 0%~75% +#define SWDT_75To100PCT ((uint16_t)0x0800) ///< 75%~100% +#define SWDT_0To25PCT_75To100PCT ((uint16_t)0x0900) ///< 0%~25% & 75%~100% +#define SWDT_25To50PCT_75To100PCT ((uint16_t)0x0A00) ///< 25%~50% & 75%~100% +#define SWDT_0To50PCT_75To100PCT ((uint16_t)0x0B00) ///< 0%~50% & 75%~100% +#define SWDT_50To100PCT ((uint16_t)0x0C00) ///< 50%~100% +#define SWDT_0To25PCT_50To100PCT ((uint16_t)0x0D00) ///< 0%~25% & 50%~100% +#define SWDT_25To100PCT ((uint16_t)0x0E00) ///< 25%~100% +#define SWDT_0To100PCT ((uint16_t)0x0F00) ///< 0%~100% + +/** + ******************************************************************************* + ** \brief SWDT count control in the sleep/stop mode + ******************************************************************************/ +#define SWDT_SPECIAL_MODE_COUNT_CONTINUE ((uint16_t)0x0000) ///< SWDT count continue in the sleep/stop mode +#define SWDT_SPECIAL_MODE_COUNT_STOP ((uint16_t)0x1000) ///< SWDT count stop in the sleep/stop mode + +/** + ******************************************************************************* + ** \brief WDT running state after reset + ******************************************************************************/ +#define WDT_AUTO_START_AFTER_RESET ((uint16_t)0x0000) ///< WDT Auto Start after reset +#define WDT_STOP_AFTER_RESET ((uint16_t)0x0001) ///< WDT stop after reset + +/** + ******************************************************************************* + ** \brief WDT count underflow or refresh error trigger event type + ******************************************************************************/ +#define WDT_INTERRUPT_REQUEST ((uint16_t)0x0000) ///< WDT trigger interrupt request +#define WDT_RESET_REQUEST ((uint16_t)0x0002) ///< WDT trigger reset request + +/** + ******************************************************************************* + ** \brief WDT count underflow cycle + ******************************************************************************/ +#define WDT_COUNT_UNDERFLOW_CYCLE_256 ((uint16_t)0x0000) ///< 256 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_4096 ((uint16_t)0x0004) ///< 4096 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_16384 ((uint16_t)0x0008) ///< 16384 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_65536 ((uint16_t)0x000C) ///< 65536 clock cycle + +/** + ******************************************************************************* + ** \brief WDT count clock division + ******************************************************************************/ +#define WDT_COUNT_PCLK3_DIV4 ((uint16_t)0x0020) ///< PCLK3/4 +#define WDT_COUNT_PCLK3_DIV64 ((uint16_t)0x0060) ///< PCLK3/64 +#define WDT_COUNT_PCLK3_DIV128 ((uint16_t)0x0070) ///< PCLK3/128 +#define WDT_COUNT_PCLK3_DIV256 ((uint16_t)0x0080) ///< PCLK3/256 +#define WDT_COUNT_PCLK3_DIV512 ((uint16_t)0x0090) ///< PCLK3/512 +#define WDT_COUNT_PCLK3_DIV1024 ((uint16_t)0x00A0) ///< PCLK3/1024 +#define WDT_COUNT_PCLK3_DIV2048 ((uint16_t)0x00B0) ///< PCLK3/2048 +#define WDT_COUNT_PCLK3_DIV8192 ((uint16_t)0x00D0) ///< PCLK3/8192 + +/** + ******************************************************************************* + ** \brief WDT allow refresh percent range + ******************************************************************************/ +#define WDT_100PCT ((uint16_t)0x0000) ///< 100% +#define WDT_0To25PCT ((uint16_t)0x0100) ///< 0%~25% +#define WDT_25To50PCT ((uint16_t)0x0200) ///< 25%~50% +#define WDT_0To50PCT ((uint16_t)0x0300) ///< 0%~50% +#define WDT_50To75PCT ((uint16_t)0x0400) ///< 50%~75% +#define WDT_0To25PCT_50To75PCT ((uint16_t)0x0500) ///< 0%~25% & 50%~75% +#define WDT_25To75PCT ((uint16_t)0x0600) ///< 25%~75% +#define WDT_0To75PCT ((uint16_t)0x0700) ///< 0%~75% +#define WDT_75To100PCT ((uint16_t)0x0800) ///< 75%~100% +#define WDT_0To25PCT_75To100PCT ((uint16_t)0x0900) ///< 0%~25% & 75%~100% +#define WDT_25To50PCT_75To100PCT ((uint16_t)0x0A00) ///< 25%~50% & 75%~100% +#define WDT_0To50PCT_75To100PCT ((uint16_t)0x0B00) ///< 0%~50% & 75%~100% +#define WDT_50To100PCT ((uint16_t)0x0C00) ///< 50%~100% +#define WDT_0To25PCT_50To100PCT ((uint16_t)0x0D00) ///< 0%~25% & 50%~100% +#define WDT_25To100PCT ((uint16_t)0x0E00) ///< 25%~100% +#define WDT_0To100PCT ((uint16_t)0x0F00) ///< 0%~100% + +/** + ******************************************************************************* + ** \brief WDT count control in the sleep mode + ******************************************************************************/ +#define WDT_SPECIAL_MODE_COUNT_CONTINUE ((uint16_t)0x0000) ///< WDT count continue in the sleep mode +#define WDT_SPECIAL_MODE_COUNT_STOP ((uint16_t)0x1000) ///< WDT count stop in the sleep mode + +/** + ******************************************************************************* + ** \brief HRC frequency select + ******************************************************************************/ +#define HRC_FREQUENCY_20MHZ ((uint16_t)0x0000) ///< HRC frequency 20MHZ +#define HRC_FREQUENCY_16MHZ ((uint16_t)0x0001) ///< HRC frequency 16MHZ + +/** + ******************************************************************************* + ** \brief HRC oscillation state control + ******************************************************************************/ +#define HRC_OSCILLATION_START ((uint16_t)0x0000) ///< HRC oscillation start +#define HRC_OSCILLATION_STOP ((uint16_t)0x0100) ///< HRC oscillation stop + +/** + ******************************************************************************* + ** \brief VDU0 threshold voltage select + ******************************************************************************/ +#define VDU0_VOLTAGE_THRESHOLD_1P5 ((uint8_t)0x00) ///< VDU0 voltage threshold 1.9V +#define VDU0_VOLTAGE_THRESHOLD_2P0 ((uint8_t)0x01) ///< VDU0 voltage threshold 2.0V +#define VDU0_VOLTAGE_THRESHOLD_2P1 ((uint8_t)0x02) ///< VDU0 voltage threshold 2.1V +#define VDU0_VOLTAGE_THRESHOLD_2P3 ((uint8_t)0x03) ///< VDU0 voltage threshold 2.3V + +/** + ******************************************************************************* + ** \brief VDU0 running state after reset + ******************************************************************************/ +#define VDU0_START_AFTER_RESET ((uint8_t)0x00) ///< VDU0 start after reset +#define VDU0_STOP_AFTER_RESET ((uint8_t)0x04) ///< VDU0 stop after reset + +/** + ******************************************************************************* + ** \brief NMI pin filter sample clock division + ******************************************************************************/ +#define NMI_PIN_FILTER_PCLK3_DIV1 ((uint8_t)0x00) ///< PCLK3 +#define NMI_PIN_FILTER_PCLK3_DIV8 ((uint8_t)0x04) ///< PCLK3/8 +#define NMI_PIN_FILTER_PCLK3_DIV32 ((uint8_t)0x08) ///< PCLK3/32 +#define NMI_PIN_FILTER_PCLK3_DIV64 ((uint8_t)0x0C) ///< PCLK3/64 + +/** + ******************************************************************************* + ** \brief NMI pin trigger edge type + ******************************************************************************/ +#define NMI_PIN_TRIGGER_EDGE_FALLING ((uint8_t)0x00) ///< Falling edge trigger +#define NMI_PIN_TRIGGER_EDGE_RISING ((uint8_t)0x10) ///< Rising edge trigger + +/** + ******************************************************************************* + ** \brief Enable or disable NMI pin interrupt request + ******************************************************************************/ +#define NMI_PIN_IRQ_DISABLE ((uint8_t)0x00) ///< Disable NMI pin interrupt request +#define NMI_PIN_IRQ_ENABLE ((uint8_t)0x20) ///< Enable NMI pin interrupt request + +/** + ******************************************************************************* + ** \brief Enable or disable NMI digital filter function + ******************************************************************************/ +#define NMI_DIGITAL_FILTER_DISABLE ((uint8_t)0x00) ///< Disable NMI digital filter +#define NMI_DIGITAL_FILTER_ENABLE ((uint8_t)0x40) ///< Enable NMI digital filter + +/** + ******************************************************************************* + ** \brief Enable or disable NMI pin ICG function + ******************************************************************************/ +#define NMI_PIN_ICG_FUNCTION_DISABLE ((uint8_t)0x80) ///< Disable NMI pin ICG function +#define NMI_PIN_ICG_FUNCTION_ENABLE ((uint8_t)0x00) ///< Enable NMI pin ICG function + +/** + ******************************************************************************* + ** \brief ICG start configure function on/off + ******************************************************************************/ +#ifndef ICG_FUNCTION_ON +#define ICG_FUNCTION_ON (1u) +#endif + +#ifndef ICG_FUNCTION_OFF +#define ICG_FUNCTION_OFF (0u) +#endif + +/** + ******************************************************************************* + ** \brief SWDT hardware start configuration + ******************************************************************************/ +/*!< Enable or disable SWDT hardware start */ +#if (WATCH_DOG == 1) +#define ICG0_SWDT_HARDWARE_START (ICG_FUNCTION_ON) +#else +#define ICG0_SWDT_HARDWARE_START (ICG_FUNCTION_OFF) +#endif + +/*!< SWDT register config */ +#define ICG0_SWDT_AUTS (SWDT_AUTO_START_AFTER_RESET) +#define ICG0_SWDT_ITS (SWDT_RESET_REQUEST) +#define ICG0_SWDT_PERI (SWDT_COUNT_UNDERFLOW_CYCLE_256) // λʱ 0.8 +#define ICG0_SWDT_CKS (SWDT_COUNT_SWDTCLK_DIV128) +#define ICG0_SWDT_WDPT (SWDT_0To100PCT) +#define ICG0_SWDT_SLTPOFF (SWDT_SPECIAL_MODE_COUNT_CONTINUE) + +/*!< SWDT register config value */ +#if ICG0_SWDT_HARDWARE_START == ICG_FUNCTION_ON +#define ICG0_SWDT_REG_CONFIG (ICG0_SWDT_AUTS | ICG0_SWDT_ITS | ICG0_SWDT_PERI | \ + ICG0_SWDT_CKS | ICG0_SWDT_WDPT | ICG0_SWDT_SLTPOFF) +#else +#define ICG0_SWDT_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief WDT hardware start configuration + ******************************************************************************/ +/*!< Enable or disable WDT hardware start */ +#define ICG0_WDT_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< WDT register config */ +#define ICG0_WDT_AUTS (WDT_STOP_AFTER_RESET) +#define ICG0_WDT_ITS (WDT_RESET_REQUEST) +#define ICG0_WDT_PERI (WDT_COUNT_UNDERFLOW_CYCLE_16384) +#define ICG0_WDT_CKS (WDT_COUNT_PCLK3_DIV8192) +#define ICG0_WDT_WDPT (WDT_0To100PCT) +#define ICG0_WDT_SLPOFF (WDT_SPECIAL_MODE_COUNT_STOP) + +/*!< WDT register config value */ +#if ICG0_WDT_HARDWARE_START == ICG_FUNCTION_ON +#define ICG0_WDT_REG_CONFIG (ICG0_WDT_AUTS | ICG0_WDT_ITS | ICG0_WDT_PERI | \ + ICG0_WDT_CKS | ICG0_WDT_WDPT | ICG0_WDT_SLPOFF) +#else +#define ICG0_WDT_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief HRC hardware start configuration + ******************************************************************************/ +/*!< Enable or disable HRC hardware start */ +#define ICG1_HRC_HARDWARE_START (ICG_FUNCTION_ON) + +/*!< HRC register config */ +#define ICG1_HRC_FREQSEL (HRC_FREQUENCY_16MHZ) +#define ICG1_HRC_STOP (HRC_OSCILLATION_START) + +/*!< HRC register config value */ +#if ICG1_HRC_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_HRC_REG_CONFIG (ICG1_HRC_FREQSEL | ICG1_HRC_STOP) +#else +#define ICG1_HRC_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief VDU0 hardware start configuration + ******************************************************************************/ +/*!< Enable or disable VDU0 hardware start */ +#define ICG1_VDU0_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< VDU0 register config */ +#define ICG1_VDU0_BOR_LEV (VDU0_VOLTAGE_THRESHOLD_2P3) +#define ICG1_VDU0_BORDIS (VDU0_STOP_AFTER_RESET) + +/*!< VDU0 register config value */ +#if ICG1_VDU0_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_VDU0_REG_CONFIG (ICG1_VDU0_BOR_LEV | ICG1_VDU0_BORDIS) +#else +#define ICG1_VDU0_REG_CONFIG ((uint8_t)0xFF) +#endif + +/** + ******************************************************************************* + ** \brief NMI hardware start configuration + ******************************************************************************/ +/*!< Enable or disable NMI hardware start */ +#define ICG1_NMI_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< NMI register config */ +#define ICG1_NMI_SMPCLK (NMI_PIN_FILTER_PCLK3_DIV1) +#define ICG1_NMI_TRG (NMI_PIN_TRIGGER_EDGE_RISING) +#define ICG1_NMI_IMR (NMI_PIN_IRQ_DISABLE) +#define ICG1_NMI_NFEN (NMI_DIGITAL_FILTER_DISABLE) +#define ICG1_NMI_ICGENA (NMI_PIN_ICG_FUNCTION_DISABLE) + +/*!< NMI register config value */ +#if ICG1_NMI_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_NMI_REG_CONFIG (ICG1_NMI_SMPCLK | ICG1_NMI_TRG | \ + ICG1_NMI_IMR | ICG1_NMI_NFEN | ICG1_NMI_ICGENA) +#else +#define ICG1_NMI_REG_CONFIG ((uint8_t)0xFF) +#endif + +/** + ******************************************************************************* + ** \brief ICG registers configuration + ******************************************************************************/ +/*!< ICG0 register value */ +#define ICG0_REGISTER_CONSTANT (((uint32_t)ICG0_WDT_REG_CONFIG << 16) | \ + ((uint32_t)ICG0_SWDT_REG_CONFIG) | \ + ((uint32_t)0xE000E000ul)) +/*!< ICG1 register value */ +#define ICG1_REGISTER_CONSTANT (((uint32_t)ICG1_NMI_REG_CONFIG << 24) | \ + ((uint32_t)ICG1_VDU0_REG_CONFIG << 16) | \ + ((uint32_t)ICG1_HRC_REG_CONFIG) | \ + ((uint32_t)0x03F8FEFEul)) +/*!< ICG2~7 register reserved value */ +#define ICG2_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG3_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG4_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG5_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG6_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG7_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // IcgGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_ICG_ENABLE */ + +#endif /* __HC32F460_ICG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_interrupts.h b/driver/inc/hc32f460_interrupts.h new file mode 100644 index 0000000..d63da9e --- /dev/null +++ b/driver/inc/hc32f460_interrupts.h @@ -0,0 +1,542 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_interrupts.h + ** + ** A detailed description is available at + ** @link InterruptGroup Interrupt description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of interrupt. + ** + ******************************************************************************/ +#ifndef __HC32F460_INTERRUPTS_H___ +#define __HC32F460_INTERRUPTS_H___ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup InterruptGroup Interrupt + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief IRQ registration structure definition + ******************************************************************************/ +typedef struct stc_irq_regi_conf +{ + en_int_src_t enIntSrc; + IRQn_Type enIRQn; + func_ptr_t pfnCallback; +}stc_irq_regi_conf_t; + +/** + ******************************************************************************* + ** \brief stop mode interrupt wakeup source enumeration + ******************************************************************************/ +typedef enum en_int_wkup_src +{ + Extint0WU = 1u << 0, + Extint1WU = 1u << 1, + Extint2WU = 1u << 2, + Extint3WU = 1u << 3, + Extint4WU = 1u << 4, + Extint5WU = 1u << 5, + Extint6WU = 1u << 6, + Extint7WU = 1u << 7, + Extint8WU = 1u << 8, + Extint9WU = 1u << 9, + Extint10WU = 1u << 10, + Extint11WU = 1u << 11, + Extint12WU = 1u << 12, + Extint13WU = 1u << 13, + Extint14WU = 1u << 14, + Extint15WU = 1u << 15, + SwdtWU = 1u << 16, + Vdu1WU = 1u << 17, + Vdu2WU = 1u << 18, + CmpWU = 1u << 19, + WakeupTimerWU = 1u << 20, + RtcAlarmWU = 1u << 21, + RtcPeriodWU = 1u << 22, + Timer0WU = 1u << 23, + Usart1RxWU = 1u << 25, +}en_int_wkup_src_t; + +/** + ******************************************************************************* + ** \brief event enumeration + ******************************************************************************/ +typedef enum en_evt +{ + Event0 = 1u << 0, + Event1 = 1u << 1, + Event2 = 1u << 2, + Event3 = 1u << 3, + Event4 = 1u << 4, + Event5 = 1u << 5, + Event6 = 1u << 6, + Event7 = 1u << 7, + Event8 = 1u << 8, + Event9 = 1u << 9, + Event10 = 1u << 10, + Event11 = 1u << 11, + Event12 = 1u << 12, + Event13 = 1u << 13, + Event14 = 1u << 14, + Event15 = 1u << 15, + Event16 = 1u << 16, + Event17 = 1u << 17, + Event18 = 1u << 18, + Event19 = 1u << 19, + Event20 = 1u << 20, + Event21 = 1u << 21, + Event22 = 1u << 22, + Event23 = 1u << 23, + Event24 = 1u << 24, + Event25 = 1u << 25, + Event26 = 1u << 26, + Event27 = 1u << 27, + Event28 = 1u << 28, + Event29 = 1u << 29, + Event30 = 1u << 30, + Event31 = 1u << 31, +}en_evt_t; + +/** + ******************************************************************************* + ** \brief interrupt enumeration + ******************************************************************************/ +typedef enum en_int +{ + Int0 = 1u << 0, + Int1 = 1u << 1, + Int2 = 1u << 2, + Int3 = 1u << 3, + Int4 = 1u << 4, + Int5 = 1u << 5, + Int6 = 1u << 6, + Int7 = 1u << 7, + Int8 = 1u << 8, + Int9 = 1u << 9, + Int10 = 1u << 10, + Int11 = 1u << 11, + Int12 = 1u << 12, + Int13 = 1u << 13, + Int14 = 1u << 14, + Int15 = 1u << 15, + Int16 = 1u << 16, + Int17 = 1u << 17, + Int18 = 1u << 18, + Int19 = 1u << 19, + Int20 = 1u << 20, + Int21 = 1u << 21, + Int22 = 1u << 22, + Int23 = 1u << 23, + Int24 = 1u << 24, + Int25 = 1u << 25, + Int26 = 1u << 26, + Int27 = 1u << 27, + Int28 = 1u << 28, + Int29 = 1u << 29, + Int30 = 1u << 30, + Int31 = 1u << 31, +}en_int_t; + + +/*! Bit mask definition*/ +#define BIT_MASK_00 (1ul << 0) +#define BIT_MASK_01 (1ul << 1) +#define BIT_MASK_02 (1ul << 2) +#define BIT_MASK_03 (1ul << 3) +#define BIT_MASK_04 (1ul << 4) +#define BIT_MASK_05 (1ul << 5) +#define BIT_MASK_06 (1ul << 6) +#define BIT_MASK_07 (1ul << 7) +#define BIT_MASK_08 (1ul << 8) +#define BIT_MASK_09 (1ul << 9) +#define BIT_MASK_10 (1ul << 10) +#define BIT_MASK_11 (1ul << 11) +#define BIT_MASK_12 (1ul << 12) +#define BIT_MASK_13 (1ul << 13) +#define BIT_MASK_14 (1ul << 14) +#define BIT_MASK_15 (1ul << 15) +#define BIT_MASK_16 (1ul << 16) +#define BIT_MASK_17 (1ul << 17) +#define BIT_MASK_18 (1ul << 18) +#define BIT_MASK_19 (1ul << 19) +#define BIT_MASK_20 (1ul << 20) +#define BIT_MASK_21 (1ul << 21) +#define BIT_MASK_22 (1ul << 22) +#define BIT_MASK_23 (1ul << 23) +#define BIT_MASK_24 (1ul << 24) +#define BIT_MASK_25 (1ul << 25) +#define BIT_MASK_26 (1ul << 26) +#define BIT_MASK_27 (1ul << 27) +#define BIT_MASK_28 (1ul << 28) +#define BIT_MASK_29 (1ul << 29) +#define BIT_MASK_30 (1ul << 30) +#define BIT_MASK_31 (1ul << 31) + +/*! Default Priority for IRQ, Possible values are 0 (high priority) to 15 (low priority) */ +#define DDL_IRQ_PRIORITY_DEFAULT 15u + +/*! Interrupt priority level 00 ~ 15*/ +#define DDL_IRQ_PRIORITY_00 (0u) +#define DDL_IRQ_PRIORITY_01 (1u) +#define DDL_IRQ_PRIORITY_02 (2u) +#define DDL_IRQ_PRIORITY_03 (3u) +#define DDL_IRQ_PRIORITY_04 (4u) +#define DDL_IRQ_PRIORITY_05 (5u) +#define DDL_IRQ_PRIORITY_06 (6u) +#define DDL_IRQ_PRIORITY_07 (7u) +#define DDL_IRQ_PRIORITY_08 (8u) +#define DDL_IRQ_PRIORITY_09 (9u) +#define DDL_IRQ_PRIORITY_10 (10u) +#define DDL_IRQ_PRIORITY_11 (11u) +#define DDL_IRQ_PRIORITY_12 (12u) +#define DDL_IRQ_PRIORITY_13 (13u) +#define DDL_IRQ_PRIORITY_14 (14u) +#define DDL_IRQ_PRIORITY_15 (15u) + +/** + ******************************************************************************* + ** \brief AOS software trigger function + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_SW_Trigger(void) +{ + bM4_AOS_INT_SFTTRG_STRG = 1u; +} + +/** + ******************************************************************************* + ** \brief AOS common trigger source 1 config. + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_COM_Trigger1(en_event_src_t enTrig) +{ + M4_AOS->COMTRG1 = enTrig; +} + +/** + ******************************************************************************* + ** \brief AOS common trigger source 2 config. + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_COM_Trigger2(en_event_src_t enTrig) +{ + M4_AOS->COMTRG2 = enTrig; +} + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern en_result_t enIrqRegistration(const stc_irq_regi_conf_t *pstcIrqRegiConf); +extern en_result_t enIrqResign(IRQn_Type enIRQn); +extern en_result_t enShareIrqEnable(en_int_src_t enIntSrc); +extern en_result_t enShareIrqDisable(en_int_src_t enIntSrc); +extern en_result_t enIntWakeupEnable(uint32_t u32WakeupSrc); +extern en_result_t enIntWakeupDisable(uint32_t u32WakeupSrc); +extern en_result_t enEventEnable(uint32_t u32Event); +extern en_result_t enEventDisable(uint32_t u32Event); +extern en_result_t enIntEnable(uint32_t u32Int); +extern en_result_t enIntDisable(uint32_t u32Int); + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +__WEAKDEF void NMI_IrqHandler(void); +__WEAKDEF void HardFault_IrqHandler(void); +__WEAKDEF void MemManage_IrqHandler(void); +__WEAKDEF void BusFault_IrqHandler(void); +__WEAKDEF void UsageFault_IrqHandler(void); +__WEAKDEF void SVC_IrqHandler(void); +__WEAKDEF void DebugMon_IrqHandler(void); +__WEAKDEF void PendSV_IrqHandler(void); +__WEAKDEF void SysTick_IrqHandler(void); + +__WEAKDEF void Extint00_IrqHandler(void); +__WEAKDEF void Extint01_IrqHandler(void); +__WEAKDEF void Extint02_IrqHandler(void); +__WEAKDEF void Extint03_IrqHandler(void); +__WEAKDEF void Extint04_IrqHandler(void); +__WEAKDEF void Extint05_IrqHandler(void); +__WEAKDEF void Extint06_IrqHandler(void); +__WEAKDEF void Extint07_IrqHandler(void); +__WEAKDEF void Extint08_IrqHandler(void); +__WEAKDEF void Extint09_IrqHandler(void); +__WEAKDEF void Extint10_IrqHandler(void); +__WEAKDEF void Extint11_IrqHandler(void); +__WEAKDEF void Extint12_IrqHandler(void); +__WEAKDEF void Extint13_IrqHandler(void); +__WEAKDEF void Extint14_IrqHandler(void); +__WEAKDEF void Extint15_IrqHandler(void); + +__WEAKDEF void Dma1Tc0_IrqHandler(void); +__WEAKDEF void Dma1Tc1_IrqHandler(void); +__WEAKDEF void Dma1Tc2_IrqHandler(void); +__WEAKDEF void Dma1Tc3_IrqHandler(void); +__WEAKDEF void Dma2Tc0_IrqHandler(void); +__WEAKDEF void Dma2Tc1_IrqHandler(void); +__WEAKDEF void Dma2Tc2_IrqHandler(void); +__WEAKDEF void Dma2Tc3_IrqHandler(void); +__WEAKDEF void Dma1Btc0_IrqHandler(void); +__WEAKDEF void Dma1Btc1_IrqHandler(void); +__WEAKDEF void Dma1Btc2_IrqHandler(void); +__WEAKDEF void Dma1Btc3_IrqHandler(void); +__WEAKDEF void Dma2Btc0_IrqHandler(void); +__WEAKDEF void Dma2Btc1_IrqHandler(void); +__WEAKDEF void Dma2Btc2_IrqHandler(void); +__WEAKDEF void Dma2Btc3_IrqHandler(void); +__WEAKDEF void Dma1Err0_IrqHandler(void); +__WEAKDEF void Dma1Err1_IrqHandler(void); +__WEAKDEF void Dma1Err2_IrqHandler(void); +__WEAKDEF void Dma1Err3_IrqHandler(void); +__WEAKDEF void Dma2Err0_IrqHandler(void); +__WEAKDEF void Dma2Err1_IrqHandler(void); +__WEAKDEF void Dma2Err2_IrqHandler(void); +__WEAKDEF void Dma2Err3_IrqHandler(void); + +__WEAKDEF void EfmPgmEraseErr_IrqHandler(void); +__WEAKDEF void EfmColErr_IrqHandler(void); +__WEAKDEF void EfmOpEnd_IrqHandler(void); +__WEAKDEF void QspiInt_IrqHandler(void); +__WEAKDEF void Dcu1_IrqHandler(void); +__WEAKDEF void Dcu2_IrqHandler(void); +__WEAKDEF void Dcu3_IrqHandler(void); +__WEAKDEF void Dcu4_IrqHandler(void); + +__WEAKDEF void Timer01GCMA_IrqHandler(void); +__WEAKDEF void Timer01GCMB_IrqHandler(void); +__WEAKDEF void Timer02GCMA_IrqHandler(void); +__WEAKDEF void Timer02GCMB_IrqHandler(void); + +__WEAKDEF void MainOscStop_IrqHandler(void); +__WEAKDEF void WakeupTimer_IrqHandler(void); +__WEAKDEF void Swdt_IrqHandler(void); + +__WEAKDEF void Timer61GCMA_IrqHandler(void); +__WEAKDEF void Timer61GCMB_IrqHandler(void); +__WEAKDEF void Timer61GCMC_IrqHandler(void); +__WEAKDEF void Timer61GCMD_IrqHandler(void); +__WEAKDEF void Timer61GCME_IrqHandler(void); +__WEAKDEF void Timer61GCMF_IrqHandler(void); +__WEAKDEF void Timer61GOV_IrqHandler(void); +__WEAKDEF void Timer61GUD_IrqHandler(void); +__WEAKDEF void Timer61GDT_IrqHandler(void); +__WEAKDEF void Timer61SCMA_IrqHandler(void); +__WEAKDEF void Timer61SCMB_IrqHandler(void); + +__WEAKDEF void Timer62GCMA_IrqHandler(void); +__WEAKDEF void Timer62GCMB_IrqHandler(void); +__WEAKDEF void Timer62GCMC_IrqHandler(void); +__WEAKDEF void Timer62GCMD_IrqHandler(void); +__WEAKDEF void Timer62GCME_IrqHandler(void); +__WEAKDEF void Timer62GCMF_IrqHandler(void); +__WEAKDEF void Timer62GOV_IrqHandler(void); +__WEAKDEF void Timer62GUD_IrqHandler(void); +__WEAKDEF void Timer62GDT_IrqHandler(void); +__WEAKDEF void Timer62SCMA_IrqHandler(void); +__WEAKDEF void Timer62SCMB_IrqHandler(void); + +__WEAKDEF void Timer63GCMA_IrqHandler(void); +__WEAKDEF void Timer63GCMB_IrqHandler(void); +__WEAKDEF void Timer63GCMC_IrqHandler(void); +__WEAKDEF void Timer63GCMD_IrqHandler(void); +__WEAKDEF void Timer63GCME_IrqHandler(void); +__WEAKDEF void Timer63GCMF_IrqHandler(void); +__WEAKDEF void Timer63GOV_IrqHandler(void); +__WEAKDEF void Timer63GUD_IrqHandler(void); +__WEAKDEF void Timer63GDT_IrqHandler(void); +__WEAKDEF void Timer63SCMA_IrqHandler(void); +__WEAKDEF void Timer63SCMB_IrqHandler(void); + +__WEAKDEF void TimerA1OV_IrqHandler(void); +__WEAKDEF void TimerA1UD_IrqHandler(void); +__WEAKDEF void TimerA1CMP_IrqHandler(void); +__WEAKDEF void TimerA2OV_IrqHandler(void); +__WEAKDEF void TimerA2UD_IrqHandler(void); +__WEAKDEF void TimerA2CMP_IrqHandler(void); +__WEAKDEF void TimerA3OV_IrqHandler(void); +__WEAKDEF void TimerA3UD_IrqHandler(void); +__WEAKDEF void TimerA3CMP_IrqHandler(void); +__WEAKDEF void TimerA4OV_IrqHandler(void); +__WEAKDEF void TimerA4UD_IrqHandler(void); +__WEAKDEF void TimerA4CMP_IrqHandler(void); +__WEAKDEF void TimerA5OV_IrqHandler(void); +__WEAKDEF void TimerA5UD_IrqHandler(void); +__WEAKDEF void TimerA5CMP_IrqHandler(void); +__WEAKDEF void TimerA6OV_IrqHandler(void); +__WEAKDEF void TimerA6UD_IrqHandler(void); +__WEAKDEF void TimerA6CMP_IrqHandler(void); + +__WEAKDEF void UsbGlobal_IrqHandler(void); + +__WEAKDEF void Usart1RxErr_IrqHandler(void); +__WEAKDEF void Usart1RxEnd_IrqHandler(void); +__WEAKDEF void Usart1TxEmpty_IrqHandler(void); +__WEAKDEF void Usart1TxEnd_IrqHandler(void); +__WEAKDEF void Usart1RxTO_IrqHandler(void); +__WEAKDEF void Usart2RxErr_IrqHandler(void); +__WEAKDEF void Usart2RxEnd_IrqHandler(void); +__WEAKDEF void Usart2TxEmpty_IrqHandler(void); +__WEAKDEF void Usart2TxEnd_IrqHandler(void); +__WEAKDEF void Usart2RxTO_IrqHandler(void); +__WEAKDEF void Usart3RxErr_IrqHandler(void); +__WEAKDEF void Usart3RxEnd_IrqHandler(void); +__WEAKDEF void Usart3TxEmpty_IrqHandler(void); +__WEAKDEF void Usart3TxEnd_IrqHandler(void); +__WEAKDEF void Usart3RxTO_IrqHandler(void); +__WEAKDEF void Usart4RxErr_IrqHandler(void); +__WEAKDEF void Usart4RxEnd_IrqHandler(void); +__WEAKDEF void Usart4TxEmpty_IrqHandler(void); +__WEAKDEF void Usart4TxEnd_IrqHandler(void); +__WEAKDEF void Usart4RxTO_IrqHandler(void); + +__WEAKDEF void Spi1RxEnd_IrqHandler(void); +__WEAKDEF void Spi1TxEmpty_IrqHandler(void); +__WEAKDEF void Spi1Err_IrqHandler(void); +__WEAKDEF void Spi1Idle_IrqHandler(void); +__WEAKDEF void Spi2RxEnd_IrqHandler(void); +__WEAKDEF void Spi2TxEmpty_IrqHandler(void); +__WEAKDEF void Spi2Err_IrqHandler(void); +__WEAKDEF void Spi2Idle_IrqHandler(void); +__WEAKDEF void Spi3RxEnd_IrqHandler(void); +__WEAKDEF void Spi3TxEmpty_IrqHandler(void); +__WEAKDEF void Spi3Err_IrqHandler(void); +__WEAKDEF void Spi3Idle_IrqHandler(void); +__WEAKDEF void Spi4RxEnd_IrqHandler(void); +__WEAKDEF void Spi4TxEmpty_IrqHandler(void); +__WEAKDEF void Spi4Err_IrqHandler(void); +__WEAKDEF void Spi4Idle_IrqHandler(void); + +__WEAKDEF void Timer41GCMUH_IrqHandler(void); +__WEAKDEF void Timer41GCMUL_IrqHandler(void); +__WEAKDEF void Timer41GCMVH_IrqHandler(void); +__WEAKDEF void Timer41GCMVL_IrqHandler(void); +__WEAKDEF void Timer41GCMWH_IrqHandler(void); +__WEAKDEF void Timer41GCMWL_IrqHandler(void); +__WEAKDEF void Timer41GOV_IrqHandler(void); +__WEAKDEF void Timer41GUD_IrqHandler(void); +__WEAKDEF void Timer41ReloadU_IrqHandler(void); +__WEAKDEF void Timer41ReloadV_IrqHandler(void); +__WEAKDEF void Timer41ReloadW_IrqHandler(void); +__WEAKDEF void Timer42GCMUH_IrqHandler(void); +__WEAKDEF void Timer42GCMUL_IrqHandler(void); +__WEAKDEF void Timer42GCMVH_IrqHandler(void); +__WEAKDEF void Timer42GCMVL_IrqHandler(void); +__WEAKDEF void Timer42GCMWH_IrqHandler(void); +__WEAKDEF void Timer42GCMWL_IrqHandler(void); +__WEAKDEF void Timer42GOV_IrqHandler(void); +__WEAKDEF void Timer42GUD_IrqHandler(void); +__WEAKDEF void Timer42ReloadU_IrqHandler(void); +__WEAKDEF void Timer42ReloadV_IrqHandler(void); +__WEAKDEF void Timer42ReloadW_IrqHandler(void); +__WEAKDEF void Timer43GCMUH_IrqHandler(void); +__WEAKDEF void Timer43GCMUL_IrqHandler(void); +__WEAKDEF void Timer43GCMVH_IrqHandler(void); +__WEAKDEF void Timer43GCMVL_IrqHandler(void); +__WEAKDEF void Timer43GCMWH_IrqHandler(void); +__WEAKDEF void Timer43GCMWL_IrqHandler(void); +__WEAKDEF void Timer43GOV_IrqHandler(void); +__WEAKDEF void Timer43GUD_IrqHandler(void); +__WEAKDEF void Timer43ReloadU_IrqHandler(void); +__WEAKDEF void Timer43ReloadV_IrqHandler(void); +__WEAKDEF void Timer43ReloadW_IrqHandler(void); + +__WEAKDEF void Emb1_IrqHandler(void); +__WEAKDEF void Emb2_IrqHandler(void); +__WEAKDEF void Emb3_IrqHandler(void); +__WEAKDEF void Emb4_IrqHandler(void); + +__WEAKDEF void I2s1Tx_IrqHandler(void); +__WEAKDEF void I2s1Rx_IrqHandler(void); +__WEAKDEF void I2s1Err_IrqHandler(void); +__WEAKDEF void I2s2Tx_IrqHandler(void); +__WEAKDEF void I2s2Rx_IrqHandler(void); +__WEAKDEF void I2s2Err_IrqHandler(void); +__WEAKDEF void I2s3Tx_IrqHandler(void); +__WEAKDEF void I2s3Rx_IrqHandler(void); +__WEAKDEF void I2s3Err_IrqHandler(void); +__WEAKDEF void I2s4Tx_IrqHandler(void); +__WEAKDEF void I2s4Rx_IrqHandler(void); +__WEAKDEF void I2s4Err_IrqHandler(void); + +__WEAKDEF void I2c1RxEnd_IrqHandler(void); +__WEAKDEF void I2c1TxEnd_IrqHandler(void); +__WEAKDEF void I2c1TxEmpty_IrqHandler(void); +__WEAKDEF void I2c1Err_IrqHandler(void); +__WEAKDEF void I2c2RxEnd_IrqHandler(void); +__WEAKDEF void I2c2TxEnd_IrqHandler(void); +__WEAKDEF void I2c2TxEmpty_IrqHandler(void); +__WEAKDEF void I2c2Err_IrqHandler(void); +__WEAKDEF void I2c3RxEnd_IrqHandler(void); +__WEAKDEF void I2c3TxEnd_IrqHandler(void); +__WEAKDEF void I2c3TxEmpty_IrqHandler(void); +__WEAKDEF void I2c3Err_IrqHandler(void); + +__WEAKDEF void Pvd1_IrqHandler(void); +__WEAKDEF void Pvd2_IrqHandler(void); + +__WEAKDEF void FcmErr_IrqHandler(void); +__WEAKDEF void FcmEnd_IrqHandler(void); +__WEAKDEF void FcmOV_IrqHandler(void); + +__WEAKDEF void Wdt_IrqHandler(void); + +__WEAKDEF void ADC1A_IrqHandler(void); +__WEAKDEF void ADC1B_IrqHandler(void); +__WEAKDEF void ADC1ChCmp_IrqHandler(void); +__WEAKDEF void ADC1SeqCmp_IrqHandler(void); +__WEAKDEF void ADC2A_IrqHandler(void); +__WEAKDEF void ADC2B_IrqHandler(void); +__WEAKDEF void ADC2ChCmp_IrqHandler(void); +__WEAKDEF void ADC2SeqCmp_IrqHandler(void); + +__WEAKDEF void Sdio1_IrqHandler(void); +__WEAKDEF void Sdio2_IrqHandler(void); + +__WEAKDEF void Can_IrqHandler(void); + +//@} // InterruptGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_INTERRUPTS_ENABLE */ + +#endif /* __HC32F460_INTERRUPTS_H___ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_keyscan.h b/driver/inc/hc32f460_keyscan.h new file mode 100644 index 0000000..a82474b --- /dev/null +++ b/driver/inc/hc32f460_keyscan.h @@ -0,0 +1,191 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_keyscan.h + ** + ** A detailed description is available at + ** @link KeyscanGroup Keyscan description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of keyscan. + ** + ******************************************************************************/ + +#ifndef __HC32F460_KEYSCAN_H__ +#define __HC32F460_KEYSCAN_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + * \defgroup KeyscanGroup Matrix Key Scan Module (KeyScan) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Enumeration to hi-z state cycles of each keyout + ** + ** \note + ******************************************************************************/ +typedef enum en_hiz_cycle +{ + Hiz4 = 0u, + Hiz8 = 1u, + Hiz16 = 2u, + Hiz32 = 3u, + Hiz64 = 4u, + Hiz256 = 5u, + Hiz512 = 6u, + Hiz1K = 7u, +}en_hiz_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to low state cycles of each keyout + ** + ** \note + ******************************************************************************/ +typedef enum en_low_cycle +{ + Low8 = 3u, + Low16 = 4u, + Low32 = 5u, + Low64 = 6u, + Low128 = 7u, + Low256 = 8u, + Low512 = 9u, + Low1K = 10u, + Low2K = 11u, + Low4K = 12u, + Low8K = 13u, + Low16K = 14u, + Low32K = 15u, + Low64K = 16u, + Low128K = 17u, + Low256K = 18u, + Low512K = 19u, + Low1M = 20u, + Low2M = 21u, + Low4M = 22u, + Low8M = 23u, + Low16M = 24u, +}en_low_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to key scan clock + ** + ** \note + ******************************************************************************/ +typedef enum en_keyscan_clk +{ + KeyscanHclk = 0u, ///< use HCLK as scan clock + KeyscanLrc = 1u, ///< use internal Low RC as scan clock + KeyscanXtal32 = 2u, ///< use external XTAL32 as scan clock +}en_keyscan_clk_t; + +/** + ******************************************************************************* + ** \brief Enumeration to KEYOUT combination + ******************************************************************************/ +typedef enum en_keyout_sel +{ + Keyout0To1 = 1u, ///< KEYOUT 0 to 1 are selected + Keyout0To2 = 2u, ///< KEYOUT 0 to 2 are selected + Keyout0To3 = 3u, ///< KEYOUT 0 to 3 are selected + Keyout0To4 = 4u, ///< KEYOUT 0 to 4 are selected + Keyout0To5 = 5u, ///< KEYOUT 0 to 5 are selected + Keyout0To6 = 6u, ///< KEYOUT 0 to 6 are selected + Keyout0To7 = 7u, ///< KEYOUT 0 to 7 are selected +}en_keyout_sel_t; + +/** + ******************************************************************************* + ** \brief Enumeration to KEYIN combination + ******************************************************************************/ +typedef enum en_keyin_sel +{ + Keyin00 = 1u << 0, ///< KEYIN 0 is selected + Keyin01 = 1u << 1, ///< KEYIN 1 is selected + Keyin02 = 1u << 2, ///< KEYIN 2 is selected + Keyin03 = 1u << 3, ///< KEYIN 3 is selected + Keyin04 = 1u << 4, ///< KEYIN 4 is selected + Keyin05 = 1u << 5, ///< KEYIN 5 is selected + Keyin06 = 1u << 6, ///< KEYIN 6 is selected + Keyin07 = 1u << 7, ///< KEYIN 7 is selected + Keyin08 = 1u << 8, ///< KEYIN 8 is selected + Keyin09 = 1u << 9, ///< KEYIN 9 is selected + Keyin10 = 1u << 10, ///< KEYIN 10 is selected + Keyin11 = 1u << 11, ///< KEYIN 11 is selected + Keyin12 = 1u << 12, ///< KEYIN 12 is selected + Keyin13 = 1u << 13, ///< KEYIN 13 is selected + Keyin14 = 1u << 14, ///< KEYIN 14 is selected + Keyin15 = 1u << 15, ///< KEYIN 15 is selected +}en_keyin_sel_t; + +/** + ******************************************************************************* + ** \brief Keyscan configuration + ** + ** \note The Keyscan configuration structure + ******************************************************************************/ +typedef struct stc_keyscan_config +{ + en_hiz_cycle_t enHizCycle; ///< KEYOUT Hiz state cycles, ref @ en_hiz_cycle_t for details + en_low_cycle_t enLowCycle; ///< KEYOUT Low state cycles, ref @ en_low_cycle_t for details + en_keyscan_clk_t enKeyscanClk; ///< Key scan clock, ref @ en_keyscan_clk_t for details + en_keyout_sel_t enKeyoutSel; ///< KEYOUT selection, ref @ en_keyout_sel_t for details + uint16_t u16KeyinSel; ///< KEYIN selection, ref @ en_keyin_sel_t for details +}stc_keyscan_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t KEYSCAN_Init(const stc_keyscan_config_t *pstcKeyscanConfig); +extern en_result_t KEYSCAN_DeInit(void); +extern en_result_t KEYSCAN_Start(void); +extern en_result_t KEYSCAN_Stop(void); +extern uint8_t KEYSCAN_GetColIdx(void); + +//@} // KeyscanGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_KEYSCAN_ENABLE */ + +#endif /* __HC32F460_KEYSCAN_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_mpu.h b/driver/inc/hc32f460_mpu.h new file mode 100644 index 0000000..b46e6ce --- /dev/null +++ b/driver/inc/hc32f460_mpu.h @@ -0,0 +1,293 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_mpu.h + ** + ** A detailed description is available at + ** @link MpuGroup MPU description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of MPU. + ** + ******************************************************************************/ +#ifndef __HC32F460_MPU_H__ +#define __HC32F460_MPU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_MPU_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup MpuGroup Memory Protection Unit(MPU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief MPU region number enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_num +{ + MpuRegionNum0 = 0u, ///< MPU region number 0 + MpuRegionNum1 = 1u, ///< MPU region number 1 + MpuRegionNum2 = 2u, ///< MPU region number 2 + MpuRegionNum3 = 3u, ///< MPU region number 3 + MpuRegionNum4 = 4u, ///< MPU region number 4 + MpuRegionNum5 = 5u, ///< MPU region number 5 + MpuRegionNum6 = 6u, ///< MPU region number 6 + MpuRegionNum7 = 7u, ///< MPU region number 7 + MpuRegionNum8 = 8u, ///< MPU region number 8 + MpuRegionNum9 = 9u, ///< MPU region number 9 + MpuRegionNum10 = 10u, ///< MPU region number 10 + MpuRegionNum11 = 11u, ///< MPU region number 11 + MpuRegionNum12 = 12u, ///< MPU region number 12 + MpuRegionNum13 = 13u, ///< MPU region number 13 + MpuRegionNum14 = 14u, ///< MPU region number 14 + MpuRegionNum15 = 15u, ///< MPU region number 15 +} en_mpu_region_num_t; + +/** + ******************************************************************************* + ** \brief MPU region size enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_size +{ + MpuRegionSize32Byte = 4u, ///< 32 Byte + MpuRegionSize64Byte = 5u, ///< 64 Byte + MpuRegionSize128Byte = 6u, ///< 126 Byte + MpuRegionSize256Byte = 7u, ///< 256 Byte + MpuRegionSize512Byte = 8u, ///< 512 Byte + MpuRegionSize1KByte = 9u, ///< 1K Byte + MpuRegionSize2KByte = 10u, ///< 2K Byte + MpuRegionSize4KByte = 11u, ///< 4K Byte + MpuRegionSize8KByte = 12u, ///< 8K Byte + MpuRegionSize16KByte = 13u, ///< 16K Byte + MpuRegionSize32KByte = 14u, ///< 32K Byte + MpuRegionSize64KByte = 15u, ///< 64K Byte + MpuRegionSize128KByte = 16u, ///< 128K Byte + MpuRegionSize256KByte = 17u, ///< 256K Byte + MpuRegionSize512KByte = 18u, ///< 512K Byte + MpuRegionSize1MByte = 19u, ///< 1M Byte + MpuRegionSize2MByte = 20u, ///< 2M Byte + MpuRegionSize4MByte = 21u, ///< 4M Byte + MpuRegionSize8MByte = 22u, ///< 8M Byte + MpuRegionSize16MByte = 23u, ///< 16M Byte + MpuRegionSize32MByte = 24u, ///< 32M Byte + MpuRegionSize64MByte = 25u, ///< 64M Byte + MpuRegionSize128MByte = 26u, ///< 128M Byte + MpuRegionSize256MByte = 27u, ///< 256M Byte + MpuRegionSize512MByte = 28u, ///< 512M Byte + MpuRegionSize1GByte = 29u, ///< 1G Byte + MpuRegionSize2GByte = 30u, ///< 2G Byte + MpuRegionSize4GByte = 31u, ///< 4G Byte +} en_mpu_region_size_t; + +/** + ******************************************************************************* + ** \brief MPU region enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_type +{ + SMPU1Region = 0u, ///< System DMA_1 MPU + SMPU2Region = 1u, ///< System DMA_2 MPU + FMPURegion = 2u, ///< System USBFS_DMA MPU +} en_mpu_region_type_t; + +/** + ******************************************************************************* + ** \brief MPU action selection enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_action_sel +{ + MpuNoneAction = 0u, ///< MPU don't action. + MpuTrigBusError = 1u, ///< MPU trigger bus error + MpuTrigNmi = 2u, ///< MPU trigger bus NMI interrupt + MpuTrigReset = 3u, ///< MPU trigger reset +} en_mpu_action_sel_t; + +/** + ******************************************************************************* + ** \brief MPU IP protection mode enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_ip_prot_mode +{ + AesReadProt = (1ul << 0), ///< AES read protection + AesWriteProt = (1ul << 1), ///< AES write protection + HashReadProt = (1ul << 2), ///< HASH read protection + HashWriteProt = (1ul << 3), ///< HASH write protection + TrngReadProt = (1ul << 4), ///< TRNG read protection + TrngWriteProt = (1ul << 5), ///< TRNG write protection + CrcReadProt = (1ul << 6), ///< CRC read protection + CrcWriteProt = (1ul << 7), ///< CRC write protection + FmcReadProt = (1ul << 8), ///< FMC read protection + FmcWriteProt = (1ul << 9), ///< FMC write protection + WdtReadProt = (1ul << 12), ///< WDT read protection + WdtWriteProt = (1ul << 13), ///< WDT write protection + SwdtReadProt = (1ul << 14), ///< WDT read protection + SwdtWriteProt = (1ul << 15), ///< WDT write protection + BksramReadProt = (1ul << 16), ///< BKSRAM read protection + BksramWriteProt = (1ul << 17), ///< BKSRAM write protection + RtcReadProt = (1ul << 18), ///< RTC read protection + RtcWriteProt = (1ul << 19), ///< RTC write protection + DmpuReadProt = (1ul << 20), ///< DMPU read protection + DmpuWriteProt = (1ul << 21), ///< DMPU write protection + SramcReadProt = (1ul << 22), ///< SRAMC read protection + SramcWriteProt = (1ul << 23), ///< SRAMC write protection + IntcReadProt = (1ul << 24), ///< INTC read protection + IntcWriteProt = (1ul << 25), ///< INTC write protection + SyscReadProt = (1ul << 26), ///< SYSC read protection + SyscWriteProt = (1ul << 27), ///< SYSC write protection + MstpReadProt = (1ul << 28), ///< MSTP read protection + MstpWriteProt = (1ul << 29), ///< MSTP write protection + BusErrProt = (1ul << 31), ///< BUSERR write protection +} en_mpu_ip_prot_mode_t; + +/** + ******************************************************************************* + ** \brief MPU protection region permission + ** + ******************************************************************************/ +typedef struct stc_mpu_prot_region_permission +{ + en_mpu_action_sel_t enAction; ///< Specifies MPU action + + en_functional_state_t enRegionEnable; ///< Disable: Disable region protection; Enable:Enable region protection + + en_functional_state_t enWriteEnable; ///< Disable: Prohibited to write; Enable:permitted to write + + en_functional_state_t enReadEnable; ///< Disable: Prohibited to read; Enable:permitted to read + +} stc_mpu_prot_region_permission_t; + +/** + ******************************************************************************* + ** \brief MPU background region permission + ** + ******************************************************************************/ +typedef struct stc_mpu_bkgd_region_permission +{ + en_functional_state_t enWriteEnable; ///< Disable: Prohibited to write; Enable:permitted to write + + en_functional_state_t enReadEnable; ///< Disable: Prohibited to read; Enable:permitted to read +} stc_mpu_bkgd_region_permission_t_t; + +/** + ******************************************************************************* + ** \brief MPU background region initialization configuration + ** + ******************************************************************************/ +typedef struct stc_mpu_bkgd_region_init +{ + stc_mpu_bkgd_region_permission_t_t stcSMPU1BkgdPermission; ///< Specifies SMPU1 background permission and this stuctrue detail refer of @ref stc_mpu_bkgd_region_permission_t_t + + stc_mpu_bkgd_region_permission_t_t stcSMPU2BkgdPermission; ///< Specifies SMPU2 background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t + + stc_mpu_bkgd_region_permission_t_t stcFMPUBkgdPermission; ///< Specifies FMPU background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t +} stc_mpu_bkgd_region_init_t; + +/** + ******************************************************************************* + ** \brief MPU protect region initialization configuration + ** + ******************************************************************************/ +typedef struct stc_mpu_prot_region_init +{ + uint32_t u32RegionBaseAddress; ///< Specifies region base address + + en_mpu_region_size_t enRegionSize; ///< Specifies region size and This parameter can be a value of @ref en_mpu_region_size_t + + stc_mpu_prot_region_permission_t stcSMPU1Permission; ///< Specifies DMA1 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t + + stc_mpu_prot_region_permission_t stcSMPU2Permission; ///< Specifies DMA2 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t + + stc_mpu_prot_region_permission_t stcFMPUPermission; ///< Specifies USBFS-DMA MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t +} stc_mpu_prot_region_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t MPU_ProtRegionInit(en_mpu_region_num_t enRegionNum, + const stc_mpu_prot_region_init_t *pstcInitCfg); +en_result_t MPU_BkgdRegionInit(const stc_mpu_bkgd_region_init_t *pstcInitCfg); +en_result_t MPU_SetRegionSize(en_mpu_region_num_t enRegionNum, + en_mpu_region_size_t enRegionSize); +en_mpu_region_size_t MPU_GetRegionSize(en_mpu_region_num_t enRegionNum); +en_result_t MPU_SetRegionBaseAddress(en_mpu_region_num_t enRegionNum, + uint32_t u32RegionBaseAddr); +uint32_t MPU_GetRegionBaseAddress(en_mpu_region_num_t enRegionNum); +en_result_t MPU_SetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType, + en_mpu_action_sel_t enActionSel); +en_mpu_action_sel_t MPU_GetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_ProtRegionCmd(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_result_t MPU_RegionTypeCmd(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_flag_status_t MPU_GetStatus(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_ClearStatus(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_WriteProtCmd(en_functional_state_t enState); +en_result_t MPU_IpProtCmd(uint32_t u32ProtMode, + en_functional_state_t enState); + +//@} // MpuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_MPU_ENABLE */ + +#endif /* __HC32F460_MPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_ots.h b/driver/inc/hc32f460_ots.h new file mode 100644 index 0000000..53a00ff --- /dev/null +++ b/driver/inc/hc32f460_ots.h @@ -0,0 +1,139 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_ots.h + ** + ** A detailed description is available at + ** @link OtsGroup Ots description @endlink + ** + ** - 2018-10-26 CDT First version for Device Driver Library of Ots. + ** + ******************************************************************************/ +#ifndef __HC32F460_OTS_H__ +#define __HC32F460_OTS_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_OTS_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup OtsGroup On-chip Temperature Sensor(OTS) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* Automatically turn off the analog temperature sensor after the temperature + measurement is over. */ +typedef enum en_ots_auto_off +{ + OtsAutoOff_Disable = 0x0, ///< Disable automatically turn off OTS. + OtsAutoOff_Enable = 0x1, ///< Enable automatically turn off OTS. +} en_ots_auto_off_t; + +/* Temperature measurement end interrupt request. */ +typedef enum en_ots_ie +{ + OtsInt_Disable = 0x0, ///< Disable OTS interrupt. + OtsInt_Enable = 0x1, ///< Enable OTS interrupt. +} en_ots_ie_t; + +/* OTS clock selection. */ +typedef enum en_ots_clk_sel +{ + OtsClkSel_Xtal = 0x0, ///< Select XTAL as OTS clock. + OtsClkSel_Hrc = 0x1, ///< Select HRC as OTS clock. +} en_ots_clk_sel_t; + +/* OTS OTS initialization structure definition. */ +typedef struct stc_ots_init +{ + en_ots_auto_off_t enAutoOff; ///< @ref en_ots_auto_off_t. + en_ots_clk_sel_t enClkSel; ///< @ref en_ots_clk_sel_t. + float32_t f32SlopeK; ///< K: Temperature slope (calculated by calibration experiment). */ + float32_t f32OffsetM; ///< M: Temperature offset (calculated by calibration experiment). */ +} stc_ots_init_t; + +/* OTS common trigger source select */ +typedef enum en_ots_com_trigger +{ + OtsComTrigger_1 = 0x1, ///< Select common trigger 1. + OtsComTrigger_2 = 0x2, ///< Select common trigger 2. + OtsComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_ots_com_trigger_t; + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @brief Start OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Start(void) +{ + bM4_OTS_CTL_OTSST = (uint32_t)1u; +} + +/** + * @brief Stop OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Stop(void) +{ + bM4_OTS_CTL_OTSST = (uint32_t)0u; +} + +en_result_t OTS_Init(const stc_ots_init_t *pstcInit); +void OTS_DeInit(void); + +en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout); + +void OTS_IntCmd(en_functional_state_t enNewState); +void OTS_SetTriggerSrc(en_event_src_t enEvent); +void OTS_ComTriggerCmd(en_ots_com_trigger_t enComTrigger, en_functional_state_t enState); + +en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \ + uint16_t *pu16Ecr, float32_t *pf32A, \ + uint32_t u32Timeout); + +float OTS_CalculateTemp(void); + +//@} // OtsGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_OTS_ENABLE */ + +#endif /* __HC32F460_OTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_pwc.h b/driver/inc/hc32f460_pwc.h new file mode 100644 index 0000000..f170784 --- /dev/null +++ b/driver/inc/hc32f460_pwc.h @@ -0,0 +1,567 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_pwc.h + ** + ** A detailed description is available at + ** @link PwcGroup PWC description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of PWC. + ** + ******************************************************************************/ +#ifndef __HC32F460_PWC_H__ +#define __HC32F460_PWC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_PWC_ENABLE == DDL_ON) + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup PwcGroup Power Control(PWC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The power down mode. + ** + ******************************************************************************/ +typedef enum en_pwc_powerdown_md +{ + PowerDownMd1 = 0u, ///< Power down mode 1. + PowerDownMd2 = 1u, ///< Power down mode 2. + PowerDownMd3 = 2u, ///< Power down mode 3. + PowerDownMd4 = 3u, ///< Power down mode 4. +}en_pwc_powerdown_md_t; + +/** + ******************************************************************************* + ** \brief The IO retain status under power down mode. + ** + ******************************************************************************/ +typedef enum en_pwc_iortn +{ + IoPwrDownRetain = 0u, ///< Io keep under power down mode. + IoPwrRstRetain = 1u, ///< Io keep after power reset. + IoHighImp = 2u, ///< IO high impedance either power down or power reset. +}en_pwc_iortn_t; + +/** + ******************************************************************************* + ** \brief The driver ability while different speed mode enter stop mode. + ** + ******************************************************************************/ +typedef enum en_pwc_stopdas +{ + StopHighspeed = 0u, ///< The driver ability while high speed mode enter stop mode. + StopUlowspeed = 3u, ///< The driver ability while ultra_low speed mode enter stop mode. +}en_pwc_stopdas_t; + +/** + ******************************************************************************* + ** \brief The dynamic power driver voltage select. + ** + ******************************************************************************/ +typedef enum en_pwc_rundrvs +{ + RunUHighspeed = 0u, ///< The ultra_high speed. + RunUlowspeed = 2u, ///< The ultra_low speed. + RunHighspeed = 3u, ///< The high speed. +}en_pwc_rundrvs_t; + +/** + ******************************************************************************* + ** \brief The dynamic power driver ability scaling. + ** + ******************************************************************************/ +typedef enum en_pwc_drvability_sca +{ + Ulowspeed = 8u, ///< The ultra_low speed. + HighSpeed = 15u, ///< The high speed. +}en_pwc_drvability_sca_t; + +/** + ******************************************************************************* + ** \brief The power down wake up time select. + ** + ******************************************************************************/ +typedef enum en_pwc_waketime_sel +{ + Vcap01 = 0u, ///< Wake up while vcap capacitance 2*0.1uf. + Vcap0047 = 1u, ///< Wake up while vcap capacitance 2*0.047uf. +}en_pwc_waketime_sel_t; + +/** + ******************************************************************************* + ** \brief The wait or not wait flash stable while stop mode awake. + ** + ******************************************************************************/ +typedef enum en_pwc_stop_flash_sel +{ + Wait = 0u, ///< wait flash stable. + NotWait = 1u, ///< Not Wait flash stable. +}en_pwc_stop_flash_sel_t; + +/** + ******************************************************************************* + ** \brief The clk value while stop mode awake. + ** + ******************************************************************************/ +typedef enum en_pwc_stop_clk_sel +{ + ClkFix = 0u, ///< clock fix. + ClkMrc = 1u, ///< clock source is MRC, only ram code. +}en_pwc_stop_clk_sel_t; + +/** + ******************************************************************************* + ** \brief The power down wake up event edge select. + ** + ******************************************************************************/ +typedef enum en_pwc_edge_sel +{ + EdgeFalling = 0u, ///< Falling edge. + EdgeRising = 1u, ///< Rising edge. +}en_pwc_edge_sel_t; + +/** + ******************************************************************************* + ** \brief The voltage detect edge select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvdedge_sel +{ + OverVcc = 0u, ///< PVD > VCC. + BelowVcc = 1u, ///< PVD < VCC. +}en_pwc_pvdedge_sel_t; + +/** + ******************************************************************************* + ** \brief The flag of wake_up timer compare result. + ** + ******************************************************************************/ +typedef enum en_pwc_wkover_flag +{ + UnEqual = 0u, ///< Timer value unequal with the wake_up compare value whitch set. + Equal = 1u, ///< Timer value equal with the wake_up compare value whitch set.. +}en_pwc_wkover_flag_t; + +/** + ******************************************************************************* + ** \brief The RAM operating mode. + ** + ******************************************************************************/ +typedef enum en_pwc_ram_op_md +{ + HighSpeedMd = 0x8043, ///< Work at high speed. + UlowSpeedMd = 0x9062, ///< Work at ultra low speed. +}en_pwc_ram_op_md_t; + +/** + ******************************************************************************* + ** \brief The wake up clock select. + ** + ******************************************************************************/ +typedef enum en_pwc_wkclk_sel +{ + Wk64hz = 0u, ///< 64Hz. + WkXtal32 = 1u, ///< Xtal32. + WkLrc = 2u, ///< Lrc. +}en_pwc_wkclk_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd digital filtering sampling clock select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvdfiltclk_sel +{ + PvdLrc025 = 0u, ///< 0.25 LRC cycle. + PvdLrc05 = 1u, ///< 0.5 LRC cycle. + PvdLrc1 = 2u, ///< LRC 1 div. + PvdLrc2 = 3u, ///< LRC 2 div. +}en_pwc_pvdfiltclk_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd2 level select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvd2level_sel +{ + Pvd2Level0 = 0u, ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode. + Pvd2Level1 = 1u, ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode. + Pvd2Level2 = 2u, ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode. + Pvd2Level3 = 3u, ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode. + Pvd2Level4 = 4u, ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode. + Pvd2Level5 = 5u, ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode. + Pvd2Level6 = 6u, ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode. + Pvd2Level7 = 7u, ///< 1.1V.while high_speed & ultra_low speed mode, 1.15V.while ultra_high speed mode. +}en_pwc_pvd2level_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd1 level select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvd1level_sel +{ + Pvd1Level0 = 0u, ///< 2.0V.while high_speed & ultra_low speed mode, 2.09V.while ultra_high speed mode. + Pvd1Level1 = 1u, ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode. + Pvd1Level2 = 2u, ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode. + Pvd1Level3 = 3u, ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode. + Pvd1Level4 = 4u, ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode. + Pvd1Level5 = 5u, ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode. + Pvd1Level6 = 6u, ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode. + Pvd1Level7 = 7u, ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode. +}en_pwc_pvd1level_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd interrupt select. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd_int_sel +{ + NonMskInt = 0u, ///< Non-maskable Interrupt. + MskInt = 1u, ///< Maskable Interrupt. +}en_pwc_pvd_int_sel_t; + +/** + ******************************************************************************* + ** \brief The handle of pvd mode. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd_md +{ + PvdInt = 0u, ///< The handle of pvd is interrupt. + PvdReset = 1u, ///< The handle of pvd is reset. +}en_pwc_pvd_md_t; + +/** + ******************************************************************************* + ** \brief The unit of pvd detect. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd +{ + PvdU1 = 0u, ///< The uint1 of pvd detect. + PvdU2 = 1u, ///< The unit2 of pvd detect. +}en_pwc_pvd_t; + +/** + ******************************************************************************* + ** \brief The power mode configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_pwr_mode_cfg +{ + en_pwc_powerdown_md_t enPwrDownMd; ///< Power down mode. + en_functional_state_t enRLdo; ///< Enable or disable RLDO. + en_functional_state_t enRetSram; ///< Enable or disable Ret_Sram. + en_pwc_iortn_t enIoRetain; ///< IO retain. + en_pwc_waketime_sel_t enPwrDWkupTm; ///< The power down wake up time select. +}stc_pwc_pwr_mode_cfg_t; + +/** + ******************************************************************************* + ** \brief The stop mode configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_stop_mode_cfg +{ + en_pwc_stopdas_t enStpDrvAbi; ///< Driver ability while enter stop mode. + en_pwc_stop_flash_sel_t enStopFlash; ///< Flash mode while stop mode awake. + en_pwc_stop_clk_sel_t enStopClk; ///< Clock value while stop mode awake. + en_functional_state_t enPll; ///< Whether the PLL enable or disable while enter stop mode. +}stc_pwc_stop_mode_cfg_t; + +/** + ******************************************************************************* + ** \brief The power down wake_up timer control. + ** + ******************************************************************************/ +typedef struct stc_pwc_wktm_ctl +{ + uint16_t u16WktmCmp; ///< The wake_up timer compare value. + en_pwc_wkover_flag_t enWkOverFlag; ///< The flag of compare result. + en_pwc_wkclk_sel_t enWkclk; ///< The clock of wake_up timer. + en_functional_state_t enWktmEn; ///< Enable or disable wake_up timer. +}stc_pwc_wktm_ctl_t; + +/** + ******************************************************************************* + ** \brief The pvd control. + ** + ******************************************************************************/ +typedef struct stc_pwc_pvd_ctl +{ + en_functional_state_t enPvdIREn; ///< Enable or disable pvd interrupt(reset). + en_pwc_pvd_md_t enPvdMode; ///< The handle of pvd is interrupt or reset. + en_functional_state_t enPvdCmpOutEn; ///< Enable or disable pvd output compare result . +}stc_pwc_pvd_ctl_t; + +/** + ******************************************************************************* + ** \brief The power down wake_up event configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_pvd_cfg +{ + stc_pwc_pvd_ctl_t stcPvd1Ctl; ///< Pvd1 control configuration. + stc_pwc_pvd_ctl_t stcPvd2Ctl; ///< Pvd2 control configuration. + en_functional_state_t enPvd1FilterEn; ///< Pvd1 filtering enable or disable. + en_functional_state_t enPvd2FilterEn; ///< Pvd2 filtering enable or disable. + en_pwc_pvdfiltclk_sel_t enPvd1Filtclk; ///< Pvd1 filtering sampling clock. + en_pwc_pvdfiltclk_sel_t enPvd2Filtclk; ///< Pvd2 filtering sampling clock. + en_pwc_pvd1level_sel_t enPvd1Level; ///< Pvd1 voltage. + en_pwc_pvd2level_sel_t enPvd2Level; ///< Pvd2 voltage. + en_pwc_pvd_int_sel_t enPvd1Int; ///< Pvd1 interrupt. + en_pwc_pvd_int_sel_t enPvd2Int; ///< Pvd2 interrupt. +}stc_pwc_pvd_cfg_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define PWC_PDWKEN0_WKUP00 ((uint8_t)0x01) +#define PWC_PDWKEN0_WKUP01 ((uint8_t)0x02) +#define PWC_PDWKEN0_WKUP02 ((uint8_t)0x04) +#define PWC_PDWKEN0_WKUP03 ((uint8_t)0x08) +#define PWC_PDWKEN0_WKUP10 ((uint8_t)0x10) +#define PWC_PDWKEN0_WKUP11 ((uint8_t)0x20) +#define PWC_PDWKEN0_WKUP12 ((uint8_t)0x40) +#define PWC_PDWKEN0_WKUP13 ((uint8_t)0x80) + +#define PWC_PDWKEN1_WKUP20 ((uint8_t)0x01) +#define PWC_PDWKEN1_WKUP21 ((uint8_t)0x02) +#define PWC_PDWKEN1_WKUP22 ((uint8_t)0x04) +#define PWC_PDWKEN1_WKUP23 ((uint8_t)0x08) +#define PWC_PDWKEN1_WKUP30 ((uint8_t)0x10) +#define PWC_PDWKEN1_WKUP31 ((uint8_t)0x20) +#define PWC_PDWKEN1_WKUP32 ((uint8_t)0x40) +#define PWC_PDWKEN1_WKUP33 ((uint8_t)0x80) + +#define PWC_PDWKEN2_PVD1 ((uint8_t)0x01) +#define PWC_PDWKEN2_PVD2 ((uint8_t)0x02) +#define PWC_PDWKEN2_NMI ((uint8_t)0x04) +#define PWC_PDWKEN2_RTCPRD ((uint8_t)0x10) +#define PWC_PDWKEN2_RTCAL ((uint8_t)0x20) +#define PWC_PDWKEN2_WKTM ((uint8_t)0x80) + +#define PWC_PDWKUP_EDGE_WKP0 ((uint8_t)0x01) +#define PWC_PDWKUP_EDGE_WKP1 ((uint8_t)0x02) +#define PWC_PDWKUP_EDGE_WKP2 ((uint8_t)0x04) +#define PWC_PDWKUP_EDGE_WKP3 ((uint8_t)0x08) +#define PWC_PDWKUP_EDGE_PVD1 ((uint8_t)0x10) +#define PWC_PDWKUP_EDGE_PVD2 ((uint8_t)0x20) +#define PWC_PDWKUP_EDGE_NMI ((uint8_t)0x40) + +#define PWC_RAMPWRDOWN_SRAM1 ((uint32_t)0x00000001) +#define PWC_RAMPWRDOWN_SRAM2 ((uint32_t)0x00000002) +#define PWC_RAMPWRDOWN_SRAM3 ((uint32_t)0x00000004) +#define PWC_RAMPWRDOWN_SRAMH ((uint32_t)0x00000008) +#define PWC_RAMPWRDOWN_USBFS ((uint32_t)0x00000010) +#define PWC_RAMPWRDOWN_SDIOC0 ((uint32_t)0x00000020) +#define PWC_RAMPWRDOWN_SDIOC1 ((uint32_t)0x00000040) +#define PWC_RAMPWRDOWN_CAN ((uint32_t)0x00000080) +#define PWC_RAMPWRDOWN_CACHE ((uint32_t)0x00000100) +#define PWC_RAMPWRDOWN_FULL ((uint32_t)0x000001FF) + +#define PWC_STOPWKUPEN_EIRQ0 ((uint32_t)0x00000001) +#define PWC_STOPWKUPEN_EIRQ1 ((uint32_t)0x00000002) +#define PWC_STOPWKUPEN_EIRQ2 ((uint32_t)0x00000004) +#define PWC_STOPWKUPEN_EIRQ3 ((uint32_t)0x00000008) +#define PWC_STOPWKUPEN_EIRQ4 ((uint32_t)0x00000010) +#define PWC_STOPWKUPEN_EIRQ5 ((uint32_t)0x00000020) +#define PWC_STOPWKUPEN_EIRQ6 ((uint32_t)0x00000040) +#define PWC_STOPWKUPEN_EIRQ7 ((uint32_t)0x00000080) +#define PWC_STOPWKUPEN_EIRQ8 ((uint32_t)0x00000100) +#define PWC_STOPWKUPEN_EIRQ9 ((uint32_t)0x00000200) +#define PWC_STOPWKUPEN_EIRQ10 ((uint32_t)0x00000400) +#define PWC_STOPWKUPEN_EIRQ11 ((uint32_t)0x00000800) +#define PWC_STOPWKUPEN_EIRQ12 ((uint32_t)0x00001000) +#define PWC_STOPWKUPEN_EIRQ13 ((uint32_t)0x00002000) +#define PWC_STOPWKUPEN_EIRQ14 ((uint32_t)0x00004000) +#define PWC_STOPWKUPEN_EIRQ15 ((uint32_t)0x00008000) +#define PWC_STOPWKUPEN_SWDT ((uint32_t)0x00010000) +#define PWC_STOPWKUPEN_VDU1 ((uint32_t)0x00020000) +#define PWC_STOPWKUPEN_VDU2 ((uint32_t)0x00040000) +#define PWC_STOPWKUPEN_CMPI0 ((uint32_t)0x00080000) +#define PWC_STOPWKUPEN_WKTM ((uint32_t)0x00100000) +#define PWC_STOPWKUPEN_RTCAL ((uint32_t)0x00200000) +#define PWC_STOPWKUPEN_RTCPRD ((uint32_t)0x00400000) +#define PWC_STOPWKUPEN_TMR0 ((uint32_t)0x00800000) +#define PWC_STOPWKUPEN_USARTRXD ((uint32_t)0x02000000) + +#define PWC_PTWK0_WKUPFLAG ((uint8_t)0x01) +#define PWC_PTWK1_WKUPFLAG ((uint8_t)0x02) +#define PWC_PTWK2_WKUPFLAG ((uint8_t)0x04) +#define PWC_PTWK3_WKUPFLAG ((uint8_t)0x08) +#define PWC_PVD1_WKUPFLAG ((uint8_t)0x10) +#define PWC_PVD2_WKUPFLAG ((uint8_t)0x20) +#define PWC_NMI_WKUPFLAG ((uint8_t)0x40) + +#define PWC_RTCPRD_WKUPFALG ((uint8_t)0x10) +#define PWC_RTCAL_WKUPFLAG ((uint8_t)0x20) +#define PWC_WKTM_WKUPFLAG ((uint8_t)0x80) + +#define PWC_WKTMCMP_MSK ((uint16_t)0x0FFF) + +#define PWC_FCG0_PERIPH_SRAMH ((uint32_t)0x00000001) +#define PWC_FCG0_PERIPH_SRAM12 ((uint32_t)0x00000010) +#define PWC_FCG0_PERIPH_SRAM3 ((uint32_t)0x00000100) +#define PWC_FCG0_PERIPH_SRAMRET ((uint32_t)0x00000400) +#define PWC_FCG0_PERIPH_DMA1 ((uint32_t)0x00004000) +#define PWC_FCG0_PERIPH_DMA2 ((uint32_t)0x00008000) +#define PWC_FCG0_PERIPH_FCM ((uint32_t)0x00010000) +#define PWC_FCG0_PERIPH_AOS ((uint32_t)0x00020000) +#define PWC_FCG0_PERIPH_AES ((uint32_t)0x00100000) +#define PWC_FCG0_PERIPH_HASH ((uint32_t)0x00200000) +#define PWC_FCG0_PERIPH_TRNG ((uint32_t)0x00400000) +#define PWC_FCG0_PERIPH_CRC ((uint32_t)0x00800000) +#define PWC_FCG0_PERIPH_DCU1 ((uint32_t)0x01000000) +#define PWC_FCG0_PERIPH_DCU2 ((uint32_t)0x02000000) +#define PWC_FCG0_PERIPH_DCU3 ((uint32_t)0x04000000) +#define PWC_FCG0_PERIPH_DCU4 ((uint32_t)0x08000000) +#define PWC_FCG0_PERIPH_KEY ((uint32_t)0x80000000) + + +#define PWC_FCG1_PERIPH_CAN ((uint32_t)0x00000001) +#define PWC_FCG1_PERIPH_QSPI ((uint32_t)0x00000008) +#define PWC_FCG1_PERIPH_I2C1 ((uint32_t)0x00000010) +#define PWC_FCG1_PERIPH_I2C2 ((uint32_t)0x00000020) +#define PWC_FCG1_PERIPH_I2C3 ((uint32_t)0x00000040) +#define PWC_FCG1_PERIPH_USBFS ((uint32_t)0x00000100) +#define PWC_FCG1_PERIPH_SDIOC1 ((uint32_t)0x00000400) +#define PWC_FCG1_PERIPH_SDIOC2 ((uint32_t)0x00000800) +#define PWC_FCG1_PERIPH_I2S1 ((uint32_t)0x00001000) +#define PWC_FCG1_PERIPH_I2S2 ((uint32_t)0x00002000) +#define PWC_FCG1_PERIPH_I2S3 ((uint32_t)0x00004000) +#define PWC_FCG1_PERIPH_I2S4 ((uint32_t)0x00008000) +#define PWC_FCG1_PERIPH_SPI1 ((uint32_t)0x00010000) +#define PWC_FCG1_PERIPH_SPI2 ((uint32_t)0x00020000) +#define PWC_FCG1_PERIPH_SPI3 ((uint32_t)0x00040000) +#define PWC_FCG1_PERIPH_SPI4 ((uint32_t)0x00080000) +#define PWC_FCG1_PERIPH_USART1 ((uint32_t)0x01000000) +#define PWC_FCG1_PERIPH_USART2 ((uint32_t)0x02000000) +#define PWC_FCG1_PERIPH_USART3 ((uint32_t)0x04000000) +#define PWC_FCG1_PERIPH_USART4 ((uint32_t)0x08000000) + +#define PWC_FCG2_PERIPH_TIM01 ((uint32_t)0x00000001) +#define PWC_FCG2_PERIPH_TIM02 ((uint32_t)0x00000002) +#define PWC_FCG2_PERIPH_TIMA1 ((uint32_t)0x00000004) +#define PWC_FCG2_PERIPH_TIMA2 ((uint32_t)0x00000008) +#define PWC_FCG2_PERIPH_TIMA3 ((uint32_t)0x00000010) +#define PWC_FCG2_PERIPH_TIMA4 ((uint32_t)0x00000020) +#define PWC_FCG2_PERIPH_TIMA5 ((uint32_t)0x00000040) +#define PWC_FCG2_PERIPH_TIMA6 ((uint32_t)0x00000080) +#define PWC_FCG2_PERIPH_TIM41 ((uint32_t)0x00000100) +#define PWC_FCG2_PERIPH_TIM42 ((uint32_t)0x00000200) +#define PWC_FCG2_PERIPH_TIM43 ((uint32_t)0x00000400) +#define PWC_FCG2_PERIPH_EMB ((uint32_t)0x00008000) +#define PWC_FCG2_PERIPH_TIM61 ((uint32_t)0x00010000) +#define PWC_FCG2_PERIPH_TIM62 ((uint32_t)0x00020000) +#define PWC_FCG2_PERIPH_TIM63 ((uint32_t)0x00040000) + +#define PWC_FCG3_PERIPH_ADC1 ((uint32_t)0x00000001) +#define PWC_FCG3_PERIPH_ADC2 ((uint32_t)0x00000002) +#define PWC_FCG3_PERIPH_CMP ((uint32_t)0x00000100) +#define PWC_FCG3_PERIPH_OTS ((uint32_t)0x00001000) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void PWC_PowerModeCfg(const stc_pwc_pwr_mode_cfg_t* pstcPwrMdCfg); +void PWC_EnterPowerDownMd(void); + +void PWC_PdWakeup0Cmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState); +void PWC_PdWakeup1Cmd(uint32_t u32Wkup1Event, en_functional_state_t enNewState); +void PWC_PdWakeup2Cmd(uint32_t u32Wkup2Event, en_functional_state_t enNewState); +void PWC_PdWakeupEvtEdgeCfg(uint8_t u8WkupEvent, en_pwc_edge_sel_t enEdge); + +en_flag_status_t PWC_GetWakeup0Flag(uint8_t u8WkupFlag); +en_flag_status_t PWC_GetWakeup1Flag(uint8_t u8WkupFlag); +void PWC_ClearWakeup0Flag(uint8_t u8WkupFlag); +void PWC_ClearWakeup1Flag(uint8_t u8WkupFlag); +void PWC_PwrMonitorCmd(en_functional_state_t enNewState); + +void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState); +void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState); +void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState); +void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState); + +en_result_t PWC_StopModeCfg(const stc_pwc_stop_mode_cfg_t* pstcStpMdCfg); +void PWC_StopWkupCmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState); + +void PWC_EnterStopMd(void); +void PWC_EnterSleepMd(void); + +void PWC_Xtal32CsCmd(en_functional_state_t enNewState); +void PWC_HrcPwrCmd(en_functional_state_t enNewState); +void PWC_PllPwrCmd(en_functional_state_t enNewState); +void PWC_RamPwrdownCmd(uint32_t u32RamCtlBit, en_functional_state_t enNewState); +void PWC_RamOpMdConfig(en_pwc_ram_op_md_t enRamOpMd); + +void PWC_WktmControl(const stc_pwc_wktm_ctl_t* pstcWktmCtl); + +void PWC_PvdCfg(const stc_pwc_pvd_cfg_t* pstcPvdCfg); +void PWC_Pvd1Cmd(en_functional_state_t enNewState); +void PWC_Pvd2Cmd(en_functional_state_t enNewState); +void PWC_ExVccCmd(en_functional_state_t enNewState); +void PWC_ClearPvdFlag(en_pwc_pvd_t enPvd); +en_flag_status_t PWC_GetPvdFlag(en_pwc_pvd_t enPvd); +en_flag_status_t PWC_GetPvdStatus(en_pwc_pvd_t enPvd); + +void PWC_enNvicBackup(void); +void PWC_enNvicRecover(void); +void PWC_ClkBackup(void); +void PWC_ClkRecover(void); +void PWC_IrqClkBackup(void); +void PWC_IrqClkRecover(void); + +en_result_t PWC_HS2LS(void); +en_result_t PWC_LS2HS(void); +en_result_t PWC_HS2HP(void); +en_result_t PWC_HP2HS(void); +en_result_t PWC_LS2HP(void); +en_result_t PWC_HP2LS(void); + +//@} // PwcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_PWC_ENABLE */ + +#endif /* __HC32F460_PWC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_qspi.h b/driver/inc/hc32f460_qspi.h new file mode 100644 index 0000000..6bcbf6d --- /dev/null +++ b/driver/inc/hc32f460_qspi.h @@ -0,0 +1,402 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_qspi.h + ** + ** A detailed description is available at + ** @link QspiGroup Queued SPI description @endlink + ** + ** - 2018-11-20 CDT First version for Device Driver Library of Qspi. + ** + ******************************************************************************/ +#ifndef __HC32F460_QSPI_H__ +#define __HC32F460_QSPI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_QSPI_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup QspiGroup Queued SPI(QSPI) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief QSPI spi protocol enumeration + ******************************************************************************/ +typedef enum en_qspi_spi_protocol +{ + QspiProtocolExtendSpi = 0u, ///< Extend spi protocol + QspiProtocolTwoWiresSpi = 1u, ///< Two wires spi protocol + QspiProtocolFourWiresSpi = 2u, ///< Four wires spi protocol +} en_qspi_spi_protocol_t; + +/** + ******************************************************************************* + ** \brief QSPI spi Mode enumeration + ******************************************************************************/ +typedef enum en_qspi_spi_mode +{ + QspiSpiMode0 = 0u, ///< Spi mode 0(QSCK normalcy is Low level) + QspiSpiMode3 = 1u, ///< Spi mode 3(QSCK normalcy is High level) +} en_qspi_spi_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI bus communication mode enumeration + ******************************************************************************/ +typedef enum en_qspi_bus_mode +{ + QspiBusModeRomAccess = 0u, ///< Rom access mode + QspiBusModeDirectAccess = 1u, ///< Direct communication mode +} en_qspi_bus_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI prefetch data stop config enumeration + ******************************************************************************/ +typedef enum en_qspi_prefetch_config +{ + QspiPrefetchStopComplete = 0u, ///< Stop after prefetch data complete + QspiPrefetchStopImmediately = 1u, ///< Immediately stop prefetch +} en_qspi_prefetch_config_t; + +/** + ******************************************************************************* + ** \brief QSPI read mode enumeration + ******************************************************************************/ +typedef enum en_qspi_read_mode +{ + QspiReadModeStandard = 0u, ///< Standard read + QspiReadModeFast = 1u, ///< Fast read + QspiReadModeTwoWiresOutput = 2u, ///< Two wires output fast read + QspiReadModeTwoWiresIO = 3u, ///< Two wires input/output fast read + QspiReadModeFourWiresOutput = 4u, ///< Four wires output fast read + QspiReadModeFourWiresIO = 5u, ///< Four wires input/output fast read + QspiReadModeCustomStandard = 6u, ///< Custom standard read + QspiReadModeCustomFast = 7u, ///< Custom fast read +} en_qspi_read_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN valid extend time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_valid_extend_time +{ + QspiQssnValidExtendNot = 0u, ///< Don't extend QSSN valid time + QspiQssnValidExtendSck32 = 1u, ///< QSSN valid time extend 32 QSCK cycles + QspiQssnValidExtendSck128 = 2u, ///< QSSN valid time extend 138 QSCK cycles + QspiQssnValidExtendSckEver = 3u, ///< QSSN valid time extend to ever +} en_qspi_qssn_valid_extend_time_t; + +/** + ******************************************************************************* + ** \brief QSPI QSCK duty cycle correction enumeration + ******************************************************************************/ +typedef enum en_qspi_qsck_duty_correction +{ + QspiQsckDutyCorrNot = 0u, ///< Don't correction duty cycle + QspiQsckDutyCorrHalfHclk = 1u, ///< QSCK's rising edge delay 0.5 HCLK cycle when Qsck select HCLK is odd +} en_qspi_qsck_duty_correction_t; + +/** + ******************************************************************************* + ** \brief QSPI WP Pin output level enumeration + ******************************************************************************/ +typedef enum en_qspi_wp_pin_level +{ + QspiWpPinOutputLow = 0u, ///< WP pin(QIO2) output low level + QspiWpPinOutputHigh = 1u, ///< WP pin(QIO2) output high level +} en_qspi_wp_pin_level_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN setup delay time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_setup_delay +{ + QspiQssnSetupDelayHalfQsck = 0u, ///< QSSN setup delay 0.5 QSCK output than QSCK first rising edge + QspiQssnSetupDelay1Dot5Qsck = 1u, ///< QSSN setup delay 1.5 QSCK output than QSCK first rising edge +} en_qspi_qssn_setup_delay_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN hold delay time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_hold_delay +{ + QspiQssnHoldDelayHalfQsck = 0u, ///< QSSN hold delay 0.5 QSCK release than QSCK last rising edge + QspiQssnHoldDelay1Dot5Qsck = 1u, ///< QSSN hold delay 1.5 QSCK release than QSCK last rising edge +} en_qspi_qssn_hold_delay_t; + +/** + ******************************************************************************* + ** \brief QSPI address width enumeration + ******************************************************************************/ +typedef enum en_qspi_addr_width +{ + QspiAddressByteOne = 0u, ///< One byte address + QspiAddressByteTwo = 1u, ///< Two byte address + QspiAddressByteThree = 2u, ///< Three byte address + QspiAddressByteFour = 3u, ///< Four byte address +} en_qspi_addr_width_t; + +/** + ******************************************************************************* + ** \brief QSPI flag type enumeration + ******************************************************************************/ +typedef enum en_qspi_flag_type +{ + QspiFlagBusBusy = 0u, ///< QSPI bus work status flag in direct communication mode + QspiFlagXipMode = 1u, ///< XIP mode status signal + QspiFlagRomAccessError = 2u, ///< Trigger rom access error flag in direct communication mode + QspiFlagPrefetchBufferFull = 3u, ///< Prefetch buffer area status signal + QspiFlagPrefetchStop = 4u, ///< Prefetch action status signal +} en_qspi_flag_type_t; + +/** + ******************************************************************************* + ** \brief QSPI clock division enumeration + ******************************************************************************/ +typedef enum en_qspi_clk_div +{ + QspiHclkDiv2 = 0u, ///< Clock source: HCLK/2 + QspiHclkDiv3 = 2u, ///< Clock source: HCLK/3 + QspiHclkDiv4 = 3u, ///< Clock source: HCLK/4 + QspiHclkDiv5 = 4u, ///< Clock source: HCLK/5 + QspiHclkDiv6 = 5u, ///< Clock source: HCLK/6 + QspiHclkDiv7 = 6u, ///< Clock source: HCLK/7 + QspiHclkDiv8 = 7u, ///< Clock source: HCLK/8 + QspiHclkDiv9 = 8u, ///< Clock source: HCLK/9 + QspiHclkDiv10 = 9u, ///< Clock source: HCLK/10 + QspiHclkDiv11 = 10u, ///< Clock source: HCLK/11 + QspiHclkDiv12 = 11u, ///< Clock source: HCLK/12 + QspiHclkDiv13 = 12u, ///< Clock source: HCLK/13 + QspiHclkDiv14 = 13u, ///< Clock source: HCLK/14 + QspiHclkDiv15 = 14u, ///< Clock source: HCLK/15 + QspiHclkDiv16 = 15u, ///< Clock source: HCLK/16 + QspiHclkDiv17 = 16u, ///< Clock source: HCLK/17 + QspiHclkDiv18 = 17u, ///< Clock source: HCLK/18 + QspiHclkDiv19 = 18u, ///< Clock source: HCLK/19 + QspiHclkDiv20 = 19u, ///< Clock source: HCLK/20 + QspiHclkDiv21 = 20u, ///< Clock source: HCLK/21 + QspiHclkDiv22 = 21u, ///< Clock source: HCLK/22 + QspiHclkDiv23 = 22u, ///< Clock source: HCLK/23 + QspiHclkDiv24 = 23u, ///< Clock source: HCLK/24 + QspiHclkDiv25 = 24u, ///< Clock source: HCLK/25 + QspiHclkDiv26 = 25u, ///< Clock source: HCLK/26 + QspiHclkDiv27 = 26u, ///< Clock source: HCLK/27 + QspiHclkDiv28 = 27u, ///< Clock source: HCLK/28 + QspiHclkDiv29 = 28u, ///< Clock source: HCLK/29 + QspiHclkDiv30 = 29u, ///< Clock source: HCLK/30 + QspiHclkDiv31 = 30u, ///< Clock source: HCLK/31 + QspiHclkDiv32 = 31u, ///< Clock source: HCLK/32 + QspiHclkDiv33 = 32u, ///< Clock source: HCLK/33 + QspiHclkDiv34 = 33u, ///< Clock source: HCLK/34 + QspiHclkDiv35 = 34u, ///< Clock source: HCLK/35 + QspiHclkDiv36 = 35u, ///< Clock source: HCLK/36 + QspiHclkDiv37 = 36u, ///< Clock source: HCLK/37 + QspiHclkDiv38 = 37u, ///< Clock source: HCLK/38 + QspiHclkDiv39 = 38u, ///< Clock source: HCLK/39 + QspiHclkDiv40 = 39u, ///< Clock source: HCLK/40 + QspiHclkDiv41 = 40u, ///< Clock source: HCLK/41 + QspiHclkDiv42 = 41u, ///< Clock source: HCLK/42 + QspiHclkDiv43 = 42u, ///< Clock source: HCLK/43 + QspiHclkDiv44 = 43u, ///< Clock source: HCLK/44 + QspiHclkDiv45 = 44u, ///< Clock source: HCLK/45 + QspiHclkDiv46 = 45u, ///< Clock source: HCLK/46 + QspiHclkDiv47 = 46u, ///< Clock source: HCLK/47 + QspiHclkDiv48 = 47u, ///< Clock source: HCLK/48 + QspiHclkDiv49 = 48u, ///< Clock source: HCLK/49 + QspiHclkDiv50 = 49u, ///< Clock source: HCLK/50 + QspiHclkDiv51 = 50u, ///< Clock source: HCLK/51 + QspiHclkDiv52 = 51u, ///< Clock source: HCLK/52 + QspiHclkDiv53 = 52u, ///< Clock source: HCLK/53 + QspiHclkDiv54 = 53u, ///< Clock source: HCLK/54 + QspiHclkDiv55 = 54u, ///< Clock source: HCLK/55 + QspiHclkDiv56 = 55u, ///< Clock source: HCLK/56 + QspiHclkDiv57 = 56u, ///< Clock source: HCLK/57 + QspiHclkDiv58 = 57u, ///< Clock source: HCLK/58 + QspiHclkDiv59 = 58u, ///< Clock source: HCLK/59 + QspiHclkDiv60 = 59u, ///< Clock source: HCLK/60 + QspiHclkDiv61 = 60u, ///< Clock source: HCLK/61 + QspiHclkDiv62 = 61u, ///< Clock source: HCLK/62 + QspiHclkDiv63 = 62u, ///< Clock source: HCLK/63 + QspiHclkDiv64 = 63u, ///< Clock source: HCLK/64 +} en_qspi_clk_div_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN minimum interval time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_interval_time +{ + QspiQssnIntervalQsck1 = 0u, ///< QSSN signal min interval time 1 QSCK + QspiQssnIntervalQsck2 = 1u, ///< QSSN signal min interval time 2 QSCK + QspiQssnIntervalQsck3 = 2u, ///< QSSN signal min interval time 3 QSCK + QspiQssnIntervalQsck4 = 3u, ///< QSSN signal min interval time 4 QSCK + QspiQssnIntervalQsck5 = 4u, ///< QSSN signal min interval time 5 QSCK + QspiQssnIntervalQsck6 = 5u, ///< QSSN signal min interval time 6 QSCK + QspiQssnIntervalQsck7 = 6u, ///< QSSN signal min interval time 7 QSCK + QspiQssnIntervalQsck8 = 7u, ///< QSSN signal min interval time 8 QSCK + QspiQssnIntervalQsck9 = 8u, ///< QSSN signal min interval time 9 QSCK + QspiQssnIntervalQsck10 = 9u, ///< QSSN signal min interval time 10 QSCK + QspiQssnIntervalQsck11 = 10u, ///< QSSN signal min interval time 11 QSCK + QspiQssnIntervalQsck12 = 11u, ///< QSSN signal min interval time 12 QSCK + QspiQssnIntervalQsck13 = 12u, ///< QSSN signal min interval time 13 QSCK + QspiQssnIntervalQsck14 = 13u, ///< QSSN signal min interval time 14 QSCK + QspiQssnIntervalQsck15 = 14u, ///< QSSN signal min interval time 15 QSCK + QspiQssnIntervalQsck16 = 15u, ///< QSSN signal min interval time 16 QSCK +} en_qspi_qssn_interval_time_t; + +/** + ******************************************************************************* + ** \brief QSPI virtual period enumeration + ******************************************************************************/ +typedef enum en_qspi_virtual_period +{ + QspiVirtualPeriodQsck3 = 0u, ///< Virtual period select 3 QSCK + QspiVirtualPeriodQsck4 = 1u, ///< Virtual period select 4 QSCK + QspiVirtualPeriodQsck5 = 2u, ///< Virtual period select 5 QSCK + QspiVirtualPeriodQsck6 = 3u, ///< Virtual period select 6 QSCK + QspiVirtualPeriodQsck7 = 4u, ///< Virtual period select 7 QSCK + QspiVirtualPeriodQsck8 = 5u, ///< Virtual period select 8 QSCK + QspiVirtualPeriodQsck9 = 6u, ///< Virtual period select 9 QSCK + QspiVirtualPeriodQsck10 = 7u, ///< Virtual period select 10 QSCK + QspiVirtualPeriodQsck11 = 8u, ///< Virtual period select 11 QSCK + QspiVirtualPeriodQsck12 = 9u, ///< Virtual period select 12 QSCK + QspiVirtualPeriodQsck13 = 10u, ///< Virtual period select 13 QSCK + QspiVirtualPeriodQsck14 = 11u, ///< Virtual period select 14 QSCK + QspiVirtualPeriodQsck15 = 12u, ///< Virtual period select 15 QSCK + QspiVirtualPeriodQsck16 = 13u, ///< Virtual period select 16 QSCK + QspiVirtualPeriodQsck17 = 14u, ///< Virtual period select 17 QSCK + QspiVirtualPeriodQsck18 = 15u, ///< Virtual period select 18 QSCK +} en_qspi_virtual_period_t; + +/** + ******************************************************************************* + ** \brief QSPI communication protocol structure definition + ******************************************************************************/ +typedef struct stc_qspi_comm_protocol +{ + en_qspi_spi_protocol_t enReceProtocol; ///< Receive data stage SPI protocol + en_qspi_spi_protocol_t enTransAddrProtocol; ///< Transmit address stage SPI protocol + en_qspi_spi_protocol_t enTransInstrProtocol; ///< Transmit instruction stage SPI protocol + en_qspi_read_mode_t enReadMode; ///< Serial interface read mode +} stc_qspi_comm_protocol_t; + +/** + ******************************************************************************* + ** \brief QSPI init structure definition + ******************************************************************************/ +typedef struct stc_qspi_init +{ + en_qspi_clk_div_t enClkDiv; ///< Clock division + en_qspi_spi_mode_t enSpiMode; ///< Specifies SPI mode + en_qspi_bus_mode_t enBusCommMode; ///< Bus communication mode + en_qspi_prefetch_config_t enPrefetchMode; ///< Config prefetch stop location + en_functional_state_t enPrefetchFuncEn; ///< Disable: disable prefetch function, Enable: enable prefetch function + stc_qspi_comm_protocol_t stcCommProtocol; ///< Qspi communication protocol config + en_qspi_qssn_valid_extend_time_t enQssnValidExtendTime; ///< QSSN valid extend time function select after QSPI access bus + en_qspi_qssn_interval_time_t enQssnIntervalTime; ///< QSSN minimum interval time + en_qspi_qsck_duty_correction_t enQsckDutyCorr; ///< QSCK output duty cycles correction + en_qspi_virtual_period_t enVirtualPeriod; ///< Virtual period config + en_qspi_wp_pin_level_t enWpPinLevel; ///< WP pin(QIO2) level select + en_qspi_qssn_setup_delay_t enQssnSetupDelayTime; ///< QSSN setup delay time choose + en_qspi_qssn_hold_delay_t enQssnHoldDelayTime; ///< QSSN hold delay time choose + en_functional_state_t enFourByteAddrReadEn; ///< Read instruction code select when set address width is four bytes + en_qspi_addr_width_t enAddrWidth; ///< Serial interface address width choose + uint8_t u8RomAccessInstr; ///< Rom access mode instruction +} stc_qspi_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< 4-byte instruction mode using instruction set */ +#define QSPI_4BINSTR_STANDARD_READ 0x13u +#define QSPI_4BINSTR_FAST_READ 0x0Cu +#define QSPI_4BINSTR_TWO_WIRES_OUTPUT_READ 0x3Cu +#define QSPI_4BINSTR_TWO_WIRES_IO_READ 0xBCu +#define QSPI_4BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Cu +#define QSPI_4BINSTR_FOUR_WIRES_IO_READ 0xECu +#define QSPI_4BINSTR_EXIT_4BINSTR_MODE 0xB7u + +/*!< 3-byte instruction mode using instruction set */ +#define QSPI_3BINSTR_STANDARD_READ 0x03u +#define QSPI_3BINSTR_FAST_READ 0x0Bu +#define QSPI_3BINSTR_TWO_WIRES_OUTPUT_READ 0x3Bu +#define QSPI_3BINSTR_TWO_WIRES_IO_READ 0xBBu +#define QSPI_3BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Bu +#define QSPI_3BINSTR_FOUR_WIRES_IO_READ 0xEBu +#define QSPI_3BINSTR_ENTER_4BINSTR_MODE 0xE9u + +/*!< General instruction set */ +#define QSPI_WRITE_MODE_ENABLE 0x06u + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t QSPI_DeInit(void); +en_result_t QSPI_Init(const stc_qspi_init_t *pstcQspiInitCfg); +en_result_t QSPI_SetAddrWidth(en_qspi_addr_width_t enAddrWidth); +en_result_t QSPI_SetExtendAddress(uint8_t u8Addr); +en_result_t QSPI_CommProtocolConfig(const stc_qspi_comm_protocol_t *pstcCommProtocol); +en_result_t QSPI_PrefetchCmd(en_functional_state_t enNewSta); +en_result_t QSPI_SetClockDiv(en_qspi_clk_div_t enClkDiv); +en_result_t QSPI_SetWPPinLevel(en_qspi_wp_pin_level_t enWpLevel); + +/* Rom access mode functions */ +en_result_t QSPI_SetRomAccessInstruct(uint8_t u8Instr); +en_result_t QSPI_XipModeCmd(uint8_t u8Instr, en_functional_state_t enNewSta); + +/* Direct communication mode functions */ +en_result_t QSPI_WriteDirectCommValue(uint8_t u8Val); +uint8_t QSPI_ReadDirectCommValue(void); +en_result_t QSPI_EnterDirectCommMode(void); +en_result_t QSPI_ExitDirectCommMode(void); + +/* Flags and get buffer functions */ +uint8_t QSPI_GetPrefetchBufferNum(void); +en_flag_status_t QSPI_GetFlag(en_qspi_flag_type_t enFlag); +en_result_t QSPI_ClearFlag(en_qspi_flag_type_t enFlag); + +//@} // QspiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_QSPI_ENABLE */ + +#endif /* __HC32F460_QSPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_rmu.h b/driver/inc/hc32f460_rmu.h new file mode 100644 index 0000000..1217490 --- /dev/null +++ b/driver/inc/hc32f460_rmu.h @@ -0,0 +1,96 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rmu.h + ** + ** A detailed description is available at + ** @link RmuGroup RMU description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of RMU + ** + ******************************************************************************/ +#ifndef __HC32F460_RMU_H__ +#define __HC32F460_RMU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_RMU_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup RmuGroup Reset Management Unit(RMU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief system reset cause flag + ** + ******************************************************************************/ +typedef struct stc_rmu_rstcause +{ + en_flag_status_t enMultiRst; ///< Multiply reset cause + en_flag_status_t enXtalErr; ///< Xtal error reset + en_flag_status_t enClkFreqErr; ///< Clk freqence error reset + en_flag_status_t enRamEcc; ///< Ram ECC reset + en_flag_status_t enRamParityErr; ///< Ram parity error reset + en_flag_status_t enMpuErr; ///< Mpu error reset + en_flag_status_t enSoftware; ///< Software reset + en_flag_status_t enPowerDown; ///< Power down reset + en_flag_status_t enSwdt; ///< Special watchdog timer reset + en_flag_status_t enWdt; ///< Watchdog timer reset + en_flag_status_t enPvd2; ///< Program voltage Dectection 2 reset + en_flag_status_t enPvd1; ///< Program voltage Dectection 1 reset + en_flag_status_t enBrownOut; ///< Brown out reset + en_flag_status_t enRstPin; ///< Reset pin reset + en_flag_status_t enPowerOn; ///< Power on reset +}stc_rmu_rstcause_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t RMU_GetResetCause(stc_rmu_rstcause_t *pstcData); +en_result_t RMU_ClrResetFlag(void); + +//@} // RmuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_RMU_ENABLE */ + +#endif /* __HC32F460_RMU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/inc/hc32f460_rtc.h b/driver/inc/hc32f460_rtc.h new file mode 100644 index 0000000..31544f0 --- /dev/null +++ b/driver/inc/hc32f460_rtc.h @@ -0,0 +1,274 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rtc.h + ** + ** A detailed description is available at + ** @link RtcGroup Real-Time Clock description @endlink + ** + ** - 2018-11-22 CDT First version for Device Driver Library of RTC. + ** + ******************************************************************************/ +#ifndef __HC32F460_RTC_H__ +#define __HC32F460_RTC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_RTC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup RtcGroup Real-Time Clock(RTC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief RTC period interrupt type enumeration + ******************************************************************************/ +typedef enum en_rtc_period_int_type +{ + RtcPeriodIntInvalid = 0u, ///< Period interrupt invalid + RtcPeriodIntHalfSec = 1u, ///< 0.5 second period interrupt + RtcPeriodIntOneSec = 2u, ///< 1 second period interrupt + RtcPeriodIntOneMin = 3u, ///< 1 minute period interrupt + RtcPeriodIntOneHour = 4u, ///< 1 hour period interrupt + RtcPeriodIntOneDay = 5u, ///< 1 day period interrupt + RtcPeriodIntOneMon = 6u ///< 1 month period interrupt +} en_rtc_period_int_type_t; + +/** + ******************************************************************************* + ** \brief RTC time format enumeration + ******************************************************************************/ +typedef enum en_rtc_time_format +{ + RtcTimeFormat12Hour = 0u, ///< 12 hours mode + RtcTimeFormat24Hour = 1u, ///< 24 hours mode +} en_rtc_time_format_t; + +/** + ******************************************************************************* + ** \brief RTC 1Hz output compensation way enumeration + ******************************************************************************/ +typedef enum en_rtc_output_compen +{ + RtcOutputCompenDistributed = 0u, ///< Distributed compensation 1hz output + RtcOutputCompenUniform = 1u, ///< Uniform Compensation 1hz output +} en_rtc_output_compen_t; + +/** + ******************************************************************************* + ** \brief RTC work mode enumeration + ******************************************************************************/ +typedef enum en_rtc_work_mode +{ + RtcModeNormalCount = 0u, ///< Normal count mode + RtcModeReadOrWrite = 1u, ///< Read or write mode +} en_rtc_work_mode_t; + +/** + ******************************************************************************* + ** \brief RTC count clock source enumeration + ******************************************************************************/ +typedef enum en_rtc_clk_source +{ + RtcClkXtal32 = 0u, ///< XTAL32 as clock source + RtcClkLrc = 1u, ///< LRC as clock source +} en_rtc_clk_source_t; + +/** + ******************************************************************************* + ** \brief RTC data format enumeration + ******************************************************************************/ +typedef enum en_rtc_data_format +{ + RtcDataFormatDec = 0u, ///< Decimal format + RtcDataFormatBcd = 1u, ///< BCD format +} en_rtc_data_format_t; + +/** + ******************************************************************************* + ** \brief RTC 12 hour AM/PM enumeration + ******************************************************************************/ +typedef enum en_rtc_hour12_ampm +{ + RtcHour12Am = 0u, ///< Ante meridiem + RtcHour12Pm = 1u, ///< Post meridiem +} en_rtc_hour12_ampm_t; + +/** + ******************************************************************************* + ** \brief RTC month enumeration + ******************************************************************************/ +typedef enum en_rtc_month +{ + RtcMonthJanuary = 1u, ///< January + RtcMonthFebruary = 2u, ///< February + RtcMonthMarch = 3u, ///< March + RtcMonthApril = 4u, ///< April + RtcMonthMay = 5u, ///< May + RtcMonthJune = 6u, ///< June + RtcMonthJuly = 7u, ///< July + RtcMonthAugust = 8u, ///< August + RtcMonthSeptember = 9u, ///< September + RtcMonthOctober = 10u, ///< October + RtcMonthNovember = 11u, ///< November + RtcMonthDecember = 12u, ///< December +} en_rtc_month_t; + +/** + ******************************************************************************* + ** \brief RTC weekday enumeration + ******************************************************************************/ +typedef enum en_rtc_weekday +{ + RtcWeekdaySunday = 0u, ///< Sunday + RtcWeekdayMonday = 1u, ///< Monday + RtcWeekdayTuesday = 2u, ///< Tuesday + RtcWeekdayWednesday = 3u, ///< Wednesday + RtcWeekdayThursday = 4u, ///< Thursday + RtcWeekdayFriday = 5u, ///< Friday + RtcWeekdaySaturday = 6u ///< Saturday +} en_rtc_weekday_t; + +/** + ******************************************************************************* + ** \brief RTC alarm weekday enumeration + ******************************************************************************/ +typedef enum en_rtc_alarm_weekday +{ + RtcAlarmWeekdaySunday = 0x01u, ///< Sunday + RtcAlarmWeekdayMonday = 0x02u, ///< Monday + RtcAlarmWeekdayTuesday = 0x04u, ///< Tuesday + RtcAlarmWeekdayWednesday = 0x08u, ///< Wednesday + RtcAlarmWeekdayThursday = 0x10u, ///< Thursday + RtcAlarmWeekdayFriday = 0x20u, ///< Friday + RtcAlarmWeekdaySaturday = 0x40u, ///< Saturday +} en_rtc_alarm_weekday_t; + +/** + ******************************************************************************* + ** \brief RTC interrupt request type enumeration + ******************************************************************************/ +typedef enum en_rtc_irq_type_ +{ + RtcIrqPeriod = 0u, ///< Period count interrupt request + RtcIrqAlarm = 1u, ///< Alarm interrupt request +} en_rtc_irq_type_t; + +/** + ******************************************************************************* + ** \brief RTC date and time structure definition + ******************************************************************************/ +typedef struct stc_rtc_date_time +{ + uint8_t u8Year; ///< Year (range 0-99) + uint8_t u8Month; ///< Month (range 1-12) + uint8_t u8Day; ///< Day (range 1-31) + uint8_t u8Hour; ///< Hours (range 1-12 when 12 hour format; range 0-23 when 24 hour format) + uint8_t u8Minute; ///< Minutes (range 0-59) + uint8_t u8Second; ///< Seconds (range 0-59) + uint8_t u8Weekday; ///< Weekday (range 0-6) + en_rtc_hour12_ampm_t enAmPm; ///< The value is valid when 12-hour format +} stc_rtc_date_time_t; + +/** + ******************************************************************************* + ** \brief RTC alarm time structure definition + ******************************************************************************/ +typedef struct stc_rtc_alarm_time +{ + uint8_t u8Minute; ///< Minutes (range 0-59) + uint8_t u8Hour; ///< Hours (range 1-12 when 12 hour format; range 0-23 when 24 hour format) + uint8_t u8Weekday; ///< Weekday (range RtcAlarmWeekdaySunday to RtcAlarmWeekdaySaturday) + en_rtc_hour12_ampm_t enAmPm; ///< The value is valid when 12-hour format +} stc_rtc_alarm_time_t; + +/** + ******************************************************************************* + ** \brief RTC init structure definition + ******************************************************************************/ +typedef struct stc_rtc_init +{ + en_rtc_clk_source_t enClkSource; ///< Clock source + en_rtc_period_int_type_t enPeriodInt; ///< Period interrupt condition + en_rtc_time_format_t enTimeFormat; ///< RTC time format + en_rtc_output_compen_t enCompenWay; ///< 1HZ output compensation way + uint16_t u16CompenVal; ///< Clock error compensation value + en_functional_state_t enCompenEn; ///< Enable/Disable clock error compensation +} stc_rtc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t RTC_DeInit(void); +en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit); +en_result_t RTC_Cmd(en_functional_state_t enNewSta); +en_result_t RTC_EnterRwMode(void); +en_result_t RTC_ExitRwMode(void); + +/* Extend functions */ +en_result_t RTC_PeriodIntConfig(en_rtc_period_int_type_t enIntType); +en_result_t RTC_LowPowerSwitch(void); +en_result_t RTC_SetClkCompenValue(uint16_t u16CompenVal); +en_result_t RTC_ClkCompenCmd(en_functional_state_t enNewSta); +en_result_t RTC_OneHzOutputCmd(en_functional_state_t enNewSta); + +/* Date and time functions */ +en_result_t RTC_SetDateTime(en_rtc_data_format_t enFormat, const stc_rtc_date_time_t *pstcRtcDateTime, + en_functional_state_t enUpdateDateEn, en_functional_state_t enUpdateTimeEn); +en_result_t RTC_GetDateTime(en_rtc_data_format_t enFormat, stc_rtc_date_time_t *pstcRtcDateTime); + +/* Alarm functions */ +en_result_t RTC_SetAlarmTime(en_rtc_data_format_t enFormat, const stc_rtc_alarm_time_t *pstcRtcAlarmTime); +en_result_t RTC_GetAlarmTime(en_rtc_data_format_t enFormat, stc_rtc_alarm_time_t *pstcRtcAlarmTime); +en_result_t RTC_AlarmCmd(en_functional_state_t enNewSta); + +/* Interrupt and flags management functions ******************************************/ +en_result_t RTC_IrqCmd(en_rtc_irq_type_t enIrq, en_functional_state_t enNewSta); +en_flag_status_t RTC_GetAlarmFlag(void); +en_result_t RTC_ClearAlarmFlag(void); + +//@} // RtcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_RTC_ENABLE */ + +#endif /* __HC32F460_RTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_sdioc.h b/driver/inc/hc32f460_sdioc.h new file mode 100644 index 0000000..2fd546a --- /dev/null +++ b/driver/inc/hc32f460_sdioc.h @@ -0,0 +1,559 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sdioc.h + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-11 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ +#ifndef __HC32F460_SDIOC_H__ +#define __HC32F460_SDIOC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SDIOC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SdiocGroup Secure Digital Input and Output Controller(SDIOC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SDIOC mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_mode +{ + SdiocModeSD = 0u, ///< The SD mode + SdiocModeMMC = 1u, ///< The MMC mode +} en_sdioc_mode_t; + +/** + ******************************************************************************* + ** \brief SDIOC transfer bus width enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_bus_width +{ + SdiocBusWidth4Bit = 0u, ///< The SDIOC bus width 4 bit + SdiocBusWidth8Bit = 1u, ///< The SDIOC bus width 8 bit + SdiocBusWidth1Bit = 2u, ///< The SDIOC bus width 1 bit +} en_sdioc_bus_width_t; + +/** + ******************************************************************************* + ** \brief SDIOC clock division enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_clk_div +{ + SdiocClkDiv_1 = 0x00u, ///< EXCLK/1 + SdiocClkDiv_2 = 0x01u, ///< EXCLK/2 + SdiocClkDiv_4 = 0x02u, ///< EXCLK/4 + SdiocClkDiv_8 = 0x04u, ///< EXCLK/8 + SdiocClkDiv_16 = 0x08u, ///< EXCLK/16 + SdiocClkDiv_32 = 0x10u, ///< EXCLK/32 + SdiocClkDiv_64 = 0x20u, ///< EXCLK/64 + SdiocClkDiv_128 = 0x40u, ///< EXCLK/128 + SdiocClkDiv_256 = 0x80u, ///< EXCLK/256 +} en_sdioc_clk_div_t; + +/** + ******************************************************************************* + ** \brief SDIOC response type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_type +{ + SdiocResponseNoneBit = 0u, ///< No Response + SdiocResponse136Bit = 1u, ///< Response Length 136 + SdiocResponse48Bit = 2u, ///< Response Length 48 + SdiocResponse48BitCheckBusy = 3u, ///< Response Length 48 check Busy after response +} en_sdioc_response_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC response index enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_index +{ + SdiocCmdNoRsp = 0u, ///< No Response + SdiocCmdRspR1 = 1u, ///< Command Response 1 + SdiocCmdRspR1b = 2u, ///< Command Response 1 with busy + SdiocCmdRspR2 = 3u, ///< Command Response 2 + SdiocCmdRspR3 = 4u, ///< Command Response 3 + SdiocCmdRspR4 = 5u, ///< Command Response 4 + SdiocCmdRspR5 = 6u, ///< Command Response 5 + SdiocCmdRspR5b = 7u, ///< Command Response 5 with busy + SdiocCmdRspR6 = 8u, ///< Command Response 6 + SdiocCmdRspR7 = 9u, ///< Command Response 7 +} en_sdioc_response_index_t; + +/** + ******************************************************************************* + ** \brief SDIOC command type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_cmd_type +{ + SdiocCmdNormal = 0u, ///< Other commands + SdiocCmdSuspend = 1u, ///< CMD52 for writing "Bus Suspend" in CCCR + SdiocCmdResume = 2u, ///< CMD52 for writing "Function Select" in CCCR + SdiocCmdAbort = 3u, ///< CMD12, CMD52 for writing "I/O Abort" in CCCR +} en_sdioc_cmd_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC data transfer direction enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_transfer_dir +{ + SdiocTransferToCard = 0u, ///< Write (Host to Card) + SdiocTransferToHost = 1u, ///< Read (Card to Host) +} en_sdioc_transfer_dir_t; + +/** + ******************************************************************************* + ** \brief SDIOC data transfer mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_transfer_mode +{ + SdiocTransferSingle = 0u, ///< Single Block transfer + SdiocTransferInfinite = 1u, ///< Infinite Block transfer + SdiocTransferMultiple = 2u, ///< Multiple Block transfer + SdiocTransferStopMultiple = 3u, ///< Stop Multiple Block transfer +} en_sdioc_transfer_mode_t; + +/** + ******************************************************************************* + ** \brief SD data timeout time enumeration + ** + ******************************************************************************/ +typedef enum en_sd_data_timeout +{ + SdiocDtoSdclk_2_13 = 0u, ///< Timeout time: SDCLK*2^13 + SdiocDtoSdclk_2_14 = 1u, ///< Timeout time: SDCLK*2^14 + SdiocDtoSdclk_2_15 = 2u, ///< Timeout time: SDCLK*2^15 + SdiocDtoSdclk_2_16 = 3u, ///< Timeout time: SDCLK*2^16 + SdiocDtoSdclk_2_17 = 4u, ///< Timeout time: SDCLK*2^17 + SdiocDtoSdclk_2_18 = 5u, ///< Timeout time: SDCLK*2^18 + SdiocDtoSdclk_2_19 = 6u, ///< Timeout time: SDCLK*2^19 + SdiocDtoSdclk_2_20 = 7u, ///< Timeout time: SDCLK*2^20 + SdiocDtoSdclk_2_21 = 8u, ///< Timeout time: SDCLK*2^21 + SdiocDtoSdclk_2_22 = 9u, ///< Timeout time: SDCLK*2^22 + SdiocDtoSdclk_2_23 = 10u, ///< Timeout time: SDCLK*2^23 + SdiocDtoSdclk_2_24 = 11u, ///< Timeout time: SDCLK*2^24 + SdiocDtoSdclk_2_25 = 12u, ///< Timeout time: SDCLK*2^25 + SdiocDtoSdclk_2_26 = 13u, ///< Timeout time: SDCLK*2^26 + SdiocDtoSdclk_2_27 = 14u, ///< Timeout time: SDCLK*2^27 +} en_sdioc_data_timeout_t; + +/** + ******************************************************************************* + ** \brief SDIOC dat line type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_dat_line_type +{ + SdiocDat0Line = 0u, ///< DAT0 Line + SdiocDat1Line = 1u, ///< DAT1 Line + SdiocDat2Line = 2u, ///< DAT2 Line + SdiocDat3Line = 3u, ///< DAT3 Line +} en_sdioc_dat_line_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC software reset type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_sw_reset +{ + SdiocSwResetDatLine = 0u, ///< Only part of data circuit is reset. + SdiocSwResetCmdLine = 1u, ///< Only part of command circuit is reset. + SdiocSwResetAll = 2u, ///< Reset the entire Host Controller except for the card detection circuit. +} en_sdioc_sw_reset_t; + +/** + ******************************************************************************* + ** \brief SDIOC host status enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_host_status +{ + SdiocCommandInhibitCmd = (1u << 0), ///< Command Inhibit(CMD). 1: Cannot issue command; 0:Can issue command using only CMD line + SdiocCommandInhibitData = (1u << 1), ///< Command Inhibit(DAT). 1: Cannot issue command which uses the DAT line; 0:Can issue command which uses the DAT line + SdiocDataLineActive = (1u << 2), ///< 1: DAT Line Active; 0: DAT Line Inactive + SdiocWriteTransferActive = (1u << 8), ///< Write Transfer Active.1: Transferring data; 0: No valid data + SdiocReadTransferActive = (1u << 9), ///< Read Transfer Active.1: Transferring data; 0: No valid data + SdiocBufferWriteEnble = (1u << 10), ///< 1: Write enable; 0: Write Disable + SdiocBufferReadEnble = (1u << 11), ///< 1: Read enable; 0: Read Disable + SdiocCardInserted = (1u << 16), ///< 1: Card Inserted; 0: Reset or Debouncing or No Card + SdiocCardStateStable = (1u << 17), ///< 1: No Card or Inserted; 0: Reset or Debouncing + SdiocCardDetectPinLvl = (1u << 18), ///< 1: Card present; 0: No card present + SdiocWriteProtectPinLvl = (1u << 19), ///< 1: Write enabled; 0: Write protected + SdiocData0PinLvl = (1u << 20), ///< 1: DAT0 line signal level high; 0: DAT0 line signal level low + SdiocData1PinLvl = (1u << 21), ///< 1: DAT1 line signal level high; 0: DAT1 line signal level low + SdiocData2PinLvl = (1u << 22), ///< 1: DAT2 line signal level high; 0: DAT2 line signal level low + SdiocData3PinLvl = (1u << 23), ///< 1: DAT3 line signal level high; 0: DAT3 line signal level low + SdiocCmdPinLvl = (1u << 24), ///< 1: CMD line signal level high; 0: CMD line signal level low +} en_sdioc_host_status_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_nor_int_sel +{ + SdiocCommandComplete = (1u << 0), ///< Command Complete. 1: Command complete; 0:No command complete + SdiocTransferComplete = (1u << 1), ///< Transfer Complete. 1: Data transfer complete; 0:No transfer complete + SdiocBlockGapEvent = (1u << 2), ///< Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + SdiocBufferWriteReady = (1u << 4), ///< Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + SdiocBufferReadReady = (1u << 5), ///< Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + SdiocCardInsertedInt = (1u << 6), ///< Write Transfer Active.1: Transferring data; 0: No valid data + SdiocCardRemoval = (1u << 7), ///< Card Removal. 1: Card removed; 0: Card state stable or Debouncing + SdiocCardInt = (1u << 8), ///< Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + SdiocErrorInt = (1u << 15), ///< Error Interrupt. 1: Error; 0: No Error +} en_sdioc_nor_int_sel_t, en_sdioc_nor_int_flag_t; + +/** + ******************************************************************************* + ** \brief SDIOC error interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_err_int_sel +{ + SdiocCmdTimeoutErr = (1u << 0), ///< Command Timeout Error. 1: Timer out; 0:No Error + SdiocCmdCrcErr = (1u << 1), ///< Command CRC Error. 1: Command CRC Error Generated; 0:No Error + SdiocCmdEndBitErr = (1u << 2), ///< Command End Bit Error. 1: End Bit Error Generated; 0:No Error + SdiocCmdIndexErr = (1u << 3), ///< Command Index Error. 1: Command Index Error Generatedr; 0:No Error + SdiocDataTimeoutErr = (1u << 4), ///< Data Timeout Error. 1: Timer out; 0:No Error + SdiocDataCrcErr = (1u << 5), ///< Data CRC Error. 1: Data CRC Error Generated; 0:No Error + SdiocDataEndBitErr = (1u << 6), ///< Data End Bit Error. 1: End Bit Error Generated; 0:No Error + SdiocAutoCmd12Err = (1u << 8), ///< Auto CMD12 Error. 1: Error; 0:No Error +} en_sdioc_err_int_sel_t, en_sdioc_err_int_flag_t; + +/** + ******************************************************************************* + ** \brief SDIOC auto CMD12 error status enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_atuo_cmd_err_status +{ + SdiocAutoCmd12NotExecuted = (1u << 0), ///< Auto CMD12 Not Executed. 1: Not executed; 0:Executed + SdiocAutoCmd12Timeout = (1u << 1), ///< Auto CMD12 Timeout Error. 1: Time out; 0:No error + SdiocAutoCmd12CrcErr = (1u << 2), ///< Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + SdiocAutoCmd12EndBitErr = (1u << 3), ///< Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + SdiocAutoCmd12IndexErr = (1u << 4), ///< Auto CMD12 Index Error. 1: Error; 0: No error + SdiocCmdNotIssuedErr = (1u << 7), ///< Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error +} en_sdioc_atuo_cmd_err_sel_t, en_sdioc_atuo_cmd_err_status_t; + +/** + ******************************************************************************* + ** \brief SDIOC speed mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_speed_mode +{ + SdiocNormalSpeedMode = 0u, ///< Normal speed mode + SdiocHighSpeedMode = 1u, ///< High speed mode +} en_sdioc_speed_mode_t; + +/** + ******************************************************************************* + ** \brief SDIOC response register enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_reg +{ + SdiocRegResp01 = 0x00u, ///< Response 0/1 Register + SdiocRegResp23 = 0x04u, ///< Response 2/3 Register + SdiocRegResp45 = 0x08u, ///< Response 4/5 Register + SdiocRegResp67 = 0x0Cu, ///< Response 5/6 Register +} en_sdioc_response_reg_t; + +/** + ****************************************************************************** + ** \brief SDIOC output clock frequency enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_clk_freq +{ + SdiocClk400K = 400000u, ///< SDIOC clock: 40KHz + SdiocClk20M = 20000000u, ///< SDIOC clock: 20MHz + SdiocClk25M = 25000000u, ///< SDIOC clock: 25MHz + SdiocClk40M = 40000000u, ///< SDIOC clock: 40MHz + SdiocClk50M = 50000000u, ///< SDIOC clock: 50MHz +} en_sdioc_clk_freq_t; + +/** + ****************************************************************************** + ** \brief SDIOC detect the source of card enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_detect_signal +{ + SdiocSdcdPinLevel = 0u, ///< SDCD# is selected (for normal use) + SdiocCardDetectTestLevel = 1u, ///< The Card Detect Test Level is selected(for test purpose) +} en_sdioc_detect_signal_t; + +/** + ******************************************************************************* + ** \brief SDIOC Command configure structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_cmd_cfg +{ + uint8_t u8CmdIndex; ///< Command index + + uint32_t u32Argument; ///< The argument of command + + en_sdioc_cmd_type_t enCmdType; ///< Command type + + en_sdioc_response_index_t enRspIndex; ///< Response index, refer @ref en_sdioc_response_index_t for details + + en_functional_state_t enDataPresentEnable; ///< Enable: Data is present and shall be transferred using the DAT line, Disable: Commands using only CMD line +} stc_sdioc_cmd_cfg_t; + +/** + ******************************************************************************* + ** \brief SDIOC Data configure structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_data_cfg +{ + uint16_t u16BlkSize; ///< Block size + + uint16_t u16BlkCnt; ///< Block count + + en_functional_state_t enAutoCmd12Enable; ///< Enable: Auto CMD12 enable, Disable: Auto CMD12 disable + + en_sdioc_transfer_dir_t enTransferDir; ///< Specifies the data transfer direction of the SDIOC controller. + ///< This parameter can be a value of @ref en_sdioc_transfer_dir_t. + + en_sdioc_data_timeout_t enDataTimeOut; ///< Specifies the data timeout period in card bus clock periods. + ///< This parameter can be a value of @ref en_sdioc_data_timeout_t. + + en_sdioc_transfer_mode_t enTransferMode; ///< Specifies the data transfer mode of the SDIOC controller. + ///< This parameter can be a value of @ref en_sdioc_transfer_mode_t. +} stc_sdioc_data_cfg_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt enable structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_normal_irq_en +{ + union + { + uint16_t u16NormalIntsgEn; ///< SDIOC normal interrupt enable + stc_sdioc_errintsgen_field_t stcNormalIntsgEn; ///< SDIOC normal interrupt enable bit-field structure + }; +} stc_sdioc_normal_irq_en_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt enable structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_error_irq_en +{ + union + { + uint16_t u16ErrorIntsgEn; ///< SDIOC error interrupt enable + stc_sdioc_errintsgen_field_t stcErrorIntsgEn; ///< SDIOC error interrupt enable bit-field structure + }; +} stc_sdioc_error_irq_en_t; + +/** + ******************************************************************************* + ** \brief SDIOC error status callback functions + ** + ******************************************************************************/ +typedef struct stc_sdioc_normal_irq_cb +{ + func_ptr_t pfnCommandCompleteIrqCb; ///< Pointer to command complete callback function + + func_ptr_t pfnTransferCompleteIrqCb; ///< Pointer to transfer complete callback function + + func_ptr_t pfnBlockGapIrqCb; ///< Pointer to Block gap callback function + + func_ptr_t pfnBufferWriteReadyIrqCb; ///< Pointer to buffer write ready callback function + + func_ptr_t pfnBufferReadReadyIrqCb; ///< Pointer to buffer read ready callback function + + func_ptr_t pfnCardInsertIrqCb; ///< Pointer to card insertion callback function + + func_ptr_t pfnCardRemovalIrqCb; ///< Pointer to card removal callback function + + func_ptr_t pfnCardIrqCb; ///< Pointer to card interrupt callback function +} stc_sdioc_normal_irq_cb_t; + +/** + ******************************************************************************* + ** \brief SDIOC error status callback functions + ** + ******************************************************************************/ +typedef struct stc_sdioc_error_irq_cb +{ + func_ptr_t pfnCmdTimeoutErrIrqCb; ///< Pointer to command timeout error interrupt callback function + + func_ptr_t pfnCmdCrcErrIrqCb; ///< Pointer to command CRC error interrupt callback function + + func_ptr_t pfnCmdEndBitErrIrqCb; ///< Pointer to command end bit error interrupt callback function + + func_ptr_t pfnCmdIndexErrIrqCb; ///< Pointer to command index error interrupt callback function + + func_ptr_t pfnDataTimeoutErrIrqCb; ///< Pointer to data timeout error interrupt callback function + + func_ptr_t pfnDataCrcErrIrqCb; ///< Pointer to data CRC error interrupt callback function + + func_ptr_t pfnDataEndBitErrIrqCb; ///< Pointer to data end bit error interrupt callback function + + func_ptr_t pfnAutoCmdErrIrqCb; ///< Pointer to command error interrupt callback function +} stc_sdioc_error_irq_cb_t; + +/** + ******************************************************************************* + ** \brief SDIOC initialization configuration + ** + ******************************************************************************/ +typedef struct stc_sdioc_init +{ + stc_sdioc_normal_irq_en_t *pstcNormalIrqEn; ///< Pointer to normal interrupt enable structure + + stc_sdioc_normal_irq_cb_t *pstcNormalIrqCb; ///< Pointer to normal interrupt callback function structure + + stc_sdioc_error_irq_en_t *pstcErrorIrqEn; ///< Pointer to error interrupt enable structure + + stc_sdioc_error_irq_cb_t *pstcErrorIrqCb; ///< Pointer to error interrupt callback structure +} stc_sdioc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void SDIOC_IrqHandler(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_init_t *pstcInitCfg); +en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx); +void SDIOC_SetMode(const M4_SDIOC_TypeDef *SDIOCx, en_sdioc_mode_t enMode); +en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_cmd_cfg_t *pstcCmdCfg); +uint32_t SDIOC_GetResponse(const M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_response_reg_t enRespReg); +en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len); +en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len); +en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_data_cfg_t *pstcDataCfg); +en_result_t SDIOC_SdclkCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_SetClkDiv(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_clk_div_t enClkDiv); +en_sdioc_clk_div_t SDIOC_GetClkDiv(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetClk(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ClkFreq); +en_result_t SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_bus_width_t enBusWidth); +en_sdioc_bus_width_t SDIOC_GetBusWidth(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_speed_mode_t enSpeedMode); +en_sdioc_speed_mode_t SDIOC_GetSpeedMode(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetDataTimeout(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_data_timeout_t enTimeout); +en_sdioc_data_timeout_t SDIOC_GetDataTimeout(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetCardDetectSignal(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_detect_signal_t enDetectSignal); +en_flag_status_t SDIOC_GetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_BusPowerOn(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_BusPowerOff(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_StopAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_InterruptAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_sw_reset_t enSwResetType); +en_flag_status_t SDIOC_GetStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_host_status_t enHostStatus); +en_result_t SDIOC_NormalIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd); +en_result_t SDIOC_NormalIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd); +en_flag_status_t SDIOC_GetNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt); +en_result_t SDIOC_ClearNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt); +en_result_t SDIOC_ErrIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd); +en_result_t SDIOC_ErrIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd); +en_flag_status_t SDIOC_GetErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt); +en_result_t SDIOC_ClearErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt); +en_result_t SDIOC_ForceErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt); +en_flag_status_t SDIOC_GetAutoCmdErrStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_status_t enAutoCmdErr); +en_result_t SDIOC_ForceAutoCmdErr(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_sel_t enAutoCmdErr); + +//@} // SdiocGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SDIOC_ENABLE */ + +#endif /* __HC32F460_SDIOC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_spi.h b/driver/inc/hc32f460_spi.h new file mode 100644 index 0000000..5afbf57 --- /dev/null +++ b/driver/inc/hc32f460_spi.h @@ -0,0 +1,426 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_spi.h + ** + ** A detailed description is available at + ** @link SpiGroup Serial Peripheral Interface description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of Spi. + ** + ******************************************************************************/ +#ifndef __HC32F460_SPI_H__ +#define __HC32F460_SPI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SPI_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SpiGroup Serial Peripheral Interface(SPI) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SPI parity enumeration + ******************************************************************************/ +typedef enum en_spi_parity +{ + SpiParityEven = 0u, ///< Select even parity send and receive + SpiParityOdd = 1u, ///< Select odd parity send and receive +} en_spi_parity_t; + +/** + ******************************************************************************* + ** \brief SPI master/slave mode enumeration + ******************************************************************************/ +typedef enum en_spi_master_slave_mode +{ + SpiModeSlave = 0u, ///< Spi slave mode + SpiModeMaster = 1u, ///< Spi master mode +} en_spi_master_slave_mode_t; + +/** + ******************************************************************************* + ** \brief SPI transmission mode enumeration + ******************************************************************************/ +typedef enum en_spi_trans_mode +{ + SpiTransFullDuplex = 0u, ///< Full duplex sync serial communication + SpiTransOnlySend = 1u, ///< Only send serial communication +} en_spi_trans_mode_t; + +/** + ******************************************************************************* + ** \brief SPI work mode enumeration + ******************************************************************************/ +typedef enum en_spi_work_mode +{ + SpiWorkMode4Line = 0u, ///< 4 lines spi work mode + SpiWorkMode3Line = 1u, ///< 3 lines spi work mode(clock sync running) +} en_spi_work_mode_t; + +/** + ******************************************************************************* + ** \brief SPI SS interval time enumeration + ******************************************************************************/ +typedef enum en_spi_ss_interval_time +{ + SpiSsIntervalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1 + SpiSsIntervalSck2PlusPck2 = 1u, ///< Spi SS interval time 2 SCK plus 2 PCLK1 + SpiSsIntervalSck3PlusPck2 = 2u, ///< Spi SS interval time 3 SCK plus 2 PCLK1 + SpiSsIntervalSck4PlusPck2 = 3u, ///< Spi SS interval time 4 SCK plus 2 PCLK1 + SpiSsIntervalSck5PlusPck2 = 4u, ///< Spi SS interval time 5 SCK plus 2 PCLK1 + SpiSsIntervalSck6PlusPck2 = 5u, ///< Spi SS interval time 6 SCK plus 2 PCLK1 + SpiSsIntervalSck7PlusPck2 = 6u, ///< Spi SS interval time 7 SCK plus 2 PCLK1 + SpiSsIntervalSck8PlusPck2 = 7u, ///< Spi SS interval time 8 SCK plus 2 PCLK1 +} en_spi_ss_interval_time_t; + +/** + ******************************************************************************* + ** \brief SPI SS setup delay SCK enumeration + ******************************************************************************/ +typedef enum en_spi_ss_setup_delay +{ + SpiSsSetupDelaySck1 = 0u, ///< Spi SS setup delay 1 SCK + SpiSsSetupDelaySck2 = 1u, ///< Spi SS setup delay 2 SCK + SpiSsSetupDelaySck3 = 2u, ///< Spi SS setup delay 3 SCK + SpiSsSetupDelaySck4 = 3u, ///< Spi SS setup delay 4 SCK + SpiSsSetupDelaySck5 = 4u, ///< Spi SS setup delay 5 SCK + SpiSsSetupDelaySck6 = 5u, ///< Spi SS setup delay 6 SCK + SpiSsSetupDelaySck7 = 6u, ///< Spi SS setup delay 7 SCK + SpiSsSetupDelaySck8 = 7u, ///< Spi SS setup delay 8 SCK +} en_spi_ss_setup_delay_t; + +/** + ******************************************************************************* + ** \brief SPI SS hold delay SCK enumeration + ******************************************************************************/ +typedef enum en_spi_ss_hold_delay +{ + SpiSsHoldDelaySck1 = 0u, ///< Spi SS hold delay 1 SCK + SpiSsHoldDelaySck2 = 1u, ///< Spi SS hold delay 2 SCK + SpiSsHoldDelaySck3 = 2u, ///< Spi SS hold delay 3 SCK + SpiSsHoldDelaySck4 = 3u, ///< Spi SS hold delay 4 SCK + SpiSsHoldDelaySck5 = 4u, ///< Spi SS hold delay 5 SCK + SpiSsHoldDelaySck6 = 5u, ///< Spi SS hold delay 6 SCK + SpiSsHoldDelaySck7 = 6u, ///< Spi SS hold delay 7 SCK + SpiSsHoldDelaySck8 = 7u, ///< Spi SS hold delay 8 SCK +} en_spi_ss_hold_delay_t; + +/** + ******************************************************************************* + ** \brief SPI slave select polarity enumeration + ******************************************************************************/ +typedef enum en_spi_ss_polarity +{ + SpiSsLowValid = 0u, ///< SS0~3 signal low level valid + SpiSsHighValid = 1u, ///< SS0~3 signal high level valid +} en_spi_ss_polarity_t; + +/** + ******************************************************************************* + ** \brief SPI data register read object enumeration + ******************************************************************************/ +typedef enum en_spi_read_object +{ + SpiReadReceiverBuffer = 0u, ///< Read receive buffer + SpiReadSendBuffer = 1u, ///< Read send buffer(must be read when TDEF=1) +} en_spi_read_object_t; + +/** + ******************************************************************************* + ** \brief SPI frame number enumeration + ******************************************************************************/ +typedef enum en_spi_frame_number +{ + SpiFrameNumber1 = 0u, ///< 1 frame data + SpiFrameNumber2 = 1u, ///< 2 frame data + SpiFrameNumber3 = 2u, ///< 3 frame data + SpiFrameNumber4 = 3u, ///< 4 frame data +} en_spi_frame_number_t; + +/** + ******************************************************************************* + ** \brief SPI SS setup delay SCK option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_setup_delay_option +{ + SpiSsSetupDelayTypicalSck1 = 0u, ///< SS setup delay 1 SCK + SpiSsSetupDelayCustomValue = 1u, ///< SS setup delay SCKDL register set value +} en_spi_ss_setup_delay_option_t; + +/** + ******************************************************************************* + ** \brief SPI SS hold delay SCK option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_hold_delay_option +{ + SpiSsHoldDelayTypicalSck1 = 0u, ///< SS hold delay 1 SCK + SpiSsHoldDelayCustomValue = 1u, ///< SS hold delay SSDL register set value +} en_spi_ss_hold_delay_option_t; + +/** + ******************************************************************************* + ** \brief SPI SS interval time option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_interval_time_option +{ + SpiSsIntervalTypicalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1 + SpiSsIntervalCustomValue = 1u, ///< Spi SS interval time NXTDL register set value +} en_spi_ss_interval_time_option_t; + +/** + ******************************************************************************* + ** \brief SPI first bit position enumeration + ******************************************************************************/ +typedef enum en_spi_first_bit_position +{ + SpiFirstBitPositionMSB = 0u, ///< Spi first bit to MSB + SpiFirstBitPositionLSB = 1u, ///< Spi first bit to LSB +} en_spi_first_bit_position_t; + +/** + ******************************************************************************* + ** \brief SPI data length enumeration + ******************************************************************************/ +typedef enum en_spi_data_length +{ + SpiDataLengthBit4 = 0u, ///< 4 bits + SpiDataLengthBit5 = 1u, ///< 5 bits + SpiDataLengthBit6 = 2u, ///< 6 bits + SpiDataLengthBit7 = 3u, ///< 7 bits + SpiDataLengthBit8 = 4u, ///< 8 bits + SpiDataLengthBit9 = 5u, ///< 9 bits + SpiDataLengthBit10 = 6u, ///< 10 bits + SpiDataLengthBit11 = 7u, ///< 11 bits + SpiDataLengthBit12 = 8u, ///< 12 bits + SpiDataLengthBit13 = 9u, ///< 13 bits + SpiDataLengthBit14 = 10u, ///< 14 bits + SpiDataLengthBit15 = 11u, ///< 15 bits + SpiDataLengthBit16 = 12u, ///< 16 bits + SpiDataLengthBit20 = 13u, ///< 20 bits + SpiDataLengthBit24 = 14u, ///< 24 bits + SpiDataLengthBit32 = 15u, ///< 32 bits +} en_spi_data_length_t; + +/** + ******************************************************************************* + ** \brief SPI SS valid channel select enumeration + ******************************************************************************/ +typedef enum en_spi_ss_valid_channel +{ + SpiSsValidChannel0 = 0u, ///< Select SS0 valid + SpiSsValidChannel1 = 1u, ///< Select SS1 valid + SpiSsValidChannel2 = 2u, ///< Select SS2 valid + SpiSsValidChannel3 = 3u, ///< Select SS3 valid +} en_spi_ss_valid_channel_t; + +/** + ******************************************************************************* + ** \brief SPI clock division enumeration + ******************************************************************************/ +typedef enum en_spi_clk_div +{ + SpiClkDiv2 = 0u, ///< Spi pclk1 division 2 + SpiClkDiv4 = 1u, ///< Spi pclk1 division 4 + SpiClkDiv8 = 2u, ///< Spi pclk1 division 8 + SpiClkDiv16 = 3u, ///< Spi pclk1 division 16 + SpiClkDiv32 = 4u, ///< Spi pclk1 division 32 + SpiClkDiv64 = 5u, ///< Spi pclk1 division 64 + SpiClkDiv128 = 6u, ///< Spi pclk1 division 128 + SpiClkDiv256 = 7u, ///< Spi pclk1 division 256 +} en_spi_clk_div_t; + +/** + ******************************************************************************* + ** \brief SPI SCK polarity enumeration + ******************************************************************************/ +typedef enum en_spi_sck_polarity +{ + SpiSckIdleLevelLow = 0u, ///< SCK is low level when SCK idle + SpiSckIdleLevelHigh = 1u, ///< SCK is high level when SCK idle +} en_spi_sck_polarity_t; + +/** + ******************************************************************************* + ** \brief SPI SCK phase enumeration + ******************************************************************************/ +typedef enum en_spi_sck_phase +{ + SpiSckOddSampleEvenChange = 0u, ///< SCK Odd edge data sample,even edge data change + SpiSckOddChangeEvenSample = 1u, ///< SCK Odd edge data change,even edge data sample +} en_spi_sck_phase_t; + +/** + ******************************************************************************* + ** \brief SPI interrupt request type enumeration + ******************************************************************************/ +typedef enum en_spi_irq_type +{ + SpiIrqIdle = 0u, ///< Spi idle interrupt request + SpiIrqReceive = 1u, ///< Spi receive interrupt request + SpiIrqSend = 2u, ///< Spi send interrupt request + SpiIrqError = 3u, ///< Spi error interrupt request +} en_spi_irq_type_t; + +/** + ******************************************************************************* + ** \brief SPI flag type enumeration + ******************************************************************************/ +typedef enum en_spi_flag_type +{ + SpiFlagReceiveBufferFull = 0u, ///< Receive buffer full flag + SpiFlagSendBufferEmpty = 1u, ///< Send buffer empty flag + SpiFlagUnderloadError = 2u, ///< Underload error flag + SpiFlagParityError = 3u, ///< Parity error flag + SpiFlagModeFaultError = 4u, ///< Mode fault error flag + SpiFlagSpiIdle = 5u, ///< SPI idle flag + SpiFlagOverloadError = 6u, ///< Overload error flag +} en_spi_flag_type_t; + +/** + ******************************************************************************* + ** \brief SPI SS channel enumeration + ******************************************************************************/ +typedef enum en_spi_ss_channel +{ + SpiSsChannel0 = 0u, ///< SS0 channel + SpiSsChannel1 = 1u, ///< SS1 channel + SpiSsChannel2 = 2u, ///< SS2 channel + SpiSsChannel3 = 3u, ///< SS3 channel +} en_spi_ss_channel_t; + +/** + ******************************************************************************* + ** \brief SPI bus delay structure definition + ** + ** \note Slave mode stc_spi_delay_config_t is invalid + ******************************************************************************/ +typedef struct stc_spi_delay_config +{ + en_spi_ss_setup_delay_option_t enSsSetupDelayOption; ///< SS setup delay time option + en_spi_ss_setup_delay_t enSsSetupDelayTime; ///< SS setup delay time(the value valid when enSsSetupDelayOption is custom) + en_spi_ss_hold_delay_option_t enSsHoldDelayOption; ///< SS hold delay time option + en_spi_ss_hold_delay_t enSsHoldDelayTime; ///< SS hold delay time(the value valid when enSsHoldDelayOption is custom) + en_spi_ss_interval_time_option_t enSsIntervalTimeOption; ///< SS interval time option + en_spi_ss_interval_time_t enSsIntervalTime; ///< SS interval time(the value valid when enSsIntervalTimeOption is custom) +} stc_spi_delay_config_t; + +/** + ******************************************************************************* + ** \brief SPI SS config structure definition + ** + ** \note 3 lines mode stc_spi_ss_config_t is invalid + ******************************************************************************/ +typedef struct stc_spi_ss_config +{ + en_spi_ss_valid_channel_t enSsValidBit; ///< SS valid channel select + en_spi_ss_polarity_t enSs0Polarity; ///< SS0 signal polarity + en_spi_ss_polarity_t enSs1Polarity; ///< SS1 signal polarity + en_spi_ss_polarity_t enSs2Polarity; ///< SS2 signal polarity + en_spi_ss_polarity_t enSs3Polarity; ///< SS3 signal polarity +} stc_spi_ss_config_t; + +/** + ******************************************************************************* + ** \brief SPI init structure definition + ******************************************************************************/ +typedef struct stc_spi_init_t +{ + stc_spi_delay_config_t stcDelayConfig; ///< SPI delay structure(Slave mode is invalid) + stc_spi_ss_config_t stcSsConfig; ///< SS polarity and channel structure(3 lines mode invalid) + en_spi_read_object_t enReadBufferObject; ///< Data register read object select(must be read when TDEF=1) + en_spi_sck_polarity_t enSckPolarity; ///< Sck polarity + en_spi_sck_phase_t enSckPhase; ///< Sck phase(This value must be SpiSckOddChangeEvenSample in 3-line mode) + en_spi_clk_div_t enClkDiv; ///< SPI clock division + en_spi_data_length_t enDataLength; ///< Data length + en_spi_first_bit_position_t enFirstBitPosition; ///< Data first bit position + en_spi_frame_number_t enFrameNumber; ///< Data frame number + en_spi_work_mode_t enWorkMode; ///< Spi work mode + en_spi_trans_mode_t enTransMode; ///< transmission mode + en_spi_master_slave_mode_t enMasterSlaveMode; ///< Spi master/slave mode + en_functional_state_t enCommAutoSuspendEn; ///< Enable/disable Communication auto suspend + en_functional_state_t enModeFaultErrorDetectEn; ///< Enable/disable Mode fault error detect + en_functional_state_t enParitySelfDetectEn; ///< Enable/disable Parity self detect + en_functional_state_t enParityEn; ///< Enable/disable Parity(if enable parity and SPI_CR1.TXMDS=1, receive data don't parity) + en_spi_parity_t enParity; ///< Parity mode select +} stc_spi_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t SPI_DeInit(M4_SPI_TypeDef *SPIx); +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInitCfg); +en_result_t SPI_GeneralLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); +en_result_t SPI_ReverseLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); +en_result_t SPI_Cmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); + +/* Send and receive data functions */ +en_result_t SPI_SendData8(M4_SPI_TypeDef *SPIx, uint8_t u8Data); +en_result_t SPI_SendData16(M4_SPI_TypeDef *SPIx, uint16_t u16Data); +en_result_t SPI_SendData32(M4_SPI_TypeDef *SPIx, uint32_t u32Data); +uint8_t SPI_ReceiveData8(const M4_SPI_TypeDef *SPIx); +uint16_t SPI_ReceiveData16(const M4_SPI_TypeDef *SPIx); +uint32_t SPI_ReceiveData32(const M4_SPI_TypeDef *SPIx); + +/* Communication configure functions */ +en_result_t SPI_SetSsPolarity(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel, + en_spi_ss_polarity_t enPolarity); +en_result_t SPI_SetSsValidChannel(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel); +en_result_t SPI_SetReadDataRegObject(M4_SPI_TypeDef *SPIx, en_spi_read_object_t enObject); +en_result_t SPI_SetFrameNumber(M4_SPI_TypeDef *SPIx, en_spi_frame_number_t enFrameNum); +en_result_t SPI_SetDataLength(M4_SPI_TypeDef *SPIx, en_spi_data_length_t enDataLength); +en_result_t SPI_SetFirstBitPosition(M4_SPI_TypeDef *SPIx, en_spi_first_bit_position_t enPosition); +en_result_t SPI_SetClockDiv(M4_SPI_TypeDef *SPIx, en_spi_clk_div_t enClkDiv); + +/* Interrupt and flags functions */ +en_result_t SPI_IrqCmd(M4_SPI_TypeDef *SPIx, en_spi_irq_type_t enIrq, + en_functional_state_t enNewSta); +en_flag_status_t SPI_GetFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag); +en_result_t SPI_ClearFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag); + +//@} // SpiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SPI_ENABLE */ + +#endif /* __HC32F460_SPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_sram.h b/driver/inc/hc32f460_sram.h new file mode 100644 index 0000000..cc7147d --- /dev/null +++ b/driver/inc/hc32f460_sram.h @@ -0,0 +1,190 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sram.h + ** + ** A detailed description is available at + ** @link SramGroup Internal SRAM description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of SRAM. + ** + ******************************************************************************/ + +#ifndef __HC32F460_SRAM_H__ +#define __HC32F460_SRAM_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SRAM_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + * \defgroup SramGroup Internal SRAM + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +///< SRAM wait cycle register, parity/ECC check register protect code definition +#define SRAM_PROTECT_CODE (0x0000003Bu) + +/******************************************************************************* + Start addr. End addr. Size Function + SRAM1 0x20000000 0x2000FFFF 64KB Even Parity Check + SRAM2 0x20010000 0x2001FFFF 64KB Even Parity Check + SRAM3 0x20020000 0x20026FFF 28KB ECC Check + SRAM_Ret 0x200F0000 0x200F0FFF 4KB Even Parity Check + SRAM_HS 0x1FFF8000 0x1FFFFFFF 32KB Even Parity Check + ******************************************************************************/ +///< SRAM1 base address definition +#define SRAM1_BASE_ADDR (*((volatile unsigned int*)(0x20000000UL))) + +///< SRAM2 base address definition +#define SRAM2_BASE_ADDR (*((volatile unsigned int*)(0x20010000UL))) + +///< SRAM3 base address definition +#define SRAM3_BASE_ADDR (*((volatile unsigned int*)(0x20020000UL))) + +///< Retention SRAM base address definition +#define SRAMRET_BASE_ADDR (*((volatile unsigned int*)(0x200F0000UL))) + +///< High speed SRAM base address definition +#define SRAMHS_BASE_ADDR (*((volatile unsigned int*)(0x1FFF8000UL))) + + +typedef enum en_sram_index +{ + Sram12Idx = 1u << 0, + Sram3Idx = 1u << 1, + SramHsIdx = 1u << 2, + SramRetIdx = 1u << 3, +}en_sram_index_t; +/** + ******************************************************************************* + ** \brief Enumeration to the write/read cycles of SRAM + ** + ** \note + ******************************************************************************/ +typedef enum en_sram_rw_cycle +{ + SramCycle1 = 0u, + SramCycle2 = 1u, + SramCycle3 = 2u, + SramCycle4 = 3u, + SramCycle5 = 4u, + SramCycle6 = 5u, + SramCycle7 = 6u, + SramCycle8 = 7u, +}en_sram_rw_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to ECC check mode + ** + ** \note + ******************************************************************************/ +typedef enum en_ecc_mode +{ + EccMode0 = 0u, ///< disable ECC check function + EccMode1 = 1u, ///< no 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected + EccMode2 = 2u, ///< generate 1 bit ECC flag, but no interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected + EccMode3 = 3u, ///< generate 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected +}en_ecc_mode_t; + +/** + ******************************************************************************* + ** \brief Enumeration to operation after ECC/Parity error + ** + ** \note + ******************************************************************************/ +typedef enum en_ecc_py_err_op +{ + SramNmi = 0u, ///< Generate NMI after ECC/Parity error detected + SramReset = 1u, ///< Generate Reset after ECC/Parity error detected +}en_ecc_py_err_op_t; + +/** + ******************************************************************************* + ** \brief Enumeration to the ECC/Parity error status of each SRAM + ** + ** \note + ******************************************************************************/ +typedef enum en_sram_err_status +{ + Sram3EccErr1 = 1u << 0, ///< SRAM3 1 bit ECC error + Sram3EccErr2 = 1u << 1, ///< SRAM3 2 bit ECC error + Sram12ParityErr = 1u << 2, ///< SRAM1/2 parity error + SramHSParityErr = 1u << 3, ///< High speed SRAM parity error + SramRetParityErr = 1u << 4, ///< Retention SRAM parity error +}en_sram_err_status_t; + +/** + ******************************************************************************* + ** \brief SRAM configuration + ** + ** \note The SRAM configuration structure + ******************************************************************************/ +typedef struct stc_sram_config +{ + uint8_t u8SramIdx; ///< SRAM index, ref @ en_sram_index_t for details + en_sram_rw_cycle_t enSramRC; ///< SRAM read wait cycle setting + en_sram_rw_cycle_t enSramWC; ///< SRAM write wait cycle setting + en_ecc_mode_t enSramEccMode; ///< SRAM ECC mode setting + en_ecc_py_err_op_t enSramEccOp; ///< SRAM3 ECC error handling setting + en_ecc_py_err_op_t enSramPyOp; ///< SRAM1/2/HS/Ret Parity error handling setting + +}stc_sram_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig); +extern en_result_t SRAM_DeInit(void); +extern en_result_t SRAM_WT_Disable(void); +extern en_result_t SRAM_WT_Enable(void); +extern en_result_t SRAM_CK_Disable(void); +extern en_result_t SRAM_CK_Enable(void); +extern en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus); +extern en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus); + +//@} // SramGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SRAM_ENABLE */ + +#endif /* __HC32F460_SRAM_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_swdt.h b/driver/inc/hc32f460_swdt.h new file mode 100644 index 0000000..63d94c4 --- /dev/null +++ b/driver/inc/hc32f460_swdt.h @@ -0,0 +1,86 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_swdt.h + ** + ** A detailed description is available at + ** @link SwdtGroup Special Watchdog Counter description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of SWDT. + ** + ******************************************************************************/ +#ifndef __HC32F460_SWDT_H__ +#define __HC32F460_SWDT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SWDT_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SwdtGroup Special Watchdog Counter(SWDT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT flag type enumeration + ******************************************************************************/ +typedef enum en_swdt_flag_type +{ + SwdtFlagCountUnderflow = 0u, ///< Count underflow flag + SwdtFlagRefreshError = 1u, ///< Refresh error flag +} en_swdt_flag_type_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t SWDT_RefreshCounter(void); +uint16_t SWDT_GetCountValue(void); + +/* Flags functions */ +en_flag_status_t SWDT_GetFlag(en_swdt_flag_type_t enFlag); +en_result_t SWDT_ClearFlag(en_swdt_flag_type_t enFlag); + +//@} // SwdtGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SWDT_ENABLE */ + +#endif /* __HC32F460_SWDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_timer0.h b/driver/inc/hc32f460_timer0.h new file mode 100644 index 0000000..46b570f --- /dev/null +++ b/driver/inc/hc32f460_timer0.h @@ -0,0 +1,209 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer0.h + ** + ** A detailed description is available at + ** @link Timer0Group description @endlink + ** + ** - 2018-10-11 CDT First version for Device Driver Library of TIMER0. + ** + ******************************************************************************/ + +#ifndef __HC32F460_TIMER0_H__ +#define __HC32F460_TIMER0_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_TIMER0_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup Timer0Group Timer0 + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Timer0 channel enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_channel +{ + Tim0_ChannelA = 0x00u, + Tim0_ChannelB = 0x01u +}en_tim0_channel_t; + +/** + ******************************************************************************* + ** \brief Timer0 Async Mode clock enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_async_clock_src +{ + Tim0_LRC = 0x00u, + Tim0_XTAL32 = 0x01u +}en_tim0_async_clock_src_t; + +/** + ******************************************************************************* + ** \brief Timer0 Sync Mode clock enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_sync_clock_src +{ + Tim0_Pclk1 = 0x00u, + Tim0_InsideHardTrig = 0x01u +}en_tim0_sync_clock_src_t; + +/** + ******************************************************************************* + ** \brief Timer0 counter mode enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_counter_mode +{ + Tim0_Sync = 0x00u, + Tim0_Async = 0x01u +}en_tim0_counter_mode_t; + +/** + ******************************************************************************* + ** \brief Timer0 trigger event mode enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_function +{ + Tim0_OutputCapare = 0x00u, + Tim0_InputCaptrue = 0x01u +}en_tim0_function_t; + +/** + ******************************************************************************* + ** \brief Timer0 clock division enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_clock_div +{ + Tim0_ClkDiv0 = 0u, + Tim0_ClkDiv2, + Tim0_ClkDiv4, + Tim0_ClkDiv8, + Tim0_ClkDiv16, + Tim0_ClkDiv32, + Tim0_ClkDiv64, + Tim0_ClkDiv128, + Tim0_ClkDiv256, + Tim0_ClkDiv512, + Tim0_ClkDiv1024 +}en_tim0_clock_div_t; + +/** + ******************************************************************************* + ** \brief Timer0 common trigger source select enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_com_trigger +{ + Tim0ComTrigger_1 = 1u, ///< Select common trigger 1. + Tim0ComTrigger_2 = 2u, ///< Select common trigger 2. + Tim0ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_tim0_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Timer0 trigger function init structrue definition + ** + ******************************************************************************/ +typedef struct stc_tim0_trigger_init +{ + en_tim0_function_t Tim0_OCMode; ///GCMAR / GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR / GCMDR-->GCMBR + ** Double buffer stransfer: Compare Ouput: GCMER-->GCMCR-->GCMAR / GCMFR-->GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR-->GCMER /GCMFR-->GCMDR-->GCMBR + ** For Period register: + ** Single buffer stransfer: PERBR-->PERAR + ** Double buffer stransfer: PERCR-->PERBR-->PERAR + ******************************************************************************/ +typedef enum en_timer6_buf_gcmp_prd +{ + Timer6GcmpPrdSingleBuf = 0u, ///< Single buffer stransfer + Timer6GcmpPrdDoubleBuf = 1u, ///< Double buffer stransfer +}en_timer6_buf_gcmp_prd_t; + +/** + ****************************************************************************** + ** \brief Timer6 buffer - Special compare register transfer function selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_buf_spcl_cmp +{ + Timer6SpclSingleBuf = 0u, ///< Single buffer stransfer: Compare Ouput: SCMCR-->SCMAR / SCMDR-->SCMBR + Timer6SpclDoubleBuf = 1u, ///< Double buffer stransfer: Compare Ouput: SCMER-->SCMCR-->SCMAR / SCMFR-->SCMDR-->SCMBR +}en_timer6_buf_spcl_cmp_t; + +/** + ****************************************************************************** + ** \brief Timer6 buffer - Special compare register transfer opportunity selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_buf_spcl_opt +{ + Timer6SplcOptNone = 0u, ///< No transfer + Timer6SplcOptOverFlow = 1u, ///< Transfer when over flow (About sawtooth mode,accord to the count direction) + Timer6SplcOptUnderFlow = 2u, ///< Transfer when under flow (About sawtooth mode,accord to the count direction) + Timer6SplcOptBoth = 3u, ///< Transfer when over flow or under flow (About sawtooth mode,accord to the count direction) +}en_timer6_buf_spcl_opt_t; + +/** + ****************************************************************************** + ** \brief ADT dead timer control - PWMx dead timer separate set + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_dconr_sepa +{ + Timer6PWMxDtSeparate = 0u, ///< The dead timer of up count and down count separate set by DTUAR and DTDAR + Timer6PWMxDtEqual = 1u, ///< the values of DTUAR and DTDAR are equal automatically +}en_timer6_dconr_sepa_t; + +/** + ****************************************************************************** + ** \brief ADT filter control- TRIx/PWMx port filter sample clock selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_fconr_fltclk +{ + Timer6FltClkPclk0Div1 = 0u, ///< PCLK0 + Timer6FltClkPclk0Div4 = 1u, ///< PCLK0/4 + Timer6FltClkPclk0Div16 = 2u, ///< PCLK0/16 + Timer6FltClkPclk0Div64 = 3u, ///< PCLK0/64 +}en_timer6_fconr_fltclk_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period repeat- TIMx valid period repeat function selection(trigger interrupt or AOS event) + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_vperr_pcnts +{ + Timer6PeriodCnts0 = 0u, ///< Valid period repeat function disable + Timer6PeriodCnts1 = 1u, ///< Enable every other one period + Timer6PeriodCnts2 = 2u, ///< Enable every other two periods + Timer6PeriodCnts3 = 3u, ///< Enable every other three periods + Timer6PeriodCnts4 = 4u, ///< Enable every other four periods + Timer6PeriodCnts5 = 5u, ///< Enable every other five periods + Timer6PeriodCnts6 = 6u, ///< Enable every other six periods + Timer6PeriodCnts7 = 7u, ///< Enable every other seven periods +}en_timer6_vperr_pcnts_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period repeat- Count condition select + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_vperr_pcnte +{ + Timer6PeriodCnteDisable = 0u, ///< Valid period repeat function disable + Timer6PeriodCnteMin = 1u, ///< Over flow and under flow point of Sawtooth wave mode, or under flow point of Triangular wave mode + Timer6PeriodCnteMax = 2u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow point of Triangular wave mode + Timer6PeriodCnteBoth = 3u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow and under flow point of Triangular wave mode +}en_timer6_vperr_pcnte_t; + +/** + ****************************************************************************** + ** \brief Timer6 Hardware(Start/Stop/Clear/Capture) event trigger select + ** + ** \note + ******************************************************************************/ + +typedef enum en_timer6_hw_trig +{ + Timer6HwTrigAos0 = 0u, ///< Hardware trigger event from AOS0(HTSSR0) + Timer6HwTrigAos1 = 1u, ///< Hardware trigger event from AOS1(HTSSR1) + Timer6HwTrigPWMARise = 4u, ///< Hardware trigger event from PWMA rising + Timer6HwTrigPWMAFall = 5u, ///< Hardware trigger event from PWMA falling + Timer6HwTrigPWMBRise = 6u, ///< Hardware trigger event from PWMA rising + Timer6HwTrigPWMBFall = 7u, ///< Hardware trigger event from PWMA falling + Timer6HwTrigTimTriARise = 8u, ///< Hardware trigger event from TRIGA rising + Timer6HwTrigTimTriAFall = 9u, ///< Hardware trigger event from TRIGA falling + Timer6HwTrigTimTriBRise = 10u, ///< Hardware trigger event from TRIGB rising + Timer6HwTrigTimTriBFall = 11u, ///< Hardware trigger event from TRIGB falling + Timer6HwTrigEnd = 16u, +}en_timer6_hw_trig_t; + +/** + ****************************************************************************** + ** \brief Timer6 hardware (up count/down count) event trigger select + ** + ** \note + ******************************************************************************/ + +typedef enum en_timer6_hw_cnt +{ + Timer6HwCntPWMALowPWMBRise = 0u, ///< PWMB Rising trigger when PWMA is low level + Timer6HwCntPWMALowPWMBFall = 1u, ///< PWMB falling trigger when PWMA is low level + Timer6HwCntPWMAHighPWMBRise = 2u, ///< PWMB Rising trigger when PWMA is high level + Timer6HwCntPWMAHighPWMBFall = 3u, ///< PWMB falling trigger when PWMA is high level + Timer6HwCntPWMBLowPWMARise = 4u, ///< PWMA Rising trigger when PWMB is low level + Timer6HwCntPWMBLowPWMAFall = 5u, ///< PWMA falling trigger when PWMB is low level + Timer6HwCntPWMBHighPWMARise = 6u, ///< PWMA Rising trigger when PWMB is high level + Timer6HwCntPWMBHighPWMAFall = 7u, ///< PWMA falling trigger when PWMB is high level + Timer6HwCntTRIGARise = 8u, ///< TRIGA rising trigger + Timer6HwCntTRIGAFall = 9u, ///< TRIGA falling trigger + Timer6HwCntTRIGBRise = 10u, ///< TRIGB rising trigger + Timer6HwCntTRIGBFall = 11u, ///< TRIGB falling trigger + Timer6HwCntAos0 = 16u, ///< AOS0 trigger + Timer6HwCntAos1 = 17u, ///< AOS1 trigger + Timer6HwCntMax = 18u, +}en_timer6_hw_cnt_t; + + +/** + ****************************************************************************** + ** \brief Timer6 interrupt type + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_irq_type +{ + Timer6INTENA = 0u, ///< Interrupt of count equal to GCMA (or capture input A) + Timer6INTENB = 1u, ///< Interrupt of count equal to GCMB (or capture input B) + Timer6INTENC = 2u, ///< Interrupt of count equal to GCMC + Timer6INTEND = 3u, ///< Interrupt of count equal to GCMD + Timer6INTENE = 4u, ///< Interrupt of count equal to GCME + Timer6INTENF = 5u, ///< Interrupt of count equal to GCMF + Timer6INTENOVF = 6u, ///< Interrupt of over flow of sawtooth wave mode or peak point of triangular wave mode + Timer6INTENUDF = 7u, ///< Interrupt of under flow of sawtooth wave mode or valley point of triangular wave mode + Timer6INTENDTE = 8u, ///< Interrupt of dead timer error + Timer6INTENSAU = 16u, ///< Interrupt of count up equally compared with SCMA + Timer6INTENSAD = 17u, ///< Interrupt of count down equally compared with SCMA + Timer6INTENSBU = 18u, ///< Interrupt of count up equally compared with SCMB + Timer6INTENSBD = 19u, ///< Interrupt of count down equally compared with SCMB +}en_timer6_irq_type_t; + + +/** + ****************************************************************************** + ** \brief Timer6 status flag + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_status +{ + Timer6CMAF = 0u, ///< Status flag of count equal to GCMA (or capture input A) + Timer6CMBF = 1u, ///< Status flag of count equal to GCMB (or capture input B) + Timer6CMCF = 2u, ///< Status flag of count equal to GCMC + Timer6CMDF = 3u, ///< Status flag of count equal to GCMD + Timer6CMEF = 4u, ///< Status flag of count equal to GCME + Timer6CMFF = 5u, ///< Status flag of count equal to GCMF + Timer6OVFF = 6u, ///< Status flag of over flow of sawtooth wave mode or peak point of triangular wave mode + Timer6UDFF = 7u, ///< Status flag of under flow of sawtooth wave mode or valley point of triangular wave mode + Timer6DTEF = 8u, ///< Status flag of dead timer error + Timer6CMSAUF = 9u, ///< Status flag of count up equally compared with SCMA + Timer6CMSADF = 10u, ///< Status flag of count down equally compared with SCMA + Timer6CMSBUF = 11u, ///< Status flag of count up equally compared with SCMB + Timer6CMSBDF = 12u, ///< Status flag of count down equally compared with SCMB + Timer6VPERNUM = 21, ///< Number of valid period + Timer6DIRF = 31, ///< Count direction +}en_timer6_status_t; + +/** + ******************************************************************************* + ** \brief Timer6 common trigger source select enumeration + ** + ******************************************************************************/ +typedef enum en_timer6_com_trigger +{ + Timer6ComTrigger_1 = 1u, ///< Select common trigger 1. + Timer6ComTrigger_2 = 2u, ///< Select common trigger 2. + Timer6ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_timer6_com_trigger_t; + +/** + ****************************************************************************** + ** \brief Timer6 software synchronous config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_sw_sync +{ + bool bTimer61; ///< Timer6 unit1 + bool bTimer62; ///< Timer6 unit2 + bool bTimer63; ///< Timer6 unit3 +}stc_timer6_sw_sync_t; + +/** + ****************************************************************************** + ** \brief Timer6 base init structure definition + ** \note + ******************************************************************************/ +typedef struct stc_timer6_basecnt_cfg +{ + en_timer6_count_mode_t enCntMode; ///< Count mode + en_timer6_count_dir_t enCntDir; ///< Count direction + en_timer6_clk_div_t enCntClkDiv; ///< Count clock division select +}stc_timer6_basecnt_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Trig port config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_port_trig_cfg +{ + bool bFltEn; ///< trig source capture input filter enable + en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock +}stc_tiemr6_port_trig_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 port output config +** \note + ******************************************************************************/ +typedef struct stc_timer6_port_output_cfg +{ + en_timer6_func_mode_t enPortMode; ///< Port mode + bool bOutEn; ///< Output enable / disable + en_timer6_pconr_cmpc_t enPerc; ///< Port state when counter match the period + en_timer6_pconr_cmpc_t enCmpc; ///< Port state when counter match GCMAR(GCMBR) + en_timer6_pconr_stastps_t enStaStp; ///< Post state selection when count start/stop + en_timer6_pconr_port_out_t enStaOut; ///< Port state when count start + en_timer6_pconr_port_out_t enStpOut; ///< port stop when count stop + en_timer6_pconr_disval_t enDisVal; ///< Port output state when brake +}stc_timer6_port_output_cfg_t; + + +/** + ****************************************************************************** + ** \brief Timer6 port input config +** \note + ******************************************************************************/ +typedef struct stc_timer6_port_input_cfg +{ + en_timer6_input_port_t enPortSel; ///< Port select + en_timer6_func_mode_t enPortMode; ///< Port mode + bool bFltEn; ///< trig source capture input filter enable + en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock +}stc_timer6_port_input_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 hardware dead time function config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_deadtime_cfg +{ + bool bEnDeadtime; ///< Enable hardware dead time function + bool bEnDtBufUp; ///< Enable buffer transfer for up count dead time register(DTUBR-->DTUAR) + bool bEnDtBufDwn; ///< Enable buffer transfer for down count dead time register(DTDBR-->DTDAR) + bool bEnDtEqualUpDwn; ///< Enable down count dead time register equal to up count DT register +}stc_timer6_deadtime_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_validper_cfg +{ + en_timer6_vperr_pcnts_t enValidCntNum; ///< Valid period selection + en_timer6_vperr_pcnte_t enValidCdtEn; ///< Count condition of valid period + bool bPeriodSCMA; ///< Sepcial signal A valid period selection enable + bool bPeriodSCMB; ///< Sepcial signal A valid period selection enable +}stc_timer6_validper_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 general compare register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_gcmp_buf_cfg +{ + bool bEnGcmpTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_gcmp_prd_t enGcmpBufTransType; ///< Sigle or double buffer transfer +}stc_timer6_gcmp_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 period register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_period_buf_cfg +{ + bool bEnPeriodTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_gcmp_prd_t enPeriodBufTransType; ///< Sigle or double buffer transfer +}stc_timer6_period_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Specila compare register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_spcl_buf_cfg +{ + bool bEnSpclTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_spcl_cmp_t enSpclBufTransType; ///< Sigle or double buffer transfer + en_timer6_buf_spcl_opt_t enSpclBufOptType; ///< Buffer transfer opportunity +}stc_timer6_spcl_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Z phase input mask config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_zmask_cfg +{ + en_timer6_gconr_zmsk_t enZMaskCycle; ///< Z phase input mask periods selection + bool bFltPosCntMaksEn; ///< As position count timer, position counter clear function enable(TRUE) or disable(FALSE) during the time of Z phase input mask + bool bFltRevCntMaksEn; ///< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) during the time of Z phase input mask +}stc_timer6_zmask_cfg_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* IRQ config */ +en_result_t Timer6_ConfigIrq(M4_TMR6_TypeDef *TMR6x, en_timer6_irq_type_t enTimer6Irq, bool bEn); +/* Get status(flag) */ +uint8_t Timer6_GetStatus(M4_TMR6_TypeDef *TMR6x, en_timer6_status_t enStatus); + +/* Base functions */ +en_result_t Timer6_DeInit(M4_TMR6_TypeDef *TMR6x); +en_result_t Timer6_Init(M4_TMR6_TypeDef *TMR6x, const stc_timer6_basecnt_cfg_t* pstcTimer6BaseCntCfg); +/* Timer6 unit start count*/ +en_result_t Timer6_StartCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit stop count*/ +en_result_t Timer6_StopCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit Set Count Value*/ +en_result_t Timer6_SetCount(M4_TMR6_TypeDef *TMR6x, uint16_t u16Value); +/* Timer6 unit Get Count Value*/ +uint16_t Timer6_GetCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit Clear Count Value*/ +en_result_t Timer6_ClearCount(M4_TMR6_TypeDef *TMR6x); + +/* Timer6 unit Set Period and buffer Value*/ +en_result_t Timer6_SetPeriod(M4_TMR6_TypeDef *TMR6x, en_timer6_period_t enTimer6Periodx, uint16_t u16Period); +/* Timer6 unit set general compare register value*/ +en_result_t Timer6_SetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare, uint16_t u16Compare); +/* Timer6 unit set specoal compare register value*/ +en_result_t Timer6_SetSpecialCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_special_compare_t enTimer6SpclCmp, uint16_t u16SpclCmp); +/* Timer6 unit get general compare register value*/ +uint16_t Timer6_GetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare); + +/* Timer6 unit set period buffer transfer function*/ +en_result_t Timer6_SetPeriodBuf(M4_TMR6_TypeDef *TMR6x, const stc_timer6_period_buf_cfg_t* pstcTimer6PrdBufCfg); +/* Timer6 unit set general compare buffer transfer function*/ +en_result_t Timer6_SetGeneralBuf(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_gcmp_buf_cfg_t* pstcTimer6GenBufCfg); +/* Timer6 unit set special compare buffer transfer function*/ +en_result_t Timer6_SetSpecialBuf(M4_TMR6_TypeDef *TMR6x,en_timer6_special_compare_t enTimer6SpclCmp, const stc_timer6_spcl_buf_cfg_t* pstcTimer6SpclBufCfg); + +/* Timer6 unit Set valid period Value*/ +en_result_t Timer6_SetValidPeriod(M4_TMR6_TypeDef *TMR6x, const stc_timer6_validper_cfg_t* pstcTimer6ValidPerCfg); + +/* Config Input prot and filter function */ +en_result_t Timer6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, const stc_timer6_port_input_cfg_t* pstcTimer6PortInputCfg); +/* Config output prot function */ +en_result_t Timer6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_port_output_cfg_t* pstcTimer6PortOutCfg); + +/* Set dead time register value */ +en_result_t Timer6_SetDeadTimeValue(M4_TMR6_TypeDef *TMR6x, en_timer6_dead_time_reg_t enTimer6DTReg, uint16_t u16DTValue); +/* Config dead time function */ +en_result_t Timer6_ConfigDeadTime(M4_TMR6_TypeDef *TMR6x, const stc_timer6_deadtime_cfg_t* pstcTimer6DTCfg); + +/* Config Software Synchrony Stop */ +en_result_t Timer6_SwSyncStart(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStart); +/* Config Software Synchrony Start */ +en_result_t Timer6_SwSyncStop(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStop); +/* Config Software Synchrony Clear */ +en_result_t Timer6_SwSyncClear(const stc_timer6_sw_sync_t* pstcTimer6SwSyncClear); +/* Get Software Synchrony Status */ +en_result_t Timer6_GetSwSyncState(stc_timer6_sw_sync_t* pstcTimer6SwSyncState); + +/* Config Hardware up count event */ +en_result_t Timer6_ConfigHwCntUp(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntUp); +/* Clear Hardware up count event */ +en_result_t Timer6_ClearHwCntUp(M4_TMR6_TypeDef *TMR6x); +/* Config Hardware down count event */ +en_result_t Timer6_ConfigHwCntDwn(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntDwn); +/* Clear Hardware down count event */ +en_result_t Timer6_ClearHwCntDwn(M4_TMR6_TypeDef *TMR6x); + + +/* Config Hardware start event */ +en_result_t Timer6_ConfigHwStart(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStart); +/* Clear Hardware start event */ +en_result_t Timer6_ClearHwStart(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware start event */ +en_result_t Timer6_EnableHwStart(M4_TMR6_TypeDef *TMR6x); +/* Dsiable Hardware start event */ +en_result_t Timer6_DisableHwStart(M4_TMR6_TypeDef *TMR6x); + +/* Config Hardware stop event */ +en_result_t Timer6_ConfigHwStop(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStop); +/* Clear Hardware stop event */ +en_result_t Timer6_ClearHwStop(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware stop event */ +en_result_t Timer6_EnableHwStop(M4_TMR6_TypeDef *TMR6x); +/* Disable Hardware stop event */ +en_result_t Timer6_DisableHwStop(M4_TMR6_TypeDef *TMR6x); + +/* Config Hardware clear event */ +en_result_t Timer6_ConfigHwClear(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwClear); +/* Clear Hardware clear event */ +en_result_t Timer6_ClearHwClear(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware clear event */ +en_result_t Timer6_EnableHwClear(M4_TMR6_TypeDef *TMR6x); +/* Dsiable Hardware clear event */ +en_result_t Timer6_DisableHwClear(M4_TMR6_TypeDef *TMR6x); + + +/* Config Hardware capture event A */ +en_result_t Timer6_ConfigHwCaptureA(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureA); +/* Clear Hardware capture event A */ +en_result_t Timer6_ClearHwCaptureA(M4_TMR6_TypeDef *TMR6x); +/* Config Hardware capture event B */ +en_result_t Timer6_ConfigHwCaptureB(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureB); +/* Clear Hardware capture event B */ +en_result_t Timer6_ClearHwCaptureB(M4_TMR6_TypeDef *TMR6x); + + +/* Set trigger source 0 of hardware event */ +en_result_t Timer6_SetTriggerSrc0(en_event_src_t enTriggerSrc); +/* Set trigger source 1 of hardware event */ +en_result_t Timer6_SetTriggerSrc1(en_event_src_t enTriggerSrc); +/* Enable or disable Timer6 common trigger for Hardware trigger source 0 */ +void TIMER6_ComTriggerCmd0(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState); +/* Enable or disable Timer6 common trigger for Hardware trigger source 1 */ +void TIMER6_ComTriggerCmd1(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState); + +/* Z phase input mask config */ +en_result_t Timer6_ConfigZMask(M4_TMR6_TypeDef *TMR6x, const stc_timer6_zmask_cfg_t* pstcTimer6ZMaskCfg); + +//@} // Timer6Group + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_TIMER6_ENABLE */ + +#endif /* __HC32F460_TIMER6_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_timera.h b/driver/inc/hc32f460_timera.h new file mode 100644 index 0000000..5143819 --- /dev/null +++ b/driver/inc/hc32f460_timera.h @@ -0,0 +1,493 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timera.h + ** + ** A detailed description is available at + ** @link TimeraGroup Timer A description @endlink + ** + ** - 2018-11-08 CDT First version for Device Driver Library of + ** Timera. + ** + ******************************************************************************/ +#ifndef __HC32F460_TIMERA_H__ +#define __HC32F460_TIMERA_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_TIMERA_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup TimeraGroup Timer A(Timera) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Timera channel enumeration + ******************************************************************************/ +typedef enum en_timera_channel +{ + TimeraCh1 = 0u, ///< Timera channel 1 + TimeraCh2 = 1u, ///< Timera channel 2 + TimeraCh3 = 2u, ///< Timera channel 3 + TimeraCh4 = 3u, ///< Timera channel 4 + TimeraCh5 = 4u, ///< Timera channel 5 + TimeraCh6 = 5u, ///< Timera channel 6 + TimeraCh7 = 6u, ///< Timera channel 7 + TimeraCh8 = 7u, ///< Timera channel 8 +} en_timera_channel_t; + +/** + ******************************************************************************* + ** \brief Clock division enumeration + ******************************************************************************/ +typedef enum en_timera_clk_div +{ + TimeraPclkDiv1 = 0u, ///< Count clock: pclk + TimeraPclkDiv2 = 1u, ///< Count clock: pclk/2 + TimeraPclkDiv4 = 2u, ///< Count clock: pclk/4 + TimeraPclkDiv8 = 3u, ///< Count clock: pclk/8 + TimeraPclkDiv16 = 4u, ///< Count clock: pclk/16 + TimeraPclkDiv32 = 5u, ///< Count clock: pclk/32 + TimeraPclkDiv64 = 6u, ///< Count clock: pclk/64 + TimeraPclkDiv128 = 7u, ///< Count clock: pclk/128 + TimeraPclkDiv256 = 8u, ///< Count clock: pclk/256 + TimeraPclkDiv512 = 9u, ///< Count clock: pclk/512 + TimeraPclkDiv1024 = 10u, ///< Count clock: pclk/1024 +} en_timera_clk_div_t; + +/** + ******************************************************************************* + ** \brief Count mode enumeration + ******************************************************************************/ +typedef enum en_timera_count_mode +{ + TimeraCountModeSawtoothWave = 0u, ///< Sawtooth wave mode + TimeraCountModeTriangularWave = 1u, ///< Triangular wave mode +} en_timera_count_mode_t; + +/** + ******************************************************************************* + ** \brief Count direction enumeration + ******************************************************************************/ +typedef enum en_timera_count_dir +{ + TimeraCountDirDown = 0u, ///< Counter counting down + TimeraCountDirUp = 1u, ///< Counter counting up +} en_timera_count_dir_t; + +/** + ******************************************************************************* + ** \brief Input port filter clock division enumeration + ******************************************************************************/ +typedef enum en_timera_filter_clk_div +{ + TimeraFilterPclkDiv1 = 0u, ///< Filter clock: pclk + TimeraFilterPclkDiv4 = 1u, ///< Filter clock: pclk/4 + TimeraFilterPclkDiv16 = 2u, ///< Filter clock: pclk/16 + TimeraFilterPclkDiv64 = 3u, ///< Filter clock: pclk/64 +} en_timera_filter_clk_div_t; + +/** + ******************************************************************************* + ** \brief Input port filter source enumeration + ** + ** \note __ is unit number,range 1~6 + ******************************************************************************/ +typedef enum en_timera_filter_source +{ + TimeraFilterSourceCh1 = 0u, ///< TIMA__PWM1 input port + TimeraFilterSourceCh2 = 1u, ///< TIMA__PWM2 input port + TimeraFilterSourceCh3 = 2u, ///< TIMA__PWM3 input port + TimeraFilterSourceCh4 = 3u, ///< TIMA__PWM4 input port + TimeraFilterSourceCh5 = 4u, ///< TIMA__PWM5 input port + TimeraFilterSourceCh6 = 5u, ///< TIMA__PWM6 input port + TimeraFilterSourceCh7 = 6u, ///< TIMA__PWM7 input port + TimeraFilterSourceCh8 = 7u, ///< TIMA__PWM8 input port + TimeraFilterSourceClkA = 8u, ///< TIMA__CLKA input port + TimeraFilterSourceClkB = 9u, ///< TIMA__CLKB input port + TimeraFilterSourceTrig = 10u, ///< TIMA__TRIG input port +} en_timera_filter_source_t; + +/** + ******************************************************************************* + ** \brief Timera interrupt request type enumeration + ******************************************************************************/ +typedef enum en_timera_irq_type +{ + TimeraIrqCaptureOrCompareCh1 = 0u, ///< Interrupt request when channel 1 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh2 = 1u, ///< Interrupt request when channel 2 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh3 = 2u, ///< Interrupt request when channel 3 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh4 = 3u, ///< Interrupt request when channel 4 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh5 = 4u, ///< Interrupt request when channel 5 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh6 = 5u, ///< Interrupt request when channel 6 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh7 = 6u, ///< Interrupt request when channel 7 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh8 = 7u, ///< Interrupt request when channel 8 trigger capture event or compare value equal count value + TimeraIrqOverflow = 8u, ///< Count overflow interrupt request + TimeraIrqUnderflow = 9u, ///< Count underflow interrupt request +} en_timera_irq_type_t; + +/** + ******************************************************************************* + ** \brief Timera flag type enumeration + ******************************************************************************/ +typedef enum en_timera_flag_type +{ + TimeraFlagCaptureOrCompareCh1 = 0u, ///< Match flag when channel 1 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh2 = 1u, ///< Match flag when channel 2 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh3 = 2u, ///< Match flag when channel 3 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh4 = 3u, ///< Match flag when channel 4 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh5 = 4u, ///< Match flag when channel 5 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh6 = 5u, ///< Match flag when channel 6 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh7 = 6u, ///< Match flag when channel 7 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh8 = 7u, ///< Match flag when channel 8 trigger capture complete or compare value equal count value + TimeraFlagOverflow = 8u, ///< Count overflow flag + TimeraFlagUnderflow = 9u, ///< Count underflow flag +} en_timera_flag_type_t; + +/** + ******************************************************************************* + ** \brief Timera function mode selection enumeration + ******************************************************************************/ +typedef enum en_timera_func_mode +{ + TimeraModeCompareOutput = 0u, ///< Compare output function + TimeraModeCaptureInput = 1u, ///< Capture input function +} en_timera_func_mode_t; + +/** + ******************************************************************************* + ** \brief Timera count start port output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_count_start_output +{ + TimeraCountStartOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCountStartOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCountStartOutputKeep = 2u, ///< TIMA__PWMn port output to keep +} en_timera_count_start_output_t; + +/** + ******************************************************************************* + ** \brief Timera count stop port output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_count_stop_output +{ + TimeraCountStopOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCountStopOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCountStopOutputKeep = 2u, ///< TIMA__PWMn port output to keep +} en_timera_count_stop_output_t; + +/** + ******************************************************************************* + ** \brief Timera compare value match output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_compare_match_output +{ + TimeraCompareMatchOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCompareMatchOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCompareMatchOutputKeep = 2u, ///< TIMA__PWMn port output to keep + TimeraCompareMatchOutputReverse = 3u, ///< TIMA__PWMn port output reverse +} en_timera_compare_match_output_t; + +/** + ******************************************************************************* + ** \brief Timera period value match output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_period_match_output +{ + TimeraPeriodMatchOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraPeriodMatchOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraPeriodMatchOutputKeep = 2u, ///< TIMA__PWMn port output to keep + TimeraPeriodMatchOutputReverse = 3u, ///< TIMA__PWMn port output reverse +} en_timera_period_match_output_t; + +/** + ******************************************************************************* + ** \brief Timera specify output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_specify_output +{ + TimeraSpecifyOutputInvalid = 0u, ///< TIMA__PWMn port output invalid + TimeraSpecifyOutputLow = 2u, ///< TIMA__PWMn port output low level from next period + TimeraSpecifyOutputHigh = 3u, ///< TIMA__PWMn port output high level from next period +} en_timera_specify_output_t; + +/** + ******************************************************************************* + ** \brief Timera common trigger source enumeration + ******************************************************************************/ +typedef enum en_timera_com_trigger +{ + TimeraComTrigger_1 = 1u, ///< Select common trigger 1. + TimeraComTrigger_2 = 2u, ///< Select common trigger 2. + TimeraComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_timera_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Timera base init structure definition + ******************************************************************************/ +typedef struct stc_timera_base_init +{ + en_timera_clk_div_t enClkDiv; ///< Count clock division select,This is invalid when counting internal or external event + en_timera_count_mode_t enCntMode; ///< Timera count mode + en_timera_count_dir_t enCntDir; ///< Timera count direction + en_functional_state_t enSyncStartupEn; ///< Enable/disable synchronization startup when unit 1 startup,unit 1 set bit invalid + uint16_t u16PeriodVal; ///< Period value +} stc_timera_base_init_t; + +/** + ******************************************************************************* + ** \brief Timera compare output init structure definition + ******************************************************************************/ +typedef struct stc_timera_compare_init +{ + uint16_t u16CompareVal; ///< Compare value + en_timera_count_start_output_t enStartCountOutput; ///< Port status set when count start + en_timera_count_stop_output_t enStopCountOutput; ///< Port status set when count stop + en_timera_compare_match_output_t enCompareMatchOutput; ///< Port status set when compare value match + en_timera_period_match_output_t enPeriodMatchOutput; ///< Port status set when period value match + en_timera_specify_output_t enSpecifyOutput; ///< Specify port status,next period valid,priority more than other port status set + en_functional_state_t enCacheEn; ///< Enable/Disable cache，Only unit 1ã€3ã€5ã€7 valid + en_functional_state_t enTriangularTroughTransEn; ///< Enable/Disable triangular wave trough transmit cache value，Only unit 1ã€3ã€5ã€7 valid + en_functional_state_t enTriangularCrestTransEn; ///< Enable/Disable triangular wave crest transmit cache value，Only unit 1ã€3ã€5ã€7 valid + uint16_t u16CompareCacheVal; ///< Compare cache value,Only unit 1ã€3ã€5ã€7 valid +} stc_timera_compare_init_t; + +/** + ******************************************************************************* + ** \brief Timera capture input init structure definition + ******************************************************************************/ +typedef struct stc_timera_capture_init +{ + en_functional_state_t enCapturePwmRisingEn; ///< Enable/Disable capture channel n active when TIMA__PWMn sample rising + en_functional_state_t enCapturePwmFallingEn; ///< Enable/Disable capture channel n active when TIMA__PWMn sample falling + en_functional_state_t enCaptureSpecifyEventEn; ///< Enable/Disable capture channel n active when specify event trigger,event value is TMRA_HTSSR1 + en_timera_filter_clk_div_t enPwmClkDiv; ///< TIMA__PWMn filter clock select + en_functional_state_t enPwmFilterEn; ///< Enable/Disable TIMA__PWMn filter functions + en_functional_state_t enCaptureTrigRisingEn; ///< Enable/Disable capture channel 4 active when TIMA__TRIG sample rising, only CCONR4 valid + en_functional_state_t enCaptureTrigFallingEn; ///< Enable/Disable capture channel 4 active when TIMA__TRIG sample falling, only CCONR4 valid + en_timera_filter_clk_div_t enTrigClkDiv; ///< TIMA__TRIG filter clock select, only CCONR4 valid + en_functional_state_t enTrigFilterEn; ///< Enable/Disable TIMA__TRIG filter functions , only CCONR4 valid +} stc_timera_capture_init_t; + +/** + ******************************************************************************* + ** \brief Timera Orthogonal coding init structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ** \note n=2ã€4ã€6 when m=1ã€3ã€5 or n=1ã€3ã€5 when m=2ã€4ã€6 + ******************************************************************************/ +typedef struct stc_timera_orthogonal_coding_init +{ + en_functional_state_t enIncClkALowAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enIncClkALowAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enIncClkAHighAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enIncClkAHighAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enIncClkBLowAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enIncClkBLowAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enIncClkBHighAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enIncClkBHighAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enIncTrigRisingEn; ///< TIMA__TRIG sample rising edge hardware increase + en_functional_state_t enIncTrigFallingEn; ///< TIMA__TRIG sample falling edge hardware increase + en_functional_state_t enIncSpecifyEventTriggerEn; ///< TIMA_HTSSR0 register Specify event trigger hardware increase + en_functional_state_t enIncAnotherUnitOverflowEn; ///< Unit n generate count overflow hardware increase when current unit is m. + en_functional_state_t enIncAnotherUnitUnderflowEn; ///< Unit n generate count underflow hardware increase when current unit is m. + en_functional_state_t enDecClkALowAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enDecClkALowAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enDecClkAHighAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enDecClkAHighAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enDecClkBLowAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enDecClkBLowAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enDecClkBHighAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enDecClkBHighAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enDecTrigRisingEn; ///< TIMA__TRIG sample rising edge hardware increase + en_functional_state_t enDecTrigFallingEn; ///< TIMA__TRIG sample falling edge hardware increase + en_functional_state_t enDecSpecifyEventTriggerEn; ///< TIMA_HTSSR0 register Specify event trigger hardware increase + en_functional_state_t enDecAnotherUnitUnderflowEn; ///< Unit n generate count overflow hardware increase when current unit is m. + en_functional_state_t enDecAnotherUnitOverflowEn; ///< Unit n generate count underflow hardware increase when current unit is m. + en_timera_filter_clk_div_t enClkAClkDiv; ///< TIMA__CLKA filter clock select + en_functional_state_t enClkAFilterEn; ///< Enable/Disable TIMA__CLKA filter functions + en_timera_filter_clk_div_t enClkBClkDiv; ///< TIMA__CLKB filter clock select + en_functional_state_t enClkBFilterEn; ///< Enable/Disable TIMA__CLKB filter functions + en_timera_filter_clk_div_t enTrigClkDiv; ///< TIMA__TRIG filter clock select + en_functional_state_t enTrigFilterEn; ///< Enable/Disable TIMA__TRIG filter functions +} stc_timera_orthogonal_coding_init_t; + +/** + ******************************************************************************* + ** \brief Timera hardware startup config structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note TMRA_HTSSR0 trigger startup only when unit 2~6 valid,unit 1 is invalid + ******************************************************************************/ +typedef struct stc_timera_hw_startup_config +{ + en_functional_state_t enTrigRisingStartupEn; ///< Hardware startup TIMA_ when TIMA__TRIG sample rising edge(sync start valid) + en_functional_state_t enTrigFallingStartupEn; ///< Hardware startup TIMA_ when TIMA__TRIG sample falling edge(sync start valid) + en_functional_state_t enSpecifyEventStartupEn; ///< Hardware startup TIMA_ when TIMA_HTSSR0 register Specify event trigger +} stc_timera_hw_startup_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware stop config structure definition + ** + ** \note __ is unit number,range 1~6 + ******************************************************************************/ +typedef struct stc_timera_hw_stop_config +{ + en_functional_state_t enTrigRisingStopEn; ///< Hardware stop TIMA_ when TIMA__TRIG sample rising edge + en_functional_state_t enTrigFallingStopEn; ///< Hardware stop TIMA_ when TIMA__TRIG sample falling edge + en_functional_state_t enSpecifyEventStopEn; ///< Hardware stop TIMA_ when TIMA_HTSSR0 register Specify event trigger +} stc_timera_hw_stop_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware clear config structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note n=2ã€4ã€6 when m=1ã€3ã€5 or n=1ã€3ã€5 when m=2ã€4ã€6 + ******************************************************************************/ +typedef struct stc_timera_hw_clear_config +{ + en_functional_state_t enTrigRisingClearEn; ///< Hardware clear TIMA_ when TIMA__TRIG sample rising edge + en_functional_state_t enTrigFallingClearEn; ///< Hardware clear TIMA_ when TIMA__TRIG sample falling edge + en_functional_state_t enSpecifyEventClearEn; ///< Hardware clear TIMA_ when TIMA_HTSSR0 register Specify event trigger + en_functional_state_t enAnotherUnitTrigRisingClearEn; ///< Hardware clear TIMA_ when unit n TRIG port sample rising when current unit is m. + en_functional_state_t enAnotherUnitTrigFallingClearEn; ///< Hardware clear TIMA_ when unit n TRIG port sample falling when current unit is m. + en_functional_state_t enChannel3RisingClearEn; ///< Hardware clear TIMA_ when TIMA__PWM3 sample rising edge + en_functional_state_t enChannel3FallingClearEn; ///< Hardware clear TIMA_ when TIMA__PWM3 sample falling edge +} stc_timera_hw_clear_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware trigger init structure definition + ******************************************************************************/ +typedef struct stc_timera_hw_trigger_init +{ + stc_timera_hw_startup_config_t stcHwStartup; ///< Hardware startup condition config + stc_timera_hw_stop_config_t stcHwStop; ///< Hardware stop condition config + stc_timera_hw_clear_config_t stcHwClear; ///< Hardware clear condition config +} stc_timera_hw_trigger_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t TIMERA_DeInit(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_BaseInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_base_init_t *pstcBaseInit); +en_result_t TIMERA_SetCurrCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Cnt); +uint16_t TIMERA_GetCurrCount(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_SetPeriodValue(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Period); +uint16_t TIMERA_GetPeriodValue(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_SyncStartupCmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta); +en_result_t TIMERA_Cmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta); + +/* Compare output functions */ +en_result_t TIMERA_CompareInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_compare_init_t *pstcCompareInit); +en_result_t TIMERA_SetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareVal); +uint16_t TIMERA_GetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel); +en_result_t TIMERA_SetCacheValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareCache); +en_result_t TIMERA_CompareCacheCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); +en_result_t TIMERA_SpecifyOutputSta(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_timera_specify_output_t enOutputSta); +en_result_t TIMERA_CompareCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); + +/* Capture input functions */ +en_result_t TIMERA_CaptureInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_capture_init_t *pstcCapInit); +en_result_t TIMERA_CaptureFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta); +uint16_t TIMERA_GetCaptureValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel); + +/* Orthogonal coding functions */ +en_result_t TIMERA_OrthogonalCodingInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_orthogonal_coding_init_t *pstcCodingInit); +en_result_t TIMERA_SetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16CodingCnt); +uint16_t TIMERA_GetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_OrthogonalCodingFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta); + +/* Hardware control functions */ +en_result_t TIMERA_HwTriggerInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_trigger_init_t *pstcHwTriggerInit); +en_result_t TIMERA_HwStartupConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_startup_config_t *pstcHwStartup); +en_result_t TIMERA_HwStopConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_stop_config_t *pstcHwStop); +en_result_t TIMERA_HwClearConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_clear_config_t *pstcHwClear); + +/* interrupt and flags functions */ +en_result_t TIMERA_IrqCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_irq_type_t enIrq, + en_functional_state_t enNewSta); +en_flag_status_t TIMERA_GetFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag); +en_result_t TIMERA_ClearFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag); + +/* Event config functions */ +en_result_t TIMERA_EventCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); +en_result_t TIMERA_SetCountTriggerSrc(en_event_src_t enTriggerSrc); +en_result_t TIMERA_SetCaptureTriggerSrc(en_event_src_t enTriggerSrc); +en_result_t TIMERA_CountComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta); +en_result_t TIMERA_CaptureComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta); + +//@} // TimeraGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_TIMERA_ENABLE */ + +#endif /* __HC32F460_TIMERA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_trng.h b/driver/inc/hc32f460_trng.h new file mode 100644 index 0000000..6131a9c --- /dev/null +++ b/driver/inc/hc32f460_trng.h @@ -0,0 +1,100 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_trng.h + ** + ** A detailed description is available at + ** @link TrngGroup Trng description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Trng. + ** + ******************************************************************************/ +#ifndef __HC32F460_TRNG_H__ +#define __HC32F460_TRNG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_TRNG_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup TrngGroup True Random Number Generator(TRNG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* The data register loads the new initial value from the random number + generator before the random number is generated. */ +typedef enum en_trng_load_ctrl +{ + TrngLoadNewInitValue_Disable = 0x0, ///< Disable load new initial values. + TrngLoadNewInitValue_Enable = 0x1, ///< Enable load new initial values. +} en_trng_load_ctrl_t; + +/* Shift n times when capturing random noise. */ +typedef enum en_trng_shift_cnt +{ + TrngShiftCount_32 = 0x3, ///< Shift 32 times when capturing random noise. + TrngShiftCount_64 = 0x4, ///< Shift 64 times when capturing random noise. + TrngShiftCount_128 = 0x5, ///< Shift 128 times when capturing random noise. + TrngShiftCount_256 = 0x6, ///< Shift 256 times when capturing random noise. +} en_trng_shift_cnt_t; + +/* TRNG initialization structure definition. */ +typedef struct stc_trng_init +{ + en_trng_load_ctrl_t enLoadCtrl; ///< @ref en_trng_load_ctrl_t. + en_trng_shift_cnt_t enShiftCount; ///< @ref en_trng_shift_cnt_t. +} stc_trng_init_t; + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +en_result_t TRNG_Init(const stc_trng_init_t *pstcInit); +void TRNG_DeInit(void); +en_result_t TRNG_Generate(uint32_t *pu32Random, uint8_t u8Length, uint32_t u32Timeout); + +void TRNG_StartIT(void); +void TRNG_GetRandomNum(uint32_t *pu32Random, uint8_t u8Length); + +//@} // TrngGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_TRNG_ENABLE */ + +#endif /* __HC32F460_TRNG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_usart.h b/driver/inc/hc32f460_usart.h new file mode 100644 index 0000000..1447455 --- /dev/null +++ b/driver/inc/hc32f460_usart.h @@ -0,0 +1,359 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_usart.h + ** + ** A detailed description is available at + ** @link UsartGroup USART description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of USART. + ** + ******************************************************************************/ +#ifndef __HC32F460_USART_H__ +#define __HC32F460_USART_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_USART_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup UsartGroup Universal Synchronous Asynchronous Receiver \ + ** Transmitter(USART) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief USART tx mode in multiple processor mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_mp_tx_mode +{ + UsartMpTxData = 0u, ///< USART Send data in multiple-processor mode + UsartMpTxId = 1u, ///< USART Send ID in multiple-processor mode +} en_usart_mp_tx_mode_t; + +/** + ******************************************************************************* + ** \brief USART clock prescale enumeration + ** + ******************************************************************************/ +typedef enum en_usart_clk_div +{ + UsartClkDiv_1 = 0u, ///< PCLK/1 + UsartClkDiv_4 = 1u, ///< PCLK/4 + UsartClkDiv_16 = 2u, ///< PCLK/16 + UsartClkDiv_64 = 3u, ///< PCLK/64 +} en_usart_clk_div_t; + +/** + ****************************************************************************** + ** \brief USART mode + ** + ******************************************************************************/ +typedef enum en_usart_mode +{ + UsartUartMode = 0u, ///< UART mode + UsartClkSyncMode = 1u, ///< Clock sync mode + UsartSmartCardMode = 2u, ///< Smart card mode +} en_usart_mode_t; + +/** + ****************************************************************************** + ** \brief USART data direction + ** + ******************************************************************************/ +typedef enum en_usart_data_dir +{ + UsartDataLsbFirst = 0u, ///< LSB first + UsartDataMsbFirst = 1u, ///< MSB first +} en_usart_data_dir_t; + +/** + ****************************************************************************** + ** \brief USART sample mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sample_mode +{ + UsartSampleBit16 = 0u, ///< 16 Bit + UsartSampleBit8 = 1u, ///< 8 Bit +} en_usart_sample_mode_t; + +/** + ****************************************************************************** + ** \brief USART data length enumeration + ** + ******************************************************************************/ +typedef enum en_usart_data_len +{ + UsartDataBits8 = 0u, ///< 8 Bit + UsartDataBits9 = 1u, ///< 9 Bit +} en_usart_data_len_t; + +/** + ****************************************************************************** + ** \brief USART parity format enumeration + ** + ******************************************************************************/ +typedef enum en_usart_parity +{ + UsartParityNone = 0u, ///< No parity bit is used. + UsartParityEven = 1u, ///< Even parity bit is used. + UsartParityOdd = 2u, ///< Odd parity bit is used. +} en_usart_parity_t; + +/** + ****************************************************************************** + ** \brief USART functions enumeration + ** + ******************************************************************************/ +typedef enum en_usart_func +{ + UsartRx = 0u, ///< UART RX function + UsartRxInt = 1u, ///< USART RX interrupt function + UsartTx = 2u, ///< UART TX function + UsartTxEmptyInt = 3u, ///< USART TX empty interrupt function + UsartTimeOut = 4u, ///< UART RX timeout function + UsartTimeOutInt = 5u, ///< UART RX timeout interrupt function + UsartSilentMode = 6u, ///< USART silent function + UsartTxCmpltInt = 7u, ///< USART TX complete interrupt function + UsartTxAndTxEmptyInt = 8u, ///< USART TX function and USART TX empty interrupt function + UsartParityCheck = 9u, ///< USART Parity check function + UsartNoiseFilter = 10u, ///< USART noise filter function + UsartFracBaudrate = 11u, ///< USART fractional baudrate function + UsartMulProcessor = 12u, ///< USART multiple processor function + UsartSmartCard = 13u, ///< USART smart card mode function + UsartCts = 14u, ///< USART CTS function +} en_usart_func_t; + +/** + ******************************************************************************* + ** \brief USART status type enumeration + ** + ******************************************************************************/ +typedef enum en_usart_status +{ + UsartParityErr = (1u << 0), ///< USART parity error + UsartFrameErr = (1u << 1), ///< USART receive frame error + UsartOverrunErr = (1u << 3), ///< USART receive over-run error + UsartRxNoEmpty = (1u << 5), ///< USART data receive register is not empty + UsartTxComplete = (1u << 6), ///< USART transfer completely + UsartTxEmpty = (1u << 7), ///< USART data transfer register is empty + UsartRxTimeOut = (1u << 8), ///< USART data receive timeout + UsartRxMpb = (1u << 16), ///< USART multiple processor id or normal data, 0: receive date; 1: received ID +} en_usart_status_t; + +/** + ******************************************************************************* + ** \brief USART Stop bit length select enumeration + ** + ******************************************************************************/ +typedef enum en_usart_stop_bit +{ + UsartOneStopBit = 0u, ///< 1 Stop Bit + UsartTwoStopBit = 1u, ///< 2 Stop Bit +} en_usart_stop_bit_t; + +/** + ******************************************************************************* + ** \brief USART start bit detect mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sb_detect_mode +{ + UsartStartBitLowLvl = 0u, ///< Start bit: RD pin low level + UsartStartBitFallEdge = 1u, ///< Start bit: RD pin falling edge +} en_usart_sb_detect_mode_t; + +/** + ******************************************************************************* + ** \brief USART clock mode selection enumeration + ** + ******************************************************************************/ +typedef enum en_usart_clk_mode +{ + UsartIntClkCkNoOutput = 0u, ///< Select internal clock source and don't output clock. + UsartIntClkCkOutput = 1u, ///< Select internal clock source and output clock. + UsartExtClk = 2u, ///< Select external clock source. +} en_usart_clk_mode_t; + +/** + ******************************************************************************* + ** \brief USART smart-card mode selection enumeration + ** + ******************************************************************************/ +typedef enum en_usart_hw_flow_ctrl +{ + UsartRtsEnable = 0u, ///< Enable RTS function. + UsartCtsEnable = 1u, ///< Enable CTS function. +} en_usart_hw_flow_ctrl_t; + +/** + ****************************************************************************** + ** \brief USART etu clocks of smart card enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sc_etu_clk +{ + UsartScEtuClk32 = 0u, ///< 1 etu = 32/f + UsartScEtuClk64 = 1u, ///< 1 etu = 64/f + UsartScEtuClk128 = 3u, ///< 1 etu = 128/f + UsartScEtuClk256 = 5u, ///< 1 etu = 256/f + UsartScEtuClk372 = 6u, ///< 1 etu = 372/f +} en_usart_sc_etu_clk_t; + +/** + ******************************************************************************* + ** \brief Uart mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_uart_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_len_t enDataLength; ///< 8/9 Bit character length and this parameter can be a value of @ref en_usart_data_len_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t + + en_usart_stop_bit_t enStopBit; ///< Stop bit and this parameter can be a value of @ref en_usart_stop_bit_t + + en_usart_parity_t enParity; ///< Parity format and this parameter can be a value of @ref en_usart_parity_t + + en_usart_sample_mode_t enSampleMode; ///< USART sample mode, and this parameter can be a value of @ref en_usart_sample_mode_t + + en_usart_sb_detect_mode_t enDetectMode; ///< USART start bit detect mode and this parameter can be a value of @ref en_usart_sb_detect_mode_t + + en_usart_hw_flow_ctrl_t enHwFlow; ///< Hardware flow control and this parameter can be a value of @ref en_usart_hw_flow_ctrl_t +} stc_usart_uart_init_t; + +/** + ******************************************************************************* + ** \brief Clock sync mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_clksync_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t + + en_usart_hw_flow_ctrl_t enHwFlow; ///< Hardware flow control and this parameter can be a value of @ref en_usart_hw_flow_ctrl_t +} stc_usart_clksync_init_t; + +/** + ******************************************************************************* + ** \brief Smart card mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_sc_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t +} stc_usart_sc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t USART_UART_Init(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInitCfg); +en_result_t USART_CLKSYNC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_clksync_init_t *pstcInitCfg); +en_result_t USART_SC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_sc_init_t *pstcInitCfg); +en_result_t USART_DeInit(M4_USART_TypeDef *USARTx); +en_flag_status_t USART_GetStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus); +en_result_t USART_ClearStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus); +en_result_t USART_FuncCmd(M4_USART_TypeDef *USARTx, + en_usart_func_t enFunc, + en_functional_state_t enCmd); +en_result_t USART_SetParity(M4_USART_TypeDef *USARTx, + en_usart_parity_t enParity); +en_usart_parity_t USART_GetParity(M4_USART_TypeDef *USARTx); +en_result_t USART_SetOverSampling(M4_USART_TypeDef *USARTx, + en_usart_sample_mode_t enSampleMode); +en_usart_sample_mode_t USART_GetOverSampling(M4_USART_TypeDef *USARTx); +en_result_t USART_SetDataDirection(M4_USART_TypeDef *USARTx, + en_usart_data_dir_t enDir); +en_usart_data_dir_t USART_GetTransferDirection(M4_USART_TypeDef *USARTx); +en_result_t USART_SetDataLength(M4_USART_TypeDef *USARTx, + en_usart_data_len_t enDataLen); +en_usart_data_len_t USART_GetDataLength(M4_USART_TypeDef *USARTx); +en_result_t USART_SetClkMode(M4_USART_TypeDef *USARTx, + en_usart_clk_mode_t enClkMode); +en_usart_clk_mode_t USART_GetClkMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetMode(M4_USART_TypeDef *USARTx, + en_usart_mode_t enMode); +en_usart_mode_t USART_GetMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetStopBitsLength(M4_USART_TypeDef *USARTx, + en_usart_stop_bit_t enStopBit); +en_usart_stop_bit_t USART_GetStopBitsLength(M4_USART_TypeDef *USARTx); +en_result_t USART_SetSbDetectMode(M4_USART_TypeDef *USARTx, + en_usart_sb_detect_mode_t enDetectMode); +en_usart_sb_detect_mode_t USART_GetSbDetectMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, + en_usart_hw_flow_ctrl_t enHwFlowCtrl); +en_usart_hw_flow_ctrl_t USART_GetHwFlowCtrl(M4_USART_TypeDef *USARTx); +en_result_t USART_SetClockDiv(M4_USART_TypeDef *USARTx, + en_usart_clk_div_t enClkPrescale); +en_usart_clk_div_t USART_GetClockDiv(M4_USART_TypeDef *USARTx); +en_result_t USART_SetScEtuClk(M4_USART_TypeDef *USARTx, + en_usart_sc_etu_clk_t enEtuClk); +en_usart_sc_etu_clk_t USART_GetScEtuClk(M4_USART_TypeDef *USARTx); +en_result_t USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data); +uint16_t USART_RecData(M4_USART_TypeDef *USARTx); +en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); + +//@} // UsartGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_USART_ENABLE */ + +#endif /* __HC32F460_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_utility.h b/driver/inc/hc32f460_utility.h new file mode 100644 index 0000000..d4eda98 --- /dev/null +++ b/driver/inc/hc32f460_utility.h @@ -0,0 +1,108 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_utility.h + ** + ** A detailed description is available at + ** @link DdlUtilityGroup Ddl Utility description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library Utility. + ** + ******************************************************************************/ +#ifndef __HC32F460_UTILITY_H__ +#define __HC32F460_UTILITY_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_UTILITY_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DdlUtilityGroup Device Driver Library Utility(DDLUTILITY) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/* A approximate delay */ +void Ddl_Delay1ms(uint32_t u32Cnt); +void Ddl_Delay1us(uint32_t u32Cnt); + +/* Systick functions */ +en_result_t SysTick_Init(uint32_t u32Freq); +void SysTick_Delay(uint32_t u32Delay); +void SysTick_IncTick(void); +uint32_t SysTick_GetTick(void); +void SysTick_Suspend(void); +void SysTick_Resume(void); + +/*! Ddl assert, you can add your own assert functions by implement the function +Ddl_AssertHook definition follow the function Ddl_AssertHook declaration */ +#ifdef __DEBUG +#define DDL_ASSERT(x) \ +do{ \ + ((x) ? (void)0 : Ddl_AssertHandler((uint8_t *)__FILE__, __LINE__)); \ +}while(0) +/* Exported function */ +void Ddl_AssertHandler(uint8_t *file, int16_t line); +#else +#define DDL_ASSERT(x) (void)(0) +#endif /* __DEBUG */ + +#if (DDL_PRINT_ENABLE == DDL_ON) +#include + +en_result_t UART_PrintfInit(M4_USART_TypeDef *UARTx, + uint32_t u32Baudrate, + void (*PortInit)(void)); + +#define DDL_PrintfInit (void)UART_PrintfInit +#define DDL_Printf (void)printf +#else +#define DDL_PrintfInit(x, y, z) +#define DDL_Printf(fmt, ...) +#endif + +//@} // DdlUtilityGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_UTILITY_ENABLE */ + +#endif /* __HC32F460_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/inc/hc32f460_wdt.h b/driver/inc/hc32f460_wdt.h new file mode 100644 index 0000000..0ae3521 --- /dev/null +++ b/driver/inc/hc32f460_wdt.h @@ -0,0 +1,162 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_wdt.h + ** + ** A detailed description is available at + ** @link WdtGroup Watchdog Counter description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of WDT. + ** + ******************************************************************************/ +#ifndef __HC32F460_WDT_H__ +#define __HC32F460_WDT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_WDT_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup WdtGroup WatchDog Counter(WDT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief WDT count cycle enumeration + ******************************************************************************/ +typedef enum en_wdt_count_cycle +{ + WdtCountCycle256 = 0u, ///< 256 cycle + WdtCountCycle4096 = 1u, ///< 4096 cycle + WdtCountCycle16384 = 2u, ///< 16384 cycle + WdtCountCycle65536 = 3u, ///< 65536 cycle +} en_wdt_count_cycle_t; + +/** + ******************************************************************************* + ** \brief WDT count clock division enumeration + ******************************************************************************/ +typedef enum en_wdt_clk_div +{ + WdtPclk3Div4 = 2u, ///< PCLK3/4 + WdtPclk3Div64 = 6u, ///< PCLK3/64 + WdtPclk3Div128 = 7u, ///< PCLK3/128 + WdtPclk3Div256 = 8u, ///< PCLK3/256 + WdtPclk3Div512 = 9u, ///< PCLK3/512 + WdtPclk3Div1024 = 10u, ///< PCLK3/1024 + WdtPclk3Div2048 = 11u, ///< PCLK3/2048 + WdtPclk3Div8192 = 13u, ///< PCLK3/8192 +} en_wdt_clk_div_t; + +/** + ******************************************************************************* + ** \brief WDT allow refresh percent range enumeration + ******************************************************************************/ +typedef enum en_wdt_refresh_range +{ + WdtRefresh100Pct = 0u, ///< 100% + WdtRefresh0To25Pct = 1u, ///< 0%~25% + WdtRefresh25To50Pct = 2u, ///< 25%~50% + WdtRefresh0To50Pct = 3u, ///< 0%~50% + WdtRefresh50To75Pct = 4u, ///< 50%~75% + WdtRefresh0To25PctAnd50To75Pct = 5u, ///< 0%~25% & 50%~75% + WdtRefresh25To75Pct = 6u, ///< 25%~75% + WdtRefresh0To75Pct = 7u, ///< 0%~75% + WdtRefresh75To100Pct = 8u, ///< 75%~100% + WdtRefresh0To25PctAnd75To100Pct = 9u, ///< 0%~25% & 75%~100% + WdtRefresh25To50PctAnd75To100Pct = 10u, ///< 25%~50% & 75%~100% + WdtRefresh0To50PctAnd75To100Pct = 11u, ///< 0%~50% & 75%~100% + WdtRefresh50To100Pct = 12u, ///< 50%~100% + WdtRefresh0To25PctAnd50To100Pct = 13u, ///< 0%~25% & 50%~100% + WdtRefresh25To100Pct = 14u, ///< 25%~100% + WdtRefresh0To100Pct = 15u, ///< 0%~100% +} en_wdt_refresh_range_t; + +/** + ******************************************************************************* + ** \brief WDT refresh error or count underflow trigger event type enumeration + ******************************************************************************/ +typedef enum en_wdt_event_request_type +{ + WdtTriggerInterruptRequest = 0u, ///< Interrupt request + WdtTriggerResetRequest = 1u, ///< Reset request +} en_wdt_event_request_type_t; + +/** + ******************************************************************************* + ** \brief WDT flag type enumeration + ******************************************************************************/ +typedef enum en_wdt_flag_type +{ + WdtFlagCountUnderflow = 0u, ///< Count underflow flag + WdtFlagRefreshError = 1u, ///< Refresh error flag +} en_wdt_flag_type_t; + +/** + ******************************************************************************* + ** \brief WDT init structure definition + ******************************************************************************/ +typedef struct stc_wdt_init +{ + en_wdt_count_cycle_t enCountCycle; ///< Count cycle + en_wdt_clk_div_t enClkDiv; ///< Count clock division + en_wdt_refresh_range_t enRefreshRange; ///< Allow refresh percent range + en_functional_state_t enSleepModeCountEn; ///< Enable/disable count in the sleep mode + en_wdt_event_request_type_t enRequestType; ///< Refresh error or count underflow trigger event type +} stc_wdt_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit); +en_result_t WDT_RefreshCounter(void); +uint16_t WDT_GetCountValue(void); + +/* Flags functions */ +en_flag_status_t WDT_GetFlag(en_wdt_flag_type_t enFlag); +en_result_t WDT_ClearFlag(en_wdt_flag_type_t enFlag); + +//@} // WdtGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_WDT_ENABLE */ + +#endif /* __HC32F460_WDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_adc.c b/driver/src/hc32f460_adc.c new file mode 100644 index 0000000..da61a4c --- /dev/null +++ b/driver/src/hc32f460_adc.c @@ -0,0 +1,1739 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_adc.c + ** + ** A detailed description is available at + ** @link AdcGroup Adc description @endlink + ** + ** - 2018-11-30 CDT First version for Device Driver Library of Adc. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_adc.h" +#include "hc32f460_utility.h" + +#if (DDL_ADC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup AdcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for ADC peripherals. */ +#define IS_ADC_PERIPH(ADCx) \ +( ((ADCx) == M4_ADC1) || \ + ((ADCx) == M4_ADC2)) + +/*! Parameter validity check for ADC1 channel index. */ +#define IS_ADC1_CH_INDEX(x) \ +( ((x) < ADC1_CH_COUNT)) + +/*! Parameter validity check for ADC2 channel index. */ +#define IS_ADC2_CH_INDEX(x) \ +( ((x) < ADC2_CH_COUNT)) + +/*! Parameter validity check for ADC average count. */ +#define IS_ADC_AVCNT(AVCNT) \ +( ((AVCNT) == AdcAvcnt_2) || \ + (((AVCNT) >= AdcAvcnt_4) && ((AVCNT) <= AdcAvcnt_256))) + +/*! Parameter validity check for ADC data alignment. */ +#define IS_ADC_DATA_ALIGN(ALIGN) \ +( ((ALIGN) == AdcDataAlign_Right) || \ + ((ALIGN) == AdcDataAlign_Left)) + +/*! Parameter validity check for ADC auto clear DR. */ +#define IS_ADC_CLREN(EN) \ +( ((EN) == AdcClren_Enable) || \ + ((EN) == AdcClren_Disable)) + +/*! Parameter validity check for ADC resolution. */ +#define IS_ADC_RESOLUTION(RESOLUTION) \ +( ((RESOLUTION) == AdcResolution_8Bit) || \ + ((RESOLUTION) == AdcResolution_10Bit) || \ + ((RESOLUTION) == AdcResolution_12Bit)) + +/*! Parameter validity check for ADC scan convert mode. */ +#define IS_ADC_SCAN_MODE(MODE) \ +( ((MODE) == AdcMode_SAOnce) || \ + ((MODE) == AdcMode_SAContinuous) || \ + ((MODE) == AdcMode_SAOnceSBOnce) || \ + ((MODE) == AdcMode_SAContinuousSBOnce)) + +/*! Parameter validity check for ADC RSCHSEL. */ +#define IS_ADC_RSCHSEL(SEL) \ +( ((SEL) == AdcRschsel_Continue) || \ + ((SEL) == AdcRschsel_Restart)) + +/*! Parameter validity check for ADC SA trigger source. */ +#define IS_ADC_TRGEN(EN) \ +( ((EN) == AdcTrgen_Enable) || \ + ((EN) == AdcTrgen_Disable)) + +/*! Parameter validity check for ADC SA trigger source. */ +#define IS_ADC_TRGSEL(SEL) \ +( ((SEL) == AdcTrgsel_ADTRGX) || \ + ((SEL) == AdcTrgsel_TRGX0) || \ + ((SEL) == AdcTrgsel_TRGX1) || \ + ((SEL) == AdcTrgsel_TRGX0_TRGX1)) + +/*! Parameter validity check for ADC common trigger. */ +#define IS_ADC_COM_TRIGGER(x) \ +( ((x) == AdcComTrigger_1) || \ + ((x) == AdcComTrigger_2) || \ + ((x) == AdcComTrigger_1_2)) + +/*! Parameter validity check for ADC EOCAIEN/ENCBIEN. */ +#define IS_ADC_EOCIEN(EN) \ +( ((EN) == AdcEocien_Disable) || \ + ((EN) == AdcEocien_Enable)) + +/*! Parameter validity check for ADC sampling time. */ +#define IS_ADC_SAMPLE_TIME(TIME) \ +( ((TIME) == 255u) || \ + (((TIME) >= 5u) && ((TIME) <= 254u))) + +/*! Parameter validity check for ADC sync trigger mode. */ +#define IS_ADC_SYNC_MODE(MODE) \ +( ((MODE) == AdcSync_SingleSerial) || \ + ((MODE) == AdcSync_SingleParallel) || \ + ((MODE) == AdcSync_ContinuousSerial) || \ + ((MODE) == AdcSync_ContinuousParallel)) + +/*! Parameter validity check for ADC sync able. */ +#define IS_ADC_SYNC_ENABLE(EN) \ +( ((EN) == AdcSync_Disable) || \ + ((EN) == AdcSync_Enable)) + +/*! Parameter validity check for ADC ADWIEN */ +#define IS_ADC_AWDIEN(EN) \ +( ((EN) == AdcAwdInt_Disable) || \ + ((EN) == AdcAwdInt_Enable)) + +/*! Parameter validity check for ADC AWDSS */ +#define IS_ADC_AWDSS(SS) \ +( ((SS) == AdcAwdSel_SA_SB) || \ + ((SS) == AdcAwdSel_SA) || \ + ((SS) == AdcAwdSel_SB) || \ + ((SS) == AdcAwdSel_SB_SA)) + +/*! Parameter validity check for ADC AWDMD */ +#define IS_ADC_AWDMD(MD) \ +( ((MD) == AdcAwdCmpMode_0) || \ + ((MD) == AdcAwdCmpMode_1)) + +/*! Parameter validity check for ADC AWDEN */ +#define IS_ADC_AWDEN(EN) \ +( ((EN) == AdcAwd_Disable) || \ + ((EN) == AdcAwd_Enable)) + +/*! Parameter validity check for ADC PGA control */ +#define IS_ADC_PGA_CTL(CTL) \ +( ((CTL) == AdcPgaCtl_Invalid) || \ + ((CTL) == AdcPgaCtl_Amplify)) + +/*! Parameter validity check for ADC gain factor. */ +#define IS_ADC_PGA_FACTOR(FACTOR) \ +( ((FACTOR) == AdcPgaFactor_2) || \ + (((FACTOR) >= AdcPgaFactor_2P133) && ((FACTOR) <= AdcPgaFactor_32))) + +/*! Parameter validity check for ADC PGA negative. */ +#define IS_ADC_PGA_NEGATIVE(N) \ +( ((N) == AdcPgaNegative_VSSA) || \ + ((N) == AdcPgaNegative_PGAVSS)) + +/*! Parameter validity check for ADC trigger source event . */ +#define IS_ADC_TRIG_SRC_EVENT(x) \ +( ((x) == EVT_PORT_EIRQ0) || \ + (((x) > EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void ADC_ReadAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes an ADC instance. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcInit Pointer to ADC initialization structure. + ** See @ref stc_adc_init_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (NULL != pstcInit)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_RESOLUTION(pstcInit->enResolution)); + DDL_ASSERT(IS_ADC_DATA_ALIGN(pstcInit->enDataAlign)); + DDL_ASSERT(IS_ADC_CLREN(pstcInit->enAutoClear)); + DDL_ASSERT(IS_ADC_SCAN_MODE(pstcInit->enScanMode)); + DDL_ASSERT(IS_ADC_RSCHSEL(pstcInit->enRschsel)); + + /* Stop ADC conversion. */ + ADCx->STR = 0u; + + ADCx->CR0_f.ACCSEL = pstcInit->enResolution; + ADCx->CR0_f.DFMT = pstcInit->enDataAlign; + ADCx->CR0_f.CLREN = pstcInit->enAutoClear; + ADCx->CR0_f.MS = pstcInit->enScanMode; + ADCx->CR1_f.RSCHSEL = pstcInit->enRschsel; + + /* Disable EOC(End Of Conversion) interrupts default. */ + ADCx->ICR = (uint8_t)0x0; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes an ADC instance. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DeInit(M4_ADC_TypeDef *ADCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + /* Set the value of all registers to the reset value. */ + /* Stop ADC conversion. */ + ADCx->STR = 0u; + ADCx->CR0 = 0u; + ADCx->CR1 = 0u; + ADCx->TRGSR = 0u; + ADCx->CHSELRA0 = 0u; + ADCx->CHSELRB0 = 0u; + ADCx->AVCHSELR0 = 0u; + ADCx->AWDCHSR0 = 0u; + ADCx->SSTR0 = (uint8_t)0x0B; + ADCx->SSTR1 = (uint8_t)0x0B; + ADCx->SSTR2 = (uint8_t)0x0B; + ADCx->SSTR3 = (uint8_t)0x0B; + ADCx->SSTR4 = (uint8_t)0x0B; + ADCx->SSTR5 = (uint8_t)0x0B; + ADCx->SSTR6 = (uint8_t)0x0B; + ADCx->SSTR7 = (uint8_t)0x0B; + ADCx->SSTR8 = (uint8_t)0x0B; + ADCx->CHMUXR0 = (uint16_t)0x3210; + ADCx->CHMUXR1 = (uint16_t)0x7654; + ADCx->ISR = 0u; + ADCx->ICR = (uint8_t)0x03; + ADCx->AWDCR = 0u; + ADCx->AWDDR0 = 0u; + ADCx->AWDDR1 = 0u; + ADCx->AWDCHSR0 = 0u; + ADCx->AWDSR0 = 0u; + + if (M4_ADC1 == ADCx) + { + ADCx->CHSELRA1 = 0u; + ADCx->CHSELRB1 = 0u; + ADCx->AVCHSELR1 = 0u; + ADCx->CHMUXR2 = (uint16_t)0xBA98; + ADCx->CHMUXR3 = (uint16_t)0xFEDC; + ADCx->SYNCCR = (uint16_t)0x0C00; + ADCx->AWDCHSR1 = 0u; + ADCx->AWDSR1 = 0u; + ADCx->PGACR = 0u; + ADCx->PGAGSR = 0u; + ADCx->PGAINSR0 = 0u; + ADCx->PGAINSR1 = 0u; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set scan mode. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param[in] enMode See @ref en_adc_scan_mode_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_SetScanMode(M4_ADC_TypeDef *ADCx, en_adc_scan_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_SCAN_MODE(enMode)); + + ADCx->CR0_f.MS = enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcTrgCfg Pointer to ADC trigger source configuration structure. + ** \arg u8Sequence The sequence which you want to set it's trigger source. + ** \arg enTrgEnable Enable or disable trigger source. + ** \arg enTrgSel The type of trigger source. + ** \arg enInTrg0 Event number @ref en_event_src_t. + ** \arg enInTrg1 Event number @ref en_event_src_t. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** \note Sequence A and Sequence B CAN NOT set the same trigger source. + ** + ******************************************************************************/ +en_result_t ADC_ConfigTriggerSrc(M4_ADC_TypeDef *ADCx, + const stc_adc_trg_cfg_t *pstcTrgCfg) +{ + uint32_t u32TrgSelR; + __IO uint32_t *io32AdcxTrgSelR0; + __IO uint32_t *io32AdcxTrgSelR1; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && + (NULL != pstcTrgCfg) && + (pstcTrgCfg->u8Sequence <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_TRGSEL(pstcTrgCfg->enTrgSel)); + + if (ADC_SEQ_A == pstcTrgCfg->u8Sequence) + { + ADCx->TRGSR_f.TRGSELA = pstcTrgCfg->enTrgSel; + } + else + { + ADCx->TRGSR_f.TRGSELB = pstcTrgCfg->enTrgSel; + } + + if (AdcTrgsel_ADTRGX != pstcTrgCfg->enTrgSel) + { + if (M4_ADC1 == ADCx) + { + io32AdcxTrgSelR0 = &(M4_AOS->ADC1_ITRGSELR0); + io32AdcxTrgSelR1 = &(M4_AOS->ADC1_ITRGSELR1); + } + else + { + io32AdcxTrgSelR0 = &(M4_AOS->ADC2_ITRGSELR0); + io32AdcxTrgSelR1 = &(M4_AOS->ADC2_ITRGSELR1); + } + + if ((pstcTrgCfg->enTrgSel & AdcTrgsel_TRGX0) == AdcTrgsel_TRGX0) + { + DDL_ASSERT(IS_ADC_TRIG_SRC_EVENT(pstcTrgCfg->enInTrg0)); + + u32TrgSelR = *io32AdcxTrgSelR0; + u32TrgSelR &= ~0x1FFul; + u32TrgSelR |= pstcTrgCfg->enInTrg0; + *io32AdcxTrgSelR0 = u32TrgSelR; + } + if ((pstcTrgCfg->enTrgSel & AdcTrgsel_TRGX1) == AdcTrgsel_TRGX1) + { + DDL_ASSERT(IS_ADC_TRIG_SRC_EVENT(pstcTrgCfg->enInTrg1)); + + u32TrgSelR = *io32AdcxTrgSelR1; + u32TrgSelR &= ~0x1FFul; + u32TrgSelR |= pstcTrgCfg->enInTrg1; + *io32AdcxTrgSelR1 = u32TrgSelR; + } + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to set it's trigger source. + ** + ** \param [in] enState Enable or disable trigger source. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_TriggerSrcCmd(M4_ADC_TypeDef *ADCx, + uint8_t u8Seq, + en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (u8Seq <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (ADC_SEQ_A == u8Seq) + { + ADCx->TRGSR_f.TRGENA = enState; + } + else + { + ADCx->TRGSR_f.TRGENB = enState; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC common trigger. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enTrgSel ADC trigger source type. See @ref en_adc_trgsel_t for details. + ** + ** \param [in] enComTrigger ADC common trigger selection. See @ref en_adc_com_trigger_t for details. + ** + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, en_adc_trgsel_t enTrgSel, \ + en_adc_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = enComTrigger; + uint32_t u32ITRGSELRAddr; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_TRGSEL(enTrgSel) && (enTrgSel != AdcTrgsel_ADTRGX)); + DDL_ASSERT(IS_ADC_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (M4_ADC1 == ADCx) + { + u32ITRGSELRAddr = (uint32_t)&M4_AOS->ADC1_ITRGSELR0; + } + else + { + u32ITRGSELRAddr = (uint32_t)&M4_AOS->ADC2_ITRGSELR0; + } + + u32ComTrig <<= 30u; + + if ((enTrgSel & AdcTrgsel_TRGX0) == AdcTrgsel_TRGX0) + { + if (enState == Enable) + { + *(__IO uint32_t *)u32ITRGSELRAddr |= u32ComTrig; + } + else + { + *(__IO uint32_t *)u32ITRGSELRAddr &= ~u32ComTrig; + } + } + + if ((enTrgSel & AdcTrgsel_TRGX1) == AdcTrgsel_TRGX1) + { + u32ITRGSELRAddr += 4ul; + if (enState == Enable) + { + *(__IO uint32_t *)u32ITRGSELRAddr |= u32ComTrig; + } + else + { + *(__IO uint32_t *)u32ITRGSELRAddr &= ~u32ComTrig; + } + } +} + +/** + ******************************************************************************* + ** \brief Add ADC channel. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcChCfg Pointer to ADC channel configuration structure. + ** \arg u32Channel The channel(s) you want to configure. + ** \arg u8Sequence The sequence which the channel(s) belong(s) to. + ** \arg pu8SampTime Pointer to sampling time. + ** eg. u32Channel = 1001b + ** pu8SampTime[0] = channel 0's time + ** pu8SampTime[1] = channel 3's time + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** \note Sequence A and Sequence B CAN NOT set the same channel!!! + ** + ******************************************************************************/ +en_result_t ADC_AddAdcChannel(M4_ADC_TypeDef *ADCx, const stc_adc_ch_cfg_t *pstcChCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t j; + uint32_t u32ChannelSel; + __IO uint8_t *io8Sstr; + + if ((NULL != ADCx) && + (NULL != pstcChCfg) && + (pstcChCfg->u8Sequence <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32ChannelSel = pstcChCfg->u32Channel & ADC1_CH_ALL; + if (ADC_SEQ_A == pstcChCfg->u8Sequence) + { + ADCx->CHSELRA0 |= (uint16_t)u32ChannelSel; + ADCx->CHSELRA1 |= (uint16_t)(u32ChannelSel >> 16u); + } + else + { + ADCx->CHSELRB0 |= (uint16_t)u32ChannelSel; + ADCx->CHSELRB1 |= (uint16_t)(u32ChannelSel >> 16u); + } + } + else + { + u32ChannelSel = pstcChCfg->u32Channel & ADC2_CH_ALL; + if (ADC_SEQ_A == pstcChCfg->u8Sequence) + { + ADCx->CHSELRA0 |= (uint16_t)u32ChannelSel; + } + else + { + ADCx->CHSELRB0 |= (uint16_t)u32ChannelSel; + } + } + + /* Set sampling time */ + i = 0u; + j = 0u; + io8Sstr = &(ADCx->SSTR0); + while (0u != u32ChannelSel) + { + if (u32ChannelSel & 0x1ul) + { + io8Sstr[i] = pstcChCfg->pu8SampTime[j++]; + } + u32ChannelSel >>= 1u; + i++; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete ADC channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s) you want to delete. + ** \arg ADC1_CH0 ~ ADC1_CH16 + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note You can use this function to delete ADC channel(s) + ** and then set the corresponding pin(s) of the channel(s) + ** to the other mode you need in your application. + ** + ******************************************************************************/ +en_result_t ADC_DelAdcChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->CHSELRA0 &= (uint16_t)(~u16ChSelR0); + ADCx->CHSELRB0 &= (uint16_t)(~u16ChSelR0); + + if (M4_ADC1 == ADCx) + { + ADCx->CHSELRA1 &= (uint16_t)(~u16ChSelR1); + ADCx->CHSELRB1 &= (uint16_t)(~u16ChSelR1); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC interrupt configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence to be configured. + ** + ** \param [in] enState Enable or Disable sequence conversion done interrupt. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_SeqITCmd(M4_ADC_TypeDef *ADCx, + uint8_t u8Seq, + en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8Msk = 0u; + + if ((NULL != ADCx) && (u8Seq <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + u8Msk = (uint8_t)(0x1ul << u8Seq); + ADCx->ISR &= (uint8_t)(~u8Msk); + + if (Enable == enState) + { + ADCx->ICR |= u8Msk; + } + else + { + ADCx->ICR &= (uint8_t)(~u8Msk); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC average conversion configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enAvgCnt Average after enAvgCnt conversions. + ** See @ref en_adc_avcnt_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ConfigAvg(M4_ADC_TypeDef *ADCx, en_adc_avcnt_t enAvgCnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_AVCNT(enAvgCnt)); + + ADCx->CR0_f.AVCNT = enAvgCnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Add average channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s), which will be set as average channel(s). + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note The channel must first be configured as an analog channel + ** by function ADC_AddAdcChannel. + ** + ******************************************************************************/ +en_result_t ADC_AddAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16AvgChR0; + uint16_t u16AvgChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel &= ADC1_CH_ALL; + } + else + { + u32Channel &= ADC2_CH_ALL; + } + + u16AvgChR0 = (uint16_t)u32Channel; + u16AvgChR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AVCHSELR0 |= u16AvgChR0; + if (M4_ADC1 == ADCx) + { + ADCx->AVCHSELR1 |= u16AvgChR1; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete average channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The average channel(s) which you want to delete. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DelAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16AvgChR0; + uint16_t u16AvgChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16AvgChR0 = (uint16_t)u32Channel; + u16AvgChR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AVCHSELR0 &= (uint16_t)(~u16AvgChR0); + if (M4_ADC1 == ADCx) + { + ADCx->AVCHSELR1 &= (uint16_t)(~u16AvgChR1); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC AWD(analog watch dog) configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcAwdCfg Pointer to the configuration structure. + ** See @ref stc_adc_awd_cfg_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ConfigAwd(M4_ADC_TypeDef *ADCx, const stc_adc_awd_cfg_t *pstcAwdCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (NULL != pstcAwdCfg)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_AWDMD(pstcAwdCfg->enAwdmd)); + DDL_ASSERT(IS_ADC_AWDSS(pstcAwdCfg->enAwdss)); + + ADCx->AWDCR_f.AWDEN = AdcAwd_Disable; + ADCx->AWDCR_f.AWDIEN = AdcAwdInt_Disable; + ADCx->AWDCR_f.AWDMD = pstcAwdCfg->enAwdmd; + ADCx->AWDCR_f.AWDSS = pstcAwdCfg->enAwdss; + + ADCx->AWDDR0 = pstcAwdCfg->u16AwdDr0; + ADCx->AWDDR1 = pstcAwdCfg->u16AwdDr1; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC AWD(analog watch dog). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enState Enable or disable AWD. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_AwdCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + ADCx->AWDCR_f.AWDEN = enState; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC AWD(analog watch dog) interrupt. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enState Enable or disable AWD interrupt. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_AwdITCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + ADCx->AWDCR_f.AWDIEN = enState; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Add AWD channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s), which will be set as AWD channel(s). + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note The channel must first be configured as an analog channel + ** by function ADC_AddAdcChannel. + ** + ******************************************************************************/ +en_result_t ADC_AddAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel &= ADC1_CH_ALL; + } + else + { + u32Channel &= ADC2_CH_ALL; + } + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AWDCHSR0 |= u16ChSelR0; + if (M4_ADC1 == ADCx) + { + ADCx->AWDCHSR1 |= u16ChSelR1; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete AWD channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The AWD channel(s) which you are going to delete. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DelAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AWDCHSR0 &= (uint16_t)(~u16ChSelR0); + if (M4_ADC1 == ADCx) + { + ADCx->AWDCHSR1 &= (uint16_t)(~u16ChSelR1); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC programmable gain amplifier(PGA) configuration. + ** + ** \param [in] enFactor PGA gain factor. + ** \param [in] enNegativeIn PGA negative input select. + ** + ** \retval None. + ** + ** \note Only ADC1 has PGA. + ** + ******************************************************************************/ +void ADC_ConfigPga(en_adc_pga_factor_t enFactor, en_adc_pga_negative_t enNegativeIn) +{ + DDL_ASSERT(IS_ADC_PGA_FACTOR(enFactor)); + DDL_ASSERT(IS_ADC_PGA_NEGATIVE(enNegativeIn)); + + M4_ADC1->PGAGSR_f.GAIN = enFactor; + M4_ADC1->PGAINSR1_f.PGAVSSEN = enNegativeIn; +} + +/** + ******************************************************************************* + ** \brief Enable or disable PGA. + ** + ** \param [in] enState Enable or disable PGA. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_PgaCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (Enable == enState) + { + M4_ADC1->PGACR_f.PGACTL = AdcPgaCtl_Amplify; + } + else + { + M4_ADC1->PGACR_f.PGACTL = AdcPgaCtl_Invalid; + } +} + +/** + ******************************************************************************* + ** \brief Add PGA channel(s). + ** + ** \param[in] u32Channel The channel(s), which you want to gain. + ** + ** \retval None. + ** + ** \note Only ADC1 has PGA. The channel must first + ** be configured as an analog channel + ** by function ADC_AddAdcChannel + ** + ******************************************************************************/ +void ADC_AddPgaChannel(uint32_t u32Channel) +{ + M4_ADC1->PGAINSR0 |= ((uint16_t)(u32Channel & PGA_CH_ALL)); +} + +/** + ******************************************************************************* + ** \brief Delete PGA channel(s). + ** + ** \param[in] u32Channel The PGA channel(s) which will be deleted. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_DelPgaChannel(uint32_t u32Channel) +{ + M4_ADC1->PGAINSR0 &= (uint16_t)(~u32Channel); +} + +/** + ******************************************************************************* + ** \brief ADC sync mode configuration. + ** + ** \param [in] enMode Synchronous mode types. + ** \param [in] u8TrgDelay ADC2 trigger delay time. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ConfigSync(en_adc_sync_mode_t enMode, uint8_t u8TrgDelay) +{ + DDL_ASSERT(IS_ADC_SYNC_MODE(enMode)); + + /* Disable synchronous mode first. */ + M4_ADC1->SYNCCR_f.SYNCEN = AdcSync_Disable; + + M4_ADC1->SYNCCR_f.SYNCMD = enMode; + M4_ADC1->SYNCCR_f.SYNCDLY = u8TrgDelay; +} + +/** + ******************************************************************************* + ** \brief Enable or disable sync mode. + ** + ** \param [in] enState Enable or disable sync mode. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_SyncCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + M4_ADC1->SYNCCR_f.SYNCEN = enState; +} + +/** + ******************************************************************************* + ** \brief Start an ADC conversion. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note Software startup only support sequence A. + ** + ******************************************************************************/ +en_result_t ADC_StartConvert(M4_ADC_TypeDef *ADCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->STR = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop an ADC conversion and clear flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Timeout. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_StopConvert(M4_ADC_TypeDef *ADCx) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t u32TimeCount = 0u; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + enRet = Ok; + /* Make sure the ADC is really stopped. */ + while (ADCx->STR == 1u) + { + /* Stop ADC conversion. */ + ADCx->STR = 0u; + if (++u32TimeCount > 10000u) + { + enRet = ErrorTimeout; + break; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the conversion status flag. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to get + ** it's conversion status flag. + ** + ** \retval Set ADC converted done. + ** \retval Reset ADC is converting or parameter error. + ** + ******************************************************************************/ +en_flag_status_t ADC_GetEocFlag(const M4_ADC_TypeDef *ADCx, uint8_t u8Seq) +{ + en_flag_status_t enFlag = Reset; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (ADCx->ISR & ((uint8_t)(0x1ul << u8Seq))) + { + enFlag = Set; + } + + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear conversion status flag of sequence A or sequence B. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to clear + ** it's conversion status flag. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrEocFlag(M4_ADC_TypeDef *ADCx, uint8_t u8Seq) +{ + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->ISR &= (uint8_t)(~(0x1ul << u8Seq)); + } +} + +/** + ******************************************************************************* + ** \brief ADC start sequence A, check it's EOC status and get the data. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [out] pu16AdcData The address to store ADC value. + ** The location of the data store depends on + ** the parameter u8Length. + ** u8Length >= ADCx_CH_COUNT(ADC1_CH_COUNT or ADC2_CH_COUNT), + ** all of the ADC data regs will be read: + ** pu16AdcData[0] = data of Channel 0, + ** pu16AdcData[1] = data of Channel 1, + ** pu16AdcData[2] = data of Channel 2, + ** ... + ** u8Length < ADCx_CH_COUNT(ADC1_CH_COUNT or ADC2_CH_COUNT), + ** only the data of the enabled channles will be read: + ** pu16AdcData[0] = data of the 1st enabled channel, + ** pu16AdcData[1] = data of the 2nd enabled channel, + ** pu16AdcData[2] = data of the 3rd enabled channel, + ** ... + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Timeout. + ** \retval OperationInProgress ADC is converting. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_PollingSa(M4_ADC_TypeDef *ADCx, + uint16_t *pu16AdcData, + uint8_t u8Length, + uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8AllDataLength = 0u; + uint32_t u32Channel = 0u; + uint32_t u32AdcTimeout = 0u; + __IO uint32_t u32TimeCount = 0u; + + if ((NULL != ADCx) && (NULL != pu16AdcData) && (0u != u8Length)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + if (u8Length >= ADC1_CH_COUNT) + { + u8AllDataLength = ADC1_CH_COUNT; + } + else + { + u32Channel = (uint32_t)ADCx->CHSELRA1; + u32Channel <<= 16u; + u32Channel |= (uint32_t)ADCx->CHSELRA0; + } + } + else + { + if (u8Length >= ADC2_CH_COUNT) + { + u8AllDataLength = ADC2_CH_COUNT; + } + else + { + u32Channel = (uint32_t)M4_ADC1->CHSELRA0; + } + } + + /* Start ADC conversion. */ + ADCx->STR = (uint8_t)0x01; + + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32AdcTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32AdcTimeout) + { + if (ADCx->ISR_f.EOCAF) + { + /* Get ADC data. */ + if (u8AllDataLength) + { + ADC_ReadAllData(ADCx, pu16AdcData, u8AllDataLength); + } + else + { + ADC_GetChData(ADCx, u32Channel, pu16AdcData, u8Length); + } + + /* Clear sequence A flag. */ + ADCx->ISR_f.EOCAF = 0u; + enRet = Ok; + break; + } + u32TimeCount++; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reading all data regs of an ADC. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [out] pu16AdcData The address where the data will be stored. + ** pu16AdcData[0] = data of Channel 0, + ** pu16AdcData[1] = data of Channel 1, + ** pu16AdcData[2] = data of Channel 2, + ** ... + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length) +{ + en_result_t enRet = ErrorInvalidParameter; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + if (((M4_ADC1 == ADCx) && (u8Length >= ADC1_CH_COUNT)) || + ((M4_ADC2 == ADCx) && (u8Length >= ADC2_CH_COUNT))) + { + ADC_ReadAllData(ADCx, pu16AdcData, u8Length); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reading the data of the specified channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base + ** \arg M4_ADC1 ADC unit 1 instance register base + ** \arg M4_ADC2 ADC unit 2 instance register base + ** + ** \param [in] u32TargetCh The specified channel(s) + ** + ** \param [out] pu16AdcData The address where the data will be stored. + ** pu16AdcData[0] = data of the 1st enabled channel, + ** pu16AdcData[1] = data of the 2nd enabled channel, + ** pu16AdcData[2] = data of the 3rd enabled channel, + ** eg. u32TargetCh = 1001b + ** pu16AdcData[0] = Channel 0's data, + ** pu16AdcData[1] = Channel 3's data, + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_GetChData(const M4_ADC_TypeDef *ADCx, + uint32_t u32TargetCh, + uint16_t *pu16AdcData, + uint8_t u8Length) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t j; + uint32_t u32Channel; + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + if ((NULL != ADCx) && (NULL != pu16AdcData) && (0u != u8Length)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel = u32TargetCh & ADC1_CH_ALL; + } + else + { + u32Channel = u32TargetCh & ADC2_CH_ALL; + } + + i = 0u; + j = 0u; + while ((0u != u32Channel) && (0u != u8Length)) + { + if (0u != (u32Channel & 0x1ul)) + { + pu16AdcData[j] = pu16DataReg[i]; + j++; + u8Length--; + } + + u32Channel >>= 1u; + i++; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the value of a specified channel via channel index. + ** + ** \param [in] ADCx Pointer to ADC instance register base + ** \arg M4_ADC1 ADC unit 1 instance register base + ** \arg M4_ADC2 ADC unit 2 instance register base + ** + ** \param [in] u8ChIndex The index of the specified channel. + ** u8ChIndex < ADC1_CH_COUNT while ADCx == M4_ADC1; + ** u8ChIndex < ADC2_CH_COUNT while ADCx == M4_ADC2. + ** + ** \retval An uint16_t value -- the ADC value of the specified channel. + ** + ******************************************************************************/ +uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex) +{ + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + return pu16DataReg[u8ChIndex]; +} + +/** + ******************************************************************************* + ** \brief Get all AWD channels status flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval u32AwdFlag 0 -- No ADC channel meets AWD comparison conditions. + ** !0 -- The bit value of the channel that satisfies the + ** AWD condition is 1. + ** + ******************************************************************************/ +uint32_t ADC_GetAwdFlag(const M4_ADC_TypeDef *ADCx) +{ + uint32_t u32AwdFlag; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32AwdFlag = ADCx->AWDSR1; + u32AwdFlag <<= 16u; + u32AwdFlag |= ADCx->AWDSR0; + } + else + { + u32AwdFlag = ADCx->AWDSR0; + } + + return u32AwdFlag; +} + +/** + ******************************************************************************* + ** \brief Clear all AWD channels status flags + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrAwdFlag(M4_ADC_TypeDef *ADCx) +{ + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->AWDSR0 = 0u; + if (M4_ADC1 == ADCx) + { + ADCx->AWDSR0 = 0u; + ADCx->AWDSR1 = 0u; + } + } +} + +/** + ******************************************************************************* + ** \brief Clear AWD specified channels status flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32AwdCh The channel(s) which you want to clear it's flag(s). + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrAwdChFlag(M4_ADC_TypeDef *ADCx, uint32_t u32AwdCh) +{ + uint16_t u16ChR0; + uint16_t u16ChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChR0 = (uint16_t)u32AwdCh; + u16ChR1 = (uint16_t)(u32AwdCh >> 16u); + + ADCx->AWDSR0 &= (uint16_t)(~u16ChR0); + if (M4_ADC1 == ADCx) + { + ADCx->AWDSR1 &= (uint16_t)(~u16ChR1); + } + } +} + +/** + ******************************************************************************* + ** \brief Remap an ADC pin to channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32DestChannel Destination channel(s). + ** + ** \param [in] u8AdcPin ADC pin number. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, + uint32_t u32DestChannel, + uint8_t u8AdcPin) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t u8OffsetReg; + uint8_t u8ChPos; + uint16_t u16AdcPin = u8AdcPin; + __IO uint16_t *io16Chmuxr = NULL; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + enRet = Ok; + if (M4_ADC1 == ADCx) + { + if (u16AdcPin <= ADC1_IN15) + { + u32DestChannel &= ADC1_PIN_MASK_ALL; + } + else + { + enRet = ErrorInvalidParameter; + } + } + else + { + if ((u16AdcPin > ADC12_IN4) && (u16AdcPin < ADC12_IN11)) + { + u16AdcPin -= 4u; + u32DestChannel &= ADC2_PIN_MASK_ALL; + } + else + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + i = 0u; + while (0u != u32DestChannel) + { + if (u32DestChannel & 0x1ul) + { + u8OffsetReg = i / 4u; + u8ChPos = (i % 4u) * 4u; + io16Chmuxr = &(ADCx->CHMUXR0) + u8OffsetReg; + *io16Chmuxr &= (uint16_t)(~(0xFul << u8ChPos)); + *io16Chmuxr |= (uint16_t)(u16AdcPin << u8ChPos); + } + + u32DestChannel >>= 1u; + i++; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the number of the pin corresponding to the specified channel. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8ChIndex This channel that you want to get its pin number. + ** + ** \retval [0, 15] The correct ADC pin number. + ** \retval [0xFF] The invalid ADC pin number. + ** + ******************************************************************************/ +uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex) +{ + uint8_t u8OffsetPin; + uint8_t u8OffsetReg; + uint8_t u8ChPos; + uint8_t u8AdcPin = ADC_PIN_INVALID; + __IO const uint16_t *io16Chmuxr = NULL; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + DDL_ASSERT(IS_ADC1_CH_INDEX(u8ChIndex)); + u8OffsetPin = 0u; + } + else + { + DDL_ASSERT(IS_ADC2_CH_INDEX(u8ChIndex)); + u8OffsetPin = 4u; + } + + u8OffsetReg = u8ChIndex / 4u; + u8ChPos = (u8ChIndex % 4u) * 4u; + io16Chmuxr = &(ADCx->CHMUXR0) + u8OffsetReg; + u8AdcPin = (uint8_t)((*io16Chmuxr >> u8ChPos) & ((uint16_t)0xF)); + u8AdcPin += u8OffsetPin; + + return u8AdcPin; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Read all data of an ADC. pu16AdcData[0] = DR0, pu16AdcData[1] = DR1, ... + ** + ******************************************************************************/ +static void ADC_ReadAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length) +{ + uint8_t i; + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + for (i = 0u; i < u8Length; i++) + { + pu16AdcData[i] = pu16DataReg[i]; + } +} + +//@} // AdcGroup + +#endif /* DDL_ADC_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_aes.c b/driver/src/hc32f460_aes.c new file mode 100644 index 0000000..d549d30 --- /dev/null +++ b/driver/src/hc32f460_aes.c @@ -0,0 +1,311 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_aes.c + ** + ** A detailed description is available at + ** @link AesGroup Aes description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Aes. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_aes.h" +#include "hc32f460_utility.h" + +#if (DDL_AES_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup AesGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* AES block length in bytes is 16. */ +#define AES_BLOCK_LEN ((uint8_t)16) + +/* Each encryption operation takes 440 system clock cycles. */ +#define AES_ENCRYPT_TIMEOUT (440u) + +/* Each decryption operation takes 580 system clock cycles. */ +#define AES_DECRYPT_TIMEOUT (580u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void AES_WriteData(const uint8_t *pu8SrcData); +static void AES_ReadData(uint8_t *pu8Dest); +static void AES_WriteKey(const uint8_t *pu8Key); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief AES128 encryption(ECB mode). + ** + ** \param [in] pu8Plaintext Pointer to plaintext(the source data which will be encrypted) + ** + ** \param [in] u32PlaintextSize Length of plaintext in bytes. + ** + ** \param [in] pu8Key Pointer to the AES key. + ** + ** \param [out] pu8Ciphertext The destination address to store the result of the encryption. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout AES works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t AES_Encrypt(const uint8_t *pu8Plaintext, + uint32_t u32PlaintextSize, + const uint8_t *pu8Key, + uint8_t *pu8Ciphertext) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32BlockOffset; + uint32_t u32Index; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8Plaintext) && + (0u != u32PlaintextSize) && + (NULL != pu8Key) && + (NULL != pu8Ciphertext) && + (0u == (u32PlaintextSize & 0xFu)) && /* u32PlaintextSize % AES_BLOCK_LEN */ + (0u == ((uint32_t)pu8Plaintext & 0x3u)) && /* (uint32_t)pu8Ciphertext % 4u */ + (0u == ((uint32_t)pu8Key & 0x3u)) && /* (uint32_t)pu8Key % 4u */ + (0u == ((uint32_t)pu8Ciphertext & 0x3u))) /* (uint32_t)pu8Plaintext % 4u */ + { + /* Write the key to the register. */ + AES_WriteKey(pu8Key); + u32BlockOffset = 0u; + while (0u != u32PlaintextSize) + { + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + + /* Write data. */ + u32Index = u32BlockOffset * AES_BLOCK_LEN; + AES_WriteData(&pu8Plaintext[u32Index]); + + /* Set AES encrypt. */ + bM4_AES_CR_MODE = 0u; + + /* Start AES calculating. */ + bM4_AES_CR_START = 1u; + + enRet = ErrorTimeout; + u32TimeCount = 0u; + while (u32TimeCount < AES_ENCRYPT_TIMEOUT) + { + if (bM4_AES_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (enRet == ErrorTimeout) + { + break; + } + + AES_ReadData(&pu8Ciphertext[u32Index]); + u32PlaintextSize -= AES_BLOCK_LEN; + u32BlockOffset++; + } + + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief AES128 decryption(ECB mode). + ** + ** \param [in] pu8Ciphertext Pointer to ciphertext(the source data which will be decrypted) + ** + ** \param [in] u32CiphertextSize Length of ciphertext in bytes. + ** + ** \param [in] pu8Key Pointer to the AES key. + ** + ** \param [out] pu8Plaintext The destination address to store the result of the decryption. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout AES works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext, + uint32_t u32CiphertextSize, + const uint8_t *pu8Key, + uint8_t *pu8Plaintext) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32BlockOffset; + uint32_t u32Index; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8Ciphertext) && + (0u != u32CiphertextSize) && + (NULL != pu8Key) && + (NULL != pu8Plaintext) && + (0u == (u32CiphertextSize & 0xFu)) && /* u32CiphertextSize % AES_BLOCK_LEN */ + (0u == ((uint32_t)pu8Ciphertext & 0x3u)) && /* (uint32_t)pu8Ciphertext % 4u */ + (0u == ((uint32_t)pu8Key & 0x3u)) && /* (uint32_t)pu8Key % 4u */ + (0u == ((uint32_t)pu8Plaintext & 0x3u))) /* (uint32_t)pu8Plaintext % 4u */ + { + /* Write the key to the register. */ + AES_WriteKey(pu8Key); + u32BlockOffset = 0u; + while (0u != u32CiphertextSize) + { + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + + /* Write data. */ + u32Index = u32BlockOffset * AES_BLOCK_LEN; + AES_WriteData(&pu8Ciphertext[u32Index]); + + /* Set AES decrypt. */ + bM4_AES_CR_MODE = 1u; + + /* Start AES calculating. */ + bM4_AES_CR_START = 1u; + + enRet = ErrorTimeout; + u32TimeCount = 0u; + while (u32TimeCount < AES_DECRYPT_TIMEOUT) + { + if (bM4_AES_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (enRet == ErrorTimeout) + { + break; + } + + AES_ReadData(&pu8Plaintext[u32Index]); + u32CiphertextSize -= AES_BLOCK_LEN; + u32BlockOffset++; + } + + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + } + + return enRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Writes the input buffer in data register. + ** + ** \param [in] pu8SrcData Pointer to source data buffer. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + uint32_t u32SrcAddr = (uint32_t)pu8SrcData; + uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0); + + for (i = 0u; i < 4u; i++) + { + *(__IO uint32_t *)u32DrAddr = *(uint32_t*)u32SrcAddr; + u32SrcAddr += 4u; + u32DrAddr += 4u; + } +} + +/** + ******************************************************************************* + ** \brief Reads the from data register. + ** + ** \param [out] pu8Dest Pointer to the destination buffer. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_ReadData(uint8_t *pu8Dest) +{ + uint8_t i; + uint32_t u32DestAddr = (uint32_t)pu8Dest; + uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0); + + for (i = 0u; i < 4u; i++) + { + *(uint32_t*)u32DestAddr = *(__IO uint32_t *)u32DrAddr; + u32DestAddr += 4u; + u32DrAddr += 4u; + } +} + +/** + ******************************************************************************* + ** \brief Writes the input buffer in key register. + ** + ** \param [in] pu8Key Pointer to AES key. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_WriteKey(const uint8_t *pu8Key) +{ + uint8_t i; + uint32_t u32SrcKeyAddr = (uint32_t)pu8Key; + uint32_t u32KeyAddr = (uint32_t)&(M4_AES->KR0); + + for (i = 0u; i < 4u; i++) + { + *(__IO uint32_t *)u32KeyAddr = *(uint32_t*)u32SrcKeyAddr; + u32SrcKeyAddr += 4u; + u32KeyAddr += 4u; + } +} + +//@} // AesGroup + +#endif /* DDL_AES_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_can.c b/driver/src/hc32f460_can.c new file mode 100644 index 0000000..2deb1c3 --- /dev/null +++ b/driver/src/hc32f460_can.c @@ -0,0 +1,562 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_can.c + ** + ** A detailed description is available at + ** @link CanGroup CAN description @endlink + ** + ** - 2018-12-13 CDT First version for Device Driver Library of CAN. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_can.h" +#include "hc32f460_utility.h" + +#if (DDL_CAN_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CanGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CAN_RESET_ENABLE() (M4_CAN->CFG_STAT_f.RESET = 1u) +#define CAN_RESET_DISABLE() \ +do{ \ + do{ \ + M4_CAN->CFG_STAT_f.RESET = 0u; \ +}while(M4_CAN->CFG_STAT_f.RESET); \ +}while(0) + +#define CAN_RW_MEM32(addr) (*(__IO uint32_t *)(addr)) + +#define CAN_ACF_ID_REG_SEL ((uint8_t)0x00u) +#define CAN_ACF_MASK_REG_SEL ((uint8_t)0x01u) + + +/*! Parameter validity check for CAN Mode \a CanMode. */ +#define IS_CAN_MODE_VALID(CanMode) \ +( (CanExternalLoopBackMode == (CanMode)) || \ + (CanInternalLoopBackMode == (CanMode)) || \ + (CanTxSignalPrimaryMode == (CanMode)) || \ + (CanTxSignalSecondaryMode == (CanMode)) || \ + (CanListenOnlyMode == (CanMode)) \ +) + +/*! Parameter validity check for CAN Tx Cmd \a TxCmd. */ +#define IS_TX_CMD_VALID(TxCmd) \ +( (CanPTBTxCmd == (TxCmd)) || \ + (CanPTBTxAbortCmd == (TxCmd)) || \ + (CanSTBTxOneCmd == (TxCmd)) || \ + (CanSTBTxAllCmd == (TxCmd)) || \ + (CanSTBTxAbortCmd == (TxCmd)) \ +) + +/*! Parameter validity check for CAN status \a enCanStatus. */ +#define IS_CAN_STATUS_VALID(enCanStatus) \ +( (CanRxActive == (enCanStatus)) || \ + (CanTxActive == (enCanStatus)) || \ + (CanBusoff == (enCanStatus)) \ +) + +/*! Parameter validity check for CAN Irq type \a enCanIrqType. */ +#define IS_CAN_IRQ_TYPE_VALID(enCanIrqType) \ +( (CanRxIrqEn == (enCanIrqType)) || \ + (CanRxOverIrqEn == (enCanIrqType)) || \ + (CanRxBufFullIrqEn == (enCanIrqType)) || \ + (CanRxBufAlmostFullIrqEn == (enCanIrqType)) || \ + (CanTxPrimaryIrqEn == (enCanIrqType)) || \ + (CanTxSecondaryIrqEn == (enCanIrqType)) || \ + (CanErrorIrqEn == (enCanIrqType)) || \ + (CanErrorPassiveIrqEn == (enCanIrqType)) || \ + (CanArbiLostIrqEn == (enCanIrqType)) || \ + (CanBusErrorIrqEn == (enCanIrqType)) \ +) + +/*! Parameter validity check for CAN Irq flag type \a enCanIrqFLg. */ +#define IS_CAN_IRQ_FLAG_VALID(enCanIrqFLg) \ +( (CanTxBufFullIrqFlg == (enCanIrqFLg)) || \ + (CanRxIrqFlg == (enCanIrqFLg)) || \ + (CanRxOverIrqFlg == (enCanIrqFLg)) || \ + (CanRxBufFullIrqFlg == (enCanIrqFLg)) || \ + (CanRxBufAlmostFullIrqFlg == (enCanIrqFLg)) || \ + (CanTxPrimaryIrqFlg == (enCanIrqFLg)) || \ + (CanTxSecondaryIrqFlg == (enCanIrqFLg)) || \ + (CanErrorIrqFlg == (enCanIrqFLg)) || \ + (CanAbortIrqFlg == (enCanIrqFLg)) || \ + (CanErrorWarningIrqFlg == (enCanIrqFLg)) || \ + (CanErrorPassivenodeIrqFlg == (enCanIrqFLg)) || \ + (CanErrorPassiveIrqFlg == (enCanIrqFLg)) || \ + (CanArbiLostIrqFlg == (enCanIrqFLg)) || \ + (CanBusErrorIrqFlg == (enCanIrqFLg)) \ +) + +/*! Parameter validity check for CAN filter \a enCanFilter. */ +#define IS_CAN_FILTER_VALID(enCanFilter) \ +( (enCanFilter) <= CanFilterSel8) + +/*! Parameter validity check for CAN filter count \a u8Count. */ +#define IS_CAN_FILTER_COUNT_VALID(u8Count) \ +( (u8Count) <= 8u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configures the can base functions + ** + ** \param [in] pstcCanInitCfg The can initial config struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_Init(const stc_can_init_config_t *pstcCanInitCfg) +{ + uint8_t i; + if (NULL != pstcCanInitCfg) + { + DDL_ASSERT(IS_CAN_FILTER_COUNT_VALID(pstcCanInitCfg->u8FilterCount)); + + CAN_RESET_ENABLE(); + M4_CAN->BT_f.PRESC = pstcCanInitCfg->stcCanBt.PRESC; + M4_CAN->BT_f.SEG_1 = pstcCanInitCfg->stcCanBt.SEG_1; + M4_CAN->BT_f.SEG_2 = pstcCanInitCfg->stcCanBt.SEG_2; + M4_CAN->BT_f.SJW = pstcCanInitCfg->stcCanBt.SJW; + M4_CAN->TCTRL_f.TSMODE = pstcCanInitCfg->enCanSTBMode; + CAN_FilterConfig(pstcCanInitCfg->pstcFilter, pstcCanInitCfg->u8FilterCount); + + CAN_RESET_DISABLE(); + M4_CAN->RCTRL_f.RBALL = pstcCanInitCfg->enCanRxBufAll; + M4_CAN->RCTRL_f.ROM = pstcCanInitCfg->enCanRxBufMode; + M4_CAN->RCTRL_f.SACK = pstcCanInitCfg->enCanSAck; + M4_CAN->LIMIT_f.AFWL = pstcCanInitCfg->stcWarningLimit.CanWarningLimitVal; + M4_CAN->LIMIT_f.EWL = pstcCanInitCfg->stcWarningLimit.CanErrorWarningLimitVal; + + // Enable filters. + for (i=0u; iu8FilterCount; i++) + { + CAN_FilterCmd(pstcCanInitCfg->pstcFilter[i].enFilterSel, Enable); + } + } +} + +/** + ******************************************************************************* + ** \brief De-Init (RESET CAN register) + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_DeInit(void) +{ + CAN_RESET_ENABLE(); +} + +/** + ******************************************************************************* + ** \brief Configures the can Mode + ** + ** \param [in] enMode The can mode enum. @ref en_can_mode_t + ** \param [in] enNewState The new state of the can filter chanel. + ** \arg Enable Enable filter. + ** \arg Disable Disable filter. + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_MODE_VALID(enMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(CanListenOnlyMode == enMode) + { + M4_CAN->TCMD_f.LOM = enNewState; + }else + { + if(Enable == enNewState) + { + M4_CAN->CFG_STAT |= enMode; + }else + { + M4_CAN->CFG_STAT &= ~enMode; + } + } +} + + +/** + ******************************************************************************* + ** \brief Configures the can acceptance filter + ** + ** \param [in] pstcFilter Pointer to a stc_can_filter_t type array. + ** @ref stc_can_filter_t + ** \param [in] u8FilterCount Number of filters that to be configured. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_FilterConfig(const stc_can_filter_t pstcFilter[], uint8_t u8FilterCount) +{ + uint8_t i; + + if(NULL != pstcFilter) + { + DDL_ASSERT(IS_CAN_FILTER_COUNT_VALID(u8FilterCount)); + + for (i=0u; iACFCTRL_f.ACFADR = pstcFilter[i].enFilterSel; + //<ACFCTRL_f.SELMASK = CAN_ACF_ID_REG_SEL; + M4_CAN->ACF = pstcFilter[i].u32CODE; + //<ACFCTRL_f.SELMASK = CAN_ACF_MASK_REG_SEL; + M4_CAN->ACF = pstcFilter[i].u32MASK; + //<ACF_f.AIDEE = ((pstcFilter[i].enAcfFormat >> 1ul) & 0x01u); + M4_CAN->ACF_f.AIDE = (pstcFilter[i].enAcfFormat & 0x01ul); + } + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the specified can acceptance filter. + ** + ** \param [in] enFilter Specifies a filter. + ** @ref en_can_filter_sel_t + ** \param [in] enNewState The new state of the specified filter. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_FilterCmd(en_can_filter_sel_t enFilter, en_functional_state_t enNewState) +{ + uint8_t u8FilterSel; + + DDL_ASSERT(IS_CAN_FILTER_VALID(enFilter)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u8FilterSel = (uint8_t)(1ul << enFilter); + + if(Enable == enNewState) + { + M4_CAN->ACFEN |= u8FilterSel; + }else + { + M4_CAN->ACFEN &= (uint8_t)(~u8FilterSel); + } +} + +/** + ******************************************************************************* + ** \brief Configures the can Tx frame set + ** + ** \param [in] pstcTxFrame The can Tx frame struct. + ** @ref stc_can_txframe_t + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame) +{ + uint32_t u32TBUFAddr; + + if(NULL != pstcTxFrame) + { + u32TBUFAddr = (uint32_t)&M4_CAN->TBUF; + M4_CAN->TCMD_f.TBSEL = pstcTxFrame->enBufferSel; + CAN_RW_MEM32(u32TBUFAddr) = pstcTxFrame->TBUF32_0; + CAN_RW_MEM32(u32TBUFAddr+4) = pstcTxFrame->TBUF32_1; + CAN_RW_MEM32(u32TBUFAddr+8) = pstcTxFrame->TBUF32_2[0]; + CAN_RW_MEM32(u32TBUFAddr+12) = pstcTxFrame->TBUF32_2[1]; + + if(CanSTBSel == pstcTxFrame->enBufferSel) + { + M4_CAN->TCTRL_f.TSNEXT = Enable; + } + } +} + +/** + ******************************************************************************* + ** \brief Configures the can Tx Command + ** + ** \param [in] enTxCmd The can Tx Command. + ** + ** \retval Can Tx buffer status @ref en_can_tx_buf_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd) +{ + DDL_ASSERT(IS_TX_CMD_VALID(enTxCmd)); + + M4_CAN->TCMD |= enTxCmd; + + return (en_can_tx_buf_status_t)M4_CAN->TCTRL_f.TSSTAT; +} + +/** + ******************************************************************************* + ** \brief Configures the can Rx frame + ** + ** \param [in] pstcRxFrame The can Rx frame. + ** @ref stc_can_rxframe_t + ** \retval Can rx buffer status @ref en_can_rx_buf_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame) +{ + uint32_t u32RBUFAddr; + + if(NULL != pstcRxFrame) + { + u32RBUFAddr = (uint32_t)&M4_CAN->RBUF; + pstcRxFrame->RBUF32_0 = CAN_RW_MEM32(u32RBUFAddr); + pstcRxFrame->RBUF32_1 = CAN_RW_MEM32(u32RBUFAddr+4); + pstcRxFrame->RBUF32_2[0] = CAN_RW_MEM32(u32RBUFAddr+8); + pstcRxFrame->RBUF32_2[1] = CAN_RW_MEM32(u32RBUFAddr+12); + + M4_CAN->RCTRL_f.RREL = 1u; + } + return (en_can_rx_buf_status_t)M4_CAN->RCTRL_f.RSSTAT; +} + + +/** + ******************************************************************************* + ** \brief Get the can Error Status + ** + ** \param None + ** + ** \retval en_can_error_t The can error status + ** + ** \note None + ** + ******************************************************************************/ +en_can_error_t CAN_ErrorStatusGet(void) +{ + en_can_error_t enRet = UNKOWN_ERROR; + + if(6u > M4_CAN->EALCAP_f.KOER) + { + enRet = (en_can_error_t)M4_CAN->EALCAP_f.KOER; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the can Status + ** + ** \param enCanStatus The can status + ** \arg true + ** \arg false + ** \retval bool + ** + ** \note None + ** + ******************************************************************************/ +bool CAN_StatusGet(en_can_status_t enCanStatus) +{ + bool bRet = false; + DDL_ASSERT(IS_CAN_STATUS_VALID(enCanStatus)); + + if(M4_CAN->CFG_STAT & enCanStatus) + { + bRet = true; + } + return bRet; +} + +/** + ******************************************************************************* + ** \brief Configures the can Interrupt enable + ** + ** \param [in] enCanIrqType The can interrupt type. + ** \param [in] enNewState The new state of the can interrupt. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState) +{ + volatile uint32_t *u32pIE; + + DDL_ASSERT(IS_CAN_IRQ_TYPE_VALID(enCanIrqType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + if(Enable == enNewState) + { + *u32pIE |= enCanIrqType; + }else + { + *u32pIE &= ~((uint32_t)enCanIrqType); + } +} + +/** + ******************************************************************************* + ** \brief Get the can Interrupt Flag + ** + ** \param [in] enCanIrqFlgType The can interrupt Flag. + ** + ** \retval bool + ** + ** \note None + ** + ******************************************************************************/ +bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType) +{ + volatile uint32_t *u32pIE = NULL; + bool bRet = false; + + DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + if( *u32pIE & enCanIrqFlgType) + { + bRet = true; + } + return bRet; +} + +/** + ******************************************************************************* + ** \brief Clear the can Interrupt Flag + ** + ** \param [in] enCanIrqFlgType The can interrupt type. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType) +{ + volatile uint32_t *u32pIE = NULL; + uint32_t u32IETempMsk = 0xFF2A00FF; + + DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + *u32pIE = (((*u32pIE)&u32IETempMsk) | (uint32_t)enCanIrqFlgType); +} + + +/** + ******************************************************************************* + ** \brief Get the can Rx Error Counter + ** + ** \param None + ** + ** \retval Error Counter(0~255) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_RxErrorCntGet(void) +{ + return M4_CAN->RECNT; +} + +/** + ******************************************************************************* + ** \brief Get the can Tx Error Counter + ** + ** \param None + ** + ** \retval Error Counter(0~255) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_TxErrorCntGet(void) +{ + return M4_CAN->TECNT; +} + +/** + ******************************************************************************* + ** \brief Get the can Arbitration lost captrue + ** + ** \param None + ** + ** \retval address(0~31) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_ArbitrationLostCap(void) +{ + return M4_CAN->EALCAP_f.ALC; +} + + +//@} // CanGroup + +#endif /* DDL_CAN_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/src/hc32f460_can1.c b/driver/src/hc32f460_can1.c new file mode 100644 index 0000000..ff08fe1 --- /dev/null +++ b/driver/src/hc32f460_can1.c @@ -0,0 +1,532 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_can.c + ** + ** A detailed description is available at + ** @link CanGroup CAN description @endlink + ** + ** - 2018-12-13 CDT First version for Device Driver Library of CAN. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_can.h" +#include "hc32f460_utility.h" + +#if (DDL_CAN_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CanGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CAN_RESET_ENABLE() (M4_CAN->CFG_STAT_f.RESET = 1u) +#define CAN_RESET_DISABLE() \ +do{ \ + do{ \ + M4_CAN->CFG_STAT_f.RESET = 0u; \ +}while(M4_CAN->CFG_STAT_f.RESET); \ +}while(0) + +#define CAN_RW_MEM32(addr) (*(__IO uint32_t *)(addr)) + +#define CAN_ACF_ID_REG_SEL ((uint8_t)0x00u) +#define CAN_ACF_MASK_REG_SEL ((uint8_t)0x01u) + + +/*! Parameter validity check for CAN Mode \a CanMode. */ +#define IS_CAN_MODE_VALID(CanMode) \ +( (CanExternalLoopBackMode == (CanMode)) || \ + (CanInternalLoopBackMode == (CanMode)) || \ + (CanTxSignalPrimaryMode == (CanMode)) || \ + (CanTxSignalSecondaryMode == (CanMode)) || \ + (CanListenOnlyMode == (CanMode)) \ +) + +/*! Parameter validity check for CAN Tx Cmd \a TxCmd. */ +#define IS_TX_CMD_VALID(TxCmd) \ +( (CanPTBTxCmd == (TxCmd)) || \ + (CanPTBTxAbortCmd == (TxCmd)) || \ + (CanSTBTxOneCmd == (TxCmd)) || \ + (CanSTBTxAllCmd == (TxCmd)) || \ + (CanSTBTxAbortCmd == (TxCmd)) \ +) + +/*! Parameter validity check for CAN status \a enCanStatus. */ +#define IS_CAN_STATUS_VALID(enCanStatus) \ +( (CanRxActive == (enCanStatus)) || \ + (CanTxActive == (enCanStatus)) || \ + (CanBusoff == (enCanStatus)) \ +) + +/*! Parameter validity check for CAN Irq type \a enCanIrqType. */ +#define IS_CAN_IRQ_TYPE_VALID(enCanIrqType) \ +( (CanRxIrqEn == (enCanIrqType)) || \ + (CanRxOverIrqEn == (enCanIrqType)) || \ + (CanRxBufFullIrqEn == (enCanIrqType)) || \ + (CanRxBufAlmostFullIrqEn == (enCanIrqType)) || \ + (CanTxPrimaryIrqEn == (enCanIrqType)) || \ + (CanTxSecondaryIrqEn == (enCanIrqType)) || \ + (CanErrorIrqEn == (enCanIrqType)) || \ + (CanErrorPassiveIrqEn == (enCanIrqType)) || \ + (CanArbiLostIrqEn == (enCanIrqType)) || \ + (CanBusErrorIrqEn == (enCanIrqType)) \ +) + +/*! Parameter validity check for CAN Irq flag type \a enCanIrqFLg. */ +#define IS_CAN_IRQ_FLAG_VALID(enCanIrqFLg) \ +( (CanTxBufFullIrqFlg == (enCanIrqFLg)) || \ + (CanRxIrqFlg == (enCanIrqFLg)) || \ + (CanRxOverIrqFlg == (enCanIrqFLg)) || \ + (CanRxBufFullIrqFlg == (enCanIrqFLg)) || \ + (CanRxBufAlmostFullIrqFlg == (enCanIrqFLg)) || \ + (CanTxPrimaryIrqFlg == (enCanIrqFLg)) || \ + (CanTxSecondaryIrqFlg == (enCanIrqFLg)) || \ + (CanErrorIrqFlg == (enCanIrqFLg)) || \ + (CanAbortIrqFlg == (enCanIrqFLg)) || \ + (CanErrorWarningIrqFlg == (enCanIrqFLg)) || \ + (CanErrorPassivenodeIrqFlg == (enCanIrqFLg)) || \ + (CanErrorPassiveIrqFlg == (enCanIrqFLg)) || \ + (CanArbiLostIrqFlg == (enCanIrqFLg)) || \ + (CanBusErrorIrqFlg == (enCanIrqFLg)) \ +) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configures the can base functions + ** + ** \param [in] pstcCanInitCfg The can initial config struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_Init(stc_can_init_config_t *pstcCanInitCfg) +{ + if (NULL != pstcCanInitCfg) + { + M4_CAN->RCTRL_f.SACK = pstcCanInitCfg->enCanSAck; + M4_CAN->TCTRL_f.TSMODE = pstcCanInitCfg->enCanSTBMode; + M4_CAN->RCTRL_f.RBALL = pstcCanInitCfg->enCanRxBufAll; + M4_CAN->RCTRL_f.ROM = pstcCanInitCfg->enCanRxBufMode; + + M4_CAN->RTIE = 0x00u; + + CAN_RESET_ENABLE(); + + M4_CAN->BT_f.PRESC = pstcCanInitCfg->stcCanBt.PRESC; + M4_CAN->BT_f.SEG_1 = pstcCanInitCfg->stcCanBt.SEG_1; + M4_CAN->BT_f.SEG_2 = pstcCanInitCfg->stcCanBt.SEG_2; + M4_CAN->BT_f.SJW = pstcCanInitCfg->stcCanBt.SJW; + + M4_CAN->LIMIT_f.AFWL = pstcCanInitCfg->stcWarningLimit.CanWarningLimitVal; + M4_CAN->LIMIT_f.EWL = pstcCanInitCfg->stcWarningLimit.CanErrorWarningLimitVal; + + CAN_RESET_DISABLE(); + } +} + +/** + ******************************************************************************* + ** \brief De-Init (RESET CAN register) + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_DeInit(void) +{ + CAN_RESET_ENABLE(); +} + +/** + ******************************************************************************* + ** \brief Configures the can Mode + ** + ** \param [in] enMode The can mode enum. @ref en_can_mode_t + ** \param [in] enNewState The new state of the can filter chanel. + ** \arg Enable Enable filter. + ** \arg Disable Disable filter. + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_MODE_VALID(enMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(CanListenOnlyMode == enMode) + { + M4_CAN->TCMD_f.LOM = enNewState; + }else + { + if(Enable == enNewState) + { + M4_CAN->CFG_STAT |= enMode; + }else + { + M4_CAN->CFG_STAT &= ~enMode; + } + } + +} + + +/** + ******************************************************************************* + ** \brief Configures the can acceptance filter + ** + ** \param [in] pstcFilter The can filter config struct. + ** @ref stc_can_filter_t + ** \param [in] enNewState The new state of the can filter chanel. + ** \arg Enable Enable filter. + ** \arg Disable Disable filter. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_FilterConfig(const stc_can_filter_t *pstcFilter, en_functional_state_t enNewState) +{ + if(NULL != pstcFilter) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CAN_RESET_ENABLE(); + + //<ACFCTRL_f.ACFADR = pstcFilter->enFilterSel; + + //<ACFCTRL_f.SELMASK = CAN_ACF_ID_REG_SEL; + M4_CAN->ACF = pstcFilter->u32CODE; + + //<ACFCTRL_f.SELMASK = CAN_ACF_MASK_REG_SEL; + M4_CAN->ACF = pstcFilter->u32MASK; + + //<ACF_f.AIDEE = ((pstcFilter->enAcfFormat >> 1ul) & 0x01u); + M4_CAN->ACF_f.AIDE = (pstcFilter->enAcfFormat & 0x01ul); + + if(Enable == enNewState) + { + M4_CAN->ACFEN |= (uint8_t)(1ul << pstcFilter->enFilterSel); + }else + { + M4_CAN->ACFEN &= (uint8_t)(~(1ul << (pstcFilter->enFilterSel))); + } + + CAN_RESET_DISABLE(); + } +} + + +/** + ******************************************************************************* + ** \brief Configures the can Tx frame set + ** + ** \param [in] pstcTxFrame The can Tx frame struct. + ** @ref stc_can_txframe_t + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame) +{ + uint32_t u32TBUFAddr; + + if(NULL != pstcTxFrame) + { + u32TBUFAddr = (uint32_t)&M4_CAN->TBUF; + M4_CAN->TCMD_f.TBSEL = pstcTxFrame->enBufferSel; + CAN_RW_MEM32(u32TBUFAddr) = pstcTxFrame->TBUF32_0; + CAN_RW_MEM32(u32TBUFAddr+4) = pstcTxFrame->TBUF32_1; + CAN_RW_MEM32(u32TBUFAddr+8) = pstcTxFrame->TBUF32_2[0]; + CAN_RW_MEM32(u32TBUFAddr+12) = pstcTxFrame->TBUF32_2[1]; + + if(CanSTBSel == pstcTxFrame->enBufferSel) + { + M4_CAN->TCTRL_f.TSNEXT = Enable; + } + } +} + +/** + ******************************************************************************* + ** \brief Configures the can Tx Command + ** + ** \param [in] enTxCmd The can Tx Command. + ** + ** \retval Can Tx buffer status @ref en_can_tx_buf_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd) +{ + DDL_ASSERT(IS_TX_CMD_VALID(enTxCmd)); + + M4_CAN->TCMD |= enTxCmd; + + return (en_can_tx_buf_status_t)M4_CAN->TCTRL_f.TSSTAT; + +} + +/** + ******************************************************************************* + ** \brief Configures the can Rx frame + ** + ** \param [in] pstcRxFrame The can Rx frame. + ** @ref stc_can_rxframe_t + ** \retval Can rx buffer status @ref en_can_rx_buf_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame) +{ + uint32_t u32RBUFAddr; + + if(NULL != pstcRxFrame) + { + u32RBUFAddr = (uint32_t)&M4_CAN->RBUF; + pstcRxFrame->RBUF32_0 = CAN_RW_MEM32(u32RBUFAddr); + pstcRxFrame->RBUF32_1 = CAN_RW_MEM32(u32RBUFAddr+4); + pstcRxFrame->RBUF32_2[0] = CAN_RW_MEM32(u32RBUFAddr+8); + pstcRxFrame->RBUF32_2[1] = CAN_RW_MEM32(u32RBUFAddr+12); + + M4_CAN->RCTRL_f.RREL = 1u; + } + return (en_can_rx_buf_status_t)M4_CAN->RCTRL_f.RSSTAT; +} + + +/** + ******************************************************************************* + ** \brief Get the can Error Status + ** + ** \param None + ** + ** \retval en_can_error_t The can error status + ** + ** \note None + ** + ******************************************************************************/ +en_can_error_t CAN_ErrorStatusGet(void) +{ + en_can_error_t enRet = UNKOWN_ERROR; + + if(6u > M4_CAN->EALCAP_f.KOER) + { + enRet = (en_can_error_t)M4_CAN->EALCAP_f.KOER; + } + return enRet; + +} + +/** + ******************************************************************************* + ** \brief Get the can Status + ** + ** \param enCanStatus The can status + ** \arg true + ** \arg false + ** \retval bool + ** + ** \note None + ** + ******************************************************************************/ +bool CAN_StatusGet(en_can_status_t enCanStatus) +{ + bool bRet = false; + DDL_ASSERT(IS_CAN_STATUS_VALID(enCanStatus)); + + if(M4_CAN->CFG_STAT & enCanStatus) + { + bRet = true; + } + return bRet; +} + +/** + ******************************************************************************* + ** \brief Configures the can Interrupt enable + ** + ** \param [in] enCanIrqType The can interrupt type. + ** \param [in] enNewState The new state of the can interrupt. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState) +{ + volatile uint32_t *u32pIE; + + DDL_ASSERT(IS_CAN_IRQ_TYPE_VALID(enCanIrqType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + if(Enable == enNewState) + { + *u32pIE |= enCanIrqType; + }else + { + *u32pIE &= ~((uint32_t)enCanIrqType); + } + +} + +/** + ******************************************************************************* + ** \brief Get the can Interrupt Flag + ** + ** \param [in] enCanIrqFlgType The can interrupt Flag. + ** + ** \retval bool + ** + ** \note None + ** + ******************************************************************************/ +bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType) +{ + volatile uint32_t *u32pIE = NULL; + bool bRet = false; + + DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + if( *u32pIE & enCanIrqFlgType) + { + bRet = true; + } + return bRet; +} + +/** + ******************************************************************************* + ** \brief Clear the can Interrupt Flag + ** + ** \param [in] enCanIrqFlgType The can interrupt type. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType) +{ + volatile uint32_t *u32pIE = NULL; + uint32_t u32IETempMsk = 0xFF2A00FF; + + DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + *u32pIE = (((*u32pIE)&u32IETempMsk) | (uint32_t)enCanIrqFlgType); +} + + +/** + ******************************************************************************* + ** \brief Get the can Rx Error Counter + ** + ** \param None + ** + ** \retval Error Counter(0~255) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_RxErrorCntGet(void) +{ + return M4_CAN->RECNT; +} + +/** + ******************************************************************************* + ** \brief Get the can Tx Error Counter + ** + ** \param None + ** + ** \retval Error Counter(0~255) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_TxErrorCntGet(void) +{ + return M4_CAN->TECNT; +} + +/** + ******************************************************************************* + ** \brief Get the can Arbitration lost captrue + ** + ** \param None + ** + ** \retval address(0~31) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_ArbitrationLostCap(void) +{ + return M4_CAN->EALCAP_f.ALC; +} + + +//@} // CanGroup + +#endif /* DDL_CAN_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/src/hc32f460_clk.c b/driver/src/hc32f460_clk.c new file mode 100644 index 0000000..eda8677 --- /dev/null +++ b/driver/src/hc32f460_clk.c @@ -0,0 +1,1813 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_clk.c + ** + ** A detailed description is available at + ** @link CmuGroup Clock description @endlink + ** + ** - 2018-10-13 CDT First version for Device Driver Library of CMU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_clk.h" +#include "hc32f460_utility.h" + +#if (DDL_CLK_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CmuGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CLK_XTAL_TIMEOUT ((uint16_t)0x1000u) +#define CLK_XTAL32_TIMEOUT ((uint8_t)0x05u) +#define CLK_HRC_TIMEOUT ((uint16_t)0x1000u) +#define CLK_MRC_TIMEOUT ((uint8_t)0x05u) +#define CLK_LRC_TIMEOUT ((uint8_t)0x05u) +#define CLK_MPLL_TIMEOUT ((uint16_t)0x1000u) +#define CLK_UPLL_TIMEOUT ((uint16_t)0x1000u) + +/* TBDs 30us based 200M frequency. */ +#define CLK_FCG_STABLE ((uint16_t)0x200u) +#define CLK_SYSCLK_STABLE ((uint16_t)0x200u) +#define CLK_USBCLK_STABLE ((uint16_t)0x200u) + +#define CLK_PLL_DIV_MIN (2u) +#define CLK_PLL_DIV_MAX (16u) + +#define CLK_PLLQ_DIV_MIN (1u) +#define CLK_PLLQ_DIV_MAX (16u) + +#define CLK_PLLN_MIN (20u) +#define CLK_PLLN_MAX (480u) + +#define CLK_PLLM_MIN (1u) +#define CLK_PLLM_MAX (24u) + +#define CLK_UPLLM_MIN (2u) +#define CLK_UPLLM_MAX (24u) + +#define CLK_PLL_VCO_IN_MIN (1u*1000u*1000u) +#define CLK_PLL_VCO_IN_MAX (24u*1000u*1000u) + +#define CLK_PLL_VCO_OUT_MIN (240u*1000u*1000u) +#define CLK_PLL_VCO_OUT_MAX (480u*1000u*1000u) + +#define ENABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50001u) +#define DISABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50000u) + +#define ENABLE_CLOCK_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa501u) +#define DISABLE_CLOCK_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~1u)))) + +#define ENABLE_CLOCK1_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa502u) +#define DISABLE_CLOCK1_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~2u)))) + + +#define DEFAULT_FCG0 (0xFFFFFAEEul) +#define DEFAULT_FCG1 (0xFFFFFFFFul) +#define DEFAULT_FCG2 (0xFFFFFFFFul) +#define DEFAULT_FCG3 (0xFFFFFFFFul) +#define FCG2_WITHOUT_EMB (0xFFFF7FFFul) + +#define FCG0_OFFSET_FCM (16ul) +#define FCG1_OFFSET_CAN (0ul) +#define FCG1_OFFSET_QSPI (3ul) +#define FCG1_OFFSET_USBFS (8ul) +#define FCG1_OFFSET_SPI1 (16ul) +#define FCG1_OFFSET_SPI2 (17ul) +#define FCG1_OFFSET_SPI3 (18ul) +#define FCG1_OFFSET_SPI4 (19ul) +#define FCG3_OFFSET_ADC1 (0ul) +#define FCG3_OFFSET_ADC2 (1ul) +#define FCG3_OFFSET_DAC (4ul) + +/*! Parameter validity check for XTAL stablization time \a stb. */ +#define IS_XTAL_STB_VALID(stb) \ +( (ClkXtalStbCycle35 <= (stb)) && \ + (ClkXtalStbCycle8163 >= (stb))) + +/*! Parameter validity check for pll source \a src. */ +#define IS_PLL_SOURCE(src) \ +( (ClkPllSrcXTAL == (src)) || \ + (ClkPllSrcHRC == (src))) + +/*! Parameter validity check for mpll div \a pllp, pllr, upll div \a pllp, pllq, pllr*/ +#define IS_PLL_DIV_VALID(pllx) \ +( (CLK_PLL_DIV_MIN <= (pllx)) && \ + (CLK_PLL_DIV_MAX >= (pllx))) + +/*! Parameter validity check for pll div \a pllq. */ +#define IS_PLLQ_DIV_VALID(pllx) \ +( (CLK_PLLQ_DIV_MIN <= (pllx)) && \ + (CLK_PLLQ_DIV_MAX >= (pllx))) + +/*! Parameter validity check for plln \a plln. */ +#define IS_PLLN_VALID(plln) \ +( (CLK_PLLN_MIN <= (plln)) && \ + (CLK_PLLN_MAX >= (plln))) + +/*! Parameter validity check for pllm \a pllm. */ +#define IS_PLLM_VALID(pllm) \ +( (CLK_PLLM_MIN <= (pllm)) && \ + (CLK_PLLM_MAX >= (pllm))) + +/*! Parameter validity check for pllm \a pllm. */ +#define IS_UPLLM_VALID(pllm) \ +( (CLK_UPLLM_MIN <= (pllm)) && \ + (CLK_UPLLM_MAX >= (pllm))) + +/*! Parameter validity check for pllsource/pllm \a vco_in. */ +#define IS_PLL_VCO_IN_VALID(vco_in) \ +( (CLK_PLL_VCO_IN_MIN <= (vco_in)) && \ + (CLK_PLL_VCO_IN_MAX >= (vco_in))) + +/*! Parameter validity check for pllsource/pllm*plln \a vco_out. */ +#define IS_PLL_VCO_OUT_VALID(vco_out) \ +( (CLK_PLL_VCO_OUT_MIN <= (vco_out)) && \ + (CLK_PLL_VCO_OUT_MAX >= (vco_out))) + +/*! Parameter validity check for system clock source \a syssrc. */ +#define IS_SYSCLK_SOURCE(syssrc) \ +( (ClkSysSrcHRC == (syssrc)) || \ + ((ClkSysSrcMRC <= (syssrc)) && \ + (CLKSysSrcMPLL >= (syssrc)))) + +/*! Parameter validity check for usb clock source \a usbsrc. */ +#define IS_USBCLK_SOURCE(usbsrc) \ +( ((ClkUsbSrcSysDiv2 <= (usbsrc)) && \ + (ClkUsbSrcSysDiv4 >= (usbsrc))) || \ + ((ClkUsbSrcMpllp <= (usbsrc)) && \ + (ClkUsbSrcUpllr >= (usbsrc)))) + +/*! Parameter validity check for peripheral(adc/trng/I2S) clock source \a adcsrc. */ +#define IS_PERICLK_SOURCE(adcsrc) \ +( (ClkPeriSrcPclk == (adcsrc)) || \ + ((ClkPeriSrcMpllp <= (adcsrc)) && \ + (ClkPeriSrcUpllr >= (adcsrc)))) + +/*! Parameter validity check for output clock source \a outsrc. */ +#define IS_OUTPUTCLK_SOURCE(outsrc) \ +( (ClkOutputSrcHrc == (outsrc)) || \ + (ClkOutputSrcMrc == (outsrc)) || \ + (ClkOutputSrcLrc == (outsrc)) || \ + (ClkOutputSrcXtal == (outsrc)) || \ + (ClkOutputSrcXtal32 == (outsrc)) || \ + (ClkOutputSrcMpllp == (outsrc)) || \ + (ClkOutputSrcUpllp == (outsrc)) || \ + (ClkOutputSrcMpllq == (outsrc)) || \ + (ClkOutputSrcUpllq == (outsrc)) || \ + (ClkOutputSrcSysclk == (outsrc))) + +/*! Parameter validity check for fcm source \a fcmsrc. */ +#define IS_FCM_SOURCE(fcmsrc) \ +( (ClkFcmSrcXtal == (fcmsrc)) || \ + ((ClkFcmSrcXtal32 <= (fcmsrc)) && \ + (ClkFcmSrcRtcLrc >= (fcmsrc)))) + +/*! Parameter validity check for output clock channel \a outch. */ +#define IS_OUTPUTCLK_CHANNEL(outch) \ +( (ClkOutputCh1 == (outch)) || \ + (ClkOutputCh2 == (outch))) + +/*! Parameter validity check for fcm reference \a ref. */ +#define IS_FCM_REF(ref) \ +( (ClkFcmExtRef == (ref)) || \ + (ClkFcmInterRef == (ref))) + +/*! Parameter validity check for fcm edge \a edge. */ +#define IS_FCM_EDGE(edge) \ +( (ClkFcmEdgeRising == (edge)) || \ + (ClkFcmEdgeFalling == (edge)) || \ + (ClkFcmEdgeBoth == (edge))) + +/*! Parameter validity check for fcm filter clock \a clk. */ +#define IS_FCM_FILTER_CLK(clk) \ +( (ClkFcmFilterClkNone == (clk)) || \ + (ClkFcmFilterClkFcmSrc == (clk)) || \ + (ClkFcmFilterClkFcmSrcDiv4 == (clk)) || \ + (ClkFcmFilterClkFcmSrcDiv16 == (clk))) + +/*! Parameter validity check for fcm abnormal handle \a handle. */ +#define IS_FCM_HANDLE(handle) \ +( (ClkFcmHandleInterrupt == (handle)) || \ + (ClkFcmHandleReset == (handle))) + +/*! Parameter validity check for debug clock division \a div. */ +#define IS_TPIUCLK_DIV_VALID(div) \ +( (ClkTpiuclkDiv1 == (div)) || \ + (ClkTpiuclkDiv2 == (div)) || \ + (ClkTpiuclkDiv4 == (div))) + +/*! Parameter validity check for output clock division \a div. */ +#define IS_OUTPUTCLK_DIV_VALID(div) \ +( (ClkOutputDiv1 == (div)) || \ + ((ClkOutputDiv2 <= (div)) && \ + (ClkOutputDiv128 >= (div)))) + +/*! Parameter validity check for fcm measurement source division \a div. */ +#define IS_FCM_MEASRC_DIV_VALID(div) \ +( (ClkFcmMeaDiv1 == (div)) || \ + (ClkFcmMeaDiv4 == (div)) || \ + (ClkFcmMeaDiv8 == (div)) || \ + (ClkFcmMeaDiv32 == (div))) + +/*! Parameter validity check for internal reference source division \a div. */ +#define IS_FCM_INTREF_DIV_VALID(div) \ +( (ClkFcmIntrefDiv32 == (div)) || \ + (ClkFcmIntrefDiv128 == (div)) || \ + (ClkFcmIntrefDiv1024 == (div)) || \ + (ClkFcmIntrefDiv8192 == (div))) + +/*! Parameter validity check for system clock config \a cfg. */ +#define IS_SYSCLK_CONFIG_VALID(cfg) \ +( ((cfg)->enHclkDiv <= ((cfg)->enPclk1Div)) && \ + ((cfg)->enHclkDiv <= ((cfg)->enPclk3Div)) && \ + ((cfg)->enHclkDiv <= ((cfg)->enPclk4Div)) && \ + ((cfg)->enPclk0Div <= ((cfg)->enPclk1Div)) && \ + ((cfg)->enPclk0Div <= ((cfg)->enPclk3Div)) && \ + (((cfg)->enPclk2Div-(cfg)->enPclk4Div == 3) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 2) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 1) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 0) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 1) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 2) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 3))) + + +/*! Parameter validity check for clock status \a flag. */ +#define IS_CLK_FLAG(flag) \ +( (ClkFlagHRCRdy == (flag)) || \ + (ClkFlagXTALRdy == (flag)) || \ + (ClkFlagMPLLRdy == (flag)) || \ + (ClkFlagUPLLRdy == (flag)) || \ + (ClkFlagXTALStoppage == (flag))) +/*! Parameter validity check for fcm status \a flag. */ +#define IS_FCM_FLAG(flag) \ +( (ClkFcmFlagOvf == (flag)) || \ + (ClkFcmFlagMendf == (flag)) || \ + (ClkFcmFlagErrf == (flag))) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configures the external high speed oscillator(XTAL). + ** + ** \param [in] pstcXtalCfg The XTAL configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_XtalConfig(const stc_clk_xtal_cfg_t *pstcXtalCfg) +{ + if(NULL != pstcXtalCfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALCFGR_f.SUPDRV = pstcXtalCfg->enFastStartup; + M4_SYSREG->CMU_XTALCFGR_f.XTALMS = pstcXtalCfg->enMode; + M4_SYSREG->CMU_XTALCFGR_f.XTALDRV = pstcXtalCfg->enDrv; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Configures the XTAL stable time. + ** + ** \param [in] enXtalStb The XTAL stable time. + ** + ** \retval None + ** + ** \note One of the stable clock is 1/8 LRC clock. + ** + ******************************************************************************/ +void CLK_XtalStbConfig(const en_clk_xtal_stb_cycle_t enXtalStb) +{ + DDL_ASSERT(IS_XTAL_STB_VALID(enXtalStb)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALSTBCR_f.XTALSTB = enXtalStb; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the XTAL stoppage. + ** + ** \param [in] pstcXtalStpCfg The XTAL stoppage configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_XtalStpConfig(const stc_clk_xtal_stp_cfg_t *pstcXtalStpCfg) +{ + if(NULL != pstcXtalStpCfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDE = pstcXtalStpCfg->enDetect; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDRIS = pstcXtalStpCfg->enMode; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDRE = pstcXtalStpCfg->enModeReset; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDIE = pstcXtalStpCfg->enModeInt; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the XTAL. + ** + ** \param [in] enNewState The new state of the XTAL. + ** \arg Enable Enable XTAL. + ** \arg Disable Disable XTAL. + ** + ** \retval en_result_t + ** + ** \note XTAL can not be stopped if it is used as system clock source or pll + ** clock source. + ** + ******************************************************************************/ +en_result_t CLK_XtalCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0u; + en_flag_status_t status; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcXTAL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else if(ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC) + { + if(0u == M4_SYSREG->CMU_PLLCR_f.MPLLOFF) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 0u; + do + { + status = CLK_GetFlagStatus(ClkFlagXTALRdy); + timeout++; + }while((timeout < CLK_XTAL_TIMEOUT) && (status != Set)); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the external low speed oscillator(XTAL32). + ** + ** \param [in] pstcXtal32Cfg The XTAL32 configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_Xtal32Config(const stc_clk_xtal32_cfg_t *pstcXtal32Cfg) +{ + if(NULL != pstcXtal32Cfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTAL32CFGR_f.XTAL32DRV = pstcXtal32Cfg->enDrv; + M4_SYSREG->CMU_XTAL32NFR_f.XTAL32NF = pstcXtal32Cfg->enFilterMode; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the XTAL32. + ** + ** \param [in] enNewState The new state of the XTAL32. + ** \arg Enable Enable XTAL32. + ** \arg Disable Disable XTAL32. + ** + ** \retval en_result_t + ** + ** \note XTAL32 can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcXTAL32 == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_XTAL32CR_f.XTAL32STP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTAL32CR_f.XTAL32STP = 0u; + do + { + timeout++; + }while(timeout < CLK_XTAL32_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal high speed oscillator(HRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_HrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_HRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the HRC. + ** + ** \param [in] enNewState The new state of the HRC. + ** \arg Enable Enable HRC. + ** \arg Disable Disable HRC. + ** + ** \retval en_result_t + ** + ** \note HRC can not be stopped if it is used as system clock source or pll + ** clock source. + ** + ******************************************************************************/ +en_result_t CLK_HrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status; + en_result_t enRet = Ok; + + ENABLE_CLOCK_REG_WRITE(); + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if(Disable == enNewState) + { + if(ClkSysSrcHRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else if(ClkPllSrcHRC == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC) + { + if(0u == M4_SYSREG->CMU_PLLCR_f.MPLLOFF) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 0u; + do + { + status = CLK_GetFlagStatus(ClkFlagHRCRdy); + timeout++; + }while((timeout < CLK_HRC_TIMEOUT) && (status != Set)); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal middle speed oscillator(MRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_MrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_MRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the MRC. + ** + ** \param [in] enNewState The new state of the MRC. + ** \arg Enable Enable MRC. + ** \arg Disable Disable MRC. + ** + ** \retval en_result_t + ** + ** \note MRC can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_MrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcMRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_MRCCR_f.MRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_MRCCR_f.MRCSTP = 0u; + do + { + timeout++; + }while(timeout < CLK_MRC_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal low speed oscillator(LRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_LrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_LRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the LRC. + ** + ** \param [in] enNewState The new state of the LRC. + ** \arg Enable Enable LRC. + ** \arg Disable Disable LRC. + ** + ** \retval en_result_t + ** + ** \note LRC can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_LrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcLRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_LRCCR_f.LRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_LRCCR_f.LRCSTP = 0u; + do + { + timeout++; + }while(timeout < CLK_LRC_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Select pll clock source. + ** + ** \param [in] enPllSrc The pll clock source. + ** \arg ClkPllSrcXTAL Select XTAL as pll clock source. + ** \arg ClkPllSrcHRC Select HRC as pll clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetPllSource(en_clk_pll_source_t enPllSrc) +{ + DDL_ASSERT(IS_PLL_SOURCE(enPllSrc)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_PLLCFGR_f.PLLSRC = enPllSrc; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the MPLL. + ** + ** \param [in] pstcMpllCfg The MPLL configures struct. + ** + ** \retval None + ** + ** \note The pllsource/pllm is between 1MHz and 24MHz. + ** The pllsource/pllm*plln is between 240MHz and 480MHz. + ** The maximum of pllsource/pllm*plln/pllp is 200MHz. + ** + ******************************************************************************/ +void CLK_MpllConfig(const stc_clk_mpll_cfg_t *pstcMpllCfg) +{ +#ifdef __DEBUG + uint32_t vcoIn = 0ul; + uint32_t vcoOut = 0ul; +#endif /* #ifdef __DEBUG */ + + if(NULL != pstcMpllCfg) + { + DDL_ASSERT(IS_PLL_DIV_VALID(pstcMpllCfg->PllpDiv)); + DDL_ASSERT(IS_PLLQ_DIV_VALID(pstcMpllCfg->PllqDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcMpllCfg->PllrDiv)); + DDL_ASSERT(IS_PLLN_VALID(pstcMpllCfg->plln)); + DDL_ASSERT(IS_PLLM_VALID(pstcMpllCfg->pllmDiv)); + +#ifdef __DEBUG + vcoIn = ((ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / pstcMpllCfg->pllmDiv); + vcoOut = vcoIn * pstcMpllCfg->plln; + + DDL_ASSERT(IS_PLL_VCO_IN_VALID(vcoIn)); + DDL_ASSERT(IS_PLL_VCO_OUT_VALID(vcoOut)); +#endif /* #ifdef __DEBUG */ + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_PLLCFGR_f.MPLLP = pstcMpllCfg->PllpDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLQ = pstcMpllCfg->PllqDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLR = pstcMpllCfg->PllrDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLN = pstcMpllCfg->plln - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLM = pstcMpllCfg->pllmDiv - 1ul; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the MPLL. + ** + ** \param [in] enNewState The new state of the MPLL. + ** \arg Enable Enable MPLL. + ** \arg Disable Disable MPLL. + ** + ** \retval en_result_t + ** + ** \note MPLL can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_MpllCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 1u; + } + } + else + { + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 0u; + do + { + status = CLK_GetFlagStatus(ClkFlagMPLLRdy); + timeout++; + }while((timeout < CLK_MPLL_TIMEOUT) && (status != Set)); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the UPLL. + ** + ** \param [in] pstcUpllCfg The UPLL configures struct. + ** + ** \retval None + ** + ** \note The pllsource/pllm is between 1MHz and 24MHz. + ** The pllsource/pllm*plln is between 240MHz and 480MHz. + ** The maximum of pllsource/pllm*plln/pllp is 200MHz. + ** + ******************************************************************************/ +void CLK_UpllConfig(const stc_clk_upll_cfg_t *pstcUpllCfg) +{ +#ifdef __DEBUG + uint32_t vcoIn = 0ul; + uint32_t vcoOut = 0ul; +#endif /* #ifdef __DEBUG */ + + if(NULL != pstcUpllCfg) + { + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllpDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllqDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllrDiv)); + DDL_ASSERT(IS_PLLN_VALID(pstcUpllCfg->plln)); + DDL_ASSERT(IS_UPLLM_VALID(pstcUpllCfg->pllmDiv)); + +#ifdef __DEBUG + vcoIn = ((ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / pstcUpllCfg->pllmDiv); + vcoOut = vcoIn * pstcUpllCfg->plln; + + DDL_ASSERT(IS_PLL_VCO_IN_VALID(vcoIn)); + DDL_ASSERT(IS_PLL_VCO_OUT_VALID(vcoOut)); +#endif /* #ifdef __DEBUG */ + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UPLLCFGR_f.UPLLP = pstcUpllCfg->PllpDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLQ = pstcUpllCfg->PllqDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLR = pstcUpllCfg->PllrDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLN = pstcUpllCfg->plln - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLM = pstcUpllCfg->pllmDiv - 1u; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the UPLL. + ** + ** \param [in] enNewState The new state of the UPLL. + ** \arg Enable Enable UPLL. + ** \arg Disable Disable UPLL. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t CLK_UpllCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UPLLCR_f.UPLLOFF = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_CLOCK_REG_WRITE(); + + do + { + status = CLK_GetFlagStatus(ClkFlagUPLLRdy); + timeout++; + }while((timeout < CLK_UPLL_TIMEOUT) && (status != ((Enable == enNewState) ? Set : Reset))); + + return Ok; +} + + +/** + ******************************************************************************* + ** \brief Select system clock source. + ** + ** \param [in] enTargetSysSrc The system clock source. + ** \arg ClkSysSrcHRC Select HRC as system clock source. + ** \arg ClkSysSrcMRC Select MRC as system clock source. + ** \arg ClkSysSrcLRC Select LRC as system clock source. + ** \arg ClkSysSrcXTAL Select XTAL as system clock source. + ** \arg ClkSysSrcXTAL32 Select XTAL32 as system clock source. + ** \arg CLKSysSrcMPLL Select MPLL as system clock source. + ** + ** \retval None + ** + ** \note Must close all of the fcg register before switch system clock source. + ** + ******************************************************************************/ +void CLK_SetSysClkSource(en_clk_sys_source_t enTargetSysSrc) +{ + __IO uint32_t timeout = 0ul; + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + DDL_ASSERT(IS_SYSCLK_SOURCE(enTargetSysSrc)); + + ENABLE_FCG0_REG_WRITE(); + + /* Only current system clock source or target system clock source is MPLL + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if((CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) || + (CLKSysSrcMPLL == enTargetSysSrc)) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = DEFAULT_FCG0; + M4_MSTP->FCG1 = DEFAULT_FCG1; + M4_MSTP->FCG2 = DEFAULT_FCG2; + M4_MSTP->FCG3 = DEFAULT_FCG3; + + /* Wait stable after close fcg. */ + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + + /* Switch to target system clock source. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_CKSWR_f.CKSW = enTargetSysSrc; + + DISABLE_CLOCK_REG_WRITE(); + + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_SYSCLK_STABLE); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + DISABLE_FCG0_REG_WRITE(); + + /* Wait stable after open fcg. */ + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + + SystemCoreClockUpdate(); +} + +/** + ******************************************************************************* + ** \brief Get system clock source. + ** + ** \param None + ** + ** \retval The system clock source. + ** + ** \note None + ** + ******************************************************************************/ +en_clk_sys_source_t CLK_GetSysClkSource(void) +{ + return (en_clk_sys_source_t)M4_SYSREG->CMU_CKSWR_f.CKSW; +} + + +/** + ******************************************************************************* + ** \brief Configures the division factor for hclk,exck,pclk0,pclk1,pclk2,pclk3, + ** pclk4 from system clock. + ** + ** \param [in] pstcSysclkCfg The system clock configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SysClkConfig(const stc_clk_sysclk_cfg_t *pstcSysclkCfg) +{ + __IO uint32_t timeout = 0ul; + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + ENABLE_FCG0_REG_WRITE(); + + if(NULL != pstcSysclkCfg) + { + DDL_ASSERT(IS_SYSCLK_CONFIG_VALID(pstcSysclkCfg)); + + /* Only current system clock source is MPLL need to close fcg0~fcg3 and + open fcg0~fcg3 during switch system clock division. + We need to backup fcg0~fcg3 before close them. */ + if(CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = DEFAULT_FCG0; + M4_MSTP->FCG1 = DEFAULT_FCG1; + M4_MSTP->FCG2 = DEFAULT_FCG2; + M4_MSTP->FCG3 = DEFAULT_FCG3; + + /* Wait stable after close fcg. */ + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + + /* Switch to target system clock division. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_SCFGR = ( (uint32_t)pstcSysclkCfg->enPclk0Div | + ((uint32_t)pstcSysclkCfg->enPclk1Div << 4u) | + ((uint32_t)pstcSysclkCfg->enPclk2Div << 8u) | + ((uint32_t)pstcSysclkCfg->enPclk3Div << 12u) | + ((uint32_t)pstcSysclkCfg->enPclk4Div << 16u) | + ((uint32_t)pstcSysclkCfg->enExclkDiv << 20u) | + ((uint32_t)pstcSysclkCfg->enHclkDiv << 24u) | + ((uint32_t)pstcSysclkCfg->enHclkDiv << 28u)); + + DISABLE_CLOCK_REG_WRITE(); + + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_SYSCLK_STABLE); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + DISABLE_FCG0_REG_WRITE(); + + /* Wait stable after open fcg. */ + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + else + { + /* code */ + } +} + + +/** + ******************************************************************************* + ** \brief Get clock frequency. + ** + ** \param [in] pstcClkFreq The clock source struct. + ** + ** \retval The clock frequency include system clock,hclk,exck,pclk0,pclk1,pclk2 + ** pclk3,pclk4. + ** + ** \note None + ** + ******************************************************************************/ +void CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq) +{ + uint32_t plln = 0u, pllp = 0u, pllm = 0u, pllsource = 0u; + + if(NULL != pstcClkFreq) + { + /* Get system clock. */ + switch(M4_SYSREG->CMU_CKSWR_f.CKSW) + { + case ClkSysSrcHRC: + /* HRC used as system clock. */ + pstcClkFreq->sysclkFreq = HRC_VALUE; + break; + case ClkSysSrcMRC: + /* MRC used as system clock. */ + pstcClkFreq->sysclkFreq = MRC_VALUE; + break; + case ClkSysSrcLRC: + /* LRC used as system clock. */ + pstcClkFreq->sysclkFreq = LRC_VALUE; + break; + case ClkSysSrcXTAL: + /* XTAL used as system clock. */ + pstcClkFreq->sysclkFreq = XTAL_VALUE; + break; + case ClkSysSrcXTAL32: + /* XTAL32 used as system clock. */ + pstcClkFreq->sysclkFreq = XTAL32_VALUE; + break; + default: + /* MPLLP used as system clock. */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + pllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + plln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + pllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + if (ClkPllSrcXTAL == pllsource) + { + pstcClkFreq->sysclkFreq = (XTAL_VALUE)/(pllm+1u)*(plln+1u)/(pllp+1u); + } + else if (ClkPllSrcHRC == pllsource) + { + pstcClkFreq->sysclkFreq = (HRC_VALUE)/(pllm+1u)*(plln+1u)/(pllp+1u); + } + else + { + //else + } + break; + } + + /* Get hclk. */ + pstcClkFreq->hclkFreq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.HCLKS; + + /* Get exck. */ + pstcClkFreq->exckFreq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.EXCKS; + + /* Get pclk0. */ + pstcClkFreq->pclk0Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK0S; + + /* Get pclk1. */ + pstcClkFreq->pclk1Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK1S; + + /* Get pclk2. */ + pstcClkFreq->pclk2Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK2S; + + /* Get pclk3. */ + pstcClkFreq->pclk3Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK3S; + + /* Get pclk4. */ + pstcClkFreq->pclk4Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK4S; + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Get PLL clock frequency. + ** + ** \param [in] pstcPllClkFreq The PLL clock source struct. + ** + ** \retval The clock frequency include mpllp, mpllq, mpllr, upllp, upllq, upllr. + ** + ** \note None + ** + ******************************************************************************/ +void CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq) +{ + uint32_t pllsource; + uint32_t mplln = 0u, mpllp = 0u, mpllq = 0u, mpllr = 0u, mpllm = 0u; + uint32_t uplln = 0u, upllp = 0u, upllq = 0u, upllr = 0u, upllm = 0u; + + /* Get pll clock source */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + + /* Get Mpll parameter value */ + mpllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + mpllq = M4_SYSREG->CMU_PLLCFGR_f.MPLLQ; + mpllr = M4_SYSREG->CMU_PLLCFGR_f.MPLLR; + mplln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + mpllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + + /* Get Upll paramter value */ + upllp = M4_SYSREG->CMU_UPLLCFGR_f.UPLLP; + upllq = M4_SYSREG->CMU_UPLLCFGR_f.UPLLQ; + upllr = M4_SYSREG->CMU_UPLLCFGR_f.UPLLR; + uplln = M4_SYSREG->CMU_UPLLCFGR_f.UPLLN; + upllm = M4_SYSREG->CMU_UPLLCFGR_f.UPLLM; + + /* Get mpllp ,mpllr, mpllq, upllp, upllq, upllr clock frequency */ + if (ClkPllSrcXTAL == pllsource) + { + pstcPllClkFreq->mpllp = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllp+1u); + pstcPllClkFreq->mpllq = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllq+1u); + pstcPllClkFreq->mpllr = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllr+1u); + pstcPllClkFreq->upllp = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllp+1u); + pstcPllClkFreq->upllq = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllq+1u); + pstcPllClkFreq->upllr = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllr+1u); + } + else if (ClkPllSrcHRC == pllsource) + { + pstcPllClkFreq->mpllp = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllp+1u); + pstcPllClkFreq->mpllq = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllq+1u); + pstcPllClkFreq->mpllr = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllr+1u); + pstcPllClkFreq->upllp = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllp+1u); + pstcPllClkFreq->upllq = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllq+1u); + pstcPllClkFreq->upllr = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllr+1u); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Select usb clock source. + ** + ** \param [in] enTargetUsbSrc The usb clock source. + ** \arg ClkUsbSrcSysDiv2 Select 1/2 system clock as usb clock source. + ** \arg ClkUsbSrcSysDiv3 Select 1/3 system clock as usb clock source. + ** \arg ClkUsbSrcSysDiv4 Select 1/4 system clock as usb clock source. + ** \arg ClkUsbSrcMpllp Select MPLLP as usb clock source. + ** \arg ClkUsbSrcMpllq Select MPLLQ as usb clock source. + ** \arg ClkUsbSrcMpllr Select MPLLR as usb clock source. + ** \arg ClkUsbSrcUpllp Select UPLLP as usb clock source. + ** \arg ClkUsbSrcUpllq Select UPLLQ as usb clock source. + ** \arg ClkUsbSrcUpllr Select UPLLR as usb clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetUsbClkSource(en_clk_usb_source_t enTargetUsbSrc) +{ + + DDL_ASSERT(IS_USBCLK_SOURCE(enTargetUsbSrc)); + + /* Switch to target usb clock source. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UFSCKCFGR_f.USBCKS = enTargetUsbSrc; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Select peripheral(adc/trng) clock source. + ** + ** \param [in] enTargetPeriSrc The peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcPclk Select PCLK2 as adc analog clok, PCLK4 as adc digital clock. Select PCLK4 as trng clock. + ** \arg ClkPeriSrcMpllp Select MPLLP as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcMpllq Select MPLLQ as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcMpllr Select MPLLR as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllp Select UPLLP as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllq Select UPLLQ as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllr Select UPLLR as peripheral(adc/trng) clock source. + ** + ** \retval None + ** + ******************************************************************************/ +void CLK_SetPeriClkSource(en_clk_peri_source_t enTargetPeriSrc) +{ + DDL_ASSERT(IS_PERICLK_SOURCE(enTargetPeriSrc)); + + ENABLE_CLOCK1_REG_WRITE(); + + /* Switch to target adc clock source. */ + M4_SYSREG->CMU_PERICKSEL_f.PERICKSEL = enTargetPeriSrc; + + DISABLE_CLOCK1_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Select I2S clock source. + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** \param [in] enTargetPeriSrc The I2S clock source. + ** \arg ClkPeriSrcPclk Select PCLK3 as I2S clock source. + ** \arg ClkPeriSrcMpllp Select MPLLP as I2S clock source. + ** \arg ClkPeriSrcMpllq Select MPLLQ as I2S clock source. + ** \arg ClkPeriSrcMpllr Select MPLLR as I2S clock source. + ** \arg ClkPeriSrcUpllp Select UPLLP as I2S clock source. + ** \arg ClkPeriSrcUpllq Select UPLLQ as I2S clock source. + ** \arg ClkPeriSrcUpllr Select UPLLR as I2S clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg, en_clk_peri_source_t enTargetPeriSrc) +{ + DDL_ASSERT(IS_PERICLK_SOURCE(enTargetPeriSrc)); + + ENABLE_CLOCK1_REG_WRITE(); + + if(M4_I2S1 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S1CKSEL = enTargetPeriSrc; + } + else if(M4_I2S2 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S2CKSEL = enTargetPeriSrc; + } + else if(M4_I2S3 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S3CKSEL = enTargetPeriSrc; + } + else if(M4_I2S4 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S4CKSEL = enTargetPeriSrc; + } + else + { + /* code */ + } + + DISABLE_CLOCK1_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get I2S clock source. + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** + ** \retval en_clk_peri_source_t The I2S clock source. + ** + ** \note None + ** + ******************************************************************************/ +en_clk_peri_source_t CLK_GetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg) +{ + en_clk_peri_source_t enI2sClkSource = ClkPeriSrcPclk; + + if(M4_I2S1 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S1CKSEL; + } + else if(M4_I2S2 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S2CKSEL; + } + else if(M4_I2S3 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S3CKSEL; + } + else if(M4_I2S4 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S4CKSEL; + } + else + { + /* code */ + } + + return enI2sClkSource; +} + +/** + ******************************************************************************* + ** \brief Configures the debug clock. + ** + ** \param [in] enTpiuDiv The division of debug clock from system + ** clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_TpiuClkConfig(const en_clk_tpiuclk_div_factor_t enTpiuDiv) +{ + DDL_ASSERT(IS_TPIUCLK_DIV_VALID(enTpiuDiv)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_TPIUCKCFGR_f.TPIUCKS = enTpiuDiv; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the debug clock. + ** + ** \param [in] enNewState The new state of the debug clock. + ** \arg Enable Enable debug clock. + ** \arg Disable Disable debug clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_TpiuClkCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_TPIUCKCFGR_f.TPIUCKOE = enNewState; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the output clock. + ** + ** \param [in] enCh The clock output channel. + ** \param [in] pstcOutputCfg The clock output configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_OutputClkConfig(en_clk_output_ch_t enCh, const stc_clk_output_cfg_t *pstcOutputCfg) +{ + if(NULL != pstcOutputCfg) + { + DDL_ASSERT(IS_OUTPUTCLK_CHANNEL(enCh)); + DDL_ASSERT(IS_OUTPUTCLK_SOURCE(pstcOutputCfg->enOutputSrc)); + DDL_ASSERT(IS_OUTPUTCLK_DIV_VALID(pstcOutputCfg->enOutputDiv)); + + ENABLE_CLOCK_REG_WRITE(); + + switch(enCh) + { + case ClkOutputCh1: + M4_SYSREG->CMU_MCO1CFGR_f.MCO1SEL = pstcOutputCfg->enOutputSrc; + M4_SYSREG->CMU_MCO1CFGR_f.MCO1DIV = pstcOutputCfg->enOutputDiv; + break; + case ClkOutputCh2: + M4_SYSREG->CMU_MCO2CFGR_f.MCO2SEL = pstcOutputCfg->enOutputSrc; + M4_SYSREG->CMU_MCO2CFGR_f.MCO2DIV = pstcOutputCfg->enOutputDiv; + break; + default: + break; + } + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the clock output. + ** + ** \param [in] enCh The clock output channel. + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_OutputClkCmd(en_clk_output_ch_t enCh, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + switch(enCh) + { + case ClkOutputCh1: + M4_SYSREG->CMU_MCO1CFGR_f.MCO1EN = enNewState; + break; + case ClkOutputCh2: + M4_SYSREG->CMU_MCO2CFGR_f.MCO2EN = enNewState; + break; + default: + break; + } + + DISABLE_CLOCK_REG_WRITE(); +} + + +/** + ******************************************************************************* + ** \brief Get the specified clock flag status. + ** + ** \param [in] enClkFlag The specified clock flag. + ** \arg ClkFlagHRCRdy HRC is ready or not. + ** \arg ClkFlagXTALRdy XTAL is ready or not. + ** \arg ClkFlagMPLLRdy MPLL is ready or not. + ** \arg ClkFlagUPLLRdy UPLL is ready or not. + ** \arg ClkFlagXTALStoppage XTAL is detected stoppage or not. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t CLK_GetFlagStatus(en_clk_flag_t enClkFlag) +{ + en_flag_status_t status; + + DDL_ASSERT(IS_CLK_FLAG(enClkFlag)); + + switch(enClkFlag) + { + case ClkFlagHRCRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.HRCSTBF) ? Set : Reset); + break; + case ClkFlagXTALRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.XTALSTBF) ? Set : Reset); + break; + case ClkFlagMPLLRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.MPLLSTBF) ? Set : Reset); + break; + case ClkFlagUPLLRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.UPLLSTBF) ? Set : Reset); + break; + default: + status = ((1u == M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF) ? Set : Reset); + break; + } + + return status; +} + + +/** + ******************************************************************************* + ** \brief Configures the clock frequency measurement. + ** + ** \param [in] pstcClkFcmCfg The clock frequency measurement configures + ** struct. + ** + ** \retval None + ** + ** \note Configures the window,measurement,reference and interrupt independently. + ** + ******************************************************************************/ +void CLK_FcmConfig(const stc_clk_fcm_cfg_t *pstcClkFcmCfg) +{ + if(NULL != pstcClkFcmCfg) + { + /* Window config. */ + if(pstcClkFcmCfg->pstcFcmWindowCfg) + { + /* Set window lower. */ + M4_FCM->LVR = pstcClkFcmCfg->pstcFcmWindowCfg->windowLower; + /* Set window upper. */ + M4_FCM->UVR = pstcClkFcmCfg->pstcFcmWindowCfg->windowUpper; + } + + /* Measure config. */ + if(pstcClkFcmCfg->pstcFcmMeaCfg) + { + DDL_ASSERT(IS_FCM_SOURCE(pstcClkFcmCfg->pstcFcmMeaCfg->enSrc)); + DDL_ASSERT(IS_FCM_MEASRC_DIV_VALID(pstcClkFcmCfg->pstcFcmMeaCfg->enSrcDiv)); + + /* Measure source. */ + M4_FCM->MCCR_f.MCKS = pstcClkFcmCfg->pstcFcmMeaCfg->enSrc; + /* Measure source division. */ + M4_FCM->MCCR_f.MDIVS = pstcClkFcmCfg->pstcFcmMeaCfg->enSrcDiv; + } + + /* Reference config. */ + if(pstcClkFcmCfg->pstcFcmRefCfg) + { + DDL_ASSERT(IS_FCM_REF(pstcClkFcmCfg->pstcFcmRefCfg->enRefSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmRefCfg->enExtRef)); + DDL_ASSERT(IS_FCM_SOURCE(pstcClkFcmCfg->pstcFcmRefCfg->enIntRefSrc)); + DDL_ASSERT(IS_FCM_INTREF_DIV_VALID(pstcClkFcmCfg->pstcFcmRefCfg->enIntRefDiv)); + DDL_ASSERT(IS_FCM_EDGE(pstcClkFcmCfg->pstcFcmRefCfg->enEdge)); + DDL_ASSERT(IS_FCM_FILTER_CLK(pstcClkFcmCfg->pstcFcmRefCfg->enFilterClk)); + + M4_FCM->RCCR_f.INEXS = pstcClkFcmCfg->pstcFcmRefCfg->enRefSel; + M4_FCM->RCCR_f.EXREFE = pstcClkFcmCfg->pstcFcmRefCfg->enExtRef; + M4_FCM->RCCR_f.RCKS = pstcClkFcmCfg->pstcFcmRefCfg->enIntRefSrc; + M4_FCM->RCCR_f.RDIVS = pstcClkFcmCfg->pstcFcmRefCfg->enIntRefDiv; + M4_FCM->RCCR_f.EDGES = pstcClkFcmCfg->pstcFcmRefCfg->enEdge; + M4_FCM->RCCR_f.DNFS = pstcClkFcmCfg->pstcFcmRefCfg->enFilterClk; + } + + /* Interrupt config. */ + if(pstcClkFcmCfg->pstcFcmIntCfg) + { + DDL_ASSERT(IS_FCM_HANDLE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleReset)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleInterrupt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enOvfInterrupt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enEndInterrupt)); + + M4_FCM->RIER_f.ERRINTRS = pstcClkFcmCfg->pstcFcmIntCfg->enHandleSel; + M4_FCM->RIER_f.ERRE = pstcClkFcmCfg->pstcFcmIntCfg->enHandleReset; + M4_FCM->RIER_f.ERRIE = pstcClkFcmCfg->pstcFcmIntCfg->enHandleInterrupt; + M4_FCM->RIER_f.MENDIE = pstcClkFcmCfg->pstcFcmIntCfg->enEndInterrupt; + M4_FCM->RIER_f.OVFIE = pstcClkFcmCfg->pstcFcmIntCfg->enOvfInterrupt; + } + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the clock frequency measurement. + ** + ** \param [in] enNewState The new state of the clock frequency + ** measurement. + ** \arg Enable Enable clock frequency measurement. + ** \arg Disable Disable clock frequency measurement. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_FcmCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_FCM->STR = enNewState; +} + +/** + ******************************************************************************* + ** \brief Get fcm counter value. + ** + ** \param None + ** + ** \retval The fcm counter value. + ** + ** \note None + ** + ******************************************************************************/ +uint16_t CLK_GetFcmCounter(void) +{ + return (uint16_t)(M4_FCM->CNTR & 0xFFFFu); +} + +/** + ******************************************************************************* + ** \brief Get the specified fcm flag status. + ** + ** \param [in] enFcmFlag The specified fcm flag. + ** \arg ClkFcmFlagOvf The fcm counter overflow or not. + ** \arg ClkFcmFlagMendf The end of the measurement or not. + ** \arg ClkFcmFlagErrf Whether the frequency is abnormal or not. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t CLK_GetFcmFlag(en_clk_fcm_flag_t enFcmFlag) +{ + en_flag_status_t status = Reset; + + DDL_ASSERT(IS_FCM_FLAG(enFcmFlag)); + + switch(enFcmFlag) + { + case ClkFcmFlagOvf: + status = (en_flag_status_t)M4_FCM->SR_f.OVF; + break; + case ClkFcmFlagMendf: + status = (en_flag_status_t)M4_FCM->SR_f.MENDF; + break; + case ClkFcmFlagErrf: + status = (en_flag_status_t)M4_FCM->SR_f.ERRF; + break; + default: + break; + } + + return status; +} + +/** + ******************************************************************************* + ** \brief Clear the specified fcm flag status. + ** + ** \param [in] enFcmFlag The specified fcm flag. + ** \arg ClkFcmFlagOvf Clear the fcm counter overflow flag. + ** \arg ClkFcmFlagMendf Clear the end of the measurement flag. + ** \arg ClkFcmFlagErrf Clear the frequency abnormal flag. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_ClearFcmFlag(en_clk_fcm_flag_t enFcmFlag) +{ + DDL_ASSERT(IS_FCM_FLAG(enFcmFlag)); + + switch(enFcmFlag) + { + case ClkFcmFlagOvf: + M4_FCM->CLR_f.OVFCLR = Set; + break; + case ClkFcmFlagMendf: + M4_FCM->CLR_f.MENDFCLR = Set; + break; + case ClkFcmFlagErrf: + M4_FCM->CLR_f.ERRFCLR = Set; + break; + default: + break; + } +} + +/** + ******************************************************************************* + ** \brief Clear the XTAL error flag. + ** + ** \param None + ** + ** \retval None + ** + ** \note The system clock should not be XTAL before call this function. + ** + ******************************************************************************/ +void CLK_ClearXtalStdFlag(void) +{ + /* Enable register write. */ + ENABLE_CLOCK_REG_WRITE(); + + if(Set == M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF) + { + /* Clear the XTAL STD flag */ + M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF = Reset; + } + + /* Disbale register write. */ + DISABLE_CLOCK_REG_WRITE(); +} + + +//@} // CmuGroup + +#endif /* DDL_CLK_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_cmp.c b/driver/src/hc32f460_cmp.c new file mode 100644 index 0000000..dde45b7 --- /dev/null +++ b/driver/src/hc32f460_cmp.c @@ -0,0 +1,1046 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_cmp.c + ** + ** A detailed description is available at + ** @link CmpGroup CMP @endlink + ** + ** - 2018-10-22 CDT First version for Device Driver Library of CMP. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_cmp.h" +#include "hc32f460_utility.h" + +#if (DDL_CMP_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CmpGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for CMP Instances. */ +#define IS_VALID_CMP(__CMPx__) \ +( (M4_CMP1 == (__CMPx__)) || \ + (M4_CMP2 == (__CMPx__)) || \ + (M4_CMP3 == (__CMPx__))) + +/*!< Parameter valid check for CMP function */ +#define IS_VALID_CMP_FUNCTION(x) \ +( (CmpOutput == (x)) || \ + (CmpOutpuInv == (x)) || \ + (CmpVcoutOutput == (x))) + +/*! Parameter validity check for edge sel. */ +#define IS_VALID_EDGESEL(x) \ +( (CmpNoneEdge == (x)) || \ + (CmpBothEdge == (x)) || \ + (CmpRisingEdge == (x)) || \ + (CmpFaillingEdge == (x))) + +/*!< Parameter CMP FLT validity check for clock division. */ +#define IS_VALID_FLTCLK_DIVISION(x) \ +( (CmpNoneFlt == (x)) || \ + (CmpFltPclk3Div1 == (x)) || \ + (CmpFltPclk3Div2 == (x)) || \ + (CmpFltPclk3Div4 == (x)) || \ + (CmpFltPclk3Div8 == (x)) || \ + (CmpFltPclk3Div16 == (x)) || \ + (CmpFltPclk3Div32 == (x)) || \ + (CmpFltPclk3Div64 == (x))) + +/*!< Parameter validity check for INP4 SEL. */ +#define IS_VALID_INP4SEL(x) \ +( (CmpInp4None == (x)) || \ + (CmpInp4PGAO == (x)) || \ + (CmpInp4PGAO_BP == (x)) || \ + (CmpInp4CMP1_INP4 == (x))) + +/*!< Parameter validity check for INP INPUT SEL. */ +#define IS_VALID_INPSEL(x) \ +( (CmpInpNone == (x)) || \ + (CmpInp1 == (x)) || \ + (CmpInp2 == (x)) || \ + (CmpInp3 == (x)) || \ + (CmpInp4 == (x)) || \ + (CmpInp1_Inp2 == (x)) || \ + (CmpInp1_Inp3 == (x)) || \ + (CmpInp2_Inp3 == (x)) || \ + (CmpInp1_Inp4 == (x)) || \ + (CmpInp2_Inp4 == (x)) || \ + (CmpInp3_Inp4 == (x)) || \ + (CmpInp1_Inp2_Inp3 == (x)) || \ + (CmpInp1_Inp2_Inp4 == (x)) || \ + (CmpInp1_Inp3_Inp4 == (x)) || \ + (CmpInp2_Inp3_Inp4 == (x)) || \ + (CmpInp1_Inp2_Inp3_Inp4 == (x))) + +/*!< Parameter validity check for INM INPUT SEL. */ +#define IS_VALID_INMSEL(x) \ +( (CmpInm1 == (x)) || \ + (CmpInm2 == (x)) || \ + (CmpInm3 == (x)) || \ + (CmpInm4 == (x)) || \ + (CmpInmNone == (x))) + +/*!< Parameter validity check for CMP_CR channel. */ +#define IS_VALID_CMP_CR_CH(x) \ +( (CmpDac1 == (x)) || \ + (CmpDac2 == (x))) + +/*!< Parameter validity check for ADC internal reference voltage path. */ +#define IS_VALID_ADC_REF_VOLT_PATH(x) \ +( (CmpAdcRefVoltPathDac1 == (x)) || \ + (CmpAdcRefVoltPathDac2 == (x)) || \ + (CmpAdcRefVoltPathVref == (x))) + +/*!< RVADC Write Protection Key. */ +#define RVADC_WRITE_PROT_KEY (0x5500u) + +/*!< Timer4x ECER register address. */ +#define CMP_CR_DADRx(__DACx__) \ +( (CmpDac1 == (__DACx__)) ? &M4_CMP_CR->DADR1 : &M4_CMP_CR->DADR2) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes the specified CMP. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] pstcInitCfg Pointer to CMP configure structure + ** \arg This parameter detail refer @ref stc_cmp_init_t + ** + ** \retval Ok CMP is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - CMPx is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t CMP_Init(M4_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx && pstcInitCfg pointer */ + if ((IS_VALID_CMP(CMPx)) && (NULL != pstcInitCfg)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_EDGESEL(pstcInitCfg->enEdgeSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpIntEN)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpInvEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpOutputEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpVcoutOutputEn)); + DDL_ASSERT(IS_VALID_FLTCLK_DIVISION(pstcInitCfg->enFltClkDiv)); + + /* De-Initialize CMP */ + CMPx->CTRL = (uint16_t)0x0000u; + CMPx->VLTSEL = (uint16_t)0x0000u; + CMPx->CVSSTB = (uint16_t)0x0005u; + CMPx->CVSPRD = (uint16_t)0x000Fu; + + CMPx->CTRL_f.IEN = (uint16_t)pstcInitCfg->enCmpIntEN; + CMPx->CTRL_f.INV = (uint16_t)pstcInitCfg->enCmpInvEn; + CMPx->CTRL_f.EDGSL = (uint16_t)pstcInitCfg->enEdgeSel; + CMPx->CTRL_f.FLTSL = (uint16_t)pstcInitCfg->enFltClkDiv; + CMPx->CTRL_f.CMPOE = (uint16_t)pstcInitCfg->enCmpOutputEn; + CMPx->CTRL_f.OUTEN = (uint16_t)pstcInitCfg->enCmpVcoutOutputEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize CMP + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_DeInit(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL = (uint16_t)0x0000u; + CMPx->VLTSEL = (uint16_t)0x0000u; + CMPx->CVSSTB = (uint16_t)0x0005u; + CMPx->CVSPRD = (uint16_t)0x000Fu; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP working + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enCmd The CMP function state + ** \arg Disable Disable CMP working + ** \arg Enable Enable CMP working + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_Cmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + CMPx->CTRL_f.CMPON = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP interrupt request + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enCmd The CMP interrupt function state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ******************************************************************************/ +en_result_t CMP_IrqCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.IEN = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set scan time(scan stable&&period) + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] u8ScanStable CMP scan stable value + ** \arg u8ScanStable < 16 + ** \param [in] u8ScanPeriod CMP scan period value + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ** \note u8ScanStable && u8ScanPeriod value must meet following condition: + ** u8ScanPeriod > u8ScanStable + FLTSL_DIV*4 + 5 + ** FLTSL_DIV is filter sample period division(refer CMPx->CTRL_f.FLTSL) + ** + ******************************************************************************/ +en_result_t CMP_SetScanTime(M4_CMP_TypeDef *CMPx, + uint8_t u8ScanStable, + uint8_t u8ScanPeriod) +{ + uint16_t u16Flts; + uint16_t u16FltslDiv; + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if ((!IS_VALID_CMP(CMPx)) || (u8ScanStable & 0xF0u)) + { + enRet = ErrorInvalidParameter; + } + else + { + u16Flts = CMPx->CTRL_f.FLTSL; + u16FltslDiv = ((uint16_t)1u << (u16Flts - 1u)); + + if ((0u != u16Flts) && + (u8ScanPeriod <= (u8ScanStable + u16FltslDiv * 4u + 5u))) + { + enRet = ErrorInvalidParameter; + } + else + { + CMPx->CVSSTB_f.STB = u8ScanStable; + CMPx->CVSPRD_f.PRD = u8ScanPeriod; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the specified CMP function. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enFunc CMP function selection + ** \arg CmpVcoutOutput CMP Vcout output enable function + ** \arg CmpOutpuInv CMP output invert enable function + ** \arg CmpOutput CMP output enable function + ** \param [in] enCmd CMP functional state + ** \arg Enable Enable the specified CMP function + ** \arg Disable Disable the specified CMP function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_FuncCmd(M4_CMP_TypeDef *CMPx, + en_cmp_func_t enFunc, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_CMP_FUNCTION(enFunc)); + + if (Enable == enCmd) + { + CMPx->CTRL |= (uint16_t)enFunc; + } + else + { + CMPx->CTRL &= (uint16_t)(~((uint16_t)enFunc)); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start CMP scan + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Start successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_StartScan(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.CVSEN = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop CMP scan + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Stop successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_StopScan(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.CVSEN = (uint16_t)0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP filter sample clock division. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enFltClkDiv The CMP filter sample clock division selection + ** \arg CmpNoneFlt Unuse filter + ** \arg CmpFltPclk3Div1 PCLK3/1 + ** \arg CmpFltPclk3Div2 PCLK3/2 + ** \arg CmpFltPclk3Div4 PCLK3/4 + ** \arg CmpFltPclk3Div8 PCLK3/8 + ** \arg CmpFltPclk3Div16 PCLK3/16 + ** \arg CmpFltPclk3Div32 PCLK3/32 + ** \arg CmpFltPclk3Div64 PCLK3/64 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetFilterClkDiv(M4_CMP_TypeDef *CMPx, + en_cmp_fltclk_div_t enFltClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_FLTCLK_DIVISION(enFltClkDiv)); + CMPx->CTRL_f.FLTSL = (uint16_t)enFltClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP filter sample clock division. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpNoneFlt Unuse filter + ** \retval CmpFltPclk3Div1 PCLK3/1 + ** \retval CmpFltPclk3Div2 PCLK3/2 + ** \retval CmpFltPclk3Div4 PCLK3/4 + ** \retval CmpFltPclk3Div8 PCLK3/8 + ** \retval CmpFltPclk3Div16 PCLK3/16 + ** \retval CmpFltPclk3Div32 PCLK3/32 + ** \retval CmpFltPclk3Div64 PCLK3/64 + ** + ******************************************************************************/ +en_cmp_fltclk_div_t CMP_GetFilterClkDiv(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_fltclk_div_t)CMPx->CTRL_f.FLTSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP detection edge selection. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enEdgeSel The CMP detection edge selection + ** \arg CmpNoneEdge None edge detection + ** \arg CmpRisingEdge Rising edge detection + ** \arg CmpFaillingEdge Falling edge detection + ** \arg CmpBothEdge Falling or Rising edge detection + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetEdgeSel(M4_CMP_TypeDef *CMPx, + en_cmp_edge_sel_t enEdgeSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_EDGESEL(enEdgeSel)); + CMPx->CTRL_f.EDGSL = (uint16_t)enEdgeSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP detection edge selection. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpNoneEdge None edge detection + ** \retval CmpRisingEdge Rising edge detection + ** \retval CmpFaillingEdge Falling edge detection + ** \retval CmpBothEdge Falling or Rising edge detection + ** + ******************************************************************************/ +en_cmp_edge_sel_t CMP_GetEdgeSel(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_edge_sel_t)CMPx->CTRL_f.EDGSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP input sel + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] pstcInputSel The CMP input selection structure + ** \arg This parameter detail refer @ref stc_cmp_input_sel_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_InputSel(M4_CMP_TypeDef *CMPx, + const stc_cmp_input_sel_t *pstcInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx && pstcInputSel pointer */ + if ((IS_VALID_CMP(CMPx)) && (NULL != pstcInputSel)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INMSEL(pstcInputSel->enInmSel)); + DDL_ASSERT(IS_VALID_INPSEL(pstcInputSel->enInpSel)); + DDL_ASSERT(IS_VALID_INP4SEL(pstcInputSel->enInp4Sel)); + + if ((CmpInp4PGAO == pstcInputSel->enInp4Sel) || + (CmpInp4PGAO_BP == pstcInputSel->enInp4Sel)) + { + if (M4_CMP3 != CMPx) + { + enRet = Ok; + } + } + else if (CmpInp4CMP1_INP4 == pstcInputSel->enInp4Sel) + { + if (M4_CMP1 == CMPx) + { + enRet = Ok; + } + } + else + { + enRet = Ok; + } + + if (enRet == Ok) + { + CMPx->VLTSEL_f.CVSL = (uint16_t)pstcInputSel->enInpSel; + CMPx->VLTSEL_f.RVSL = (uint16_t)pstcInputSel->enInmSel; + CMPx->VLTSEL_f.C4SL = (uint16_t)pstcInputSel->enInp4Sel; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInpNone None input + ** \arg CmpInp1 INP1 input + ** \arg CmpInp2 INP2 input + ** \arg CmpInp1_Inp2 INP1 INP2 input + ** \arg CmpInp3 INP3 input + ** \arg CmpInp1_Inp3 INP1 INP3 input + ** \arg CmpInp2_Inp3 INP2 INP3 input + ** \arg CmpInp1_Inp2_Inp3 INP1 INP2 INP3 input + ** \arg CmpInp4 INP4 input + ** \arg CmpInp1_Inp4 INP1 INP4 input + ** \arg CmpInp2_Inp4 INP2 INP4 input + ** \arg CmpInp1_Inp2_Inp4 INP1 INP2 INP4 input + ** \arg CmpInp3_Inp4 INP3 INP4 input + ** \arg CmpInp1_Inp3_Inp4 INP1 INP3 INP4 input + ** \arg CmpInp2_Inp3_Inp4 INP2 INP3 INP4 input + ** \arg CmpInp1_Inp2_Inp3_Inp4 INP1 INP2 INP3 INP4 input + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetInp(M4_CMP_TypeDef *CMPx, en_cmp_inp_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INPSEL(enInputSel)); + CMPx->VLTSEL_f.CVSL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInpNone None input + ** \retval CmpInp1 INP1 input + ** \retval CmpInp2 INP2 input + ** \retval CmpInp1_Inp2 INP1 INP2 input + ** \retval CmpInp3 INP3 input + ** \retval CmpInp1_Inp3 INP1 INP3 input + ** \retval CmpInp2_Inp3 INP2 INP3 input + ** \retval CmpInp1_Inp2_Inp3 INP1 INP2 INP3 input + ** \retval CmpInp4 INP4 input + ** \retval CmpInp1_Inp4 INP1 INP4 input + ** \retval CmpInp2_Inp4 INP2 INP4 input + ** \retval CmpInp1_Inp2_Inp4 INP1 INP2 INP4 input + ** \retval CmpInp3_Inp4 INP3 INP4 input + ** \retval CmpInp1_Inp3_Inp4 INP1 INP3 INP4 input + ** \retval CmpInp2_Inp3_Inp4 INP2 INP3 INP4 input + ** \retval CmpInp1_Inp2_Inp3_Inp4 INP1 INP2 INP3 INP4 input + ** + ******************************************************************************/ +en_cmp_inp_sel_t CMP_GetInp(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp_sel_t)CMPx->VLTSEL_f.CVSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP INM input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInmNone None input + ** \arg CmpInm1 INM1 input + ** \arg CmpInm2 INM2 input + ** \arg CmpInm3 INM3 input + ** \arg CmpInm4 INM4 input + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ******************************************************************************/ +en_result_t CMP_SetInm(M4_CMP_TypeDef *CMPx, en_cmp_inm_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INMSEL(enInputSel)); + CMPx->VLTSEL_f.RVSL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP INM input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInmNone None input + ** \retval CmpInm1 INM1 input + ** \retval CmpInm2 INM2 input + ** \retval CmpInm3 INM3 input + ** \retval CmpInm4 INM4 input + ** + ******************************************************************************/ +en_cmp_inm_sel_t CMP_GetInm(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inm_sel_t)CMPx->VLTSEL_f.RVSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP4 input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInp4None None input + ** \arg CmpInp4PGAO PGAO output + ** \arg CmpInp4PGAO_BP PGAO_BP output + ** \arg CmpInp4CMP1_INP4 CMP1_INP4 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ** \note Inp4 Selection is valid only for M4_CMP1 + ** and M4_CMP2. + ** + ******************************************************************************/ +en_result_t CMP_SetInp4(M4_CMP_TypeDef *CMPx,en_cmp_inp4_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + DDL_ASSERT(M4_CMP3 != CMPx); + DDL_ASSERT(IS_VALID_INP4SEL(enInputSel)); + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->VLTSEL_f.C4SL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP INP4 input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInp4None None input + ** \retval CmpInp4PGAO PGAO output + ** \retval CmpInp4PGAO_BP PGAO_BP output + ** \retval CmpInp4CMP1_INP4 CMP1_INP4 + ** + ** \note Inp4 Selection is valid only for M4_CMP1 + ** and M4_CMP2. + ** + ******************************************************************************/ +en_cmp_inp4_sel_t CMP_GetInp4(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp4_sel_t)CMPx->VLTSEL_f.C4SL; +} + +/** + ******************************************************************************* + ** \brief Get CMP output state + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpOutputLow Compare output Low "0" + ** \retval CmpOutputHigh Compare output High "1" + ** + ******************************************************************************/ +en_cmp_output_state_t CMP_GetOutputState(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_output_state_t)(CMPx->MON_f.OMON); +} + +/** + ******************************************************************************* + ** \brief Get CMP INP state + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpOutputLow Compare output Low "0" + ** \retval CmpOutputHigh Compare output High "1" + ** + ******************************************************************************/ +en_cmp_inp_state_t CMP_GetInpState(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp_state_t)(CMPx->MON_f.CVST); +} + +/** + ******************************************************************************* + ** \brief Initialize CMP DAC + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** \param [in] pstcInitCfg Pointer to CMP DAC configure structure + ** \arg This parameter detail refer @ref stc_cmp_dac_init_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_Init(en_cmp_dac_ch_t enCh, + const stc_cmp_dac_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_CMP_CR_CH(enCh)) && (pstcInitCfg != NULL)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpDacEN)); + + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); /* Disable DAC */ + + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = pstcInitCfg->u8DacData; /* Set DAC data */ + + if (Enable == pstcInitCfg->enCmpDacEN) + { + M4_CMP_CR->DACR |= (uint16_t)(1ul << enCh); /* Enable DAC */ + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize CMP DAC + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_DeInit(en_cmp_dac_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP DAC working + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP DAC channel: DAC1 + ** \arg CmpDac2 CMP DAC channel: DAC2 + ** \param [in] enCmd The CMP DAC function state + ** \arg Disable Disable CMP DAC working + ** \arg Enable Enable CMP DAC working + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_Cmd(en_cmp_dac_ch_t enCh, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + if(Enable == enCmd) + { + M4_CMP_CR->DACR |= (uint16_t)(1ul << enCh); + } + else + { + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DAC data register value + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** \param [in] u8DacData DAC data register value + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_SetData(en_cmp_dac_ch_t enCh, uint8_t u8DacData) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = u8DacData; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DAC data register value + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** + ** \retval DAC data register value + ** + ******************************************************************************/ +uint8_t CMP_DAC_GetData(en_cmp_dac_ch_t enCh) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP_CR_CH(enCh)); + + return *(__IO uint8_t *)CMP_CR_DADRx(enCh); +} + +/** + ******************************************************************************* + ** \brief Set ADC internal reference voltage path + ** + ** \param [in] enRefVoltPath ADC internal reference voltage path + ** \arg CmpAdcRefVoltPathDac1 ADC internal reference voltage path: DAC1 + ** \arg CmpAdcRefVoltPathDac2 ADC internal reference voltage path: DAC2 + ** \arg CmpAdcRefVoltPathVref ADC internal reference voltage path: VREF + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enRefVoltPath is invalid. + ** + ******************************************************************************/ +en_result_t CMP_ADC_SetRefVoltPath(en_cmp_adc_int_ref_volt_path_t enRefVoltPath) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_ADC_REF_VOLT_PATH(enRefVoltPath)) + { + M4_CMP_CR->RVADC = RVADC_WRITE_PROT_KEY; /* Release write protection */ + M4_CMP_CR->RVADC = enRefVoltPath; /* Set reference voltage path */ + enRet = Ok; + } + + return enRet; +} + +//@} // CmpGroup + +#endif /* DDL_CMP_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_crc.c b/driver/src/hc32f460_crc.c new file mode 100644 index 0000000..1cdf7fb --- /dev/null +++ b/driver/src/hc32f460_crc.c @@ -0,0 +1,327 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_crc.c + ** + ** A detailed description is available at + ** @link CrcGroup Crc description @endlink + ** + ** - 2019-03-07 CDT First version for Device Driver Library of Crc. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_crc.h" +#include "hc32f460_utility.h" + +#if (DDL_CRC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CrcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Definition of CRC16 data register. */ +#define M4_CRC16_DAT (*((__IO uint16_t *)&M4_CRC->DAT0)) + +/* Definition of CRC16 checksum register. */ +#define M4_CRC16_RSLT (*((__IO uint16_t *)&M4_CRC->RESLT)) + +/* Definition of CRC16 initial value register. */ +#define M4_CRC16_INIT (M4_CRC16_RSLT) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static uint32_t CRC_ProcChecksum(uint32_t u32Checksum); +static uint32_t CRC_ReverseBits(uint32_t u32Data); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize the CRC. + ** + ** \param [in] u32Config Bit[1]: CRC_SEL_16B or CRC_SEL_32B. + ** Bit[2]: CRC_REFIN_DISABLE or CRC_REFIN_ENABLE. + ** Bit[3]: CRC_REFOUT_DISABLE or CRC_REFOUT_ENABLE. + ** Bit[4]: CRC_XOROUT_DISABLE or CRC_XOROUT_ENABLE. + ** See the definitions for details. + ** + ** \retval None + ** + ******************************************************************************/ +void CRC_Init(uint32_t u32Config) +{ + u32Config &= CRC_CONFIG_MASK; + + M4_CRC->CR = u32Config; +} + +/** + ******************************************************************************* + ** \brief CRC16 calculation. + ** + ** \param [in] u16InitVal Initial value of CRC16. + ** + ** \param [in] pu16Data Pointer to the buffer containing the data to be computed. + ** + ** \param [in] u32Length Length of the buffer to be computed. + ** + ** \retval 16-bit CRC checksum. + ** + ******************************************************************************/ +uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length) +{ + uint16_t u16Ret = 0u; + uint32_t u32Count; + + if (NULL != pu16Data) + { + M4_CRC16_INIT = u16InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC16_DAT = pu16Data[u32Count]; + } + + u16Ret = M4_CRC16_RSLT; + } + + return u16Ret; +} + +/** + ******************************************************************************* + ** \brief CRC32 calculation. + ** + ** \param [in] u32InitVal Initial value of CRC32. + ** + ** \param [in] pu32Data Pointer to the buffer containing the data to be computed. + ** + ** \param [in] u32Length Length of the buffer to be computed. + ** + ** \retval 32-bit CRC checksum. + ** + ******************************************************************************/ +uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length) +{ + uint32_t u32Ret = 0u; + uint32_t u32Count; + + M4_CRC->RESLT = u32InitVal; + + if (NULL != pu32Data) + { + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC->DAT0 = pu32Data[u32Count]; + } + + u32Ret = M4_CRC->RESLT; + } + + return u32Ret; +} + +/** + ******************************************************************************* + ** \brief CRC16 check. + ** + ** \param [in] u16InitVal Initial value of CRC16. + ** + ** \param [in] u16Checksum CRC16 checksum of the source data. + ** + ** \param [in] pu16Data Pointer to the buffer containing the data to be checked. + ** + ** \param [in] u32Length Length of the buffer to be checked. + ** + ** \retval true CRC16 checks successfully. + ** \retval false CRC16 checks unsuccessfully. + ** + ******************************************************************************/ +bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16Checksum, const uint16_t *pu16Data, uint32_t u32Length) +{ + bool bRet = false; + uint32_t u32Count; + uint16_t u16CrcChecksum; + + if (NULL != pu16Data) + { + u16CrcChecksum = (uint16_t)CRC_ProcChecksum((uint32_t)u16Checksum); + M4_CRC16_INIT = u16InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC16_DAT = pu16Data[u32Count]; + } + + M4_CRC16_DAT = u16CrcChecksum; + + if (bM4_CRC_FLG_FLAG) + { + bRet = true; + } + } + + return bRet; +} + +/** + ******************************************************************************* + ** \brief CRC32 check. + ** + ** \param [in] u32InitVal Initial value of CRC32. + ** + ** \param [in] u32Checksum CRC32 checksum of the source data. + ** + ** \param [in] pu32Data Pointer to the buffer containing the data to be checked. + ** + ** \param [in] u32Length Length of the buffer to be checked. + ** + ** \retval true CRC32 checks successfully. + ** \retval false CRC32 checks unsuccessfully. + ** + ******************************************************************************/ +bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32Checksum, const uint32_t *pu32Data, uint32_t u32Length) +{ + bool bRet = false; + uint32_t u32Count; + uint32_t u32CrcChecksum; + + if (NULL != pu32Data) + { + u32CrcChecksum = CRC_ProcChecksum(u32Checksum); + M4_CRC->RESLT = u32InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC->DAT0 = pu32Data[u32Count]; + } + + M4_CRC->DAT0 = u32CrcChecksum; + + if (bM4_CRC_FLG_FLAG) + { + bRet = true; + } + } + + return bRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Processes the checksum of CRC. + ** + ** \param [in] u32Checksum The checksum of CRC16 or CRC32. + ** + ** \retval 32-bit new checksum will be used by CRC checking. + ** + ******************************************************************************/ +static uint32_t CRC_ProcChecksum(uint32_t u32Checksum) +{ + uint8_t i; + uint8_t u8Size = 16u; + uint8_t u8Offset; + uint32_t u32Config; + uint32_t u32FinalChecksum; + uint32_t u32Temp; + + u32Config = M4_CRC->CR; + u32FinalChecksum = u32Checksum; + + if ((u32Config & CRC_SEL_32B) == CRC_SEL_32B) + { + u8Size = 32u; + } + + if ((u32Config & CRC_REFOUT_ENABLE) == CRC_REFOUT_DISABLE) + { + /* Bits reversing. */ + u32FinalChecksum = CRC_ReverseBits(u32Checksum); + if (u8Size == 16u) + { + u32FinalChecksum >>= 16u; + u32FinalChecksum &= 0xFFFFu; + } + } + + if ((u32Config & CRC_XOROUT_ENABLE) == CRC_XOROUT_DISABLE) + { + /* Bits NOT. */ + u32FinalChecksum = ~u32FinalChecksum; + } + + if ((u32Config & CRC_REFIN_ENABLE) == CRC_REFIN_DISABLE) + { + u8Size /= 8u; + /* Bits reversing in bytes. */ + for (i = 0u; i < u8Size; i++) + { + u8Offset = i * 8u; + u32Temp = (u32FinalChecksum >> u8Offset) & 0xFFul; + u32Temp = CRC_ReverseBits(u32Temp); + u32Temp = u32Temp >> (24u - u8Offset); + u32FinalChecksum &= ~((uint32_t)0xFF << u8Offset); + u32FinalChecksum |= u32Temp; + } + } + + return u32FinalChecksum; +} + +/** + ******************************************************************************* + ** \brief Reverse bits. + ** + ** \param [in] u32Data The data to be reversed bits. + ** + ** \retval 32-bit new data. + ** + ******************************************************************************/ +static uint32_t CRC_ReverseBits(uint32_t u32Data) +{ + u32Data = (((u32Data & 0xAAAAAAAAul) >> 1u) | ((u32Data & 0x55555555ul) << 1u)); + u32Data = (((u32Data & 0xCCCCCCCCul) >> 2u) | ((u32Data & 0x33333333ul) << 2u)); + u32Data = (((u32Data & 0xF0F0F0F0ul) >> 4u) | ((u32Data & 0x0F0F0F0Ful) << 4u)); + u32Data = (((u32Data & 0xFF00FF00ul) >> 8u) | ((u32Data & 0x00FF00FFul) << 8u)); + + return ((u32Data >> 16u) | (u32Data << 16u)); +} + +//@} // CrcGroup + +#endif /* DDL_CRC_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_dcu.c b/driver/src/hc32f460_dcu.c new file mode 100644 index 0000000..71fdbed --- /dev/null +++ b/driver/src/hc32f460_dcu.c @@ -0,0 +1,975 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dcu.c + ** + ** A detailed description is available at + ** @link DcuGroup DCU description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of DCU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_dcu.h" +#include "hc32f460_utility.h" + +#if (DDL_DCU_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup DcuGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for DCU Instances. */ +#define IS_VALID_DCU(__DCUx__) \ +( (M4_DCU1 == (__DCUx__)) || \ + (M4_DCU2 == (__DCUx__)) || \ + (M4_DCU3 == (__DCUx__)) || \ + (M4_DCU4 == (__DCUx__))) + +/*!< Parameter valid check for DCU DATA register. */ +#define IS_VALID_DCU_DATA_REG(x) \ +( (DcuRegisterData0 == (x)) || \ + (DcuRegisterData1 == (x)) || \ + (DcuRegisterData2 == (x))) + +/*!< Parameter valid check for DCU operation mode. */ +#define IS_VALID_DCU_OPERATION(x) \ +( (DcuOpAdd == (x)) || \ + (DcuOpSub == (x)) || \ + (DcuInvalid == (x)) || \ + (DcuOpCompare == (x)) || \ + (DcuHwTrigOpAdd == (x)) || \ + (DcuHwTrigOpSub == (x))) + +/*!< Parameter valid check for DCU data size. */ +#define IS_VALID_DCU_DATAZ_SIZE(x) \ +( (DcuDataBit8 == (x)) || \ + (DcuDataBit16 == (x)) || \ + (DcuDataBit32 == (x))) + +/*!< Parameter valid check for DCU compare trigger mode type. */ +#define IS_VALID_DCU_CMP_TRIG_MODE(x) \ +( (DcuCmpTrigbyData0 == (x)) || \ + (DcuCmpTrigbyData012 == (x))) + +/*!< Parameter valid check for DCU interrupt. */ +#define IS_VALID_DCU_INT(x) \ +( (DcuIntOp == (x)) || \ + (DcuIntLs2 == (x)) || \ + (DcuIntEq2 == (x)) || \ + (DcuIntGt2 == (x)) || \ + (DcuIntLs1 == (x)) || \ + (DcuIntEq1 == (x)) || \ + (DcuIntGt1 == (x))) + +/*!< Parameter valid check for DCU interrupt mode. */ +#define IS_VALID_DCU_INT_WIN_MODE(x) \ +( (DcuIntInvalid == (x)) || \ + (DcuWinIntInvalid == (x)) || \ + (DcuInsideWinCmpInt == (x)) || \ + (DcuOutsideWinCmpInt == (x))) + +/*!< Parameter valid check for external trigger event. */ +#define IS_VALID_TRG_SRC_EVENT(x) \ +( (((x) >= EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/*! Parameter valid check for DCU common trigger. */ +#define IS_DCU_COM_TRIGGER(x) \ +( ((x) == DcuComTrigger_1) || \ + ((x) == DcuComTrigger_2) || \ + ((x) == DcuComTrigger_1_2)) + +/*!< Get the specified DATA register address of the specified DCU unit */ +#define DCU_DATAx(__DCUx__, __DATAx__) ((uint32_t)(&(__DCUx__)->DATA0) + ((uint32_t)(__DATAx__)) * 4u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes a DCU. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to DCU configure structure + ** \arg This parameter detail refer @ref stc_dcu_init_t + ** + ** \retval Ok DCU is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - DCUx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx && pstcInitCfg pointer */ + if ((IS_VALID_DCU(DCUx)) && (NULL != pstcInitCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enIntCmd)); + DDL_ASSERT(IS_VALID_DCU_OPERATION(pstcInitCfg->enOperation)); + DDL_ASSERT(IS_VALID_DCU_DATAZ_SIZE(pstcInitCfg->enDataSize)); + DDL_ASSERT(IS_VALID_DCU_INT_WIN_MODE(pstcInitCfg->enIntWinMode)); + DDL_ASSERT(IS_VALID_DCU_CMP_TRIG_MODE(pstcInitCfg->enCmpTriggerMode)); + + /* De-initialize dcu register value */ + DCUx->CTL = 0ul; + DCUx->INTSEL = 0ul; + DCUx->FLAGCLR = 0x7Ful; + + /* Set dcu operation mode */ + DCUx->CTL_f.MODE = (uint32_t)pstcInitCfg->enOperation; + + /* Set dcu data sieze */ + DCUx->CTL_f.DATASIZE = (uint32_t)pstcInitCfg->enDataSize; + + /* Set dcu compare trigger mode */ + DCUx->CTL_f.COMP_TRG = (uint32_t)pstcInitCfg->enCmpTriggerMode; + + /* Set dcu interrupt window mode */ + DCUx->INTSEL_f.INT_WIN = (uint32_t)pstcInitCfg->enIntWinMode; + + DCUx->INTSEL = pstcInitCfg->u32IntSel; + DCUx->CTL_f.INTEN = (uint32_t)(pstcInitCfg->enIntCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes a DCU. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval Ok De-Initialized successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* De-initialize dcu register value */ + DCUx->CTL = 0u; + DCUx->INTSEL = 0u; + DCUx->FLAGCLR = 0x7Fu; + *TRGSELx = EVT_MAX; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DCU operation mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enMode DCU operation mode + ** \arg DcuInvalid Invalid + ** \arg DcuOpAdd Operation: Add + ** \arg DcuOpSub Operation: Sub + ** \arg DcuHwTrigOpAdd Operation: Hardware trigger Add + ** \arg DcuHwTrigOpSub Operation: Hardware trigger Sub + ** \arg DcuOpCompare Operation: Compare + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx, + en_dcu_operation_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_OPERATION(enMode)); + + DCUx->CTL_f.MODE = (uint32_t)enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU operation mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuInvalid Invalid + ** \retval DcuOpAdd Operation: Add + ** \retval DcuOpSub Operation: Sub + ** \retval DcuHwTrigOpAdd Operation: Hardware trigger Add + ** \retval DcuHwTrigOpSub Operation: Hardware trigger Sub + ** \retval DcuOpCompare Operation: Compare + ** + ******************************************************************************/ +en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_operation_mode_t)DCUx->CTL_f.MODE; +} + +/** + ******************************************************************************* + ** \brief Set DCU data size. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enSize DCU data size + ** \arg DcuDataBit8 8 bit + ** \arg DcuDataBit16 16 bit + ** \arg DcuDataBit32 32 bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATAZ_SIZE(enSize)); + + DCUx->CTL_f.DATASIZE = (uint32_t)enSize; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU data size. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuDataBit8 8 bit + ** \retval DcuDataBit16 16 bit + ** \retval DcuDataBit32 32 bit + ** + ******************************************************************************/ +en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_data_size_t)(DCUx->CTL_f.DATASIZE); +} + +/** + ******************************************************************************* + ** \brief Set DCU interrup window. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enIntWinMode Interrupt window mode + ** \arg DcuIntInvalid DCU don't occur interrupt + ** \arg DcuWinIntInvalid DCU window interrupt is invalid. + ** \arg DcuInsideWinCmpInt DCU occur interrupt when DATA2 <= DATA0 <= DATA2 + ** \arg DcuOutsideWinCmpInt DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx, + en_dcu_int_win_mode_t enIntWinMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT_WIN_MODE(enIntWinMode)); + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + DCUx->INTSEL_f.INT_WIN = (uint32_t)enIntWinMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU interrup window. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuIntInvalid DCU don't occur interrupt + ** \retval DcuWinIntInvalid DCU window interrupt is invalid. + ** \retval DcuInsideWinCmpInt DCU occur interrupt when DATA2 <= DATA0 <= DATA2 + ** \retval DcuOutsideWinCmpInt DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 + ** + ******************************************************************************/ +en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_int_win_mode_t)(DCUx->INTSEL_f.INT_WIN); +} + +/** + ******************************************************************************* + ** \brief Set DCU compare trigger mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enTriggerMode DCU compare trigger mode + ** \arg DcuCmpTrigbyData0 DCU compare triggered by DATA0 + ** \arg DcuCmpTrigbyData012 DCU compare triggered by DATA0 or DATA1 or DATA2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx, + en_dcu_cmp_trigger_mode_t enTriggerMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_CMP_TRIG_MODE(enTriggerMode)); + + DCUx->CTL_f.COMP_TRG = (uint32_t)enTriggerMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU compare trigger mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuCmpTrigbyData0 DCU compare triggered by DATA0 + ** \retval DcuCmpTrigbyData012 DCU compare triggered by DATA0 or DATA1 or DATA2 + ** + ******************************************************************************/ +en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_cmp_trigger_mode_t)(DCUx->CTL_f.COMP_TRG); +} + +/** + ******************************************************************************* + ** \brief Enable DCU interrupt. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enCmd DCU interrupt state + ** \arg Enable Enable the DCU interrupt function + ** \arg Disable Disable the DCU interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_IrqCmd(M4_DCU_TypeDef *DCUx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + DCUx->CTL_f.INTEN = (uint32_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the specified DCU flag + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enFlag The specified DCU flag + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enStatus is invalid. + ** + ******************************************************************************/ +en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_INT(enFlag)); + + return ((DCUx->FLAG & enFlag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified DCU flag + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enFlag the specified DCU flag + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT(enFlag)); + DCUx->FLAGCLR = (uint32_t)enFlag; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable DCU interrupt. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enIntSel DCU interrupt selection + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** \param [in] enCmd DCU interrupt functional state + ** \arg Enable Enable the specified DCU interrupt function + ** \arg Disable Disable the specified DCU interrupt function + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - DCUx is invalid + ** - enIntSel is invalid + ** + ******************************************************************************/ +en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx, + en_dcu_int_sel_t enIntSel, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT(enIntSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + enRet = Ok; + switch(enIntSel) + { + case DcuIntOp: + DCUx->INTSEL_f.INT_OP = (uint32_t)enCmd; + break; + case DcuIntLs2: + DCUx->INTSEL_f.INT_LS2 = (uint32_t)enCmd; + break; + case DcuIntEq2: + DCUx->INTSEL_f.INT_EQ2 = (uint32_t)enCmd; + break; + case DcuIntGt2: + DCUx->INTSEL_f.INT_GT2 = (uint32_t)enCmd; + break; + case DcuIntLs1: + DCUx->INTSEL_f.INT_LS1 = (uint32_t)enCmd; + break; + case DcuIntEq1: + DCUx->INTSEL_f.INT_EQ1 = (uint32_t)enCmd; + break; + case DcuIntGt1: + DCUx->INTSEL_f.INT_GT1 = (uint32_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint8_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u8Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint8_t u8Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint8_t *)DCU_DATAx(DCUx, enDataReg) = u8Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint16_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u16Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint16_t u16Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint16_t *)DCU_DATAx(DCUx, enDataReg) = u16Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint32_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u32Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint32_t u32Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint32_t *)DCU_DATAx(DCUx, enDataReg) = u32Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DCU trigger source number + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enTriggerSrc The trigger source. + ** \arg This parameter can be any value of @ref en_event_src_t + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx, + en_event_src_t enTriggerSrc) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + if (NULL != TRGSELx) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_TRG_SRC_EVENT(enTriggerSrc)); + + *TRGSELx = (*TRGSELx & (~((uint32_t)EVT_MAX))) | (uint32_t)enTriggerSrc; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable DCU common trigger. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enComTrigger DCU common trigger selection. See @ref en_dcu_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx, + en_dcu_com_trigger_t enComTrigger, + en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + if (NULL != TRGSELx) + { + DDL_ASSERT(IS_DCU_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } + } +} + +/** + ******************************************************************************* + ** \brief Get DCU trigger source register address + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DCUx_TRGSEL address DCUx is valid + ** \retval NULL DCUx is invalid + ** + ******************************************************************************/ +static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx) +{ + __IO uint32_t *TRGSELx = NULL; + + if (M4_DCU1 == DCUx) + { + TRGSELx = &M4_AOS->DCU1_TRGSEL; + } + else if (M4_DCU2 == DCUx) + { + TRGSELx = &M4_AOS->DCU2_TRGSEL; + } + else if (M4_DCU3 == DCUx) + { + TRGSELx = &M4_AOS->DCU3_TRGSEL; + } + else if (M4_DCU4 == DCUx) + { + TRGSELx = &M4_AOS->DCU4_TRGSEL; + } + else + { + TRGSELx = NULL; + } + + return TRGSELx; +} + +//@} // DcuGroup + +#endif /* DDL_DCU_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_dmac.c b/driver/src/hc32f460_dmac.c new file mode 100644 index 0000000..a4eba02 --- /dev/null +++ b/driver/src/hc32f460_dmac.c @@ -0,0 +1,1827 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dmac.c + ** + ** A detailed description is available at + ** @link DmacGroup DMAC description @endlink + ** + ** - 2018-11-18 CDT First version for Device Driver Library of DMAC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_dmac.h" +#include "hc32f460_utility.h" + +#if (DDL_DMAC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup DmacGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define DMA_CNT (10u) +#define DMA_IDLE (0u) +#define DMA_BUSY (1u) + +#define DMACH0 (0x01u) +#define DMACH1 (0x02u) +#define DMACH2 (0x04u) +#define DMACH3 (0x08u) + +#define DMATIMEOUT1 (0x5000u) +#define DMATIMEOUT2 (0x1000u) + +#define DMA_CHCTL_DEFAULT (0x00001000ul) +#define DMA_DTCTL_DEFAULT (0x00000001ul) +#define DMA_DAR_DEFAULT (0x00000000ul) +#define DMA_SAR_DEFAULT (0x00000000ul) +#define DMA_RPT_DEFAULT (0x00000000ul) +#define DMA_LLP_DEFAULT (0x00000000ul) +#define DMA_SNSEQCTL_DEFAULT (0x00000000ul) +#define DMA_DNSEQCTL_DEFAULT (0x00000000ul) +#define DMA_RCFGCTL_DEFAULT (0x00000000ul) + +/***************** Bits definition for DMA_INTSTAT0 register ****************/ +#define DMA_INTSTAT0_TRNERR_Pos (0U) /*!< DMA_INTSTAT0: TRNERR Position */ +#define DMA_INTSTAT0_REQERR_Pos (16U) /*!< DMA_INTSTAT0: REQERR Position */ + +/***************** Bits definition for DMA_INTSTAT1 register ****************/ +#define DMA_INTSTAT1_TC_Pos (0U) /*!< DMA_INTSTAT1: TC Position */ +#define DMA_INTSTAT1_BTC_Pos (16U) /*!< DMA_INTSTAT1: BTC Position */ + +/***************** Bits definition for DMA_INTMASK0 register ****************/ +#define DMA_INTMASK0_MSKTRNERR_Pos (0U) /*!< DMA_INTMASK0: MSKTRNERR Position */ +#define DMA_INTMASK0_MSKREQERR_Pos (16U) /*!< DMA_INTMASK0: MSKREQERR Position */ + +/***************** Bits definition for DMA_INTMASK1 register ****************/ +#define DMA_INTMASK1_MSKTC_Pos (0U) /*!< DMA_INTMASK1: MSKTC Position */ +#define DMA_INTMASK1_MSKBTC_Pos (16U) /*!< DMA_INTMASK1: MSKBTC Position */ + +/***************** Bits definition for DMA_INTCLR0 register *****************/ +#define DMA_INTCLR0_CLRTRNERR_Pos (0U) /*!< DMA_INTCLR0: CLRTRNERR Position */ +#define DMA_INTCLR0_CLRREQERR_Pos (16U) /*!< DMA_INTCLR0: CLRREQERR Position */ + +/***************** Bits definition for DMA_INTCLR1 register *****************/ +#define DMA_INTCLR1_CLRTC_Pos (0U) /*!< DMA_INTCLR1: CLRTC Position */ +#define DMA_INTCLR1_CLRBTC_Pos (16U) /*!< DMA_INTCLR1: CLRBTC Position */ + +/******************* Bits definition for DMA_CHEN register ******************/ +#define DMA_CHEN_CHEN_Pos (0U) /*!< DMA_CHEN: CHEN Position */ + +/************** Bits definition for DMA_DTCTLx(x=0~3) register **************/ +#define DMA_DTCTL_BLKSIZE_Pos (0ul) /*!< DMA_DTCTLx: BLKSIZE Position */ +#define DMA_DTCTL_BLKSIZE_Msk (0x3FFul << DMA_DTCTL_BLKSIZE_Pos) /*!< DMA_DTCTLx: BLKSIZE Mask 0x000003FF */ +#define DMA_DTCTL_BLKSIZE (DMA_DTCTL_BLKSIZE_Msk) + +#define DMA_DTCTL_CNT_Pos (16ul) /*!< DMA_DTCTLx: CNT Position */ +#define DMA_DTCTL_CNT_Msk (0xFFFFul << DMA_DTCTL_CNT_Pos) /*!< DMA_DTCTLx: CNT Mask 0xFFFF0000 */ +#define DMA_DTCTL_CNT (DMA_DTCTL_CNT_Msk) + +/*************** Bits definition for DMA_RPTx(x=0~3) register ***************/ +#define DMA_RPT_SRPT_Pos (0ul) /*!< DMA_RPTx: SRPT Position */ +#define DMA_RPT_SRPT_Msk (0x3FFul << DMA_RPT_SRPT_Pos) /*!< DMA_RPTx: SRPT Mask 0x000003FF */ +#define DMA_RPT_SRPT (DMA_RPT_SRPT_Msk) + +#define DMA_RPT_DRPT_Pos (16ul) /*!< DMA_RPTx: DRPT Position */ +#define DMA_RPT_DRPT_Msk (0x3FFul << DMA_RPT_DRPT_Pos) /*!< DMA_RPTx: DRPT Mask 0x03FF0000 */ +#define DMA_RPT_DRPT (DMA_RPT_DRPT_Msk) + +/*************** Bits definition for DMA_RPTBx(x=0~3) register ***************/ +#define DMA_RPTB_SRPTB_Pos (0ul) /*!< DMA_RPTBx: SRPTB Position */ +#define DMA_RPTB_SRPTB_Msk (0x3FFul << DMA_RPTB_SRPTB_Pos) /*!< DMA_RPTBx: SRPTB Mask 0x000003FF */ +#define DMA_RPTB_SRPTB (DMA_RPTB_SRPTB_Msk) + +#define DMA_RPTB_DRPTB_Pos (16ul) /*!< DMA_RPTBx: DRPTB Position */ +#define DMA_RPTB_DRPTB_Msk (0x3FFul << DMA_RPTB_DRPTB_Pos) /*!< DMA_RPTBx: DRPTB Mask 0x03FF0000 */ +#define DMA_RPTB_DRPTB (DMA_RPTB_DRPTB_Msk) + +/************* Bits definition for DMA_SNSEQCTLx(x=0~3) register ************/ +#define DMA_SNSEQCTL_SOFFSET_Pos (0ul) /*!< DMA_SNSEQCTLx: SOFFSET Position */ +#define DMA_SNSEQCTL_SOFFSET_Msk (0xFFFFFul << DMA_SNSEQCTL_SOFFSET_Pos) /*!< DMA_SNSEQCTLx: SOFFSET Mask 0x000FFFFF */ +#define DMA_SNSEQCTL_SOFFSET (DMA_SNSEQCTL_SOFFSET_Msk) + +#define DMA_SNSEQCTL_SNSCNT_Pos (20ul) /*!< DMA_SNSEQCTLx: SNSCNT Position */ +#define DMA_SNSEQCTL_SNSCNT_Msk (0xFFFul << DMA_SNSEQCTL_SNSCNT_Pos) /*!< DMA_SNSEQCTLx: SNSCNT Mask 0xFFF00000 */ +#define DMA_SNSEQCTL_SNSCNT (DMA_SNSEQCTL_SNSCNT_Msk) + +/************* Bits definition for DMA_SNSEQCTLBx(x=0~3) register ************/ +#define DMA_SNSEQCTLB_SNSDIST_Pos (0ul) /*!< DMA_SNSEQCTLBx: SNSDIST Position */ +#define DMA_SNSEQCTLB_SNSDIST_Msk (0xFFFFFul << DMA_SNSEQCTLB_SNSDIST_Pos) /*!< DMA_SNSEQCTLBx: SNSDIST Mask 0x000FFFFF */ +#define DMA_SNSEQCTLB_SNSDIST (DMA_SNSEQCTLB_SNSDIST_Msk) + +#define DMA_SNSEQCTLB_SNSCNTB_Pos (20ul) /*!< DMA_SNSEQCTLBx: SNSCNTB Position */ +#define DMA_SNSEQCTLB_SNSCNTB_Msk (0xFFFul << DMA_SNSEQCTLB_SNSCNTB_Pos) /*!< DMA_SNSEQCTLBx: SNSCNTB Mask 0xFFF00000 */ +#define DMA_SNSEQCTLB_SNSCNTB (DMA_SNSEQCTLB_SNSCNTB_Msk) + +/************* Bits definition for DMA_DNSEQCTLx(x=0~3) register ************/ +#define DMA_DNSEQCTL_DOFFSET_Pos (0ul) /*!< DMA_DNSEQCTLx: DOFFSET Position */ +#define DMA_DNSEQCTL_DOFFSET_Msk (0xFFFFFul << DMA_DNSEQCTL_DOFFSET_Pos) /*!< DMA_DNSEQCTLx: DOFFSET Mask 0x000FFFFF */ +#define DMA_DNSEQCTL_DOFFSET (DMA_DNSEQCTL_DOFFSET_Msk) + +#define DMA_DNSEQCTL_DNSCNT_Pos (20ul) /*!< DMA_DNSEQCTLx: DNSCNT Position */ +#define DMA_DNSEQCTL_DNSCNT_Msk (0xFFFul << DMA_DNSEQCTL_DNSCNT_Pos) /*!< DMA_DNSEQCTLx: DNSCNT Mask 0xFFF00000 */ +#define DMA_DNSEQCTL_DNSCNT (DMA_DNSEQCTL_DNSCNT_Msk) + +/************* Bits definition for DMA_DNSEQCTLx(x=0~3) register ************/ +#define DMA_DNSEQCTLB_DNSDIST_Pos (0ul) /*!< DMA_DNSEQCTLBx: DNSDIST Position */ +#define DMA_DNSEQCTLB_DNSDIST_Msk (0xFFFFFul << DMA_DNSEQCTLB_DNSDIST_Pos) /*!< DMA_DNSEQCTLBx: DNSDIST Mask 0x000FFFFF */ +#define DMA_DNSEQCTLB_DNSDIST (DMA_DNSEQCTLB_DNSDIST_Msk) + +#define DMA_DNSEQCTLB_DNSCNTB_Pos (20ul) /*!< DMA_DNSEQCTLBx: DNSCNTB Position */ +#define DMA_DNSEQCTLB_DNSCNTB_Msk (0xFFFul << DMA_DNSEQCTLB_DNSCNTB_Pos) /*!< DMA_DNSEQCTLBx: DNSCNTB Mask 0xFFF00000 */ +#define DMA_DNSEQCTLB_DNSCNTB (DMA_DNSEQCTLB_DNSCNTB_Msk) + +/**************** Bits definition for DMA_LLPx(x=0~7) register **************/ +#define DMA_LLP_LLP_Pos (2ul) /*!< DMA_LLPx: LLP Position */ +#define DMA_LLP_LLP_Msk (0x3FFFFFFFul << DMA_LLP_LLP_Pos) /*!< DMA_LLPx: LLP Mask 0xFFFFFFC */ +#define DMA_LLP_LLP (DMA_LLP_LLP_Msk) + +/*************** Bits definition for DMA_CHxCTL(x=0~3) register *************/ +#define DMA_CHCTL_SINC_Pos (0ul) /*!< DMA_CHxCTL: SINC Position */ +#define DMA_CHCTL_SINC_Msk (0x3ul << DMA_CHCTL_SINC_Pos) /*!< DMA_CHxCTL: SINC Mask 0x00000003 */ +#define DMA_CHCTL_SINC (DMA_CHCTL_SINC_Msk) + +#define DMA_CHCTL_DINC_Pos (2ul) /*!< DMA_CHxCTL: DINC Position */ +#define DMA_CHCTL_DINC_Msk (0x3ul << DMA_CHCTL_DINC_Pos) /*!< DMA_CHxCTL: DINC Mask 0x0000000C */ +#define DMA_CHCTL_DINC (DMA_CHCTL_DINC_Msk) + +#define DMA_CHCTL_SRPTEN_Pos (4ul) /*!< DMA_CHxCTL: SRPTEN Position */ +#define DMA_CHCTL_SRPTEN_Msk (0x1ul << DMA_CHCTL_SRPTEN_Pos) /*!< DMA_CHxCTL: SRPTEN Mask 0x00000010 */ +#define DMA_CHCTL_SRPTEN (DMA_CHCTL_SRPTEN_Msk) + +#define DMA_CHCTL_DRPTEN_Pos (5ul) /*!< DMA_CHxCTL: DRPTEN Position */ +#define DMA_CHCTL_DRPTEN_Msk (0x1ul << DMA_CHCTL_DRPTEN_Pos) /*!< DMA_CHxCTL: DRPTEN Mask 0x00000020 */ +#define DMA_CHCTL_DRPTEN (DMA_CHCTL_DRPTEN_Msk) + +#define DMA_CHCTL_SNSEQEN_Pos (6ul) /*!< DMA_CHxCTL: SNSEQEN Position */ +#define DMA_CHCTL_SNSEQEN_Msk (0x1ul << DMA_CHCTL_SNSEQEN_Pos) /*!< DMA_CHxCTL: SNSEQEN Mask 0x00000040 */ +#define DMA_CHCTL_SNSEQEN (DMA_CHCTL_SNSEQEN_Msk) + +#define DMA_CHCTL_DNSEQEN_Pos (7ul) /*!< DMA_CHxCTL: DNSEQEN Position */ +#define DMA_CHCTL_DNSEQEN_Msk (0x1ul << DMA_CHCTL_DNSEQEN_Pos) /*!< DMA_CHxCTL: DNSEQEN Mask 0x00000080 */ +#define DMA_CHCTL_DNSEQEN (DMA_CHCTL_DNSEQEN_Msk) + +#define DMA_CHCTL_HSIZE_Pos (8ul) /*!< DMA_CHxCTL: HSIZE Position */ +#define DMA_CHCTL_HSIZE_Msk (0x3ul << DMA_CHCTL_HSIZE_Pos) /*!< DMA_CHxCTL: HSIZE Mask 0x00000300 */ +#define DMA_CHCTL_HSIZE (DMA_CHCTL_HSIZE_Msk) + +#define DMA_CHCTL_LLPEN_Pos (10ul) /*!< DMA_CHxCTL: LLPEN Position */ +#define DMA_CHCTL_LLPEN_Msk (0x1ul << DMA_CHCTL_LLPEN_Pos) /*!< DMA_CHxCTL: LLPEN Mask 0x00000400 */ +#define DMA_CHCTL_LLPEN (DMA_CHCTL_LLPEN_Msk) + +#define DMA_CHCTL_LLPRUN_Pos (11ul) /*!< DMA_CHxCTL: LLPRUN Position */ +#define DMA_CHCTL_LLPRUN_Msk (0x1ul << DMA_CHCTL_LLPRUN_Pos) /*!< DMA_CHxCTL: LLPRUN Mask 0x00000800 */ +#define DMA_CHCTL_LLPRUN (DMA_CHCTL_LLPRUN_Msk) + +#define DMA_CHCTL_IE_Pos (12ul) /*!< DMA_CHxCTL: IE Position */ +#define DMA_CHCTL_IE_Msk (0x1ul << DMA_CHCTL_IE_Pos) /*!< DMA_CHxCTL: IE Mask 0x00001000 */ +#define DMA_CHCTL_IE (DMA_CHCTL_IE_Msk) + +/*********************** DMA REGISTERx(x=0~3) register **********************/ +#define _DMA_CH_REG_OFFSET(ch) ((ch) * 0x40ul) +#define _DMA_CH_REG(reg_base, ch) (*(volatile uint32_t *)((uint32_t)(reg_base) + _DMA_CH_REG_OFFSET(ch))) + +#define WRITE_DMA_CH_REG(reg_base, ch, val) (_DMA_CH_REG((reg_base), (ch)) = (val)) +#define READ_DMA_CH_REG(reg_base, ch) (_DMA_CH_REG((reg_base), (ch))) + +#define SET_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) |= (1ul << (pos))) +#define CLR_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) &= (~(1ul << (pos)))) + +#define WRITE_DMA_CH_TRGSEL(reg_base, ch, val) ((*(volatile uint32_t *)((uint32_t)(reg_base) + (ch) * 4ul)) = (val)) + +#define MODIFY_DMA_CH_REG(reg_base, ch, msk, val) {do { \ + WRITE_DMA_CH_REG((reg_base), (ch), ((READ_DMA_CH_REG((reg_base), (ch)) & (~(msk))) | ((val) << (msk##_Pos)))); \ +} while(0);} + +/*! Parameter valid check for Dmac register pointer. */ +#define IS_VALID_DMA_REG(x) \ +( (M4_DMA1 == (x)) || \ + (M4_DMA2 == (x))) + +/*! Parameter valid check for Dmac Channel. */ +#define IS_VALID_CH(x) \ +( (DmaCh0 == (x)) || \ + (DmaCh1 == (x)) || \ + (DmaCh2 == (x)) || \ + (DmaCh3 == (x))) + +/*! Parameter valid check for Dmac irq selection. */ +#define IS_VALID_IRQ_SEL(x) \ +( (TrnErrIrq == (x)) || \ + (TrnReqErrIrq == (x)) || \ + (TrnCpltIrq == (x)) || \ + (BlkTrnCpltIrq == (x))) + +/*! Parameter valid check for Dmac re_config count mode. */ +#define IS_VALID_CNT_MODE(x) \ +( (CntFix == (x)) || \ + (CntSrcAddr == (x)) || \ + (CntDesAddr == (x))) + +/*! Parameter valid check for Dmac re_config source address mode. */ +#define IS_VALID_SADDR_MODE(x) \ +( (SaddrFix == (x)) || \ + (SaddrNseq == (x)) || \ + (SaddrRep == (x))) + +/*! Parameter valid check for Dmac re_config destination address mode. */ +#define IS_VALID_DADDR_MODE(x) \ +( (DaddrFix == (x)) || \ + (DaddrNseq == (x)) || \ + (DaddrRep == (x))) + +/*! Parameter valid check for Dmac status. */ +#define IS_VALID_DMA_STA(x) \ +( (DmaSta == (x)) || \ + (ReCfgSta == (x)) || \ + (DmaCh0Sta == (x)) || \ + (DmaCh1Sta == (x)) || \ + (DmaCh2Sta == (x)) || \ + (DmaCh3Sta == (x))) + +/*! Parameter valid check for Dmac transfer data width. */ +#define IS_VALID_TRN_WIDTH(x) \ +( (Dma8Bit == (x)) || \ + (Dma16Bit == (x)) || \ + (Dma32Bit == (x))) + +/*! Parameter valid check for Dmac address mode. */ +#define IS_VALID_ADDR_MODE(x) \ +( (AddressFix == (x)) || \ + (AddressIncrease == (x)) || \ + (AddressDecrease == (x))) + +/*! Parameter valid check for Dmac link-list-pointer mode. */ +#define IS_VALID_LLP_MODE(x) \ +( (LlpWaitNextReq == (x)) || \ + (LlpRunNow == (x))) + +/*! Parameter validity check for DMA common trigger. */ +#define IS_DMA_COM_TRIGGER(x) \ +( ((x) == DmaComTrigger_1) || \ + ((x) == DmaComTrigger_2) || \ + ((x) == DmaComTrigger_1_2)) + +/*! Parameter valid check for Dmac transfer block size. */ +#define IS_VALID_BLKSIZE(x) \ +( !((x) & (uint16_t)(~(DMA_DTCTL_BLKSIZE_Msk >> DMA_DTCTL_BLKSIZE_Pos)))) + +/*! Parameter valid check for Dmac transfer count. */ +#define IS_VALID_TRNCNT(x) \ +( !((x) & ~(DMA_DTCTL_CNT_Msk >> DMA_DTCTL_CNT_Pos))) + +/*! Parameter valid check for Dmac source repeat size. */ +#define IS_VALID_SRPT_SIZE(x) \ +( !((x) & ~(DMA_RPT_SRPT_Msk >> DMA_RPT_SRPT_Pos))) + +/*! Parameter valid check for Dmac destination repeat size. */ +#define IS_VALID_DRPT_SIZE(x) \ +( !((x) & ~(DMA_RPT_DRPT_Msk >> DMA_RPT_DRPT_Pos))) + +/*! Parameter valid check for Dmac source repeatB size. */ +#define IS_VALID_SRPTB_SIZE(x) \ +( !((x) & ~(DMA_RPTB_SRPTB_Msk >> DMA_RPTB_SRPTB_Pos))) + +/*! Parameter valid check for Dmac destinationB repeat size. */ +#define IS_VALID_DRPTB_SIZE(x) \ +( !((x) & ~(DMA_RPTB_DRPTB_Msk >> DMA_RPTB_DRPTB_Pos))) + +/*! Parameter valid check for Dmac source no-sequence count. */ +#define IS_VALID_SNSCNT(x) \ +( !((x) & ~(DMA_SNSEQCTL_SNSCNT_Msk >> DMA_SNSEQCTL_SNSCNT_Pos))) + +/*! Parameter valid check for Dmac source no-sequence offset. */ +#define IS_VALID_SNSOFFSET(x) \ +( !((x) & ~(DMA_SNSEQCTL_SOFFSET_Msk >> DMA_SNSEQCTL_SOFFSET_Pos))) + +/*! Parameter valid check for Dmac source no-sequence countB. */ +#define IS_VALID_SNSCNTB(x) \ +( !((x) & ~(DMA_SNSEQCTLB_SNSCNTB_Msk >> DMA_SNSEQCTLB_SNSCNTB_Pos))) + +/*! Parameter valid check for Dmac source no-sequence distance. */ +#define IS_VALID_SNSDIST(x) \ +( !((x) & ~(DMA_SNSEQCTLB_SNSDIST_Msk >> DMA_SNSEQCTLB_SNSDIST_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence count. */ +#define IS_VALID_DNSCNT(x) \ +( !((x) & ~(DMA_DNSEQCTL_DNSCNT_Msk >> DMA_DNSEQCTL_DNSCNT_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence offset. */ +#define IS_VALID_DNSOFFSET(x) \ +( !((x) & ~(DMA_DNSEQCTL_DOFFSET_Msk >> DMA_DNSEQCTL_DOFFSET_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence countB. */ +#define IS_VALID_DNSCNTB(x) \ +( !((x) & ~(DMA_DNSEQCTLB_DNSCNTB_Msk >> DMA_DNSEQCTLB_DNSCNTB_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence distance. */ +#define IS_VALID_DNSDIST(x) \ +( !((x) & ~(DMA_DNSEQCTLB_DNSDIST_Msk >> DMA_DNSEQCTLB_DNSDIST_Pos))) + +/*! Parameter valid check for Dmac link-list-pointer. */ +#define IS_VALID_LLP(x) (!((x) & ~DMA_LLP_LLP_Msk)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static volatile uint8_t DmaChEnState = DMA_IDLE; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Enable or disable the dma. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->EN_f.EN = enNewState; +} + +/** + ******************************************************************************* + ** \brief Enable the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Interrupt enabled normally. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, + uint8_t u8Ch, + en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTMASK0 &= ~(1ul << (u8Ch + DMA_INTMASK0_MSKTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTMASK0 &= ~(1ul << (u8Ch + DMA_INTMASK0_MSKREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTMASK1 &= ~(1ul << (u8Ch + DMA_INTMASK1_MSKTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTMASK1 &= ~(1ul << (u8Ch + DMA_INTMASK1_MSKBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Interrupt disabled normally. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, + uint8_t u8Ch, + en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTMASK0 |= (1ul << (u8Ch + DMA_INTMASK0_MSKTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTMASK0 |= (1ul << (u8Ch + DMA_INTMASK0_MSKREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTMASK1 |= (1ul << (u8Ch + DMA_INTMASK1_MSKTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTMASK1 |= (1ul << (u8Ch + DMA_INTMASK1_MSKBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the specified dma interrupt flag status. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval the specified dma flag status + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel) +{ + uint32_t u32IntStat = 0ul; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + switch(enIrqSel) + { + case TrnErrIrq: + u32IntStat = (pstcDmaReg->INTSTAT0 & (1ul << (u8Ch \ + + DMA_INTSTAT0_TRNERR_Pos))); + break; + case TrnReqErrIrq: + u32IntStat = (pstcDmaReg->INTSTAT0 & (1ul << (u8Ch \ + + DMA_INTSTAT0_REQERR_Pos))); + break; + case TrnCpltIrq: + u32IntStat = (pstcDmaReg->INTSTAT1 & (1ul << (u8Ch \ + + DMA_INTSTAT1_TC_Pos))); + break; + case BlkTrnCpltIrq: + u32IntStat = (pstcDmaReg->INTSTAT1 & (1ul << (u8Ch \ + + DMA_INTSTAT1_BTC_Pos))); + break; + default: + break; + } + + return (u32IntStat ? Set:Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTCLR0 |= (1ul << (u8Ch + DMA_INTCLR0_CLRTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTCLR0 |= (1ul << (u8Ch + DMA_INTCLR0_CLRREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTCLR1 |= (1ul << (u8Ch + DMA_INTCLR1_CLRTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTCLR1 |= (1ul << (u8Ch + DMA_INTCLR1_CLRBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState) +{ + uint16_t u16Timeout = 0u; + uint32_t u32Temp = 0u; + uint32_t u32Cnt; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(DMA_IDLE == DmaChEnState) + { + DmaChEnState = DMA_BUSY; + + /* Read back channel enable register except current channel */ + u32Temp = (pstcDmaReg->CHEN & (~(1ul << u8Ch))); + if(0ul != u32Temp) + { + if(((pstcDmaReg->CHEN & 0x01ul) == 0x01ul) && (u8Ch != DmaCh0)) + { + u32Cnt = pstcDmaReg->DTCTL0_f.CNT; + if(pstcDmaReg->MONDTCTL0_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL0_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x01ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x02ul) == 0x02ul) && (u8Ch != DmaCh1)) + { + u32Cnt = pstcDmaReg->DTCTL1_f.CNT; + if(pstcDmaReg->MONDTCTL1_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL1_f.CNT < u32Cnt) + { + u16Timeout = 0u; + while(Reset != (pstcDmaReg->CHEN & 0x02ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x04ul) == 0x04ul) && (u8Ch != DmaCh2)) + { + u16Timeout = 0u; + u32Cnt = pstcDmaReg->DTCTL2_f.CNT; + if(pstcDmaReg->MONDTCTL2_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL2_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x04ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x08ul) == 0x08ul) && (u8Ch != DmaCh3)) + { + u16Timeout = 0u; + u32Cnt = pstcDmaReg->DTCTL3_f.CNT; + if(pstcDmaReg->MONDTCTL3_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL3_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x08ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + } + + switch(enNewState) + { + case Enable: + pstcDmaReg->CHEN |= (1ul << (u8Ch + DMA_CHEN_CHEN_Pos)) & 0x0fu; + break; + case Disable: + pstcDmaReg->CHEN &= (~(1ul << (u8Ch + DMA_CHEN_CHEN_Pos))) & 0x0fu; + break; + } + + DmaChEnState = DMA_IDLE; + return Ok; + } + + return Error; +} + +/** + ******************************************************************************* + ** \brief DMA repeat & non_sequence Re_Config control configuration. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDmaReCfg The configuration struct of DMA. + ** \arg u16SrcRptBSize The source repeat size. + ** \arg u16SrcRptBSize; The source repeat size. + ** \arg u16DesRptBSize; The destination repeat size. + ** \arg enSaddrMd; DMA re_config source address mode. + ** \arg enDaddrMd; DMA re_config destination address mode. + ** \arg enCntMd; DMA re_config count mode. + ** \arg stcSrcNseqBCfg; The source no_sequence re_config. + ** \arg stcDesNseqBCfg; The destination no_sequence re_config. + ** + ** \retval None + ** + ** \note This function should be used while DMA disable. + ** + ******************************************************************************/ +void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_recfg_ctl_t* pstcDmaReCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_CNT_MODE(pstcDmaReCfg->enCntMd)); + DDL_ASSERT(IS_VALID_DADDR_MODE(pstcDmaReCfg->enDaddrMd)); + DDL_ASSERT(IS_VALID_SADDR_MODE(pstcDmaReCfg->enSaddrMd)); + + pstcDmaReg->RCFGCTL_f.SARMD = pstcDmaReCfg->enSaddrMd; + pstcDmaReg->RCFGCTL_f.DARMD = pstcDmaReCfg->enDaddrMd; + pstcDmaReg->RCFGCTL_f.CNTMD = pstcDmaReCfg->enCntMd; + pstcDmaReg->RCFGCTL_f.RCFGCHS = u8Ch; + + if(SaddrRep == pstcDmaReCfg->enSaddrMd) + { + /* Set DMA source repeat size B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPT_SRPT, (uint32_t)pstcDmaReCfg->u16SrcRptBSize); + } + else if(SaddrNseq == pstcDmaReCfg->enSaddrMd) + { + /* Set DMA source no_sequence B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTL_SOFFSET, pstcDmaReCfg->stcSrcNseqBCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcDmaReCfg->stcSrcNseqBCfg.u16Cnt); + } + else + { + /* */ + } + + if(DaddrRep == pstcDmaReCfg->enDaddrMd) + { + /* Set DMA destination repeat size B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPT_DRPT, (uint32_t)pstcDmaReCfg->u16DesRptBSize); + } + else if(DaddrNseq == pstcDmaReCfg->enDaddrMd) + { + /* Set DMA destination no_sequence B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDmaReCfg->stcDesNseqBCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDmaReCfg->stcDesNseqBCfg.u16Cnt); + } + else + { + /* */ + } +} + +/** + ******************************************************************************* + ** \brief Disable or enable DMA Re_Config. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->RCFGCTL_f.RCFGEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief Configure DMA Re_Config LLP. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ReCfgLlp(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->RCFGCTL_f.RCFGCHS = u8Ch; + pstcDmaReg->RCFGCTL_f.RCFGLLP = enNewState; +} + +/** + ******************************************************************************* + ** \brief Get the specified dma flag status. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enDmaChFlag The specified dma flag. + ** \arg DmaSta The DMA status. + ** \arg ReCfgSta The DMA re_config stauts. + ** \arg DmaCh0Sta The DMA channel 0 status. + ** \arg DmaCh1Sta The DMA channel 1 status. + ** \arg DmaCh2Sta The DMA channel 2 status. + ** \arg DmaCh3Sta The DMA channel 3 status. + ** + ** \retval the specified dma flag status + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag) +{ + uint32_t u32IntStat = 0ul; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_DMA_STA(enDmaChFlag)); + + switch(enDmaChFlag) + { + case DmaSta: + u32IntStat = pstcDmaReg->CHSTAT_f.DMAACT; + break; + case ReCfgSta: + u32IntStat = pstcDmaReg->CHSTAT_f.RCFGACT; + break; + case DmaCh0Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH0); + break; + case DmaCh1Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH1); + break; + case DmaCh2Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH2); + break; + case DmaCh3Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH3); + break; + default: + break; + } + return (u32IntStat ? Set:Reset); +} + +/** + ******************************************************************************* + ** \brief Set the source address of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 DMAC unit 2 registers + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Address The source address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, u32Address); + + /* Ensure the address has been writed */ + while(u32Address != READ_DMA_CH_REG(&pstcDmaReg->MONSAR0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, u32Address); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination address of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 DMAC unit 2 registers + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Address The destination address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, u32Address); + + /* Ensure the address has been writed */ + while(u32Address != READ_DMA_CH_REG(&pstcDmaReg->MONDAR0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, u32Address); + } + } + + return enRet; + +} + + +/** + ******************************************************************************* + ** \brief Set the block size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16BlkSize The block size. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_BLKSIZE(u16BlkSize)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)u16BlkSize); + + /* Ensure the block size has been writed */ + while(u16BlkSize != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->MONDTCTL0, u8Ch) & DMA_DTCTL_BLKSIZE)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)u16BlkSize); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the transfer count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16TrnCnt The transfer count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_TRNCNT(u16TrnCnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)u16TrnCnt); + + /* Ensure the transfer count has been writed */ + while(u16TrnCnt != ((READ_DMA_CH_REG(&pstcDmaReg->MONDTCTL0, u8Ch) & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)u16TrnCnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the source repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The source repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SRPT_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)u16Size); + + /* Ensure the source repeat size has been writed */ + while(u16Size != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->MONRPT0, u8Ch) & DMA_RPT_SRPT)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The destination repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DRPT_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)u16Size); + + /* Ensure the destination repeat size has been writed */ + while(u16Size != ((READ_DMA_CH_REG(&pstcDmaReg->MONRPT0, u8Ch) & DMA_RPT_DRPT) >> DMA_RPT_DRPT_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)u16Size); + } + } + + return enRet; +} + + +/** + ******************************************************************************* + ** \brief Set the source repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The source repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SRPTB_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_SRPTB, (uint32_t)u16Size); + + /* Ensure the source repeat size has been writed */ + while(u16Size != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch) & DMA_RPTB_SRPTB)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_SRPTB, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The destination repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesRptBSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DRPTB_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_DRPTB, (uint32_t)u16Size); + + /* Ensure the destination repeat size has been writed */ + while(u16Size != ((READ_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch) & DMA_RPTB_DRPTB) >> DMA_RPTB_DRPTB_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_DRPTB, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the source no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcSrcNseqCfg + ** \arg u32offset The source no-sequence offset. + ** \arg u16cnt The source no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseq_cfg_t* pstcSrcNseqCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SNSOFFSET(pstcSrcNseqCfg->u32Offset)); + DDL_ASSERT(IS_VALID_SNSCNT(pstcSrcNseqCfg->u16Cnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SOFFSET, pstcSrcNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcSrcNseqCfg->u16Cnt); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcSrcNseqCfg->u32Offset | ((uint32_t)pstcSrcNseqCfg->u16Cnt << DMA_SNSEQCTL_SNSCNT_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->MONSNSEQCTL0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SOFFSET, pstcSrcNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcSrcNseqCfg->u16Cnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the source no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcSrcNseqBCfg + ** \arg u32NseqDist The source no-sequence distance. + ** \arg u16cntB The source no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SNSDIST(pstcSrcNseqBCfg->u32NseqDist)); + DDL_ASSERT(IS_VALID_SNSCNTB(pstcSrcNseqBCfg->u16CntB)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTLB_SNSDIST, pstcSrcNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTLB_SNSCNTB, (uint32_t)pstcSrcNseqBCfg->u16CntB); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcSrcNseqBCfg->u32NseqDist | ((uint32_t)pstcSrcNseqBCfg->u16CntB << DMA_SNSEQCTLB_SNSCNTB_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, + DMA_SNSEQCTLB_SNSDIST, pstcSrcNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, + DMA_SNSEQCTLB_SNSCNTB, (uint32_t)pstcSrcNseqBCfg->u16CntB); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDesNseqCfg + ** \arg u32offset The destination no-sequence offset. + ** \arg u16cnt The destination no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseq_cfg_t* pstcDesNseqCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DNSOFFSET(pstcDesNseqCfg->u32Offset)); + DDL_ASSERT(IS_VALID_DNSCNT(pstcDesNseqCfg->u16Cnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDesNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDesNseqCfg->u16Cnt); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcDesNseqCfg->u32Offset | ((uint32_t)pstcDesNseqCfg->u16Cnt << DMA_DNSEQCTL_DNSCNT_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->MONDNSEQCTL0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, + DMA_DNSEQCTL_DOFFSET, pstcDesNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, + DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDesNseqCfg->u16Cnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDesNseqBCfg + ** \arg u32offset The destination no-sequence offset. + ** \arg u16cnt The destination no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseqb_cfg_t* pstcDesNseqBCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DNSDIST(pstcDesNseqBCfg->u32NseqDist)); + DDL_ASSERT(IS_VALID_DNSCNTB(pstcDesNseqBCfg->u16CntB)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTLB_DNSDIST, pstcDesNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTLB_DNSCNTB, (uint32_t)pstcDesNseqBCfg->u16CntB); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcDesNseqBCfg->u32NseqDist | ((uint32_t)pstcDesNseqBCfg->u16CntB << DMA_DNSEQCTLB_DNSCNTB_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, + DMA_DNSEQCTLB_DNSDIST, pstcDesNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, + DMA_DNSEQCTLB_DNSCNTB, (uint32_t)pstcDesNseqBCfg->u16CntB); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set linked list pointer of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Pointer The decriptor pointer. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_LLP(u32Pointer)); + + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, u32Pointer); + + /* Ensure the destination repeat size has been writed */ + while(u32Pointer != ((READ_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch) & DMA_LLP_LLP) >> DMA_LLP_LLP_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, u32Pointer); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set The DMA trigger source. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enSrc The DMA trigger source. + ** + ** \retval None. + ** + ** \note Before call this function, shoud ensure enable AOS. + ** + ******************************************************************************/ +void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + + if(M4_DMA1 == pstcDmaReg) + { + WRITE_DMA_CH_TRGSEL(&M4_AOS->DMA1_TRGSEL0,u8Ch,enSrc); + } + else if(M4_DMA2 == pstcDmaReg) + { + WRITE_DMA_CH_TRGSEL(&M4_AOS->DMA2_TRGSEL0,u8Ch,enSrc); + } + else + { + //else + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable DMA common trigger.. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enComTrigger DMA common trigger selection. + ** \arg DmaComTrigger_1 + ** \arg DmaComTrigger_2 + ** \arg DmaComTrigger_1_2 + ** \param [in] enNewState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState) +{ + __IO uint32_t *TRGSELx; + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_DMA_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (M4_DMA1 == pstcDmaReg) + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA1_TRGSEL0) + u8Ch*4UL); + } + else + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA2_TRGSEL0) + u8Ch*4UL); + } + + if (Enable == enNewState) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable DMA re-config common trigger.. + ** + ** \param [in] enComTrigger DMA common trigger selection. + ** \arg DmaComTrigger_1 + ** \arg DmaComTrigger_2 + ** \arg DmaComTrigger_1_2 + ** \param [in] enNewState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_DMA_COM_TRIGGER(enComTrigger)); + + if (Enable == enNewState) + { + M4_AOS->DMA_TRGSELRC |= (u32ComTrig << 30u); + } + else + { + M4_AOS->DMA_TRGSELRC &= ~(u32ComTrig << 30u); + } +} +/** + ******************************************************************************* + ** \brief Set linked list pointer of the specified dma channel. + ** + ** \param [in] enSrc The DMA trigger source. + ** + ** \retval None. + ** + ** \note Before call this function, should ensure enable AOS. + ** + ******************************************************************************/ +void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc) +{ + + M4_AOS->DMA_TRGSELRC_f.TRGSEL = enSrc; + +} +/** + ******************************************************************************* + ** \brief The configuration of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcChCfg The configuration pointer. + ** \arg enSrcInc The source address mode. + ** \arg enDesInc The destination address mode. + ** \arg enSrcRptEn The source repeat function(enable or disable). + ** \arg enDesRptEn The destination repeat function(enable or disable). + ** \arg enSrcNseqEn The source no_sequence function(enable or disable). + ** \arg enDesNseqEn The destination no_sequence function(enable or disable). + ** \arg enTrnWidth The transfer data width. + ** \arg enLlpEn The linked list pointer function(enable or disable). + ** \arg enLlpMd The linked list pointer mode. + ** \arg enIntEn The interrupt function(enable or disable). + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_ch_cfg_t* pstcChCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_ADDR_MODE(pstcChCfg->enSrcInc)); + DDL_ASSERT(IS_VALID_ADDR_MODE(pstcChCfg->enDesInc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enSrcRptEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enDesRptEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enSrcNseqEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enDesNseqEn)); + DDL_ASSERT(IS_VALID_TRN_WIDTH(pstcChCfg->enTrnWidth)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enLlpEn)); + DDL_ASSERT(IS_VALID_LLP_MODE(pstcChCfg->enLlpMd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enIntEn)); + + /* Set the source address mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_SINC, pstcChCfg->enSrcInc); + /* Set the destination address mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DINC, pstcChCfg->enDesInc); + /* Enable or disable source repeat function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_SRPTEN, pstcChCfg->enSrcRptEn); + /* Enable or disable destination repeat function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DRPTEN, pstcChCfg->enDesRptEn); + /* Enable or disable source no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_SNSEQEN, pstcChCfg->enSrcNseqEn); + /* Enable or disable destination no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DNSEQEN, pstcChCfg->enDesNseqEn); + /* Set the transfer data width. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_HSIZE, pstcChCfg->enTrnWidth); + /* Enable or disable linked list pointer no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_LLPEN, pstcChCfg->enLlpEn); + /* Set the linked list pointer mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_LLPRUN, pstcChCfg->enLlpMd); + /* Enable or disable channel interrupt function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_IE, pstcChCfg->enIntEn); +} + +/** + ******************************************************************************* + ** \brief The configuration of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDmaCfg The configuration pointer. + ** \arg enSrcInc The source address mode. + ** \arg enDesInc The destination address mode. + ** \arg enSrcRptEn The source repeat function(enable or disable). + ** \arg enDesRptEn The destination repeat function(enable or disable). + ** \arg enSrcNseqEn The source no_sequence function(enable or disable). + ** \arg enDesNseqEn The destination no_sequence function(enable or disable). + ** \arg enTrnWidth The transfer data width. + ** \arg enLlpEn The linked list pointer function(enable or disable). + ** \arg enLlpMd The linked list pointer mode. + ** \arg enIntEn The interrupt function(enable or disable). + ** + ** \retval None. + ** + ** \note This function should be used after enable DMAx clk(PWC_Fcg0PeriphClockCmd) + ** and before channel enable. + ** + ******************************************************************************/ +void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_config_t* pstcDmaCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_BLKSIZE(pstcDmaCfg->u16BlockSize)); + DDL_ASSERT(IS_VALID_TRNCNT(pstcDmaCfg->u16TransferCnt)); + DDL_ASSERT(IS_VALID_SRPT_SIZE(pstcDmaCfg->u16SrcRptSize)); + DDL_ASSERT(IS_VALID_DRPT_SIZE(pstcDmaCfg->u16DesRptSize)); + + /* Enable DMA. */ + DMA_Cmd(pstcDmaReg, Enable); + /* Disable DMA interrupt */ + CLR_DMA_CH_REG_BIT(&pstcDmaReg->CH0CTL , u8Ch, DMA_CHCTL_IE_Pos); + /* Set DMA source address. */ + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, pstcDmaCfg->u32SrcAddr); + /* Set DMA destination address. */ + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, pstcDmaCfg->u32DesAddr); + /* Set DMA transfer block size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)pstcDmaCfg->u16BlockSize); + /* Set DMA transfer count. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)pstcDmaCfg->u16TransferCnt); + /* Set DMA source repeat size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)pstcDmaCfg->u16SrcRptSize); + /* Set DMA destination repeat size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)pstcDmaCfg->u16DesRptSize); + /* Set DMA source no_sequence. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_SOFFSET, pstcDmaCfg->stcSrcNseqCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcDmaCfg->stcSrcNseqCfg.u16Cnt); + /* Set DMA destination no_sequence. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDmaCfg->stcDesNseqCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDmaCfg->stcDesNseqCfg.u16Cnt); + /* Set DMA linked list pointer. */ + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, pstcDmaCfg->u32DmaLlp); + /* Set DMA channel parameter. */ + DMA_ChannelCfg(pstcDmaReg, u8Ch, &pstcDmaCfg->stcDmaChCfg); +} + +void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + /* reset dma channel */ + WRITE_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, DMA_DAR_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, DMA_SAR_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, DMA_LLP_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->RCFGCTL, u8Ch, DMA_RCFGCTL_DEFAULT); + + /* Set trigger source event max */ + DMA_SetTriggerSrc(pstcDmaReg, u8Ch, EVT_MAX); + /* disable channel */ + DMA_ChannelCmd(pstcDmaReg, u8Ch, Disable); +} + +#endif /* DDL_DMAC_ENABLE */ + +//@} // DmacGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_efm.c b/driver/src/hc32f460_efm.c new file mode 100644 index 0000000..4625f3d --- /dev/null +++ b/driver/src/hc32f460_efm.c @@ -0,0 +1,942 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_efm.c + ** + ** A detailed description is available at + ** @link EfmGroup EFM description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of EFM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_efm.h" +#include "hc32f460_utility.h" + +#if (DDL_EFM_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup EfmGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define EFM_LOCK (0x00000000u) +#define EFM_UNLOCK (0x00000001u) +#define EFM_KEY1 (0x0123ul) +#define EFM_KEY2 (0x3210ul) + +#define EFM_PROTECT_ADDR_MSK (0x000FFFFFu) + +/* Parameter validity check for pointer. */ +#define IS_VALID_POINTER(x) (NULL != (x)) + +/* Parameter validity check for flash latency. */ +#define IS_VALID_FLASH_LATENCY(x) \ +( ((x) == EFM_LATENCY_0) || \ + ((x) == EFM_LATENCY_1) || \ + ((x) == EFM_LATENCY_2) || \ + ((x) == EFM_LATENCY_3) || \ + ((x) == EFM_LATENCY_4) || \ + ((x) == EFM_LATENCY_5) || \ + ((x) == EFM_LATENCY_6) || \ + ((x) == EFM_LATENCY_7) || \ + ((x) == EFM_LATENCY_8) || \ + ((x) == EFM_LATENCY_9) || \ + ((x) == EFM_LATENCY_10) || \ + ((x) == EFM_LATENCY_11) || \ + ((x) == EFM_LATENCY_12) || \ + ((x) == EFM_LATENCY_13) || \ + ((x) == EFM_LATENCY_14) || \ + ((x) == EFM_LATENCY_15)) + +/* Parameter validity check for read mode. */ +#define IS_VALID_READ_MD(MD) \ +( ((MD) == NormalRead) || \ + ((MD) == UltraPowerRead)) + +/* Parameter validity check for erase/program mode. */ +#define IS_VALID_ERASE_PGM_MD(MD) \ +( ((MD) == EFM_MODE_READONLY) || \ + ((MD) == EFM_MODE_SINGLEPROGRAM) || \ + ((MD) == EFM_MODE_SINGLEPROGRAMRB) || \ + ((MD) == EFM_MODE_SEQUENCEPROGRAM) || \ + ((MD) == EFM_MODE_SECTORERASE) || \ + ((MD) == EFM_MODE_CHIPERASE)) + +/* Parameter validity check for flash flag. */ +#define IS_VALID_FLASH_FLAG(flag) \ +( ((flag) == EFM_FLAG_WRPERR) || \ + ((flag) == EFM_FLAG_PEPRTERR) || \ + ((flag) == EFM_FLAG_PGSZERR) || \ + ((flag) == EFM_FLAG_PGMISMTCH) || \ + ((flag) == EFM_FLAG_EOP) || \ + ((flag) == EFM_FLAG_COLERR) || \ + ((flag) == EFM_FLAG_RDY)) + +/* Parameter validity check for flash clear flag. */ +#define IS_VALID_CLEAR_FLASH_FLAG(flag) \ +( ((flag) == EFM_FLAG_WRPERR) || \ + ((flag) == EFM_FLAG_PEPRTERR) || \ + ((flag) == EFM_FLAG_PGSZERR) || \ + ((flag) == EFM_FLAG_PGMISMTCH) || \ + ((flag) == EFM_FLAG_EOP) || \ + ((flag) == EFM_FLAG_COLERR)) + +/* Parameter validity check for flash interrupt. */ +#define IS_VALID_EFM_INT_SEL(int) \ +( ((int) == PgmErsErrInt) || \ + ((int) == EndPgmInt) || \ + ((int) == ColErrInt)) + +/* Parameter validity check for flash address. */ +#define IS_VALID_FLASH_ADDR(addr) \ +( ((addr) == 0x00000000u) || \ + (((addr) >= 0x00000001u) && \ + ((addr) <= 0x0007FFDFu))) + +/* Parameter validity check for flash address. */ +#define IS_VALID_OTP_LOCK_ADDR(addr) \ +( ((addr) >= 0x03000FC0u) || \ + ((addr) <= 0x03000FF8u)) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Unlock the flash. + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_Unlock(void) +{ + M4_EFM->FAPRT = EFM_KEY1; + M4_EFM->FAPRT = EFM_KEY2; +} + +/** + ******************************************************************************* + ** \brief Lock the flash. + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_Lock(void) +{ + if(EFM_UNLOCK == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = EFM_KEY2; + M4_EFM->FAPRT = EFM_KEY2; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the flash. + ** + ** \param [in] enNewState The new state of the flash. + ** \arg Enable Enable flash. + ** \arg Disable Stop flash. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_FlashCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FSTP_f.FSTP = ((Enable == enNewState) ? 0ul : 1ul); +} +/** + ******************************************************************************* + ** \brief Sets the code latency value.. + ** + ** \param [in] u32Latency specifies the FLASH Latency value. + ** \arg EFM_LATENCY_0 FLASH 0 Latency cycle + ** \arg EFM_LATENCY_1 FLASH 1 Latency cycle + ** \arg EFM_LATENCY_2 FLASH 2 Latency cycles + ** \arg EFM_LATENCY_3 FLASH 3 Latency cycles + ** \arg EFM_LATENCY_4 FLASH 4 Latency cycles + ** \arg EFM_LATENCY_5 FLASH 5 Latency cycles + ** \arg EFM_LATENCY_6 FLASH 6 Latency cycles + ** \arg EFM_LATENCY_7 FLASH 7 Latency cycles + ** \arg EFM_LATENCY_8 FLASH 8 Latency cycles + ** \arg EFM_LATENCY_9 FLASH 9 Latency cycles + ** \arg EFM_LATENCY_10 FLASH 10 Latency cycles + ** \arg EFM_LATENCY_11 FLASH 11 Latency cycles + ** \arg EFM_LATENCY_12 FLASH 12 Latency cycles + ** \arg EFM_LATENCY_13 FLASH 13 Latency cycles + ** \arg EFM_LATENCY_14 FLASH 14 Latency cycles + ** \arg EFM_LATENCY_15 FLASH 15 Latency cycles + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetLatency(uint32_t u32Latency) +{ + DDL_ASSERT(IS_VALID_FLASH_LATENCY(u32Latency)); + + M4_EFM->FRMC_f.FLWT = u32Latency; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the flash instruction cache. + ** + ** \param [in] enNewState The new state of the flash instruction cache. + ** \arg Enable Enable flash instruction cache. + ** \arg Disable Disable flash instruction cache. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_InstructionCacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FRMC_f.CACHE = enNewState; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the data cache reset. + ** + ** \param [in] enNewState The new state of the data cache reset. + ** \arg Enable Enable data cache reset. + ** \arg Disable Disable data cache reset. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_DataCacheRstCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FRMC_f.CRST = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the flash read mode. + ** + ** \param [in] enReadMD The flash read mode. + ** \arg NormalRead Normal read mode. + ** \arg UltraPowerRead Ultra_Low power read mode. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetReadMode(en_efm_read_md_t enReadMD) +{ + DDL_ASSERT(IS_VALID_READ_MD(enReadMD)); + M4_EFM->FRMC_f.SLPMD = enReadMD; +} + +/** + ******************************************************************************* + ** \brief Enable or disable erase / program. + ** + ** \param [in] enNewState The new state of the erase / program. + ** \arg Enable Enable erase / program. + ** \arg Disable Disable erase / program. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_ErasePgmCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FWMC_f.PEMODE = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the flash erase program mode. + ** + ** \param [in] u32Mode The flash erase program mode. + ** \arg EFM_MODE_READONLY The flash read only. + ** \arg EFM_MODE_SINGLEPROGRAM The flash single program. + ** \arg EFM_MODE_SINGLEPROGRAMRB The flash single program with read back. + ** \arg EFM_MODE_SEQUENCEPROGRAM The flash sequence program. + ** \arg EFM_MODE_SECTORERASE The flash sector erase. + ** \arg EFM_MODE_CHIPERASE The flash mass erase. + ** + ** \retval en_result_t. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SetErasePgmMode(uint32_t u32Mode) +{ + en_result_t enRet = Ok; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_ERASE_PGM_MD(u32Mode)); + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + break; + } + } + if(Ok == enRet) + { + M4_EFM->FWMC_f.PEMODE = Enable; + M4_EFM->FWMC_f.PEMOD = u32Mode; + M4_EFM->FWMC_f.PEMODE = Disable; + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Enable or disable the specified interrupt. + ** + ** \param [in] enInt The specified interrupt. + ** \arg PgmErsErrInt Program erase error interrupt. + ** \arg EndPgmInt End of Program interrupt. + ** \arg ReadErrInt Read collided error flag. + ** + ** \param [in] enNewState The new state of the specified interrupt. + ** \arg Enable Enable the specified interrupt. + ** \arg Disable Disable the specified interrupt. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_EFM_INT_SEL(enInt)); + + switch(enInt) + { + case PgmErsErrInt: + M4_EFM->FITE_f.PEERRITE = enNewState; + break; + case EndPgmInt: + M4_EFM->FITE_f.OPTENDITE = enNewState; + break; + case ColErrInt: + M4_EFM->FITE_f.COLERRITE = enNewState; + break; + default: + break; + } +} + +/** + ******************************************************************************* + ** \brief Checks whether the specified FLASH flag is set or not.. + ** + ** \param [in] u32flag Specifies the FLASH flag to check. + ** \arg EFM_FLAG_WRPERR Flash write protect error flag. + ** \arg EFM_FLAG_PEPRTERR Flash program protect area error flag. + ** \arg EFM_FLAG_PGSZERR Flash program size error flag. + ** \arg EFM_FLAG_PGMISMTCH Flash program miss match flag. + ** \arg EFM_FLAG_EOP Flash end of program flag. + ** \arg EFM_FLAG_COLERR Flash collision error flag. + ** \arg EFM_FLAG_RDY Flash ready flag. + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag) +{ + DDL_ASSERT(IS_VALID_FLASH_FLAG(u32flag)); + + return ((0ul == (M4_EFM->FSR & u32flag)) ? Reset :Set); +} + +/** + ******************************************************************************* + ** \brief Checks whether the specified FLASH flag is set or not.. + ** + ** \param [in] u32flag Specifies the FLASH flag to clear. + ** \arg EFM_FLAG_WRPERR Flash write protect error flag. + ** \arg EFM_FLAG_PEPRTERR Flash program protect area error flag. + ** \arg EFM_FLAG_PGSZERR Flash program size error flag. + ** \arg EFM_FLAG_PGMISMTCH Flash program miss match flag. + ** \arg EFM_FLAG_EOP Flash end of program flag. + ** \arg EFM_FLAG_COLERR Flash collision error flag. + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +void EFM_ClearFlag(uint32_t u32flag) +{ + //DDL_ASSERT(IS_VALID_CLEAR_FLASH_FLAG(u32flag)); + + M4_EFM->FSCLR = u32flag; +} +/** + ******************************************************************************* + ** \brief Get the flash status. + ** + ** \param None + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +en_efm_flash_status_t EFM_GetStatus(void) +{ + en_efm_flash_status_t enFlashStatus = FlashEOP; + + if(1ul == M4_EFM->FSR_f.RDY ) + { + enFlashStatus = FlashReady; + } + else if(1ul == M4_EFM->FSR_f.COLERR) + { + enFlashStatus = FlashRWErr; + } + else if(1ul == M4_EFM->FSR_f.OPTEND) + { + enFlashStatus = FlashEOP; + } + else if(1ul == M4_EFM->FSR_f.PGMISMTCH) + { + enFlashStatus = FlashPgMissMatch; + } + else if(1ul == M4_EFM->FSR_f.PGSZERR) + { + enFlashStatus = FlashPgSizeErr; + } + else if(1ul == M4_EFM->FSR_f.PEPRTERR) + { + enFlashStatus = FlashPgareaPErr; + } + else if(1ul == M4_EFM->FSR_f.PEWERR) + { + enFlashStatus = FlashWRPErr; + } + else + { + //else + } + + return enFlashStatus; +} + +/** + ******************************************************************************* + ** \brief Set flash the windows protect address. + ** + ** \param [in] stcAddr The specified windows protect address. + ** \arg StartAddr The start of windows protect address. + ** \arg EndAddr The end of windows protect address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr) +{ + M4_EFM->FPMTSW_f.FPMTSW = (stcAddr.StartAddr & EFM_PROTECT_ADDR_MSK); + M4_EFM->FPMTEW_f.FPMTEW = (stcAddr.EndAddr & EFM_PROTECT_ADDR_MSK); +} + +/** + ******************************************************************************* + ** \brief Set bus state while flash program & erase. + ** + ** \param [in] enState The specified bus state while flash program & erase. + ** \arg BusBusy The bus busy. + ** \arg BusRelease The bus release. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetBusState(en_efm_bus_sta_t enState) +{ + M4_EFM->FWMC_f.BUSHLDCTL = enState; +} + +/** + ******************************************************************************* + ** \brief Flash single program without read back. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Data The specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enRet = Ok; + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAM; + /* program data. */ + *(uint32_t*)u32Addr = u32Data; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + if(u32Data != *(uint32_t*)u32Addr) + { + enRet = Error; + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash single program with read back. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Data The specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enRet = Ok; + uint8_t u8tmp = 0u; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program with read back mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAMRB; + /* program data. */ + *(uint32_t*)u32Addr = u32Data; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + if(1ul == M4_EFM->FSR_f.PGMISMTCH) + { + enRet = Error; + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +static void *EFM_Memcpy(void *pvDst, void *pvSrc, uint32_t u32Count) +{ + uint8_t *u8TmpDst = (uint8_t *)pvDst; + uint8_t *u8TmpSrc = (uint8_t *)pvSrc; + + DDL_ASSERT(IS_VALID_POINTER(pvDst)); + DDL_ASSERT(IS_VALID_POINTER(pvSrc)); + + while (u32Count--) + { + *u8TmpDst++ = *u8TmpSrc++; + } + + return pvDst; +} +/** + ******************************************************************************* + ** \brief Flash sequence program. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Len The len of specified program data. + ** \param [in] *pBuf The pointer of specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf) +{ + en_result_t enRet = Ok; + uint8_t u8tmp; + uint32_t i; + uint16_t u16Timeout = 0u; + uint32_t u32Tmp = 0xFFFFFFFFul; + uint32_t *u32pSrc = pBuf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint32_t u32LoopWords = u32Len >> 2ul; + uint32_t u32RemainBytes = u32Len % 4ul; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + DDL_ASSERT(IS_VALID_POINTER(pBuf)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set sequence program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SEQUENCEPROGRAM; + /* clear read collided error flag.*/ + EFM_ClearFlag(EFM_FLAG_COLERR); + EFM_ClearFlag(EFM_FLAG_WRPERR); + + /* program data. */ + for(i = 0ul; i < u32LoopWords; i++) + { + *u32pDest++ = *u32pSrc++; + /* wait operate end. */ + while(1ul != M4_EFM->FSR_f.OPTEND) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + /* clear end flag. */ + EFM_ClearFlag(EFM_FLAG_EOP); + } + if(u32RemainBytes) + { + EFM_Memcpy(&u32Tmp, u32pSrc, u32RemainBytes); + *u32pDest++ = u32Tmp; + } + + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + + u16Timeout = 0u; + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash sector erase. + ** + ** \param [in] u32Addr The uncertain(random) address in the specified sector. + ** + ** \retval en_result_t + ** + ** \note The address should be word align. + ** + ******************************************************************************/ +en_result_t EFM_SectorErase(uint32_t u32Addr) +{ + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable erase. */ + EFM_ErasePgmCmd(Enable); + /* Set sector erase mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SECTORERASE; + + *(uint32_t*)u32Addr = 0x12345678u; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash mass erase. + ** + ** \param [in] u32Addr The uncertain(random) address in the flash. + ** + ** \retval en_result_t + ** + ** \note The address should be word align. + ** + ******************************************************************************/ +en_result_t EFM_MassErase(uint32_t u32Addr) +{ + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable erase. */ + EFM_ErasePgmCmd(Enable); + /* Set sector erase mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_CHIPERASE; + + *(uint32_t*)u32Addr = 0x12345678u; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get flash switch status. + ** + ** \param None. + ** + ** \retval en_flag_status_t + ** \arg Set The flash has switched, the start address is sector1. + ** \arg Reset The flash did not switch, the start address is sector0. + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t EFM_GetSwitchStatus(void) +{ + return ((0u == M4_EFM->FSWP_f.FSWP) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Lock OTP data block. + ** + ** \param u32Addr The addr to lock. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_OtpLock(uint32_t u32Addr) +{ + DDL_ASSERT(IS_VALID_OTP_LOCK_ADDR(u32Addr)); + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAM; + + /* Lock the otp block. */ + *(uint32_t*)u32Addr = 0ul; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + return enRet; +} +/** + ******************************************************************************* + ** \brief read unique ID. + ** + ** \param None + ** + ** \retval uint32_t + ** + ** \note None + ** + ******************************************************************************/ +stc_efm_unique_id_t EFM_ReadUID(void) +{ + stc_efm_unique_id_t stcUID; + + stcUID.uniqueID1 = M4_EFM->UQID1; + stcUID.uniqueID2 = M4_EFM->UQID2; + stcUID.uniqueID3 = M4_EFM->UQID3; + + return stcUID; +} + +//@} // EfmGroup + +#endif /* DDL_EFM_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_emb.c b/driver/src/hc32f460_emb.c new file mode 100644 index 0000000..9fe5840 --- /dev/null +++ b/driver/src/hc32f460_emb.c @@ -0,0 +1,487 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_emb.c + ** + ** A detailed description is available at + ** @link EMBGroup EMB description @endlink + ** + ** - 2018-11-24 CDT First version for Device Driver Library of EMB. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_emb.h" +#include "hc32f460_utility.h" + +#if (DDL_EMB_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup EMBGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for emb unit */ +#define IS_VALID_EMB_UNIT(__EMBx__) \ +( (M4_EMB1 == (__EMBx__)) || \ + (M4_EMB2 == (__EMBx__)) || \ + (M4_EMB3 == (__EMBx__)) || \ + (M4_EMB4 == (__EMBx__))) + +/*!< Parameter valid check for emb status*/ +#define IS_VALID_EMB_STATUS_TYPE(x) \ +( (EMBFlagPortIn == (x)) || \ + (EMBFlagPWMSame == (x)) || \ + (EMBFlagCmp == (x)) || \ + (EMBFlagOSCFail == (x)) || \ + (EMBPortInState == (x)) || \ + (EMBPWMState == (x))) + +/*!< Parameter valid check for emb status clear*/ +#define IS_VALID_EMB_STATUS_CLR(x) \ +( (EMBPortInFlagClr == (x)) || \ + (EMBPWMSameFlagCLr == (x)) || \ + (EMBCmpFlagClr == (x)) || \ + (EMBOSCFailFlagCLr == (x))) + +/*!< Parameter valid check for emb irq enable*/ +#define IS_VALID_EMB_IRQ(x) \ +( (PORTBrkIrq == (x)) || \ + (PWMSmBrkIrq == (x)) || \ + (CMPBrkIrq == (x)) || \ + (OSCFailBrkIrq == (x))) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/******************************************************************************* + * \brief EMB interrupt request enable or disable + * + * \param [in] EMBx EMB unit + * \param [in] enEMBIrq Irq type + * \param [in] bEn true/false + * + * \retval en_result_t Ok: config success + ******************************************************************************/ +en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx, + en_emb_irq_type_t enEMBIrq, + bool bEn) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_EMB_UNIT(EMBx)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_IRQ(enEMBIrq)); + + enRet = Ok; + switch (enEMBIrq) + { + case PORTBrkIrq: + EMBx->INTEN_f.PORTINTEN = (uint32_t)bEn; + break; + case PWMSmBrkIrq: + EMBx->INTEN_f.PWMINTEN = (uint32_t)bEn; + break; + case CMPBrkIrq: + EMBx->INTEN_f.CMPINTEN = (uint32_t)bEn; + break; + case OSCFailBrkIrq: + EMBx->INTEN_f.OSINTEN = (uint32_t)bEn; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get EMB status + ** + ** \param [in] EMBx EMB unit + ** + ** \param [in] enStatus EMB status type + ** + ** \retval EMB status + ** + ******************************************************************************/ +bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus) +{ + bool status = false; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_UNIT(EMBx)); + DDL_ASSERT(IS_VALID_EMB_STATUS_TYPE(enStatus)); + + switch (enStatus) + { + case EMBFlagPortIn: + status = EMBx->STAT_f.PORTINF; + break; + case EMBFlagPWMSame: + status = EMBx->STAT_f.PWMSF; + break; + case EMBFlagCmp: + status = EMBx->STAT_f.CMPF; + break; + case EMBFlagOSCFail: + status = EMBx->STAT_f.OSF; + break; + case EMBPortInState: + status = EMBx->STAT_f.PORTINST; + break; + case EMBPWMState: + status = EMBx->STAT_f.PWMST; + break; + default: + break; + } + + return status; +} + +/** + ******************************************************************************* + ** \brief EMB clear status(Recover from protection state) + ** + ** \param [in] EMBx EMB unit + ** + ** \param [in] enStatusClr EMB status clear type + ** + ** \retval en_result_t Ok: Config Success + ** + ******************************************************************************/ +en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx, + en_emb_status_clr_t enStatusClr) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_EMB_UNIT(EMBx)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATUS_CLR(enStatusClr)); + + enRet = Ok; + switch (enStatusClr) + { + case EMBPortInFlagClr: + EMBx->STATCLR_f.PORTINFCLR = 1ul; + break; + case EMBPWMSameFlagCLr: + EMBx->STATCLR_f.PWMSFCLR = 1ul; + break; + case EMBCmpFlagClr: + EMBx->STATCLR_f.CMPFCLR = 1ul; + break; + case EMBOSCFailFlagCLr: + EMBx->STATCLR_f.OSFCLR = 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/******************************************************************************* + * \brief EMB Control Register(CR) for timer6 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBConfigCR EMB Config CR pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcEMBConfigCR) + { + if (pstcEMBConfigCR->bEnPortBrake) + { + u32Val |= 1ul; + } + if (pstcEMBConfigCR->bEnCmp1Brake) + { + u32Val |= 1ul << 1; + } + if (pstcEMBConfigCR->bEnCmp2Brake) + { + u32Val |= 1ul << 2; + } + if (pstcEMBConfigCR->bEnCmp3Brake) + { + u32Val |= 1ul << 3; + } + if (pstcEMBConfigCR->bEnOSCFailBrake) + { + u32Val |= 1ul << 5; + } + if (pstcEMBConfigCR->bEnTimer61PWMSBrake) + { + u32Val |= 1ul << 6; + } + if (pstcEMBConfigCR->bEnTimer62PWMSBrake) + { + u32Val |= 1ul << 7; + } + if (pstcEMBConfigCR->bEnTimer63PWMSBrake) + { + u32Val |= 1ul << 8; + } + if (EMBPortFltDiv0 == pstcEMBConfigCR->enPortInFltClkSel) + { + } + if (EMBPortFltDiv8 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 1ul << 28; + } + if (EMBPortFltDiv32 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 2ul << 28; + } + if (EMBPortFltDiv128 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 3ul << 28; + } + if (pstcEMBConfigCR->bEnPorInFlt) + { + u32Val |= 1ul << 30; + } + if (pstcEMBConfigCR->bEnPortInLevelSel_Low) + { + u32Val |= 1ul << 31; + } + + M4_EMB1->CTL = u32Val; + enRet = Ok; + } + + return enRet; +} + + +/******************************************************************************* + * \brief EMB Control Register(CR) for timer4 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBConfigCR EMB Config CR pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_ctrl_timer4_t* pstcEMBConfigCR) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if ((M4_EMB1 != EMBx) && \ + (IS_VALID_EMB_UNIT(EMBx)) && \ + (NULL != pstcEMBConfigCR)) + { + if (pstcEMBConfigCR->bEnPortBrake) + { + u32Val |= 1ul; + } + if (pstcEMBConfigCR->bEnCmp1Brake) + { + u32Val |= 1ul << 1; + } + if (pstcEMBConfigCR->bEnCmp2Brake) + { + u32Val |= 1ul << 2; + } + if (pstcEMBConfigCR->bEnCmp3Brake) + { + u32Val |= 1ul << 3; + } + if (pstcEMBConfigCR->bEnOSCFailBrake) + { + u32Val |= 1ul << 5; + } + if (pstcEMBConfigCR->bEnTimer4xWHLSammeBrake) + { + u32Val |= 1ul << 6; + } + if (pstcEMBConfigCR->bEnTimer4xVHLSammeBrake) + { + u32Val |= 1ul << 7; + } + if (pstcEMBConfigCR->bEnTimer4xUHLSammeBrake) + { + u32Val |= 1ul << 8; + } + if (EMBPortFltDiv0 == pstcEMBConfigCR->enPortInFltClkSel) + { + } + if (EMBPortFltDiv8 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 1ul << 28; + } + if (EMBPortFltDiv32 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 2ul << 28; + } + if (EMBPortFltDiv128 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 3ul << 28; + } + if (pstcEMBConfigCR->bEnPorInFlt) + { + u32Val |= 1ul << 30; + } + if (pstcEMBConfigCR->bEnPortInLevelSel_Low) + { + u32Val |= 1ul << 31; + } + + EMBx->CTL = u32Val; + enRet = Ok; + } + + return enRet; +} + +/******************************************************************************* + * \brief EMB detect PWM atcive level (short detection) selection for timer6 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBPWMlv EMB en detect active level pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcEMBPWMlv) + { + if (pstcEMBPWMlv->bEnTimer61HighLevelDect) + { + u32Val |= 0x1ul; + } + if (pstcEMBPWMlv->bEnTimer62HighLevelDect) + { + u32Val |= 0x2ul; + } + if (pstcEMBPWMlv->bEnTimer63HighLevelDect) + { + u32Val |= 0x4ul; + } + + M4_EMB1->PWMLV = u32Val; + enRet = Ok; + } + + return enRet; +} + + +/******************************************************************************* + * \brief EMB detect PWM atcive level (short detection) selection for timer4 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBPWMlv EMB en detect active level pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_EMB_UNIT(EMBx)) && \ + (M4_EMB1 != EMBx) && \ + (NULL != pstcEMBPWMlv)) + { + if (pstcEMBPWMlv->bEnWHLphaseHighLevelDect) + { + u32Val |= 0x1ul; + } + if (pstcEMBPWMlv->bEnVHLPhaseHighLevelDect) + { + u32Val |= 0x2ul; + } + if (pstcEMBPWMlv->bEnUHLPhaseHighLevelDect) + { + u32Val |= 0x4ul; + } + + EMBx->PWMLV = u32Val; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief EMB Software brake + ** + ** \param [in] EMBx EMB unit + ** +** \param [in] bEn true: Software Brake Enable / false: Software Brake Disable + ** + ** \retval en_result_t Ok: Config Success + ** + ******************************************************************************/ +en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_UNIT(EMBx)); + + EMBx->SOE_f.SOE = (uint32_t)bEn; + + return Ok; +} + +//@} // EMBGroup + +#endif /* DDL_EMB_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_event_port.c b/driver/src/hc32f460_event_port.c new file mode 100644 index 0000000..fafc2ad --- /dev/null +++ b/driver/src/hc32f460_event_port.c @@ -0,0 +1,468 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_event_port.c + ** + ** A detailed description is available at + ** @link EventPortGroup EventPort description @endlink + ** + ** - 2018-12-07 CDT First version for Device Driver Library of EventPort. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_event_port.h" +#include "hc32f460_utility.h" + +#if (DDL_EVENT_PORT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup EventPortGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define EP1_BASE 0x40010800ul + 0x0100ul +#define EP2_BASE 0x40010800ul + 0x011Cul +#define EP3_BASE 0x40010800ul + 0x0138ul +#define EP4_BASE 0x40010800ul + 0x0154ul +#define EP1_DIR_BASE 0x00ul +#define EP1_IDR_BASE 0x04ul +#define EP1_ODR_BASE 0x08ul +#define EP1_ORR_BASE 0x0Cul +#define EP1_OSR_BASE 0x10ul +#define EP1_RISR_BASE 0x14ul +#define EP1_FAL_BASE 0x18ul +#define EP_NFCR_BASE 0x40010800ul + 0x0170ul + + +/*! Parameter validity check for port group. */ +#define IS_VALID_EVENT_PORT(x) \ +( ((x) == EventPort1) || \ + ((x) == EventPort2) || \ + ((x) == EventPort3) || \ + ((x) == EventPort4)) + +/*! Parameter validity check for pin. */ +#define IS_VALID_EVENT_PIN(x) \ +( ((x) == EventPin00) || \ + ((x) == EventPin01) || \ + ((x) == EventPin02) || \ + ((x) == EventPin03) || \ + ((x) == EventPin04) || \ + ((x) == EventPin05) || \ + ((x) == EventPin06) || \ + ((x) == EventPin07) || \ + ((x) == EventPin08) || \ + ((x) == EventPin09) || \ + ((x) == EventPin10) || \ + ((x) == EventPin11) || \ + ((x) == EventPin12) || \ + ((x) == EventPin13) || \ + ((x) == EventPin14) || \ + ((x) == EventPin15)) + +/*! Parameter valid check for Event Port common trigger. */ +#define IS_EP_COM_TRIGGER(x) \ +( ((x) == EpComTrigger_1) || \ + ((x) == EpComTrigger_2) || \ + ((x) == EpComTrigger_1_2)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Event Port init + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \param [in] pstcEventPortInit Structure pointer of event port configuration + ** + ** \retval Ok Init successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_Init(en_event_port_t enEventPort, uint16_t u16EventPin, \ + const stc_event_port_init_t *pstcEventPortInit) +{ + en_result_t enRet = Ok; + + uint32_t *EPDIRx; ///< Direction register + uint32_t *EPORRx; ///< Reset after trigger enable register + uint32_t *EPOSRx; ///< Set after trigger enable register + uint32_t *EPRISRx; ///< Rising edge detect enable register + uint32_t *EPFALx; ///< Falling edge detect enable register + + EPDIRx = (uint32_t *)(EP1_BASE + EP1_DIR_BASE + (0x1C * enEventPort)); + EPORRx = (uint32_t *)(EP1_BASE + EP1_ORR_BASE + (0x1C * enEventPort)); + EPOSRx = (uint32_t *)(EP1_BASE + EP1_OSR_BASE + (0x1C * enEventPort)); + EPRISRx= (uint32_t *)(EP1_BASE + EP1_RISR_BASE+ (0x1C * enEventPort)); + EPFALx = (uint32_t *)(EP1_BASE + EP1_FAL_BASE + (0x1C * enEventPort)); + + /* Direction configure */ + if (EventPortOut == pstcEventPortInit->enDirection) + { + *EPDIRx |= u16EventPin; + } + else + { + *EPDIRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Reset if be triggered */ + if (Enable == pstcEventPortInit->enReset) + { + *EPORRx |= u16EventPin; + } + else + { + *EPORRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Set if be triggered */ + if (Enable == pstcEventPortInit->enSet) + { + *EPOSRx |= u16EventPin; + } + else + { + *EPOSRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Rising edge detect setting */ + if (Enable == pstcEventPortInit->enRisingDetect) + { + *EPRISRx |= u16EventPin; + } + else + { + *EPRISRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Falling edge detect setting */ + if (Enable == pstcEventPortInit->enFallingDetect) + { + *EPFALx |= u16EventPin; + } + else + { + *EPFALx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Noise filter setting */ + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTNFCR_f.NFEN1 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS1 = pstcEventPortInit->enFilterClk; + break; + case EventPort2: + M4_AOS->PEVNTNFCR_f.NFEN2 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS2 = pstcEventPortInit->enFilterClk; + break; + case EventPort3: + M4_AOS->PEVNTNFCR_f.NFEN3 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS3 = pstcEventPortInit->enFilterClk; + break; + case EventPort4: + M4_AOS->PEVNTNFCR_f.NFEN4 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS4 = pstcEventPortInit->enFilterClk; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Event Port de-init, restore all registers to default value + ** + ** \param None + ** + ** \retval Ok De-init successful + ** + ******************************************************************************/ +en_result_t EVENTPORT_DeInit(void) +{ + uint32_t EPDIRx ; + uint32_t EPODRx ; + uint32_t EPORRx ; + uint32_t EPOSRx ; + uint32_t EPRISRx; + uint32_t EPFALx ; + uint8_t u8EPCnt; + + EPDIRx = (uint32_t)(EP1_BASE + EP1_DIR_BASE); + EPODRx = (uint32_t)(EP1_BASE + EP1_ODR_BASE); + EPORRx = (uint32_t)(EP1_BASE + EP1_ORR_BASE); + EPOSRx = (uint32_t)(EP1_BASE + EP1_OSR_BASE); + EPRISRx = (uint32_t)(EP1_BASE + EP1_RISR_BASE); + EPFALx = (uint32_t)(EP1_BASE + EP1_FAL_BASE); + + /* Restore all registers to default value */ + M4_AOS->PORT_PEVNTTRGSR12 = 0x1FFul; + M4_AOS->PORT_PEVNTTRGSR34 = 0x1FFul; + M4_AOS->PEVNTNFCR = 0ul; + for (u8EPCnt = 0u; u8EPCnt < 4u; u8EPCnt++) + { + *(uint32_t *)(EPDIRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPODRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPORRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPOSRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPRISRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPFALx + 0x1Cul * u8EPCnt) = 0ul; + } + return Ok; +} + +/** + ******************************************************************************* + ** \brief Event Port trigger source select + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enTriggerSrc Event port trigger source. This parameter + ** can be any value of @ref en_event_src_t + ** \retval Ok Trigger source is set + ** ErrorInvalidParameter Invalid event port enum + ** + ******************************************************************************/ +en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort, \ + en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + if ((EventPort1 == enEventPort) || (EventPort2 == enEventPort)) + { + M4_AOS->PORT_PEVNTTRGSR12 = enTriggerSrc; + } + else if ((EventPort3 == enEventPort) || (EventPort4 == enEventPort)) + { + M4_AOS->PORT_PEVNTTRGSR34 = enTriggerSrc; + } + else + { + enRet = ErrorInvalidParameter; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Event Port common trigger. + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enComTrigger Event port common trigger selection. + ** See @ref en_event_port_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort, \ + en_event_port_com_trigger_t enComTrigger, \ + en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + __IO uint32_t *TRGSELx; + + TRGSELx = (__IO uint32_t *)((uint32_t)&M4_AOS->PORT_PEVNTTRGSR12 + (4UL * ((uint32_t)enEventPort/2UL))); + + if (NULL != TRGSELx) + { + DDL_ASSERT(IS_EP_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } + } +} + +/** + ******************************************************************************* + ** \brief Read Event Port value after be triggered + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** + ** \retval uint16_t The output port value + ** + ******************************************************************************/ +uint16_t EVENTPORT_GetData(en_event_port_t enEventPort) +{ + uint16_t u16Data = 0u; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + switch (enEventPort) + { + case EventPort1: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR1 & 0xFFFFul); + break; + case EventPort2: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR2 & 0xFFFFul); + break; + case EventPort3: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR3 & 0xFFFFul); + break; + case EventPort4: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR4 & 0xFFFFul); + break; + } + return u16Data; +} + +/** + ******************************************************************************* + ** \brief Read Event Pin value after triggered + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enEventPin GPIO pin index, This parameter can be + ** any value of @ref en_event_pin_t + ** \retval en_flag_status_t The output port pin value + ** + ******************************************************************************/ +en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort, en_event_pin_t enEventPin) +{ + bool bBitValue = false; + + switch (enEventPort) + { + case EventPort1: + bBitValue = M4_AOS->PEVNTIDR1 & enEventPin; + break; + case EventPort2: + bBitValue = M4_AOS->PEVNTIDR2 & enEventPin; + break; + case EventPort3: + bBitValue = M4_AOS->PEVNTIDR3 & enEventPin; + break; + case EventPort4: + bBitValue = M4_AOS->PEVNTIDR4 & enEventPin; + break; + } + return (en_flag_status_t)(bool)((!!bBitValue)); +} + +/** + ******************************************************************************* + ** \brief Set Event Port Pin + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \retval Ok Set successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort, en_event_pin_t u16EventPin) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTODR1 |= u16EventPin; + break; + case EventPort2: + M4_AOS->PEVNTODR2 |= u16EventPin; + break; + case EventPort3: + M4_AOS->PEVNTODR3 |= u16EventPin; + break; + case EventPort4: + M4_AOS->PEVNTODR4 |= u16EventPin; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reset Event Port Pin + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \retval Ok Reset successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort, en_event_pin_t u16EventPin) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTODR1 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort2: + M4_AOS->PEVNTODR2 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort3: + M4_AOS->PEVNTODR3 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort4: + M4_AOS->PEVNTODR4 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +//@} // EventPortGroup + +#endif /* DDL_EVENT_PORT_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/driver/src/hc32f460_exint_nmi_swi.c b/driver/src/hc32f460_exint_nmi_swi.c new file mode 100644 index 0000000..56f5e9c --- /dev/null +++ b/driver/src/hc32f460_exint_nmi_swi.c @@ -0,0 +1,337 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_exint_nmi_swi.c + ** + ** A detailed description is available at + ** @link ExintNmiSwiGroup Exint/Nmi/Swi description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of exint, Nmi, SW interrupt. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_exint_nmi_swi.h" +#include "hc32f460_utility.h" + +#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup ExintNmiSwiGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + /*! Parameter validity check for external interrupt channel. */ +#define IS_VALID_CH(x) \ +( ((x) == ExtiCh00) || \ + ((x) == ExtiCh01) || \ + ((x) == ExtiCh02) || \ + ((x) == ExtiCh03) || \ + ((x) == ExtiCh04) || \ + ((x) == ExtiCh05) || \ + ((x) == ExtiCh06) || \ + ((x) == ExtiCh07) || \ + ((x) == ExtiCh08) || \ + ((x) == ExtiCh09) || \ + ((x) == ExtiCh10) || \ + ((x) == ExtiCh11) || \ + ((x) == ExtiCh12) || \ + ((x) == ExtiCh13) || \ + ((x) == ExtiCh14) || \ + ((x) == ExtiCh15)) + +/*! Parameter validity check for null pointer. */ +#define IS_NULL_POINT(x) (NULL != (x)) + +/*! Parameter validity check for external interrupt trigger method. */ +#define IS_VALID_LEVEL(x) \ +( ((x) == ExIntLowLevel) || \ + ((x) == ExIntBothEdge) || \ + ((x) == ExIntRisingEdge) || \ + ((x) == ExIntFallingEdge)) + +/*! Parameter validity check for NMI interrupt source. */ +#define IS_VALID_NMI_SRC(x) \ +( ((x) == NmiSrcNmi) || \ + ((x) == NmiSrcSwdt) || \ + ((x) == NmiSrcVdu1) || \ + ((x) == NmiSrcVdu2) || \ + ((x) == NmiSrcXtalStop) || \ + ((x) == NmiSrcSramPE) || \ + ((x) == NmiSrcSramDE) || \ + ((x) == NmiSrcMpu) || \ + ((x) == NmiSrcWdt)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnNmiCallback; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief External Int initialization + ** + ** \param [in] pstcExtiConfig EXTI configure structure + ** + ** \retval Ok EXTI initialized + ** + ******************************************************************************/ +en_result_t EXINT_Init(const stc_exint_config_t *pstcExtiConfig) +{ + stc_intc_eirqcr_field_t *EIRQCRx; + + DDL_ASSERT(IS_VALID_CH(pstcExtiConfig->enExitCh)); + + EIRQCRx = (stc_intc_eirqcr_field_t *)((uint32_t)(&M4_INTC->EIRQCR0) + \ + (uint32_t)(4ul * (uint32_t)(pstcExtiConfig->enExitCh))); + + /* Set filter function */ + EIRQCRx->EFEN = pstcExtiConfig->enFilterEn; + EIRQCRx->EISMPCLK = pstcExtiConfig->enFltClk; + + /* Set detection level */ + EIRQCRx->EIRQTRG = pstcExtiConfig->enExtiLvl; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get External interrupt request flag + ** + ** \param [in] enExint NMI Int source, This parameter can be + ** any value of @ref en_exti_ch_t + ** + ** \retval Set Corresponding Ex.Int request flag be set + ** Reset Corresponding Ex.Int request flag not be set + ** + ******************************************************************************/ +en_int_status_t EXINT_IrqFlgGet(en_exti_ch_t enExint) +{ + en_int_status_t enRet; + DDL_ASSERT(IS_VALID_CH(enExint)); + + enRet = (1u == !!(M4_INTC->EIFR & (1ul<EICFR |= (uint32_t)(1ul << enExint); + return Ok; +} + +/** + ******************************************************************************* + ** \brief NMI initialization + ** + ** \param [in] pstcNmiConfig NMI configure structure + ** + ** \retval Ok NMI initialized + ** ErrorInvalidParameter NMI configuration pointer is null + ** + ******************************************************************************/ +en_result_t NMI_Init(const stc_nmi_config_t *pstcNmiConfig) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcNmiConfig) + { + /* NMI callback function */ + pfnNmiCallback = pstcNmiConfig->pfnNmiCallback; + /* Set filter function */ + M4_INTC->NMICR_f.NFEN = pstcNmiConfig->enFilterEn; + /* Set filter clock */ + M4_INTC->NMICR_f.NSMPCLK = pstcNmiConfig->enFilterClk; + /* Set detection level */ + M4_INTC->NMICR_f.NMITRG = pstcNmiConfig->enNmiLvl; + /* Set NMI source */ + M4_INTC->NMIENR = (uint32_t)pstcNmiConfig->u16NmiSrc; + enRet = Ok; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Init Non-Maskable Interrupt (NMI) + ** + ** \param None + ** + ** \retval Ok NMI De-initialized + ** + ******************************************************************************/ +en_result_t NMI_DeInit(void) +{ + /* Set internal data */ + pfnNmiCallback = NULL; + + /* clear NMI control register */ + M4_INTC->NMICR = 0u; + + /* clear NMI enable register */ + M4_INTC->NMIENR = 0u; + + /* clear all NMI flags */ + M4_INTC->NMIFR = 0u; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get NMI interrupt request flag + ** + ** \param [in] enNmiSrc NMI Int source, This parameter can be + ** any value of @ref en_nmi_src_t + ** + ** \retval Set Corresponding NMI flag be set + ** Reset Corresponding NMI flag not be set + ** + ******************************************************************************/ +en_int_status_t NMI_IrqFlgGet(en_nmi_src_t enNmiSrc) +{ + DDL_ASSERT(IS_VALID_NMI_SRC(enNmiSrc)); + + en_int_status_t enRet = Reset; + switch (enNmiSrc) + { + case NmiSrcNmi: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.NMIFR); + break; + case NmiSrcSwdt: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.SWDTFR); + break; + case NmiSrcVdu1: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.PVD1FR); + break; + case NmiSrcVdu2: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.PVD2FR); + break; + case NmiSrcXtalStop: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.XTALSTPFR); + break; + case NmiSrcSramPE: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.REPFR); + break; + case NmiSrcSramDE: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.RECCFR); + break; + case NmiSrcMpu: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.BUSMFR); + break; + case NmiSrcWdt: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.WDTFR); + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear NMI interrupt request flag + ** + ** \param [in] u16NmiSrc NMI Int source, This parameter can be + ** any composited value of @ref en_nmi_src_t + ** + ** \retval Ok Interrupt source be cleared + ** + ******************************************************************************/ +en_result_t NMI_IrqFlgClr(uint16_t u16NmiSrc) +{ + M4_INTC->NMICFR |= u16NmiSrc; + return Ok; +} + +/** + ******************************************************************************* + ** \brief ISR for NMI + ** + ******************************************************************************/ +void NMI_IrqHandler(void) +{ + DDL_ASSERT(IS_NULL_POINT(pfnNmiCallback)); + + pfnNmiCallback(); +} + +/** + ******************************************************************************* + ** \brief Enable Softeware Interrupt (SWI) + ** + * \param [in] u32SwiCh This parameter can be any composited + * value of @ref en_swi_ch_t + ** + ** \retval Ok SWI initialized + ** + ******************************************************************************/ +en_result_t SWI_Enable(uint32_t u32SwiCh) +{ + M4_INTC->SWIER |= u32SwiCh; + return Ok; +} + +/** + ******************************************************************************* + ** \brief De-Init Softeware Interrupt (SWI) + ** + * \param [in] u32SwiCh This parameter can be any composited + * value of @ref en_swi_ch_t + ** + ** \retval Ok SWI de-initialized + ** + ******************************************************************************/ +en_result_t SWI_Disable(uint32_t u32SwiCh) +{ + /* clear software interrupt enable register */ + M4_INTC->SWIER &= ~u32SwiCh; + + return Ok; +} + +//@} // ExintNmiSwiGroup + +#endif /* DDL_EXINT_NMI_SWI_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_gpio.c b/driver/src/hc32f460_gpio.c new file mode 100644 index 0000000..16b8656 --- /dev/null +++ b/driver/src/hc32f460_gpio.c @@ -0,0 +1,671 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_gpio.c + ** + ** A detailed description is available at + ** @link GpioGroup Gpio description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of Gpio. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_gpio.h" +#include "hc32f460_utility.h" + +#if (DDL_GPIO_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup GpioGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define GPIO_BASE (0x40053800ul) +#define PODR_BASE (0x0004ul) +#define POER_BASE (0x0006ul) +#define POSR_BASE (0x0008ul) +#define PORR_BASE (0x000Aul) +#define PCR_BASE (0x0400ul) +#define PFSR_BASE (0x0402ul) + +/*! Parameter validity check for port group. */ +#define IS_VALID_PORT(x) \ +( ((x) == PortA) || \ + ((x) == PortB) || \ + ((x) == PortC) || \ + ((x) == PortD) || \ + ((x) == PortE) || \ + ((x) == PortH)) + +/*! Parameter validity check for pin. */ +#define IS_VALID_PIN(x) \ +( ((x) == Pin00) || \ + ((x) == Pin01) || \ + ((x) == Pin02) || \ + ((x) == Pin03) || \ + ((x) == Pin04) || \ + ((x) == Pin05) || \ + ((x) == Pin06) || \ + ((x) == Pin07) || \ + ((x) == Pin08) || \ + ((x) == Pin09) || \ + ((x) == Pin10) || \ + ((x) == Pin11) || \ + ((x) == Pin12) || \ + ((x) == Pin13) || \ + ((x) == Pin14) || \ + ((x) == Pin15)) + +/*! Parameter validity check for debug pins. */ +#define IS_VALID_DEBUGPIN(x) ((x) <= 0x1Fu) + +/*! Parameter validity check for pin mode. */ +#define IS_VALID_PINMODE(x) \ +( ((x) == Pin_Mode_In) || \ + ((x) == Pin_Mode_Out) || \ + ((x) == Pin_Mode_Ana)) + +/*! Parameter validity check for pin drive capacity. */ +#define IS_VALID_PINDRV(x) \ +( ((x) == Pin_Drv_L) || \ + ((x) == Pin_Drv_M) || \ + ((x) == Pin_Drv_H)) + +/*! Parameter validity check for pin output type. */ +#define IS_VALID_PINTYPE(x) \ +( ((x) == Pin_OType_Cmos) || \ + ((x) == Pin_OType_Od)) + +/*! Parameter validity check for pin read wait cycle. */ +#define IS_VALID_READWAIT(x) \ +( ((x) == WaitCycle0) || \ + ((x) == WaitCycle1) || \ + ((x) == WaitCycle2) || \ + ((x) == WaitCycle3)) + +/*! Parameter validity check for pin function */ +#define IS_VALID_FUNC(x) \ +( ((x) == Func_Gpio) || \ + (((x) >= Func_Fcmref) && \ + ((x) <= Func_I2s)) || \ + ((x) == Func_Evnpt) || \ + ((x) == Func_Eventout) || \ + (((x) >= Func_Usart1_Tx) && \ + ((x) <= Func_I2s2_Ck))) + +/*! Parameter validity check for pin sub-function */ +#define IS_VALID_SUBFUNC(x) \ +( ((x) == Func_Gpio) || \ + ((x) == Func_Fcmref) || \ + ((x) == Func_Rtcout) || \ + ((x) == Func_Vcout) || \ + ((x) == Func_Adtrg) || \ + ((x) == Func_Mclkout) || \ + ((x) == Func_Tim4) || \ + ((x) == Func_Tim6) || \ + ((x) == Func_Tima0) || \ + ((x) == Func_Tima1) || \ + ((x) == Func_Tima2) || \ + ((x) == Func_Emb) || \ + ((x) == Func_Usart_Ck) || \ + ((x) == Func_Spi_Nss) || \ + ((x) == Func_Qspi) || \ + ((x) == Func_Key) || \ + ((x) == Func_Sdio) || \ + ((x) == Func_I2s) || \ + ((x) == Func_UsbF) || \ + ((x) == Func_Evnpt) || \ + ((x) == Func_Eventout)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Port init + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \param [in] pstcPortInit Structure pointer of port configuration + ** + ** \retval Ok Port initial successful + ** + ******************************************************************************/ +en_result_t PORT_Init(en_port_t enPort, uint16_t u16Pin, const stc_port_init_t *pstcPortInit) +{ + stc_port_pcr_field_t *PCRx; + stc_port_pfsr_field_t * PFSRx; + uint8_t u8PinPos = 0u; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + DDL_ASSERT(IS_VALID_PINMODE(pstcPortInit->enPinMode)); + DDL_ASSERT(IS_VALID_PINDRV(pstcPortInit->enPinDrv)); + DDL_ASSERT(IS_VALID_PINTYPE(pstcPortInit->enPinOType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enLatch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enExInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enInvert)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enPullUp)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enPinSubFunc)); + + PORT_Unlock(); + for (u8PinPos = 0u; u8PinPos < 16u; u8PinPos ++) + { + if (u16Pin & (1ul<PCRA0) + \ + enPort * 0x40ul + u8PinPos * 0x04ul); + PFSRx = (stc_port_pfsr_field_t *)((uint32_t)(&M4_PORT->PFSRA0) + \ + enPort * 0x40ul + u8PinPos * 0x04ul); + + /* Input latch function setting */ + PCRx->LTE = pstcPortInit->enLatch; + + /* External interrupt input enable setting */ + PCRx->INTE = pstcPortInit->enExInt; + + /* In_Out invert setting */ + PCRx->INVE = pstcPortInit->enInvert; + + /* Pin pull-up setting */ + PCRx->PUU = pstcPortInit->enPullUp; + + /* CMOS/OD output setting */ + PCRx->NOD = pstcPortInit->enPinOType; + + /* Pin drive mode setting */ + PCRx->DRV = pstcPortInit->enPinDrv; + + /* Pin mode setting */ + switch (pstcPortInit->enPinMode) + { + case Pin_Mode_In: + PCRx->DDIS = 0u; + PCRx->POUTE = 0u; + break; + case Pin_Mode_Out: + PCRx->DDIS = 0u; + PCRx->POUTE = 1u; + break; + case Pin_Mode_Ana: + PCRx->DDIS = 1u; + break; + default: + break; + } + /* Sub function enable setting */ + PFSRx->BFE = pstcPortInit->enPinSubFunc; + } + } + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port de-init + ** + ** \param None + ** + ** \retval Ok GPIO de-initial successful + ** + ******************************************************************************/ +en_result_t PORT_DeInit(void) +{ + uint8_t u8PortIdx, u8PinIdx; + PORT_Unlock(); + + for (u8PortIdx = (uint8_t)PortA; u8PortIdx <= (uint8_t)PortH; u8PortIdx++) + { + *(uint16_t *)(GPIO_BASE + PODR_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + POER_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + POSR_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + PORR_BASE + u8PortIdx * 0x10ul) = 0u; + for (u8PinIdx = 0u; u8PinIdx < 16u; u8PinIdx++) + { + if (((uint8_t)PortH == u8PortIdx) && (3u == u8PinIdx)) + { + break; + } + *(uint16_t *)(GPIO_BASE + PCR_BASE + u8PortIdx * 0x40ul + u8PinIdx * 0x4ul) = 0u; + *(uint16_t *)(GPIO_BASE + PFSR_BASE + u8PortIdx * 0x40ul + u8PinIdx * 0x4ul) = 0u; + } + } + M4_PORT->PCCR = 0u; + M4_PORT->PINAER = 0u; + M4_PORT->PSPCR = 0x1Fu; + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Special control register Setting + ** + ** \param [in] u8DebugPort Debug port setting register, This parameter + ** can be any composed value of @ref en_debug_port_t + ** + ** \param [in] enFunc The new state of the debug ports. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Debug port set successful + ** + ******************************************************************************/ +en_result_t PORT_DebugPortSetting(uint8_t u8DebugPort, en_functional_state_t enFunc) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_DEBUGPIN(u8DebugPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enFunc)); + + PORT_Unlock(); + + if (Enable == enFunc) + { + M4_PORT->PSPCR |= (uint16_t)(u8DebugPort & 0x1Ful); + } + else + { + M4_PORT->PSPCR &= (uint16_t)(~(u8DebugPort & 0x1Ful)); + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port Public Setting + ** + ** \param [in] pstcPortPubSet Structure pointer of public setting (PCCR) + ** + ** \retval Ok Port public register set successful + ** + ******************************************************************************/ +en_result_t PORT_PubSetting(const stc_port_pub_set_t *pstcPortPubSet) +{ + DDL_ASSERT(IS_VALID_FUNC(pstcPortPubSet->enSubFuncSel)); + DDL_ASSERT(IS_VALID_READWAIT(pstcPortPubSet->enReadWait)); + PORT_Unlock(); + + /* PCCR setting */ + /* Sub function setting */ + M4_PORT->PCCR_f.BFSEL = pstcPortPubSet->enSubFuncSel; + + /* PIDRx, PCRxy read wait cycle setting */ + M4_PORT->PCCR_f.RDWT = pstcPortPubSet->enReadWait; + + PORT_Lock(); + return Ok; +} + + +/** + ******************************************************************************* + ** \brief PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PORT_Unlock(void) +{ + M4_PORT->PWPR = 0xA501u; +} + +/** + ******************************************************************************* + ** \brief SPCR, PCCR, PINAER, PCRxy, PFSRxy write disable + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PORT_Lock(void) +{ + M4_PORT->PWPR = 0xA500u; +} + +/** + ******************************************************************************* + ** \brief Read Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** + ** \retval uint16_t The output port value + ** + ******************************************************************************/ +uint16_t PORT_GetData(en_port_t enPort) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + uint32_t *PIDRx; + PIDRx = (uint32_t *)((uint32_t)(&M4_PORT->PIDRA) + 0x10u * enPort); + return (uint16_t)(*PIDRx); +} + +/** + ******************************************************************************* + ** \brief Read Pin value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] enPin GPIO pin index, This parameter can be + ** any value of @ref en_pin_t + ** \retval en_flag_status_t The output port pin value + ** + ******************************************************************************/ +en_flag_status_t PORT_GetBit(en_port_t enPort, en_pin_t enPin) +{ + uint32_t *PIDRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_VALID_PIN(enPin)); + + PIDRx = (uint32_t *)((uint32_t)(&M4_PORT->PIDRA) + 0x10u * enPort); + return (en_flag_status_t)((bool)(!!(*PIDRx & (enPin)))); +} + +/** + ******************************************************************************* + ** \brief Set Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** + ** \retval Ok Data be set to corresponding port + ** + ******************************************************************************/ +en_result_t PORT_SetPortData(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PODRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PODRx = (uint16_t *)((uint32_t)(&M4_PORT->PODRA) + 0x10u * enPort); + *PODRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** + ** \retval Ok Data be reset to corresponding port + ** + ******************************************************************************/ +en_result_t PORT_ResetPortData(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PODRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PODRx = (uint16_t *)((uint32_t)(&M4_PORT->PODRA) + 0x10u * enPort); + *PODRx &= (uint16_t)(~u16Pin); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port Pin Output enable + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \param [in] enNewState The new state of pin direction setting + ** \retval Ok Set successful to corresponding port/pin + ** + ******************************************************************************/ +en_result_t PORT_OE(en_port_t enPort, uint16_t u16Pin, en_functional_state_t enNewState) +{ + uint16_t *POERx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POERx = (uint16_t *)((uint32_t)(&M4_PORT->POERA) + 0x10ul * enPort); + if (Enable == enNewState) + { + *POERx |= u16Pin; + } + else + { + *POERx &= (uint16_t)(~u16Pin); + } + return Ok; + +} + +/** + ******************************************************************************* + ** \brief Set Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetBits(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *POSRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POSRx = (uint16_t *)((uint32_t)(&M4_PORT->POSRA) + 0x10u * enPort); + *POSRx |= u16Pin; + return Ok; + +} + +/** + ******************************************************************************* + ** \brief Reset Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_ResetBits(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PORRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PORRx = (uint16_t *)((uint32_t)(&M4_PORT->PORRA) + 0x10u * enPort); + *PORRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Toggle Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *POTRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POTRx = (uint16_t *)((uint32_t)(&M4_PORT->POTRA) + 0x10u * enPort); + *POTRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set port always ON + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] enNewState The new state of the port always ON function. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_AlwaysOn(en_port_t enPort, en_functional_state_t enNewState) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + PORT_Unlock(); + + if (Enable == enNewState) + { + M4_PORT->PINAER |= Enable << (uint8_t)enPort; + } + else + { + M4_PORT->PINAER &= (uint16_t)(~(((1ul << (uint8_t)enPort)) & 0x1Ful)); + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set Port Pin function + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any value of @ref en_pin_t + ** \param [in] enFuncSel Function selection, This parameter can be + ** any value of @ref en_port_func_t + ** + ** \param [in] enSubFunc The new state of the gpio sub-function. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin, en_port_func_t enFuncSel, \ + en_functional_state_t enSubFunc) +{ + stc_port_pfsr_field_t *PFSRx; + uint8_t u8PinPos = 0u; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_VALID_FUNC(enFuncSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enSubFunc)); + + PORT_Unlock(); + + for (u8PinPos = 0u; u8PinPos < 16u; u8PinPos ++) + { + if (u16Pin & (uint16_t)(1ul<PFSRA0) \ + + 0x40ul * enPort + 0x4ul * u8PinPos); + + /* main function setting */ + PFSRx->FSEL = enFuncSel; + + /* sub function enable setting */ + PFSRx->BFE = (Enable == enSubFunc ? Enable : Disable); + } + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set global sub-function + ** + ** \param [in] enFuncSel Function selection, This parameter can be + ** some values of @ref en_port_func_t, cannot + ** large than 15u + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetSubFunc(en_port_func_t enFuncSel) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_SUBFUNC(enFuncSel)); + + PORT_Unlock(); + + M4_PORT->PCCR_f.BFSEL = enFuncSel; + + PORT_Lock(); + return Ok; +} + +//@} // GpioGroup + +#endif /* DDL_GPIO_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/driver/src/hc32f460_hash.c b/driver/src/hc32f460_hash.c new file mode 100644 index 0000000..393736b --- /dev/null +++ b/driver/src/hc32f460_hash.c @@ -0,0 +1,301 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_hash.c + ** + ** A detailed description is available at + ** @link HashGroup HASH description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of HASH. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_hash.h" +#include "hc32f460_utility.h" + +#if (DDL_HASH_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup HashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Constants definitions. */ +#define HASH_GROUP_LEN (64u) +#define LAST_GROUP_MAX_LEN (56u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void HASH_WriteData(const uint8_t *pu8SrcData); +static void HASH_GetMsgDigest(uint8_t *pu8MsgDigest); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize the HASH. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void HASH_Init(void) +{ + /* Stop hash calculating */ + bM4_HASH_CR_START = 0u; +} + +/** + ******************************************************************************* + ** \brief DeInitialize the HASH. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void HASH_DeInit(void) +{ + /* Stop hash calculating */ + bM4_HASH_CR_START = 0u; + + /* Reset register CR. */ + M4_HASH->CR = 0u; +} + +/** + ******************************************************************************* + ** \brief HASH(SHA256) processes pu8SrcData. + ** + ** \param [in] pu8SrcData Pointer to the source data buffer (buffer to + ** be hashed). + ** + ** \param [in] u32SrcDataSize Length of the input buffer in bytes. + ** + ** \param [out] pu8MsgDigest Pointer to the computed digest. Its size + ** must be 32 bytes. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout HASH works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t HASH_Start(const uint8_t *pu8SrcData, + uint32_t u32SrcDataSize, + uint8_t *pu8MsgDigest, + uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8FillBuffer[HASH_GROUP_LEN]; + uint8_t u8FirstGroup = 0u; + uint8_t u8HashEnd = 0u; + uint8_t u8DataEndMark = 0u; + uint32_t u32Index = 0u; + uint32_t u32BitLenHi; + uint32_t u32BitLenLo; + uint32_t u32HashTimeout; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8SrcData) && + (0u != u32SrcDataSize) && + (NULL != pu8MsgDigest) && + (0u != u32Timeout)) + { + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32HashTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + u32BitLenHi = (u32SrcDataSize >> 29u) & 0x7u; + u32BitLenLo = (u32SrcDataSize << 3u); + + while (1u) + { + /* Stop hash calculating. */ + bM4_HASH_CR_START = 0u; + + if (u32SrcDataSize >= HASH_GROUP_LEN) + { + HASH_WriteData(&pu8SrcData[u32Index]); + u32SrcDataSize -= HASH_GROUP_LEN; + u32Index += HASH_GROUP_LEN; + } + else if (u32SrcDataSize >= LAST_GROUP_MAX_LEN) + { + memset(u8FillBuffer, 0, HASH_GROUP_LEN); + memcpy(u8FillBuffer, &pu8SrcData[u32Index], u32SrcDataSize); + u8FillBuffer[u32SrcDataSize] = 0x80u; + u8DataEndMark = 1u; + HASH_WriteData(u8FillBuffer); + u32SrcDataSize = 0u; + } + else + { + u8HashEnd = 1u; + } + + if (u8HashEnd != 0u) + { + memset(u8FillBuffer, 0, HASH_GROUP_LEN); + if (u32SrcDataSize > 0u) + { + memcpy(u8FillBuffer, &pu8SrcData[u32Index], u32SrcDataSize); + } + if (u8DataEndMark == 0u) + { + u8FillBuffer[u32SrcDataSize] = 0x80u; + } + u8FillBuffer[63u] = (uint8_t)(u32BitLenLo); + u8FillBuffer[62u] = (uint8_t)(u32BitLenLo >> 8u); + u8FillBuffer[61u] = (uint8_t)(u32BitLenLo >> 16u); + u8FillBuffer[60u] = (uint8_t)(u32BitLenLo >> 24u); + u8FillBuffer[59u] = (uint8_t)(u32BitLenHi); + u8FillBuffer[58u] = (uint8_t)(u32BitLenHi >> 8u); + u8FillBuffer[57u] = (uint8_t)(u32BitLenHi >> 16u); + u8FillBuffer[56u] = (uint8_t)(u32BitLenHi >> 24u); + HASH_WriteData(u8FillBuffer); + } + + /* check if first group */ + if (0u == u8FirstGroup) + { + u8FirstGroup = 1u; + /* Set first group. */ + bM4_HASH_CR_FST_GRP = 1u; + } + else + { + /* Set continuous group. */ + bM4_HASH_CR_FST_GRP = 0u; + } + + /* Start hash calculating. */ + bM4_HASH_CR_START = 1u; + + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32HashTimeout) + { + if (bM4_HASH_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if ((ErrorTimeout == enRet) || (u8HashEnd != 0u)) + { + break; + } + } + + if (Ok == enRet) + { + /* HASH calculated done */ + HASH_GetMsgDigest(pu8MsgDigest); + } + + /* Stop hash calculating. */ + bM4_HASH_CR_START = 0u; + } + + return enRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Writes the input buffer in data register. + ** + ** \param [in] pu8SrcData Pointer to source data buffer. + ** + ** \retval None + ** + ******************************************************************************/ +static void HASH_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + uint8_t j; + uint32_t u32Temp; + __IO uint32_t *io32HashDr = &(M4_HASH->DR15); + + for (i = 0u; i < 16u; i++) + { + j = i * 4u + 3u; + u32Temp = (uint32_t)pu8SrcData[j]; + u32Temp |= ((uint32_t)pu8SrcData[j-1u]) << 8u; + u32Temp |= ((uint32_t)pu8SrcData[j-2u]) << 16u; + u32Temp |= ((uint32_t)pu8SrcData[j-3u]) << 24u; + + *io32HashDr = u32Temp; + io32HashDr++; + } +} + +/** + ******************************************************************************* + ** \brief Provides the message digest result. + ** + ** \param [out] pu8MsgDigest Pointer to the message digest. + ** + ** \retval None + ** + ******************************************************************************/ +static void HASH_GetMsgDigest(uint8_t *pu8MsgDigest) +{ + uint8_t i; + uint8_t j; + uint32_t u32Temp; + __IO uint32_t *io32HashHr = &(M4_HASH->HR7); + + for (i = 0u; i < 8u; i++) + { + j = i * 4u + 3u; + u32Temp = *io32HashHr; + + pu8MsgDigest[j] = (uint8_t)u32Temp; + pu8MsgDigest[j-1u] = (uint8_t)(u32Temp >> 8u); + pu8MsgDigest[j-2u] = (uint8_t)(u32Temp >> 16u); + pu8MsgDigest[j-3u] = (uint8_t)(u32Temp >> 24u); + + io32HashHr++; + } +} + +//@} // HashGroup + +#endif /* DDL_HASH_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_i2c.c b/driver/src/hc32f460_i2c.c new file mode 100644 index 0000000..f5b4fdd --- /dev/null +++ b/driver/src/hc32f460_i2c.c @@ -0,0 +1,1318 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2c.c + ** + ** A detailed description is available at + ** @link I2cGroup Inter-Integrated Circuit(I2C) description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of I2C. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_i2c.h" +#include "hc32f460_utility.h" + +#if (DDL_I2C_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup I2cGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Config I2C peripheral */ +#define I2C_SRC_CLK (SystemCoreClock >> M4_SYSREG->CMU_SCFGR_f.PCLK3S) +#define I2C_ANA_FILTER_VALID (1U) +#define I2C_CLK_TIMEOUT_VALID (1U) + +#define I2C_BAUDRATE_MAX (400000ul) + +/*! Parameter validity check for unit. */ +#define IS_VALID_UNIT(x) \ +( ((x) == M4_I2C1) || \ + ((x) == M4_I2C2) || \ + ((x) == M4_I2C3)) + +/*! Parameter check for I2C baudrate value !*/ +#define IS_VALID_SPEED(speed) ((speed) <= (I2C_BAUDRATE_MAX)) + +/*! Parameter check for I2C baudrate calculate prccess !*/ +#define IS_VALID_FDIV(x) \ +( ((x) == I2C_CLK_DIV1) || \ + ((x) == I2C_CLK_DIV2) || \ + ((x) == I2C_CLK_DIV4) || \ + ((x) == I2C_CLK_DIV8) || \ + ((x) == I2C_CLK_DIV16) || \ + ((x) == I2C_CLK_DIV32) || \ + ((x) == I2C_CLK_DIV64) || \ + ((x) == I2C_CLK_DIV128)) + +#define IS_VALID_BAUDWIDTH(result) ((result) == true) + +/*! Parameter check for Digital filter config !*/ +#define IS_VALID_DIGITAL_FILTER(x) \ +( ((x) == Filter1BaseCycle) || \ + ((x) == Filter2BaseCycle) || \ + ((x) == Filter3BaseCycle) || \ + ((x) == Filter4BaseCycle)) + +/*! Parameter check for address mode !*/ +#define IS_VALID_ADRMODE(x) \ +( ((x) == Adr7bit) || \ + ((x) == Adr10bit)) + +/*! Parameter check for I2C transfer direction !*/ +#define IS_VALID_TRANS_DIR(x) \ +( ((x) == I2CDirReceive) || \ + ((x) == I2CDirTrans)) + +/*! Parameter check for Time out control switch !*/ +#define IS_VALID_TIMOUT_SWITCH(x) \ +( ((x) == TimeoutFunOff) || \ + ((x) == LowTimerOutOn) || \ + ((x) == HighTimeOutOn) || \ + ((x) == BothTimeOutOn)) + +/*! Parameter check for I2C 7 bit address range !*/ +#define IS_VALID_7BIT_ADR(x) ((x) <= 0x7F) + +/*! Parameter check for I2C 10 bit address range !*/ +#define IS_VALID_10BIT_ADR(x) ((x) <= 0x3FF) + +/*! Parameter check for readable I2C status bit !*/ +#define IS_VALID_RD_STATUS_BIT(x) \ +( ((x) == I2C_SR_STARTF) || \ + ((x) == I2C_SR_SLADDR0F) || \ + ((x) == I2C_SR_SLADDR1F) || \ + ((x) == I2C_SR_TENDF) || \ + ((x) == I2C_SR_STOPF) || \ + ((x) == I2C_SR_RFULLF) || \ + ((x) == I2C_SR_TEMPTYF) || \ + ((x) == I2C_SR_ARLOF) || \ + ((x) == I2C_SR_ACKRF) || \ + ((x) == I2C_SR_NACKF) || \ + ((x) == I2C_SR_TMOUTF) || \ + ((x) == I2C_SR_MSL) || \ + ((x) == I2C_SR_BUSY) || \ + ((x) == I2C_SR_TRA) || \ + ((x) == I2C_SR_GENCALLF) || \ + ((x) == I2C_SR_SMBDEFAULTF) || \ + ((x) == I2C_SR_SMBHOSTF) || \ + ((x) == I2C_SR_SMBALRTF)) + +#define IS_VALID_ACK_CONFIG(x) \ +( ((x) == I2c_ACK) || \ + ((x) == I2c_NACK)) + +#define I2C_SCL_HIGHT_LOW_LVL_SUM_MAX ((float32_t)0x1F * (float32_t)2) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Try to wait a status of specified flags + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Flag specifies the flag to check, + ** This parameter can be one of the following values: + ** I2C_SR_STARTF + ** I2C_SR_SLADDR0F + ** I2C_SR_SLADDR1F + ** I2C_SR_TENDF + ** I2C_SR_STOPF + ** I2C_SR_RFULLF + ** I2C_SR_TEMPTYF + ** I2C_SR_ARLOF + ** I2C_SR_ACKRF: ACK status + ** I2C_SR_NACKF: NACK Flag + ** I2C_SR_TMOUTF + ** I2C_SR_MSL + ** I2C_SR_BUSY + ** I2C_SR_TRA + ** I2C_SR_GENCALLF + ** I2C_SR_SMBDEFAULTF + ** I2C_SR_SMBHOSTF + ** I2C_SR_SMBALRTF + ** \param [in] enStatus Expected status, This parameter can be one of + ** the following values: + ** Set + ** Reset + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Successfully gotten the expected status of the specified flags + ** \retval ErrorTimeout Failed to get expected status of specified flags. + ******************************************************************************/ +en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *pstcI2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorTimeout; + uint32_t u32RegStatusBit; + + for(;;) + { + u32RegStatusBit = (pstcI2Cx->SR & u32Flag); + if(((enStatus == Set) && (u32Flag == u32RegStatusBit)) + || ((enStatus == Reset) && (0UL == u32RegStatusBit))) + { + enRet = Ok; + } + + if((Ok == enRet) || (0UL == u32Timeout)) + { + break; + } + else + { + u32Timeout--; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2C generate start condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState new state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.START = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C generate restart condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateReStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.RESTART = enNewState; + +} + +/** + ******************************************************************************* + ** \brief I2C generate stop condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateStop(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.STOP = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the baudrate for I2C peripheral. + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + ** 1. pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + ** step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + ** I2cSrcClk -- I2c source clock + ** Baudrate -- baudrate of i2c + ** SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + ** according to i2c bus hardware parameter. + ** dnfsum -- 0 if digital filter off; + ** Filter capacity if digital filter on(1 ~ 4) + ** step2: chose a division item which is similar and bigger than div + ** from @ref I2C_Clock_Division. + ** 2. pstcI2cInit->u32Baudrate : Baudrate configuration + ** 3. pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + ** time, should be number of T(i2c clock period time) + ** @param [out] pf32Error Baudrate error + ** @retval en_result_t Enumeration value: + ** @arg Ok: Configurate success + ** @arg ErrorInvalidParameter: Invalid parameter + ******************************************************************************/ +en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error) +{ + en_result_t enRet = Ok; + uint32_t I2cSrcClk; + uint32_t I2cDivClk; + uint32_t SclCnt; + uint32_t Baudrate; + uint32_t dnfsum = 0UL; + uint32_t divsum = 2UL; + uint32_t TheoryBaudrate; + float32_t WidthTotal; + float32_t SumTotal; + float32_t WidthHL; + float32_t fErr = 0.0F; + + if ((NULL == pstcI2cInit) || (NULL == pf32Error)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_VALID_FDIV(pstcI2cInit->u32ClockDiv)); + + /* Get configuration for i2c */ + I2cSrcClk = I2C_SRC_CLK; + I2cDivClk = 1ul << pstcI2cInit->u32ClockDiv; + SclCnt = pstcI2cInit->u32SclTime; + Baudrate = pstcI2cInit->u32Baudrate; + + /* Judge digital filter status */ + if(1u == pstcI2Cx->FLTR_f.DNFEN) + { + dnfsum = pstcI2Cx->FLTR_f.DNF+1ul; + } + + /* Judge if clock divider on*/ + if(I2C_CLK_DIV1 == pstcI2cInit->u32ClockDiv) + { + divsum = 3ul; + } + + WidthTotal = (float32_t)I2cSrcClk / (float32_t)Baudrate / (float32_t)I2cDivClk; + SumTotal = (2.0F*(float32_t)divsum) + (2.0F*(float32_t)dnfsum) + (float32_t)SclCnt; + WidthHL = WidthTotal - SumTotal; + + /* Integer for WidthTotal, rounding off */ + if ((WidthTotal - (float32_t)((uint32_t)WidthTotal)) >= 0.5F) + { + WidthTotal = (float32_t)((uint32_t)WidthTotal) + 1.0F; + } + else + { + WidthTotal = (float32_t)((uint32_t)WidthTotal); + } + + if(WidthTotal <= SumTotal) + { + /* Err, Should set a smaller division value for pstcI2cInit->u32ClockDiv */ + enRet = ErrorInvalidParameter; + } + else + { + if(WidthHL > I2C_SCL_HIGHT_LOW_LVL_SUM_MAX) + { + /* Err, Should set a bigger division value for pstcI2cInit->u32ClockDiv */ + enRet = ErrorInvalidParameter; + } + else + { + TheoryBaudrate = I2cSrcClk / (uint32_t)WidthTotal / I2cDivClk; + fErr = ((float32_t)Baudrate - (float32_t)TheoryBaudrate) / (float32_t)TheoryBaudrate; + + /* Write register */ + pstcI2Cx->CCR_f.FREQ = pstcI2cInit->u32ClockDiv; + pstcI2Cx->CCR_f.SLOWW = (uint32_t)WidthHL/2u; + pstcI2Cx->CCR_f.SHIGHW = (uint32_t)WidthHL - ((uint32_t)WidthHL)/2u; + } + } + } + + if((NULL != pf32Error) && (Ok == enRet)) + { + *pf32Error = fErr; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize I2C unit + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \retval Ok Process finished. + ******************************************************************************/ +en_result_t I2C_DeInit(M4_I2C_TypeDef* pstcI2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Reset peripheral register and internal status*/ + pstcI2Cx->CR1_f.PE = 0u; + pstcI2Cx->CR1_f.SWRST = 1u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Initialize I2C peripheral according to the structure + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + ** 1. pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + ** step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + ** I2cSrcClk -- I2c source clock + ** Baudrate -- baudrate of i2c + ** SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + ** according to i2c bus hardware parameter. + ** dnfsum -- 0 if digital filter off; + ** Filter capacity if digital filter on(1 ~ 4) + ** step2: chose a division item which is similar and bigger than div + ** from @ref I2C_Clock_Division. + ** 2. pstcI2cInit->u32Baudrate : Baudrate configuration + ** 3. pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + ** time, should be number of T(i2c clock period time) + ** @param [out] pf32Error Baudrate error + ** @retval en_result_t Enumeration value: + ** @arg Ok: Configurate success + ** @arg ErrorInvalidParameter: Invalid parameter + ******************************************************************************/ +en_result_t I2C_Init(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error) +{ + en_result_t enRes = Ok; + if((NULL == pstcI2cInit) || (NULL == pstcI2Cx)) + { + enRes = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_VALID_FDIV(pstcI2cInit->u32ClockDiv)); + + /* Register and internal status reset */ + pstcI2Cx->CR1_f.PE = 0u; + pstcI2Cx->CR1_f.SWRST = 1u; + + pstcI2Cx->CR1_f.PE = 1u; + + enRes = I2C_BaudrateConfig(pstcI2Cx, pstcI2cInit, pf32Error); + + pstcI2Cx->CR1_f.ENGC = 0u; + pstcI2Cx->CR1_f.SWRST = 0u; + pstcI2Cx->CR1_f.PE = 0u; + } + return enRes; +} + +/** + ******************************************************************************* + ** \brief I2C slave address0 config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \param [in] enAdrMode Address mode,can be Adr7bit or Adr10bit + ** \param [in] u32Adr The slave address + ** \retval None + ******************************************************************************/ +void I2C_SlaveAdr0Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_ADRMODE(enAdrMode)); + + pstcI2Cx->SLR0_f.SLADDR0EN = enNewState; + pstcI2Cx->SLR0_f.ADDRMOD0 = enAdrMode; + if(Adr7bit == enAdrMode) + { + DDL_ASSERT(IS_VALID_7BIT_ADR(u32Adr)); + pstcI2Cx->SLR0_f.SLADDR0 = u32Adr << 1ul; + } + else + { + DDL_ASSERT(IS_VALID_10BIT_ADR(u32Adr)); + pstcI2Cx->SLR0_f.SLADDR0 = u32Adr; + } +} + +/** + ******************************************************************************* + ** \brief I2C slave address1 config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \param [in] enAdrMode Address mode,can be Adr7bit or Adr10bit + ** \param [in] u32Adr The slave address + ** \retval None + ******************************************************************************/ +void I2C_SlaveAdr1Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_ADRMODE(enAdrMode)); + + pstcI2Cx->SLR1_f.SLADDR1EN = enNewState; + pstcI2Cx->SLR1_f.ADDRMOD1 = enAdrMode; + if(Adr7bit == enAdrMode) + { + DDL_ASSERT(IS_VALID_7BIT_ADR(u32Adr)); + pstcI2Cx->SLR1_f.SLADDR1 = u32Adr << 1ul; + } + else + { + DDL_ASSERT(IS_VALID_10BIT_ADR(u32Adr)); + pstcI2Cx->SLR1_f.SLADDR1 = u32Adr; + } +} + +/** + ******************************************************************************* + ** \brief I2C function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_Cmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.PE = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C fast ACK function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the fast ACK function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_FastAckCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + pstcI2Cx->CR3_f.FACKEN = 0ul; + } + else + { + pstcI2Cx->CR3_f.FACKEN = 1ul; + } +} + +/** + ******************************************************************************* + ** \brief I2C bus wait function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the fast ACK function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_BusWaitCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + uint32_t u32CR4_Reg = ((uint32_t)&pstcI2Cx->CR3) + 4ul; + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + *(__IO uint32_t *)u32CR4_Reg |= (1ul << 10ul); + } + else + { + *(__IO uint32_t *)u32CR4_Reg &= ~(1ul << 10ul); + } +} + +/** + ******************************************************************************* + ** \brief I2C SMBUS function configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2C_SmbusInitStruct + ** Pointer to I2C SMBUS configuration structure + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ******************************************************************************/ +en_result_t I2C_SmbusConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_smbus_init_t* pstcI2C_SmbusInitStruct) +{ + en_result_t enRet = Ok; + if(NULL != pstcI2C_SmbusInitStruct) + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enHostAdrMatchFunc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enDefaultAdrMatchFunc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enAlarmAdrMatchFunc)); + + pstcI2Cx->CR1_f.SMBHOSTEN = pstcI2C_SmbusInitStruct->enHostAdrMatchFunc; + pstcI2Cx->CR1_f.SMBDEFAULTEN = pstcI2C_SmbusInitStruct->enDefaultAdrMatchFunc; + pstcI2Cx->CR1_f.SMBALRTEN = pstcI2C_SmbusInitStruct->enAlarmAdrMatchFunc; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2C SMBUS function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_SmBusCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.SMBUS = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C digital filter function configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enDigiFilterMode Chose the digital filter mode, This parameter + ** can be one of the following values: + ** Filter1BaseCycle + ** Filter2BaseCycle + ** Filter3BaseCycle + ** Filter4BaseCycle + ** \retval None + ******************************************************************************/ +void I2C_DigitalFilterConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_digital_filter_mode_t enDigiFilterMode) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_DIGITAL_FILTER(enDigiFilterMode)); + + pstcI2Cx->FLTR_f.DNF = enDigiFilterMode; +} + +/** + ******************************************************************************* + ** \brief I2C digital filter function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_DigitalFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->FLTR_f.DNFEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C analog filter function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_AnalogFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->FLTR_f.ANFEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C general call function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GeneralCallCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.ENGC = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C status bit get + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32StatusBit specifies the flag to check, + ** This parameter can be one of the following values: + ** I2C_SR_STARTF + ** I2C_SR_SLADDR0F + ** I2C_SR_SLADDR1F + ** I2C_SR_TENDF + ** I2C_SR_STOPF + ** I2C_SR_RFULLF + ** I2C_SR_TEMPTYF + ** I2C_SR_ARLOF + ** I2C_SR_ACKRF: ACK status + ** I2C_SR_NACKF: NACK Flag + ** I2C_SR_TMOUTF + ** I2C_SR_MSL + ** I2C_SR_BUSY + ** I2C_SR_TRA + ** I2C_SR_GENCALLF + ** I2C_SR_SMBDEFAULTF + ** I2C_SR_SMBHOSTF + ** I2C_SR_SMBALRTF + ** \retval en_flag_status_t The status of the I2C status flag, may be Set or Reset. + ******************************************************************************/ +en_flag_status_t I2C_GetStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit) +{ + en_flag_status_t enRet = Reset; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_RD_STATUS_BIT(u32StatusBit)); + + if(0ul != (pstcI2Cx->SR & u32StatusBit)) + { + enRet = Set; + } + else + { + enRet = Reset; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear I2C status flag + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32StatusBit specifies the flag to clear, + ** This parameter can be any combination of the following values: + ** I2C_CLR_STARTFCLR + ** I2C_CLR_SLADDR0FCLR + ** I2C_CLR_SLADDR1FCLR + ** I2C_CLR_TENDFCLR + ** I2C_CLR_STOPFCLR + ** I2C_CLR_RFULLFCLR + ** I2C_CLR_TEMPTYFCLR + ** I2C_CLR_ARLOFCLR + ** I2C_CLR_NACKFCLR + ** I2C_CLR_TMOUTFCLR + ** I2C_CLR_GENCALLFCLR + ** I2C_CLR_SMBDEFAULTFCLR + ** I2C_CLR_SMBHOSTFCLR + ** I2C_CLR_SMBALRTFCLR + ** \retval None + ******************************************************************************/ +void I2C_ClearStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + pstcI2Cx->CLR |= (u32StatusBit & I2C_CLR_MASK); +} + +/** + ******************************************************************************* + ** \brief I2C software reset function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_SoftwareResetCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.SWRST = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C interrupt function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32IntEn Specifies the I2C interrupts sources to be configuration + ** This parameter can be any combination of the following values: + ** I2C_CR2_STARTIE + ** I2C_CR2_SLADDR0EN + ** I2C_CR2_SLADDR1EN + ** I2C_CR2_TENDIE + ** I2C_CR2_STOPIE + ** I2C_CR2_RFULLIE + ** I2C_CR2_TEMPTYIE + ** I2C_CR2_ARLOIE + ** I2C_CR2_NACKIE + ** I2C_CR2_TMOURIE + ** I2C_CR2_GENCALLIE + ** I2C_CR2_SMBDEFAULTIE + ** I2C_CR2_SMBHOSTIE + ** I2C_CR2_SMBALRTIE + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_IntCmd(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32IntEn, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + pstcI2Cx->CR2 |= u32IntEn; + } + else + { + pstcI2Cx->CR2 &= ~u32IntEn; + } +} + +/** + ******************************************************************************* + ** \brief I2C write data register + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u8Data The data to be send + ** \retval None + ******************************************************************************/ +void I2C_WriteData(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Data) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + pstcI2Cx->DTR = u8Data; +} + +/** + ******************************************************************************* + ** \brief I2C read data register + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \retval uint8_t The value of the received data + ******************************************************************************/ +uint8_t I2C_ReadData(M4_I2C_TypeDef* pstcI2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + return pstcI2Cx->DRR; +} + +/** + ******************************************************************************* + ** \brief I2C ACK status configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32AckConfig I2C ACK configurate. + ** I2c_ACK: Send ACK after date received. + ** I2c_NACK: Send NACK after date received. + ** \retval None + ******************************************************************************/ +void I2C_AckConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_ack_config_t u32AckConfig) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_ACK_CONFIG(u32AckConfig)); + + pstcI2Cx->CR1_f.ACK = u32AckConfig; +} + +/** + ******************************************************************************* + ** \brief I2C clock timer out function config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcTimoutInit Pointer to I2C timeout function structure + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ******************************************************************************/ +en_result_t I2C_ClkTimeOutConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_clock_timeout_init_t* pstcTimoutInit) +{ + en_result_t enRet = Ok; + if(NULL != pstcTimoutInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_TIMOUT_SWITCH(pstcTimoutInit->enClkTimeOutSwitch)); + + pstcI2Cx->SLTR_f.TOUTHIGH = pstcTimoutInit->u16TimeOutHigh; + pstcI2Cx->SLTR_f.TOUTLOW = pstcTimoutInit->u16TimeOutLow; + + pstcI2Cx->CR3 &= ~0x00000007ul; + pstcI2Cx->CR3 |= pstcTimoutInit->enClkTimeOutSwitch; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx start + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Start success + ** \retval ErrorTimeout Start time out + ******************************************************************************/ +en_result_t I2C_Start(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_BUSY, Reset, u32Timeout); + + if(Ok == enRet) + { + /* generate start signal */ + I2C_GenerateStart(pstcI2Cx, Enable); + /* Judge if start success*/ + enRet = I2C_WaitStatus(pstcI2Cx, (I2C_SR_BUSY | I2C_SR_STARTF), Set, u32Timeout); + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx restart + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Restart successfully + ** \retval ErrorTimeout Restart time out + ******************************************************************************/ +en_result_t I2C_Restart(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Clear start status flag */ + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STARTFCLR); + /* Send restart condition */ + I2C_GenerateReStart(pstcI2Cx, Enable); + /* Judge if start success*/ + enRet = I2C_WaitStatus(pstcI2Cx, (I2C_SR_BUSY | I2C_SR_STARTF), Set, u32Timeout); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send address + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u8Addr The address to be sent + ** \param [in] enDir Can be I2CDirTrans or I2CDirReceive + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval Error: Send suscessfully and receive NACK + ** \retval ErrorTimeout: Send address time out + ******************************************************************************/ +en_result_t I2C_TransAddr(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Addr, en_trans_direction_t enDir, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_7BIT_ADR(u8Addr)); + DDL_ASSERT(IS_VALID_TRANS_DIR(enDir)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + + if(Ok == enRet) + { + /* Send I2C address */ + I2C_WriteData(pstcI2Cx, (u8Addr << 1u) | (uint8_t)enDir); + + if(I2CDirTrans == enDir) + { + /* If in master transfer process, Need wait transfer end */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + } + else + { + /* If in master receive process, Need wait TRA flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TRA, Reset, u32Timeout); + } + + if(enRet == Ok) + { + /* If receive NACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) == Set) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send address 10 bit + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u16Addr The address to be sent + ** \param [in] enDir Can be I2CDirTrans or I2CDirReceive + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval Error: Send suscessfully and receive NACK + ** \retval ErrorTimeout: Send address time out + ******************************************************************************/ +en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* pstcI2Cx, uint16_t u16Addr, en_trans_direction_t enDir, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_10BIT_ADR(u16Addr)); + DDL_ASSERT(IS_VALID_TRANS_DIR(enDir)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + if(Ok == enRet) + { + /* Write 11110 + SLA(bit9:8) + W#(1bit) */ + I2C_WriteData(pstcI2Cx, (uint8_t)((u16Addr>>7u) & 0x06u) | 0xF0u | (uint8_t)I2CDirTrans); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + if(Ok == enRet) + { + /* If receive ACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) == Reset) + { + /* Write SLA(bit7:0)*/ + I2C_WriteData(pstcI2Cx, (uint8_t)(u16Addr & 0xFFu)); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + if(Ok == enRet) + { + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) != Reset) + { + enRet = Error; + } + } + } + else + { + enRet = Error; + } + } + } + + if((I2CDirReceive == enDir) && (Ok == enRet)) + { + /* Restart */ + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STARTFCLR); + I2C_GenerateReStart(pstcI2Cx, Enable); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STARTF, Set, u32Timeout); + + if(Ok == enRet) + { + /* Write 11110 + SLA(bit9:8) + R(1bit) */ + I2C_WriteData(pstcI2Cx, (uint8_t)((u16Addr>>7u) & 0x06u) | 0xF0u | (uint8_t)I2CDirReceive); + /* If in master receive process, Need wait TRA flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TRA, Reset, u32Timeout); + + if(Ok == enRet) + { + /* If receive NACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) != Reset) + { + enRet = Error; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send data + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] au8TxData The data array to be sent + ** \param [in] u32Size Number of data in array pau8TxData + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval ErrorTimeout: Send data time out + ** \retval ErrorInvalidParameter: au8TxData is NULL + ******************************************************************************/ +en_result_t I2C_TransData(M4_I2C_TypeDef* pstcI2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + en_result_t enRet = Ok; + __IO uint32_t u32Cnt = 0ul; + + if(au8TxData != NULL) + { + while((u32Cnt != u32Size) && (enRet == Ok)) + { + /* Wait tx buffer empty */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + + if(enRet == Ok) + { + /* Send one byte data */ + I2C_WriteData(pstcI2Cx, au8TxData[u32Cnt]); + + /* Wait transfer end */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + /* If receive NACK in slave tx mode */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_NACKF) == Set) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_NACKFCLR); + /* Exit data transfer */ + break; + } + + u32Cnt++; + } + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx receive data + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [out] au8RxData Array to hold the received data + ** \param [in] u32Size Number of data to be received + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ** \retval ErrorInvalidParameter: au8RxData is NULL + ******************************************************************************/ +en_result_t I2C_ReceiveData(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + if(au8RxData != NULL) + { + uint32_t u32FastAckDis = (pstcI2Cx->CR3_f.FACKEN); + for(uint32_t i=0ul; i= 2ul) && (i == (u32Size - 2ul))) + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + else + { + if(i != (u32Size - 1ul)) + { + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + + if(enRet == Ok) + { + /* read data from register */ + au8RxData[i] = I2C_ReadData(pstcI2Cx); + } + else + { + break; + } + } + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx master receive data and stop + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [out] au8RxData Array to hold the received data + ** \param [in] u32Size Number of data to be received + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ** \retval ErrorInvalidParameter: au8RxData is NULL + ******************************************************************************/ +en_result_t I2C_MasterDataReceiveAndStop(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + if(au8RxData != NULL) + { + uint32_t u32FastAckDis = (pstcI2Cx->CR3_f.FACKEN); + for(uint32_t i=0ul; i= 2ul) && (i == (u32Size - 2ul))) + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + else + { + if(i != (u32Size - 1ul)) + { + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + + if(enRet == Ok) + { + /* Stop before read last data */ + if(i == (u32Size - 1ul)) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STOPFCLR); + I2C_GenerateStop(pstcI2Cx, Enable); + } + + /* read data from register */ + au8RxData[i] = I2C_ReadData(pstcI2Cx); + + /* Wait stop flag after DRR read */ + if(i == (u32Size - 1ul)) + { + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STOPF, Set, u32Timeout); + } + } + else + { + break; + } + } + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx stop + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ******************************************************************************/ +en_result_t I2C_Stop(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Clear stop flag */ + while((Set == I2C_GetStatus(pstcI2Cx, I2C_SR_STOPF)) && (u32Timeout > 0ul)) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STOPFCLR); + u32Timeout--; + } + I2C_GenerateStop(pstcI2Cx, Enable); + /* Wait stop flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STOPF, Set, u32Timeout); + + return enRet; +} + +//@} // I2cGroup + +#endif /* DDL_I2C_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_i2s.c b/driver/src/hc32f460_i2s.c new file mode 100644 index 0000000..ab18d3a --- /dev/null +++ b/driver/src/hc32f460_i2s.c @@ -0,0 +1,437 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2s.c + ** + ** A detailed description is available at + ** @link I2sGroup Inter-IC Sound Bus description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of I2S. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_i2s.h" +#include "hc32f460_utility.h" + +#if (DDL_I2S_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup I2sGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for I2S register pointer */ +#define IS_VALID_I2S_REG(x) \ +( (M4_I2S1 == (x)) || \ + (M4_I2S2 == (x)) || \ + (M4_I2S3 == (x)) || \ + (M4_I2S4 == (x))) + +/*!< Parameter valid check for I2S function */ +#define IS_VALID_I2S_FUNCTION(x) \ +( (TxEn == (x)) || \ + (TxIntEn == (x)) || \ + (RxEn == (x)) || \ + (RxIntEn == (x)) || \ + (ErrIntEn == (x))) + +/*!< Parameter valid check for I2S status bits */ +#define IS_VALID_I2S_STATUS(x) \ +( (TxBufAlarmFlag == (x)) || \ + (RxBufAlarmFlag == (x)) || \ + (TxBufEmptFlag == (x)) || \ + (TxBufFullFlag == (x)) || \ + (RxBufEmptFlag == (x)) || \ + (RxBufFullFlag == (x))) + +/*!< Parameter valid check for I2S error flag */ +#define IS_VALID_I2S_ERR_FLAG(x) \ +( (ClrTxErrFlag == (x)) || \ + (ClrRxErrFlag == (x))) + +/*!< Parameter valid check for I2S mode */ +#define IS_VALID_I2S_MODE(x) \ +( (I2sMaster == (x)) || \ + (I2sSlave == (x))) + +/*!< Parameter valid check for I2S full duplex mode */ +#define IS_VALID_I2S_DUPLEX_MODE(x) \ +( (I2s_HalfDuplex == (x)) || \ + (I2s_FullDuplex == (x))) + +/*!< Parameter valid check for I2S standard */ +#define IS_VALID_I2S_STANDARD(x) \ +( (Std_Philips == (x)) || \ + (Std_MSBJust == (x)) || \ + (Std_LSBJust == (x)) || \ + (Std_PCM == (x))) + +/*!< Parameter valid check for I2S data length */ +#define IS_VALID_I2S_DATA_LEN(x) \ +( (I2s_DataLen_16Bit == (x)) || \ + (I2s_DataLen_24Bit == (x)) || \ + (I2s_DataLen_32Bit == (x))) + +/*!< Parameter valid check for I2S channel data length */ +#define IS_VALID_I2S_CHANNEL_LEN(x) \ +( (I2s_ChLen_16Bit == (x)) || \ + (I2s_ChLen_32Bit == (x))) + +/*!< Parameter valid check for I2S MCK output config */ +#define IS_VALID_I2S_MCKOUT(x) \ +( (Disable == (x)) || \ + (Enable == (x))) + +/*!< Parameter valid check for I2S EXCK config */ +#define IS_VALID_I2S_EXCK(x) \ +( (Disable == (x)) || \ + (Enable == (x))) + +/*!< Parameter valid check for I2S audio frequecy */ +#define IS_I2S_AUDIO_FREQ(FREQ) \ +( (((FREQ) >= I2S_AudioFreq_8k) && ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) + +/*! I2S registers reset value */ +#define I2S_REG_CTRL_RESET_VALUE (0x00002200ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief I2S function command + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enFunc I2S function + ** \arg Refer @ref en_i2s_func_t + ** \param [in] enNewState New status + ** \arg Refer @ref en_functional_state_t + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_FuncCmd(M4_I2S_TypeDef* pstcI2sReg, en_i2s_func_t enFunc, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_FUNCTION(enFunc)); + + if(Enable == enNewState) + { + if(0ul == (pstcI2sReg->CTRL & (1ul << enFunc))) + { + pstcI2sReg->CTRL |= (1ul << enFunc); + } + } + else + { + if(0ul != (pstcI2sReg->CTRL & (1ul << enFunc))) + { + pstcI2sReg->CTRL &= ~(1ul << (uint8_t)enFunc); + } + } +} + +/** + ******************************************************************************* + ** \brief Get I2S status bit + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enStd I2S status bit + ** \arg Refer @ref en_i2s_std_t + ** + ** \retval Set flag is set + ** \retval Reset flag is reset + ** + ******************************************************************************/ +en_flag_status_t I2S_GetStatus(M4_I2S_TypeDef* pstcI2sReg, en_i2s_std_t enStd) +{ + en_flag_status_t enRet = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_STATUS(enStd)); + + if (0ul != ((uint32_t)(pstcI2sReg->SR & (1ul << (uint8_t)enStd)))) + { + enRet = Set; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear I2S error flag + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enErrFlag I2S Error flag + ** \arg Refer @ref en_i2s_err_flag_t + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_ClrErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_ERR_FLAG(enErrFlag)); + + pstcI2sReg->ER |= (1ul << (uint8_t)enErrFlag); +} + +/** + ******************************************************************************* + ** \brief Get I2S error flag + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enErrFlag I2S Error flag + ** \arg Refer @ref en_i2s_err_flag_t + ** + ** \retval Set flag is set + ** \retval Reset flag is reset + ** + ******************************************************************************/ +en_flag_status_t I2S_GetErrFlag(M4_I2S_TypeDef* pstcI2sReg, + en_i2s_err_flag_t enErrFlag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_ERR_FLAG(enErrFlag)); + + return (en_flag_status_t)((uint32_t)(pstcI2sReg->ER | (1ul << (uint8_t)enErrFlag))); +} + +/** + ******************************************************************************* + ** \brief Write data to I2s data send register + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] u32Data Data to be send + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_SendData(M4_I2S_TypeDef* pstcI2sReg, uint32_t u32Data) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + pstcI2sReg->TXBUF = u32Data; +} + +/** + ******************************************************************************* + ** \brief Read data from I2s data receive register + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** + ** \retval uint32_t The data read out + ** + ******************************************************************************/ +uint32_t I2S_RevData(const M4_I2S_TypeDef* pstcI2sReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + return pstcI2sReg->RXBUF; +} + +/** + ******************************************************************************* + ** \brief Initialize I2S module + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** \param [in] pstcI2sCfg Pointer to I2S configuration structure + ** + ** \retval Ok Initialize successfully done + ** + ******************************************************************************/ +en_result_t I2s_Init(M4_I2S_TypeDef* pstcI2sReg, const stc_i2s_config_t* pstcI2sCfg) +{ + uint32_t i2sclk = 0ul, tmp=0ul; + uint8_t u8ChanelDataBit,u8ChanMul; + uint16_t i2sdiv, i2sodd; + stc_i2s_cfgr_field_t stcCFGR_Tmp = {0}; + stc_i2s_ctrl_field_t stcCTRL_Tmp = {0}; + en_result_t enRes = Ok; + uint32_t u32AdrTmp = 0ul; + + if((NULL == pstcI2sReg)||(NULL == pstcI2sCfg)) + { + enRes = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_MODE(pstcI2sCfg->enMode)); + DDL_ASSERT(IS_VALID_I2S_DUPLEX_MODE(pstcI2sCfg->enFullDuplexMode)); + DDL_ASSERT(IS_VALID_I2S_STANDARD(pstcI2sCfg->enStandrad)); + DDL_ASSERT(IS_VALID_I2S_DATA_LEN(pstcI2sCfg->enDataBits)); + DDL_ASSERT(IS_VALID_I2S_CHANNEL_LEN(pstcI2sCfg->enChanelLen)); + DDL_ASSERT(IS_VALID_I2S_MCKOUT(pstcI2sCfg->enMcoOutEn)); + DDL_ASSERT(IS_VALID_I2S_EXCK(pstcI2sCfg->enExckEn)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(pstcI2sCfg->u32AudioFreq)); + + /* Set config register to default value*/ + pstcI2sReg->CTRL = I2S_REG_CTRL_RESET_VALUE; + /* Clear status register*/ + pstcI2sReg->ER_f.TXERR = 1ul; + pstcI2sReg->ER_f.RXERR = 1ul; + + //*(uint32_t*)&stcCTRL_Tmp = pstcI2sReg->CTRL; + u32AdrTmp = (uint32_t)&stcCTRL_Tmp; + *(uint32_t*)u32AdrTmp = pstcI2sReg->CTRL; + + /* ---- config I2s clock source---- */ + if(Enable == pstcI2sCfg->enExckEn) + { + /* Set external clock as I2S clock source */ + stcCTRL_Tmp.CLKSEL = 1ul; + stcCTRL_Tmp.I2SPLLSEL = 0ul; + /* Set the I2S clock to the external clock value */ + i2sclk = I2S_EXTERNAL_CLOCK_VAL; + } + else + { + /* Set internal clock as I2S clock source */ + stcCTRL_Tmp.CLKSEL = 0ul; + stcCTRL_Tmp.I2SPLLSEL = 1ul; + /* Get i2s clock internal frequency */ + i2sclk = pstcI2sCfg->u32I2sInterClkFreq; + } + /* config audio sampple rate */ + if(I2s_ChLen_16Bit == pstcI2sCfg->enChanelLen) + { + u8ChanelDataBit = 16u; + u8ChanMul = 8u; + } + else + { + u8ChanelDataBit = 32u; + u8ChanMul = 4u; + } + + /*config I2S clock*/ + if(true == pstcI2sCfg->enMcoOutEn) + { + /* MCLK output is enabled */ + tmp = i2sclk/(pstcI2sCfg->u32AudioFreq * u8ChanelDataBit * 2ul * u8ChanMul); + } + else + { + /* MCLK output is disabled */ + tmp = i2sclk/(pstcI2sCfg->u32AudioFreq * u8ChanelDataBit * 2ul); + } + i2sodd = (uint16_t)(tmp & 0x0001ul); + i2sdiv = (uint16_t)((tmp - (uint32_t)i2sodd) / 2ul); + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2u) || (i2sdiv > 0xFFu)) + { + /* Set the default values */ + i2sdiv = 2u; + i2sodd = 0u; + } + + /* Write I2SPR register */ + pstcI2sReg->PR_f.I2SDIV = (uint8_t)i2sdiv; + + /* Config and write I2S_CFGR */ + stcCFGR_Tmp.CHLEN = pstcI2sCfg->enChanelLen; + stcCFGR_Tmp.DATLEN = pstcI2sCfg->enDataBits; + stcCFGR_Tmp.I2SSTD = pstcI2sCfg->enStandrad; + stcCFGR_Tmp.PCMSYNC = PCM_SYNC_FRAME; + pstcI2sReg->CFGR_f = stcCFGR_Tmp; + + /* Config CTRL register */ + stcCTRL_Tmp.WMS = pstcI2sCfg->enMode; + stcCTRL_Tmp.DUPLEX = pstcI2sCfg->enFullDuplexMode; + if(I2sMaster == pstcI2sCfg->enMode) + { + stcCTRL_Tmp.CKOE = 1u; + stcCTRL_Tmp.LRCKOE = 1u; + } + stcCTRL_Tmp.SDOE = 1u; + stcCTRL_Tmp.MCKOE = pstcI2sCfg->enMcoOutEn; + stcCTRL_Tmp.ODD = (uint8_t)i2sodd; + stcCTRL_Tmp.RXBIRQWL = RXBUF_IRQ_WL; + stcCTRL_Tmp.TXBIRQWL = TXBUF_IRQ_WL; + //pstcI2sReg->CTRL = *(uint32_t*)&stcCTRL_Tmp; + u32AdrTmp = (uint32_t)&stcCTRL_Tmp; + pstcI2sReg->CTRL = *(uint32_t*)u32AdrTmp; + } + return enRes; +} + +/** + ******************************************************************************* + ** \brief De-Initialize I2S module + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t I2s_DeInit(M4_I2S_TypeDef* pstcI2sReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + /* Set config register to default value*/ + pstcI2sReg->CTRL = I2S_REG_CTRL_RESET_VALUE; + /* Clear status register*/ + pstcI2sReg->ER_f.TXERR = 1u; + pstcI2sReg->ER_f.RXERR = 1u; + + return Ok; +} + +//@} // I2sGroup + +#endif /* DDL_I2S_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_icg.c b/driver/src/hc32f460_icg.c new file mode 100644 index 0000000..a3033d0 --- /dev/null +++ b/driver/src/hc32f460_icg.c @@ -0,0 +1,83 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_icg.c + ** + ** A detailed description is available at + ** @link IcgGroup Initialize Configure description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of ICG. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_icg.h" + +#if (DDL_ICG_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup IcgGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +const uint32_t u32ICG[] __attribute__((section(".icg_sec"))) = +#elif defined (__CC_ARM) +const uint32_t u32ICG[] __attribute__((at(0x400))) = +#elif defined (__ICCARM__) +__root const uint32_t u32ICG[] @ 0x400 = +#else +#error "unsupported compiler!!" +#endif +{ + /* ICG 0~ 3 */ + ICG0_REGISTER_CONSTANT, + ICG1_REGISTER_CONSTANT, + ICG2_REGISTER_CONSTANT, + ICG3_REGISTER_CONSTANT, + /* ICG 4~ 7 */ + ICG4_REGISTER_CONSTANT, + ICG5_REGISTER_CONSTANT, + ICG6_REGISTER_CONSTANT, + ICG7_REGISTER_CONSTANT, +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +//@} // IcgGroup + +#endif /* DDL_ICG_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/driver/src/hc32f460_interrupts.c b/driver/src/hc32f460_interrupts.c new file mode 100644 index 0000000..4cd1bbd --- /dev/null +++ b/driver/src/hc32f460_interrupts.c @@ -0,0 +1,3783 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/*****************************************************************************/ +/** \file hc32f460_interrupts.c + ** + ** A detailed description is available at + ** @link InterruptGroup Interrupt description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of interrupt. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_interrupts.h" +#include "hc32f460_utility.h" + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup InterruptGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for null pointer. */ +#define IS_NULL_POINT(x) (NULL != (x)) + +/*! Max IRQ Handler. */ +#define IRQ_NUM_MAX (128u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +func_ptr_t IrqHandler[IRQ_NUM_MAX] = {NULL}; + +/** + ******************************************************************************* + ** \brief IRQ Registration + ** + ** param [in] pstcIrqRegiConf, IRQ registration + ** configure structure + ** + ** retval Ok, IRQ register successfully. + ** ErrorInvalidParameter, IRQ No. and + ** Vector No. are not match. + ** ErrorUninitialized, Make sure the + ** Interrupt select register (INTSEL) is + ** default value (0x1FFu) before setting. + ** + *****************************************************************************/ +en_result_t enIrqRegistration(const stc_irq_regi_conf_t *pstcIrqRegiConf) +{ + // todo, assert ... + stc_intc_sel_field_t *stcIntSel; + en_result_t enRet = Ok; + + //DDL_ASSERT(NULL != pstcIrqRegiConf->pfnCallback); + DDL_ASSERT(IS_NULL_POINT(pstcIrqRegiConf->pfnCallback)); + + /* IRQ032~127 whether out of range */ + if (((((pstcIrqRegiConf->enIntSrc/32)*6 + 32) > pstcIrqRegiConf->enIRQn) || \ + (((pstcIrqRegiConf->enIntSrc/32)*6 + 37) < pstcIrqRegiConf->enIRQn)) && \ + (pstcIrqRegiConf->enIRQn >= 32)) + { + enRet = ErrorInvalidParameter; + } + else + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + \ + (4u * pstcIrqRegiConf->enIRQn)); + if (0x1FFu == stcIntSel->INTSEL) + { + stcIntSel->INTSEL = pstcIrqRegiConf->enIntSrc; + IrqHandler[pstcIrqRegiConf->enIRQn] = pstcIrqRegiConf->pfnCallback; + } + else + { + enRet = ErrorUninitialized; + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief IRQ Resign + ** + ** param [in] enIRQn, IRQ enumunation (Int000_IRQn ~ + ** Int127_IRQn + ** + ** retval Ok, IRQ resign sucessfully. + ** ErrorInvalidParameter, IRQ No. is out + ** of range + ** + *****************************************************************************/ +en_result_t enIrqResign(IRQn_Type enIRQn) +{ + stc_intc_sel_field_t *stcIntSel; + en_result_t enRet = Ok; + + if ((enIRQn < Int000_IRQn) || (enIRQn > Int127_IRQn)) + { + enRet = ErrorInvalidParameter; + } + else + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + (4ul * enIRQn)); + stcIntSel->INTSEL = 0x1FFu; + IrqHandler[enIRQn] = NULL; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Share IRQ handler enable + ** + ** param [in] enIntSrc, interrupt souce, This parameter + ** can be any value of @ref en_int_src_t + ** + ** retval Ok + ** + ******************************************************************************/ +en_result_t enShareIrqEnable(en_int_src_t enIntSrc) +{ + uint32_t *VSSELx; + + //todo assert + + VSSELx = (uint32_t *)(((uint32_t)&M4_INTC->VSSEL128) + (4u * (enIntSrc/32u))); + *VSSELx |= (uint32_t)(1ul << (enIntSrc & 0x1Fu)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Share IRQ handler disable + ** + ** param [in] enIntSrc, interrupt souce, This parameter + ** can be any value of @ref en_int_src_t + ** + ** retval Ok + ** + ******************************************************************************/ +en_result_t enShareIrqDisable(en_int_src_t enIntSrc) +{ + uint32_t *VSSELx; + + //todo assert + + VSSELx = (uint32_t *)(((uint32_t)&M4_INTC->VSSEL128) + (4u * (enIntSrc/32u))); + *VSSELx &= ~(uint32_t)(1ul << (enIntSrc & 0x1Fu)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Enable stop mode wakeup source + ** + ** param [in] u32WakeupSrc, This parameter can be any + ** composed value of @ref en_int_wkup_src_t + ** + ** retval Ok, corresponding wakeup source be enabled + ** ErrorInvalidParameter, parameter with + ** non-definition bits + ** + ******************************************************************************/ +en_result_t enIntWakeupEnable(uint32_t u32WakeupSrc) +{ + en_result_t enRet = Ok; + if (0ul != (u32WakeupSrc & 0xFD000000ul)) + { + enRet = ErrorInvalidParameter; + } + else + { + M4_INTC->WUPEN |= u32WakeupSrc; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Disable stop mode wakeup source + ** + ** param [in] u32WakeupSrc, This parameter can be any + ** composed value of @ref en_int_wkup_src_t + ** + ** retval Ok, corresponding wakeup source be disabled + ** ErrorInvalidParameter, parameter with + ** non-definition bits + ** + ******************************************************************************/ +en_result_t enIntWakeupDisable(uint32_t u32WakeupSrc) +{ + en_result_t enRet = Ok; + if (0ul != (u32WakeupSrc & 0xFD000000u)) + { + enRet = ErrorInvalidParameter; + } + else + { + M4_INTC->WUPEN &= ~u32WakeupSrc; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Event enable + ** + ** param [in] u32Event, This parameter can be + ** any composed value of @ref en_evt_t + ** + ** retval Ok, corresponding event Ch. be enabled + ** + ******************************************************************************/ +en_result_t enEventEnable(uint32_t u32Event) +{ + M4_INTC->EVTER |= u32Event; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Event enable + ** + ** param [in] u32Event, This parameter can be + ** any composed value of @ref en_evt_t + ** + ** retval Ok, corresponding event Ch. be disabled + ** + ******************************************************************************/ +en_result_t enEventDisable(uint32_t u32Event) +{ + M4_INTC->EVTER &= ~u32Event; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Interrupt enable + ** + * param [in] u32Int, This parameter can be any composed + * value of @ref en_int_t + ** + ** retval Ok, corresponding interrupt vector be enabled + ** + ******************************************************************************/ +en_result_t enIntEnable(uint32_t u32Int) +{ + M4_INTC->IER |= u32Int; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Interrupt disable + ** + * param [in] u32Int, This parameter can be any composed + * value of @ref en_int_t + ** + ** retval Ok, corresponding interrupt vector be disabled + ** + ******************************************************************************/ +en_result_t enIntDisable(uint32_t u32Int) +{ + M4_INTC->IER &= ~u32Int; + return Ok; +} + +/** + ******************************************************************************* + ** \brief NMI IRQ handler + ** + ******************************************************************************/ +void NMI_Handler(void) +{ + NMI_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Hard Fault IRQ handler + ** + ******************************************************************************/ +//void HardFault_Handler(void) +//{ +// HardFault_IrqHandler(); +//} + +/** + ******************************************************************************* + ** \brief MPU Fault IRQ handler + ** + ******************************************************************************/ +void MemManage_Handler(void) +{ + MemManage_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Bus Fault IRQ handler + ** + ******************************************************************************/ +void BusFault_Handler(void) +{ + BusFault_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Usage Fault IRQ handler + ** + ******************************************************************************/ +void UsageFault_Handler(void) +{ + UsageFault_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief SVCall IRQ handler + ** + ******************************************************************************/ +void SVC_Handler(void) +{ + SVC_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief DebugMon IRQ handler + ** + ******************************************************************************/ +void DebugMon_Handler(void) +{ + DebugMon_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief PendSV IRQ handler + ** + ******************************************************************************/ +//void PendSV_Handler(void) +//{ +// PendSV_IrqHandler(); +//} + +/** + ******************************************************************************* + ** \brief Systick IRQ handler + ** + ******************************************************************************/ +void SysTick_Handler(void) +{ + SysTick_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Int No.000 IRQ handler + ** + ******************************************************************************/ +void IRQ000_Handler(void) +{ + if (NULL != IrqHandler[Int000_IRQn]) + { + IrqHandler[Int000_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.001 IRQ handler + ** + ******************************************************************************/ +void IRQ001_Handler(void) +{ + if (NULL != IrqHandler[Int001_IRQn]) + { + IrqHandler[Int001_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.002 IRQ handler + ** + ******************************************************************************/ +void IRQ002_Handler(void) +{ + if (NULL != IrqHandler[Int002_IRQn]) + { + IrqHandler[Int002_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.003 IRQ handler + ** + ******************************************************************************/ +void IRQ003_Handler(void) +{ + if (NULL != IrqHandler[Int003_IRQn]) + { + IrqHandler[Int003_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.004 IRQ handler + ** + ******************************************************************************/ +void IRQ004_Handler(void) +{ + if (NULL != IrqHandler[Int004_IRQn]) + { + IrqHandler[Int004_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.005 IRQ handler + ** + ******************************************************************************/ +void IRQ005_Handler(void) +{ + if (NULL != IrqHandler[Int005_IRQn]) + { + IrqHandler[Int005_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.006 IRQ handler + ** + ******************************************************************************/ +void IRQ006_Handler(void) +{ + if (NULL != IrqHandler[Int006_IRQn]) + { + IrqHandler[Int006_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.007 IRQ handler + ** + ******************************************************************************/ +void IRQ007_Handler(void) +{ + if (NULL != IrqHandler[Int007_IRQn]) + { + IrqHandler[Int007_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.008 IRQ handler + ** + ******************************************************************************/ +void IRQ008_Handler(void) +{ + if (NULL != IrqHandler[Int008_IRQn]) + { + IrqHandler[Int008_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.009 IRQ handler + ** + ******************************************************************************/ +void IRQ009_Handler(void) +{ + if (NULL != IrqHandler[Int009_IRQn]) + { + IrqHandler[Int009_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.010 IRQ handler + ** + ******************************************************************************/ +void IRQ010_Handler(void) +{ + if (NULL != IrqHandler[Int010_IRQn]) + { + IrqHandler[Int010_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.011 IRQ handler + ** + ******************************************************************************/ +void IRQ011_Handler(void) +{ + if (NULL != IrqHandler[Int011_IRQn]) + { + IrqHandler[Int011_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.012 IRQ handler + ** + ******************************************************************************/ +void IRQ012_Handler(void) +{ + if (NULL != IrqHandler[Int012_IRQn]) + { + IrqHandler[Int012_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.013 IRQ handler + ** + ******************************************************************************/ +void IRQ013_Handler(void) +{ + if (NULL != IrqHandler[Int013_IRQn]) + { + IrqHandler[Int013_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.014 IRQ handler + ** + ******************************************************************************/ +void IRQ014_Handler(void) +{ + if (NULL != IrqHandler[Int014_IRQn]) + { + IrqHandler[Int014_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.015 IRQ handler + ** + ******************************************************************************/ +void IRQ015_Handler(void) +{ + if (NULL != IrqHandler[Int015_IRQn]) + { + IrqHandler[Int015_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.016 IRQ handler + ** + ******************************************************************************/ +void IRQ016_Handler(void) +{ + if (NULL != IrqHandler[Int016_IRQn]) + { + IrqHandler[Int016_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.017 IRQ handler + ** + ******************************************************************************/ +void IRQ017_Handler(void) +{ + if (NULL != IrqHandler[Int017_IRQn]) + { + IrqHandler[Int017_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.018 IRQ handler + ** + ******************************************************************************/ +void IRQ018_Handler(void) +{ + if (NULL != IrqHandler[Int018_IRQn]) + { + IrqHandler[Int018_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.019 IRQ handler + ** + ******************************************************************************/ +void IRQ019_Handler(void) +{ + if (NULL != IrqHandler[Int019_IRQn]) + { + IrqHandler[Int019_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.020 IRQ handler + ** + ******************************************************************************/ +void IRQ020_Handler(void) +{ + if (NULL != IrqHandler[Int020_IRQn]) + { + IrqHandler[Int020_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.021 IRQ handler + ** + ******************************************************************************/ +void IRQ021_Handler(void) +{ + if (NULL != IrqHandler[Int021_IRQn]) + { + IrqHandler[Int021_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.022 IRQ handler + ** + ******************************************************************************/ +void IRQ022_Handler(void) +{ + if (NULL != IrqHandler[Int022_IRQn]) + { + IrqHandler[Int022_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.023 IRQ handler + ** + ******************************************************************************/ +void IRQ023_Handler(void) +{ + if (NULL != IrqHandler[Int023_IRQn]) + { + IrqHandler[Int023_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.024 IRQ handler + ** + ******************************************************************************/ +void IRQ024_Handler(void) +{ + if (NULL != IrqHandler[Int024_IRQn]) + { + IrqHandler[Int024_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.025 IRQ handler + ** + ******************************************************************************/ +void IRQ025_Handler(void) +{ + if (NULL != IrqHandler[Int025_IRQn]) + { + IrqHandler[Int025_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.026 IRQ handler + ** + ******************************************************************************/ +void IRQ026_Handler(void) +{ + if (NULL != IrqHandler[Int026_IRQn]) + { + IrqHandler[Int026_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.027 IRQ handler + ** + ******************************************************************************/ +void IRQ027_Handler(void) +{ + if (NULL != IrqHandler[Int027_IRQn]) + { + IrqHandler[Int027_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.028 IRQ handler + ** + ******************************************************************************/ +void IRQ028_Handler(void) +{ + if (NULL != IrqHandler[Int028_IRQn]) + { + IrqHandler[Int028_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.029 IRQ handler + ** + ******************************************************************************/ +void IRQ029_Handler(void) +{ + if (NULL != IrqHandler[Int029_IRQn]) + { + IrqHandler[Int029_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.030 IRQ handler + ** + ******************************************************************************/ +void IRQ030_Handler(void) +{ + if (NULL != IrqHandler[Int030_IRQn]) + { + IrqHandler[Int030_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.031 IRQ handler + ** + ******************************************************************************/ +void IRQ031_Handler(void) +{ + if (NULL != IrqHandler[Int031_IRQn]) + { + IrqHandler[Int031_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.032 IRQ handler + ** + ******************************************************************************/ +void IRQ032_Handler(void) +{ + if (NULL != IrqHandler[Int032_IRQn]) + { + IrqHandler[Int032_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.033 IRQ handler + ** + ******************************************************************************/ +void IRQ033_Handler(void) +{ + if (NULL != IrqHandler[Int033_IRQn]) + { + IrqHandler[Int033_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.034 IRQ handler + ** + ******************************************************************************/ +void IRQ034_Handler(void) +{ + if (NULL != IrqHandler[Int034_IRQn]) + { + IrqHandler[Int034_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.035 IRQ handler + ** + ******************************************************************************/ +void IRQ035_Handler(void) +{ + if (NULL != IrqHandler[Int035_IRQn]) + { + IrqHandler[Int035_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.036 IRQ handler + ** + ******************************************************************************/ +void IRQ036_Handler(void) +{ + if (NULL != IrqHandler[Int036_IRQn]) + { + IrqHandler[Int036_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.037 IRQ handler + ** + ******************************************************************************/ +void IRQ037_Handler(void) +{ + if (NULL != IrqHandler[Int037_IRQn]) + { + IrqHandler[Int037_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.038 IRQ handler + ** + ******************************************************************************/ +void IRQ038_Handler(void) +{ + if (NULL != IrqHandler[Int038_IRQn]) + { + IrqHandler[Int038_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.039 IRQ handler + ** + ******************************************************************************/ +void IRQ039_Handler(void) +{ + if (NULL != IrqHandler[Int039_IRQn]) + { + IrqHandler[Int039_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.040 IRQ handler + ** + ******************************************************************************/ +void IRQ040_Handler(void) +{ + if (NULL != IrqHandler[Int040_IRQn]) + { + IrqHandler[Int040_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.041 IRQ handler + ** + ******************************************************************************/ +void IRQ041_Handler(void) +{ + if (NULL != IrqHandler[Int041_IRQn]) + { + IrqHandler[Int041_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.042 IRQ handler + ** + ******************************************************************************/ +void IRQ042_Handler(void) +{ + if (NULL != IrqHandler[Int042_IRQn]) + { + IrqHandler[Int042_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.043 IRQ handler + ** + ******************************************************************************/ +void IRQ043_Handler(void) +{ + if (NULL != IrqHandler[Int043_IRQn]) + { + IrqHandler[Int043_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.044 IRQ handler + ** + ******************************************************************************/ +void IRQ044_Handler(void) +{ + if (NULL != IrqHandler[Int044_IRQn]) + { + IrqHandler[Int044_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.045 IRQ handler + ** + ******************************************************************************/ +void IRQ045_Handler(void) +{ + if (NULL != IrqHandler[Int045_IRQn]) + { + IrqHandler[Int045_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.046 IRQ handler + ** + ******************************************************************************/ +void IRQ046_Handler(void) +{ + if (NULL != IrqHandler[Int046_IRQn]) + { + IrqHandler[Int046_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.047 IRQ handler + ** + ******************************************************************************/ +void IRQ047_Handler(void) +{ + if (NULL != IrqHandler[Int047_IRQn]) + { + IrqHandler[Int047_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.048 IRQ handler + ** + ******************************************************************************/ +void IRQ048_Handler(void) +{ + if (NULL != IrqHandler[Int048_IRQn]) + { + IrqHandler[Int048_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.049 IRQ handler + ** + ******************************************************************************/ +void IRQ049_Handler(void) +{ + if (NULL != IrqHandler[Int049_IRQn]) + { + IrqHandler[Int049_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.050 IRQ handler + ** + ******************************************************************************/ +void IRQ050_Handler(void) +{ + if (NULL != IrqHandler[Int050_IRQn]) + { + IrqHandler[Int050_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.051 IRQ handler + ** + ******************************************************************************/ +void IRQ051_Handler(void) +{ + if (NULL != IrqHandler[Int051_IRQn]) + { + IrqHandler[Int051_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.052 IRQ handler + ** + ******************************************************************************/ +void IRQ052_Handler(void) +{ + if (NULL != IrqHandler[Int052_IRQn]) + { + IrqHandler[Int052_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.053 IRQ handler + ** + ******************************************************************************/ +void IRQ053_Handler(void) +{ + if (NULL != IrqHandler[Int053_IRQn]) + { + IrqHandler[Int053_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.054 IRQ handler + ** + ******************************************************************************/ +void IRQ054_Handler(void) +{ + if (NULL != IrqHandler[Int054_IRQn]) + { + IrqHandler[Int054_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.055 IRQ handler + ** + ******************************************************************************/ +void IRQ055_Handler(void) +{ + if (NULL != IrqHandler[Int055_IRQn]) + { + IrqHandler[Int055_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.056 IRQ handler + ** + ******************************************************************************/ +void IRQ056_Handler(void) +{ + if (NULL != IrqHandler[Int056_IRQn]) + { + IrqHandler[Int056_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.057 IRQ handler + ** + ******************************************************************************/ +void IRQ057_Handler(void) +{ + if (NULL != IrqHandler[Int057_IRQn]) + { + IrqHandler[Int057_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.058 IRQ handler + ** + ******************************************************************************/ +void IRQ058_Handler(void) +{ + if (NULL != IrqHandler[Int058_IRQn]) + { + IrqHandler[Int058_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.059 IRQ handler + ** + ******************************************************************************/ +void IRQ059_Handler(void) +{ + if (NULL != IrqHandler[Int059_IRQn]) + { + IrqHandler[Int059_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.060 IRQ handler + ** + ******************************************************************************/ +void IRQ060_Handler(void) +{ + if (NULL != IrqHandler[Int060_IRQn]) + { + IrqHandler[Int060_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.061 IRQ handler + ** + ******************************************************************************/ +void IRQ061_Handler(void) +{ + if (NULL != IrqHandler[Int061_IRQn]) + { + IrqHandler[Int061_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.062 IRQ handler + ** + ******************************************************************************/ +void IRQ062_Handler(void) +{ + if (NULL != IrqHandler[Int062_IRQn]) + { + IrqHandler[Int062_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.063 IRQ handler + ** + ******************************************************************************/ +void IRQ063_Handler(void) +{ + if (NULL != IrqHandler[Int063_IRQn]) + { + IrqHandler[Int063_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.064 IRQ handler + ** + ******************************************************************************/ +void IRQ064_Handler(void) +{ + if (NULL != IrqHandler[Int064_IRQn]) + { + IrqHandler[Int064_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.065 IRQ handler + ** + ******************************************************************************/ +void IRQ065_Handler(void) +{ + if (NULL != IrqHandler[Int065_IRQn]) + { + IrqHandler[Int065_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.066 IRQ handler + ** + ******************************************************************************/ +void IRQ066_Handler(void) +{ + if (NULL != IrqHandler[Int066_IRQn]) + { + IrqHandler[Int066_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.067 IRQ handler + ** + ******************************************************************************/ +void IRQ067_Handler(void) +{ + if (NULL != IrqHandler[Int067_IRQn]) + { + IrqHandler[Int067_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.068 IRQ handler + ** + ******************************************************************************/ +void IRQ068_Handler(void) +{ + if (NULL != IrqHandler[Int068_IRQn]) + { + IrqHandler[Int068_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.069 IRQ handler + ** + ******************************************************************************/ +void IRQ069_Handler(void) +{ + if (NULL != IrqHandler[Int069_IRQn]) + { + IrqHandler[Int069_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.070 IRQ handler + ** + ******************************************************************************/ +void IRQ070_Handler(void) +{ + if (NULL != IrqHandler[Int070_IRQn]) + { + IrqHandler[Int070_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.071 IRQ handler + ** + ******************************************************************************/ +void IRQ071_Handler(void) +{ + if (NULL != IrqHandler[Int071_IRQn]) + { + IrqHandler[Int071_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.072 IRQ handler + ** + ******************************************************************************/ +void IRQ072_Handler(void) +{ + if (NULL != IrqHandler[Int072_IRQn]) + { + IrqHandler[Int072_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.073 IRQ handler + ** + ******************************************************************************/ +void IRQ073_Handler(void) +{ + if (NULL != IrqHandler[Int073_IRQn]) + { + IrqHandler[Int073_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.074 IRQ handler + ** + ******************************************************************************/ +void IRQ074_Handler(void) +{ + if (NULL != IrqHandler[Int074_IRQn]) + { + IrqHandler[Int074_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.075 IRQ handler + ** + ******************************************************************************/ +void IRQ075_Handler(void) +{ + if (NULL != IrqHandler[Int075_IRQn]) + { + IrqHandler[Int075_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.076 IRQ handler + ** + ******************************************************************************/ +void IRQ076_Handler(void) +{ + if (NULL != IrqHandler[Int076_IRQn]) + { + IrqHandler[Int076_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.077 IRQ handler + ** + ******************************************************************************/ +void IRQ077_Handler(void) +{ + if (NULL != IrqHandler[Int077_IRQn]) + { + IrqHandler[Int077_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.078 IRQ handler + ** + ******************************************************************************/ +void IRQ078_Handler(void) +{ + if (NULL != IrqHandler[Int078_IRQn]) + { + IrqHandler[Int078_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.079 IRQ handler + ** + ******************************************************************************/ +void IRQ079_Handler(void) +{ + if (NULL != IrqHandler[Int079_IRQn]) + { + IrqHandler[Int079_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.080 IRQ handler + ** + ******************************************************************************/ +void IRQ080_Handler(void) +{ + if (NULL != IrqHandler[Int080_IRQn]) + { + IrqHandler[Int080_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.081 IRQ handler + ** + ******************************************************************************/ +void IRQ081_Handler(void) +{ + if (NULL != IrqHandler[Int081_IRQn]) + { + IrqHandler[Int081_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.082 IRQ handler + ** + ******************************************************************************/ +void IRQ082_Handler(void) +{ + if (NULL != IrqHandler[Int082_IRQn]) + { + IrqHandler[Int082_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.083 IRQ handler + ** + ******************************************************************************/ +void IRQ083_Handler(void) +{ + if (NULL != IrqHandler[Int083_IRQn]) + { + IrqHandler[Int083_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.084 IRQ handler + ** + ******************************************************************************/ +void IRQ084_Handler(void) +{ + if (NULL != IrqHandler[Int084_IRQn]) + { + IrqHandler[Int084_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.085 IRQ handler + ** + ******************************************************************************/ +void IRQ085_Handler(void) +{ + if (NULL != IrqHandler[Int085_IRQn]) + { + IrqHandler[Int085_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.086 IRQ handler + ** + ******************************************************************************/ +void IRQ086_Handler(void) +{ + if (NULL != IrqHandler[Int086_IRQn]) + { + IrqHandler[Int086_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.087 IRQ handler + ** + ******************************************************************************/ +void IRQ087_Handler(void) +{ + if (NULL != IrqHandler[Int087_IRQn]) + { + IrqHandler[Int087_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.088 IRQ handler + ** + ******************************************************************************/ +void IRQ088_Handler(void) +{ + if (NULL != IrqHandler[Int088_IRQn]) + { + IrqHandler[Int088_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.089 IRQ handler + ** + ******************************************************************************/ +void IRQ089_Handler(void) +{ + if (NULL != IrqHandler[Int089_IRQn]) + { + IrqHandler[Int089_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.090 IRQ handler + ** + ******************************************************************************/ +void IRQ090_Handler(void) +{ + if (NULL != IrqHandler[Int090_IRQn]) + { + IrqHandler[Int090_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.091 IRQ handler + ** + ******************************************************************************/ +void IRQ091_Handler(void) +{ + if (NULL != IrqHandler[Int091_IRQn]) + { + IrqHandler[Int091_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.092 IRQ handler + ** + ******************************************************************************/ +void IRQ092_Handler(void) +{ + if (NULL != IrqHandler[Int092_IRQn]) + { + IrqHandler[Int092_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.093 IRQ handler + ** + ******************************************************************************/ +void IRQ093_Handler(void) +{ + if (NULL != IrqHandler[Int093_IRQn]) + { + IrqHandler[Int093_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.094 IRQ handler + ** + ******************************************************************************/ +void IRQ094_Handler(void) +{ + if (NULL != IrqHandler[Int094_IRQn]) + { + IrqHandler[Int094_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.095 IRQ handler + ** + ******************************************************************************/ +void IRQ095_Handler(void) +{ + if (NULL != IrqHandler[Int095_IRQn]) + { + IrqHandler[Int095_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.096 IRQ handler + ** + ******************************************************************************/ +void IRQ096_Handler(void) +{ + if (NULL != IrqHandler[Int096_IRQn]) + { + IrqHandler[Int096_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.097 IRQ handler + ** + ******************************************************************************/ +void IRQ097_Handler(void) +{ + if (NULL != IrqHandler[Int097_IRQn]) + { + IrqHandler[Int097_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.098 IRQ handler + ** + ******************************************************************************/ +void IRQ098_Handler(void) +{ + if (NULL != IrqHandler[Int098_IRQn]) + { + IrqHandler[Int098_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.099 IRQ handler + ** + ******************************************************************************/ +void IRQ099_Handler(void) +{ + if (NULL != IrqHandler[Int099_IRQn]) + { + IrqHandler[Int099_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.100 IRQ handler + ** + ******************************************************************************/ +void IRQ100_Handler(void) +{ + if (NULL != IrqHandler[Int100_IRQn]) + { + IrqHandler[Int100_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.101 IRQ handler + ** + ******************************************************************************/ +void IRQ101_Handler(void) +{ + if (NULL != IrqHandler[Int101_IRQn]) + { + IrqHandler[Int101_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.102 IRQ handler + ** + ******************************************************************************/ +void IRQ102_Handler(void) +{ + if (NULL != IrqHandler[Int102_IRQn]) + { + IrqHandler[Int102_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.103 IRQ handler + ** + ******************************************************************************/ +void IRQ103_Handler(void) +{ + if (NULL != IrqHandler[Int103_IRQn]) + { + IrqHandler[Int103_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.104 IRQ handler + ** + ******************************************************************************/ +void IRQ104_Handler(void) +{ + if (NULL != IrqHandler[Int104_IRQn]) + { + IrqHandler[Int104_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.105 IRQ handler + ** + ******************************************************************************/ +void IRQ105_Handler(void) +{ + if (NULL != IrqHandler[Int105_IRQn]) + { + IrqHandler[Int105_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.106 IRQ handler + ** + ******************************************************************************/ +void IRQ106_Handler(void) +{ + if (NULL != IrqHandler[Int106_IRQn]) + { + IrqHandler[Int106_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.107 IRQ handler + ** + ******************************************************************************/ +void IRQ107_Handler(void) +{ + if (NULL != IrqHandler[Int107_IRQn]) + { + IrqHandler[Int107_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.108 IRQ handler + ** + ******************************************************************************/ +void IRQ108_Handler(void) +{ + if (NULL != IrqHandler[Int108_IRQn]) + { + IrqHandler[Int108_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.109 IRQ handler + ** + ******************************************************************************/ +void IRQ109_Handler(void) +{ + if (NULL != IrqHandler[Int109_IRQn]) + { + IrqHandler[Int109_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.110 IRQ handler + ** + ******************************************************************************/ +void IRQ110_Handler(void) +{ + if (NULL != IrqHandler[Int110_IRQn]) + { + IrqHandler[Int110_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.111 IRQ handler + ** + ******************************************************************************/ +void IRQ111_Handler(void) +{ + if (NULL != IrqHandler[Int111_IRQn]) + { + IrqHandler[Int111_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.112 IRQ handler + ** + ******************************************************************************/ +void IRQ112_Handler(void) +{ + if (NULL != IrqHandler[Int112_IRQn]) + { + IrqHandler[Int112_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.113 IRQ handler + ** + ******************************************************************************/ +void IRQ113_Handler(void) +{ + if (NULL != IrqHandler[Int113_IRQn]) + { + IrqHandler[Int113_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.114 IRQ handler + ** + ******************************************************************************/ +void IRQ114_Handler(void) +{ + if (NULL != IrqHandler[Int114_IRQn]) + { + IrqHandler[Int114_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.115 IRQ handler + ** + ******************************************************************************/ +void IRQ115_Handler(void) +{ + if (NULL != IrqHandler[Int115_IRQn]) + { + IrqHandler[Int115_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.116 IRQ handler + ** + ******************************************************************************/ +void IRQ116_Handler(void) +{ + if (NULL != IrqHandler[Int116_IRQn]) + { + IrqHandler[Int116_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.117 IRQ handler + ** + ******************************************************************************/ +void IRQ117_Handler(void) +{ + if (NULL != IrqHandler[Int117_IRQn]) + { + IrqHandler[Int117_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.118 IRQ handler + ** + ******************************************************************************/ +void IRQ118_Handler(void) +{ + if (NULL != IrqHandler[Int118_IRQn]) + { + IrqHandler[Int118_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.119 IRQ handler + ** + ******************************************************************************/ +void IRQ119_Handler(void) +{ + if (NULL != IrqHandler[Int119_IRQn]) + { + IrqHandler[Int119_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.120 IRQ handler + ** + ******************************************************************************/ +void IRQ120_Handler(void) +{ + if (NULL != IrqHandler[Int120_IRQn]) + { + IrqHandler[Int120_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.121 IRQ handler + ** + ******************************************************************************/ +void IRQ121_Handler(void) +{ + if (NULL != IrqHandler[Int121_IRQn]) + { + IrqHandler[Int121_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.122 IRQ handler + ** + ******************************************************************************/ +void IRQ122_Handler(void) +{ + if (NULL != IrqHandler[Int122_IRQn]) + { + IrqHandler[Int122_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.123 IRQ handler + ** + ******************************************************************************/ +void IRQ123_Handler(void) +{ + if (NULL != IrqHandler[Int123_IRQn]) + { + IrqHandler[Int123_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.124 IRQ handler + ** + ******************************************************************************/ +void IRQ124_Handler(void) +{ + if (NULL != IrqHandler[Int124_IRQn]) + { + IrqHandler[Int124_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.125 IRQ handler + ** + ******************************************************************************/ +void IRQ125_Handler(void) +{ + if (NULL != IrqHandler[Int125_IRQn]) + { + IrqHandler[Int125_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.126 IRQ handler + ** + ******************************************************************************/ +void IRQ126_Handler(void) +{ + if (NULL != IrqHandler[Int126_IRQn]) + { + IrqHandler[Int126_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.127 IRQ handler + ** + ******************************************************************************/ +void IRQ127_Handler(void) +{ + if (NULL != IrqHandler[Int127_IRQn]) + { + IrqHandler[Int127_IRQn](); + } +} + +#if (DDL_INTERRUPTS_SHARE_ENABLE == DDL_ON) +/** + ******************************************************************************* + ** \brief Int No.128 share IRQ handler + ** + ******************************************************************************/ +void IRQ128_Handler(void) +{ + uint32_t VSSEL128 = M4_INTC->VSSEL128; + + /* external interrupt 00 */ + if ((1ul == bM4_INTC_EIFR_EIFR0) && (VSSEL128 & BIT_MASK_00)) + { + Extint00_IrqHandler(); + } + /* external interrupt 01 */ + if ((1ul == bM4_INTC_EIFR_EIFR1) && (VSSEL128 & BIT_MASK_01)) + { + Extint01_IrqHandler(); + } + /* external interrupt 02 */ + if ((1ul == bM4_INTC_EIFR_EIFR2) && (VSSEL128 & BIT_MASK_02)) + { + Extint02_IrqHandler(); + } + /* external interrupt 03 */ + if ((1ul == bM4_INTC_EIFR_EIFR3) && (VSSEL128 & BIT_MASK_03)) + { + Extint03_IrqHandler(); + } + /* external interrupt 04 */ + if ((1ul == bM4_INTC_EIFR_EIFR4) && (VSSEL128 & BIT_MASK_04)) + { + Extint04_IrqHandler(); + } + /* external interrupt 05 */ + if ((1ul == bM4_INTC_EIFR_EIFR5) && (VSSEL128 & BIT_MASK_05)) + { + Extint05_IrqHandler(); + } + /* external interrupt 06 */ + if ((1ul == bM4_INTC_EIFR_EIFR6) && (VSSEL128 & BIT_MASK_06)) + { + Extint06_IrqHandler(); + } + /* external interrupt 07 */ + if ((1ul == bM4_INTC_EIFR_EIFR7) && (VSSEL128 & BIT_MASK_07)) + { + Extint07_IrqHandler(); + } + /* external interrupt 08 */ + if ((1ul == bM4_INTC_EIFR_EIFR8) && (VSSEL128 & BIT_MASK_08)) + { + Extint08_IrqHandler(); + } + /* external interrupt 09 */ + if ((1ul == bM4_INTC_EIFR_EIFR9) && (VSSEL128 & BIT_MASK_09)) + { + Extint09_IrqHandler(); + } + /* external interrupt 10 */ + if ((1ul == bM4_INTC_EIFR_EIFR10) && (VSSEL128 & BIT_MASK_10)) + { + Extint10_IrqHandler(); + } + /* external interrupt 11 */ + if ((1ul == bM4_INTC_EIFR_EIFR11) && (VSSEL128 & BIT_MASK_11)) + { + Extint11_IrqHandler(); + } + /* external interrupt 12 */ + if ((1ul == bM4_INTC_EIFR_EIFR12) && (VSSEL128 & BIT_MASK_12)) + { + Extint12_IrqHandler(); + } + /* external interrupt 13 */ + if ((1ul == bM4_INTC_EIFR_EIFR13) && (VSSEL128 & BIT_MASK_13)) + { + Extint13_IrqHandler(); + } + /* external interrupt 14 */ + if ((1ul == bM4_INTC_EIFR_EIFR14) && (VSSEL128 & BIT_MASK_14)) + { + Extint14_IrqHandler(); + } + /* external interrupt 15 */ + if ((1ul == bM4_INTC_EIFR_EIFR15) && (VSSEL128 & BIT_MASK_15)) + { + Extint15_IrqHandler(); + } +} + + +/** + ******************************************************************************* + ** \brief Int No.129 share IRQ handler + ** + ******************************************************************************/ +void IRQ129_Handler(void) +{ + uint32_t VSSEL129 =M4_INTC->VSSEL129; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + + if (1ul == bM4_DMA1_CH0CTL_IE) + { + /* DMA1 ch.0 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC0) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC0) && (VSSEL129 & BIT_MASK_00)) + { + Dma1Tc0_IrqHandler(); + } + } + /* DMA1 ch.0 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC0) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC0) && (VSSEL129 & BIT_MASK_08)) + { + Dma1Btc0_IrqHandler(); + } + } + /* DMA1 ch.0 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00010001ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00010001ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err0_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CH1CTL_IE) + { + /* DMA1 ch.1 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC1) && (VSSEL129 & BIT_MASK_01)) + { + Dma1Tc1_IrqHandler(); + } + } + /* DMA1 ch.1 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC1) && (VSSEL129 & BIT_MASK_09)) + { + Dma1Btc1_IrqHandler(); + } + } + /* DMA1 ch.1 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00020002ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00020002ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err1_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CH2CTL_IE) + { + /* DMA1 ch.2 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC2) && (VSSEL129 & BIT_MASK_02)) + { + Dma1Tc2_IrqHandler(); + } + } + /* DMA1 ch.2 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC2) && (VSSEL129 & BIT_MASK_10)) + { + Dma1Btc2_IrqHandler(); + } + } + /* DMA1 ch.2 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00040004ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00040004ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err2_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CH3CTL_IE) + { + /* DMA1 ch.3 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC3) && (VSSEL129 & BIT_MASK_03)) + { + Dma1Tc3_IrqHandler(); + } + } + /* DMA1 ch.3 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC3) && (VSSEL129 & BIT_MASK_11)) + { + Dma1Btc3_IrqHandler(); + } + } + /* DMA1 ch.3 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00080008ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00080008ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err3_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH0CTL_IE) + { + /* DMA2 ch.0 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC0) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC0) && (VSSEL129 & BIT_MASK_04)) + { + Dma2Tc0_IrqHandler(); + } + } + /* DMA2 ch.0 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC0) + { + if ((1ul == bM4_DMA2_INTSTAT1_BTC0) && (VSSEL129 & BIT_MASK_12)) + { + Dma2Btc0_IrqHandler(); + } + } + /* DMA2 Ch.0 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00010001ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00010001ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err0_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH1CTL_IE) + { + /* DMA2 ch.1 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC1) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC1) && (VSSEL129 & BIT_MASK_05)) + { + Dma2Tc1_IrqHandler(); + } + } + /* DMA2 ch.1 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC1) && (VSSEL129 & BIT_MASK_13)) + { + Dma2Btc1_IrqHandler(); + } + } + /* DMA2 Ch.1 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00020002ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00020002ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err1_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH2CTL_IE) + { + /* DMA2 ch.2 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC2) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC2) && (VSSEL129 & BIT_MASK_06)) + { + Dma2Tc2_IrqHandler(); + } + } + /* DMA2 ch.2 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC2) && (VSSEL129 & BIT_MASK_14)) + { + Dma2Btc2_IrqHandler(); + } + } + /* DMA2 Ch.2 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00040004ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00040004ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err2_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH3CTL_IE) + { + /* DMA2 ch.3 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC3) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC3) && (VSSEL129 & BIT_MASK_07)) + { + Dma2Tc3_IrqHandler(); + } + } + /* DMA2 ch.3 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC3) && (VSSEL129 & BIT_MASK_15)) + { + Dma2Btc3_IrqHandler(); + } + } + /* DMA2 Ch.3 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00080008ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00080008ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err3_IrqHandler(); + } + } + /* EFM program/erase Error */ + if (1ul == bM4_EFM_FITE_PEERRITE) + { + if ((M4_EFM->FSR & 0x0Fu) && (VSSEL129 & BIT_MASK_18)) + { + EfmPgmEraseErr_IrqHandler(); + } + } + /* EFM collision Error */ + if (1ul == bM4_EFM_FITE_COLERRITE) + { + if ((1ul == bM4_EFM_FSR_COLERR) && (VSSEL129 & BIT_MASK_19)) + { + EfmColErr_IrqHandler(); + } + } + /* EFM operate end */ + if (1ul == bM4_EFM_FITE_OPTENDITE) + { + if ((1ul == bM4_EFM_FSR_OPTEND) && (VSSEL129 & BIT_MASK_20)) + { + EfmOpEnd_IrqHandler(); + } + } + /* QSPI interrupt */ + if ((1ul == M4_QSPI->SR_f.RAER) && (VSSEL129 & BIT_MASK_22)) + { + QspiInt_IrqHandler(); + } + /* DCU ch.1 */ + u32Tmp1 = M4_DCU1->INTSEL; + u32Tmp2 = M4_DCU1->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_23)) + { + Dcu1_IrqHandler(); + } + /* DCU ch.2 */ + u32Tmp1 = M4_DCU2->INTSEL; + u32Tmp2 = M4_DCU2->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_24)) + { + Dcu2_IrqHandler(); + } + /* DCU ch.3 */ + u32Tmp1 = M4_DCU3->INTSEL; + u32Tmp2 = M4_DCU3->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_25)) + { + Dcu3_IrqHandler(); + } + /* DCU ch.4 */ + u32Tmp1 = M4_DCU4->INTSEL; + u32Tmp2 = M4_DCU4->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_26)) + { + Dcu4_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.130 share IRQ handler + ** + ******************************************************************************/ +void IRQ130_Handler(void) +{ + uint32_t VSSEL130 = M4_INTC->VSSEL130; + /* Timer0 Ch. 1 A compare match */ + if (1ul == bM4_TMR01_BCONR_INTENA) + { + if ((1ul == bM4_TMR01_STFLR_CMAF) && (VSSEL130 & BIT_MASK_00)) + { + Timer01GCMA_IrqHandler(); + } + } + /* Timer0 Ch. 1 B compare match */ + if (1ul == bM4_TMR01_BCONR_INTENB) + { + if ((1ul == bM4_TMR01_STFLR_CMBF) && (VSSEL130 & BIT_MASK_01)) + { + Timer01GCMB_IrqHandler(); + } + } + /* Timer0 Ch. 2 A compare match */ + if (1ul == bM4_TMR02_BCONR_INTENA) + { + if ((1ul == bM4_TMR02_STFLR_CMAF) && (VSSEL130 & BIT_MASK_02)) + { + Timer02GCMA_IrqHandler(); + } + } + /* Timer0 Ch. 2 B compare match */ + if (1ul == bM4_TMR02_BCONR_INTENB) + { + if ((1ul == bM4_TMR02_STFLR_CMBF) && (VSSEL130 & BIT_MASK_03)) + { + Timer02GCMB_IrqHandler(); + } + } + /* Main-OSC stop */ + if (1ul == bM4_SYSREG_CMU_XTALSTDCR_XTALSTDIE) + { + if ((1ul == bM4_SYSREG_CMU_XTALSTDSR_XTALSTDF) && (VSSEL130 & BIT_MASK_21)) + { + MainOscStop_IrqHandler(); + } + } + /* Wakeup timer */ + if ((1ul == bM4_WKTM_CR_WKOVF) && (VSSEL130 & BIT_MASK_22)) + { + WakeupTimer_IrqHandler(); + } + /* SWDT */ + if ((M4_SWDT->SR & (BIT_MASK_16 | BIT_MASK_17)) && (VSSEL130 & BIT_MASK_23)) + { + Swdt_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.131 share IRQ handler + ** + ******************************************************************************/ +void IRQ131_Handler(void) +{ + uint32_t VSSEL131 = M4_INTC->VSSEL131; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* Timer6 Ch.1 A compare match */ + if (1ul == bM4_TMR61_ICONR_INTENA) + { + if ((1ul == bM4_TMR61_STFLR_CMAF) && (VSSEL131 & BIT_MASK_00)) + { + Timer61GCMA_IrqHandler(); + } + } + /* Timer6 Ch.1 B compare match */ + if (1ul == bM4_TMR61_ICONR_INTENB) + { + if ((1ul == bM4_TMR61_STFLR_CMBF) && (VSSEL131 & BIT_MASK_01)) + { + Timer61GCMB_IrqHandler(); + } + } + /* Timer6 Ch.1 C compare match */ + if (1ul == bM4_TMR61_ICONR_INTENC) + { + if ((1ul == bM4_TMR61_STFLR_CMCF) && (VSSEL131 & BIT_MASK_02)) + { + Timer61GCMC_IrqHandler(); + } + } + /* Timer6 Ch.1 D compare match */ + if (1ul == bM4_TMR61_ICONR_INTEND) + { + if ((1ul == bM4_TMR61_STFLR_CMDF) && (VSSEL131 & BIT_MASK_03)) + { + Timer61GCMD_IrqHandler(); + } + } + /* Timer6 Ch.1 E compare match */ + if (1ul == bM4_TMR61_ICONR_INTENE) + { + if ((1ul == bM4_TMR61_STFLR_CMEF) && (VSSEL131 & BIT_MASK_04)) + { + Timer61GCME_IrqHandler(); + } + } + /* Timer6 Ch.1 F compare match */ + if (1ul == bM4_TMR61_ICONR_INTENF) + { + if ((1ul == bM4_TMR61_STFLR_CMFF) && (VSSEL131 & BIT_MASK_05)) + { + Timer61GCMF_IrqHandler(); + } + } + /* Timer6 Ch.1 overflow */ + if (1ul == bM4_TMR61_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR61_STFLR_OVFF) && (VSSEL131 & BIT_MASK_06)) + { + Timer61GOV_IrqHandler(); + } + } + /* Timer6 Ch.1 underflow */ + if (1ul == bM4_TMR61_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR61_STFLR_UDFF) && (VSSEL131 & BIT_MASK_07)) + { + Timer61GUD_IrqHandler(); + } + } + /* Timer6 Ch.1 dead time */ + if (1ul == bM4_TMR61_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR61_STFLR_DTEF)) && (VSSEL131 & BIT_MASK_08)) + { + Timer61GDT_IrqHandler(); + } + } + /* Timer6 Ch.1 A up-down compare match */ + u32Tmp1 = (M4_TMR61->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR61->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_11)) + { + Timer61SCMA_IrqHandler(); + } + /* Timer6 Ch.1 B up-down compare match */ + u32Tmp1 = (M4_TMR61->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR61->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_12)) + { + Timer61SCMB_IrqHandler(); + } + /* Timer6 Ch.2 A compare match */ + if (1ul == bM4_TMR62_ICONR_INTENA) + { + if ((1ul == bM4_TMR62_STFLR_CMAF) && (VSSEL131 & BIT_MASK_16)) + { + Timer62GCMA_IrqHandler(); + } + } + /* Timer6 Ch.2 B compare match */ + if (1ul == bM4_TMR62_ICONR_INTENB) + { + if ((1ul == bM4_TMR62_STFLR_CMBF) && (VSSEL131 & BIT_MASK_17)) + { + Timer62GCMB_IrqHandler(); + } + } + /* Timer6 Ch.2 C compare match */ + if (1ul == bM4_TMR62_ICONR_INTENC) + { + if ((1ul == bM4_TMR62_STFLR_CMCF) && (VSSEL131 & BIT_MASK_18)) + { + Timer62GCMC_IrqHandler(); + } + } + /* Timer6 Ch.2 D compare match */ + if (1ul == bM4_TMR62_ICONR_INTEND) + { + if ((1ul == bM4_TMR62_STFLR_CMDF) && (VSSEL131 & BIT_MASK_19)) + { + Timer62GCMD_IrqHandler(); + } + } + /* Timer6 Ch.2 E compare match */ + if (1ul == bM4_TMR62_ICONR_INTENE) + { + if ((1ul == bM4_TMR62_STFLR_CMEF) && (VSSEL131 & BIT_MASK_20)) + { + Timer62GCME_IrqHandler(); + } + } + /* Timer6 Ch.2 F compare match */ + if (1ul == bM4_TMR62_ICONR_INTENF) + { + if ((1ul == bM4_TMR62_STFLR_CMFF) && (VSSEL131 & BIT_MASK_21)) + { + Timer62GCMF_IrqHandler(); + } + } + /* Timer6 Ch.2 overflow */ + if (1ul == bM4_TMR62_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR62_STFLR_OVFF) && (VSSEL131 & BIT_MASK_22)) + { + Timer62GOV_IrqHandler(); + } + } + /* Timer6 Ch.2 underflow */ + if (1ul == bM4_TMR62_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR62_STFLR_UDFF) && (VSSEL131 & BIT_MASK_23)) + { + Timer62GUD_IrqHandler(); + } + } + /* Timer6 Ch.2 dead time */ + if (1ul == bM4_TMR62_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR62_STFLR_DTEF)) && (VSSEL131 & BIT_MASK_24)) + { + Timer62GDT_IrqHandler(); + } + } + /* Timer6 Ch.2 A up-down compare match */ + u32Tmp1 = (M4_TMR62->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR62->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_27)) + { + Timer62SCMA_IrqHandler(); + } + /* Timer6 Ch.2 B up-down compare match */ + u32Tmp1 = (M4_TMR62->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR62->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_28)) + { + Timer62SCMB_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.132 share IRQ handler + ** + ******************************************************************************/ +void IRQ132_Handler(void) +{ + uint32_t VSSEL132 = M4_INTC->VSSEL132; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* Timer6 Ch.3 A compare match */ + if (1ul == bM4_TMR63_ICONR_INTENA) + { + if ((1ul == bM4_TMR63_STFLR_CMAF) && (VSSEL132 & BIT_MASK_00)) + { + Timer63GCMA_IrqHandler(); + } + } + /* Timer6 Ch.3 B compare match */ + if (1ul == bM4_TMR63_ICONR_INTENB) + { + if ((1ul == bM4_TMR63_STFLR_CMBF) && (VSSEL132 & BIT_MASK_01)) + { + Timer63GCMB_IrqHandler(); + } + } + /* Timer6 Ch.3 C compare match */ + if (1ul == bM4_TMR63_ICONR_INTENC) + { + if ((1ul == bM4_TMR63_STFLR_CMCF) && (VSSEL132 & BIT_MASK_02)) + { + Timer63GCMC_IrqHandler(); + } + } + /* Timer6 Ch.3 D compare match */ + if (1ul == bM4_TMR63_ICONR_INTEND) + { + if ((1ul == bM4_TMR63_STFLR_CMDF) && (VSSEL132 & BIT_MASK_03)) + { + Timer63GCMD_IrqHandler(); + } + } + /* Timer6 Ch.3 E compare match */ + if (1ul == bM4_TMR63_ICONR_INTENE) + { + if ((1ul == bM4_TMR63_STFLR_CMEF) && (VSSEL132 & BIT_MASK_04)) + { + Timer63GCME_IrqHandler(); + } + } + /* Timer6 Ch.3 F compare match */ + if (1ul == bM4_TMR63_ICONR_INTENF) + { + if ((1ul == bM4_TMR63_STFLR_CMFF) && (VSSEL132 & BIT_MASK_05)) + { + Timer63GCMF_IrqHandler(); + } + } + /* Timer6 Ch.3 overflow */ + if (1ul == bM4_TMR63_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR63_STFLR_OVFF) && (VSSEL132 & BIT_MASK_06)) + { + Timer63GOV_IrqHandler(); + } + } + /* Timer6 Ch.3 underflow */ + if (1ul == bM4_TMR63_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR63_STFLR_UDFF) && (VSSEL132 & BIT_MASK_07)) + { + Timer63GUD_IrqHandler(); + } + } + /* Timer6 Ch.3 dead time */ + if (1ul == bM4_TMR63_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR63_STFLR_DTEF)) && (VSSEL132 & BIT_MASK_08)) + { + Timer63GDT_IrqHandler(); + } + } + /* Timer6 Ch.3 A up-down compare match */ + u32Tmp1 = (M4_TMR63->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR63->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL132 & BIT_MASK_11)) + { + Timer63SCMA_IrqHandler(); + } + /* Timer6 Ch.3 B up-down compare match */ + u32Tmp1 = (M4_TMR63->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR63->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL132 & BIT_MASK_12)) + { + Timer63SCMB_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.136 share IRQ handler + ** + ******************************************************************************/ +void IRQ136_Handler(void) +{ + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + uint32_t VSSEL136 = M4_INTC->VSSEL136; + + u32Tmp1 = M4_TMRA1->BCSTR; + /* TimerA Ch.1 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_00)) + { + TimerA1OV_IrqHandler(); + } + /* TimerA Ch.1 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_01)) + { + TimerA1UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA1->ICONR; + u32Tmp2 = M4_TMRA1->STFLR; + /* TimerA Ch.1 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_02)) + { + TimerA1CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA2->BCSTR; + /* TimerA Ch.2 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_03)) + { + TimerA2OV_IrqHandler(); + } + /* TimerA Ch.2 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_04)) + { + TimerA2UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA2->ICONR; + u32Tmp2 = M4_TMRA2->STFLR; + /* TimerA Ch.2 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_05)) + { + TimerA2CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA3->BCSTR; + /* TimerA Ch.3 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_06)) + { + TimerA3OV_IrqHandler(); + } + /* TimerA Ch.3 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_07)) + { + TimerA3UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA3->ICONR; + u32Tmp2 = M4_TMRA3->STFLR; + /* TimerA Ch.3 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_08)) + { + TimerA3CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA4->BCSTR; + /* TimerA Ch.4 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_09)) + { + TimerA4OV_IrqHandler(); + } + /* TimerA Ch.4 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_10)) + { + TimerA4UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA4->ICONR; + u32Tmp2 = M4_TMRA4->STFLR; + /* TimerA Ch.4 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_11)) + { + TimerA4CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA5->BCSTR; + /* TimerA Ch.5 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_12)) + { + TimerA5OV_IrqHandler(); + } + /* TimerA Ch.5 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_13)) + { + TimerA5UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA5->ICONR; + u32Tmp2 = M4_TMRA5->STFLR; + /* TimerA Ch.5 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_14)) + { + TimerA5CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA6->BCSTR; + /* TimerA Ch.6 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_16)) + { + TimerA6OV_IrqHandler(); + } + /* TimerA Ch.6 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_17)) + { + TimerA6UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA6->ICONR; + u32Tmp2 = M4_TMRA6->STFLR; + /* TimerA Ch.6 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_18)) + { + TimerA6CMP_IrqHandler(); + } + /* USBFS global interrupt */ + if(1ul == bM4_USBFS_GAHBCFG_GINTMSK) + { + u32Tmp1 = M4_USBFS->GINTMSK & 0xF77CFCFBul; + u32Tmp2 = M4_USBFS->GINTSTS & 0xF77CFCFBul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL136 & BIT_MASK_19)) + { + UsbGlobal_IrqHandler(); + } + } + + u32Tmp1 = M4_USART1->SR; + u32Tmp2 = M4_USART1->CR1; + /* USART Ch.1 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL136 & BIT_MASK_22)) + { + Usart1RxErr_IrqHandler(); + } + /* USART Ch.1 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL136 & BIT_MASK_23)) + { + Usart1RxEnd_IrqHandler(); + } + /* USART Ch.1 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL136 & BIT_MASK_24)) + { + Usart1TxEmpty_IrqHandler(); + } + /* USART Ch.1 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL136 & BIT_MASK_25)) + { + Usart1TxEnd_IrqHandler(); + } + /* USART Ch.1 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL136 & BIT_MASK_26)) + { + Usart1RxTO_IrqHandler(); + } + + u32Tmp1 = M4_USART2->SR; + u32Tmp2 = M4_USART2->CR1; + /* USART Ch.2 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL136 & BIT_MASK_27)) + { + Usart2RxErr_IrqHandler(); + } + /* USART Ch.2 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL136 & BIT_MASK_28)) + { + Usart2RxEnd_IrqHandler(); + } + /* USART Ch.2 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL136 & BIT_MASK_29)) + { + Usart2TxEmpty_IrqHandler(); + } + /* USART Ch.2 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL136 & BIT_MASK_30)) + { + Usart2TxEnd_IrqHandler(); + } + /* USART Ch.2 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL136 & BIT_MASK_31)) + { + Usart2RxTO_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.137 share IRQ handler + ** + ******************************************************************************/ +void IRQ137_Handler(void) +{ + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + uint32_t VSSEL137 = M4_INTC->VSSEL137; + + u32Tmp1 = M4_USART3->SR; + u32Tmp2 = M4_USART3->CR1; + /* USART Ch.3 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL137 & BIT_MASK_00)) + { + Usart3RxErr_IrqHandler(); + } + /* USART Ch.3 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_01)) + { + Usart3RxEnd_IrqHandler(); + } + /* USART Ch.3 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_02)) + { + Usart3TxEmpty_IrqHandler(); + } + /* USART Ch.3 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL137 & BIT_MASK_03)) + { + Usart3TxEnd_IrqHandler(); + } + /* USART Ch.3 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL137 & BIT_MASK_04)) + { + Usart3RxTO_IrqHandler(); + } + + u32Tmp1 = M4_USART4->SR; + u32Tmp2 = M4_USART4->CR1; + /* USART Ch.4 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL137 & BIT_MASK_05)) + { + Usart4RxErr_IrqHandler(); + } + /* USART Ch.4 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_06)) + { + Usart4RxEnd_IrqHandler(); + } + /* USART Ch.4 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_07)) + { + Usart4TxEmpty_IrqHandler(); + } + /* USART Ch.4 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL137 & BIT_MASK_08)) + { + Usart4TxEnd_IrqHandler(); + } + /* USART Ch.4 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL137 & BIT_MASK_09)) + { + Usart4RxTO_IrqHandler(); + } + + u32Tmp1 = M4_SPI1->CR1; + u32Tmp2 = M4_SPI1->SR; + /* SPI Ch.1 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_11)) + { + Spi1RxEnd_IrqHandler(); + } + /* SPI Ch.1 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_12)) + { + Spi1TxEmpty_IrqHandler(); + } + /* SPI Ch.1 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_13)) + { + Spi1Idle_IrqHandler(); + } + /* SPI Ch.1 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_14)) + { + Spi1Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI2->CR1; + u32Tmp2 = M4_SPI2->SR; + /* SPI Ch.2 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_16)) + { + Spi2RxEnd_IrqHandler(); + } + /* SPI Ch.2 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_17)) + { + Spi2TxEmpty_IrqHandler(); + } + /* SPI Ch.2 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_18)) + { + Spi2Idle_IrqHandler(); + } + /* SPI Ch.2 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_19)) + { + Spi2Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI3->CR1; + u32Tmp2 = M4_SPI3->SR; + /* SPI Ch.3 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_21)) + { + Spi3RxEnd_IrqHandler(); + } + /* SPI Ch.3 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_22)) + { + Spi3TxEmpty_IrqHandler(); + } + /* SPI Ch.3 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_23)) + { + Spi3Idle_IrqHandler(); + } + /* SPI Ch.3 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_24)) + { + Spi3Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI4->CR1; + u32Tmp2 = M4_SPI4->SR; + /* SPI Ch.4 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_26)) + { + Spi4RxEnd_IrqHandler(); + } + /* SPI Ch.4 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_27)) + { + Spi4TxEmpty_IrqHandler(); + } + /* SPI Ch.4 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_28)) + { + Spi4Idle_IrqHandler(); + } + /* SPI Ch.4 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_29)) + { + Spi4Err_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.138 share IRQ handler + ** + ******************************************************************************/ +void IRQ138_Handler(void) +{ + uint32_t u32Tmp1 = 0u; + uint32_t VSSEL138 = M4_INTC->VSSEL138; + + u32Tmp1 = M4_TMR41->OCSRU; + /* Timer4 Ch.1 U phase higher compare match */ + if ((VSSEL138 & BIT_MASK_00) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMUH_IrqHandler(); + } + /* Timer4 Ch.1 U phase lower compare match */ + if ((VSSEL138 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->OCSRV; + /* Timer4 Ch.1 V phase higher compare match */ + if ((VSSEL138 & BIT_MASK_02) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMVH_IrqHandler(); + } + /* Timer4 Ch.1 V phase lower compare match */ + if ((VSSEL138 & BIT_MASK_03) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->OCSRW; + /* Timer4 Ch.1 W phase higher compare match */ + if ((VSSEL138 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMWH_IrqHandler(); + } + /* Timer4 Ch.1 W phase lower compare match */ + if ((VSSEL138 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->CCSR; + /* Timer4 Ch.1 overflow */ + if ((VSSEL138 & BIT_MASK_06) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer41GOV_IrqHandler(); + } + /* Timer4 Ch.1 underflow */ + if ((VSSEL138 & BIT_MASK_07) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer41GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->RCSR; + /* Timer4 Ch.1 U phase reload */ + if ((VSSEL138 & BIT_MASK_08) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer41ReloadU_IrqHandler(); + } + /* Timer4 Ch.1 V phase reload */ + if ((VSSEL138 & BIT_MASK_09) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer41ReloadV_IrqHandler(); + } + /* Timer4 Ch.1 W phase reload */ + if ((VSSEL138 & BIT_MASK_10) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer41ReloadW_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRU; + /* Timer4 Ch.2 U phase higher compare match */ + if ((VSSEL138 & BIT_MASK_16) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMUH_IrqHandler(); + } + /* Timer4 Ch.2 U phase lower compare match */ + if ((VSSEL138 & BIT_MASK_17) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRV; + /* Timer4 Ch.2 V phase higher compare match */ + if ((VSSEL138 & BIT_MASK_18) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer42GCMVH_IrqHandler(); + } + /* Timer4 Ch.2 V phase lower compare match */ + if ((VSSEL138 & BIT_MASK_19) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer42GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRW; + /* Timer4 Ch.2 W phase higher compare match */ + if ((VSSEL138 & BIT_MASK_20) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer42GCMWH_IrqHandler(); + } + /* Timer4 Ch.2 W phase lower compare match */ + if ((VSSEL138 & BIT_MASK_21) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer42GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->CCSR; + /* Timer4 Ch.2 overflow */ + if ((VSSEL138 & BIT_MASK_22) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer42GOV_IrqHandler(); + } + /* Timer4 Ch.2 underflow */ + if ((VSSEL138 & BIT_MASK_23) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer42GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->RCSR; + /* Timer4 Ch.2 U phase reload */ + if ((VSSEL138 & BIT_MASK_24) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer42ReloadU_IrqHandler(); + } + /* Timer4 Ch.2 V phase reload */ + if ((VSSEL138 & BIT_MASK_25) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer42ReloadV_IrqHandler(); + } + /* Timer4 Ch.2 W phase reload */ + if ((VSSEL138 & BIT_MASK_26) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer42ReloadW_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.139 share IRQ handler + ** + ******************************************************************************/ +void IRQ139_Handler(void) +{ + uint32_t u32Tmp1 = 0u; + uint32_t VSSEL139 = M4_INTC->VSSEL139; + + u32Tmp1 = M4_TMR43->OCSRU; + /* Timer4 Ch.3 U phase higher compare match */ + if ((VSSEL139 & BIT_MASK_00) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMUH_IrqHandler(); + } + /* Timer4 Ch.3 U phase lower compare match */ + if ((VSSEL139 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->OCSRV; + /* Timer4 Ch.3 V phase higher compare match */ + if ((VSSEL139 & BIT_MASK_02) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMVH_IrqHandler(); + } + /* Timer4 Ch.3 V phase lower compare match */ + if ((VSSEL139 & BIT_MASK_03) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->OCSRW; + /* Timer4 Ch.3 W phase higher compare match */ + if ((VSSEL139 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMWH_IrqHandler(); + } + /* Timer4 Ch.3 W phase lower compare match */ + if ((VSSEL139 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->CCSR; + /* Timer4 Ch.3 overflow */ + if ((VSSEL139 & BIT_MASK_06) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer43GOV_IrqHandler(); + } + /* Timer4 Ch.3 underflow */ + if ((VSSEL139 & BIT_MASK_07) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer43GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->RCSR; + /* Timer4 Ch.3 U phase reload */ + if ((VSSEL139 & BIT_MASK_08) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer41ReloadU_IrqHandler(); + } + /* Timer4 Ch.3 V phase reload */ + if ((VSSEL139 & BIT_MASK_09) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer43ReloadV_IrqHandler(); + } + /* Timer4 Ch.3 W phase reload */ + if ((VSSEL139 & BIT_MASK_10) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer43ReloadW_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.140 share IRQ handler + ** + ******************************************************************************/ +void IRQ140_Handler(void) +{ + uint32_t VSSEL140 = M4_INTC->VSSEL140; + uint32_t u32Tmp1 = 0u; + uint32_t u32Tmp2 = 0u; + /* EMB1 */ + u32Tmp1 = M4_EMB1->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB1->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_06)) + { + Emb1_IrqHandler(); + } + /* EMB2 */ + u32Tmp1 = M4_EMB2->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB2->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_07)) + { + Emb2_IrqHandler(); + } + /* EMB3 */ + u32Tmp1 = M4_EMB3->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB3->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_08)) + { + Emb3_IrqHandler(); + } + /* EMB4*/ + u32Tmp1 = M4_EMB4->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB4->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_09)) + { + Emb4_IrqHandler(); + } + + /* I2S Ch.1 Transmit */ + if(1ul == bM4_I2S1_CTRL_TXIE) + { + if ((1ul == bM4_I2S1_SR_TXBA) && (VSSEL140 & BIT_MASK_16)) + { + I2s1Tx_IrqHandler(); + } + } + /* I2S Ch.1 Receive */ + if(1ul == bM4_I2S1_CTRL_RXIE) + { + if ((1ul == bM4_I2S1_SR_RXBA) && (VSSEL140 & BIT_MASK_17)) + { + I2s1Rx_IrqHandler(); + } + } + /* I2S Ch.1 Error */ + if(1ul == bM4_I2S1_CTRL_EIE) + { + if ((M4_I2S1->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_18)) + { + I2s1Err_IrqHandler(); + } + } + /* I2S Ch.2 Transmit */ + if(1ul == bM4_I2S2_CTRL_TXIE) + { + if ((1ul == bM4_I2S2_SR_TXBA) && (VSSEL140 & BIT_MASK_19)) + { + I2s2Tx_IrqHandler(); + } + } + /* I2S Ch.2 Receive */ + if(1ul == bM4_I2S2_CTRL_RXIE) + { + if ((1ul == bM4_I2S2_SR_RXBA) && (VSSEL140 & BIT_MASK_20)) + { + I2s2Rx_IrqHandler(); + } + } + /* I2S Ch.2 Error */ + if(1ul == bM4_I2S2_CTRL_EIE) + { + if ((M4_I2S2->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_21)) + { + I2s2Err_IrqHandler(); + } + } + /* I2S Ch.3 Transmit */ + if(1ul == bM4_I2S3_CTRL_TXIE) + { + if ((1ul == bM4_I2S3_SR_TXBA) && (VSSEL140 & BIT_MASK_22)) + { + I2s3Tx_IrqHandler(); + } + } + /* I2S Ch.3 Receive */ + if(1ul == bM4_I2S3_CTRL_RXIE) + { + if ((1ul == bM4_I2S3_SR_RXBA) && (VSSEL140 & BIT_MASK_23)) + { + I2s3Rx_IrqHandler(); + } + } + /* I2S Ch.3 Error */ + if(1ul == bM4_I2S3_CTRL_EIE) + { + if ((M4_I2S3->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_24)) + { + I2s3Err_IrqHandler(); + } + } + /* I2S Ch.4 Transmit */ + if(1ul == bM4_I2S4_CTRL_TXIE) + { + if ((1ul == bM4_I2S4_SR_TXBA) && (VSSEL140 & BIT_MASK_25)) + { + I2s4Tx_IrqHandler(); + } + } + /* I2S Ch.4 Receive */ + if(1ul == bM4_I2S4_CTRL_RXIE) + { + if ((1ul == bM4_I2S4_SR_RXBA) && (VSSEL140 & BIT_MASK_26)) + { + I2s4Rx_IrqHandler(); + } + } + /* I2S Ch.4 Error */ + if(1ul == bM4_I2S4_CTRL_EIE) + { + if ((M4_I2S4->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_27)) + { + I2s4Err_IrqHandler(); + } + } +} + +/** + ******************************************************************************* + ** \brief Int No.141 share IRQ handler + ** + ******************************************************************************/ +void IRQ141_Handler(void) +{ + uint32_t VSSEL141 = M4_INTC->VSSEL141; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* I2C Ch.1 Receive completed */ + if(1ul == bM4_I2C1_CR2_RFULLIE) + { + if ((1ul == bM4_I2C1_SR_RFULLF) && (VSSEL141 & BIT_MASK_04)) + { + I2c1RxEnd_IrqHandler(); + } + } + /* I2C Ch.1 Transmit data empty */ + if(1ul == bM4_I2C1_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C1_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_05)) + { + I2c1TxEmpty_IrqHandler(); + } + } + /* I2C Ch.1 Transmit completed */ + if(1ul == bM4_I2C1_CR2_TENDIE) + { + if ((1ul == bM4_I2C1_SR_TENDF) && (VSSEL141 & BIT_MASK_06)) + { + I2c1TxEnd_IrqHandler(); + } + } + /* I2C Ch.1 Error */ + u32Tmp1 = M4_I2C1->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C1->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_07)) + { + I2c1Err_IrqHandler(); + } + /* I2C Ch.2 Receive completed */ + if(1ul == bM4_I2C2_CR2_RFULLIE) + { + if ((1ul == bM4_I2C2_SR_RFULLF) && (VSSEL141 & BIT_MASK_08)) + { + I2c2RxEnd_IrqHandler(); + } + } + /* I2C Ch.2 Transmit data empty */ + if(1ul == bM4_I2C2_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C2_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_09)) + { + I2c2TxEmpty_IrqHandler(); + } + } + /* I2C Ch.2 Transmit completed */ + if(1ul == bM4_I2C2_CR2_TENDIE) + { + if ((1ul == bM4_I2C2_SR_TENDF) && (VSSEL141 & BIT_MASK_10)) + { + I2c2TxEnd_IrqHandler(); + } + } + /* I2C Ch.2 Error */ + u32Tmp1 = M4_I2C2->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C2->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_11)) + { + I2c2Err_IrqHandler(); + } + /* I2C Ch.3 Receive completed */ + if(1ul == bM4_I2C3_CR2_RFULLIE) + { + if ((1ul == bM4_I2C3_SR_RFULLF) && (VSSEL141 & BIT_MASK_12)) + { + I2c3RxEnd_IrqHandler(); + } + } + /* I2C Ch.3 Transmit data empty */ + if(1ul == bM4_I2C3_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C3_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_13)) + { + I2c3TxEmpty_IrqHandler(); + } + } + /* I2C Ch.3 Transmit completed */ + if(1ul == bM4_I2C3_CR2_TENDIE) + { + if ((1ul == bM4_I2C3_SR_TENDF) && (VSSEL141 & BIT_MASK_14)) + { + I2c3TxEnd_IrqHandler(); + } + } + /* I2C Ch.3 Error */ + u32Tmp1 = M4_I2C3->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C3->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_15)) + { + I2c3Err_IrqHandler(); + } + /* PVD Ch.1 detected */ + if (1ul == M4_SYSREG->PWR_PVDDSR_f.PVD1DETFLG) + { + if((1ul == bM4_SYSREG_PWR_PVDDSR_PVD1DETFLG) && (VSSEL141 & BIT_MASK_17)) + { + Pvd1_IrqHandler(); + } + } + if (1ul == M4_SYSREG->PWR_PVDDSR_f.PVD2DETFLG) + { + /* PVD Ch.2 detected */ + if((1ul == bM4_SYSREG_PWR_PVDDSR_PVD2DETFLG) && (VSSEL141 & BIT_MASK_18)) + { + Pvd2_IrqHandler(); + } + } + /* Freq. calculate error detected */ + if(1ul == bM4_FCM_RIER_ERRIE) + { + if((1ul == bM4_FCM_SR_ERRF) && (VSSEL141 & BIT_MASK_20)) + { + FcmErr_IrqHandler(); + } + } + /* Freq. calculate completed */ + if(1ul == bM4_FCM_RIER_MENDIE) + { + if((1ul == bM4_FCM_SR_MENDF) && (VSSEL141 & BIT_MASK_21)) + { + FcmEnd_IrqHandler(); + } + } + /* Freq. calculate overflow */ + if(1ul == bM4_FCM_RIER_OVFIE) + { + if((1ul == bM4_FCM_SR_OVF) && (VSSEL141 & BIT_MASK_22)) + { + FcmOV_IrqHandler(); + } + } + + /* WDT */ + if ((M4_WDT->SR & (BIT_MASK_16 | BIT_MASK_17)) && (VSSEL141 & BIT_MASK_23)) + { + Wdt_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.142 share IRQ handler + ** + ******************************************************************************/ +void IRQ142_Handler(void) +{ + uint32_t u32VSSEL142 = M4_INTC->VSSEL142; + uint16_t u16Tmp = 0u; + /* ADC unit.1 seq. A */ + if (1ul == bM4_ADC1_ICR_EOCAIEN) + { + if ((1ul == bM4_ADC1_ISR_EOCAF) && (u32VSSEL142 & BIT_MASK_00)) + { + ADC1A_IrqHandler(); + } + } + /* ADC unit.1 seq. B */ + if (1ul == bM4_ADC1_ICR_EOCBIEN) + { + if ((1ul == bM4_ADC1_ISR_EOCBF) && (u32VSSEL142 & BIT_MASK_01)) + { + ADC1B_IrqHandler(); + } + } + /* ADC unit.1 seq. A */ + u16Tmp = M4_ADC1->AWDSR0; + if (1ul == bM4_ADC1_AWDCR_AWDIEN) + { + if (((1ul == bM4_ADC1_AWDSR1_AWDF16) || (u16Tmp)) && (u32VSSEL142 & BIT_MASK_02)) + { + ADC1ChCmp_IrqHandler(); + } + } + /* ADC unit.1 seq. cmp */ + if (1ul == bM4_ADC1_AWDCR_AWDIEN) + { + if (((1ul == bM4_ADC1_AWDSR1_AWDF16) || (u16Tmp)) && (u32VSSEL142 & BIT_MASK_03)) + { + ADC1SeqCmp_IrqHandler(); + } + } + + /* ADC unit.2 seq. A */ + if (1ul == bM4_ADC2_ICR_EOCAIEN) + { + if ((1ul == bM4_ADC2_ISR_EOCAF) && (u32VSSEL142 & BIT_MASK_04)) + { + ADC2A_IrqHandler(); + } + } + /* ADC unit.2 seq. B */ + if (1ul == bM4_ADC2_ICR_EOCBIEN) + { + if ((1ul == bM4_ADC2_ISR_EOCBF) && (u32VSSEL142 & BIT_MASK_05)) + { + ADC2B_IrqHandler(); + } + } + /* ADC unit.2 seq. A */ + if (1ul == bM4_ADC2_AWDCR_AWDIEN) + { + if ((M4_ADC2->AWDSR0 & 0x1FFu) && (u32VSSEL142 & BIT_MASK_06)) + { + ADC2ChCmp_IrqHandler(); + } + } + /* ADC unit.2 seq. cmp */ + if (1ul == bM4_ADC2_AWDCR_AWDIEN) + { + if ((M4_ADC2->AWDSR0 & 0x1FFu) && (u32VSSEL142 & BIT_MASK_07)) + { + ADC2SeqCmp_IrqHandler(); + } + } +} + +/** + ******************************************************************************* + ** \brief Int No.143 share IRQ handler + ** + ******************************************************************************/ +void IRQ143_Handler(void) +{ + uint8_t RTIF = 0u; + uint8_t RTIE = 0u; + uint8_t ERRINT = 0u; + uint8_t TTCFG = 0u; + uint16_t NORINTST = 0u; + uint16_t NORINTSGEN = 0u; + uint16_t ERRINTST = 0u; + uint16_t ERRINTSGEN = 0u; + + /* SDIO Ch.1 */ + if (1ul == bM4_INTC_VSSEL143_VSEL2) + { + NORINTST = M4_SDIOC1->NORINTST; + NORINTSGEN = M4_SDIOC1->NORINTSGEN; + ERRINTST = M4_SDIOC1->ERRINTST; + ERRINTSGEN = M4_SDIOC1->ERRINTSGEN; + + if ((NORINTST & NORINTSGEN & 0x1F7u) || (ERRINTST & ERRINTSGEN & 0x017Fu)) + { + Sdio1_IrqHandler(); + } + } + + /* SDIO Ch.2 */ + if (1ul == bM4_INTC_VSSEL143_VSEL5) + { + NORINTST = M4_SDIOC2->NORINTST; + NORINTSGEN = M4_SDIOC2->NORINTSGEN; + ERRINTST = M4_SDIOC2->ERRINTST; + ERRINTSGEN = M4_SDIOC2->ERRINTSGEN; + + if ((NORINTST & NORINTSGEN & 0x1F7u) || (ERRINTST & ERRINTSGEN & 0x017Fu)) + { + Sdio2_IrqHandler(); + } + } + + /* CAN */ + if (1ul == bM4_INTC_VSSEL143_VSEL6) + { + RTIF = M4_CAN->RTIF; + RTIE = M4_CAN->RTIE; + ERRINT = M4_CAN->ERRINT; + TTCFG = M4_CAN->TTCFG; + if ( (TTCFG & BIT_MASK_05) || \ + (RTIF & BIT_MASK_00) || \ + (RTIF & RTIE & 0xFEu) || \ + ((ERRINT & BIT_MASK_00) && (ERRINT & BIT_MASK_01)) || \ + ((ERRINT & BIT_MASK_02) && (ERRINT & BIT_MASK_03)) || \ + ((ERRINT & BIT_MASK_04) && (ERRINT & BIT_MASK_05)) || \ + ((TTCFG & BIT_MASK_03) && (TTCFG & BIT_MASK_04)) || \ + ((TTCFG & BIT_MASK_06) && (TTCFG & BIT_MASK_07))) + { + Can_IrqHandler(); + } + } +} + +#endif + +//@} // InterruptGroup + +#endif /* DDL_INTERRUPTS_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_keyscan.c b/driver/src/hc32f460_keyscan.c new file mode 100644 index 0000000..43f2fab --- /dev/null +++ b/driver/src/hc32f460_keyscan.c @@ -0,0 +1,207 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_keyscan.c + ** + ** A detailed description is available at + ** @link KeyscanGroup Keyscan module description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of keyscan. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_keyscan.h" +#include "hc32f460_utility.h" + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup KeyscanGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for Hiz cycle */ +#define IS_VALID_HIZ_CLCYE(x) \ +( ((x) == Hiz4) || \ + ((x) == Hiz8) || \ + ((x) == Hiz16) || \ + ((x) == Hiz32) || \ + ((x) == Hiz64) || \ + ((x) == Hiz256) || \ + ((x) == Hiz512) || \ + ((x) == Hiz1K)) + +/*! Parameter validity check for Low cycle */ +#define IS_VALID_LOW_CLCYE(x) \ +( ((x) == Low8) || \ + ((x) == Low16) || \ + ((x) == Low32) || \ + ((x) == Low64) || \ + ((x) == Low128) || \ + ((x) == Low256) || \ + ((x) == Low512) || \ + ((x) == Low1K) || \ + ((x) == Low2K) || \ + ((x) == Low4K) || \ + ((x) == Low8K) || \ + ((x) == Low16K) || \ + ((x) == Low32K) || \ + ((x) == Low64K) || \ + ((x) == Low128K) || \ + ((x) == Low256K) || \ + ((x) == Low512K) || \ + ((x) == Low1M) || \ + ((x) == Low2M) || \ + ((x) == Low4M) || \ + ((x) == Low8M) || \ + ((x) == Low16M)) + +/*! Parameter validity check for scan clock */ +#define IS_VALID_SCAN_CLK(x) \ +( ((x) == KeyscanHclk) || \ + ((x) == KeyscanLrc) || \ + ((x) == KeyscanXtal32)) + +/*! Parameter validity check for keyout selection */ +#define IS_VALID_KEY_OUT(x) \ +( ((x) == Keyout0To1) || \ + ((x) == Keyout0To2) || \ + ((x) == Keyout0To3) || \ + ((x) == Keyout0To4) || \ + ((x) == Keyout0To5) || \ + ((x) == Keyout0To6) || \ + ((x) == Keyout0To7)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief KEYSCAN initialization + ** + ** \param [in] pstcKeyscanConfig KEYSCAN configure structure + ** + ** \retval Ok KEYSCAN initialized + ** ErrorInvalidMode Uninitialized, cannot configure it properly + ** + ******************************************************************************/ +en_result_t KEYSCAN_Init(const stc_keyscan_config_t *pstcKeyscanConfig) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_HIZ_CLCYE(pstcKeyscanConfig->enHizCycle)); + DDL_ASSERT(IS_VALID_LOW_CLCYE(pstcKeyscanConfig->enLowCycle)); + DDL_ASSERT(IS_VALID_SCAN_CLK(pstcKeyscanConfig->enKeyscanClk)); + DDL_ASSERT(IS_VALID_KEY_OUT(pstcKeyscanConfig->enKeyoutSel)); + + /* cannot configure keyscan control register when running */ + if (Set == M4_KEYSCAN->SER_f.SEN) + { + enRet = ErrorInvalidMode; + } + else + { + M4_KEYSCAN->SCR_f.T_HIZ = pstcKeyscanConfig->enHizCycle; + M4_KEYSCAN->SCR_f.T_LLEVEL = pstcKeyscanConfig->enLowCycle; + M4_KEYSCAN->SCR_f.CKSEL = pstcKeyscanConfig->enKeyscanClk; + M4_KEYSCAN->SCR_f.KEYOUTSEL = pstcKeyscanConfig->enKeyoutSel; + M4_KEYSCAN->SCR_f.KEYINSEL = pstcKeyscanConfig->u16KeyinSel; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief KEYSCAN de-initialization + ** + ** \param None + ** + ** \retval Ok KEYSCAN de-initialized + ** + ******************************************************************************/ +en_result_t KEYSCAN_DeInit(void) +{ + M4_KEYSCAN->SER = 0ul; + M4_KEYSCAN->SCR = 0ul; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Start keyscan function + ** + ** \param None + ** + ** \retval Ok Keyscan function started + ** + ******************************************************************************/ +en_result_t KEYSCAN_Start(void) +{ + M4_KEYSCAN->SER_f.SEN = Set; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Stop keyscan function + ** + ** \param None + ** + ** \retval Ok Keyscan function stopped + ** + ******************************************************************************/ +en_result_t KEYSCAN_Stop(void) +{ + M4_KEYSCAN->SER_f.SEN = Reset; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get Key column index + ** + ** \param None + ** + ** \retval uint8_t Index of KEYOUT + ** + ******************************************************************************/ +uint8_t KEYSCAN_GetColIdx(void) +{ + return (uint8_t)(M4_KEYSCAN->SSR_f.INDEX); +} + +//@} // KeyscanGroup + +#endif /* DDL_KEYSCAN_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_mpu.c b/driver/src/hc32f460_mpu.c new file mode 100644 index 0000000..d0b3940 --- /dev/null +++ b/driver/src/hc32f460_mpu.c @@ -0,0 +1,1057 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_mpu.c + ** + ** A detailed description is available at + ** @link MpuGroup MPU description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of MPU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_mpu.h" +#include "hc32f460_utility.h" + +#if (DDL_MPU_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup MpuGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for MPU region number. */ +#define IS_VALID_MPU_REGION_NUM(x) \ +( (MpuRegionNum0 == (x)) || \ + (MpuRegionNum1 == (x)) || \ + (MpuRegionNum2 == (x)) || \ + (MpuRegionNum3 == (x)) || \ + (MpuRegionNum4 == (x)) || \ + (MpuRegionNum5 == (x)) || \ + (MpuRegionNum6 == (x)) || \ + (MpuRegionNum7 == (x)) || \ + (MpuRegionNum8 == (x)) || \ + (MpuRegionNum9 == (x)) || \ + (MpuRegionNum10 == (x)) || \ + (MpuRegionNum11 == (x)) || \ + (MpuRegionNum12 == (x)) || \ + (MpuRegionNum13 == (x)) || \ + (MpuRegionNum14 == (x)) || \ + (MpuRegionNum15 == (x))) + +/*!< Parameter valid check for MPU region size. */ +#define IS_VALID_MPU_REGION_SIZE(x) \ +( (MpuRegionSize32Byte == (x)) || \ + (MpuRegionSize64Byte == (x)) || \ + (MpuRegionSize128Byte == (x)) || \ + (MpuRegionSize256Byte == (x)) || \ + (MpuRegionSize512Byte == (x)) || \ + (MpuRegionSize1KByte == (x)) || \ + (MpuRegionSize2KByte == (x)) || \ + (MpuRegionSize4KByte == (x)) || \ + (MpuRegionSize8KByte == (x)) || \ + (MpuRegionSize16KByte == (x)) || \ + (MpuRegionSize32KByte == (x)) || \ + (MpuRegionSize64KByte == (x)) || \ + (MpuRegionSize128KByte == (x)) || \ + (MpuRegionSize256KByte == (x)) || \ + (MpuRegionSize512KByte == (x)) || \ + (MpuRegionSize1MByte == (x)) || \ + (MpuRegionSize2MByte == (x)) || \ + (MpuRegionSize4MByte == (x)) || \ + (MpuRegionSize8MByte == (x)) || \ + (MpuRegionSize16MByte == (x)) || \ + (MpuRegionSize32MByte == (x)) || \ + (MpuRegionSize64MByte == (x)) || \ + (MpuRegionSize128MByte == (x)) || \ + (MpuRegionSize256MByte == (x)) || \ + (MpuRegionSize512MByte == (x)) || \ + (MpuRegionSize1GByte == (x)) || \ + (MpuRegionSize2GByte == (x)) || \ + (MpuRegionSize4GByte == (x))) + +/*!< Parameter valid check for MPU region type. */ +#define IS_VALID_MPU_REGION_TYPE(x) \ +( (SMPU1Region == (x)) || \ + (SMPU2Region == (x)) || \ + (FMPURegion == (x))) + +/*!< Parameter valid check for MPU action. */ +#define IS_VALID_MPU_ACTION(x) \ +( (MpuTrigNmi == (x)) || \ + (MpuTrigReset == (x)) || \ + (MpuNoneAction == (x)) || \ + (MpuTrigBusError == (x))) + +/******************************************************************************/ +/* MPU */ +/******************************************************************************/ +/*!< Get the RGD register address of the specified MPU region */ +#define MPU_RGDx(__REGION_NUM__) ((uint32_t)(&M4_MPU->RGD0) + ((uint32_t)(__REGION_NUM__)) * 4u) + +/*!< Get the RGCR register address of the specified MPU region */ +#define MPU_RGCRx(__REGION_NUM__) ((uint32_t)(&M4_MPU->RGCR0) + ((uint32_t)(__REGION_NUM__)) * 4u) + +/*!< MPU RGD register: RGADDR position */ +#define MPU_RGD_RGADDR_Pos (5u) /*!< MPU_RGD: RGADDR Position */ + +/*!< MPU write protection key */ +#define MPU_WRITE_PROT_KEY (0x96A4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Configure MPU protect region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] pstcInitCfg Pointer to MPU protection region configuration structure + ** \arg the structure detail refer @ref stc_mpu_prot_region_init_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - pstcInitCfg == NULL + ** - pstcInitCfg->u32RegionBaseAddress is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t MPU_ProtRegionInit(en_mpu_region_num_t enRegionNum, + const stc_mpu_prot_region_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32WriteProt = M4_MPU->WP; + stc_mpu_rgd0_field_t *RGD_f = NULL; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + /* Check pointer parameters */ + if (NULL != pstcInitCfg) + { + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_SIZE(pstcInitCfg->enRegionSize)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcSMPU1Permission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enReadEnable)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcSMPU2Permission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enReadEnable)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcFMPUPermission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enReadEnable)); + + /* Check base address and region size */ + if (!(pstcInitCfg->u32RegionBaseAddress & (~ (0xFFFFFFFFUL << ((uint32_t)pstcInitCfg->enRegionSize + 1UL))))) + { + /* Disable write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | 1ul); + + /* Get RGD && RGCR register address */ + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + /* Disable region protection function */ + RGCR_f->FRG0E = (uint32_t)0ul; + RGCR_f->S1RG0E = (uint32_t)0ul; + RGCR_f->S2RG0E = (uint32_t)0ul; + + /* Set region size */ + RGD_f->MPURG0SIZE = (uint32_t)(pstcInitCfg->enRegionSize); + + /* Set region base address */ + RGD_f->MPURG0ADDR = (pstcInitCfg->u32RegionBaseAddress >> MPU_RGD_RGADDR_Pos); + + /* Set region FMPU */ + RGCR_f->FRG0RP = (pstcInitCfg->stcFMPUPermission.enReadEnable) ? 0ul : 1ul; + RGCR_f->FRG0WP = (pstcInitCfg->stcFMPUPermission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->FRG0E = (uint32_t)(pstcInitCfg->stcFMPUPermission.enRegionEnable); + M4_MPU->CR_f.FMPUACT = (uint32_t)(pstcInitCfg->stcFMPUPermission.enAction); + + /* Set region SMPU1 */ + RGCR_f->S1RG0RP = (pstcInitCfg->stcSMPU1Permission.enReadEnable) ? 0ul : 1ul; + RGCR_f->S1RG0WP = (pstcInitCfg->stcSMPU1Permission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->S1RG0E = (uint32_t)(pstcInitCfg->stcSMPU1Permission.enRegionEnable); + M4_MPU->CR_f.SMPU1ACT = (uint32_t)(pstcInitCfg->stcSMPU1Permission.enAction); + + /* Set region SMPU2 */ + RGCR_f->S2RG0RP = (pstcInitCfg->stcSMPU2Permission.enReadEnable) ? 0ul : 1ul; + RGCR_f->S2RG0WP = (pstcInitCfg->stcSMPU2Permission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->S2RG0E = (uint32_t)(pstcInitCfg->stcSMPU2Permission.enRegionEnable); + M4_MPU->CR_f.SMPU2ACT = (uint32_t)(pstcInitCfg->stcSMPU2Permission.enAction); + + /* Recover write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | u32WriteProt); + enRet = Ok; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure MPU background region. + ** + ** \param [in] pstcInitCfg Pointer to MPU background region configuration structure + ** \arg the structure detail refer @ref stc_mpu_bkgd_region_init_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - pstcInitCfg == NULL + ** - pstcInitCfg->u32RegionBaseAddress is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t MPU_BkgdRegionInit(const stc_mpu_bkgd_region_init_t *pstcInitCfg) +{ + uint32_t u32WriteProt = M4_MPU->WP; + en_result_t enRet = ErrorInvalidParameter; + + /* Check pointer parameters */ + if (NULL != pstcInitCfg) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1BkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1BkgdPermission.enReadEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2BkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2BkgdPermission.enReadEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUBkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUBkgdPermission.enReadEnable)); + + /* Disable write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | 1ul); + + /* Set SMPU1 */ + M4_MPU->CR_f.SMPU1BWP = (pstcInitCfg->stcSMPU1BkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.SMPU1BRP = (pstcInitCfg->stcSMPU1BkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Set SMPU2 */ + M4_MPU->CR_f.SMPU2BWP = (pstcInitCfg->stcSMPU2BkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.SMPU2BRP = (pstcInitCfg->stcSMPU2BkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Set FMPU */ + M4_MPU->CR_f.FMPUBWP = (pstcInitCfg->stcFMPUBkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.FMPUBRP = (pstcInitCfg->stcFMPUBkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Recover write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | u32WriteProt); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU size of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enRegionSize MPU region size + ** \arg This parameter can be a value of @ref en_mpu_region_size_t + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_SetRegionSize(en_mpu_region_num_t enRegionNum, + en_mpu_region_size_t enRegionSize) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_SIZE(enRegionSize)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + RGD_f->MPURG0SIZE = (uint32_t)enRegionSize; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get MPU size of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** + ** \retval MPU size of the specified region. + ** + ******************************************************************************/ +en_mpu_region_size_t MPU_GetRegionSize(en_mpu_region_num_t enRegionNum) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + + return (en_mpu_region_size_t)(RGD_f->MPURG0SIZE); +} + +/** + ******************************************************************************* + ** \brief Set MPU base address of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] u32RegionBaseAddr the specified base address + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_SetRegionBaseAddress(en_mpu_region_num_t enRegionNum, + uint32_t u32RegionBaseAddr) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + RGD_f->MPURG0ADDR = (u32RegionBaseAddr >> MPU_RGD_RGADDR_Pos); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get MPU base address of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t +s ** + ** \retval MPU base address of the specified region. + ** + ******************************************************************************/ +uint32_t MPU_GetRegionBaseAddress(en_mpu_region_num_t enRegionNum) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + + return (RGD_f->MPURG0ADDR << MPU_RGD_RGADDR_Pos); +} + +/** + ******************************************************************************* + ** \brief Set the action of the specified MPU region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enActionSel MPU action + ** \arg MpuNoneAction MPU don't action. + ** \arg MpuTrigBusError MPU trigger bus error + ** \arg MpuTrigNmi MPU trigger bus NMI interrupt + ** \arg MpuTrigReset MPU trigger reset + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enActionSel is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType, + en_mpu_action_sel_t enActionSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_MPU_ACTION(enActionSel)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1ACT = (uint32_t)enActionSel; + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2ACT = (uint32_t)enActionSel; + break; + case FMPURegion: + M4_MPU->CR_f.FMPUACT = (uint32_t)enActionSel; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the action of the specified MPU region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval MpuNoneAction MPU don't action. + ** \retval MpuTrigBusError MPU trigger bus error + ** \retval MpuTrigNmi MPU trigger bus NMI interrupt + ** \retval MpuTrigReset MPU trigger reset + ** + ******************************************************************************/ +en_mpu_action_sel_t MPU_GetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32ActionSel = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32ActionSel = M4_MPU->CR_f.SMPU1ACT; + break; + case SMPU2Region: + u32ActionSel = M4_MPU->CR_f.SMPU2ACT; + break; + case FMPURegion: + u32ActionSel = M4_MPU->CR_f.FMPUACT; + break; + default: + break; + } + + return (en_mpu_action_sel_t)(u32ActionSel); +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region and type. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region function + ** \arg Disable Disable the specified MPU region function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_ProtRegionCmd(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0E = (uint32_t)enState; + break; + case SMPU2Region: + RGCR_f->S2RG0E = (uint32_t)enState; + break; + case FMPURegion: + RGCR_f->FRG0E = (uint32_t)enState; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified type region function of MPU + ** \arg Disable Disable the specified type region function of MPU + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_RegionTypeCmd(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1E = (uint32_t)enState; + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2E = (uint32_t)enState; + break; + case FMPURegion: + M4_MPU->CR_f.FMPUE = (uint32_t)enState; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU status + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enMpuRegionType is invalid. + ** + ******************************************************************************/ +en_flag_status_t MPU_GetStatus(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32Flag = 0ul; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32Flag = M4_MPU->SR_f.SMPU1EAF; + break; + case SMPU2Region: + u32Flag = M4_MPU->SR_f.SMPU2EAF; + break; + case FMPURegion: + u32Flag = M4_MPU->SR_f.FMPUEAF; + break; + default: + break; + } + + return (en_flag_status_t)(u32Flag); +} + +/** + ******************************************************************************* + ** \brief Clear MPU status. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_ClearStatus(en_mpu_region_type_t enMpuRegionType) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->ECLR_f.SMPU1ECLR = 1u; + break; + case SMPU2Region: + M4_MPU->ECLR_f.SMPU2ECLR = 1u; + break; + case FMPURegion: + M4_MPU->ECLR_f.FMPUECLR = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU read permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region read permission + ** \arg Disable Disable the specified MPU region read permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0RP = (Enable == enState) ? 0ul : 1ul; + break; + case SMPU2Region: + RGCR_f->S2RG0RP = (Enable == enState) ? 0ul : 1ul; + break; + case FMPURegion: + RGCR_f->FRG0RP = (Enable == enState) ? 0ul : 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU read permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = RGCR_f->S1RG0RP; + break; + case SMPU2Region: + u32State = RGCR_f->S2RG0RP; + break; + case FMPURegion: + u32State = RGCR_f->FRG0RP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU write permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region write permission + ** \arg Disable Disable the specified MPU region write permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + RGCR_f->S2RG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + RGCR_f->FRG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU write permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = RGCR_f->S1RG0WP; + break; + case SMPU2Region: + u32State = RGCR_f->S2RG0WP; + break; + case FMPURegion: + u32State = RGCR_f->FRG0WP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU read permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region read permission + ** \arg Disable Disable the specified MPU region read permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1BRP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2BRP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + M4_MPU->CR_f.FMPUBRP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU read permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = M4_MPU->CR_f.SMPU1BRP; + break; + case SMPU2Region: + u32State = M4_MPU->CR_f.SMPU2BRP; + break; + case FMPURegion: + u32State = M4_MPU->CR_f.FMPUBRP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU write permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region write permission + ** \arg Disable Disable the specified MPU region write permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1BWP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2BWP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + M4_MPU->CR_f.FMPUBWP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU write permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = M4_MPU->CR_f.SMPU1BWP; + break; + case SMPU2Region: + u32State = M4_MPU->CR_f.SMPU2BWP; + break; + case FMPURegion: + u32State = M4_MPU->CR_f.FMPUBWP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region and type. + ** + ** \param [in] enState MPU write protection state + ** \arg Enable Enable the write protection function + ** \arg Disable Disable the write protection function + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_WriteProtCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + M4_MPU->WP = (MPU_WRITE_PROT_KEY | ((Enable == enState) ? 0ul : 1ul)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Enable the specified IP Write/Read protection. + ** + ** \param [in] u32ProtMode Ip protection mode + ** \arg AesReadProt AES read protection + ** \arg AesWriteProt AES write protection + ** \arg HashReadProt HASH read protection + ** \arg HashWriteProt HASH write protection + ** \arg TrngReadProt TRNG read protection + ** \arg TrngWriteProt TRNG write protection + ** \arg CrcReadProt CRC read protection + ** \arg CrcWriteProt CRC write protection + ** \arg FmcReadProt FMC read protection + ** \arg FmcWriteProt FMC write protection + ** \arg WdtReadProt WDT read protection + ** \arg WdtWriteProt WDT write protection + ** \arg SwdtReadProt WDT read protection + ** \arg SwdtWriteProt WDT write protection + ** \arg BksramReadProt BKSRAM read protection + ** \arg BksramWriteProt BKSRAM write protection + ** \arg RtcReadProt RTC read protection + ** \arg RtcWriteProt RTC write protection + ** \arg DmpuReadProt DMPU read protection + ** \arg DmpuWriteProt DMPU write protection + ** \arg SramcReadProt SRAMC read protection + ** \arg SramcWriteProt SRAMC write protection + ** \arg IntcReadProt INTC read protection + ** \arg IntcWriteProt INTC write protection + ** \arg SyscReadProt SYSC read protection + ** \arg SyscWriteProt SYSC write protection + ** \arg MstpWriteProt MSTP write protection + ** \arg MstpWriteProt MSTP write protection + ** \arg BusErrProt BUSERR write protection + ** \param [in] enState MPU IP protection state + ** \arg Enable Enable the IP protection function + ** \arg Disable Disable the IP protection function + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_IpProtCmd(uint32_t u32ProtMode, + en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if(Enable == enState) + { + M4_SYSREG->MPU_IPPR |= u32ProtMode; + } + else + { + M4_SYSREG->MPU_IPPR &= (~u32ProtMode); + } + + return Ok; +} + +//@} // MpuGroup + +#endif /* DDL_MPU_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_ots.c b/driver/src/hc32f460_ots.c new file mode 100644 index 0000000..74ddaba --- /dev/null +++ b/driver/src/hc32f460_ots.c @@ -0,0 +1,386 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_ots.c + ** + ** A detailed description is available at + ** @link OtsGroup Ots description @endlink + ** + ** - 2018-10-26 CDT First version for Device Driver Library of Ots. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_ots.h" +#include "hc32f460_utility.h" + +#if (DDL_OTS_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup OtsGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for OTS auto off configuration value. */ +#define IS_OTS_AUTO_OFF(EN) \ +( ((EN) == OtsAutoOff_Disable) || \ + ((EN) == OtsAutoOff_Enable)) + +/*! Parameter validity check for OTS interrupt enable/disable. */ +#define IS_OTS_IE(IE) \ +( ((IE) == OtsInt_Disable) || \ + ((IE) == OtsInt_Enable)) + +/*! Parameter validity check for OTS clock selection configuration value. */ +#define IS_OTS_CLK_SEL(CLK) \ +( ((CLK) == OtsClkSel_Xtal) || \ + ((CLK) == OtsClkSel_Hrc)) + +/*! Parameter validity check for OTS trigger source event . */ +#define IS_OTS_TRIG_SRC_EVENT(x) \ +( (((x) >= EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/*! Parameter validity check for OTS common trigger. */ +#define IS_OTS_COM_TRIGGER(x) \ +( ((x) == OtsComTrigger_1) || \ + ((x) == OtsComTrigger_2) || \ + ((x) == OtsComTrigger_1_2)) + +#define EXPERIMENT_COUNT ((uint8_t)10) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static float32_t m_f32SlopeK = 0.0f; +static float32_t m_f32OffsetM = 0.0f; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief Initializes the OTS. + ** + ** \param [in] pstcInit See @ref stc_ots_init_t for details. + ** + ** \retval Ok No error occurred. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t OTS_Init(const stc_ots_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + DDL_ASSERT(IS_OTS_AUTO_OFF(pstcInit->enAutoOff)); + DDL_ASSERT(IS_OTS_CLK_SEL(pstcInit->enClkSel)); + + /* Stop ots sampling. */ + bM4_OTS_CTL_OTSST = 0u; + /* Disable OTS interrupt default. */ + bM4_OTS_CTL_OTSIE = OtsInt_Disable; + + bM4_OTS_CTL_TSSTP = pstcInit->enAutoOff; + bM4_OTS_CTL_OTSCK = pstcInit->enClkSel; + m_f32SlopeK = pstcInit->f32SlopeK; + m_f32OffsetM = pstcInit->f32OffsetM; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes the TRNG. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_DeInit(void) +{ + /* Stop ots sampling. */ + bM4_OTS_CTL_OTSST = 0u; + + /* Set the value of all registers to the reset value. */ + M4_OTS->CTL = 0u; + M4_OTS->DR1 = 0u; + M4_OTS->DR2 = 0u; + M4_OTS->ECR = 0u; +} + +/** + ******************************************************************************* + ** \brief Get temperature via normal mode. + ** + ** \param [out] pf32Temp The address to store the temperature value. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout OTS works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pf32Temp != NULL) + { + enRet = ErrorTimeout; + + OTS_Start(); + do + { + if (bM4_OTS_CTL_OTSST == 0ul) + { + *pf32Temp = OTS_CalculateTemp(); + enRet = Ok; + break; + } + } while (u32Timeout-- != 0ul); + OTS_Stop(); + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Enable or disable OTS interrupt. + ** + ** \param [in] enState Enable or disable OTS interrupt. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_IntCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + bM4_OTS_CTL_OTSIE = (uint32_t)enState; +} + +/** + ******************************************************************************* + ** \brief Set OTS AOS trigger source. + ** + ** \param [in] enEvent See @ref en_event_src_t for details. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_SetTriggerSrc(en_event_src_t enEvent) +{ + uint32_t u32OtrTrg = M4_AOS->OTS_TRG; + + DDL_ASSERT(IS_OTS_TRIG_SRC_EVENT(enEvent) && (EVT_OTS != enEvent)); + + u32OtrTrg &= ~0x1FFul; + u32OtrTrg |= enEvent; + + M4_AOS->OTS_TRG = u32OtrTrg; +} + +/** + ******************************************************************************* + ** \brief Enable or disable OTS common trigger. + ** + ** \param [in] enComTrigger OTS common trigger selection. See @ref en_ots_com_trigger_t for details. + ** + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_ComTriggerCmd(en_ots_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = enComTrigger; + + DDL_ASSERT(IS_OTS_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + u32ComTrig <<= 30u; + + if (enState == Enable) + { + M4_AOS->OTS_TRG |= u32ComTrig; + } + else + { + M4_AOS->OTS_TRG &= ~u32ComTrig; + } +} + +/** +******************************************************************************* +** \brief OTS scaling experiment. If you want to get a more accurate temperature value, +** you need to do a calibration experiment. +** +** \param [out] pu16Dr1 Address to store OTS data register 1. +** +** \param [out] pu16Dr2 Address to store OTS data register 2. +** +** \param [out] pu16Ecr Address to store OTS error compensation register. +** +** \param [out] pf32A Address to store parameter A(for calibration experiments). +** +** \param [in] u32Timeout Timeout value. +** +** \retval Ok No error occurred. +** \retval ErrorTimeout OTS works timeout. +** \retval ErrorInvalidParameter Parameter error. +******************************************************************************/ +en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \ + uint16_t *pu16Ecr, float32_t *pf32A, \ + uint32_t u32Timeout) +{ + float32_t f32Dr1; + float32_t f32Dr2; + float32_t f32Ecr; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu16Dr1) && (NULL != pu16Dr2) && \ + (NULL != pu16Ecr) && (NULL != pf32A)) + { + enRet = ErrorTimeout; + OTS_Start(); + do + { + if (bM4_OTS_CTL_OTSST == 0ul) + { + enRet = Ok; + break; + } + } while (u32Timeout-- != 0ul); + OTS_Stop(); + + if (enRet == Ok) + { + *pu16Dr1 = M4_OTS->DR1; + *pu16Dr2 = M4_OTS->DR2; + + f32Dr1 = (float32_t)(*pu16Dr1); + f32Dr2 = (float32_t)(*pu16Dr2); + + if (bM4_OTS_CTL_OTSCK == OtsClkSel_Hrc) + { + *pu16Ecr = M4_OTS->ECR; + f32Ecr = (float32_t)(*pu16Ecr); + } + else + { + *pu16Ecr = 1U; + f32Ecr = 1.0f; + } + + if ((*pu16Dr1 != 0U) && (*pu16Dr2 != 0U) && (*pu16Ecr != 0U)) + { + *pf32A = ((1.0f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr; + } + } + } + + return enRet; +} + + +/** +******************************************************************************* +** \brief Calculate the value of temperature. +** +** \retval A float32_t type value of temperature value. +******************************************************************************/ +float OTS_CalculateTemp(void) +{ + float32_t f32Ret = 0.0f; + uint16_t u16Dr1 = M4_OTS->DR1; + uint16_t u16Dr2 = M4_OTS->DR2; + uint16_t u16Ecr = M4_OTS->ECR; + float32_t f32Dr1 = (float32_t)u16Dr1; + float32_t f32Dr2 = (float32_t)u16Dr2; + float32_t f32Ecr = (float32_t)u16Ecr; + + if (bM4_OTS_CTL_OTSCK == OtsClkSel_Xtal) + { + f32Ecr = 1.0f; + } + + if ((u16Dr1 != 0U) && (u16Dr2 != 0U) && (u16Ecr != 0U)) + { + f32Ret = m_f32SlopeK * ((1.0f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr + m_f32OffsetM; + } + + return f32Ret; +} + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +//@} // OtsGroup + +#endif /* DDL_OTS_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_pwc.c b/driver/src/hc32f460_pwc.c new file mode 100644 index 0000000..9d0bb35 --- /dev/null +++ b/driver/src/hc32f460_pwc.c @@ -0,0 +1,2025 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_pwc.c + ** + ** A detailed description is available at + ** @link PwcGroup PWC description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of PWC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_pwc.h" +#include "hc32f460_utility.h" + +#if (DDL_PWC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup PwcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define ENABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50001u) +#define DISABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50000u) + +#define ENABLE_PWR_REG0_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa503u) +#define DISABLE_PWR_REG0_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~3u)))) + +#define ENABLE_PWR_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa502u) +#define DISABLE_PWR_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~2u)))) + +#define ENABLE_PVD_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa508u) +#define DISABLE_PVD_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~8u)))) + +/*! Parameter validity check for wake up event. */ +#define IS_PWC_WKUP_EVENT(evt) ((0x00u) != ((evt) & (0xFF))) + +/*! Parameter validity check for wake up event. */ +#define IS_PWC_WKUP2_EVENT(evt) ((0x00u) != ((evt) & (0xB7))) + +#define IS_PWC_WKUP_EDGE_EVENT(evt) ((0x00u) != ((evt) & (0x7F))) + +/*! Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP0_FLAG(flag) ((0x00u) != ((flag) & (0x7F))) + +/*! Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP1_FLAG(flag) ((0x07u) != ((flag) & (0xB8))) + +/*! Parameter validity check for power down mode. */ +#define IS_PWC_PWR_DOWN_MODE(md) \ +( ((md) == PowerDownMd1) || \ + ((md) == PowerDownMd2) || \ + ((md) == PowerDownMd3) || \ + ((md) == PowerDownMd4)) + +/*! Parameter validity check for power down wake_up time control. */ +#define IS_PWC_PWR_DOWN_WKUP_TIM(x) \ +( ((x) == Vcap01) || \ + ((x) == Vcap0047)) + +/*! Parameter validity check for IO retain state while power down. */ +#define IS_PWC_PWR_DWON_IO_STATE(x) \ +( ((x) == IoPwrDownRetain) || \ + ((x) == IoPwrRstRetain) || \ + ((x) == IoHighImp)) + +/*! Parameter validity check for driver ability while enter stop mode. */ +#define IS_PWC_STP_DRIVER_ABILITY(x) \ +( ((x) == StopHighspeed) || \ + ((x) == StopUlowspeed)) + +/*! Parameter validity check for driver ability. */ +#define IS_PWC_DRIVER_ABILITY(x) \ +( ((x) == Ulowspeed) || \ + ((x) == HighSpeed)) + +/*! Parameter validity check for dynamic voltage. */ +#define IS_PWC_DYNAMIC_VOLTAGE(val) \ +( ((val) == RunUHighspeed) || \ + ((val) == RunUlowspeed) || \ + ((val) == RunHighspeed)) + +/*! Parameter validity check for wake_up edge. */ +#define IS_PWC_EDGE_SEL(edg) \ +( ((edg) == EdgeFalling) || \ + ((edg) == EdgeRising)) + +/*! Parameter validity check for peripheral in fcg0. */ +#define IS_PWC_FCG0_PERIPH(per) \ +( (((per) & (0x700C3AEEu)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg1. */ +#define IS_PWC_FCG1_PERIPH(per) \ +( (((per) & (0xF0F00286u)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg2. */ +#define IS_PWC_FCG2_PERIPH(per) \ +( (((per) & (0xFFF87800u)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg3. */ +#define IS_PWC_FCG3_PERIPH(per) \ +( (((per) & (0xFFFFEEECu)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for clock value while stop mode mode. */ +#define IS_PWC_STOP_MODE_CLK(clk) \ +( ((clk) == ClkFix) || \ + ((clk) == ClkMrc)) + +/*! Parameter validity check for flash mode while stop mode mode. */ +#define IS_PWC_STOP_MODE_FLASH(x) \ +( ((x) == Wait) || \ + ((x) == NotWait)) + +/*! Parameter validity check for wake_up timer over flag. */ +#define IS_PWC_WKTMOVER_FLAG(flag) \ +( ((flag) == UnEqual) || \ + ((flag) == Equal)) + +/*! Parameter validity check for ram operate mode. */ +#define IS_PWC_RAM_OP_MD(x) \ +( ((x) == HighSpeedMd) || \ + ((x) == UlowSpeedMd)) + +/*! Parameter validity check for wake_up timer clock. */ +#define IS_PWC_WKTM_CLK(clk) \ +( ((clk) == Wk64hz) || \ + ((clk) == WkXtal32) || \ + ((clk) == WkLrc)) + + +/*! Parameter validity check for handle of pvd. */ +#define IS_PWC_PVD_MD(x) \ +( ((x) == PvdInt) || \ + ((x) == PvdReset)) + + +/*! Parameter validity check for pvd1 level. */ +#define IS_PWC_PVD_FILTER_CLK(clk) \ +( ((clk) == PvdLrc025) || \ + ((clk) == PvdLrc05) || \ + ((clk) == PvdLrc1) || \ + ((clk) == PvdLrc2)) + +/*! Parameter validity check for pvd2 level. */ +#define IS_PWC_PVD2_LEVEL(lvl) \ +( ((lvl) == Pvd2Level0) || \ + ((lvl) == Pvd2Level1) || \ + ((lvl) == Pvd2Level2) || \ + ((lvl) == Pvd2Level3) || \ + ((lvl) == Pvd2Level4) || \ + ((lvl) == Pvd2Level5) || \ + ((lvl) == Pvd2Level6) || \ + ((lvl) == Pvd2Level7)) + +/*! Parameter validity check for pvd1 level. */ +#define IS_PWC_PVD1_LEVEL(lvl) \ +( ((lvl) == Pvd1Level0) || \ + ((lvl) == Pvd1Level1) || \ + ((lvl) == Pvd1Level2) || \ + ((lvl) == Pvd1Level3) || \ + ((lvl) == Pvd1Level4) || \ + ((lvl) == Pvd1Level5) || \ + ((lvl) == Pvd1Level6) || \ + ((lvl) == Pvd1Level7)) + +/*! Parameter validity check for pvd interrupt. */ +#define IS_PWC_PVD_INT_SEL(x) \ +( ((x) == NonMskInt) || \ + ((x) == MskInt)) + +/*! Parameter validity check for valid wakeup source from stop mode. */ +#define IS_VALID_WKUP_SRC(x) \ +( ((x) == INT_USART1_WUPI) || \ + ((x) == INT_TMR01_GCMA) || \ + ((x) == INT_RTC_ALM) || \ + ((x) == INT_RTC_PRD) || \ + ((x) == INT_WKTM_PRD) || \ + ((x) == INT_ACMP1) || \ + ((x) == INT_PVD_PVD1) || \ + ((x) == INT_PVD_PVD2) || \ + ((x) == INT_SWDT_REFUDF) || \ + ((x) == INT_PORT_EIRQ0) || \ + ((x) == INT_PORT_EIRQ1) || \ + ((x) == INT_PORT_EIRQ2) || \ + ((x) == INT_PORT_EIRQ3) || \ + ((x) == INT_PORT_EIRQ4) || \ + ((x) == INT_PORT_EIRQ5) || \ + ((x) == INT_PORT_EIRQ6) || \ + ((x) == INT_PORT_EIRQ7) || \ + ((x) == INT_PORT_EIRQ8) || \ + ((x) == INT_PORT_EIRQ9) || \ + ((x) == INT_PORT_EIRQ10) || \ + ((x) == INT_PORT_EIRQ11) || \ + ((x) == INT_PORT_EIRQ12) || \ + ((x) == INT_PORT_EIRQ13) || \ + ((x) == INT_PORT_EIRQ14) || \ + ((x) == INT_PORT_EIRQ15)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint32_t NVIC_ISER_BAK[5]; +uint8_t u8HrcState = 0u; +uint8_t u8MrcState = 0u; +uint8_t u8WkupIntCnt = 0u; +uint8_t u8StopFlag = 0u; +uint8_t u8SysClkSrc = 1u; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The power mode configuration. + ** + ** \param [in] pstcPwrMdCfg The power mode configuration. + ** \arg enPwrDownMd The power down mode. + ** \arg enRLdo Enable or disable RLDO. + ** \arg enRetSram Enable or disable RetSram. + ** \arg enIoRetain The IO state while power down. + ** \arg enPwrDWkupTm The wake_up timer while power down. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PowerModeCfg(const stc_pwc_pwr_mode_cfg_t* pstcPwrMdCfg) +{ + DDL_ASSERT(IS_PWC_PWR_DOWN_MODE(pstcPwrMdCfg->enPwrDownMd )); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPwrMdCfg->enRLdo)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPwrMdCfg->enRetSram)); + DDL_ASSERT(IS_PWC_PWR_DWON_IO_STATE(pstcPwrMdCfg->enIoRetain)); + DDL_ASSERT(IS_PWC_PWR_DOWN_WKUP_TIM(pstcPwrMdCfg->enPwrDWkupTm)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC0 = (pstcPwrMdCfg->enPwrDownMd | + (uint8_t)(((Enable == pstcPwrMdCfg->enRLdo) ? 0u : 1u) << 2u) | + (uint8_t)(((Enable == pstcPwrMdCfg->enRetSram) ? 0u : 1u) << 3u) | + (pstcPwrMdCfg->enIoRetain << 4u)); + + M4_SYSREG->PWR_PWRC3 = (pstcPwrMdCfg->enPwrDWkupTm | (0x03)); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enter power down mode. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be put ram + ** + ******************************************************************************/ +__RAM_FUNC void PWC_EnterPowerDownMd(void) +{ + ENABLE_PVD_REG_WRITE(); + + /* Reset PVD1IRS & PVD2IRS */ + M4_SYSREG->PWR_PVDCR1 &= 0xddu; + + DISABLE_PVD_REG_WRITE(); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 1u; + + __disable_irq(); + M4_SYSREG->PWR_PWRC0_f.PWDN = 1u; + for(uint8_t i = 0u; i < 10u; i++) + { + __NOP(); + } + __enable_irq(); + + DISABLE_PWR_REG_WRITE(); + + __WFI(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup0Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN0_WKUP00 Wake_up 0_0 event + ** \arg PWC_PDWKEN0_WKUP01 Wake_up 0_1 event + ** \arg PWC_PDWKEN0_WKUP02 Wake_up 0_2 event + ** \arg PWC_PDWKEN0_WKUP03 Wake_up 0_3 event + ** \arg PWC_PDWKEN0_WKUP10 Wake_up 1_0 event + ** \arg PWC_PDWKEN0_WKUP11 Wake_up 1_1 event + ** \arg PWC_PDWKEN0_WKUP12 Wake_up 1_2 event + ** \arg PWC_PDWKEN0_WKUP13 Wake_up 1_3 event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup0Cmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP_EVENT(u32Wkup0Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE0 |= (uint8_t)u32Wkup0Event; + } + else + { + M4_SYSREG->PWR_PDWKE0 &= (uint8_t)(~u32Wkup0Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup1Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN1_WKUP20 Wake_up 2_0 event + ** \arg PWC_PDWKEN1_WKUP21 Wake_up 2_1 event + ** \arg PWC_PDWKEN1_WKUP22 Wake_up 2_2 event + ** \arg PWC_PDWKEN1_WKUP23 Wake_up 2_3 event + ** \arg PWC_PDWKEN1_WKUP30 Wake_up 3_0 event + ** \arg PWC_PDWKEN1_WKUP31 Wake_up 3_1 event + ** \arg PWC_PDWKEN1_WKUP32 Wake_up 3_2 event + ** \arg PWC_PDWKEN1_WKUP33 Wake_up 3_3 event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup1Cmd(uint32_t u32Wkup1Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP_EVENT(u32Wkup1Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE1 |= (uint8_t)u32Wkup1Event; + } + else + { + M4_SYSREG->PWR_PDWKE1 &= (uint8_t)(~u32Wkup1Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup2Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN2_PVD1 Wake_up PVD1 event + ** \arg PWC_PDWKEN2_PVD2 Wake_up PVD2 event + ** \arg PWC_PDWKEN2_NMI Wake_up NMI event + ** \arg PWC_PDWKEN2_RTCPRD Wake_up RTCPRD event + ** \arg PWC_PDWKEN2_RTCAL Wake_up RTCAL event + ** \arg PWC_PDWKEN2_WKTM Wake_up WKTM event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup2Cmd(uint32_t u32Wkup2Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP2_EVENT(u32Wkup2Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE2 |= (uint8_t)u32Wkup2Event; + } + else + { + M4_SYSREG->PWR_PDWKE2 &= (uint8_t)(~u32Wkup2Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configure the power down wake up event edge. + ** + ** \param [in] u8WkupEvent The wake_up event in PDWKEN0. + ** \arg PWC_PDWKUP_EDGE_WKP0 Wake_up WKP0 event + ** \arg PWC_PDWKUP_EDGE_WKP1 Wake_up WKP1 event + ** \arg PWC_PDWKUP_EDGE_WKP2 Wake_up WKP2 event + ** \arg PWC_PDWKUP_EDGE_WKP3 Wake_up WKP3 event + ** \arg PWC_PDWKUP_EDGE_PVD1 Wake_up PVD1 event + ** \arg PWC_PDWKUP_EDGE_PVD2 Wake_up PVD2 event + ** \arg PWC_PDWKUP_EDGE_NMI Wake_up NMI event + ** + ** \param [in] enEdge The wake_up event edge select. + ** \arg EdgeRising Wake_up event edge rising. + ** \arg EdgeFalling Wake_up event edge falling. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeupEvtEdgeCfg(uint8_t u8WkupEvent, en_pwc_edge_sel_t enEdge) +{ + DDL_ASSERT(IS_PWC_WKUP_EDGE_EVENT(u8WkupEvent)); + DDL_ASSERT(IS_PWC_EDGE_SEL(enEdge)); + + ENABLE_PWR_REG_WRITE(); + + if(EdgeRising == enEdge) + { + M4_SYSREG->PWR_PDWKES |= (uint8_t)u8WkupEvent; + } + else + { + M4_SYSREG->PWR_PDWKES &= (uint8_t)(~u8WkupEvent); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get wake_up event in PDWKF0 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF0. + ** \arg PWC_PTWK0_WKUPFLAG Ptwk0 wake_up flag + ** \arg PWC_PTWK1_WKUPFLAG Ptwk1 wake_up flag + ** \arg PWC_PTWK2_WKUPFLAG Ptwk2 wake_up flag + ** \arg PWC_PTWK3_WKUPFLAG Ptwk3 wake_up flag + ** \arg PWC_PVD1_WKUPFLAG Pvd1 wake_up flag + ** \arg PWC_PVD2_WKUPFLAG Pvd2 wake_up flag + ** \arg PWC_NMI_WKUPFLAG Nmi wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetWakeup0Flag(uint8_t u8WkupFlag) +{ + uint8_t u8flag; + DDL_ASSERT(IS_PWC_WKUP0_FLAG(u8WkupFlag)); + + u8flag = (M4_SYSREG->PWR_PDWKF0 & u8WkupFlag); + + return ((0u == u8flag) ? Reset : Set); +} + +/** + ******************************************************************************* + ** \brief Get wake_up event in PDWKF1 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF1. + ** \arg PWC_RTCPRD_WKUPFALG Rtcprd wake_up flag + ** \arg PWC_RTCAL_WKUPFLAG Rtcal wake_up flag + ** \arg PWC_WKTM_WKUPFLAG Wktm wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetWakeup1Flag(uint8_t u8WkupFlag) +{ + uint8_t u8flag; + DDL_ASSERT(IS_PWC_WKUP1_FLAG(u8WkupFlag)); + + u8flag = (M4_SYSREG->PWR_PDWKF1 & u8WkupFlag); + + return ((0u == u8flag) ? Reset : Set); +} + +/** + ******************************************************************************* + ** \brief clear wake_up event in PDWKF0 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF0. + ** \arg PWC_PTWK0_WKUPFLAG Ptwk0 wake_up flag + ** \arg PWC_PTWK1_WKUPFLAG Ptwk1 wake_up flag + ** \arg PWC_PTWK2_WKUPFLAG Ptwk2 wake_up flag + ** \arg PWC_PTWK3_WKUPFLAG Ptwk3 wake_up flag + ** \arg PWC_PVD1_WKUPFLAG Pvd1 wake_up flag + ** \arg PWC_PVD2_WKUPFLAG Pvd2 wake_up flag + ** \arg PWC_NMI_WKUPFLAG Nmi wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearWakeup0Flag(uint8_t u8WkupFlag) +{ + DDL_ASSERT(IS_PWC_WKUP0_FLAG(u8WkupFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PDWKF0 &= (uint8_t)(~u8WkupFlag); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief clear wake_up event in PDWKF1 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF1. + ** \arg PWC_RTCPRD_WKUPFALG Rtcprd wake_up flag + ** \arg PWC_RTCAL_WKUPFLAG Rtcal wake_up flag + ** \arg PWC_WKTM_WKUPFLAG Wktm wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearWakeup1Flag(uint8_t u8WkupFlag) +{ + DDL_ASSERT(IS_PWC_WKUP1_FLAG(u8WkupFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PDWKF1 &= (uint8_t)(~u8WkupFlag); + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief Enable or disable power monitor . + ** + ** \param [in] enNewState The power monitor state. + ** \arg Enable Enable power monitor. + ** \arg Disable Disable power monitor. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PwrMonitorCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWCMR_f.ADBUFE = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG0 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg0Periph The peripheral in FCG0. + ** \arg PWC_FCG0_PERIPH_SRAMH RAMHS clock + ** \arg PWC_FCG0_PERIPH_SRAM12 RAM0 clock + ** \arg PWC_FCG0_PERIPH_SRAM3 ECCRAM clock + ** \arg PWC_FCG0_PERIPH_SRAMRET RetRAM clock + ** \arg PWC_FCG0_PERIPH_DMA1 DMA1 clock + ** \arg PWC_FCG0_PERIPH_DMA2 DMA2 clock + ** \arg PWC_FCG0_PERIPH_FCM FCM clock + ** \arg PWC_FCG0_PERIPH_AOS PTDIS clock + ** \arg PWC_FCG0_PERIPH_AES AES clock + ** \arg PWC_FCG0_PERIPH_HASH HASH clock + ** \arg PWC_FCG0_PERIPH_TRNG TRNG clock + ** \arg PWC_FCG0_PERIPH_CRC CRC clock + ** \arg PWC_FCG0_PERIPH_DCU1 DCU1 clock + ** \arg PWC_FCG0_PERIPH_DCU2 DCU2 clock + ** \arg PWC_FCG0_PERIPH_DCU3 DCU3 clock + ** \arg PWC_FCG0_PERIPH_DCU4 DCU4 clock + ** \arg PWC_FCG0_PERIPH_KEY KEY clock + + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG0_PERIPH(u32Fcg0Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_FCG0_REG_WRITE(); + + if(Enable == enNewState) + { + M4_MSTP->FCG0 &= ~u32Fcg0Periph; + } + else + { + M4_MSTP->FCG0 |= u32Fcg0Periph; + } + + DISABLE_FCG0_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG1 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg1Periph The peripheral in FCG1. + ** \arg PWC_FCG1_PERIPH_CAN CAN clock + ** \arg PWC_FCG1_PERIPH_QSPI QSPI clock + ** \arg PWC_FCG1_PERIPH_I2C1 I2C1 clock + ** \arg PWC_FCG1_PERIPH_I2C2 I2C2 clock + ** \arg PWC_FCG1_PERIPH_I2C3 I2C3 clock + ** \arg PWC_FCG1_PERIPH_USBFS USBFS clock + ** \arg PWC_FCG1_PERIPH_SDIOC1 SDIOC1 clock + ** \arg PWC_FCG1_PERIPH_SDIOC2 SDIOC2 clock + ** \arg PWC_FCG1_PERIPH_I2S1 I2S1 clock + ** \arg PWC_FCG1_PERIPH_I2S2 I2S2 clock + ** \arg PWC_FCG1_PERIPH_I2S3 I2S3 clock + ** \arg PWC_FCG1_PERIPH_I2S4 I2S4 clock + ** \arg PWC_FCG1_PERIPH_SPI1 SPI1 clock + ** \arg PWC_FCG1_PERIPH_SPI2 SPI2 clock + ** \arg PWC_FCG1_PERIPH_SPI3 SPI3 clock + ** \arg PWC_FCG1_PERIPH_SPI4 SPI4 clock + ** \arg PWC_FCG1_PERIPH_USART1 USART1 clock + ** \arg PWC_FCG1_PERIPH_USART2 USART2 clock + ** \arg PWC_FCG1_PERIPH_USART3 USART3 clock + ** \arg PWC_FCG1_PERIPH_USART4 USART4 clock + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG1_PERIPH(u32Fcg1Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG1 &= ~u32Fcg1Periph; + } + else + { + M4_MSTP->FCG1 |= u32Fcg1Periph; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG2 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg2Periph The peripheral in FCG2. + ** \arg PWC_FCG2_PERIPH_TIM01 TIM01 clock + ** \arg PWC_FCG2_PERIPH_TIM02 TIM02 clock + ** \arg PWC_FCG2_PERIPH_TIMA1 TIMA1 clock + ** \arg PWC_FCG2_PERIPH_TIMA2 TIMA2 clock + ** \arg PWC_FCG2_PERIPH_TIMA3 TIMA3 clock + ** \arg PWC_FCG2_PERIPH_TIMA4 TIMA4 clock + ** \arg PWC_FCG2_PERIPH_TIMA5 TIMA5 clock + ** \arg PWC_FCG2_PERIPH_TIMA6 TIMA6 clock + ** \arg PWC_FCG2_PERIPH_TIM41 TIM41 clock + ** \arg PWC_FCG2_PERIPH_TIM42 TIM42 clock + ** \arg PWC_FCG2_PERIPH_TIM43 TIM43 clock + ** \arg PWC_FCG2_PERIPH_EMB EMB clock + ** \arg PWC_FCG2_PERIPH_TIM61 TIM61 clock + ** \arg PWC_FCG2_PERIPH_TIM62 TIM62 clock + ** \arg PWC_FCG2_PERIPH_TIM63 TIM63 clock + + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG2_PERIPH(u32Fcg2Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG2 &= ~u32Fcg2Periph; + } + else + { + M4_MSTP->FCG2 |= u32Fcg2Periph; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG3 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg3Periph The peripheral in FCG3. + ** \arg PWC_FCG3_PERIPH_ADC1 ADC1 clock + ** \arg PWC_FCG3_PERIPH_ADC2 ADC2 clock + ** \arg PWC_FCG3_PERIPH_CMP CMP clock + ** \arg PWC_FCG3_PERIPH_OTS OTS clock + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG3_PERIPH(u32Fcg3Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG3 &= ~u32Fcg3Periph; + } + else + { + M4_MSTP->FCG3 |= u32Fcg3Periph; + } +} + +/** + ******************************************************************************* + ** \brief The stop mode configuration. + ** + ** \param [in] pstcStpMdCfg Pointer to stop mode configuration structure. + ** \arg Enable Enable stop mode. + ** \arg Disable Disable stop mode. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t PWC_StopModeCfg(const stc_pwc_stop_mode_cfg_t* pstcStpMdCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_PWC_STOP_MODE_FLASH(pstcStpMdCfg->enStopFlash)); + DDL_ASSERT(IS_PWC_STOP_MODE_CLK(pstcStpMdCfg->enStopClk)); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_STPMCR = (pstcStpMdCfg->enStopFlash | + (pstcStpMdCfg->enStopClk << 1u) | + (1u << 14u)); + + /* if should close HRC & PLL while stop mode, please disable before modifying the register */ + if(Disable == pstcStpMdCfg->enPll) + { + /* PLL is system clock */ + if(5u == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Disable PLL */ + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 1u; + } + } + + /* Hrc power should be enable. */ + M4_SYSREG->PWR_PWRC1_f.VHRCSD = 0u; + M4_SYSREG->PWR_PWRC1_f.VPLLSD = ((Enable == pstcStpMdCfg->enPll) ? 0u : 1u); + M4_SYSREG->PWR_PWRC1_f.STPDAS = pstcStpMdCfg->enStpDrvAbi; + + DISABLE_PWR_REG0_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup0Event The wake_up event in PDWKEN0. + ** \arg PWC_STOPWKUPEN_EIRQ0 EIRQ0 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ1 EIRQ1 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ2 EIRQ2 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ3 EIRQ3 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ4 EIRQ4 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ5 EIRQ5 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ6 EIRQ6 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ7 EIRQ7 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ8 EIRQ8 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ9 EIRQ9 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ10 EIRQ10 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ11 EIRQ11 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ12 EIRQ12 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ13 EIRQ13 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ14 EIRQ14 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ15 EIRQ15 wake_up event + ** \arg PWC_STOPWKUPEN_SWDT SWDT wake_up event + ** \arg PWC_STOPWKUPEN_VDU1 VDU1 wake_up event + ** \arg PWC_STOPWKUPEN_VDU2 VDU2 wake_up event + ** \arg PWC_STOPWKUPEN_CMPI0 CMPI0 wake_up event + ** \arg PWC_STOPWKUPEN_WKTM WKTM wake_up event + ** \arg PWC_STOPWKUPEN_RTCAL RTCAL wake_up event + ** \arg PWC_STOPWKUPEN_RTCPRD RTCPRD wake_up event + ** \arg PWC_STOPWKUPEN_TMR0 TMR0 wake_up event + ** \arg PWC_STOPWKUPEN_USARTRXD USARTRXD wake_up event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_StopWkupCmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_INTC->WUPEN |= u32Wkup0Event; + } + else + { + M4_INTC->WUPEN &= ~u32Wkup0Event; + } +} + +/** + ******************************************************************************* + ** \brief Enter sleep mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_EnterSleepMd(void) +{ + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 0u; + M4_SYSREG->PWR_PWRC0_f.PWDN = 0u; + + DISABLE_PWR_REG_WRITE(); + + __WFI(); +} +/** + ******************************************************************************* + ** \brief Ram area power down commond. + ** + ** \param [in] u32RamCtlBit The ram area contol. + ** \arg PWC_RAMPWRDOWN_SRAM1 Ram0(0x20000000-0x2000FFFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAM2 Ram1(0x20010000-0x2001FFFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAM3 Ram2(0x20020000-0x20026FFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAMH Ram3(0x1FFF8000-0x1FFFFFFF) power down control. + ** \arg PWC_RAMPWRDOWN_USBFS Usbfs power down control. + ** \arg PWC_RAMPWRDOWN_SDIOC0 Sdioc0 power down control. + ** \arg PWC_RAMPWRDOWN_SDIOC1 Sdioc1 power down control. + ** \arg PWC_RAMPWRDOWN_CAN Can power down control. + ** \arg PWC_RAMPWRDOWN_CACHE Cache power down control. + ** \arg PWC_RAMPWRDOWN_FULL Full. + ** + ** \param [in] enNewState The new state of the Ram area. + ** \arg Enable Ten ram area run. + ** \arg Disable The ram area power down. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_RamPwrdownCmd(uint32_t u32RamCtlBit, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_RAMPC0 &= ~u32RamCtlBit; + } + else + { + M4_SYSREG->PWR_RAMPC0 |= u32RamCtlBit; + } + + DISABLE_PWR_REG_WRITE(); +} + +void PWC_RamOpMdConfig(en_pwc_ram_op_md_t enRamOpMd) +{ + DDL_ASSERT(IS_PWC_RAM_OP_MD(enRamOpMd)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_RAMOPM = enRamOpMd; + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief Enable or disable XTAL/RTC/WKTM bias current. + ** + ** \param [in] enNewState The XTAL/RTC/WKTM bias current state. + ** \arg Enable Enable XTAL/RTC/WKTM bias current. + ** \arg Disable Disable XTAL/RTC/WKTM bias current. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Xtal32CsCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_XTAL32CS_f.CSDIS = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief wake_up timer control. + ** + ** \param [in] pstcWktmCtl The wake_up timer configuration. + ** \arg enWktmEn Enable or disable wake_up timer. + ** \arg enWkclk The wake_up timer clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_WktmControl(const stc_pwc_wktm_ctl_t* pstcWktmCtl) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcWktmCtl->enWktmEn)); + DDL_ASSERT(IS_PWC_WKTM_CLK(pstcWktmCtl->enWkclk)); + DDL_ASSERT(IS_PWC_WKTMOVER_FLAG(pstcWktmCtl->enWkOverFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_WKTM->CR = ((pstcWktmCtl->u16WktmCmp & PWC_WKTMCMP_MSK) | + (pstcWktmCtl->enWkOverFlag << 12) | + (pstcWktmCtl->enWkclk << 13) | + (pstcWktmCtl->enWktmEn << 15)); + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief The pvd configuration. + ** + ** \param [in] pstcPvdCfg The pvd configuration. + ** \arg enPtwk0Edge Ptwk0 edge + ** \arg enPtwk1Edge Ptwk1 edge + ** \arg enPtwk2Edge Ptwk2 edge + ** \arg enPtwk3Edge Ptwk3 edge + ** \arg enPvd1Edge Pvd1 edge + ** \arg enPvd1Edge Pvd2 edge + ** \arg enNmiEdge Nmi edge + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PvdCfg(const stc_pwc_pvd_cfg_t* pstcPvdCfg) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd1Ctl.enPvdIREn)); + DDL_ASSERT(IS_PWC_PVD_MD(pstcPvdCfg->stcPvd1Ctl.enPvdMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd1Ctl.enPvdCmpOutEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd2Ctl.enPvdIREn)); + DDL_ASSERT(IS_PWC_PVD_MD(pstcPvdCfg->stcPvd2Ctl.enPvdMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd2Ctl.enPvdCmpOutEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->enPvd1FilterEn)); + DDL_ASSERT(IS_PWC_PVD_FILTER_CLK(pstcPvdCfg->enPvd1Filtclk)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->enPvd2FilterEn)); + DDL_ASSERT(IS_PWC_PVD_FILTER_CLK(pstcPvdCfg->enPvd2Filtclk)); + DDL_ASSERT(IS_PWC_PVD1_LEVEL(pstcPvdCfg->enPvd1Level)); + DDL_ASSERT(IS_PWC_PVD2_LEVEL(pstcPvdCfg->enPvd2Level)); + DDL_ASSERT(IS_PWC_PVD_INT_SEL(pstcPvdCfg->enPvd1Int)); + DDL_ASSERT(IS_PWC_PVD_INT_SEL(pstcPvdCfg->enPvd2Int)); + + ENABLE_PVD_REG_WRITE(); + + /* Config Pvd control. */ + M4_SYSREG->PWR_PVDCR1 = (pstcPvdCfg->stcPvd1Ctl.enPvdIREn | + (pstcPvdCfg->stcPvd1Ctl.enPvdMode << 1) | + (pstcPvdCfg->stcPvd1Ctl.enPvdCmpOutEn << 2) | + (pstcPvdCfg->stcPvd2Ctl.enPvdIREn<< 4) | + (pstcPvdCfg->stcPvd2Ctl.enPvdMode << 5) | + (pstcPvdCfg->stcPvd2Ctl.enPvdCmpOutEn << 6)); + /* Set pvd filter sampling. */ + M4_SYSREG->PWR_PVDFCR = (~(pstcPvdCfg->enPvd1FilterEn) | + (pstcPvdCfg->enPvd1Filtclk << 1) | + ((~pstcPvdCfg->enPvd2FilterEn) << 4) | + (pstcPvdCfg->enPvd2Filtclk << 5)); + /* Set pvd level. */ + M4_SYSREG->PWR_PVDLCR = (pstcPvdCfg->enPvd1Level | + (pstcPvdCfg->enPvd2Level << 4)); + /* Set pvd interrupt(non_maskable or maskable). */ + M4_SYSREG->PWR_PVDICR = (pstcPvdCfg->enPvd1Int | + (pstcPvdCfg->enPvd2Int << 4)); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable pvd1. + ** + ** \param [in] enNewState The pvd1 state. + ** \arg Enable Enable pvd1. + ** \arg Disable Disable pvd1. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Pvd1Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.PVD1EN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable pvd2. + ** + ** \param [in] enNewState The pvd2 state. + ** \arg Enable Enable pvd2. + ** \arg Disable Disable pvd2. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Pvd2Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.PVD2EN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable external vcc. + ** + ** \param [in] enNewState The external vcc state. + ** \arg Enable Enable external vcc. + ** \arg Disable Disable external vcc. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ExVccCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.EXVCCINEN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get pvd detection status. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetPvdStatus(en_pwc_pvd_t enPvd) +{ + uint8_t u8flag = 0u; + + switch(enPvd) + { + case PvdU1: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD1MON; + break; + case PvdU2: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD2MON; + break; + default: + break; + } + + return ((1u == u8flag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Get pvd detection flag. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetPvdFlag(en_pwc_pvd_t enPvd) +{ + uint8_t u8flag = 0u; + + switch(enPvd) + { + case PvdU1: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD1DETFLG; + break; + case PvdU2: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD2DETFLG; + break; + default: + break; + } + + return ((1u == u8flag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear pvd detection flag. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearPvdFlag(en_pwc_pvd_t enPvd) +{ + ENABLE_PVD_REG_WRITE(); + switch(enPvd) + { + case PvdU1: + M4_SYSREG->PWR_PVDDSR_f.PVD1MON = 0u; + break; + case PvdU2: + M4_SYSREG->PWR_PVDDSR_f.PVD2MON = 0u; + break; + default: + break; + } + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable HRC power. + ** + ** \param [in] enNewState The HRC power state. + ** \arg Enable Enable HRC power. + ** \arg Disable Disable HRC power. + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_HrcPwrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC1_f.VHRCSD = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable PLL power. + ** + ** \param [in] enNewState The PLL power state. + ** \arg Enable Enable PLL power. + ** \arg Disable Disable PLL power. + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_PllPwrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC1_f.VPLLSD = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief NVIC backup and disable before entry from stop mode + ** + ** param None + ** + ** retval None + ** + *****************************************************************************/ +void PWC_enNvicBackup(void) +{ + uint8_t u8Cnt; + stc_intc_sel_field_t *stcIntSel; + uint32_t u32WakeupSrc = INT_MAX; + + /* Backup NVIC set enable register for IRQ0~143*/ + for (u8Cnt = 0u; u8Cnt < sizeof(NVIC_ISER_BAK)/sizeof(uint32_t); u8Cnt++) + { + NVIC_ISER_BAK[u8Cnt] = NVIC->ISER[u8Cnt]; + } + + /* Disable share vector */ + for (u8Cnt = 128u; u8Cnt < 144u; u8Cnt++) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + + for (u8Cnt = 0u; u8Cnt < 128u; u8Cnt++) + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + (4ul * u8Cnt)); + /* Disable NVIC if it is the wakeup-able source from stop mode */ + u32WakeupSrc = stcIntSel->INTSEL; + if (IS_VALID_WKUP_SRC(u32WakeupSrc)) + { + switch (stcIntSel->INTSEL) + { + case INT_USART1_WUPI: + if (Reset == bM4_INTC_WUPEN_RXWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_TMR01_GCMA: + if (Reset == bM4_INTC_WUPEN_TMR0WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_RTC_ALM: + if (Reset == bM4_INTC_WUPEN_RTCALMWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_RTC_PRD: + if (Reset == bM4_INTC_WUPEN_RTCPRDWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_WKTM_PRD: + if (Reset == bM4_INTC_WUPEN_WKTMWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_ACMP1: + if (Reset == bM4_INTC_WUPEN_CMPI0WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PVD_PVD1: + if (Reset == bM4_INTC_WUPEN_PVD1WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PVD_PVD2: + if (Reset == bM4_INTC_WUPEN_PVD2WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_SWDT_REFUDF: + if (Reset == bM4_INTC_WUPEN_SWDTWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ0: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN0) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ1: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN1) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ2: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN2) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ3: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN3) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ4: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN4) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ5: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN5) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ6: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN6) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ7: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN7) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ8: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN8) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ9: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN9) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ10: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN10) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ11: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN11) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ12: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN12) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ13: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN13) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ14: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN14) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ15: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN15) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + default: + break; + } + } + /* Disable NVIC for all none-wakeup source */ + else if (INT_MAX != stcIntSel->INTSEL) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + else + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief NVIC recover after wakeup from stop mode + ** + ** param None + ** + ** retval None + ** + *****************************************************************************/ +void PWC_enNvicRecover(void) +{ + uint8_t u8Cnt; + + for (u8Cnt = 0u; u8Cnt < sizeof(NVIC_ISER_BAK)/sizeof(uint32_t); u8Cnt++) + { + NVIC->ISER[u8Cnt] = NVIC_ISER_BAK[u8Cnt]; + } +} + +/** + ******************************************************************************* + ** \brief Select system clock source. + ** + ** \param [in] u8SysSrc The system clock source. + ** + ** \retval None + ** + ** \note Must close all of the fcg register before switch system clock source. + ** This function only be called in func. PWC_enClockBackup and + ** PWC_enClockRecover. + ** If need to switch system clock please call CLK_SetSysClkSource. + ** + ******************************************************************************/ +static void PWC_SetSysClk(uint8_t u8SysSrc) +{ + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + /* Only current system clock source or target system clock source is MPLL + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if((5u == M4_SYSREG->CMU_CKSWR_f.CKSW) || (5u == u8SysSrc)) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = 0xFFFFFAEEul; + M4_MSTP->FCG1 = 0xFFFFFFFFul; + M4_MSTP->FCG2 = 0xFFFFFFFFul; + M4_MSTP->FCG3 = 0xFFFFFFFFul; + + Ddl_Delay1us(1ul); + } + + /* Switch to target system clock source. */ + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->CMU_CKSWR_f.CKSW = u8SysSrc; + + DISABLE_PWR_REG0_WRITE(); + + /* update system clock frequency. */ + SystemCoreClockUpdate(); + + Ddl_Delay1us(1ul); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + Ddl_Delay1us(1ul); +} +/** + ******************************************************************************* + ** \brief Backup HRC/MRC state and system clock , enable HRC/MRC ,set MRC as + ** system clock before enter stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +static void PWC_enClockBackup(void) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status = Reset; + + /* HRC state backup. */ + u8HrcState = (uint8_t)bM4_SYSREG_CMU_HRCCR_HRCSTP; + /* System clock backup*/ + u8SysClkSrc = M4_SYSREG->CMU_CKSWR_f.CKSW; + + ENABLE_PWR_REG0_WRITE(); + + /* Enable HRC before enter stop mode. */ + if(0u != u8HrcState) + { + bM4_SYSREG_CMU_HRCCR_HRCSTP = 0u; + do + { + status = (en_flag_status_t)M4_SYSREG->CMU_OSCSTBSR_f.HRCSTBF; + timeout++; + }while((timeout < 0x1000ul) && (status != Set)); + } + else + { + /* code */ + } + /* When system clock source is HRC and MPLL, set MRC as system clock. . */ + if((0u == u8SysClkSrc) || (5u == u8SysClkSrc)) + { + /* MRC state backup. */ + u8MrcState = (uint8_t)bM4_SYSREG_CMU_MRCCR_MRCSTP; + if(0u != u8MrcState) + { + bM4_SYSREG_CMU_MRCCR_MRCSTP = 0u; + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + PWC_SetSysClk(1u); + } + else + { + /* code */ + } + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Recover HRC/MRC state and system clock after wakeup stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +static void PWC_enClockRecover(void) +{ + ENABLE_PWR_REG0_WRITE(); + + if((0u == u8SysClkSrc) || (5u == u8SysClkSrc)) + { + /* Recover MRC state & system clock source. */ + M4_SYSREG->CMU_MRCCR_f.MRCSTP = u8MrcState; + PWC_SetSysClk(u8SysClkSrc); + } + /* Recover HRC state after wakeup stop mode. */ + M4_SYSREG->CMU_HRCCR_f.HRCSTP = u8HrcState; + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Clock backup before enter stop mode and mark it. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called before func. PWC_EnterStopMd. + ******************************************************************************/ +void PWC_ClkBackup(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* HRC/MRC backup and switch system clock as MRC before entry from stop mode. */ + PWC_enClockBackup(); + + /* Mark the system clock has been switch as MRC, and will enter the stop mode. */ + u8StopFlag = 1u; + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + ******************************************************************************* + ** \brief Clock recover after wakeup stop mode. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called after func. PWC_EnterStopMd. + ******************************************************************************/ +void PWC_ClkRecover(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* Mark the system clock will be switch as MRC, and has waked_up from stop mode. */ + u8StopFlag = 0u; + + /* Recover HRC/MRC state and system clock after wakeup stop mode. */ + PWC_enClockRecover(); + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + ******************************************************************************* + ** \brief Clock backup before exit wakup interrupt. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called before exit wakup interrput. + ******************************************************************************/ +void PWC_IrqClkBackup(void) +{ + if((1ul == u8StopFlag) && (1ul == u8WkupIntCnt)) + { + /* HRC/MRC backup and switch system clock as MRC. */ + PWC_enClockBackup(); + } + u8WkupIntCnt--; +} + +/** + ******************************************************************************* + ** \brief Clock recover after enter wakeup interrupt. + ** + ** \param None + ** + ** \retval None + ** +** \note This function should be called after enter wakup interrput. + ******************************************************************************/ +void PWC_IrqClkRecover(void) +{ + /* The varibale to display how many waked_up interrupt has been occured + simultaneously and to decided whether backup clock before exit wake_up + interrupt. */ + u8WkupIntCnt++; + + if(1ul == u8StopFlag) + { + /* Recover HRC/MRC state and system clock. */ + PWC_enClockRecover(); + } +} + +/** + ******************************************************************************* + ** \brief Enter stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_EnterStopMd(void) +{ + /* NVIC backup and disable before entry from stop mode.*/ + PWC_enNvicBackup(); + /* Clock backup and switch system clock as MRC before entry from stop mode. */ + PWC_ClkBackup(); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 1u; + M4_SYSREG->PWR_PWRC0_f.PWDN = 0u; + + DISABLE_PWR_REG0_WRITE(); + + __WFI(); + + /* Recover HRC/MRC state and system clock after wakeup from stop mode. */ + PWC_ClkRecover(); + /* NVIC recover after wakeup from stop mode. */ + PWC_enNvicRecover(); +} + +/** + ******************************************************************************* + ** \brief Switch MCU from low_speed (HCLK < 8MHz) to high-speed (HCLK > 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HS2LS(void) +{ + uint32_t u32To = 10000ul; + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 1u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 1u; + } + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_RAMOPM = 0x9062u; + while((0x9062 != M4_SYSREG->PWR_RAMOPM) || (1u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + M4_SYSREG->PWR_PWRC2 = 0xE1U; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-speed (HCLK > 8MHz) to low_speed (HCLK < 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_LS2HS(void) +{ + uint32_t u32To = 10000ul; + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xFFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + Ddl_Delay1ms(1ul); + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 0u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 0u; + } + + M4_SYSREG->PWR_RAMOPM = 0x8043u; + while((0x8043 != M4_SYSREG->PWR_RAMOPM) || (0u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + DISABLE_PWR_REG_WRITE(); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-speed (HCLK > 8MHz) to high-performance mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_HS2HP(void) +{ + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xCFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-performance to high-speed (HCLK > 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HP2HS(void) +{ + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xFFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from low-speed (HCLK <= 8MHz) to high-performance mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_LS2HP(void) +{ + uint32_t u32To = 10000ul; + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xCFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + Ddl_Delay1ms(1); + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 0u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 0u; + } + + M4_SYSREG->PWR_RAMOPM = 0x8043u; + while((0x8043 != M4_SYSREG->PWR_RAMOPM) || (0u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + DISABLE_PWR_REG_WRITE(); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-performance to low-speed (HCLK <= 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HP2LS(void) +{ + uint32_t u32To = 10000ul; + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 1u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 1u; + } + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_RAMOPM = 0x9062u; + u32To = 10000ul; + while((0x9062 != M4_SYSREG->PWR_RAMOPM) || (1u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + M4_SYSREG->PWR_PWRC2 = 0xD1U; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + DISABLE_PWR_REG_WRITE(); + + Ddl_Delay1ms(1); + + return Ok; +} + +#endif /* DDL_PWC_ENABLE */ + +//@} // PwcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_qspi.c b/driver/src/hc32f460_qspi.c new file mode 100644 index 0000000..1f471aa --- /dev/null +++ b/driver/src/hc32f460_qspi.c @@ -0,0 +1,756 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_qspi.c + ** + ** A detailed description is available at + ** @link QspiGroup Queued SPI description @endlink + ** + ** - 2018-11-20 CDT First version for Device Driver Library of Qspi. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_qspi.h" +#include "hc32f460_utility.h" + +#if (DDL_QSPI_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup QspiGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for clock division */ +#define IS_VALID_CLK_DIV(x) \ +( ((x) == QspiHclkDiv2) || \ + (((x) >= QspiHclkDiv3) && ((x) <= QspiHclkDiv64))) + +/*!< Parameter valid check for spi mode */ +#define IS_VALID_SPI_MODE(x) \ +( (QspiSpiMode0 == (x)) || \ + (QspiSpiMode3 == (x))) + +/*!< Parameter valid check for bus communication mode */ +#define IS_VALID_BUS_COMM_MODE(x) \ +( (QspiBusModeRomAccess == (x)) || \ + (QspiBusModeDirectAccess == (x))) + +/*!< Parameter valid check for prefetch stop location */ +#define IS_VALID_PREFETCH_STOP_LOCATION(x) \ +( (QspiPrefetchStopComplete == (x)) || \ + (QspiPrefetchStopImmediately == (x))) + +/*!< Parameter valid check for receive data protocol */ +#define IS_VALID_RECE_DATA_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for transmit address protocol */ +#define IS_VALID_TRANS_ADDR_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for transmit instruction protocol */ +#define IS_VALID_TRANS_INSTRUCT_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for serial interface read mode */ +#define IS_VALID_INTERFACE_READ_MODE(x) \ +( (QspiReadModeStandard == (x)) || \ + (QspiReadModeFast == (x)) || \ + (QspiReadModeTwoWiresOutput == (x)) || \ + (QspiReadModeTwoWiresIO == (x)) || \ + (QspiReadModeFourWiresOutput == (x)) || \ + (QspiReadModeFourWiresIO == (x)) || \ + (QspiReadModeCustomStandard == (x)) || \ + (QspiReadModeCustomFast == (x))) + +/*!< Parameter valid check for QSSN valid extend delay time */ +#define IS_VALID_QSSN_VALID_EXTEND_TIME(x) \ +( (QspiQssnValidExtendNot == (x)) || \ + (QspiQssnValidExtendSck32 == (x)) || \ + (QspiQssnValidExtendSck128 == (x)) || \ + (QspiQssnValidExtendSckEver == (x))) + +/*!< Parameter valid check for QSSN minimum interval time */ +#define IS_VALID_QSSN_INTERVAL_TIME(x) \ +( (QspiQssnIntervalQsck1 == (x)) || \ + (QspiQssnIntervalQsck2 == (x)) || \ + (QspiQssnIntervalQsck3 == (x)) || \ + (QspiQssnIntervalQsck4 == (x)) || \ + (QspiQssnIntervalQsck5 == (x)) || \ + (QspiQssnIntervalQsck6 == (x)) || \ + (QspiQssnIntervalQsck7 == (x)) || \ + (QspiQssnIntervalQsck8 == (x)) || \ + (QspiQssnIntervalQsck9 == (x)) || \ + (QspiQssnIntervalQsck10 == (x)) || \ + (QspiQssnIntervalQsck11 == (x)) || \ + (QspiQssnIntervalQsck12 == (x)) || \ + (QspiQssnIntervalQsck13 == (x)) || \ + (QspiQssnIntervalQsck14 == (x)) || \ + (QspiQssnIntervalQsck15 == (x)) || \ + (QspiQssnIntervalQsck16 <= (x))) + +/*!< Parameter valid check for QSCK duty correction */ +#define IS_VALID_QSCK_DUTY_CORR(x) \ +( (QspiQsckDutyCorrNot == (x)) || \ + (QspiQsckDutyCorrHalfHclk == (x))) + +/*!< Parameter valid check for virtual cycles */ +#define IS_VALID_VIRTUAL_CYCLES(x) \ +( (QspiVirtualPeriodQsck3 == (x)) || \ + (QspiVirtualPeriodQsck4 == (x)) || \ + (QspiVirtualPeriodQsck5 == (x)) || \ + (QspiVirtualPeriodQsck6 == (x)) || \ + (QspiVirtualPeriodQsck7 == (x)) || \ + (QspiVirtualPeriodQsck8 == (x)) || \ + (QspiVirtualPeriodQsck9 == (x)) || \ + (QspiVirtualPeriodQsck10 == (x)) || \ + (QspiVirtualPeriodQsck11 == (x)) || \ + (QspiVirtualPeriodQsck12 == (x)) || \ + (QspiVirtualPeriodQsck13 == (x)) || \ + (QspiVirtualPeriodQsck14 == (x)) || \ + (QspiVirtualPeriodQsck15 == (x)) || \ + (QspiVirtualPeriodQsck16 == (x)) || \ + (QspiVirtualPeriodQsck17 == (x)) || \ + (QspiVirtualPeriodQsck18 == (x))) + +/*!< Parameter valid check for WP pin output level */ +#define IS_VALID_WP_OUTPUT_LEVEL(x) \ +( (QspiWpPinOutputLow == (x)) || \ + (QspiWpPinOutputHigh == (x))) + +/*!< Parameter valid check for QSSN setup delay time */ +#define IS_VALID_QSSN_SETUP_DELAY(x) \ +( (QspiQssnSetupDelayHalfQsck == (x)) || \ + (QspiQssnSetupDelay1Dot5Qsck == (x))) + +/*!< Parameter valid check for QSSN hold delay time */ +#define IS_VALID_QSSN_HOLD_TIME(x) \ +( (QspiQssnHoldDelayHalfQsck == (x)) || \ + (QspiQssnHoldDelay1Dot5Qsck == (x))) + +/*!< Parameter valid check for interface address width */ +#define IS_VALID_INTERFACE_ADDR_WIDTH(x) \ +( (QspiAddressByteOne == (x)) || \ + (QspiAddressByteTwo == (x)) || \ + (QspiAddressByteThree == (x)) || \ + (QspiAddressByteFour == (x))) + +/*!< Parameter valid check for extend address */ +#define IS_VALID_SET_EXTEND_ADDR(x) ((x) <= 0x3Fu) + +/*!< Parameter valid check for get flag type */ +#define IS_VALID_GET_FLAG_TYPE(x) \ +( (QspiFlagBusBusy == (x)) || \ + (QspiFlagXipMode == (x)) || \ + (QspiFlagRomAccessError == (x)) || \ + (QspiFlagPrefetchBufferFull == (x)) || \ + (QspiFlagPrefetchStop == (x))) + +/*!< Parameter valid check for clear flag type */ +#define IS_VALID_CLEAR_FLAG_TYPE(x) (QspiFlagRomAccessError == (x)) + +/*!< QSPI registers reset value */ +#define QSPI_REG_CR_RESET_VALUE (0x003F0000ul) +#define QSPI_REG_CSCR_RESET_VALUE (0x0000000Ful) +#define QSPI_REG_FCR_RESET_VALUE (0x000080B3ul) +#define QSPI_REG_SR_RESET_VALUE (0x00008000ul) +#define QSPI_REG_CCMD_RESET_VALUE (0x00000000ul) +#define QSPI_REG_XCMD_RESET_VALUE (0x000000FFul) +#define QSPI_REG_EXAR_RESET_VALUE (0x00000000ul) +#define QSPI_REG_SR2_RESET_VALUE (0x00000000ul) +#define QSPI_REG_DCOM_RESET_VALUE (0x00000000ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize QSPI unit + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_DeInit(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR = QSPI_REG_CR_RESET_VALUE; + if (1u == M4_QSPI->SR_f.RAER) + { + M4_QSPI->SR2_f.RAERCLR = 1u; + } + M4_QSPI->CSCR = QSPI_REG_CSCR_RESET_VALUE; + M4_QSPI->FCR = QSPI_REG_FCR_RESET_VALUE; + M4_QSPI->EXAR = QSPI_REG_EXAR_RESET_VALUE; + M4_QSPI->SR = QSPI_REG_SR_RESET_VALUE; + M4_QSPI->CCMD = QSPI_REG_CCMD_RESET_VALUE; + M4_QSPI->XCMD = QSPI_REG_XCMD_RESET_VALUE; + M4_QSPI->DCOM = QSPI_REG_DCOM_RESET_VALUE; + M4_QSPI->SR2 = QSPI_REG_SR2_RESET_VALUE; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize QSPI unit + ** + ** \param [in] pstcQspiInitCfg Pointer to qspi configuration + ** \arg See the struct #stc_qspi_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_Init(const stc_qspi_init_t *pstcQspiInitCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcQspiInitCfg) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CLK_DIV(pstcQspiInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_SPI_MODE(pstcQspiInitCfg->enSpiMode)); + DDL_ASSERT(IS_VALID_BUS_COMM_MODE(pstcQspiInitCfg->enBusCommMode)); + DDL_ASSERT(IS_VALID_PREFETCH_STOP_LOCATION(pstcQspiInitCfg->enPrefetchMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcQspiInitCfg->enPrefetchFuncEn)); + DDL_ASSERT(IS_VALID_RECE_DATA_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enReceProtocol)); + DDL_ASSERT(IS_VALID_TRANS_ADDR_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enTransAddrProtocol)); + DDL_ASSERT(IS_VALID_TRANS_INSTRUCT_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enTransInstrProtocol)); + DDL_ASSERT(IS_VALID_INTERFACE_READ_MODE(pstcQspiInitCfg->stcCommProtocol.enReadMode)); + DDL_ASSERT(IS_VALID_QSSN_VALID_EXTEND_TIME(pstcQspiInitCfg->enQssnValidExtendTime)); + DDL_ASSERT(IS_VALID_QSSN_INTERVAL_TIME(pstcQspiInitCfg->enQssnIntervalTime)); + DDL_ASSERT(IS_VALID_QSCK_DUTY_CORR(pstcQspiInitCfg->enQsckDutyCorr)); + DDL_ASSERT(IS_VALID_VIRTUAL_CYCLES(pstcQspiInitCfg->enVirtualPeriod)); + DDL_ASSERT(IS_VALID_WP_OUTPUT_LEVEL(pstcQspiInitCfg->enWpPinLevel)); + DDL_ASSERT(IS_VALID_QSSN_SETUP_DELAY(pstcQspiInitCfg->enQssnSetupDelayTime)); + DDL_ASSERT(IS_VALID_QSSN_HOLD_TIME(pstcQspiInitCfg->enQssnHoldDelayTime)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcQspiInitCfg->enFourByteAddrReadEn)); + DDL_ASSERT(IS_VALID_INTERFACE_ADDR_WIDTH(pstcQspiInitCfg->enAddrWidth)); + + /* Configure control register */ + M4_QSPI->CR_f.DIV = pstcQspiInitCfg->enClkDiv; + M4_QSPI->CR_f.SPIMD3 = pstcQspiInitCfg->enSpiMode; + M4_QSPI->CR_f.PFE = pstcQspiInitCfg->enPrefetchFuncEn; + M4_QSPI->CR_f.PFSAE = pstcQspiInitCfg->enPrefetchMode; + M4_QSPI->CR_f.MDSEL = pstcQspiInitCfg->stcCommProtocol.enReadMode; + + /* Custom read mode */ + if ((QspiReadModeCustomFast == pstcQspiInitCfg->stcCommProtocol.enReadMode) || + (QspiReadModeCustomStandard == pstcQspiInitCfg->stcCommProtocol.enReadMode)) + { + M4_QSPI->CR_f.IPRSL = pstcQspiInitCfg->stcCommProtocol.enTransInstrProtocol; + M4_QSPI->CR_f.APRSL = pstcQspiInitCfg->stcCommProtocol.enTransAddrProtocol; + M4_QSPI->CR_f.DPRSL = pstcQspiInitCfg->stcCommProtocol.enReceProtocol; + } + else + { + M4_QSPI->CR_f.IPRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.APRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.DPRSL = QspiProtocolExtendSpi; + } + + /* Configure chip select control register */ + M4_QSPI->CSCR_f.SSNW = pstcQspiInitCfg->enQssnValidExtendTime; + M4_QSPI->CSCR_f.SSHW = pstcQspiInitCfg->enQssnIntervalTime; + + /* Configure format control register */ + if (((pstcQspiInitCfg->enClkDiv % 2) != 0) && + (pstcQspiInitCfg->enQsckDutyCorr != QspiQsckDutyCorrNot)) + { + M4_QSPI->FCR_f.DUTY = QspiQsckDutyCorrNot; + } + else + { + M4_QSPI->FCR_f.DUTY = pstcQspiInitCfg->enQsckDutyCorr; + } + M4_QSPI->FCR_f.DMCYCN = pstcQspiInitCfg->enVirtualPeriod; + M4_QSPI->FCR_f.WPOL = pstcQspiInitCfg->enWpPinLevel; + M4_QSPI->FCR_f.SSNLD = pstcQspiInitCfg->enQssnSetupDelayTime; + M4_QSPI->FCR_f.SSNHD = pstcQspiInitCfg->enQssnHoldDelayTime; + M4_QSPI->FCR_f.FOUR_BIC = pstcQspiInitCfg->enFourByteAddrReadEn; + M4_QSPI->FCR_f.AWSL = pstcQspiInitCfg->enAddrWidth; + M4_QSPI->CR_f.DCOME = pstcQspiInitCfg->enBusCommMode; + + /* Configure ROM access instruction */ + M4_QSPI->CCMD = pstcQspiInitCfg->u8RomAccessInstr; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Config communication protocol structure + ** + ** \param [in] pstcCommProtocol Pointer to qspi communication protocol configuration + ** \arg See the struct #stc_qspi_comm_protocol_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_CommProtocolConfig(const stc_qspi_comm_protocol_t *pstcCommProtocol) +{ + en_result_t enRet = Ok; + + if (NULL == pstcCommProtocol) + { + enRet = Error; + } + else + { + DDL_ASSERT(IS_VALID_RECE_DATA_PROTOCOL(pstcCommProtocol->enReceProtocol)); + DDL_ASSERT(IS_VALID_TRANS_ADDR_PROTOCOL(pstcCommProtocol->enTransAddrProtocol)); + DDL_ASSERT(IS_VALID_TRANS_INSTRUCT_PROTOCOL(pstcCommProtocol->enTransInstrProtocol)); + DDL_ASSERT(IS_VALID_INTERFACE_READ_MODE(pstcCommProtocol->enReadMode)); + + M4_QSPI->CR_f.MDSEL = pstcCommProtocol->enReadMode; + /* Custom read mode */ + if ((QspiReadModeCustomFast == pstcCommProtocol->enReadMode) || + (QspiReadModeCustomStandard == pstcCommProtocol->enReadMode)) + { + M4_QSPI->CR_f.IPRSL = pstcCommProtocol->enTransInstrProtocol; + M4_QSPI->CR_f.APRSL = pstcCommProtocol->enTransAddrProtocol; + M4_QSPI->CR_f.DPRSL = pstcCommProtocol->enReceProtocol; + } + else + { + M4_QSPI->CR_f.IPRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.APRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.DPRSL = QspiProtocolExtendSpi; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable prefetch function + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable prefetch function + ** \arg Enable Enable prefetch function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_PrefetchCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_QSPI->CR_f.PFE = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set clock division + ** + ** \param [in] enClkDiv Clock division + ** \arg QspiHclkDiv2 Clock source: HCLK/2 + ** \arg QspiHclkDiv3 Clock source: HCLK/3 + ** \arg QspiHclkDiv4 Clock source: HCLK/4 + ** \arg QspiHclkDiv5 Clock source: HCLK/5 + ** \arg QspiHclkDiv6 Clock source: HCLK/6 + ** \arg QspiHclkDiv7 Clock source: HCLK/7 + ** \arg QspiHclkDiv8 Clock source: HCLK/8 + ** \arg QspiHclkDiv9 Clock source: HCLK/9 + ** \arg QspiHclkDiv10 Clock source: HCLK/10 + ** \arg QspiHclkDiv11 Clock source: HCLK/11 + ** \arg QspiHclkDiv12 Clock source: HCLK/12 + ** \arg QspiHclkDiv13 Clock source: HCLK/13 + ** \arg QspiHclkDiv14 Clock source: HCLK/14 + ** \arg QspiHclkDiv15 Clock source: HCLK/15 + ** \arg QspiHclkDiv16 Clock source: HCLK/16 + ** \arg QspiHclkDiv17 Clock source: HCLK/17 + ** \arg QspiHclkDiv18 Clock source: HCLK/18 + ** \arg QspiHclkDiv19 Clock source: HCLK/19 + ** \arg QspiHclkDiv20 Clock source: HCLK/20 + ** \arg QspiHclkDiv21 Clock source: HCLK/21 + ** \arg QspiHclkDiv22 Clock source: HCLK/22 + ** \arg QspiHclkDiv23 Clock source: HCLK/23 + ** \arg QspiHclkDiv24 Clock source: HCLK/24 + ** \arg QspiHclkDiv25 Clock source: HCLK/25 + ** \arg QspiHclkDiv26 Clock source: HCLK/26 + ** \arg QspiHclkDiv27 Clock source: HCLK/27 + ** \arg QspiHclkDiv28 Clock source: HCLK/28 + ** \arg QspiHclkDiv29 Clock source: HCLK/29 + ** \arg QspiHclkDiv30 Clock source: HCLK/30 + ** \arg QspiHclkDiv31 Clock source: HCLK/31 + ** \arg QspiHclkDiv32 Clock source: HCLK/32 + ** \arg QspiHclkDiv33 Clock source: HCLK/33 + ** \arg QspiHclkDiv34 Clock source: HCLK/34 + ** \arg QspiHclkDiv35 Clock source: HCLK/35 + ** \arg QspiHclkDiv36 Clock source: HCLK/36 + ** \arg QspiHclkDiv37 Clock source: HCLK/37 + ** \arg QspiHclkDiv38 Clock source: HCLK/38 + ** \arg QspiHclkDiv39 Clock source: HCLK/39 + ** \arg QspiHclkDiv40 Clock source: HCLK/40 + ** \arg QspiHclkDiv41 Clock source: HCLK/41 + ** \arg QspiHclkDiv42 Clock source: HCLK/42 + ** \arg QspiHclkDiv43 Clock source: HCLK/43 + ** \arg QspiHclkDiv44 Clock source: HCLK/44 + ** \arg QspiHclkDiv45 Clock source: HCLK/45 + ** \arg QspiHclkDiv46 Clock source: HCLK/46 + ** \arg QspiHclkDiv47 Clock source: HCLK/47 + ** \arg QspiHclkDiv48 Clock source: HCLK/48 + ** \arg QspiHclkDiv49 Clock source: HCLK/49 + ** \arg QspiHclkDiv50 Clock source: HCLK/50 + ** \arg QspiHclkDiv51 Clock source: HCLK/51 + ** \arg QspiHclkDiv52 Clock source: HCLK/52 + ** \arg QspiHclkDiv53 Clock source: HCLK/53 + ** \arg QspiHclkDiv54 Clock source: HCLK/54 + ** \arg QspiHclkDiv55 Clock source: HCLK/55 + ** \arg QspiHclkDiv56 Clock source: HCLK/56 + ** \arg QspiHclkDiv57 Clock source: HCLK/57 + ** \arg QspiHclkDiv58 Clock source: HCLK/58 + ** \arg QspiHclkDiv59 Clock source: HCLK/59 + ** \arg QspiHclkDiv60 Clock source: HCLK/60 + ** \arg QspiHclkDiv61 Clock source: HCLK/61 + ** \arg QspiHclkDiv62 Clock source: HCLK/62 + ** \arg QspiHclkDiv63 Clock source: HCLK/63 + ** \arg QspiHclkDiv64 Clock source: HCLK/64 + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetClockDiv(en_qspi_clk_div_t enClkDiv) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_CLK_DIV(enClkDiv)); + + M4_QSPI->CR_f.DIV = enClkDiv; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set WP Pin level + ** + ** \param [in] enWpLevel WP pin level + ** \arg QspiWpPinOutputLow WP pin(QIO2) output low level + ** \arg QspiWpPinOutputHigh WP pin(QIO2) output high level + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetWPPinLevel(en_qspi_wp_pin_level_t enWpLevel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_WP_OUTPUT_LEVEL(enWpLevel)); + + M4_QSPI->FCR_f.WPOL = enWpLevel; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set communication address width + ** + ** \param [in] enAddrWidth Communication address width + ** \arg QspiAddressByteOne One byte address + ** \arg QspiAddressByteTwo Two byte address + ** \arg QspiAddressByteThree Three byte address + ** \arg QspiAddressByteFour Four byte address + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetAddrWidth(en_qspi_addr_width_t enAddrWidth) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_INTERFACE_ADDR_WIDTH(enAddrWidth)); + + M4_QSPI->FCR_f.AWSL = enAddrWidth; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set extend address value + ** + ** \param [in] u8Addr Extend address value + ** \arg 0~0x3F + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetExtendAddress(uint8_t u8Addr) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_SET_EXTEND_ADDR(u8Addr)); + + M4_QSPI->EXAR_f.EXADR = u8Addr; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set rom access instruction + ** + ** \param [in] u8Instr Rom access instruction + ** \arg 0~0xFF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetRomAccessInstruct(uint8_t u8Instr) +{ + en_result_t enRet = Ok; + + M4_QSPI->CCMD = u8Instr; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write direct communication value + ** + ** \param [in] u8Val Direct communication value + ** \arg 0~0xFF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_WriteDirectCommValue(uint8_t u8Val) +{ + en_result_t enRet = Ok; + + M4_QSPI->DCOM = u8Val; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read direct communication value + ** + ** \param [in] None + ** + ** \retval uint8_t Direct communication read value + ** + ******************************************************************************/ +uint8_t QSPI_ReadDirectCommValue(void) +{ + return ((uint8_t)M4_QSPI->DCOM); +} + +/** + ******************************************************************************* + ** \brief Enable or disable xip mode + ** + ** \param [in] u8Instr Enable or disable xip mode instruction + ** \arg 0~0xFF + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable xip mode + ** \arg Enable Enable xip mode + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_XipModeCmd(uint8_t u8Instr, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_QSPI->XCMD = u8Instr; + if (Enable == enNewSta) + { + M4_QSPI->CR_f.XIPE = 1u; + } + else + { + M4_QSPI->CR_f.XIPE = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enter direct communication mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ** \note If you are in XIP mode, you need to exit XIP mode and then start direct communication mode. + ** + ******************************************************************************/ +en_result_t QSPI_EnterDirectCommMode(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR_f.DCOME = 1u; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Exit direct communication mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_ExitDirectCommMode(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR_f.DCOME = 0u; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get prefetch buffer current byte number + ** + ** \param [in] None + ** + ** \retval uint8_t Current buffer byte number + ** + ******************************************************************************/ +uint8_t QSPI_GetPrefetchBufferNum(void) +{ + return ((uint8_t)M4_QSPI->SR_f.PFNUM); +} + +/** + ******************************************************************************* + ** \brief Get flag status + ** + ** \param [in] enFlag Choose need get status's flag + ** \arg QspiFlagBusBusy QSPI bus work status flag in direct communication mode + ** \arg QspiFlagXipMode XIP mode status signal + ** \arg QspiFlagRomAccessError Trigger rom access error flag in direct communication mode + ** \arg QspiFlagPrefetchBufferFull Prefetch buffer area status signal + ** \arg QspiFlagPrefetchStop Prefetch action status signal + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t QSPI_GetFlag(en_qspi_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + DDL_ASSERT(IS_VALID_GET_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case QspiFlagBusBusy: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.BUSY; + break; + case QspiFlagXipMode: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.XIPF; + break; + case QspiFlagRomAccessError: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.RAER; + break; + case QspiFlagPrefetchBufferFull: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.PFFUL; + break; + case QspiFlagPrefetchStop: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.PFAN; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear flag status + ** + ** \param [in] enFlag Choose need get status's flag + ** \arg QspiFlagRomAccessError Trigger rom access error flag in direct communication mode + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_ClearFlag(en_qspi_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + if (QspiFlagRomAccessError == enFlag) + { + M4_QSPI->SR2_f.RAERCLR = 1u; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +//@} // QspiGroup + +#endif /* DDL_QSPI_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_rmu.c b/driver/src/hc32f460_rmu.c new file mode 100644 index 0000000..301f462 --- /dev/null +++ b/driver/src/hc32f460_rmu.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rmu.c + ** + ** A detailed description is available at + ** @link RmuGroup RMU description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of RMU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_rmu.h" +#include "hc32f460_utility.h" + +#if (DDL_RMU_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup RmuGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define ENABLE_RMU_REG_WRITE() (M4_SYSREG->PWR_FPRC = 0xa502u) +#define DISABLE_RMU_REG_WRITE() (M4_SYSREG->PWR_FPRC = 0xa500u) + +#define RMU_FLAG_TIM ((uint16_t)0x1000u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Get the chip reset cause. + ** + ** \param [in] pstcData Pointer to return reset cause structure. + ** + ** \retval Ok Get successfully. + ** + ******************************************************************************/ +en_result_t RMU_GetResetCause(stc_rmu_rstcause_t *pstcData) +{ + uint16_t u16RstCause = 0u; + stc_sysreg_rmu_rstf0_field_t *RMU_RSTF0_f = NULL; + + if(NULL == pstcData) + { + return ErrorInvalidParameter; + } + + u16RstCause = M4_SYSREG->RMU_RSTF0; + RMU_RSTF0_f = (stc_sysreg_rmu_rstf0_field_t *)(&u16RstCause); + + pstcData->enMultiRst = (en_flag_status_t)(RMU_RSTF0_f->MULTIRF == 1u); + pstcData->enXtalErr = (en_flag_status_t)(RMU_RSTF0_f->XTALERF == 1u); + pstcData->enClkFreqErr = (en_flag_status_t)(RMU_RSTF0_f->CKFERF == 1u); + pstcData->enRamEcc = (en_flag_status_t)(RMU_RSTF0_f->RAECRF == 1u); + pstcData->enRamParityErr = (en_flag_status_t)(RMU_RSTF0_f->RAPERF == 1u); + pstcData->enMpuErr = (en_flag_status_t)(RMU_RSTF0_f->MPUERF == 1u); + pstcData->enSoftware = (en_flag_status_t)(RMU_RSTF0_f->SWRF == 1u); + pstcData->enPowerDown = (en_flag_status_t)(RMU_RSTF0_f->PDRF == 1u); + pstcData->enSwdt = (en_flag_status_t)(RMU_RSTF0_f->SWDRF == 1u); + pstcData->enWdt = (en_flag_status_t)(RMU_RSTF0_f->WDRF == 1u); + pstcData->enPvd2 = (en_flag_status_t)(RMU_RSTF0_f->PVD2RF == 1u); + pstcData->enPvd1 = (en_flag_status_t)(RMU_RSTF0_f->PVD2RF == 1u); + pstcData->enBrownOut = (en_flag_status_t)(RMU_RSTF0_f->BORF == 1u); + pstcData->enRstPin = (en_flag_status_t)(RMU_RSTF0_f->PINRF == 1u); + pstcData->enPowerOn = (en_flag_status_t)(RMU_RSTF0_f->PORF == 1u); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Clear the reset flag. + ** + ** \param None + ** + ** \retval Ok Clear successfully. + ** + ** \note clear reset flag should be done after read RMU_RSTF0 register. + ******************************************************************************/ +en_result_t RMU_ClrResetFlag(void) +{ + uint16_t u16status = 0u; + uint32_t u32timeout = 0u; + + ENABLE_RMU_REG_WRITE(); + + do + { + u32timeout++; + M4_SYSREG->RMU_RSTF0_f.CLRF = 1u; + u16status = M4_SYSREG->RMU_RSTF0; + }while((u32timeout != RMU_FLAG_TIM) && u16status); + + DISABLE_RMU_REG_WRITE(); + + if(u32timeout >= RMU_FLAG_TIM) + { + return ErrorTimeout; + } + + return Ok; +} + + +//@} // RmuGroup + +#endif /* DDL_RMU_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/src/hc32f460_rtc.c b/driver/src/hc32f460_rtc.c new file mode 100644 index 0000000..577f46f --- /dev/null +++ b/driver/src/hc32f460_rtc.c @@ -0,0 +1,978 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rtc.c + ** + ** A detailed description is available at + ** @link RtcGroup Real-Time Clock description @endlink + ** + ** - 2018-11-22 CDT First version for Device Driver Library of RTC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_rtc.h" +#include "hc32f460_utility.h" + +#if (DDL_RTC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup RtcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for clock source type */ +#define IS_VALID_CLK_SOURCE_TYPE(x) \ +( (RtcClkXtal32 == (x)) || \ + (RtcClkLrc == (x))) + +/*!< Parameter valid check for period interrupt condition */ +#define IS_VALID_PERIOD_INT_CONDITION(x) \ +( (RtcPeriodIntInvalid == (x)) || \ + (RtcPeriodIntHalfSec == (x)) || \ + (RtcPeriodIntOneSec == (x)) || \ + (RtcPeriodIntOneMin == (x)) || \ + (RtcPeriodIntOneHour == (x)) || \ + (RtcPeriodIntOneDay == (x)) || \ + (RtcPeriodIntOneMon == (x))) + +/*!< Parameter valid check for time format */ +#define IS_VALID_TIME_FORMAT(x) \ +( (RtcTimeFormat12Hour == (x)) || \ + (RtcTimeFormat24Hour == (x))) + +/*!< Parameter valid check for compensation way */ +#define IS_VALID_COMPEN_WAY(x) \ +( (RtcOutputCompenDistributed == (x)) || \ + (RtcOutputCompenUniform == (x))) + +/*!< Parameter valid check for compensation value range */ +#define IS_VALID_COMPEN_VALUE_RANGE(x) ((x) <= 0x1FFu) + +/*!< Parameter valid check for data format */ +#define IS_VALID_DATA_FORMAT(x) \ +( (RtcDataFormatDec == (x)) || \ + (RtcDataFormatBcd == (x))) + +/*!< Parameter valid check for time second */ +#define IS_VALID_TIME_SECOND(x) ((x) <= 59u) + +/*!< Parameter valid check for time minute */ +#define IS_VALID_TIME_MINUTE(x) ((x) <= 59u) + +/*!< Parameter valid check for time hour */ +#define IS_VALID_TIME_HOUR12(x) (((x) >= 1u) && ((x) <= 12u)) +#define IS_VALID_TIME_HOUR24(x) ((x) <= 23u) + +/*!< Parameter valid check for date weekday */ +#define IS_VALID_DATE_WEEKDAY(x) ((x) <= 6u) + +/*!< Parameter valid check for date day */ +#define IS_VALID_DATE_DAY(x) (((x) >= 1u) && ((x) <= 31u)) + +/*!< Parameter valid check for date month */ +#define IS_VALID_DATE_MONTH(x) (((x) >= 1u) && ((x) <= 12u)) + +/*!< Parameter valid check for date year */ +#define IS_VALID_DATE_YEAR(x) ((x) <= 99u) + +/*!< Parameter valid check for hour12 am/pm */ +#define IS_VALID_HOUR12_AMPM(x) \ +( (RtcHour12Am == (x)) || \ + (RtcHour12Pm == (x))) + +/*!< Parameter valid check for alarm weekday */ +#define IS_VALID_ALARM_WEEKDAY(x) (((x) >= 1u) && ((x) <= 0x7Fu)) + +/*!< Parameter valid check for interrupt request type */ +#define IS_VALID_IRQ_TYPE(x) \ +( (RtcIrqPeriod == (x)) || \ + (RtcIrqAlarm == (x))) + +/*!< 12 hour format am/pm status bit */ +#define RTC_HOUR12_AMPM_MASK (0x20u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize RTC + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout De-Initialize timeout + ** + ******************************************************************************/ +en_result_t RTC_DeInit(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + M4_RTC->CR0_f.RESET = 0u; + /* Waiting for normal count status or end of RTC software reset */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR0_f.RESET; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + /* Initialize all RTC registers */ + M4_RTC->CR0_f.RESET = 1u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize RTC + ** + ** \param [in] pstcRtcInit Pointer to RTC init configuration + ** \arg See the struct #stc_rtc_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcInit) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CLK_SOURCE_TYPE(pstcRtcInit->enClkSource)); + DDL_ASSERT(IS_VALID_PERIOD_INT_CONDITION(pstcRtcInit->enPeriodInt)); + DDL_ASSERT(IS_VALID_TIME_FORMAT(pstcRtcInit->enTimeFormat)); + DDL_ASSERT(IS_VALID_COMPEN_WAY(pstcRtcInit->enCompenWay)); + DDL_ASSERT(IS_VALID_COMPEN_VALUE_RANGE(pstcRtcInit->u16CompenVal)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcRtcInit->enCompenEn)); + + /* Configure clock */ + if (RtcClkLrc == pstcRtcInit->enClkSource) + { + M4_RTC->CR3_f.LRCEN = 1u; + } + M4_RTC->CR3_f.RCKSEL = pstcRtcInit->enClkSource; + + /* Configure control register */ + M4_RTC->CR1_f.PRDS = pstcRtcInit->enPeriodInt; + M4_RTC->CR1_f.AMPM = pstcRtcInit->enTimeFormat; + M4_RTC->CR1_f.ONEHZSEL = pstcRtcInit->enCompenWay; + + /* Configure clock error compensation register */ + M4_RTC->ERRCRH_f.COMP8 = ((uint32_t)pstcRtcInit->u16CompenVal >> 8u) & 0x01u; + M4_RTC->ERRCRL = (uint32_t)pstcRtcInit->u16CompenVal & 0x00FFu; + M4_RTC->ERRCRH_f.COMPEN = pstcRtcInit->enCompenEn; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enter RTC read/write mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout Enter mode timeout + ** + ******************************************************************************/ +en_result_t RTC_EnterRwMode(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + /* Mode switch when RTC is running */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 1u; + /* Waiting for RWEN bit set */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 0u)); + + if (0u == u8RegSta) + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Exit RTC read/write mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout Exit mode timeout + ** + ******************************************************************************/ +en_result_t RTC_ExitRwMode(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + /* Mode switch when RTC is running */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 0u; + /* Waiting for RWEN bit reset */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC count + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC count + ** \arg Enable Enable RTC count + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_Cmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->CR1_f.START = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief RTC period interrupt config + ** + ** \param [in] enIntType Period interrupt request type + ** \arg RtcPeriodIntInvalid Period interrupt invalid + ** \arg RtcPeriodIntHalfSec 0.5 second period interrupt + ** \arg RtcPeriodIntOneSec 1 second period interrupt + ** \arg RtcPeriodIntOneMin 1 minute period interrupt + ** \arg RtcPeriodIntOneHour 1 hour period interrupt + ** \arg RtcPeriodIntOneDay 1 day period interrupt + ** \arg RtcPeriodIntOneMon 1 month period interrupt + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_PeriodIntConfig(en_rtc_period_int_type_t enIntType) +{ + uint8_t u8RtcSta; + uint8_t u8IntSta; + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PERIOD_INT_CONDITION(enIntType)); + + u8RtcSta = (uint8_t)M4_RTC->CR1_f.START; + u8IntSta = (uint8_t)M4_RTC->CR2_f.PRDIE; + /* Disable period interrupt when START=1 and PRDIE=1 */ + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.PRDIE = 0u; + } + M4_RTC->CR1_f.PRDS = enIntType; + + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.PRDIE = 1u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief RTC switch to low power mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidMode RTC count not start + ** \retval ErrorTimeout Switch timeout + ** + ******************************************************************************/ +en_result_t RTC_LowPowerSwitch(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = ErrorInvalidMode; + + /* Check RTC work status */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 1u; + /* Waiting for RTC RWEN bit set */ + u32Timeout = SystemCoreClock / 100u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 0u)); + + if (0u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + M4_RTC->CR2_f.RWREQ = 0u; + /* Waiting for RTC RWEN bit reset */ + u32TimeCnt = 0u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + enRet = Ok; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC 1hz output compensation value + ** + ** \param [in] u16CompenVal Clock compensation value + ** \arg 0~0x1FF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_SetClkCompenValue(uint16_t u16CompenVal) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COMPEN_VALUE_RANGE(u16CompenVal)); + + M4_RTC->ERRCRH_f.COMP8 = ((uint32_t)u16CompenVal >> 8u) & 0x01u; + M4_RTC->ERRCRL = (uint32_t)u16CompenVal & 0x00FFu; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable clock compensation + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC clock compensation + ** \arg Enable Enable RTC clock compensation + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_ClkCompenCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->ERRCRH_f.COMPEN = enNewSta; + + return enRet; +} + + +/** + ******************************************************************************* + ** \brief Enable or disable RTC 1hz output + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC 1hz output + ** \arg Enable Enable RTC 1hz output + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_OneHzOutputCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->CR1_f.ONEHZOE = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC current date and time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [in] pstcRtcDateTime Pointer to RTC date and time configuration + ** \arg See the struct #stc_rtc_date_time_t + ** + ** \param [in] enUpdateDateEn The function new state(Contain year/month/day/weekday) + ** \arg Disable Disable update RTC date + ** \arg Enable Enable update RTC date + ** + ** \param [in] enUpdateTimeEn The function new state(Contain hour/minute/second) + ** \arg Disable Disable update RTC time + ** \arg Enable Enable update RTC time + ** + ** \retval Ok Process successfully done + ** \retval Error Enter or exit read/write mode failed + ** \retval ErrorInvalidParameter Parameter enUpdateDateEn or enUpdateTimeEn invalid + ** + ******************************************************************************/ +en_result_t RTC_SetDateTime(en_rtc_data_format_t enFormat, const stc_rtc_date_time_t *pstcRtcDateTime, + en_functional_state_t enUpdateDateEn, en_functional_state_t enUpdateTimeEn) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enUpdateDateEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enUpdateTimeEn)); + + /* Check update status */ + if (((Disable == enUpdateDateEn) && (Disable == enUpdateTimeEn)) || (NULL == pstcRtcDateTime)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check the date parameters */ + if (Enable == enUpdateDateEn) + { + if (RtcDataFormatDec == enFormat) + { + DDL_ASSERT(IS_VALID_DATE_YEAR(pstcRtcDateTime->u8Year)); + DDL_ASSERT(IS_VALID_DATE_MONTH(pstcRtcDateTime->u8Month)); + DDL_ASSERT(IS_VALID_DATE_DAY(pstcRtcDateTime->u8Day)); + } + else + { + DDL_ASSERT(IS_VALID_DATE_YEAR(BCD2DEC(pstcRtcDateTime->u8Year))); + DDL_ASSERT(IS_VALID_DATE_MONTH(BCD2DEC(pstcRtcDateTime->u8Month))); + DDL_ASSERT(IS_VALID_DATE_DAY(BCD2DEC(pstcRtcDateTime->u8Day))); + } + DDL_ASSERT(IS_VALID_DATE_WEEKDAY(pstcRtcDateTime->u8Weekday)); + } + /* Check the time parameters */ + if (Enable == enUpdateTimeEn) + { + if (RtcDataFormatDec == enFormat) + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(pstcRtcDateTime->u8Hour)); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcDateTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(pstcRtcDateTime->u8Hour)); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(pstcRtcDateTime->u8Minute)); + DDL_ASSERT(IS_VALID_TIME_SECOND(pstcRtcDateTime->u8Second)); + } + else + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(BCD2DEC(pstcRtcDateTime->u8Hour))); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcDateTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(BCD2DEC(pstcRtcDateTime->u8Hour))); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(BCD2DEC(pstcRtcDateTime->u8Minute))); + DDL_ASSERT(IS_VALID_TIME_SECOND(BCD2DEC(pstcRtcDateTime->u8Second))); + } + } + + /* Enter read/write mode */ + if (RTC_EnterRwMode() == ErrorTimeout) + { + enRet = Error; + } + else + { + /* Update date */ + if (Enable == enUpdateDateEn) + { + if (RtcDataFormatDec == enFormat) + { + M4_RTC->YEAR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Year); + M4_RTC->MON = DEC2BCD((uint32_t)pstcRtcDateTime->u8Month); + M4_RTC->DAY = DEC2BCD((uint32_t)pstcRtcDateTime->u8Day); + } + else + { + M4_RTC->YEAR = pstcRtcDateTime->u8Year; + M4_RTC->MON = pstcRtcDateTime->u8Month; + M4_RTC->DAY = pstcRtcDateTime->u8Day; + } + M4_RTC->WEEK = pstcRtcDateTime->u8Weekday; + } + /* Update time */ + if (Enable == enUpdateTimeEn) + { + if (RtcDataFormatDec == enFormat) + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcDateTime->enAmPm)) + { + M4_RTC->HOUR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Hour) | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->HOUR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Hour); + } + M4_RTC->MIN = DEC2BCD((uint32_t)pstcRtcDateTime->u8Minute); + M4_RTC->SEC = DEC2BCD((uint32_t)pstcRtcDateTime->u8Second); + } + else + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcDateTime->enAmPm)) + { + M4_RTC->HOUR = (uint32_t)pstcRtcDateTime->u8Hour | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->HOUR = (uint32_t)pstcRtcDateTime->u8Hour; + } + M4_RTC->MIN = pstcRtcDateTime->u8Minute; + M4_RTC->SEC = pstcRtcDateTime->u8Second; + } + } + /* Exit read/write mode */ + if (RTC_ExitRwMode() == ErrorTimeout) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC current date and time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [out] pstcRtcDateTime Pointer to RTC date and time configuration + ** \arg See the struct #stc_rtc_date_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Enter or exit read/write mode failed + ** + ******************************************************************************/ +en_result_t RTC_GetDateTime(en_rtc_data_format_t enFormat, stc_rtc_date_time_t *pstcRtcDateTime) +{ + en_result_t enRet = Ok; + + if(NULL == pstcRtcDateTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + /* Enter read/write mode */ + if (RTC_EnterRwMode() == ErrorTimeout) + { + enRet = Error; + } + else + { + /* Get RTC date and time registers */ + pstcRtcDateTime->u8Year = (uint8_t)(M4_RTC->YEAR); + pstcRtcDateTime->u8Month = (uint8_t)(M4_RTC->MON); + pstcRtcDateTime->u8Day = (uint8_t)(M4_RTC->DAY); + pstcRtcDateTime->u8Weekday = (uint8_t)(M4_RTC->WEEK); + pstcRtcDateTime->u8Hour = (uint8_t)(M4_RTC->HOUR); + pstcRtcDateTime->u8Minute = (uint8_t)(M4_RTC->MIN); + pstcRtcDateTime->u8Second = (uint8_t)(M4_RTC->SEC); + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + if (RTC_HOUR12_AMPM_MASK == (pstcRtcDateTime->u8Hour & RTC_HOUR12_AMPM_MASK)) + { + pstcRtcDateTime->u8Hour &= (uint8_t)(~RTC_HOUR12_AMPM_MASK); + pstcRtcDateTime->enAmPm = RtcHour12Pm; + } + else + { + pstcRtcDateTime->enAmPm = RtcHour12Am; + } + } + + /* Check decimal format*/ + if (RtcDataFormatDec == enFormat) + { + pstcRtcDateTime->u8Year = BCD2DEC(pstcRtcDateTime->u8Year); + pstcRtcDateTime->u8Month = BCD2DEC(pstcRtcDateTime->u8Month); + pstcRtcDateTime->u8Day = BCD2DEC(pstcRtcDateTime->u8Day); + pstcRtcDateTime->u8Hour = BCD2DEC(pstcRtcDateTime->u8Hour); + pstcRtcDateTime->u8Minute = BCD2DEC(pstcRtcDateTime->u8Minute); + pstcRtcDateTime->u8Second = BCD2DEC(pstcRtcDateTime->u8Second); + } + + /* exit read/write mode */ + if (RTC_ExitRwMode() == ErrorTimeout) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC alarm time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [in] pstcRtcAlarmTime Pointer to RTC alarm time configuration + ** \arg See the struct #stc_rtc_alarm_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_SetAlarmTime(en_rtc_data_format_t enFormat, const stc_rtc_alarm_time_t *pstcRtcAlarmTime) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcAlarmTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + if (RtcDataFormatDec == enFormat) + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(pstcRtcAlarmTime->u8Hour)); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcAlarmTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(pstcRtcAlarmTime->u8Hour)); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(pstcRtcAlarmTime->u8Minute)); + } + else + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(BCD2DEC(pstcRtcAlarmTime->u8Hour))); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcAlarmTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(BCD2DEC(pstcRtcAlarmTime->u8Hour))); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(BCD2DEC(pstcRtcAlarmTime->u8Minute))); + } + DDL_ASSERT(IS_VALID_ALARM_WEEKDAY(pstcRtcAlarmTime->u8Weekday)); + + /* Configure alarm registers */ + if (RtcDataFormatDec == enFormat) + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcAlarmTime->enAmPm)) + { + M4_RTC->ALMHOUR = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Hour) | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->ALMHOUR = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Hour); + } + M4_RTC->ALMMIN = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Minute); + } + else + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcAlarmTime->enAmPm)) + { + M4_RTC->ALMHOUR = (uint32_t)pstcRtcAlarmTime->u8Hour | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->ALMHOUR = (uint32_t)pstcRtcAlarmTime->u8Hour; + } + M4_RTC->ALMMIN = pstcRtcAlarmTime->u8Minute; + } + M4_RTC->ALMWEEK = pstcRtcAlarmTime->u8Weekday; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC alarm time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [out] pstcRtcAlarmTime Pointer to RTC alarm time configuration + ** \arg See the struct #stc_rtc_alarm_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_GetAlarmTime(en_rtc_data_format_t enFormat, stc_rtc_alarm_time_t *pstcRtcAlarmTime) +{ + en_result_t enRet = Ok; + + if(NULL == pstcRtcAlarmTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + /* Get RTC date and time register */ + pstcRtcAlarmTime->u8Weekday = (uint8_t)M4_RTC->ALMWEEK; + pstcRtcAlarmTime->u8Minute = (uint8_t)M4_RTC->ALMMIN; + pstcRtcAlarmTime->u8Hour = (uint8_t)M4_RTC->ALMHOUR; + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + if ((pstcRtcAlarmTime->u8Hour & RTC_HOUR12_AMPM_MASK) == RTC_HOUR12_AMPM_MASK) + { + pstcRtcAlarmTime->u8Hour &= (uint8_t)(~RTC_HOUR12_AMPM_MASK); + pstcRtcAlarmTime->enAmPm = RtcHour12Pm; + } + else + { + pstcRtcAlarmTime->enAmPm = RtcHour12Am; + } + } + + /* Check decimal format*/ + if (RtcDataFormatDec == enFormat) + { + pstcRtcAlarmTime->u8Hour = BCD2DEC(pstcRtcAlarmTime->u8Hour); + pstcRtcAlarmTime->u8Minute = BCD2DEC(pstcRtcAlarmTime->u8Minute); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC alarm function + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC alarm function + ** \arg Enable Enable RTC alarm function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_AlarmCmd(en_functional_state_t enNewSta) +{ + uint8_t u8RtcSta; + uint8_t u8IntSta; + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u8RtcSta = (uint8_t)M4_RTC->CR1_f.START; + u8IntSta = (uint8_t)M4_RTC->CR2_f.ALMIE; + /* Disable alarm interrupt and clear alarm flag when START=1 and ALMIE=1 */ + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.ALMIE = 0u; + } + M4_RTC->CR2_f.ALME = enNewSta; + + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR1_f.ALMFCLR = 0u; + M4_RTC->CR2_f.ALMIE = u8IntSta; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC interrupt request + ** + ** \param [in] enIrq RTC interrupt request type + ** \arg RtcIrqPeriod Period count interrupt request + ** \arg RtcIrqAlarm Alarm interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_IrqCmd(en_rtc_irq_type_t enIrq, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_IRQ_TYPE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + /* enable/disable interrupt */ + switch (enIrq) + { + case RtcIrqPeriod: + M4_RTC->CR2_f.PRDIE = enNewSta; + break; + case RtcIrqAlarm: + M4_RTC->CR2_f.ALMIE = enNewSta; + break; + default: + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC Alarm flag status + ** + ** \param [in] None + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t RTC_GetAlarmFlag(void) +{ + return (en_flag_status_t)(M4_RTC->CR2_f.ALMF); +} + +/** + ******************************************************************************* + ** \brief Clear RTC Alarm flag status + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_ClearAlarmFlag(void) +{ + en_result_t enRet = Ok; + + M4_RTC->CR1_f.ALMFCLR = 0u; + + return enRet; +} + +//@} // RtcGroup + +#endif /* DDL_RTC_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/driver/src/hc32f460_sdioc.c b/driver/src/hc32f460_sdioc.c new file mode 100644 index 0000000..4a70252 --- /dev/null +++ b/driver/src/hc32f460_sdioc.c @@ -0,0 +1,2222 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sdioc.c + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-11 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_sdioc.h" +#include "hc32f460_utility.h" + +#if (DDL_SDIOC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SdiocGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief SDIOC internal data + ** + ******************************************************************************/ +typedef struct stc_sdioc_intern_data +{ + stc_sdioc_normal_irq_cb_t stcNormalIrqCb; ///< Normal irq callback function structure + + stc_sdioc_error_irq_cb_t stcErrorIrqCb; ///< Error irq callback function structure +} stc_sdioc_intern_data_t; + +/** + ******************************************************************************* + ** \brief SDIOC instance data + ** + ******************************************************************************/ +typedef struct stc_sdioc_instance_data +{ + const M4_SDIOC_TypeDef *SDIOCx; ///< pointer to registers of an instance + + stc_sdioc_intern_data_t stcInternData; ///< module internal data of instance +} stc_sdioc_instance_data_t; + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for SDIOC Instances. */ +#define IS_VALID_SDIOC(__SDIOCx__) \ +( (M4_SDIOC1 == (__SDIOCx__)) || \ + (M4_SDIOC2 == (__SDIOCx__))) + +/*!< Parameter valid check for SDIOC mode. */ +#define IS_VALID_SDIOC_MODE(x) \ +( (SdiocModeSD == (x)) || \ + (SdiocModeMMC == (x))) + +/*!< Parameter valid check for SDIOC Response Register. */ +#define IS_VALID_SDIOC_RESP(x) \ +( (SdiocRegResp01 == (x)) || \ + (SdiocRegResp23 == (x)) || \ + (SdiocRegResp45 == (x)) || \ + (SdiocRegResp67 == (x))) + +/*!< Parameter valid check for SDIOC bus width. */ +#define IS_VALID_SDIOC_BUS_WIDTH(x) \ +( (SdiocBusWidth1Bit == (x)) || \ + (SdiocBusWidth4Bit == (x)) || \ + (SdiocBusWidth8Bit == (x))) + +/*!< Parameter valid check for SDIOC speed mode. */ +#define IS_VALID_SDIOC_SPEED_MODE(x) \ +( (SdiocHighSpeedMode == (x)) || \ + (SdiocNormalSpeedMode == (x))) + +/*!< Parameter valid check for SDIOC Clock division. */ +#define IS_VALID_SDIOC_CLK_DIV(x) \ +( (SdiocClkDiv_1 == (x)) || \ + (SdiocClkDiv_2 == (x)) || \ + (SdiocClkDiv_4 == (x)) || \ + (SdiocClkDiv_8 == (x)) || \ + (SdiocClkDiv_16 == (x)) || \ + (SdiocClkDiv_32 == (x)) || \ + (SdiocClkDiv_64 == (x)) || \ + (SdiocClkDiv_128 == (x)) || \ + (SdiocClkDiv_256 == (x))) + +/*!< Parameter valid check for SDIOC command type. */ +#define IS_VALID_SDIOC_CMD_TYPE(x) \ +( (SdiocCmdAbort == (x)) || \ + (SdiocCmdResume == (x)) || \ + (SdiocCmdNormal == (x)) || \ + (SdiocCmdSuspend == (x))) + +/*!< Parameter valid check for SDIOC data transfer direction. */ +#define IS_VALID_SDIOC_TRANSFER_DIR(x) \ +( (SdiocTransferToCard == (x)) || \ + (SdiocTransferToHost == (x))) + +/*!< Parameter valid check for SDIOC software reset type. */ +#define IS_VALID_SDIOC_SWRESETTYPE(x) \ +( (SdiocSwResetAll == (x)) || \ + (SdiocSwResetCmdLine == (x)) || \ + (SdiocSwResetDatLine == (x))) + +/*!< Parameter valid check for SDIOC data transfer mode. */ +#define IS_VALID_SDIOC_TRANSFER_MODE(x) \ +( (SdiocTransferSingle == (x)) || \ + (SdiocTransferInfinite == (x)) || \ + (SdiocTransferMultiple == (x)) || \ + (SdiocTransferStopMultiple == (x))) + +/*!< Parameter valid check for SDIOC data timeout. */ +#define IS_VALID_SDIOC_DATA_TIMEOUT(x) \ +( (SdiocDtoSdclk_2_13 == (x)) || \ + (SdiocDtoSdclk_2_14 == (x)) || \ + (SdiocDtoSdclk_2_15 == (x)) || \ + (SdiocDtoSdclk_2_16 == (x)) || \ + (SdiocDtoSdclk_2_17 == (x)) || \ + (SdiocDtoSdclk_2_18 == (x)) || \ + (SdiocDtoSdclk_2_19 == (x)) || \ + (SdiocDtoSdclk_2_20 == (x)) || \ + (SdiocDtoSdclk_2_21 == (x)) || \ + (SdiocDtoSdclk_2_22 == (x)) || \ + (SdiocDtoSdclk_2_23 == (x)) || \ + (SdiocDtoSdclk_2_24 == (x)) || \ + (SdiocDtoSdclk_2_25 == (x)) || \ + (SdiocDtoSdclk_2_26 == (x)) || \ + (SdiocDtoSdclk_2_27 == (x))) + +/*!< Parameter valid check for SDIOC Response type name. */ +#define IS_VALID_SDIOC_RESP_TYPE_NAME(x) \ +( (SdiocCmdRspR1 == (x)) || \ + (SdiocCmdRspR1b == (x)) || \ + (SdiocCmdRspR2 == (x)) || \ + (SdiocCmdRspR3 == (x)) || \ + (SdiocCmdRspR4 == (x)) || \ + (SdiocCmdRspR5 == (x)) || \ + (SdiocCmdRspR5b == (x)) || \ + (SdiocCmdRspR6 == (x)) || \ + (SdiocCmdRspR7 == (x)) || \ + (SdiocCmdNoRsp == (x))) + +/*!< Parameter valid check for SDIOC data timeout. */ +#define IS_VALID_SDIOC_HOST_STATUS(x) \ +( (SdiocCmdPinLvl == (x)) || \ + (SdiocData0PinLvl == (x)) || \ + (SdiocData1PinLvl == (x)) || \ + (SdiocData2PinLvl == (x)) || \ + (SdiocData3PinLvl == (x)) || \ + (SdiocCardInserted == (x)) || \ + (SdiocDataLineActive == (x)) || \ + (SdiocCardStateStable == (x)) || \ + (SdiocBufferReadEnble == (x)) || \ + (SdiocBufferWriteEnble == (x)) || \ + (SdiocCardDetectPinLvl == (x)) || \ + (SdiocCommandInhibitCmd == (x)) || \ + (SdiocWriteProtectPinLvl == (x)) || \ + (SdiocCommandInhibitData == (x)) || \ + (SdiocReadTransferActive == (x)) || \ + (SdiocWriteTransferActive == (x))) + +/*!< Parameter valid check for SDIOC normal interrupt. */ +#define IS_VALID_SDIOC_NOR_INT(x) \ +( (SdiocCardInt == (x)) || \ + (SdiocErrorInt == (x)) || \ + (SdiocCardRemoval == (x)) || \ + (SdiocBlockGapEvent == (x)) || \ + (SdiocCardInsertedInt == (x)) || \ + (SdiocCommandComplete == (x)) || \ + (SdiocBufferReadReady == (x)) || \ + (SdiocBufferWriteReady == (x)) || \ + (SdiocTransferComplete == (x))) + +/*!< Parameter valid check for SDIOC error interrupt. */ +#define IS_VALID_SDIOC_ERR_INT(x) \ +( (SdiocCmdCrcErr == (x)) || \ + (SdiocDataCrcErr == (x)) || \ + (SdiocCmdIndexErr == (x)) || \ + (SdiocCmdEndBitErr == (x)) || \ + (SdiocAutoCmd12Err == (x)) || \ + (SdiocCmdTimeoutErr == (x)) || \ + (SdiocDataEndBitErr == (x)) || \ + (SdiocDataTimeoutErr == (x))) + +/*!< Parameter valid check for SDIOC auto CMD12 error status. */ +#define IS_VALID_SDIOC_AUTOCMD_ERR(x) \ +( (SdiocCmdNotIssuedErr == (x)) || \ + (SdiocAutoCmd12CrcErr == (x)) || \ + (SdiocAutoCmd12Timeout == (x)) || \ + (SdiocAutoCmd12IndexErr == (x)) || \ + (SdiocAutoCmd12EndBitErr == (x)) || \ + (SdiocAutoCmd12NotExecuted == (x))) + +/*!< Parameter valid check for SDIOC detect card signal. */ +#define IS_VALID_SDIOC_DETECT_SIG(x) \ +( (SdiocSdcdPinLevel == (x)) || \ + (SdiocCardDetectTestLevel == (x))) + +/*!< Parameter valid check for SDIOC data block count value. */ +#define IS_VALID_SDIOC_BLKCNT(x) ((x) != 0u) + +/*!< Parameter valid check for SDIOC data block size value. */ +#define IS_VALID_SDIOC_BLKSIZE(x) (!((x) & 0xF000ul)) + +/*!< Parameter valid check for SDIOC command value. */ +#define IS_VALID_SDIOC_CMD_VAL(x) (!(0xC0u & (x))) + +/*!< Parameter valid check for buffer address. */ +#define IS_VALID_TRANSFER_BUF_ALIGN(x) (!((SDIOC_BUF_ALIGN_SIZE-1ul) & ((uint32_t)(x)))) + +/*!< Parameter valid check for SDIOC command value. */ +#define IS_VALID_TRANSFER_BUF_LEN(x) (!((SDIOC_BUF_ALIGN_SIZE-1ul) & ((uint32_t)(x)))) + +/*!< SDIOC unit max count value. */ +#define SDIOC_UNIT_MAX_CNT (ARRAY_SZ(m_astcSdiocInstanceDataLut)) + +/*!< SDIOC default sdclk frequency. */ +#define SDIOC_SDCLK_400K (400000ul) + +/*!< Get the specified register address of the specified SDIOC unit */ +#define SDIOC_ARG01(__SDIOCx__) ((uint32_t)(&((__SDIOCx__)->ARG0))) +#define SDIOC_BUF01(__SDIOCx__) ((uint32_t)(&((__SDIOCx__)->BUF0))) +#define SDIOC_RESPx(__SDIOCx__, RESP_REG) ((uint32_t)(&((__SDIOCx__)->RESP0)) + (uint32_t)(RESP_REG)) + +/* SDIOC buffer align size */ +#define SDIOC_BUF_ALIGN_SIZE (4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static en_sdioc_clk_div_t SdiocGetClkDiv(uint32_t u32Exclk, + uint32_t u32SdiocClkFreq); +static stc_sdioc_intern_data_t* SdiocGetInternDataPtr(const M4_SDIOC_TypeDef *SDIOCx); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Get SDIOC clock division. + ** + ** \param [in] u32Exclk Exclk frequency + ** \param [in] u32ClkFreq SDIOC clock frequency + ** + ** \retval SdiocClkDiv_1 EXCLK/1 + ** \retval SdiocClkDiv_2 EXCLK/2 + ** \retval SdiocClkDiv_4 EXCLK/4 + ** \retval SdiocClkDiv_8 EXCLK/8 + ** \retval SdiocClkDiv_16 EXCLK/16 + ** \retval SdiocClkDiv_32 EXCLK/32 + ** \retval SdiocClkDiv_64 EXCLK/64 + ** \retval SdiocClkDiv_128 EXCLK/128 + ** \retval SdiocClkDiv_256 EXCLK/256 + ** + ******************************************************************************/ +static en_sdioc_clk_div_t SdiocGetClkDiv(uint32_t u32Exclk, + uint32_t u32ClkFreq) +{ + uint32_t u32SdClkDiv = 0ul; + en_sdioc_clk_div_t enClockDiv = SdiocClkDiv_256; + + if(0ul != u32ClkFreq) + { + u32SdClkDiv = u32Exclk / u32ClkFreq; + if (u32Exclk % u32ClkFreq) + { + u32SdClkDiv++; + } + + if ((128ul < u32SdClkDiv) && (u32SdClkDiv <= 256ul)) + { + enClockDiv = SdiocClkDiv_256; + } + else if ((64ul < u32SdClkDiv) && (u32SdClkDiv <= 128ul)) + { + enClockDiv = SdiocClkDiv_128; + } + else if ((32ul < u32SdClkDiv) && (u32SdClkDiv <= 64ul)) + { + enClockDiv = SdiocClkDiv_64; + } + else if ((16ul < u32SdClkDiv) && (u32SdClkDiv <= 32ul)) + { + enClockDiv = SdiocClkDiv_32; + } + else if ((16ul < u32SdClkDiv) && (u32SdClkDiv <= 32ul)) + { + enClockDiv = SdiocClkDiv_32; + } + else if ((8ul < u32SdClkDiv) && (u32SdClkDiv <= 16ul)) + { + enClockDiv = SdiocClkDiv_16; + } + else if ((4ul < u32SdClkDiv) && (u32SdClkDiv <= 8ul)) + { + enClockDiv = SdiocClkDiv_8; + } + else if ((2ul < u32SdClkDiv) && (u32SdClkDiv <= 4ul)) + { + enClockDiv = SdiocClkDiv_4; + } + else if ((1ul < u32SdClkDiv) && (u32SdClkDiv <= 2ul)) + { + enClockDiv = SdiocClkDiv_2; + } + else + { + enClockDiv = SdiocClkDiv_1; + } + } + + return enClockDiv; +} + +/** + ******************************************************************************* + ** \brief Return the internal data for a certain SDIOC instance. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_sdioc_intern_data_t* SdiocGetInternDataPtr(const M4_SDIOC_TypeDef *SDIOCx) +{ + uint8_t i; + stc_sdioc_intern_data_t *pstcInternData = NULL; + static stc_sdioc_instance_data_t m_astcSdiocInstanceDataLut[2]; + + m_astcSdiocInstanceDataLut[0].SDIOCx = M4_SDIOC1; + m_astcSdiocInstanceDataLut[1].SDIOCx = M4_SDIOC2; + + if (NULL != SDIOCx) + { + for (i = 0u; i < SDIOC_UNIT_MAX_CNT; i++) + { + if (SDIOCx == m_astcSdiocInstanceDataLut[i].SDIOCx) + { + pstcInternData = &m_astcSdiocInstanceDataLut[i].stcInternData; + break; + } + } + } + + return pstcInternData; +} + +/** + ******************************************************************************* + ** \brief SDIOC instance interrupt service routine + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval None + ** + ******************************************************************************/ +void SDIOC_IrqHandler(M4_SDIOC_TypeDef *SDIOCx) +{ + stc_sdioc_intern_data_t *pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + + /* Check for NULL pointer */ + if (NULL != pstcSdiocInternData) + { + /**************** Normal interrupt handler ****************/ + if (1u == SDIOCx->NORINTST_f.CC) /* Command complete */ + { + SDIOCx->NORINTST_f.CC = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.TC) /* Transfer complete */ + { + SDIOCx->NORINTST_f.TC = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BGE) /* Block gap event */ + { + SDIOCx->NORINTST_f.BGE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BWR) /* Buffer write ready */ + { + SDIOCx->NORINTST_f.BWR = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BRR) /* Buffer read ready */ + { + SDIOCx->NORINTST_f.BRR = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CIST) /* Card insertion */ + { + SDIOCx->NORINTST_f.CIST = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CRM) /* Card removal */ + { + SDIOCx->NORINTST_f.CRM = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CINT) /* Card interrupt */ + { + SDIOCx->NORINTST_f.CINT = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb(); + } + } + + /**************** Error interrupt handler ****************/ + if (1u == SDIOCx->ERRINTST_f.CTOE) /* Command timeout error */ + { + SDIOCx->ERRINTST_f.CTOE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CCE) /* Command CRC error */ + { + SDIOCx->ERRINTST_f.CCE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CEBE) /* Command end bit error */ + { + SDIOCx->ERRINTST_f.CEBE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CIE) /* Command index error */ + { + SDIOCx->ERRINTST_f.CIE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DTOE) /* Data timeout error */ + { + SDIOCx->ERRINTST_f.DTOE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DEBE) /* Data end bit error */ + { + SDIOCx->ERRINTST_f.DEBE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DCE) /* Data CRC error */ + { + SDIOCx->ERRINTST_f.DCE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.ACE) /* Auto CMD12 error */ + { + SDIOCx->ERRINTST_f.ACE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb(); + } + } + } +} + +/** + ******************************************************************************* + ** \brief Initializes a SDIOC. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcInitCfg Pointer to SDIOC configure structure + ** \arg This parameter detail refer @ref stc_sdioc_init_t + ** + ** \retval Ok SDIOC initialized normally + ** \retval ErrorTimeout SDIOCx reset timeout + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_init_t *pstcInitCfg) +{ + __IO uint32_t i = 0ul; + uint32_t u32Exclk = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_intern_data_t *pstcSdiocInternData = NULL; + + /* Get pointer to internal data structure. */ + pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + if (NULL != pstcSdiocInternData) /* Check for instance available or not */ + { + /* Reset all */ + SDIOCx->SFTRST_f.RSTA = 1u; + while (0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + + if (i < u32Cnt) + { + /* Get EXCLK frequency */ + u32Exclk = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.EXCKS); + + SDIOCx->CLKCON_f.FS = SdiocGetClkDiv(u32Exclk, SdiocClk400K); + SDIOCx->CLKCON_f.CE = (uint16_t)1u; + SDIOCx->CLKCON_f.ICE = (uint16_t)1u; + SDIOCx->PWRCON_f.PWON = (uint8_t)1u; /* Power on */ + + /* Enable all status */ + SDIOCx->ERRINTST = (uint16_t)0x017Fu; /* Clear Error interrupt status */ + SDIOCx->ERRINTSTEN = (uint16_t)0x017Fu; /* Enable Error interrupt status */ + SDIOCx->NORINTST = (uint16_t)0x00F7u; /* Clear Normal interrupt status */ + SDIOCx->NORINTSTEN = (uint16_t)0x01F7u; /* Enable Normal interrupt status */ + + /* Enable normal interrupt signal */ + if (NULL != pstcInitCfg) + { + if (NULL != pstcInitCfg->pstcNormalIrqEn) + { + SDIOCx->NORINTSGEN = pstcInitCfg->pstcNormalIrqEn->u16NormalIntsgEn; + } + + /* Set normal interrupt callback functions */ + if (NULL != pstcInitCfg->pstcNormalIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCommandCompleteIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnTransferCompleteIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBlockGapIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBufferWriteReadyIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBufferReadReadyIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardInsertIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardRemovalIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardIrqCb; + } + + /* Enable error interrupt signal */ + if (NULL != pstcInitCfg->pstcErrorIrqEn) + { + SDIOCx->ERRINTSGEN = pstcInitCfg->pstcErrorIrqEn->u16ErrorIntsgEn; + } + + /* Set error interrupt callback functions */ + if (NULL != pstcInitCfg->pstcErrorIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdTimeoutErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdCrcErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdEndBitErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdIndexErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataTimeoutErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataEndBitErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataCrcErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnAutoCmdErrIrqCb; + } + } + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes the specified SDIOC unit. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorTimeout SDIOCx reset timeout. + ** \retval ErrorInvalidParameter SDIOCx is invalid. + ** + ******************************************************************************/ +en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx) +{ + __IO uint32_t i = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_intern_data_t *pstcSdiocInternData = NULL; + + /* Get pointer to internal data structure. */ + pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + if (NULL != pstcSdiocInternData) /* Check for instance available or not */ + { + /* Reset all */ + SDIOCx->SFTRST_f.RSTA = 1u; + while (0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + + if (i < u32Cnt) + { + /* Set normal interrupt callback functions */ + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb = NULL; + + /* Set error interrupt callback functions */ + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb = NULL; + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + * @brief Set SDIOC mode. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] enMode SDIOCx mode + * @arg SdiocModeSD: SD mode + * @arg SdiocModeMMC: MMC mode + */ +void SDIOC_SetMode(const M4_SDIOC_TypeDef *SDIOCx, en_sdioc_mode_t enMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_MODE(enMode)); + + if (M4_SDIOC1 == SDIOCx) + { + M4_PERIC->SDIOC_SYCTLREG_f.SELMMC1 = (uint32_t)enMode; + } + else + { + M4_PERIC->SDIOC_SYCTLREG_f.SELMMC2 = (uint32_t)enMode; + } +} + +/** + ******************************************************************************* + ** \brief Send SD command + ** + ** This function sends command on CMD line + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcCmdCfg Pointer to command transfer configuration structure. + ** \arg This parameter detail refer @ref stc_sdioc_cmd_cfg_t + ** + ** \retval Ok Command sent normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcCmdCfg == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_cmd_cfg_t *pstcCmdCfg) +{ + uint32_t u32Addr; + stc_sdioc_cmd_field_t stcCmdField; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for NULL pointer */ + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pstcCmdCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_CMD_VAL(pstcCmdCfg->u8CmdIndex)); + DDL_ASSERT(IS_VALID_SDIOC_CMD_TYPE(pstcCmdCfg->enCmdType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCmdCfg->enDataPresentEnable)); + DDL_ASSERT(IS_VALID_SDIOC_RESP_TYPE_NAME(pstcCmdCfg->enRspIndex)); + + enRet = Ok; + switch (pstcCmdCfg->enRspIndex) + { + case SdiocCmdNoRsp: + stcCmdField.RESTYP = SdiocResponseNoneBit; + stcCmdField.CCE = 0u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR2: + stcCmdField.RESTYP = SdiocResponse136Bit; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR3: + case SdiocCmdRspR4: + stcCmdField.RESTYP = SdiocResponse48Bit; + stcCmdField.CCE = 0u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR1: + case SdiocCmdRspR5: + case SdiocCmdRspR6: + case SdiocCmdRspR7: + stcCmdField.RESTYP = SdiocResponse48Bit; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 1u; + break; + case SdiocCmdRspR1b: + case SdiocCmdRspR5b: + stcCmdField.RESTYP = SdiocResponse48BitCheckBusy; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + stcCmdField.RESERVED2 = (uint16_t)0u; + stcCmdField.TYP = (uint16_t)pstcCmdCfg->enCmdType; + stcCmdField.IDX = (uint16_t)pstcCmdCfg->u8CmdIndex; + stcCmdField.DAT = (uint16_t)(pstcCmdCfg->enDataPresentEnable); + + u32Addr = SDIOC_ARG01(SDIOCx); + *(__IO uint32_t *)u32Addr = pstcCmdCfg->u32Argument; + + u32Addr = (uint32_t)&stcCmdField; + SDIOCx->CMD = *(uint16_t *)u32Addr; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the response received from the card for the last command + ** + ** This function sends command on CMD line + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enRespReg Response Specifies the SDIOC response register. + ** \arg SdiocRegResp01 Response0 and Response1 Register + ** \arg SdiocRegResp23 Response2 and Response3 Register + ** \arg SdiocRegResp45 Response4 and Response5 Register + ** \arg SdiocRegResp67 Response6 and Response7 Register + ** + ** \retval The Corresponding response register value + ** + ******************************************************************************/ +uint32_t SDIOC_GetResponse(const M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_response_reg_t enRespReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_RESP(enRespReg)); + + return *(__IO uint32_t *)SDIOC_RESPx(SDIOCx, enRespReg) ; +} + +/** + ******************************************************************************* + ** \brief Read data from SDIOCx data buffer + ** + ** This function reads 32-bit data from data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] au8Data Buffer which will store SDIOC_BUFFER data + ** \param [in] u32Len Data length + ** + ** \retval Ok Data is read normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pu32Data == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len) +{ + uint32_t i = 0ul; + uint32_t u32Temp = 0ul;; + __IO uint32_t *SDIO_BUF_REG = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pu8Data pointer */ + if ((NULL != au8Data) && \ + (IS_VALID_SDIOC(SDIOCx)) && \ + (IS_VALID_TRANSFER_BUF_LEN(u32Len))) + { + SDIO_BUF_REG = (__IO uint32_t *)SDIOC_BUF01(SDIOCx); + + while (i < u32Len) + { + u32Temp = *SDIO_BUF_REG; + au8Data[i++] = (uint8_t)((u32Temp >> 0ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 8ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 16ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 24ul) & 0x000000FF); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write data to SDIOCx data buffer + ** + ** This function writes 32-bit data to data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] au8Data Buffer which will be wrote to SDIOC_BUFFER + ** \param [in] u32Len Data length + ** + ** \retval Ok Data is written normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pu8Data == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len) +{ + uint32_t i = 0ul; + uint32_t u32Temp = 0ul; + __IO uint32_t *SDIO_BUF_REG = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pu8Data pointer */ + if ((NULL != au8Data) && \ + (IS_VALID_SDIOC(SDIOCx)) && \ + (IS_VALID_TRANSFER_BUF_LEN(u32Len))) + { + SDIO_BUF_REG = (__IO uint32_t *)SDIOC_BUF01(SDIOCx); + + while (i < u32Len) + { + u32Temp = (((uint32_t)au8Data[i++]) << 0ul) & 0x000000FFul; + u32Temp += (((uint32_t)au8Data[i++]) << 8ul) & 0x0000FF00ul; + u32Temp += (((uint32_t)au8Data[i++]) << 16ul) & 0x00FF0000ul; + u32Temp += (((uint32_t)au8Data[i++]) << 24ul) & 0xFF000000ul; + + *SDIO_BUF_REG = u32Temp; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure SDIOCx data parameters + ** + ** This function writes 32-bit data to data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcDataCfg Pointer to SDIOC data transfer configuration structure + ** \arg This parameter detail refer @ref stc_sdioc_data_cfg_t + ** + ** \retval Ok configure normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcDataCfg == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_data_cfg_t *pstcDataCfg) +{ + uint16_t u16BlkCnt = (uint16_t)0; + uint32_t u32Addr; + stc_sdioc_transmode_field_t stcTransModeField = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pstcDataCfg pointer */ + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pstcDataCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_BLKCNT(pstcDataCfg->u16BlkCnt)); + DDL_ASSERT(IS_VALID_SDIOC_BLKSIZE(pstcDataCfg->u16BlkSize)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcDataCfg->enAutoCmd12Enable)); + DDL_ASSERT(IS_VALID_SDIOC_DATA_TIMEOUT(pstcDataCfg->enDataTimeOut)); + DDL_ASSERT(IS_VALID_SDIOC_TRANSFER_DIR(pstcDataCfg->enTransferDir)); + DDL_ASSERT(IS_VALID_SDIOC_TRANSFER_MODE(pstcDataCfg->enTransferMode)); + + enRet = Ok; + + switch (pstcDataCfg->enTransferMode) + { + case SdiocTransferSingle: + stcTransModeField.MULB = 0u; + stcTransModeField.BCE = 0u; + break; + case SdiocTransferInfinite: + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 0u; + break; + case SdiocTransferMultiple: + u16BlkCnt = pstcDataCfg->u16BlkCnt; + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 1u; + break; + case SdiocTransferStopMultiple: + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + stcTransModeField.RESERVED0 = (uint16_t)0u; + stcTransModeField.DDIR = (uint16_t)(pstcDataCfg->enTransferDir); + stcTransModeField.ATCEN = (uint16_t)(pstcDataCfg->enAutoCmd12Enable); + + /* Set the SDIOC Data Transfer Timeout value */ + SDIOCx->TOUTCON = (uint8_t)(pstcDataCfg->enDataTimeOut); + /* Set the SDIOC Block Count value */ + SDIOCx->BLKCNT = u16BlkCnt; + /* Set the SDIOC Block Size value */ + SDIOCx->BLKSIZE = pstcDataCfg->u16BlkSize; + /* Set the SDIOC Data Transfer Mode */ + u32Addr = (uint32_t)&stcTransModeField; + SDIOCx->TRANSMODE = *(uint16_t *)u32Addr; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable SDCLK output + ** + ** SD host drives SDCLK line. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd The SDCLK functional state command + ** \arg Enable Enable SDCLK function + ** \arg Disable Disable SDCLK function + ** + ** \retval Ok SDCLK output of SDIOCx enabled normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SdclkCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + SDIOCx->CLKCON_f.CE = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the clock division of SD clock + ** + ** This function changes the SD clock division. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enClkDiv SDIOC clock division value + ** \arg SdiocClkDiv_1 EXCLK/1 + ** \arg SdiocClkDiv_2 EXCLK/2 + ** \arg SdiocClkDiv_4 EXCLK/4 + ** \arg SdiocClkDiv_8 EXCLK/8 + ** \arg SdiocClkDiv_16 EXCLK/16 + ** \arg SdiocClkDiv_32 EXCLK/32 + ** \arg SdiocClkDiv_64 EXCLK/64 + ** \arg SdiocClkDiv_128 EXCLK/128 + ** \arg SdiocClkDiv_256 EXCLK/256 + ** + ** \retval Ok SDIOC clock division is changed normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetClkDiv(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_CLK_DIV(enClkDiv)); + + /* Set clock division */ + SDIOCx->CLKCON_f.FS = (uint16_t)enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the clock division of SD clock + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocClkDiv_1 EXCLK/1 + ** \retval SdiocClkDiv_2 EXCLK/2 + ** \retval SdiocClkDiv_4 EXCLK/4 + ** \retval SdiocClkDiv_8 EXCLK/8 + ** \retval SdiocClkDiv_16 EXCLK/16 + ** \retval SdiocClkDiv_32 EXCLK/32 + ** \retval SdiocClkDiv_64 EXCLK/64 + ** \retval SdiocClkDiv_128 EXCLK/128 + ** + ******************************************************************************/ +en_sdioc_clk_div_t SDIOC_GetClkDiv(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return ((en_sdioc_clk_div_t)SDIOCx->CLKCON_f.FS); +} + +/** + ******************************************************************************* + ** \brief Get the clock division of SD clock + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32ClkFreq SDIOC clock frequency + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetClk(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ClkFreq) +{ + uint32_t u32Exclk = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Get EXCLK frequency */ + u32Exclk = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.EXCKS); + + SDIOCx->CLKCON_f.CE = (uint16_t)0u; + SDIOCx->CLKCON_f.FS = (uint16_t)SdiocGetClkDiv(u32Exclk, u32ClkFreq); + SDIOCx->CLKCON_f.CE = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the bus width of SD Bus + ** + ** This function changes the SD bus width. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enBusWidth Bus width + ** \arg SdiocBusWidth1Bit The SDIOC bus width 1 bit + ** \arg SdiocBusWidth4Bit The SDIOC bus width 4 bit + ** \arg SdiocBusWidth8Bit The SDIOC bus width 8 bit + ** + ** \retval Ok Bus width is set normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - SDIOCx is invalid + ** - enBusWidth is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_bus_width_t enBusWidth) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_BUS_WIDTH(enBusWidth)); + + enRet = Ok; + + switch (enBusWidth) + { + case SdiocBusWidth1Bit: + SDIOCx->HOSTCON_f.EXDW = 0u; + SDIOCx->HOSTCON_f.DW = 0u; + break; + case SdiocBusWidth4Bit: + SDIOCx->HOSTCON_f.EXDW = 0u; + SDIOCx->HOSTCON_f.DW = 1u; + break; + case SdiocBusWidth8Bit: + SDIOCx->HOSTCON_f.EXDW = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the bus width of SD Bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocBusWidth1Bit The SDIOC bus width 1 bit + ** \retval SdiocBusWidth4Bit The SDIOC bus width 4 bit + ** \retval SdiocBusWidth8Bit The SDIOC bus width 8 bit + ** + ******************************************************************************/ +en_sdioc_bus_width_t SDIOC_GetBusWidth(M4_SDIOC_TypeDef *SDIOCx) +{ + en_sdioc_bus_width_t enBusWidth = SdiocBusWidth4Bit; + + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + if (0u == SDIOCx->HOSTCON_f.EXDW) + { + if (0u == SDIOCx->HOSTCON_f.DW) + { + enBusWidth = SdiocBusWidth1Bit; + } + } + else + { + enBusWidth = SdiocBusWidth8Bit; + } + + return enBusWidth; +} + +/** + ******************************************************************************* + ** \brief Set the bus speed mode of SD Bus + ** + ** This function changes the SD bus speed mode. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enSpeedMode Speed mode + ** \arg SdiocHighSpeedMode High speed mode + ** \arg SdiocNormalSpeedMode Normal speed mode + ** + ** \retval Ok Bus speed is set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_speed_mode_t enSpeedMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_SPEED_MODE(enSpeedMode)); + + /* Set high speed mode */ + SDIOCx->HOSTCON_f.HSEN = ((SdiocHighSpeedMode == enSpeedMode) ? 1u : 0u); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the bus speed mode of SD Bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocHighSpeedMode High speed mode + ** \retval SdiocNormalSpeedMode Normal speed mode + ** + ******************************************************************************/ +en_sdioc_speed_mode_t SDIOC_GetSpeedMode(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return ((SDIOCx->HOSTCON_f.HSEN) ? SdiocHighSpeedMode : SdiocNormalSpeedMode); +} + +/** + ******************************************************************************* + ** \brief Set data timeout counter value + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enTimeout Data timeout count value + ** \arg SdiocDtoSdclk_2_13 Timeout time: SDCLK*2^13 + ** \arg SdiocDtoSdclk_2_14 Timeout time: SDCLK*2^14 + ** \arg SdiocDtoSdclk_2_15 Timeout time: SDCLK*2^15 + ** \arg SdiocDtoSdclk_2_16 Timeout time: SDCLK*2^16 + ** \arg SdiocDtoSdclk_2_17 Timeout time: SDCLK*2^17 + ** \arg SdiocDtoSdclk_2_18 Timeout time: SDCLK*2^18 + ** \arg SdiocDtoSdclk_2_19 Timeout time: SDCLK*2^19 + ** \arg SdiocDtoSdclk_2_20 Timeout time: SDCLK*2^20 + ** \arg SdiocDtoSdclk_2_21 Timeout time: SDCLK*2^21 + ** \arg SdiocDtoSdclk_2_22 Timeout time: SDCLK*2^22 + ** \arg SdiocDtoSdclk_2_23 Timeout time: SDCLK*2^23 + ** \arg SdiocDtoSdclk_2_24 Timeout time: SDCLK*2^24 + ** \arg SdiocDtoSdclk_2_25 Timeout time: SDCLK*2^25 + ** \arg SdiocDtoSdclk_2_26 Timeout time: SDCLK*2^26 + ** \arg SdiocDtoSdclk_2_27 Timeout time: SDCLK*2^27 + ** + ** \retval Ok Bus speed is set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetDataTimeout(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_data_timeout_t enTimeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_DATA_TIMEOUT(enTimeout)); + + /* Set data timeout */ + SDIOCx->TOUTCON_f.DTO = (uint8_t)enTimeout; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get data timeout counter value + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocDtoSdclk_2_13 Timeout time: SDCLK*2^13 + ** \retval SdiocDtoSdclk_2_14 Timeout time: SDCLK*2^14 + ** \retval SdiocDtoSdclk_2_15 Timeout time: SDCLK*2^15 + ** \retval SdiocDtoSdclk_2_16 Timeout time: SDCLK*2^16 + ** \retval SdiocDtoSdclk_2_17 Timeout time: SDCLK*2^17 + ** \retval SdiocDtoSdclk_2_18 Timeout time: SDCLK*2^18 + ** \retval SdiocDtoSdclk_2_19 Timeout time: SDCLK*2^19 + ** \retval SdiocDtoSdclk_2_20 Timeout time: SDCLK*2^20 + ** \retval SdiocDtoSdclk_2_21 Timeout time: SDCLK*2^21 + ** \retval SdiocDtoSdclk_2_22 Timeout time: SDCLK*2^22 + ** \retval SdiocDtoSdclk_2_23 Timeout time: SDCLK*2^23 + ** \retval SdiocDtoSdclk_2_24 Timeout time: SDCLK*2^24 + ** \retval SdiocDtoSdclk_2_25 Timeout time: SDCLK*2^25 + ** \retval SdiocDtoSdclk_2_26 Timeout time: SDCLK*2^26 + ** \retval SdiocDtoSdclk_2_27 Timeout time: SDCLK*2^27 + ** + ******************************************************************************/ +en_sdioc_data_timeout_t SDIOC_GetDataTimeout(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return (en_sdioc_data_timeout_t)(SDIOCx->TOUTCON_f.DTO); +} + +/** + ******************************************************************************* + ** \brief Set the card detect signal + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enDetectSignal Card detect signal + ** \arg SdiocSdcdPinLevel SDCD# is selected (for normal use) + ** \arg SdiocCardDetectTestLevel The Card Detect Test Level is selected(for test purpose) + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetCardDetectSignal(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_detect_signal_t enDetectSignal) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_DETECT_SIG(enDetectSignal)); + SDIOCx->HOSTCON_f.CDSS = (uint8_t)enDetectSignal; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get card inserted or not. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Set Card Inserted + ** \retval Reset No Card + ** + ** \note This bit is enabled while the Card Detect Signal Selection is set to 1 + ** and it indicates card inserted or not. + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return (en_flag_status_t)(SDIOCx->HOSTCON_f.CDTL); +} + +/** + ******************************************************************************* + ** \brief Power on SD bus power + ** + ** This function starts power supply on SD bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Power on normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_BusPowerOn(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->PWRCON_f.PWON = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Power off SD bus power + ** + ** This function stops power supply on SD bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Power off normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_BusPowerOff(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->PWRCON_f.PWON = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Stop At Block Gap Request during block gap + ** + ** This function is used to stop data trasnfer of multi-block transfer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Stop At Block Gap Request functional state + ** \arg Enable Enable the function of Stop At Block Gap Request + ** \arg Disable Disable the function of Stop At Block Gap Request + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_StopAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.SABGR = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Restart data transfer + ** + ** This function is used to restart data transfer when transfer is pending + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->BLKGPCON_f.CR = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Read Wait Control + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Read Wait Control functional state + ** \arg Enable Enable the Read Wait Control function + ** \arg Disable Disable the Read Wait Control function + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.RWC = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Interrupt At Block Gap + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Interrupt At Block Gap functional state + ** \arg Enable Enable the function of Interrupt At Block Gap + ** \arg Disable Disable the function of Interrupt At Block Gap + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_InterruptAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.IABG = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Generate software reset to SD card + ** + ** This function generates software reset all command to SD card + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enSwResetType Software reset type + ** \arg SdiocSwResetAll This reset affects the entire Host Controller except for the card detection circuit. + ** \arg SdiocSwResetCmdLine Only part of command circuit is reset. + ** \arg SdiocSwResetDataLine Only part of data circuit is reset. + ** + ** \retval Ok Software reset is done normally + ** \retval ErrorTimeout SDIOCx reset timeout + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - SDIOCx is invalid + ** - enSwResetType is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_sw_reset_t enSwResetType) +{ + __IO uint32_t i = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_SWRESETTYPE(enSwResetType)); + + enRet = Ok; + switch (enSwResetType) + { + case SdiocSwResetAll: + SDIOCx->SFTRST_f.RSTA = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + case SdiocSwResetCmdLine: + SDIOCx->SFTRST_f.RSTC = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTC) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + case SdiocSwResetDatLine: + SDIOCx->SFTRST_f.RSTD = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTD) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (i > u32Cnt) + { + enRet = ErrorTimeout; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the status of SDIOC host controller + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enHostStatus SDIOC host status + ** \arg SdiocCommandInhibitCmd Command Inhibit(CMD). 1: Cannot issue command; 0:Can issue command using only CMD line + ** \arg SdiocCommandInhibitData Command Inhibit(DAT). 1: Cannot issue command which uses the DAT line; 0:Can issue command which uses the DAT line + ** \arg SdiocDataLineActive 1: DAT Line Active; 0: DAT Line Inactive + ** \arg SdiocWriteTransferActive Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocReadTransferActive Read Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocBufferWriteEnble 1: Write enable; 0: Write Disable + ** \arg SdiocBufferReadEnble 1: Read enable; 0: Read Disable + ** \arg SdiocCardInserted 1: Card Inserted; 0: Reset or Debouncing or No Card + ** \arg SdiocCardStateStable 1: No Card or Inserted; 0: Reset or Debouncing + ** \arg SdiocCardDetectPinLvl 1: Card present; 0: No card present + ** \arg SdiocWriteProtectPinLvl 1: Write enabled; 0: Write protected + ** \arg SdiocData0PinLvl 1: DAT0 line signal level high; 0: DAT0 line signal level low + ** \arg SdiocData1PinLvl 1: DAT1 line signal level high; 0: DAT1 line signal level low + ** \arg SdiocData2PinLvl 1: DAT2 line signal level high; 0: DAT2 line signal level low + ** \arg SdiocData3PinLvl 1: DAT3 line signal level high; 0: DAT3 line signal level low + ** \arg SdiocCmdPinLvl 1: CMD line signal level high; 0: CMD line signal level low + ** + ** \retval Set The specified status is set + ** \retval Reset The specified status is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_host_status_t enHostStatus) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_HOST_STATUS(enHostStatus)); + + return ((SDIOCx->PSTAT & ((uint32_t)enHostStatus)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the specified signal of SDIOC normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** \param [in] enCmd SDIOC normal interrupt signal functional state + ** \arg Enable Enable the specified signal of SD normal interrupt + ** \arg Disable Disable the specified signal of SD normal interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_NormalIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + if (Enable == enCmd) + { + SDIOCx->NORINTSGEN |= (uint16_t)enNorInt; + } + else + { + SDIOCx->NORINTSGEN &= (uint16_t)(~((uint16_t)enNorInt)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the status of SDIOC normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** \param [in] enCmd SDIOC normal interrupt status functional state + ** \arg Enable Enable the specified status of SD normal interrupt + ** \arg Disable Disable the specified status of SD normal interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_NormalIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + if (Enable == enCmd) + { + SDIOCx->NORINTSTEN |= (uint16_t)enNorInt; + } + else + { + SDIOCx->NORINTSTEN &= (uint16_t)(~((uint16_t)enNorInt)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the flag of SD normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** + ** \retval Set The specified interupt flag is set + ** \retval Reset The specified interupt flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + return ((SDIOCx->NORINTST & ((uint16_t)enNorInt)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the flag of SD normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ClearNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + SDIOCx->NORINTST = (uint16_t)enNorInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the signal of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** \param [in] enCmd SDIOC error interrupt signal functional state + ** \arg Enable Enable the specified signal of SD error interrupt + ** \arg Disable Disable the specified signal of SD error interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ErrIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + if (Enable == enCmd) + { + SDIOCx->ERRINTSGEN |= (uint16_t)enErrInt; + } + else + { + SDIOCx->ERRINTSGEN &= (uint16_t)enErrInt; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the status of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** \param [in] enCmd SDIOC error interrupt status functional state + ** \arg Enable Enable the specified status of SD error interrupt + ** \arg Disable Disable the specified status of SD error interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ErrIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + if (Enable == enCmd) + { + SDIOCx->ERRINTSTEN |= (uint16_t)enErrInt; + } + else + { + SDIOCx->ERRINTSTEN &= (uint16_t)enErrInt; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the flag of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Set The specified interupt flag is set + ** \retval Reset The specified interupt flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + + return ((SDIOCx->ERRINTST & ((uint16_t)enErrInt)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the flag of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ClearErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + SDIOCx->ERRINTST = (uint16_t)enErrInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Force the specified error interrupt flag + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ForceErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + SDIOCx->FEE |= (uint16_t)enErrInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the status of auto CMD12 error + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enAutoCmdErr SDIOC auto cmd error status selection + ** \arg SdiocAutoCmd12NotExecuted Auto CMD12 Not Executed. 1: Not executed; 0:Executed + ** \arg SdiocAutoCmd12Timeout Auto CMD12 Timeout Error. 1: Time out; 0:No error + ** \arg SdiocAutoCmd12CrcErr Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + ** \arg SdiocAutoCmd12EndBitErr Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + ** \arg SdiocAutoCmd12IndexErr Auto CMD12 Index Error. 1: Error; 0: No error + ** \arg SdiocCmdNotIssuedErr Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error + ** + ** \retval Set The specified status flag is set + ** \retval Reset The specified status flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetAutoCmdErrStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_status_t enAutoCmdErr) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_AUTOCMD_ERR(enAutoCmdErr)); + + return ((SDIOCx->ATCERRST & ((uint16_t)enAutoCmdErr)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Force the specified auto CMD12 error + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enAutoCmdErr SDIOC auto cmd error selection + ** \arg SdiocAutoCmd12NotExecuted Auto CMD12 Not Executed. 1: Not executed; 0:Executed + ** \arg SdiocAutoCmd12Timeout Auto CMD12 Timeout Error. 1: Time out; 0:No error + ** \arg SdiocAutoCmd12CrcErr Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + ** \arg SdiocAutoCmd12EndBitErr Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + ** \arg SdiocAutoCmd12IndexErr Auto CMD12 Index Error. 1: Error; 0: No error + ** \arg SdiocCmdNotIssuedErr Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ForceAutoCmdErr(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_sel_t enAutoCmdErr) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_AUTOCMD_ERR(enAutoCmdErr)); + SDIOCx->FEA |= (uint16_t)enAutoCmdErr; + enRet = Ok; + } + + return enRet; +} + +//@} // SdiocGroup + +#endif /* DDL_SDIOC_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_spi.c b/driver/src/hc32f460_spi.c new file mode 100644 index 0000000..8d24845 --- /dev/null +++ b/driver/src/hc32f460_spi.c @@ -0,0 +1,1132 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_spi.c + ** + ** A detailed description is available at + ** @link SpiGroup Serial Peripheral Interface description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of Spi. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_spi.h" +#include "hc32f460_utility.h" + +#if (DDL_SPI_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SpiGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for SPI unit */ +#define IS_VALID_SPI_UNIT(x) \ +( (M4_SPI1 == (x)) || \ + (M4_SPI2 == (x)) || \ + (M4_SPI3 == (x)) || \ + (M4_SPI4 == (x))) + +/*!< Parameter valid check for SS setup delay option */ +#define IS_VALID_SS_SETUP_DELAY_OPTION(x) \ +( (SpiSsSetupDelayTypicalSck1 == (x)) || \ + (SpiSsSetupDelayCustomValue == (x))) + +/*!< Parameter valid check for SS setup delay time */ +#define IS_VALID_SS_SETUP_DELAY_TIME(x) \ +( (SpiSsSetupDelaySck1 == (x)) || \ + (SpiSsSetupDelaySck2 == (x)) || \ + (SpiSsSetupDelaySck3 == (x)) || \ + (SpiSsSetupDelaySck4 == (x)) || \ + (SpiSsSetupDelaySck5 == (x)) || \ + (SpiSsSetupDelaySck6 == (x)) || \ + (SpiSsSetupDelaySck7 == (x)) || \ + (SpiSsSetupDelaySck8 == (x))) + +/*!< Parameter valid check for SS hold delay time */ +#define IS_VALID_SS_HOLD_DELAY_TIME(x) \ +( (SpiSsHoldDelaySck1 == (x)) || \ + (SpiSsHoldDelaySck2 == (x)) || \ + (SpiSsHoldDelaySck3 == (x)) || \ + (SpiSsHoldDelaySck4 == (x)) || \ + (SpiSsHoldDelaySck5 == (x)) || \ + (SpiSsHoldDelaySck6 == (x)) || \ + (SpiSsHoldDelaySck7 == (x)) || \ + (SpiSsHoldDelaySck8 == (x))) + +/*!< Parameter valid check for SS hold delay option */ +#define IS_VALID_SS_HOLD_DELAY_OPTION(x) \ +( (SpiSsHoldDelayTypicalSck1 == (x)) || \ + (SpiSsHoldDelayCustomValue == (x))) + +/*!< Parameter valid check for SS interval time option */ +#define IS_VALID_SS_INTERVAL_TIME_OPTION(x) \ +( (SpiSsIntervalTypicalSck1PlusPck2 == (x)) || \ + (SpiSsIntervalCustomValue == (x))) + +/*!< Parameter valid check for SS interval time */ +#define IS_VALID_SS_INTERVAL_TIME(x) \ +( (SpiSsIntervalSck1PlusPck2 == (x)) || \ + (SpiSsIntervalSck2PlusPck2 == (x)) || \ + (SpiSsIntervalSck3PlusPck2 == (x)) || \ + (SpiSsIntervalSck4PlusPck2 == (x)) || \ + (SpiSsIntervalSck5PlusPck2 == (x)) || \ + (SpiSsIntervalSck6PlusPck2 == (x)) || \ + (SpiSsIntervalSck7PlusPck2 == (x)) || \ + (SpiSsIntervalSck8PlusPck2 == (x))) + +/*!< Parameter valid check for SS valid channel select */ +#define IS_VALID_SS_VALID_CHANNEL(x) \ +( (SpiSsValidChannel0 == (x)) || \ + (SpiSsValidChannel1 == (x)) || \ + (SpiSsValidChannel2 == (x)) || \ + (SpiSsValidChannel3 == (x))) + +/*!< Parameter valid check for SS polarity */ +#define IS_VALID_SS_POLARITY(x) \ +( (SpiSsLowValid == (x)) || \ + (SpiSsHighValid == (x))) + +/*!< Parameter valid check for read data register object */ +#define IS_VALID_READ_DATA_REG_OBJECT(x) \ +( (SpiReadReceiverBuffer == (x)) || \ + (SpiReadSendBuffer == (x))) + +/*!< Parameter valid check for SCK polarity */ +#define IS_VALID_SCK_POLARITY(x) \ +( (SpiSckIdleLevelLow == (x)) || \ + (SpiSckIdleLevelHigh == (x))) + +/*!< Parameter valid check for SCK phase */ +#define IS_VALID_SCK_PHASE(x) \ +( (SpiSckOddSampleEvenChange == (x)) || \ + (SpiSckOddChangeEvenSample == (x))) + +/*!< Parameter valid check for clock division */ +#define IS_VALID_CLK_DIV(x) \ +( (SpiClkDiv2 == (x)) || \ + (SpiClkDiv4 == (x)) || \ + (SpiClkDiv8 == (x)) || \ + (SpiClkDiv16 == (x)) || \ + (SpiClkDiv32 == (x)) || \ + (SpiClkDiv64 == (x)) || \ + (SpiClkDiv128 == (x)) || \ + (SpiClkDiv256 == (x))) + +/*!< Parameter valid check for data length */ +#define IS_VALID_DATA_LENGTH(x) \ +( (SpiDataLengthBit4 == (x)) || \ + (SpiDataLengthBit5 == (x)) || \ + (SpiDataLengthBit6 == (x)) || \ + (SpiDataLengthBit7 == (x)) || \ + (SpiDataLengthBit8 == (x)) || \ + (SpiDataLengthBit9 == (x)) || \ + (SpiDataLengthBit10 == (x)) || \ + (SpiDataLengthBit11 == (x)) || \ + (SpiDataLengthBit12 == (x)) || \ + (SpiDataLengthBit13 == (x)) || \ + (SpiDataLengthBit14 == (x)) || \ + (SpiDataLengthBit15 == (x)) || \ + (SpiDataLengthBit16 == (x)) || \ + (SpiDataLengthBit20 == (x)) || \ + (SpiDataLengthBit24 == (x)) || \ + (SpiDataLengthBit32 == (x))) + +/*!< Parameter valid check for first bit position */ +#define IS_VALID_FIRST_BIT_POSITION(x) \ +( (SpiFirstBitPositionMSB == (x)) || \ + (SpiFirstBitPositionLSB == (x))) + +/*!< Parameter valid check for frame number */ +#define IS_VALID_FRAME_NUMBER(x) \ +( (SpiFrameNumber1 == (x)) || \ + (SpiFrameNumber2 == (x)) || \ + (SpiFrameNumber3 == (x)) || \ + (SpiFrameNumber4 == (x))) + +/*!< Parameter valid check for work mode */ +#define IS_VALID_WORK_MODE(x) \ +( (SpiWorkMode4Line == (x)) || \ + (SpiWorkMode3Line == (x))) + +/*!< Parameter valid check for transmission mode */ +#define IS_VALID_COMM_MODE(x) \ +( (SpiTransFullDuplex == (x)) || \ + (SpiTransOnlySend == (x))) + +/*!< Parameter valid check for master slave mode */ +#define IS_VALID_MASTER_SLAVE_MODE(x) \ +( (SpiModeSlave == (x)) || \ + (SpiModeMaster == (x))) + +/*!< Parameter valid check for parity mode */ +#define IS_VALID_PARITY_MODE(x) \ +( (SpiParityEven == (x)) || \ + (SpiParityOdd == (x))) + +/*!< Parameter valid check for SS channel */ +#define IS_VALID_SS_CHANNEL(x) \ +( (SpiSsChannel0 == (x)) || \ + (SpiSsChannel1 == (x)) || \ + (SpiSsChannel2 == (x)) || \ + (SpiSsChannel3 == (x))) + +/*!< Parameter valid check for irq type */ +#define IS_VALID_IRQ_TYPE(x) \ +( (SpiIrqIdle == (x)) || \ + (SpiIrqReceive == (x)) || \ + (SpiIrqSend == (x)) || \ + (SpiIrqError == (x))) + +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (SpiFlagReceiveBufferFull == (x)) || \ + (SpiFlagSendBufferEmpty == (x)) || \ + (SpiFlagUnderloadError == (x)) || \ + (SpiFlagParityError == (x)) || \ + (SpiFlagModeFaultError == (x)) || \ + (SpiFlagSpiIdle == (x)) || \ + (SpiFlagOverloadError == (x))) + +/*!< SPI registers reset value */ +#define SPI_REG_DR_RESET_VALUE 0x00000000ul +#define SPI_REG_CR1_RESET_VALUE 0x00000000ul +#define SPI_REG_CFG1_RESET_VALUE 0x00000010ul +#define SPI_REG_SR_RESET_VALUE 0x00000020ul +#define SPI_REG_CFG2_RESET_VALUE 0x0000031Dul + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize SPI unit + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_DeInit(M4_SPI_TypeDef *SPIx) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t regTemp = 0ul; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + regTemp = SPIx->SR; + if (SPI_REG_SR_RESET_VALUE != regTemp) + { + SPIx->SR = SPI_REG_SR_RESET_VALUE; + } + SPIx->CR1 = SPI_REG_CR1_RESET_VALUE; + SPIx->DR = SPI_REG_DR_RESET_VALUE; + SPIx->CFG1 = SPI_REG_CFG1_RESET_VALUE; + SPIx->CFG2 = SPI_REG_CFG2_RESET_VALUE; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize SPI unit + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] pstcSpiInitCfg Pointer to SPI init configuration + ** \arg See the struct #stc_spi_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** - pstcSpiInitCfg == NULL + ** + ******************************************************************************/ +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if((IS_VALID_SPI_UNIT(SPIx)) && (NULL != pstcSpiInitCfg)) + { + DDL_ASSERT(IS_VALID_SS_SETUP_DELAY_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayOption)); + DDL_ASSERT(IS_VALID_SS_SETUP_DELAY_TIME(pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayTime)); + DDL_ASSERT(IS_VALID_SS_HOLD_DELAY_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayOption)); + DDL_ASSERT(IS_VALID_SS_HOLD_DELAY_TIME(pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayTime)); + DDL_ASSERT(IS_VALID_SS_INTERVAL_TIME_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsIntervalTimeOption)); + DDL_ASSERT(IS_VALID_SS_INTERVAL_TIME(pstcSpiInitCfg->stcDelayConfig.enSsIntervalTime)); + DDL_ASSERT(IS_VALID_SS_VALID_CHANNEL(pstcSpiInitCfg->stcSsConfig.enSsValidBit)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs0Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs1Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs2Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs3Polarity)); + DDL_ASSERT(IS_VALID_READ_DATA_REG_OBJECT(pstcSpiInitCfg->enReadBufferObject)); + DDL_ASSERT(IS_VALID_SCK_POLARITY(pstcSpiInitCfg->enSckPolarity)); + DDL_ASSERT(IS_VALID_SCK_PHASE(pstcSpiInitCfg->enSckPhase)); + DDL_ASSERT(IS_VALID_CLK_DIV(pstcSpiInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_DATA_LENGTH(pstcSpiInitCfg->enDataLength)); + DDL_ASSERT(IS_VALID_FIRST_BIT_POSITION(pstcSpiInitCfg->enFirstBitPosition)); + DDL_ASSERT(IS_VALID_FRAME_NUMBER(pstcSpiInitCfg->enFrameNumber)); + DDL_ASSERT(IS_VALID_WORK_MODE(pstcSpiInitCfg->enWorkMode)); + DDL_ASSERT(IS_VALID_COMM_MODE(pstcSpiInitCfg->enTransMode)); + DDL_ASSERT(IS_VALID_MASTER_SLAVE_MODE(pstcSpiInitCfg->enMasterSlaveMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enCommAutoSuspendEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enModeFaultErrorDetectEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enParitySelfDetectEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enParityEn)); + DDL_ASSERT(IS_VALID_PARITY_MODE(pstcSpiInitCfg->enParity)); + + /* Master mode */ + if (SpiModeMaster == pstcSpiInitCfg->enMasterSlaveMode) + { + SPIx->CFG2_f.MSSIE = pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayOption; + SPIx->CFG2_f.MSSDLE = pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayOption; + SPIx->CFG2_f.MIDIE = pstcSpiInitCfg->stcDelayConfig.enSsIntervalTimeOption; + SPIx->CFG1_f.MSSI = pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayTime; + SPIx->CFG1_f.MSSDL = pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayTime; + SPIx->CFG1_f.MIDI = pstcSpiInitCfg->stcDelayConfig.enSsIntervalTime; + } + else + { + SPIx->CFG2_f.MSSIE = SpiSsSetupDelayTypicalSck1; + SPIx->CFG2_f.MSSDLE = SpiSsHoldDelayTypicalSck1; + SPIx->CFG2_f.MIDIE = SpiSsIntervalTypicalSck1PlusPck2; + SPIx->CFG1_f.MSSI = SpiSsSetupDelaySck1; + SPIx->CFG1_f.MSSDL = SpiSsHoldDelaySck1; + SPIx->CFG1_f.MIDI = SpiSsIntervalSck1PlusPck2; + } + + /* 4 lines spi mode */ + if (SpiWorkMode4Line == pstcSpiInitCfg->enWorkMode) + { + SPIx->CFG2_f.SSA = pstcSpiInitCfg->stcSsConfig.enSsValidBit; + SPIx->CFG1_f.SS0PV = pstcSpiInitCfg->stcSsConfig.enSs0Polarity; + SPIx->CFG1_f.SS1PV = pstcSpiInitCfg->stcSsConfig.enSs1Polarity; + SPIx->CFG1_f.SS2PV = pstcSpiInitCfg->stcSsConfig.enSs2Polarity; + SPIx->CFG1_f.SS3PV = pstcSpiInitCfg->stcSsConfig.enSs3Polarity; + } + else + { + SPIx->CFG2_f.SSA = SpiSsValidChannel0; + SPIx->CFG1_f.SS0PV = SpiSsLowValid; + SPIx->CFG1_f.SS1PV = SpiSsLowValid; + SPIx->CFG1_f.SS2PV = SpiSsLowValid; + SPIx->CFG1_f.SS3PV = SpiSsLowValid; + } + + /* Configure communication config register 1 */ + SPIx->CFG1_f.SPRDTD = pstcSpiInitCfg->enReadBufferObject; + SPIx->CFG1_f.FTHLV = pstcSpiInitCfg->enFrameNumber; + + /* Configure communication config register 2 */ + SPIx->CFG2_f.LSBF = pstcSpiInitCfg->enFirstBitPosition; + SPIx->CFG2_f.DSIZE = pstcSpiInitCfg->enDataLength; + SPIx->CFG2_f.MBR = pstcSpiInitCfg->enClkDiv; + SPIx->CFG2_f.CPOL = pstcSpiInitCfg->enSckPolarity; + SPIx->CFG2_f.CPHA = pstcSpiInitCfg->enSckPhase; + + /* Configure control register */ + SPIx->CR1_f.SPIMDS = pstcSpiInitCfg->enWorkMode; + SPIx->CR1_f.TXMDS = pstcSpiInitCfg->enTransMode; + SPIx->CR1_f.MSTR = pstcSpiInitCfg->enMasterSlaveMode; + SPIx->CR1_f.CSUSPE = pstcSpiInitCfg->enCommAutoSuspendEn; + SPIx->CR1_f.MODFE = pstcSpiInitCfg->enModeFaultErrorDetectEn; + SPIx->CR1_f.PATE = pstcSpiInitCfg->enParitySelfDetectEn; + SPIx->CR1_f.PAE = pstcSpiInitCfg->enParityEn; + SPIx->CR1_f.PAOE = pstcSpiInitCfg->enParity; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI general loopback + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable general loopback + ** \arg Enable Enable general loopback + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_GeneralLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPLPBK2 = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI reverse loopback + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable reverse loopback + ** \arg Enable Enable reverse loopback + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_ReverseLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPLPBK = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI working + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable SPI working + ** \arg Enable Enable SPI working + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_Cmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPE = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 8bit data or 4/5/6/7 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u8Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData8(M4_SPI_TypeDef *SPIx, uint8_t u8Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u8Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 16bit data or 9/10/11/12/13/14/15 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u16Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData16(M4_SPI_TypeDef *SPIx, uint16_t u16Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u16Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 32bit data or 20/24 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u32Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData32(M4_SPI_TypeDef *SPIx, uint32_t u32Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u32Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI receive 8bit data or 4/5/6/7 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint8_t Receive data value + ** + ******************************************************************************/ +uint8_t SPI_ReceiveData8(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint8_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI receive 16bit data or 9/10/11/12/13/14/15 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint16_t Receive data value + ** + ******************************************************************************/ +uint16_t SPI_ReceiveData16(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint16_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI receive 32bit data or 20/24 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint32_t Receive data value + ** + ******************************************************************************/ +uint32_t SPI_ReceiveData32(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint32_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI set SS channel valid level polarity + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enChannel Select Slave channel + ** \arg SpiSsChannel0 SS0 channel + ** \arg SpiSsChannel1 SS1 channel + ** \arg SpiSsChannel2 SS2 channel + ** \arg SpiSsChannel3 SS3 channel + ** + ** \param [in] enPolarity SS channel valid level polarity + ** \arg SpiSsLowValid SS0~3 signal low level valid + ** \arg SpiSsHighValid SS0~3 signal high level valid + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetSsPolarity(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel, + en_spi_ss_polarity_t enPolarity) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_SS_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_SS_POLARITY(enPolarity)); + + switch (enChannel) + { + case SpiSsChannel0: + SPIx->CFG1_f.SS0PV = enPolarity; + break; + case SpiSsChannel1: + SPIx->CFG1_f.SS1PV = enPolarity; + break; + case SpiSsChannel2: + SPIx->CFG1_f.SS2PV = enPolarity; + break; + case SpiSsChannel3: + SPIx->CFG1_f.SS3PV = enPolarity; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set SS valid channel + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enChannel Select Slave channel + ** \arg SpiSsChannel0 SS0 channel + ** \arg SpiSsChannel1 SS1 channel + ** \arg SpiSsChannel2 SS2 channel + ** \arg SpiSsChannel3 SS3 channel + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetSsValidChannel(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_SS_CHANNEL(enChannel)); + + SPIx->CFG2_f.SSA = enChannel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set read data register object + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enObject Read data register object + ** \arg SpiReadReceiverBuffer Read receive buffer + ** \arg SpiReadSendBuffer Read send buffer(must be read when TDEF=1) + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetReadDataRegObject(M4_SPI_TypeDef *SPIx, en_spi_read_object_t enObject) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_READ_DATA_REG_OBJECT(enObject)); + + SPIx->CFG1_f.SPRDTD = enObject; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set frame number + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFrameNum Once read or write frame number + ** \arg SpiFrameNumber1 1 frame data + ** \arg SpiFrameNumber2 2 frame data + ** \arg SpiFrameNumber3 3 frame data + ** \arg SpiFrameNumber4 4 frame data + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetFrameNumber(M4_SPI_TypeDef *SPIx, en_spi_frame_number_t enFrameNum) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FRAME_NUMBER(enFrameNum)); + + SPIx->CFG1_f.FTHLV = enFrameNum; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set data length + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enDataLength Read or write data length + ** \arg SpiDataLengthBit4 4 bits + ** \arg SpiDataLengthBit5 5 bits + ** \arg SpiDataLengthBit6 6 bits + ** \arg SpiDataLengthBit7 7 bits + ** \arg SpiDataLengthBit8 8 bits + ** \arg SpiDataLengthBit9 9 bits + ** \arg SpiDataLengthBit10 10 bits + ** \arg SpiDataLengthBit11 11 bits + ** \arg SpiDataLengthBit12 12 bits + ** \arg SpiDataLengthBit13 13 bits + ** \arg SpiDataLengthBit14 14 bits + ** \arg SpiDataLengthBit15 15 bits + ** \arg SpiDataLengthBit16 16 bits + ** \arg SpiDataLengthBit20 20 bits + ** \arg SpiDataLengthBit24 24 bits + ** \arg SpiDataLengthBit32 32 bits + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetDataLength(M4_SPI_TypeDef *SPIx, en_spi_data_length_t enDataLength) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_DATA_LENGTH(enDataLength)); + + SPIx->CFG2_f.DSIZE = enDataLength; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set first bit position + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enPosition First bit position + ** \arg SpiFirstBitPositionMSB Spi first bit to MSB + ** \arg SpiFirstBitPositionLSB Spi first bit to LSB + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetFirstBitPosition(M4_SPI_TypeDef *SPIx, en_spi_first_bit_position_t enPosition) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FIRST_BIT_POSITION(enPosition)); + + SPIx->CFG2_f.LSBF = enPosition; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set clock division + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enClkDiv Clock division + ** \arg SpiClkDiv2 Spi pclk1 division 2 + ** \arg SpiClkDiv4 Spi pclk1 division 4 + ** \arg SpiClkDiv8 Spi pclk1 division 8 + ** \arg SpiClkDiv16 Spi pclk1 division 16 + ** \arg SpiClkDiv32 Spi pclk1 division 32 + ** \arg SpiClkDiv64 Spi pclk1 division 64 + ** \arg SpiClkDiv128 Spi pclk1 division 128 + ** \arg SpiClkDiv256 Spi pclk1 division 256 + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetClockDiv(M4_SPI_TypeDef *SPIx, en_spi_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_CLK_DIV(enClkDiv)); + + SPIx->CFG2_f.MBR = enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI interrupt request + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enIrq SPI interrupt request type + ** \arg SpiIrqIdle Spi idle interrupt request + ** \arg SpiIrqReceive Spi receive interrupt request + ** \arg SpiIrqSend Spi send interrupt request + ** \arg SpiIrqError Spi error interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_IrqCmd(M4_SPI_TypeDef *SPIx, en_spi_irq_type_t enIrq, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_IRQ_TYPE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enIrq) + { + case SpiIrqIdle: + SPIx->CR1_f.IDIE = enNewSta; + break; + case SpiIrqReceive: + SPIx->CR1_f.RXIE = enNewSta; + break; + case SpiIrqSend: + SPIx->CR1_f.TXIE = enNewSta; + break; + case SpiIrqError: + SPIx->CR1_f.EIE = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get SPI flag status + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFlag SPI flag type + ** \arg SpiFlagReceiveBufferFull Receive buffer full flag + ** \arg SpiFlagSendBufferEmpty Send buffer empty flag + ** \arg SpiFlagUnderloadError Underload error flag + ** \arg SpiFlagParityError Parity error flag + ** \arg SpiFlagModeFaultError Mode fault error flag + ** \arg SpiFlagSpiIdle SPI idle flag + ** \arg SpiFlagOverloadErro Overload error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t SPI_GetFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + if (IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SpiFlagReceiveBufferFull: + enFlagSta = (en_flag_status_t)SPIx->SR_f.RDFF; + break; + case SpiFlagSendBufferEmpty: + enFlagSta = (en_flag_status_t)SPIx->SR_f.TDEF; + break; + case SpiFlagUnderloadError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.UDRERF; + break; + case SpiFlagParityError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.PERF; + break; + case SpiFlagModeFaultError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.MODFERF; + break; + case SpiFlagSpiIdle: + enFlagSta = (en_flag_status_t)(bool)(!SPIx->SR_f.IDLNF); + break; + case SpiFlagOverloadError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.OVRERF; + break; + default: + break; + } + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear SPI flag status + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFlag SPI flag type + ** \arg SpiFlagReceiveBufferFull Receive buffer full flag + ** \arg SpiFlagSendBufferEmpty Send buffer empty flag + ** \arg SpiFlagUnderloadError Underload error flag + ** \arg SpiFlagParityError Parity error flag + ** \arg SpiFlagModeFaultError Mode fault error flag + ** \arg SpiFlagSpiIdle SPI empty flag + ** \arg SpiFlagOverloadErro Overload error flag + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_ClearFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SpiFlagReceiveBufferFull: + SPIx->SR_f.RDFF = 0u; + break; + case SpiFlagSendBufferEmpty: + SPIx->SR_f.TDEF = 0u; + break; + case SpiFlagUnderloadError: + SPIx->SR_f.UDRERF = 0u; + break; + case SpiFlagParityError: + SPIx->SR_f.PERF = 0u; + break; + case SpiFlagModeFaultError: + SPIx->SR_f.MODFERF = 0u; + break; + case SpiFlagSpiIdle: + SPIx->SR_f.IDLNF = 0u; + break; + case SpiFlagOverloadError: + SPIx->SR_f.OVRERF = 0u; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +//@} // SpiGroup + +#endif /* DDL_SPI_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_sram.c b/driver/src/hc32f460_sram.c new file mode 100644 index 0000000..a7f8828 --- /dev/null +++ b/driver/src/hc32f460_sram.c @@ -0,0 +1,286 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sram.c + ** + ** A detailed description is available at + ** @link SramGroup Internal SRAM module description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of SRAM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_sram.h" +#include "hc32f460_utility.h" + +#if (DDL_SRAM_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SramGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for ECC/Parity error handling. */ +#define IS_VALID_ERR_OP(x) \ +( ((x) == SramNmi) || \ + ((x) == SramReset)) + +/*! Parameter validity check for SRAM ECC mode */ +#define IS_VALID_ECC_MD(x) \ +( ((x) == EccMode0) || \ + ((x) == EccMode1) || \ + ((x) == EccMode2) || \ + ((x) == EccMode3)) + +/*! Parameter validity check for SRAM Index */ +#define IS_VALID_INDEX(x) \ +( ((x) == Sram12Idx) || \ + ((x) == Sram3Idx) || \ + ((x) == SramHsIdx) || \ + ((x) == SramRetIdx)) + +/*! Parameter validity check for SRAM R/W wait cycle */ +#define IS_VALID_WAIT_CYCLE(x) \ +( ((x) == SramCycle1) || \ + ((x) == SramCycle2) || \ + ((x) == SramCycle3) || \ + ((x) == SramCycle4) || \ + ((x) == SramCycle5) || \ + ((x) == SramCycle6) || \ + ((x) == SramCycle7) || \ + ((x) == SramCycle8)) + +/*! Parameter validity check for SRAM error status */ +#define IS_VALID_ERR(x) \ +( ((x) == Sram3EccErr1) || \ + ((x) == Sram3EccErr2) || \ + ((x) == Sram12ParityErr) || \ + ((x) == SramHSParityErr) || \ + ((x) == SramRetParityErr)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SRAM read, write wait cycle register disable function + ** + ** \param None + ** + ** \retval Ok SRAM R/W wait cycle register disabled + ** + ******************************************************************************/ +en_result_t SRAM_WT_Disable(void) +{ + M4_SRAMC->WTPR = 0x76u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM read, write wait cycle register enable function + ** + ** \param None + ** + ** \retval Ok SRAM R/W wait cycle register enabled + ** + ******************************************************************************/ +en_result_t SRAM_WT_Enable(void) +{ + M4_SRAMC->WTPR = 0x77u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM ECC/Parity check register disable function + ** + ** \param None + ** + ** \retval Ok SRAM ECC/Parity check register disabled + ** + ******************************************************************************/ +en_result_t SRAM_CK_Disable(void) +{ + M4_SRAMC->CKPR = 0x76u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM ECC/Parity check register enable function + ** + ** \param None + ** + ** \retval Ok SRAM ECC/Parity check register enabled + ** + ******************************************************************************/ +en_result_t SRAM_CK_Enable(void) +{ + M4_SRAMC->CKPR = 0x77u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get SRAM ECC/Parity error status flag + ** + ** \param [in] enSramErrStatus SRAM error status, This parameter can be + ** some values of @ref en_sram_err_status_t + ** + ** \retval Set Corresponding error occurs + ** Reset Corresponding error not occurs + ** + ******************************************************************************/ +en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus) +{ + DDL_ASSERT(IS_VALID_ERR(enSramErrStatus)); + if (true == !!(enSramErrStatus & M4_SRAMC->CKSR)) + { + return Set; + } + else + { + return Reset; + } +} + +/** + ******************************************************************************* + ** \brief Clear SRAM ECC/Parity error status flag + ** + ** \param [in] enSramErrStatus SRAM error status, This parameter can be + ** some values of @ref en_sram_err_status_t + ** + ** \retval Ok Corresponding error flag be cleared + ** ErrorInvalidParameter Invalid parameter + ** + ******************************************************************************/ +en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus) +{ + DDL_ASSERT(IS_VALID_ERR(enSramErrStatus)); + M4_SRAMC->CKSR |= enSramErrStatus; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM initialization + ** + ** \param [in] pstcSramConfig SRAM configure structure + ** + ** \retval Ok SRAM initialized + ** ErrorInvalidParameter Invalid parameter + ** + ******************************************************************************/ +en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig) +{ + uint8_t i = 0u; + uint8_t u8TmpIdx; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramRC)); + DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramWC)); + DDL_ASSERT(IS_VALID_ECC_MD(pstcSramConfig->enSramEccMode)); + DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramEccOp)); + DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramPyOp)); + + u8TmpIdx = pstcSramConfig->u8SramIdx; + + if (0u == u8TmpIdx) + { + enRet = ErrorInvalidParameter; + } + else + { + SRAM_WT_Enable(); + SRAM_CK_Enable(); + for (i = 0u; i < 4u; i++) + { + if (true == (u8TmpIdx & 0x01u)) + { + M4_SRAMC->WTCR |= (pstcSramConfig->enSramRC | \ + (pstcSramConfig->enSramWC << 4ul)) << (i * 8ul); + } + u8TmpIdx >>= 1u; + } + /* SRAM3 ECC config */ + if (pstcSramConfig->u8SramIdx & Sram3Idx) + { + M4_SRAMC->CKCR_f.ECCMOD = pstcSramConfig->enSramEccMode; + M4_SRAMC->CKCR_f.ECCOAD = pstcSramConfig->enSramEccOp; + } + /* SRAM1/2/HS/Ret parity config */ + else + { + M4_SRAMC->CKCR_f.PYOAD = pstcSramConfig->enSramPyOp; + } + + SRAM_WT_Disable(); + SRAM_CK_Disable(); + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief SRAM de-initialization + ** + ** \param None + ** + ** \retval Ok SRAM de-initialized + ** + ******************************************************************************/ +en_result_t SRAM_DeInit(void) +{ + /* SRAM R/W wait register */ + M4_SRAMC->WTPR = 0x77ul; + M4_SRAMC->WTCR = 0ul; + M4_SRAMC->WTPR = 0x76ul; + + /* SRAM check register */ + M4_SRAMC->CKPR = 0x77ul; + M4_SRAMC->CKCR = 0ul; + M4_SRAMC->CKPR = 0x76ul; + + /* SRAM status register */ + M4_SRAMC->CKSR = 0x1Ful; + + return Ok; +} + +//@} // SramGroup + +#endif /* DDL_SRAM_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_swdt.c b/driver/src/hc32f460_swdt.c new file mode 100644 index 0000000..57d5766 --- /dev/null +++ b/driver/src/hc32f460_swdt.c @@ -0,0 +1,170 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_swdt.c + ** + ** A detailed description is available at + ** @link SwdtGroup Special Watchdog Counter description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of SWDT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_swdt.h" +#include "hc32f460_utility.h" + +#if (DDL_SWDT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SwdtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (SwdtFlagCountUnderflow == (x)) || \ + (SwdtFlagRefreshError == (x))) + +/*!< SWDT_RR register refresh key */ +#define SWDT_REFRESH_START_KEY ((uint16_t)0x0123) +#define SWDT_REFRESH_END_KEY_ ((uint16_t)0x3210) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT refresh counter + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t SWDT_RefreshCounter(void) +{ + en_result_t enRet = Ok; + + M4_SWDT->RR = SWDT_REFRESH_START_KEY; + M4_SWDT->RR = SWDT_REFRESH_END_KEY_; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get SWDT counter current count value + ** + ** \param [in] None + ** + ** \retval uint16_t SWDT counter current count value + ** + ******************************************************************************/ +uint16_t SWDT_GetCountValue(void) +{ + return ((uint16_t)M4_SWDT->SR_f.CNT); +} + +/** + ******************************************************************************* + ** \brief Get SWDT flag status + ** + ** \param [in] enFlag SWDT flag type + ** \arg SwdtFlagCountUnderflow Count underflow flag + ** \arg SwdtFlagRefreshError Refresh error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t SWDT_GetFlag(en_swdt_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SwdtFlagCountUnderflow: + enFlagSta = (en_flag_status_t)M4_SWDT->SR_f.UDF; + break; + case SwdtFlagRefreshError: + enFlagSta = (en_flag_status_t)M4_SWDT->SR_f.REF; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear SWDT flag status + ** + ** \param [in] enFlag SWDT flag type + ** \arg SwdtFlagCountUnderflow Count underflow flag + ** \arg SwdtFlagRefreshError Refresh error flag + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t SWDT_ClearFlag(en_swdt_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SwdtFlagCountUnderflow: + M4_SWDT->SR_f.UDF = 0u; + break; + case SwdtFlagRefreshError: + M4_SWDT->SR_f.REF = 0u; + break; + default: + break; + } + + return enRet; +} + +//@} // SwdtGroup + +#endif /* DDL_SWDT_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/driver/src/hc32f460_timer0.c b/driver/src/hc32f460_timer0.c new file mode 100644 index 0000000..497f5d9 --- /dev/null +++ b/driver/src/hc32f460_timer0.c @@ -0,0 +1,967 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer0.c + ** + ** A detailed description is available at + ** @link Timer0Group description @endlink + ** + ** - 2018-10-11 CDT First version for Device Driver Library of TIMER0. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer0.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER0_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer0Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Parameter validity check for unit. */ +#define IS_VALID_UNIT(x) \ +( ((x) == M4_TMR01) || \ + ((x) == M4_TMR02)) + +/* Parameter validity check for channel. */ +#define IS_VALID_CHANNEL(x) \ +( ((x) == Tim0_ChannelA) || \ + ((x) == Tim0_ChannelB)) + +/* Parameter validity check for command. */ +#define IS_VALID_COMMAND(x) \ +( ((x) == Disable) || \ + ((x) == Enable)) + +/* Parameter validity check for timer0 function mode. */ +#define IS_VALID_FUNCTION(x) \ +( ((x) == Tim0_OutputCapare) || \ + ((x) == Tim0_InputCaptrue)) + +/* Parameter validity check for clock division. */ +#define IS_VALID_CLK_DIVISION(x) \ +( ((x) == Tim0_ClkDiv0) || \ + ((x) == Tim0_ClkDiv2) || \ + ((x) == Tim0_ClkDiv4) || \ + ((x) == Tim0_ClkDiv8) || \ + ((x) == Tim0_ClkDiv16) || \ + ((x) == Tim0_ClkDiv32) || \ + ((x) == Tim0_ClkDiv64) || \ + ((x) == Tim0_ClkDiv128) || \ + ((x) == Tim0_ClkDiv256) || \ + ((x) == Tim0_ClkDiv512) || \ + ((x) == Tim0_ClkDiv1024)) + +/* Parameter validity check for synchronous clock source. */ +#define IS_VALID_CLK_SYN_SRC(x) \ +( ((x) == Tim0_Pclk1) || \ + ((x) == Tim0_InsideHardTrig)) + +/* Parameter validity check for asynchronous clock source. */ +#define IS_VALID_CLK_ASYN_SRC(x) \ +( ((x) == Tim0_LRC) || \ + ((x) == Tim0_XTAL32)) + +/* Parameter validity check for counter clock mode. */ +#define IS_VALID_CLK_MODE(x) \ +( ((x) == Tim0_Sync) || \ + ((x) == Tim0_Async)) + +/* Parameter validity check for counter clock mode for M4_TMR01. */ +#define IS_VALID_CLK_MODE_UNIT01(x) \ +( (x) == Tim0_Async) + +/* Parameter validity check for external trigger event. */ +#define IS_VALID_TRIG_SRC_EVENT(x) \ +( ((x) <= EVT_PORT_EIRQ15) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW))) + +/* Parameter validity check for common trigger. */ +#define IS_VALID_TIM0_COM_TRIGGER(x) \ +( ((x) == Tim0ComTrigger_1) || \ + ((x) == Tim0ComTrigger_2) || \ + ((x) == Tim0ComTrigger_1_2)) + +/* Delay count for time out */ +#define TIMER0_TMOUT (0x5000ul) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Get clock mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval Tim0_Sync: Synchronous clock + ** \retval Tim0_Async: Asynchronous clock + ** + ******************************************************************************/ +static en_tim0_counter_mode_t TIMER0_GetClkMode(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh) +{ + en_tim0_counter_mode_t enMode = Tim0_Sync; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + switch(enCh) + { + case Tim0_ChannelA: + enMode = (en_tim0_counter_mode_t)pstcTim0Reg->BCONR_f.SYNSA; + break; + case Tim0_ChannelB: + enMode = (en_tim0_counter_mode_t)pstcTim0Reg->BCONR_f.SYNSB; + break; + default: + break; + } + return enMode; +} + +/** + ******************************************************************************* + ** \brief Time delay for register write in asynchronous mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enIsPublicReg Enable for BCONR and STFLR register delay + ** + ** \retval None + ** + ******************************************************************************/ +static void AsyncDelay(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enIsPublicReg) +{ + en_functional_state_t enDelayEn = Disable; + en_tim0_counter_mode_t enModeA = TIMER0_GetClkMode(pstcTim0Reg, Tim0_ChannelA); + en_tim0_counter_mode_t enModeB = TIMER0_GetClkMode(pstcTim0Reg, Tim0_ChannelB); + + if(Enable == enIsPublicReg) + { + if((Tim0_Async == enModeA) || (Tim0_Async == enModeB)) + { + enDelayEn = Enable; + } + } + else + { + if(Tim0_Async == TIMER0_GetClkMode(pstcTim0Reg, enCh)) + { + enDelayEn = Enable; + } + } + + if(Enable == enDelayEn) + { + for(uint32_t i=0ul; iSTFLR_f.CMAF; + break; + case Tim0_ChannelB: + enFlag = (en_flag_status_t)pstcTim0Reg->STFLR_f.CMBF; + break; + default: + break; + } + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear Timer0 status flag + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Timer0_ChA or Timer0_ChB + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_ClearFlag(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->STFLR_f.CMAF =0u; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0u != pstcTim0Reg->STFLR_f.CMAF) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->STFLR_f.CMBF = 0u; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0u != pstcTim0Reg->STFLR_f.CMBF) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Command the timer0 function + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Timer0_ChA or Timer0_ChB + ** + ** \param [in] enCmd Disable or Enable the function + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_Cmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enCmd) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_COMMAND(enCmd)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.CSTA = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.CSTA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.CSTB = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.CSTB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Select the timer0 function mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enFunc Timer0 function,Tim0_OutputCapare or Tim0_InputCapture + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_SetFunc(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_tim0_function_t enFunc) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_FUNCTION(enFunc)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.CAPMDA = enFunc; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enFunc != pstcTim0Reg->BCONR_f.CAPMDA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.CAPMDB = enFunc; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enFunc != pstcTim0Reg->BCONR_f.CAPMDB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 interrupt function command + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enCmd Disable or Enable the function + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_IntCmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enCmd) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_COMMAND(enCmd)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.INTENA = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.INTENA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.INTENB = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.INTENB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer0 counter register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval uint16_t Count register + ** + ******************************************************************************/ +uint16_t TIMER0_GetCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + uint16_t u16Value = 0u; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + u16Value = (uint16_t)((pstcTim0Reg->CNTAR)&0xFFFFu); + } + else + { + u16Value = (uint16_t)((pstcTim0Reg->CNTBR)&0xFFFFu); + } + + return u16Value; +} + +/** + ******************************************************************************* + ** \brief Write Timer0 counter register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] u16Cnt Data to write + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_WriteCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + uint16_t u16Cnt) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->CNTAR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CNTAR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->CNTBR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CNTBR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer0 base compare count register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval uint16_t Base compare count register + ** + ******************************************************************************/ +uint16_t TIMER0_GetCmpReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + uint16_t u16Value = 0u; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + u16Value = (uint16_t)((pstcTim0Reg->CMPAR)&0xFFFFu); + } + else + { + u16Value = (uint16_t)((pstcTim0Reg->CMPBR)&0xFFFFu); + } + return u16Value; +} + +/** + ******************************************************************************* + ** \brief Wirte Timer0 base compare count register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] u16Cnt Data to write + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_WriteCmpReg(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + uint16_t u16Cnt) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->CMPAR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CMPAR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->CMPBR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CMPBR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 peripheral base function initialize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] pstcBaseInit Timer0 function base parameter structure + ** + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_BaseInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + const stc_tim0_base_init_t* pstcBaseInit) +{ + stc_tmr0_bconr_field_t stcBconrTmp; + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + if (NULL != pstcBaseInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_CLK_DIVISION(pstcBaseInit->Tim0_ClockDivision)); + DDL_ASSERT(IS_VALID_CLK_SYN_SRC(pstcBaseInit->Tim0_SyncClockSource)); + DDL_ASSERT(IS_VALID_CLK_ASYN_SRC(pstcBaseInit->Tim0_AsyncClockSource)); + DDL_ASSERT(IS_VALID_CLK_MODE(pstcBaseInit->Tim0_CounterMode)); + + if((M4_TMR01 == pstcTim0Reg)&&(Tim0_ChannelA == enCh)) + { + DDL_ASSERT(IS_VALID_CLK_MODE_UNIT01(pstcBaseInit->Tim0_CounterMode)); + } + + /*Read current BCONR register */ + stcBconrTmp = pstcTim0Reg->BCONR_f; + /* Clear current configurate CH */ + if(Tim0_ChannelA == enCh) + { + *(uint32_t *)&stcBconrTmp &= 0xFFFF0000ul; + } + else + { + *(uint32_t *)&stcBconrTmp &= 0x0000FFFFul; + } + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(*(uint32_t *)&stcBconrTmp != *(uint32_t *)&(pstcTim0Reg->BCONR_f)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + switch(enCh) + { + case Tim0_ChannelA: + + switch(pstcBaseInit->Tim0_CounterMode) + { + case Tim0_Sync: + stcBconrTmp.SYNCLKA = pstcBaseInit->Tim0_SyncClockSource; + break; + case Tim0_Async: + stcBconrTmp.ASYNCLKA = pstcBaseInit->Tim0_AsyncClockSource; + break; + default: + break; + } + /*set clock division*/ + stcBconrTmp.CKDIVA = pstcBaseInit->Tim0_ClockDivision; + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer compare value*/ + pstcTim0Reg->CMPAR = pstcBaseInit->Tim0_CmpValue; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer counter mode*/ + pstcTim0Reg->BCONR_f.SYNSA = pstcBaseInit->Tim0_CounterMode; + AsyncDelay(pstcTim0Reg, enCh, Enable); + u32TimeOut = 0ul; + while(pstcBaseInit->Tim0_CounterMode != pstcTim0Reg->BCONR_f.SYNSA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + break; + + case Tim0_ChannelB: + switch(pstcBaseInit->Tim0_CounterMode) + { + case Tim0_Sync: + stcBconrTmp.SYNCLKB = pstcBaseInit->Tim0_SyncClockSource; + break; + case Tim0_Async: + stcBconrTmp.ASYNCLKB = pstcBaseInit->Tim0_AsyncClockSource; + break; + default: + break; + } + /*set clock division*/ + stcBconrTmp.CKDIVB = pstcBaseInit->Tim0_ClockDivision; + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer compare value*/ + pstcTim0Reg->CMPBR = pstcBaseInit->Tim0_CmpValue; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer counter mode*/ + pstcTim0Reg->BCONR_f.SYNSB = pstcBaseInit->Tim0_CounterMode; + AsyncDelay(pstcTim0Reg, enCh, Enable); + u32TimeOut = 0ul; + while(pstcBaseInit->Tim0_CounterMode != pstcTim0Reg->BCONR_f.SYNSB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + + default: + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 peripheral base function initalize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval Ok Process finished. + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_DeInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + switch(enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR &= 0xFFFF0000ul; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0ul != (pstcTim0Reg->BCONR & 0x0000FFFFul)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + pstcTim0Reg->CMPAR = 0x0000FFFFul; + pstcTim0Reg->CNTAR = 0x00000000ul; + pstcTim0Reg->STFLR_f.CMAF =0u; + break; + + case Tim0_ChannelB: + pstcTim0Reg->BCONR &= 0x0000FFFFul; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0ul != (pstcTim0Reg->BCONR & 0xFFFF0000ul)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + pstcTim0Reg->CMPBR = 0x0000FFFFul; + pstcTim0Reg->CNTBR = 0x00000000ul; + pstcTim0Reg->STFLR_f.CMBF =0u; + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set external trigger source for Timer0 + ** + ** \param [in] enEvent External event source + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER0_SetTriggerSrc(en_event_src_t enEvent) +{ + DDL_ASSERT(IS_VALID_TRIG_SRC_EVENT(enEvent)); + + M4_AOS->TMR0_HTSSR_f.TRGSEL = enEvent; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer0 common trigger. + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_tim0_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER0_ComTriggerCmd(en_tim0_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIM0_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR0_HTSSR |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR0_HTSSR &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Timer0 hardware trigger function initalize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] pStcInit Timer0 hareware trigger function structure + ** + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TIMER0_HardTriggerInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + const stc_tim0_trigger_init_t* pStcInit) +{ + stc_tmr0_bconr_field_t stcBconrTmp; + en_result_t enRet = Ok; + + if(NULL != pStcInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_FUNCTION(pStcInit->Tim0_OCMode)); + DDL_ASSERT(IS_VALID_TRIG_SRC_EVENT(pStcInit->Tim0_SelTrigSrc)); + + /*Read current BCONR register */ + stcBconrTmp = pstcTim0Reg->BCONR_f; + + switch(enCh) + { + case Tim0_ChannelA: + /*set work on input captrue or output capare*/ + stcBconrTmp.CAPMDA = pStcInit->Tim0_OCMode; + /*enable input capture*/ + stcBconrTmp.HICPA = pStcInit->Tim0_InTrigEnable; + /*enable trigger clear counter*/ + stcBconrTmp.HCLEA = pStcInit->Tim0_InTrigClear; + /*enable trigger start counter*/ + stcBconrTmp.HSTAA = pStcInit->Tim0_InTrigStart; + /*enable trigger stop counter*/ + stcBconrTmp.HSTPA = pStcInit->Tim0_InTrigStop; + + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + break; + case Tim0_ChannelB: + /*set work on input captrue or output capare*/ + stcBconrTmp.CAPMDB = pStcInit->Tim0_OCMode; + /*enable input capture*/ + stcBconrTmp.HICPB = pStcInit->Tim0_InTrigEnable; + /*enable trigger clear counter*/ + stcBconrTmp.HCLEB = pStcInit->Tim0_InTrigClear; + /*enable trigger start counter*/ + stcBconrTmp.HSTAB = pStcInit->Tim0_InTrigStart; + /*enable trigger stop counter*/ + stcBconrTmp.HSTPB = pStcInit->Tim0_InTrigStop; + + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + break; + default: + break; + } + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /* Set trigger source*/ + M4_AOS->TMR0_HTSSR_f.TRGSEL = pStcInit->Tim0_SelTrigSrc; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; + +} + +//@} // Timer0Group + +#endif /* DDL_TIMER0_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_timer4_cnt.c b/driver/src/hc32f460_timer4_cnt.c new file mode 100644 index 0000000..1b655b4 --- /dev/null +++ b/driver/src/hc32f460_timer4_cnt.c @@ -0,0 +1,842 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_cnt.c + ** + ** A detailed description is available at + ** @link Timer4CntGroup Timer4CNT description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4CNT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_cnt.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_CNT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4CntGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for CNT pclk division */ +#define IS_VALID_CNT_CLK_DIV(x) \ +( (Timer4CntPclkDiv1 == (x)) || \ + (Timer4CntPclkDiv2 == (x)) || \ + (Timer4CntPclkDiv4 == (x)) || \ + (Timer4CntPclkDiv8 == (x)) || \ + (Timer4CntPclkDiv16 == (x)) || \ + (Timer4CntPclkDiv32 == (x)) || \ + (Timer4CntPclkDiv64 == (x)) || \ + (Timer4CntPclkDiv128 == (x)) || \ + (Timer4CntPclkDiv256 == (x)) || \ + (Timer4CntPclkDiv512 == (x)) || \ + (Timer4CntPclkDiv1024 == (x))) + +/*!< Parameter validity check for CNT mode */ +#define IS_VALID_CNT_MODE(x) \ +( (Timer4CntSawtoothWave == (x)) || \ + (Timer4CntTriangularWave == (x))) + +/*!< Parameter validity check for CNT interrupt mask */ +#define IS_VALID_CNT_INT_MSK(x) \ +( (Timer4CntIntMask0 == (x)) || \ + (Timer4CntIntMask1 == (x)) || \ + (Timer4CntIntMask2 == (x)) || \ + (Timer4CntIntMask3 == (x)) || \ + (Timer4CntIntMask4 == (x)) || \ + (Timer4CntIntMask5 == (x)) || \ + (Timer4CntIntMask6 == (x)) || \ + (Timer4CntIntMask7 == (x)) || \ + (Timer4CntIntMask8 == (x)) || \ + (Timer4CntIntMask9 == (x)) || \ + (Timer4CntIntMask10 == (x)) || \ + (Timer4CntIntMask11 == (x)) || \ + (Timer4CntIntMask12 == (x)) || \ + (Timer4CntIntMask13 == (x)) || \ + (Timer4CntIntMask14 == (x)) || \ + (Timer4CntIntMask15 == (x))) + +/*!< Parameter validity check for CNT match interrupt type */ +#define IS_VALID_CNT_INT_TYPE(x) \ +( (Timer4CntZeroMatchInt == (x)) || \ + (Timer4CntPeakMatchInt == (x))) + +/*!< Parameter validity check for CNT clock source */ +#define IS_VALID_CNT_CLK(x) \ +( (Timer4CntPclk == (x)) || \ + (Timer4CntExtclk == (x))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] pstcInitCfg Pointer to CNT initialization configuration structure + ** \arg This parameter detail refer @ref stc_timer4_cnt_init_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Init(M4_TMR4_TypeDef *TMR4x, + const stc_timer4_cnt_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_tmr4_ccsr_field_t CCSR_f = {0}; + stc_tmr4_cvpr_field_t CVPR_f = {0}; + + /* Check for TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK(pstcInitCfg->enClk)); + DDL_ASSERT(IS_VALID_CNT_MODE(pstcInitCfg->enCntMode)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enBufferCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enZeroIntCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enPeakIntCmd)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(pstcInitCfg->enZeroIntMsk)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(pstcInitCfg->enPeakIntMsk)); + + /* Set default value */ + TMR4x->CCSR = (uint16_t)0x0050u; + TMR4x->CNTR = (uint16_t)0x0000u; + TMR4x->CPSR = (uint16_t)0xFFFFu; + TMR4x->CVPR = (uint16_t)0x0000u; + + /* stop count of CNT */ + CCSR_f.STOP = 1u; + + /* set count clock div of CNT */ + CCSR_f.CKDIV = pstcInitCfg->enClkDiv; + + /* set cnt mode */ + CCSR_f.MODE = pstcInitCfg->enCntMode; + + /* set buffer enable bit */ + CCSR_f.BUFEN = (uint16_t)(pstcInitCfg->enBufferCmd); + + /* set external clock enable bit */ + CCSR_f.ECKEN = (Timer4CntExtclk == pstcInitCfg->enClk) ? ((uint16_t)1u) : ((uint16_t)0u); + + /* Set interrupt enable */ + CCSR_f.IRQZEN = (uint16_t)(pstcInitCfg->enZeroIntCmd); + CCSR_f.IRQPEN = (uint16_t)(pstcInitCfg->enPeakIntCmd); + + /* set intterrupt mask times */ + CVPR_f.ZIM = (uint16_t)(pstcInitCfg->enZeroIntMsk); + CVPR_f.PIM = (uint16_t)(pstcInitCfg->enPeakIntMsk); + + /* Set Timer4 register */ + TMR4x->CVPR_f = CVPR_f; + TMR4x->CCSR_f = CCSR_f; + TMR4x->CPSR = pstcInitCfg->u16Cycle; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_DeInit(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Set default value */ + TMR4x->CCSR = (uint16_t)0x0050u; + TMR4x->CNTR = (uint16_t)0x0000u; + TMR4x->CPSR = (uint16_t)0xFFFFu; + TMR4x->CVPR = (uint16_t)0x0000u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT clock source + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCntClk Timer4 CNT clock source + ** \arg Timer4CntPclk Uses the internal clock (PCLK) as CNT's count clock. + ** \arg Timer4CntExtclk Uses an external input clock (EXCK) as CNT's count clock. + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetClock(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_clk_t enCntClk) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK(enCntClk)); + /* set external clock enable bit */ + TMR4x->CCSR_f.ECKEN = (uint16_t)(enCntClk); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT clock source + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntPclk Uses the internal clock (PCLK) as CNT's count clock. + ** \retval Timer4CntExtclk Uses an external input clock (EXCK) as CNT's count clock. + ** + ******************************************************************************/ +en_timer4_cnt_clk_t TIMER4_CNT_GetClock(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_clk_t)(TMR4x->CCSR_f.ECKEN); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT clock division + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enClkDiv Timer4 CNT clock division + ** \arg Timer4CntPclkDiv1 Timer4 CNT clock: PCLK + ** \arg Timer4CntPclkDiv2 Timer4 CNT clock: PCLK/2 + ** \arg Timer4CntPclkDiv4 Timer4 CNT clock: PCLK/4 + ** \arg Timer4CntPclkDiv8 Timer4 CNT clock: PCLK/8 + ** \arg Timer4CntPclkDiv16 Timer4 CNT clock: PCLK/16 + ** \arg Timer4CntPclkDiv32 Timer4 CNT clock: PCLK/32 + ** \arg Timer4CntPclkDiv64 Timer4 CNT clock: PCLK/64 + ** \arg Timer4CntPclkDiv128 Timer4 CNT clock: PCLK/128 + ** \arg Timer4CntPclkDiv256 Timer4 CNT clock: PCLK/256 + ** \arg Timer4CntPclkDiv512 Timer4 CNT clock: PCLK/512 + ** \arg Timer4CntPclkDiv1024 Timer4 CNT clock: PCLK/1024 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetClockDiv(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(enClkDiv)); + TMR4x->CCSR_f.CKDIV = (uint16_t)enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT clock division + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntPclkDiv1 Timer4 CNT clock: PCLK + ** \retval Timer4CntPclkDiv2 Timer4 CNT clock: PCLK/2 + ** \retval Timer4CntPclkDiv4 Timer4 CNT clock: PCLK/4 + ** \retval Timer4CntPclkDiv8 Timer4 CNT clock: PCLK/8 + ** \retval Timer4CntPclkDiv16 Timer4 CNT clock: PCLK/16 + ** \retval Timer4CntPclkDiv32 Timer4 CNT clock: PCLK/32 + ** \retval Timer4CntPclkDiv64 Timer4 CNT clock: PCLK/64 + ** \retval Timer4CntPclkDiv128 Timer4 CNT clock: PCLK/128 + ** \retval Timer4CntPclkDiv256 Timer4 CNT clock: PCLK/256 + ** \retval Timer4CntPclkDiv512 Timer4 CNT clock: PCLK/512 + ** \retval Timer4CntPclkDiv1024 Timer4 CNT clock: PCLK/1024 + ** + ******************************************************************************/ +en_timer4_cnt_clk_div_t TIMER4_CNT_GetClockDiv(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_clk_div_t)(TMR4x->CCSR_f.CKDIV); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enMode Timer4 CNT mode + ** \arg Timer4CntSawtoothWave Timer4 count mode:sawtooth wave + ** \arg Timer4CntTriangularWave Timer4 count mode:triangular wave + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_MODE(enMode)); + TMR4x->CCSR_f.MODE = (uint16_t)enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntSawtoothWave Timer4 count mode:sawtooth wave + ** \retval Timer4CntTriangularWave Timer4 count mode:triangular wave + ** + ******************************************************************************/ +en_timer4_cnt_mode_t TIMER4_CNT_GetMode(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_mode_t)(TMR4x->CCSR_f.MODE); +} + +/** + ******************************************************************************* + ** \brief Start Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Start successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Start(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.STOP = (uint16_t)0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Stop successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Stop(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.STOP = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT interrupt + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType The specified type of Timer4 CNT interrupt + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** \param [in] enCmd DCU interrupt functional state + ** \arg Enable Enable the specified Timer4 CNT interrupt function + ** \arg Disable Disable the specified Timer4 CNT interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - enIntType is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_IrqCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CCSR_f.IRQZEN = (uint16_t)enCmd; + break; + case Timer4CntPeakMatchInt: + TMR4x->CCSR_f.IRQPEN = (uint16_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Reset None interrupt request on Timer4 CNT + ** \retval Set Detection interrupt request on Timer4 CNT + ** + ******************************************************************************/ +en_flag_status_t TIMER4_CNT_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + uint16_t u16Flag = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + switch (enIntType) + { + case Timer4CntZeroMatchInt: + u16Flag = TMR4x->CCSR_f.IRQZF; + break; + case Timer4CntPeakMatchInt: + u16Flag = TMR4x->CCSR_f.IRQPF; + break; + default: + break; + } + + return (en_flag_status_t)u16Flag; +} + +/** + ******************************************************************************* + ** \brief Clear Timer4 CNT interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - enIntType is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CCSR_f.IRQZF = (uint16_t)0u; + break; + case Timer4CntPeakMatchInt: + TMR4x->CCSR_f.IRQPF = (uint16_t)0u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the cycle value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] u16Cycle The Timer4 CNT cycle value + ** \arg number of 16bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetCycleVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Cycle) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CPSR = u16Cycle; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the cycle value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval The cycle value of the specified Timer4 CNT. + ** + ******************************************************************************/ +uint16_t TIMER4_CNT_GetCycleVal(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return TMR4x->CPSR; +} + +/** + ******************************************************************************* + ** \brief Clear Timer4 CNT register CNTR + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_ClearCountVal(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.CLEAR = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the current count value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] u16Count The Timer4 CNT current count value + ** \arg number of 16bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetCountVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Count) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CNTR = u16Count; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT current count value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval The current count value of the specified Timer4 CNT. + ** + ******************************************************************************/ +uint16_t TIMER4_CNT_GetCountVal(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return TMR4x->CNTR; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT interrupt mask times + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** \param [in] enMaskTimes Timer4 CNT interrupt mask times + ** \arg Timer4CntIntMask0 CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak. + ** \arg Timer4CntIntMask1 CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count). + ** \arg Timer4CntIntMask2 CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count). + ** \arg Timer4CntIntMask3 CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count). + ** \arg Timer4CntIntMask4 CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count). + ** \arg Timer4CntIntMask5 CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count). + ** \arg Timer4CntIntMask6 CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count). + ** \arg Timer4CntIntMask7 CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count). + ** \arg Timer4CntIntMask8 CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count). + ** \arg Timer4CntIntMask9 CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count). + ** \arg Timer4CntIntMask10 CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count). + ** \arg Timer4CntIntMask11 CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count). + ** \arg Timer4CntIntMask12 CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count). + ** \arg Timer4CntIntMask13 CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count). + ** \arg Timer4CntIntMask14 CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count). + ** \arg Timer4CntIntMask15 CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count). + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetIntMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType, + en_timer4_cnt_int_mask_t enMaskTimes) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(enMaskTimes)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CVPR_f.ZIM = (uint16_t)enMaskTimes; + break; + case Timer4CntPeakMatchInt: + TMR4x->CVPR_f.PIM = (uint16_t)enMaskTimes; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT interrupt mask times + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Timer4CntIntMask0 CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak. + ** \retval Timer4CntIntMask1 CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count). + ** \retval Timer4CntIntMask2 CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count). + ** \retval Timer4CntIntMask3 CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count). + ** \retval Timer4CntIntMask4 CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count). + ** \retval Timer4CntIntMask5 CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count). + ** \retval Timer4CntIntMask6 CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count). + ** \retval Timer4CntIntMask7 CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count). + ** \retval Timer4CntIntMask8 CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count). + ** \retval Timer4CntIntMask9 CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count). + ** \retval Timer4CntIntMask10 CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count). + ** \retval Timer4CntIntMask11 CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count). + ** \retval Timer4CntIntMask12 CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count). + ** \retval Timer4CntIntMask13 CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count). + ** \retval Timer4CntIntMask14 CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count). + ** \retval Timer4CntIntMask15 CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count). + ** + ******************************************************************************/ +en_timer4_cnt_int_mask_t TIMER4_CNT_GetIntMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + uint16_t u16MaskTimes = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + switch (enIntType) + { + case Timer4CntZeroMatchInt: + u16MaskTimes = TMR4x->CVPR_f.ZIM; + break; + case Timer4CntPeakMatchInt: + u16MaskTimes = TMR4x->CVPR_f.PIM; + break; + default: + break; + } + + return (en_timer4_cnt_int_mask_t)u16MaskTimes; +} + +//@} // Timer4CntGroup + +#endif /* DDL_TIMER4_CNT_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_timer4_emb.c b/driver/src/hc32f460_timer4_emb.c new file mode 100644 index 0000000..b47a0f0 --- /dev/null +++ b/driver/src/hc32f460_timer4_emb.c @@ -0,0 +1,278 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_emb.c + ** + ** A detailed description is available at + ** @link Timer4EmbGroup Timer4EMB description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4EMB. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_emb.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_EMB_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4EmbGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter valid check for EMB HOLD mode. */ +#define IS_VALID_EMB_HOLD_MODE(x) \ +( (EmbHoldPwm == (x)) || \ + (EmbChangePwm == (x))) + +/*!< Parameter valid check for EMB state. */ +#define IS_VALID_EMB_STATE(x) \ +( (EmbTrigPwmOutputHiz == (x)) || \ + (EmbTrigPwmOutputNormal == (x)) || \ + (EmbTrigPwmOutputLowLevel == (x)) || \ + (EmbTrigPwmOutputHighLevel == (x))) + +/*!< Timer4x ECER register address. */ +#define TMR4_ECERx(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) ? &M4_TMR4_CR->ECER1 : \ + ((M4_TMR42 == (__TMRx__)) ? &M4_TMR4_CR->ECER2 : &M4_TMR4_CR->ECER3)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize Timer4 EMB + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] pstcInitCfg The pointer of EMB configure structure + ** \arg This parameter detail refer @ref stc_timer4_emb_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_Init(M4_TMR4_TypeDef *TMR4x, + const stc_timer4_emb_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATE(pstcInitCfg->enEmbState)); + DDL_ASSERT(IS_VALID_EMB_HOLD_MODE(pstcInitCfg->enPwmHold)); + + /* Set EMB HOLD mode */ + TMR4x->ECSR_f.HOLD = (uint16_t)(pstcInitCfg->enPwmHold); + + /* Set EMB state */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)(pstcInitCfg->enEmbState); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize Timer4 EMB + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok De-Initialize successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_DeInit(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Set reset value(0x0000) to register ESCR */ + TMR4x->ECSR = 0u; + + /* Set reset value(0x0000) to register ECER */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)0ul; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 EMB HOLD mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enHoldMode EMB HOLD mode + ** \arg EmbChangePwm Don't hold PWM output when EMB signal occurs + ** \arg EmbHoldPwm Hold PWM output when EMB signal occurs + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_SetHoldMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_emb_hold_mode_t enHoldMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_HOLD_MODE(enHoldMode)); + + /* Set EMB HOLD mode */ + TMR4x->ECSR_f.HOLD = (uint16_t)enHoldMode; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 EMB HOLD mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval EmbChangePwm Don't hold PWM output when EMB signal occurs + ** \retval EmbHoldPwm Hold PWM output when EMB signal occurs + ** + ******************************************************************************/ +en_timer4_emb_hold_mode_t TIMER4_EMB_GetHoldMode(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_emb_hold_mode_t)(TMR4x->ECSR_f.HOLD); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 EMB state + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enEmbState EMB state + ** \arg EmbTrigPwmOutputNormal PWM output signal normally. + ** \arg EmbTrigPwmOutputHiz PWM output Hiz signal. + ** \arg EmbTrigPwmOutputLowLevel PWM output low level signal. + ** \arg EmbTrigPwmOutputHighLevel PWM output high level signal. + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_SetState(const M4_TMR4_TypeDef *TMR4x, + en_timer4_emb_state_t enEmbState) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATE(enEmbState)); + + /* Set EMB state */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)enEmbState; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 EMB state + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval EmbTrigPwmOutputNormal PWM output signal normally. + ** \retval EmbTrigPwmOutputHiz PWM output Hiz signal. + ** \retval EmbTrigPwmOutputLowLevel PWM output low level signal. + ** \retval EmbTrigPwmOutputHighLevel PWM output high level signal. + ** + ******************************************************************************/ +en_timer4_emb_state_t TIMER4_EMB_GetState(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return *(__IO en_timer4_emb_state_t *)TMR4_ECERx(TMR4x); +} + +//@} // Timer4EmbGroup + +#endif /* DDL_TIMER4_EMB_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_timer4_oco.c b/driver/src/hc32f460_timer4_oco.c new file mode 100644 index 0000000..25281df --- /dev/null +++ b/driver/src/hc32f460_timer4_oco.c @@ -0,0 +1,1295 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_oco.c + ** + ** A detailed description is available at + ** @link Timer4OcoGroup Timer4OCO description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4OCO. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_oco.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_OCO_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4OcoGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for oco channel */ +#define IS_VALID_OCO_CH(x) \ +( (Timer4OcoOuh == (x)) || \ + (Timer4OcoOul == (x)) || \ + (Timer4OcoOvh == (x)) || \ + (Timer4OcoOvl == (x)) || \ + (Timer4OcoOwh == (x)) || \ + (Timer4OcoOwl == (x))) + +/*!< Parameter validity check for oco low channel */ +#define IS_VALID_OCO_LOW_CH(x) \ +( (Timer4OcoOul == (x)) || \ + (Timer4OcoOvl == (x)) || \ + (Timer4OcoOwl == (x))) + +/*!< Parameter validity check for even high channel */ +#define IS_VALID_OCO_HIGH_CH(x) \ +( (Timer4OcoOuh == (x)) || \ + (Timer4OcoOvh == (x)) || \ + (Timer4OcoOwh == (x))) + +/*!< Parameter validity check for occr buffer mode */ +#define IS_VALID_OCCR_BUF_MODE(x) \ +( (OccrBufDisable == (x)) || \ + (OccrBufTrsfByCntZero == (x)) || \ + (OccrBufTrsfByCntPeak == (x)) || \ + (OccrBufTrsfByCntZeroOrCntPeak == (x)) || \ + (OccrBufTrsfByCntZeroZicZero == (x)) || \ + (OccrBufTrsfByCntPeakPicZero == (x)) || \ + (OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for ocmr buffer mode */ +#define IS_VALID_OCMR_BUF_MODE(x) \ +( (OcmrBufDisable == (x)) || \ + (OcmrBufTrsfByCntZero == (x)) || \ + (OcmrBufTrsfByCntPeak == (x)) || \ + (OcmrBufTrsfByCntZeroOrCntPeak == (x)) || \ + (OcmrBufTrsfByCntZeroZicZero == (x)) || \ + (OcmrBufTrsfByCntPeakPicZero == (x)) || \ + (OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for output level type */ +#define IS_VALID_OP_PORT_LEVEL(x) \ +( (OcPortLevelLow == (x)) || \ + (OcPortLevelHigh == (x))) + +/*!< Parameter validity check for oco OP state */ +#define IS_VALID_OP_STATE(x) \ +( (OcoOpOutputLow == (x)) || \ + (OcoOpOutputHigh == (x)) || \ + (OcoOpOutputHold == (x)) || \ + (OcoOpOutputReverse == (x))) + +/*!< Parameter validity check for oco OCF state */ +#define IS_VALID_OCF_STATE(x) \ +( (OcoOcfSet == (x)) || \ + (OcoOcfHold == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_OCCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCCRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_OCMRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCMRHUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_OCERx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCERU + (((uint32_t)(__CH__))/2ul)*4ul) +#define TMR4_OCSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCSRU + (((uint32_t)(__CH__))/2ul)*4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize OCO module + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcInitCfg The pointer of OCO configure structure + ** \arg This parameter detail refer @ref stc_timer4_oco_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_timer4_oco_init_t* pstcInitCfg) +{ + __IO stc_tmr4_ocsr_field_t* pstcOCSR = NULL; + __IO stc_tmr4_ocer_field_t* pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enOcoIntCmd)); + DDL_ASSERT(IS_VALID_OP_PORT_LEVEL(pstcInitCfg->enPortLevel)); + DDL_ASSERT(IS_VALID_OCMR_BUF_MODE(pstcInitCfg->enOcmrBufMode)); + DDL_ASSERT(IS_VALID_OCCR_BUF_MODE(pstcInitCfg->enOccrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x,enCh); + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x,enCh); + + /* Set OCMR and OCCR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + pstcOCSR->OCEH = (uint16_t)0u; + pstcOCSR->OCFH = (uint16_t)0u; + + /* OCMR buffer */ + switch (pstcInitCfg->enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + /* OCCR buffer */ + switch (pstcInitCfg->enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (enRet == Ok) + { + /* Set initial OP level */ + pstcOCSR->OCPH = (uint16_t)(pstcInitCfg->enPortLevel); + /* set interrupt enable */ + pstcOCSR->OCIEH = (uint16_t)(pstcInitCfg->enOcoIntCmd); + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + pstcOCSR->OCEL = (uint16_t)0u; + pstcOCSR->OCFL = (uint16_t)0u; + + /* OCMR buffer */ + switch (pstcInitCfg->enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + /* OCCR buffer */ + switch (pstcInitCfg->enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (enRet == Ok) + { + /* Set initial OP level */ + pstcOCSR->OCPL = (uint16_t)(pstcInitCfg->enPortLevel); + /* set interrupt enable */ + pstcOCSR->OCIEL = (uint16_t)(pstcInitCfg->enOcoIntCmd); + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize OCO module + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO uint16_t* pu16OCCR = NULL; + __IO uint32_t u32OCMR = 0ul; + __IO stc_tmr4_ocsr_field_t* pstcOCSR = NULL; + __IO stc_tmr4_ocer_field_t* pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + u32OCMR = TMR4_OCMRx(TMR4x, enCh); + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set default value */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + pstcOCSR->OCEH = (uint16_t)0u; + pstcOCSR->OCFH = (uint16_t)0u; + pstcOCSR->OCIEH = (uint16_t)0u; + pstcOCSR->OCPH = (uint16_t)0u; + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + pstcOCER->MCECH = (uint16_t)0u; + *pu16OCCR = (uint16_t)0u; + *(__IO uint16_t*)u32OCMR = (uint16_t)0u; + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + pstcOCSR->OCEL = (uint16_t)0u; + pstcOCSR->OCFL = (uint16_t)0u; + pstcOCSR->OCIEL = (uint16_t)0u; + pstcOCSR->OCPL = (uint16_t)0u; + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + pstcOCER->MCECL = (uint16_t)0u; + *pu16OCCR = (uint16_t)0u; + *(__IO uint32_t*)u32OCMR = (uint32_t)0ul; + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set occr buffer mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enOccrBufMode Occr buffer mode + ** \arg OccrBufDisable Disable the register buffer function + ** \arg OccrBufTrsfByCntZero Register buffer transfer when counter value is 0x0000 + ** \arg OccrBufTrsfByCntPeak Register buffer transfer when counter value is CPSR + ** \arg OccrBufTrsfByCntZeroOrCntPeak Register buffer transfer when the value is both 0 and CPSR + ** \arg OccrBufTrsfByCntZeroZicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 + ** \arg OccrBufTrsfByCntPeakPicZero Register buffer transfer when counter value is CPSR and peak value detection mask counter value is 0 ** + ** \arg OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 or + ** counter value is CPSR and peak value detection mask counter value is 0 + ** \retval Ok OCO occr buffer mode initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** - enOccrBufMode is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOccrBufMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_occr_buf_t enOccrBufMode) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OCCR_BUF_MODE(enOccrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set OCCR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + /* OCCR buffer */ + switch (enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + /* OCCR buffer */ + switch (enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set occr buffer mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enOcmrBufMode Occr buffer mode + ** \arg OcmrBufDisable Disable the register buffer function + ** \arg OcmrBufTrsfByCntZero Register buffer transfer when counter value is 0x0000 + ** \arg OcmrBufTrsfByCntPeak Register buffer transfer when counter value is CPSR + ** \arg OcmrBufTrsfByCntZeroOrCntPeak Register buffer transfer when the value is both 0 and CPSR + ** \arg OcmrBufTrsfByCntZeroZicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 + ** \arg OcmrBufTrsfByCntPeakPicZero Register buffer transfer when counter value is CPSR and peak value detection mask counter value is 0 ** + ** \arg OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 or + ** counter value is CPSR and peak value detection mask counter value is 0 + ** + ** \retval Ok OCO ocmr buffer mode initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** - enOcmrBufMode is invalid. + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOcmrBufMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_ocmr_buf_t enOcmrBufMode) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OCMR_BUF_MODE(enOcmrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set OCMR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + /* OCMR buffer */ + switch (enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + /* OCMR buffer */ + switch (enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Extend the matching determination conditions of OCO channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd Extend the match conditions functional state + ** \arg Enable Extend the match conditions function + ** \arg Disable Don't extend the match conditions function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_ExtMatchCondCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCER->MCECH = (uint16_t)enCmd) : (pstcOCER->MCECL = (uint16_t)enCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set compare mode of OCO high channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcMode pointer to structure of compare mode + ** \arg This parameter detail refer @ref stc_oco_high_ch_compare_mode_t + ** + ** \retval Ok OCO high channel compare mode is set successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcMode pointer is NULL + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetHighChCompareMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_oco_high_ch_compare_mode_t *pstcMode) +{ + uint16_t u16OCMR = 0u; + __IO uint16_t *pu16OCMR = NULL; + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcMode pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcMode)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_HIGH_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroNotMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakNotMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownCntMatchOpState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntZeroMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntUpCntMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntPeakMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntDownCntMatchOcfState)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcMode->enMatchConditionExtendCmd)); + + /* Get pointer of current channel OCO register address */ + pu16OCMR = (__IO uint16_t*)TMR4_OCMRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + pstcOCER->MCECH = (uint16_t)(pstcMode->enMatchConditionExtendCmd); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroMatchOpState << 10u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroNotMatchOpState << 14u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntUpCntMatchOpState << 8u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakMatchOpState << 6u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakNotMatchOpState << 12u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntDownCntMatchOpState << 4u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroMatchOcfState << 3u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntUpCntMatchOcfState << 2u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakMatchOcfState << 1u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntDownCntMatchOcfState << 0u); + + *pu16OCMR = u16OCMR; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set compare mode of OCO low channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcMode pointer to structure of compare mode + ** \arg This parameter detail refer @ref TIMER4_OCO_SetLowChCompareMode + ** + ** \retval Ok OCO low channel compare mode is set successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcMode pointer is NULL + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetLowChCompareMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_oco_low_ch_compare_mode_t *pstcMode) +{ + uint32_t u32OCMR = 0ul; + __IO uint32_t *pu32OCMR = NULL; + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer and pstcMode pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcMode)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_LOW_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowNotMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowNotMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntZeroMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntUpCntMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntPeakMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntDownCntMatchOcfState)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcMode->enMatchConditionExtendCmd)); + + /* Get pointer of current channel OCO register address */ + pu32OCMR = (__IO uint32_t*)TMR4_OCMRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh);; + + pstcOCER->MCECL = (uint16_t)(pstcMode->enMatchConditionExtendCmd); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowMatchHighMatchLowChOpState << 26u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowMatchHighNotMatchLowChOpState << 10u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowNotMatchHighMatchLowChOpState << 30u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowNotMatchHighNotMatchLowChOpState << 14u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowMatchHighMatchLowChOpState << 24u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowMatchHighNotMatchLowChOpState << 8u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowNotMatchHighMatchLowChOpState << 18u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowMatchHighMatchLowChOpState << 22u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowMatchHighNotMatchLowChOpState << 6u) ; + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowNotMatchHighMatchLowChOpState << 28u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowNotMatchHighNotMatchLowChOpState << 12u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowMatchHighMatchLowChOpState << 20u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowMatchHighNotMatchLowChOpState << 4u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowNotMatchHighMatchLowChOpState << 16u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroMatchOcfState << 3u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntMatchOcfState << 2u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakMatchOcfState << 1u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownCntMatchOcfState << 0u); + + *pu32OCMR = u32OCMR; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set output function + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd The output functional state + ** \arg Enable Enable output function + ** \arg Disable Disable output function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_OutputCompareCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + /* set register */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCEH = (uint16_t)enCmd) : (pstcOCSR->OCEL = (uint16_t)enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set OCO interrupt function + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd The interrupt functional state + ** \arg Enable Enable interrupt function + ** \arg Disable Disable interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_IrqCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + /* set register */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCIEH = (uint16_t)enCmd) : (pstcOCSR->OCIEL = (uint16_t)enCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OCO interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Reset None interrupt request on Timer4 OCO + ** \retval Set Detection interrupt request on Timer4 OCO + ** + ******************************************************************************/ +en_flag_status_t TIMER4_OCO_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + en_flag_status_t enFlag = Reset; + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + /* set return value */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + enFlag = (en_flag_status_t)(pstcOCSR->OCFH); + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + enFlag = (en_flag_status_t)(pstcOCSR->OCFL); + } + else + { + /* Do nothing: only avoid MISRA warning */ + } + + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear OCO interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Ok OCO interrupt flag is clear + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + /* set return value */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCFH = 0u) : (pstcOCSR->OCFL = 0u); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set OP pin level of OCO + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enLevel OP port level of OCO + ** \arg OcPortLevelLow Output low level to OC port + ** \arg OcPortLevelHigh Output high level to OC port + ** + ** \retval Ok OCO interrupt flag is clear + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOpPortLevel(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_port_level_t enLevel) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_PORT_LEVEL(enLevel)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCFH = (uint16_t)enLevel) : (pstcOCSR->OCFL = (uint16_t)enLevel); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OP pin level of OCO + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval OcPortLevelLow Output low level to OC port + ** \retval OcPortLevelHigh Output high level to OC port + ** + ******************************************************************************/ +en_timer4_oco_port_level_t TIMER4_OCO_GetOpPinLevel(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_timer4_oco_port_level_t enLevel = OcPortLevelLow; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + enLevel = (en_timer4_oco_port_level_t)(pstcOCSR->OCPH); + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + enLevel = (en_timer4_oco_port_level_t)(pstcOCSR->OCPL); + } + else + { + /* Do nothing: only avoid MISRA warning */ + } + + return enLevel; +} + +/** + ******************************************************************************* + ** \brief Write OCCR register + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] u16Occr The value of occr + ** \arg 16bit value + ** + ** \retval Ok OCCR written + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_WriteOccr(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + uint16_t u16Occr) +{ + __IO uint16_t *pu16OCCR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + /* set register */ + *pu16OCCR = u16Occr; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OCCR register value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval OCCR register value + ** + ******************************************************************************/ +uint16_t TIMER4_OCO_ReadOccr(const M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO uint16_t* pu16OCCR = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + + return (*pu16OCCR); +} + +//@} // Timer4OcoGroup + +#endif /* DDL_TIMER4_OCO_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_timer4_pwm.c b/driver/src/hc32f460_timer4_pwm.c new file mode 100644 index 0000000..0a1c983 --- /dev/null +++ b/driver/src/hc32f460_timer4_pwm.c @@ -0,0 +1,600 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_pwm.c + ** + ** A detailed description is available at + ** @link Timer4PwmGroup Timer4PWM description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4PWM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_pwm.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_PWM_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4PwmGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for PWM channel */ +#define IS_VALID_PWM_CH(x) \ +( (Timer4PwmU == (x)) || \ + (Timer4PwmV == (x)) || \ + (Timer4PwmW == (x))) + +/*!< Parameter validity check for PWM mode */ +#define IS_VALID_PWM_MODE(x) \ +( (PwmThroughMode == (x)) || \ + (PwmDeadTimerMode == (x)) || \ + (PwmDeadTimerFilterMode == (x))) + +/*!< Parameter valid check for PWM output state. */ +#define IS_VALID_PWM_OUTPUT_STATE(x) \ +( (PwmHPwmLHold == (x)) || \ + (PwmHPwmLReverse == (x)) || \ + (PwmHReversePwmLHold == (x)) || \ + (PwmHHoldPwmLReverse == (x))) + +/*!< Parameter valid check for PWM clock division. */ +#define IS_VALID_PWM_CLK_DIV(x) \ +( (PwmPlckDiv1 == (x)) || \ + (PwmPlckDiv2 == (x)) || \ + (PwmPlckDiv4 == (x)) || \ + (PwmPlckDiv8 == (x)) || \ + (PwmPlckDiv16 == (x)) || \ + (PwmPlckDiv32 == (x)) || \ + (PwmPlckDiv64 == (x)) || \ + (PwmPlckDiv128 == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_RCSRx(__TMR4x__) ((uint32_t)&(__TMR4x__)->RCSR) +#define TMR4_POCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->POCRU + ((uint32_t)(__CH__))*4ul) +#define TMR4_PDARx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PDARU + ((uint32_t)(__CH__))*8ul) +#define TMR4_PDBRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PDBRU + ((uint32_t)(__CH__))*8ul) +#define TMR4_PFSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PFSRU + ((uint32_t)(__CH__))*8ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize a couple PWM channels + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] pstcInitCfg The pointer of PWM configure structure + ** \arg This parameter detail refer @ref stc_timer4_pwm_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + const stc_timer4_pwm_init_t *pstcInitCfg) +{ + __IO stc_tmr4_pocr_field_t *pstcPOCR_f = NULL; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + en_result_t enRet = Ok; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_MODE(pstcInitCfg->enMode)); + DDL_ASSERT(IS_VALID_PWM_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enRtIntMaskCmd)); + DDL_ASSERT(IS_VALID_PWM_OUTPUT_STATE(pstcInitCfg->enOutputState)); + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + pstcPOCR_f = (__IO stc_tmr4_pocr_field_t*)TMR4_POCRx(TMR4x, enCh); + + /* Configure PWM mode */ + pstcPOCR_f->PWMMD = (uint16_t)(pstcInitCfg->enMode); + + /* Configure PWM mode */ + pstcPOCR_f->LVLS = (uint16_t)(pstcInitCfg->enOutputState); + + /* Set timer clock division */ + pstcPOCR_f->DIVCK = (uint16_t)(pstcInitCfg->enClkDiv); + + /* Set interrupt mask */ + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTIDU = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + case Timer4PwmV: + pstcRCSR_f->RTIDV = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + case Timer4PwmW: + pstcRCSR_f->RTIDW = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize a couple PWM channels + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = Ok; + __IO uint16_t *pu16PDAR = NULL; + __IO uint16_t *pu16PDBR = NULL; + __IO uint16_t *pu16PFSR = NULL; + __IO stc_tmr4_pocr_field_t *pstcPOCR_f = NULL; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Get pointer of current channel PWM register address */ + pu16PDAR = (__IO uint16_t*)TMR4_PDARx(TMR4x, enCh); + pu16PDBR = (__IO uint16_t*)TMR4_PDBRx(TMR4x, enCh); + pu16PFSR = (__IO uint16_t*)TMR4_PFSRx(TMR4x, enCh); + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + pstcPOCR_f = (__IO stc_tmr4_pocr_field_t*)TMR4_POCRx(TMR4x, enCh); + + *pu16PDAR = (uint16_t)0u; + *pu16PDBR = (uint16_t)0u; + *pu16PFSR = (uint16_t)0u; + pstcPOCR_f->DIVCK = (uint16_t)0u; + pstcPOCR_f->LVLS = (uint16_t)0u; + pstcPOCR_f->PWMMD = (uint16_t)0u; + + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTIDU = (uint16_t)0u; + break; + case Timer4PwmV: + pstcRCSR_f->RTIDV = (uint16_t)0u; + break; + case Timer4PwmW: + pstcRCSR_f->RTIDW = (uint16_t)0u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok Start timer successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_StartTimer(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTEU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTEV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTEW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok Stop timer successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_StopTimer(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTSU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTSV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTSW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get PWM reload-timer interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Reset None interrupt request on PWM reload-timer + ** \retval Set Detection interrupt request on PWM reload-timer + ** + ******************************************************************************/ +en_flag_status_t TIMER4_PWM_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + uint16_t u16Flag = 0u; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + + switch (enCh) + { + case Timer4PwmU: + u16Flag = pstcRCSR_f->RTIFU; + break; + case Timer4PwmV: + u16Flag = pstcRCSR_f->RTIFV; + break; + case Timer4PwmW: + u16Flag = pstcRCSR_f->RTIFW; + break; + default: + break; + } + + return (en_flag_status_t)u16Flag; +} + +/** + ******************************************************************************* + ** \brief Clear PWM reload-timer interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok PWM reload-timer interrupt flag is clear + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + enRet = Ok; + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTICU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTICV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTICW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write timer count cycle + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] u16PDAR PDAR value + ** \arg 0~65535 + ** \param [in] u16PDBR PDBR value + ** \arg 0~65535 + ** + ** \retval Ok Timer count cycle is written + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_WriteDeadRegionValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t u16PDAR, + uint16_t u16PDBR) +{ + __IO uint16_t *pu16PDAR = NULL; + __IO uint16_t *pu16PDBR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + pu16PDAR = (__IO uint16_t *)TMR4_PDARx(TMR4x, enCh); + pu16PDBR = (__IO uint16_t *)TMR4_PDBRx(TMR4x, enCh); + + /* set the register */ + *pu16PDAR = u16PDAR; + *pu16PDBR = u16PDBR; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read dead region count value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [out] u16PDAR Pointer of uint16_t type + ** \arg 0~65535 + ** \param [out] u16PDBR Pointer of uint16_t type + ** \arg 0~65535 + ** + ** \retval Ok Read successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_ReadDeadRegionValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t *u16PDAR, + uint16_t *u16PDBR) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + *u16PDAR = *(__IO uint16_t *)TMR4_PDARx(TMR4x, enCh); + *u16PDBR = *(__IO uint16_t *)TMR4_PDBRx(TMR4x, enCh); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set cycle of PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] u16Count PWM pulse counter value + ** \arg 0~65535 + ** + ** \retval Ok Cycle of PWM timer is set + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_SetFilterCountValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t u16Count) +{ + __IO uint16_t *pu16PFSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + pu16PFSR = (__IO uint16_t*)TMR4_PFSRx(TMR4x, enCh); + *pu16PFSR =u16Count; + + enRet = Ok; + } + + return enRet; +} + +//@} // Timer4PwmGroup + +#endif /* DDL_TIMER4_PWM_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_timer4_sevt.c b/driver/src/hc32f460_timer4_sevt.c new file mode 100644 index 0000000..e2724a2 --- /dev/null +++ b/driver/src/hc32f460_timer4_sevt.c @@ -0,0 +1,593 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_sevt.c + ** + ** A detailed description is available at + ** @link Timer4SevtGroup Timer4SEVT description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4SEVT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_sevt.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_SEVT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4SevtGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for SEVT channel */ +#define IS_VALID_SEVT_CH(x) \ +( (Timer4SevtCh0 == (x)) || \ + (Timer4SevtCh1 == (x)) || \ + (Timer4SevtCh2 == (x)) || \ + (Timer4SevtCh3 == (x)) || \ + (Timer4SevtCh4 == (x)) || \ + (Timer4SevtCh5 == (x))) + +/*!< Parameter validity check for adct buffer mode */ +#define IS_VALID_SEVT_BUF_MODE(x) \ +( (SevtBufDisable == (x)) || \ + (SevtBufCntZero == (x)) || \ + (SevtBufCntPeak == (x)) || \ + (SevtBufCntZeroOrCntPeak == (x)) || \ + (SevtBufCntZeroZicZero == (x)) || \ + (SevtBufCntPeakPicZero == (x)) || \ + (SevtBufCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for SEVT trigger event */ +#define IS_VALID_SEVT_TRG_EVT(x) \ +( (SevtTrgEvtSCMUH == (x)) || \ + (SevtTrgEvtSCMUL == (x)) || \ + (SevtTrgEvtSCMVH == (x)) || \ + (SevtTrgEvtSCMVL == (x)) || \ + (SevtTrgEvtSCMWH == (x)) || \ + (SevtTrgEvtSCMWL == (x))) + +/*!< Parameter validity check for SEVT OCCR selection */ +#define IS_VALID_SEVT_OCCR_SEL(x) \ +( (SevtSelOCCRxh == (x)) || \ + (SevtSelOCCRxl == (x))) + +/*!< Parameter validity check for SEVT running mode */ +#define IS_VALID_SEVT_MODE(x) \ +( (SevtDelayTrigMode == (x)) || \ + (SevtCompareTrigMode == (x))) + +/*!< Parameter validity check for SEVT mask time */ +#define IS_VALID_SEVT_MSK(x) \ +( (Timer4SevtMask0 == (x)) || \ + (Timer4SevtMask1 == (x)) || \ + (Timer4SevtMask2 == (x)) || \ + (Timer4SevtMask3 == (x)) || \ + (Timer4SevtMask4 == (x)) || \ + (Timer4SevtMask5 == (x)) || \ + (Timer4SevtMask6 == (x)) || \ + (Timer4SevtMask7 == (x)) || \ + (Timer4SevtMask8 == (x)) || \ + (Timer4SevtMask9 == (x)) || \ + (Timer4SevtMask10 == (x)) || \ + (Timer4SevtMask11 == (x)) || \ + (Timer4SevtMask12 == (x)) || \ + (Timer4SevtMask13 == (x)) || \ + (Timer4SevtMask14 == (x)) || \ + (Timer4SevtMask15 == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_SCCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCCRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_SCSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCSRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_SCMRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCMRUH + ((uint32_t)(__CH__))*4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize a Special-Event channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] pstcInitCfg The pointer of SEVT configure structure + ** \arg This parameter detail refer @ref stc_timer4_sevt_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + const stc_timer4_sevt_init_t *pstcInitCfg) +{ + __IO uint16_t *pu16SCCR = NULL; + __IO stc_tmr4_scsr_field_t stcSCSR_f; + __IO stc_tmr4_scmr_field_t stcSCMR_f; + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_MODE(pstcInitCfg->enMode)); + DDL_ASSERT(IS_VALID_SEVT_BUF_MODE(pstcInitCfg->enBuf)); + DDL_ASSERT(IS_VALID_SEVT_MSK(pstcInitCfg->enMaskTimes)); + DDL_ASSERT(IS_VALID_SEVT_TRG_EVT(pstcInitCfg->enTrigEvt)); + DDL_ASSERT(IS_VALID_SEVT_OCCR_SEL(pstcInitCfg->enOccrSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpAmcZicCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpAmcPicCmd)); + + enRet = Ok; + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + /* Configure default parameter */ + *pu16SCCR = (uint16_t)0u; + *(__IO uint16_t*)pstcSCSR_f = (uint16_t)0x0000u; + *(__IO uint16_t*)pstcSCMR_f = (uint16_t)0xFF00u; + + switch (pstcInitCfg->enBuf) + { + case SevtBufDisable: + stcSCSR_f.BUFEN = (uint16_t)0u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZero: + stcSCSR_f.BUFEN = (uint16_t)1u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntPeak: + stcSCSR_f.BUFEN = (uint16_t)2u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZeroOrCntPeak: + stcSCSR_f.BUFEN = (uint16_t)3u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZeroZicZero: + stcSCSR_f.BUFEN = (uint16_t)1u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + case SevtBufCntPeakPicZero: + stcSCSR_f.BUFEN = (uint16_t)2u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + case SevtBufCntZeroZicZeroOrCntPeakPicZero: + stcSCSR_f.BUFEN = (uint16_t)3u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (Ok == enRet) + { + /* Configure start trigger output channel number */ + stcSCSR_f.EVTOS = (uint16_t)(pstcInitCfg->enTrigEvt); + + /* Select SEVT running mode */ + stcSCSR_f.EVTMS = (uint16_t)(pstcInitCfg->enMode); + + /* select OCO OCCR register: OCCR(x) */ + stcSCSR_f.EVTDS = (uint16_t)(pstcInitCfg->enOccrSel); + + /* Set the comparison with CNT interrupt mask counter */ + stcSCMR_f.AMC = (uint16_t)(pstcInitCfg->enMaskTimes); + stcSCMR_f.MZCE = (uint16_t)(pstcInitCfg->enCmpAmcZicCmd); + stcSCMR_f.MPCE = (uint16_t)(pstcInitCfg->enCmpAmcPicCmd); + + *pstcSCSR_f = stcSCSR_f; + *pstcSCMR_f = stcSCMR_f; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize a SEVT channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO uint16_t *pu16SCCR = NULL; + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + /* Configure default parameter */ + *pu16SCCR = 0u; + *(__IO uint16_t*)pstcSCSR_f = (uint16_t)0x0000u; + *(__IO uint16_t*)pstcSCMR_f = (uint16_t)0xFF00u; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger event. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] enTrgEvt Timer4 Special-EVT Event + ** \arg SevtTrgEvtSCMUH Timer4 Special-EVT Event: TMR4_Ux_SCMUH + ** \arg SevtTrgEvtSCMUL Timer4 Special-EVT Event: TMR4_Ux_SCMUL + ** \arg SevtTrgEvtSCMVH Timer4 Special-EVT Event: TMR4_Ux_SCMVH + ** \arg SevtTrgEvtSCMVL Timer4 Special-EVT Event: TMR4_Ux_SCMVL + ** \arg SevtTrgEvtSCMWH Timer4 Special-EVT Event: TMR4_Ux_SCMWH + ** \arg SevtTrgEvtSCMWL Timer4 Special-EVT Event: TMR4_Ux_SCMWL + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetTriggerEvent(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + en_timer4_sevt_trigger_evt_t enTrgEvt) +{ + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_TRG_EVT(enTrgEvt)); + + /* Get actual address of register list of current channel */ + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCSR_f->EVTOS = (uint16_t)(enTrgEvt); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger condition. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] pstcTrigCond The pointer of SEVT trigger condition structure + ** \arg This parameter detail refer @ref stc_timer4_sevt_trigger_cond_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetTriggerCond(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + const stc_timer4_sevt_trigger_cond_t *pstcTrigCond) +{ + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enUpMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enZeroMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enDownMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enPeakMatchCmd)); + + /* Get actual address of register list of current channel */ + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCSR_f->PEN = (uint16_t)(pstcTrigCond->enPeakMatchCmd); + pstcSCSR_f->ZEN = (uint16_t)(pstcTrigCond->enZeroMatchCmd); + pstcSCSR_f->UEN = (uint16_t)(pstcTrigCond->enUpMatchCmd); + pstcSCSR_f->DEN = (uint16_t)(pstcTrigCond->enDownMatchCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write compare or delay value to Timer4 SEVT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] u16SccrVal Timer4 SEVT compare value + ** + ** \retval Ok Compare or delay value to Timer4 SEVT is set + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_WriteSCCR(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + uint16_t u16SccrVal) +{ + __IO uint16_t *pu16SCCR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + *pu16SCCR = u16SccrVal; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read compare value or delay value of ATVR + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Value of register SCCR + ** + ******************************************************************************/ +uint16_t TIMER4_SEVT_ReadSCCR(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO uint16_t *pu16SCCR = NULL; + + /* check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + + return *pu16SCCR; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger event. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] enMaskTimes Timer4 Special-EVT event mask times + ** \arg Timer4SevtMask0 Mask 0 time. + ** \arg Timer4SevtMask1 Mask 1 times. + ** \arg Timer4SevtMask2 Mask 2 times. + ** \arg Timer4SevtMask3 Mask 3 times. + ** \arg Timer4SevtMask4 Mask 4 times. + ** \arg Timer4SevtMask5 Mask 5 times. + ** \arg Timer4SevtMask6 Mask 6 times. + ** \arg Timer4SevtMask7 Mask 7 times. + ** \arg Timer4SevtMask8 Mask 8 times. + ** \arg Timer4SevtMask9 Mask 9 times. + ** \arg Timer4SevtMask10 Mask 10 times + ** \arg Timer4SevtMask11 Mask 11 times + ** \arg Timer4SevtMask12 Mask 12 times + ** \arg Timer4SevtMask13 Mask 13 times + ** \arg Timer4SevtMask14 Mask 14 times + ** \arg Timer4SevtMask15 Mask 15 times + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + en_timer4_sevt_mask_t enMaskTimes) +{ + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_MSK(enMaskTimes)); + + /* Get actual address of register list of current channel */ + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + pstcSCMR_f->AMC = (uint16_t)(enMaskTimes); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 SEVT mask count. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Timer4SevtMask0 Mask 0 time. + ** \retval Timer4SevtMask1 Mask 1 times. + ** \retval Timer4SevtMask2 Mask 2 times. + ** \retval Timer4SevtMask3 Mask 3 times. + ** \retval Timer4SevtMask4 Mask 4 times. + ** \retval Timer4SevtMask5 Mask 5 times. + ** \retval Timer4SevtMask6 Mask 6 times. + ** \retval Timer4SevtMask7 Mask 7 times. + ** \retval Timer4SevtMask8 Mask 8 times. + ** \retval Timer4SevtMask9 Mask 9 times. + ** \retval Timer4SevtMask10 Mask 10 times + ** \retval Timer4SevtMask11 Mask 11 times + ** \retval Timer4SevtMask12 Mask 12 times + ** \retval Timer4SevtMask13 Mask 13 times + ** \retval Timer4SevtMask14 Mask 14 times + ** \retval Timer4SevtMask15 Mask 15 times + ** + ******************************************************************************/ +en_timer4_sevt_mask_t TIMER4_SEVT_GetMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + return (en_timer4_sevt_mask_t)pstcSCMR_f->AMC; +} + +//@} // Timer4SevtGroup + +#endif /* DDL_TIMER4_SEVT_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_timer6.c b/driver/src/hc32f460_timer6.c new file mode 100644 index 0000000..461c25b --- /dev/null +++ b/driver/src/hc32f460_timer6.c @@ -0,0 +1,1786 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer6.c + ** + ** A detailed description is available at + ** @link Timer6Group Timer6 description @endlink + ** + ** - 2018-11-23 CDT First version for Device Driver Library of Timer6. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer6.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER6_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer6Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for normal timer6 unit */ +#define IS_VALID_NORMAL_TIMER6_UNIT(__TMR6x__) \ +( (M4_TMR61 == (__TMR6x__)) || \ + (M4_TMR62 == (__TMR6x__)) || \ + (M4_TMR63 == (__TMR6x__))) + +/*!< Parameter valid check for period register*/ +#define IS_VALID_PERIOD_TYPE(x) \ +( (Timer6PeriodA == (x)) || \ + (Timer6PeriodB == (x)) || \ + (Timer6PeriodC == (x))) +/*!< Parameter valid check for General compare register*/ +#define IS_VALID_GEN_CMP_TYPE(x) \ +( (Timer6GenCompareA == (x)) || \ + (Timer6GenCompareB == (x)) || \ + (Timer6GenCompareC == (x)) || \ + (Timer6GenCompareD == (x)) || \ + (Timer6GenCompareE == (x)) || \ + (Timer6GenCompareF == (x))) + +/*!< Parameter valid check for Special compare register*/ +#define IS_VALID_SPECIAL_CMP_TYPE(x) \ +( (Timer6SpclCompA == (x)) || \ + (Timer6SpclCompB == (x)) || \ + (Timer6SpclCompC == (x)) || \ + (Timer6SpclCompD == (x)) || \ + (Timer6SpclCompE == (x)) || \ + (Timer6SpclCompF == (x))) +/*!< Parameter valid check for Count clock division */ +#define IS_VALID_COUNT_CLK_DIV(x) \ +( (Timer6PclkDiv1 == (x)) || \ + (Timer6PclkDiv2 == (x)) || \ + (Timer6PclkDiv4 == (x)) || \ + (Timer6PclkDiv8 == (x)) || \ + (Timer6PclkDiv16 == (x)) || \ + (Timer6PclkDiv64 == (x)) || \ + (Timer6PclkDiv256 == (x)) || \ + (Timer6PclkDiv1024 == (x))) + +/*!< Parameter valid check for count mode */ +#define IS_VALID_COUNT_MODE(x) \ +( (Timer6CntSawtoothMode == (x)) || \ + (Timer6CntTriangularModeA == (x)) || \ + (Timer6CntTriangularModeB == (x))) + +/*!< Parameter valid check for count direction */ +#define IS_VALID_COUNT_DIR(x) \ +( (Timer6CntDirDown == (x)) || \ + (Timer6CntDirUp == (x))) + +/*!< Parameter valid check for timer6 output port */ +#define IS_VALID_TIMER6_OUTPUT_PORT(x) \ +( (Timer6PWMA == (x)) || \ + (Timer6PWMB == (x))) + +/*!< Parameter valid check for timer6 input port */ +#define IS_VALID_TIMER6_INPUT_PORT(x) \ +( (Timer6PWMA == (x)) || \ + (Timer6PWMB == (x)) || \ + (Timer6TrigA == (x)) || \ + (Timer6TrigB == (x))) + +/*!< Parameter valid check for start/stop count output status */ +#define IS_VALID_STA_STP_OUTPUT_STATUS(x) \ +( (Timer6PWMxPortOutLow == (x)) || \ + (Timer6PWMxPortOutHigh == (x))) + +/*!< Parameter valid check for match output status */ +#define IS_VALID_MATCH_OUTPUT_STATUS(x) \ +( (Timer6PWMxCompareLow == (x)) || \ + (Timer6PWMxCompareHigh == (x)) || \ + (Timer6PWMxCompareKeep == (x)) || \ + (Timer6PWMxCompareInv == (x))) + +/*!< Parameter valid check for match output status */ +#define IS_VALID_MATCH_OUTPUT_STATUS(x) \ +( (Timer6PWMxCompareLow == (x)) || \ + (Timer6PWMxCompareHigh == (x)) || \ + (Timer6PWMxCompareKeep == (x)) || \ + (Timer6PWMxCompareInv == (x))) + +/*!< Parameter valid check for port filter clock */ +#define IS_VALID_PORT_FILTER_CLOCK(x) \ +( (Timer6FltClkPclk0Div1 == (x)) || \ + (Timer6FltClkPclk0Div4 == (x)) || \ + (Timer6FltClkPclk0Div16 == (x)) || \ + (Timer6FltClkPclk0Div64 == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_VPERR_PCNT_NUM(x) \ +( (Timer6PeriodCnts0 == (x)) || \ + (Timer6PeriodCnts1 == (x)) || \ + (Timer6PeriodCnts2 == (x)) || \ + (Timer6PeriodCnts3 == (x)) || \ + (Timer6PeriodCnts4 == (x)) || \ + (Timer6PeriodCnts5 == (x)) || \ + (Timer6PeriodCnts6 == (x)) || \ + (Timer6PeriodCnts7 == (x))) +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_VPERR_PCNT_EN_SOURCE(x) \ +( (Timer6PeriodCnteDisable == (x)) || \ + (Timer6PeriodCnteMin == (x)) || \ + (Timer6PeriodCnteMax == (x)) || \ + (Timer6PeriodCnteBoth == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_IRQ_SOURCE(x) \ +( (Timer6INTENA == (x)) || \ + (Timer6INTENB == (x)) || \ + (Timer6INTENC == (x)) || \ + (Timer6INTEND == (x)) || \ + (Timer6INTENE == (x)) || \ + (Timer6INTENF == (x)) || \ + (Timer6INTENOVF == (x)) || \ + (Timer6INTENUDF == (x)) || \ + (Timer6INTENDTE == (x)) || \ + (Timer6INTENSAU == (x)) || \ + (Timer6INTENSAD == (x)) || \ + (Timer6INTENSBU == (x)) || \ + (Timer6INTENSBD == (x))) + +/*!< Parameter valid check for status type */ +#define IS_VALID_STATUS_TYPE(x) \ +( (Timer6CMAF == (x)) || \ + (Timer6CMBF == (x)) || \ + (Timer6CMCF == (x)) || \ + (Timer6CMDF == (x)) || \ + (Timer6CMEF == (x)) || \ + (Timer6CMFF == (x)) || \ + (Timer6OVFF == (x)) || \ + (Timer6UDFF == (x)) || \ + (Timer6DTEF == (x)) || \ + (Timer6CMSAUF == (x)) || \ + (Timer6CMSADF == (x)) || \ + (Timer6CMSBUF == (x)) || \ + (Timer6CMSBDF == (x)) || \ + (Timer6VPERNUM == (x)) || \ + (Timer6DIRF == (x))) + +/*!< Parameter valid check for hardware up count/down count event type */ +#define IS_VALID_HW_COUNT_TYPE(x) \ +( (Timer6HwCntPWMALowPWMBRise == (x)) || \ + (Timer6HwCntPWMALowPWMBFall == (x)) || \ + (Timer6HwCntPWMAHighPWMBRise == (x)) || \ + (Timer6HwCntPWMAHighPWMBFall == (x)) || \ + (Timer6HwCntPWMBLowPWMARise == (x)) || \ + (Timer6HwCntPWMBLowPWMAFall == (x)) || \ + (Timer6HwCntPWMBHighPWMARise == (x)) || \ + (Timer6HwCntPWMBHighPWMAFall == (x)) || \ + (Timer6HwCntTRIGARise == (x)) || \ + (Timer6HwCntTRIGAFall == (x)) || \ + (Timer6HwCntTRIGBRise == (x)) || \ + (Timer6HwCntTRIGBFall == (x)) || \ + (Timer6HwCntAos0 == (x)) || \ + (Timer6HwCntAos1 == (x))) + +/*!< Parameter valid check for hardware up start/stop/clear/capture event type */ +#define IS_VALID_HW_STA_STP_CLR_CAP_TYPE(x) \ +( (Timer6HwTrigAos0 == (x)) || \ + (Timer6HwTrigAos1 == (x)) || \ + (Timer6HwTrigPWMARise == (x)) || \ + (Timer6HwTrigPWMAFall == (x)) || \ + (Timer6HwTrigPWMBRise == (x)) || \ + (Timer6HwTrigPWMBFall == (x)) || \ + (Timer6HwTrigTimTriARise == (x)) || \ + (Timer6HwTrigTimTriAFall == (x)) || \ + (Timer6HwTrigTimTriBRise == (x)) || \ + (Timer6HwTrigTimTriBFall == (x)) || \ + (Timer6HwTrigEnd == (x))) + +/*!< Parameter valid check for timer6 input port type */ +#define IS_VALID_INPUT_PORT_TYPE(x) \ +( (Timer6xCHA == (x)) || \ + (Timer6xCHB == (x)) || \ + (Timer6TrigA == (x)) || \ + (Timer6TrigB == (x))) + +/*!< Parameter valid check for GenCMP and period register buffer transfer type*/ +#define IS_VALID_GCMP_PRD_BUF_TYPE(x) \ +( (Timer6GcmpPrdSingleBuf == (x)) || \ + (Timer6GcmpPrdDoubleBuf == (x))) + +/*!< Parameter valid check for special compare register buffer transfer type */ +#define IS_VALID_SPCL_BUF_TYPE(x) \ +( (Timer6SpclSingleBuf == (x)) || \ + (Timer6SpclDoubleBuf == (x))) + +/*!< Parameter valid check for spcl register transfer opportunity type */ +#define IS_VALID_SPCL_TRANS_OPT_TYPE(x) \ +( (Timer6SplcOptNone == (x)) || \ + (Timer6SplcOptOverFlow == (x)) || \ + (Timer6SplcOptUnderFlow == (x)) || \ + (Timer6SplcOptBoth == (x))) + +/*!< Parameter valid check for dead time register type */ +#define IS_VALID_DEAD_TIME_TYPE(x) \ +( (Timer6DeadTimUpAR == (x)) || \ + (Timer6DeadTimUpBR == (x)) || \ + (Timer6DeadTimDwnAR == (x)) || \ + (Timer6DeadTimDwnBR == (x))) + +/*!< Parameter valid check for Z Phase input mask periods */ +#define IS_VALID_ZPHASE_MASK_PRD(x) \ +( (Timer6ZMaskDis == (x)) || \ + (Timer6ZMask4Cyl == (x)) || \ + (Timer6ZMask8Cyl == (x)) || \ + (Tiemr6ZMask16Cyl == (x))) + +/*!< Parameter valid check for event source */ +#define IS_VALID_EVENT_SOURCE(x) ((x) <= 511) + +/*!< Parameter validity check for common trigger. */ +#define IS_VALID_TIMER6_COM_TRIGGER(x) \ +( (Timer6ComTrigger_1 == (x)) || \ + (Timer6ComTrigger_2 == (x)) || \ + (Timer6ComTrigger_1_2 == (x))) + +/*! TimerA registers reset value */ +#define TIMERA_REG_CNTER_RESET_VALUE (0x0000u) +#define TIMERA_REG_GCONR_RESET_VALUE (0x00000100ul) +#define TIMERA_REG_ICONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_PCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_BCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_DCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_FCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_VPERR_RESET_VALUE (0x00000000ul) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/******************************************************************************* + * \brief Timer6 interrupt request enable or disable + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Irq Irq type + * \param [in] bEn true/false + * + * \retval Ok: config successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigIrq(M4_TMR6_TypeDef *TMR6x, en_timer6_irq_type_t enTimer6Irq, bool bEn) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_IRQ_SOURCE(enTimer6Irq)); + + switch (enTimer6Irq) + { + case Timer6INTENA: + TMR6x->ICONR_f.INTENA = bEn; + break; + case Timer6INTENB: + TMR6x->ICONR_f.INTENB = bEn; + break; + case Timer6INTENC: + TMR6x->ICONR_f.INTENC = bEn; + break; + case Timer6INTEND: + TMR6x->ICONR_f.INTEND = bEn; + break; + case Timer6INTENE: + TMR6x->ICONR_f.INTENE = bEn; + break; + case Timer6INTENF: + TMR6x->ICONR_f.INTENF = bEn; + break; + case Timer6INTENOVF: + TMR6x->ICONR_f.INTENOVF = bEn; + break; + case Timer6INTENUDF: + TMR6x->ICONR_f.INTENUDF = bEn; + break; + case Timer6INTENDTE: + TMR6x->ICONR_f.INTENDTE = bEn; + break; + case Timer6INTENSAU: + TMR6x->ICONR_f.INTENSAU = bEn; + break; + case Timer6INTENSAD: + TMR6x->ICONR_f.INTENSAD = bEn; + break; + case Timer6INTENSBU: + TMR6x->ICONR_f.INTENSBU = bEn; + break; + case Timer6INTENSBD: + TMR6x->ICONR_f.INTENSBD = bEn; + break; + default: + break; + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get Timer6 status flag + ** + ** \param [in] TMR6x Timer6 unit + ** + ** \param [in] enStatus Timer6 status type + ** + ** \retval Timer6 status + ** + ******************************************************************************/ +uint8_t Timer6_GetStatus(M4_TMR6_TypeDef *TMR6x, en_timer6_status_t enStatus) +{ + uint8_t status = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_STATUS_TYPE(enStatus)); + + switch (enStatus) + { + case Timer6CMAF: + status = (uint8_t)TMR6x->STFLR_f.CMAF; + break; + case Timer6CMBF: + status = (uint8_t)TMR6x->STFLR_f.CMBF; + break; + case Timer6CMCF: + status = (uint8_t)TMR6x->STFLR_f.CMCF; + break; + case Timer6CMDF: + status = (uint8_t)TMR6x->STFLR_f.CMDF; + break; + case Timer6CMEF: + status = (uint8_t)TMR6x->STFLR_f.CMEF; + break; + case Timer6CMFF: + status = (uint8_t)TMR6x->STFLR_f.CMFF; + break; + case Timer6OVFF: + status = (uint8_t)TMR6x->STFLR_f.OVFF; + break; + case Timer6UDFF: + status = (uint8_t)TMR6x->STFLR_f.UDFF; + break; + case Timer6DTEF: + status = (uint8_t)TMR6x->STFLR_f.DTEF; + break; + case Timer6CMSAUF: + status = (uint8_t)TMR6x->STFLR_f.CMSAUF; + break; + case Timer6CMSADF: + status = (uint8_t)TMR6x->STFLR_f.CMSADF; + break; + case Timer6CMSBUF: + status = (uint8_t)TMR6x->STFLR_f.CMSBUF; + break; + case Timer6CMSBDF: + status = (uint8_t)TMR6x->STFLR_f.CMSBDF; + break; + case Timer6VPERNUM: + status = (uint8_t)TMR6x->STFLR_f.VPERNUM; + break; + case Timer6DIRF: + status = (uint8_t)TMR6x->STFLR_f.DIRF; + break; + default: + break; + } + + return status; +} + + + +/** + ******************************************************************************* + ** \brief De-Initialize Timer6 unit + ** + ** \param [in] TMR6x Timer6 unit + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_DeInit(M4_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER = TIMERA_REG_CNTER_RESET_VALUE; + TMR6x->GCONR = TIMERA_REG_GCONR_RESET_VALUE; + TMR6x->PCONR = TIMERA_REG_PCONR_RESET_VALUE; + TMR6x->ICONR = TIMERA_REG_ICONR_RESET_VALUE; + TMR6x->BCONR = TIMERA_REG_BCONR_RESET_VALUE; + TMR6x->DCONR = TIMERA_REG_DCONR_RESET_VALUE; + TMR6x->FCONR = TIMERA_REG_FCONR_RESET_VALUE; + TMR6x->VPERR = TIMERA_REG_VPERR_RESET_VALUE; + TMR6x->HSTAR = 0x00000000ul; + TMR6x->HSTPR = 0x00000000ul; + TMR6x->HCLRR = 0x00000000ul; + TMR6x->HCPAR = 0x00000000ul; + TMR6x->HCPBR = 0x00000000ul; + TMR6x->HCUPR = 0x00000000ul; + TMR6x->HCDOR = 0x00000000ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Base Config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6BaseCntCfg Bsee Config Pointer + * + * \retval Ok: Config Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_Init(M4_TMR6_TypeDef *TMR6x, const stc_timer6_basecnt_cfg_t* pstcTimer6BaseCntCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6BaseCntCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_COUNT_MODE(pstcTimer6BaseCntCfg->enCntMode)); + DDL_ASSERT(IS_VALID_COUNT_DIR(pstcTimer6BaseCntCfg->enCntDir)); + DDL_ASSERT(IS_VALID_COUNT_CLK_DIV(pstcTimer6BaseCntCfg->enCntClkDiv)); + + + TMR6x->GCONR_f.MODE = pstcTimer6BaseCntCfg->enCntMode; + TMR6x->GCONR_f.DIR = pstcTimer6BaseCntCfg->enCntDir; + TMR6x->GCONR_f.CKDIV = pstcTimer6BaseCntCfg->enCntClkDiv; + } + return enRet; +} + +/******************************************************************************* + * \brief Timer6 Unit Start Count + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_StartCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->GCONR_f.START = 1ul; + + return Ok; +} + +/******************************************************************************* + * \brief TImer6 Unit Stop Count + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_StopCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->GCONR_f.START = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Unit Set Count Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] u16Value Count Value + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_SetCount(M4_TMR6_TypeDef *TMR6x, uint16_t u16Value) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER_f.CNT = u16Value; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Unit Get Count Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] u16Value Count Value + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +uint16_t Timer6_GetCount(M4_TMR6_TypeDef *TMR6x) +{ + uint16_t u16Value; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u16Value = (uint16_t)TMR6x->CNTER_f.CNT; + + return u16Value; +} + +/******************************************************************************* + * \brief Timer6 Unit Clear Count Value + * + * + * \param [in] TMR6x Timer6 unit + * + * + * \retval Ok: Set Successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER_f.CNT = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 unit set count period and buffer value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Periodx Period register name + * \param [in] u16Period Count period value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetPeriod(M4_TMR6_TypeDef *TMR6x, en_timer6_period_t enTimer6Periodx, uint16_t u16Period) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_TYPE(enTimer6Periodx)); + + switch (enTimer6Periodx) + { + case Timer6PeriodA: + TMR6x->PERAR = u16Period; + break; + case Timer6PeriodB: + TMR6x->PERBR = u16Period; + break; + case Timer6PeriodC: + TMR6x->PERCR = u16Period; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 unit Set General Compare Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Compare General Compare Register name + * \param [in] u16Compare General Compare Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare, uint16_t u16Compare) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GEN_CMP_TYPE(enTimer6Compare)); + + switch (enTimer6Compare) + { + case Timer6GenCompareA: + TMR6x->GCMAR = u16Compare; + break; + case Timer6GenCompareB: + TMR6x->GCMBR = u16Compare; + break; + case Timer6GenCompareC: + TMR6x->GCMCR = u16Compare; + break; + case Timer6GenCompareD: + TMR6x->GCMDR = u16Compare; + break; + case Timer6GenCompareE: + TMR6x->GCMER = u16Compare; + break; + case Timer6GenCompareF: + TMR6x->GCMFR = u16Compare; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 unit Set Special Compare Register Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6SpclCmp General Compare Register name + * \param [in] u16SpclCmp General Compare Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetSpecialCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_special_compare_t enTimer6SpclCmp, uint16_t u16SpclCmp) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_SPECIAL_CMP_TYPE(enTimer6SpclCmp)); + + switch (enTimer6SpclCmp) + { + case Timer6SpclCompA: + TMR6x->SCMAR = u16SpclCmp; + break; + case Timer6SpclCompB: + TMR6x->SCMBR = u16SpclCmp; + break; + case Timer6SpclCompC: + TMR6x->SCMCR = u16SpclCmp; + break; + case Timer6SpclCompD: + TMR6x->SCMDR = u16SpclCmp; + break; + case Timer6SpclCompE: + TMR6x->SCMER = u16SpclCmp; + break; + case Timer6SpclCompF: + TMR6x->SCMFR = u16SpclCmp; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config general compare buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6PWMPort PWM channel of timer6 + * \param [in] pstcTimer6GenBufCfg General Compare Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetGeneralBuf(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_gcmp_buf_cfg_t* pstcTimer6GenBufCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_TIMER6_OUTPUT_PORT(enTimer6PWMPort)); + DDL_ASSERT(IS_VALID_GCMP_PRD_BUF_TYPE(pstcTimer6GenBufCfg->enGcmpBufTransType)); + + switch (enTimer6PWMPort) + { + case Timer6PWMA: + TMR6x->BCONR_f.BENA = pstcTimer6GenBufCfg->bEnGcmpTransBuf; + TMR6x->BCONR_f.BSEA = pstcTimer6GenBufCfg->enGcmpBufTransType; + break; + case Timer6PWMB: + TMR6x->BCONR_f.BENB = pstcTimer6GenBufCfg->bEnGcmpTransBuf; + TMR6x->BCONR_f.BSEB = pstcTimer6GenBufCfg->enGcmpBufTransType; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config special compare buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6SpclCmp Special Compare Register nameunit + * \param [in] pstcTimer6SpclBufCfg Special Compare Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetSpecialBuf(M4_TMR6_TypeDef *TMR6x,en_timer6_special_compare_t enTimer6SpclCmp, const stc_timer6_spcl_buf_cfg_t* pstcTimer6SpclBufCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_SPECIAL_CMP_TYPE(enTimer6SpclCmp)); + DDL_ASSERT(IS_VALID_SPCL_BUF_TYPE(pstcTimer6SpclBufCfg->enSpclBufTransType)); + DDL_ASSERT(IS_VALID_SPCL_TRANS_OPT_TYPE(pstcTimer6SpclBufCfg->enSpclBufOptType)); + + switch (enTimer6SpclCmp) + { + case Timer6SpclCompA: + TMR6x->BCONR_f.BENSPA = pstcTimer6SpclBufCfg->bEnSpclTransBuf; + TMR6x->BCONR_f.BSESPA = pstcTimer6SpclBufCfg->enSpclBufTransType; + TMR6x->BCONR_f.BTRSPA = pstcTimer6SpclBufCfg->enSpclBufOptType; + break; + case Timer6SpclCompB: + TMR6x->BCONR_f.BENSPB = pstcTimer6SpclBufCfg->bEnSpclTransBuf; + TMR6x->BCONR_f.BSESPB = pstcTimer6SpclBufCfg->enSpclBufTransType; + TMR6x->BCONR_f.BTRSPB = pstcTimer6SpclBufCfg->enSpclBufOptType; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config period buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6PrdBufCfg Period Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * + ******************************************************************************/ +en_result_t Timer6_SetPeriodBuf(M4_TMR6_TypeDef *TMR6x, const stc_timer6_period_buf_cfg_t* pstcTimer6PrdBufCfg) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GCMP_PRD_BUF_TYPE(pstcTimer6PrdBufCfg->enPeriodBufTransType)); + + TMR6x->BCONR_f.BENP = pstcTimer6PrdBufCfg->bEnPeriodTransBuf; + TMR6x->BCONR_f.BSEP = pstcTimer6PrdBufCfg->enPeriodBufTransType; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 unit get General Compare Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Compare General Compare Register name + * + * + * \retval u16TempValue: General Compare Register value + * + ******************************************************************************/ +uint16_t Timer6_GetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare) +{ + uint16_t u16TempValue = 0u; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GEN_CMP_TYPE(enTimer6Compare)); + + switch (enTimer6Compare) + { + case Timer6GenCompareA: + u16TempValue = (uint16_t)TMR6x->GCMAR; + break; + case Timer6GenCompareB: + u16TempValue = (uint16_t)TMR6x->GCMBR; + break; + case Timer6GenCompareC: + u16TempValue = (uint16_t)TMR6x->GCMCR; + break; + case Timer6GenCompareD: + u16TempValue = (uint16_t)TMR6x->GCMDR; + break; + case Timer6GenCompareE: + u16TempValue = (uint16_t)TMR6x->GCMER; + break; + case Timer6GenCompareF: + u16TempValue = (uint16_t)TMR6x->GCMFR; + break; + default: + break; + } + + return u16TempValue; +} + +/*********************************************************************** + * \brief Timer6 Config valid count period + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6ValidPerCfg Valid Count Period Pointer + * + * \retval Ok: Config successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ***********************************************************************/ +en_result_t Timer6_SetValidPeriod(M4_TMR6_TypeDef *TMR6x, const stc_timer6_validper_cfg_t* pstcTimer6ValidPerCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6ValidPerCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_VPERR_PCNT_EN_SOURCE(pstcTimer6ValidPerCfg->enValidCdtEn)); + DDL_ASSERT(IS_VALID_VPERR_PCNT_NUM(pstcTimer6ValidPerCfg->enValidCntNum)); + + TMR6x->VPERR_f.PCNTS = pstcTimer6ValidPerCfg->enValidCntNum; + TMR6x->VPERR_f.PCNTE = pstcTimer6ValidPerCfg->enValidCdtEn; + TMR6x->VPERR_f.SPPERIA = pstcTimer6ValidPerCfg->bPeriodSCMA; + TMR6x->VPERR_f.SPPERIB = pstcTimer6ValidPerCfg->bPeriodSCMB; + } + return enRet; +} + +/******************************************************************************* + * \brief Port input config(Trig) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6PortInputCfg Point Input Config Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, const stc_timer6_port_input_cfg_t* pstcTimer6PortInputCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + if (NULL == pstcTimer6PortInputCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + switch (pstcTimer6PortInputCfg->enPortSel) + { + case Timer6xCHA: + TMR6x->PCONR_f.CAPMDA = pstcTimer6PortInputCfg->enPortMode; + TMR6x->FCONR_f.NOFIENGA = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKGA = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6xCHB: + TMR6x->PCONR_f.CAPMDB = pstcTimer6PortInputCfg->enPortMode; + TMR6x->FCONR_f.NOFIENGB = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKGB = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6TrigA: + TMR6x->FCONR_f.NOFIENTA = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKTA = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6TrigB: + TMR6x->FCONR_f.NOFIENTB = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKTB = pstcTimer6PortInputCfg->enFltClk; + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + } + return enRet; +} + +/******************************************************************************* + * \brief Timer6 Output Port config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6PWMPort Timer6 Port(PWMA/PWMB) + * \param [in] pstcTimer6PortOutCfg timer6 Port Config Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x, + en_timer6_chx_port_t enTimer6PWMPort, + const stc_timer6_port_output_cfg_t* pstcTimer6PortOutCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_TIMER6_OUTPUT_PORT(enTimer6PWMPort)); + + if (NULL == pstcTimer6PortOutCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + switch (enTimer6PWMPort) + { + case Timer6PWMA: + TMR6x->PCONR_f.CAPMDA = pstcTimer6PortOutCfg->enPortMode; + TMR6x->PCONR_f.STACA = pstcTimer6PortOutCfg->enStaOut; + TMR6x->PCONR_f.STPCA = pstcTimer6PortOutCfg->enStpOut; + TMR6x->PCONR_f.STASTPSA = pstcTimer6PortOutCfg->enStaStp; + TMR6x->PCONR_f.CMPCA = pstcTimer6PortOutCfg->enCmpc; + TMR6x->PCONR_f.PERCA = pstcTimer6PortOutCfg->enPerc; + TMR6x->PCONR_f.OUTENA = pstcTimer6PortOutCfg->bOutEn; + TMR6x->PCONR_f.EMBVALA = pstcTimer6PortOutCfg->enDisVal; + break; + + case Timer6PWMB: + TMR6x->PCONR_f.CAPMDB = pstcTimer6PortOutCfg->enPortMode; + TMR6x->PCONR_f.STACB = pstcTimer6PortOutCfg->enStaOut; + TMR6x->PCONR_f.STPCB = pstcTimer6PortOutCfg->enStpOut; + TMR6x->PCONR_f.STASTPSB = pstcTimer6PortOutCfg->enStaStp; + TMR6x->PCONR_f.CMPCB = pstcTimer6PortOutCfg->enCmpc; + TMR6x->PCONR_f.PERCB = pstcTimer6PortOutCfg->enPerc; + TMR6x->PCONR_f.OUTENB = pstcTimer6PortOutCfg->bOutEn; + TMR6x->PCONR_f.EMBVALB = pstcTimer6PortOutCfg->enDisVal; + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + } + return enRet; +} + + +/******************************************************************************* + * \brief Timer6 unit Set DeadTime Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6DTReg DeadTime Register name + * \param [in] u16DTValue DeadTime Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetDeadTimeValue(M4_TMR6_TypeDef *TMR6x, en_timer6_dead_time_reg_t enTimer6DTReg, uint16_t u16DTValue) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEAD_TIME_TYPE(enTimer6DTReg)); + + switch (enTimer6DTReg) + { + case Timer6DeadTimUpAR: + TMR6x->DTUAR = u16DTValue; + break; + case Timer6DeadTimUpBR: + TMR6x->DTUBR = u16DTValue; + break; + case Timer6DeadTimDwnAR: + TMR6x->DTDAR = u16DTValue; + break; + case Timer6DeadTimDwnBR: + TMR6x->DTDBR = u16DTValue; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Config DeadTime function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6DTCfg Timer6 dead time config pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_ConfigDeadTime(M4_TMR6_TypeDef *TMR6x, const stc_timer6_deadtime_cfg_t* pstcTimer6DTCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + if (NULL == pstcTimer6DTCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + TMR6x->DCONR_f.SEPA = pstcTimer6DTCfg->bEnDtEqualUpDwn; + TMR6x->DCONR_f.DTBENU = pstcTimer6DTCfg->bEnDtBufUp; + TMR6x->DCONR_f.DTBEND = pstcTimer6DTCfg->bEnDtBufDwn; + TMR6x->DCONR_f.DTCEN = pstcTimer6DTCfg->bEnDeadtime; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Start + * + * + * \param [in] pstcTimer6SwSyncStart Software Synchrony Start Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncStart(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStart) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncStart) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncStart->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncStart->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncStart->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SSTAR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Stop + * + * + * \param [in] pstcTimer6SwSyncStop Software Synchrony Stop Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncStop(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStop) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncStop) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncStop->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncStop->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncStop->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SSTPR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Clear + * + * + * \param [in] pstcTimer6SwSyncClear Software Synchrony Clear Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncClear(const stc_timer6_sw_sync_t* pstcTimer6SwSyncClear) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncClear) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncClear->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncClear->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncClear->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SCLRR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Get Software Synchrony status + * + * + * \param [in] pstcTimer6SwSyncState Software Synchrony State Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_GetSwSyncState(stc_timer6_sw_sync_t* pstcTimer6SwSyncState) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6SwSyncState) + { + enRet = ErrorInvalidParameter; + } + else + { + if (M4_TMR6_CR->SSTAR & 0x1ul) + { + pstcTimer6SwSyncState->bTimer61 = true; + } + else + { + pstcTimer6SwSyncState->bTimer61 = false; + } + if (M4_TMR6_CR->SSTAR & 0x2ul) + { + pstcTimer6SwSyncState->bTimer62 = true; + } + else + { + pstcTimer6SwSyncState->bTimer62 = false; + } + if (M4_TMR6_CR->SSTAR & 0x4ul) + { + pstcTimer6SwSyncState->bTimer63 = true; + } + else + { + pstcTimer6SwSyncState->bTimer63 = false; + } + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 Hardware UpCount Event config + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCntUp Hardware UpCount Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCntUp(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntUp) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_COUNT_TYPE(enTimer6HwCntUp)); + + u32Val = TMR6x->HCUPR; + TMR6x->HCUPR = u32Val | (1ul << enTimer6HwCntUp); + + return Ok; +} + +/************************************************************** + * \brief Clear Timer6 Hardware UpCount Event + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ************************************************************/ +en_result_t Timer6_ClearHwCntUp(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCUPR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Set Timer6 Hardware DownCount Event + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCntDwn Hardware DownCount Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCntDwn(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntDwn) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_COUNT_TYPE(enTimer6HwCntDwn)); + + u32Val = TMR6x->HCDOR; + TMR6x->HCDOR = u32Val | (1ul << enTimer6HwCntDwn); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Timer6 Hardware DownCount Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCntDwn(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCDOR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwStart Hardware Start Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwStart(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStart) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwStart)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val | (1ul << enTimer6HwStart); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwStart(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HSTAR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwStart(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val | (1ul << 31u); + + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwStart(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwStop Hardware Stop Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwStop(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStop) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwStop)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val | (1ul << enTimer6HwStop); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwStop(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HSTPR = 0ul; + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwStop(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val | (1ul << 31u); + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwStop(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwClear Hardware Clear Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwClear(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwClear) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwClear)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val | (1ul << enTimer6HwClear); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwClear(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCLRR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwClear(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val | (1ul << 31u); + + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwClear(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Capture Event A + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCaptureA Hardware capture event A selection + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCaptureA(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureA) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwCaptureA)); + + u32Val = TMR6x->HCPAR; + TMR6x->HCPAR = u32Val | (1ul << enTimer6HwCaptureA); + //TMR6x->PCONR_f.CAPMDA = 1; + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Capture Event A + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCaptureA(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCPAR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Capture Event B + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCaptureB Hardware capture event B selection + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCaptureB(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureB) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwCaptureB)); + + u32Val = TMR6x->HCPBR; + TMR6x->HCPBR = u32Val | (1ul << enTimer6HwCaptureB); + //TMR6x->PCONR_f.CAPMDB = 1; + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Capture Event B + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCaptureB(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCPBR = 0ul; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set trigger source 0 of hardware event + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement/capture + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_SetTriggerSrc0(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMR6_HTSSR1_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source 1 of hardware event + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement/capture + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_SetTriggerSrc1(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMR6_HTSSR2_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer6 common trigger for hardware trigger register 0 + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_timer6_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER6_ComTriggerCmd0(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIMER6_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR6_HTSSR1 |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR6_HTSSR1 &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer6 common trigger for hardware trigger register 1 + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_timer6_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER6_ComTriggerCmd1(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIMER6_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR6_HTSSR2 |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR6_HTSSR2 &= ~(u32ComTrig << 30u); + } +} + +/******************************************************************************* + * \brief Z phase input mask config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6ZMaskCfg Z phase input mask config pointer + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigZMask(M4_TMR6_TypeDef *TMR6x, const stc_timer6_zmask_cfg_t* pstcTimer6ZMaskCfg) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_ZPHASE_MASK_PRD(pstcTimer6ZMaskCfg->enZMaskCycle)); + + TMR6x->GCONR_f.ZMSKVAL = pstcTimer6ZMaskCfg->enZMaskCycle; + TMR6x->GCONR_f.ZMSKPOS = pstcTimer6ZMaskCfg->bFltPosCntMaksEn; + TMR6x->GCONR_f.ZMSKREV = pstcTimer6ZMaskCfg->bFltRevCntMaksEn; + + return Ok; +} + + +//@} // Timer6Group + +#endif /* DDL_TIMER6_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_timera.c b/driver/src/hc32f460_timera.c new file mode 100644 index 0000000..d458886 --- /dev/null +++ b/driver/src/hc32f460_timera.c @@ -0,0 +1,1972 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timera.c + ** + ** A detailed description is available at + ** @link TimeraGroup Timer A description @endlink + ** + ** - 2018-11-08 CDT First version for Device Driver Library of + ** Timera. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timera.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMERA_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup TimeraGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for normal timera unit */ +#define IS_VALID_NORMAL_TIMERA_UNIT(x) \ +( (M4_TMRA1 == (x)) || \ + (M4_TMRA2 == (x)) || \ + (M4_TMRA3 == (x)) || \ + (M4_TMRA4 == (x)) || \ + (M4_TMRA5 == (x)) || \ + (M4_TMRA6 == (x))) + +/*!< Parameter valid check for sync startup timera unit */ +#define IS_VALID_SYNC_STARTUP_TIMERA_UNIT(x) \ +( (M4_TMRA2 == (x)) || \ + (M4_TMRA3 == (x)) || \ + (M4_TMRA4 == (x)) || \ + (M4_TMRA5 == (x)) || \ + (M4_TMRA6 == (x))) + +/*!< Parameter valid check for Count clock division */ +#define IS_VALID_COUNT_CLK_DIV(x) \ +( (TimeraPclkDiv1 == (x)) || \ + (TimeraPclkDiv2 == (x)) || \ + (TimeraPclkDiv4 == (x)) || \ + (TimeraPclkDiv8 == (x)) || \ + (TimeraPclkDiv16 == (x)) || \ + (TimeraPclkDiv32 == (x)) || \ + (TimeraPclkDiv64 == (x)) || \ + (TimeraPclkDiv128 == (x)) || \ + (TimeraPclkDiv256 == (x)) || \ + (TimeraPclkDiv512 == (x)) || \ + (TimeraPclkDiv1024 == (x))) + +/*!< Parameter valid check for count mode */ +#define IS_VALID_COUNT_MODE(x) \ +( (TimeraCountModeSawtoothWave == (x)) || \ + (TimeraCountModeTriangularWave == (x))) + +/*!< Parameter valid check for count direction */ +#define IS_VALID_COUNT_DIR(x) \ +( (TimeraCountDirUp == (x)) || \ + (TimeraCountDirDown == (x))) + +/*!< Parameter valid check for normal timera channel */ +#define IS_VALID_NORMAL_TIMERA_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh2 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh4 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh6 == (x)) || \ + (TimeraCh7 == (x)) || \ + (TimeraCh8 == (x))) + +/*!< Parameter valid check for set cache channel */ +#define IS_VALID_SET_CACHE_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh7 == (x))) + +/*!< Parameter valid check for enable cache channel */ +#define IS_VALID_ENABLE_CACHE_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh7 == (x))) + +/*!< Parameter valid check for timera count start output status */ +#define IS_VALID_COUNT_START_OUTPUT(x) \ +( (TimeraCountStartOutputLow == (x)) || \ + (TimeraCountStartOutputHigh == (x)) || \ + (TimeraCountStartOutputKeep == (x))) + +/*!< Parameter valid check for timera count stop output status */ +#define IS_VALID_COUNT_STOP_OUTPUT(x) \ +( (TimeraCountStopOutputLow == (x)) || \ + (TimeraCountStopOutputHigh == (x)) || \ + (TimeraCountStopOutputKeep == (x))) + +/*!< Parameter valid check for compare match output status */ +#define IS_VALID_COMPARE_MATCH_OUTPUT(x) \ +( (TimeraCompareMatchOutputLow == (x)) || \ + (TimeraCompareMatchOutputHigh == (x)) || \ + (TimeraCompareMatchOutputKeep == (x)) || \ + (TimeraCompareMatchOutputReverse == (x))) + +/*!< Parameter valid check for period match output status */ +#define IS_VALID_PERIOD_MATCH_OUTPUT(x) \ +( (TimeraPeriodMatchOutputLow == (x)) || \ + (TimeraPeriodMatchOutputHigh == (x)) || \ + (TimeraPeriodMatchOutputKeep == (x)) || \ + (TimeraPeriodMatchOutputReverse == (x))) + +/*!< Parameter valid check for specify output status */ +#define IS_VALID_SPECIFY_OUTPUT_STATUS(x) \ +( (TimeraSpecifyOutputInvalid == (x)) || \ + (TimeraSpecifyOutputLow == (x)) || \ + (TimeraSpecifyOutputHigh == (x))) + +/*!< Parameter valid check for port filter clock */ +#define IS_VALID_PORT_FILTER_CLOCK(x) \ +( (TimeraFilterPclkDiv1 == (x)) || \ + (TimeraFilterPclkDiv4 == (x)) || \ + (TimeraFilterPclkDiv16 == (x)) || \ + (TimeraFilterPclkDiv64 == (x))) + +/*!< Parameter valid check for capture filter port source */ +#define IS_VALID_CAPTURE_FILTER_PORT_SOURCE(x) \ +( (TimeraFilterSourceCh1 == (x)) || \ + (TimeraFilterSourceCh2 == (x)) || \ + (TimeraFilterSourceCh3 == (x)) || \ + (TimeraFilterSourceCh4 == (x)) || \ + (TimeraFilterSourceCh5 == (x)) || \ + (TimeraFilterSourceCh6 == (x)) || \ + (TimeraFilterSourceCh7 == (x)) || \ + (TimeraFilterSourceCh8 == (x)) || \ + (TimeraFilterSourceTrig == (x))) + +/*!< Parameter valid check for coding filter port source */ +#define IS_VALID_CODING_FILTER_PORT_SOURCE(x) \ +( (TimeraFilterSourceClkA == (x)) || \ + (TimeraFilterSourceClkB == (x)) || \ + (TimeraFilterSourceTrig == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_IRQ_SOURCE(x) \ +( (TimeraIrqCaptureOrCompareCh1 == (x)) || \ + (TimeraIrqCaptureOrCompareCh2 == (x)) || \ + (TimeraIrqCaptureOrCompareCh3 == (x)) || \ + (TimeraIrqCaptureOrCompareCh4 == (x)) || \ + (TimeraIrqCaptureOrCompareCh5 == (x)) || \ + (TimeraIrqCaptureOrCompareCh6 == (x)) || \ + (TimeraIrqCaptureOrCompareCh7 == (x)) || \ + (TimeraIrqCaptureOrCompareCh8 == (x)) || \ + (TimeraIrqOverflow == (x)) || \ + (TimeraIrqUnderflow == (x))) + +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (TimeraFlagCaptureOrCompareCh1 == (x)) || \ + (TimeraFlagCaptureOrCompareCh2 == (x)) || \ + (TimeraFlagCaptureOrCompareCh3 == (x)) || \ + (TimeraFlagCaptureOrCompareCh4 == (x)) || \ + (TimeraFlagCaptureOrCompareCh5 == (x)) || \ + (TimeraFlagCaptureOrCompareCh6 == (x)) || \ + (TimeraFlagCaptureOrCompareCh7 == (x)) || \ + (TimeraFlagCaptureOrCompareCh8 == (x)) || \ + (TimeraFlagOverflow == (x)) || \ + (TimeraFlagUnderflow == (x))) + +/*! Parameter valid check for common trigger. */ +#define IS_VALID_COM_TRIGGER(x) \ +( (TimeraComTrigger_1 == (x)) || \ + (TimeraComTrigger_2 == (x)) || \ + (TimeraComTrigger_1_2 == (x))) + +/*!< Parameter valid check for event source */ +#define IS_VALID_EVENT_SOURCE(x) ((x) <= 511u) + +/*!< Timera registers reset value */ +#define TIMERA_REG_CNTER_RESET_VALUE (0x0000u) +#define TIMERA_REG_PERAR_RESET_VALUE (0xFFFFu) +#define TIMERA_REG_CMPAR_RESET_VALUE (0xFFFFu) +#define TIMERA_REG_BCSTR_RESET_VALUE (0x0002u) +#define TIMERA_REG_ICONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_ECONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_FCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_STFLR_RESET_VALUE (0x0000u) +#define TIMERA_REG_BCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_CCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_PCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCUPR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCDOR_RESET_VALUE (0x0000u) + +#define TIMERA_REG_HTSSR0_RESET_VALUE (0x000001FFul) +#define TIMERA_REG_HTSSR1_RESET_VALUE (0x000001FFul) + +/*!< Timera calculate register address of channel */ +#define TIMERA_CALC_REG_ADDR(reg, chl) ((uint32_t)(&(reg)) + (chl)*0x4u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize Timera unit + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_DeInit(M4_TMRA_TypeDef *TIMERAx) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32Cnt = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = TIMERA_REG_CNTER_RESET_VALUE; + TIMERAx->PERAR = TIMERA_REG_PERAR_RESET_VALUE; + TIMERAx->BCSTR = TIMERA_REG_BCSTR_RESET_VALUE; + TIMERAx->ICONR = TIMERA_REG_ICONR_RESET_VALUE; + TIMERAx->ECONR = TIMERA_REG_ECONR_RESET_VALUE; + TIMERAx->FCONR = TIMERA_REG_FCONR_RESET_VALUE; + TIMERAx->STFLR = TIMERA_REG_STFLR_RESET_VALUE; + TIMERAx->HCONR = TIMERA_REG_HCONR_RESET_VALUE; + TIMERAx->HCUPR = TIMERA_REG_HCUPR_RESET_VALUE; + TIMERAx->HCDOR = TIMERA_REG_HCDOR_RESET_VALUE; + + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, u32Cnt) = TIMERA_REG_CMPAR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 4u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, u32Cnt * 2u) = TIMERA_REG_BCONR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, u32Cnt) = TIMERA_REG_CCONR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, u32Cnt) = TIMERA_REG_PCONR_RESET_VALUE; + } + + M4_AOS->TMRA_HTSSR0 = TIMERA_REG_HTSSR0_RESET_VALUE; + M4_AOS->TMRA_HTSSR1 = TIMERA_REG_HTSSR1_RESET_VALUE; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit base function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcBaseInit Pointer to timera base init configuration + ** \arg See the struct #stc_timera_base_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidMode Unit 1 sync startup invalid + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcBaseInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_BaseInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_base_init_t *pstcBaseInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcBaseInit)) + { + DDL_ASSERT(IS_VALID_COUNT_CLK_DIV(pstcBaseInit->enClkDiv)); + DDL_ASSERT(IS_VALID_COUNT_MODE(pstcBaseInit->enCntMode)); + DDL_ASSERT(IS_VALID_COUNT_DIR(pstcBaseInit->enCntDir)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcBaseInit->enSyncStartupEn)); + + /* Configure control status register */ + TIMERAx->BCSTR_f.CKDIV = pstcBaseInit->enClkDiv; + TIMERAx->BCSTR_f.MODE = pstcBaseInit->enCntMode; + TIMERAx->BCSTR_f.DIR = pstcBaseInit->enCntDir; + + /* Unit 1 sync startup invalid */ + if ((M4_TMRA1 == TIMERAx) && (Enable == pstcBaseInit->enSyncStartupEn)) + { + enRet = ErrorInvalidMode; + } + else + { + TIMERAx->BCSTR_f.SYNST = pstcBaseInit->enSyncStartupEn; + enRet = Ok; + } + + /* Configure period value register */ + TIMERAx->PERAR = pstcBaseInit->u16PeriodVal; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera current count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16Cnt Timera current count value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCurrCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Cnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = u16Cnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera current count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera current count value + ** + ******************************************************************************/ +uint16_t TIMERA_GetCurrCount(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16CurrCntVal = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16CurrCntVal = (uint16_t)TIMERAx->CNTER; + } + + return u16CurrCntVal; +} + +/** + ******************************************************************************* + ** \brief Set Timera period value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16Period Timera period value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetPeriodValue(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Period) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->PERAR = u16Period; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera period count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera current period value + ** + ******************************************************************************/ +uint16_t TIMERA_GetPeriodValue(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16PeriodVal = 0u; + + /* Check parameters */ + if (IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16PeriodVal = (uint16_t)TIMERAx->PERAR; + } + + return u16PeriodVal; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera software synchronous startup + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable synchronous startup + ** \arg Enable Enable synchronous startup + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SyncStartupCmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SYNC_STARTUP_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + TIMERAx->BCSTR_f.SYNST = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera startup + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera startup + ** \arg Enable Enable timera startup + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_Cmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + TIMERAx->BCSTR_f.START = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit compare function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] pstcCompareInit Pointer to timera compare init configuration + ** \arg See the struct #stc_timera_compare_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCompareInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_CompareInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_compare_init_t *pstcCompareInit) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + __IO stc_tmra_bconr_field_t *pstcTimeraCache; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCompareInit)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_COUNT_START_OUTPUT(pstcCompareInit->enStartCountOutput)); + DDL_ASSERT(IS_VALID_COUNT_STOP_OUTPUT(pstcCompareInit->enStopCountOutput)); + DDL_ASSERT(IS_VALID_COMPARE_MATCH_OUTPUT(pstcCompareInit->enCompareMatchOutput)); + DDL_ASSERT(IS_VALID_PERIOD_MATCH_OUTPUT(pstcCompareInit->enPeriodMatchOutput)); + DDL_ASSERT(IS_VALID_SPECIFY_OUTPUT_STATUS(pstcCompareInit->enSpecifyOutput)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enCacheEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enTriangularCrestTransEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enTriangularTroughTransEn)); + + /* Configure port control register */ + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->STAC = pstcCompareInit->enStartCountOutput; + pstcTimeraPort->STPC = pstcCompareInit->enStopCountOutput; + pstcTimeraPort->CMPC = pstcCompareInit->enCompareMatchOutput; + pstcTimeraPort->PERC = pstcCompareInit->enPeriodMatchOutput; + pstcTimeraPort->FORC = pstcCompareInit->enSpecifyOutput; + + /* Configure cache control register */ + if ((TimeraCh1 == enChannel) || (TimeraCh3 == enChannel) || + (TimeraCh5 == enChannel) || (TimeraCh7 == enChannel)) + { + pstcTimeraCache = (stc_tmra_bconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, enChannel); + pstcTimeraCache->BSE0 = pstcCompareInit->enTriangularCrestTransEn; + pstcTimeraCache->BSE1 = pstcCompareInit->enTriangularTroughTransEn; + pstcTimeraCache->BEN = pstcCompareInit->enCacheEn; + /* Configure compare cache value register */ + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel + 1); + pstcTimeraCompare->CMP = pstcCompareInit->u16CompareCacheVal; + } + + /* Configure compare value register */ + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + pstcTimeraCompare->CMP = pstcCompareInit->u16CompareVal; + + /* Set compare output function */ + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enChannel); + pstcTimeraCapture->CAPMD = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera compare value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] u16CompareVal Timera campare value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareVal) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + pstcTimeraCompare->CMP = u16CompareVal; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera compare value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \retval uint16_t Timera compare value + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +uint16_t TIMERA_GetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel) +{ + uint16_t u16CompareVal = 0u; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + u16CompareVal = (uint16_t)pstcTimeraCompare->CMP; + } + + return u16CompareVal; +} + +/** + ******************************************************************************* + ** \brief Set Timera compare cache value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh7 Timera channel 7 + ** + ** \param [in] u16CompareCache Timera compare cache value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCacheValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareCache) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_SET_CACHE_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel + 1); + pstcTimeraCompare->CMP = u16CompareCache; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera compare cache + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh7 Timera channel 7 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera compare cache + ** \arg Enable Enable timera compare cache + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CompareCacheCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_bconr_field_t *pstcTimeraCache; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_ENABLE_CACHE_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + /* Configure cache control register */ + pstcTimeraCache = (stc_tmra_bconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, enChannel); + pstcTimeraCache->BEN = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Specify Timera port output status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enOutputSta Timera port output status + ** \arg TimeraSpecifyOutputInvalid Port output invalid + ** \arg TimeraSpecifyOutputLow Port output low level from next period + ** \arg TimeraSpecifyOutputHigh Port output high level from next period + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SpecifyOutputSta(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_timera_specify_output_t enOutputSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_SPECIFY_OUTPUT_STATUS(enOutputSta)); + + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->FORC = enOutputSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera compare function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera compare function + ** \arg Enable Enable timera compare function + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CompareCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->OUTEN = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit capture function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera capture channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] pstcCapInit Pointer to timera capture init configuration + ** \arg See the struct #stc_timera_capture_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCapInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_capture_init_t *pstcCapInit) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCapInit)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCapturePwmRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCapturePwmFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureSpecifyEventEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enPwmFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enTrigFilterEn)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCapInit->enPwmClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCapInit->enTrigClkDiv)); + + /* Configure capture control register */ + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enChannel); + pstcTimeraCapture->HICP0 = pstcCapInit->enCapturePwmRisingEn; + pstcTimeraCapture->HICP1 = pstcCapInit->enCapturePwmFallingEn; + pstcTimeraCapture->HICP2 = pstcCapInit->enCaptureSpecifyEventEn; + pstcTimeraCapture->NOFICKCP = pstcCapInit->enPwmClkDiv; + pstcTimeraCapture->NOFIENCP = pstcCapInit->enPwmFilterEn; + + /* TIMA__TRIG port capture function only valid for TimeraCh3 */ + if (TimeraCh3 == enChannel) + { + pstcTimeraCapture->HICP3 = pstcCapInit->enCaptureTrigRisingEn; + pstcTimeraCapture->HICP4 = pstcCapInit->enCaptureTrigFallingEn; + /* Configure filter control register */ + TIMERAx->FCONR_f.NOFICKTG = pstcCapInit->enTrigClkDiv; + TIMERAx->FCONR_f.NOFIENTG = pstcCapInit->enTrigFilterEn; + } + + /* Set capture input function */ + pstcTimeraCapture->CAPMD = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera capture filter + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFilterPort Timera capture filter input port + ** \arg TimeraFilterSourceCh1 TIMA__PWM1 input port + ** \arg TimeraFilterSourceCh2 TIMA__PWM2 input port + ** \arg TimeraFilterSourceCh3 TIMA__PWM3 input port + ** \arg TimeraFilterSourceCh4 TIMA__PWM4 input port + ** \arg TimeraFilterSourceCh5 TIMA__PWM5 input port + ** \arg TimeraFilterSourceCh6 TIMA__PWM6 input port + ** \arg TimeraFilterSourceCh7 TIMA__PWM7 input port + ** \arg TimeraFilterSourceCh8 TIMA__PWM8 input port + ** \arg TimeraFilterSourceTrig TIMA__TRIG input port + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera capture filter + ** \arg Enable Enable timera capture filter + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_CAPTURE_FILTER_PORT_SOURCE(enFilterPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (TimeraFilterSourceTrig == enFilterPort) + { + TIMERAx->FCONR_f.NOFIENTG = enNewSta; + } + else + { + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enFilterPort); + pstcTimeraCapture->NOFIENCP = enNewSta; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera capture value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera capture channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \retval uint16_t Timera capture value + ** + ******************************************************************************/ +uint16_t TIMERA_GetCaptureValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel) +{ + uint16_t u16CapVal = 0u; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + u16CapVal = (uint16_t)pstcTimeraCompare->CMP; + } + + return u16CapVal; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit orthogonal coding function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcCodingInit Pointer to timera orthogonal coding configuration + ** \arg See the struct #stc_timera_orthogonal_coding_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCodingInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_OrthogonalCodingInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_orthogonal_coding_init_t *pstcCodingInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCodingInit)) + { + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enTrigClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enClkBClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enClkAClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enTrigFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enClkBFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enClkAFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkALowAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkALowAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkAHighAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkAHighAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBLowAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBLowAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBHighAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBHighAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncSpecifyEventTriggerEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncAnotherUnitOverflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncAnotherUnitUnderflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkALowAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkALowAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkAHighAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkAHighAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBLowAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBLowAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBHighAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBHighAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecSpecifyEventTriggerEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecAnotherUnitOverflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecAnotherUnitUnderflowEn)); + + /* Configure hardware increase event register */ + TIMERAx->HCUPR_f.HCUP0 = pstcCodingInit->enIncClkALowAndClkBRisingEn; + TIMERAx->HCUPR_f.HCUP1 = pstcCodingInit->enIncClkALowAndClkBFallingEn; + TIMERAx->HCUPR_f.HCUP2 = pstcCodingInit->enIncClkAHighAndClkBRisingEn; + TIMERAx->HCUPR_f.HCUP3 = pstcCodingInit->enIncClkAHighAndClkBFallingEn; + TIMERAx->HCUPR_f.HCUP4 = pstcCodingInit->enIncClkBLowAndClkARisingEn; + TIMERAx->HCUPR_f.HCUP5 = pstcCodingInit->enIncClkBLowAndClkAFallingEn; + TIMERAx->HCUPR_f.HCUP6 = pstcCodingInit->enIncClkBHighAndClkARisingEn; + TIMERAx->HCUPR_f.HCUP7 = pstcCodingInit->enIncClkBHighAndClkAFallingEn; + TIMERAx->HCUPR_f.HCUP8 = pstcCodingInit->enIncTrigRisingEn; + TIMERAx->HCUPR_f.HCUP9 = pstcCodingInit->enIncTrigFallingEn; + TIMERAx->HCUPR_f.HCUP10 = pstcCodingInit->enIncSpecifyEventTriggerEn; + TIMERAx->HCUPR_f.HCUP11 = pstcCodingInit->enIncAnotherUnitOverflowEn; + TIMERAx->HCUPR_f.HCUP12 = pstcCodingInit->enIncAnotherUnitUnderflowEn; + + /* Configure hardware decrease event register */ + TIMERAx->HCDOR_f.HCDO0 = pstcCodingInit->enDecClkALowAndClkBRisingEn; + TIMERAx->HCDOR_f.HCDO1 = pstcCodingInit->enDecClkALowAndClkBFallingEn; + TIMERAx->HCDOR_f.HCDO2 = pstcCodingInit->enDecClkAHighAndClkBRisingEn; + TIMERAx->HCDOR_f.HCDO3 = pstcCodingInit->enDecClkAHighAndClkBFallingEn; + TIMERAx->HCDOR_f.HCDO4 = pstcCodingInit->enDecClkBLowAndClkARisingEn; + TIMERAx->HCDOR_f.HCDO5 = pstcCodingInit->enDecClkBLowAndClkAFallingEn; + TIMERAx->HCDOR_f.HCDO6 = pstcCodingInit->enDecClkBHighAndClkARisingEn; + TIMERAx->HCDOR_f.HCDO7 = pstcCodingInit->enDecClkBHighAndClkAFallingEn; + TIMERAx->HCDOR_f.HCDO8 = pstcCodingInit->enDecTrigRisingEn; + TIMERAx->HCDOR_f.HCDO9 = pstcCodingInit->enDecTrigFallingEn; + TIMERAx->HCDOR_f.HCDO10 = pstcCodingInit->enDecSpecifyEventTriggerEn; + TIMERAx->HCDOR_f.HCDO11 = pstcCodingInit->enDecAnotherUnitOverflowEn; + TIMERAx->HCDOR_f.HCDO12 = pstcCodingInit->enDecAnotherUnitUnderflowEn; + + /* Configure filter control register */ + TIMERAx->FCONR_f.NOFICKTG = pstcCodingInit->enTrigClkDiv; + TIMERAx->FCONR_f.NOFIENTG = pstcCodingInit->enTrigFilterEn; + TIMERAx->FCONR_f.NOFICKCB = pstcCodingInit->enClkBClkDiv; + TIMERAx->FCONR_f.NOFIENCB = pstcCodingInit->enClkBFilterEn; + TIMERAx->FCONR_f.NOFICKCA = pstcCodingInit->enClkAClkDiv; + TIMERAx->FCONR_f.NOFIENCA = pstcCodingInit->enClkAFilterEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera orthogonal coding value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16CodingCnt Timera orthogonal coding value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16CodingCnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = u16CodingCnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera orthogonal coding value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera orthogonal coding value + ** + ******************************************************************************/ +uint16_t TIMERA_GetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16CodingCnt = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16CodingCnt = (uint16_t)TIMERAx->CNTER; + } + + return u16CodingCnt; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera orthogonal coding filter + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFilterPort Timera orthogonal coding filter input port + ** \arg TimeraFilterSourceClkA TIMA__CLKA input port + ** \arg TimeraFilterSourceClkB TIMA__CLKB input port + ** \arg TimeraFilterSourceTrig TIMA__TRIG input port + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera orthogonal coding filter + ** \arg Enable Enable timera orthogonal coding filter + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_OrthogonalCodingFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_CODING_FILTER_PORT_SOURCE(enFilterPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enFilterPort) + { + case TimeraFilterSourceClkA: + TIMERAx->FCONR_f.NOFIENCA = enNewSta; + break; + case TimeraFilterSourceClkB: + TIMERAx->FCONR_f.NOFIENCB = enNewSta; + break; + case TimeraFilterSourceTrig: + TIMERAx->FCONR_f.NOFIENTG = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit hardware trigger event function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwTriggerInit Pointer to timera hardware trigger event configuration + ** \arg See the struct #stc_timera_hw_trigger_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwTriggerInit == NULL + ** + ** \note If sync startup(BCSTR.SYNST) bit set 1 trigger hardware sync startup when HCONR.HSTA1~0 bit set + ** + ******************************************************************************/ +en_result_t TIMERA_HwTriggerInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_trigger_init_t *pstcHwTriggerInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwTriggerInit)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enTrigRisingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enTrigFallingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enSpecifyEventStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enTrigRisingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enTrigFallingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enSpecifyEventStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enSpecifyEventClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enChannel3RisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enChannel3FallingClearEn)); + + /* Configure hardware startup conditions */ + TIMERAx->HCONR_f.HSTA0 = pstcHwTriggerInit->stcHwStartup.enTrigRisingStartupEn; + TIMERAx->HCONR_f.HSTA1 = pstcHwTriggerInit->stcHwStartup.enTrigFallingStartupEn; + TIMERAx->HCONR_f.HSTA2 = pstcHwTriggerInit->stcHwStartup.enSpecifyEventStartupEn; + + /* Configure hardware stop conditions */ + TIMERAx->HCONR_f.HSTP0 = pstcHwTriggerInit->stcHwStop.enTrigRisingStopEn; + TIMERAx->HCONR_f.HSTP1 = pstcHwTriggerInit->stcHwStop.enTrigFallingStopEn; + TIMERAx->HCONR_f.HSTP2 = pstcHwTriggerInit->stcHwStop.enSpecifyEventStopEn; + + /* Configure hardware clear conditions */ + TIMERAx->HCONR_f.HCLE0 = pstcHwTriggerInit->stcHwClear.enTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE1 = pstcHwTriggerInit->stcHwClear.enTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE2 = pstcHwTriggerInit->stcHwClear.enSpecifyEventClearEn; + TIMERAx->HCONR_f.HCLE3 = pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE4 = pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE5 = pstcHwTriggerInit->stcHwClear.enChannel3RisingClearEn; + TIMERAx->HCONR_f.HCLE6 = pstcHwTriggerInit->stcHwClear.enChannel3FallingClearEn; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware startup Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwStartup Pointer to timera hardware startup configuration + ** \arg See the struct #stc_timera_hw_startup_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwStartup == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwStartupConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_startup_config_t *pstcHwStartup) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwStartup)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enTrigRisingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enTrigFallingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enSpecifyEventStartupEn)); + + TIMERAx->HCONR_f.HSTA0 = pstcHwStartup->enTrigRisingStartupEn; + TIMERAx->HCONR_f.HSTA1 = pstcHwStartup->enTrigFallingStartupEn; + TIMERAx->HCONR_f.HSTA2 = pstcHwStartup->enSpecifyEventStartupEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware stop Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwStop Pointer to timera hardware stop configuration + ** \arg See the struct #stc_timera_hw_stop_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwStop == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwStopConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_stop_config_t *pstcHwStop) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwStop)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enTrigRisingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enTrigFallingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enSpecifyEventStopEn)); + + TIMERAx->HCONR_f.HSTP0 = pstcHwStop->enTrigRisingStopEn; + TIMERAx->HCONR_f.HSTP1 = pstcHwStop->enTrigFallingStopEn; + TIMERAx->HCONR_f.HSTP2 = pstcHwStop->enSpecifyEventStopEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware clear Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwClear Pointer to timera hardware clear configuration + ** \arg See the struct #stc_timera_hw_clear_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwClear == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwClearConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_clear_config_t *pstcHwClear) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwClear)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enSpecifyEventClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enAnotherUnitTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enAnotherUnitTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enChannel3RisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enChannel3FallingClearEn)); + + TIMERAx->HCONR_f.HCLE0 = pstcHwClear->enTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE1 = pstcHwClear->enTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE2 = pstcHwClear->enSpecifyEventClearEn; + TIMERAx->HCONR_f.HCLE3 = pstcHwClear->enAnotherUnitTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE4 = pstcHwClear->enAnotherUnitTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE5 = pstcHwClear->enChannel3RisingClearEn; + TIMERAx->HCONR_f.HCLE6 = pstcHwClear->enChannel3FallingClearEn; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera interrupt request + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enIrq Timera interrupt request + ** \arg TimeraIrqCaptureOrCompareCh1 Channel 1 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh2 Channel 2 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh3 Channel 3 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh4 Channel 4 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh5 Channel 5 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh6 Channel 6 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh7 Channel 7 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh8 Channel 8 interrupt request + ** \arg TimeraIrqOverflow Count overflow interrupt request + ** \arg TimeraIrqUnderflow Count underflow interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera interrupt request + ** \arg Enable Enable timera interrupt request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_IrqCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_irq_type_t enIrq, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_IRQ_SOURCE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enIrq) + { + case TimeraIrqCaptureOrCompareCh1: + TIMERAx->ICONR_f.ITEN1 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh2: + TIMERAx->ICONR_f.ITEN2 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh3: + TIMERAx->ICONR_f.ITEN3 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh4: + TIMERAx->ICONR_f.ITEN4 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh5: + TIMERAx->ICONR_f.ITEN5 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh6: + TIMERAx->ICONR_f.ITEN6 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh7: + TIMERAx->ICONR_f.ITEN7 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh8: + TIMERAx->ICONR_f.ITEN8 = enNewSta; + break; + case TimeraIrqOverflow: + TIMERAx->BCSTR_f.ITENOVF = enNewSta; + break; + case TimeraIrqUnderflow: + TIMERAx->BCSTR_f.ITENUDF = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera event request + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera event request channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera event request + ** \arg Enable Enable timera event request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_EventCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + switch (enChannel) + { + case TimeraCh1: + TIMERAx->ECONR_f.ETEN1 = enNewSta; + break; + case TimeraCh2: + TIMERAx->ECONR_f.ETEN2 = enNewSta; + break; + case TimeraCh3: + TIMERAx->ECONR_f.ETEN3 = enNewSta; + break; + case TimeraCh4: + TIMERAx->ECONR_f.ETEN4 = enNewSta; + break; + case TimeraCh5: + TIMERAx->ECONR_f.ETEN5 = enNewSta; + break; + case TimeraCh6: + TIMERAx->ECONR_f.ETEN6 = enNewSta; + break; + case TimeraCh7: + TIMERAx->ECONR_f.ETEN7 = enNewSta; + break; + case TimeraCh8: + TIMERAx->ECONR_f.ETEN8 = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera flag status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFlag Timera flag type + ** \arg TimeraFlagCaptureOrCompareCh1 Channel 1 match flag + ** \arg TimeraFlagCaptureOrCompareCh2 Channel 2 match flag + ** \arg TimeraFlagCaptureOrCompareCh3 Channel 3 match flag + ** \arg TimeraFlagCaptureOrCompareCh4 Channel 4 match flag + ** \arg TimeraFlagCaptureOrCompareCh5 Channel 5 match flag + ** \arg TimeraFlagCaptureOrCompareCh6 Channel 6 match flag + ** \arg TimeraFlagCaptureOrCompareCh7 Channel 7 match flag + ** \arg TimeraFlagCaptureOrCompareCh8 Channel 8 match flag + ** \arg TimeraFlagOverflow Count overflow flag + ** \arg TimeraFlagUnderflow Count underflow flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t TIMERA_GetFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case TimeraFlagCaptureOrCompareCh1: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF1; + break; + case TimeraFlagCaptureOrCompareCh2: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF2; + break; + case TimeraFlagCaptureOrCompareCh3: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF3; + break; + case TimeraFlagCaptureOrCompareCh4: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF4; + break; + case TimeraFlagCaptureOrCompareCh5: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF5; + break; + case TimeraFlagCaptureOrCompareCh6: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF6; + break; + case TimeraFlagCaptureOrCompareCh7: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF7; + break; + case TimeraFlagCaptureOrCompareCh8: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF8; + break; + case TimeraFlagOverflow: + enFlagSta = (en_flag_status_t)TIMERAx->BCSTR_f.OVFF; + break; + case TimeraFlagUnderflow: + enFlagSta = (en_flag_status_t)TIMERAx->BCSTR_f.UDFF; + break; + default: + break; + } + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear Timera flag status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFlag Timera flag type + ** \arg TimeraFlagCaptureOrCompareCh1 Channel 1 match flag + ** \arg TimeraFlagCaptureOrCompareCh2 Channel 2 match flag + ** \arg TimeraFlagCaptureOrCompareCh3 Channel 3 match flag + ** \arg TimeraFlagCaptureOrCompareCh4 Channel 4 match flag + ** \arg TimeraFlagCaptureOrCompareCh5 Channel 5 match flag + ** \arg TimeraFlagCaptureOrCompareCh6 Channel 6 match flag + ** \arg TimeraFlagCaptureOrCompareCh7 Channel 7 match flag + ** \arg TimeraFlagCaptureOrCompareCh8 Channel 8 match flag + ** \arg TimeraFlagOverflow Count overflow flag + ** \arg TimeraFlagUnderflow Count underflow flag + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_ClearFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case TimeraFlagCaptureOrCompareCh1: + TIMERAx->STFLR_f.CMPF1 = 0u; + break; + case TimeraFlagCaptureOrCompareCh2: + TIMERAx->STFLR_f.CMPF2 = 0u; + break; + case TimeraFlagCaptureOrCompareCh3: + TIMERAx->STFLR_f.CMPF3 = 0u; + break; + case TimeraFlagCaptureOrCompareCh4: + TIMERAx->STFLR_f.CMPF4 = 0u; + break; + case TimeraFlagCaptureOrCompareCh5: + TIMERAx->STFLR_f.CMPF5 = 0u; + break; + case TimeraFlagCaptureOrCompareCh6: + TIMERAx->STFLR_f.CMPF6 = 0u; + break; + case TimeraFlagCaptureOrCompareCh7: + TIMERAx->STFLR_f.CMPF7 = 0u; + break; + case TimeraFlagCaptureOrCompareCh8: + TIMERAx->STFLR_f.CMPF8 = 0u; + break; + case TimeraFlagOverflow: + TIMERAx->BCSTR_f.OVFF = 0u; + break; + case TimeraFlagUnderflow: + TIMERAx->BCSTR_f.UDFF = 0u; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set counter event trigger source + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_SetCountTriggerSrc(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMRA_HTSSR0_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set capture event trigger source + ** + ** \param [in] enTriggerSrc Capture event trigger source + ** \arg 0-511 Used to trigger the capture function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_SetCaptureTriggerSrc(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMRA_HTSSR1_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable TimerA counter common trigger. + ** + ** \param [in] enComTrigger TimerA common trigger selection. + ** \arg TimeraComTrigger_1 Select common trigger 1 + ** \arg TimeraComTrigger_2 Select common trigger 2 + ** \arg TimeraComTrigger_1_2 Select common trigger 1 and 2 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable the specified common trigger. + ** \arg Enable Enable the specified common trigger. + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_CountComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + uint32_t u32ComTrig; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u32ComTrig = (uint32_t)enComTrigger << 30u; + if (enNewSta == Enable) + { + M4_AOS->TMRA_HTSSR0 |= u32ComTrig; + } + else + { + M4_AOS->TMRA_HTSSR0 &= ~u32ComTrig; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable TimerA capture common trigger. + ** + ** \param [in] enComTrigger TimerA common trigger selection. + ** \arg TimeraComTrigger_1 Select common trigger 1 + ** \arg TimeraComTrigger_2 Select common trigger 2 + ** \arg TimeraComTrigger_1_2 Select common trigger 1 and 2 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable the specified common trigger. + ** \arg Enable Enable the specified common trigger. + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + uint32_t u32ComTrig; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u32ComTrig = (uint32_t)enComTrigger << 30u; + if (enNewSta == Enable) + { + M4_AOS->TMRA_HTSSR1 |= u32ComTrig; + } + else + { + M4_AOS->TMRA_HTSSR1 &= ~u32ComTrig; + } + + return enRet; +} + +//@} // TimeraGroup + +#endif /* DDL_TIMERA_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_trng.c b/driver/src/hc32f460_trng.c new file mode 100644 index 0000000..95a994a --- /dev/null +++ b/driver/src/hc32f460_trng.c @@ -0,0 +1,263 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_trng.c + ** + ** A detailed description is available at + ** @link TrngGroup Trng description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Trng. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_trng.h" +#include "hc32f460_utility.h" + +#if (DDL_TRNG_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup TrngGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for TRNG load control. */ +#define IS_TRNG_LOAD_CTRL(CTRL) \ +( ((CTRL) == TrngLoadNewInitValue_Enable) || \ + ((CTRL) == TrngLoadNewInitValue_Disable)) + +/*! Parameter validity check for TRNG shift count. */ +#define IS_TRNG_SHIFT_COUNT(COUNT) \ +( ((COUNT) == TrngShiftCount_32) || \ + ((COUNT) == TrngShiftCount_64) || \ + ((COUNT) == TrngShiftCount_128) || \ + ((COUNT) == TrngShiftCount_256)) + + +#define RANDOM_NUM_LENGTH (2u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes the TRNG. + ** + ** \param [in] pstcInit Pointer to TRNG initialization structure. + ** \arg enLoadCtrl + ** \- TrngLoadNewInitValue_Enable Data register load new initial value before + ** random number is generated. + ** \- TrngLoadNewInitValue_Disable Data register do not load new initial value + ** before random number is generated. + ** + ** \arg enShiftCount Shift count control bit when capturing random noise. + ** \- TrngShiftCount_32 Shift 32 times. + ** \- TrngShiftCount_64 Shift 64 times. + ** \- TrngShiftCount_128 Shift 128 times. + ** \- TrngShiftCount_256 Shift 256 times. + ** + ** \retval Ok No error occurred. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TRNG_Init(const stc_trng_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + /* Parameter validity check */ + DDL_ASSERT(IS_TRNG_LOAD_CTRL(pstcInit->enLoadCtrl)); + DDL_ASSERT(IS_TRNG_SHIFT_COUNT(pstcInit->enShiftCount)); + + /* Stop TRNG generating*/ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + + M4_TRNG->MR_f.LOAD = pstcInit->enLoadCtrl; + M4_TRNG->MR_f.CNT = pstcInit->enShiftCount; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes the TRNG. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_DeInit(void) +{ + /* Stop TRNG generating*/ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + + /* Set the value of all registers to the reset value. */ + M4_TRNG->CR = 0u; + M4_TRNG->MR = 0x12ul; + M4_TRNG->DR0 = 0x08000000ul; + M4_TRNG->DR0 = 0x08000200ul; +} + +/** + ******************************************************************************* + ** \brief Start TRNG and generate random number. + ** + ** \param [out] pu32Random The destination address where the random + ** number will be stored. + ** \param [in] u8Length Random number length(in word). + ** TRNG generates two random numbers(2 words) at one time. + ** u8Length >= 2, both random numbers will be read. + ** u8Length < 2, only one random number will be read. + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout TRNG works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TRNG_Generate(uint32_t *pu32Random, uint8_t u8Length, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32TrngTimeout; + __IO uint32_t u32TimeCount; + + if ((NULL != pu32Random) && (0u != u32Timeout) && (0u != u8Length)) + { + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32TrngTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + + /* Turn on TRNG circuit. */ + bM4_TRNG_CR_EN = 1u; + + /* Start TRNG to generate random number. */ + bM4_TRNG_CR_RUN = 1u; + + /* wait generation done and check if timeout. */ + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32TrngTimeout) + { + if (bM4_TRNG_CR_RUN == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (Ok == enRet) + { + /* read the random number. */ + pu32Random[0u] = M4_TRNG->DR0; + if (u8Length >= RANDOM_NUM_LENGTH) + { + pu32Random[1u] = M4_TRNG->DR1; + } + } + + /* Stop TRNG generating. */ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit. */ + bM4_TRNG_CR_EN = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start TRNG only. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_StartIT(void) +{ + /* Turn on TRNG circuit. */ + bM4_TRNG_CR_EN = 1u; + + /* Start TRNG to generate random number. */ + bM4_TRNG_CR_RUN = 1u; +} + +/** + ******************************************************************************* + ** \brief Get random number. + ** + ** \param [out] pu32Random The destination address where the random + ** number will be stored. + ** \param [in] u8Length Random number length(in word). + ** TRNG generates two random numbers(2 words) at one time. + ** u8Length >= 2, both random numbers will be read. + ** u8Length < 2, only one random number will be read. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_GetRandomNum(uint32_t *pu32Random, uint8_t u8Length) +{ + if ((NULL != pu32Random) && (0u != u8Length)) + { + pu32Random[0u] = M4_TRNG->DR0; + if (u8Length >= RANDOM_NUM_LENGTH) + { + pu32Random[1u] = M4_TRNG->DR1; + } + + /* Stop TRNG generating */ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + } +} + +//@} // TrngGroup + +#endif /* DDL_TRNG_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_usart.c b/driver/src/hc32f460_usart.c new file mode 100644 index 0000000..8ad5614 --- /dev/null +++ b/driver/src/hc32f460_usart.c @@ -0,0 +1,1640 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_usart.c + ** + ** A detailed description is available at + ** @link UsartGroup USART description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of USART. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_usart.h" +#include "hc32f460_utility.h" + +#if (DDL_USART_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup UsartGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for USART Instances. */ +#define IS_VALID_USART(__USARTx__) \ +( (M4_USART1 == (__USARTx__)) || \ + (M4_USART2 == (__USARTx__)) || \ + (M4_USART3 == (__USARTx__)) || \ + (M4_USART4 == (__USARTx__))) + +/*!< Parameter valid check for USART clock prescale. */ +#define IS_VALID_USART_CLK_DIV(x) \ +( (UsartClkDiv_1 == (x)) || \ + (UsartClkDiv_4 == (x)) || \ + (UsartClkDiv_16 == (x)) || \ + (UsartClkDiv_64 == (x))) + +/*!< Parameter valid check for USART function type. */ +#define IS_VALID_USART_FUNC(x) \ +( (UsartRx == (x)) || \ + (UsartTx == (x)) || \ + (UsartCts == (x)) || \ + (UsartRxInt == (x)) || \ + (UsartTimeOut == (x)) || \ + (UsartSmartCard == (x)) || \ + (UsartSilentMode == (x)) || \ + (UsartTxEmptyInt == (x)) || \ + (UsartTimeOutInt == (x)) || \ + (UsartTxCmpltInt == (x)) || \ + (UsartParityCheck == (x)) || \ + (UsartNoiseFilter == (x)) || \ + (UsartFracBaudrate == (x)) || \ + (UsartMulProcessor == (x)) || \ + (UsartTxAndTxEmptyInt == (x))) + +/*!< Parameter valid check for USART function type. */ +#define IS_VALID_USART_STATUS(x) \ +( (UsartRxMpb == (x)) || \ + (UsartTxEmpty == (x)) || \ + (UsartFrameErr == (x)) || \ + (UsartRxNoEmpty == (x)) || \ + (UsartRxTimeOut == (x)) || \ + (UsartParityErr == (x)) || \ + (UsartOverrunErr == (x)) || \ + (UsartTxComplete == (x))) + +/*!< Parameter valid check for USART clock mode. */ +#define IS_VALID_USART_CLK_MODE(x) \ +( (UsartExtClk == (x)) || \ + (UsartIntClkCkOutput == (x)) || \ + (UsartIntClkCkNoOutput == (x))) + +/*!< Parameter valid check for USART stop bit. */ +#define IS_VALID_USART_STOP_BIT(x) \ +( (UsartOneStopBit == (x)) || \ + (UsartTwoStopBit == (x))) + +/*!< Parameter valid check for USART parity bit. */ +#define IS_VALID_USART_PARITY_BIT(x) \ +( (UsartParityOdd == (x)) || \ + (UsartParityEven == (x)) || \ + (UsartParityNone == (x))) + +/*!< Parameter valid check for USART data length. */ +#define IS_VALID_USART_DATA_LEN(x) \ +( (UsartDataBits8 == (x)) || \ + (UsartDataBits9 == (x))) + +/*!< Parameter valid check for USART data direction. */ +#define IS_VALID_USART_DATA_DIR(x) \ +( (UsartDataLsbFirst == (x)) || \ + (UsartDataMsbFirst == (x))) + +/*!< Parameter valid check for USART sample mode. */ +#define IS_VALID_USART_SAMPLE_MODE(x) \ +( (UsartSampleBit8 == (x)) || \ + (UsartSampleBit16 == (x))) + +/*!< Parameter valid check for USART sample mode. */ +#define IS_VALID_USART_HW_FLOW_MODE(x) \ +( (UsartRtsEnable == (x)) || \ + (UsartCtsEnable == (x))) + +/*!< Parameter valid check for USART detect mode. */ +#define IS_VALID_USART_SB_DETECT_MODE(x) \ +( (UsartStartBitLowLvl == (x)) || \ + (UsartStartBitFallEdge == (x))) + +/*!< Parameter valid check for USART mode. */ +#define IS_VALID_USART_MODE(x) \ +( (UsartUartMode == (x)) || \ + (UsartClkSyncMode == (x)) || \ + (UsartSmartCardMode == (x))) + +/*!< Parameter valid check for USART ETU clocks number. */ +#define IS_VALID_USART_ETU_CLK(x) \ +( (UsartScEtuClk32 == (x)) || \ + (UsartScEtuClk64 == (x)) || \ + (UsartScEtuClk128 == (x)) || \ + (UsartScEtuClk256 == (x)) || \ + (UsartScEtuClk372 == (x))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static uint32_t UsartGetClk(const M4_USART_TypeDef *USARTx); +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); +static en_result_t SetClkSyncBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); +static en_result_t SetScBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize UART mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to USART mode configure structure + ** \arg This parameter detail refer @ref stc_usart_uart_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_UART_Init(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_STOP_BIT(pstcInitCfg->enStopBit)); + DDL_ASSERT(IS_VALID_USART_PARITY_BIT(pstcInitCfg->enParity)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + DDL_ASSERT(IS_VALID_USART_DATA_LEN(pstcInitCfg->enDataLength)); + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(pstcInitCfg->enHwFlow)); + DDL_ASSERT(IS_VALID_USART_SAMPLE_MODE(pstcInitCfg->enSampleMode)); + DDL_ASSERT(IS_VALID_USART_SB_DETECT_MODE(pstcInitCfg->enDetectMode)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + /* Set USART mode */ + CR3_f.SCEN = (uint32_t)0ul; + CR1_f.MS = (uint32_t)0ul; + + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + CR1_f.M = (uint32_t)(pstcInitCfg->enDataLength); + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + CR2_f.STOP = (uint32_t)(pstcInitCfg->enStopBit); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + + switch(pstcInitCfg->enParity) + { + case UsartParityNone: + CR1_f.PCE = (uint32_t)0ul; + break; + case UsartParityEven: + CR1_f.PS = (uint32_t)0ul; + CR1_f.PCE = (uint32_t)1ul; + break; + case UsartParityOdd: + CR1_f.PS = (uint32_t)1ul; + CR1_f.PCE = (uint32_t)1ul; + break; + default: + break; + } + + CR3_f.CTSE = (uint32_t)(pstcInitCfg->enHwFlow); + CR1_f.SBS = (uint32_t)(pstcInitCfg->enDetectMode); + CR1_f.OVER8 = (uint32_t)(pstcInitCfg->enSampleMode); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Initialize clock sync mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to clock sync mode configure structure + ** \arg This parameter detail refer @ref stc_usart_clksync_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_CLKSYNC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_clksync_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(pstcInitCfg->enHwFlow)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + /* Set Clock Sync mode */ + CR3_f.SCEN = (uint32_t)0ul; + CR1_f.MS = (uint32_t)1ul; + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + CR3_f.CTSE = (uint32_t)(pstcInitCfg->enHwFlow); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize smart card mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to smart card mode configure structure + ** \arg This parameter detail refer @ref stc_usart_sc_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_SC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_sc_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + CR1_f.PCE = (uint32_t)1ul; + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + CR3_f.SCEN = (uint32_t)1ul; /* Set USART mode */ + CR3_f.BCN = (uint32_t)UsartScEtuClk372; /* ETU = 372 * CK */ + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval Ok USART is de-initialized normally + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_DeInit(M4_USART_TypeDef *USARTx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get flag status + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStatus Choose need get status's flag + ** \arg UsartParityError Parity check error + ** \arg UsartFrameError Frame error + ** \arg UsartOverRunError Overrun error + ** \arg UsartRxRegNoEmpty Rx register is no empty + ** \arg UsartTxComplete Transfer completely + ** \arg UsartTxRegNoEmpty Tx register is no empty + ** \arg UsartRxTimeOut Data receive timeout + ** \arg UsartRxDataType Data is multiple processor id or normal data. + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enStatus is invalid. + ** + ******************************************************************************/ +en_flag_status_t USART_GetStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + DDL_ASSERT(IS_VALID_USART_STATUS(enStatus)); + + return ((USARTx->SR & enStatus) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified USART status + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStatus The specified status + ** \arg UsartParityErr Parity check error + ** \arg UsartFrameErr Frame error + ** \arg UsartOverRunErr Overrun error + ** \arg UsartRxTimeOut Data receive timeout + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enStatus is invalid + ** + ******************************************************************************/ +en_result_t USART_ClearStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch (enStatus) + { + case UsartParityErr: + USARTx->CR1_f.CPE = 1ul; + break; + case UsartFrameErr: + USARTx->CR1_f.CFE = 1ul; + break; + case UsartOverrunErr: + USARTx->CR1_f.CORE = 1ul; + break; + case UsartRxTimeOut: + USARTx->CR1_f.CRTOF = 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure USART function. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enFunc USART function selection + ** \arg UsartTimeOut UART RX timeout function + ** \arg UsartTimeOutInt UART RX timeout interrupt function + ** \arg UsartRx UART RX function + ** \arg UsartTx UART TX function + ** \arg UsartSilentMode USART silent function + ** \arg UsartRxInt USART RX interrupt function + ** \arg UsartTxCmpltInt USART TX complete interrupt function + ** \arg UsartTxEmptyInt USART TX empty interrupt function + ** \arg UsartParityCheck USART Parity check function + ** \arg UsartFracBaudrate USART fractional baudrate function + ** \arg UsartNoiseFilter USART noise filter function + ** \param [in] enCmd USART functional state + ** \arg Enable Enable the specified USART function + ** \arg Disable Disable the specified USART function + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx == NULL + ** + ******************************************************************************/ +en_result_t USART_FuncCmd(M4_USART_TypeDef *USARTx, + en_usart_func_t enFunc, + en_functional_state_t enCmd) +{ + uint32_t u32Addr; + __IO stc_usart_cr1_field_t CR1_f; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enFunc) + { + case UsartRx: + USARTx->CR1_f.RE = (uint32_t)enCmd; + break; + case UsartRxInt: + USARTx->CR1_f.RIE = (uint32_t)enCmd; + break; + case UsartTx: + USARTx->CR1_f.TE = (uint32_t)enCmd; + break; + case UsartTxEmptyInt: + USARTx->CR1_f.TXEIE = (uint32_t)enCmd; + break; + case UsartTimeOut: + USARTx->CR1_f.RTOE = (uint32_t)enCmd; + break; + case UsartTimeOutInt: + USARTx->CR1_f.RTOIE = (uint32_t)enCmd; + break; + case UsartSilentMode: + USARTx->CR1_f.SLME = (uint32_t)enCmd; + break; + case UsartParityCheck: + USARTx->CR1_f.PCE = (uint32_t)enCmd; + break; + case UsartNoiseFilter: + USARTx->CR1_f.NFE = (uint32_t)enCmd; + break; + case UsartTxCmpltInt: + USARTx->CR1_f.TCIE = (uint32_t)enCmd; + break; + case UsartTxAndTxEmptyInt: + CR1_f = USARTx->CR1_f; + CR1_f.TE = (uint32_t)enCmd; + CR1_f.TXEIE = (uint32_t)enCmd; + u32Addr = (uint32_t)&CR1_f; + USARTx->CR1 = *(__IO uint32_t *)u32Addr; + break; + case UsartFracBaudrate: + USARTx->CR1_f.FBME = (uint32_t)enCmd; + break; + case UsartMulProcessor: + USARTx->CR2_f.MPE = (uint32_t)enCmd; + break; + case UsartSmartCard: + USARTx->CR3_f.SCEN = (uint32_t)enCmd; + break; + case UsartCts: + USARTx->CR3_f.CTSE = (uint32_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set USART parity bit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enParity USART parity selection + ** \arg UsartParityNone USART none parity + ** \arg UsartParityEven USART even parity + ** \arg UsartParityOdd USART odd parity + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enParity is invalid + ** + ******************************************************************************/ +en_result_t USART_SetParity(M4_USART_TypeDef *USARTx, + en_usart_parity_t enParity) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enParity) + { + case UsartParityNone: + USARTx->CR1_f.PCE = (uint32_t)0ul; + break; + case UsartParityEven: + USARTx->CR1_f.PS = (uint32_t)0ul; + USARTx->CR1_f.PCE = (uint32_t)1u; + break; + case UsartParityOdd: + USARTx->CR1_f.PS = (uint32_t)1ul; + USARTx->CR1_f.PCE = (uint32_t)1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART parity bit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartParityNone USART none parity + ** \retval UsartParityEven USART even parity + ** \retval UsartParityOdd USART odd parity + ** + ******************************************************************************/ +en_usart_parity_t USART_GetParity(M4_USART_TypeDef *USARTx) +{ + en_usart_parity_t enParity = UsartParityNone; + + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + if(0ul == USARTx->CR1_f.PCE) + { + enParity = UsartParityNone; + } + else if(0ul == USARTx->CR1_f.PS) + { + enParity = UsartParityEven; + } + else + { + enParity = UsartParityOdd; + } + + return enParity; +} + +/** + ******************************************************************************* + ** \brief Set USART over sampling. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enSampleMode USART parity selection + ** \arg UsartSampleBit16 16 Bit + ** \arg UsartSampleBit8 8 Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetOverSampling(M4_USART_TypeDef *USARTx, + en_usart_sample_mode_t enSampleMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_SAMPLE_MODE(enSampleMode)); + + USARTx->CR1_f.OVER8 = (uint32_t)enSampleMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART over sampling. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartSampleBit16 16 Bit + ** \retval UsartSampleBit8 8 Bit + ** + ******************************************************************************/ +en_usart_sample_mode_t USART_GetOverSampling(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sample_mode_t)USARTx->CR1_f.OVER8; +} + +/** + ******************************************************************************* + ** \brief Set USART data transfer direction. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDir USART data direction selection + ** \arg UsartDataLsbFirst USART data LSB first + ** \arg UsartDataMsbFirst USART data MSB first + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetTransferDirection(M4_USART_TypeDef *USARTx, + en_usart_data_dir_t enDir) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_DATA_DIR(enDir)); + + USARTx->CR1_f.ML = (uint32_t)enDir; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART data transfer direction. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartDataLsbFirst USART data LSB first + ** \retval UsartDataMsbFirst USART data MSB first + ** + ******************************************************************************/ +en_usart_data_dir_t USART_GetTransferDirection(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_data_dir_t)(USARTx->CR1_f.ML); +} + +/** + ******************************************************************************* + ** \brief Set USART data bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDataLen USART data bit length + ** \arg UsartDataBits8 8 Bit + ** \arg UsartDataBits8 9 Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetDataLength(M4_USART_TypeDef *USARTx, + en_usart_data_len_t enDataLen) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_DATA_LEN(enDataLen)); + + USARTx->CR1_f.M = (uint32_t)enDataLen; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART data bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartDataBits8 Data bit length:8 Bits + ** \retval UsartDataBits8 Data bit length:9 Bits + ** + ******************************************************************************/ +en_usart_data_len_t USART_GetDataLength(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_data_len_t)(USARTx->CR1_f.M); +} + +/** + ******************************************************************************* + ** \brief Set USART clock mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enClkMode USART clock mode selection + ** \arg UsartExtClk Select external clock source + ** \arg UsartIntClkCkOutput Select internal clock source and output clock + ** \arg UsartIntClkCkNoOutput Select internal clock source and don't output clock + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetClkMode(M4_USART_TypeDef *USARTx, + en_usart_clk_mode_t enClkMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_CLK_MODE(enClkMode)); + + USARTx->CR2_f.CLKC = (uint32_t)enClkMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartExtClk Select external clock source + ** \retval UsartIntClkCkOutput Select internal clock source and output clock + ** \retval UsartIntClkCkNoOutput Select internal clock source and don't output clock + ** + ******************************************************************************/ +en_usart_clk_mode_t USART_GetClkMode(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_clk_mode_t)(USARTx->CR2_f.CLKC); +} + +/** + ******************************************************************************* + ** \brief Set USART mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enMode USART clock mode selection + ** \arg UsartUartMode UART mode + ** \arg UsartClkSyncMode Clock sync mode + ** \arg UsartSmartCardMode Smart card mode + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enMode is invalid + ** + ******************************************************************************/ +en_result_t USART_SetMode(M4_USART_TypeDef *USARTx, + en_usart_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enMode) + { + case UsartUartMode: + USARTx->CR3_f.SCEN = (uint32_t)0ul; + USARTx->CR1_f.MS = (uint32_t)0ul; + break; + case UsartClkSyncMode: + USARTx->CR3_f.SCEN = (uint32_t)0ul; + USARTx->CR1_f.MS = (uint32_t)1ul; + break; + case UsartSmartCardMode: + USARTx->CR3_f.SCEN = (uint32_t)1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartUartMode UART mode + ** \retval UsartClkSyncMode Clock sync mode + ** \retval UsartSmartCardMode Smart card mode + ** + ******************************************************************************/ +en_usart_mode_t USART_GetMode(M4_USART_TypeDef *USARTx) +{ + en_usart_mode_t enMode; + + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + if (1ul == USARTx->CR3_f.SCEN) + { + enMode = UsartSmartCardMode; + } + else if (1ul == USARTx->CR1_f.MS) + { + enMode = UsartClkSyncMode; + } + else + { + enMode = UsartUartMode; + } + + return enMode; +} + +/** + ******************************************************************************* + ** \brief Set USART stop bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStopBit USART stop bit selection + ** \arg UsartOneStopBit 1 Stop Bit + ** \arg UsartTwoStopBits 2 Stop Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetStopBitsLength(M4_USART_TypeDef *USARTx, + en_usart_stop_bit_t enStopBit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_STOP_BIT(enStopBit)); + + USARTx->CR2_f.STOP = (uint32_t)enStopBit; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART stop bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartOneStopBit 1 Stop Bit + ** \retval UsartTwoStopBits 2 Stop Bit + ** + ******************************************************************************/ +en_usart_stop_bit_t USART_GetStopBitsLength(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_stop_bit_t)(USARTx->CR2_f.STOP); +} + +/** + ******************************************************************************* + ** \brief Set USART detect mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDetectMode USART start bit detect mode + ** \arg UsartStartBitLowLvl Start bit: RD pin low level + ** \arg UsartStartBitFallEdge Start bit: RD pin falling edge + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetSbDetectMode(M4_USART_TypeDef *USARTx, + en_usart_sb_detect_mode_t enDetectMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_SB_DETECT_MODE(enDetectMode)); + + USARTx->CR1_f.SBS = (uint32_t)enDetectMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART detect mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartStartBitLowLvl Start bit: RD pin low level + ** \retval UsartStartBitFallEdge Start bit: RD pin falling edge + ** + ******************************************************************************/ +en_usart_sb_detect_mode_t USART_GetSbDetectMode(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sb_detect_mode_t)(USARTx->CR1_f.SBS); +} + + +/** + ******************************************************************************* + ** \brief Set USART hardware flow control. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enHwFlowCtrl Hardware flow control + ** \arg UsartRtsEnable Enable RTS + ** \arg UsartCtsEnable Enable CTS + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, + en_usart_hw_flow_ctrl_t enHwFlowCtrl) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(enHwFlowCtrl)); + + USARTx->CR3_f.CTSE = (uint32_t)enHwFlowCtrl; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART hardware flow control. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartRtsEnable Enable RTS + ** \retval UsartCtsEnable Enable CTS + ** + ******************************************************************************/ +en_usart_hw_flow_ctrl_t USART_GetHwFlowCtrl(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_hw_flow_ctrl_t)(USARTx->CR3_f.CTSE); +} + +/** + ******************************************************************************* + ** \brief Set USART clock prescale. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enClkPrescale USART clock prescale + ** \arg UsartClkDiv_0 PCLK/1 + ** \arg UsartClkDiv_4 PCLK/4 + ** \arg UsartClkDiv_16 PCLK/16 + ** \arg UsartClkDiv_64 PCLK/64 + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetClockDiv(M4_USART_TypeDef *USARTx, + en_usart_clk_div_t enClkPrescale) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(enClkPrescale)); + + USARTx->PR_f.PSC = (uint32_t)enClkPrescale; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock division. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartClkDiv_0 PCLK/1 + ** \retval UsartClkDiv_4 PCLK/4 + ** \retval UsartClkDiv_16 PCLK/16 + ** \retval UsartClkDiv_64 PCLK/64 + ** + ******************************************************************************/ +en_usart_clk_div_t USART_GetClockDiv(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_clk_div_t)(USARTx->PR_f.PSC); +} + +/** + ******************************************************************************* + ** \brief Set USART ETU clocks of smart card. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enEtuClk ETU clocks of smart card + ** \arg UsartScEtuClk32 1 etu = 32/f + ** \arg UsartScEtuClk64 1 etu = 64/f + ** \arg UsartScEtuClk93 1 etu = 93/f + ** \arg UsartScEtuClk128 1 etu = 128/f + ** \arg UsartScEtuClk186 1 etu = 186/f + ** \arg UsartScEtuClk256 1 etu = 256/f + ** \arg UsartScEtuClk372 1 etu = 372/f + ** \arg UsartScEtuClk512 1 etu = 512/f + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetScEtuClk(M4_USART_TypeDef *USARTx, + en_usart_sc_etu_clk_t enEtuClk) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_ETU_CLK(enEtuClk)); + + USARTx->CR3_f.BCN = (uint32_t)enEtuClk; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set USART ETU clocks of smart card. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartScEtuClk32 1 etu = 32/f + ** \retval UsartScEtuClk64 1 etu = 64/f + ** \retval UsartScEtuClk93 1 etu = 93/f + ** \retval UsartScEtuClk128 1 etu = 128/f + ** \retval UsartScEtuClk186 1 etu = 186/f + ** \retval UsartScEtuClk256 1 etu = 256/f + ** \retval UsartScEtuClk372 1 etu = 372/f + ** \retval UsartScEtuClk512 1 etu = 512/f + ** + ******************************************************************************/ +en_usart_sc_etu_clk_t USART_GetScEtuClk(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sc_etu_clk_t)(USARTx->CR3_f.BCN); +} + +/** + ****************************************************************************** + ** \brief Write UART data buffer + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u16Data Send data + ** + ** \retval Ok Data has been successfully sent + ** + ******************************************************************************/ +en_result_t USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + USARTx->DR_f.TDR = (uint32_t)u16Data; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Read UART data buffer + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint16_t USART_RecData(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return ((uint16_t)(USARTx->DR_f.RDR)); +} + +/** + ******************************************************************************* + ** \brief Set USART baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + if(1ul == USARTx->CR3_f.SCEN) + { + enRet = SetScBaudrate(USARTx, u32Baudrate); + } + else if(1ul == USARTx->CR1_f.MS) + { + enRet = SetClkSyncBaudrate(USARTx, u32Baudrate); + } + else + { + enRet = SetUartBaudrate(USARTx, u32Baudrate); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set UART mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t B = 0ul; + uint32_t C = 0ul; + uint32_t OVER8 = 0ul; + float32_t DIV = 0.0f; + uint64_t u64Tmp = 0u; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + + if (C > 0ul) + { + B = u32Baudrate; + OVER8 = USARTx->CR1_f.OVER8; + /* FBME = 0 Calculation formula */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV = ((float)C / ((float)B * 8.0f * (2.0f - (float)OVER8))) - 1.0f; + DIV_Integer = (uint32_t)(DIV); + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B) / C) - 128 */ + /* E = (C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B)) - 1 */ + /* DIV_Fraction = (((2 - OVER8) * (DIV_Integer + 1) * 2048 * B) / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)2ul - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + 1ul) * (uint64_t)B); + DIV_Fraction = (uint32_t)(2048ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set smart card mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetScBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t B = 0ul; + uint32_t C = 0ul; + uint32_t S = 0ul; + float32_t DIV = 0.0f; + uint64_t u64Tmp = 0u; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + const uint16_t au16EtuClkCnts[] = {32u, 64u, 93u, 128u, 186u, 256u, 372u, 512u}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + + if (C > 0ul) + { + B = u32Baudrate; + S = au16EtuClkCnts[USARTx->CR3_f.BCN]; + + /* FBME = 0 Calculation formula */ + /* B = C / (2 * S * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 2 * S)) - 1 */ + DIV = ((float)C / ((float)B * (float)S * 2.0f)) - 1.0f; + DIV_Integer = (uint32_t)DIV; + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / ((2 * S) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((2 * S) * (DIV_Integer + 1) * 256 * B / C) - 128 */ + /* DIV_Fraction = ((DIV_Integer + 1) * B * S * 512 / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)DIV_Integer + 1ul) * B * S); + DIV_Fraction = (uint32_t)(512ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set synchronous clock mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetClkSyncBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t C = 0ul; + uint32_t B = 0ul; + uint64_t u64Tmp = 0u; + float32_t DIV = 0.0f; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + if (C > 0ul) + { + B = u32Baudrate; + + /* FBME = 0 Calculation formula */ + /* B = C / (4 * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 4)) - 1 */ + DIV = ((float)C / ((float)B * 4.0f)) - 1.0f; + DIV_Integer = (uint32_t)DIV; + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (4 * (DIV_Integer + 1) * 256 * B / C) - 128 */ + /* DIV_Fraction = ((DIV_Integer + 1) * B * 1024 / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)DIV_Integer + 1ul) * (uint64_t)B); + DIV_Fraction = (uint32_t)(1024ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval USART clock frequency + ** + ******************************************************************************/ +static uint32_t UsartGetClk(const M4_USART_TypeDef *USARTx) +{ + uint32_t u32PClk1 = 0ul; + uint32_t u32UartClk = 0ul; + + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + u32PClk1 = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.PCLK1S); + u32UartClk = u32PClk1 / (1ul << (2ul * USARTx->PR_f.PSC)); + + return u32UartClk; +} + +//@} // UsartGroup + +#endif /* DDL_USART_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_utility.c b/driver/src/hc32f460_utility.c new file mode 100644 index 0000000..e619d64 --- /dev/null +++ b/driver/src/hc32f460_utility.c @@ -0,0 +1,531 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_utility.c + ** + ** A detailed description is available at + ** @link DdlUtilityGroup Ddl Utility description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library Utility. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_utility.h" + +#if (DDL_UTILITY_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup DdlUtilityGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#if (DDL_PRINT_ENABLE == DDL_ON) +/*!< Parameter valid check for USART Instances. */ +#define IS_VALID_UART(x) \ +( (M4_USART1 == (x)) || \ + (M4_USART2 == (x)) || \ + (M4_USART3 == (x)) || \ + (M4_USART4 == (x))) + +#define UART_EnableClk(x) \ +do { \ + if (M4_USART1 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART1 = 0ul; \ + } \ + else if (M4_USART2 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART2 = 0ul; \ + } \ + else if (M4_USART3 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART3 = 0ul; \ + } \ + else \ + { \ + M4_MSTP->FCG1_f.USART4 = 0ul; \ + } \ +} while (0) +#endif + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static uint32_t m_u32TickStep = 0UL; +static __IO uint32_t m_u32TickCount = 0UL; + +#if (DDL_PRINT_ENABLE == DDL_ON) +static M4_USART_TypeDef *m_PrintfDevice; +static uint32_t m_u32PrintfTimeout; +#endif + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +#if (DDL_PRINT_ENABLE == DDL_ON) +/** + ******************************************************************************* + ** \brief UART transmit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] cData The data for transmitting + ** + ** \retval An en_result_t enumeration value: + ** - Ok: Send successfully + ** - ErrorTimeout: Send timeout + ** - ErrorInvalidParameter: The parameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t UartPutChar(M4_USART_TypeDef *USARTx, char cData) +{ + uint32_t u32TxEmpty; + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t u32Timeout = m_u32PrintfTimeout; + + if (NULL != USARTx) + { + /* Wait TX data register empty */ + do + { + u32Timeout--; + u32TxEmpty = USARTx->SR_f.TXE; + } while ((u32Timeout > 0ul) && (0ul == u32TxEmpty)); + + if (u32TxEmpty > 0ul) + { + USARTx->DR = (uint32_t)cData; + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set synchronous clock mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, uint32_t u32Baudrate) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + float32_t DIV; + uint64_t u64Tmp; + uint32_t DIV_Integer; + uint32_t DIV_Fraction; + uint32_t u32PClk1; + uint32_t u32UartClk; + en_result_t enRet = ErrorInvalidParameter; + + u32PClk1 = SystemCoreClock / (1ul << (M4_SYSREG->CMU_SCFGR_f.PCLK1S)); + u32UartClk = u32PClk1 / (1ul << (2ul * (USARTx->PR_f.PSC))); + + B = u32Baudrate; + C = u32UartClk; + DIV_Fraction = 0ul; + + if ((0ul != C) && (0ul != B)) + { + OVER8 = USARTx->CR1_f.OVER8; + + /* FBME = 0 Calculation formula */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV = ((float)C / ((float)B * 8.0f * (2.0f - (float)OVER8))) - 1.0f; + DIV_Integer = (uint32_t)(DIV); + + if ((DIV < 0.0f) || (DIV_Integer > 0xFFul)) + { + enRet = ErrorInvalidParameter; + } + else + { + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B) / C) - 128 */ + /* E = (C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B)) - 1 */ + /* DIV_Fraction = (((2 - OVER8) * (DIV_Integer + 1) * 2048 * B) / C) - 128 */ + u64Tmp = (2u - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + 1u) * (uint64_t)B; + DIV_Fraction = (uint32_t)(2048ul * u64Tmp/C - 128ul); + } + + USARTx->CR1_f.FBME = (DIV_Fraction > 0UL) ? 1ul : 0ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + enRet = Ok; + } + } + + return enRet; +} + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +/** + ******************************************************************************* + ** \brief Re-target _write function. + ** + ** \param [in] fd + ** \param [in] data + ** \param [in] size + ** + ** \retval int32_t + ** + ******************************************************************************/ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) + { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) + { + if (Ok != UartPutChar(m_PrintfDevice, data[i])) + { + break; + } + } + } + + return i ? i : -1; +} + +#else +/** + ******************************************************************************* + ** \brief Re-target fputc function. + ** + ** \param [in] ch + ** \param [in] f + ** + ** \retval int32_t + ** + ******************************************************************************/ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (Ok == UartPutChar(m_PrintfDevice, (char)ch)) ? ch: -1; +} +#endif + +/** + ******************************************************************************* + ** \brief Debug printf initialization function + ** + ** \param [in] UARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** \param [in] PortInit The pointer of printf port initialization function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t UART_PrintfInit(M4_USART_TypeDef *UARTx, + uint32_t u32Baudrate, + void (*PortInit)(void)) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_UART(UARTx) && (0ul != u32Baudrate) && (NULL != PortInit)) + { + /* Initialize port */ + PortInit(); + + /* Enable clock */ + UART_EnableClk(UARTx); + + /* Initialize USART */ + UARTx->CR1_f.ML = 0ul; /* LSB */ + UARTx->CR1_f.MS = 0ul; /* UART mode */ + UARTx->CR1_f.OVER8 = 1ul; /* 8bit sampling mode */ + UARTx->CR1_f.M = 0ul; /* 8 bit data length */ + UARTx->CR1_f.PCE = 0ul; /* no parity bit */ + + /* Set baudrate */ + if(Ok != SetUartBaudrate(UARTx, u32Baudrate)) + { + enRet = Error; + } + else + { + UARTx->CR2 = 0ul; /* 1 stop bit, single uart mode */ + UARTx->CR3 = 0ul; /* CTS disable, Smart Card mode disable */ + UARTx->CR1_f.TE = 1ul; /* TX enable */ + + m_PrintfDevice = UARTx; + m_u32PrintfTimeout = (SystemCoreClock / u32Baudrate); + } + } + + return enRet; +} +#endif /* DDL_PRINT_ENABLE */ + +/** + ******************************************************************************* + ** \brief Delay function, delay 1ms approximately + ** + ** \param [in] u32Cnt ms + ** + ** \retval none + ** + ******************************************************************************/ +void Ddl_Delay1ms(uint32_t u32Cnt) +{ + volatile uint32_t i; + uint32_t u32Cyc; + + u32Cyc = SystemCoreClock; + u32Cyc = u32Cyc / 10000ul; + while (u32Cnt-- > 0ul) + { + i = u32Cyc; + while (i-- > 0ul) + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief Delay function, delay 1us approximately + ** + ** \param [in] u32Cnt us + ** + ** \retval none + ** + ******************************************************************************/ +void Ddl_Delay1us(uint32_t u32Cnt) +{ + uint32_t u32Cyc; + volatile uint32_t i; + + if(SystemCoreClock > 10000000ul) + { + u32Cyc = SystemCoreClock / 10000000ul; + while(u32Cnt-- > 0ul) + { + i = u32Cyc; + while (i-- > 0ul) + { + ; + } + } + } + else + { + while(u32Cnt-- > 0ul) + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief This function Initializes the interrupt frequency of the SysTick. + ** + ** \param [in] u32Freq SysTick interrupt frequency (1 to 1000). + ** + ** \retval Ok SysTick Initializes succeed + ** \retval Error SysTick Initializes failed + ** + ******************************************************************************/ +__WEAKDEF en_result_t SysTick_Init(uint32_t u32Freq) +{ + en_result_t enRet = Error; + + if ((0UL != u32Freq) && (u32Freq <= 1000UL)) + { + m_u32TickStep = 1000UL / u32Freq; + /* Configure the SysTick interrupt */ + if (0UL == SysTick_Config(SystemCoreClock / u32Freq)) + { + enRet = Ok; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief This function provides minimum delay (in milliseconds). + ** + ** \param [in] u32Delay Delay specifies the delay time. + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Delay(uint32_t u32Delay) +{ + const uint32_t tickStart = SysTick_GetTick(); + uint32_t tickEnd; + uint32_t tickMax; + + if (m_u32TickStep != 0UL) + { + tickMax = 0xFFFFFFFFUL / m_u32TickStep * m_u32TickStep; + /* Add a freq to guarantee minimum wait */ + if ((u32Delay >= tickMax) || ((tickMax - u32Delay) < m_u32TickStep)) + { + tickEnd = tickMax; + } + else + { + tickEnd = u32Delay + m_u32TickStep; + } + + while ((SysTick_GetTick() - tickStart) < tickEnd) + { + } + } +} + +/** + ******************************************************************************* + ** \brief This function is called to increment a global variable "u32TickCount". + ** \note This variable is incremented in SysTick ISR. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_IncTick(void) +{ + m_u32TickCount += m_u32TickStep; +} + +/** + ******************************************************************************* + ** \brief Provides a tick value in millisecond. + ** + ** \param None + ** + ** \retval Tick value + ** + ******************************************************************************/ +__WEAKDEF uint32_t SysTick_GetTick(void) +{ + return m_u32TickCount; +} + +/** + ******************************************************************************* + ** \brief Suspend SysTick increment. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Suspend(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + ******************************************************************************* + ** \brief Resume SysTick increment. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Resume(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + ******************************************************************************* + ** \brief ddl assert error handle function + ** + ** \param [in] file Point to the current assert the wrong file + ** \param [in] line Point line assert the wrong file in the current + ** + ******************************************************************************/ +#ifdef __DEBUG +__WEAKDEF void Ddl_AssertHandler(uint8_t *file, int16_t line) +{ + /* Users can re-implement this function to print information */ +#if (DDL_PRINT_ENABLE == DDL_ON) + printf("Wrong parameters value: file %s on line %d\r\n", file, line); +#else + (void)file; + (void)line; +#endif + for (;;) + { + ; + } +} +#endif /* __DEBUG */ + +//@} // DdlUtilityGroup + +#endif /* DDL_UTILITY_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/hc32f460_wdt.c b/driver/src/hc32f460_wdt.c new file mode 100644 index 0000000..c4c56d9 --- /dev/null +++ b/driver/src/hc32f460_wdt.c @@ -0,0 +1,254 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_wdt.c + ** + ** A detailed description is available at + ** @link WdtGroup Watchdog Counter description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of WDT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_wdt.h" +#include "hc32f460_utility.h" + +#if (DDL_WDT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup WdtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter validity check for count cycle */ +#define IS_VALID_COUNT_CYCLE(x) \ +( (WdtCountCycle256 == (x)) || \ + (WdtCountCycle4096 == (x)) || \ + (WdtCountCycle16384 == (x)) || \ + (WdtCountCycle65536 == (x))) + +/*!< Parameter validity check for clock division */ +#define IS_VALID_CLOCK_DIV(x) \ +( (WdtPclk3Div4 == (x)) || \ + (WdtPclk3Div64 == (x)) || \ + (WdtPclk3Div128 == (x)) || \ + (WdtPclk3Div256 == (x)) || \ + (WdtPclk3Div512 == (x)) || \ + (WdtPclk3Div1024 == (x)) || \ + (WdtPclk3Div2048 == (x)) || \ + (WdtPclk3Div8192 == (x))) + +/*!< Parameter validity check for allow refresh percent range */ +#define IS_VALID_ALLOW_REFRESH_RANGE(x) \ +( (WdtRefresh100Pct == (x)) || \ + (WdtRefresh0To25Pct == (x)) || \ + (WdtRefresh25To50Pct == (x)) || \ + (WdtRefresh0To50Pct == (x)) || \ + (WdtRefresh50To75Pct == (x)) || \ + (WdtRefresh0To25PctAnd50To75Pct == (x)) || \ + (WdtRefresh25To75Pct == (x)) || \ + (WdtRefresh0To75Pct == (x)) || \ + (WdtRefresh75To100Pct == (x)) || \ + (WdtRefresh0To25PctAnd75To100Pct == (x)) || \ + (WdtRefresh25To50PctAnd75To100Pct == (x)) || \ + (WdtRefresh0To50PctAnd75To100Pct == (x)) || \ + (WdtRefresh50To100Pct == (x)) || \ + (WdtRefresh0To25PctAnd50To100Pct == (x)) || \ + (WdtRefresh25To100Pct == (x)) || \ + (WdtRefresh0To100Pct == (x))) + +/*!< Parameter validity check for event request type */ +#define IS_VALID_EVENT_REQUEST_TYPE(x) \ +( (WdtTriggerInterruptRequest == (x)) || \ + (WdtTriggerResetRequest == (x))) + +/*!< Parameter validity check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (WdtFlagCountUnderflow == (x)) || \ + (WdtFlagRefreshError == (x))) + +/*!< WDT_RR register refresh key */ +#define WDT_REFRESH_START_KEY ((uint16_t)0x0123) +#define WDT_REFRESH_END_KEY ((uint16_t)0x3210) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize WDT function + ** + ** \param [in] pstcWdtInit Pointer to WDT init configuration + ** \arg See the struct #stc_wdt_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit) +{ + en_result_t enRet = Ok; + uint32_t regTemp; + + if (NULL == pstcWdtInit) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_COUNT_CYCLE(pstcWdtInit->enCountCycle)); + DDL_ASSERT(IS_VALID_CLOCK_DIV(pstcWdtInit->enClkDiv)); + DDL_ASSERT(IS_VALID_ALLOW_REFRESH_RANGE(pstcWdtInit->enRefreshRange)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcWdtInit->enSleepModeCountEn)); + DDL_ASSERT(IS_VALID_EVENT_REQUEST_TYPE(pstcWdtInit->enRequestType)); + + /* software start mode */ + regTemp = ((((uint32_t)pstcWdtInit->enRequestType) << 31) | \ + (((uint32_t)(bool)(!pstcWdtInit->enSleepModeCountEn)) << 16) | \ + (((uint32_t)pstcWdtInit->enRefreshRange) << 8) | \ + (((uint32_t)pstcWdtInit->enClkDiv) << 4) | \ + ((uint32_t)pstcWdtInit->enCountCycle)); + /* store the new value */ + M4_WDT->CR = regTemp; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief WDT refresh counter(First refresh start count when software start) + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t WDT_RefreshCounter(void) +{ + en_result_t enRet = Ok; + + M4_WDT->RR = WDT_REFRESH_START_KEY; + M4_WDT->RR = WDT_REFRESH_END_KEY; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get WDT counter current count value + ** + ** \param [in] None + ** + ** \retval uint16_t WDT counter current count value + ** + ******************************************************************************/ +uint16_t WDT_GetCountValue(void) +{ + return ((uint16_t)M4_WDT->SR_f.CNT); +} + +/** + ******************************************************************************* + ** \brief Get WDT flag status + ** + ** \param [in] enFlag WDT flag type + ** \arg WdtFlagCountUnderflow Count underflow flag + ** \arg WdtFlagRefreshError Refresh error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t WDT_GetFlag(en_wdt_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case WdtFlagCountUnderflow: + enFlagSta = (en_flag_status_t)M4_WDT->SR_f.UDF; + break; + case WdtFlagRefreshError: + enFlagSta = (en_flag_status_t)M4_WDT->SR_f.REF; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear WDT flag status + ** + ** \param [in] enFlag WDT flag type + ** \arg WdtFlagCountUnderflow Count underflow flag + ** \arg WdtFlagRefreshError Refresh error flag + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t WDT_ClearFlag(en_wdt_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case WdtFlagCountUnderflow: + M4_WDT->SR_f.UDF = 0u; + break; + case WdtFlagRefreshError: + M4_WDT->SR_f.REF = 0u; + break; + default: + break; + } + + return enRet; +} + +//@} // WdtGroup + +#endif /* DDL_WDT_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/common/hc32_common.h b/mcu/common/hc32_common.h new file mode 100644 index 0000000..f8424c8 --- /dev/null +++ b/mcu/common/hc32_common.h @@ -0,0 +1,219 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32_common.h + ** + ** A detailed description is available at + ** @link Hc32CommonGroup Hc32 Series Comm Part description @endlink + ** + ** - 2018-10-18 CDT First version for Hc32 Series of common part. + ** + ******************************************************************************/ +#ifndef __HC32_COMMON_H__ +#define __HC32_COMMON_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include +#include +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup Hc32CommonGroup Hc32 Series Common Part(HC32COMMON) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief single precision floating point number (4 byte) + ******************************************************************************/ +typedef float float32_t; + +/** + ******************************************************************************* + ** \brief double precision floating point number (8 byte) + ******************************************************************************/ +typedef double float64_t; + +/** + ******************************************************************************* + ** \brief function pointer type to void/void function + ******************************************************************************/ +typedef void (*func_ptr_t)(void); + +/** + ******************************************************************************* + ** \brief function pointer type to void/uint8_t function + ******************************************************************************/ +typedef void (*func_ptr_arg1_t)(uint8_t); + +/** + ******************************************************************************* + ** \brief functional state + ******************************************************************************/ +typedef enum en_functional_state +{ + Disable = 0u, + Enable = 1u, +} en_functional_state_t; + +/** + ******************************************************************************* + ** \brief flag status + ******************************************************************************/ +typedef enum en_flag_status +{ + Reset = 0u, + Set = 1u, +} en_flag_status_t, en_int_status_t; + +/** + ******************************************************************************* + ** \brief generic error codes + ******************************************************************************/ +typedef enum en_result +{ + Ok = 0u, ///< No error + Error = 1u, ///< Non-specific error code + ErrorAddressAlignment = 2u, ///< Address alignment does not match + ErrorAccessRights = 3u, ///< Wrong mode (e.g. user/system) mode is set + ErrorInvalidParameter = 4u, ///< Provided parameter is not valid + ErrorOperationInProgress = 5u, ///< A conflicting or requested operation is still in progress + ErrorInvalidMode = 6u, ///< Operation not allowed in current mode + ErrorUninitialized = 7u, ///< Module (or part of it) was not initialized properly + ErrorBufferFull = 8u, ///< Circular buffer can not be written because the buffer is full + ErrorTimeout = 9u, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) + ErrorNotReady = 10u, ///< A requested final state is not reached + OperationInProgress = 11u, ///< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) +} en_result_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Device include + ******************************************************************************/ +#if defined(HC32F460) +#include "hc32f460.h" +#include "system_hc32f460.h" +#elif defined(HC32xxxx) +#include "hc32xxxx.h" +#include "system_hc32xxxx.h" +#else +#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)" +#endif + +/*! Weak and Align compiler definition */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __WEAKDEF + #define __WEAKDEF __attribute__((weak)) + #endif /* __WEAKDEF */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN __attribute__((aligned (4))) + #endif /* __ALIGN_BEGIN */ + #ifndef __NOINLINE + #define __NOINLINE __attribute__((noinline)) + #endif /* __NOINLINE */ + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif /* __UNUSED */ + #ifndef __RAM_FUNC + #define __RAM_FUNC __attribute__((long_call, section(".ramfunc"))) + /* Usage: void __RAM_FUNC foo(void) */ + #endif /* __RAM_FUNC */ +#elif defined (__ICCARM__) ///< IAR Compiler +#define __WEAKDEF __weak +#define __ALIGN_BEGIN _Pragma("data_alignment=4") +#define __NOINLINE _Pragma("optimize = no_inline") +#define __UNUSED __attribute__((unused)) +#define __RAM_FUNC __ramfunc +#elif defined (__CC_ARM) ///< ARM Compiler +#define __WEAKDEF __attribute__((weak)) +#define __ALIGN_BEGIN __align(4) +#define __NOINLINE __attribute__((noinline)) +#define __UNUSED __attribute__((unused)) +/* RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. */ +#define __RAM_FUNC +#else +#error "unsupported compiler!!" +#endif /* __GNUC__ */ + +/*! Pointer correspond to zero value */ +#if !defined (NULL) +#define NULL (0) +#endif + +/*! Memory clear */ +#define MEM_ZERO_STRUCT(x) do { \ + memset((void*)&(x), 0l, (sizeof(x))); \ + }while(0) + +/*! Decimal to BCD */ +#define DEC2BCD(x) ((((x) / 10u) << 4u) + ((x) % 10u)) + +/*! BCD to decimal */ +#define BCD2DEC(x) ((((x) >> 4u) * 10u) + ((x) & 0x0Fu)) + +/*! Returns the minimum value out of two values */ +#define MIN(x, y) ((x) < (y) ? (x) : (y)) + +/*! Returns the maximum value out of two values */ +#define MAX(x, y) ((x) > (y) ? (x) : (y)) + +/*! Returns the dimension of an array */ +#define ARRAY_SZ(X) (sizeof((X)) / sizeof((X)[0])) + +/*! Check if it is a functional state */ +#define IS_FUNCTIONAL_STATE(state) (((state) == Disable) || ((state) == Enable)) + +#define BIT_SET(value,bit) ((value) |= (bit)) + +#define BIT_CLEAR(value,bit) ((value) &= ~(bit)) + +#define BIT_READ(value,bit) ((value) & (bit)) + +#define BIT_VALUE(index) (1ul << (index)) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // Hc32CommonGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_COMMON_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/common/hc32_ddl.h b/mcu/common/hc32_ddl.h new file mode 100644 index 0000000..adee0e9 --- /dev/null +++ b/mcu/common/hc32_ddl.h @@ -0,0 +1,267 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32_ddl.h + ** + ** A detailed description is available at + ** @link Hc32DdlGroup Hc32 Series Ddl description @endlink + ** + ** - 2018-10-22 CDT First version for Hc32 Series Device Driver + ** Library. + ** + ******************************************************************************/ +#ifndef __HC32_DDL_H__ +#define __HC32_DDL_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup Hc32DdlGroup Hc32 Series Device Driver Library(HC32DDL) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Defined use device driver library */ +#if !defined (USE_DEVICE_DRIVER_LIB) +/** + ******************************************************************************* + ** \brief Comment the line below if you will not use the device driver library. + ** In this case, the application code will be based on direct access to + ** peripherals registers. + ******************************************************************************/ +/* #define USE_DEVICE_DRIVER_LIB */ +#endif /* USE_DEVICE_DRIVER_LIB */ + +/** + ******************************************************************************* + ** \brief Hc32 Series device driver library version number + ******************************************************************************/ +#define HC32_DDL_VERSION_MAIN (0x02u) ///< [31:24] main version +#define HC32_DDL_VERSION_SUB1 (0x00u) ///< [23:16] sub1 version +#define HC32_DDL_VERSION_SUB2 (0x00u) ///< [15:8] sub2 version +#define HC32_DDL_VERSION_RC (0x00u) ///< [7:0] release candidate +#define HC32_DDL_VERSION ((HC32_DDL_VERSION_MAIN << 24) | \ + (HC32_DDL_VERSION_SUB1 << 16) | \ + (HC32_DDL_VERSION_SUB2 << 8 ) | \ + (HC32_DDL_VERSION_RC)) + +/*! Use device driver library */ +#if defined (USE_DEVICE_DRIVER_LIB) +/** + ******************************************************************************* + ** \brief Include module's header file + ******************************************************************************/ +#if (DDL_ADC_ENABLE == DDL_ON) +#include "hc32f460_adc.h" +#endif /* DDL_ADC_ENABLE */ + +#if (DDL_AES_ENABLE == DDL_ON) +#include "hc32f460_aes.h" +#endif /* DDL_AES_ENABLE */ + +#if (DDL_CAN_ENABLE == DDL_ON) +#include "hc32f460_can.h" +#endif /* DDL_CAN_ENABLE */ + +#if (DDL_CLK_ENABLE == DDL_ON) +#include "hc32f460_clk.h" +#endif /* DDL_CLK_ENABLE */ + +#if (DDL_CMP_ENABLE == DDL_ON) +#include "hc32f460_cmp.h" +#endif /* DDL_CMP_ENABLE */ + +#if (DDL_CRC_ENABLE == DDL_ON) +#include "hc32f460_crc.h" +#endif /* DDL_CRC_ENABLE */ + +#if (DDL_DCU_ENABLE == DDL_ON) +#include "hc32f460_dcu.h" +#endif /* DDL_DCU_ENABLE */ + +#if (DDL_DMAC_ENABLE == DDL_ON) +#include "hc32f460_dmac.h" +#endif /* DDL_DMAC_ENABLE */ + +#if (DDL_EFM_ENABLE == DDL_ON) +#include "hc32f460_efm.h" +#endif /* DDL_EFM_ENABLE */ + +#if (DDL_EMB_ENABLE == DDL_ON) +#include "hc32f460_emb.h" +#endif /* DDL_EMB_ENABLE */ + +#if (DDL_EVENT_PORT_ENABLE == DDL_ON) +#include "hc32f460_event_port.h" +#endif /* DDL_EVENT_PORT_ENABLE */ + +#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON) +#include "hc32f460_exint_nmi_swi.h" +#endif /* DDL_EXINT_NMI_SWI_ENABLE */ + +#if (DDL_GPIO_ENABLE == DDL_ON) +#include "hc32f460_gpio.h" +#endif /* DDL_GPIO_ENABLE */ + +#if (DDL_HASH_ENABLE == DDL_ON) +#include "hc32f460_hash.h" +#endif /* DDL_HASH_ENABLE */ + +#if (DDL_I2C_ENABLE == DDL_ON) +#include "hc32f460_i2c.h" +#endif /* DDL_I2C_ENABLE */ + +#if (DDL_I2S_ENABLE == DDL_ON) +#include "hc32f460_i2s.h" +#endif /* DDL_I2S_ENABLE */ + +#if (DDL_ICG_ENABLE == DDL_ON) +#include "hc32f460_icg.h" +#endif /* DDL_ICG_ENABLE */ + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) +#include "hc32f460_interrupts.h" +#endif /* DDL_INTERRUPTS_ENABLE */ + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) +#include "hc32f460_keyscan.h" +#endif /* DDL_KEYSCAN_ENABLE */ + +#if (DDL_MPU_ENABLE == DDL_ON) +#include "hc32f460_mpu.h" +#endif /* DDL_MPU_ENABLE */ + +#if (DDL_OTS_ENABLE == DDL_ON) +#include "hc32f460_ots.h" +#endif /* DDL_OTS_ENABLE */ + +#if (DDL_PWC_ENABLE == DDL_ON) +#include "hc32f460_pwc.h" +#endif /* DDL_PWC_ENABLE */ + +#if (DDL_QSPI_ENABLE == DDL_ON) +#include "hc32f460_qspi.h" +#endif /* DDL_QSPI_ENABLE */ + +#if (DDL_RMU_ENABLE == DDL_ON) +#include "hc32f460_rmu.h" +#endif /* DDL_RMU_ENABLE */ + +#if (DDL_RTC_ENABLE == DDL_ON) +#include "hc32f460_rtc.h" +#endif /* DDL_RTC_ENABLE */ + +#if (DDL_SDIOC_ENABLE == DDL_ON) +#include "hc32f460_sdioc.h" +#endif /* DDL_SDIOC_ENABLE */ + +#if (DDL_SPI_ENABLE == DDL_ON) +#include "hc32f460_spi.h" +#endif /* DDL_SPI_ENABLE */ + +#if (DDL_SRAM_ENABLE == DDL_ON) +#include "hc32f460_sram.h" +#endif /* DDL_SRAM_ENABLE */ + +#if (DDL_SWDT_ENABLE == DDL_ON) +#include "hc32f460_swdt.h" +#endif /* DDL_SWDT_ENABLE */ + +#if (DDL_TIMER0_ENABLE == DDL_ON) +#include "hc32f460_timer0.h" +#endif /* DDL_TIMER0_ENABLE */ + +#if (DDL_TIMER4_CNT_ENABLE == DDL_ON) +#include "hc32f460_timer4_cnt.h" +#endif /* DDL_TIMER4_CNT_ENABLE */ + +#if (DDL_TIMER4_EMB_ENABLE == DDL_ON) +#include "hc32f460_timer4_emb.h" +#endif /* DDL_TIMER4_EMB_ENABLE */ + +#if (DDL_TIMER4_OCO_ENABLE == DDL_ON) +#include "hc32f460_timer4_oco.h" +#endif /* DDL_TIMER4_OCO_ENABLE */ + +#if (DDL_TIMER4_PWM_ENABLE == DDL_ON) +#include "hc32f460_timer4_pwm.h" +#endif /* DDL_TIMER4_PWM_ENABLE */ + +#if (DDL_TIMER4_SEVT_ENABLE == DDL_ON) +#include "hc32f460_timer4_sevt.h" +#endif /* DDL_TIMER4_SEVT_ENABLE */ + +#if (DDL_TIMER6_ENABLE == DDL_ON) +#include "hc32f460_timer6.h" +#endif /* DDL_TIMER6_ENABLE */ + +#if (DDL_TIMERA_ENABLE == DDL_ON) +#include "hc32f460_timera.h" +#endif /* DDL_TIMERA_ENABLE */ + +#if (DDL_TRNG_ENABLE == DDL_ON) +#include "hc32f460_trng.h" +#endif /* DDL_TRNG_ENABLE */ + +#if (DDL_USART_ENABLE == DDL_ON) +#include "hc32f460_usart.h" +#endif /* DDL_USART_ENABLE */ + +#if (DDL_USBFS_ENABLE == DDL_ON) +#include "hc32f460_usbfs.h" +#endif /* DDL_USBFS_ENABLE */ + +#if (DDL_UTILITY_ENABLE == DDL_ON) +#include "hc32f460_utility.h" +#endif /* DDL_UTILITY_ENABLE */ + +#if (DDL_WDT_ENABLE == DDL_ON) +#include "hc32f460_wdt.h" +#endif /* DDL_WDT_ENABLE */ + + +#endif /* USE_DEVICE_DRIVER_LIB */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // Hc32DdlGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_DDL_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/common/hc32f460.h b/mcu/common/hc32f460.h new file mode 100644 index 0000000..fabb78c --- /dev/null +++ b/mcu/common/hc32f460.h @@ -0,0 +1,30602 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file HC32F460.h + ** + ** Auto generate. + ** Headerfile for HC32F460 series MCU + ** + ** History: + ** + ** - 2020-12-16 1.03 First version for Device Driver Library of HC32F460 series MCU. + ** + ******************************************************************************/ + +#ifndef __HC32F460_H__ +#define __HC32F460_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Configuration of the Cortex-M4 Processor and Core Peripherals + ******************************************************************************/ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< HC32F460 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< HC32F460 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/******************************************************************************* + * Interrupt Number Definition + ******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManageFault_IRQn = -12, /* 4 MemManage Fault */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + DM_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + Int000_IRQn = 0, + Int001_IRQn = 1, + Int002_IRQn = 2, + Int003_IRQn = 3, + Int004_IRQn = 4, + Int005_IRQn = 5, + Int006_IRQn = 6, + Int007_IRQn = 7, + Int008_IRQn = 8, + Int009_IRQn = 9, + Int010_IRQn = 10, + Int011_IRQn = 11, + Int012_IRQn = 12, + Int013_IRQn = 13, + Int014_IRQn = 14, + Int015_IRQn = 15, + Int016_IRQn = 16, + Int017_IRQn = 17, + Int018_IRQn = 18, + Int019_IRQn = 19, + Int020_IRQn = 20, + Int021_IRQn = 21, + Int022_IRQn = 22, + Int023_IRQn = 23, + Int024_IRQn = 24, + Int025_IRQn = 25, + Int026_IRQn = 26, + Int027_IRQn = 27, + Int028_IRQn = 28, + Int029_IRQn = 29, + Int030_IRQn = 30, + Int031_IRQn = 31, + Int032_IRQn = 32, + Int033_IRQn = 33, + Int034_IRQn = 34, + Int035_IRQn = 35, + Int036_IRQn = 36, + Int037_IRQn = 37, + Int038_IRQn = 38, + Int039_IRQn = 39, + Int040_IRQn = 40, + Int041_IRQn = 41, + Int042_IRQn = 42, + Int043_IRQn = 43, + Int044_IRQn = 44, + Int045_IRQn = 45, + Int046_IRQn = 46, + Int047_IRQn = 47, + Int048_IRQn = 48, + Int049_IRQn = 49, + Int050_IRQn = 50, + Int051_IRQn = 51, + Int052_IRQn = 52, + Int053_IRQn = 53, + Int054_IRQn = 54, + Int055_IRQn = 55, + Int056_IRQn = 56, + Int057_IRQn = 57, + Int058_IRQn = 58, + Int059_IRQn = 59, + Int060_IRQn = 60, + Int061_IRQn = 61, + Int062_IRQn = 62, + Int063_IRQn = 63, + Int064_IRQn = 64, + Int065_IRQn = 65, + Int066_IRQn = 66, + Int067_IRQn = 67, + Int068_IRQn = 68, + Int069_IRQn = 69, + Int070_IRQn = 70, + Int071_IRQn = 71, + Int072_IRQn = 72, + Int073_IRQn = 73, + Int074_IRQn = 74, + Int075_IRQn = 75, + Int076_IRQn = 76, + Int077_IRQn = 77, + Int078_IRQn = 78, + Int079_IRQn = 79, + Int080_IRQn = 80, + Int081_IRQn = 81, + Int082_IRQn = 82, + Int083_IRQn = 83, + Int084_IRQn = 84, + Int085_IRQn = 85, + Int086_IRQn = 86, + Int087_IRQn = 87, + Int088_IRQn = 88, + Int089_IRQn = 89, + Int090_IRQn = 90, + Int091_IRQn = 91, + Int092_IRQn = 92, + Int093_IRQn = 93, + Int094_IRQn = 94, + Int095_IRQn = 95, + Int096_IRQn = 96, + Int097_IRQn = 97, + Int098_IRQn = 98, + Int099_IRQn = 99, + Int100_IRQn = 100, + Int101_IRQn = 101, + Int102_IRQn = 102, + Int103_IRQn = 103, + Int104_IRQn = 104, + Int105_IRQn = 105, + Int106_IRQn = 106, + Int107_IRQn = 107, + Int108_IRQn = 108, + Int109_IRQn = 109, + Int110_IRQn = 110, + Int111_IRQn = 111, + Int112_IRQn = 112, + Int113_IRQn = 113, + Int114_IRQn = 114, + Int115_IRQn = 115, + Int116_IRQn = 116, + Int117_IRQn = 117, + Int118_IRQn = 118, + Int119_IRQn = 119, + Int120_IRQn = 120, + Int121_IRQn = 121, + Int122_IRQn = 122, + Int123_IRQn = 123, + Int124_IRQn = 124, + Int125_IRQn = 125, + Int126_IRQn = 126, + Int127_IRQn = 127, + Int128_IRQn = 128, + Int129_IRQn = 129, + Int130_IRQn = 130, + Int131_IRQn = 131, + Int132_IRQn = 132, + Int133_IRQn = 133, + Int134_IRQn = 134, + Int135_IRQn = 135, + Int136_IRQn = 136, + Int137_IRQn = 137, + Int138_IRQn = 138, + Int139_IRQn = 139, + Int140_IRQn = 140, + Int141_IRQn = 141, + Int142_IRQn = 142, + Int143_IRQn = 143, + +}IRQn_Type; + +#include +#include + +/** + ******************************************************************************* + ** \brief Event number enumeration + ******************************************************************************/ +typedef enum en_event_src +{ + EVT_SWI_IRQ0 = 0u, + EVT_SWI_IRQ1 = 1u, + EVT_SWI_IRQ2 = 2u, + EVT_SWI_IRQ3 = 3u, + EVT_SWI_IRQ4 = 4u, + EVT_SWI_IRQ5 = 5u, + EVT_SWI_IRQ6 = 6u, + EVT_SWI_IRQ7 = 7u, + EVT_SWI_IRQ8 = 8u, + EVT_SWI_IRQ9 = 9u, + EVT_SWI_IRQ10 = 10u, + EVT_SWI_IRQ11 = 11u, + EVT_SWI_IRQ12 = 12u, + EVT_SWI_IRQ13 = 13u, + EVT_SWI_IRQ14 = 14u, + EVT_SWI_IRQ15 = 15u, + EVT_SWI_IRQ16 = 16u, + EVT_SWI_IRQ17 = 17u, + EVT_SWI_IRQ18 = 18u, + EVT_SWI_IRQ19 = 19u, + EVT_SWI_IRQ20 = 20u, + EVT_SWI_IRQ21 = 21u, + EVT_SWI_IRQ22 = 22u, + EVT_SWI_IRQ23 = 23u, + EVT_SWI_IRQ24 = 24u, + EVT_SWI_IRQ25 = 25u, + EVT_SWI_IRQ26 = 26u, + EVT_SWI_IRQ27 = 27u, + EVT_SWI_IRQ28 = 28u, + EVT_SWI_IRQ29 = 29u, + EVT_SWI_IRQ30 = 30u, + EVT_SWI_IRQ31 = 31u, + + /* External Interrupt. */ + EVT_PORT_EIRQ0 = 0u, + EVT_PORT_EIRQ1 = 1u, + EVT_PORT_EIRQ2 = 2u, + EVT_PORT_EIRQ3 = 3u, + EVT_PORT_EIRQ4 = 4u, + EVT_PORT_EIRQ5 = 5u, + EVT_PORT_EIRQ6 = 6u, + EVT_PORT_EIRQ7 = 7u, + EVT_PORT_EIRQ8 = 8u, + EVT_PORT_EIRQ9 = 9u, + EVT_PORT_EIRQ10 = 10u, + EVT_PORT_EIRQ11 = 11u, + EVT_PORT_EIRQ12 = 12u, + EVT_PORT_EIRQ13 = 13u, + EVT_PORT_EIRQ14 = 14u, + EVT_PORT_EIRQ15 = 15u, + + /* DMAC */ + EVT_DMA1_TC0 = 32u, + EVT_DMA1_TC1 = 33u, + EVT_DMA1_TC2 = 34u, + EVT_DMA1_TC3 = 35u, + EVT_DMA2_TC0 = 36u, + EVT_DMA2_TC1 = 37u, + EVT_DMA2_TC2 = 38u, + EVT_DMA2_TC3 = 39u, + EVT_DMA1_BTC0 = 40u, + EVT_DMA1_BTC1 = 41u, + EVT_DMA1_BTC2 = 42u, + EVT_DMA1_BTC3 = 43u, + EVT_DMA2_BTC0 = 44u, + EVT_DMA2_BTC1 = 45u, + EVT_DMA2_BTC2 = 46u, + EVT_DMA2_BTC3 = 47u, + + /* EFM */ + EVT_EFM_OPTEND = 52u, + + /* USB SOF */ + EVT_USBFS_SOF = 53u, + + /* DCU */ + EVT_DCU1 = 55u, + EVT_DCU2 = 56u, + EVT_DCU3 = 57u, + EVT_DCU4 = 58u, + + /* TIMER 0 */ + EVT_TMR01_GCMA = 64u, + EVT_TMR01_GCMB = 65u, + EVT_TMR02_GCMA = 66u, + EVT_TMR02_GCMB = 67u, + + /* RTC */ + EVT_RTC_ALM = 81u, + EVT_RTC_PRD = 82u, + + /* TIMER 6 */ + EVT_TMR61_GCMA = 96u, + EVT_TMR61_GCMB = 97u, + EVT_TMR61_GCMC = 98u, + EVT_TMR61_GCMD = 99u, + EVT_TMR61_GCME = 100u, + EVT_TMR61_GCMF = 101u, + EVT_TMR61_GOVF = 102u, + EVT_TMR61_GUDF = 103u, + EVT_TMR61_SCMA = 107u, + EVT_TMR61_SCMB = 108u, + EVT_TMR62_GCMA = 112u, + EVT_TMR62_GCMB = 113u, + EVT_TMR62_GCMC = 114u, + EVT_TMR62_GCMD = 115u, + EVT_TMR62_GCME = 116u, + EVT_TMR62_GCMF = 117u, + EVT_TMR62_GOVF = 118u, + EVT_TMR62_GUDF = 119u, + EVT_TMR62_SCMA = 123u, + EVT_TMR62_SCMB = 124u, + EVT_TMR63_GCMA = 128u, + EVT_TMR63_GCMB = 129u, + EVT_TMR63_GCMC = 130u, + EVT_TMR63_GCMD = 131u, + EVT_TMR63_GCME = 132u, + EVT_TMR63_GCMF = 133u, + EVT_TMR63_GOVF = 134u, + EVT_TMR63_GUDF = 135u, + EVT_TMR63_SCMA = 139u, + EVT_TMR63_SCMB = 140u, + + /* TIMER A */ + EVT_TMRA1_OVF = 256u, + EVT_TMRA1_UDF = 257u, + EVT_TMRA1_CMP = 258u, + EVT_TMRA2_OVF = 259u, + EVT_TMRA2_UDF = 260u, + EVT_TMRA2_CMP = 261u, + EVT_TMRA3_OVF = 262u, + EVT_TMRA3_UDF = 263u, + EVT_TMRA3_CMP = 264u, + EVT_TMRA4_OVF = 265u, + EVT_TMRA4_UDF = 266u, + EVT_TMRA4_CMP = 267u, + EVT_TMRA5_OVF = 268u, + EVT_TMRA5_UDF = 269u, + EVT_TMRA5_CMP = 270u, + EVT_TMRA6_OVF = 272u, + EVT_TMRA6_UDF = 273u, + EVT_TMRA6_CMP = 274u, + + /* USART */ + EVT_USART1_EI = 278u, + EVT_USART1_RI = 279u, + EVT_USART1_TI = 280u, + EVT_USART1_TCI = 281u, + EVT_USART1_RTO = 282u, + EVT_USART2_EI = 283u, + EVT_USART2_RI = 284u, + EVT_USART2_TI = 285u, + EVT_USART2_TCI = 286u, + EVT_USART2_RTO = 287u, + EVT_USART3_EI = 288u, + EVT_USART3_RI = 289u, + EVT_USART3_TI = 290u, + EVT_USART3_TCI = 291u, + EVT_USART3_RTO = 292u, + EVT_USART4_EI = 293u, + EVT_USART4_RI = 294u, + EVT_USART4_TI = 295u, + EVT_USART4_TCI = 296u, + EVT_USART4_RTO = 297u, + + /* SPI */ + EVT_SPI1_SPRI = 299u, + EVT_SPI1_SPTI = 300u, + EVT_SPI1_SPII = 301u, + EVT_SPI1_SPEI = 302u, + EVT_SPI1_SPTEND = 303u, + EVT_SPI2_SPRI = 304u, + EVT_SPI2_SPTI = 305u, + EVT_SPI2_SPII = 306u, + EVT_SPI2_SPEI = 307u, + EVT_SPI2_SPTEND = 308u, + EVT_SPI3_SPRI = 309u, + EVT_SPI3_SPTI = 310u, + EVT_SPI3_SPII = 311u, + EVT_SPI3_SPEI = 312u, + EVT_SPI3_SPTEND = 313u, + EVT_SPI4_SPRI = 314u, + EVT_SPI4_SPTI = 315u, + EVT_SPI4_SPII = 316u, + EVT_SPI4_SPEI = 317u, + EVT_SPI4_SPTEND = 318u, + + /* AOS */ + EVT_AOS_STRG = 319u, + + /* TIMER 4 */ + EVT_TMR41_SCMUH = 368u, + EVT_TMR41_SCMUL = 369u, + EVT_TMR41_SCMVH = 370u, + EVT_TMR41_SCMVL = 371u, + EVT_TMR41_SCMWH = 372u, + EVT_TMR41_SCMWL = 373u, + EVT_TMR42_SCMUH = 374u, + EVT_TMR42_SCMUL = 375u, + EVT_TMR42_SCMVH = 376u, + EVT_TMR42_SCMVL = 377u, + EVT_TMR42_SCMWH = 378u, + EVT_TMR42_SCMWL = 379u, + EVT_TMR43_SCMUH = 384u, + EVT_TMR43_SCMUL = 385u, + EVT_TMR43_SCMVH = 386u, + EVT_TMR43_SCMVL = 387u, + EVT_TMR43_SCMWH = 388u, + EVT_TMR43_SCMWL = 389u, + + /* EVENT PORT */ + EVT_EVENT_PORT1 = 394u, + EVT_EVENT_PORT2 = 395u, + EVT_EVENT_PORT3 = 396u, + EVT_EVENT_PORT4 = 397u, + + /* I2S */ + EVT_I2S1_TXIRQOUT = 400u, + EVT_I2S1_RXIRQOUT = 401u, + EVT_I2S2_TXIRQOUT = 403u, + EVT_I2S2_RXIRQOUT = 404u, + EVT_I2S3_TXIRQOUT = 406u, + EVT_I2S3_RXIRQOUT = 407u, + EVT_I2S4_TXIRQOUT = 409u, + EVT_I2S4_RXIRQOUT = 410u, + + /* COMPARATOR */ + EVT_ACMP1 = 416u, + EVT_ACMP2 = 417u, + EVT_ACMP3 = 418u, + + /* I2C */ + EVT_I2C1_RXI = 420u, + EVT_I2C1_TXI = 421u, + EVT_I2C1_TEI = 422u, + EVT_I2C1_EEI = 423u, + EVT_I2C2_RXI = 424u, + EVT_I2C2_TXI = 425u, + EVT_I2C2_TEI = 426u, + EVT_I2C2_EEI = 427u, + EVT_I2C3_RXI = 428u, + EVT_I2C3_TXI = 429u, + EVT_I2C3_TEI = 430u, + EVT_I2C3_EEI = 431u, + + /* PVD */ + EVT_PVD_PVD1 = 433u, + EVT_PVD_PVD2 = 434u, + + /* OTS */ + EVT_OTS = 435u, + + /* WDT */ + EVT_WDT_REFUDF = 439u, + + /* ADC */ + EVT_ADC1_EOCA = 448u, + EVT_ADC1_EOCB = 449u, + EVT_ADC1_CHCMP = 450u, + EVT_ADC1_SEQCMP = 451u, + EVT_ADC2_EOCA = 452u, + EVT_ADC2_EOCB = 453u, + EVT_ADC2_CHCMP = 454u, + EVT_ADC2_SEQCMP = 455u, + + /* TRNG */ + EVT_TRNG_END = 456u, + + /* SDIO */ + EVT_SDIOC1_DMAR = 480u, + EVT_SDIOC1_DMAW = 481u, + EVT_SDIOC2_DMAR = 483u, + EVT_SDIOC2_DMAW = 484u, + EVT_MAX = 511u, +}en_event_src_t; + +/** + ******************************************************************************* + ** \brief Interrupt number enumeration + ******************************************************************************/ +typedef enum en_int_src +{ + INT_SWI_IRQ0 = 0u, + INT_SWI_IRQ1 = 1u, + INT_SWI_IRQ2 = 2u, + INT_SWI_IRQ3 = 3u, + INT_SWI_IRQ4 = 4u, + INT_SWI_IRQ5 = 5u, + INT_SWI_IRQ6 = 6u, + INT_SWI_IRQ7 = 7u, + INT_SWI_IRQ8 = 8u, + INT_SWI_IRQ9 = 9u, + INT_SWI_IRQ10 = 10u, + INT_SWI_IRQ11 = 11u, + INT_SWI_IRQ12 = 12u, + INT_SWI_IRQ13 = 13u, + INT_SWI_IRQ14 = 14u, + INT_SWI_IRQ15 = 15u, + INT_SWI_IRQ16 = 16u, + INT_SWI_IRQ17 = 17u, + INT_SWI_IRQ18 = 18u, + INT_SWI_IRQ19 = 19u, + INT_SWI_IRQ20 = 20u, + INT_SWI_IRQ21 = 21u, + INT_SWI_IRQ22 = 22u, + INT_SWI_IRQ23 = 23u, + INT_SWI_IRQ24 = 24u, + INT_SWI_IRQ25 = 25u, + INT_SWI_IRQ26 = 26u, + INT_SWI_IRQ27 = 27u, + INT_SWI_IRQ28 = 28u, + INT_SWI_IRQ29 = 29u, + INT_SWI_IRQ30 = 30u, + INT_SWI_IRQ31 = 31u, + + /* External Interrupt. */ + INT_PORT_EIRQ0 = 0u, + INT_PORT_EIRQ1 = 1u, + INT_PORT_EIRQ2 = 2u, + INT_PORT_EIRQ3 = 3u, + INT_PORT_EIRQ4 = 4u, + INT_PORT_EIRQ5 = 5u, + INT_PORT_EIRQ6 = 6u, + INT_PORT_EIRQ7 = 7u, + INT_PORT_EIRQ8 = 8u, + INT_PORT_EIRQ9 = 9u, + INT_PORT_EIRQ10 = 10u, + INT_PORT_EIRQ11 = 11u, + INT_PORT_EIRQ12 = 12u, + INT_PORT_EIRQ13 = 13u, + INT_PORT_EIRQ14 = 14u, + INT_PORT_EIRQ15 = 15u, + + /* DMAC */ + INT_DMA1_TC0 = 32u, + INT_DMA1_TC1 = 33u, + INT_DMA1_TC2 = 34u, + INT_DMA1_TC3 = 35u, + INT_DMA2_TC0 = 36u, + INT_DMA2_TC1 = 37u, + INT_DMA2_TC2 = 38u, + INT_DMA2_TC3 = 39u, + INT_DMA1_BTC0 = 40u, + INT_DMA1_BTC1 = 41u, + INT_DMA1_BTC2 = 42u, + INT_DMA1_BTC3 = 43u, + INT_DMA2_BTC0 = 44u, + INT_DMA2_BTC1 = 45u, + INT_DMA2_BTC2 = 46u, + INT_DMA2_BTC3 = 47u, + INT_DMA1_ERR = 48u, + INT_DMA2_ERR = 49u, + + /* EFM */ + INT_EFM_PEERR = 50u, + INT_EFM_COLERR = 51u, + INT_EFM_OPTEND = 52u, + + /* QSPI */ + INT_QSPI_INTR = 54u, + + /* DCU */ + INT_DCU1 = 55u, + INT_DCU2 = 56u, + INT_DCU3 = 57u, + INT_DCU4 = 58u, + + /* TIMER 0 */ + INT_TMR01_GCMA = 64u, + INT_TMR01_GCMB = 65u, + INT_TMR02_GCMA = 66u, + INT_TMR02_GCMB = 67u, + + /* RTC */ + INT_RTC_ALM = 81u, + INT_RTC_PRD = 82u, + + /* XTAL32 stop */ + INT_XTAL32_STOP = 84u, + + /* XTAL stop */ + INT_XTAL_STOP = 85u, + + /* wake-up timer */ + INT_WKTM_PRD = 86u, + + /* SWDT */ + INT_SWDT_REFUDF = 87u, + + /* TIMER 6 */ + INT_TMR61_GCMA = 96u, + INT_TMR61_GCMB = 97u, + INT_TMR61_GCMC = 98u, + INT_TMR61_GCMD = 99u, + INT_TMR61_GCME = 100u, + INT_TMR61_GCMF = 101u, + INT_TMR61_GOVF = 102u, + INT_TMR61_GUDF = 103u, + INT_TMR61_GDTE = 104u, + INT_TMR61_SCMA = 107u, + INT_TMR61_SCMB = 108u, + INT_TMR62_GCMA = 112u, + INT_TMR62_GCMB = 113u, + INT_TMR62_GCMC = 114u, + INT_TMR62_GCMD = 115u, + INT_TMR62_GCME = 116u, + INT_TMR62_GCMF = 117u, + INT_TMR62_GOVF = 118u, + INT_TMR62_GUDF = 119u, + INT_TMR62_GDTE = 120u, + INT_TMR62_SCMA = 123u, + INT_TMR62_SCMB = 124u, + INT_TMR63_GCMA = 128u, + INT_TMR63_GCMB = 129u, + INT_TMR63_GCMC = 130u, + INT_TMR63_GCMD = 131u, + INT_TMR63_GCME = 132u, + INT_TMR63_GCMF = 133u, + INT_TMR63_GOVF = 134u, + INT_TMR63_GUDF = 135u, + INT_TMR63_GDTE = 136u, + INT_TMR63_SCMA = 139u, + INT_TMR63_SCMB = 140u, + + /* TIMER A */ + INT_TMRA1_OVF = 256u, + INT_TMRA1_UDF = 257u, + INT_TMRA1_CMP = 258u, + INT_TMRA2_OVF = 259u, + INT_TMRA2_UDF = 260u, + INT_TMRA2_CMP = 261u, + INT_TMRA3_OVF = 262u, + INT_TMRA3_UDF = 263u, + INT_TMRA3_CMP = 264u, + INT_TMRA4_OVF = 265u, + INT_TMRA4_UDF = 266u, + INT_TMRA4_CMP = 267u, + INT_TMRA5_OVF = 268u, + INT_TMRA5_UDF = 269u, + INT_TMRA5_CMP = 270u, + INT_TMRA6_OVF = 272u, + INT_TMRA6_UDF = 273u, + INT_TMRA6_CMP = 274u, + + /* USB FS */ + INT_USBFS_GLB = 275u, + + /* USRAT */ + INT_USART1_EI = 278u, + INT_USART1_RI = 279u, + INT_USART1_TI = 280u, + INT_USART1_TCI = 281u, + INT_USART1_RTO = 282u, + INT_USART1_WUPI = 432u, + INT_USART2_EI = 283u, + INT_USART2_RI = 284u, + INT_USART2_TI = 285u, + INT_USART2_TCI = 286u, + INT_USART2_RTO = 287u, + INT_USART3_EI = 288u, + INT_USART3_RI = 289u, + INT_USART3_TI = 290u, + INT_USART3_TCI = 291u, + INT_USART3_RTO = 292u, + INT_USART4_EI = 293u, + INT_USART4_RI = 294u, + INT_USART4_TI = 295u, + INT_USART4_TCI = 296u, + INT_USART4_RTO = 297u, + + /* SPI */ + INT_SPI1_SPRI = 299u, + INT_SPI1_SPTI = 300u, + INT_SPI1_SPII = 301u, + INT_SPI1_SPEI = 302u, + INT_SPI2_SPRI = 304u, + INT_SPI2_SPTI = 305u, + INT_SPI2_SPII = 306u, + INT_SPI2_SPEI = 307u, + INT_SPI3_SPRI = 309u, + INT_SPI3_SPTI = 310u, + INT_SPI3_SPII = 311u, + INT_SPI3_SPEI = 312u, + INT_SPI4_SPRI = 314u, + INT_SPI4_SPTI = 315u, + INT_SPI4_SPII = 316u, + INT_SPI4_SPEI = 317u, + + /* TIMER 4 */ + INT_TMR41_GCMUH = 320u, + INT_TMR41_GCMUL = 321u, + INT_TMR41_GCMVH = 322u, + INT_TMR41_GCMVL = 323u, + INT_TMR41_GCMWH = 324u, + INT_TMR41_GCMWL = 325u, + INT_TMR41_GOVF = 326u, + INT_TMR41_GUDF = 327u, + INT_TMR41_RLOU = 328u, + INT_TMR41_RLOV = 329u, + INT_TMR41_RLOW = 330u, + INT_TMR42_GCMUH = 336u, + INT_TMR42_GCMUL = 337u, + INT_TMR42_GCMVH = 338u, + INT_TMR42_GCMVL = 339u, + INT_TMR42_GCMWH = 340u, + INT_TMR42_GCMWL = 341u, + INT_TMR42_GOVF = 342u, + INT_TMR42_GUDF = 343u, + INT_TMR42_RLOU = 344u, + INT_TMR42_RLOV = 345u, + INT_TMR42_RLOW = 346u, + INT_TMR43_GCMUH = 352u, + INT_TMR43_GCMUL = 353u, + INT_TMR43_GCMVH = 354u, + INT_TMR43_GCMVL = 355u, + INT_TMR43_GCMWH = 356u, + INT_TMR43_GCMWL = 357u, + INT_TMR43_GOVF = 358u, + INT_TMR43_GUDF = 359u, + INT_TMR43_RLOU = 360u, + INT_TMR43_RLOV = 361u, + INT_TMR43_RLOW = 362u, + + /* EMB */ + INT_EMB_GR0 = 390u, + INT_EMB_GR1 = 391u, + INT_EMB_GR2 = 392u, + INT_EMB_GR3 = 393u, + + /* EVENT PORT */ + INT_EVENT_PORT1 = 394u, + INT_EVENT_PORT2 = 395u, + INT_EVENT_PORT3 = 396u, + INT_EVENT_PORT4 = 397u, + + /* I2S */ + INT_I2S1_TXIRQOUT = 400u, + INT_I2S1_RXIRQOUT = 401u, + INT_I2S1_ERRIRQOUT = 402u, + INT_I2S2_TXIRQOUT = 403u, + INT_I2S2_RXIRQOUT = 404u, + INT_I2S2_ERRIRQOUT = 405u, + INT_I2S3_TXIRQOUT = 406u, + INT_I2S3_RXIRQOUT = 407u, + INT_I2S3_ERRIRQOUT = 408u, + INT_I2S4_TXIRQOUT = 409u, + INT_I2S4_RXIRQOUT = 410u, + INT_I2S4_ERRIRQOUT = 411u, + + /* COMPARATOR */ + INT_ACMP1 = 416u, + INT_ACMP2 = 417u, + INT_ACMP3 = 418u, + + /* I2C */ + INT_I2C1_RXI = 420u, + INT_I2C1_TXI = 421u, + INT_I2C1_TEI = 422u, + INT_I2C1_EEI = 423u, + INT_I2C2_RXI = 424u, + INT_I2C2_TXI = 425u, + INT_I2C2_TEI = 426u, + INT_I2C2_EEI = 427u, + INT_I2C3_RXI = 428u, + INT_I2C3_TXI = 429u, + INT_I2C3_TEI = 430u, + INT_I2C3_EEI = 431u, + + /* PVD */ + INT_PVD_PVD1 = 433u, + INT_PVD_PVD2 = 434u, + + /* Temp. sensor */ + INT_OTS = 435u, + + /* FCM */ + INT_FCMFERRI = 436u, + INT_FCMMENDI = 437u, + INT_FCMCOVFI = 438u, + + /* WDT */ + INT_WDT_REFUDF = 439u, + + /* ADC */ + INT_ADC1_EOCA = 448u, + INT_ADC1_EOCB = 449u, + INT_ADC1_CHCMP = 450u, + INT_ADC1_SEQCMP = 451u, + INT_ADC2_EOCA = 452u, + INT_ADC2_EOCB = 453u, + INT_ADC2_CHCMP = 454u, + INT_ADC2_SEQCMP = 455u, + + /* TRNG */ + INT_TRNG_END = 456u, + + /* SDIOC */ + INT_SDIOC1_SD = 482u, + INT_SDIOC2_SD = 485u, + + /* CAN */ + INT_CAN_INT = 486u, + + INT_MAX = 511u, +}en_int_src_t; + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +typedef struct +{ + __IO uint8_t STRT : 1; + uint8_t RESERVED1 : 7; +} stc_adc_str_field_t; + +typedef struct +{ + __IO uint16_t MS : 2; + uint16_t RESERVED2 : 2; + __IO uint16_t ACCSEL : 2; + __IO uint16_t CLREN : 1; + __IO uint16_t DFMT : 1; + __IO uint16_t AVCNT : 3; + uint16_t RESERVED11 : 5; +} stc_adc_cr0_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 2; + __IO uint16_t RSCHSEL : 1; + uint16_t RESERVED3 :13; +} stc_adc_cr1_field_t; + +typedef struct +{ + __IO uint16_t TRGSELA : 3; + uint16_t RESERVED3 : 4; + __IO uint16_t TRGENA : 1; + __IO uint16_t TRGSELB : 3; + uint16_t RESERVED11 : 4; + __IO uint16_t TRGENB : 1; +} stc_adc_trgsr_field_t; + +typedef struct +{ + __IO uint16_t CHSELA16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_chselra1_field_t; + +typedef struct +{ + __IO uint16_t CHSELB16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_chselrb1_field_t; + +typedef struct +{ + __IO uint16_t AVCHSEL16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_avchselr1_field_t; + +typedef struct +{ + __IO uint16_t CH00MUX : 4; + __IO uint16_t CH01MUX : 4; + __IO uint16_t CH02MUX : 4; + __IO uint16_t CH03MUX : 4; +} stc_adc_chmuxr0_field_t; + +typedef struct +{ + __IO uint16_t CH04MUX : 4; + __IO uint16_t CH05MUX : 4; + __IO uint16_t CH06MUX : 4; + __IO uint16_t CH07MUX : 4; +} stc_adc_chmuxr1_field_t; + +typedef struct +{ + __IO uint16_t CH08MUX : 4; + __IO uint16_t CH09MUX : 4; + __IO uint16_t CH10MUX : 4; + __IO uint16_t CH11MUX : 4; +} stc_adc_chmuxr2_field_t; + +typedef struct +{ + __IO uint16_t CH12MUX : 4; + __IO uint16_t CH13MUX : 4; + __IO uint16_t CH14MUX : 4; + __IO uint16_t CH15MUX : 4; +} stc_adc_chmuxr3_field_t; + +typedef struct +{ + __IO uint8_t EOCAF : 1; + __IO uint8_t EOCBF : 1; + uint8_t RESERVED2 : 6; +} stc_adc_isr_field_t; + +typedef struct +{ + __IO uint8_t EOCAIEN : 1; + __IO uint8_t EOCBIEN : 1; + uint8_t RESERVED2 : 6; +} stc_adc_icr_field_t; + +typedef struct +{ + __IO uint16_t SYNCEN : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t SYNCMD : 3; + uint16_t RESERVED7 : 1; + __IO uint16_t SYNCDLY : 8; +} stc_adc_synccr_field_t; + +typedef struct +{ + __IO uint16_t AWDEN : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t AWDMD : 1; + uint16_t RESERVED5 : 1; + __IO uint16_t AWDSS : 2; + __IO uint16_t AWDIEN : 1; + uint16_t RESERVED9 : 7; +} stc_adc_awdcr_field_t; + +typedef struct +{ + __IO uint16_t AWDCH16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_awdchsr1_field_t; + +typedef struct +{ + __IO uint16_t AWDF16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_awdsr1_field_t; + +typedef struct +{ + __IO uint16_t PGACTL : 4; + uint16_t RESERVED4 :12; +} stc_adc_pgacr_field_t; + +typedef struct +{ + __IO uint16_t GAIN : 4; + uint16_t RESERVED4 :12; +} stc_adc_pgagsr_field_t; + +typedef struct +{ + __IO uint16_t PGAINSEL : 9; + uint16_t RESERVED9 : 7; +} stc_adc_pgainsr0_field_t; + +typedef struct +{ + __IO uint16_t PGAVSSEN : 1; + uint16_t RESERVED1 :15; +} stc_adc_pgainsr1_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 1; + uint32_t RESERVED2 :30; +} stc_aes_cr_field_t; + +typedef struct +{ + __IO uint32_t STRG : 1; + uint32_t RESERVED1 :31; +} stc_aos_int_sfttrg_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu1_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu2_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu3_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu4_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma1_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma1_trgsel3_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma2_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma_trgselrc_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmr6_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmr0_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_port_pevnttrgsr12_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_port_pevnttrgsr34_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmra_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_ots_trg_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_adc1_itrgselr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_adc2_itrgselr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :23; +} stc_aos_comtrg1_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :23; +} stc_aos_comtrg2_field_t; + +typedef struct +{ + __IO uint32_t PDIR00 : 1; + __IO uint32_t PDIR01 : 1; + __IO uint32_t PDIR02 : 1; + __IO uint32_t PDIR03 : 1; + __IO uint32_t PDIR04 : 1; + __IO uint32_t PDIR05 : 1; + __IO uint32_t PDIR06 : 1; + __IO uint32_t PDIR07 : 1; + __IO uint32_t PDIR08 : 1; + __IO uint32_t PDIR09 : 1; + __IO uint32_t PDIR10 : 1; + __IO uint32_t PDIR11 : 1; + __IO uint32_t PDIR12 : 1; + __IO uint32_t PDIR13 : 1; + __IO uint32_t PDIR14 : 1; + __IO uint32_t PDIR15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntdirr_field_t; + +typedef struct +{ + __IO uint32_t PIN00 : 1; + __IO uint32_t PIN01 : 1; + __IO uint32_t PIN02 : 1; + __IO uint32_t PIN03 : 1; + __IO uint32_t PIN04 : 1; + __IO uint32_t PIN05 : 1; + __IO uint32_t PIN06 : 1; + __IO uint32_t PIN07 : 1; + __IO uint32_t PIN08 : 1; + __IO uint32_t PIN09 : 1; + __IO uint32_t PIN10 : 1; + __IO uint32_t PIN11 : 1; + __IO uint32_t PIN12 : 1; + __IO uint32_t PIN13 : 1; + __IO uint32_t PIN14 : 1; + __IO uint32_t PIN15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntidr_field_t; + +typedef struct +{ + __IO uint32_t POUT00 : 1; + __IO uint32_t POUT01 : 1; + __IO uint32_t POUT02 : 1; + __IO uint32_t POUT03 : 1; + __IO uint32_t POUT04 : 1; + __IO uint32_t POUT05 : 1; + __IO uint32_t POUT06 : 1; + __IO uint32_t POUT07 : 1; + __IO uint32_t POUT08 : 1; + __IO uint32_t POUT09 : 1; + __IO uint32_t POUT10 : 1; + __IO uint32_t POUT11 : 1; + __IO uint32_t POUT12 : 1; + __IO uint32_t POUT13 : 1; + __IO uint32_t POUT14 : 1; + __IO uint32_t POUT15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntodr_field_t; + +typedef struct +{ + __IO uint32_t POR00 : 1; + __IO uint32_t POR01 : 1; + __IO uint32_t POR02 : 1; + __IO uint32_t POR03 : 1; + __IO uint32_t POR04 : 1; + __IO uint32_t POR05 : 1; + __IO uint32_t POR06 : 1; + __IO uint32_t POR07 : 1; + __IO uint32_t POR08 : 1; + __IO uint32_t POR09 : 1; + __IO uint32_t POR10 : 1; + __IO uint32_t POR11 : 1; + __IO uint32_t POR12 : 1; + __IO uint32_t POR13 : 1; + __IO uint32_t POR14 : 1; + __IO uint32_t POR15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntorr_field_t; + +typedef struct +{ + __IO uint32_t POS00 : 1; + __IO uint32_t POS01 : 1; + __IO uint32_t POS02 : 1; + __IO uint32_t POS03 : 1; + __IO uint32_t POS04 : 1; + __IO uint32_t POS05 : 1; + __IO uint32_t POS06 : 1; + __IO uint32_t POS07 : 1; + __IO uint32_t POS08 : 1; + __IO uint32_t POS09 : 1; + __IO uint32_t POS10 : 1; + __IO uint32_t POS11 : 1; + __IO uint32_t POS12 : 1; + __IO uint32_t POS13 : 1; + __IO uint32_t POS14 : 1; + __IO uint32_t POS15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntosr_field_t; + +typedef struct +{ + __IO uint32_t RIS00 : 1; + __IO uint32_t RIS01 : 1; + __IO uint32_t RIS02 : 1; + __IO uint32_t RIS03 : 1; + __IO uint32_t RIS04 : 1; + __IO uint32_t RIS05 : 1; + __IO uint32_t RIS06 : 1; + __IO uint32_t RIS07 : 1; + __IO uint32_t RIS08 : 1; + __IO uint32_t RIS09 : 1; + __IO uint32_t RIS10 : 1; + __IO uint32_t RIS11 : 1; + __IO uint32_t RIS12 : 1; + __IO uint32_t RIS13 : 1; + __IO uint32_t RIS14 : 1; + __IO uint32_t RIS15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntrisr_field_t; + +typedef struct +{ + __IO uint32_t FAL00 : 1; + __IO uint32_t FAL01 : 1; + __IO uint32_t FAL02 : 1; + __IO uint32_t FAL03 : 1; + __IO uint32_t FAL04 : 1; + __IO uint32_t FAL05 : 1; + __IO uint32_t FAL06 : 1; + __IO uint32_t FAL07 : 1; + __IO uint32_t FAL08 : 1; + __IO uint32_t FAL09 : 1; + __IO uint32_t FAL10 : 1; + __IO uint32_t FAL11 : 1; + __IO uint32_t FAL12 : 1; + __IO uint32_t FAL13 : 1; + __IO uint32_t FAL14 : 1; + __IO uint32_t FAL15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntfal_field_t; + +typedef struct +{ + __IO uint32_t NFEN1 : 1; + __IO uint32_t DIVS1 : 2; + uint32_t RESERVED3 : 5; + __IO uint32_t NFEN2 : 1; + __IO uint32_t DIVS2 : 2; + uint32_t RESERVED11 : 5; + __IO uint32_t NFEN3 : 1; + __IO uint32_t DIVS3 : 2; + uint32_t RESERVED19 : 5; + __IO uint32_t NFEN4 : 1; + __IO uint32_t DIVS4 : 2; + uint32_t RESERVED27 : 5; +} stc_aos_pevntnfcr_field_t; + +typedef struct +{ + __IO uint8_t BUSOFF : 1; + __IO uint8_t TACTIVE : 1; + __IO uint8_t RACTIVE : 1; + __IO uint8_t TSSS : 1; + __IO uint8_t TPSS : 1; + __IO uint8_t LBMI : 1; + __IO uint8_t LBME : 1; + __IO uint8_t RESET : 1; +} stc_can_cfg_stat_field_t; + +typedef struct +{ + __IO uint8_t TSA : 1; + __IO uint8_t TSALL : 1; + __IO uint8_t TSONE : 1; + __IO uint8_t TPA : 1; + __IO uint8_t TPE : 1; + __IO uint8_t STBY : 1; + __IO uint8_t LOM : 1; + __IO uint8_t TBSEL : 1; +} stc_can_tcmd_field_t; + +typedef struct +{ + __IO uint8_t TSSTAT : 2; + uint8_t RESERVED2 : 2; + __IO uint8_t TTBM : 1; + __IO uint8_t TSMODE : 1; + __IO uint8_t TSNEXT : 1; + uint8_t RESERVED7 : 1; +} stc_can_tctrl_field_t; + +typedef struct +{ + __IO uint8_t RSSTAT : 2; + uint8_t RESERVED2 : 1; + __IO uint8_t RBALL : 1; + __IO uint8_t RREL : 1; + __IO uint8_t ROV : 1; + __IO uint8_t ROM : 1; + __IO uint8_t SACK : 1; +} stc_can_rctrl_field_t; + +typedef struct +{ + __IO uint8_t TSFF : 1; + __IO uint8_t EIE : 1; + __IO uint8_t TSIE : 1; + __IO uint8_t TPIE : 1; + __IO uint8_t RAFIE : 1; + __IO uint8_t RFIE : 1; + __IO uint8_t ROIE : 1; + __IO uint8_t RIE : 1; +} stc_can_rtie_field_t; + +typedef struct +{ + __IO uint8_t AIF : 1; + __IO uint8_t EIF : 1; + __IO uint8_t TSIF : 1; + __IO uint8_t TPIF : 1; + __IO uint8_t RAFIF : 1; + __IO uint8_t RFIF : 1; + __IO uint8_t ROIF : 1; + __IO uint8_t RIF : 1; +} stc_can_rtif_field_t; + +typedef struct +{ + __IO uint8_t BEIF : 1; + __IO uint8_t BEIE : 1; + __IO uint8_t ALIF : 1; + __IO uint8_t ALIE : 1; + __IO uint8_t EPIF : 1; + __IO uint8_t EPIE : 1; + __IO uint8_t EPASS : 1; + __IO uint8_t EWARN : 1; +} stc_can_errint_field_t; + +typedef struct +{ + __IO uint8_t EWL : 4; + __IO uint8_t AFWL : 4; +} stc_can_limit_field_t; + +typedef struct +{ + __IO uint32_t SEG_1 : 8; + __IO uint32_t SEG_2 : 7; + uint32_t RESERVED15 : 1; + __IO uint32_t SJW : 7; + uint32_t RESERVED23 : 1; + __IO uint32_t PRESC : 8; +} stc_can_bt_field_t; + +typedef struct +{ + __IO uint8_t ALC : 5; + __IO uint8_t KOER : 3; +} stc_can_ealcap_field_t; + +typedef struct +{ + __IO uint8_t ACFADR : 4; + uint8_t RESERVED4 : 1; + __IO uint8_t SELMASK : 1; + uint8_t RESERVED6 : 2; +} stc_can_acfctrl_field_t; + +typedef struct +{ + __IO uint8_t AE_1 : 1; + __IO uint8_t AE_2 : 1; + __IO uint8_t AE_3 : 1; + __IO uint8_t AE_4 : 1; + __IO uint8_t AE_5 : 1; + __IO uint8_t AE_6 : 1; + __IO uint8_t AE_7 : 1; + __IO uint8_t AE_8 : 1; +} stc_can_acfen_field_t; + +typedef struct +{ + __IO uint32_t ACODEORAMASK :29; + __IO uint32_t AIDE : 1; + __IO uint32_t AIDEE : 1; + uint32_t RESERVED31 : 1; +} stc_can_acf_field_t; + +typedef struct +{ + __IO uint8_t TBPTR : 6; + __IO uint8_t TBF : 1; + __IO uint8_t TBE : 1; +} stc_can_tbslot_field_t; + +typedef struct +{ + __IO uint8_t TTEN : 1; + __IO uint8_t T_PRESC : 2; + __IO uint8_t TTIF : 1; + __IO uint8_t TTIE : 1; + __IO uint8_t TEIF : 1; + __IO uint8_t WTIF : 1; + __IO uint8_t WTIE : 1; +} stc_can_ttcfg_field_t; + +typedef struct +{ + __IO uint32_t REF_ID :29; + uint32_t RESERVED29 : 2; + __IO uint32_t REF_IDE : 1; +} stc_can_ref_msg_field_t; + +typedef struct +{ + __IO uint16_t TTPTR : 6; + uint16_t RESERVED6 : 2; + __IO uint16_t TTYPE : 3; + uint16_t RESERVED11 : 1; + __IO uint16_t TEW : 4; +} stc_can_trg_cfg_field_t; + +typedef struct +{ + __IO uint16_t FLTSL : 3; + uint16_t RESERVED3 : 2; + __IO uint16_t EDGSL : 2; + __IO uint16_t IEN : 1; + __IO uint16_t CVSEN : 1; + uint16_t RESERVED9 : 3; + __IO uint16_t OUTEN : 1; + __IO uint16_t INV : 1; + __IO uint16_t CMPOE : 1; + __IO uint16_t CMPON : 1; +} stc_cmp_ctrl_field_t; + +typedef struct +{ + __IO uint16_t RVSL : 4; + uint16_t RESERVED4 : 4; + __IO uint16_t CVSL : 4; + __IO uint16_t C4SL : 3; + uint16_t RESERVED15 : 1; +} stc_cmp_vltsel_field_t; + +typedef struct +{ + __IO uint16_t OMON : 1; + uint16_t RESERVED1 : 7; + __IO uint16_t CVST : 4; + uint16_t RESERVED12 : 4; +} stc_cmp_mon_field_t; + +typedef struct +{ + __IO uint16_t STB : 4; + uint16_t RESERVED4 :12; +} stc_cmp_cvsstb_field_t; + +typedef struct +{ + __IO uint16_t PRD : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cvsprd_field_t; + +typedef struct +{ + __IO uint16_t DATA : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cr_dadr1_field_t; + +typedef struct +{ + __IO uint16_t DATA : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cr_dadr2_field_t; + +typedef struct +{ + __IO uint16_t DA1EN : 1; + __IO uint16_t DA2EN : 1; + uint16_t RESERVED2 :14; +} stc_cmp_cr_dacr_field_t; + +typedef struct +{ + __IO uint16_t DA1SW : 1; + __IO uint16_t DA2SW : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t VREFSW : 1; + uint16_t RESERVED5 : 3; + __IO uint16_t WPRT : 8; +} stc_cmp_cr_rvadc_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t CRC_SEL : 1; + __IO uint32_t REFIN : 1; + __IO uint32_t REFOUT : 1; + __IO uint32_t XOROUT : 1; + uint32_t RESERVED5 :27; +} stc_crc_cr_field_t; + +typedef struct +{ + __IO uint32_t FLAG : 1; + uint32_t RESERVED1 :31; +} stc_crc_flg_field_t; + +typedef struct +{ + __IO uint32_t AUTH : 1; + __IO uint32_t REMVLOCK : 1; + __IO uint32_t SAFTYLOCK1 : 1; + __IO uint32_t SAFTYLOCK2 : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t CPUSTOP : 1; + __IO uint32_t CPUSLEEP : 1; + uint32_t RESERVED10 :22; +} stc_dbgc_mcustat_field_t; + +typedef struct +{ + __IO uint32_t EDBGRQ : 1; + __IO uint32_t RESTART : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t DIRQ : 1; + uint32_t RESERVED9 :23; +} stc_dbgc_mcuctl_field_t; + +typedef struct +{ + __IO uint32_t ERASEREQ : 1; + __IO uint32_t ERASEACK : 1; + __IO uint32_t ERASEERR : 1; + uint32_t RESERVED3 :29; +} stc_dbgc_fmcctl_field_t; + +typedef struct +{ + __IO uint32_t CDBGPWRUPREQ : 1; + __IO uint32_t CDBGPWRUPACK : 1; + uint32_t RESERVED2 :30; +} stc_dbgc_mcudbgstat_field_t; + +typedef struct +{ + __IO uint32_t SWDTSTP : 1; + __IO uint32_t WDTSTP : 1; + __IO uint32_t RTCSTP : 1; + __IO uint32_t PVD0STP : 1; + __IO uint32_t PVD1STP : 1; + __IO uint32_t PVD2STP : 1; + uint32_t RESERVED6 : 8; + __IO uint32_t TMR01STP : 1; + __IO uint32_t TMR02STP : 1; + uint32_t RESERVED16 : 4; + __IO uint32_t TMR41STP : 1; + __IO uint32_t TMR42STP : 1; + __IO uint32_t TMR43STP : 1; + __IO uint32_t TM61STP : 1; + __IO uint32_t TM62STP : 1; + __IO uint32_t TMR63STP : 1; + __IO uint32_t TMRA1STP : 1; + __IO uint32_t TMRA2STP : 1; + __IO uint32_t TMRA3STP : 1; + __IO uint32_t TMRA4STP : 1; + __IO uint32_t TMRA5STP : 1; + __IO uint32_t TMRA6STP : 1; +} stc_dbgc_mcustpctl_field_t; + +typedef struct +{ + __IO uint32_t TRACEMODE : 2; + __IO uint32_t TRACEIOEN : 1; + uint32_t RESERVED3 :29; +} stc_dbgc_mcutracectl_field_t; + +typedef struct +{ + __IO uint32_t MODE : 3; + __IO uint32_t DATASIZE : 2; + uint32_t RESERVED5 : 3; + __IO uint32_t COMP_TRG : 1; + uint32_t RESERVED9 :22; + __IO uint32_t INTEN : 1; +} stc_dcu_ctl_field_t; + +typedef struct +{ + __IO uint32_t FLAG_OP : 1; + __IO uint32_t FLAG_LS2 : 1; + __IO uint32_t FLAG_EQ2 : 1; + __IO uint32_t FLAG_GT2 : 1; + __IO uint32_t FLAG_LS1 : 1; + __IO uint32_t FLAG_EQ1 : 1; + __IO uint32_t FLAG_GT1 : 1; + uint32_t RESERVED7 :25; +} stc_dcu_flag_field_t; + +typedef struct +{ + __IO uint32_t CLR_OP : 1; + __IO uint32_t CLR_LS2 : 1; + __IO uint32_t CLR_EQ2 : 1; + __IO uint32_t CLR_GT2 : 1; + __IO uint32_t CLR_LS1 : 1; + __IO uint32_t CLR_EQ1 : 1; + __IO uint32_t CLR_GT1 : 1; + uint32_t RESERVED7 :25; +} stc_dcu_flagclr_field_t; + +typedef struct +{ + __IO uint32_t INT_OP : 1; + __IO uint32_t INT_LS2 : 1; + __IO uint32_t INT_EQ2 : 1; + __IO uint32_t INT_GT2 : 1; + __IO uint32_t INT_LS1 : 1; + __IO uint32_t INT_EQ1 : 1; + __IO uint32_t INT_GT1 : 1; + __IO uint32_t INT_WIN : 2; + uint32_t RESERVED9 :23; +} stc_dcu_intsel_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + uint32_t RESERVED1 :31; +} stc_dma_en_field_t; + +typedef struct +{ + __IO uint32_t TRNERR : 4; + uint32_t RESERVED4 :12; + __IO uint32_t REQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intstat0_field_t; + +typedef struct +{ + __IO uint32_t TC : 4; + uint32_t RESERVED4 :12; + __IO uint32_t BTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intstat1_field_t; + +typedef struct +{ + __IO uint32_t MSKTRNERR : 4; + uint32_t RESERVED4 :12; + __IO uint32_t MSKREQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intmask0_field_t; + +typedef struct +{ + __IO uint32_t MSKTC : 4; + uint32_t RESERVED4 :12; + __IO uint32_t MSKBTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intmask1_field_t; + +typedef struct +{ + __IO uint32_t CLRTRNERR : 4; + uint32_t RESERVED4 :12; + __IO uint32_t CLRREQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intclr0_field_t; + +typedef struct +{ + __IO uint32_t CLRTC : 4; + uint32_t RESERVED4 :12; + __IO uint32_t CLRBTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intclr1_field_t; + +typedef struct +{ + __IO uint32_t CHEN : 4; + uint32_t RESERVED4 :28; +} stc_dma_chen_field_t; + +typedef struct +{ + __IO uint32_t DMAACT : 1; + __IO uint32_t RCFGACT : 1; + uint32_t RESERVED2 :14; + __IO uint32_t CHACT : 4; + uint32_t RESERVED20 :12; +} stc_dma_chstat_field_t; + +typedef struct +{ + __IO uint32_t RCFGEN : 1; + __IO uint32_t RCFGLLP : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t RCFGCHS : 4; + uint32_t RESERVED12 : 4; + __IO uint32_t SARMD : 2; + __IO uint32_t DARMD : 2; + __IO uint32_t CNTMD : 2; + uint32_t RESERVED22 :10; +} stc_dma_rcfgctl_field_t; + +typedef struct +{ + __IO uint32_t BLKSIZE :10; + uint32_t RESERVED10 : 6; + __IO uint32_t CNT :16; +} stc_dma_dtctl_field_t; + +typedef struct +{ + __IO uint32_t SRPT :10; + uint32_t RESERVED10 : 6; + __IO uint32_t DRPT :10; + uint32_t RESERVED26 : 6; +} stc_dma_rpt_field_t; + +typedef struct +{ + __IO uint32_t SRPTB :10; + uint32_t RESERVED10 : 6; + __IO uint32_t DRPTB :10; + uint32_t RESERVED26 : 6; +} stc_dma_rptb_field_t; + +typedef struct +{ + __IO uint32_t SOFFSET :20; + __IO uint32_t SNSCNT :12; +} stc_dma_snseqctl_field_t; + +typedef struct +{ + __IO uint32_t SNSDIST :20; + __IO uint32_t SNSCNTB :12; +} stc_dma_snseqctlb_field_t; + +typedef struct +{ + __IO uint32_t DOFFSET :20; + __IO uint32_t DNSCNT :12; +} stc_dma_dnseqctl_field_t; + +typedef struct +{ + __IO uint32_t DNSDIST :20; + __IO uint32_t DNSCNTB :12; +} stc_dma_dnseqctlb_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t LLP :30; +} stc_dma_llp_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch0ctl_field_t; + +typedef struct +{ + __IO uint32_t BLKSIZE :10; + uint32_t RESERVED10 : 6; + __IO uint32_t CNT :16; +} stc_dma_mondtctl_field_t; + +typedef struct +{ + __IO uint32_t SRPT :10; + uint32_t RESERVED10 : 6; + __IO uint32_t DRPT :10; + uint32_t RESERVED26 : 6; +} stc_dma_monrpt_field_t; + +typedef struct +{ + __IO uint32_t SOFFSET :20; + __IO uint32_t SNSCNT :12; +} stc_dma_monsnseqctl_field_t; + +typedef struct +{ + __IO uint32_t DOFFSET :20; + __IO uint32_t DNSCNT :12; +} stc_dma_mondnseqctl_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch1ctl_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch2ctl_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch3ctl_field_t; + +typedef struct +{ + __IO uint32_t FAPRT :16; + uint32_t RESERVED16 :16; +} stc_efm_faprt_field_t; + +typedef struct +{ + __IO uint32_t FSTP : 1; + uint32_t RESERVED1 :31; +} stc_efm_fstp_field_t; + +typedef struct +{ + __IO uint32_t SLPMD : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t FLWT : 4; + __IO uint32_t LVM : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t CACHE : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t CRST : 1; + uint32_t RESERVED25 : 7; +} stc_efm_frmc_field_t; + +typedef struct +{ + __IO uint32_t PEMODE : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t PEMOD : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t BUSHLDCTL : 1; + uint32_t RESERVED9 :23; +} stc_efm_fwmc_field_t; + +typedef struct +{ + __IO uint32_t PEWERR : 1; + __IO uint32_t PEPRTERR : 1; + __IO uint32_t PGSZERR : 1; + __IO uint32_t PGMISMTCH : 1; + __IO uint32_t OPTEND : 1; + __IO uint32_t COLERR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t RDY : 1; + uint32_t RESERVED9 :23; +} stc_efm_fsr_field_t; + +typedef struct +{ + __IO uint32_t PEWERRCLR : 1; + __IO uint32_t PEPRTERRCLR : 1; + __IO uint32_t PGSZERRCLR : 1; + __IO uint32_t PGMISMTCHCLR : 1; + __IO uint32_t OPTENDCLR : 1; + __IO uint32_t COLERRCLR : 1; + uint32_t RESERVED6 :26; +} stc_efm_fsclr_field_t; + +typedef struct +{ + __IO uint32_t PEERRITE : 1; + __IO uint32_t OPTENDITE : 1; + __IO uint32_t COLERRITE : 1; + uint32_t RESERVED3 :29; +} stc_efm_fite_field_t; + +typedef struct +{ + __IO uint32_t FSWP : 1; + uint32_t RESERVED1 :31; +} stc_efm_fswp_field_t; + +typedef struct +{ + __IO uint32_t FPMTSW :19; + uint32_t RESERVED19 :13; +} stc_efm_fpmtsw_field_t; + +typedef struct +{ + __IO uint32_t FPMTEW :19; + uint32_t RESERVED19 :13; +} stc_efm_fpmtew_field_t; + +typedef struct +{ + __IO uint32_t REMPRT :16; + uint32_t RESERVED16 :16; +} stc_efm_mmf_remprt_field_t; + +typedef struct +{ + __IO uint32_t RM0SIZE : 5; + uint32_t RESERVED5 : 7; + __IO uint32_t RM0TADDR :17; + uint32_t RESERVED29 : 2; + __IO uint32_t EN0 : 1; +} stc_efm_mmf_remcr0_field_t; + +typedef struct +{ + __IO uint32_t RM1SIZE : 5; + uint32_t RESERVED5 : 7; + __IO uint32_t RM1TADDR :17; + uint32_t RESERVED29 : 2; + __IO uint32_t EN1 : 1; +} stc_efm_mmf_remcr1_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t FRANDS :14; + uint32_t RESERVED15 : 1; + __IO uint32_t FRANDFG : 1; + uint32_t RESERVED17 :15; +} stc_efm_efm_frands_field_t; + +typedef struct +{ + __IO uint32_t PORTINEN : 1; + __IO uint32_t CMPEN : 3; + uint32_t RESERVED4 : 1; + __IO uint32_t OSCSTPEN : 1; + __IO uint32_t PWMSEN : 3; + uint32_t RESERVED9 :19; + __IO uint32_t NFSEL : 2; + __IO uint32_t NFEN : 1; + __IO uint32_t INVSEL : 1; +} stc_emb_ctl_field_t; + +typedef struct +{ + __IO uint32_t PWMLV : 3; + uint32_t RESERVED3 :29; +} stc_emb_pwmlv_field_t; + +typedef struct +{ + __IO uint32_t SOE : 1; + uint32_t RESERVED1 :31; +} stc_emb_soe_field_t; + +typedef struct +{ + __IO uint32_t PORTINF : 1; + __IO uint32_t PWMSF : 1; + __IO uint32_t CMPF : 1; + __IO uint32_t OSF : 1; + __IO uint32_t PORTINST : 1; + __IO uint32_t PWMST : 1; + uint32_t RESERVED6 :26; +} stc_emb_stat_field_t; + +typedef struct +{ + __IO uint32_t PORTINFCLR : 1; + __IO uint32_t PWMSFCLR : 1; + __IO uint32_t CMPFCLR : 1; + __IO uint32_t OSFCLR : 1; + uint32_t RESERVED4 :28; +} stc_emb_statclr_field_t; + +typedef struct +{ + __IO uint32_t PORTINTEN : 1; + __IO uint32_t PWMINTEN : 1; + __IO uint32_t CMPINTEN : 1; + __IO uint32_t OSINTEN : 1; + uint32_t RESERVED4 :28; +} stc_emb_inten_field_t; + +typedef struct +{ + __IO uint32_t LVR :16; + uint32_t RESERVED16 :16; +} stc_fcm_lvr_field_t; + +typedef struct +{ + __IO uint32_t UVR :16; + uint32_t RESERVED16 :16; +} stc_fcm_uvr_field_t; + +typedef struct +{ + __IO uint32_t CNTR :16; + uint32_t RESERVED16 :16; +} stc_fcm_cntr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :31; +} stc_fcm_str_field_t; + +typedef struct +{ + __IO uint32_t MDIVS : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t MCKS : 4; + uint32_t RESERVED8 :24; +} stc_fcm_mccr_field_t; + +typedef struct +{ + __IO uint32_t RDIVS : 2; + uint32_t RESERVED2 : 1; + __IO uint32_t RCKS : 4; + __IO uint32_t INEXS : 1; + __IO uint32_t DNFS : 2; + uint32_t RESERVED10 : 2; + __IO uint32_t EDGES : 2; + uint32_t RESERVED14 : 1; + __IO uint32_t EXREFE : 1; + uint32_t RESERVED16 :16; +} stc_fcm_rccr_field_t; + +typedef struct +{ + __IO uint32_t ERRIE : 1; + __IO uint32_t MENDIE : 1; + __IO uint32_t OVFIE : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t ERRINTRS : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ERRE : 1; + uint32_t RESERVED8 :24; +} stc_fcm_rier_field_t; + +typedef struct +{ + __IO uint32_t ERRF : 1; + __IO uint32_t MENDF : 1; + __IO uint32_t OVF : 1; + uint32_t RESERVED3 :29; +} stc_fcm_sr_field_t; + +typedef struct +{ + __IO uint32_t ERRFCLR : 1; + __IO uint32_t MENDFCLR : 1; + __IO uint32_t OVFCLR : 1; + uint32_t RESERVED3 :29; +} stc_fcm_clr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t FST_GRP : 1; + uint32_t RESERVED2 :30; +} stc_hash_cr_field_t; + +typedef struct +{ + __IO uint32_t PE : 1; + __IO uint32_t SMBUS : 1; + __IO uint32_t SMBALRTEN : 1; + __IO uint32_t SMBDEFAULTEN : 1; + __IO uint32_t SMBHOSTEN : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t ENGC : 1; + __IO uint32_t RESTART : 1; + __IO uint32_t START : 1; + __IO uint32_t STOP : 1; + __IO uint32_t ACK : 1; + uint32_t RESERVED11 : 4; + __IO uint32_t SWRST : 1; + uint32_t RESERVED16 :16; +} stc_i2c_cr1_field_t; + +typedef struct +{ + __IO uint32_t STARTIE : 1; + __IO uint32_t SLADDR0IE : 1; + __IO uint32_t SLADDR1IE : 1; + __IO uint32_t TENDIE : 1; + __IO uint32_t STOPIE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t RFULLIE : 1; + __IO uint32_t TEMPTYIE : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t ARLOIE : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t NACKIE : 1; + uint32_t RESERVED13 : 1; + __IO uint32_t TMOUTIE : 1; + uint32_t RESERVED15 : 5; + __IO uint32_t GENCALLIE : 1; + __IO uint32_t SMBDEFAULTIE : 1; + __IO uint32_t SMBHOSTIE : 1; + __IO uint32_t SMBALRTIE : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_cr2_field_t; + +typedef struct +{ + __IO uint32_t TMOUTEN : 1; + __IO uint32_t LTMOUT : 1; + __IO uint32_t HTMOUT : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t FACKEN : 1; + uint32_t RESERVED8 :24; +} stc_i2c_cr3_field_t; + +typedef struct +{ + __IO uint32_t SLADDR0 :10; + uint32_t RESERVED10 : 2; + __IO uint32_t SLADDR0EN : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t ADDRMOD0 : 1; + uint32_t RESERVED16 :16; +} stc_i2c_slr0_field_t; + +typedef struct +{ + __IO uint32_t SLADDR1 :10; + uint32_t RESERVED10 : 2; + __IO uint32_t SLADDR1EN : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t ADDRMOD1 : 1; + uint32_t RESERVED16 :16; +} stc_i2c_slr1_field_t; + +typedef struct +{ + __IO uint32_t TOUTLOW :16; + __IO uint32_t TOUTHIGH :16; +} stc_i2c_sltr_field_t; + +typedef struct +{ + __IO uint32_t STARTF : 1; + __IO uint32_t SLADDR0F : 1; + __IO uint32_t SLADDR1F : 1; + __IO uint32_t TENDF : 1; + __IO uint32_t STOPF : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t RFULLF : 1; + __IO uint32_t TEMPTYF : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t ARLOF : 1; + __IO uint32_t ACKRF : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t NACKF : 1; + uint32_t RESERVED13 : 1; + __IO uint32_t TMOUTF : 1; + uint32_t RESERVED15 : 1; + __IO uint32_t MSL : 1; + __IO uint32_t BUSY : 1; + __IO uint32_t TRA : 1; + uint32_t RESERVED19 : 1; + __IO uint32_t GENCALLF : 1; + __IO uint32_t SMBDEFAULTF : 1; + __IO uint32_t SMBHOSTF : 1; + __IO uint32_t SMBALRTF : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_sr_field_t; + +typedef struct +{ + __IO uint32_t STARTFCLR : 1; + __IO uint32_t SLADDR0FCLR : 1; + __IO uint32_t SLADDR1FCLR : 1; + __IO uint32_t TENDFCLR : 1; + __IO uint32_t STOPFCLR : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t RFULLFCLR : 1; + __IO uint32_t TEMPTYFCLR : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t ARLOFCLR : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t NACKFCLR : 1; + uint32_t RESERVED13 : 1; + __IO uint32_t TMOUTFCLR : 1; + uint32_t RESERVED15 : 5; + __IO uint32_t GENCALLFCLR : 1; + __IO uint32_t SMBDEFAULTFCLR : 1; + __IO uint32_t SMBHOSTFCLR : 1; + __IO uint32_t SMBALRTFCLR : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_clr_field_t; + +typedef struct +{ + __IO uint8_t DT : 8; +} stc_i2c_dtr_field_t; + +typedef struct +{ + __IO uint8_t DR : 8; +} stc_i2c_drr_field_t; + +typedef struct +{ + __IO uint32_t SLOWW : 5; + uint32_t RESERVED5 : 3; + __IO uint32_t SHIGHW : 5; + uint32_t RESERVED13 : 3; + __IO uint32_t FREQ : 3; + uint32_t RESERVED19 :13; +} stc_i2c_ccr_field_t; + +typedef struct +{ + __IO uint32_t DNF : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t DNFEN : 1; + __IO uint32_t ANFEN : 1; + uint32_t RESERVED6 :26; +} stc_i2c_fltr_field_t; + +typedef struct +{ + __IO uint32_t TXE : 1; + __IO uint32_t TXIE : 1; + __IO uint32_t RXE : 1; + __IO uint32_t RXIE : 1; + __IO uint32_t EIE : 1; + __IO uint32_t WMS : 1; + __IO uint32_t ODD : 1; + __IO uint32_t MCKOE : 1; + __IO uint32_t TXBIRQWL : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t RXBIRQWL : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t FIFOR : 1; + __IO uint32_t CODECRC : 1; + __IO uint32_t I2SPLLSEL : 1; + __IO uint32_t SDOE : 1; + __IO uint32_t LRCKOE : 1; + __IO uint32_t CKOE : 1; + __IO uint32_t DUPLEX : 1; + __IO uint32_t CLKSEL : 1; + uint32_t RESERVED24 : 8; +} stc_i2s_ctrl_field_t; + +typedef struct +{ + __IO uint32_t TXBA : 1; + __IO uint32_t RXBA : 1; + __IO uint32_t TXBE : 1; + __IO uint32_t TXBF : 1; + __IO uint32_t RXBE : 1; + __IO uint32_t RXBF : 1; + uint32_t RESERVED6 :26; +} stc_i2s_sr_field_t; + +typedef struct +{ + __IO uint32_t TXERR : 1; + __IO uint32_t RXERR : 1; + uint32_t RESERVED2 :30; +} stc_i2s_er_field_t; + +typedef struct +{ + __IO uint32_t I2SSTD : 2; + __IO uint32_t DATLEN : 2; + __IO uint32_t CHLEN : 1; + __IO uint32_t PCMSYNC : 1; + uint32_t RESERVED6 :26; +} stc_i2s_cfgr_field_t; + +typedef struct +{ + __IO uint32_t I2SDIV : 8; + uint32_t RESERVED8 :24; +} stc_i2s_pr_field_t; + +typedef struct +{ + __IO uint32_t SWDTAUTS : 1; + __IO uint32_t SWDTITS : 1; + __IO uint32_t SWDTPERI : 2; + __IO uint32_t SWDTCKS : 4; + __IO uint32_t SWDTWDPT : 4; + __IO uint32_t SWDTSLPOFF : 1; + uint32_t RESERVED13 : 3; + __IO uint32_t WDTAUTS : 1; + __IO uint32_t WDTITS : 1; + __IO uint32_t WDTPERI : 2; + __IO uint32_t WDTCKS : 4; + __IO uint32_t WDTWDPT : 4; + __IO uint32_t WDTSLPOFF : 1; + uint32_t RESERVED29 : 3; +} stc_icg_icg0_field_t; + +typedef struct +{ + __IO uint32_t HRCFREQSEL : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t HRCSTOP : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t BOR_LEV : 2; + __IO uint32_t BORDIS : 1; + uint32_t RESERVED19 : 7; + __IO uint32_t SMPCLK : 2; + __IO uint32_t NMITRG : 1; + __IO uint32_t NMIENR : 1; + __IO uint32_t NFEN : 1; + __IO uint32_t NMIICGENA : 1; +} stc_icg_icg1_field_t; + +typedef struct +{ + __IO uint32_t NMITRG : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t NSMPCLK : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t NFEN : 1; + uint32_t RESERVED8 :24; +} stc_intc_nmicr_field_t; + +typedef struct +{ + __IO uint32_t NMIENR : 1; + __IO uint32_t SWDTENR : 1; + __IO uint32_t PVD1ENR : 1; + __IO uint32_t PVD2ENR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPENR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPENR : 1; + __IO uint32_t RECCENR : 1; + __IO uint32_t BUSMENR : 1; + __IO uint32_t WDTENR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmienr_field_t; + +typedef struct +{ + __IO uint32_t NMIFR : 1; + __IO uint32_t SWDTFR : 1; + __IO uint32_t PVD1FR : 1; + __IO uint32_t PVD2FR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPFR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPFR : 1; + __IO uint32_t RECCFR : 1; + __IO uint32_t BUSMFR : 1; + __IO uint32_t WDTFR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmifr_field_t; + +typedef struct +{ + __IO uint32_t NMICFR : 1; + __IO uint32_t SWDTCFR : 1; + __IO uint32_t PVD1CFR : 1; + __IO uint32_t PVD2CFR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPCFR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPCFR : 1; + __IO uint32_t RECCCFR : 1; + __IO uint32_t BUSMCFR : 1; + __IO uint32_t WDTCFR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmicfr_field_t; + +typedef struct +{ + __IO uint32_t EIRQTRG : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t EISMPCLK : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t EFEN : 1; + uint32_t RESERVED8 :24; +} stc_intc_eirqcr_field_t; + +typedef struct +{ + __IO uint32_t EIRQWUEN :16; + __IO uint32_t SWDTWUEN : 1; + __IO uint32_t PVD1WUEN : 1; + __IO uint32_t PVD2WUEN : 1; + __IO uint32_t CMPI0WUEN : 1; + __IO uint32_t WKTMWUEN : 1; + __IO uint32_t RTCALMWUEN : 1; + __IO uint32_t RTCPRDWUEN : 1; + __IO uint32_t TMR0WUEN : 1; + uint32_t RESERVED24 : 1; + __IO uint32_t RXWUEN : 1; + uint32_t RESERVED26 : 6; +} stc_intc_wupen_field_t; + +typedef struct +{ + __IO uint32_t EIFR0 : 1; + __IO uint32_t EIFR1 : 1; + __IO uint32_t EIFR2 : 1; + __IO uint32_t EIFR3 : 1; + __IO uint32_t EIFR4 : 1; + __IO uint32_t EIFR5 : 1; + __IO uint32_t EIFR6 : 1; + __IO uint32_t EIFR7 : 1; + __IO uint32_t EIFR8 : 1; + __IO uint32_t EIFR9 : 1; + __IO uint32_t EIFR10 : 1; + __IO uint32_t EIFR11 : 1; + __IO uint32_t EIFR12 : 1; + __IO uint32_t EIFR13 : 1; + __IO uint32_t EIFR14 : 1; + __IO uint32_t EIFR15 : 1; + uint32_t RESERVED16 :16; +} stc_intc_eifr_field_t; + +typedef struct +{ + __IO uint32_t EICFR0 : 1; + __IO uint32_t EICFR1 : 1; + __IO uint32_t EICFR2 : 1; + __IO uint32_t EICFR3 : 1; + __IO uint32_t EICFR4 : 1; + __IO uint32_t EICFR5 : 1; + __IO uint32_t EICFR6 : 1; + __IO uint32_t EICFR7 : 1; + __IO uint32_t EICFR8 : 1; + __IO uint32_t EICFR9 : 1; + __IO uint32_t EICFR10 : 1; + __IO uint32_t EICFR11 : 1; + __IO uint32_t EICFR12 : 1; + __IO uint32_t EICFR13 : 1; + __IO uint32_t EICFR14 : 1; + __IO uint32_t EICFR15 : 1; + uint32_t RESERVED16 :16; +} stc_intc_eicfr_field_t; + +typedef struct +{ + __IO uint32_t INTSEL : 9; + uint32_t RESERVED9 :23; +} stc_intc_sel_field_t; + +typedef struct +{ + __IO uint32_t VSEL0 : 1; + __IO uint32_t VSEL1 : 1; + __IO uint32_t VSEL2 : 1; + __IO uint32_t VSEL3 : 1; + __IO uint32_t VSEL4 : 1; + __IO uint32_t VSEL5 : 1; + __IO uint32_t VSEL6 : 1; + __IO uint32_t VSEL7 : 1; + __IO uint32_t VSEL8 : 1; + __IO uint32_t VSEL9 : 1; + __IO uint32_t VSEL10 : 1; + __IO uint32_t VSEL11 : 1; + __IO uint32_t VSEL12 : 1; + __IO uint32_t VSEL13 : 1; + __IO uint32_t VSEL14 : 1; + __IO uint32_t VSEL15 : 1; + __IO uint32_t VSEL16 : 1; + __IO uint32_t VSEL17 : 1; + __IO uint32_t VSEL18 : 1; + __IO uint32_t VSEL19 : 1; + __IO uint32_t VSEL20 : 1; + __IO uint32_t VSEL21 : 1; + __IO uint32_t VSEL22 : 1; + __IO uint32_t VSEL23 : 1; + __IO uint32_t VSEL24 : 1; + __IO uint32_t VSEL25 : 1; + __IO uint32_t VSEL26 : 1; + __IO uint32_t VSEL27 : 1; + __IO uint32_t VSEL28 : 1; + __IO uint32_t VSEL29 : 1; + __IO uint32_t VSEL30 : 1; + __IO uint32_t VSEL31 : 1; +} stc_intc_vssel_field_t; + +typedef struct +{ + __IO uint32_t SWIE0 : 1; + __IO uint32_t SWIE1 : 1; + __IO uint32_t SWIE2 : 1; + __IO uint32_t SWIE3 : 1; + __IO uint32_t SWIE4 : 1; + __IO uint32_t SWIE5 : 1; + __IO uint32_t SWIE6 : 1; + __IO uint32_t SWIE7 : 1; + __IO uint32_t SWIE8 : 1; + __IO uint32_t SWIE9 : 1; + __IO uint32_t SWIE10 : 1; + __IO uint32_t SWIE11 : 1; + __IO uint32_t SWIE12 : 1; + __IO uint32_t SWIE13 : 1; + __IO uint32_t SWIE14 : 1; + __IO uint32_t SWIE15 : 1; + __IO uint32_t SWIE16 : 1; + __IO uint32_t SWIE17 : 1; + __IO uint32_t SWIE18 : 1; + __IO uint32_t SWIE19 : 1; + __IO uint32_t SWIE20 : 1; + __IO uint32_t SWIE21 : 1; + __IO uint32_t SWIE22 : 1; + __IO uint32_t SWIE23 : 1; + __IO uint32_t SWIE24 : 1; + __IO uint32_t SWIE25 : 1; + __IO uint32_t SWIE26 : 1; + __IO uint32_t SWIE27 : 1; + __IO uint32_t SWIE28 : 1; + __IO uint32_t SWIE29 : 1; + __IO uint32_t SWIE30 : 1; + __IO uint32_t SWIE31 : 1; +} stc_intc_swier_field_t; + +typedef struct +{ + __IO uint32_t EVTE0 : 1; + __IO uint32_t EVTE1 : 1; + __IO uint32_t EVTE2 : 1; + __IO uint32_t EVTE3 : 1; + __IO uint32_t EVTE4 : 1; + __IO uint32_t EVTE5 : 1; + __IO uint32_t EVTE6 : 1; + __IO uint32_t EVTE7 : 1; + __IO uint32_t EVTE8 : 1; + __IO uint32_t EVTE9 : 1; + __IO uint32_t EVTE10 : 1; + __IO uint32_t EVTE11 : 1; + __IO uint32_t EVTE12 : 1; + __IO uint32_t EVTE13 : 1; + __IO uint32_t EVTE14 : 1; + __IO uint32_t EVTE15 : 1; + __IO uint32_t EVTE16 : 1; + __IO uint32_t EVTE17 : 1; + __IO uint32_t EVTE18 : 1; + __IO uint32_t EVTE19 : 1; + __IO uint32_t EVTE20 : 1; + __IO uint32_t EVTE21 : 1; + __IO uint32_t EVTE22 : 1; + __IO uint32_t EVTE23 : 1; + __IO uint32_t EVTE24 : 1; + __IO uint32_t EVTE25 : 1; + __IO uint32_t EVTE26 : 1; + __IO uint32_t EVTE27 : 1; + __IO uint32_t EVTE28 : 1; + __IO uint32_t EVTE29 : 1; + __IO uint32_t EVTE30 : 1; + __IO uint32_t EVTE31 : 1; +} stc_intc_evter_field_t; + +typedef struct +{ + __IO uint32_t IER0 : 1; + __IO uint32_t IER1 : 1; + __IO uint32_t IER2 : 1; + __IO uint32_t IER3 : 1; + __IO uint32_t IER4 : 1; + __IO uint32_t IER5 : 1; + __IO uint32_t IER6 : 1; + __IO uint32_t IER7 : 1; + __IO uint32_t IER8 : 1; + __IO uint32_t IER9 : 1; + __IO uint32_t IER10 : 1; + __IO uint32_t IER11 : 1; + __IO uint32_t IER12 : 1; + __IO uint32_t IER13 : 1; + __IO uint32_t IER14 : 1; + __IO uint32_t IER15 : 1; + __IO uint32_t IER16 : 1; + __IO uint32_t IER17 : 1; + __IO uint32_t IER18 : 1; + __IO uint32_t IER19 : 1; + __IO uint32_t IER20 : 1; + __IO uint32_t IER21 : 1; + __IO uint32_t IER22 : 1; + __IO uint32_t IER23 : 1; + __IO uint32_t IER24 : 1; + __IO uint32_t IER25 : 1; + __IO uint32_t IER26 : 1; + __IO uint32_t IER27 : 1; + __IO uint32_t IER28 : 1; + __IO uint32_t IER29 : 1; + __IO uint32_t IER30 : 1; + __IO uint32_t IER31 : 1; +} stc_intc_ier_field_t; + +typedef struct +{ + __IO uint32_t KEYINSEL :16; + __IO uint32_t KEYOUTSEL : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t CKSEL : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t T_LLEVEL : 5; + __IO uint32_t T_HIZ : 3; +} stc_keyscan_scr_field_t; + +typedef struct +{ + __IO uint32_t SEN : 1; + uint32_t RESERVED1 :31; +} stc_keyscan_ser_field_t; + +typedef struct +{ + __IO uint32_t INDEX : 3; + uint32_t RESERVED3 :29; +} stc_keyscan_ssr_field_t; + +typedef struct +{ + __IO uint32_t MPURG0SIZE : 5; + __IO uint32_t MPURG0ADDR :27; +} stc_mpu_rgd0_field_t; + +typedef struct +{ + __IO uint32_t MPURG1SIZE : 5; + __IO uint32_t MPURG1ADDR :27; +} stc_mpu_rgd1_field_t; + +typedef struct +{ + __IO uint32_t MPURG2SIZE : 5; + __IO uint32_t MPURG2ADDR :27; +} stc_mpu_rgd2_field_t; + +typedef struct +{ + __IO uint32_t MPURG3SIZE : 5; + __IO uint32_t MPURG3ADDR :27; +} stc_mpu_rgd3_field_t; + +typedef struct +{ + __IO uint32_t MPURG4SIZE : 5; + __IO uint32_t MPURG4ADDR :27; +} stc_mpu_rgd4_field_t; + +typedef struct +{ + __IO uint32_t MPURG5SIZE : 5; + __IO uint32_t MPURG5ADDR :27; +} stc_mpu_rgd5_field_t; + +typedef struct +{ + __IO uint32_t MPURG6SIZE : 5; + __IO uint32_t MPURG6ADDR :27; +} stc_mpu_rgd6_field_t; + +typedef struct +{ + __IO uint32_t MPURG7SIZE : 5; + __IO uint32_t MPURG7ADDR :27; +} stc_mpu_rgd7_field_t; + +typedef struct +{ + __IO uint32_t MPURG8SIZE : 5; + __IO uint32_t MPURG8ADDR :27; +} stc_mpu_rgd8_field_t; + +typedef struct +{ + __IO uint32_t MPURG9SIZE : 5; + __IO uint32_t MPURG9ADDR :27; +} stc_mpu_rgd9_field_t; + +typedef struct +{ + __IO uint32_t MPURG10SIZE : 5; + __IO uint32_t MPURG10ADDR :27; +} stc_mpu_rgd10_field_t; + +typedef struct +{ + __IO uint32_t MPURG11SIZE : 5; + __IO uint32_t MPURG11ADDR :27; +} stc_mpu_rgd11_field_t; + +typedef struct +{ + __IO uint32_t MPURG12SIZE : 5; + __IO uint32_t MPURG12ADDR :27; +} stc_mpu_rgd12_field_t; + +typedef struct +{ + __IO uint32_t MPURG13SIZE : 5; + __IO uint32_t MPURG13ADDR :27; +} stc_mpu_rgd13_field_t; + +typedef struct +{ + __IO uint32_t MPURG14SIZE : 5; + __IO uint32_t MPURG14ADDR :27; +} stc_mpu_rgd14_field_t; + +typedef struct +{ + __IO uint32_t MPURG15SIZE : 5; + __IO uint32_t MPURG15ADDR :27; +} stc_mpu_rgd15_field_t; + +typedef struct +{ + __IO uint32_t S2RG0RP : 1; + __IO uint32_t S2RG0WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG0E : 1; + __IO uint32_t S1RG0RP : 1; + __IO uint32_t S1RG0WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG0E : 1; + __IO uint32_t FRG0RP : 1; + __IO uint32_t FRG0WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG0E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr0_field_t; + +typedef struct +{ + __IO uint32_t S2RG1RP : 1; + __IO uint32_t S2RG1WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG1E : 1; + __IO uint32_t S1RG1RP : 1; + __IO uint32_t S1RG1WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG1E : 1; + __IO uint32_t FRG1RP : 1; + __IO uint32_t FRG1WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG1E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr1_field_t; + +typedef struct +{ + __IO uint32_t S2RG2RP : 1; + __IO uint32_t S2RG2WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG2E : 1; + __IO uint32_t S1RG2RP : 1; + __IO uint32_t S1RG2WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG2E : 1; + __IO uint32_t FRG2RP : 1; + __IO uint32_t FRG2WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG2E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr2_field_t; + +typedef struct +{ + __IO uint32_t S2RG3RP : 1; + __IO uint32_t S2RG3WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG3E : 1; + __IO uint32_t S1RG3RP : 1; + __IO uint32_t S1RG3WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG3E : 1; + __IO uint32_t FRG3RP : 1; + __IO uint32_t FRG3WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG3E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr3_field_t; + +typedef struct +{ + __IO uint32_t S2RG4RP : 1; + __IO uint32_t S2RG4WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG4E : 1; + __IO uint32_t S1RG4RP : 1; + __IO uint32_t S1RG4WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG4E : 1; + __IO uint32_t FRG4RP : 1; + __IO uint32_t FRG4WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG4E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr4_field_t; + +typedef struct +{ + __IO uint32_t S2RG5RP : 1; + __IO uint32_t S2RG5WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG5E : 1; + __IO uint32_t S1RG5RP : 1; + __IO uint32_t S1RG5WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG5E : 1; + __IO uint32_t FRG5RP : 1; + __IO uint32_t FRG5WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG5E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr5_field_t; + +typedef struct +{ + __IO uint32_t S2RG6RP : 1; + __IO uint32_t S2RG6WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG6E : 1; + __IO uint32_t S1RG6RP : 1; + __IO uint32_t S1RG6WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG6E : 1; + __IO uint32_t FRG6RP : 1; + __IO uint32_t FRG6WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG6E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr6_field_t; + +typedef struct +{ + __IO uint32_t S2RG7RP : 1; + __IO uint32_t S2RG7WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG7E : 1; + __IO uint32_t S1RG7RP : 1; + __IO uint32_t S1RG7WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG7E : 1; + __IO uint32_t FRG7RP : 1; + __IO uint32_t FRG7WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG7E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr7_field_t; + +typedef struct +{ + __IO uint32_t S2RG8RP : 1; + __IO uint32_t S2RG8WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG8E : 1; + __IO uint32_t S1RG8RP : 1; + __IO uint32_t S1RG8WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG8E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr8_field_t; + +typedef struct +{ + __IO uint32_t S2RG9RP : 1; + __IO uint32_t S2RG9WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG9E : 1; + __IO uint32_t S1RG9RP : 1; + __IO uint32_t S1RG9WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG9E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr9_field_t; + +typedef struct +{ + __IO uint32_t S2RG10RP : 1; + __IO uint32_t S2RG10WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG10E : 1; + __IO uint32_t S1RG10RP : 1; + __IO uint32_t S1RG10WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG10E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr10_field_t; + +typedef struct +{ + __IO uint32_t S2RG11RP : 1; + __IO uint32_t S2RG11WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG11E : 1; + __IO uint32_t S1RG11RP : 1; + __IO uint32_t S1RG11WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG11E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr11_field_t; + +typedef struct +{ + __IO uint32_t S2RG12RP : 1; + __IO uint32_t S2RG12WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG12E : 1; + __IO uint32_t S1RG12RP : 1; + __IO uint32_t S1RG12WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG12E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr12_field_t; + +typedef struct +{ + __IO uint32_t S2RG13RP : 1; + __IO uint32_t S2RG13WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG13E : 1; + __IO uint32_t S1RG13RP : 1; + __IO uint32_t S1RG13WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG13E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr13_field_t; + +typedef struct +{ + __IO uint32_t S2RG14RP : 1; + __IO uint32_t S2RG14WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG14E : 1; + __IO uint32_t S1RG14RP : 1; + __IO uint32_t S1RG14WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG14E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr14_field_t; + +typedef struct +{ + __IO uint32_t S2RG15RP : 1; + __IO uint32_t S2RG15WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG15E : 1; + __IO uint32_t S1RG15RP : 1; + __IO uint32_t S1RG15WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG15E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr15_field_t; + +typedef struct +{ + __IO uint32_t SMPU2BRP : 1; + __IO uint32_t SMPU2BWP : 1; + __IO uint32_t SMPU2ACT : 2; + uint32_t RESERVED4 : 3; + __IO uint32_t SMPU2E : 1; + __IO uint32_t SMPU1BRP : 1; + __IO uint32_t SMPU1BWP : 1; + __IO uint32_t SMPU1ACT : 2; + uint32_t RESERVED12 : 3; + __IO uint32_t SMPU1E : 1; + __IO uint32_t FMPUBRP : 1; + __IO uint32_t FMPUBWP : 1; + __IO uint32_t FMPUACT : 2; + uint32_t RESERVED20 : 3; + __IO uint32_t FMPUE : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_cr_field_t; + +typedef struct +{ + __IO uint32_t SMPU2EAF : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SMPU1EAF : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t FMPUEAF : 1; + uint32_t RESERVED17 :15; +} stc_mpu_sr_field_t; + +typedef struct +{ + __IO uint32_t SMPU2ECLR : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SMPU1ECLR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t FMPUECLR : 1; + uint32_t RESERVED17 :15; +} stc_mpu_eclr_field_t; + +typedef struct +{ + __IO uint32_t MPUWE : 1; + __IO uint32_t WKEY :15; + uint32_t RESERVED16 :16; +} stc_mpu_wp_field_t; + +typedef struct +{ + __IO uint32_t SRAMH : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t SRAM12 : 1; + uint32_t RESERVED5 : 3; + __IO uint32_t SRAM3 : 1; + uint32_t RESERVED9 : 1; + __IO uint32_t SRAMRET : 1; + uint32_t RESERVED11 : 3; + __IO uint32_t DMA1 : 1; + __IO uint32_t DMA2 : 1; + __IO uint32_t FCM : 1; + __IO uint32_t AOS : 1; + uint32_t RESERVED18 : 2; + __IO uint32_t AES : 1; + __IO uint32_t HASH : 1; + __IO uint32_t TRNG : 1; + __IO uint32_t CRC : 1; + __IO uint32_t DCU1 : 1; + __IO uint32_t DCU2 : 1; + __IO uint32_t DCU3 : 1; + __IO uint32_t DCU4 : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t KEY : 1; +} stc_mstp_fcg0_field_t; + +typedef struct +{ + __IO uint32_t CAN : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t QSPI : 1; + __IO uint32_t IIC1 : 1; + __IO uint32_t IIC2 : 1; + __IO uint32_t IIC3 : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t USBFS : 1; + uint32_t RESERVED9 : 1; + __IO uint32_t SDIOC1 : 1; + __IO uint32_t SDIOC2 : 1; + __IO uint32_t I2S1 : 1; + __IO uint32_t I2S2 : 1; + __IO uint32_t I2S3 : 1; + __IO uint32_t I2S4 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t SPI2 : 1; + __IO uint32_t SPI3 : 1; + __IO uint32_t SPI4 : 1; + uint32_t RESERVED20 : 4; + __IO uint32_t USART1 : 1; + __IO uint32_t USART2 : 1; + __IO uint32_t USART3 : 1; + __IO uint32_t USART4 : 1; + uint32_t RESERVED28 : 4; +} stc_mstp_fcg1_field_t; + +typedef struct +{ + __IO uint32_t TIMER0_1 : 1; + __IO uint32_t TIMER0_2 : 1; + __IO uint32_t TIMERA_1 : 1; + __IO uint32_t TIMERA_2 : 1; + __IO uint32_t TIMERA_3 : 1; + __IO uint32_t TIMERA_4 : 1; + __IO uint32_t TIMERA_5 : 1; + __IO uint32_t TIMERA_6 : 1; + __IO uint32_t TIMER4_1 : 1; + __IO uint32_t TIMER4_2 : 1; + __IO uint32_t TIMER4_3 : 1; + uint32_t RESERVED11 : 4; + __IO uint32_t EMB : 1; + __IO uint32_t TIMER6_1 : 1; + __IO uint32_t TIMER6_2 : 1; + __IO uint32_t TIMER6_3 : 1; + uint32_t RESERVED19 :13; +} stc_mstp_fcg2_field_t; + +typedef struct +{ + __IO uint32_t ADC1 : 1; + __IO uint32_t ADC2 : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t CMP : 1; + uint32_t RESERVED9 : 3; + __IO uint32_t OTS : 1; + uint32_t RESERVED13 :19; +} stc_mstp_fcg3_field_t; + +typedef struct +{ + __IO uint32_t PRT0 : 1; + uint32_t RESERVED1 :15; + __IO uint32_t FCG0PCWE :16; +} stc_mstp_fcg0pc_field_t; + +typedef struct +{ + __IO uint16_t OTSST : 1; + __IO uint16_t OTSCK : 1; + __IO uint16_t OTSIE : 1; + __IO uint16_t TSSTP : 1; + uint16_t RESERVED4 :12; +} stc_ots_ctl_field_t; + +typedef struct +{ + __IO uint32_t TSOFS : 8; + __IO uint32_t TSSLP :24; +} stc_ots_lpr_field_t; + +typedef struct +{ + __IO uint32_t DFB : 1; + __IO uint32_t SOFEN : 1; + uint32_t RESERVED2 :30; +} stc_peric_usbfs_syctlreg_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t SELMMC1 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SELMMC2 : 1; + uint32_t RESERVED4 :28; +} stc_peric_sdioc_syctlreg_field_t; + +typedef struct +{ + __IO uint16_t PIN00 : 1; + __IO uint16_t PIN01 : 1; + __IO uint16_t PIN02 : 1; + __IO uint16_t PIN03 : 1; + __IO uint16_t PIN04 : 1; + __IO uint16_t PIN05 : 1; + __IO uint16_t PIN06 : 1; + __IO uint16_t PIN07 : 1; + __IO uint16_t PIN08 : 1; + __IO uint16_t PIN09 : 1; + __IO uint16_t PIN10 : 1; + __IO uint16_t PIN11 : 1; + __IO uint16_t PIN12 : 1; + __IO uint16_t PIN13 : 1; + __IO uint16_t PIN14 : 1; + __IO uint16_t PIN15 : 1; +} stc_port_pidr_field_t; + +typedef struct +{ + __IO uint16_t POUT00 : 1; + __IO uint16_t POUT01 : 1; + __IO uint16_t POUT02 : 1; + __IO uint16_t POUT03 : 1; + __IO uint16_t POUT04 : 1; + __IO uint16_t POUT05 : 1; + __IO uint16_t POUT06 : 1; + __IO uint16_t POUT07 : 1; + __IO uint16_t POUT08 : 1; + __IO uint16_t POUT09 : 1; + __IO uint16_t POUT10 : 1; + __IO uint16_t POUT11 : 1; + __IO uint16_t POUT12 : 1; + __IO uint16_t POUT13 : 1; + __IO uint16_t POUT14 : 1; + __IO uint16_t POUT15 : 1; +} stc_port_podr_field_t; + +typedef struct +{ + __IO uint16_t POUTE00 : 1; + __IO uint16_t POUTE01 : 1; + __IO uint16_t POUTE02 : 1; + __IO uint16_t POUTE03 : 1; + __IO uint16_t POUTE04 : 1; + __IO uint16_t POUTE05 : 1; + __IO uint16_t POUTE06 : 1; + __IO uint16_t POUTE07 : 1; + __IO uint16_t POUTE08 : 1; + __IO uint16_t POUTE09 : 1; + __IO uint16_t POUTE10 : 1; + __IO uint16_t POUTE11 : 1; + __IO uint16_t POUTE12 : 1; + __IO uint16_t POUTE13 : 1; + __IO uint16_t POUTE14 : 1; + __IO uint16_t POUTE15 : 1; +} stc_port_poer_field_t; + +typedef struct +{ + __IO uint16_t POS00 : 1; + __IO uint16_t POS01 : 1; + __IO uint16_t POS02 : 1; + __IO uint16_t POS03 : 1; + __IO uint16_t POS04 : 1; + __IO uint16_t POS05 : 1; + __IO uint16_t POS06 : 1; + __IO uint16_t POS07 : 1; + __IO uint16_t POS08 : 1; + __IO uint16_t POS09 : 1; + __IO uint16_t POS10 : 1; + __IO uint16_t POS11 : 1; + __IO uint16_t POS12 : 1; + __IO uint16_t POS13 : 1; + __IO uint16_t POS14 : 1; + __IO uint16_t POS15 : 1; +} stc_port_posr_field_t; + +typedef struct +{ + __IO uint16_t POR00 : 1; + __IO uint16_t POR01 : 1; + __IO uint16_t POR02 : 1; + __IO uint16_t POR03 : 1; + __IO uint16_t POR04 : 1; + __IO uint16_t POR05 : 1; + __IO uint16_t POR06 : 1; + __IO uint16_t POR07 : 1; + __IO uint16_t POR08 : 1; + __IO uint16_t POR09 : 1; + __IO uint16_t POR10 : 1; + __IO uint16_t POR11 : 1; + __IO uint16_t POR12 : 1; + __IO uint16_t POR13 : 1; + __IO uint16_t POR14 : 1; + __IO uint16_t POR15 : 1; +} stc_port_porr_field_t; + +typedef struct +{ + __IO uint16_t POT00 : 1; + __IO uint16_t POT01 : 1; + __IO uint16_t POT02 : 1; + __IO uint16_t POT03 : 1; + __IO uint16_t POT04 : 1; + __IO uint16_t POT05 : 1; + __IO uint16_t POT06 : 1; + __IO uint16_t POT07 : 1; + __IO uint16_t POT08 : 1; + __IO uint16_t POT09 : 1; + __IO uint16_t POT10 : 1; + __IO uint16_t POT11 : 1; + __IO uint16_t POT12 : 1; + __IO uint16_t POT13 : 1; + __IO uint16_t POT14 : 1; + __IO uint16_t POT15 : 1; +} stc_port_potr_field_t; + +typedef struct +{ + __IO uint16_t PIN00 : 1; + __IO uint16_t PIN01 : 1; + __IO uint16_t PIN02 : 1; + uint16_t RESERVED3 :13; +} stc_port_pidrh_field_t; + +typedef struct +{ + __IO uint16_t POUT00 : 1; + __IO uint16_t POUT01 : 1; + __IO uint16_t POUT02 : 1; + uint16_t RESERVED3 :13; +} stc_port_podrh_field_t; + +typedef struct +{ + __IO uint16_t POUTE00 : 1; + __IO uint16_t POUTE01 : 1; + __IO uint16_t POUTE02 : 1; + uint16_t RESERVED3 :13; +} stc_port_poerh_field_t; + +typedef struct +{ + __IO uint16_t POS00 : 1; + __IO uint16_t POS01 : 1; + __IO uint16_t POS02 : 1; + uint16_t RESERVED3 :13; +} stc_port_posrh_field_t; + +typedef struct +{ + __IO uint16_t POR00 : 1; + __IO uint16_t POR01 : 1; + __IO uint16_t POR02 : 1; + uint16_t RESERVED3 :13; +} stc_port_porrh_field_t; + +typedef struct +{ + __IO uint16_t POT00 : 1; + __IO uint16_t POT01 : 1; + __IO uint16_t POT02 : 1; + uint16_t RESERVED3 :13; +} stc_port_potrh_field_t; + +typedef struct +{ + __IO uint16_t SPFE : 5; + uint16_t RESERVED5 :11; +} stc_port_pspcr_field_t; + +typedef struct +{ + __IO uint16_t BFSEL : 4; + uint16_t RESERVED4 :10; + __IO uint16_t RDWT : 2; +} stc_port_pccr_field_t; + +typedef struct +{ + __IO uint16_t PINAE : 6; + uint16_t RESERVED6 :10; +} stc_port_pinaer_field_t; + +typedef struct +{ + __IO uint16_t WE : 1; + uint16_t RESERVED1 : 7; + __IO uint16_t WP : 8; +} stc_port_pwpr_field_t; + +typedef struct +{ + __IO uint16_t POUT : 1; + __IO uint16_t POUTE : 1; + __IO uint16_t NOD : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t DRV : 2; + __IO uint16_t PUU : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t PIN : 1; + __IO uint16_t INVE : 1; + uint16_t RESERVED10 : 2; + __IO uint16_t INTE : 1; + uint16_t RESERVED13 : 1; + __IO uint16_t LTE : 1; + __IO uint16_t DDIS : 1; +} stc_port_pcr_field_t; + +typedef struct +{ + __IO uint16_t FSEL : 6; + uint16_t RESERVED6 : 2; + __IO uint16_t BFE : 1; + uint16_t RESERVED9 : 7; +} stc_port_pfsr_field_t; + +typedef struct +{ + __IO uint32_t MDSEL : 3; + __IO uint32_t PFE : 1; + __IO uint32_t PFSAE : 1; + __IO uint32_t DCOME : 1; + __IO uint32_t XIPE : 1; + __IO uint32_t SPIMD3 : 1; + __IO uint32_t IPRSL : 2; + __IO uint32_t APRSL : 2; + __IO uint32_t DPRSL : 2; + uint32_t RESERVED14 : 2; + __IO uint32_t DIV : 6; + uint32_t RESERVED22 :10; +} stc_qspi_cr_field_t; + +typedef struct +{ + __IO uint32_t SSHW : 4; + __IO uint32_t SSNW : 2; + uint32_t RESERVED6 :26; +} stc_qspi_cscr_field_t; + +typedef struct +{ + __IO uint32_t AWSL : 2; + __IO uint32_t FOUR_BIC : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t SSNHD : 1; + __IO uint32_t SSNLD : 1; + __IO uint32_t WPOL : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t DMCYCN : 4; + uint32_t RESERVED12 : 3; + __IO uint32_t DUTY : 1; + uint32_t RESERVED16 :16; +} stc_qspi_fcr_field_t; + +typedef struct +{ + __IO uint32_t BUSY : 1; + uint32_t RESERVED1 : 5; + __IO uint32_t XIPF : 1; + __IO uint32_t RAER : 1; + __IO uint32_t PFNUM : 5; + uint32_t RESERVED13 : 1; + __IO uint32_t PFFUL : 1; + __IO uint32_t PFAN : 1; + uint32_t RESERVED16 :16; +} stc_qspi_sr_field_t; + +typedef struct +{ + __IO uint32_t DCOM : 8; + uint32_t RESERVED8 :24; +} stc_qspi_dcom_field_t; + +typedef struct +{ + __IO uint32_t RIC : 8; + uint32_t RESERVED8 :24; +} stc_qspi_ccmd_field_t; + +typedef struct +{ + __IO uint32_t XIPMC : 8; + uint32_t RESERVED8 :24; +} stc_qspi_xcmd_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 7; + __IO uint32_t RAERCLR : 1; + uint32_t RESERVED8 :24; +} stc_qspi_sr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 :26; + __IO uint32_t EXADR : 6; +} stc_qspi_exar_field_t; + +typedef struct +{ + __IO uint32_t RESET : 1; + uint32_t RESERVED1 :31; +} stc_rtc_cr0_field_t; + +typedef struct +{ + __IO uint32_t PRDS : 3; + __IO uint32_t AMPM : 1; + __IO uint32_t ALMFCLR : 1; + __IO uint32_t ONEHZOE : 1; + __IO uint32_t ONEHZSEL : 1; + __IO uint32_t START : 1; + uint32_t RESERVED8 :24; +} stc_rtc_cr1_field_t; + +typedef struct +{ + __IO uint32_t RWREQ : 1; + __IO uint32_t RWEN : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t ALMF : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t PRDIE : 1; + __IO uint32_t ALMIE : 1; + __IO uint32_t ALME : 1; + uint32_t RESERVED8 :24; +} stc_rtc_cr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 4; + __IO uint32_t LRCEN : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t RCKSEL : 1; + uint32_t RESERVED8 :24; +} stc_rtc_cr3_field_t; + +typedef struct +{ + __IO uint32_t SECU : 4; + __IO uint32_t SECD : 3; + uint32_t RESERVED7 :25; +} stc_rtc_sec_field_t; + +typedef struct +{ + __IO uint32_t MINU : 4; + __IO uint32_t MIND : 3; + uint32_t RESERVED7 :25; +} stc_rtc_min_field_t; + +typedef struct +{ + __IO uint32_t HOURU : 4; + __IO uint32_t HOURD : 2; + uint32_t RESERVED6 :26; +} stc_rtc_hour_field_t; + +typedef struct +{ + __IO uint32_t WEEK : 3; + uint32_t RESERVED3 :29; +} stc_rtc_week_field_t; + +typedef struct +{ + __IO uint32_t DAYU : 4; + __IO uint32_t DAYD : 2; + uint32_t RESERVED6 :26; +} stc_rtc_day_field_t; + +typedef struct +{ + __IO uint32_t MON : 5; + uint32_t RESERVED5 :27; +} stc_rtc_mon_field_t; + +typedef struct +{ + __IO uint32_t YEARU : 4; + __IO uint32_t YEARD : 4; + uint32_t RESERVED8 :24; +} stc_rtc_year_field_t; + +typedef struct +{ + __IO uint32_t ALMMINU : 4; + __IO uint32_t ALMMIND : 3; + uint32_t RESERVED7 :25; +} stc_rtc_almmin_field_t; + +typedef struct +{ + __IO uint32_t ALMHOURU : 4; + __IO uint32_t ALMHOURD : 2; + uint32_t RESERVED6 :26; +} stc_rtc_almhour_field_t; + +typedef struct +{ + __IO uint32_t ALMWEEK : 7; + uint32_t RESERVED7 :25; +} stc_rtc_almweek_field_t; + +typedef struct +{ + __IO uint32_t COMP8 : 1; + uint32_t RESERVED1 : 6; + __IO uint32_t COMPEN : 1; + uint32_t RESERVED8 :24; +} stc_rtc_errcrh_field_t; + +typedef struct +{ + __IO uint32_t COMP : 8; + uint32_t RESERVED8 :24; +} stc_rtc_errcrl_field_t; + +typedef struct +{ + __IO uint16_t TBS :12; + uint16_t RESERVED12 : 4; +} stc_sdioc_blksize_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 1; + __IO uint16_t BCE : 1; + __IO uint16_t ATCEN : 2; + __IO uint16_t DDIR : 1; + __IO uint16_t MULB : 1; + uint16_t RESERVED6 :10; +} stc_sdioc_transmode_field_t; + +typedef struct +{ + __IO uint16_t RESTYP : 2; + uint16_t RESERVED2 : 1; + __IO uint16_t CCE : 1; + __IO uint16_t ICE : 1; + __IO uint16_t DAT : 1; + __IO uint16_t TYP : 2; + __IO uint16_t IDX : 6; + uint16_t RESERVED14 : 2; +} stc_sdioc_cmd_field_t; + +typedef struct +{ + __IO uint32_t CIC : 1; + __IO uint32_t CID : 1; + __IO uint32_t DA : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t WTA : 1; + __IO uint32_t RTA : 1; + __IO uint32_t BWE : 1; + __IO uint32_t BRE : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t CIN : 1; + __IO uint32_t CSS : 1; + __IO uint32_t CDL : 1; + __IO uint32_t WPL : 1; + __IO uint32_t DATL : 4; + __IO uint32_t CMDL : 1; + uint32_t RESERVED25 : 7; +} stc_sdioc_pstat_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 1; + __IO uint8_t DW : 1; + __IO uint8_t HSEN : 1; + uint8_t RESERVED3 : 2; + __IO uint8_t EXDW : 1; + __IO uint8_t CDTL : 1; + __IO uint8_t CDSS : 1; +} stc_sdioc_hostcon_field_t; + +typedef struct +{ + __IO uint8_t PWON : 1; + uint8_t RESERVED1 : 7; +} stc_sdioc_pwrcon_field_t; + +typedef struct +{ + __IO uint8_t SABGR : 1; + __IO uint8_t CR : 1; + __IO uint8_t RWC : 1; + __IO uint8_t IABG : 1; + uint8_t RESERVED4 : 4; +} stc_sdioc_blkgpcon_field_t; + +typedef struct +{ + __IO uint16_t ICE : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t CE : 1; + uint16_t RESERVED3 : 5; + __IO uint16_t FS : 8; +} stc_sdioc_clkcon_field_t; + +typedef struct +{ + __IO uint8_t DTO : 4; + uint8_t RESERVED4 : 4; +} stc_sdioc_toutcon_field_t; + +typedef struct +{ + __IO uint8_t RSTA : 1; + __IO uint8_t RSTC : 1; + __IO uint8_t RSTD : 1; + uint8_t RESERVED3 : 5; +} stc_sdioc_sftrst_field_t; + +typedef struct +{ + __IO uint16_t CC : 1; + __IO uint16_t TC : 1; + __IO uint16_t BGE : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWR : 1; + __IO uint16_t BRR : 1; + __IO uint16_t CIST : 1; + __IO uint16_t CRM : 1; + __IO uint16_t CINT : 1; + uint16_t RESERVED9 : 6; + __IO uint16_t EI : 1; +} stc_sdioc_norintst_field_t; + +typedef struct +{ + __IO uint16_t CTOE : 1; + __IO uint16_t CCE : 1; + __IO uint16_t CEBE : 1; + __IO uint16_t CIE : 1; + __IO uint16_t DTOE : 1; + __IO uint16_t DCE : 1; + __IO uint16_t DEBE : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACE : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintst_field_t; + +typedef struct +{ + __IO uint16_t CCEN : 1; + __IO uint16_t TCEN : 1; + __IO uint16_t BGEEN : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWREN : 1; + __IO uint16_t BRREN : 1; + __IO uint16_t CISTEN : 1; + __IO uint16_t CRMEN : 1; + __IO uint16_t CINTEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_norintsten_field_t; + +typedef struct +{ + __IO uint16_t CTOEEN : 1; + __IO uint16_t CCEEN : 1; + __IO uint16_t CEBEEN : 1; + __IO uint16_t CIEEN : 1; + __IO uint16_t DTOEEN : 1; + __IO uint16_t DCEEN : 1; + __IO uint16_t DEBEEN : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACEEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintsten_field_t; + +typedef struct +{ + __IO uint16_t CCSEN : 1; + __IO uint16_t TCSEN : 1; + __IO uint16_t BGESEN : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWRSEN : 1; + __IO uint16_t BRRSEN : 1; + __IO uint16_t CISTSEN : 1; + __IO uint16_t CRMSEN : 1; + __IO uint16_t CINTSEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_norintsgen_field_t; + +typedef struct +{ + __IO uint16_t CTOESEN : 1; + __IO uint16_t CCESEN : 1; + __IO uint16_t CEBESEN : 1; + __IO uint16_t CIESEN : 1; + __IO uint16_t DTOESEN : 1; + __IO uint16_t DCESEN : 1; + __IO uint16_t DEBESEN : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACESEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintsgen_field_t; + +typedef struct +{ + __IO uint16_t NE : 1; + __IO uint16_t TOE : 1; + __IO uint16_t CE : 1; + __IO uint16_t EBE : 1; + __IO uint16_t IE : 1; + uint16_t RESERVED5 : 2; + __IO uint16_t CMDE : 1; + uint16_t RESERVED8 : 8; +} stc_sdioc_atcerrst_field_t; + +typedef struct +{ + __IO uint16_t FNE : 1; + __IO uint16_t FTOE : 1; + __IO uint16_t FCE : 1; + __IO uint16_t FEBE : 1; + __IO uint16_t FIE : 1; + uint16_t RESERVED5 : 2; + __IO uint16_t FCMDE : 1; + uint16_t RESERVED8 : 8; +} stc_sdioc_fea_field_t; + +typedef struct +{ + __IO uint16_t FCTOE : 1; + __IO uint16_t FCCE : 1; + __IO uint16_t FCEBE : 1; + __IO uint16_t FCIE : 1; + __IO uint16_t FDTOE : 1; + __IO uint16_t FDCE : 1; + __IO uint16_t FDEBE : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t FACE : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_fee_field_t; + +typedef struct +{ + __IO uint32_t SPIMDS : 1; + __IO uint32_t TXMDS : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t MSTR : 1; + __IO uint32_t SPLPBK : 1; + __IO uint32_t SPLPBK2 : 1; + __IO uint32_t SPE : 1; + __IO uint32_t CSUSPE : 1; + __IO uint32_t EIE : 1; + __IO uint32_t TXIE : 1; + __IO uint32_t RXIE : 1; + __IO uint32_t IDIE : 1; + __IO uint32_t MODFE : 1; + __IO uint32_t PATE : 1; + __IO uint32_t PAOE : 1; + __IO uint32_t PAE : 1; + uint32_t RESERVED16 :16; +} stc_spi_cr1_field_t; + +typedef struct +{ + __IO uint32_t FTHLV : 2; + uint32_t RESERVED2 : 4; + __IO uint32_t SPRDTD : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t SS0PV : 1; + __IO uint32_t SS1PV : 1; + __IO uint32_t SS2PV : 1; + __IO uint32_t SS3PV : 1; + uint32_t RESERVED12 : 8; + __IO uint32_t MSSI : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t MSSDL : 3; + uint32_t RESERVED27 : 1; + __IO uint32_t MIDI : 3; + uint32_t RESERVED31 : 1; +} stc_spi_cfg1_field_t; + +typedef struct +{ + __IO uint32_t OVRERF : 1; + __IO uint32_t IDLNF : 1; + __IO uint32_t MODFERF : 1; + __IO uint32_t PERF : 1; + __IO uint32_t UDRERF : 1; + __IO uint32_t TDEF : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t RDFF : 1; + uint32_t RESERVED8 :24; +} stc_spi_sr_field_t; + +typedef struct +{ + __IO uint32_t CPHA : 1; + __IO uint32_t CPOL : 1; + __IO uint32_t MBR : 3; + __IO uint32_t SSA : 3; + __IO uint32_t DSIZE : 4; + __IO uint32_t LSBF : 1; + __IO uint32_t MIDIE : 1; + __IO uint32_t MSSDLE : 1; + __IO uint32_t MSSIE : 1; + uint32_t RESERVED16 :16; +} stc_spi_cfg2_field_t; + +typedef struct +{ + __IO uint32_t SRAM12_RWT : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t SRAM12_WWT : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t SRAM3_RWT : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t SRAM3_WWT : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t SRAMH_RWT : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t SRAMH_WWT : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t SRAMR_RWT : 3; + uint32_t RESERVED27 : 1; + __IO uint32_t SRAMR_WWT : 3; + uint32_t RESERVED31 : 1; +} stc_sramc_wtcr_field_t; + +typedef struct +{ + __IO uint32_t WTPRC : 1; + __IO uint32_t WTPRKW : 7; + uint32_t RESERVED8 :24; +} stc_sramc_wtpr_field_t; + +typedef struct +{ + __IO uint32_t PYOAD : 1; + uint32_t RESERVED1 :15; + __IO uint32_t ECCOAD : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t ECCMOD : 2; + uint32_t RESERVED26 : 6; +} stc_sramc_ckcr_field_t; + +typedef struct +{ + __IO uint32_t CKPRC : 1; + __IO uint32_t CKPRKW : 7; + uint32_t RESERVED8 :24; +} stc_sramc_ckpr_field_t; + +typedef struct +{ + __IO uint32_t SRAM3_1ERR : 1; + __IO uint32_t SRAM3_2ERR : 1; + __IO uint32_t SRAM12_PYERR : 1; + __IO uint32_t SRAMH_PYERR : 1; + __IO uint32_t SRAMR_PYERR : 1; + uint32_t RESERVED5 :27; +} stc_sramc_cksr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + __IO uint32_t UDF : 1; + __IO uint32_t REF : 1; + uint32_t RESERVED18 :14; +} stc_swdt_sr_field_t; + +typedef struct +{ + __IO uint32_t RF :16; + uint32_t RESERVED16 :16; +} stc_swdt_rr_field_t; + +typedef struct +{ + __IO uint16_t FLNWT : 1; + __IO uint16_t CKSMRC : 1; + uint16_t RESERVED2 :13; + __IO uint16_t STOP : 1; +} stc_sysreg_pwr_stpmcr_field_t; + +typedef struct +{ + __IO uint16_t PERICKSEL : 4; + uint16_t RESERVED4 :12; +} stc_sysreg_cmu_pericksel_field_t; + +typedef struct +{ + __IO uint16_t I2S1CKSEL : 4; + __IO uint16_t I2S2CKSEL : 4; + __IO uint16_t I2S3CKSEL : 4; + __IO uint16_t I2S4CKSEL : 4; +} stc_sysreg_cmu_i2scksel_field_t; + +typedef struct +{ + __IO uint32_t RAMPDC0 : 1; + __IO uint32_t RAMPDC1 : 1; + __IO uint32_t RAMPDC2 : 1; + __IO uint32_t RAMPDC3 : 1; + __IO uint32_t RAMPDC4 : 1; + __IO uint32_t RAMPDC5 : 1; + __IO uint32_t RAMPDC6 : 1; + __IO uint32_t RAMPDC7 : 1; + __IO uint32_t RAMPDC8 : 1; + uint32_t RESERVED9 :23; +} stc_sysreg_pwr_rampc0_field_t; + +typedef struct +{ + __IO uint32_t AESRDP : 1; + __IO uint32_t AESWRP : 1; + __IO uint32_t HASHRDP : 1; + __IO uint32_t HASHWRP : 1; + __IO uint32_t TRNGRDP : 1; + __IO uint32_t TRNGWRP : 1; + __IO uint32_t CRCRDP : 1; + __IO uint32_t CRCWRP : 1; + __IO uint32_t FMCRDP : 1; + __IO uint32_t FMCWRP : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t WDTRDP : 1; + __IO uint32_t WDTWRP : 1; + __IO uint32_t SWDTRDP : 1; + __IO uint32_t SWDTWRP : 1; + __IO uint32_t BKSRAMRDP : 1; + __IO uint32_t BKSRAMWRP : 1; + __IO uint32_t RTCRDP : 1; + __IO uint32_t RTCWRP : 1; + __IO uint32_t DMPURDP : 1; + __IO uint32_t DMPUWRP : 1; + __IO uint32_t SRAMCRDP : 1; + __IO uint32_t SRAMCWRP : 1; + __IO uint32_t INTCRDP : 1; + __IO uint32_t INTCWRP : 1; + __IO uint32_t SYSCRDP : 1; + __IO uint32_t SYSCWRP : 1; + __IO uint32_t MSTPRDP : 1; + __IO uint32_t MSTPWRP : 1; + uint32_t RESERVED30 : 1; + __IO uint32_t BUSERRE : 1; +} stc_sysreg_mpu_ippr_field_t; + +typedef struct +{ + __IO uint32_t PCLK0S : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t PCLK1S : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t PCLK2S : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t PCLK3S : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t PCLK4S : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t EXCKS : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t HCLKS : 3; + uint32_t RESERVED27 : 5; +} stc_sysreg_cmu_scfgr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t USBCKS : 4; +} stc_sysreg_cmu_ufsckcfgr_field_t; + +typedef struct +{ + __IO uint8_t CKSW : 3; + uint8_t RESERVED3 : 5; +} stc_sysreg_cmu_ckswr_field_t; + +typedef struct +{ + __IO uint8_t MPLLOFF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_pllcr_field_t; + +typedef struct +{ + __IO uint8_t UPLLOFF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_upllcr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtalcr_field_t; + +typedef struct +{ + __IO uint8_t HRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_hrccr_field_t; + +typedef struct +{ + __IO uint8_t MRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_mrccr_field_t; + +typedef struct +{ + __IO uint8_t HRCSTBF : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t XTALSTBF : 1; + uint8_t RESERVED4 : 1; + __IO uint8_t MPLLSTBF : 1; + __IO uint8_t UPLLSTBF : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_cmu_oscstbsr_field_t; + +typedef struct +{ + __IO uint8_t MCO1SEL : 4; + __IO uint8_t MCO1DIV : 3; + __IO uint8_t MCO1EN : 1; +} stc_sysreg_cmu_mco1cfgr_field_t; + +typedef struct +{ + __IO uint8_t MCO2SEL : 4; + __IO uint8_t MCO2DIV : 3; + __IO uint8_t MCO2EN : 1; +} stc_sysreg_cmu_mco2cfgr_field_t; + +typedef struct +{ + __IO uint8_t TPIUCKS : 2; + uint8_t RESERVED2 : 5; + __IO uint8_t TPIUCKOE : 1; +} stc_sysreg_cmu_tpiuckcfgr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTDIE : 1; + __IO uint8_t XTALSTDRE : 1; + __IO uint8_t XTALSTDRIS : 1; + uint8_t RESERVED3 : 4; + __IO uint8_t XTALSTDE : 1; +} stc_sysreg_cmu_xtalstdcr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTDF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtalstdsr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTB : 4; + uint8_t RESERVED4 : 4; +} stc_sysreg_cmu_xtalstbcr_field_t; + +typedef struct +{ + __IO uint16_t PORF : 1; + __IO uint16_t PINRF : 1; + __IO uint16_t BORF : 1; + __IO uint16_t PVD1RF : 1; + __IO uint16_t PVD2RF : 1; + __IO uint16_t WDRF : 1; + __IO uint16_t SWDRF : 1; + __IO uint16_t PDRF : 1; + __IO uint16_t SWRF : 1; + __IO uint16_t MPUERF : 1; + __IO uint16_t RAPERF : 1; + __IO uint16_t RAECRF : 1; + __IO uint16_t CKFERF : 1; + __IO uint16_t XTALERF : 1; + __IO uint16_t MULTIRF : 1; + __IO uint16_t CLRF : 1; +} stc_sysreg_rmu_rstf0_field_t; + +typedef struct +{ + __IO uint8_t PVD1NMIS : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t PVD2NMIS : 1; + uint8_t RESERVED5 : 3; +} stc_sysreg_pwr_pvdicr_field_t; + +typedef struct +{ + __IO uint8_t PVD1MON : 1; + __IO uint8_t PVD1DETFLG : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t PVD2MON : 1; + __IO uint8_t PVD2DETFLG : 1; + uint8_t RESERVED6 : 2; +} stc_sysreg_pwr_pvddsr_field_t; + +typedef struct +{ + __IO uint32_t MPLLM : 5; + uint32_t RESERVED5 : 2; + __IO uint32_t PLLSRC : 1; + __IO uint32_t MPLLN : 9; + uint32_t RESERVED17 : 3; + __IO uint32_t MPLLR : 4; + __IO uint32_t MPLLQ : 4; + __IO uint32_t MPLLP : 4; +} stc_sysreg_cmu_pllcfgr_field_t; + +typedef struct +{ + __IO uint32_t UPLLM : 5; + uint32_t RESERVED5 : 3; + __IO uint32_t UPLLN : 9; + uint32_t RESERVED17 : 3; + __IO uint32_t UPLLR : 4; + __IO uint32_t UPLLQ : 4; + __IO uint32_t UPLLP : 4; +} stc_sysreg_cmu_upllcfgr_field_t; + +typedef struct +{ + __IO uint16_t FPRCB0 : 1; + __IO uint16_t FPRCB1 : 1; + __IO uint16_t FPRCB2 : 1; + __IO uint16_t FPRCB3 : 1; + uint16_t RESERVED4 : 4; + __IO uint16_t FPRCWE : 8; +} stc_sysreg_pwr_fprc_field_t; + +typedef struct +{ + __IO uint8_t PDMDS : 2; + __IO uint8_t VVDRSD : 1; + __IO uint8_t RETRAMSD : 1; + __IO uint8_t IORTN : 2; + uint8_t RESERVED6 : 1; + __IO uint8_t PWDN : 1; +} stc_sysreg_pwr_pwrc0_field_t; + +typedef struct +{ + __IO uint8_t VPLLSD : 1; + __IO uint8_t VHRCSD : 1; + uint8_t RESERVED2 : 4; + __IO uint8_t STPDAS : 2; +} stc_sysreg_pwr_pwrc1_field_t; + +typedef struct +{ + __IO uint8_t DDAS : 4; + __IO uint8_t DVS : 2; + uint8_t RESERVED6 : 2; +} stc_sysreg_pwr_pwrc2_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 2; + __IO uint8_t PDTS : 1; + uint8_t RESERVED3 : 5; +} stc_sysreg_pwr_pwrc3_field_t; + +typedef struct +{ + __IO uint8_t WKE00 : 1; + __IO uint8_t WKE01 : 1; + __IO uint8_t WKE02 : 1; + __IO uint8_t WKE03 : 1; + __IO uint8_t WKE10 : 1; + __IO uint8_t WKE11 : 1; + __IO uint8_t WKE12 : 1; + __IO uint8_t WKE13 : 1; +} stc_sysreg_pwr_pdwke0_field_t; + +typedef struct +{ + __IO uint8_t WKE20 : 1; + __IO uint8_t WKE21 : 1; + __IO uint8_t WKE22 : 1; + __IO uint8_t WKE23 : 1; + __IO uint8_t WKE30 : 1; + __IO uint8_t WKE31 : 1; + __IO uint8_t WKE32 : 1; + __IO uint8_t WKE33 : 1; +} stc_sysreg_pwr_pdwke1_field_t; + +typedef struct +{ + __IO uint8_t VD1WKE : 1; + __IO uint8_t VD2WKE : 1; + __IO uint8_t NMIWKE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t RTCPRDWKE : 1; + __IO uint8_t RTCALMWKE : 1; + uint8_t RESERVED6 : 1; + __IO uint8_t WKTMWKE : 1; +} stc_sysreg_pwr_pdwke2_field_t; + +typedef struct +{ + __IO uint8_t WK0EGS : 1; + __IO uint8_t WK1EGS : 1; + __IO uint8_t WK2EGS : 1; + __IO uint8_t WK3EGS : 1; + __IO uint8_t VD1EGS : 1; + __IO uint8_t VD2EGS : 1; + __IO uint8_t NMIEGS : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pdwkes_field_t; + +typedef struct +{ + __IO uint8_t PTWK0F : 1; + __IO uint8_t PTWK1F : 1; + __IO uint8_t PTWK2F : 1; + __IO uint8_t PTWK3F : 1; + __IO uint8_t VD1WKF : 1; + __IO uint8_t VD2WKF : 1; + __IO uint8_t NMIWKF : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pdwkf0_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t RTCPRDWKF : 1; + __IO uint8_t RTCALMWKF : 1; + uint8_t RESERVED6 : 1; + __IO uint8_t WKTMWKF : 1; +} stc_sysreg_pwr_pdwkf1_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 7; + __IO uint8_t ADBUFE : 1; +} stc_sysreg_pwr_pwcmr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t XTALDRV : 2; + __IO uint8_t XTALMS : 1; + __IO uint8_t SUPDRV : 1; +} stc_sysreg_cmu_xtalcfgr_field_t; + +typedef struct +{ + __IO uint8_t EXVCCINEN : 1; + uint8_t RESERVED1 : 4; + __IO uint8_t PVD1EN : 1; + __IO uint8_t PVD2EN : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdcr0_field_t; + +typedef struct +{ + __IO uint8_t PVD1IRE : 1; + __IO uint8_t PVD1IRS : 1; + __IO uint8_t PVD1CMPOE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2IRE : 1; + __IO uint8_t PVD2IRS : 1; + __IO uint8_t PVD2CMPOE : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdcr1_field_t; + +typedef struct +{ + __IO uint8_t PVD1NFDIS : 1; + __IO uint8_t PVD1NFCKS : 2; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2NFDIS : 1; + __IO uint8_t PVD2NFCKS : 2; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdfcr_field_t; + +typedef struct +{ + __IO uint8_t PVD1LVL : 3; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2LVL : 3; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdlcr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32STP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtal32cr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32DRV : 3; + uint8_t RESERVED3 : 5; +} stc_sysreg_cmu_xtal32cfgr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32NF : 2; + uint8_t RESERVED2 : 6; +} stc_sysreg_cmu_xtal32nfr_field_t; + +typedef struct +{ + __IO uint8_t LRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_lrccr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 7; + __IO uint8_t CSDIS : 1; +} stc_sysreg_pwr_xtal32cs_field_t; + +typedef struct +{ + __IO uint32_t CNTA :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cntar_field_t; + +typedef struct +{ + __IO uint32_t CNTB :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cntbr_field_t; + +typedef struct +{ + __IO uint32_t CMPA :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cmpar_field_t; + +typedef struct +{ + __IO uint32_t CMPB :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cmpbr_field_t; + +typedef struct +{ + __IO uint32_t CSTA : 1; + __IO uint32_t CAPMDA : 1; + __IO uint32_t INTENA : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t CKDIVA : 4; + __IO uint32_t SYNSA : 1; + __IO uint32_t SYNCLKA : 1; + __IO uint32_t ASYNCLKA : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t HSTAA : 1; + __IO uint32_t HSTPA : 1; + __IO uint32_t HCLEA : 1; + __IO uint32_t HICPA : 1; + __IO uint32_t CSTB : 1; + __IO uint32_t CAPMDB : 1; + __IO uint32_t INTENB : 1; + uint32_t RESERVED19 : 1; + __IO uint32_t CKDIVB : 4; + __IO uint32_t SYNSB : 1; + __IO uint32_t SYNCLKB : 1; + __IO uint32_t ASYNCLKB : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t HSTAB : 1; + __IO uint32_t HSTPB : 1; + __IO uint32_t HCLEB : 1; + __IO uint32_t HICPB : 1; +} stc_tmr0_bconr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + uint32_t RESERVED1 :15; + __IO uint32_t CMBF : 1; + uint32_t RESERVED17 :15; +} stc_tmr0_stflr_field_t; + +typedef struct +{ + __IO uint16_t OCEH : 1; + __IO uint16_t OCEL : 1; + __IO uint16_t OCPH : 1; + __IO uint16_t OCPL : 1; + __IO uint16_t OCIEH : 1; + __IO uint16_t OCIEL : 1; + __IO uint16_t OCFH : 1; + __IO uint16_t OCFL : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_ocsr_field_t; + +typedef struct +{ + __IO uint16_t CHBUFEN : 2; + __IO uint16_t CLBUFEN : 2; + __IO uint16_t MHBUFEN : 2; + __IO uint16_t MLBUFEN : 2; + __IO uint16_t LMCH : 1; + __IO uint16_t LMCL : 1; + __IO uint16_t LMMH : 1; + __IO uint16_t LMML : 1; + __IO uint16_t MCECH : 1; + __IO uint16_t MCECL : 1; + uint16_t RESERVED14 : 2; +} stc_tmr4_ocer_field_t; + +typedef struct +{ + __IO uint16_t OCFDCH : 1; + __IO uint16_t OCFPKH : 1; + __IO uint16_t OCFUCH : 1; + __IO uint16_t OCFZRH : 1; + __IO uint16_t OPDCH : 2; + __IO uint16_t OPPKH : 2; + __IO uint16_t OPUCH : 2; + __IO uint16_t OPZRH : 2; + __IO uint16_t OPNPKH : 2; + __IO uint16_t OPNZRH : 2; +} stc_tmr4_ocmrh_field_t; + +typedef struct +{ + __IO uint32_t OCFDCL : 1; + __IO uint32_t OCFPKL : 1; + __IO uint32_t OCFUCL : 1; + __IO uint32_t OCFZRL : 1; + __IO uint32_t OPDCL : 2; + __IO uint32_t OPPKL : 2; + __IO uint32_t OPUCL : 2; + __IO uint32_t OPZRL : 2; + __IO uint32_t OPNPKL : 2; + __IO uint32_t OPNZRL : 2; + __IO uint32_t EOPNDCL : 2; + __IO uint32_t EOPNUCL : 2; + __IO uint32_t EOPDCL : 2; + __IO uint32_t EOPPKL : 2; + __IO uint32_t EOPUCL : 2; + __IO uint32_t EOPZRL : 2; + __IO uint32_t EOPNPKL : 2; + __IO uint32_t EOPNZRL : 2; +} stc_tmr4_ocmrl_field_t; + +typedef struct +{ + __IO uint16_t CKDIV : 4; + __IO uint16_t CLEAR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BUFEN : 1; + __IO uint16_t IRQPEN : 1; + __IO uint16_t IRQPF : 1; + uint16_t RESERVED10 : 3; + __IO uint16_t IRQZEN : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKEN : 1; +} stc_tmr4_ccsr_field_t; + +typedef struct +{ + __IO uint16_t ZIM : 4; + __IO uint16_t PIM : 4; + __IO uint16_t ZIC : 4; + __IO uint16_t PIC : 4; +} stc_tmr4_cvpr_field_t; + +typedef struct +{ + __IO uint16_t DIVCK : 4; + __IO uint16_t PWMMD : 2; + __IO uint16_t LVLS : 2; + uint16_t RESERVED8 : 8; +} stc_tmr4_pocr_field_t; + +typedef struct +{ + __IO uint16_t RTIDU : 1; + __IO uint16_t RTIDV : 1; + __IO uint16_t RTIDW : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t RTIFU : 1; + __IO uint16_t RTICU : 1; + __IO uint16_t RTEU : 1; + __IO uint16_t RTSU : 1; + __IO uint16_t RTIFV : 1; + __IO uint16_t RTICV : 1; + __IO uint16_t RTEV : 1; + __IO uint16_t RTSV : 1; + __IO uint16_t RTIFW : 1; + __IO uint16_t RTICW : 1; + __IO uint16_t RTEW : 1; + __IO uint16_t RTSW : 1; +} stc_tmr4_rcsr_field_t; + +typedef struct +{ + __IO uint16_t BUFEN : 2; + __IO uint16_t EVTOS : 3; + __IO uint16_t LMC : 1; + uint16_t RESERVED6 : 2; + __IO uint16_t EVTMS : 1; + __IO uint16_t EVTDS : 1; + uint16_t RESERVED10 : 2; + __IO uint16_t DEN : 1; + __IO uint16_t PEN : 1; + __IO uint16_t UEN : 1; + __IO uint16_t ZEN : 1; +} stc_tmr4_scsr_field_t; + +typedef struct +{ + __IO uint16_t AMC : 4; + uint16_t RESERVED4 : 2; + __IO uint16_t MZCE : 1; + __IO uint16_t MPCE : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_scmr_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 7; + __IO uint16_t HOLD : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_ecsr_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer1_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer2_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer3_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :16; +} stc_tmr6_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_perbr_field_t; + +typedef struct +{ + __IO uint32_t PERC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_percr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t GCME :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmer_field_t; + +typedef struct +{ + __IO uint32_t GCMF :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmfr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmbr_field_t; + +typedef struct +{ + __IO uint32_t SCMC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmcr_field_t; + +typedef struct +{ + __IO uint32_t SCMD :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmdr_field_t; + +typedef struct +{ + __IO uint32_t SCME :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmer_field_t; + +typedef struct +{ + __IO uint32_t SCMF :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmfr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtdar_field_t; + +typedef struct +{ + __IO uint32_t DTUB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtubr_field_t; + +typedef struct +{ + __IO uint32_t DTDB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtdbr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSKVAL : 2; + uint32_t RESERVED20 :12; +} stc_tmr6_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + __IO uint32_t INTENE : 1; + __IO uint32_t INTENF : 1; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDTE : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; + uint32_t RESERVED20 :12; +} stc_tmr6_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPMDA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t EMBVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPMDB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + uint32_t RESERVED25 : 2; + __IO uint32_t EMBVALB : 2; + uint32_t RESERVED29 : 3; +} stc_tmr6_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + __IO uint32_t BSEA : 1; + __IO uint32_t BENB : 1; + __IO uint32_t BSEB : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t BENP : 1; + __IO uint32_t BSEP : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t BENSPA : 1; + __IO uint32_t BSESPA : 1; + uint32_t RESERVED18 : 2; + __IO uint32_t BTRSPA : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t BENSPB : 1; + __IO uint32_t BSESPB : 1; + uint32_t RESERVED26 : 2; + __IO uint32_t BTRSPB : 2; + uint32_t RESERVED30 : 2; +} stc_tmr6_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTBENU : 1; + __IO uint32_t DTBEND : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t SEPA : 1; + uint32_t RESERVED9 :23; +} stc_tmr6_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 9; +} stc_tmr6_fconr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t SPPERIA : 1; + __IO uint32_t SPPERIB : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; + uint32_t RESERVED21 :11; +} stc_tmr6_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + __IO uint32_t CMEF : 1; + __IO uint32_t CMFF : 1; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __IO uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __IO uint32_t DIRF : 1; +} stc_tmr6_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t STARTS : 1; +} stc_tmr6_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t STOPS : 1; +} stc_tmr6_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCLE0 : 1; + __IO uint32_t HCLE1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCLE4 : 1; + __IO uint32_t HCLE5 : 1; + __IO uint32_t HCLE6 : 1; + __IO uint32_t HCLE7 : 1; + __IO uint32_t HCLE8 : 1; + __IO uint32_t HCLE9 : 1; + __IO uint32_t HCLE10 : 1; + __IO uint32_t HCLE11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t CLEARS : 1; +} stc_tmr6_hclrr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + uint32_t RESERVED12 :20; +} stc_tmr6_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + uint32_t RESERVED12 :20; +} stc_tmr6_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + uint32_t RESERVED18 :14; +} stc_tmr6_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + uint32_t RESERVED18 :14; +} stc_tmr6_hcdor_field_t; + +typedef struct +{ + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; + __IO uint32_t SSTA3 : 1; + uint32_t RESERVED3 :13; + __IO uint32_t RESV0 : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t RESV : 1; + uint32_t RESERVED25 : 7; +} stc_tmr6_cr_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; + __IO uint32_t SSTP3 : 1; + uint32_t RESERVED3 :29; +} stc_tmr6_cr_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLE1 : 1; + __IO uint32_t SCLE2 : 1; + __IO uint32_t SCLE3 : 1; + uint32_t RESERVED3 :29; +} stc_tmr6_cr_sclrr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :16; +} stc_tmra_cnter_field_t; + +typedef struct +{ + __IO uint32_t PER :16; + uint32_t RESERVED16 :16; +} stc_tmra_perar_field_t; + +typedef struct +{ + __IO uint32_t CMP :16; + uint32_t RESERVED16 :16; +} stc_tmra_cmpar_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t DIR : 1; + __IO uint32_t MODE : 1; + __IO uint32_t SYNST : 1; + __IO uint32_t CKDIV : 4; + uint32_t RESERVED8 : 4; + __IO uint32_t ITENOVF : 1; + __IO uint32_t ITENUDF : 1; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + uint32_t RESERVED16 :16; +} stc_tmra_bcstr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + __IO uint32_t HSTA2 : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + __IO uint32_t HSTP2 : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t HCLE0 : 1; + __IO uint32_t HCLE1 : 1; + __IO uint32_t HCLE2 : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t HCLE3 : 1; + __IO uint32_t HCLE4 : 1; + __IO uint32_t HCLE5 : 1; + __IO uint32_t HCLE6 : 1; + uint32_t RESERVED16 :16; +} stc_tmra_hconr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + __IO uint32_t HCUP12 : 1; + uint32_t RESERVED13 :19; +} stc_tmra_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + __IO uint32_t HCDO12 : 1; + uint32_t RESERVED13 :19; +} stc_tmra_hcdor_field_t; + +typedef struct +{ + __IO uint32_t ITEN1 : 1; + __IO uint32_t ITEN2 : 1; + __IO uint32_t ITEN3 : 1; + __IO uint32_t ITEN4 : 1; + __IO uint32_t ITEN5 : 1; + __IO uint32_t ITEN6 : 1; + __IO uint32_t ITEN7 : 1; + __IO uint32_t ITEN8 : 1; + uint32_t RESERVED8 :24; +} stc_tmra_iconr_field_t; + +typedef struct +{ + __IO uint32_t ETEN1 : 1; + __IO uint32_t ETEN2 : 1; + __IO uint32_t ETEN3 : 1; + __IO uint32_t ETEN4 : 1; + __IO uint32_t ETEN5 : 1; + __IO uint32_t ETEN6 : 1; + __IO uint32_t ETEN7 : 1; + __IO uint32_t ETEN8 : 1; + uint32_t RESERVED8 :24; +} stc_tmra_econr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENTG : 1; + __IO uint32_t NOFICKTG : 2; + uint32_t RESERVED3 : 5; + __IO uint32_t NOFIENCA : 1; + __IO uint32_t NOFICKCA : 2; + uint32_t RESERVED11 : 1; + __IO uint32_t NOFIENCB : 1; + __IO uint32_t NOFICKCB : 2; + uint32_t RESERVED15 :17; +} stc_tmra_fconr_field_t; + +typedef struct +{ + __IO uint32_t CMPF1 : 1; + __IO uint32_t CMPF2 : 1; + __IO uint32_t CMPF3 : 1; + __IO uint32_t CMPF4 : 1; + __IO uint32_t CMPF5 : 1; + __IO uint32_t CMPF6 : 1; + __IO uint32_t CMPF7 : 1; + __IO uint32_t CMPF8 : 1; + uint32_t RESERVED8 :24; +} stc_tmra_stflr_field_t; + +typedef struct +{ + __IO uint32_t BEN : 1; + __IO uint32_t BSE0 : 1; + __IO uint32_t BSE1 : 1; + uint32_t RESERVED3 :29; +} stc_tmra_bconr_field_t; + +typedef struct +{ + __IO uint32_t CAPMD : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t HICP0 : 1; + __IO uint32_t HICP1 : 1; + __IO uint32_t HICP2 : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t HICP3 : 1; + __IO uint32_t HICP4 : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t NOFIENCP : 1; + __IO uint32_t NOFICKCP : 2; + uint32_t RESERVED15 :17; +} stc_tmra_cconr_field_t; + +typedef struct +{ + __IO uint32_t STAC : 2; + __IO uint32_t STPC : 2; + __IO uint32_t CMPC : 2; + __IO uint32_t PERC : 2; + __IO uint32_t FORC : 2; + uint32_t RESERVED10 : 2; + __IO uint32_t OUTEN : 1; + uint32_t RESERVED13 :19; +} stc_tmra_pconr_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t RUN : 1; + uint32_t RESERVED2 :30; +} stc_trng_cr_field_t; + +typedef struct +{ + __IO uint32_t LOAD : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CNT : 3; + uint32_t RESERVED5 :27; +} stc_trng_mr_field_t; + +typedef struct +{ + __IO uint32_t PE : 1; + __IO uint32_t FE : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t ORE : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t RXNE : 1; + __IO uint32_t TC : 1; + __IO uint32_t TXE : 1; + __IO uint32_t RTOF : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t MPB : 1; + uint32_t RESERVED17 :15; +} stc_usart_sr_field_t; + +typedef struct +{ + __IO uint32_t TDR : 9; + __IO uint32_t MPID : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t RDR : 9; + uint32_t RESERVED25 : 7; +} stc_usart_dr_field_t; + +typedef struct +{ + __IO uint32_t DIV_FRACTION : 7; + uint32_t RESERVED7 : 1; + __IO uint32_t DIV_INTEGER : 8; + uint32_t RESERVED16 :16; +} stc_usart_brr_field_t; + +typedef struct +{ + __IO uint32_t RTOE : 1; + __IO uint32_t RTOIE : 1; + __IO uint32_t RE : 1; + __IO uint32_t TE : 1; + __IO uint32_t SLME : 1; + __IO uint32_t RIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t TXEIE : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t PS : 1; + __IO uint32_t PCE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t M : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t OVER8 : 1; + __IO uint32_t CPE : 1; + __IO uint32_t CFE : 1; + uint32_t RESERVED18 : 1; + __IO uint32_t CORE : 1; + __IO uint32_t CRTOF : 1; + uint32_t RESERVED21 : 3; + __IO uint32_t MS : 1; + uint32_t RESERVED25 : 3; + __IO uint32_t ML : 1; + __IO uint32_t FBME : 1; + __IO uint32_t NFE : 1; + __IO uint32_t SBS : 1; +} stc_usart_cr1_field_t; + +typedef struct +{ + __IO uint32_t MPE : 1; + uint32_t RESERVED1 :10; + __IO uint32_t CLKC : 2; + __IO uint32_t STOP : 1; + uint32_t RESERVED14 :18; +} stc_usart_cr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t SCEN : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t CTSE : 1; + uint32_t RESERVED10 :11; + __IO uint32_t BCN : 3; + uint32_t RESERVED24 : 8; +} stc_usart_cr3_field_t; + +typedef struct +{ + __IO uint32_t PSC : 2; + uint32_t RESERVED2 :30; +} stc_usart_pr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 6; + __IO uint32_t VBUSOVEN : 1; + __IO uint32_t VBUSVAL : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_usbfs_gvbuscfg_field_t; + +typedef struct +{ + __IO uint32_t GINTMSK : 1; + __IO uint32_t HBSTLEN : 4; + __IO uint32_t DMAEN : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXFELVL : 1; + __IO uint32_t PTXFELVL : 1; + uint32_t RESERVED9 :23; +} stc_usbfs_gahbcfg_field_t; + +typedef struct +{ + __IO uint32_t TOCAL : 3; + uint32_t RESERVED3 : 3; + __IO uint32_t PHYSEL : 1; + uint32_t RESERVED7 : 3; + __IO uint32_t TRDT : 4; + uint32_t RESERVED14 :15; + __IO uint32_t FHMOD : 1; + __IO uint32_t FDMOD : 1; + uint32_t RESERVED31 : 1; +} stc_usbfs_gusbcfg_field_t; + +typedef struct +{ + __IO uint32_t CSRST : 1; + __IO uint32_t HSRST : 1; + __IO uint32_t FCRST : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t RXFFLSH : 1; + __IO uint32_t TXFFLSH : 1; + __IO uint32_t TXFNUM : 5; + uint32_t RESERVED11 :19; + __IO uint32_t DMAREQ : 1; + __IO uint32_t AHBIDL : 1; +} stc_usbfs_grstctl_field_t; + +typedef struct +{ + __IO uint32_t CMOD : 1; + __IO uint32_t MMIS : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SOF : 1; + __IO uint32_t RXFNE : 1; + __IO uint32_t NPTXFE : 1; + __IO uint32_t GINAKEFF : 1; + __IO uint32_t GONAKEFF : 1; + uint32_t RESERVED8 : 2; + __IO uint32_t ESUSP : 1; + __IO uint32_t USBSUSP : 1; + __IO uint32_t USBRST : 1; + __IO uint32_t ENUMDNE : 1; + __IO uint32_t ISOODRP : 1; + __IO uint32_t EOPF : 1; + uint32_t RESERVED16 : 2; + __IO uint32_t IEPINT : 1; + __IO uint32_t OEPINT : 1; + __IO uint32_t IISOIXFR : 1; + __IO uint32_t IPXFR_INCOMPISOOUT : 1; + __IO uint32_t DATAFSUSP : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t HPRTINT : 1; + __IO uint32_t HCINT : 1; + __IO uint32_t PTXFE : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t CIDSCHG : 1; + __IO uint32_t DISCINT : 1; + __IO uint32_t VBUSVINT : 1; + __IO uint32_t WKUINT : 1; +} stc_usbfs_gintsts_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t MMISM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SOFM : 1; + __IO uint32_t RXFNEM : 1; + __IO uint32_t NPTXFEM : 1; + __IO uint32_t GINAKEFFM : 1; + __IO uint32_t GONAKEFFM : 1; + uint32_t RESERVED8 : 2; + __IO uint32_t ESUSPM : 1; + __IO uint32_t USBSUSPM : 1; + __IO uint32_t USBRSTM : 1; + __IO uint32_t ENUMDNEM : 1; + __IO uint32_t ISOODRPM : 1; + __IO uint32_t EOPFM : 1; + uint32_t RESERVED16 : 2; + __IO uint32_t IEPIM : 1; + __IO uint32_t OEPIM : 1; + __IO uint32_t IISOIXFRM : 1; + __IO uint32_t IPXFRM_INCOMPISOOUTM : 1; + __IO uint32_t DATAFSUSPM : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t HPRTIM : 1; + __IO uint32_t HCIM : 1; + __IO uint32_t PTXFEM : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t CIDSCHGM : 1; + __IO uint32_t DISCIM : 1; + __IO uint32_t VBUSVIM : 1; + __IO uint32_t WKUIM : 1; +} stc_usbfs_gintmsk_field_t; + +typedef struct +{ + __IO uint32_t CHNUM_EPNUM : 4; + __IO uint32_t BCNT :11; + __IO uint32_t DPID : 2; + __IO uint32_t PKTSTS : 4; + uint32_t RESERVED21 :11; +} stc_usbfs_grxstsr_field_t; + +typedef struct +{ + __IO uint32_t CHNUM_EPNUM : 4; + __IO uint32_t BCNT :11; + __IO uint32_t DPID : 2; + __IO uint32_t PKTSTS : 4; + uint32_t RESERVED21 :11; +} stc_usbfs_grxstsp_field_t; + +typedef struct +{ + __IO uint32_t RXFD :11; + uint32_t RESERVED11 :21; +} stc_usbfs_grxfsiz_field_t; + +typedef struct +{ + __IO uint32_t NPTXFSA :16; + __IO uint32_t NPTXFD :16; +} stc_usbfs_hnptxfsiz_field_t; + +typedef struct +{ + __IO uint32_t NPTXFSAV :16; + __IO uint32_t NPTQXSAV : 8; + __IO uint32_t NPTXQTOP : 7; + uint32_t RESERVED31 : 1; +} stc_usbfs_hnptxsts_field_t; + +typedef struct +{ + __IO uint32_t PTXSA :12; + uint32_t RESERVED12 : 4; + __IO uint32_t PTXFD :11; + uint32_t RESERVED27 : 5; +} stc_usbfs_hptxfsiz_field_t; + +typedef struct +{ + __IO uint32_t INEPTXSA :12; + uint32_t RESERVED12 : 4; + __IO uint32_t INEPTXFD :10; + uint32_t RESERVED26 : 6; +} stc_usbfs_dieptxf_field_t; + +typedef struct +{ + __IO uint32_t FSLSPCS : 2; + __IO uint32_t FSLSS : 1; + uint32_t RESERVED3 :29; +} stc_usbfs_hcfg_field_t; + +typedef struct +{ + __IO uint32_t FRIVL :16; + uint32_t RESERVED16 :16; +} stc_usbfs_hfir_field_t; + +typedef struct +{ + __IO uint32_t FRNUM :16; + __IO uint32_t FTREM :16; +} stc_usbfs_hfnum_field_t; + +typedef struct +{ + __IO uint32_t PTXFSAVL :16; + __IO uint32_t PTXQSAV : 8; + __IO uint32_t PTXQTOP : 8; +} stc_usbfs_hptxsts_field_t; + +typedef struct +{ + __IO uint32_t HAINT :12; + uint32_t RESERVED12 :20; +} stc_usbfs_haint_field_t; + +typedef struct +{ + __IO uint32_t HAINTM :12; + uint32_t RESERVED12 :20; +} stc_usbfs_haintmsk_field_t; + +typedef struct +{ + __IO uint32_t PCSTS : 1; + __IO uint32_t PCDET : 1; + __IO uint32_t PENA : 1; + __IO uint32_t PENCHNG : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t PRES : 1; + __IO uint32_t PSUSP : 1; + __IO uint32_t PRST : 1; + uint32_t RESERVED9 : 1; + __IO uint32_t PLSTS : 2; + __IO uint32_t PWPR : 1; + uint32_t RESERVED13 : 4; + __IO uint32_t PSPD : 2; + uint32_t RESERVED19 :13; +} stc_usbfs_hprt_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + __IO uint32_t EPNUM : 4; + __IO uint32_t EPDIR : 1; + uint32_t RESERVED16 : 1; + __IO uint32_t LSDEV : 1; + __IO uint32_t EPTYP : 2; + uint32_t RESERVED20 : 2; + __IO uint32_t DAD : 7; + __IO uint32_t ODDFRM : 1; + __IO uint32_t CHDIS : 1; + __IO uint32_t CHENA : 1; +} stc_usbfs_hcchar_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t CHH : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t NAK : 1; + __IO uint32_t ACK : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXERR : 1; + __IO uint32_t BBERR : 1; + __IO uint32_t FRMOR : 1; + __IO uint32_t DTERR : 1; + uint32_t RESERVED11 :21; +} stc_usbfs_hcint_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t CHHM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STALLM : 1; + __IO uint32_t NAKM : 1; + __IO uint32_t ACKM : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXERRM : 1; + __IO uint32_t BBERRM : 1; + __IO uint32_t FRMORM : 1; + __IO uint32_t DTERRM : 1; + uint32_t RESERVED11 :21; +} stc_usbfs_hcintmsk_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + __IO uint32_t DPID : 2; + uint32_t RESERVED31 : 1; +} stc_usbfs_hctsiz_field_t; + +typedef struct +{ + __IO uint32_t DSPD : 2; + __IO uint32_t NZLSOHSK : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t DAD : 7; + __IO uint32_t PFIVL : 2; + uint32_t RESERVED13 :19; +} stc_usbfs_dcfg_field_t; + +typedef struct +{ + __IO uint32_t RWUSIG : 1; + __IO uint32_t SDIS : 1; + __IO uint32_t GINSTS : 1; + __IO uint32_t GONSTS : 1; + uint32_t RESERVED4 : 3; + __IO uint32_t SGINAK : 1; + __IO uint32_t CGINAK : 1; + __IO uint32_t SGONAK : 1; + __IO uint32_t CGONAK : 1; + __IO uint32_t POPRGDNE : 1; + uint32_t RESERVED12 :20; +} stc_usbfs_dctl_field_t; + +typedef struct +{ + __IO uint32_t SUSPSTS : 1; + __IO uint32_t ENUMSPD : 2; + __IO uint32_t EERR : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t FNSOF :14; + uint32_t RESERVED22 :10; +} stc_usbfs_dsts_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t EPDM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOM : 1; + __IO uint32_t ITTXFEMSK : 1; + __IO uint32_t INEPNMM : 1; + __IO uint32_t INEPNEM : 1; + uint32_t RESERVED7 :25; +} stc_usbfs_diepmsk_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t EPDM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STUPM : 1; + __IO uint32_t OTEPDM : 1; + uint32_t RESERVED5 :27; +} stc_usbfs_doepmsk_field_t; + +typedef struct +{ + __IO uint32_t IEPINT : 6; + uint32_t RESERVED6 :10; + __IO uint32_t OEPINT : 6; + uint32_t RESERVED22 :10; +} stc_usbfs_daint_field_t; + +typedef struct +{ + __IO uint32_t IEPINTM : 6; + uint32_t RESERVED6 :10; + __IO uint32_t OEPINTM : 6; + uint32_t RESERVED22 :10; +} stc_usbfs_daintmsk_field_t; + +typedef struct +{ + __IO uint32_t INEPTXFEM : 6; + uint32_t RESERVED6 :26; +} stc_usbfs_diepempmsk_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ : 2; + uint32_t RESERVED2 :13; + __IO uint32_t USBAEP : 1; + uint32_t RESERVED16 : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + uint32_t RESERVED20 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t TXFNUM : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + uint32_t RESERVED28 : 2; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_diepctl0_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOC : 1; + __IO uint32_t TTXFE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t INEPNE : 1; + __IO uint32_t TXFE : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_diepint0_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ : 7; + uint32_t RESERVED7 :12; + __IO uint32_t PKTCNT : 2; + uint32_t RESERVED21 :11; +} stc_usbfs_dieptsiz0_field_t; + +typedef struct +{ + __IO uint32_t INEPTFSAV :16; + uint32_t RESERVED16 :16; +} stc_usbfs_dtxfsts0_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + uint32_t RESERVED11 : 4; + __IO uint32_t USBAEP : 1; + __IO uint32_t EONUM_DPID : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + uint32_t RESERVED20 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t TXFNUM : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + __IO uint32_t SD0PID_SEVNFRM : 1; + __IO uint32_t SODDFRM : 1; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_diepctl_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOC : 1; + __IO uint32_t TTXFE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t INEPNE : 1; + __IO uint32_t TXFE : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_diepint_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + uint32_t RESERVED29 : 3; +} stc_usbfs_dieptsiz_field_t; + +typedef struct +{ + __IO uint32_t INEPTFSAV :16; + uint32_t RESERVED16 :16; +} stc_usbfs_dtxfsts_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ : 2; + uint32_t RESERVED2 :13; + __IO uint32_t USBAEP : 1; + uint32_t RESERVED16 : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + __IO uint32_t SNPM : 1; + __IO uint32_t STALL : 1; + uint32_t RESERVED22 : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + uint32_t RESERVED28 : 2; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_doepctl0_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STUP : 1; + __IO uint32_t OTEPDIS : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t B2BSTUP : 1; + uint32_t RESERVED7 :25; +} stc_usbfs_doepint_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ : 7; + uint32_t RESERVED7 :12; + __IO uint32_t PKTCNT : 1; + uint32_t RESERVED20 : 9; + __IO uint32_t STUPCNT : 2; + uint32_t RESERVED31 : 1; +} stc_usbfs_doeptsiz0_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + uint32_t RESERVED11 : 4; + __IO uint32_t USBAEP : 1; + __IO uint32_t DPID : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + __IO uint32_t SNPM : 1; + __IO uint32_t STALL : 1; + uint32_t RESERVED22 : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + __IO uint32_t SD0PID : 1; + __IO uint32_t SD1PID : 1; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_doepctl_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + uint32_t RESERVED29 : 3; +} stc_usbfs_doeptsiz_field_t; + +typedef struct +{ + __IO uint32_t STPPCLK : 1; + __IO uint32_t GATEHCLK : 1; + uint32_t RESERVED2 :30; +} stc_usbfs_pcgcctl_field_t; + +typedef struct +{ + __IO uint32_t PERI : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t CKS : 4; + __IO uint32_t WDPT : 4; + uint32_t RESERVED12 : 4; + __IO uint32_t SLPOFF : 1; + uint32_t RESERVED17 :14; + __IO uint32_t ITS : 1; +} stc_wdt_cr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + __IO uint32_t UDF : 1; + __IO uint32_t REF : 1; + uint32_t RESERVED18 :14; +} stc_wdt_sr_field_t; + +typedef struct +{ + __IO uint32_t RF :16; + uint32_t RESERVED16 :16; +} stc_wdt_rr_field_t; + +typedef struct +{ + __IO uint16_t WKTMCMP :12; + __IO uint16_t WKOVF : 1; + __IO uint16_t WKCKS : 2; + __IO uint16_t WKTCE : 1; +} stc_wktm_cr_field_t; + + +typedef struct +{ + union + { + __IO uint8_t STR; + stc_adc_str_field_t STR_f; + }; + uint8_t RESERVED1[1]; + union + { + __IO uint16_t CR0; + stc_adc_cr0_field_t CR0_f; + }; + union + { + __IO uint16_t CR1; + stc_adc_cr1_field_t CR1_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint16_t TRGSR; + stc_adc_trgsr_field_t TRGSR_f; + }; + __IO uint16_t CHSELRA0; + union + { + __IO uint16_t CHSELRA1; + stc_adc_chselra1_field_t CHSELRA1_f; + }; + __IO uint16_t CHSELRB0; + union + { + __IO uint16_t CHSELRB1; + stc_adc_chselrb1_field_t CHSELRB1_f; + }; + __IO uint16_t AVCHSELR0; + union + { + __IO uint16_t AVCHSELR1; + stc_adc_avchselr1_field_t AVCHSELR1_f; + }; + uint8_t RESERVED10[8]; + __IO uint8_t SSTR0; + __IO uint8_t SSTR1; + __IO uint8_t SSTR2; + __IO uint8_t SSTR3; + __IO uint8_t SSTR4; + __IO uint8_t SSTR5; + __IO uint8_t SSTR6; + __IO uint8_t SSTR7; + __IO uint8_t SSTR8; + __IO uint8_t SSTR9; + __IO uint8_t SSTR10; + __IO uint8_t SSTR11; + __IO uint8_t SSTR12; + __IO uint8_t SSTR13; + __IO uint8_t SSTR14; + __IO uint8_t SSTR15; + __IO uint8_t SSTRL; + uint8_t RESERVED27[7]; + union + { + __IO uint16_t CHMUXR0; + stc_adc_chmuxr0_field_t CHMUXR0_f; + }; + union + { + __IO uint16_t CHMUXR1; + stc_adc_chmuxr1_field_t CHMUXR1_f; + }; + union + { + __IO uint16_t CHMUXR2; + stc_adc_chmuxr2_field_t CHMUXR2_f; + }; + union + { + __IO uint16_t CHMUXR3; + stc_adc_chmuxr3_field_t CHMUXR3_f; + }; + uint8_t RESERVED31[6]; + union + { + __IO uint8_t ISR; + stc_adc_isr_field_t ISR_f; + }; + union + { + __IO uint8_t ICR; + stc_adc_icr_field_t ICR_f; + }; + uint8_t RESERVED33[4]; + union + { + __IO uint16_t SYNCCR; + stc_adc_synccr_field_t SYNCCR_f; + }; + uint8_t RESERVED34[2]; + __IO uint16_t DR0; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t DR3; + __IO uint16_t DR4; + __IO uint16_t DR5; + __IO uint16_t DR6; + __IO uint16_t DR7; + __IO uint16_t DR8; + __IO uint16_t DR9; + __IO uint16_t DR10; + __IO uint16_t DR11; + __IO uint16_t DR12; + __IO uint16_t DR13; + __IO uint16_t DR14; + __IO uint16_t DR15; + __IO uint16_t DR16; + uint8_t RESERVED51[46]; + union + { + __IO uint16_t AWDCR; + stc_adc_awdcr_field_t AWDCR_f; + }; + uint8_t RESERVED52[2]; + __IO uint16_t AWDDR0; + __IO uint16_t AWDDR1; + uint8_t RESERVED54[4]; + __IO uint16_t AWDCHSR0; + union + { + __IO uint16_t AWDCHSR1; + stc_adc_awdchsr1_field_t AWDCHSR1_f; + }; + __IO uint16_t AWDSR0; + union + { + __IO uint16_t AWDSR1; + stc_adc_awdsr1_field_t AWDSR1_f; + }; + uint8_t RESERVED58[12]; + union + { + __IO uint16_t PGACR; + stc_adc_pgacr_field_t PGACR_f; + }; + union + { + __IO uint16_t PGAGSR; + stc_adc_pgagsr_field_t PGAGSR_f; + }; + uint8_t RESERVED60[8]; + union + { + __IO uint16_t PGAINSR0; + stc_adc_pgainsr0_field_t PGAINSR0_f; + }; + union + { + __IO uint16_t PGAINSR1; + stc_adc_pgainsr1_field_t PGAINSR1_f; + }; +}M4_ADC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_aes_cr_field_t CR_f; + }; + uint8_t RESERVED1[12]; + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t KR0; + __IO uint32_t KR1; + __IO uint32_t KR2; + __IO uint32_t KR3; +}M4_AES_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t INT_SFTTRG; + stc_aos_int_sfttrg_field_t INT_SFTTRG_f; + }; + union + { + __IO uint32_t DCU1_TRGSEL; + stc_aos_dcu1_trgsel_field_t DCU1_TRGSEL_f; + }; + union + { + __IO uint32_t DCU2_TRGSEL; + stc_aos_dcu2_trgsel_field_t DCU2_TRGSEL_f; + }; + union + { + __IO uint32_t DCU3_TRGSEL; + stc_aos_dcu3_trgsel_field_t DCU3_TRGSEL_f; + }; + union + { + __IO uint32_t DCU4_TRGSEL; + stc_aos_dcu4_trgsel_field_t DCU4_TRGSEL_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL0; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL0_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL1; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL1_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL2; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL2_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL3; + stc_aos_dma1_trgsel3_field_t DMA1_TRGSEL3_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL0; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL0_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL1; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL1_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL2; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL2_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL3; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL3_f; + }; + union + { + __IO uint32_t DMA_TRGSELRC; + stc_aos_dma_trgselrc_field_t DMA_TRGSELRC_f; + }; + union + { + __IO uint32_t TMR6_HTSSR1; + stc_aos_tmr6_htssr_field_t TMR6_HTSSR1_f; + }; + union + { + __IO uint32_t TMR6_HTSSR2; + stc_aos_tmr6_htssr_field_t TMR6_HTSSR2_f; + }; + union + { + __IO uint32_t TMR0_HTSSR; + stc_aos_tmr0_htssr_field_t TMR0_HTSSR_f; + }; + union + { + __IO uint32_t PORT_PEVNTTRGSR12; + stc_aos_port_pevnttrgsr12_field_t PORT_PEVNTTRGSR12_f; + }; + union + { + __IO uint32_t PORT_PEVNTTRGSR34; + stc_aos_port_pevnttrgsr34_field_t PORT_PEVNTTRGSR34_f; + }; + union + { + __IO uint32_t TMRA_HTSSR0; + stc_aos_tmra_htssr_field_t TMRA_HTSSR0_f; + }; + union + { + __IO uint32_t TMRA_HTSSR1; + stc_aos_tmra_htssr_field_t TMRA_HTSSR1_f; + }; + union + { + __IO uint32_t OTS_TRG; + stc_aos_ots_trg_field_t OTS_TRG_f; + }; + union + { + __IO uint32_t ADC1_ITRGSELR0; + stc_aos_adc1_itrgselr_field_t ADC1_ITRGSELR0_f; + }; + union + { + __IO uint32_t ADC1_ITRGSELR1; + stc_aos_adc1_itrgselr_field_t ADC1_ITRGSELR1_f; + }; + union + { + __IO uint32_t ADC2_ITRGSELR0; + stc_aos_adc2_itrgselr_field_t ADC2_ITRGSELR0_f; + }; + union + { + __IO uint32_t ADC2_ITRGSELR1; + stc_aos_adc2_itrgselr_field_t ADC2_ITRGSELR1_f; + }; + union + { + __IO uint32_t COMTRG1; + stc_aos_comtrg1_field_t COMTRG1_f; + }; + union + { + __IO uint32_t COMTRG2; + stc_aos_comtrg2_field_t COMTRG2_f; + }; + uint8_t RESERVED28[144]; + union + { + __IO uint32_t PEVNTDIRR1; + stc_aos_pevntdirr_field_t PEVNTDIRR1_f; + }; + union + { + __IO uint32_t PEVNTIDR1; + stc_aos_pevntidr_field_t PEVNTIDR1_f; + }; + union + { + __IO uint32_t PEVNTODR1; + stc_aos_pevntodr_field_t PEVNTODR1_f; + }; + union + { + __IO uint32_t PEVNTORR1; + stc_aos_pevntorr_field_t PEVNTORR1_f; + }; + union + { + __IO uint32_t PEVNTOSR1; + stc_aos_pevntosr_field_t PEVNTOSR1_f; + }; + union + { + __IO uint32_t PEVNTRISR1; + stc_aos_pevntrisr_field_t PEVNTRISR1_f; + }; + union + { + __IO uint32_t PEVNTFAL1; + stc_aos_pevntfal_field_t PEVNTFAL1_f; + }; + union + { + __IO uint32_t PEVNTDIRR2; + stc_aos_pevntdirr_field_t PEVNTDIRR2_f; + }; + union + { + __IO uint32_t PEVNTIDR2; + stc_aos_pevntidr_field_t PEVNTIDR2_f; + }; + union + { + __IO uint32_t PEVNTODR2; + stc_aos_pevntodr_field_t PEVNTODR2_f; + }; + union + { + __IO uint32_t PEVNTORR2; + stc_aos_pevntorr_field_t PEVNTORR2_f; + }; + union + { + __IO uint32_t PEVNTOSR2; + stc_aos_pevntosr_field_t PEVNTOSR2_f; + }; + union + { + __IO uint32_t PEVNTRISR2; + stc_aos_pevntrisr_field_t PEVNTRISR2_f; + }; + union + { + __IO uint32_t PEVNTFAL2; + stc_aos_pevntfal_field_t PEVNTFAL2_f; + }; + union + { + __IO uint32_t PEVNTDIRR3; + stc_aos_pevntdirr_field_t PEVNTDIRR3_f; + }; + union + { + __IO uint32_t PEVNTIDR3; + stc_aos_pevntidr_field_t PEVNTIDR3_f; + }; + union + { + __IO uint32_t PEVNTODR3; + stc_aos_pevntodr_field_t PEVNTODR3_f; + }; + union + { + __IO uint32_t PEVNTORR3; + stc_aos_pevntorr_field_t PEVNTORR3_f; + }; + union + { + __IO uint32_t PEVNTOSR3; + stc_aos_pevntosr_field_t PEVNTOSR3_f; + }; + union + { + __IO uint32_t PEVNTRISR3; + stc_aos_pevntrisr_field_t PEVNTRISR3_f; + }; + union + { + __IO uint32_t PEVNTFAL3; + stc_aos_pevntfal_field_t PEVNTFAL3_f; + }; + union + { + __IO uint32_t PEVNTDIRR4; + stc_aos_pevntdirr_field_t PEVNTDIRR4_f; + }; + union + { + __IO uint32_t PEVNTIDR4; + stc_aos_pevntidr_field_t PEVNTIDR4_f; + }; + union + { + __IO uint32_t PEVNTODR4; + stc_aos_pevntodr_field_t PEVNTODR4_f; + }; + union + { + __IO uint32_t PEVNTORR4; + stc_aos_pevntorr_field_t PEVNTORR4_f; + }; + union + { + __IO uint32_t PEVNTOSR4; + stc_aos_pevntosr_field_t PEVNTOSR4_f; + }; + union + { + __IO uint32_t PEVNTRISR4; + stc_aos_pevntrisr_field_t PEVNTRISR4_f; + }; + union + { + __IO uint32_t PEVNTFAL4; + stc_aos_pevntfal_field_t PEVNTFAL4_f; + }; + union + { + __IO uint32_t PEVNTNFCR; + stc_aos_pevntnfcr_field_t PEVNTNFCR_f; + }; +}M4_AOS_TypeDef; + +typedef struct +{ + __IO uint32_t RBUF; + uint8_t RESERVED1[76]; + __IO uint32_t TBUF; + uint8_t RESERVED2[76]; + union + { + __IO uint8_t CFG_STAT; + stc_can_cfg_stat_field_t CFG_STAT_f; + }; + union + { + __IO uint8_t TCMD; + stc_can_tcmd_field_t TCMD_f; + }; + union + { + __IO uint8_t TCTRL; + stc_can_tctrl_field_t TCTRL_f; + }; + union + { + __IO uint8_t RCTRL; + stc_can_rctrl_field_t RCTRL_f; + }; + union + { + __IO uint8_t RTIE; + stc_can_rtie_field_t RTIE_f; + }; + union + { + __IO uint8_t RTIF; + stc_can_rtif_field_t RTIF_f; + }; + union + { + __IO uint8_t ERRINT; + stc_can_errint_field_t ERRINT_f; + }; + union + { + __IO uint8_t LIMIT; + stc_can_limit_field_t LIMIT_f; + }; + union + { + __IO uint32_t BT; + stc_can_bt_field_t BT_f; + }; + uint8_t RESERVED11[4]; + union + { + __IO uint8_t EALCAP; + stc_can_ealcap_field_t EALCAP_f; + }; + uint8_t RESERVED12[1]; + __IO uint8_t RECNT; + __IO uint8_t TECNT; + union + { + __IO uint8_t ACFCTRL; + stc_can_acfctrl_field_t ACFCTRL_f; + }; + uint8_t RESERVED15[1]; + union + { + __IO uint8_t ACFEN; + stc_can_acfen_field_t ACFEN_f; + }; + uint8_t RESERVED16[1]; + union + { + __IO uint32_t ACF; + stc_can_acf_field_t ACF_f; + }; + uint8_t RESERVED17[2]; + union + { + __IO uint8_t TBSLOT; + stc_can_tbslot_field_t TBSLOT_f; + }; + union + { + __IO uint8_t TTCFG; + stc_can_ttcfg_field_t TTCFG_f; + }; + union + { + __IO uint32_t REF_MSG; + stc_can_ref_msg_field_t REF_MSG_f; + }; + union + { + __IO uint16_t TRG_CFG; + stc_can_trg_cfg_field_t TRG_CFG_f; + }; + __IO uint16_t TT_TRIG; + __IO uint16_t TT_WTRIG; +}M4_CAN_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t CTRL; + stc_cmp_ctrl_field_t CTRL_f; + }; + union + { + __IO uint16_t VLTSEL; + stc_cmp_vltsel_field_t VLTSEL_f; + }; + union + { + __IO uint16_t MON; + stc_cmp_mon_field_t MON_f; + }; + union + { + __IO uint16_t CVSSTB; + stc_cmp_cvsstb_field_t CVSSTB_f; + }; + union + { + __IO uint16_t CVSPRD; + stc_cmp_cvsprd_field_t CVSPRD_f; + }; +}M4_CMP_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[256]; + union + { + __IO uint16_t DADR1; + stc_cmp_cr_dadr1_field_t DADR1_f; + }; + union + { + __IO uint16_t DADR2; + stc_cmp_cr_dadr2_field_t DADR2_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint16_t DACR; + stc_cmp_cr_dacr_field_t DACR_f; + }; + uint8_t RESERVED3[2]; + union + { + __IO uint16_t RVADC; + stc_cmp_cr_rvadc_field_t RVADC_f; + }; +}M4_CMP_CR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_crc_cr_field_t CR_f; + }; + __IO uint32_t RESLT; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t FLG; + stc_crc_flg_field_t FLG_f; + }; + uint8_t RESERVED3[112]; + __IO uint32_t DAT0; + __IO uint32_t DAT1; + __IO uint32_t DAT2; + __IO uint32_t DAT3; + __IO uint32_t DAT4; + __IO uint32_t DAT5; + __IO uint32_t DAT6; + __IO uint32_t DAT7; + __IO uint32_t DAT8; + __IO uint32_t DAT9; + __IO uint32_t DAT10; + __IO uint32_t DAT11; + __IO uint32_t DAT12; + __IO uint32_t DAT13; + __IO uint32_t DAT14; + __IO uint32_t DAT15; + __IO uint32_t DAT16; + __IO uint32_t DAT17; + __IO uint32_t DAT18; + __IO uint32_t DAT19; + __IO uint32_t DAT20; + __IO uint32_t DAT21; + __IO uint32_t DAT22; + __IO uint32_t DAT23; + __IO uint32_t DAT24; + __IO uint32_t DAT25; + __IO uint32_t DAT26; + __IO uint32_t DAT27; + __IO uint32_t DAT28; + __IO uint32_t DAT29; + __IO uint32_t DAT30; + __IO uint32_t DAT31; +}M4_CRC_TypeDef; + +typedef struct +{ + __IO uint32_t AUTHID0; + __IO uint32_t AUTHID1; + __IO uint32_t AUTHID2; + __IO uint32_t RESV0; + union + { + __IO uint32_t MCUSTAT; + stc_dbgc_mcustat_field_t MCUSTAT_f; + }; + union + { + __IO uint32_t MCUCTL; + stc_dbgc_mcuctl_field_t MCUCTL_f; + }; + union + { + __IO uint32_t FMCCTL; + stc_dbgc_fmcctl_field_t FMCCTL_f; + }; + union + { + __IO uint32_t MCUDBGSTAT; + stc_dbgc_mcudbgstat_field_t MCUDBGSTAT_f; + }; + union + { + __IO uint32_t MCUSTPCTL; + stc_dbgc_mcustpctl_field_t MCUSTPCTL_f; + }; + union + { + __IO uint32_t MCUTRACECTL; + stc_dbgc_mcutracectl_field_t MCUTRACECTL_f; + }; +}M4_DBGC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CTL; + stc_dcu_ctl_field_t CTL_f; + }; + union + { + __IO uint32_t FLAG; + stc_dcu_flag_field_t FLAG_f; + }; + __IO uint32_t DATA0; + __IO uint32_t DATA1; + __IO uint32_t DATA2; + union + { + __IO uint32_t FLAGCLR; + stc_dcu_flagclr_field_t FLAGCLR_f; + }; + union + { + __IO uint32_t INTSEL; + stc_dcu_intsel_field_t INTSEL_f; + }; +}M4_DCU_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t EN; + stc_dma_en_field_t EN_f; + }; + union + { + __IO uint32_t INTSTAT0; + stc_dma_intstat0_field_t INTSTAT0_f; + }; + union + { + __IO uint32_t INTSTAT1; + stc_dma_intstat1_field_t INTSTAT1_f; + }; + union + { + __IO uint32_t INTMASK0; + stc_dma_intmask0_field_t INTMASK0_f; + }; + union + { + __IO uint32_t INTMASK1; + stc_dma_intmask1_field_t INTMASK1_f; + }; + union + { + __IO uint32_t INTCLR0; + stc_dma_intclr0_field_t INTCLR0_f; + }; + union + { + __IO uint32_t INTCLR1; + stc_dma_intclr1_field_t INTCLR1_f; + }; + union + { + __IO uint32_t CHEN; + stc_dma_chen_field_t CHEN_f; + }; + uint8_t RESERVED8[4]; + union + { + __IO uint32_t CHSTAT; + stc_dma_chstat_field_t CHSTAT_f; + }; + uint8_t RESERVED9[4]; + union + { + __IO uint32_t RCFGCTL; + stc_dma_rcfgctl_field_t RCFGCTL_f; + }; + uint8_t RESERVED10[16]; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + union + { + __IO uint32_t DTCTL0; + stc_dma_dtctl_field_t DTCTL0_f; + }; + union + { + __IO uint32_t RPT0; + stc_dma_rpt_field_t RPT0_f; + __IO uint32_t RPTB0; + stc_dma_rptb_field_t RPTB0_f; + }; + union + { + __IO uint32_t SNSEQCTL0; + stc_dma_snseqctl_field_t SNSEQCTL0_f; + __IO uint32_t SNSEQCTLB0; + stc_dma_snseqctlb_field_t SNSEQCTLB0_f; + }; + union + { + __IO uint32_t DNSEQCTL0; + stc_dma_dnseqctl_field_t DNSEQCTL0_f; + __IO uint32_t DNSEQCTLB0; + stc_dma_dnseqctlb_field_t DNSEQCTLB0_f; + }; + union + { + __IO uint32_t LLP0; + stc_dma_llp_field_t LLP0_f; + }; + union + { + __IO uint32_t CH0CTL; + stc_dma_ch0ctl_field_t CH0CTL_f; + }; + __IO uint32_t MONSAR0; + __IO uint32_t MONDAR0; + union + { + __IO uint32_t MONDTCTL0; + stc_dma_mondtctl_field_t MONDTCTL0_f; + }; + union + { + __IO uint32_t MONRPT0; + stc_dma_monrpt_field_t MONRPT0_f; + }; + union + { + __IO uint32_t MONSNSEQCTL0; + stc_dma_monsnseqctl_field_t MONSNSEQCTL0_f; + }; + union + { + __IO uint32_t MONDNSEQCTL0; + stc_dma_mondnseqctl_field_t MONDNSEQCTL0_f; + }; + uint8_t RESERVED27[8]; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + union + { + __IO uint32_t DTCTL1; + stc_dma_dtctl_field_t DTCTL1_f; + }; + union + { + __IO uint32_t RPT1; + stc_dma_rpt_field_t RPT1_f; + __IO uint32_t RPTB1; + stc_dma_rptb_field_t RPTB1_f; + }; + union + { + __IO uint32_t SNSEQCTL1; + stc_dma_snseqctl_field_t SNSEQCTL1_f; + __IO uint32_t SNSEQCTLB1; + stc_dma_snseqctlb_field_t SNSEQCTLB1_f; + }; + union + { + __IO uint32_t DNSEQCTL1; + stc_dma_dnseqctl_field_t DNSEQCTL1_f; + __IO uint32_t DNSEQCTLB1; + stc_dma_dnseqctlb_field_t DNSEQCTLB1_f; + }; + union + { + __IO uint32_t LLP1; + stc_dma_llp_field_t LLP1_f; + }; + union + { + __IO uint32_t CH1CTL; + stc_dma_ch1ctl_field_t CH1CTL_f; + }; + __IO uint32_t MONSAR1; + __IO uint32_t MONDAR1; + union + { + __IO uint32_t MONDTCTL1; + stc_dma_mondtctl_field_t MONDTCTL1_f; + }; + union + { + __IO uint32_t MONRPT1; + stc_dma_monrpt_field_t MONRPT1_f; + }; + union + { + __IO uint32_t MONSNSEQCTL1; + stc_dma_monsnseqctl_field_t MONSNSEQCTL1_f; + }; + union + { + __IO uint32_t MONDNSEQCTL1; + stc_dma_mondnseqctl_field_t MONDNSEQCTL1_f; + }; + uint8_t RESERVED44[8]; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + union + { + __IO uint32_t DTCTL2; + stc_dma_dtctl_field_t DTCTL2_f; + }; + union + { + __IO uint32_t RPT2; + stc_dma_rpt_field_t RPT2_f; + __IO uint32_t RPTB2; + stc_dma_rptb_field_t RPTB2_f; + }; + union + { + __IO uint32_t SNSEQCTL2; + stc_dma_snseqctl_field_t SNSEQCTL2_f; + __IO uint32_t SNSEQCTLB2; + stc_dma_snseqctlb_field_t SNSEQCTLB2_f; + }; + union + { + __IO uint32_t DNSEQCTL2; + stc_dma_dnseqctl_field_t DNSEQCTL2_f; + __IO uint32_t DNSEQCTLB2; + stc_dma_dnseqctlb_field_t DNSEQCTLB2_f; + }; + union + { + __IO uint32_t LLP2; + stc_dma_llp_field_t LLP2_f; + }; + union + { + __IO uint32_t CH2CTL; + stc_dma_ch2ctl_field_t CH2CTL_f; + }; + __IO uint32_t MONSAR2; + __IO uint32_t MONDAR2; + union + { + __IO uint32_t MONDTCTL2; + stc_dma_mondtctl_field_t MONDTCTL2_f; + }; + union + { + __IO uint32_t MONRPT2; + stc_dma_monrpt_field_t MONRPT2_f; + }; + union + { + __IO uint32_t MONSNSEQCTL2; + stc_dma_monsnseqctl_field_t MONSNSEQCTL2_f; + }; + union + { + __IO uint32_t MONDNSEQCTL2; + stc_dma_mondnseqctl_field_t MONDNSEQCTL2_f; + }; + uint8_t RESERVED61[8]; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + union + { + __IO uint32_t DTCTL3; + stc_dma_dtctl_field_t DTCTL3_f; + }; + union + { + __IO uint32_t RPT3; + stc_dma_rpt_field_t RPT3_f; + __IO uint32_t RPTB3; + stc_dma_rptb_field_t RPTB3_f; + }; + union + { + __IO uint32_t SNSEQCTL3; + stc_dma_snseqctl_field_t SNSEQCTL3_f; + __IO uint32_t SNSEQCTLB3; + stc_dma_snseqctlb_field_t SNSEQCTLB3_f; + }; + union + { + __IO uint32_t DNSEQCTL3; + stc_dma_dnseqctl_field_t DNSEQCTL3_f; + __IO uint32_t DNSEQCTLB3; + stc_dma_dnseqctlb_field_t DNSEQCTLB3_f; + }; + union + { + __IO uint32_t LLP3; + stc_dma_llp_field_t LLP3_f; + }; + union + { + __IO uint32_t CH3CTL; + stc_dma_ch3ctl_field_t CH3CTL_f; + }; + __IO uint32_t MONSAR3; + __IO uint32_t MONDAR3; + union + { + __IO uint32_t MONDTCTL3; + stc_dma_mondtctl_field_t MONDTCTL3_f; + }; + union + { + __IO uint32_t MONRPT3; + stc_dma_monrpt_field_t MONRPT3_f; + }; + union + { + __IO uint32_t MONSNSEQCTL3; + stc_dma_monsnseqctl_field_t MONSNSEQCTL3_f; + }; + union + { + __IO uint32_t MONDNSEQCTL3; + stc_dma_mondnseqctl_field_t MONDNSEQCTL3_f; + }; +}M4_DMA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t FAPRT; + stc_efm_faprt_field_t FAPRT_f; + }; + union + { + __IO uint32_t FSTP; + stc_efm_fstp_field_t FSTP_f; + }; + union + { + __IO uint32_t FRMC; + stc_efm_frmc_field_t FRMC_f; + }; + union + { + __IO uint32_t FWMC; + stc_efm_fwmc_field_t FWMC_f; + }; + union + { + __IO uint32_t FSR; + stc_efm_fsr_field_t FSR_f; + }; + union + { + __IO uint32_t FSCLR; + stc_efm_fsclr_field_t FSCLR_f; + }; + union + { + __IO uint32_t FITE; + stc_efm_fite_field_t FITE_f; + }; + union + { + __IO uint32_t FSWP; + stc_efm_fswp_field_t FSWP_f; + }; + union + { + __IO uint32_t FPMTSW; + stc_efm_fpmtsw_field_t FPMTSW_f; + }; + union + { + __IO uint32_t FPMTEW; + stc_efm_fpmtew_field_t FPMTEW_f; + }; + uint8_t RESERVED10[40]; + __IO uint32_t UQID1; + __IO uint32_t UQID2; + __IO uint32_t UQID3; + uint8_t RESERVED13[164]; + union + { + __IO uint32_t MMF_REMPRT; + stc_efm_mmf_remprt_field_t MMF_REMPRT_f; + }; + union + { + __IO uint32_t MMF_REMCR0; + stc_efm_mmf_remcr0_field_t MMF_REMCR0_f; + }; + union + { + __IO uint32_t MMF_REMCR1; + stc_efm_mmf_remcr1_field_t MMF_REMCR1_f; + }; + uint8_t RESERVED16[248]; + union + { + __IO uint32_t EFM_FRANDS; + stc_efm_efm_frands_field_t EFM_FRANDS_f; + }; +}M4_EFM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CTL; + stc_emb_ctl_field_t CTL_f; + }; + union + { + __IO uint32_t PWMLV; + stc_emb_pwmlv_field_t PWMLV_f; + }; + union + { + __IO uint32_t SOE; + stc_emb_soe_field_t SOE_f; + }; + union + { + __IO uint32_t STAT; + stc_emb_stat_field_t STAT_f; + }; + union + { + __IO uint32_t STATCLR; + stc_emb_statclr_field_t STATCLR_f; + }; + union + { + __IO uint32_t INTEN; + stc_emb_inten_field_t INTEN_f; + }; +}M4_EMB_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t LVR; + stc_fcm_lvr_field_t LVR_f; + }; + union + { + __IO uint32_t UVR; + stc_fcm_uvr_field_t UVR_f; + }; + union + { + __IO uint32_t CNTR; + stc_fcm_cntr_field_t CNTR_f; + }; + union + { + __IO uint32_t STR; + stc_fcm_str_field_t STR_f; + }; + union + { + __IO uint32_t MCCR; + stc_fcm_mccr_field_t MCCR_f; + }; + union + { + __IO uint32_t RCCR; + stc_fcm_rccr_field_t RCCR_f; + }; + union + { + __IO uint32_t RIER; + stc_fcm_rier_field_t RIER_f; + }; + union + { + __IO uint32_t SR; + stc_fcm_sr_field_t SR_f; + }; + union + { + __IO uint32_t CLR; + stc_fcm_clr_field_t CLR_f; + }; +}M4_FCM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_hash_cr_field_t CR_f; + }; + uint8_t RESERVED1[12]; + __IO uint32_t HR7; + __IO uint32_t HR6; + __IO uint32_t HR5; + __IO uint32_t HR4; + __IO uint32_t HR3; + __IO uint32_t HR2; + __IO uint32_t HR1; + __IO uint32_t HR0; + uint8_t RESERVED9[16]; + __IO uint32_t DR15; + __IO uint32_t DR14; + __IO uint32_t DR13; + __IO uint32_t DR12; + __IO uint32_t DR11; + __IO uint32_t DR10; + __IO uint32_t DR9; + __IO uint32_t DR8; + __IO uint32_t DR7; + __IO uint32_t DR6; + __IO uint32_t DR5; + __IO uint32_t DR4; + __IO uint32_t DR3; + __IO uint32_t DR2; + __IO uint32_t DR1; + __IO uint32_t DR0; +}M4_HASH_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR1; + stc_i2c_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_i2c_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t CR3; + stc_i2c_cr3_field_t CR3_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t SLR0; + stc_i2c_slr0_field_t SLR0_f; + }; + union + { + __IO uint32_t SLR1; + stc_i2c_slr1_field_t SLR1_f; + }; + union + { + __IO uint32_t SLTR; + stc_i2c_sltr_field_t SLTR_f; + }; + union + { + __IO uint32_t SR; + stc_i2c_sr_field_t SR_f; + }; + union + { + __IO uint32_t CLR; + stc_i2c_clr_field_t CLR_f; + }; + union + { + __IO uint8_t DTR; + stc_i2c_dtr_field_t DTR_f; + }; + uint8_t RESERVED9[3]; + union + { + __IO uint8_t DRR; + stc_i2c_drr_field_t DRR_f; + }; + uint8_t RESERVED10[3]; + union + { + __IO uint32_t CCR; + stc_i2c_ccr_field_t CCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_i2c_fltr_field_t FLTR_f; + }; +}M4_I2C_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CTRL; + stc_i2s_ctrl_field_t CTRL_f; + }; + union + { + __IO uint32_t SR; + stc_i2s_sr_field_t SR_f; + }; + union + { + __IO uint32_t ER; + stc_i2s_er_field_t ER_f; + }; + union + { + __IO uint32_t CFGR; + stc_i2s_cfgr_field_t CFGR_f; + }; + __IO uint32_t TXBUF; + __IO uint32_t RXBUF; + union + { + __IO uint32_t PR; + stc_i2s_pr_field_t PR_f; + }; +}M4_I2S_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ICG0; + stc_icg_icg0_field_t ICG0_f; + }; + union + { + __IO uint32_t ICG1; + stc_icg_icg1_field_t ICG1_f; + }; + __IO uint32_t ICG2; + __IO uint32_t ICG3; + __IO uint32_t ICG4; + __IO uint32_t ICG5; + __IO uint32_t ICG6; + __IO uint32_t ICG7; +}M4_ICG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t NMICR; + stc_intc_nmicr_field_t NMICR_f; + }; + union + { + __IO uint32_t NMIENR; + stc_intc_nmienr_field_t NMIENR_f; + }; + union + { + __IO uint32_t NMIFR; + stc_intc_nmifr_field_t NMIFR_f; + }; + union + { + __IO uint32_t NMICFR; + stc_intc_nmicfr_field_t NMICFR_f; + }; + union + { + __IO uint32_t EIRQCR0; + stc_intc_eirqcr_field_t EIRQCR0_f; + }; + union + { + __IO uint32_t EIRQCR1; + stc_intc_eirqcr_field_t EIRQCR1_f; + }; + union + { + __IO uint32_t EIRQCR2; + stc_intc_eirqcr_field_t EIRQCR2_f; + }; + union + { + __IO uint32_t EIRQCR3; + stc_intc_eirqcr_field_t EIRQCR3_f; + }; + union + { + __IO uint32_t EIRQCR4; + stc_intc_eirqcr_field_t EIRQCR4_f; + }; + union + { + __IO uint32_t EIRQCR5; + stc_intc_eirqcr_field_t EIRQCR5_f; + }; + union + { + __IO uint32_t EIRQCR6; + stc_intc_eirqcr_field_t EIRQCR6_f; + }; + union + { + __IO uint32_t EIRQCR7; + stc_intc_eirqcr_field_t EIRQCR7_f; + }; + union + { + __IO uint32_t EIRQCR8; + stc_intc_eirqcr_field_t EIRQCR8_f; + }; + union + { + __IO uint32_t EIRQCR9; + stc_intc_eirqcr_field_t EIRQCR9_f; + }; + union + { + __IO uint32_t EIRQCR10; + stc_intc_eirqcr_field_t EIRQCR10_f; + }; + union + { + __IO uint32_t EIRQCR11; + stc_intc_eirqcr_field_t EIRQCR11_f; + }; + union + { + __IO uint32_t EIRQCR12; + stc_intc_eirqcr_field_t EIRQCR12_f; + }; + union + { + __IO uint32_t EIRQCR13; + stc_intc_eirqcr_field_t EIRQCR13_f; + }; + union + { + __IO uint32_t EIRQCR14; + stc_intc_eirqcr_field_t EIRQCR14_f; + }; + union + { + __IO uint32_t EIRQCR15; + stc_intc_eirqcr_field_t EIRQCR15_f; + }; + union + { + __IO uint32_t WUPEN; + stc_intc_wupen_field_t WUPEN_f; + }; + union + { + __IO uint32_t EIFR; + stc_intc_eifr_field_t EIFR_f; + }; + union + { + __IO uint32_t EICFR; + stc_intc_eicfr_field_t EICFR_f; + }; + union + { + __IO uint32_t SEL0; + stc_intc_sel_field_t SEL0_f; + }; + union + { + __IO uint32_t SEL1; + stc_intc_sel_field_t SEL1_f; + }; + union + { + __IO uint32_t SEL2; + stc_intc_sel_field_t SEL2_f; + }; + union + { + __IO uint32_t SEL3; + stc_intc_sel_field_t SEL3_f; + }; + union + { + __IO uint32_t SEL4; + stc_intc_sel_field_t SEL4_f; + }; + union + { + __IO uint32_t SEL5; + stc_intc_sel_field_t SEL5_f; + }; + union + { + __IO uint32_t SEL6; + stc_intc_sel_field_t SEL6_f; + }; + union + { + __IO uint32_t SEL7; + stc_intc_sel_field_t SEL7_f; + }; + union + { + __IO uint32_t SEL8; + stc_intc_sel_field_t SEL8_f; + }; + union + { + __IO uint32_t SEL9; + stc_intc_sel_field_t SEL9_f; + }; + union + { + __IO uint32_t SEL10; + stc_intc_sel_field_t SEL10_f; + }; + union + { + __IO uint32_t SEL11; + stc_intc_sel_field_t SEL11_f; + }; + union + { + __IO uint32_t SEL12; + stc_intc_sel_field_t SEL12_f; + }; + union + { + __IO uint32_t SEL13; + stc_intc_sel_field_t SEL13_f; + }; + union + { + __IO uint32_t SEL14; + stc_intc_sel_field_t SEL14_f; + }; + union + { + __IO uint32_t SEL15; + stc_intc_sel_field_t SEL15_f; + }; + union + { + __IO uint32_t SEL16; + stc_intc_sel_field_t SEL16_f; + }; + union + { + __IO uint32_t SEL17; + stc_intc_sel_field_t SEL17_f; + }; + union + { + __IO uint32_t SEL18; + stc_intc_sel_field_t SEL18_f; + }; + union + { + __IO uint32_t SEL19; + stc_intc_sel_field_t SEL19_f; + }; + union + { + __IO uint32_t SEL20; + stc_intc_sel_field_t SEL20_f; + }; + union + { + __IO uint32_t SEL21; + stc_intc_sel_field_t SEL21_f; + }; + union + { + __IO uint32_t SEL22; + stc_intc_sel_field_t SEL22_f; + }; + union + { + __IO uint32_t SEL23; + stc_intc_sel_field_t SEL23_f; + }; + union + { + __IO uint32_t SEL24; + stc_intc_sel_field_t SEL24_f; + }; + union + { + __IO uint32_t SEL25; + stc_intc_sel_field_t SEL25_f; + }; + union + { + __IO uint32_t SEL26; + stc_intc_sel_field_t SEL26_f; + }; + union + { + __IO uint32_t SEL27; + stc_intc_sel_field_t SEL27_f; + }; + union + { + __IO uint32_t SEL28; + stc_intc_sel_field_t SEL28_f; + }; + union + { + __IO uint32_t SEL29; + stc_intc_sel_field_t SEL29_f; + }; + union + { + __IO uint32_t SEL30; + stc_intc_sel_field_t SEL30_f; + }; + union + { + __IO uint32_t SEL31; + stc_intc_sel_field_t SEL31_f; + }; + union + { + __IO uint32_t SEL32; + stc_intc_sel_field_t SEL32_f; + }; + union + { + __IO uint32_t SEL33; + stc_intc_sel_field_t SEL33_f; + }; + union + { + __IO uint32_t SEL34; + stc_intc_sel_field_t SEL34_f; + }; + union + { + __IO uint32_t SEL35; + stc_intc_sel_field_t SEL35_f; + }; + union + { + __IO uint32_t SEL36; + stc_intc_sel_field_t SEL36_f; + }; + union + { + __IO uint32_t SEL37; + stc_intc_sel_field_t SEL37_f; + }; + union + { + __IO uint32_t SEL38; + stc_intc_sel_field_t SEL38_f; + }; + union + { + __IO uint32_t SEL39; + stc_intc_sel_field_t SEL39_f; + }; + union + { + __IO uint32_t SEL40; + stc_intc_sel_field_t SEL40_f; + }; + union + { + __IO uint32_t SEL41; + stc_intc_sel_field_t SEL41_f; + }; + union + { + __IO uint32_t SEL42; + stc_intc_sel_field_t SEL42_f; + }; + union + { + __IO uint32_t SEL43; + stc_intc_sel_field_t SEL43_f; + }; + union + { + __IO uint32_t SEL44; + stc_intc_sel_field_t SEL44_f; + }; + union + { + __IO uint32_t SEL45; + stc_intc_sel_field_t SEL45_f; + }; + union + { + __IO uint32_t SEL46; + stc_intc_sel_field_t SEL46_f; + }; + union + { + __IO uint32_t SEL47; + stc_intc_sel_field_t SEL47_f; + }; + union + { + __IO uint32_t SEL48; + stc_intc_sel_field_t SEL48_f; + }; + union + { + __IO uint32_t SEL49; + stc_intc_sel_field_t SEL49_f; + }; + union + { + __IO uint32_t SEL50; + stc_intc_sel_field_t SEL50_f; + }; + union + { + __IO uint32_t SEL51; + stc_intc_sel_field_t SEL51_f; + }; + union + { + __IO uint32_t SEL52; + stc_intc_sel_field_t SEL52_f; + }; + union + { + __IO uint32_t SEL53; + stc_intc_sel_field_t SEL53_f; + }; + union + { + __IO uint32_t SEL54; + stc_intc_sel_field_t SEL54_f; + }; + union + { + __IO uint32_t SEL55; + stc_intc_sel_field_t SEL55_f; + }; + union + { + __IO uint32_t SEL56; + stc_intc_sel_field_t SEL56_f; + }; + union + { + __IO uint32_t SEL57; + stc_intc_sel_field_t SEL57_f; + }; + union + { + __IO uint32_t SEL58; + stc_intc_sel_field_t SEL58_f; + }; + union + { + __IO uint32_t SEL59; + stc_intc_sel_field_t SEL59_f; + }; + union + { + __IO uint32_t SEL60; + stc_intc_sel_field_t SEL60_f; + }; + union + { + __IO uint32_t SEL61; + stc_intc_sel_field_t SEL61_f; + }; + union + { + __IO uint32_t SEL62; + stc_intc_sel_field_t SEL62_f; + }; + union + { + __IO uint32_t SEL63; + stc_intc_sel_field_t SEL63_f; + }; + union + { + __IO uint32_t SEL64; + stc_intc_sel_field_t SEL64_f; + }; + union + { + __IO uint32_t SEL65; + stc_intc_sel_field_t SEL65_f; + }; + union + { + __IO uint32_t SEL66; + stc_intc_sel_field_t SEL66_f; + }; + union + { + __IO uint32_t SEL67; + stc_intc_sel_field_t SEL67_f; + }; + union + { + __IO uint32_t SEL68; + stc_intc_sel_field_t SEL68_f; + }; + union + { + __IO uint32_t SEL69; + stc_intc_sel_field_t SEL69_f; + }; + union + { + __IO uint32_t SEL70; + stc_intc_sel_field_t SEL70_f; + }; + union + { + __IO uint32_t SEL71; + stc_intc_sel_field_t SEL71_f; + }; + union + { + __IO uint32_t SEL72; + stc_intc_sel_field_t SEL72_f; + }; + union + { + __IO uint32_t SEL73; + stc_intc_sel_field_t SEL73_f; + }; + union + { + __IO uint32_t SEL74; + stc_intc_sel_field_t SEL74_f; + }; + union + { + __IO uint32_t SEL75; + stc_intc_sel_field_t SEL75_f; + }; + union + { + __IO uint32_t SEL76; + stc_intc_sel_field_t SEL76_f; + }; + union + { + __IO uint32_t SEL77; + stc_intc_sel_field_t SEL77_f; + }; + union + { + __IO uint32_t SEL78; + stc_intc_sel_field_t SEL78_f; + }; + union + { + __IO uint32_t SEL79; + stc_intc_sel_field_t SEL79_f; + }; + union + { + __IO uint32_t SEL80; + stc_intc_sel_field_t SEL80_f; + }; + union + { + __IO uint32_t SEL81; + stc_intc_sel_field_t SEL81_f; + }; + union + { + __IO uint32_t SEL82; + stc_intc_sel_field_t SEL82_f; + }; + union + { + __IO uint32_t SEL83; + stc_intc_sel_field_t SEL83_f; + }; + union + { + __IO uint32_t SEL84; + stc_intc_sel_field_t SEL84_f; + }; + union + { + __IO uint32_t SEL85; + stc_intc_sel_field_t SEL85_f; + }; + union + { + __IO uint32_t SEL86; + stc_intc_sel_field_t SEL86_f; + }; + union + { + __IO uint32_t SEL87; + stc_intc_sel_field_t SEL87_f; + }; + union + { + __IO uint32_t SEL88; + stc_intc_sel_field_t SEL88_f; + }; + union + { + __IO uint32_t SEL89; + stc_intc_sel_field_t SEL89_f; + }; + union + { + __IO uint32_t SEL90; + stc_intc_sel_field_t SEL90_f; + }; + union + { + __IO uint32_t SEL91; + stc_intc_sel_field_t SEL91_f; + }; + union + { + __IO uint32_t SEL92; + stc_intc_sel_field_t SEL92_f; + }; + union + { + __IO uint32_t SEL93; + stc_intc_sel_field_t SEL93_f; + }; + union + { + __IO uint32_t SEL94; + stc_intc_sel_field_t SEL94_f; + }; + union + { + __IO uint32_t SEL95; + stc_intc_sel_field_t SEL95_f; + }; + union + { + __IO uint32_t SEL96; + stc_intc_sel_field_t SEL96_f; + }; + union + { + __IO uint32_t SEL97; + stc_intc_sel_field_t SEL97_f; + }; + union + { + __IO uint32_t SEL98; + stc_intc_sel_field_t SEL98_f; + }; + union + { + __IO uint32_t SEL99; + stc_intc_sel_field_t SEL99_f; + }; + union + { + __IO uint32_t SEL100; + stc_intc_sel_field_t SEL100_f; + }; + union + { + __IO uint32_t SEL101; + stc_intc_sel_field_t SEL101_f; + }; + union + { + __IO uint32_t SEL102; + stc_intc_sel_field_t SEL102_f; + }; + union + { + __IO uint32_t SEL103; + stc_intc_sel_field_t SEL103_f; + }; + union + { + __IO uint32_t SEL104; + stc_intc_sel_field_t SEL104_f; + }; + union + { + __IO uint32_t SEL105; + stc_intc_sel_field_t SEL105_f; + }; + union + { + __IO uint32_t SEL106; + stc_intc_sel_field_t SEL106_f; + }; + union + { + __IO uint32_t SEL107; + stc_intc_sel_field_t SEL107_f; + }; + union + { + __IO uint32_t SEL108; + stc_intc_sel_field_t SEL108_f; + }; + union + { + __IO uint32_t SEL109; + stc_intc_sel_field_t SEL109_f; + }; + union + { + __IO uint32_t SEL110; + stc_intc_sel_field_t SEL110_f; + }; + union + { + __IO uint32_t SEL111; + stc_intc_sel_field_t SEL111_f; + }; + union + { + __IO uint32_t SEL112; + stc_intc_sel_field_t SEL112_f; + }; + union + { + __IO uint32_t SEL113; + stc_intc_sel_field_t SEL113_f; + }; + union + { + __IO uint32_t SEL114; + stc_intc_sel_field_t SEL114_f; + }; + union + { + __IO uint32_t SEL115; + stc_intc_sel_field_t SEL115_f; + }; + union + { + __IO uint32_t SEL116; + stc_intc_sel_field_t SEL116_f; + }; + union + { + __IO uint32_t SEL117; + stc_intc_sel_field_t SEL117_f; + }; + union + { + __IO uint32_t SEL118; + stc_intc_sel_field_t SEL118_f; + }; + union + { + __IO uint32_t SEL119; + stc_intc_sel_field_t SEL119_f; + }; + union + { + __IO uint32_t SEL120; + stc_intc_sel_field_t SEL120_f; + }; + union + { + __IO uint32_t SEL121; + stc_intc_sel_field_t SEL121_f; + }; + union + { + __IO uint32_t SEL122; + stc_intc_sel_field_t SEL122_f; + }; + union + { + __IO uint32_t SEL123; + stc_intc_sel_field_t SEL123_f; + }; + union + { + __IO uint32_t SEL124; + stc_intc_sel_field_t SEL124_f; + }; + union + { + __IO uint32_t SEL125; + stc_intc_sel_field_t SEL125_f; + }; + union + { + __IO uint32_t SEL126; + stc_intc_sel_field_t SEL126_f; + }; + union + { + __IO uint32_t SEL127; + stc_intc_sel_field_t SEL127_f; + }; + union + { + __IO uint32_t VSSEL128; + stc_intc_vssel_field_t VSSEL128_f; + }; + union + { + __IO uint32_t VSSEL129; + stc_intc_vssel_field_t VSSEL129_f; + }; + union + { + __IO uint32_t VSSEL130; + stc_intc_vssel_field_t VSSEL130_f; + }; + union + { + __IO uint32_t VSSEL131; + stc_intc_vssel_field_t VSSEL131_f; + }; + union + { + __IO uint32_t VSSEL132; + stc_intc_vssel_field_t VSSEL132_f; + }; + union + { + __IO uint32_t VSSEL133; + stc_intc_vssel_field_t VSSEL133_f; + }; + union + { + __IO uint32_t VSSEL134; + stc_intc_vssel_field_t VSSEL134_f; + }; + union + { + __IO uint32_t VSSEL135; + stc_intc_vssel_field_t VSSEL135_f; + }; + union + { + __IO uint32_t VSSEL136; + stc_intc_vssel_field_t VSSEL136_f; + }; + union + { + __IO uint32_t VSSEL137; + stc_intc_vssel_field_t VSSEL137_f; + }; + union + { + __IO uint32_t VSSEL138; + stc_intc_vssel_field_t VSSEL138_f; + }; + union + { + __IO uint32_t VSSEL139; + stc_intc_vssel_field_t VSSEL139_f; + }; + union + { + __IO uint32_t VSSEL140; + stc_intc_vssel_field_t VSSEL140_f; + }; + union + { + __IO uint32_t VSSEL141; + stc_intc_vssel_field_t VSSEL141_f; + }; + union + { + __IO uint32_t VSSEL142; + stc_intc_vssel_field_t VSSEL142_f; + }; + union + { + __IO uint32_t VSSEL143; + stc_intc_vssel_field_t VSSEL143_f; + }; + union + { + __IO uint32_t SWIER; + stc_intc_swier_field_t SWIER_f; + }; + union + { + __IO uint32_t EVTER; + stc_intc_evter_field_t EVTER_f; + }; + union + { + __IO uint32_t IER; + stc_intc_ier_field_t IER_f; + }; +}M4_INTC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SCR; + stc_keyscan_scr_field_t SCR_f; + }; + union + { + __IO uint32_t SER; + stc_keyscan_ser_field_t SER_f; + }; + union + { + __IO uint32_t SSR; + stc_keyscan_ssr_field_t SSR_f; + }; +}M4_KEYSCAN_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t RGD0; + stc_mpu_rgd0_field_t RGD0_f; + }; + union + { + __IO uint32_t RGD1; + stc_mpu_rgd1_field_t RGD1_f; + }; + union + { + __IO uint32_t RGD2; + stc_mpu_rgd2_field_t RGD2_f; + }; + union + { + __IO uint32_t RGD3; + stc_mpu_rgd3_field_t RGD3_f; + }; + union + { + __IO uint32_t RGD4; + stc_mpu_rgd4_field_t RGD4_f; + }; + union + { + __IO uint32_t RGD5; + stc_mpu_rgd5_field_t RGD5_f; + }; + union + { + __IO uint32_t RGD6; + stc_mpu_rgd6_field_t RGD6_f; + }; + union + { + __IO uint32_t RGD7; + stc_mpu_rgd7_field_t RGD7_f; + }; + union + { + __IO uint32_t RGD8; + stc_mpu_rgd8_field_t RGD8_f; + }; + union + { + __IO uint32_t RGD9; + stc_mpu_rgd9_field_t RGD9_f; + }; + union + { + __IO uint32_t RGD10; + stc_mpu_rgd10_field_t RGD10_f; + }; + union + { + __IO uint32_t RGD11; + stc_mpu_rgd11_field_t RGD11_f; + }; + union + { + __IO uint32_t RGD12; + stc_mpu_rgd12_field_t RGD12_f; + }; + union + { + __IO uint32_t RGD13; + stc_mpu_rgd13_field_t RGD13_f; + }; + union + { + __IO uint32_t RGD14; + stc_mpu_rgd14_field_t RGD14_f; + }; + union + { + __IO uint32_t RGD15; + stc_mpu_rgd15_field_t RGD15_f; + }; + union + { + __IO uint32_t RGCR0; + stc_mpu_rgcr0_field_t RGCR0_f; + }; + union + { + __IO uint32_t RGCR1; + stc_mpu_rgcr1_field_t RGCR1_f; + }; + union + { + __IO uint32_t RGCR2; + stc_mpu_rgcr2_field_t RGCR2_f; + }; + union + { + __IO uint32_t RGCR3; + stc_mpu_rgcr3_field_t RGCR3_f; + }; + union + { + __IO uint32_t RGCR4; + stc_mpu_rgcr4_field_t RGCR4_f; + }; + union + { + __IO uint32_t RGCR5; + stc_mpu_rgcr5_field_t RGCR5_f; + }; + union + { + __IO uint32_t RGCR6; + stc_mpu_rgcr6_field_t RGCR6_f; + }; + union + { + __IO uint32_t RGCR7; + stc_mpu_rgcr7_field_t RGCR7_f; + }; + union + { + __IO uint32_t RGCR8; + stc_mpu_rgcr8_field_t RGCR8_f; + }; + union + { + __IO uint32_t RGCR9; + stc_mpu_rgcr9_field_t RGCR9_f; + }; + union + { + __IO uint32_t RGCR10; + stc_mpu_rgcr10_field_t RGCR10_f; + }; + union + { + __IO uint32_t RGCR11; + stc_mpu_rgcr11_field_t RGCR11_f; + }; + union + { + __IO uint32_t RGCR12; + stc_mpu_rgcr12_field_t RGCR12_f; + }; + union + { + __IO uint32_t RGCR13; + stc_mpu_rgcr13_field_t RGCR13_f; + }; + union + { + __IO uint32_t RGCR14; + stc_mpu_rgcr14_field_t RGCR14_f; + }; + union + { + __IO uint32_t RGCR15; + stc_mpu_rgcr15_field_t RGCR15_f; + }; + union + { + __IO uint32_t CR; + stc_mpu_cr_field_t CR_f; + }; + union + { + __IO uint32_t SR; + stc_mpu_sr_field_t SR_f; + }; + union + { + __IO uint32_t ECLR; + stc_mpu_eclr_field_t ECLR_f; + }; + union + { + __IO uint32_t WP; + stc_mpu_wp_field_t WP_f; + }; +}M4_MPU_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t FCG0; + stc_mstp_fcg0_field_t FCG0_f; + }; + union + { + __IO uint32_t FCG1; + stc_mstp_fcg1_field_t FCG1_f; + }; + union + { + __IO uint32_t FCG2; + stc_mstp_fcg2_field_t FCG2_f; + }; + union + { + __IO uint32_t FCG3; + stc_mstp_fcg3_field_t FCG3_f; + }; + union + { + __IO uint32_t FCG0PC; + stc_mstp_fcg0pc_field_t FCG0PC_f; + }; +}M4_MSTP_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t CTL; + stc_ots_ctl_field_t CTL_f; + }; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t ECR; + union + { + __IO uint32_t LPR; + stc_ots_lpr_field_t LPR_f; + }; +}M4_OTS_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t USBFS_SYCTLREG; + stc_peric_usbfs_syctlreg_field_t USBFS_SYCTLREG_f; + }; + union + { + __IO uint32_t SDIOC_SYCTLREG; + stc_peric_sdioc_syctlreg_field_t SDIOC_SYCTLREG_f; + }; +}M4_PERIC_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t PIDRA; + stc_port_pidr_field_t PIDRA_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t PODRA; + stc_port_podr_field_t PODRA_f; + }; + union + { + __IO uint16_t POERA; + stc_port_poer_field_t POERA_f; + }; + union + { + __IO uint16_t POSRA; + stc_port_posr_field_t POSRA_f; + }; + union + { + __IO uint16_t PORRA; + stc_port_porr_field_t PORRA_f; + }; + union + { + __IO uint16_t POTRA; + stc_port_potr_field_t POTRA_f; + }; + uint8_t RESERVED6[2]; + union + { + __IO uint16_t PIDRB; + stc_port_pidr_field_t PIDRB_f; + }; + uint8_t RESERVED7[2]; + union + { + __IO uint16_t PODRB; + stc_port_podr_field_t PODRB_f; + }; + union + { + __IO uint16_t POERB; + stc_port_poer_field_t POERB_f; + }; + union + { + __IO uint16_t POSRB; + stc_port_posr_field_t POSRB_f; + }; + union + { + __IO uint16_t PORRB; + stc_port_porr_field_t PORRB_f; + }; + union + { + __IO uint16_t POTRB; + stc_port_potr_field_t POTRB_f; + }; + uint8_t RESERVED12[2]; + union + { + __IO uint16_t PIDRC; + stc_port_pidr_field_t PIDRC_f; + }; + uint8_t RESERVED13[2]; + union + { + __IO uint16_t PODRC; + stc_port_podr_field_t PODRC_f; + }; + union + { + __IO uint16_t POERC; + stc_port_poer_field_t POERC_f; + }; + union + { + __IO uint16_t POSRC; + stc_port_posr_field_t POSRC_f; + }; + union + { + __IO uint16_t PORRC; + stc_port_porr_field_t PORRC_f; + }; + union + { + __IO uint16_t POTRC; + stc_port_potr_field_t POTRC_f; + }; + uint8_t RESERVED18[2]; + union + { + __IO uint16_t PIDRD; + stc_port_pidr_field_t PIDRD_f; + }; + uint8_t RESERVED19[2]; + union + { + __IO uint16_t PODRD; + stc_port_podr_field_t PODRD_f; + }; + union + { + __IO uint16_t POERD; + stc_port_poer_field_t POERD_f; + }; + union + { + __IO uint16_t POSRD; + stc_port_posr_field_t POSRD_f; + }; + union + { + __IO uint16_t PORRD; + stc_port_porr_field_t PORRD_f; + }; + union + { + __IO uint16_t POTRD; + stc_port_potr_field_t POTRD_f; + }; + uint8_t RESERVED24[2]; + union + { + __IO uint16_t PIDRE; + stc_port_pidr_field_t PIDRE_f; + }; + uint8_t RESERVED25[2]; + union + { + __IO uint16_t PODRE; + stc_port_podr_field_t PODRE_f; + }; + union + { + __IO uint16_t POERE; + stc_port_poer_field_t POERE_f; + }; + union + { + __IO uint16_t POSRE; + stc_port_posr_field_t POSRE_f; + }; + union + { + __IO uint16_t PORRE; + stc_port_porr_field_t PORRE_f; + }; + union + { + __IO uint16_t POTRE; + stc_port_potr_field_t POTRE_f; + }; + uint8_t RESERVED30[2]; + union + { + __IO uint16_t PIDRH; + stc_port_pidrh_field_t PIDRH_f; + }; + uint8_t RESERVED31[2]; + union + { + __IO uint16_t PODRH; + stc_port_podrh_field_t PODRH_f; + }; + union + { + __IO uint16_t POERH; + stc_port_poerh_field_t POERH_f; + }; + union + { + __IO uint16_t POSRH; + stc_port_posrh_field_t POSRH_f; + }; + union + { + __IO uint16_t PORRH; + stc_port_porrh_field_t PORRH_f; + }; + union + { + __IO uint16_t POTRH; + stc_port_potrh_field_t POTRH_f; + }; + uint8_t RESERVED36[918]; + union + { + __IO uint16_t PSPCR; + stc_port_pspcr_field_t PSPCR_f; + }; + uint8_t RESERVED37[2]; + union + { + __IO uint16_t PCCR; + stc_port_pccr_field_t PCCR_f; + }; + union + { + __IO uint16_t PINAER; + stc_port_pinaer_field_t PINAER_f; + }; + union + { + __IO uint16_t PWPR; + stc_port_pwpr_field_t PWPR_f; + }; + uint8_t RESERVED40[2]; + union + { + __IO uint16_t PCRA0; + stc_port_pcr_field_t PCRA0_f; + }; + union + { + __IO uint16_t PFSRA0; + stc_port_pfsr_field_t PFSRA0_f; + }; + union + { + __IO uint16_t PCRA1; + stc_port_pcr_field_t PCRA1_f; + }; + union + { + __IO uint16_t PFSRA1; + stc_port_pfsr_field_t PFSRA1_f; + }; + union + { + __IO uint16_t PCRA2; + stc_port_pcr_field_t PCRA2_f; + }; + union + { + __IO uint16_t PFSRA2; + stc_port_pfsr_field_t PFSRA2_f; + }; + union + { + __IO uint16_t PCRA3; + stc_port_pcr_field_t PCRA3_f; + }; + union + { + __IO uint16_t PFSRA3; + stc_port_pfsr_field_t PFSRA3_f; + }; + union + { + __IO uint16_t PCRA4; + stc_port_pcr_field_t PCRA4_f; + }; + union + { + __IO uint16_t PFSRA4; + stc_port_pfsr_field_t PFSRA4_f; + }; + union + { + __IO uint16_t PCRA5; + stc_port_pcr_field_t PCRA5_f; + }; + union + { + __IO uint16_t PFSRA5; + stc_port_pfsr_field_t PFSRA5_f; + }; + union + { + __IO uint16_t PCRA6; + stc_port_pcr_field_t PCRA6_f; + }; + union + { + __IO uint16_t PFSRA6; + stc_port_pfsr_field_t PFSRA6_f; + }; + union + { + __IO uint16_t PCRA7; + stc_port_pcr_field_t PCRA7_f; + }; + union + { + __IO uint16_t PFSRA7; + stc_port_pfsr_field_t PFSRA7_f; + }; + union + { + __IO uint16_t PCRA8; + stc_port_pcr_field_t PCRA8_f; + }; + union + { + __IO uint16_t PFSRA8; + stc_port_pfsr_field_t PFSRA8_f; + }; + union + { + __IO uint16_t PCRA9; + stc_port_pcr_field_t PCRA9_f; + }; + union + { + __IO uint16_t PFSRA9; + stc_port_pfsr_field_t PFSRA9_f; + }; + union + { + __IO uint16_t PCRA10; + stc_port_pcr_field_t PCRA10_f; + }; + union + { + __IO uint16_t PFSRA10; + stc_port_pfsr_field_t PFSRA10_f; + }; + union + { + __IO uint16_t PCRA11; + stc_port_pcr_field_t PCRA11_f; + }; + union + { + __IO uint16_t PFSRA11; + stc_port_pfsr_field_t PFSRA11_f; + }; + union + { + __IO uint16_t PCRA12; + stc_port_pcr_field_t PCRA12_f; + }; + union + { + __IO uint16_t PFSRA12; + stc_port_pfsr_field_t PFSRA12_f; + }; + union + { + __IO uint16_t PCRA13; + stc_port_pcr_field_t PCRA13_f; + }; + union + { + __IO uint16_t PFSRA13; + stc_port_pfsr_field_t PFSRA13_f; + }; + union + { + __IO uint16_t PCRA14; + stc_port_pcr_field_t PCRA14_f; + }; + union + { + __IO uint16_t PFSRA14; + stc_port_pfsr_field_t PFSRA14_f; + }; + union + { + __IO uint16_t PCRA15; + stc_port_pcr_field_t PCRA15_f; + }; + union + { + __IO uint16_t PFSRA15; + stc_port_pfsr_field_t PFSRA15_f; + }; + union + { + __IO uint16_t PCRB0; + stc_port_pcr_field_t PCRB0_f; + }; + union + { + __IO uint16_t PFSRB0; + stc_port_pfsr_field_t PFSRB0_f; + }; + union + { + __IO uint16_t PCRB1; + stc_port_pcr_field_t PCRB1_f; + }; + union + { + __IO uint16_t PFSRB1; + stc_port_pfsr_field_t PFSRB1_f; + }; + union + { + __IO uint16_t PCRB2; + stc_port_pcr_field_t PCRB2_f; + }; + union + { + __IO uint16_t PFSRB2; + stc_port_pfsr_field_t PFSRB2_f; + }; + union + { + __IO uint16_t PCRB3; + stc_port_pcr_field_t PCRB3_f; + }; + union + { + __IO uint16_t PFSRB3; + stc_port_pfsr_field_t PFSRB3_f; + }; + union + { + __IO uint16_t PCRB4; + stc_port_pcr_field_t PCRB4_f; + }; + union + { + __IO uint16_t PFSRB4; + stc_port_pfsr_field_t PFSRB4_f; + }; + union + { + __IO uint16_t PCRB5; + stc_port_pcr_field_t PCRB5_f; + }; + union + { + __IO uint16_t PFSRB5; + stc_port_pfsr_field_t PFSRB5_f; + }; + union + { + __IO uint16_t PCRB6; + stc_port_pcr_field_t PCRB6_f; + }; + union + { + __IO uint16_t PFSRB6; + stc_port_pfsr_field_t PFSRB6_f; + }; + union + { + __IO uint16_t PCRB7; + stc_port_pcr_field_t PCRB7_f; + }; + union + { + __IO uint16_t PFSRB7; + stc_port_pfsr_field_t PFSRB7_f; + }; + union + { + __IO uint16_t PCRB8; + stc_port_pcr_field_t PCRB8_f; + }; + union + { + __IO uint16_t PFSRB8; + stc_port_pfsr_field_t PFSRB8_f; + }; + union + { + __IO uint16_t PCRB9; + stc_port_pcr_field_t PCRB9_f; + }; + union + { + __IO uint16_t PFSRB9; + stc_port_pfsr_field_t PFSRB9_f; + }; + union + { + __IO uint16_t PCRB10; + stc_port_pcr_field_t PCRB10_f; + }; + union + { + __IO uint16_t PFSRB10; + stc_port_pfsr_field_t PFSRB10_f; + }; + union + { + __IO uint16_t PCRB11; + stc_port_pcr_field_t PCRB11_f; + }; + union + { + __IO uint16_t PFSRB11; + stc_port_pfsr_field_t PFSRB11_f; + }; + union + { + __IO uint16_t PCRB12; + stc_port_pcr_field_t PCRB12_f; + }; + union + { + __IO uint16_t PFSRB12; + stc_port_pfsr_field_t PFSRB12_f; + }; + union + { + __IO uint16_t PCRB13; + stc_port_pcr_field_t PCRB13_f; + }; + union + { + __IO uint16_t PFSRB13; + stc_port_pfsr_field_t PFSRB13_f; + }; + union + { + __IO uint16_t PCRB14; + stc_port_pcr_field_t PCRB14_f; + }; + union + { + __IO uint16_t PFSRB14; + stc_port_pfsr_field_t PFSRB14_f; + }; + union + { + __IO uint16_t PCRB15; + stc_port_pcr_field_t PCRB15_f; + }; + union + { + __IO uint16_t PFSRB15; + stc_port_pfsr_field_t PFSRB15_f; + }; + union + { + __IO uint16_t PCRC0; + stc_port_pcr_field_t PCRC0_f; + }; + union + { + __IO uint16_t PFSRC0; + stc_port_pfsr_field_t PFSRC0_f; + }; + union + { + __IO uint16_t PCRC1; + stc_port_pcr_field_t PCRC1_f; + }; + union + { + __IO uint16_t PFSRC1; + stc_port_pfsr_field_t PFSRC1_f; + }; + union + { + __IO uint16_t PCRC2; + stc_port_pcr_field_t PCRC2_f; + }; + union + { + __IO uint16_t PFSRC2; + stc_port_pfsr_field_t PFSRC2_f; + }; + union + { + __IO uint16_t PCRC3; + stc_port_pcr_field_t PCRC3_f; + }; + union + { + __IO uint16_t PFSRC3; + stc_port_pfsr_field_t PFSRC3_f; + }; + union + { + __IO uint16_t PCRC4; + stc_port_pcr_field_t PCRC4_f; + }; + union + { + __IO uint16_t PFSRC4; + stc_port_pfsr_field_t PFSRC4_f; + }; + union + { + __IO uint16_t PCRC5; + stc_port_pcr_field_t PCRC5_f; + }; + union + { + __IO uint16_t PFSRC5; + stc_port_pfsr_field_t PFSRC5_f; + }; + union + { + __IO uint16_t PCRC6; + stc_port_pcr_field_t PCRC6_f; + }; + union + { + __IO uint16_t PFSRC6; + stc_port_pfsr_field_t PFSRC6_f; + }; + union + { + __IO uint16_t PCRC7; + stc_port_pcr_field_t PCRC7_f; + }; + union + { + __IO uint16_t PFSRC7; + stc_port_pfsr_field_t PFSRC7_f; + }; + union + { + __IO uint16_t PCRC8; + stc_port_pcr_field_t PCRC8_f; + }; + union + { + __IO uint16_t PFSRC8; + stc_port_pfsr_field_t PFSRC8_f; + }; + union + { + __IO uint16_t PCRC9; + stc_port_pcr_field_t PCRC9_f; + }; + union + { + __IO uint16_t PFSRC9; + stc_port_pfsr_field_t PFSRC9_f; + }; + union + { + __IO uint16_t PCRC10; + stc_port_pcr_field_t PCRC10_f; + }; + union + { + __IO uint16_t PFSRC10; + stc_port_pfsr_field_t PFSRC10_f; + }; + union + { + __IO uint16_t PCRC11; + stc_port_pcr_field_t PCRC11_f; + }; + union + { + __IO uint16_t PFSRC11; + stc_port_pfsr_field_t PFSRC11_f; + }; + union + { + __IO uint16_t PCRC12; + stc_port_pcr_field_t PCRC12_f; + }; + union + { + __IO uint16_t PFSRC12; + stc_port_pfsr_field_t PFSRC12_f; + }; + union + { + __IO uint16_t PCRC13; + stc_port_pcr_field_t PCRC13_f; + }; + union + { + __IO uint16_t PFSRC13; + stc_port_pfsr_field_t PFSRC13_f; + }; + union + { + __IO uint16_t PCRC14; + stc_port_pcr_field_t PCRC14_f; + }; + union + { + __IO uint16_t PFSRC14; + stc_port_pfsr_field_t PFSRC14_f; + }; + union + { + __IO uint16_t PCRC15; + stc_port_pcr_field_t PCRC15_f; + }; + union + { + __IO uint16_t PFSRC15; + stc_port_pfsr_field_t PFSRC15_f; + }; + union + { + __IO uint16_t PCRD0; + stc_port_pcr_field_t PCRD0_f; + }; + union + { + __IO uint16_t PFSRD0; + stc_port_pfsr_field_t PFSRD0_f; + }; + union + { + __IO uint16_t PCRD1; + stc_port_pcr_field_t PCRD1_f; + }; + union + { + __IO uint16_t PFSRD1; + stc_port_pfsr_field_t PFSRD1_f; + }; + union + { + __IO uint16_t PCRD2; + stc_port_pcr_field_t PCRD2_f; + }; + union + { + __IO uint16_t PFSRD2; + stc_port_pfsr_field_t PFSRD2_f; + }; + union + { + __IO uint16_t PCRD3; + stc_port_pcr_field_t PCRD3_f; + }; + union + { + __IO uint16_t PFSRD3; + stc_port_pfsr_field_t PFSRD3_f; + }; + union + { + __IO uint16_t PCRD4; + stc_port_pcr_field_t PCRD4_f; + }; + union + { + __IO uint16_t PFSRD4; + stc_port_pfsr_field_t PFSRD4_f; + }; + union + { + __IO uint16_t PCRD5; + stc_port_pcr_field_t PCRD5_f; + }; + union + { + __IO uint16_t PFSRD5; + stc_port_pfsr_field_t PFSRD5_f; + }; + union + { + __IO uint16_t PCRD6; + stc_port_pcr_field_t PCRD6_f; + }; + union + { + __IO uint16_t PFSRD6; + stc_port_pfsr_field_t PFSRD6_f; + }; + union + { + __IO uint16_t PCRD7; + stc_port_pcr_field_t PCRD7_f; + }; + union + { + __IO uint16_t PFSRD7; + stc_port_pfsr_field_t PFSRD7_f; + }; + union + { + __IO uint16_t PCRD8; + stc_port_pcr_field_t PCRD8_f; + }; + union + { + __IO uint16_t PFSRD8; + stc_port_pfsr_field_t PFSRD8_f; + }; + union + { + __IO uint16_t PCRD9; + stc_port_pcr_field_t PCRD9_f; + }; + union + { + __IO uint16_t PFSRD9; + stc_port_pfsr_field_t PFSRD9_f; + }; + union + { + __IO uint16_t PCRD10; + stc_port_pcr_field_t PCRD10_f; + }; + union + { + __IO uint16_t PFSRD10; + stc_port_pfsr_field_t PFSRD10_f; + }; + union + { + __IO uint16_t PCRD11; + stc_port_pcr_field_t PCRD11_f; + }; + union + { + __IO uint16_t PFSRD11; + stc_port_pfsr_field_t PFSRD11_f; + }; + union + { + __IO uint16_t PCRD12; + stc_port_pcr_field_t PCRD12_f; + }; + union + { + __IO uint16_t PFSRD12; + stc_port_pfsr_field_t PFSRD12_f; + }; + union + { + __IO uint16_t PCRD13; + stc_port_pcr_field_t PCRD13_f; + }; + union + { + __IO uint16_t PFSRD13; + stc_port_pfsr_field_t PFSRD13_f; + }; + union + { + __IO uint16_t PCRD14; + stc_port_pcr_field_t PCRD14_f; + }; + union + { + __IO uint16_t PFSRD14; + stc_port_pfsr_field_t PFSRD14_f; + }; + union + { + __IO uint16_t PCRD15; + stc_port_pcr_field_t PCRD15_f; + }; + union + { + __IO uint16_t PFSRD15; + stc_port_pfsr_field_t PFSRD15_f; + }; + union + { + __IO uint16_t PCRE0; + stc_port_pcr_field_t PCRE0_f; + }; + union + { + __IO uint16_t PFSRE0; + stc_port_pfsr_field_t PFSRE0_f; + }; + union + { + __IO uint16_t PCRE1; + stc_port_pcr_field_t PCRE1_f; + }; + union + { + __IO uint16_t PFSRE1; + stc_port_pfsr_field_t PFSRE1_f; + }; + union + { + __IO uint16_t PCRE2; + stc_port_pcr_field_t PCRE2_f; + }; + union + { + __IO uint16_t PFSRE2; + stc_port_pfsr_field_t PFSRE2_f; + }; + union + { + __IO uint16_t PCRE3; + stc_port_pcr_field_t PCRE3_f; + }; + union + { + __IO uint16_t PFSRE3; + stc_port_pfsr_field_t PFSRE3_f; + }; + union + { + __IO uint16_t PCRE4; + stc_port_pcr_field_t PCRE4_f; + }; + union + { + __IO uint16_t PFSRE4; + stc_port_pfsr_field_t PFSRE4_f; + }; + union + { + __IO uint16_t PCRE5; + stc_port_pcr_field_t PCRE5_f; + }; + union + { + __IO uint16_t PFSRE5; + stc_port_pfsr_field_t PFSRE5_f; + }; + union + { + __IO uint16_t PCRE6; + stc_port_pcr_field_t PCRE6_f; + }; + union + { + __IO uint16_t PFSRE6; + stc_port_pfsr_field_t PFSRE6_f; + }; + union + { + __IO uint16_t PCRE7; + stc_port_pcr_field_t PCRE7_f; + }; + union + { + __IO uint16_t PFSRE7; + stc_port_pfsr_field_t PFSRE7_f; + }; + union + { + __IO uint16_t PCRE8; + stc_port_pcr_field_t PCRE8_f; + }; + union + { + __IO uint16_t PFSRE8; + stc_port_pfsr_field_t PFSRE8_f; + }; + union + { + __IO uint16_t PCRE9; + stc_port_pcr_field_t PCRE9_f; + }; + union + { + __IO uint16_t PFSRE9; + stc_port_pfsr_field_t PFSRE9_f; + }; + union + { + __IO uint16_t PCRE10; + stc_port_pcr_field_t PCRE10_f; + }; + union + { + __IO uint16_t PFSRE10; + stc_port_pfsr_field_t PFSRE10_f; + }; + union + { + __IO uint16_t PCRE11; + stc_port_pcr_field_t PCRE11_f; + }; + union + { + __IO uint16_t PFSRE11; + stc_port_pfsr_field_t PFSRE11_f; + }; + union + { + __IO uint16_t PCRE12; + stc_port_pcr_field_t PCRE12_f; + }; + union + { + __IO uint16_t PFSRE12; + stc_port_pfsr_field_t PFSRE12_f; + }; + union + { + __IO uint16_t PCRE13; + stc_port_pcr_field_t PCRE13_f; + }; + union + { + __IO uint16_t PFSRE13; + stc_port_pfsr_field_t PFSRE13_f; + }; + union + { + __IO uint16_t PCRE14; + stc_port_pcr_field_t PCRE14_f; + }; + union + { + __IO uint16_t PFSRE14; + stc_port_pfsr_field_t PFSRE14_f; + }; + union + { + __IO uint16_t PCRE15; + stc_port_pcr_field_t PCRE15_f; + }; + union + { + __IO uint16_t PFSRE15; + stc_port_pfsr_field_t PFSRE15_f; + }; + union + { + __IO uint16_t PCRH0; + stc_port_pcr_field_t PCRH0_f; + }; + union + { + __IO uint16_t PFSRH0; + stc_port_pfsr_field_t PFSRH0_f; + }; + union + { + __IO uint16_t PCRH1; + stc_port_pcr_field_t PCRH1_f; + }; + union + { + __IO uint16_t PFSRH1; + stc_port_pfsr_field_t PFSRH1_f; + }; + union + { + __IO uint16_t PCRH2; + stc_port_pcr_field_t PCRH2_f; + }; + union + { + __IO uint16_t PFSRH2; + stc_port_pfsr_field_t PFSRH2_f; + }; +}M4_PORT_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_qspi_cr_field_t CR_f; + }; + union + { + __IO uint32_t CSCR; + stc_qspi_cscr_field_t CSCR_f; + }; + union + { + __IO uint32_t FCR; + stc_qspi_fcr_field_t FCR_f; + }; + union + { + __IO uint32_t SR; + stc_qspi_sr_field_t SR_f; + }; + union + { + __IO uint32_t DCOM; + stc_qspi_dcom_field_t DCOM_f; + }; + union + { + __IO uint32_t CCMD; + stc_qspi_ccmd_field_t CCMD_f; + }; + union + { + __IO uint32_t XCMD; + stc_qspi_xcmd_field_t XCMD_f; + }; + uint8_t RESERVED7[8]; + union + { + __IO uint32_t SR2; + stc_qspi_sr2_field_t SR2_f; + }; + uint8_t RESERVED8[2012]; + union + { + __IO uint32_t EXAR; + stc_qspi_exar_field_t EXAR_f; + }; +}M4_QSPI_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_rtc_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_rtc_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_rtc_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t CR3; + stc_rtc_cr3_field_t CR3_f; + }; + union + { + __IO uint32_t SEC; + stc_rtc_sec_field_t SEC_f; + }; + union + { + __IO uint32_t MIN; + stc_rtc_min_field_t MIN_f; + }; + union + { + __IO uint32_t HOUR; + stc_rtc_hour_field_t HOUR_f; + }; + union + { + __IO uint32_t WEEK; + stc_rtc_week_field_t WEEK_f; + }; + union + { + __IO uint32_t DAY; + stc_rtc_day_field_t DAY_f; + }; + union + { + __IO uint32_t MON; + stc_rtc_mon_field_t MON_f; + }; + union + { + __IO uint32_t YEAR; + stc_rtc_year_field_t YEAR_f; + }; + union + { + __IO uint32_t ALMMIN; + stc_rtc_almmin_field_t ALMMIN_f; + }; + union + { + __IO uint32_t ALMHOUR; + stc_rtc_almhour_field_t ALMHOUR_f; + }; + union + { + __IO uint32_t ALMWEEK; + stc_rtc_almweek_field_t ALMWEEK_f; + }; + union + { + __IO uint32_t ERRCRH; + stc_rtc_errcrh_field_t ERRCRH_f; + }; + union + { + __IO uint32_t ERRCRL; + stc_rtc_errcrl_field_t ERRCRL_f; + }; +}M4_RTC_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint16_t BLKSIZE; + stc_sdioc_blksize_field_t BLKSIZE_f; + }; + __IO uint16_t BLKCNT; + __IO uint16_t ARG0; + __IO uint16_t ARG1; + union + { + __IO uint16_t TRANSMODE; + stc_sdioc_transmode_field_t TRANSMODE_f; + }; + union + { + __IO uint16_t CMD; + stc_sdioc_cmd_field_t CMD_f; + }; + __IO uint16_t RESP0; + __IO uint16_t RESP1; + __IO uint16_t RESP2; + __IO uint16_t RESP3; + __IO uint16_t RESP4; + __IO uint16_t RESP5; + __IO uint16_t RESP6; + __IO uint16_t RESP7; + __IO uint16_t BUF0; + __IO uint16_t BUF1; + union + { + __IO uint32_t PSTAT; + stc_sdioc_pstat_field_t PSTAT_f; + }; + union + { + __IO uint8_t HOSTCON; + stc_sdioc_hostcon_field_t HOSTCON_f; + }; + union + { + __IO uint8_t PWRCON; + stc_sdioc_pwrcon_field_t PWRCON_f; + }; + union + { + __IO uint8_t BLKGPCON; + stc_sdioc_blkgpcon_field_t BLKGPCON_f; + }; + uint8_t RESERVED20[1]; + union + { + __IO uint16_t CLKCON; + stc_sdioc_clkcon_field_t CLKCON_f; + }; + union + { + __IO uint8_t TOUTCON; + stc_sdioc_toutcon_field_t TOUTCON_f; + }; + union + { + __IO uint8_t SFTRST; + stc_sdioc_sftrst_field_t SFTRST_f; + }; + union + { + __IO uint16_t NORINTST; + stc_sdioc_norintst_field_t NORINTST_f; + }; + union + { + __IO uint16_t ERRINTST; + stc_sdioc_errintst_field_t ERRINTST_f; + }; + union + { + __IO uint16_t NORINTSTEN; + stc_sdioc_norintsten_field_t NORINTSTEN_f; + }; + union + { + __IO uint16_t ERRINTSTEN; + stc_sdioc_errintsten_field_t ERRINTSTEN_f; + }; + union + { + __IO uint16_t NORINTSGEN; + stc_sdioc_norintsgen_field_t NORINTSGEN_f; + }; + union + { + __IO uint16_t ERRINTSGEN; + stc_sdioc_errintsgen_field_t ERRINTSGEN_f; + }; + union + { + __IO uint16_t ATCERRST; + stc_sdioc_atcerrst_field_t ATCERRST_f; + }; + uint8_t RESERVED30[18]; + union + { + __IO uint16_t FEA; + stc_sdioc_fea_field_t FEA_f; + }; + union + { + __IO uint16_t FEE; + stc_sdioc_fee_field_t FEE_f; + }; +}M4_SDIOC_TypeDef; + +typedef struct +{ + __IO uint32_t DR; + union + { + __IO uint32_t CR1; + stc_spi_cr1_field_t CR1_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t CFG1; + stc_spi_cfg1_field_t CFG1_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t SR; + stc_spi_sr_field_t SR_f; + }; + union + { + __IO uint32_t CFG2; + stc_spi_cfg2_field_t CFG2_f; + }; +}M4_SPI_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t WTCR; + stc_sramc_wtcr_field_t WTCR_f; + }; + union + { + __IO uint32_t WTPR; + stc_sramc_wtpr_field_t WTPR_f; + }; + union + { + __IO uint32_t CKCR; + stc_sramc_ckcr_field_t CKCR_f; + }; + union + { + __IO uint32_t CKPR; + stc_sramc_ckpr_field_t CKPR_f; + }; + union + { + __IO uint32_t CKSR; + stc_sramc_cksr_field_t CKSR_f; + }; +}M4_SRAMC_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t SR; + stc_swdt_sr_field_t SR_f; + }; + union + { + __IO uint32_t RR; + stc_swdt_rr_field_t RR_f; + }; +}M4_SWDT_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[12]; + union + { + __IO uint16_t PWR_STPMCR; + stc_sysreg_pwr_stpmcr_field_t PWR_STPMCR_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t CMU_PERICKSEL; + stc_sysreg_cmu_pericksel_field_t CMU_PERICKSEL_f; + }; + union + { + __IO uint16_t CMU_I2SCKSEL; + stc_sysreg_cmu_i2scksel_field_t CMU_I2SCKSEL_f; + }; + union + { + __IO uint32_t PWR_RAMPC0; + stc_sysreg_pwr_rampc0_field_t PWR_RAMPC0_f; + }; + __IO uint16_t PWR_RAMOPM; + uint8_t RESERVED5[2]; + union + { + __IO uint32_t MPU_IPPR; + stc_sysreg_mpu_ippr_field_t MPU_IPPR_f; + }; + union + { + __IO uint32_t CMU_SCFGR; + stc_sysreg_cmu_scfgr_field_t CMU_SCFGR_f; + }; + union + { + __IO uint8_t CMU_UFSCKCFGR; + stc_sysreg_cmu_ufsckcfgr_field_t CMU_UFSCKCFGR_f; + }; + uint8_t RESERVED8[1]; + union + { + __IO uint8_t CMU_CKSWR; + stc_sysreg_cmu_ckswr_field_t CMU_CKSWR_f; + }; + uint8_t RESERVED9[3]; + union + { + __IO uint8_t CMU_PLLCR; + stc_sysreg_cmu_pllcr_field_t CMU_PLLCR_f; + }; + uint8_t RESERVED10[3]; + union + { + __IO uint8_t CMU_UPLLCR; + stc_sysreg_cmu_upllcr_field_t CMU_UPLLCR_f; + }; + uint8_t RESERVED11[3]; + union + { + __IO uint8_t CMU_XTALCR; + stc_sysreg_cmu_xtalcr_field_t CMU_XTALCR_f; + }; + uint8_t RESERVED12[3]; + union + { + __IO uint8_t CMU_HRCCR; + stc_sysreg_cmu_hrccr_field_t CMU_HRCCR_f; + }; + uint8_t RESERVED13[1]; + union + { + __IO uint8_t CMU_MRCCR; + stc_sysreg_cmu_mrccr_field_t CMU_MRCCR_f; + }; + uint8_t RESERVED14[3]; + union + { + __IO uint8_t CMU_OSCSTBSR; + stc_sysreg_cmu_oscstbsr_field_t CMU_OSCSTBSR_f; + }; + union + { + __IO uint8_t CMU_MCO1CFGR; + stc_sysreg_cmu_mco1cfgr_field_t CMU_MCO1CFGR_f; + }; + union + { + __IO uint8_t CMU_MCO2CFGR; + stc_sysreg_cmu_mco2cfgr_field_t CMU_MCO2CFGR_f; + }; + union + { + __IO uint8_t CMU_TPIUCKCFGR; + stc_sysreg_cmu_tpiuckcfgr_field_t CMU_TPIUCKCFGR_f; + }; + union + { + __IO uint8_t CMU_XTALSTDCR; + stc_sysreg_cmu_xtalstdcr_field_t CMU_XTALSTDCR_f; + }; + union + { + __IO uint8_t CMU_XTALSTDSR; + stc_sysreg_cmu_xtalstdsr_field_t CMU_XTALSTDSR_f; + }; + uint8_t RESERVED20[31]; + __IO uint8_t CMU_MRCTRM; + __IO uint8_t CMU_HRCTRM; + uint8_t RESERVED22[63]; + union + { + __IO uint8_t CMU_XTALSTBCR; + stc_sysreg_cmu_xtalstbcr_field_t CMU_XTALSTBCR_f; + }; + uint8_t RESERVED23[29]; + union + { + __IO uint16_t RMU_RSTF0; + stc_sysreg_rmu_rstf0_field_t RMU_RSTF0_f; + }; + uint8_t RESERVED24[30]; + union + { + __IO uint8_t PWR_PVDICR; + stc_sysreg_pwr_pvdicr_field_t PWR_PVDICR_f; + }; + union + { + __IO uint8_t PWR_PVDDSR; + stc_sysreg_pwr_pvddsr_field_t PWR_PVDDSR_f; + }; + uint8_t RESERVED26[30]; + union + { + __IO uint32_t CMU_PLLCFGR; + stc_sysreg_cmu_pllcfgr_field_t CMU_PLLCFGR_f; + }; + union + { + __IO uint32_t CMU_UPLLCFGR; + stc_sysreg_cmu_upllcfgr_field_t CMU_UPLLCFGR_f; + }; + uint8_t RESERVED28[758]; + union + { + __IO uint16_t PWR_FPRC; + stc_sysreg_pwr_fprc_field_t PWR_FPRC_f; + }; + union + { + __IO uint8_t PWR_PWRC0; + stc_sysreg_pwr_pwrc0_field_t PWR_PWRC0_f; + }; + union + { + __IO uint8_t PWR_PWRC1; + stc_sysreg_pwr_pwrc1_field_t PWR_PWRC1_f; + }; + union + { + __IO uint8_t PWR_PWRC2; + stc_sysreg_pwr_pwrc2_field_t PWR_PWRC2_f; + }; + union + { + __IO uint8_t PWR_PWRC3; + stc_sysreg_pwr_pwrc3_field_t PWR_PWRC3_f; + }; + union + { + __IO uint8_t PWR_PDWKE0; + stc_sysreg_pwr_pdwke0_field_t PWR_PDWKE0_f; + }; + union + { + __IO uint8_t PWR_PDWKE1; + stc_sysreg_pwr_pdwke1_field_t PWR_PDWKE1_f; + }; + union + { + __IO uint8_t PWR_PDWKE2; + stc_sysreg_pwr_pdwke2_field_t PWR_PDWKE2_f; + }; + union + { + __IO uint8_t PWR_PDWKES; + stc_sysreg_pwr_pdwkes_field_t PWR_PDWKES_f; + }; + union + { + __IO uint8_t PWR_PDWKF0; + stc_sysreg_pwr_pdwkf0_field_t PWR_PDWKF0_f; + }; + union + { + __IO uint8_t PWR_PDWKF1; + stc_sysreg_pwr_pdwkf1_field_t PWR_PDWKF1_f; + }; + union + { + __IO uint8_t PWR_PWCMR; + stc_sysreg_pwr_pwcmr_field_t PWR_PWCMR_f; + }; + uint8_t RESERVED40[4]; + __IO uint8_t PWR_MDSWCR; + union + { + __IO uint8_t CMU_XTALCFGR; + stc_sysreg_cmu_xtalcfgr_field_t CMU_XTALCFGR_f; + }; + uint8_t RESERVED42[1]; + union + { + __IO uint8_t PWR_PVDCR0; + stc_sysreg_pwr_pvdcr0_field_t PWR_PVDCR0_f; + }; + union + { + __IO uint8_t PWR_PVDCR1; + stc_sysreg_pwr_pvdcr1_field_t PWR_PVDCR1_f; + }; + union + { + __IO uint8_t PWR_PVDFCR; + stc_sysreg_pwr_pvdfcr_field_t PWR_PVDFCR_f; + }; + union + { + __IO uint8_t PWR_PVDLCR; + stc_sysreg_pwr_pvdlcr_field_t PWR_PVDLCR_f; + }; + uint8_t RESERVED46[10]; + union + { + __IO uint8_t CMU_XTAL32CR; + stc_sysreg_cmu_xtal32cr_field_t CMU_XTAL32CR_f; + }; + union + { + __IO uint8_t CMU_XTAL32CFGR; + stc_sysreg_cmu_xtal32cfgr_field_t CMU_XTAL32CFGR_f; + }; + uint8_t RESERVED48[3]; + union + { + __IO uint8_t CMU_XTAL32NFR; + stc_sysreg_cmu_xtal32nfr_field_t CMU_XTAL32NFR_f; + }; + uint8_t RESERVED49[1]; + union + { + __IO uint8_t CMU_LRCCR; + stc_sysreg_cmu_lrccr_field_t CMU_LRCCR_f; + }; + uint8_t RESERVED50[1]; + __IO uint8_t CMU_LRCTRM; + uint8_t RESERVED51[1]; + union + { + __IO uint8_t PWR_XTAL32CS; + stc_sysreg_pwr_xtal32cs_field_t PWR_XTAL32CS_f; + }; +}M4_SYSREG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTAR; + stc_tmr0_cntar_field_t CNTAR_f; + }; + union + { + __IO uint32_t CNTBR; + stc_tmr0_cntbr_field_t CNTBR_f; + }; + union + { + __IO uint32_t CMPAR; + stc_tmr0_cmpar_field_t CMPAR_f; + }; + union + { + __IO uint32_t CMPBR; + stc_tmr0_cmpbr_field_t CMPBR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tmr0_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tmr0_stflr_field_t STFLR_f; + }; +}M4_TMR0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[2]; + __IO uint16_t OCCRUH; + uint8_t RESERVED1[2]; + __IO uint16_t OCCRUL; + uint8_t RESERVED2[2]; + __IO uint16_t OCCRVH; + uint8_t RESERVED3[2]; + __IO uint16_t OCCRVL; + uint8_t RESERVED4[2]; + __IO uint16_t OCCRWH; + uint8_t RESERVED5[2]; + __IO uint16_t OCCRWL; + union + { + __IO uint16_t OCSRU; + stc_tmr4_ocsr_field_t OCSRU_f; + }; + union + { + __IO uint16_t OCERU; + stc_tmr4_ocer_field_t OCERU_f; + }; + union + { + __IO uint16_t OCSRV; + stc_tmr4_ocsr_field_t OCSRV_f; + }; + union + { + __IO uint16_t OCERV; + stc_tmr4_ocer_field_t OCERV_f; + }; + union + { + __IO uint16_t OCSRW; + stc_tmr4_ocsr_field_t OCSRW_f; + }; + union + { + __IO uint16_t OCERW; + stc_tmr4_ocer_field_t OCERW_f; + }; + union + { + __IO uint16_t OCMRHUH; + stc_tmr4_ocmrh_field_t OCMRHUH_f; + }; + uint8_t RESERVED13[2]; + union + { + __IO uint32_t OCMRLUL; + stc_tmr4_ocmrl_field_t OCMRLUL_f; + }; + union + { + __IO uint16_t OCMRHVH; + stc_tmr4_ocmrh_field_t OCMRHVH_f; + }; + uint8_t RESERVED15[2]; + union + { + __IO uint32_t OCMRLVL; + stc_tmr4_ocmrl_field_t OCMRLVL_f; + }; + union + { + __IO uint16_t OCMRHWH; + stc_tmr4_ocmrh_field_t OCMRHWH_f; + }; + uint8_t RESERVED17[2]; + union + { + __IO uint32_t OCMRLWL; + stc_tmr4_ocmrl_field_t OCMRLWL_f; + }; + uint8_t RESERVED18[6]; + __IO uint16_t CPSR; + uint8_t RESERVED19[2]; + __IO uint16_t CNTR; + union + { + __IO uint16_t CCSR; + stc_tmr4_ccsr_field_t CCSR_f; + }; + union + { + __IO uint16_t CVPR; + stc_tmr4_cvpr_field_t CVPR_f; + }; + uint8_t RESERVED22[54]; + __IO uint16_t PFSRU; + __IO uint16_t PDARU; + __IO uint16_t PDBRU; + uint8_t RESERVED25[2]; + __IO uint16_t PFSRV; + __IO uint16_t PDARV; + __IO uint16_t PDBRV; + uint8_t RESERVED28[2]; + __IO uint16_t PFSRW; + __IO uint16_t PDARW; + __IO uint16_t PDBRW; + union + { + __IO uint16_t POCRU; + stc_tmr4_pocr_field_t POCRU_f; + }; + uint8_t RESERVED32[2]; + union + { + __IO uint16_t POCRV; + stc_tmr4_pocr_field_t POCRV_f; + }; + uint8_t RESERVED33[2]; + union + { + __IO uint16_t POCRW; + stc_tmr4_pocr_field_t POCRW_f; + }; + uint8_t RESERVED34[2]; + union + { + __IO uint16_t RCSR; + stc_tmr4_rcsr_field_t RCSR_f; + }; + uint8_t RESERVED35[12]; + __IO uint16_t SCCRUH; + uint8_t RESERVED36[2]; + __IO uint16_t SCCRUL; + uint8_t RESERVED37[2]; + __IO uint16_t SCCRVH; + uint8_t RESERVED38[2]; + __IO uint16_t SCCRVL; + uint8_t RESERVED39[2]; + __IO uint16_t SCCRWH; + uint8_t RESERVED40[2]; + __IO uint16_t SCCRWL; + union + { + __IO uint16_t SCSRUH; + stc_tmr4_scsr_field_t SCSRUH_f; + }; + union + { + __IO uint16_t SCMRUH; + stc_tmr4_scmr_field_t SCMRUH_f; + }; + union + { + __IO uint16_t SCSRUL; + stc_tmr4_scsr_field_t SCSRUL_f; + }; + union + { + __IO uint16_t SCMRUL; + stc_tmr4_scmr_field_t SCMRUL_f; + }; + union + { + __IO uint16_t SCSRVH; + stc_tmr4_scsr_field_t SCSRVH_f; + }; + union + { + __IO uint16_t SCMRVH; + stc_tmr4_scmr_field_t SCMRVH_f; + }; + union + { + __IO uint16_t SCSRVL; + stc_tmr4_scsr_field_t SCSRVL_f; + }; + union + { + __IO uint16_t SCMRVL; + stc_tmr4_scmr_field_t SCMRVL_f; + }; + union + { + __IO uint16_t SCSRWH; + stc_tmr4_scsr_field_t SCSRWH_f; + }; + union + { + __IO uint16_t SCMRWH; + stc_tmr4_scmr_field_t SCMRWH_f; + }; + union + { + __IO uint16_t SCSRWL; + stc_tmr4_scsr_field_t SCSRWL_f; + }; + union + { + __IO uint16_t SCMRWL; + stc_tmr4_scmr_field_t SCMRWL_f; + }; + uint8_t RESERVED53[16]; + union + { + __IO uint16_t ECSR; + stc_tmr4_ecsr_field_t ECSR_f; + }; +}M4_TMR4_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t ECER1; + stc_tmr4_cr_ecer1_field_t ECER1_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t ECER2; + stc_tmr4_cr_ecer2_field_t ECER2_f; + }; + uint8_t RESERVED2[2]; + union + { + __IO uint16_t ECER3; + stc_tmr4_cr_ecer3_field_t ECER3_f; + }; +}M4_TMR4_CR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tmr6_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tmr6_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_tmr6_perbr_field_t PERBR_f; + }; + union + { + __IO uint32_t PERCR; + stc_tmr6_percr_field_t PERCR_f; + }; + union + { + __IO uint32_t GCMAR; + stc_tmr6_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_tmr6_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_tmr6_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_tmr6_gcmdr_field_t GCMDR_f; + }; + union + { + __IO uint32_t GCMER; + stc_tmr6_gcmer_field_t GCMER_f; + }; + union + { + __IO uint32_t GCMFR; + stc_tmr6_gcmfr_field_t GCMFR_f; + }; + union + { + __IO uint32_t SCMAR; + stc_tmr6_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_tmr6_scmbr_field_t SCMBR_f; + }; + union + { + __IO uint32_t SCMCR; + stc_tmr6_scmcr_field_t SCMCR_f; + }; + union + { + __IO uint32_t SCMDR; + stc_tmr6_scmdr_field_t SCMDR_f; + }; + union + { + __IO uint32_t SCMER; + stc_tmr6_scmer_field_t SCMER_f; + }; + union + { + __IO uint32_t SCMFR; + stc_tmr6_scmfr_field_t SCMFR_f; + }; + union + { + __IO uint32_t DTUAR; + stc_tmr6_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_tmr6_dtdar_field_t DTDAR_f; + }; + union + { + __IO uint32_t DTUBR; + stc_tmr6_dtubr_field_t DTUBR_f; + }; + union + { + __IO uint32_t DTDBR; + stc_tmr6_dtdbr_field_t DTDBR_f; + }; + union + { + __IO uint32_t GCONR; + stc_tmr6_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tmr6_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_tmr6_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tmr6_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_tmr6_dconr_field_t DCONR_f; + }; + uint8_t RESERVED25[4]; + union + { + __IO uint32_t FCONR; + stc_tmr6_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_tmr6_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tmr6_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_tmr6_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_tmr6_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCLRR; + stc_tmr6_hclrr_field_t HCLRR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_tmr6_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_tmr6_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tmr6_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tmr6_hcdor_field_t HCDOR_f; + }; +}M4_TMR6_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[1012]; + union + { + __IO uint32_t SSTAR; + stc_tmr6_cr_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_tmr6_cr_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_tmr6_cr_sclrr_field_t SCLRR_f; + }; +}M4_TMR6_CR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tmra_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tmra_perar_field_t PERAR_f; + }; + uint8_t RESERVED2[56]; + union + { + __IO uint32_t CMPAR1; + stc_tmra_cmpar_field_t CMPAR1_f; + }; + union + { + __IO uint32_t CMPAR2; + stc_tmra_cmpar_field_t CMPAR2_f; + }; + union + { + __IO uint32_t CMPAR3; + stc_tmra_cmpar_field_t CMPAR3_f; + }; + union + { + __IO uint32_t CMPAR4; + stc_tmra_cmpar_field_t CMPAR4_f; + }; + union + { + __IO uint32_t CMPAR5; + stc_tmra_cmpar_field_t CMPAR5_f; + }; + union + { + __IO uint32_t CMPAR6; + stc_tmra_cmpar_field_t CMPAR6_f; + }; + union + { + __IO uint32_t CMPAR7; + stc_tmra_cmpar_field_t CMPAR7_f; + }; + union + { + __IO uint32_t CMPAR8; + stc_tmra_cmpar_field_t CMPAR8_f; + }; + uint8_t RESERVED10[32]; + union + { + __IO uint32_t BCSTR; + stc_tmra_bcstr_field_t BCSTR_f; + }; + union + { + __IO uint32_t HCONR; + stc_tmra_hconr_field_t HCONR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tmra_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tmra_hcdor_field_t HCDOR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tmra_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t ECONR; + stc_tmra_econr_field_t ECONR_f; + }; + union + { + __IO uint32_t FCONR; + stc_tmra_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tmra_stflr_field_t STFLR_f; + }; + uint8_t RESERVED18[32]; + union + { + __IO uint32_t BCONR1; + stc_tmra_bconr_field_t BCONR1_f; + }; + uint8_t RESERVED19[4]; + union + { + __IO uint32_t BCONR2; + stc_tmra_bconr_field_t BCONR2_f; + }; + uint8_t RESERVED20[4]; + union + { + __IO uint32_t BCONR3; + stc_tmra_bconr_field_t BCONR3_f; + }; + uint8_t RESERVED21[4]; + union + { + __IO uint32_t BCONR4; + stc_tmra_bconr_field_t BCONR4_f; + }; + uint8_t RESERVED22[36]; + union + { + __IO uint32_t CCONR1; + stc_tmra_cconr_field_t CCONR1_f; + }; + union + { + __IO uint32_t CCONR2; + stc_tmra_cconr_field_t CCONR2_f; + }; + union + { + __IO uint32_t CCONR3; + stc_tmra_cconr_field_t CCONR3_f; + }; + union + { + __IO uint32_t CCONR4; + stc_tmra_cconr_field_t CCONR4_f; + }; + union + { + __IO uint32_t CCONR5; + stc_tmra_cconr_field_t CCONR5_f; + }; + union + { + __IO uint32_t CCONR6; + stc_tmra_cconr_field_t CCONR6_f; + }; + union + { + __IO uint32_t CCONR7; + stc_tmra_cconr_field_t CCONR7_f; + }; + union + { + __IO uint32_t CCONR8; + stc_tmra_cconr_field_t CCONR8_f; + }; + uint8_t RESERVED30[32]; + union + { + __IO uint32_t PCONR1; + stc_tmra_pconr_field_t PCONR1_f; + }; + union + { + __IO uint32_t PCONR2; + stc_tmra_pconr_field_t PCONR2_f; + }; + union + { + __IO uint32_t PCONR3; + stc_tmra_pconr_field_t PCONR3_f; + }; + union + { + __IO uint32_t PCONR4; + stc_tmra_pconr_field_t PCONR4_f; + }; + union + { + __IO uint32_t PCONR5; + stc_tmra_pconr_field_t PCONR5_f; + }; + union + { + __IO uint32_t PCONR6; + stc_tmra_pconr_field_t PCONR6_f; + }; + union + { + __IO uint32_t PCONR7; + stc_tmra_pconr_field_t PCONR7_f; + }; + union + { + __IO uint32_t PCONR8; + stc_tmra_pconr_field_t PCONR8_f; + }; +}M4_TMRA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_trng_cr_field_t CR_f; + }; + union + { + __IO uint32_t MR; + stc_trng_mr_field_t MR_f; + }; + uint8_t RESERVED2[4]; + __IO uint32_t DR0; + __IO uint32_t DR1; +}M4_TRNG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SR; + stc_usart_sr_field_t SR_f; + }; + union + { + __IO uint32_t DR; + stc_usart_dr_field_t DR_f; + }; + union + { + __IO uint32_t BRR; + stc_usart_brr_field_t BRR_f; + }; + union + { + __IO uint32_t CR1; + stc_usart_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_usart_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t CR3; + stc_usart_cr3_field_t CR3_f; + }; + union + { + __IO uint32_t PR; + stc_usart_pr_field_t PR_f; + }; +}M4_USART_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t USBFS_GVBUSCFG; + stc_usbfs_usbfs_gvbuscfg_field_t USBFS_GVBUSCFG_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t GAHBCFG; + stc_usbfs_gahbcfg_field_t GAHBCFG_f; + }; + union + { + __IO uint32_t GUSBCFG; + stc_usbfs_gusbcfg_field_t GUSBCFG_f; + }; + union + { + __IO uint32_t GRSTCTL; + stc_usbfs_grstctl_field_t GRSTCTL_f; + }; + union + { + __IO uint32_t GINTSTS; + stc_usbfs_gintsts_field_t GINTSTS_f; + }; + union + { + __IO uint32_t GINTMSK; + stc_usbfs_gintmsk_field_t GINTMSK_f; + }; + union + { + __IO uint32_t GRXSTSR; + stc_usbfs_grxstsr_field_t GRXSTSR_f; + }; + union + { + __IO uint32_t GRXSTSP; + stc_usbfs_grxstsp_field_t GRXSTSP_f; + }; + union + { + __IO uint32_t GRXFSIZ; + stc_usbfs_grxfsiz_field_t GRXFSIZ_f; + }; + union + { + __IO uint32_t HNPTXFSIZ; + stc_usbfs_hnptxfsiz_field_t HNPTXFSIZ_f; + }; + union + { + __IO uint32_t HNPTXSTS; + stc_usbfs_hnptxsts_field_t HNPTXSTS_f; + }; + uint8_t RESERVED11[12]; + __IO uint32_t CID; + uint8_t RESERVED12[192]; + union + { + __IO uint32_t HPTXFSIZ; + stc_usbfs_hptxfsiz_field_t HPTXFSIZ_f; + }; + union + { + __IO uint32_t DIEPTXF1; + stc_usbfs_dieptxf_field_t DIEPTXF1_f; + }; + union + { + __IO uint32_t DIEPTXF2; + stc_usbfs_dieptxf_field_t DIEPTXF2_f; + }; + union + { + __IO uint32_t DIEPTXF3; + stc_usbfs_dieptxf_field_t DIEPTXF3_f; + }; + union + { + __IO uint32_t DIEPTXF4; + stc_usbfs_dieptxf_field_t DIEPTXF4_f; + }; + union + { + __IO uint32_t DIEPTXF5; + stc_usbfs_dieptxf_field_t DIEPTXF5_f; + }; + uint8_t RESERVED18[744]; + union + { + __IO uint32_t HCFG; + stc_usbfs_hcfg_field_t HCFG_f; + }; + union + { + __IO uint32_t HFIR; + stc_usbfs_hfir_field_t HFIR_f; + }; + union + { + __IO uint32_t HFNUM; + stc_usbfs_hfnum_field_t HFNUM_f; + }; + uint8_t RESERVED21[4]; + union + { + __IO uint32_t HPTXSTS; + stc_usbfs_hptxsts_field_t HPTXSTS_f; + }; + union + { + __IO uint32_t HAINT; + stc_usbfs_haint_field_t HAINT_f; + }; + union + { + __IO uint32_t HAINTMSK; + stc_usbfs_haintmsk_field_t HAINTMSK_f; + }; + uint8_t RESERVED24[36]; + union + { + __IO uint32_t HPRT; + stc_usbfs_hprt_field_t HPRT_f; + }; + uint8_t RESERVED25[188]; + union + { + __IO uint32_t HCCHAR0; + stc_usbfs_hcchar_field_t HCCHAR0_f; + }; + uint8_t RESERVED26[4]; + union + { + __IO uint32_t HCINT0; + stc_usbfs_hcint_field_t HCINT0_f; + }; + union + { + __IO uint32_t HCINTMSK0; + stc_usbfs_hcintmsk_field_t HCINTMSK0_f; + }; + union + { + __IO uint32_t HCTSIZ0; + stc_usbfs_hctsiz_field_t HCTSIZ0_f; + }; + __IO uint32_t HCDMA0; + uint8_t RESERVED30[8]; + union + { + __IO uint32_t HCCHAR1; + stc_usbfs_hcchar_field_t HCCHAR1_f; + }; + uint8_t RESERVED31[4]; + union + { + __IO uint32_t HCINT1; + stc_usbfs_hcint_field_t HCINT1_f; + }; + union + { + __IO uint32_t HCINTMSK1; + stc_usbfs_hcintmsk_field_t HCINTMSK1_f; + }; + union + { + __IO uint32_t HCTSIZ1; + stc_usbfs_hctsiz_field_t HCTSIZ1_f; + }; + __IO uint32_t HCDMA1; + uint8_t RESERVED35[8]; + union + { + __IO uint32_t HCCHAR2; + stc_usbfs_hcchar_field_t HCCHAR2_f; + }; + uint8_t RESERVED36[4]; + union + { + __IO uint32_t HCINT2; + stc_usbfs_hcint_field_t HCINT2_f; + }; + union + { + __IO uint32_t HCINTMSK2; + stc_usbfs_hcintmsk_field_t HCINTMSK2_f; + }; + union + { + __IO uint32_t HCTSIZ2; + stc_usbfs_hctsiz_field_t HCTSIZ2_f; + }; + __IO uint32_t HCDMA2; + uint8_t RESERVED40[8]; + union + { + __IO uint32_t HCCHAR3; + stc_usbfs_hcchar_field_t HCCHAR3_f; + }; + uint8_t RESERVED41[4]; + union + { + __IO uint32_t HCINT3; + stc_usbfs_hcint_field_t HCINT3_f; + }; + union + { + __IO uint32_t HCINTMSK3; + stc_usbfs_hcintmsk_field_t HCINTMSK3_f; + }; + union + { + __IO uint32_t HCTSIZ3; + stc_usbfs_hctsiz_field_t HCTSIZ3_f; + }; + __IO uint32_t HCDMA3; + uint8_t RESERVED45[8]; + union + { + __IO uint32_t HCCHAR4; + stc_usbfs_hcchar_field_t HCCHAR4_f; + }; + uint8_t RESERVED46[4]; + union + { + __IO uint32_t HCINT4; + stc_usbfs_hcint_field_t HCINT4_f; + }; + union + { + __IO uint32_t HCINTMSK4; + stc_usbfs_hcintmsk_field_t HCINTMSK4_f; + }; + union + { + __IO uint32_t HCTSIZ4; + stc_usbfs_hctsiz_field_t HCTSIZ4_f; + }; + __IO uint32_t HCDMA4; + uint8_t RESERVED50[8]; + union + { + __IO uint32_t HCCHAR5; + stc_usbfs_hcchar_field_t HCCHAR5_f; + }; + uint8_t RESERVED51[4]; + union + { + __IO uint32_t HCINT5; + stc_usbfs_hcint_field_t HCINT5_f; + }; + union + { + __IO uint32_t HCINTMSK5; + stc_usbfs_hcintmsk_field_t HCINTMSK5_f; + }; + union + { + __IO uint32_t HCTSIZ5; + stc_usbfs_hctsiz_field_t HCTSIZ5_f; + }; + __IO uint32_t HCDMA5; + uint8_t RESERVED55[8]; + union + { + __IO uint32_t HCCHAR6; + stc_usbfs_hcchar_field_t HCCHAR6_f; + }; + uint8_t RESERVED56[4]; + union + { + __IO uint32_t HCINT6; + stc_usbfs_hcint_field_t HCINT6_f; + }; + union + { + __IO uint32_t HCINTMSK6; + stc_usbfs_hcintmsk_field_t HCINTMSK6_f; + }; + union + { + __IO uint32_t HCTSIZ6; + stc_usbfs_hctsiz_field_t HCTSIZ6_f; + }; + __IO uint32_t HCDMA6; + uint8_t RESERVED60[8]; + union + { + __IO uint32_t HCCHAR7; + stc_usbfs_hcchar_field_t HCCHAR7_f; + }; + uint8_t RESERVED61[4]; + union + { + __IO uint32_t HCINT7; + stc_usbfs_hcint_field_t HCINT7_f; + }; + union + { + __IO uint32_t HCINTMSK7; + stc_usbfs_hcintmsk_field_t HCINTMSK7_f; + }; + union + { + __IO uint32_t HCTSIZ7; + stc_usbfs_hctsiz_field_t HCTSIZ7_f; + }; + __IO uint32_t HCDMA7; + uint8_t RESERVED65[8]; + union + { + __IO uint32_t HCCHAR8; + stc_usbfs_hcchar_field_t HCCHAR8_f; + }; + uint8_t RESERVED66[4]; + union + { + __IO uint32_t HCINT8; + stc_usbfs_hcint_field_t HCINT8_f; + }; + union + { + __IO uint32_t HCINTMSK8; + stc_usbfs_hcintmsk_field_t HCINTMSK8_f; + }; + union + { + __IO uint32_t HCTSIZ8; + stc_usbfs_hctsiz_field_t HCTSIZ8_f; + }; + __IO uint32_t HCDMA8; + uint8_t RESERVED70[8]; + union + { + __IO uint32_t HCCHAR9; + stc_usbfs_hcchar_field_t HCCHAR9_f; + }; + uint8_t RESERVED71[4]; + union + { + __IO uint32_t HCINT9; + stc_usbfs_hcint_field_t HCINT9_f; + }; + union + { + __IO uint32_t HCINTMSK9; + stc_usbfs_hcintmsk_field_t HCINTMSK9_f; + }; + union + { + __IO uint32_t HCTSIZ9; + stc_usbfs_hctsiz_field_t HCTSIZ9_f; + }; + __IO uint32_t HCDMA9; + uint8_t RESERVED75[8]; + union + { + __IO uint32_t HCCHAR10; + stc_usbfs_hcchar_field_t HCCHAR10_f; + }; + uint8_t RESERVED76[4]; + union + { + __IO uint32_t HCINT10; + stc_usbfs_hcint_field_t HCINT10_f; + }; + union + { + __IO uint32_t HCINTMSK10; + stc_usbfs_hcintmsk_field_t HCINTMSK10_f; + }; + union + { + __IO uint32_t HCTSIZ10; + stc_usbfs_hctsiz_field_t HCTSIZ10_f; + }; + __IO uint32_t HCDMA10; + uint8_t RESERVED80[8]; + union + { + __IO uint32_t HCCHAR11; + stc_usbfs_hcchar_field_t HCCHAR11_f; + }; + uint8_t RESERVED81[4]; + union + { + __IO uint32_t HCINT11; + stc_usbfs_hcint_field_t HCINT11_f; + }; + union + { + __IO uint32_t HCINTMSK11; + stc_usbfs_hcintmsk_field_t HCINTMSK11_f; + }; + union + { + __IO uint32_t HCTSIZ11; + stc_usbfs_hctsiz_field_t HCTSIZ11_f; + }; + __IO uint32_t HCDMA11; + uint8_t RESERVED85[392]; + union + { + __IO uint32_t DCFG; + stc_usbfs_dcfg_field_t DCFG_f; + }; + union + { + __IO uint32_t DCTL; + stc_usbfs_dctl_field_t DCTL_f; + }; + union + { + __IO uint32_t DSTS; + stc_usbfs_dsts_field_t DSTS_f; + }; + uint8_t RESERVED88[4]; + union + { + __IO uint32_t DIEPMSK; + stc_usbfs_diepmsk_field_t DIEPMSK_f; + }; + union + { + __IO uint32_t DOEPMSK; + stc_usbfs_doepmsk_field_t DOEPMSK_f; + }; + union + { + __IO uint32_t DAINT; + stc_usbfs_daint_field_t DAINT_f; + }; + union + { + __IO uint32_t DAINTMSK; + stc_usbfs_daintmsk_field_t DAINTMSK_f; + }; + uint8_t RESERVED92[20]; + union + { + __IO uint32_t DIEPEMPMSK; + stc_usbfs_diepempmsk_field_t DIEPEMPMSK_f; + }; + uint8_t RESERVED93[200]; + union + { + __IO uint32_t DIEPCTL0; + stc_usbfs_diepctl0_field_t DIEPCTL0_f; + }; + uint8_t RESERVED94[4]; + union + { + __IO uint32_t DIEPINT0; + stc_usbfs_diepint0_field_t DIEPINT0_f; + }; + uint8_t RESERVED95[4]; + union + { + __IO uint32_t DIEPTSIZ0; + stc_usbfs_dieptsiz0_field_t DIEPTSIZ0_f; + }; + __IO uint32_t DIEPDMA0; + union + { + __IO uint32_t DTXFSTS0; + stc_usbfs_dtxfsts0_field_t DTXFSTS0_f; + }; + uint8_t RESERVED98[4]; + union + { + __IO uint32_t DIEPCTL1; + stc_usbfs_diepctl_field_t DIEPCTL1_f; + }; + uint8_t RESERVED99[4]; + union + { + __IO uint32_t DIEPINT1; + stc_usbfs_diepint_field_t DIEPINT1_f; + }; + uint8_t RESERVED100[4]; + union + { + __IO uint32_t DIEPTSIZ1; + stc_usbfs_dieptsiz_field_t DIEPTSIZ1_f; + }; + __IO uint32_t DIEPDMA1; + union + { + __IO uint32_t DTXFSTS1; + stc_usbfs_dtxfsts_field_t DTXFSTS1_f; + }; + uint8_t RESERVED103[4]; + union + { + __IO uint32_t DIEPCTL2; + stc_usbfs_diepctl_field_t DIEPCTL2_f; + }; + uint8_t RESERVED104[4]; + union + { + __IO uint32_t DIEPINT2; + stc_usbfs_diepint_field_t DIEPINT2_f; + }; + uint8_t RESERVED105[4]; + union + { + __IO uint32_t DIEPTSIZ2; + stc_usbfs_dieptsiz_field_t DIEPTSIZ2_f; + }; + __IO uint32_t DIEPDMA2; + union + { + __IO uint32_t DTXFSTS2; + stc_usbfs_dtxfsts_field_t DTXFSTS2_f; + }; + uint8_t RESERVED108[4]; + union + { + __IO uint32_t DIEPCTL3; + stc_usbfs_diepctl_field_t DIEPCTL3_f; + }; + uint8_t RESERVED109[4]; + union + { + __IO uint32_t DIEPINT3; + stc_usbfs_diepint_field_t DIEPINT3_f; + }; + uint8_t RESERVED110[4]; + union + { + __IO uint32_t DIEPTSIZ3; + stc_usbfs_dieptsiz_field_t DIEPTSIZ3_f; + }; + __IO uint32_t DIEPDMA3; + union + { + __IO uint32_t DTXFSTS3; + stc_usbfs_dtxfsts_field_t DTXFSTS3_f; + }; + uint8_t RESERVED113[4]; + union + { + __IO uint32_t DIEPCTL4; + stc_usbfs_diepctl_field_t DIEPCTL4_f; + }; + uint8_t RESERVED114[4]; + union + { + __IO uint32_t DIEPINT4; + stc_usbfs_diepint_field_t DIEPINT4_f; + }; + uint8_t RESERVED115[4]; + union + { + __IO uint32_t DIEPTSIZ4; + stc_usbfs_dieptsiz_field_t DIEPTSIZ4_f; + }; + __IO uint32_t DIEPDMA4; + union + { + __IO uint32_t DTXFSTS4; + stc_usbfs_dtxfsts_field_t DTXFSTS4_f; + }; + uint8_t RESERVED118[4]; + union + { + __IO uint32_t DIEPCTL5; + stc_usbfs_diepctl_field_t DIEPCTL5_f; + }; + uint8_t RESERVED119[4]; + union + { + __IO uint32_t DIEPINT5; + stc_usbfs_diepint_field_t DIEPINT5_f; + }; + uint8_t RESERVED120[4]; + union + { + __IO uint32_t DIEPTSIZ5; + stc_usbfs_dieptsiz_field_t DIEPTSIZ5_f; + }; + __IO uint32_t DIEPDMA5; + union + { + __IO uint32_t DTXFSTS5; + stc_usbfs_dtxfsts_field_t DTXFSTS5_f; + }; + uint8_t RESERVED123[324]; + union + { + __IO uint32_t DOEPCTL0; + stc_usbfs_doepctl0_field_t DOEPCTL0_f; + }; + uint8_t RESERVED124[4]; + union + { + __IO uint32_t DOEPINT0; + stc_usbfs_doepint_field_t DOEPINT0_f; + }; + uint8_t RESERVED125[4]; + union + { + __IO uint32_t DOEPTSIZ0; + stc_usbfs_doeptsiz0_field_t DOEPTSIZ0_f; + }; + __IO uint32_t DOEPDMA0; + uint8_t RESERVED127[8]; + union + { + __IO uint32_t DOEPCTL1; + stc_usbfs_doepctl_field_t DOEPCTL1_f; + }; + uint8_t RESERVED128[4]; + union + { + __IO uint32_t DOEPINT1; + stc_usbfs_doepint_field_t DOEPINT1_f; + }; + uint8_t RESERVED129[4]; + union + { + __IO uint32_t DOEPTSIZ1; + stc_usbfs_doeptsiz_field_t DOEPTSIZ1_f; + }; + __IO uint32_t DOEPDMA1; + uint8_t RESERVED131[8]; + union + { + __IO uint32_t DOEPCTL2; + stc_usbfs_doepctl_field_t DOEPCTL2_f; + }; + uint8_t RESERVED132[4]; + union + { + __IO uint32_t DOEPINT2; + stc_usbfs_doepint_field_t DOEPINT2_f; + }; + uint8_t RESERVED133[4]; + union + { + __IO uint32_t DOEPTSIZ2; + stc_usbfs_doeptsiz_field_t DOEPTSIZ2_f; + }; + __IO uint32_t DOEPDMA2; + uint8_t RESERVED135[8]; + union + { + __IO uint32_t DOEPCTL3; + stc_usbfs_doepctl_field_t DOEPCTL3_f; + }; + uint8_t RESERVED136[4]; + union + { + __IO uint32_t DOEPINT3; + stc_usbfs_doepint_field_t DOEPINT3_f; + }; + uint8_t RESERVED137[4]; + union + { + __IO uint32_t DOEPTSIZ3; + stc_usbfs_doeptsiz_field_t DOEPTSIZ3_f; + }; + __IO uint32_t DOEPDMA3; + uint8_t RESERVED139[8]; + union + { + __IO uint32_t DOEPCTL4; + stc_usbfs_doepctl_field_t DOEPCTL4_f; + }; + uint8_t RESERVED140[4]; + union + { + __IO uint32_t DOEPINT4; + stc_usbfs_doepint_field_t DOEPINT4_f; + }; + uint8_t RESERVED141[4]; + union + { + __IO uint32_t DOEPTSIZ4; + stc_usbfs_doeptsiz_field_t DOEPTSIZ4_f; + }; + __IO uint32_t DOEPDMA4; + uint8_t RESERVED143[8]; + union + { + __IO uint32_t DOEPCTL5; + stc_usbfs_doepctl_field_t DOEPCTL5_f; + }; + uint8_t RESERVED144[4]; + union + { + __IO uint32_t DOEPINT5; + stc_usbfs_doepint_field_t DOEPINT5_f; + }; + uint8_t RESERVED145[4]; + union + { + __IO uint32_t DOEPTSIZ5; + stc_usbfs_doeptsiz_field_t DOEPTSIZ5_f; + }; + __IO uint32_t DOEPDMA5; + uint8_t RESERVED147[584]; + union + { + __IO uint32_t PCGCCTL; + stc_usbfs_pcgcctl_field_t PCGCCTL_f; + }; +}M4_USBFS_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_wdt_cr_field_t CR_f; + }; + union + { + __IO uint32_t SR; + stc_wdt_sr_field_t SR_f; + }; + union + { + __IO uint32_t RR; + stc_wdt_rr_field_t RR_f; + }; +}M4_WDT_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t CR; + stc_wktm_cr_field_t CR_f; + }; +}M4_WKTM_TypeDef; + + + +#define M4_ADC1 ((M4_ADC_TypeDef *)0x40040000UL) +#define M4_ADC2 ((M4_ADC_TypeDef *)0x40040400UL) +#define M4_AES ((M4_AES_TypeDef *)0x40008000UL) +#define M4_AOS ((M4_AOS_TypeDef *)0x40010800UL) +#define M4_CAN ((M4_CAN_TypeDef *)0x40070400UL) +#define M4_CMP1 ((M4_CMP_TypeDef *)0x4004A000UL) +#define M4_CMP2 ((M4_CMP_TypeDef *)0x4004A010UL) +#define M4_CMP3 ((M4_CMP_TypeDef *)0x4004A020UL) +#define M4_CMP_CR ((M4_CMP_CR_TypeDef *)0x4004A000UL) +#define M4_CRC ((M4_CRC_TypeDef *)0x40008C00UL) +#define M4_DBGC ((M4_DBGC_TypeDef *)0xE0042000UL) +#define M4_DCU1 ((M4_DCU_TypeDef *)0x40052000UL) +#define M4_DCU2 ((M4_DCU_TypeDef *)0x40052400UL) +#define M4_DCU3 ((M4_DCU_TypeDef *)0x40052800UL) +#define M4_DCU4 ((M4_DCU_TypeDef *)0x40052C00UL) +#define M4_DMA1 ((M4_DMA_TypeDef *)0x40053000UL) +#define M4_DMA2 ((M4_DMA_TypeDef *)0x40053400UL) +#define M4_EFM ((M4_EFM_TypeDef *)0x40010400UL) +#define M4_EMB1 ((M4_EMB_TypeDef *)0x40017C00UL) +#define M4_EMB2 ((M4_EMB_TypeDef *)0x40017C20UL) +#define M4_EMB3 ((M4_EMB_TypeDef *)0x40017C40UL) +#define M4_EMB4 ((M4_EMB_TypeDef *)0x40017C60UL) +#define M4_FCM ((M4_FCM_TypeDef *)0x40048400UL) +#define M4_HASH ((M4_HASH_TypeDef *)0x40008400UL) +#define M4_I2C1 ((M4_I2C_TypeDef *)0x4004E000UL) +#define M4_I2C2 ((M4_I2C_TypeDef *)0x4004E400UL) +#define M4_I2C3 ((M4_I2C_TypeDef *)0x4004E800UL) +#define M4_I2S1 ((M4_I2S_TypeDef *)0x4001E000UL) +#define M4_I2S2 ((M4_I2S_TypeDef *)0x4001E400UL) +#define M4_I2S3 ((M4_I2S_TypeDef *)0x40022000UL) +#define M4_I2S4 ((M4_I2S_TypeDef *)0x40022400UL) +#define M4_ICG ((M4_ICG_TypeDef *)0x00000400UL) +#define M4_INTC ((M4_INTC_TypeDef *)0x40051000UL) +#define M4_KEYSCAN ((M4_KEYSCAN_TypeDef *)0x40050C00UL) +#define M4_MPU ((M4_MPU_TypeDef *)0x40050000UL) +#define M4_MSTP ((M4_MSTP_TypeDef *)0x40048000UL) +#define M4_OTS ((M4_OTS_TypeDef *)0x4004A400UL) +#define M4_PERIC ((M4_PERIC_TypeDef *)0x40055400UL) +#define M4_PORT ((M4_PORT_TypeDef *)0x40053800UL) +#define M4_QSPI ((M4_QSPI_TypeDef *)0x9C000000UL) +#define M4_RTC ((M4_RTC_TypeDef *)0x4004C000UL) +#define M4_SDIOC1 ((M4_SDIOC_TypeDef *)0x4006FC00UL) +#define M4_SDIOC2 ((M4_SDIOC_TypeDef *)0x40070000UL) +#define M4_SPI1 ((M4_SPI_TypeDef *)0x4001C000UL) +#define M4_SPI2 ((M4_SPI_TypeDef *)0x4001C400UL) +#define M4_SPI3 ((M4_SPI_TypeDef *)0x40020000UL) +#define M4_SPI4 ((M4_SPI_TypeDef *)0x40020400UL) +#define M4_SRAMC ((M4_SRAMC_TypeDef *)0x40050800UL) +#define M4_SWDT ((M4_SWDT_TypeDef *)0x40049400UL) +#define M4_SYSREG ((M4_SYSREG_TypeDef *)0x40054000UL) +#define M4_TMR01 ((M4_TMR0_TypeDef *)0x40024000UL) +#define M4_TMR02 ((M4_TMR0_TypeDef *)0x40024400UL) +#define M4_TMR41 ((M4_TMR4_TypeDef *)0x40017000UL) +#define M4_TMR42 ((M4_TMR4_TypeDef *)0x40024800UL) +#define M4_TMR43 ((M4_TMR4_TypeDef *)0x40024C00UL) +#define M4_TMR4_CR ((M4_TMR4_CR_TypeDef *)0x40055408UL) +#define M4_TMR61 ((M4_TMR6_TypeDef *)0x40018000UL) +#define M4_TMR62 ((M4_TMR6_TypeDef *)0x40018400UL) +#define M4_TMR63 ((M4_TMR6_TypeDef *)0x40018800UL) +#define M4_TMR6_CR ((M4_TMR6_CR_TypeDef *)0x40018000UL) +#define M4_TMRA1 ((M4_TMRA_TypeDef *)0x40015000UL) +#define M4_TMRA2 ((M4_TMRA_TypeDef *)0x40015400UL) +#define M4_TMRA3 ((M4_TMRA_TypeDef *)0x40015800UL) +#define M4_TMRA4 ((M4_TMRA_TypeDef *)0x40015C00UL) +#define M4_TMRA5 ((M4_TMRA_TypeDef *)0x40016000UL) +#define M4_TMRA6 ((M4_TMRA_TypeDef *)0x40016400UL) +#define M4_TRNG ((M4_TRNG_TypeDef *)0x40041000UL) +#define M4_USART1 ((M4_USART_TypeDef *)0x4001D000UL) +#define M4_USART2 ((M4_USART_TypeDef *)0x4001D400UL) +#define M4_USART3 ((M4_USART_TypeDef *)0x40021000UL) +#define M4_USART4 ((M4_USART_TypeDef *)0x40021400UL) +#define M4_USBFS ((M4_USBFS_TypeDef *)0x400C0000UL) +#define M4_WDT ((M4_WDT_TypeDef *)0x40049000UL) +#define M4_WKTM ((M4_WKTM_TypeDef *)0x4004C400UL) + + +#define bM4_ADC1_STR_STRT (*((volatile unsigned int*)(0x42800000UL))) +#define bM4_ADC1_CR0_MS0 (*((volatile unsigned int*)(0x42800040UL))) +#define bM4_ADC1_CR0_MS1 (*((volatile unsigned int*)(0x42800044UL))) +#define bM4_ADC1_CR0_ACCSEL0 (*((volatile unsigned int*)(0x42800050UL))) +#define bM4_ADC1_CR0_ACCSEL1 (*((volatile unsigned int*)(0x42800054UL))) +#define bM4_ADC1_CR0_CLREN (*((volatile unsigned int*)(0x42800058UL))) +#define bM4_ADC1_CR0_DFMT (*((volatile unsigned int*)(0x4280005CUL))) +#define bM4_ADC1_CR0_AVCNT0 (*((volatile unsigned int*)(0x42800060UL))) +#define bM4_ADC1_CR0_AVCNT1 (*((volatile unsigned int*)(0x42800064UL))) +#define bM4_ADC1_CR0_AVCNT2 (*((volatile unsigned int*)(0x42800068UL))) +#define bM4_ADC1_CR1_RSCHSEL (*((volatile unsigned int*)(0x42800088UL))) +#define bM4_ADC1_TRGSR_TRGSELA0 (*((volatile unsigned int*)(0x42800140UL))) +#define bM4_ADC1_TRGSR_TRGSELA1 (*((volatile unsigned int*)(0x42800144UL))) +#define bM4_ADC1_TRGSR_TRGSELA2 (*((volatile unsigned int*)(0x42800148UL))) +#define bM4_ADC1_TRGSR_TRGENA (*((volatile unsigned int*)(0x4280015CUL))) +#define bM4_ADC1_TRGSR_TRGSELB0 (*((volatile unsigned int*)(0x42800160UL))) +#define bM4_ADC1_TRGSR_TRGSELB1 (*((volatile unsigned int*)(0x42800164UL))) +#define bM4_ADC1_TRGSR_TRGSELB2 (*((volatile unsigned int*)(0x42800168UL))) +#define bM4_ADC1_TRGSR_TRGENB (*((volatile unsigned int*)(0x4280017CUL))) +#define bM4_ADC1_CHSELRA1_CHSELA16 (*((volatile unsigned int*)(0x428001C0UL))) +#define bM4_ADC1_CHSELRB1_CHSELB16 (*((volatile unsigned int*)(0x42800240UL))) +#define bM4_ADC1_AVCHSELR1_AVCHSEL16 (*((volatile unsigned int*)(0x428002C0UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX0 (*((volatile unsigned int*)(0x42800700UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX1 (*((volatile unsigned int*)(0x42800704UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX2 (*((volatile unsigned int*)(0x42800708UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX3 (*((volatile unsigned int*)(0x4280070CUL))) +#define bM4_ADC1_CHMUXR0_CH01MUX0 (*((volatile unsigned int*)(0x42800710UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX1 (*((volatile unsigned int*)(0x42800714UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX2 (*((volatile unsigned int*)(0x42800718UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX3 (*((volatile unsigned int*)(0x4280071CUL))) +#define bM4_ADC1_CHMUXR0_CH02MUX0 (*((volatile unsigned int*)(0x42800720UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX1 (*((volatile unsigned int*)(0x42800724UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX2 (*((volatile unsigned int*)(0x42800728UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX3 (*((volatile unsigned int*)(0x4280072CUL))) +#define bM4_ADC1_CHMUXR0_CH03MUX0 (*((volatile unsigned int*)(0x42800730UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX1 (*((volatile unsigned int*)(0x42800734UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX2 (*((volatile unsigned int*)(0x42800738UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX3 (*((volatile unsigned int*)(0x4280073CUL))) +#define bM4_ADC1_CHMUXR1_CH04MUX0 (*((volatile unsigned int*)(0x42800740UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX1 (*((volatile unsigned int*)(0x42800744UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX2 (*((volatile unsigned int*)(0x42800748UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX3 (*((volatile unsigned int*)(0x4280074CUL))) +#define bM4_ADC1_CHMUXR1_CH05MUX0 (*((volatile unsigned int*)(0x42800750UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX1 (*((volatile unsigned int*)(0x42800754UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX2 (*((volatile unsigned int*)(0x42800758UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX3 (*((volatile unsigned int*)(0x4280075CUL))) +#define bM4_ADC1_CHMUXR1_CH06MUX0 (*((volatile unsigned int*)(0x42800760UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX1 (*((volatile unsigned int*)(0x42800764UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX2 (*((volatile unsigned int*)(0x42800768UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX3 (*((volatile unsigned int*)(0x4280076CUL))) +#define bM4_ADC1_CHMUXR1_CH07MUX0 (*((volatile unsigned int*)(0x42800770UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX1 (*((volatile unsigned int*)(0x42800774UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX2 (*((volatile unsigned int*)(0x42800778UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX3 (*((volatile unsigned int*)(0x4280077CUL))) +#define bM4_ADC1_CHMUXR2_CH08MUX0 (*((volatile unsigned int*)(0x42800780UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX1 (*((volatile unsigned int*)(0x42800784UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX2 (*((volatile unsigned int*)(0x42800788UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX3 (*((volatile unsigned int*)(0x4280078CUL))) +#define bM4_ADC1_CHMUXR2_CH09MUX0 (*((volatile unsigned int*)(0x42800790UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX1 (*((volatile unsigned int*)(0x42800794UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX2 (*((volatile unsigned int*)(0x42800798UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX3 (*((volatile unsigned int*)(0x4280079CUL))) +#define bM4_ADC1_CHMUXR2_CH10MUX0 (*((volatile unsigned int*)(0x428007A0UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX1 (*((volatile unsigned int*)(0x428007A4UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX2 (*((volatile unsigned int*)(0x428007A8UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX3 (*((volatile unsigned int*)(0x428007ACUL))) +#define bM4_ADC1_CHMUXR2_CH11MUX0 (*((volatile unsigned int*)(0x428007B0UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX1 (*((volatile unsigned int*)(0x428007B4UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX2 (*((volatile unsigned int*)(0x428007B8UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX3 (*((volatile unsigned int*)(0x428007BCUL))) +#define bM4_ADC1_CHMUXR3_CH12MUX0 (*((volatile unsigned int*)(0x428007C0UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX1 (*((volatile unsigned int*)(0x428007C4UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX2 (*((volatile unsigned int*)(0x428007C8UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX3 (*((volatile unsigned int*)(0x428007CCUL))) +#define bM4_ADC1_CHMUXR3_CH13MUX0 (*((volatile unsigned int*)(0x428007D0UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX1 (*((volatile unsigned int*)(0x428007D4UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX2 (*((volatile unsigned int*)(0x428007D8UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX3 (*((volatile unsigned int*)(0x428007DCUL))) +#define bM4_ADC1_CHMUXR3_CH14MUX0 (*((volatile unsigned int*)(0x428007E0UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX1 (*((volatile unsigned int*)(0x428007E4UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX2 (*((volatile unsigned int*)(0x428007E8UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX3 (*((volatile unsigned int*)(0x428007ECUL))) +#define bM4_ADC1_CHMUXR3_CH15MUX0 (*((volatile unsigned int*)(0x428007F0UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX1 (*((volatile unsigned int*)(0x428007F4UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX2 (*((volatile unsigned int*)(0x428007F8UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX3 (*((volatile unsigned int*)(0x428007FCUL))) +#define bM4_ADC1_ISR_EOCAF (*((volatile unsigned int*)(0x428008C0UL))) +#define bM4_ADC1_ISR_EOCBF (*((volatile unsigned int*)(0x428008C4UL))) +#define bM4_ADC1_ICR_EOCAIEN (*((volatile unsigned int*)(0x428008E0UL))) +#define bM4_ADC1_ICR_EOCBIEN (*((volatile unsigned int*)(0x428008E4UL))) +#define bM4_ADC1_SYNCCR_SYNCEN (*((volatile unsigned int*)(0x42800980UL))) +#define bM4_ADC1_SYNCCR_SYNCMD0 (*((volatile unsigned int*)(0x42800990UL))) +#define bM4_ADC1_SYNCCR_SYNCMD1 (*((volatile unsigned int*)(0x42800994UL))) +#define bM4_ADC1_SYNCCR_SYNCMD2 (*((volatile unsigned int*)(0x42800998UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY0 (*((volatile unsigned int*)(0x428009A0UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY1 (*((volatile unsigned int*)(0x428009A4UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY2 (*((volatile unsigned int*)(0x428009A8UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY3 (*((volatile unsigned int*)(0x428009ACUL))) +#define bM4_ADC1_SYNCCR_SYNCDLY4 (*((volatile unsigned int*)(0x428009B0UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY5 (*((volatile unsigned int*)(0x428009B4UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY6 (*((volatile unsigned int*)(0x428009B8UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY7 (*((volatile unsigned int*)(0x428009BCUL))) +#define bM4_ADC1_AWDCR_AWDEN (*((volatile unsigned int*)(0x42801400UL))) +#define bM4_ADC1_AWDCR_AWDMD (*((volatile unsigned int*)(0x42801410UL))) +#define bM4_ADC1_AWDCR_AWDSS0 (*((volatile unsigned int*)(0x42801418UL))) +#define bM4_ADC1_AWDCR_AWDSS1 (*((volatile unsigned int*)(0x4280141CUL))) +#define bM4_ADC1_AWDCR_AWDIEN (*((volatile unsigned int*)(0x42801420UL))) +#define bM4_ADC1_AWDCHSR1_AWDCH16 (*((volatile unsigned int*)(0x428015C0UL))) +#define bM4_ADC1_AWDSR1_AWDF16 (*((volatile unsigned int*)(0x42801640UL))) +#define bM4_ADC1_PGACR_PGACTL0 (*((volatile unsigned int*)(0x42801800UL))) +#define bM4_ADC1_PGACR_PGACTL1 (*((volatile unsigned int*)(0x42801804UL))) +#define bM4_ADC1_PGACR_PGACTL2 (*((volatile unsigned int*)(0x42801808UL))) +#define bM4_ADC1_PGACR_PGACTL3 (*((volatile unsigned int*)(0x4280180CUL))) +#define bM4_ADC1_PGAGSR_GAIN0 (*((volatile unsigned int*)(0x42801840UL))) +#define bM4_ADC1_PGAGSR_GAIN1 (*((volatile unsigned int*)(0x42801844UL))) +#define bM4_ADC1_PGAGSR_GAIN2 (*((volatile unsigned int*)(0x42801848UL))) +#define bM4_ADC1_PGAGSR_GAIN3 (*((volatile unsigned int*)(0x4280184CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL0 (*((volatile unsigned int*)(0x42801980UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL1 (*((volatile unsigned int*)(0x42801984UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL2 (*((volatile unsigned int*)(0x42801988UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL3 (*((volatile unsigned int*)(0x4280198CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL4 (*((volatile unsigned int*)(0x42801990UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL5 (*((volatile unsigned int*)(0x42801994UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL6 (*((volatile unsigned int*)(0x42801998UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL7 (*((volatile unsigned int*)(0x4280199CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL8 (*((volatile unsigned int*)(0x428019A0UL))) +#define bM4_ADC1_PGAINSR1_PGAVSSEN (*((volatile unsigned int*)(0x428019C0UL))) +#define bM4_ADC2_STR_STRT (*((volatile unsigned int*)(0x42808000UL))) +#define bM4_ADC2_CR0_MS0 (*((volatile unsigned int*)(0x42808040UL))) +#define bM4_ADC2_CR0_MS1 (*((volatile unsigned int*)(0x42808044UL))) +#define bM4_ADC2_CR0_ACCSEL0 (*((volatile unsigned int*)(0x42808050UL))) +#define bM4_ADC2_CR0_ACCSEL1 (*((volatile unsigned int*)(0x42808054UL))) +#define bM4_ADC2_CR0_CLREN (*((volatile unsigned int*)(0x42808058UL))) +#define bM4_ADC2_CR0_DFMT (*((volatile unsigned int*)(0x4280805CUL))) +#define bM4_ADC2_CR0_AVCNT0 (*((volatile unsigned int*)(0x42808060UL))) +#define bM4_ADC2_CR0_AVCNT1 (*((volatile unsigned int*)(0x42808064UL))) +#define bM4_ADC2_CR0_AVCNT2 (*((volatile unsigned int*)(0x42808068UL))) +#define bM4_ADC2_CR1_RSCHSEL (*((volatile unsigned int*)(0x42808088UL))) +#define bM4_ADC2_TRGSR_TRGSELA0 (*((volatile unsigned int*)(0x42808140UL))) +#define bM4_ADC2_TRGSR_TRGSELA1 (*((volatile unsigned int*)(0x42808144UL))) +#define bM4_ADC2_TRGSR_TRGSELA2 (*((volatile unsigned int*)(0x42808148UL))) +#define bM4_ADC2_TRGSR_TRGENA (*((volatile unsigned int*)(0x4280815CUL))) +#define bM4_ADC2_TRGSR_TRGSELB0 (*((volatile unsigned int*)(0x42808160UL))) +#define bM4_ADC2_TRGSR_TRGSELB1 (*((volatile unsigned int*)(0x42808164UL))) +#define bM4_ADC2_TRGSR_TRGSELB2 (*((volatile unsigned int*)(0x42808168UL))) +#define bM4_ADC2_TRGSR_TRGENB (*((volatile unsigned int*)(0x4280817CUL))) +#define bM4_ADC2_CHSELRA1_CHSELA16 (*((volatile unsigned int*)(0x428081C0UL))) +#define bM4_ADC2_CHSELRB1_CHSELB16 (*((volatile unsigned int*)(0x42808240UL))) +#define bM4_ADC2_AVCHSELR1_AVCHSEL16 (*((volatile unsigned int*)(0x428082C0UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX0 (*((volatile unsigned int*)(0x42808700UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX1 (*((volatile unsigned int*)(0x42808704UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX2 (*((volatile unsigned int*)(0x42808708UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX3 (*((volatile unsigned int*)(0x4280870CUL))) +#define bM4_ADC2_CHMUXR0_CH01MUX0 (*((volatile unsigned int*)(0x42808710UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX1 (*((volatile unsigned int*)(0x42808714UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX2 (*((volatile unsigned int*)(0x42808718UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX3 (*((volatile unsigned int*)(0x4280871CUL))) +#define bM4_ADC2_CHMUXR0_CH02MUX0 (*((volatile unsigned int*)(0x42808720UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX1 (*((volatile unsigned int*)(0x42808724UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX2 (*((volatile unsigned int*)(0x42808728UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX3 (*((volatile unsigned int*)(0x4280872CUL))) +#define bM4_ADC2_CHMUXR0_CH03MUX0 (*((volatile unsigned int*)(0x42808730UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX1 (*((volatile unsigned int*)(0x42808734UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX2 (*((volatile unsigned int*)(0x42808738UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX3 (*((volatile unsigned int*)(0x4280873CUL))) +#define bM4_ADC2_CHMUXR1_CH04MUX0 (*((volatile unsigned int*)(0x42808740UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX1 (*((volatile unsigned int*)(0x42808744UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX2 (*((volatile unsigned int*)(0x42808748UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX3 (*((volatile unsigned int*)(0x4280874CUL))) +#define bM4_ADC2_CHMUXR1_CH05MUX0 (*((volatile unsigned int*)(0x42808750UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX1 (*((volatile unsigned int*)(0x42808754UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX2 (*((volatile unsigned int*)(0x42808758UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX3 (*((volatile unsigned int*)(0x4280875CUL))) +#define bM4_ADC2_CHMUXR1_CH06MUX0 (*((volatile unsigned int*)(0x42808760UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX1 (*((volatile unsigned int*)(0x42808764UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX2 (*((volatile unsigned int*)(0x42808768UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX3 (*((volatile unsigned int*)(0x4280876CUL))) +#define bM4_ADC2_CHMUXR1_CH07MUX0 (*((volatile unsigned int*)(0x42808770UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX1 (*((volatile unsigned int*)(0x42808774UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX2 (*((volatile unsigned int*)(0x42808778UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX3 (*((volatile unsigned int*)(0x4280877CUL))) +#define bM4_ADC2_CHMUXR2_CH08MUX0 (*((volatile unsigned int*)(0x42808780UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX1 (*((volatile unsigned int*)(0x42808784UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX2 (*((volatile unsigned int*)(0x42808788UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX3 (*((volatile unsigned int*)(0x4280878CUL))) +#define bM4_ADC2_CHMUXR2_CH09MUX0 (*((volatile unsigned int*)(0x42808790UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX1 (*((volatile unsigned int*)(0x42808794UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX2 (*((volatile unsigned int*)(0x42808798UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX3 (*((volatile unsigned int*)(0x4280879CUL))) +#define bM4_ADC2_CHMUXR2_CH10MUX0 (*((volatile unsigned int*)(0x428087A0UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX1 (*((volatile unsigned int*)(0x428087A4UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX2 (*((volatile unsigned int*)(0x428087A8UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX3 (*((volatile unsigned int*)(0x428087ACUL))) +#define bM4_ADC2_CHMUXR2_CH11MUX0 (*((volatile unsigned int*)(0x428087B0UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX1 (*((volatile unsigned int*)(0x428087B4UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX2 (*((volatile unsigned int*)(0x428087B8UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX3 (*((volatile unsigned int*)(0x428087BCUL))) +#define bM4_ADC2_CHMUXR3_CH12MUX0 (*((volatile unsigned int*)(0x428087C0UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX1 (*((volatile unsigned int*)(0x428087C4UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX2 (*((volatile unsigned int*)(0x428087C8UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX3 (*((volatile unsigned int*)(0x428087CCUL))) +#define bM4_ADC2_CHMUXR3_CH13MUX0 (*((volatile unsigned int*)(0x428087D0UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX1 (*((volatile unsigned int*)(0x428087D4UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX2 (*((volatile unsigned int*)(0x428087D8UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX3 (*((volatile unsigned int*)(0x428087DCUL))) +#define bM4_ADC2_CHMUXR3_CH14MUX0 (*((volatile unsigned int*)(0x428087E0UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX1 (*((volatile unsigned int*)(0x428087E4UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX2 (*((volatile unsigned int*)(0x428087E8UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX3 (*((volatile unsigned int*)(0x428087ECUL))) +#define bM4_ADC2_CHMUXR3_CH15MUX0 (*((volatile unsigned int*)(0x428087F0UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX1 (*((volatile unsigned int*)(0x428087F4UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX2 (*((volatile unsigned int*)(0x428087F8UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX3 (*((volatile unsigned int*)(0x428087FCUL))) +#define bM4_ADC2_ISR_EOCAF (*((volatile unsigned int*)(0x428088C0UL))) +#define bM4_ADC2_ISR_EOCBF (*((volatile unsigned int*)(0x428088C4UL))) +#define bM4_ADC2_ICR_EOCAIEN (*((volatile unsigned int*)(0x428088E0UL))) +#define bM4_ADC2_ICR_EOCBIEN (*((volatile unsigned int*)(0x428088E4UL))) +#define bM4_ADC2_SYNCCR_SYNCEN (*((volatile unsigned int*)(0x42808980UL))) +#define bM4_ADC2_SYNCCR_SYNCMD0 (*((volatile unsigned int*)(0x42808990UL))) +#define bM4_ADC2_SYNCCR_SYNCMD1 (*((volatile unsigned int*)(0x42808994UL))) +#define bM4_ADC2_SYNCCR_SYNCMD2 (*((volatile unsigned int*)(0x42808998UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY0 (*((volatile unsigned int*)(0x428089A0UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY1 (*((volatile unsigned int*)(0x428089A4UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY2 (*((volatile unsigned int*)(0x428089A8UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY3 (*((volatile unsigned int*)(0x428089ACUL))) +#define bM4_ADC2_SYNCCR_SYNCDLY4 (*((volatile unsigned int*)(0x428089B0UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY5 (*((volatile unsigned int*)(0x428089B4UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY6 (*((volatile unsigned int*)(0x428089B8UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY7 (*((volatile unsigned int*)(0x428089BCUL))) +#define bM4_ADC2_AWDCR_AWDEN (*((volatile unsigned int*)(0x42809400UL))) +#define bM4_ADC2_AWDCR_AWDMD (*((volatile unsigned int*)(0x42809410UL))) +#define bM4_ADC2_AWDCR_AWDSS0 (*((volatile unsigned int*)(0x42809418UL))) +#define bM4_ADC2_AWDCR_AWDSS1 (*((volatile unsigned int*)(0x4280941CUL))) +#define bM4_ADC2_AWDCR_AWDIEN (*((volatile unsigned int*)(0x42809420UL))) +#define bM4_ADC2_AWDCHSR1_AWDCH16 (*((volatile unsigned int*)(0x428095C0UL))) +#define bM4_ADC2_AWDSR1_AWDF16 (*((volatile unsigned int*)(0x42809640UL))) +#define bM4_ADC2_PGACR_PGACTL0 (*((volatile unsigned int*)(0x42809800UL))) +#define bM4_ADC2_PGACR_PGACTL1 (*((volatile unsigned int*)(0x42809804UL))) +#define bM4_ADC2_PGACR_PGACTL2 (*((volatile unsigned int*)(0x42809808UL))) +#define bM4_ADC2_PGACR_PGACTL3 (*((volatile unsigned int*)(0x4280980CUL))) +#define bM4_ADC2_PGAGSR_GAIN0 (*((volatile unsigned int*)(0x42809840UL))) +#define bM4_ADC2_PGAGSR_GAIN1 (*((volatile unsigned int*)(0x42809844UL))) +#define bM4_ADC2_PGAGSR_GAIN2 (*((volatile unsigned int*)(0x42809848UL))) +#define bM4_ADC2_PGAGSR_GAIN3 (*((volatile unsigned int*)(0x4280984CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL0 (*((volatile unsigned int*)(0x42809980UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL1 (*((volatile unsigned int*)(0x42809984UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL2 (*((volatile unsigned int*)(0x42809988UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL3 (*((volatile unsigned int*)(0x4280998CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL4 (*((volatile unsigned int*)(0x42809990UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL5 (*((volatile unsigned int*)(0x42809994UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL6 (*((volatile unsigned int*)(0x42809998UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL7 (*((volatile unsigned int*)(0x4280999CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL8 (*((volatile unsigned int*)(0x428099A0UL))) +#define bM4_ADC2_PGAINSR1_PGAVSSEN (*((volatile unsigned int*)(0x428099C0UL))) +#define bM4_AES_CR_START (*((volatile unsigned int*)(0x42100000UL))) +#define bM4_AES_CR_MODE (*((volatile unsigned int*)(0x42100004UL))) +#define bM4_AOS_INT_SFTTRG_STRG (*((volatile unsigned int*)(0x42210000UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210080UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210084UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210088UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221008CUL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210090UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210094UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210098UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221009CUL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x422100A0UL))) +#define bM4_AOS_DCU1_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x422100F8UL))) +#define bM4_AOS_DCU1_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x422100FCUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210100UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210104UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210108UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221010CUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210110UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210114UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210118UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221011CUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x42210120UL))) +#define bM4_AOS_DCU2_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x42210178UL))) +#define bM4_AOS_DCU2_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x4221017CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210180UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210184UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210188UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221018CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210190UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210194UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210198UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221019CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x422101A0UL))) +#define bM4_AOS_DCU3_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x422101F8UL))) +#define bM4_AOS_DCU3_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x422101FCUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210200UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210204UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210208UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221020CUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210210UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210214UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210218UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221021CUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x42210220UL))) +#define bM4_AOS_DCU4_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x42210278UL))) +#define bM4_AOS_DCU4_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x4221027CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL0 (*((volatile unsigned int*)(0x42210280UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL1 (*((volatile unsigned int*)(0x42210284UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL2 (*((volatile unsigned int*)(0x42210288UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL3 (*((volatile unsigned int*)(0x4221028CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL4 (*((volatile unsigned int*)(0x42210290UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL5 (*((volatile unsigned int*)(0x42210294UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL6 (*((volatile unsigned int*)(0x42210298UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL7 (*((volatile unsigned int*)(0x4221029CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL8 (*((volatile unsigned int*)(0x422102A0UL))) +#define bM4_AOS_DMA1_TRGSEL0_COMTRG_EN0 (*((volatile unsigned int*)(0x422102F8UL))) +#define bM4_AOS_DMA1_TRGSEL0_COMTRG_EN1 (*((volatile unsigned int*)(0x422102FCUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL0 (*((volatile unsigned int*)(0x42210300UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL1 (*((volatile unsigned int*)(0x42210304UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL2 (*((volatile unsigned int*)(0x42210308UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL3 (*((volatile unsigned int*)(0x4221030CUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL4 (*((volatile unsigned int*)(0x42210310UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL5 (*((volatile unsigned int*)(0x42210314UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL6 (*((volatile unsigned int*)(0x42210318UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL7 (*((volatile unsigned int*)(0x4221031CUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL8 (*((volatile unsigned int*)(0x42210320UL))) +#define bM4_AOS_DMA1_TRGSEL1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210378UL))) +#define bM4_AOS_DMA1_TRGSEL1_COMTRG_EN1 (*((volatile unsigned int*)(0x4221037CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL0 (*((volatile unsigned int*)(0x42210380UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL1 (*((volatile unsigned int*)(0x42210384UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL2 (*((volatile unsigned int*)(0x42210388UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL3 (*((volatile unsigned int*)(0x4221038CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL4 (*((volatile unsigned int*)(0x42210390UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL5 (*((volatile unsigned int*)(0x42210394UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL6 (*((volatile unsigned int*)(0x42210398UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL7 (*((volatile unsigned int*)(0x4221039CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL8 (*((volatile unsigned int*)(0x422103A0UL))) +#define bM4_AOS_DMA1_TRGSEL2_COMTRG_EN0 (*((volatile unsigned int*)(0x422103F8UL))) +#define bM4_AOS_DMA1_TRGSEL2_COMTRG_EN1 (*((volatile unsigned int*)(0x422103FCUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL0 (*((volatile unsigned int*)(0x42210400UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL1 (*((volatile unsigned int*)(0x42210404UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL2 (*((volatile unsigned int*)(0x42210408UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL3 (*((volatile unsigned int*)(0x4221040CUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL4 (*((volatile unsigned int*)(0x42210410UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL5 (*((volatile unsigned int*)(0x42210414UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL6 (*((volatile unsigned int*)(0x42210418UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL7 (*((volatile unsigned int*)(0x4221041CUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL8 (*((volatile unsigned int*)(0x42210420UL))) +#define bM4_AOS_DMA1_TRGSEL3_COMTRG_EN0 (*((volatile unsigned int*)(0x42210478UL))) +#define bM4_AOS_DMA1_TRGSEL3_COMTRG_EN1 (*((volatile unsigned int*)(0x4221047CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL0 (*((volatile unsigned int*)(0x42210480UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL1 (*((volatile unsigned int*)(0x42210484UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL2 (*((volatile unsigned int*)(0x42210488UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL3 (*((volatile unsigned int*)(0x4221048CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL4 (*((volatile unsigned int*)(0x42210490UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL5 (*((volatile unsigned int*)(0x42210494UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL6 (*((volatile unsigned int*)(0x42210498UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL7 (*((volatile unsigned int*)(0x4221049CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL8 (*((volatile unsigned int*)(0x422104A0UL))) +#define bM4_AOS_DMA2_TRGSEL0_COMTRG_EN0 (*((volatile unsigned int*)(0x422104F8UL))) +#define bM4_AOS_DMA2_TRGSEL0_COMTRG_EN1 (*((volatile unsigned int*)(0x422104FCUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL0 (*((volatile unsigned int*)(0x42210500UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL1 (*((volatile unsigned int*)(0x42210504UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL2 (*((volatile unsigned int*)(0x42210508UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL3 (*((volatile unsigned int*)(0x4221050CUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL4 (*((volatile unsigned int*)(0x42210510UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL5 (*((volatile unsigned int*)(0x42210514UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL6 (*((volatile unsigned int*)(0x42210518UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL7 (*((volatile unsigned int*)(0x4221051CUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL8 (*((volatile unsigned int*)(0x42210520UL))) +#define bM4_AOS_DMA2_TRGSEL1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210578UL))) +#define bM4_AOS_DMA2_TRGSEL1_COMTRG_EN1 (*((volatile unsigned int*)(0x4221057CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL0 (*((volatile unsigned int*)(0x42210580UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL1 (*((volatile unsigned int*)(0x42210584UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL2 (*((volatile unsigned int*)(0x42210588UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL3 (*((volatile unsigned int*)(0x4221058CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL4 (*((volatile unsigned int*)(0x42210590UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL5 (*((volatile unsigned int*)(0x42210594UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL6 (*((volatile unsigned int*)(0x42210598UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL7 (*((volatile unsigned int*)(0x4221059CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL8 (*((volatile unsigned int*)(0x422105A0UL))) +#define bM4_AOS_DMA2_TRGSEL2_COMTRG_EN0 (*((volatile unsigned int*)(0x422105F8UL))) +#define bM4_AOS_DMA2_TRGSEL2_COMTRG_EN1 (*((volatile unsigned int*)(0x422105FCUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL0 (*((volatile unsigned int*)(0x42210600UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL1 (*((volatile unsigned int*)(0x42210604UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL2 (*((volatile unsigned int*)(0x42210608UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL3 (*((volatile unsigned int*)(0x4221060CUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL4 (*((volatile unsigned int*)(0x42210610UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL5 (*((volatile unsigned int*)(0x42210614UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL6 (*((volatile unsigned int*)(0x42210618UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL7 (*((volatile unsigned int*)(0x4221061CUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL8 (*((volatile unsigned int*)(0x42210620UL))) +#define bM4_AOS_DMA2_TRGSEL3_COMTRG_EN0 (*((volatile unsigned int*)(0x42210678UL))) +#define bM4_AOS_DMA2_TRGSEL3_COMTRG_EN1 (*((volatile unsigned int*)(0x4221067CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL0 (*((volatile unsigned int*)(0x42210680UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL1 (*((volatile unsigned int*)(0x42210684UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL2 (*((volatile unsigned int*)(0x42210688UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL3 (*((volatile unsigned int*)(0x4221068CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL4 (*((volatile unsigned int*)(0x42210690UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL5 (*((volatile unsigned int*)(0x42210694UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL6 (*((volatile unsigned int*)(0x42210698UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL7 (*((volatile unsigned int*)(0x4221069CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL8 (*((volatile unsigned int*)(0x422106A0UL))) +#define bM4_AOS_DMA_TRGSELRC_COMTRG_EN0 (*((volatile unsigned int*)(0x422106F8UL))) +#define bM4_AOS_DMA_TRGSELRC_COMTRG_EN1 (*((volatile unsigned int*)(0x422106FCUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL0 (*((volatile unsigned int*)(0x42210700UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL1 (*((volatile unsigned int*)(0x42210704UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL2 (*((volatile unsigned int*)(0x42210708UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL3 (*((volatile unsigned int*)(0x4221070CUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL4 (*((volatile unsigned int*)(0x42210710UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL5 (*((volatile unsigned int*)(0x42210714UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL6 (*((volatile unsigned int*)(0x42210718UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL7 (*((volatile unsigned int*)(0x4221071CUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL8 (*((volatile unsigned int*)(0x42210720UL))) +#define bM4_AOS_TMR6_HTSSR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210778UL))) +#define bM4_AOS_TMR6_HTSSR1_COMTRG_EN1 (*((volatile unsigned int*)(0x4221077CUL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL0 (*((volatile unsigned int*)(0x42210780UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL1 (*((volatile unsigned int*)(0x42210784UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL2 (*((volatile unsigned int*)(0x42210788UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL3 (*((volatile unsigned int*)(0x4221078CUL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL4 (*((volatile unsigned int*)(0x42210790UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL5 (*((volatile unsigned int*)(0x42210794UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL6 (*((volatile unsigned int*)(0x42210798UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL7 (*((volatile unsigned int*)(0x4221079CUL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL8 (*((volatile unsigned int*)(0x422107A0UL))) +#define bM4_AOS_TMR6_HTSSR2_COMTRG_EN0 (*((volatile unsigned int*)(0x422107F8UL))) +#define bM4_AOS_TMR6_HTSSR2_COMTRG_EN1 (*((volatile unsigned int*)(0x422107FCUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL0 (*((volatile unsigned int*)(0x42210800UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL1 (*((volatile unsigned int*)(0x42210804UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL2 (*((volatile unsigned int*)(0x42210808UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL3 (*((volatile unsigned int*)(0x4221080CUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL4 (*((volatile unsigned int*)(0x42210810UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL5 (*((volatile unsigned int*)(0x42210814UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL6 (*((volatile unsigned int*)(0x42210818UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL7 (*((volatile unsigned int*)(0x4221081CUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL8 (*((volatile unsigned int*)(0x42210820UL))) +#define bM4_AOS_TMR0_HTSSR_COMTRG_EN0 (*((volatile unsigned int*)(0x42210878UL))) +#define bM4_AOS_TMR0_HTSSR_COMTRG_EN1 (*((volatile unsigned int*)(0x4221087CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL0 (*((volatile unsigned int*)(0x42210880UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL1 (*((volatile unsigned int*)(0x42210884UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL2 (*((volatile unsigned int*)(0x42210888UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL3 (*((volatile unsigned int*)(0x4221088CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL4 (*((volatile unsigned int*)(0x42210890UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL5 (*((volatile unsigned int*)(0x42210894UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL6 (*((volatile unsigned int*)(0x42210898UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL7 (*((volatile unsigned int*)(0x4221089CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL8 (*((volatile unsigned int*)(0x422108A0UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_COMTRG_EN0 (*((volatile unsigned int*)(0x422108F8UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_COMTRG_EN1 (*((volatile unsigned int*)(0x422108FCUL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL0 (*((volatile unsigned int*)(0x42210900UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL1 (*((volatile unsigned int*)(0x42210904UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL2 (*((volatile unsigned int*)(0x42210908UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL3 (*((volatile unsigned int*)(0x4221090CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL4 (*((volatile unsigned int*)(0x42210910UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL5 (*((volatile unsigned int*)(0x42210914UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL6 (*((volatile unsigned int*)(0x42210918UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL7 (*((volatile unsigned int*)(0x4221091CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL8 (*((volatile unsigned int*)(0x42210920UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_COMTRG_EN0 (*((volatile unsigned int*)(0x42210978UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_COMTRG_EN1 (*((volatile unsigned int*)(0x4221097CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL0 (*((volatile unsigned int*)(0x42210980UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL1 (*((volatile unsigned int*)(0x42210984UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL2 (*((volatile unsigned int*)(0x42210988UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL3 (*((volatile unsigned int*)(0x4221098CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL4 (*((volatile unsigned int*)(0x42210990UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL5 (*((volatile unsigned int*)(0x42210994UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL6 (*((volatile unsigned int*)(0x42210998UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL7 (*((volatile unsigned int*)(0x4221099CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL8 (*((volatile unsigned int*)(0x422109A0UL))) +#define bM4_AOS_TMRA_HTSSR0_COMTRG_EN0 (*((volatile unsigned int*)(0x422109F8UL))) +#define bM4_AOS_TMRA_HTSSR0_COMTRG_EN1 (*((volatile unsigned int*)(0x422109FCUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL0 (*((volatile unsigned int*)(0x42210A00UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL1 (*((volatile unsigned int*)(0x42210A04UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL2 (*((volatile unsigned int*)(0x42210A08UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL3 (*((volatile unsigned int*)(0x42210A0CUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL4 (*((volatile unsigned int*)(0x42210A10UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL5 (*((volatile unsigned int*)(0x42210A14UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL6 (*((volatile unsigned int*)(0x42210A18UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL7 (*((volatile unsigned int*)(0x42210A1CUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL8 (*((volatile unsigned int*)(0x42210A20UL))) +#define bM4_AOS_TMRA_HTSSR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210A78UL))) +#define bM4_AOS_TMRA_HTSSR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210A7CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL0 (*((volatile unsigned int*)(0x42210A80UL))) +#define bM4_AOS_OTS_TRG_TRGSEL1 (*((volatile unsigned int*)(0x42210A84UL))) +#define bM4_AOS_OTS_TRG_TRGSEL2 (*((volatile unsigned int*)(0x42210A88UL))) +#define bM4_AOS_OTS_TRG_TRGSEL3 (*((volatile unsigned int*)(0x42210A8CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL4 (*((volatile unsigned int*)(0x42210A90UL))) +#define bM4_AOS_OTS_TRG_TRGSEL5 (*((volatile unsigned int*)(0x42210A94UL))) +#define bM4_AOS_OTS_TRG_TRGSEL6 (*((volatile unsigned int*)(0x42210A98UL))) +#define bM4_AOS_OTS_TRG_TRGSEL7 (*((volatile unsigned int*)(0x42210A9CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL8 (*((volatile unsigned int*)(0x42210AA0UL))) +#define bM4_AOS_OTS_TRG_COMTRG_EN0 (*((volatile unsigned int*)(0x42210AF8UL))) +#define bM4_AOS_OTS_TRG_COMTRG_EN1 (*((volatile unsigned int*)(0x42210AFCUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL0 (*((volatile unsigned int*)(0x42210B00UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL1 (*((volatile unsigned int*)(0x42210B04UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL2 (*((volatile unsigned int*)(0x42210B08UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL3 (*((volatile unsigned int*)(0x42210B0CUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL4 (*((volatile unsigned int*)(0x42210B10UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL5 (*((volatile unsigned int*)(0x42210B14UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL6 (*((volatile unsigned int*)(0x42210B18UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL7 (*((volatile unsigned int*)(0x42210B1CUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL8 (*((volatile unsigned int*)(0x42210B20UL))) +#define bM4_AOS_ADC1_ITRGSELR0_COMTRG_EN0 (*((volatile unsigned int*)(0x42210B78UL))) +#define bM4_AOS_ADC1_ITRGSELR0_COMTRG_EN1 (*((volatile unsigned int*)(0x42210B7CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL0 (*((volatile unsigned int*)(0x42210B80UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL1 (*((volatile unsigned int*)(0x42210B84UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL2 (*((volatile unsigned int*)(0x42210B88UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL3 (*((volatile unsigned int*)(0x42210B8CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL4 (*((volatile unsigned int*)(0x42210B90UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL5 (*((volatile unsigned int*)(0x42210B94UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL6 (*((volatile unsigned int*)(0x42210B98UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL7 (*((volatile unsigned int*)(0x42210B9CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL8 (*((volatile unsigned int*)(0x42210BA0UL))) +#define bM4_AOS_ADC1_ITRGSELR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210BF8UL))) +#define bM4_AOS_ADC1_ITRGSELR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210BFCUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL0 (*((volatile unsigned int*)(0x42210C00UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL1 (*((volatile unsigned int*)(0x42210C04UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL2 (*((volatile unsigned int*)(0x42210C08UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL3 (*((volatile unsigned int*)(0x42210C0CUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL4 (*((volatile unsigned int*)(0x42210C10UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL5 (*((volatile unsigned int*)(0x42210C14UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL6 (*((volatile unsigned int*)(0x42210C18UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL7 (*((volatile unsigned int*)(0x42210C1CUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL8 (*((volatile unsigned int*)(0x42210C20UL))) +#define bM4_AOS_ADC2_ITRGSELR0_COMTRG_EN0 (*((volatile unsigned int*)(0x42210C78UL))) +#define bM4_AOS_ADC2_ITRGSELR0_COMTRG_EN1 (*((volatile unsigned int*)(0x42210C7CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL0 (*((volatile unsigned int*)(0x42210C80UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL1 (*((volatile unsigned int*)(0x42210C84UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL2 (*((volatile unsigned int*)(0x42210C88UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL3 (*((volatile unsigned int*)(0x42210C8CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL4 (*((volatile unsigned int*)(0x42210C90UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL5 (*((volatile unsigned int*)(0x42210C94UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL6 (*((volatile unsigned int*)(0x42210C98UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL7 (*((volatile unsigned int*)(0x42210C9CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL8 (*((volatile unsigned int*)(0x42210CA0UL))) +#define bM4_AOS_ADC2_ITRGSELR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210CF8UL))) +#define bM4_AOS_ADC2_ITRGSELR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210CFCUL))) +#define bM4_AOS_COMTRG1_TRGSEL0 (*((volatile unsigned int*)(0x42210D00UL))) +#define bM4_AOS_COMTRG1_TRGSEL1 (*((volatile unsigned int*)(0x42210D04UL))) +#define bM4_AOS_COMTRG1_TRGSEL2 (*((volatile unsigned int*)(0x42210D08UL))) +#define bM4_AOS_COMTRG1_TRGSEL3 (*((volatile unsigned int*)(0x42210D0CUL))) +#define bM4_AOS_COMTRG1_TRGSEL4 (*((volatile unsigned int*)(0x42210D10UL))) +#define bM4_AOS_COMTRG1_TRGSEL5 (*((volatile unsigned int*)(0x42210D14UL))) +#define bM4_AOS_COMTRG1_TRGSEL6 (*((volatile unsigned int*)(0x42210D18UL))) +#define bM4_AOS_COMTRG1_TRGSEL7 (*((volatile unsigned int*)(0x42210D1CUL))) +#define bM4_AOS_COMTRG1_TRGSEL8 (*((volatile unsigned int*)(0x42210D20UL))) +#define bM4_AOS_COMTRG2_TRGSEL0 (*((volatile unsigned int*)(0x42210D80UL))) +#define bM4_AOS_COMTRG2_TRGSEL1 (*((volatile unsigned int*)(0x42210D84UL))) +#define bM4_AOS_COMTRG2_TRGSEL2 (*((volatile unsigned int*)(0x42210D88UL))) +#define bM4_AOS_COMTRG2_TRGSEL3 (*((volatile unsigned int*)(0x42210D8CUL))) +#define bM4_AOS_COMTRG2_TRGSEL4 (*((volatile unsigned int*)(0x42210D90UL))) +#define bM4_AOS_COMTRG2_TRGSEL5 (*((volatile unsigned int*)(0x42210D94UL))) +#define bM4_AOS_COMTRG2_TRGSEL6 (*((volatile unsigned int*)(0x42210D98UL))) +#define bM4_AOS_COMTRG2_TRGSEL7 (*((volatile unsigned int*)(0x42210D9CUL))) +#define bM4_AOS_COMTRG2_TRGSEL8 (*((volatile unsigned int*)(0x42210DA0UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR00 (*((volatile unsigned int*)(0x42212000UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR01 (*((volatile unsigned int*)(0x42212004UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR02 (*((volatile unsigned int*)(0x42212008UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR03 (*((volatile unsigned int*)(0x4221200CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR04 (*((volatile unsigned int*)(0x42212010UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR05 (*((volatile unsigned int*)(0x42212014UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR06 (*((volatile unsigned int*)(0x42212018UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR07 (*((volatile unsigned int*)(0x4221201CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR08 (*((volatile unsigned int*)(0x42212020UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR09 (*((volatile unsigned int*)(0x42212024UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR10 (*((volatile unsigned int*)(0x42212028UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR11 (*((volatile unsigned int*)(0x4221202CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR12 (*((volatile unsigned int*)(0x42212030UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR13 (*((volatile unsigned int*)(0x42212034UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR14 (*((volatile unsigned int*)(0x42212038UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR15 (*((volatile unsigned int*)(0x4221203CUL))) +#define bM4_AOS_PEVNTIDR1_PIN00 (*((volatile unsigned int*)(0x42212080UL))) +#define bM4_AOS_PEVNTIDR1_PIN01 (*((volatile unsigned int*)(0x42212084UL))) +#define bM4_AOS_PEVNTIDR1_PIN02 (*((volatile unsigned int*)(0x42212088UL))) +#define bM4_AOS_PEVNTIDR1_PIN03 (*((volatile unsigned int*)(0x4221208CUL))) +#define bM4_AOS_PEVNTIDR1_PIN04 (*((volatile unsigned int*)(0x42212090UL))) +#define bM4_AOS_PEVNTIDR1_PIN05 (*((volatile unsigned int*)(0x42212094UL))) +#define bM4_AOS_PEVNTIDR1_PIN06 (*((volatile unsigned int*)(0x42212098UL))) +#define bM4_AOS_PEVNTIDR1_PIN07 (*((volatile unsigned int*)(0x4221209CUL))) +#define bM4_AOS_PEVNTIDR1_PIN08 (*((volatile unsigned int*)(0x422120A0UL))) +#define bM4_AOS_PEVNTIDR1_PIN09 (*((volatile unsigned int*)(0x422120A4UL))) +#define bM4_AOS_PEVNTIDR1_PIN10 (*((volatile unsigned int*)(0x422120A8UL))) +#define bM4_AOS_PEVNTIDR1_PIN11 (*((volatile unsigned int*)(0x422120ACUL))) +#define bM4_AOS_PEVNTIDR1_PIN12 (*((volatile unsigned int*)(0x422120B0UL))) +#define bM4_AOS_PEVNTIDR1_PIN13 (*((volatile unsigned int*)(0x422120B4UL))) +#define bM4_AOS_PEVNTIDR1_PIN14 (*((volatile unsigned int*)(0x422120B8UL))) +#define bM4_AOS_PEVNTIDR1_PIN15 (*((volatile unsigned int*)(0x422120BCUL))) +#define bM4_AOS_PEVNTODR1_POUT00 (*((volatile unsigned int*)(0x42212100UL))) +#define bM4_AOS_PEVNTODR1_POUT01 (*((volatile unsigned int*)(0x42212104UL))) +#define bM4_AOS_PEVNTODR1_POUT02 (*((volatile unsigned int*)(0x42212108UL))) +#define bM4_AOS_PEVNTODR1_POUT03 (*((volatile unsigned int*)(0x4221210CUL))) +#define bM4_AOS_PEVNTODR1_POUT04 (*((volatile unsigned int*)(0x42212110UL))) +#define bM4_AOS_PEVNTODR1_POUT05 (*((volatile unsigned int*)(0x42212114UL))) +#define bM4_AOS_PEVNTODR1_POUT06 (*((volatile unsigned int*)(0x42212118UL))) +#define bM4_AOS_PEVNTODR1_POUT07 (*((volatile unsigned int*)(0x4221211CUL))) +#define bM4_AOS_PEVNTODR1_POUT08 (*((volatile unsigned int*)(0x42212120UL))) +#define bM4_AOS_PEVNTODR1_POUT09 (*((volatile unsigned int*)(0x42212124UL))) +#define bM4_AOS_PEVNTODR1_POUT10 (*((volatile unsigned int*)(0x42212128UL))) +#define bM4_AOS_PEVNTODR1_POUT11 (*((volatile unsigned int*)(0x4221212CUL))) +#define bM4_AOS_PEVNTODR1_POUT12 (*((volatile unsigned int*)(0x42212130UL))) +#define bM4_AOS_PEVNTODR1_POUT13 (*((volatile unsigned int*)(0x42212134UL))) +#define bM4_AOS_PEVNTODR1_POUT14 (*((volatile unsigned int*)(0x42212138UL))) +#define bM4_AOS_PEVNTODR1_POUT15 (*((volatile unsigned int*)(0x4221213CUL))) +#define bM4_AOS_PEVNTORR1_POR00 (*((volatile unsigned int*)(0x42212180UL))) +#define bM4_AOS_PEVNTORR1_POR01 (*((volatile unsigned int*)(0x42212184UL))) +#define bM4_AOS_PEVNTORR1_POR02 (*((volatile unsigned int*)(0x42212188UL))) +#define bM4_AOS_PEVNTORR1_POR03 (*((volatile unsigned int*)(0x4221218CUL))) +#define bM4_AOS_PEVNTORR1_POR04 (*((volatile unsigned int*)(0x42212190UL))) +#define bM4_AOS_PEVNTORR1_POR05 (*((volatile unsigned int*)(0x42212194UL))) +#define bM4_AOS_PEVNTORR1_POR06 (*((volatile unsigned int*)(0x42212198UL))) +#define bM4_AOS_PEVNTORR1_POR07 (*((volatile unsigned int*)(0x4221219CUL))) +#define bM4_AOS_PEVNTORR1_POR08 (*((volatile unsigned int*)(0x422121A0UL))) +#define bM4_AOS_PEVNTORR1_POR09 (*((volatile unsigned int*)(0x422121A4UL))) +#define bM4_AOS_PEVNTORR1_POR10 (*((volatile unsigned int*)(0x422121A8UL))) +#define bM4_AOS_PEVNTORR1_POR11 (*((volatile unsigned int*)(0x422121ACUL))) +#define bM4_AOS_PEVNTORR1_POR12 (*((volatile unsigned int*)(0x422121B0UL))) +#define bM4_AOS_PEVNTORR1_POR13 (*((volatile unsigned int*)(0x422121B4UL))) +#define bM4_AOS_PEVNTORR1_POR14 (*((volatile unsigned int*)(0x422121B8UL))) +#define bM4_AOS_PEVNTORR1_POR15 (*((volatile unsigned int*)(0x422121BCUL))) +#define bM4_AOS_PEVNTOSR1_POS00 (*((volatile unsigned int*)(0x42212200UL))) +#define bM4_AOS_PEVNTOSR1_POS01 (*((volatile unsigned int*)(0x42212204UL))) +#define bM4_AOS_PEVNTOSR1_POS02 (*((volatile unsigned int*)(0x42212208UL))) +#define bM4_AOS_PEVNTOSR1_POS03 (*((volatile unsigned int*)(0x4221220CUL))) +#define bM4_AOS_PEVNTOSR1_POS04 (*((volatile unsigned int*)(0x42212210UL))) +#define bM4_AOS_PEVNTOSR1_POS05 (*((volatile unsigned int*)(0x42212214UL))) +#define bM4_AOS_PEVNTOSR1_POS06 (*((volatile unsigned int*)(0x42212218UL))) +#define bM4_AOS_PEVNTOSR1_POS07 (*((volatile unsigned int*)(0x4221221CUL))) +#define bM4_AOS_PEVNTOSR1_POS08 (*((volatile unsigned int*)(0x42212220UL))) +#define bM4_AOS_PEVNTOSR1_POS09 (*((volatile unsigned int*)(0x42212224UL))) +#define bM4_AOS_PEVNTOSR1_POS10 (*((volatile unsigned int*)(0x42212228UL))) +#define bM4_AOS_PEVNTOSR1_POS11 (*((volatile unsigned int*)(0x4221222CUL))) +#define bM4_AOS_PEVNTOSR1_POS12 (*((volatile unsigned int*)(0x42212230UL))) +#define bM4_AOS_PEVNTOSR1_POS13 (*((volatile unsigned int*)(0x42212234UL))) +#define bM4_AOS_PEVNTOSR1_POS14 (*((volatile unsigned int*)(0x42212238UL))) +#define bM4_AOS_PEVNTOSR1_POS15 (*((volatile unsigned int*)(0x4221223CUL))) +#define bM4_AOS_PEVNTRISR1_RIS00 (*((volatile unsigned int*)(0x42212280UL))) +#define bM4_AOS_PEVNTRISR1_RIS01 (*((volatile unsigned int*)(0x42212284UL))) +#define bM4_AOS_PEVNTRISR1_RIS02 (*((volatile unsigned int*)(0x42212288UL))) +#define bM4_AOS_PEVNTRISR1_RIS03 (*((volatile unsigned int*)(0x4221228CUL))) +#define bM4_AOS_PEVNTRISR1_RIS04 (*((volatile unsigned int*)(0x42212290UL))) +#define bM4_AOS_PEVNTRISR1_RIS05 (*((volatile unsigned int*)(0x42212294UL))) +#define bM4_AOS_PEVNTRISR1_RIS06 (*((volatile unsigned int*)(0x42212298UL))) +#define bM4_AOS_PEVNTRISR1_RIS07 (*((volatile unsigned int*)(0x4221229CUL))) +#define bM4_AOS_PEVNTRISR1_RIS08 (*((volatile unsigned int*)(0x422122A0UL))) +#define bM4_AOS_PEVNTRISR1_RIS09 (*((volatile unsigned int*)(0x422122A4UL))) +#define bM4_AOS_PEVNTRISR1_RIS10 (*((volatile unsigned int*)(0x422122A8UL))) +#define bM4_AOS_PEVNTRISR1_RIS11 (*((volatile unsigned int*)(0x422122ACUL))) +#define bM4_AOS_PEVNTRISR1_RIS12 (*((volatile unsigned int*)(0x422122B0UL))) +#define bM4_AOS_PEVNTRISR1_RIS13 (*((volatile unsigned int*)(0x422122B4UL))) +#define bM4_AOS_PEVNTRISR1_RIS14 (*((volatile unsigned int*)(0x422122B8UL))) +#define bM4_AOS_PEVNTRISR1_RIS15 (*((volatile unsigned int*)(0x422122BCUL))) +#define bM4_AOS_PEVNTFAL1_FAL00 (*((volatile unsigned int*)(0x42212300UL))) +#define bM4_AOS_PEVNTFAL1_FAL01 (*((volatile unsigned int*)(0x42212304UL))) +#define bM4_AOS_PEVNTFAL1_FAL02 (*((volatile unsigned int*)(0x42212308UL))) +#define bM4_AOS_PEVNTFAL1_FAL03 (*((volatile unsigned int*)(0x4221230CUL))) +#define bM4_AOS_PEVNTFAL1_FAL04 (*((volatile unsigned int*)(0x42212310UL))) +#define bM4_AOS_PEVNTFAL1_FAL05 (*((volatile unsigned int*)(0x42212314UL))) +#define bM4_AOS_PEVNTFAL1_FAL06 (*((volatile unsigned int*)(0x42212318UL))) +#define bM4_AOS_PEVNTFAL1_FAL07 (*((volatile unsigned int*)(0x4221231CUL))) +#define bM4_AOS_PEVNTFAL1_FAL08 (*((volatile unsigned int*)(0x42212320UL))) +#define bM4_AOS_PEVNTFAL1_FAL09 (*((volatile unsigned int*)(0x42212324UL))) +#define bM4_AOS_PEVNTFAL1_FAL10 (*((volatile unsigned int*)(0x42212328UL))) +#define bM4_AOS_PEVNTFAL1_FAL11 (*((volatile unsigned int*)(0x4221232CUL))) +#define bM4_AOS_PEVNTFAL1_FAL12 (*((volatile unsigned int*)(0x42212330UL))) +#define bM4_AOS_PEVNTFAL1_FAL13 (*((volatile unsigned int*)(0x42212334UL))) +#define bM4_AOS_PEVNTFAL1_FAL14 (*((volatile unsigned int*)(0x42212338UL))) +#define bM4_AOS_PEVNTFAL1_FAL15 (*((volatile unsigned int*)(0x4221233CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR00 (*((volatile unsigned int*)(0x42212380UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR01 (*((volatile unsigned int*)(0x42212384UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR02 (*((volatile unsigned int*)(0x42212388UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR03 (*((volatile unsigned int*)(0x4221238CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR04 (*((volatile unsigned int*)(0x42212390UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR05 (*((volatile unsigned int*)(0x42212394UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR06 (*((volatile unsigned int*)(0x42212398UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR07 (*((volatile unsigned int*)(0x4221239CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR08 (*((volatile unsigned int*)(0x422123A0UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR09 (*((volatile unsigned int*)(0x422123A4UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR10 (*((volatile unsigned int*)(0x422123A8UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR11 (*((volatile unsigned int*)(0x422123ACUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR12 (*((volatile unsigned int*)(0x422123B0UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR13 (*((volatile unsigned int*)(0x422123B4UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR14 (*((volatile unsigned int*)(0x422123B8UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR15 (*((volatile unsigned int*)(0x422123BCUL))) +#define bM4_AOS_PEVNTIDR2_PIN00 (*((volatile unsigned int*)(0x42212400UL))) +#define bM4_AOS_PEVNTIDR2_PIN01 (*((volatile unsigned int*)(0x42212404UL))) +#define bM4_AOS_PEVNTIDR2_PIN02 (*((volatile unsigned int*)(0x42212408UL))) +#define bM4_AOS_PEVNTIDR2_PIN03 (*((volatile unsigned int*)(0x4221240CUL))) +#define bM4_AOS_PEVNTIDR2_PIN04 (*((volatile unsigned int*)(0x42212410UL))) +#define bM4_AOS_PEVNTIDR2_PIN05 (*((volatile unsigned int*)(0x42212414UL))) +#define bM4_AOS_PEVNTIDR2_PIN06 (*((volatile unsigned int*)(0x42212418UL))) +#define bM4_AOS_PEVNTIDR2_PIN07 (*((volatile unsigned int*)(0x4221241CUL))) +#define bM4_AOS_PEVNTIDR2_PIN08 (*((volatile unsigned int*)(0x42212420UL))) +#define bM4_AOS_PEVNTIDR2_PIN09 (*((volatile unsigned int*)(0x42212424UL))) +#define bM4_AOS_PEVNTIDR2_PIN10 (*((volatile unsigned int*)(0x42212428UL))) +#define bM4_AOS_PEVNTIDR2_PIN11 (*((volatile unsigned int*)(0x4221242CUL))) +#define bM4_AOS_PEVNTIDR2_PIN12 (*((volatile unsigned int*)(0x42212430UL))) +#define bM4_AOS_PEVNTIDR2_PIN13 (*((volatile unsigned int*)(0x42212434UL))) +#define bM4_AOS_PEVNTIDR2_PIN14 (*((volatile unsigned int*)(0x42212438UL))) +#define bM4_AOS_PEVNTIDR2_PIN15 (*((volatile unsigned int*)(0x4221243CUL))) +#define bM4_AOS_PEVNTODR2_POUT00 (*((volatile unsigned int*)(0x42212480UL))) +#define bM4_AOS_PEVNTODR2_POUT01 (*((volatile unsigned int*)(0x42212484UL))) +#define bM4_AOS_PEVNTODR2_POUT02 (*((volatile unsigned int*)(0x42212488UL))) +#define bM4_AOS_PEVNTODR2_POUT03 (*((volatile unsigned int*)(0x4221248CUL))) +#define bM4_AOS_PEVNTODR2_POUT04 (*((volatile unsigned int*)(0x42212490UL))) +#define bM4_AOS_PEVNTODR2_POUT05 (*((volatile unsigned int*)(0x42212494UL))) +#define bM4_AOS_PEVNTODR2_POUT06 (*((volatile unsigned int*)(0x42212498UL))) +#define bM4_AOS_PEVNTODR2_POUT07 (*((volatile unsigned int*)(0x4221249CUL))) +#define bM4_AOS_PEVNTODR2_POUT08 (*((volatile unsigned int*)(0x422124A0UL))) +#define bM4_AOS_PEVNTODR2_POUT09 (*((volatile unsigned int*)(0x422124A4UL))) +#define bM4_AOS_PEVNTODR2_POUT10 (*((volatile unsigned int*)(0x422124A8UL))) +#define bM4_AOS_PEVNTODR2_POUT11 (*((volatile unsigned int*)(0x422124ACUL))) +#define bM4_AOS_PEVNTODR2_POUT12 (*((volatile unsigned int*)(0x422124B0UL))) +#define bM4_AOS_PEVNTODR2_POUT13 (*((volatile unsigned int*)(0x422124B4UL))) +#define bM4_AOS_PEVNTODR2_POUT14 (*((volatile unsigned int*)(0x422124B8UL))) +#define bM4_AOS_PEVNTODR2_POUT15 (*((volatile unsigned int*)(0x422124BCUL))) +#define bM4_AOS_PEVNTORR2_POR00 (*((volatile unsigned int*)(0x42212500UL))) +#define bM4_AOS_PEVNTORR2_POR01 (*((volatile unsigned int*)(0x42212504UL))) +#define bM4_AOS_PEVNTORR2_POR02 (*((volatile unsigned int*)(0x42212508UL))) +#define bM4_AOS_PEVNTORR2_POR03 (*((volatile unsigned int*)(0x4221250CUL))) +#define bM4_AOS_PEVNTORR2_POR04 (*((volatile unsigned int*)(0x42212510UL))) +#define bM4_AOS_PEVNTORR2_POR05 (*((volatile unsigned int*)(0x42212514UL))) +#define bM4_AOS_PEVNTORR2_POR06 (*((volatile unsigned int*)(0x42212518UL))) +#define bM4_AOS_PEVNTORR2_POR07 (*((volatile unsigned int*)(0x4221251CUL))) +#define bM4_AOS_PEVNTORR2_POR08 (*((volatile unsigned int*)(0x42212520UL))) +#define bM4_AOS_PEVNTORR2_POR09 (*((volatile unsigned int*)(0x42212524UL))) +#define bM4_AOS_PEVNTORR2_POR10 (*((volatile unsigned int*)(0x42212528UL))) +#define bM4_AOS_PEVNTORR2_POR11 (*((volatile unsigned int*)(0x4221252CUL))) +#define bM4_AOS_PEVNTORR2_POR12 (*((volatile unsigned int*)(0x42212530UL))) +#define bM4_AOS_PEVNTORR2_POR13 (*((volatile unsigned int*)(0x42212534UL))) +#define bM4_AOS_PEVNTORR2_POR14 (*((volatile unsigned int*)(0x42212538UL))) +#define bM4_AOS_PEVNTORR2_POR15 (*((volatile unsigned int*)(0x4221253CUL))) +#define bM4_AOS_PEVNTOSR2_POS00 (*((volatile unsigned int*)(0x42212580UL))) +#define bM4_AOS_PEVNTOSR2_POS01 (*((volatile unsigned int*)(0x42212584UL))) +#define bM4_AOS_PEVNTOSR2_POS02 (*((volatile unsigned int*)(0x42212588UL))) +#define bM4_AOS_PEVNTOSR2_POS03 (*((volatile unsigned int*)(0x4221258CUL))) +#define bM4_AOS_PEVNTOSR2_POS04 (*((volatile unsigned int*)(0x42212590UL))) +#define bM4_AOS_PEVNTOSR2_POS05 (*((volatile unsigned int*)(0x42212594UL))) +#define bM4_AOS_PEVNTOSR2_POS06 (*((volatile unsigned int*)(0x42212598UL))) +#define bM4_AOS_PEVNTOSR2_POS07 (*((volatile unsigned int*)(0x4221259CUL))) +#define bM4_AOS_PEVNTOSR2_POS08 (*((volatile unsigned int*)(0x422125A0UL))) +#define bM4_AOS_PEVNTOSR2_POS09 (*((volatile unsigned int*)(0x422125A4UL))) +#define bM4_AOS_PEVNTOSR2_POS10 (*((volatile unsigned int*)(0x422125A8UL))) +#define bM4_AOS_PEVNTOSR2_POS11 (*((volatile unsigned int*)(0x422125ACUL))) +#define bM4_AOS_PEVNTOSR2_POS12 (*((volatile unsigned int*)(0x422125B0UL))) +#define bM4_AOS_PEVNTOSR2_POS13 (*((volatile unsigned int*)(0x422125B4UL))) +#define bM4_AOS_PEVNTOSR2_POS14 (*((volatile unsigned int*)(0x422125B8UL))) +#define bM4_AOS_PEVNTOSR2_POS15 (*((volatile unsigned int*)(0x422125BCUL))) +#define bM4_AOS_PEVNTRISR2_RIS00 (*((volatile unsigned int*)(0x42212600UL))) +#define bM4_AOS_PEVNTRISR2_RIS01 (*((volatile unsigned int*)(0x42212604UL))) +#define bM4_AOS_PEVNTRISR2_RIS02 (*((volatile unsigned int*)(0x42212608UL))) +#define bM4_AOS_PEVNTRISR2_RIS03 (*((volatile unsigned int*)(0x4221260CUL))) +#define bM4_AOS_PEVNTRISR2_RIS04 (*((volatile unsigned int*)(0x42212610UL))) +#define bM4_AOS_PEVNTRISR2_RIS05 (*((volatile unsigned int*)(0x42212614UL))) +#define bM4_AOS_PEVNTRISR2_RIS06 (*((volatile unsigned int*)(0x42212618UL))) +#define bM4_AOS_PEVNTRISR2_RIS07 (*((volatile unsigned int*)(0x4221261CUL))) +#define bM4_AOS_PEVNTRISR2_RIS08 (*((volatile unsigned int*)(0x42212620UL))) +#define bM4_AOS_PEVNTRISR2_RIS09 (*((volatile unsigned int*)(0x42212624UL))) +#define bM4_AOS_PEVNTRISR2_RIS10 (*((volatile unsigned int*)(0x42212628UL))) +#define bM4_AOS_PEVNTRISR2_RIS11 (*((volatile unsigned int*)(0x4221262CUL))) +#define bM4_AOS_PEVNTRISR2_RIS12 (*((volatile unsigned int*)(0x42212630UL))) +#define bM4_AOS_PEVNTRISR2_RIS13 (*((volatile unsigned int*)(0x42212634UL))) +#define bM4_AOS_PEVNTRISR2_RIS14 (*((volatile unsigned int*)(0x42212638UL))) +#define bM4_AOS_PEVNTRISR2_RIS15 (*((volatile unsigned int*)(0x4221263CUL))) +#define bM4_AOS_PEVNTFAL2_FAL00 (*((volatile unsigned int*)(0x42212680UL))) +#define bM4_AOS_PEVNTFAL2_FAL01 (*((volatile unsigned int*)(0x42212684UL))) +#define bM4_AOS_PEVNTFAL2_FAL02 (*((volatile unsigned int*)(0x42212688UL))) +#define bM4_AOS_PEVNTFAL2_FAL03 (*((volatile unsigned int*)(0x4221268CUL))) +#define bM4_AOS_PEVNTFAL2_FAL04 (*((volatile unsigned int*)(0x42212690UL))) +#define bM4_AOS_PEVNTFAL2_FAL05 (*((volatile unsigned int*)(0x42212694UL))) +#define bM4_AOS_PEVNTFAL2_FAL06 (*((volatile unsigned int*)(0x42212698UL))) +#define bM4_AOS_PEVNTFAL2_FAL07 (*((volatile unsigned int*)(0x4221269CUL))) +#define bM4_AOS_PEVNTFAL2_FAL08 (*((volatile unsigned int*)(0x422126A0UL))) +#define bM4_AOS_PEVNTFAL2_FAL09 (*((volatile unsigned int*)(0x422126A4UL))) +#define bM4_AOS_PEVNTFAL2_FAL10 (*((volatile unsigned int*)(0x422126A8UL))) +#define bM4_AOS_PEVNTFAL2_FAL11 (*((volatile unsigned int*)(0x422126ACUL))) +#define bM4_AOS_PEVNTFAL2_FAL12 (*((volatile unsigned int*)(0x422126B0UL))) +#define bM4_AOS_PEVNTFAL2_FAL13 (*((volatile unsigned int*)(0x422126B4UL))) +#define bM4_AOS_PEVNTFAL2_FAL14 (*((volatile unsigned int*)(0x422126B8UL))) +#define bM4_AOS_PEVNTFAL2_FAL15 (*((volatile unsigned int*)(0x422126BCUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR00 (*((volatile unsigned int*)(0x42212700UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR01 (*((volatile unsigned int*)(0x42212704UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR02 (*((volatile unsigned int*)(0x42212708UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR03 (*((volatile unsigned int*)(0x4221270CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR04 (*((volatile unsigned int*)(0x42212710UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR05 (*((volatile unsigned int*)(0x42212714UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR06 (*((volatile unsigned int*)(0x42212718UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR07 (*((volatile unsigned int*)(0x4221271CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR08 (*((volatile unsigned int*)(0x42212720UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR09 (*((volatile unsigned int*)(0x42212724UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR10 (*((volatile unsigned int*)(0x42212728UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR11 (*((volatile unsigned int*)(0x4221272CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR12 (*((volatile unsigned int*)(0x42212730UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR13 (*((volatile unsigned int*)(0x42212734UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR14 (*((volatile unsigned int*)(0x42212738UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR15 (*((volatile unsigned int*)(0x4221273CUL))) +#define bM4_AOS_PEVNTIDR3_PIN00 (*((volatile unsigned int*)(0x42212780UL))) +#define bM4_AOS_PEVNTIDR3_PIN01 (*((volatile unsigned int*)(0x42212784UL))) +#define bM4_AOS_PEVNTIDR3_PIN02 (*((volatile unsigned int*)(0x42212788UL))) +#define bM4_AOS_PEVNTIDR3_PIN03 (*((volatile unsigned int*)(0x4221278CUL))) +#define bM4_AOS_PEVNTIDR3_PIN04 (*((volatile unsigned int*)(0x42212790UL))) +#define bM4_AOS_PEVNTIDR3_PIN05 (*((volatile unsigned int*)(0x42212794UL))) +#define bM4_AOS_PEVNTIDR3_PIN06 (*((volatile unsigned int*)(0x42212798UL))) +#define bM4_AOS_PEVNTIDR3_PIN07 (*((volatile unsigned int*)(0x4221279CUL))) +#define bM4_AOS_PEVNTIDR3_PIN08 (*((volatile unsigned int*)(0x422127A0UL))) +#define bM4_AOS_PEVNTIDR3_PIN09 (*((volatile unsigned int*)(0x422127A4UL))) +#define bM4_AOS_PEVNTIDR3_PIN10 (*((volatile unsigned int*)(0x422127A8UL))) +#define bM4_AOS_PEVNTIDR3_PIN11 (*((volatile unsigned int*)(0x422127ACUL))) +#define bM4_AOS_PEVNTIDR3_PIN12 (*((volatile unsigned int*)(0x422127B0UL))) +#define bM4_AOS_PEVNTIDR3_PIN13 (*((volatile unsigned int*)(0x422127B4UL))) +#define bM4_AOS_PEVNTIDR3_PIN14 (*((volatile unsigned int*)(0x422127B8UL))) +#define bM4_AOS_PEVNTIDR3_PIN15 (*((volatile unsigned int*)(0x422127BCUL))) +#define bM4_AOS_PEVNTODR3_POUT00 (*((volatile unsigned int*)(0x42212800UL))) +#define bM4_AOS_PEVNTODR3_POUT01 (*((volatile unsigned int*)(0x42212804UL))) +#define bM4_AOS_PEVNTODR3_POUT02 (*((volatile unsigned int*)(0x42212808UL))) +#define bM4_AOS_PEVNTODR3_POUT03 (*((volatile unsigned int*)(0x4221280CUL))) +#define bM4_AOS_PEVNTODR3_POUT04 (*((volatile unsigned int*)(0x42212810UL))) +#define bM4_AOS_PEVNTODR3_POUT05 (*((volatile unsigned int*)(0x42212814UL))) +#define bM4_AOS_PEVNTODR3_POUT06 (*((volatile unsigned int*)(0x42212818UL))) +#define bM4_AOS_PEVNTODR3_POUT07 (*((volatile unsigned int*)(0x4221281CUL))) +#define bM4_AOS_PEVNTODR3_POUT08 (*((volatile unsigned int*)(0x42212820UL))) +#define bM4_AOS_PEVNTODR3_POUT09 (*((volatile unsigned int*)(0x42212824UL))) +#define bM4_AOS_PEVNTODR3_POUT10 (*((volatile unsigned int*)(0x42212828UL))) +#define bM4_AOS_PEVNTODR3_POUT11 (*((volatile unsigned int*)(0x4221282CUL))) +#define bM4_AOS_PEVNTODR3_POUT12 (*((volatile unsigned int*)(0x42212830UL))) +#define bM4_AOS_PEVNTODR3_POUT13 (*((volatile unsigned int*)(0x42212834UL))) +#define bM4_AOS_PEVNTODR3_POUT14 (*((volatile unsigned int*)(0x42212838UL))) +#define bM4_AOS_PEVNTODR3_POUT15 (*((volatile unsigned int*)(0x4221283CUL))) +#define bM4_AOS_PEVNTORR3_POR00 (*((volatile unsigned int*)(0x42212880UL))) +#define bM4_AOS_PEVNTORR3_POR01 (*((volatile unsigned int*)(0x42212884UL))) +#define bM4_AOS_PEVNTORR3_POR02 (*((volatile unsigned int*)(0x42212888UL))) +#define bM4_AOS_PEVNTORR3_POR03 (*((volatile unsigned int*)(0x4221288CUL))) +#define bM4_AOS_PEVNTORR3_POR04 (*((volatile unsigned int*)(0x42212890UL))) +#define bM4_AOS_PEVNTORR3_POR05 (*((volatile unsigned int*)(0x42212894UL))) +#define bM4_AOS_PEVNTORR3_POR06 (*((volatile unsigned int*)(0x42212898UL))) +#define bM4_AOS_PEVNTORR3_POR07 (*((volatile unsigned int*)(0x4221289CUL))) +#define bM4_AOS_PEVNTORR3_POR08 (*((volatile unsigned int*)(0x422128A0UL))) +#define bM4_AOS_PEVNTORR3_POR09 (*((volatile unsigned int*)(0x422128A4UL))) +#define bM4_AOS_PEVNTORR3_POR10 (*((volatile unsigned int*)(0x422128A8UL))) +#define bM4_AOS_PEVNTORR3_POR11 (*((volatile unsigned int*)(0x422128ACUL))) +#define bM4_AOS_PEVNTORR3_POR12 (*((volatile unsigned int*)(0x422128B0UL))) +#define bM4_AOS_PEVNTORR3_POR13 (*((volatile unsigned int*)(0x422128B4UL))) +#define bM4_AOS_PEVNTORR3_POR14 (*((volatile unsigned int*)(0x422128B8UL))) +#define bM4_AOS_PEVNTORR3_POR15 (*((volatile unsigned int*)(0x422128BCUL))) +#define bM4_AOS_PEVNTOSR3_POS00 (*((volatile unsigned int*)(0x42212900UL))) +#define bM4_AOS_PEVNTOSR3_POS01 (*((volatile unsigned int*)(0x42212904UL))) +#define bM4_AOS_PEVNTOSR3_POS02 (*((volatile unsigned int*)(0x42212908UL))) +#define bM4_AOS_PEVNTOSR3_POS03 (*((volatile unsigned int*)(0x4221290CUL))) +#define bM4_AOS_PEVNTOSR3_POS04 (*((volatile unsigned int*)(0x42212910UL))) +#define bM4_AOS_PEVNTOSR3_POS05 (*((volatile unsigned int*)(0x42212914UL))) +#define bM4_AOS_PEVNTOSR3_POS06 (*((volatile unsigned int*)(0x42212918UL))) +#define bM4_AOS_PEVNTOSR3_POS07 (*((volatile unsigned int*)(0x4221291CUL))) +#define bM4_AOS_PEVNTOSR3_POS08 (*((volatile unsigned int*)(0x42212920UL))) +#define bM4_AOS_PEVNTOSR3_POS09 (*((volatile unsigned int*)(0x42212924UL))) +#define bM4_AOS_PEVNTOSR3_POS10 (*((volatile unsigned int*)(0x42212928UL))) +#define bM4_AOS_PEVNTOSR3_POS11 (*((volatile unsigned int*)(0x4221292CUL))) +#define bM4_AOS_PEVNTOSR3_POS12 (*((volatile unsigned int*)(0x42212930UL))) +#define bM4_AOS_PEVNTOSR3_POS13 (*((volatile unsigned int*)(0x42212934UL))) +#define bM4_AOS_PEVNTOSR3_POS14 (*((volatile unsigned int*)(0x42212938UL))) +#define bM4_AOS_PEVNTOSR3_POS15 (*((volatile unsigned int*)(0x4221293CUL))) +#define bM4_AOS_PEVNTRISR3_RIS00 (*((volatile unsigned int*)(0x42212980UL))) +#define bM4_AOS_PEVNTRISR3_RIS01 (*((volatile unsigned int*)(0x42212984UL))) +#define bM4_AOS_PEVNTRISR3_RIS02 (*((volatile unsigned int*)(0x42212988UL))) +#define bM4_AOS_PEVNTRISR3_RIS03 (*((volatile unsigned int*)(0x4221298CUL))) +#define bM4_AOS_PEVNTRISR3_RIS04 (*((volatile unsigned int*)(0x42212990UL))) +#define bM4_AOS_PEVNTRISR3_RIS05 (*((volatile unsigned int*)(0x42212994UL))) +#define bM4_AOS_PEVNTRISR3_RIS06 (*((volatile unsigned int*)(0x42212998UL))) +#define bM4_AOS_PEVNTRISR3_RIS07 (*((volatile unsigned int*)(0x4221299CUL))) +#define bM4_AOS_PEVNTRISR3_RIS08 (*((volatile unsigned int*)(0x422129A0UL))) +#define bM4_AOS_PEVNTRISR3_RIS09 (*((volatile unsigned int*)(0x422129A4UL))) +#define bM4_AOS_PEVNTRISR3_RIS10 (*((volatile unsigned int*)(0x422129A8UL))) +#define bM4_AOS_PEVNTRISR3_RIS11 (*((volatile unsigned int*)(0x422129ACUL))) +#define bM4_AOS_PEVNTRISR3_RIS12 (*((volatile unsigned int*)(0x422129B0UL))) +#define bM4_AOS_PEVNTRISR3_RIS13 (*((volatile unsigned int*)(0x422129B4UL))) +#define bM4_AOS_PEVNTRISR3_RIS14 (*((volatile unsigned int*)(0x422129B8UL))) +#define bM4_AOS_PEVNTRISR3_RIS15 (*((volatile unsigned int*)(0x422129BCUL))) +#define bM4_AOS_PEVNTFAL3_FAL00 (*((volatile unsigned int*)(0x42212A00UL))) +#define bM4_AOS_PEVNTFAL3_FAL01 (*((volatile unsigned int*)(0x42212A04UL))) +#define bM4_AOS_PEVNTFAL3_FAL02 (*((volatile unsigned int*)(0x42212A08UL))) +#define bM4_AOS_PEVNTFAL3_FAL03 (*((volatile unsigned int*)(0x42212A0CUL))) +#define bM4_AOS_PEVNTFAL3_FAL04 (*((volatile unsigned int*)(0x42212A10UL))) +#define bM4_AOS_PEVNTFAL3_FAL05 (*((volatile unsigned int*)(0x42212A14UL))) +#define bM4_AOS_PEVNTFAL3_FAL06 (*((volatile unsigned int*)(0x42212A18UL))) +#define bM4_AOS_PEVNTFAL3_FAL07 (*((volatile unsigned int*)(0x42212A1CUL))) +#define bM4_AOS_PEVNTFAL3_FAL08 (*((volatile unsigned int*)(0x42212A20UL))) +#define bM4_AOS_PEVNTFAL3_FAL09 (*((volatile unsigned int*)(0x42212A24UL))) +#define bM4_AOS_PEVNTFAL3_FAL10 (*((volatile unsigned int*)(0x42212A28UL))) +#define bM4_AOS_PEVNTFAL3_FAL11 (*((volatile unsigned int*)(0x42212A2CUL))) +#define bM4_AOS_PEVNTFAL3_FAL12 (*((volatile unsigned int*)(0x42212A30UL))) +#define bM4_AOS_PEVNTFAL3_FAL13 (*((volatile unsigned int*)(0x42212A34UL))) +#define bM4_AOS_PEVNTFAL3_FAL14 (*((volatile unsigned int*)(0x42212A38UL))) +#define bM4_AOS_PEVNTFAL3_FAL15 (*((volatile unsigned int*)(0x42212A3CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR00 (*((volatile unsigned int*)(0x42212A80UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR01 (*((volatile unsigned int*)(0x42212A84UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR02 (*((volatile unsigned int*)(0x42212A88UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR03 (*((volatile unsigned int*)(0x42212A8CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR04 (*((volatile unsigned int*)(0x42212A90UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR05 (*((volatile unsigned int*)(0x42212A94UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR06 (*((volatile unsigned int*)(0x42212A98UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR07 (*((volatile unsigned int*)(0x42212A9CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR08 (*((volatile unsigned int*)(0x42212AA0UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR09 (*((volatile unsigned int*)(0x42212AA4UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR10 (*((volatile unsigned int*)(0x42212AA8UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR11 (*((volatile unsigned int*)(0x42212AACUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR12 (*((volatile unsigned int*)(0x42212AB0UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR13 (*((volatile unsigned int*)(0x42212AB4UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR14 (*((volatile unsigned int*)(0x42212AB8UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR15 (*((volatile unsigned int*)(0x42212ABCUL))) +#define bM4_AOS_PEVNTIDR4_PIN00 (*((volatile unsigned int*)(0x42212B00UL))) +#define bM4_AOS_PEVNTIDR4_PIN01 (*((volatile unsigned int*)(0x42212B04UL))) +#define bM4_AOS_PEVNTIDR4_PIN02 (*((volatile unsigned int*)(0x42212B08UL))) +#define bM4_AOS_PEVNTIDR4_PIN03 (*((volatile unsigned int*)(0x42212B0CUL))) +#define bM4_AOS_PEVNTIDR4_PIN04 (*((volatile unsigned int*)(0x42212B10UL))) +#define bM4_AOS_PEVNTIDR4_PIN05 (*((volatile unsigned int*)(0x42212B14UL))) +#define bM4_AOS_PEVNTIDR4_PIN06 (*((volatile unsigned int*)(0x42212B18UL))) +#define bM4_AOS_PEVNTIDR4_PIN07 (*((volatile unsigned int*)(0x42212B1CUL))) +#define bM4_AOS_PEVNTIDR4_PIN08 (*((volatile unsigned int*)(0x42212B20UL))) +#define bM4_AOS_PEVNTIDR4_PIN09 (*((volatile unsigned int*)(0x42212B24UL))) +#define bM4_AOS_PEVNTIDR4_PIN10 (*((volatile unsigned int*)(0x42212B28UL))) +#define bM4_AOS_PEVNTIDR4_PIN11 (*((volatile unsigned int*)(0x42212B2CUL))) +#define bM4_AOS_PEVNTIDR4_PIN12 (*((volatile unsigned int*)(0x42212B30UL))) +#define bM4_AOS_PEVNTIDR4_PIN13 (*((volatile unsigned int*)(0x42212B34UL))) +#define bM4_AOS_PEVNTIDR4_PIN14 (*((volatile unsigned int*)(0x42212B38UL))) +#define bM4_AOS_PEVNTIDR4_PIN15 (*((volatile unsigned int*)(0x42212B3CUL))) +#define bM4_AOS_PEVNTODR4_POUT00 (*((volatile unsigned int*)(0x42212B80UL))) +#define bM4_AOS_PEVNTODR4_POUT01 (*((volatile unsigned int*)(0x42212B84UL))) +#define bM4_AOS_PEVNTODR4_POUT02 (*((volatile unsigned int*)(0x42212B88UL))) +#define bM4_AOS_PEVNTODR4_POUT03 (*((volatile unsigned int*)(0x42212B8CUL))) +#define bM4_AOS_PEVNTODR4_POUT04 (*((volatile unsigned int*)(0x42212B90UL))) +#define bM4_AOS_PEVNTODR4_POUT05 (*((volatile unsigned int*)(0x42212B94UL))) +#define bM4_AOS_PEVNTODR4_POUT06 (*((volatile unsigned int*)(0x42212B98UL))) +#define bM4_AOS_PEVNTODR4_POUT07 (*((volatile unsigned int*)(0x42212B9CUL))) +#define bM4_AOS_PEVNTODR4_POUT08 (*((volatile unsigned int*)(0x42212BA0UL))) +#define bM4_AOS_PEVNTODR4_POUT09 (*((volatile unsigned int*)(0x42212BA4UL))) +#define bM4_AOS_PEVNTODR4_POUT10 (*((volatile unsigned int*)(0x42212BA8UL))) +#define bM4_AOS_PEVNTODR4_POUT11 (*((volatile unsigned int*)(0x42212BACUL))) +#define bM4_AOS_PEVNTODR4_POUT12 (*((volatile unsigned int*)(0x42212BB0UL))) +#define bM4_AOS_PEVNTODR4_POUT13 (*((volatile unsigned int*)(0x42212BB4UL))) +#define bM4_AOS_PEVNTODR4_POUT14 (*((volatile unsigned int*)(0x42212BB8UL))) +#define bM4_AOS_PEVNTODR4_POUT15 (*((volatile unsigned int*)(0x42212BBCUL))) +#define bM4_AOS_PEVNTORR4_POR00 (*((volatile unsigned int*)(0x42212C00UL))) +#define bM4_AOS_PEVNTORR4_POR01 (*((volatile unsigned int*)(0x42212C04UL))) +#define bM4_AOS_PEVNTORR4_POR02 (*((volatile unsigned int*)(0x42212C08UL))) +#define bM4_AOS_PEVNTORR4_POR03 (*((volatile unsigned int*)(0x42212C0CUL))) +#define bM4_AOS_PEVNTORR4_POR04 (*((volatile unsigned int*)(0x42212C10UL))) +#define bM4_AOS_PEVNTORR4_POR05 (*((volatile unsigned int*)(0x42212C14UL))) +#define bM4_AOS_PEVNTORR4_POR06 (*((volatile unsigned int*)(0x42212C18UL))) +#define bM4_AOS_PEVNTORR4_POR07 (*((volatile unsigned int*)(0x42212C1CUL))) +#define bM4_AOS_PEVNTORR4_POR08 (*((volatile unsigned int*)(0x42212C20UL))) +#define bM4_AOS_PEVNTORR4_POR09 (*((volatile unsigned int*)(0x42212C24UL))) +#define bM4_AOS_PEVNTORR4_POR10 (*((volatile unsigned int*)(0x42212C28UL))) +#define bM4_AOS_PEVNTORR4_POR11 (*((volatile unsigned int*)(0x42212C2CUL))) +#define bM4_AOS_PEVNTORR4_POR12 (*((volatile unsigned int*)(0x42212C30UL))) +#define bM4_AOS_PEVNTORR4_POR13 (*((volatile unsigned int*)(0x42212C34UL))) +#define bM4_AOS_PEVNTORR4_POR14 (*((volatile unsigned int*)(0x42212C38UL))) +#define bM4_AOS_PEVNTORR4_POR15 (*((volatile unsigned int*)(0x42212C3CUL))) +#define bM4_AOS_PEVNTOSR4_POS00 (*((volatile unsigned int*)(0x42212C80UL))) +#define bM4_AOS_PEVNTOSR4_POS01 (*((volatile unsigned int*)(0x42212C84UL))) +#define bM4_AOS_PEVNTOSR4_POS02 (*((volatile unsigned int*)(0x42212C88UL))) +#define bM4_AOS_PEVNTOSR4_POS03 (*((volatile unsigned int*)(0x42212C8CUL))) +#define bM4_AOS_PEVNTOSR4_POS04 (*((volatile unsigned int*)(0x42212C90UL))) +#define bM4_AOS_PEVNTOSR4_POS05 (*((volatile unsigned int*)(0x42212C94UL))) +#define bM4_AOS_PEVNTOSR4_POS06 (*((volatile unsigned int*)(0x42212C98UL))) +#define bM4_AOS_PEVNTOSR4_POS07 (*((volatile unsigned int*)(0x42212C9CUL))) +#define bM4_AOS_PEVNTOSR4_POS08 (*((volatile unsigned int*)(0x42212CA0UL))) +#define bM4_AOS_PEVNTOSR4_POS09 (*((volatile unsigned int*)(0x42212CA4UL))) +#define bM4_AOS_PEVNTOSR4_POS10 (*((volatile unsigned int*)(0x42212CA8UL))) +#define bM4_AOS_PEVNTOSR4_POS11 (*((volatile unsigned int*)(0x42212CACUL))) +#define bM4_AOS_PEVNTOSR4_POS12 (*((volatile unsigned int*)(0x42212CB0UL))) +#define bM4_AOS_PEVNTOSR4_POS13 (*((volatile unsigned int*)(0x42212CB4UL))) +#define bM4_AOS_PEVNTOSR4_POS14 (*((volatile unsigned int*)(0x42212CB8UL))) +#define bM4_AOS_PEVNTOSR4_POS15 (*((volatile unsigned int*)(0x42212CBCUL))) +#define bM4_AOS_PEVNTRISR4_RIS00 (*((volatile unsigned int*)(0x42212D00UL))) +#define bM4_AOS_PEVNTRISR4_RIS01 (*((volatile unsigned int*)(0x42212D04UL))) +#define bM4_AOS_PEVNTRISR4_RIS02 (*((volatile unsigned int*)(0x42212D08UL))) +#define bM4_AOS_PEVNTRISR4_RIS03 (*((volatile unsigned int*)(0x42212D0CUL))) +#define bM4_AOS_PEVNTRISR4_RIS04 (*((volatile unsigned int*)(0x42212D10UL))) +#define bM4_AOS_PEVNTRISR4_RIS05 (*((volatile unsigned int*)(0x42212D14UL))) +#define bM4_AOS_PEVNTRISR4_RIS06 (*((volatile unsigned int*)(0x42212D18UL))) +#define bM4_AOS_PEVNTRISR4_RIS07 (*((volatile unsigned int*)(0x42212D1CUL))) +#define bM4_AOS_PEVNTRISR4_RIS08 (*((volatile unsigned int*)(0x42212D20UL))) +#define bM4_AOS_PEVNTRISR4_RIS09 (*((volatile unsigned int*)(0x42212D24UL))) +#define bM4_AOS_PEVNTRISR4_RIS10 (*((volatile unsigned int*)(0x42212D28UL))) +#define bM4_AOS_PEVNTRISR4_RIS11 (*((volatile unsigned int*)(0x42212D2CUL))) +#define bM4_AOS_PEVNTRISR4_RIS12 (*((volatile unsigned int*)(0x42212D30UL))) +#define bM4_AOS_PEVNTRISR4_RIS13 (*((volatile unsigned int*)(0x42212D34UL))) +#define bM4_AOS_PEVNTRISR4_RIS14 (*((volatile unsigned int*)(0x42212D38UL))) +#define bM4_AOS_PEVNTRISR4_RIS15 (*((volatile unsigned int*)(0x42212D3CUL))) +#define bM4_AOS_PEVNTFAL4_FAL00 (*((volatile unsigned int*)(0x42212D80UL))) +#define bM4_AOS_PEVNTFAL4_FAL01 (*((volatile unsigned int*)(0x42212D84UL))) +#define bM4_AOS_PEVNTFAL4_FAL02 (*((volatile unsigned int*)(0x42212D88UL))) +#define bM4_AOS_PEVNTFAL4_FAL03 (*((volatile unsigned int*)(0x42212D8CUL))) +#define bM4_AOS_PEVNTFAL4_FAL04 (*((volatile unsigned int*)(0x42212D90UL))) +#define bM4_AOS_PEVNTFAL4_FAL05 (*((volatile unsigned int*)(0x42212D94UL))) +#define bM4_AOS_PEVNTFAL4_FAL06 (*((volatile unsigned int*)(0x42212D98UL))) +#define bM4_AOS_PEVNTFAL4_FAL07 (*((volatile unsigned int*)(0x42212D9CUL))) +#define bM4_AOS_PEVNTFAL4_FAL08 (*((volatile unsigned int*)(0x42212DA0UL))) +#define bM4_AOS_PEVNTFAL4_FAL09 (*((volatile unsigned int*)(0x42212DA4UL))) +#define bM4_AOS_PEVNTFAL4_FAL10 (*((volatile unsigned int*)(0x42212DA8UL))) +#define bM4_AOS_PEVNTFAL4_FAL11 (*((volatile unsigned int*)(0x42212DACUL))) +#define bM4_AOS_PEVNTFAL4_FAL12 (*((volatile unsigned int*)(0x42212DB0UL))) +#define bM4_AOS_PEVNTFAL4_FAL13 (*((volatile unsigned int*)(0x42212DB4UL))) +#define bM4_AOS_PEVNTFAL4_FAL14 (*((volatile unsigned int*)(0x42212DB8UL))) +#define bM4_AOS_PEVNTFAL4_FAL15 (*((volatile unsigned int*)(0x42212DBCUL))) +#define bM4_AOS_PEVNTNFCR_NFEN1 (*((volatile unsigned int*)(0x42212E00UL))) +#define bM4_AOS_PEVNTNFCR_DIVS10 (*((volatile unsigned int*)(0x42212E04UL))) +#define bM4_AOS_PEVNTNFCR_DIVS11 (*((volatile unsigned int*)(0x42212E08UL))) +#define bM4_AOS_PEVNTNFCR_NFEN2 (*((volatile unsigned int*)(0x42212E20UL))) +#define bM4_AOS_PEVNTNFCR_DIVS20 (*((volatile unsigned int*)(0x42212E24UL))) +#define bM4_AOS_PEVNTNFCR_DIVS21 (*((volatile unsigned int*)(0x42212E28UL))) +#define bM4_AOS_PEVNTNFCR_NFEN3 (*((volatile unsigned int*)(0x42212E40UL))) +#define bM4_AOS_PEVNTNFCR_DIVS30 (*((volatile unsigned int*)(0x42212E44UL))) +#define bM4_AOS_PEVNTNFCR_DIVS31 (*((volatile unsigned int*)(0x42212E48UL))) +#define bM4_AOS_PEVNTNFCR_NFEN4 (*((volatile unsigned int*)(0x42212E60UL))) +#define bM4_AOS_PEVNTNFCR_DIVS40 (*((volatile unsigned int*)(0x42212E64UL))) +#define bM4_AOS_PEVNTNFCR_DIVS41 (*((volatile unsigned int*)(0x42212E68UL))) +#define bM4_CAN_CFG_STAT_BUSOFF (*((volatile unsigned int*)(0x42E09400UL))) +#define bM4_CAN_CFG_STAT_TACTIVE (*((volatile unsigned int*)(0x42E09404UL))) +#define bM4_CAN_CFG_STAT_RACTIVE (*((volatile unsigned int*)(0x42E09408UL))) +#define bM4_CAN_CFG_STAT_TSSS (*((volatile unsigned int*)(0x42E0940CUL))) +#define bM4_CAN_CFG_STAT_TPSS (*((volatile unsigned int*)(0x42E09410UL))) +#define bM4_CAN_CFG_STAT_LBMI (*((volatile unsigned int*)(0x42E09414UL))) +#define bM4_CAN_CFG_STAT_LBME (*((volatile unsigned int*)(0x42E09418UL))) +#define bM4_CAN_CFG_STAT_RESET (*((volatile unsigned int*)(0x42E0941CUL))) +#define bM4_CAN_TCMD_TSA (*((volatile unsigned int*)(0x42E09420UL))) +#define bM4_CAN_TCMD_TSALL (*((volatile unsigned int*)(0x42E09424UL))) +#define bM4_CAN_TCMD_TSONE (*((volatile unsigned int*)(0x42E09428UL))) +#define bM4_CAN_TCMD_TPA (*((volatile unsigned int*)(0x42E0942CUL))) +#define bM4_CAN_TCMD_TPE (*((volatile unsigned int*)(0x42E09430UL))) +#define bM4_CAN_TCMD_STBY (*((volatile unsigned int*)(0x42E09434UL))) +#define bM4_CAN_TCMD_LOM (*((volatile unsigned int*)(0x42E09438UL))) +#define bM4_CAN_TCMD_TBSEL (*((volatile unsigned int*)(0x42E0943CUL))) +#define bM4_CAN_TCTRL_TSSTAT0 (*((volatile unsigned int*)(0x42E09440UL))) +#define bM4_CAN_TCTRL_TSSTAT1 (*((volatile unsigned int*)(0x42E09444UL))) +#define bM4_CAN_TCTRL_TTBM (*((volatile unsigned int*)(0x42E09450UL))) +#define bM4_CAN_TCTRL_TSMODE (*((volatile unsigned int*)(0x42E09454UL))) +#define bM4_CAN_TCTRL_TSNEXT (*((volatile unsigned int*)(0x42E09458UL))) +#define bM4_CAN_RCTRL_RSSTAT0 (*((volatile unsigned int*)(0x42E09460UL))) +#define bM4_CAN_RCTRL_RSSTAT1 (*((volatile unsigned int*)(0x42E09464UL))) +#define bM4_CAN_RCTRL_RBALL (*((volatile unsigned int*)(0x42E0946CUL))) +#define bM4_CAN_RCTRL_RREL (*((volatile unsigned int*)(0x42E09470UL))) +#define bM4_CAN_RCTRL_ROV (*((volatile unsigned int*)(0x42E09474UL))) +#define bM4_CAN_RCTRL_ROM (*((volatile unsigned int*)(0x42E09478UL))) +#define bM4_CAN_RCTRL_SACK (*((volatile unsigned int*)(0x42E0947CUL))) +#define bM4_CAN_RTIE_TSFF (*((volatile unsigned int*)(0x42E09480UL))) +#define bM4_CAN_RTIE_EIE (*((volatile unsigned int*)(0x42E09484UL))) +#define bM4_CAN_RTIE_TSIE (*((volatile unsigned int*)(0x42E09488UL))) +#define bM4_CAN_RTIE_TPIE (*((volatile unsigned int*)(0x42E0948CUL))) +#define bM4_CAN_RTIE_RAFIE (*((volatile unsigned int*)(0x42E09490UL))) +#define bM4_CAN_RTIE_RFIE (*((volatile unsigned int*)(0x42E09494UL))) +#define bM4_CAN_RTIE_ROIE (*((volatile unsigned int*)(0x42E09498UL))) +#define bM4_CAN_RTIE_RIE (*((volatile unsigned int*)(0x42E0949CUL))) +#define bM4_CAN_RTIF_AIF (*((volatile unsigned int*)(0x42E094A0UL))) +#define bM4_CAN_RTIF_EIF (*((volatile unsigned int*)(0x42E094A4UL))) +#define bM4_CAN_RTIF_TSIF (*((volatile unsigned int*)(0x42E094A8UL))) +#define bM4_CAN_RTIF_TPIF (*((volatile unsigned int*)(0x42E094ACUL))) +#define bM4_CAN_RTIF_RAFIF (*((volatile unsigned int*)(0x42E094B0UL))) +#define bM4_CAN_RTIF_RFIF (*((volatile unsigned int*)(0x42E094B4UL))) +#define bM4_CAN_RTIF_ROIF (*((volatile unsigned int*)(0x42E094B8UL))) +#define bM4_CAN_RTIF_RIF (*((volatile unsigned int*)(0x42E094BCUL))) +#define bM4_CAN_ERRINT_BEIF (*((volatile unsigned int*)(0x42E094C0UL))) +#define bM4_CAN_ERRINT_BEIE (*((volatile unsigned int*)(0x42E094C4UL))) +#define bM4_CAN_ERRINT_ALIF (*((volatile unsigned int*)(0x42E094C8UL))) +#define bM4_CAN_ERRINT_ALIE (*((volatile unsigned int*)(0x42E094CCUL))) +#define bM4_CAN_ERRINT_EPIF (*((volatile unsigned int*)(0x42E094D0UL))) +#define bM4_CAN_ERRINT_EPIE (*((volatile unsigned int*)(0x42E094D4UL))) +#define bM4_CAN_ERRINT_EPASS (*((volatile unsigned int*)(0x42E094D8UL))) +#define bM4_CAN_ERRINT_EWARN (*((volatile unsigned int*)(0x42E094DCUL))) +#define bM4_CAN_LIMIT_EWL0 (*((volatile unsigned int*)(0x42E094E0UL))) +#define bM4_CAN_LIMIT_EWL1 (*((volatile unsigned int*)(0x42E094E4UL))) +#define bM4_CAN_LIMIT_EWL2 (*((volatile unsigned int*)(0x42E094E8UL))) +#define bM4_CAN_LIMIT_EWL3 (*((volatile unsigned int*)(0x42E094ECUL))) +#define bM4_CAN_LIMIT_AFWL0 (*((volatile unsigned int*)(0x42E094F0UL))) +#define bM4_CAN_LIMIT_AFWL1 (*((volatile unsigned int*)(0x42E094F4UL))) +#define bM4_CAN_LIMIT_AFWL2 (*((volatile unsigned int*)(0x42E094F8UL))) +#define bM4_CAN_LIMIT_AFWL3 (*((volatile unsigned int*)(0x42E094FCUL))) +#define bM4_CAN_BT_SEG_10 (*((volatile unsigned int*)(0x42E09500UL))) +#define bM4_CAN_BT_SEG_11 (*((volatile unsigned int*)(0x42E09504UL))) +#define bM4_CAN_BT_SEG_12 (*((volatile unsigned int*)(0x42E09508UL))) +#define bM4_CAN_BT_SEG_13 (*((volatile unsigned int*)(0x42E0950CUL))) +#define bM4_CAN_BT_SEG_14 (*((volatile unsigned int*)(0x42E09510UL))) +#define bM4_CAN_BT_SEG_15 (*((volatile unsigned int*)(0x42E09514UL))) +#define bM4_CAN_BT_SEG_16 (*((volatile unsigned int*)(0x42E09518UL))) +#define bM4_CAN_BT_SEG_17 (*((volatile unsigned int*)(0x42E0951CUL))) +#define bM4_CAN_BT_SEG_20 (*((volatile unsigned int*)(0x42E09520UL))) +#define bM4_CAN_BT_SEG_21 (*((volatile unsigned int*)(0x42E09524UL))) +#define bM4_CAN_BT_SEG_22 (*((volatile unsigned int*)(0x42E09528UL))) +#define bM4_CAN_BT_SEG_23 (*((volatile unsigned int*)(0x42E0952CUL))) +#define bM4_CAN_BT_SEG_24 (*((volatile unsigned int*)(0x42E09530UL))) +#define bM4_CAN_BT_SEG_25 (*((volatile unsigned int*)(0x42E09534UL))) +#define bM4_CAN_BT_SEG_26 (*((volatile unsigned int*)(0x42E09538UL))) +#define bM4_CAN_BT_SJW0 (*((volatile unsigned int*)(0x42E09540UL))) +#define bM4_CAN_BT_SJW1 (*((volatile unsigned int*)(0x42E09544UL))) +#define bM4_CAN_BT_SJW2 (*((volatile unsigned int*)(0x42E09548UL))) +#define bM4_CAN_BT_SJW3 (*((volatile unsigned int*)(0x42E0954CUL))) +#define bM4_CAN_BT_SJW4 (*((volatile unsigned int*)(0x42E09550UL))) +#define bM4_CAN_BT_SJW5 (*((volatile unsigned int*)(0x42E09554UL))) +#define bM4_CAN_BT_SJW6 (*((volatile unsigned int*)(0x42E09558UL))) +#define bM4_CAN_BT_PRESC0 (*((volatile unsigned int*)(0x42E09560UL))) +#define bM4_CAN_BT_PRESC1 (*((volatile unsigned int*)(0x42E09564UL))) +#define bM4_CAN_BT_PRESC2 (*((volatile unsigned int*)(0x42E09568UL))) +#define bM4_CAN_BT_PRESC3 (*((volatile unsigned int*)(0x42E0956CUL))) +#define bM4_CAN_BT_PRESC4 (*((volatile unsigned int*)(0x42E09570UL))) +#define bM4_CAN_BT_PRESC5 (*((volatile unsigned int*)(0x42E09574UL))) +#define bM4_CAN_BT_PRESC6 (*((volatile unsigned int*)(0x42E09578UL))) +#define bM4_CAN_BT_PRESC7 (*((volatile unsigned int*)(0x42E0957CUL))) +#define bM4_CAN_EALCAP_ALC0 (*((volatile unsigned int*)(0x42E09600UL))) +#define bM4_CAN_EALCAP_ALC1 (*((volatile unsigned int*)(0x42E09604UL))) +#define bM4_CAN_EALCAP_ALC2 (*((volatile unsigned int*)(0x42E09608UL))) +#define bM4_CAN_EALCAP_ALC3 (*((volatile unsigned int*)(0x42E0960CUL))) +#define bM4_CAN_EALCAP_ALC4 (*((volatile unsigned int*)(0x42E09610UL))) +#define bM4_CAN_EALCAP_KOER0 (*((volatile unsigned int*)(0x42E09614UL))) +#define bM4_CAN_EALCAP_KOER1 (*((volatile unsigned int*)(0x42E09618UL))) +#define bM4_CAN_EALCAP_KOER2 (*((volatile unsigned int*)(0x42E0961CUL))) +#define bM4_CAN_ACFCTRL_ACFADR0 (*((volatile unsigned int*)(0x42E09680UL))) +#define bM4_CAN_ACFCTRL_ACFADR1 (*((volatile unsigned int*)(0x42E09684UL))) +#define bM4_CAN_ACFCTRL_ACFADR2 (*((volatile unsigned int*)(0x42E09688UL))) +#define bM4_CAN_ACFCTRL_ACFADR3 (*((volatile unsigned int*)(0x42E0968CUL))) +#define bM4_CAN_ACFCTRL_SELMASK (*((volatile unsigned int*)(0x42E09694UL))) +#define bM4_CAN_ACFEN_AE_1 (*((volatile unsigned int*)(0x42E096C0UL))) +#define bM4_CAN_ACFEN_AE_2 (*((volatile unsigned int*)(0x42E096C4UL))) +#define bM4_CAN_ACFEN_AE_3 (*((volatile unsigned int*)(0x42E096C8UL))) +#define bM4_CAN_ACFEN_AE_4 (*((volatile unsigned int*)(0x42E096CCUL))) +#define bM4_CAN_ACFEN_AE_5 (*((volatile unsigned int*)(0x42E096D0UL))) +#define bM4_CAN_ACFEN_AE_6 (*((volatile unsigned int*)(0x42E096D4UL))) +#define bM4_CAN_ACFEN_AE_7 (*((volatile unsigned int*)(0x42E096D8UL))) +#define bM4_CAN_ACFEN_AE_8 (*((volatile unsigned int*)(0x42E096DCUL))) +#define bM4_CAN_ACF_ACODEORAMASK0 (*((volatile unsigned int*)(0x42E09700UL))) +#define bM4_CAN_ACF_ACODEORAMASK1 (*((volatile unsigned int*)(0x42E09704UL))) +#define bM4_CAN_ACF_ACODEORAMASK2 (*((volatile unsigned int*)(0x42E09708UL))) +#define bM4_CAN_ACF_ACODEORAMASK3 (*((volatile unsigned int*)(0x42E0970CUL))) +#define bM4_CAN_ACF_ACODEORAMASK4 (*((volatile unsigned int*)(0x42E09710UL))) +#define bM4_CAN_ACF_ACODEORAMASK5 (*((volatile unsigned int*)(0x42E09714UL))) +#define bM4_CAN_ACF_ACODEORAMASK6 (*((volatile unsigned int*)(0x42E09718UL))) +#define bM4_CAN_ACF_ACODEORAMASK7 (*((volatile unsigned int*)(0x42E0971CUL))) +#define bM4_CAN_ACF_ACODEORAMASK8 (*((volatile unsigned int*)(0x42E09720UL))) +#define bM4_CAN_ACF_ACODEORAMASK9 (*((volatile unsigned int*)(0x42E09724UL))) +#define bM4_CAN_ACF_ACODEORAMASK10 (*((volatile unsigned int*)(0x42E09728UL))) +#define bM4_CAN_ACF_ACODEORAMASK11 (*((volatile unsigned int*)(0x42E0972CUL))) +#define bM4_CAN_ACF_ACODEORAMASK12 (*((volatile unsigned int*)(0x42E09730UL))) +#define bM4_CAN_ACF_ACODEORAMASK13 (*((volatile unsigned int*)(0x42E09734UL))) +#define bM4_CAN_ACF_ACODEORAMASK14 (*((volatile unsigned int*)(0x42E09738UL))) +#define bM4_CAN_ACF_ACODEORAMASK15 (*((volatile unsigned int*)(0x42E0973CUL))) +#define bM4_CAN_ACF_ACODEORAMASK16 (*((volatile unsigned int*)(0x42E09740UL))) +#define bM4_CAN_ACF_ACODEORAMASK17 (*((volatile unsigned int*)(0x42E09744UL))) +#define bM4_CAN_ACF_ACODEORAMASK18 (*((volatile unsigned int*)(0x42E09748UL))) +#define bM4_CAN_ACF_ACODEORAMASK19 (*((volatile unsigned int*)(0x42E0974CUL))) +#define bM4_CAN_ACF_ACODEORAMASK20 (*((volatile unsigned int*)(0x42E09750UL))) +#define bM4_CAN_ACF_ACODEORAMASK21 (*((volatile unsigned int*)(0x42E09754UL))) +#define bM4_CAN_ACF_ACODEORAMASK22 (*((volatile unsigned int*)(0x42E09758UL))) +#define bM4_CAN_ACF_ACODEORAMASK23 (*((volatile unsigned int*)(0x42E0975CUL))) +#define bM4_CAN_ACF_ACODEORAMASK24 (*((volatile unsigned int*)(0x42E09760UL))) +#define bM4_CAN_ACF_ACODEORAMASK25 (*((volatile unsigned int*)(0x42E09764UL))) +#define bM4_CAN_ACF_ACODEORAMASK26 (*((volatile unsigned int*)(0x42E09768UL))) +#define bM4_CAN_ACF_ACODEORAMASK27 (*((volatile unsigned int*)(0x42E0976CUL))) +#define bM4_CAN_ACF_ACODEORAMASK28 (*((volatile unsigned int*)(0x42E09770UL))) +#define bM4_CAN_ACF_AIDE (*((volatile unsigned int*)(0x42E09774UL))) +#define bM4_CAN_ACF_AIDEE (*((volatile unsigned int*)(0x42E09778UL))) +#define bM4_CAN_TBSLOT_TBPTR0 (*((volatile unsigned int*)(0x42E097C0UL))) +#define bM4_CAN_TBSLOT_TBPTR1 (*((volatile unsigned int*)(0x42E097C4UL))) +#define bM4_CAN_TBSLOT_TBPTR2 (*((volatile unsigned int*)(0x42E097C8UL))) +#define bM4_CAN_TBSLOT_TBPTR3 (*((volatile unsigned int*)(0x42E097CCUL))) +#define bM4_CAN_TBSLOT_TBPTR4 (*((volatile unsigned int*)(0x42E097D0UL))) +#define bM4_CAN_TBSLOT_TBPTR5 (*((volatile unsigned int*)(0x42E097D4UL))) +#define bM4_CAN_TBSLOT_TBF (*((volatile unsigned int*)(0x42E097D8UL))) +#define bM4_CAN_TBSLOT_TBE (*((volatile unsigned int*)(0x42E097DCUL))) +#define bM4_CAN_TTCFG_TTEN (*((volatile unsigned int*)(0x42E097E0UL))) +#define bM4_CAN_TTCFG_T_PRESC0 (*((volatile unsigned int*)(0x42E097E4UL))) +#define bM4_CAN_TTCFG_T_PRESC1 (*((volatile unsigned int*)(0x42E097E8UL))) +#define bM4_CAN_TTCFG_TTIF (*((volatile unsigned int*)(0x42E097ECUL))) +#define bM4_CAN_TTCFG_TTIE (*((volatile unsigned int*)(0x42E097F0UL))) +#define bM4_CAN_TTCFG_TEIF (*((volatile unsigned int*)(0x42E097F4UL))) +#define bM4_CAN_TTCFG_WTIF (*((volatile unsigned int*)(0x42E097F8UL))) +#define bM4_CAN_TTCFG_WTIE (*((volatile unsigned int*)(0x42E097FCUL))) +#define bM4_CAN_REF_MSG_REF_ID0 (*((volatile unsigned int*)(0x42E09800UL))) +#define bM4_CAN_REF_MSG_REF_ID1 (*((volatile unsigned int*)(0x42E09804UL))) +#define bM4_CAN_REF_MSG_REF_ID2 (*((volatile unsigned int*)(0x42E09808UL))) +#define bM4_CAN_REF_MSG_REF_ID3 (*((volatile unsigned int*)(0x42E0980CUL))) +#define bM4_CAN_REF_MSG_REF_ID4 (*((volatile unsigned int*)(0x42E09810UL))) +#define bM4_CAN_REF_MSG_REF_ID5 (*((volatile unsigned int*)(0x42E09814UL))) +#define bM4_CAN_REF_MSG_REF_ID6 (*((volatile unsigned int*)(0x42E09818UL))) +#define bM4_CAN_REF_MSG_REF_ID7 (*((volatile unsigned int*)(0x42E0981CUL))) +#define bM4_CAN_REF_MSG_REF_ID8 (*((volatile unsigned int*)(0x42E09820UL))) +#define bM4_CAN_REF_MSG_REF_ID9 (*((volatile unsigned int*)(0x42E09824UL))) +#define bM4_CAN_REF_MSG_REF_ID10 (*((volatile unsigned int*)(0x42E09828UL))) +#define bM4_CAN_REF_MSG_REF_ID11 (*((volatile unsigned int*)(0x42E0982CUL))) +#define bM4_CAN_REF_MSG_REF_ID12 (*((volatile unsigned int*)(0x42E09830UL))) +#define bM4_CAN_REF_MSG_REF_ID13 (*((volatile unsigned int*)(0x42E09834UL))) +#define bM4_CAN_REF_MSG_REF_ID14 (*((volatile unsigned int*)(0x42E09838UL))) +#define bM4_CAN_REF_MSG_REF_ID15 (*((volatile unsigned int*)(0x42E0983CUL))) +#define bM4_CAN_REF_MSG_REF_ID16 (*((volatile unsigned int*)(0x42E09840UL))) +#define bM4_CAN_REF_MSG_REF_ID17 (*((volatile unsigned int*)(0x42E09844UL))) +#define bM4_CAN_REF_MSG_REF_ID18 (*((volatile unsigned int*)(0x42E09848UL))) +#define bM4_CAN_REF_MSG_REF_ID19 (*((volatile unsigned int*)(0x42E0984CUL))) +#define bM4_CAN_REF_MSG_REF_ID20 (*((volatile unsigned int*)(0x42E09850UL))) +#define bM4_CAN_REF_MSG_REF_ID21 (*((volatile unsigned int*)(0x42E09854UL))) +#define bM4_CAN_REF_MSG_REF_ID22 (*((volatile unsigned int*)(0x42E09858UL))) +#define bM4_CAN_REF_MSG_REF_ID23 (*((volatile unsigned int*)(0x42E0985CUL))) +#define bM4_CAN_REF_MSG_REF_ID24 (*((volatile unsigned int*)(0x42E09860UL))) +#define bM4_CAN_REF_MSG_REF_ID25 (*((volatile unsigned int*)(0x42E09864UL))) +#define bM4_CAN_REF_MSG_REF_ID26 (*((volatile unsigned int*)(0x42E09868UL))) +#define bM4_CAN_REF_MSG_REF_ID27 (*((volatile unsigned int*)(0x42E0986CUL))) +#define bM4_CAN_REF_MSG_REF_ID28 (*((volatile unsigned int*)(0x42E09870UL))) +#define bM4_CAN_REF_MSG_REF_IDE (*((volatile unsigned int*)(0x42E0987CUL))) +#define bM4_CAN_TRG_CFG_TTPTR0 (*((volatile unsigned int*)(0x42E09880UL))) +#define bM4_CAN_TRG_CFG_TTPTR1 (*((volatile unsigned int*)(0x42E09884UL))) +#define bM4_CAN_TRG_CFG_TTPTR2 (*((volatile unsigned int*)(0x42E09888UL))) +#define bM4_CAN_TRG_CFG_TTPTR3 (*((volatile unsigned int*)(0x42E0988CUL))) +#define bM4_CAN_TRG_CFG_TTPTR4 (*((volatile unsigned int*)(0x42E09890UL))) +#define bM4_CAN_TRG_CFG_TTPTR5 (*((volatile unsigned int*)(0x42E09894UL))) +#define bM4_CAN_TRG_CFG_TTYPE0 (*((volatile unsigned int*)(0x42E098A0UL))) +#define bM4_CAN_TRG_CFG_TTYPE1 (*((volatile unsigned int*)(0x42E098A4UL))) +#define bM4_CAN_TRG_CFG_TTYPE2 (*((volatile unsigned int*)(0x42E098A8UL))) +#define bM4_CAN_TRG_CFG_TEW0 (*((volatile unsigned int*)(0x42E098B0UL))) +#define bM4_CAN_TRG_CFG_TEW1 (*((volatile unsigned int*)(0x42E098B4UL))) +#define bM4_CAN_TRG_CFG_TEW2 (*((volatile unsigned int*)(0x42E098B8UL))) +#define bM4_CAN_TRG_CFG_TEW3 (*((volatile unsigned int*)(0x42E098BCUL))) +#define bM4_CMP1_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940000UL))) +#define bM4_CMP1_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940004UL))) +#define bM4_CMP1_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940008UL))) +#define bM4_CMP1_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940014UL))) +#define bM4_CMP1_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940018UL))) +#define bM4_CMP1_CTRL_IEN (*((volatile unsigned int*)(0x4294001CUL))) +#define bM4_CMP1_CTRL_CVSEN (*((volatile unsigned int*)(0x42940020UL))) +#define bM4_CMP1_CTRL_OUTEN (*((volatile unsigned int*)(0x42940030UL))) +#define bM4_CMP1_CTRL_INV (*((volatile unsigned int*)(0x42940034UL))) +#define bM4_CMP1_CTRL_CMPOE (*((volatile unsigned int*)(0x42940038UL))) +#define bM4_CMP1_CTRL_CMPON (*((volatile unsigned int*)(0x4294003CUL))) +#define bM4_CMP1_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940040UL))) +#define bM4_CMP1_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940044UL))) +#define bM4_CMP1_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940048UL))) +#define bM4_CMP1_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294004CUL))) +#define bM4_CMP1_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940060UL))) +#define bM4_CMP1_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940064UL))) +#define bM4_CMP1_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940068UL))) +#define bM4_CMP1_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294006CUL))) +#define bM4_CMP1_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940070UL))) +#define bM4_CMP1_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940074UL))) +#define bM4_CMP1_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940078UL))) +#define bM4_CMP1_MON_OMON (*((volatile unsigned int*)(0x42940080UL))) +#define bM4_CMP1_MON_CVST0 (*((volatile unsigned int*)(0x429400A0UL))) +#define bM4_CMP1_MON_CVST1 (*((volatile unsigned int*)(0x429400A4UL))) +#define bM4_CMP1_MON_CVST2 (*((volatile unsigned int*)(0x429400A8UL))) +#define bM4_CMP1_MON_CVST3 (*((volatile unsigned int*)(0x429400ACUL))) +#define bM4_CMP1_CVSSTB_STB0 (*((volatile unsigned int*)(0x429400C0UL))) +#define bM4_CMP1_CVSSTB_STB1 (*((volatile unsigned int*)(0x429400C4UL))) +#define bM4_CMP1_CVSSTB_STB2 (*((volatile unsigned int*)(0x429400C8UL))) +#define bM4_CMP1_CVSSTB_STB3 (*((volatile unsigned int*)(0x429400CCUL))) +#define bM4_CMP1_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940100UL))) +#define bM4_CMP1_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940104UL))) +#define bM4_CMP1_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940108UL))) +#define bM4_CMP1_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294010CUL))) +#define bM4_CMP1_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940110UL))) +#define bM4_CMP1_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940114UL))) +#define bM4_CMP1_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940118UL))) +#define bM4_CMP1_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294011CUL))) +#define bM4_CMP2_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940200UL))) +#define bM4_CMP2_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940204UL))) +#define bM4_CMP2_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940208UL))) +#define bM4_CMP2_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940214UL))) +#define bM4_CMP2_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940218UL))) +#define bM4_CMP2_CTRL_IEN (*((volatile unsigned int*)(0x4294021CUL))) +#define bM4_CMP2_CTRL_CVSEN (*((volatile unsigned int*)(0x42940220UL))) +#define bM4_CMP2_CTRL_OUTEN (*((volatile unsigned int*)(0x42940230UL))) +#define bM4_CMP2_CTRL_INV (*((volatile unsigned int*)(0x42940234UL))) +#define bM4_CMP2_CTRL_CMPOE (*((volatile unsigned int*)(0x42940238UL))) +#define bM4_CMP2_CTRL_CMPON (*((volatile unsigned int*)(0x4294023CUL))) +#define bM4_CMP2_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940240UL))) +#define bM4_CMP2_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940244UL))) +#define bM4_CMP2_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940248UL))) +#define bM4_CMP2_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294024CUL))) +#define bM4_CMP2_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940260UL))) +#define bM4_CMP2_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940264UL))) +#define bM4_CMP2_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940268UL))) +#define bM4_CMP2_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294026CUL))) +#define bM4_CMP2_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940270UL))) +#define bM4_CMP2_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940274UL))) +#define bM4_CMP2_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940278UL))) +#define bM4_CMP2_MON_OMON (*((volatile unsigned int*)(0x42940280UL))) +#define bM4_CMP2_MON_CVST0 (*((volatile unsigned int*)(0x429402A0UL))) +#define bM4_CMP2_MON_CVST1 (*((volatile unsigned int*)(0x429402A4UL))) +#define bM4_CMP2_MON_CVST2 (*((volatile unsigned int*)(0x429402A8UL))) +#define bM4_CMP2_MON_CVST3 (*((volatile unsigned int*)(0x429402ACUL))) +#define bM4_CMP2_CVSSTB_STB0 (*((volatile unsigned int*)(0x429402C0UL))) +#define bM4_CMP2_CVSSTB_STB1 (*((volatile unsigned int*)(0x429402C4UL))) +#define bM4_CMP2_CVSSTB_STB2 (*((volatile unsigned int*)(0x429402C8UL))) +#define bM4_CMP2_CVSSTB_STB3 (*((volatile unsigned int*)(0x429402CCUL))) +#define bM4_CMP2_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940300UL))) +#define bM4_CMP2_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940304UL))) +#define bM4_CMP2_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940308UL))) +#define bM4_CMP2_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294030CUL))) +#define bM4_CMP2_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940310UL))) +#define bM4_CMP2_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940314UL))) +#define bM4_CMP2_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940318UL))) +#define bM4_CMP2_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294031CUL))) +#define bM4_CMP3_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940400UL))) +#define bM4_CMP3_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940404UL))) +#define bM4_CMP3_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940408UL))) +#define bM4_CMP3_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940414UL))) +#define bM4_CMP3_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940418UL))) +#define bM4_CMP3_CTRL_IEN (*((volatile unsigned int*)(0x4294041CUL))) +#define bM4_CMP3_CTRL_CVSEN (*((volatile unsigned int*)(0x42940420UL))) +#define bM4_CMP3_CTRL_OUTEN (*((volatile unsigned int*)(0x42940430UL))) +#define bM4_CMP3_CTRL_INV (*((volatile unsigned int*)(0x42940434UL))) +#define bM4_CMP3_CTRL_CMPOE (*((volatile unsigned int*)(0x42940438UL))) +#define bM4_CMP3_CTRL_CMPON (*((volatile unsigned int*)(0x4294043CUL))) +#define bM4_CMP3_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940440UL))) +#define bM4_CMP3_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940444UL))) +#define bM4_CMP3_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940448UL))) +#define bM4_CMP3_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294044CUL))) +#define bM4_CMP3_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940460UL))) +#define bM4_CMP3_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940464UL))) +#define bM4_CMP3_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940468UL))) +#define bM4_CMP3_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294046CUL))) +#define bM4_CMP3_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940470UL))) +#define bM4_CMP3_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940474UL))) +#define bM4_CMP3_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940478UL))) +#define bM4_CMP3_MON_OMON (*((volatile unsigned int*)(0x42940480UL))) +#define bM4_CMP3_MON_CVST0 (*((volatile unsigned int*)(0x429404A0UL))) +#define bM4_CMP3_MON_CVST1 (*((volatile unsigned int*)(0x429404A4UL))) +#define bM4_CMP3_MON_CVST2 (*((volatile unsigned int*)(0x429404A8UL))) +#define bM4_CMP3_MON_CVST3 (*((volatile unsigned int*)(0x429404ACUL))) +#define bM4_CMP3_CVSSTB_STB0 (*((volatile unsigned int*)(0x429404C0UL))) +#define bM4_CMP3_CVSSTB_STB1 (*((volatile unsigned int*)(0x429404C4UL))) +#define bM4_CMP3_CVSSTB_STB2 (*((volatile unsigned int*)(0x429404C8UL))) +#define bM4_CMP3_CVSSTB_STB3 (*((volatile unsigned int*)(0x429404CCUL))) +#define bM4_CMP3_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940500UL))) +#define bM4_CMP3_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940504UL))) +#define bM4_CMP3_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940508UL))) +#define bM4_CMP3_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294050CUL))) +#define bM4_CMP3_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940510UL))) +#define bM4_CMP3_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940514UL))) +#define bM4_CMP3_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940518UL))) +#define bM4_CMP3_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294051CUL))) +#define bM4_CMP_CR_DADR1_DATA0 (*((volatile unsigned int*)(0x42942000UL))) +#define bM4_CMP_CR_DADR1_DATA1 (*((volatile unsigned int*)(0x42942004UL))) +#define bM4_CMP_CR_DADR1_DATA2 (*((volatile unsigned int*)(0x42942008UL))) +#define bM4_CMP_CR_DADR1_DATA3 (*((volatile unsigned int*)(0x4294200CUL))) +#define bM4_CMP_CR_DADR1_DATA4 (*((volatile unsigned int*)(0x42942010UL))) +#define bM4_CMP_CR_DADR1_DATA5 (*((volatile unsigned int*)(0x42942014UL))) +#define bM4_CMP_CR_DADR1_DATA6 (*((volatile unsigned int*)(0x42942018UL))) +#define bM4_CMP_CR_DADR1_DATA7 (*((volatile unsigned int*)(0x4294201CUL))) +#define bM4_CMP_CR_DADR2_DATA0 (*((volatile unsigned int*)(0x42942040UL))) +#define bM4_CMP_CR_DADR2_DATA1 (*((volatile unsigned int*)(0x42942044UL))) +#define bM4_CMP_CR_DADR2_DATA2 (*((volatile unsigned int*)(0x42942048UL))) +#define bM4_CMP_CR_DADR2_DATA3 (*((volatile unsigned int*)(0x4294204CUL))) +#define bM4_CMP_CR_DADR2_DATA4 (*((volatile unsigned int*)(0x42942050UL))) +#define bM4_CMP_CR_DADR2_DATA5 (*((volatile unsigned int*)(0x42942054UL))) +#define bM4_CMP_CR_DADR2_DATA6 (*((volatile unsigned int*)(0x42942058UL))) +#define bM4_CMP_CR_DADR2_DATA7 (*((volatile unsigned int*)(0x4294205CUL))) +#define bM4_CMP_CR_DACR_DA1EN (*((volatile unsigned int*)(0x42942100UL))) +#define bM4_CMP_CR_DACR_DA2EN (*((volatile unsigned int*)(0x42942104UL))) +#define bM4_CMP_CR_RVADC_DA1SW (*((volatile unsigned int*)(0x42942180UL))) +#define bM4_CMP_CR_RVADC_DA2SW (*((volatile unsigned int*)(0x42942184UL))) +#define bM4_CMP_CR_RVADC_VREFSW (*((volatile unsigned int*)(0x42942190UL))) +#define bM4_CMP_CR_RVADC_WPRT0 (*((volatile unsigned int*)(0x429421A0UL))) +#define bM4_CMP_CR_RVADC_WPRT1 (*((volatile unsigned int*)(0x429421A4UL))) +#define bM4_CMP_CR_RVADC_WPRT2 (*((volatile unsigned int*)(0x429421A8UL))) +#define bM4_CMP_CR_RVADC_WPRT3 (*((volatile unsigned int*)(0x429421ACUL))) +#define bM4_CMP_CR_RVADC_WPRT4 (*((volatile unsigned int*)(0x429421B0UL))) +#define bM4_CMP_CR_RVADC_WPRT5 (*((volatile unsigned int*)(0x429421B4UL))) +#define bM4_CMP_CR_RVADC_WPRT6 (*((volatile unsigned int*)(0x429421B8UL))) +#define bM4_CMP_CR_RVADC_WPRT7 (*((volatile unsigned int*)(0x429421BCUL))) +#define bM4_CRC_CR_CRC_SEL (*((volatile unsigned int*)(0x42118004UL))) +#define bM4_CRC_CR_REFIN (*((volatile unsigned int*)(0x42118008UL))) +#define bM4_CRC_CR_REFOUT (*((volatile unsigned int*)(0x4211800CUL))) +#define bM4_CRC_CR_XOROUT (*((volatile unsigned int*)(0x42118010UL))) +#define bM4_CRC_FLG_FLAG (*((volatile unsigned int*)(0x42118180UL))) +#define bM4_DCU1_CTL_MODE0 (*((volatile unsigned int*)(0x42A40000UL))) +#define bM4_DCU1_CTL_MODE1 (*((volatile unsigned int*)(0x42A40004UL))) +#define bM4_DCU1_CTL_MODE2 (*((volatile unsigned int*)(0x42A40008UL))) +#define bM4_DCU1_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A4000CUL))) +#define bM4_DCU1_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A40010UL))) +#define bM4_DCU1_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A40020UL))) +#define bM4_DCU1_CTL_INTEN (*((volatile unsigned int*)(0x42A4007CUL))) +#define bM4_DCU1_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A40080UL))) +#define bM4_DCU1_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A40084UL))) +#define bM4_DCU1_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A40088UL))) +#define bM4_DCU1_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A4008CUL))) +#define bM4_DCU1_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A40090UL))) +#define bM4_DCU1_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A40094UL))) +#define bM4_DCU1_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A40098UL))) +#define bM4_DCU1_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A40280UL))) +#define bM4_DCU1_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A40284UL))) +#define bM4_DCU1_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A40288UL))) +#define bM4_DCU1_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A4028CUL))) +#define bM4_DCU1_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A40290UL))) +#define bM4_DCU1_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A40294UL))) +#define bM4_DCU1_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A40298UL))) +#define bM4_DCU1_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A40300UL))) +#define bM4_DCU1_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A40304UL))) +#define bM4_DCU1_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A40308UL))) +#define bM4_DCU1_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A4030CUL))) +#define bM4_DCU1_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A40310UL))) +#define bM4_DCU1_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A40314UL))) +#define bM4_DCU1_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A40318UL))) +#define bM4_DCU1_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A4031CUL))) +#define bM4_DCU1_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A40320UL))) +#define bM4_DCU2_CTL_MODE0 (*((volatile unsigned int*)(0x42A48000UL))) +#define bM4_DCU2_CTL_MODE1 (*((volatile unsigned int*)(0x42A48004UL))) +#define bM4_DCU2_CTL_MODE2 (*((volatile unsigned int*)(0x42A48008UL))) +#define bM4_DCU2_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A4800CUL))) +#define bM4_DCU2_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A48010UL))) +#define bM4_DCU2_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A48020UL))) +#define bM4_DCU2_CTL_INTEN (*((volatile unsigned int*)(0x42A4807CUL))) +#define bM4_DCU2_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A48080UL))) +#define bM4_DCU2_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A48084UL))) +#define bM4_DCU2_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A48088UL))) +#define bM4_DCU2_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A4808CUL))) +#define bM4_DCU2_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A48090UL))) +#define bM4_DCU2_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A48094UL))) +#define bM4_DCU2_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A48098UL))) +#define bM4_DCU2_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A48280UL))) +#define bM4_DCU2_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A48284UL))) +#define bM4_DCU2_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A48288UL))) +#define bM4_DCU2_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A4828CUL))) +#define bM4_DCU2_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A48290UL))) +#define bM4_DCU2_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A48294UL))) +#define bM4_DCU2_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A48298UL))) +#define bM4_DCU2_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A48300UL))) +#define bM4_DCU2_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A48304UL))) +#define bM4_DCU2_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A48308UL))) +#define bM4_DCU2_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A4830CUL))) +#define bM4_DCU2_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A48310UL))) +#define bM4_DCU2_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A48314UL))) +#define bM4_DCU2_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A48318UL))) +#define bM4_DCU2_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A4831CUL))) +#define bM4_DCU2_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A48320UL))) +#define bM4_DCU3_CTL_MODE0 (*((volatile unsigned int*)(0x42A50000UL))) +#define bM4_DCU3_CTL_MODE1 (*((volatile unsigned int*)(0x42A50004UL))) +#define bM4_DCU3_CTL_MODE2 (*((volatile unsigned int*)(0x42A50008UL))) +#define bM4_DCU3_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A5000CUL))) +#define bM4_DCU3_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A50010UL))) +#define bM4_DCU3_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A50020UL))) +#define bM4_DCU3_CTL_INTEN (*((volatile unsigned int*)(0x42A5007CUL))) +#define bM4_DCU3_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A50080UL))) +#define bM4_DCU3_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A50084UL))) +#define bM4_DCU3_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A50088UL))) +#define bM4_DCU3_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A5008CUL))) +#define bM4_DCU3_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A50090UL))) +#define bM4_DCU3_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A50094UL))) +#define bM4_DCU3_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A50098UL))) +#define bM4_DCU3_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A50280UL))) +#define bM4_DCU3_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A50284UL))) +#define bM4_DCU3_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A50288UL))) +#define bM4_DCU3_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A5028CUL))) +#define bM4_DCU3_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A50290UL))) +#define bM4_DCU3_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A50294UL))) +#define bM4_DCU3_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A50298UL))) +#define bM4_DCU3_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A50300UL))) +#define bM4_DCU3_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A50304UL))) +#define bM4_DCU3_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A50308UL))) +#define bM4_DCU3_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A5030CUL))) +#define bM4_DCU3_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A50310UL))) +#define bM4_DCU3_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A50314UL))) +#define bM4_DCU3_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A50318UL))) +#define bM4_DCU3_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A5031CUL))) +#define bM4_DCU3_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A50320UL))) +#define bM4_DCU4_CTL_MODE0 (*((volatile unsigned int*)(0x42A58000UL))) +#define bM4_DCU4_CTL_MODE1 (*((volatile unsigned int*)(0x42A58004UL))) +#define bM4_DCU4_CTL_MODE2 (*((volatile unsigned int*)(0x42A58008UL))) +#define bM4_DCU4_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A5800CUL))) +#define bM4_DCU4_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A58010UL))) +#define bM4_DCU4_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A58020UL))) +#define bM4_DCU4_CTL_INTEN (*((volatile unsigned int*)(0x42A5807CUL))) +#define bM4_DCU4_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A58080UL))) +#define bM4_DCU4_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A58084UL))) +#define bM4_DCU4_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A58088UL))) +#define bM4_DCU4_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A5808CUL))) +#define bM4_DCU4_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A58090UL))) +#define bM4_DCU4_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A58094UL))) +#define bM4_DCU4_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A58098UL))) +#define bM4_DCU4_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A58280UL))) +#define bM4_DCU4_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A58284UL))) +#define bM4_DCU4_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A58288UL))) +#define bM4_DCU4_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A5828CUL))) +#define bM4_DCU4_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A58290UL))) +#define bM4_DCU4_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A58294UL))) +#define bM4_DCU4_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A58298UL))) +#define bM4_DCU4_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A58300UL))) +#define bM4_DCU4_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A58304UL))) +#define bM4_DCU4_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A58308UL))) +#define bM4_DCU4_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A5830CUL))) +#define bM4_DCU4_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A58310UL))) +#define bM4_DCU4_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A58314UL))) +#define bM4_DCU4_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A58318UL))) +#define bM4_DCU4_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A5831CUL))) +#define bM4_DCU4_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A58320UL))) +#define bM4_DMA1_EN_EN (*((volatile unsigned int*)(0x42A60000UL))) +#define bM4_DMA1_INTSTAT0_TRNERR0 (*((volatile unsigned int*)(0x42A60080UL))) +#define bM4_DMA1_INTSTAT0_TRNERR1 (*((volatile unsigned int*)(0x42A60084UL))) +#define bM4_DMA1_INTSTAT0_TRNERR2 (*((volatile unsigned int*)(0x42A60088UL))) +#define bM4_DMA1_INTSTAT0_TRNERR3 (*((volatile unsigned int*)(0x42A6008CUL))) +#define bM4_DMA1_INTSTAT0_REQERR0 (*((volatile unsigned int*)(0x42A600C0UL))) +#define bM4_DMA1_INTSTAT0_REQERR1 (*((volatile unsigned int*)(0x42A600C4UL))) +#define bM4_DMA1_INTSTAT0_REQERR2 (*((volatile unsigned int*)(0x42A600C8UL))) +#define bM4_DMA1_INTSTAT0_REQERR3 (*((volatile unsigned int*)(0x42A600CCUL))) +#define bM4_DMA1_INTSTAT1_TC0 (*((volatile unsigned int*)(0x42A60100UL))) +#define bM4_DMA1_INTSTAT1_TC1 (*((volatile unsigned int*)(0x42A60104UL))) +#define bM4_DMA1_INTSTAT1_TC2 (*((volatile unsigned int*)(0x42A60108UL))) +#define bM4_DMA1_INTSTAT1_TC3 (*((volatile unsigned int*)(0x42A6010CUL))) +#define bM4_DMA1_INTSTAT1_BTC0 (*((volatile unsigned int*)(0x42A60140UL))) +#define bM4_DMA1_INTSTAT1_BTC1 (*((volatile unsigned int*)(0x42A60144UL))) +#define bM4_DMA1_INTSTAT1_BTC2 (*((volatile unsigned int*)(0x42A60148UL))) +#define bM4_DMA1_INTSTAT1_BTC3 (*((volatile unsigned int*)(0x42A6014CUL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR0 (*((volatile unsigned int*)(0x42A60180UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR1 (*((volatile unsigned int*)(0x42A60184UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR2 (*((volatile unsigned int*)(0x42A60188UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR3 (*((volatile unsigned int*)(0x42A6018CUL))) +#define bM4_DMA1_INTMASK0_MSKREQERR0 (*((volatile unsigned int*)(0x42A601C0UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR1 (*((volatile unsigned int*)(0x42A601C4UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR2 (*((volatile unsigned int*)(0x42A601C8UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR3 (*((volatile unsigned int*)(0x42A601CCUL))) +#define bM4_DMA1_INTMASK1_MSKTC0 (*((volatile unsigned int*)(0x42A60200UL))) +#define bM4_DMA1_INTMASK1_MSKTC1 (*((volatile unsigned int*)(0x42A60204UL))) +#define bM4_DMA1_INTMASK1_MSKTC2 (*((volatile unsigned int*)(0x42A60208UL))) +#define bM4_DMA1_INTMASK1_MSKTC3 (*((volatile unsigned int*)(0x42A6020CUL))) +#define bM4_DMA1_INTMASK1_MSKBTC0 (*((volatile unsigned int*)(0x42A60240UL))) +#define bM4_DMA1_INTMASK1_MSKBTC1 (*((volatile unsigned int*)(0x42A60244UL))) +#define bM4_DMA1_INTMASK1_MSKBTC2 (*((volatile unsigned int*)(0x42A60248UL))) +#define bM4_DMA1_INTMASK1_MSKBTC3 (*((volatile unsigned int*)(0x42A6024CUL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR0 (*((volatile unsigned int*)(0x42A60280UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR1 (*((volatile unsigned int*)(0x42A60284UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR2 (*((volatile unsigned int*)(0x42A60288UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR3 (*((volatile unsigned int*)(0x42A6028CUL))) +#define bM4_DMA1_INTCLR0_CLRREQERR0 (*((volatile unsigned int*)(0x42A602C0UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR1 (*((volatile unsigned int*)(0x42A602C4UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR2 (*((volatile unsigned int*)(0x42A602C8UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR3 (*((volatile unsigned int*)(0x42A602CCUL))) +#define bM4_DMA1_INTCLR1_CLRTC0 (*((volatile unsigned int*)(0x42A60300UL))) +#define bM4_DMA1_INTCLR1_CLRTC1 (*((volatile unsigned int*)(0x42A60304UL))) +#define bM4_DMA1_INTCLR1_CLRTC2 (*((volatile unsigned int*)(0x42A60308UL))) +#define bM4_DMA1_INTCLR1_CLRTC3 (*((volatile unsigned int*)(0x42A6030CUL))) +#define bM4_DMA1_INTCLR1_CLRBTC0 (*((volatile unsigned int*)(0x42A60340UL))) +#define bM4_DMA1_INTCLR1_CLRBTC1 (*((volatile unsigned int*)(0x42A60344UL))) +#define bM4_DMA1_INTCLR1_CLRBTC2 (*((volatile unsigned int*)(0x42A60348UL))) +#define bM4_DMA1_INTCLR1_CLRBTC3 (*((volatile unsigned int*)(0x42A6034CUL))) +#define bM4_DMA1_CHEN_CHEN0 (*((volatile unsigned int*)(0x42A60380UL))) +#define bM4_DMA1_CHEN_CHEN1 (*((volatile unsigned int*)(0x42A60384UL))) +#define bM4_DMA1_CHEN_CHEN2 (*((volatile unsigned int*)(0x42A60388UL))) +#define bM4_DMA1_CHEN_CHEN3 (*((volatile unsigned int*)(0x42A6038CUL))) +#define bM4_DMA1_CHSTAT_DMAACT (*((volatile unsigned int*)(0x42A60480UL))) +#define bM4_DMA1_CHSTAT_RCFGACT (*((volatile unsigned int*)(0x42A60484UL))) +#define bM4_DMA1_CHSTAT_CHACT0 (*((volatile unsigned int*)(0x42A604C0UL))) +#define bM4_DMA1_CHSTAT_CHACT1 (*((volatile unsigned int*)(0x42A604C4UL))) +#define bM4_DMA1_CHSTAT_CHACT2 (*((volatile unsigned int*)(0x42A604C8UL))) +#define bM4_DMA1_CHSTAT_CHACT3 (*((volatile unsigned int*)(0x42A604CCUL))) +#define bM4_DMA1_RCFGCTL_RCFGEN (*((volatile unsigned int*)(0x42A60580UL))) +#define bM4_DMA1_RCFGCTL_RCFGLLP (*((volatile unsigned int*)(0x42A60584UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS0 (*((volatile unsigned int*)(0x42A605A0UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS1 (*((volatile unsigned int*)(0x42A605A4UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS2 (*((volatile unsigned int*)(0x42A605A8UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS3 (*((volatile unsigned int*)(0x42A605ACUL))) +#define bM4_DMA1_RCFGCTL_SARMD0 (*((volatile unsigned int*)(0x42A605C0UL))) +#define bM4_DMA1_RCFGCTL_SARMD1 (*((volatile unsigned int*)(0x42A605C4UL))) +#define bM4_DMA1_RCFGCTL_DARMD0 (*((volatile unsigned int*)(0x42A605C8UL))) +#define bM4_DMA1_RCFGCTL_DARMD1 (*((volatile unsigned int*)(0x42A605CCUL))) +#define bM4_DMA1_RCFGCTL_CNTMD0 (*((volatile unsigned int*)(0x42A605D0UL))) +#define bM4_DMA1_RCFGCTL_CNTMD1 (*((volatile unsigned int*)(0x42A605D4UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A60900UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A60904UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A60908UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A6090CUL))) +#define bM4_DMA1_DTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A60910UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A60914UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A60918UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A6091CUL))) +#define bM4_DMA1_DTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A60920UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A60924UL))) +#define bM4_DMA1_DTCTL0_CNT0 (*((volatile unsigned int*)(0x42A60940UL))) +#define bM4_DMA1_DTCTL0_CNT1 (*((volatile unsigned int*)(0x42A60944UL))) +#define bM4_DMA1_DTCTL0_CNT2 (*((volatile unsigned int*)(0x42A60948UL))) +#define bM4_DMA1_DTCTL0_CNT3 (*((volatile unsigned int*)(0x42A6094CUL))) +#define bM4_DMA1_DTCTL0_CNT4 (*((volatile unsigned int*)(0x42A60950UL))) +#define bM4_DMA1_DTCTL0_CNT5 (*((volatile unsigned int*)(0x42A60954UL))) +#define bM4_DMA1_DTCTL0_CNT6 (*((volatile unsigned int*)(0x42A60958UL))) +#define bM4_DMA1_DTCTL0_CNT7 (*((volatile unsigned int*)(0x42A6095CUL))) +#define bM4_DMA1_DTCTL0_CNT8 (*((volatile unsigned int*)(0x42A60960UL))) +#define bM4_DMA1_DTCTL0_CNT9 (*((volatile unsigned int*)(0x42A60964UL))) +#define bM4_DMA1_DTCTL0_CNT10 (*((volatile unsigned int*)(0x42A60968UL))) +#define bM4_DMA1_DTCTL0_CNT11 (*((volatile unsigned int*)(0x42A6096CUL))) +#define bM4_DMA1_DTCTL0_CNT12 (*((volatile unsigned int*)(0x42A60970UL))) +#define bM4_DMA1_DTCTL0_CNT13 (*((volatile unsigned int*)(0x42A60974UL))) +#define bM4_DMA1_DTCTL0_CNT14 (*((volatile unsigned int*)(0x42A60978UL))) +#define bM4_DMA1_DTCTL0_CNT15 (*((volatile unsigned int*)(0x42A6097CUL))) +#define bM4_DMA1_RPT0_SRPT0 (*((volatile unsigned int*)(0x42A60980UL))) +#define bM4_DMA1_RPT0_SRPT1 (*((volatile unsigned int*)(0x42A60984UL))) +#define bM4_DMA1_RPT0_SRPT2 (*((volatile unsigned int*)(0x42A60988UL))) +#define bM4_DMA1_RPT0_SRPT3 (*((volatile unsigned int*)(0x42A6098CUL))) +#define bM4_DMA1_RPT0_SRPT4 (*((volatile unsigned int*)(0x42A60990UL))) +#define bM4_DMA1_RPT0_SRPT5 (*((volatile unsigned int*)(0x42A60994UL))) +#define bM4_DMA1_RPT0_SRPT6 (*((volatile unsigned int*)(0x42A60998UL))) +#define bM4_DMA1_RPT0_SRPT7 (*((volatile unsigned int*)(0x42A6099CUL))) +#define bM4_DMA1_RPT0_SRPT8 (*((volatile unsigned int*)(0x42A609A0UL))) +#define bM4_DMA1_RPT0_SRPT9 (*((volatile unsigned int*)(0x42A609A4UL))) +#define bM4_DMA1_RPT0_DRPT0 (*((volatile unsigned int*)(0x42A609C0UL))) +#define bM4_DMA1_RPT0_DRPT1 (*((volatile unsigned int*)(0x42A609C4UL))) +#define bM4_DMA1_RPT0_DRPT2 (*((volatile unsigned int*)(0x42A609C8UL))) +#define bM4_DMA1_RPT0_DRPT3 (*((volatile unsigned int*)(0x42A609CCUL))) +#define bM4_DMA1_RPT0_DRPT4 (*((volatile unsigned int*)(0x42A609D0UL))) +#define bM4_DMA1_RPT0_DRPT5 (*((volatile unsigned int*)(0x42A609D4UL))) +#define bM4_DMA1_RPT0_DRPT6 (*((volatile unsigned int*)(0x42A609D8UL))) +#define bM4_DMA1_RPT0_DRPT7 (*((volatile unsigned int*)(0x42A609DCUL))) +#define bM4_DMA1_RPT0_DRPT8 (*((volatile unsigned int*)(0x42A609E0UL))) +#define bM4_DMA1_RPT0_DRPT9 (*((volatile unsigned int*)(0x42A609E4UL))) +#define bM4_DMA1_RPTB0_SRPTB0 (*((volatile unsigned int*)(0x42A60980UL))) +#define bM4_DMA1_RPTB0_SRPTB1 (*((volatile unsigned int*)(0x42A60984UL))) +#define bM4_DMA1_RPTB0_SRPTB2 (*((volatile unsigned int*)(0x42A60988UL))) +#define bM4_DMA1_RPTB0_SRPTB3 (*((volatile unsigned int*)(0x42A6098CUL))) +#define bM4_DMA1_RPTB0_SRPTB4 (*((volatile unsigned int*)(0x42A60990UL))) +#define bM4_DMA1_RPTB0_SRPTB5 (*((volatile unsigned int*)(0x42A60994UL))) +#define bM4_DMA1_RPTB0_SRPTB6 (*((volatile unsigned int*)(0x42A60998UL))) +#define bM4_DMA1_RPTB0_SRPTB7 (*((volatile unsigned int*)(0x42A6099CUL))) +#define bM4_DMA1_RPTB0_SRPTB8 (*((volatile unsigned int*)(0x42A609A0UL))) +#define bM4_DMA1_RPTB0_SRPTB9 (*((volatile unsigned int*)(0x42A609A4UL))) +#define bM4_DMA1_RPTB0_DRPTB0 (*((volatile unsigned int*)(0x42A609C0UL))) +#define bM4_DMA1_RPTB0_DRPTB1 (*((volatile unsigned int*)(0x42A609C4UL))) +#define bM4_DMA1_RPTB0_DRPTB2 (*((volatile unsigned int*)(0x42A609C8UL))) +#define bM4_DMA1_RPTB0_DRPTB3 (*((volatile unsigned int*)(0x42A609CCUL))) +#define bM4_DMA1_RPTB0_DRPTB4 (*((volatile unsigned int*)(0x42A609D0UL))) +#define bM4_DMA1_RPTB0_DRPTB5 (*((volatile unsigned int*)(0x42A609D4UL))) +#define bM4_DMA1_RPTB0_DRPTB6 (*((volatile unsigned int*)(0x42A609D8UL))) +#define bM4_DMA1_RPTB0_DRPTB7 (*((volatile unsigned int*)(0x42A609DCUL))) +#define bM4_DMA1_RPTB0_DRPTB8 (*((volatile unsigned int*)(0x42A609E0UL))) +#define bM4_DMA1_RPTB0_DRPTB9 (*((volatile unsigned int*)(0x42A609E4UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A60A00UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A60A04UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A60A08UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A60A0CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A60A10UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A60A14UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A60A18UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A60A1CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A60A20UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A60A24UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A60A28UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A60A2CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A60A30UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A60A34UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A60A38UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A60A3CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A60A40UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A60A44UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A60A48UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A60A4CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A60A50UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A60A54UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A60A58UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A60A5CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A60A60UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A60A64UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A60A68UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A60A6CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A60A70UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A60A74UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A60A78UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A60A7CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST0 (*((volatile unsigned int*)(0x42A60A00UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST1 (*((volatile unsigned int*)(0x42A60A04UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST2 (*((volatile unsigned int*)(0x42A60A08UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST3 (*((volatile unsigned int*)(0x42A60A0CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST4 (*((volatile unsigned int*)(0x42A60A10UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST5 (*((volatile unsigned int*)(0x42A60A14UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST6 (*((volatile unsigned int*)(0x42A60A18UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST7 (*((volatile unsigned int*)(0x42A60A1CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST8 (*((volatile unsigned int*)(0x42A60A20UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST9 (*((volatile unsigned int*)(0x42A60A24UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST10 (*((volatile unsigned int*)(0x42A60A28UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST11 (*((volatile unsigned int*)(0x42A60A2CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST12 (*((volatile unsigned int*)(0x42A60A30UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST13 (*((volatile unsigned int*)(0x42A60A34UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST14 (*((volatile unsigned int*)(0x42A60A38UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST15 (*((volatile unsigned int*)(0x42A60A3CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST16 (*((volatile unsigned int*)(0x42A60A40UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST17 (*((volatile unsigned int*)(0x42A60A44UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST18 (*((volatile unsigned int*)(0x42A60A48UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST19 (*((volatile unsigned int*)(0x42A60A4CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB0 (*((volatile unsigned int*)(0x42A60A50UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB1 (*((volatile unsigned int*)(0x42A60A54UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB2 (*((volatile unsigned int*)(0x42A60A58UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB3 (*((volatile unsigned int*)(0x42A60A5CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB4 (*((volatile unsigned int*)(0x42A60A60UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB5 (*((volatile unsigned int*)(0x42A60A64UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB6 (*((volatile unsigned int*)(0x42A60A68UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB7 (*((volatile unsigned int*)(0x42A60A6CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB8 (*((volatile unsigned int*)(0x42A60A70UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB9 (*((volatile unsigned int*)(0x42A60A74UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB10 (*((volatile unsigned int*)(0x42A60A78UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB11 (*((volatile unsigned int*)(0x42A60A7CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A60A80UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A60A84UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A60A88UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A60A8CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A60A90UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A60A94UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A60A98UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A60A9CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A60AA0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A60AA4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A60AA8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A60AACUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A60AB0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A60AB4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A60AB8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A60ABCUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A60AC0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A60AC4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A60AC8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A60ACCUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A60AD0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A60AD4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A60AD8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A60ADCUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A60AE0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A60AE4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A60AE8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A60AECUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A60AF0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A60AF4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A60AF8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A60AFCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST0 (*((volatile unsigned int*)(0x42A60A80UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST1 (*((volatile unsigned int*)(0x42A60A84UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST2 (*((volatile unsigned int*)(0x42A60A88UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST3 (*((volatile unsigned int*)(0x42A60A8CUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST4 (*((volatile unsigned int*)(0x42A60A90UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST5 (*((volatile unsigned int*)(0x42A60A94UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST6 (*((volatile unsigned int*)(0x42A60A98UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST7 (*((volatile unsigned int*)(0x42A60A9CUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST8 (*((volatile unsigned int*)(0x42A60AA0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST9 (*((volatile unsigned int*)(0x42A60AA4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST10 (*((volatile unsigned int*)(0x42A60AA8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST11 (*((volatile unsigned int*)(0x42A60AACUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST12 (*((volatile unsigned int*)(0x42A60AB0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST13 (*((volatile unsigned int*)(0x42A60AB4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST14 (*((volatile unsigned int*)(0x42A60AB8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST15 (*((volatile unsigned int*)(0x42A60ABCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST16 (*((volatile unsigned int*)(0x42A60AC0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST17 (*((volatile unsigned int*)(0x42A60AC4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST18 (*((volatile unsigned int*)(0x42A60AC8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST19 (*((volatile unsigned int*)(0x42A60ACCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB0 (*((volatile unsigned int*)(0x42A60AD0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB1 (*((volatile unsigned int*)(0x42A60AD4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB2 (*((volatile unsigned int*)(0x42A60AD8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB3 (*((volatile unsigned int*)(0x42A60ADCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB4 (*((volatile unsigned int*)(0x42A60AE0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB5 (*((volatile unsigned int*)(0x42A60AE4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB6 (*((volatile unsigned int*)(0x42A60AE8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB7 (*((volatile unsigned int*)(0x42A60AECUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB8 (*((volatile unsigned int*)(0x42A60AF0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB9 (*((volatile unsigned int*)(0x42A60AF4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB10 (*((volatile unsigned int*)(0x42A60AF8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB11 (*((volatile unsigned int*)(0x42A60AFCUL))) +#define bM4_DMA1_LLP0_LLP0 (*((volatile unsigned int*)(0x42A60B08UL))) +#define bM4_DMA1_LLP0_LLP1 (*((volatile unsigned int*)(0x42A60B0CUL))) +#define bM4_DMA1_LLP0_LLP2 (*((volatile unsigned int*)(0x42A60B10UL))) +#define bM4_DMA1_LLP0_LLP3 (*((volatile unsigned int*)(0x42A60B14UL))) +#define bM4_DMA1_LLP0_LLP4 (*((volatile unsigned int*)(0x42A60B18UL))) +#define bM4_DMA1_LLP0_LLP5 (*((volatile unsigned int*)(0x42A60B1CUL))) +#define bM4_DMA1_LLP0_LLP6 (*((volatile unsigned int*)(0x42A60B20UL))) +#define bM4_DMA1_LLP0_LLP7 (*((volatile unsigned int*)(0x42A60B24UL))) +#define bM4_DMA1_LLP0_LLP8 (*((volatile unsigned int*)(0x42A60B28UL))) +#define bM4_DMA1_LLP0_LLP9 (*((volatile unsigned int*)(0x42A60B2CUL))) +#define bM4_DMA1_LLP0_LLP10 (*((volatile unsigned int*)(0x42A60B30UL))) +#define bM4_DMA1_LLP0_LLP11 (*((volatile unsigned int*)(0x42A60B34UL))) +#define bM4_DMA1_LLP0_LLP12 (*((volatile unsigned int*)(0x42A60B38UL))) +#define bM4_DMA1_LLP0_LLP13 (*((volatile unsigned int*)(0x42A60B3CUL))) +#define bM4_DMA1_LLP0_LLP14 (*((volatile unsigned int*)(0x42A60B40UL))) +#define bM4_DMA1_LLP0_LLP15 (*((volatile unsigned int*)(0x42A60B44UL))) +#define bM4_DMA1_LLP0_LLP16 (*((volatile unsigned int*)(0x42A60B48UL))) +#define bM4_DMA1_LLP0_LLP17 (*((volatile unsigned int*)(0x42A60B4CUL))) +#define bM4_DMA1_LLP0_LLP18 (*((volatile unsigned int*)(0x42A60B50UL))) +#define bM4_DMA1_LLP0_LLP19 (*((volatile unsigned int*)(0x42A60B54UL))) +#define bM4_DMA1_LLP0_LLP20 (*((volatile unsigned int*)(0x42A60B58UL))) +#define bM4_DMA1_LLP0_LLP21 (*((volatile unsigned int*)(0x42A60B5CUL))) +#define bM4_DMA1_LLP0_LLP22 (*((volatile unsigned int*)(0x42A60B60UL))) +#define bM4_DMA1_LLP0_LLP23 (*((volatile unsigned int*)(0x42A60B64UL))) +#define bM4_DMA1_LLP0_LLP24 (*((volatile unsigned int*)(0x42A60B68UL))) +#define bM4_DMA1_LLP0_LLP25 (*((volatile unsigned int*)(0x42A60B6CUL))) +#define bM4_DMA1_LLP0_LLP26 (*((volatile unsigned int*)(0x42A60B70UL))) +#define bM4_DMA1_LLP0_LLP27 (*((volatile unsigned int*)(0x42A60B74UL))) +#define bM4_DMA1_LLP0_LLP28 (*((volatile unsigned int*)(0x42A60B78UL))) +#define bM4_DMA1_LLP0_LLP29 (*((volatile unsigned int*)(0x42A60B7CUL))) +#define bM4_DMA1_CH0CTL_SINC0 (*((volatile unsigned int*)(0x42A60B80UL))) +#define bM4_DMA1_CH0CTL_SINC1 (*((volatile unsigned int*)(0x42A60B84UL))) +#define bM4_DMA1_CH0CTL_DINC0 (*((volatile unsigned int*)(0x42A60B88UL))) +#define bM4_DMA1_CH0CTL_DINC1 (*((volatile unsigned int*)(0x42A60B8CUL))) +#define bM4_DMA1_CH0CTL_SRPTEN (*((volatile unsigned int*)(0x42A60B90UL))) +#define bM4_DMA1_CH0CTL_DRPTEN (*((volatile unsigned int*)(0x42A60B94UL))) +#define bM4_DMA1_CH0CTL_SNSEQEN (*((volatile unsigned int*)(0x42A60B98UL))) +#define bM4_DMA1_CH0CTL_DNSEQEN (*((volatile unsigned int*)(0x42A60B9CUL))) +#define bM4_DMA1_CH0CTL_HSIZE0 (*((volatile unsigned int*)(0x42A60BA0UL))) +#define bM4_DMA1_CH0CTL_HSIZE1 (*((volatile unsigned int*)(0x42A60BA4UL))) +#define bM4_DMA1_CH0CTL_LLPEN (*((volatile unsigned int*)(0x42A60BA8UL))) +#define bM4_DMA1_CH0CTL_LLPRUN (*((volatile unsigned int*)(0x42A60BACUL))) +#define bM4_DMA1_CH0CTL_IE (*((volatile unsigned int*)(0x42A60BB0UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A60D00UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A60D04UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A60D08UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A60D0CUL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A60D10UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A60D14UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A60D18UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A60D1CUL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A60D20UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A60D24UL))) +#define bM4_DMA1_MONDTCTL0_CNT0 (*((volatile unsigned int*)(0x42A60D40UL))) +#define bM4_DMA1_MONDTCTL0_CNT1 (*((volatile unsigned int*)(0x42A60D44UL))) +#define bM4_DMA1_MONDTCTL0_CNT2 (*((volatile unsigned int*)(0x42A60D48UL))) +#define bM4_DMA1_MONDTCTL0_CNT3 (*((volatile unsigned int*)(0x42A60D4CUL))) +#define bM4_DMA1_MONDTCTL0_CNT4 (*((volatile unsigned int*)(0x42A60D50UL))) +#define bM4_DMA1_MONDTCTL0_CNT5 (*((volatile unsigned int*)(0x42A60D54UL))) +#define bM4_DMA1_MONDTCTL0_CNT6 (*((volatile unsigned int*)(0x42A60D58UL))) +#define bM4_DMA1_MONDTCTL0_CNT7 (*((volatile unsigned int*)(0x42A60D5CUL))) +#define bM4_DMA1_MONDTCTL0_CNT8 (*((volatile unsigned int*)(0x42A60D60UL))) +#define bM4_DMA1_MONDTCTL0_CNT9 (*((volatile unsigned int*)(0x42A60D64UL))) +#define bM4_DMA1_MONDTCTL0_CNT10 (*((volatile unsigned int*)(0x42A60D68UL))) +#define bM4_DMA1_MONDTCTL0_CNT11 (*((volatile unsigned int*)(0x42A60D6CUL))) +#define bM4_DMA1_MONDTCTL0_CNT12 (*((volatile unsigned int*)(0x42A60D70UL))) +#define bM4_DMA1_MONDTCTL0_CNT13 (*((volatile unsigned int*)(0x42A60D74UL))) +#define bM4_DMA1_MONDTCTL0_CNT14 (*((volatile unsigned int*)(0x42A60D78UL))) +#define bM4_DMA1_MONDTCTL0_CNT15 (*((volatile unsigned int*)(0x42A60D7CUL))) +#define bM4_DMA1_MONRPT0_SRPT0 (*((volatile unsigned int*)(0x42A60D80UL))) +#define bM4_DMA1_MONRPT0_SRPT1 (*((volatile unsigned int*)(0x42A60D84UL))) +#define bM4_DMA1_MONRPT0_SRPT2 (*((volatile unsigned int*)(0x42A60D88UL))) +#define bM4_DMA1_MONRPT0_SRPT3 (*((volatile unsigned int*)(0x42A60D8CUL))) +#define bM4_DMA1_MONRPT0_SRPT4 (*((volatile unsigned int*)(0x42A60D90UL))) +#define bM4_DMA1_MONRPT0_SRPT5 (*((volatile unsigned int*)(0x42A60D94UL))) +#define bM4_DMA1_MONRPT0_SRPT6 (*((volatile unsigned int*)(0x42A60D98UL))) +#define bM4_DMA1_MONRPT0_SRPT7 (*((volatile unsigned int*)(0x42A60D9CUL))) +#define bM4_DMA1_MONRPT0_SRPT8 (*((volatile unsigned int*)(0x42A60DA0UL))) +#define bM4_DMA1_MONRPT0_SRPT9 (*((volatile unsigned int*)(0x42A60DA4UL))) +#define bM4_DMA1_MONRPT0_DRPT0 (*((volatile unsigned int*)(0x42A60DC0UL))) +#define bM4_DMA1_MONRPT0_DRPT1 (*((volatile unsigned int*)(0x42A60DC4UL))) +#define bM4_DMA1_MONRPT0_DRPT2 (*((volatile unsigned int*)(0x42A60DC8UL))) +#define bM4_DMA1_MONRPT0_DRPT3 (*((volatile unsigned int*)(0x42A60DCCUL))) +#define bM4_DMA1_MONRPT0_DRPT4 (*((volatile unsigned int*)(0x42A60DD0UL))) +#define bM4_DMA1_MONRPT0_DRPT5 (*((volatile unsigned int*)(0x42A60DD4UL))) +#define bM4_DMA1_MONRPT0_DRPT6 (*((volatile unsigned int*)(0x42A60DD8UL))) +#define bM4_DMA1_MONRPT0_DRPT7 (*((volatile unsigned int*)(0x42A60DDCUL))) +#define bM4_DMA1_MONRPT0_DRPT8 (*((volatile unsigned int*)(0x42A60DE0UL))) +#define bM4_DMA1_MONRPT0_DRPT9 (*((volatile unsigned int*)(0x42A60DE4UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A60E00UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A60E04UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A60E08UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A60E0CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A60E10UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A60E14UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A60E18UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A60E1CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A60E20UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A60E24UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A60E28UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A60E2CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A60E30UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A60E34UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A60E38UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A60E3CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A60E40UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A60E44UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A60E48UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A60E4CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A60E50UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A60E54UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A60E58UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A60E5CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A60E60UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A60E64UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A60E68UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A60E6CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A60E70UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A60E74UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A60E78UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A60E7CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A60E80UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A60E84UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A60E88UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A60E8CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A60E90UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A60E94UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A60E98UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A60E9CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A60EA0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A60EA4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A60EA8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A60EACUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A60EB0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A60EB4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A60EB8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A60EBCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A60EC0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A60EC4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A60EC8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A60ECCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A60ED0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A60ED4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A60ED8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A60EDCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A60EE0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A60EE4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A60EE8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A60EECUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A60EF0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A60EF4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A60EF8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A60EFCUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A61100UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A61104UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A61108UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6110CUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A61110UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A61114UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A61118UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6111CUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A61120UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A61124UL))) +#define bM4_DMA1_DTCTL1_CNT0 (*((volatile unsigned int*)(0x42A61140UL))) +#define bM4_DMA1_DTCTL1_CNT1 (*((volatile unsigned int*)(0x42A61144UL))) +#define bM4_DMA1_DTCTL1_CNT2 (*((volatile unsigned int*)(0x42A61148UL))) +#define bM4_DMA1_DTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6114CUL))) +#define bM4_DMA1_DTCTL1_CNT4 (*((volatile unsigned int*)(0x42A61150UL))) +#define bM4_DMA1_DTCTL1_CNT5 (*((volatile unsigned int*)(0x42A61154UL))) +#define bM4_DMA1_DTCTL1_CNT6 (*((volatile unsigned int*)(0x42A61158UL))) +#define bM4_DMA1_DTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6115CUL))) +#define bM4_DMA1_DTCTL1_CNT8 (*((volatile unsigned int*)(0x42A61160UL))) +#define bM4_DMA1_DTCTL1_CNT9 (*((volatile unsigned int*)(0x42A61164UL))) +#define bM4_DMA1_DTCTL1_CNT10 (*((volatile unsigned int*)(0x42A61168UL))) +#define bM4_DMA1_DTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6116CUL))) +#define bM4_DMA1_DTCTL1_CNT12 (*((volatile unsigned int*)(0x42A61170UL))) +#define bM4_DMA1_DTCTL1_CNT13 (*((volatile unsigned int*)(0x42A61174UL))) +#define bM4_DMA1_DTCTL1_CNT14 (*((volatile unsigned int*)(0x42A61178UL))) +#define bM4_DMA1_DTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6117CUL))) +#define bM4_DMA1_RPT1_SRPT0 (*((volatile unsigned int*)(0x42A61180UL))) +#define bM4_DMA1_RPT1_SRPT1 (*((volatile unsigned int*)(0x42A61184UL))) +#define bM4_DMA1_RPT1_SRPT2 (*((volatile unsigned int*)(0x42A61188UL))) +#define bM4_DMA1_RPT1_SRPT3 (*((volatile unsigned int*)(0x42A6118CUL))) +#define bM4_DMA1_RPT1_SRPT4 (*((volatile unsigned int*)(0x42A61190UL))) +#define bM4_DMA1_RPT1_SRPT5 (*((volatile unsigned int*)(0x42A61194UL))) +#define bM4_DMA1_RPT1_SRPT6 (*((volatile unsigned int*)(0x42A61198UL))) +#define bM4_DMA1_RPT1_SRPT7 (*((volatile unsigned int*)(0x42A6119CUL))) +#define bM4_DMA1_RPT1_SRPT8 (*((volatile unsigned int*)(0x42A611A0UL))) +#define bM4_DMA1_RPT1_SRPT9 (*((volatile unsigned int*)(0x42A611A4UL))) +#define bM4_DMA1_RPT1_DRPT0 (*((volatile unsigned int*)(0x42A611C0UL))) +#define bM4_DMA1_RPT1_DRPT1 (*((volatile unsigned int*)(0x42A611C4UL))) +#define bM4_DMA1_RPT1_DRPT2 (*((volatile unsigned int*)(0x42A611C8UL))) +#define bM4_DMA1_RPT1_DRPT3 (*((volatile unsigned int*)(0x42A611CCUL))) +#define bM4_DMA1_RPT1_DRPT4 (*((volatile unsigned int*)(0x42A611D0UL))) +#define bM4_DMA1_RPT1_DRPT5 (*((volatile unsigned int*)(0x42A611D4UL))) +#define bM4_DMA1_RPT1_DRPT6 (*((volatile unsigned int*)(0x42A611D8UL))) +#define bM4_DMA1_RPT1_DRPT7 (*((volatile unsigned int*)(0x42A611DCUL))) +#define bM4_DMA1_RPT1_DRPT8 (*((volatile unsigned int*)(0x42A611E0UL))) +#define bM4_DMA1_RPT1_DRPT9 (*((volatile unsigned int*)(0x42A611E4UL))) +#define bM4_DMA1_RPTB1_SRPTB0 (*((volatile unsigned int*)(0x42A61180UL))) +#define bM4_DMA1_RPTB1_SRPTB1 (*((volatile unsigned int*)(0x42A61184UL))) +#define bM4_DMA1_RPTB1_SRPTB2 (*((volatile unsigned int*)(0x42A61188UL))) +#define bM4_DMA1_RPTB1_SRPTB3 (*((volatile unsigned int*)(0x42A6118CUL))) +#define bM4_DMA1_RPTB1_SRPTB4 (*((volatile unsigned int*)(0x42A61190UL))) +#define bM4_DMA1_RPTB1_SRPTB5 (*((volatile unsigned int*)(0x42A61194UL))) +#define bM4_DMA1_RPTB1_SRPTB6 (*((volatile unsigned int*)(0x42A61198UL))) +#define bM4_DMA1_RPTB1_SRPTB7 (*((volatile unsigned int*)(0x42A6119CUL))) +#define bM4_DMA1_RPTB1_SRPTB8 (*((volatile unsigned int*)(0x42A611A0UL))) +#define bM4_DMA1_RPTB1_SRPTB9 (*((volatile unsigned int*)(0x42A611A4UL))) +#define bM4_DMA1_RPTB1_DRPTB0 (*((volatile unsigned int*)(0x42A611C0UL))) +#define bM4_DMA1_RPTB1_DRPTB1 (*((volatile unsigned int*)(0x42A611C4UL))) +#define bM4_DMA1_RPTB1_DRPTB2 (*((volatile unsigned int*)(0x42A611C8UL))) +#define bM4_DMA1_RPTB1_DRPTB3 (*((volatile unsigned int*)(0x42A611CCUL))) +#define bM4_DMA1_RPTB1_DRPTB4 (*((volatile unsigned int*)(0x42A611D0UL))) +#define bM4_DMA1_RPTB1_DRPTB5 (*((volatile unsigned int*)(0x42A611D4UL))) +#define bM4_DMA1_RPTB1_DRPTB6 (*((volatile unsigned int*)(0x42A611D8UL))) +#define bM4_DMA1_RPTB1_DRPTB7 (*((volatile unsigned int*)(0x42A611DCUL))) +#define bM4_DMA1_RPTB1_DRPTB8 (*((volatile unsigned int*)(0x42A611E0UL))) +#define bM4_DMA1_RPTB1_DRPTB9 (*((volatile unsigned int*)(0x42A611E4UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A61200UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A61204UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A61208UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6120CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A61210UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A61214UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A61218UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6121CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A61220UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A61224UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A61228UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6122CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A61230UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A61234UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A61238UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6123CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A61240UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A61244UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A61248UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6124CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A61250UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A61254UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A61258UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6125CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A61260UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A61264UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A61268UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6126CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A61270UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A61274UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A61278UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6127CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST0 (*((volatile unsigned int*)(0x42A61200UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST1 (*((volatile unsigned int*)(0x42A61204UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST2 (*((volatile unsigned int*)(0x42A61208UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST3 (*((volatile unsigned int*)(0x42A6120CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST4 (*((volatile unsigned int*)(0x42A61210UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST5 (*((volatile unsigned int*)(0x42A61214UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST6 (*((volatile unsigned int*)(0x42A61218UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST7 (*((volatile unsigned int*)(0x42A6121CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST8 (*((volatile unsigned int*)(0x42A61220UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST9 (*((volatile unsigned int*)(0x42A61224UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST10 (*((volatile unsigned int*)(0x42A61228UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST11 (*((volatile unsigned int*)(0x42A6122CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST12 (*((volatile unsigned int*)(0x42A61230UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST13 (*((volatile unsigned int*)(0x42A61234UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST14 (*((volatile unsigned int*)(0x42A61238UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST15 (*((volatile unsigned int*)(0x42A6123CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST16 (*((volatile unsigned int*)(0x42A61240UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST17 (*((volatile unsigned int*)(0x42A61244UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST18 (*((volatile unsigned int*)(0x42A61248UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST19 (*((volatile unsigned int*)(0x42A6124CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB0 (*((volatile unsigned int*)(0x42A61250UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB1 (*((volatile unsigned int*)(0x42A61254UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB2 (*((volatile unsigned int*)(0x42A61258UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB3 (*((volatile unsigned int*)(0x42A6125CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB4 (*((volatile unsigned int*)(0x42A61260UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB5 (*((volatile unsigned int*)(0x42A61264UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB6 (*((volatile unsigned int*)(0x42A61268UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB7 (*((volatile unsigned int*)(0x42A6126CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB8 (*((volatile unsigned int*)(0x42A61270UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB9 (*((volatile unsigned int*)(0x42A61274UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB10 (*((volatile unsigned int*)(0x42A61278UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB11 (*((volatile unsigned int*)(0x42A6127CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A61280UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A61284UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A61288UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6128CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A61290UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A61294UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A61298UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6129CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A612A0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A612A4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A612A8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A612ACUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A612B0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A612B4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A612B8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A612BCUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A612C0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A612C4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A612C8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A612CCUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A612D0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A612D4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A612D8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A612DCUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A612E0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A612E4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A612E8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A612ECUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A612F0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A612F4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A612F8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A612FCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST0 (*((volatile unsigned int*)(0x42A61280UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST1 (*((volatile unsigned int*)(0x42A61284UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST2 (*((volatile unsigned int*)(0x42A61288UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST3 (*((volatile unsigned int*)(0x42A6128CUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST4 (*((volatile unsigned int*)(0x42A61290UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST5 (*((volatile unsigned int*)(0x42A61294UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST6 (*((volatile unsigned int*)(0x42A61298UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST7 (*((volatile unsigned int*)(0x42A6129CUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST8 (*((volatile unsigned int*)(0x42A612A0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST9 (*((volatile unsigned int*)(0x42A612A4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST10 (*((volatile unsigned int*)(0x42A612A8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST11 (*((volatile unsigned int*)(0x42A612ACUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST12 (*((volatile unsigned int*)(0x42A612B0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST13 (*((volatile unsigned int*)(0x42A612B4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST14 (*((volatile unsigned int*)(0x42A612B8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST15 (*((volatile unsigned int*)(0x42A612BCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST16 (*((volatile unsigned int*)(0x42A612C0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST17 (*((volatile unsigned int*)(0x42A612C4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST18 (*((volatile unsigned int*)(0x42A612C8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST19 (*((volatile unsigned int*)(0x42A612CCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB0 (*((volatile unsigned int*)(0x42A612D0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB1 (*((volatile unsigned int*)(0x42A612D4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB2 (*((volatile unsigned int*)(0x42A612D8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB3 (*((volatile unsigned int*)(0x42A612DCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB4 (*((volatile unsigned int*)(0x42A612E0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB5 (*((volatile unsigned int*)(0x42A612E4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB6 (*((volatile unsigned int*)(0x42A612E8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB7 (*((volatile unsigned int*)(0x42A612ECUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB8 (*((volatile unsigned int*)(0x42A612F0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB9 (*((volatile unsigned int*)(0x42A612F4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB10 (*((volatile unsigned int*)(0x42A612F8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB11 (*((volatile unsigned int*)(0x42A612FCUL))) +#define bM4_DMA1_LLP1_LLP0 (*((volatile unsigned int*)(0x42A61308UL))) +#define bM4_DMA1_LLP1_LLP1 (*((volatile unsigned int*)(0x42A6130CUL))) +#define bM4_DMA1_LLP1_LLP2 (*((volatile unsigned int*)(0x42A61310UL))) +#define bM4_DMA1_LLP1_LLP3 (*((volatile unsigned int*)(0x42A61314UL))) +#define bM4_DMA1_LLP1_LLP4 (*((volatile unsigned int*)(0x42A61318UL))) +#define bM4_DMA1_LLP1_LLP5 (*((volatile unsigned int*)(0x42A6131CUL))) +#define bM4_DMA1_LLP1_LLP6 (*((volatile unsigned int*)(0x42A61320UL))) +#define bM4_DMA1_LLP1_LLP7 (*((volatile unsigned int*)(0x42A61324UL))) +#define bM4_DMA1_LLP1_LLP8 (*((volatile unsigned int*)(0x42A61328UL))) +#define bM4_DMA1_LLP1_LLP9 (*((volatile unsigned int*)(0x42A6132CUL))) +#define bM4_DMA1_LLP1_LLP10 (*((volatile unsigned int*)(0x42A61330UL))) +#define bM4_DMA1_LLP1_LLP11 (*((volatile unsigned int*)(0x42A61334UL))) +#define bM4_DMA1_LLP1_LLP12 (*((volatile unsigned int*)(0x42A61338UL))) +#define bM4_DMA1_LLP1_LLP13 (*((volatile unsigned int*)(0x42A6133CUL))) +#define bM4_DMA1_LLP1_LLP14 (*((volatile unsigned int*)(0x42A61340UL))) +#define bM4_DMA1_LLP1_LLP15 (*((volatile unsigned int*)(0x42A61344UL))) +#define bM4_DMA1_LLP1_LLP16 (*((volatile unsigned int*)(0x42A61348UL))) +#define bM4_DMA1_LLP1_LLP17 (*((volatile unsigned int*)(0x42A6134CUL))) +#define bM4_DMA1_LLP1_LLP18 (*((volatile unsigned int*)(0x42A61350UL))) +#define bM4_DMA1_LLP1_LLP19 (*((volatile unsigned int*)(0x42A61354UL))) +#define bM4_DMA1_LLP1_LLP20 (*((volatile unsigned int*)(0x42A61358UL))) +#define bM4_DMA1_LLP1_LLP21 (*((volatile unsigned int*)(0x42A6135CUL))) +#define bM4_DMA1_LLP1_LLP22 (*((volatile unsigned int*)(0x42A61360UL))) +#define bM4_DMA1_LLP1_LLP23 (*((volatile unsigned int*)(0x42A61364UL))) +#define bM4_DMA1_LLP1_LLP24 (*((volatile unsigned int*)(0x42A61368UL))) +#define bM4_DMA1_LLP1_LLP25 (*((volatile unsigned int*)(0x42A6136CUL))) +#define bM4_DMA1_LLP1_LLP26 (*((volatile unsigned int*)(0x42A61370UL))) +#define bM4_DMA1_LLP1_LLP27 (*((volatile unsigned int*)(0x42A61374UL))) +#define bM4_DMA1_LLP1_LLP28 (*((volatile unsigned int*)(0x42A61378UL))) +#define bM4_DMA1_LLP1_LLP29 (*((volatile unsigned int*)(0x42A6137CUL))) +#define bM4_DMA1_CH1CTL_SINC0 (*((volatile unsigned int*)(0x42A61380UL))) +#define bM4_DMA1_CH1CTL_SINC1 (*((volatile unsigned int*)(0x42A61384UL))) +#define bM4_DMA1_CH1CTL_DINC0 (*((volatile unsigned int*)(0x42A61388UL))) +#define bM4_DMA1_CH1CTL_DINC1 (*((volatile unsigned int*)(0x42A6138CUL))) +#define bM4_DMA1_CH1CTL_SRPTEN (*((volatile unsigned int*)(0x42A61390UL))) +#define bM4_DMA1_CH1CTL_DRPTEN (*((volatile unsigned int*)(0x42A61394UL))) +#define bM4_DMA1_CH1CTL_SNSEQEN (*((volatile unsigned int*)(0x42A61398UL))) +#define bM4_DMA1_CH1CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6139CUL))) +#define bM4_DMA1_CH1CTL_HSIZE0 (*((volatile unsigned int*)(0x42A613A0UL))) +#define bM4_DMA1_CH1CTL_HSIZE1 (*((volatile unsigned int*)(0x42A613A4UL))) +#define bM4_DMA1_CH1CTL_LLPEN (*((volatile unsigned int*)(0x42A613A8UL))) +#define bM4_DMA1_CH1CTL_LLPRUN (*((volatile unsigned int*)(0x42A613ACUL))) +#define bM4_DMA1_CH1CTL_IE (*((volatile unsigned int*)(0x42A613B0UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A61500UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A61504UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A61508UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6150CUL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A61510UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A61514UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A61518UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6151CUL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A61520UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A61524UL))) +#define bM4_DMA1_MONDTCTL1_CNT0 (*((volatile unsigned int*)(0x42A61540UL))) +#define bM4_DMA1_MONDTCTL1_CNT1 (*((volatile unsigned int*)(0x42A61544UL))) +#define bM4_DMA1_MONDTCTL1_CNT2 (*((volatile unsigned int*)(0x42A61548UL))) +#define bM4_DMA1_MONDTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6154CUL))) +#define bM4_DMA1_MONDTCTL1_CNT4 (*((volatile unsigned int*)(0x42A61550UL))) +#define bM4_DMA1_MONDTCTL1_CNT5 (*((volatile unsigned int*)(0x42A61554UL))) +#define bM4_DMA1_MONDTCTL1_CNT6 (*((volatile unsigned int*)(0x42A61558UL))) +#define bM4_DMA1_MONDTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6155CUL))) +#define bM4_DMA1_MONDTCTL1_CNT8 (*((volatile unsigned int*)(0x42A61560UL))) +#define bM4_DMA1_MONDTCTL1_CNT9 (*((volatile unsigned int*)(0x42A61564UL))) +#define bM4_DMA1_MONDTCTL1_CNT10 (*((volatile unsigned int*)(0x42A61568UL))) +#define bM4_DMA1_MONDTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6156CUL))) +#define bM4_DMA1_MONDTCTL1_CNT12 (*((volatile unsigned int*)(0x42A61570UL))) +#define bM4_DMA1_MONDTCTL1_CNT13 (*((volatile unsigned int*)(0x42A61574UL))) +#define bM4_DMA1_MONDTCTL1_CNT14 (*((volatile unsigned int*)(0x42A61578UL))) +#define bM4_DMA1_MONDTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6157CUL))) +#define bM4_DMA1_MONRPT1_SRPT0 (*((volatile unsigned int*)(0x42A61580UL))) +#define bM4_DMA1_MONRPT1_SRPT1 (*((volatile unsigned int*)(0x42A61584UL))) +#define bM4_DMA1_MONRPT1_SRPT2 (*((volatile unsigned int*)(0x42A61588UL))) +#define bM4_DMA1_MONRPT1_SRPT3 (*((volatile unsigned int*)(0x42A6158CUL))) +#define bM4_DMA1_MONRPT1_SRPT4 (*((volatile unsigned int*)(0x42A61590UL))) +#define bM4_DMA1_MONRPT1_SRPT5 (*((volatile unsigned int*)(0x42A61594UL))) +#define bM4_DMA1_MONRPT1_SRPT6 (*((volatile unsigned int*)(0x42A61598UL))) +#define bM4_DMA1_MONRPT1_SRPT7 (*((volatile unsigned int*)(0x42A6159CUL))) +#define bM4_DMA1_MONRPT1_SRPT8 (*((volatile unsigned int*)(0x42A615A0UL))) +#define bM4_DMA1_MONRPT1_SRPT9 (*((volatile unsigned int*)(0x42A615A4UL))) +#define bM4_DMA1_MONRPT1_DRPT0 (*((volatile unsigned int*)(0x42A615C0UL))) +#define bM4_DMA1_MONRPT1_DRPT1 (*((volatile unsigned int*)(0x42A615C4UL))) +#define bM4_DMA1_MONRPT1_DRPT2 (*((volatile unsigned int*)(0x42A615C8UL))) +#define bM4_DMA1_MONRPT1_DRPT3 (*((volatile unsigned int*)(0x42A615CCUL))) +#define bM4_DMA1_MONRPT1_DRPT4 (*((volatile unsigned int*)(0x42A615D0UL))) +#define bM4_DMA1_MONRPT1_DRPT5 (*((volatile unsigned int*)(0x42A615D4UL))) +#define bM4_DMA1_MONRPT1_DRPT6 (*((volatile unsigned int*)(0x42A615D8UL))) +#define bM4_DMA1_MONRPT1_DRPT7 (*((volatile unsigned int*)(0x42A615DCUL))) +#define bM4_DMA1_MONRPT1_DRPT8 (*((volatile unsigned int*)(0x42A615E0UL))) +#define bM4_DMA1_MONRPT1_DRPT9 (*((volatile unsigned int*)(0x42A615E4UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A61600UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A61604UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A61608UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6160CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A61610UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A61614UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A61618UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6161CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A61620UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A61624UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A61628UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6162CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A61630UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A61634UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A61638UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6163CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A61640UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A61644UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A61648UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6164CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A61650UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A61654UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A61658UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6165CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A61660UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A61664UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A61668UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6166CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A61670UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A61674UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A61678UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6167CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A61680UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A61684UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A61688UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6168CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A61690UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A61694UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A61698UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6169CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A616A0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A616A4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A616A8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A616ACUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A616B0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A616B4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A616B8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A616BCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A616C0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A616C4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A616C8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A616CCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A616D0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A616D4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A616D8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A616DCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A616E0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A616E4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A616E8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A616ECUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A616F0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A616F4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A616F8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A616FCUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A61900UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A61904UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A61908UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A6190CUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A61910UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A61914UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A61918UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A6191CUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A61920UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A61924UL))) +#define bM4_DMA1_DTCTL2_CNT0 (*((volatile unsigned int*)(0x42A61940UL))) +#define bM4_DMA1_DTCTL2_CNT1 (*((volatile unsigned int*)(0x42A61944UL))) +#define bM4_DMA1_DTCTL2_CNT2 (*((volatile unsigned int*)(0x42A61948UL))) +#define bM4_DMA1_DTCTL2_CNT3 (*((volatile unsigned int*)(0x42A6194CUL))) +#define bM4_DMA1_DTCTL2_CNT4 (*((volatile unsigned int*)(0x42A61950UL))) +#define bM4_DMA1_DTCTL2_CNT5 (*((volatile unsigned int*)(0x42A61954UL))) +#define bM4_DMA1_DTCTL2_CNT6 (*((volatile unsigned int*)(0x42A61958UL))) +#define bM4_DMA1_DTCTL2_CNT7 (*((volatile unsigned int*)(0x42A6195CUL))) +#define bM4_DMA1_DTCTL2_CNT8 (*((volatile unsigned int*)(0x42A61960UL))) +#define bM4_DMA1_DTCTL2_CNT9 (*((volatile unsigned int*)(0x42A61964UL))) +#define bM4_DMA1_DTCTL2_CNT10 (*((volatile unsigned int*)(0x42A61968UL))) +#define bM4_DMA1_DTCTL2_CNT11 (*((volatile unsigned int*)(0x42A6196CUL))) +#define bM4_DMA1_DTCTL2_CNT12 (*((volatile unsigned int*)(0x42A61970UL))) +#define bM4_DMA1_DTCTL2_CNT13 (*((volatile unsigned int*)(0x42A61974UL))) +#define bM4_DMA1_DTCTL2_CNT14 (*((volatile unsigned int*)(0x42A61978UL))) +#define bM4_DMA1_DTCTL2_CNT15 (*((volatile unsigned int*)(0x42A6197CUL))) +#define bM4_DMA1_RPT2_SRPT0 (*((volatile unsigned int*)(0x42A61980UL))) +#define bM4_DMA1_RPT2_SRPT1 (*((volatile unsigned int*)(0x42A61984UL))) +#define bM4_DMA1_RPT2_SRPT2 (*((volatile unsigned int*)(0x42A61988UL))) +#define bM4_DMA1_RPT2_SRPT3 (*((volatile unsigned int*)(0x42A6198CUL))) +#define bM4_DMA1_RPT2_SRPT4 (*((volatile unsigned int*)(0x42A61990UL))) +#define bM4_DMA1_RPT2_SRPT5 (*((volatile unsigned int*)(0x42A61994UL))) +#define bM4_DMA1_RPT2_SRPT6 (*((volatile unsigned int*)(0x42A61998UL))) +#define bM4_DMA1_RPT2_SRPT7 (*((volatile unsigned int*)(0x42A6199CUL))) +#define bM4_DMA1_RPT2_SRPT8 (*((volatile unsigned int*)(0x42A619A0UL))) +#define bM4_DMA1_RPT2_SRPT9 (*((volatile unsigned int*)(0x42A619A4UL))) +#define bM4_DMA1_RPT2_DRPT0 (*((volatile unsigned int*)(0x42A619C0UL))) +#define bM4_DMA1_RPT2_DRPT1 (*((volatile unsigned int*)(0x42A619C4UL))) +#define bM4_DMA1_RPT2_DRPT2 (*((volatile unsigned int*)(0x42A619C8UL))) +#define bM4_DMA1_RPT2_DRPT3 (*((volatile unsigned int*)(0x42A619CCUL))) +#define bM4_DMA1_RPT2_DRPT4 (*((volatile unsigned int*)(0x42A619D0UL))) +#define bM4_DMA1_RPT2_DRPT5 (*((volatile unsigned int*)(0x42A619D4UL))) +#define bM4_DMA1_RPT2_DRPT6 (*((volatile unsigned int*)(0x42A619D8UL))) +#define bM4_DMA1_RPT2_DRPT7 (*((volatile unsigned int*)(0x42A619DCUL))) +#define bM4_DMA1_RPT2_DRPT8 (*((volatile unsigned int*)(0x42A619E0UL))) +#define bM4_DMA1_RPT2_DRPT9 (*((volatile unsigned int*)(0x42A619E4UL))) +#define bM4_DMA1_RPTB2_SRPTB0 (*((volatile unsigned int*)(0x42A61980UL))) +#define bM4_DMA1_RPTB2_SRPTB1 (*((volatile unsigned int*)(0x42A61984UL))) +#define bM4_DMA1_RPTB2_SRPTB2 (*((volatile unsigned int*)(0x42A61988UL))) +#define bM4_DMA1_RPTB2_SRPTB3 (*((volatile unsigned int*)(0x42A6198CUL))) +#define bM4_DMA1_RPTB2_SRPTB4 (*((volatile unsigned int*)(0x42A61990UL))) +#define bM4_DMA1_RPTB2_SRPTB5 (*((volatile unsigned int*)(0x42A61994UL))) +#define bM4_DMA1_RPTB2_SRPTB6 (*((volatile unsigned int*)(0x42A61998UL))) +#define bM4_DMA1_RPTB2_SRPTB7 (*((volatile unsigned int*)(0x42A6199CUL))) +#define bM4_DMA1_RPTB2_SRPTB8 (*((volatile unsigned int*)(0x42A619A0UL))) +#define bM4_DMA1_RPTB2_SRPTB9 (*((volatile unsigned int*)(0x42A619A4UL))) +#define bM4_DMA1_RPTB2_DRPTB0 (*((volatile unsigned int*)(0x42A619C0UL))) +#define bM4_DMA1_RPTB2_DRPTB1 (*((volatile unsigned int*)(0x42A619C4UL))) +#define bM4_DMA1_RPTB2_DRPTB2 (*((volatile unsigned int*)(0x42A619C8UL))) +#define bM4_DMA1_RPTB2_DRPTB3 (*((volatile unsigned int*)(0x42A619CCUL))) +#define bM4_DMA1_RPTB2_DRPTB4 (*((volatile unsigned int*)(0x42A619D0UL))) +#define bM4_DMA1_RPTB2_DRPTB5 (*((volatile unsigned int*)(0x42A619D4UL))) +#define bM4_DMA1_RPTB2_DRPTB6 (*((volatile unsigned int*)(0x42A619D8UL))) +#define bM4_DMA1_RPTB2_DRPTB7 (*((volatile unsigned int*)(0x42A619DCUL))) +#define bM4_DMA1_RPTB2_DRPTB8 (*((volatile unsigned int*)(0x42A619E0UL))) +#define bM4_DMA1_RPTB2_DRPTB9 (*((volatile unsigned int*)(0x42A619E4UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A61A00UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A61A04UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A61A08UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A61A0CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A61A10UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A61A14UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A61A18UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A61A1CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A61A20UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A61A24UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A61A28UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A61A2CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A61A30UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A61A34UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A61A38UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A61A3CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A61A40UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A61A44UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A61A48UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A61A4CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A61A50UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A61A54UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A61A58UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A61A5CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A61A60UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A61A64UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A61A68UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A61A6CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A61A70UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A61A74UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A61A78UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A61A7CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST0 (*((volatile unsigned int*)(0x42A61A00UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST1 (*((volatile unsigned int*)(0x42A61A04UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST2 (*((volatile unsigned int*)(0x42A61A08UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST3 (*((volatile unsigned int*)(0x42A61A0CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST4 (*((volatile unsigned int*)(0x42A61A10UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST5 (*((volatile unsigned int*)(0x42A61A14UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST6 (*((volatile unsigned int*)(0x42A61A18UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST7 (*((volatile unsigned int*)(0x42A61A1CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST8 (*((volatile unsigned int*)(0x42A61A20UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST9 (*((volatile unsigned int*)(0x42A61A24UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST10 (*((volatile unsigned int*)(0x42A61A28UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST11 (*((volatile unsigned int*)(0x42A61A2CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST12 (*((volatile unsigned int*)(0x42A61A30UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST13 (*((volatile unsigned int*)(0x42A61A34UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST14 (*((volatile unsigned int*)(0x42A61A38UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST15 (*((volatile unsigned int*)(0x42A61A3CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST16 (*((volatile unsigned int*)(0x42A61A40UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST17 (*((volatile unsigned int*)(0x42A61A44UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST18 (*((volatile unsigned int*)(0x42A61A48UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST19 (*((volatile unsigned int*)(0x42A61A4CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB0 (*((volatile unsigned int*)(0x42A61A50UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB1 (*((volatile unsigned int*)(0x42A61A54UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB2 (*((volatile unsigned int*)(0x42A61A58UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB3 (*((volatile unsigned int*)(0x42A61A5CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB4 (*((volatile unsigned int*)(0x42A61A60UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB5 (*((volatile unsigned int*)(0x42A61A64UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB6 (*((volatile unsigned int*)(0x42A61A68UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB7 (*((volatile unsigned int*)(0x42A61A6CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB8 (*((volatile unsigned int*)(0x42A61A70UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB9 (*((volatile unsigned int*)(0x42A61A74UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB10 (*((volatile unsigned int*)(0x42A61A78UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB11 (*((volatile unsigned int*)(0x42A61A7CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A61A80UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A61A84UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A61A88UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A61A8CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A61A90UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A61A94UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A61A98UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A61A9CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A61AA0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A61AA4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A61AA8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A61AACUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A61AB0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A61AB4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A61AB8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A61ABCUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A61AC0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A61AC4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A61AC8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A61ACCUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A61AD0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A61AD4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A61AD8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A61ADCUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A61AE0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A61AE4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A61AE8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A61AECUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A61AF0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A61AF4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A61AF8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A61AFCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST0 (*((volatile unsigned int*)(0x42A61A80UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST1 (*((volatile unsigned int*)(0x42A61A84UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST2 (*((volatile unsigned int*)(0x42A61A88UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST3 (*((volatile unsigned int*)(0x42A61A8CUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST4 (*((volatile unsigned int*)(0x42A61A90UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST5 (*((volatile unsigned int*)(0x42A61A94UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST6 (*((volatile unsigned int*)(0x42A61A98UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST7 (*((volatile unsigned int*)(0x42A61A9CUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST8 (*((volatile unsigned int*)(0x42A61AA0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST9 (*((volatile unsigned int*)(0x42A61AA4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST10 (*((volatile unsigned int*)(0x42A61AA8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST11 (*((volatile unsigned int*)(0x42A61AACUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST12 (*((volatile unsigned int*)(0x42A61AB0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST13 (*((volatile unsigned int*)(0x42A61AB4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST14 (*((volatile unsigned int*)(0x42A61AB8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST15 (*((volatile unsigned int*)(0x42A61ABCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST16 (*((volatile unsigned int*)(0x42A61AC0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST17 (*((volatile unsigned int*)(0x42A61AC4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST18 (*((volatile unsigned int*)(0x42A61AC8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST19 (*((volatile unsigned int*)(0x42A61ACCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB0 (*((volatile unsigned int*)(0x42A61AD0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB1 (*((volatile unsigned int*)(0x42A61AD4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB2 (*((volatile unsigned int*)(0x42A61AD8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB3 (*((volatile unsigned int*)(0x42A61ADCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB4 (*((volatile unsigned int*)(0x42A61AE0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB5 (*((volatile unsigned int*)(0x42A61AE4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB6 (*((volatile unsigned int*)(0x42A61AE8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB7 (*((volatile unsigned int*)(0x42A61AECUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB8 (*((volatile unsigned int*)(0x42A61AF0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB9 (*((volatile unsigned int*)(0x42A61AF4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB10 (*((volatile unsigned int*)(0x42A61AF8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB11 (*((volatile unsigned int*)(0x42A61AFCUL))) +#define bM4_DMA1_LLP2_LLP0 (*((volatile unsigned int*)(0x42A61B08UL))) +#define bM4_DMA1_LLP2_LLP1 (*((volatile unsigned int*)(0x42A61B0CUL))) +#define bM4_DMA1_LLP2_LLP2 (*((volatile unsigned int*)(0x42A61B10UL))) +#define bM4_DMA1_LLP2_LLP3 (*((volatile unsigned int*)(0x42A61B14UL))) +#define bM4_DMA1_LLP2_LLP4 (*((volatile unsigned int*)(0x42A61B18UL))) +#define bM4_DMA1_LLP2_LLP5 (*((volatile unsigned int*)(0x42A61B1CUL))) +#define bM4_DMA1_LLP2_LLP6 (*((volatile unsigned int*)(0x42A61B20UL))) +#define bM4_DMA1_LLP2_LLP7 (*((volatile unsigned int*)(0x42A61B24UL))) +#define bM4_DMA1_LLP2_LLP8 (*((volatile unsigned int*)(0x42A61B28UL))) +#define bM4_DMA1_LLP2_LLP9 (*((volatile unsigned int*)(0x42A61B2CUL))) +#define bM4_DMA1_LLP2_LLP10 (*((volatile unsigned int*)(0x42A61B30UL))) +#define bM4_DMA1_LLP2_LLP11 (*((volatile unsigned int*)(0x42A61B34UL))) +#define bM4_DMA1_LLP2_LLP12 (*((volatile unsigned int*)(0x42A61B38UL))) +#define bM4_DMA1_LLP2_LLP13 (*((volatile unsigned int*)(0x42A61B3CUL))) +#define bM4_DMA1_LLP2_LLP14 (*((volatile unsigned int*)(0x42A61B40UL))) +#define bM4_DMA1_LLP2_LLP15 (*((volatile unsigned int*)(0x42A61B44UL))) +#define bM4_DMA1_LLP2_LLP16 (*((volatile unsigned int*)(0x42A61B48UL))) +#define bM4_DMA1_LLP2_LLP17 (*((volatile unsigned int*)(0x42A61B4CUL))) +#define bM4_DMA1_LLP2_LLP18 (*((volatile unsigned int*)(0x42A61B50UL))) +#define bM4_DMA1_LLP2_LLP19 (*((volatile unsigned int*)(0x42A61B54UL))) +#define bM4_DMA1_LLP2_LLP20 (*((volatile unsigned int*)(0x42A61B58UL))) +#define bM4_DMA1_LLP2_LLP21 (*((volatile unsigned int*)(0x42A61B5CUL))) +#define bM4_DMA1_LLP2_LLP22 (*((volatile unsigned int*)(0x42A61B60UL))) +#define bM4_DMA1_LLP2_LLP23 (*((volatile unsigned int*)(0x42A61B64UL))) +#define bM4_DMA1_LLP2_LLP24 (*((volatile unsigned int*)(0x42A61B68UL))) +#define bM4_DMA1_LLP2_LLP25 (*((volatile unsigned int*)(0x42A61B6CUL))) +#define bM4_DMA1_LLP2_LLP26 (*((volatile unsigned int*)(0x42A61B70UL))) +#define bM4_DMA1_LLP2_LLP27 (*((volatile unsigned int*)(0x42A61B74UL))) +#define bM4_DMA1_LLP2_LLP28 (*((volatile unsigned int*)(0x42A61B78UL))) +#define bM4_DMA1_LLP2_LLP29 (*((volatile unsigned int*)(0x42A61B7CUL))) +#define bM4_DMA1_CH2CTL_SINC0 (*((volatile unsigned int*)(0x42A61B80UL))) +#define bM4_DMA1_CH2CTL_SINC1 (*((volatile unsigned int*)(0x42A61B84UL))) +#define bM4_DMA1_CH2CTL_DINC0 (*((volatile unsigned int*)(0x42A61B88UL))) +#define bM4_DMA1_CH2CTL_DINC1 (*((volatile unsigned int*)(0x42A61B8CUL))) +#define bM4_DMA1_CH2CTL_SRPTEN (*((volatile unsigned int*)(0x42A61B90UL))) +#define bM4_DMA1_CH2CTL_DRPTEN (*((volatile unsigned int*)(0x42A61B94UL))) +#define bM4_DMA1_CH2CTL_SNSEQEN (*((volatile unsigned int*)(0x42A61B98UL))) +#define bM4_DMA1_CH2CTL_DNSEQEN (*((volatile unsigned int*)(0x42A61B9CUL))) +#define bM4_DMA1_CH2CTL_HSIZE0 (*((volatile unsigned int*)(0x42A61BA0UL))) +#define bM4_DMA1_CH2CTL_HSIZE1 (*((volatile unsigned int*)(0x42A61BA4UL))) +#define bM4_DMA1_CH2CTL_LLPEN (*((volatile unsigned int*)(0x42A61BA8UL))) +#define bM4_DMA1_CH2CTL_LLPRUN (*((volatile unsigned int*)(0x42A61BACUL))) +#define bM4_DMA1_CH2CTL_IE (*((volatile unsigned int*)(0x42A61BB0UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A61D00UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A61D04UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A61D08UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A61D0CUL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A61D10UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A61D14UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A61D18UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A61D1CUL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A61D20UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A61D24UL))) +#define bM4_DMA1_MONDTCTL2_CNT0 (*((volatile unsigned int*)(0x42A61D40UL))) +#define bM4_DMA1_MONDTCTL2_CNT1 (*((volatile unsigned int*)(0x42A61D44UL))) +#define bM4_DMA1_MONDTCTL2_CNT2 (*((volatile unsigned int*)(0x42A61D48UL))) +#define bM4_DMA1_MONDTCTL2_CNT3 (*((volatile unsigned int*)(0x42A61D4CUL))) +#define bM4_DMA1_MONDTCTL2_CNT4 (*((volatile unsigned int*)(0x42A61D50UL))) +#define bM4_DMA1_MONDTCTL2_CNT5 (*((volatile unsigned int*)(0x42A61D54UL))) +#define bM4_DMA1_MONDTCTL2_CNT6 (*((volatile unsigned int*)(0x42A61D58UL))) +#define bM4_DMA1_MONDTCTL2_CNT7 (*((volatile unsigned int*)(0x42A61D5CUL))) +#define bM4_DMA1_MONDTCTL2_CNT8 (*((volatile unsigned int*)(0x42A61D60UL))) +#define bM4_DMA1_MONDTCTL2_CNT9 (*((volatile unsigned int*)(0x42A61D64UL))) +#define bM4_DMA1_MONDTCTL2_CNT10 (*((volatile unsigned int*)(0x42A61D68UL))) +#define bM4_DMA1_MONDTCTL2_CNT11 (*((volatile unsigned int*)(0x42A61D6CUL))) +#define bM4_DMA1_MONDTCTL2_CNT12 (*((volatile unsigned int*)(0x42A61D70UL))) +#define bM4_DMA1_MONDTCTL2_CNT13 (*((volatile unsigned int*)(0x42A61D74UL))) +#define bM4_DMA1_MONDTCTL2_CNT14 (*((volatile unsigned int*)(0x42A61D78UL))) +#define bM4_DMA1_MONDTCTL2_CNT15 (*((volatile unsigned int*)(0x42A61D7CUL))) +#define bM4_DMA1_MONRPT2_SRPT0 (*((volatile unsigned int*)(0x42A61D80UL))) +#define bM4_DMA1_MONRPT2_SRPT1 (*((volatile unsigned int*)(0x42A61D84UL))) +#define bM4_DMA1_MONRPT2_SRPT2 (*((volatile unsigned int*)(0x42A61D88UL))) +#define bM4_DMA1_MONRPT2_SRPT3 (*((volatile unsigned int*)(0x42A61D8CUL))) +#define bM4_DMA1_MONRPT2_SRPT4 (*((volatile unsigned int*)(0x42A61D90UL))) +#define bM4_DMA1_MONRPT2_SRPT5 (*((volatile unsigned int*)(0x42A61D94UL))) +#define bM4_DMA1_MONRPT2_SRPT6 (*((volatile unsigned int*)(0x42A61D98UL))) +#define bM4_DMA1_MONRPT2_SRPT7 (*((volatile unsigned int*)(0x42A61D9CUL))) +#define bM4_DMA1_MONRPT2_SRPT8 (*((volatile unsigned int*)(0x42A61DA0UL))) +#define bM4_DMA1_MONRPT2_SRPT9 (*((volatile unsigned int*)(0x42A61DA4UL))) +#define bM4_DMA1_MONRPT2_DRPT0 (*((volatile unsigned int*)(0x42A61DC0UL))) +#define bM4_DMA1_MONRPT2_DRPT1 (*((volatile unsigned int*)(0x42A61DC4UL))) +#define bM4_DMA1_MONRPT2_DRPT2 (*((volatile unsigned int*)(0x42A61DC8UL))) +#define bM4_DMA1_MONRPT2_DRPT3 (*((volatile unsigned int*)(0x42A61DCCUL))) +#define bM4_DMA1_MONRPT2_DRPT4 (*((volatile unsigned int*)(0x42A61DD0UL))) +#define bM4_DMA1_MONRPT2_DRPT5 (*((volatile unsigned int*)(0x42A61DD4UL))) +#define bM4_DMA1_MONRPT2_DRPT6 (*((volatile unsigned int*)(0x42A61DD8UL))) +#define bM4_DMA1_MONRPT2_DRPT7 (*((volatile unsigned int*)(0x42A61DDCUL))) +#define bM4_DMA1_MONRPT2_DRPT8 (*((volatile unsigned int*)(0x42A61DE0UL))) +#define bM4_DMA1_MONRPT2_DRPT9 (*((volatile unsigned int*)(0x42A61DE4UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A61E00UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A61E04UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A61E08UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A61E0CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A61E10UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A61E14UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A61E18UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A61E1CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A61E20UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A61E24UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A61E28UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A61E2CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A61E30UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A61E34UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A61E38UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A61E3CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A61E40UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A61E44UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A61E48UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A61E4CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A61E50UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A61E54UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A61E58UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A61E5CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A61E60UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A61E64UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A61E68UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A61E6CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A61E70UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A61E74UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A61E78UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A61E7CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A61E80UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A61E84UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A61E88UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A61E8CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A61E90UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A61E94UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A61E98UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A61E9CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A61EA0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A61EA4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A61EA8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A61EACUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A61EB0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A61EB4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A61EB8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A61EBCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A61EC0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A61EC4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A61EC8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A61ECCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A61ED0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A61ED4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A61ED8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A61EDCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A61EE0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A61EE4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A61EE8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A61EECUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A61EF0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A61EF4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A61EF8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A61EFCUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A62100UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A62104UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A62108UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6210CUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A62110UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A62114UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A62118UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6211CUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A62120UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A62124UL))) +#define bM4_DMA1_DTCTL3_CNT0 (*((volatile unsigned int*)(0x42A62140UL))) +#define bM4_DMA1_DTCTL3_CNT1 (*((volatile unsigned int*)(0x42A62144UL))) +#define bM4_DMA1_DTCTL3_CNT2 (*((volatile unsigned int*)(0x42A62148UL))) +#define bM4_DMA1_DTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6214CUL))) +#define bM4_DMA1_DTCTL3_CNT4 (*((volatile unsigned int*)(0x42A62150UL))) +#define bM4_DMA1_DTCTL3_CNT5 (*((volatile unsigned int*)(0x42A62154UL))) +#define bM4_DMA1_DTCTL3_CNT6 (*((volatile unsigned int*)(0x42A62158UL))) +#define bM4_DMA1_DTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6215CUL))) +#define bM4_DMA1_DTCTL3_CNT8 (*((volatile unsigned int*)(0x42A62160UL))) +#define bM4_DMA1_DTCTL3_CNT9 (*((volatile unsigned int*)(0x42A62164UL))) +#define bM4_DMA1_DTCTL3_CNT10 (*((volatile unsigned int*)(0x42A62168UL))) +#define bM4_DMA1_DTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6216CUL))) +#define bM4_DMA1_DTCTL3_CNT12 (*((volatile unsigned int*)(0x42A62170UL))) +#define bM4_DMA1_DTCTL3_CNT13 (*((volatile unsigned int*)(0x42A62174UL))) +#define bM4_DMA1_DTCTL3_CNT14 (*((volatile unsigned int*)(0x42A62178UL))) +#define bM4_DMA1_DTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6217CUL))) +#define bM4_DMA1_RPT3_SRPT0 (*((volatile unsigned int*)(0x42A62180UL))) +#define bM4_DMA1_RPT3_SRPT1 (*((volatile unsigned int*)(0x42A62184UL))) +#define bM4_DMA1_RPT3_SRPT2 (*((volatile unsigned int*)(0x42A62188UL))) +#define bM4_DMA1_RPT3_SRPT3 (*((volatile unsigned int*)(0x42A6218CUL))) +#define bM4_DMA1_RPT3_SRPT4 (*((volatile unsigned int*)(0x42A62190UL))) +#define bM4_DMA1_RPT3_SRPT5 (*((volatile unsigned int*)(0x42A62194UL))) +#define bM4_DMA1_RPT3_SRPT6 (*((volatile unsigned int*)(0x42A62198UL))) +#define bM4_DMA1_RPT3_SRPT7 (*((volatile unsigned int*)(0x42A6219CUL))) +#define bM4_DMA1_RPT3_SRPT8 (*((volatile unsigned int*)(0x42A621A0UL))) +#define bM4_DMA1_RPT3_SRPT9 (*((volatile unsigned int*)(0x42A621A4UL))) +#define bM4_DMA1_RPT3_DRPT0 (*((volatile unsigned int*)(0x42A621C0UL))) +#define bM4_DMA1_RPT3_DRPT1 (*((volatile unsigned int*)(0x42A621C4UL))) +#define bM4_DMA1_RPT3_DRPT2 (*((volatile unsigned int*)(0x42A621C8UL))) +#define bM4_DMA1_RPT3_DRPT3 (*((volatile unsigned int*)(0x42A621CCUL))) +#define bM4_DMA1_RPT3_DRPT4 (*((volatile unsigned int*)(0x42A621D0UL))) +#define bM4_DMA1_RPT3_DRPT5 (*((volatile unsigned int*)(0x42A621D4UL))) +#define bM4_DMA1_RPT3_DRPT6 (*((volatile unsigned int*)(0x42A621D8UL))) +#define bM4_DMA1_RPT3_DRPT7 (*((volatile unsigned int*)(0x42A621DCUL))) +#define bM4_DMA1_RPT3_DRPT8 (*((volatile unsigned int*)(0x42A621E0UL))) +#define bM4_DMA1_RPT3_DRPT9 (*((volatile unsigned int*)(0x42A621E4UL))) +#define bM4_DMA1_RPTB3_SRPTB0 (*((volatile unsigned int*)(0x42A62180UL))) +#define bM4_DMA1_RPTB3_SRPTB1 (*((volatile unsigned int*)(0x42A62184UL))) +#define bM4_DMA1_RPTB3_SRPTB2 (*((volatile unsigned int*)(0x42A62188UL))) +#define bM4_DMA1_RPTB3_SRPTB3 (*((volatile unsigned int*)(0x42A6218CUL))) +#define bM4_DMA1_RPTB3_SRPTB4 (*((volatile unsigned int*)(0x42A62190UL))) +#define bM4_DMA1_RPTB3_SRPTB5 (*((volatile unsigned int*)(0x42A62194UL))) +#define bM4_DMA1_RPTB3_SRPTB6 (*((volatile unsigned int*)(0x42A62198UL))) +#define bM4_DMA1_RPTB3_SRPTB7 (*((volatile unsigned int*)(0x42A6219CUL))) +#define bM4_DMA1_RPTB3_SRPTB8 (*((volatile unsigned int*)(0x42A621A0UL))) +#define bM4_DMA1_RPTB3_SRPTB9 (*((volatile unsigned int*)(0x42A621A4UL))) +#define bM4_DMA1_RPTB3_DRPTB0 (*((volatile unsigned int*)(0x42A621C0UL))) +#define bM4_DMA1_RPTB3_DRPTB1 (*((volatile unsigned int*)(0x42A621C4UL))) +#define bM4_DMA1_RPTB3_DRPTB2 (*((volatile unsigned int*)(0x42A621C8UL))) +#define bM4_DMA1_RPTB3_DRPTB3 (*((volatile unsigned int*)(0x42A621CCUL))) +#define bM4_DMA1_RPTB3_DRPTB4 (*((volatile unsigned int*)(0x42A621D0UL))) +#define bM4_DMA1_RPTB3_DRPTB5 (*((volatile unsigned int*)(0x42A621D4UL))) +#define bM4_DMA1_RPTB3_DRPTB6 (*((volatile unsigned int*)(0x42A621D8UL))) +#define bM4_DMA1_RPTB3_DRPTB7 (*((volatile unsigned int*)(0x42A621DCUL))) +#define bM4_DMA1_RPTB3_DRPTB8 (*((volatile unsigned int*)(0x42A621E0UL))) +#define bM4_DMA1_RPTB3_DRPTB9 (*((volatile unsigned int*)(0x42A621E4UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A62200UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A62204UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A62208UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6220CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A62210UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A62214UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A62218UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6221CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A62220UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A62224UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A62228UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6222CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A62230UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A62234UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A62238UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6223CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A62240UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A62244UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A62248UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6224CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A62250UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A62254UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A62258UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6225CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A62260UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A62264UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A62268UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6226CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A62270UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A62274UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A62278UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6227CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST0 (*((volatile unsigned int*)(0x42A62200UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST1 (*((volatile unsigned int*)(0x42A62204UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST2 (*((volatile unsigned int*)(0x42A62208UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST3 (*((volatile unsigned int*)(0x42A6220CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST4 (*((volatile unsigned int*)(0x42A62210UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST5 (*((volatile unsigned int*)(0x42A62214UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST6 (*((volatile unsigned int*)(0x42A62218UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST7 (*((volatile unsigned int*)(0x42A6221CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST8 (*((volatile unsigned int*)(0x42A62220UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST9 (*((volatile unsigned int*)(0x42A62224UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST10 (*((volatile unsigned int*)(0x42A62228UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST11 (*((volatile unsigned int*)(0x42A6222CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST12 (*((volatile unsigned int*)(0x42A62230UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST13 (*((volatile unsigned int*)(0x42A62234UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST14 (*((volatile unsigned int*)(0x42A62238UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST15 (*((volatile unsigned int*)(0x42A6223CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST16 (*((volatile unsigned int*)(0x42A62240UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST17 (*((volatile unsigned int*)(0x42A62244UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST18 (*((volatile unsigned int*)(0x42A62248UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST19 (*((volatile unsigned int*)(0x42A6224CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB0 (*((volatile unsigned int*)(0x42A62250UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB1 (*((volatile unsigned int*)(0x42A62254UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB2 (*((volatile unsigned int*)(0x42A62258UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB3 (*((volatile unsigned int*)(0x42A6225CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB4 (*((volatile unsigned int*)(0x42A62260UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB5 (*((volatile unsigned int*)(0x42A62264UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB6 (*((volatile unsigned int*)(0x42A62268UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB7 (*((volatile unsigned int*)(0x42A6226CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB8 (*((volatile unsigned int*)(0x42A62270UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB9 (*((volatile unsigned int*)(0x42A62274UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB10 (*((volatile unsigned int*)(0x42A62278UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB11 (*((volatile unsigned int*)(0x42A6227CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A62280UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A62284UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A62288UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6228CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A62290UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A62294UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A62298UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6229CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A622A0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A622A4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A622A8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A622ACUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A622B0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A622B4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A622B8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A622BCUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A622C0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A622C4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A622C8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A622CCUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A622D0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A622D4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A622D8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A622DCUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A622E0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A622E4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A622E8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A622ECUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A622F0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A622F4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A622F8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A622FCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST0 (*((volatile unsigned int*)(0x42A62280UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST1 (*((volatile unsigned int*)(0x42A62284UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST2 (*((volatile unsigned int*)(0x42A62288UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST3 (*((volatile unsigned int*)(0x42A6228CUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST4 (*((volatile unsigned int*)(0x42A62290UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST5 (*((volatile unsigned int*)(0x42A62294UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST6 (*((volatile unsigned int*)(0x42A62298UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST7 (*((volatile unsigned int*)(0x42A6229CUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST8 (*((volatile unsigned int*)(0x42A622A0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST9 (*((volatile unsigned int*)(0x42A622A4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST10 (*((volatile unsigned int*)(0x42A622A8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST11 (*((volatile unsigned int*)(0x42A622ACUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST12 (*((volatile unsigned int*)(0x42A622B0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST13 (*((volatile unsigned int*)(0x42A622B4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST14 (*((volatile unsigned int*)(0x42A622B8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST15 (*((volatile unsigned int*)(0x42A622BCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST16 (*((volatile unsigned int*)(0x42A622C0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST17 (*((volatile unsigned int*)(0x42A622C4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST18 (*((volatile unsigned int*)(0x42A622C8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST19 (*((volatile unsigned int*)(0x42A622CCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB0 (*((volatile unsigned int*)(0x42A622D0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB1 (*((volatile unsigned int*)(0x42A622D4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB2 (*((volatile unsigned int*)(0x42A622D8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB3 (*((volatile unsigned int*)(0x42A622DCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB4 (*((volatile unsigned int*)(0x42A622E0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB5 (*((volatile unsigned int*)(0x42A622E4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB6 (*((volatile unsigned int*)(0x42A622E8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB7 (*((volatile unsigned int*)(0x42A622ECUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB8 (*((volatile unsigned int*)(0x42A622F0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB9 (*((volatile unsigned int*)(0x42A622F4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB10 (*((volatile unsigned int*)(0x42A622F8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB11 (*((volatile unsigned int*)(0x42A622FCUL))) +#define bM4_DMA1_LLP3_LLP0 (*((volatile unsigned int*)(0x42A62308UL))) +#define bM4_DMA1_LLP3_LLP1 (*((volatile unsigned int*)(0x42A6230CUL))) +#define bM4_DMA1_LLP3_LLP2 (*((volatile unsigned int*)(0x42A62310UL))) +#define bM4_DMA1_LLP3_LLP3 (*((volatile unsigned int*)(0x42A62314UL))) +#define bM4_DMA1_LLP3_LLP4 (*((volatile unsigned int*)(0x42A62318UL))) +#define bM4_DMA1_LLP3_LLP5 (*((volatile unsigned int*)(0x42A6231CUL))) +#define bM4_DMA1_LLP3_LLP6 (*((volatile unsigned int*)(0x42A62320UL))) +#define bM4_DMA1_LLP3_LLP7 (*((volatile unsigned int*)(0x42A62324UL))) +#define bM4_DMA1_LLP3_LLP8 (*((volatile unsigned int*)(0x42A62328UL))) +#define bM4_DMA1_LLP3_LLP9 (*((volatile unsigned int*)(0x42A6232CUL))) +#define bM4_DMA1_LLP3_LLP10 (*((volatile unsigned int*)(0x42A62330UL))) +#define bM4_DMA1_LLP3_LLP11 (*((volatile unsigned int*)(0x42A62334UL))) +#define bM4_DMA1_LLP3_LLP12 (*((volatile unsigned int*)(0x42A62338UL))) +#define bM4_DMA1_LLP3_LLP13 (*((volatile unsigned int*)(0x42A6233CUL))) +#define bM4_DMA1_LLP3_LLP14 (*((volatile unsigned int*)(0x42A62340UL))) +#define bM4_DMA1_LLP3_LLP15 (*((volatile unsigned int*)(0x42A62344UL))) +#define bM4_DMA1_LLP3_LLP16 (*((volatile unsigned int*)(0x42A62348UL))) +#define bM4_DMA1_LLP3_LLP17 (*((volatile unsigned int*)(0x42A6234CUL))) +#define bM4_DMA1_LLP3_LLP18 (*((volatile unsigned int*)(0x42A62350UL))) +#define bM4_DMA1_LLP3_LLP19 (*((volatile unsigned int*)(0x42A62354UL))) +#define bM4_DMA1_LLP3_LLP20 (*((volatile unsigned int*)(0x42A62358UL))) +#define bM4_DMA1_LLP3_LLP21 (*((volatile unsigned int*)(0x42A6235CUL))) +#define bM4_DMA1_LLP3_LLP22 (*((volatile unsigned int*)(0x42A62360UL))) +#define bM4_DMA1_LLP3_LLP23 (*((volatile unsigned int*)(0x42A62364UL))) +#define bM4_DMA1_LLP3_LLP24 (*((volatile unsigned int*)(0x42A62368UL))) +#define bM4_DMA1_LLP3_LLP25 (*((volatile unsigned int*)(0x42A6236CUL))) +#define bM4_DMA1_LLP3_LLP26 (*((volatile unsigned int*)(0x42A62370UL))) +#define bM4_DMA1_LLP3_LLP27 (*((volatile unsigned int*)(0x42A62374UL))) +#define bM4_DMA1_LLP3_LLP28 (*((volatile unsigned int*)(0x42A62378UL))) +#define bM4_DMA1_LLP3_LLP29 (*((volatile unsigned int*)(0x42A6237CUL))) +#define bM4_DMA1_CH3CTL_SINC0 (*((volatile unsigned int*)(0x42A62380UL))) +#define bM4_DMA1_CH3CTL_SINC1 (*((volatile unsigned int*)(0x42A62384UL))) +#define bM4_DMA1_CH3CTL_DINC0 (*((volatile unsigned int*)(0x42A62388UL))) +#define bM4_DMA1_CH3CTL_DINC1 (*((volatile unsigned int*)(0x42A6238CUL))) +#define bM4_DMA1_CH3CTL_SRPTEN (*((volatile unsigned int*)(0x42A62390UL))) +#define bM4_DMA1_CH3CTL_DRPTEN (*((volatile unsigned int*)(0x42A62394UL))) +#define bM4_DMA1_CH3CTL_SNSEQEN (*((volatile unsigned int*)(0x42A62398UL))) +#define bM4_DMA1_CH3CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6239CUL))) +#define bM4_DMA1_CH3CTL_HSIZE0 (*((volatile unsigned int*)(0x42A623A0UL))) +#define bM4_DMA1_CH3CTL_HSIZE1 (*((volatile unsigned int*)(0x42A623A4UL))) +#define bM4_DMA1_CH3CTL_LLPEN (*((volatile unsigned int*)(0x42A623A8UL))) +#define bM4_DMA1_CH3CTL_LLPRUN (*((volatile unsigned int*)(0x42A623ACUL))) +#define bM4_DMA1_CH3CTL_IE (*((volatile unsigned int*)(0x42A623B0UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A62500UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A62504UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A62508UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6250CUL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A62510UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A62514UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A62518UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6251CUL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A62520UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A62524UL))) +#define bM4_DMA1_MONDTCTL3_CNT0 (*((volatile unsigned int*)(0x42A62540UL))) +#define bM4_DMA1_MONDTCTL3_CNT1 (*((volatile unsigned int*)(0x42A62544UL))) +#define bM4_DMA1_MONDTCTL3_CNT2 (*((volatile unsigned int*)(0x42A62548UL))) +#define bM4_DMA1_MONDTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6254CUL))) +#define bM4_DMA1_MONDTCTL3_CNT4 (*((volatile unsigned int*)(0x42A62550UL))) +#define bM4_DMA1_MONDTCTL3_CNT5 (*((volatile unsigned int*)(0x42A62554UL))) +#define bM4_DMA1_MONDTCTL3_CNT6 (*((volatile unsigned int*)(0x42A62558UL))) +#define bM4_DMA1_MONDTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6255CUL))) +#define bM4_DMA1_MONDTCTL3_CNT8 (*((volatile unsigned int*)(0x42A62560UL))) +#define bM4_DMA1_MONDTCTL3_CNT9 (*((volatile unsigned int*)(0x42A62564UL))) +#define bM4_DMA1_MONDTCTL3_CNT10 (*((volatile unsigned int*)(0x42A62568UL))) +#define bM4_DMA1_MONDTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6256CUL))) +#define bM4_DMA1_MONDTCTL3_CNT12 (*((volatile unsigned int*)(0x42A62570UL))) +#define bM4_DMA1_MONDTCTL3_CNT13 (*((volatile unsigned int*)(0x42A62574UL))) +#define bM4_DMA1_MONDTCTL3_CNT14 (*((volatile unsigned int*)(0x42A62578UL))) +#define bM4_DMA1_MONDTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6257CUL))) +#define bM4_DMA1_MONRPT3_SRPT0 (*((volatile unsigned int*)(0x42A62580UL))) +#define bM4_DMA1_MONRPT3_SRPT1 (*((volatile unsigned int*)(0x42A62584UL))) +#define bM4_DMA1_MONRPT3_SRPT2 (*((volatile unsigned int*)(0x42A62588UL))) +#define bM4_DMA1_MONRPT3_SRPT3 (*((volatile unsigned int*)(0x42A6258CUL))) +#define bM4_DMA1_MONRPT3_SRPT4 (*((volatile unsigned int*)(0x42A62590UL))) +#define bM4_DMA1_MONRPT3_SRPT5 (*((volatile unsigned int*)(0x42A62594UL))) +#define bM4_DMA1_MONRPT3_SRPT6 (*((volatile unsigned int*)(0x42A62598UL))) +#define bM4_DMA1_MONRPT3_SRPT7 (*((volatile unsigned int*)(0x42A6259CUL))) +#define bM4_DMA1_MONRPT3_SRPT8 (*((volatile unsigned int*)(0x42A625A0UL))) +#define bM4_DMA1_MONRPT3_SRPT9 (*((volatile unsigned int*)(0x42A625A4UL))) +#define bM4_DMA1_MONRPT3_DRPT0 (*((volatile unsigned int*)(0x42A625C0UL))) +#define bM4_DMA1_MONRPT3_DRPT1 (*((volatile unsigned int*)(0x42A625C4UL))) +#define bM4_DMA1_MONRPT3_DRPT2 (*((volatile unsigned int*)(0x42A625C8UL))) +#define bM4_DMA1_MONRPT3_DRPT3 (*((volatile unsigned int*)(0x42A625CCUL))) +#define bM4_DMA1_MONRPT3_DRPT4 (*((volatile unsigned int*)(0x42A625D0UL))) +#define bM4_DMA1_MONRPT3_DRPT5 (*((volatile unsigned int*)(0x42A625D4UL))) +#define bM4_DMA1_MONRPT3_DRPT6 (*((volatile unsigned int*)(0x42A625D8UL))) +#define bM4_DMA1_MONRPT3_DRPT7 (*((volatile unsigned int*)(0x42A625DCUL))) +#define bM4_DMA1_MONRPT3_DRPT8 (*((volatile unsigned int*)(0x42A625E0UL))) +#define bM4_DMA1_MONRPT3_DRPT9 (*((volatile unsigned int*)(0x42A625E4UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A62600UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A62604UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A62608UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6260CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A62610UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A62614UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A62618UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6261CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A62620UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A62624UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A62628UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6262CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A62630UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A62634UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A62638UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6263CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A62640UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A62644UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A62648UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6264CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A62650UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A62654UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A62658UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6265CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A62660UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A62664UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A62668UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6266CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A62670UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A62674UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A62678UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6267CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A62680UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A62684UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A62688UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6268CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A62690UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A62694UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A62698UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6269CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A626A0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A626A4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A626A8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A626ACUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A626B0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A626B4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A626B8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A626BCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A626C0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A626C4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A626C8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A626CCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A626D0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A626D4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A626D8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A626DCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A626E0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A626E4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A626E8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A626ECUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A626F0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A626F4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A626F8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A626FCUL))) +#define bM4_DMA2_EN_EN (*((volatile unsigned int*)(0x42A68000UL))) +#define bM4_DMA2_INTSTAT0_TRNERR0 (*((volatile unsigned int*)(0x42A68080UL))) +#define bM4_DMA2_INTSTAT0_TRNERR1 (*((volatile unsigned int*)(0x42A68084UL))) +#define bM4_DMA2_INTSTAT0_TRNERR2 (*((volatile unsigned int*)(0x42A68088UL))) +#define bM4_DMA2_INTSTAT0_TRNERR3 (*((volatile unsigned int*)(0x42A6808CUL))) +#define bM4_DMA2_INTSTAT0_REQERR0 (*((volatile unsigned int*)(0x42A680C0UL))) +#define bM4_DMA2_INTSTAT0_REQERR1 (*((volatile unsigned int*)(0x42A680C4UL))) +#define bM4_DMA2_INTSTAT0_REQERR2 (*((volatile unsigned int*)(0x42A680C8UL))) +#define bM4_DMA2_INTSTAT0_REQERR3 (*((volatile unsigned int*)(0x42A680CCUL))) +#define bM4_DMA2_INTSTAT1_TC0 (*((volatile unsigned int*)(0x42A68100UL))) +#define bM4_DMA2_INTSTAT1_TC1 (*((volatile unsigned int*)(0x42A68104UL))) +#define bM4_DMA2_INTSTAT1_TC2 (*((volatile unsigned int*)(0x42A68108UL))) +#define bM4_DMA2_INTSTAT1_TC3 (*((volatile unsigned int*)(0x42A6810CUL))) +#define bM4_DMA2_INTSTAT1_BTC0 (*((volatile unsigned int*)(0x42A68140UL))) +#define bM4_DMA2_INTSTAT1_BTC1 (*((volatile unsigned int*)(0x42A68144UL))) +#define bM4_DMA2_INTSTAT1_BTC2 (*((volatile unsigned int*)(0x42A68148UL))) +#define bM4_DMA2_INTSTAT1_BTC3 (*((volatile unsigned int*)(0x42A6814CUL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR0 (*((volatile unsigned int*)(0x42A68180UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR1 (*((volatile unsigned int*)(0x42A68184UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR2 (*((volatile unsigned int*)(0x42A68188UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR3 (*((volatile unsigned int*)(0x42A6818CUL))) +#define bM4_DMA2_INTMASK0_MSKREQERR0 (*((volatile unsigned int*)(0x42A681C0UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR1 (*((volatile unsigned int*)(0x42A681C4UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR2 (*((volatile unsigned int*)(0x42A681C8UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR3 (*((volatile unsigned int*)(0x42A681CCUL))) +#define bM4_DMA2_INTMASK1_MSKTC0 (*((volatile unsigned int*)(0x42A68200UL))) +#define bM4_DMA2_INTMASK1_MSKTC1 (*((volatile unsigned int*)(0x42A68204UL))) +#define bM4_DMA2_INTMASK1_MSKTC2 (*((volatile unsigned int*)(0x42A68208UL))) +#define bM4_DMA2_INTMASK1_MSKTC3 (*((volatile unsigned int*)(0x42A6820CUL))) +#define bM4_DMA2_INTMASK1_MSKBTC0 (*((volatile unsigned int*)(0x42A68240UL))) +#define bM4_DMA2_INTMASK1_MSKBTC1 (*((volatile unsigned int*)(0x42A68244UL))) +#define bM4_DMA2_INTMASK1_MSKBTC2 (*((volatile unsigned int*)(0x42A68248UL))) +#define bM4_DMA2_INTMASK1_MSKBTC3 (*((volatile unsigned int*)(0x42A6824CUL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR0 (*((volatile unsigned int*)(0x42A68280UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR1 (*((volatile unsigned int*)(0x42A68284UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR2 (*((volatile unsigned int*)(0x42A68288UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR3 (*((volatile unsigned int*)(0x42A6828CUL))) +#define bM4_DMA2_INTCLR0_CLRREQERR0 (*((volatile unsigned int*)(0x42A682C0UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR1 (*((volatile unsigned int*)(0x42A682C4UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR2 (*((volatile unsigned int*)(0x42A682C8UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR3 (*((volatile unsigned int*)(0x42A682CCUL))) +#define bM4_DMA2_INTCLR1_CLRTC0 (*((volatile unsigned int*)(0x42A68300UL))) +#define bM4_DMA2_INTCLR1_CLRTC1 (*((volatile unsigned int*)(0x42A68304UL))) +#define bM4_DMA2_INTCLR1_CLRTC2 (*((volatile unsigned int*)(0x42A68308UL))) +#define bM4_DMA2_INTCLR1_CLRTC3 (*((volatile unsigned int*)(0x42A6830CUL))) +#define bM4_DMA2_INTCLR1_CLRBTC0 (*((volatile unsigned int*)(0x42A68340UL))) +#define bM4_DMA2_INTCLR1_CLRBTC1 (*((volatile unsigned int*)(0x42A68344UL))) +#define bM4_DMA2_INTCLR1_CLRBTC2 (*((volatile unsigned int*)(0x42A68348UL))) +#define bM4_DMA2_INTCLR1_CLRBTC3 (*((volatile unsigned int*)(0x42A6834CUL))) +#define bM4_DMA2_CHEN_CHEN0 (*((volatile unsigned int*)(0x42A68380UL))) +#define bM4_DMA2_CHEN_CHEN1 (*((volatile unsigned int*)(0x42A68384UL))) +#define bM4_DMA2_CHEN_CHEN2 (*((volatile unsigned int*)(0x42A68388UL))) +#define bM4_DMA2_CHEN_CHEN3 (*((volatile unsigned int*)(0x42A6838CUL))) +#define bM4_DMA2_CHSTAT_DMAACT (*((volatile unsigned int*)(0x42A68480UL))) +#define bM4_DMA2_CHSTAT_RCFGACT (*((volatile unsigned int*)(0x42A68484UL))) +#define bM4_DMA2_CHSTAT_CHACT0 (*((volatile unsigned int*)(0x42A684C0UL))) +#define bM4_DMA2_CHSTAT_CHACT1 (*((volatile unsigned int*)(0x42A684C4UL))) +#define bM4_DMA2_CHSTAT_CHACT2 (*((volatile unsigned int*)(0x42A684C8UL))) +#define bM4_DMA2_CHSTAT_CHACT3 (*((volatile unsigned int*)(0x42A684CCUL))) +#define bM4_DMA2_RCFGCTL_RCFGEN (*((volatile unsigned int*)(0x42A68580UL))) +#define bM4_DMA2_RCFGCTL_RCFGLLP (*((volatile unsigned int*)(0x42A68584UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS0 (*((volatile unsigned int*)(0x42A685A0UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS1 (*((volatile unsigned int*)(0x42A685A4UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS2 (*((volatile unsigned int*)(0x42A685A8UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS3 (*((volatile unsigned int*)(0x42A685ACUL))) +#define bM4_DMA2_RCFGCTL_SARMD0 (*((volatile unsigned int*)(0x42A685C0UL))) +#define bM4_DMA2_RCFGCTL_SARMD1 (*((volatile unsigned int*)(0x42A685C4UL))) +#define bM4_DMA2_RCFGCTL_DARMD0 (*((volatile unsigned int*)(0x42A685C8UL))) +#define bM4_DMA2_RCFGCTL_DARMD1 (*((volatile unsigned int*)(0x42A685CCUL))) +#define bM4_DMA2_RCFGCTL_CNTMD0 (*((volatile unsigned int*)(0x42A685D0UL))) +#define bM4_DMA2_RCFGCTL_CNTMD1 (*((volatile unsigned int*)(0x42A685D4UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A68900UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A68904UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A68908UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A6890CUL))) +#define bM4_DMA2_DTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A68910UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A68914UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A68918UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A6891CUL))) +#define bM4_DMA2_DTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A68920UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A68924UL))) +#define bM4_DMA2_DTCTL0_CNT0 (*((volatile unsigned int*)(0x42A68940UL))) +#define bM4_DMA2_DTCTL0_CNT1 (*((volatile unsigned int*)(0x42A68944UL))) +#define bM4_DMA2_DTCTL0_CNT2 (*((volatile unsigned int*)(0x42A68948UL))) +#define bM4_DMA2_DTCTL0_CNT3 (*((volatile unsigned int*)(0x42A6894CUL))) +#define bM4_DMA2_DTCTL0_CNT4 (*((volatile unsigned int*)(0x42A68950UL))) +#define bM4_DMA2_DTCTL0_CNT5 (*((volatile unsigned int*)(0x42A68954UL))) +#define bM4_DMA2_DTCTL0_CNT6 (*((volatile unsigned int*)(0x42A68958UL))) +#define bM4_DMA2_DTCTL0_CNT7 (*((volatile unsigned int*)(0x42A6895CUL))) +#define bM4_DMA2_DTCTL0_CNT8 (*((volatile unsigned int*)(0x42A68960UL))) +#define bM4_DMA2_DTCTL0_CNT9 (*((volatile unsigned int*)(0x42A68964UL))) +#define bM4_DMA2_DTCTL0_CNT10 (*((volatile unsigned int*)(0x42A68968UL))) +#define bM4_DMA2_DTCTL0_CNT11 (*((volatile unsigned int*)(0x42A6896CUL))) +#define bM4_DMA2_DTCTL0_CNT12 (*((volatile unsigned int*)(0x42A68970UL))) +#define bM4_DMA2_DTCTL0_CNT13 (*((volatile unsigned int*)(0x42A68974UL))) +#define bM4_DMA2_DTCTL0_CNT14 (*((volatile unsigned int*)(0x42A68978UL))) +#define bM4_DMA2_DTCTL0_CNT15 (*((volatile unsigned int*)(0x42A6897CUL))) +#define bM4_DMA2_RPT0_SRPT0 (*((volatile unsigned int*)(0x42A68980UL))) +#define bM4_DMA2_RPT0_SRPT1 (*((volatile unsigned int*)(0x42A68984UL))) +#define bM4_DMA2_RPT0_SRPT2 (*((volatile unsigned int*)(0x42A68988UL))) +#define bM4_DMA2_RPT0_SRPT3 (*((volatile unsigned int*)(0x42A6898CUL))) +#define bM4_DMA2_RPT0_SRPT4 (*((volatile unsigned int*)(0x42A68990UL))) +#define bM4_DMA2_RPT0_SRPT5 (*((volatile unsigned int*)(0x42A68994UL))) +#define bM4_DMA2_RPT0_SRPT6 (*((volatile unsigned int*)(0x42A68998UL))) +#define bM4_DMA2_RPT0_SRPT7 (*((volatile unsigned int*)(0x42A6899CUL))) +#define bM4_DMA2_RPT0_SRPT8 (*((volatile unsigned int*)(0x42A689A0UL))) +#define bM4_DMA2_RPT0_SRPT9 (*((volatile unsigned int*)(0x42A689A4UL))) +#define bM4_DMA2_RPT0_DRPT0 (*((volatile unsigned int*)(0x42A689C0UL))) +#define bM4_DMA2_RPT0_DRPT1 (*((volatile unsigned int*)(0x42A689C4UL))) +#define bM4_DMA2_RPT0_DRPT2 (*((volatile unsigned int*)(0x42A689C8UL))) +#define bM4_DMA2_RPT0_DRPT3 (*((volatile unsigned int*)(0x42A689CCUL))) +#define bM4_DMA2_RPT0_DRPT4 (*((volatile unsigned int*)(0x42A689D0UL))) +#define bM4_DMA2_RPT0_DRPT5 (*((volatile unsigned int*)(0x42A689D4UL))) +#define bM4_DMA2_RPT0_DRPT6 (*((volatile unsigned int*)(0x42A689D8UL))) +#define bM4_DMA2_RPT0_DRPT7 (*((volatile unsigned int*)(0x42A689DCUL))) +#define bM4_DMA2_RPT0_DRPT8 (*((volatile unsigned int*)(0x42A689E0UL))) +#define bM4_DMA2_RPT0_DRPT9 (*((volatile unsigned int*)(0x42A689E4UL))) +#define bM4_DMA2_RPTB0_SRPTB0 (*((volatile unsigned int*)(0x42A68980UL))) +#define bM4_DMA2_RPTB0_SRPTB1 (*((volatile unsigned int*)(0x42A68984UL))) +#define bM4_DMA2_RPTB0_SRPTB2 (*((volatile unsigned int*)(0x42A68988UL))) +#define bM4_DMA2_RPTB0_SRPTB3 (*((volatile unsigned int*)(0x42A6898CUL))) +#define bM4_DMA2_RPTB0_SRPTB4 (*((volatile unsigned int*)(0x42A68990UL))) +#define bM4_DMA2_RPTB0_SRPTB5 (*((volatile unsigned int*)(0x42A68994UL))) +#define bM4_DMA2_RPTB0_SRPTB6 (*((volatile unsigned int*)(0x42A68998UL))) +#define bM4_DMA2_RPTB0_SRPTB7 (*((volatile unsigned int*)(0x42A6899CUL))) +#define bM4_DMA2_RPTB0_SRPTB8 (*((volatile unsigned int*)(0x42A689A0UL))) +#define bM4_DMA2_RPTB0_SRPTB9 (*((volatile unsigned int*)(0x42A689A4UL))) +#define bM4_DMA2_RPTB0_DRPTB0 (*((volatile unsigned int*)(0x42A689C0UL))) +#define bM4_DMA2_RPTB0_DRPTB1 (*((volatile unsigned int*)(0x42A689C4UL))) +#define bM4_DMA2_RPTB0_DRPTB2 (*((volatile unsigned int*)(0x42A689C8UL))) +#define bM4_DMA2_RPTB0_DRPTB3 (*((volatile unsigned int*)(0x42A689CCUL))) +#define bM4_DMA2_RPTB0_DRPTB4 (*((volatile unsigned int*)(0x42A689D0UL))) +#define bM4_DMA2_RPTB0_DRPTB5 (*((volatile unsigned int*)(0x42A689D4UL))) +#define bM4_DMA2_RPTB0_DRPTB6 (*((volatile unsigned int*)(0x42A689D8UL))) +#define bM4_DMA2_RPTB0_DRPTB7 (*((volatile unsigned int*)(0x42A689DCUL))) +#define bM4_DMA2_RPTB0_DRPTB8 (*((volatile unsigned int*)(0x42A689E0UL))) +#define bM4_DMA2_RPTB0_DRPTB9 (*((volatile unsigned int*)(0x42A689E4UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A68A00UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A68A04UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A68A08UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A68A0CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A68A10UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A68A14UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A68A18UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A68A1CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A68A20UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A68A24UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A68A28UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A68A2CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A68A30UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A68A34UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A68A38UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A68A3CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A68A40UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A68A44UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A68A48UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A68A4CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A68A50UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A68A54UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A68A58UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A68A5CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A68A60UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A68A64UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A68A68UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A68A6CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A68A70UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A68A74UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A68A78UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A68A7CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST0 (*((volatile unsigned int*)(0x42A68A00UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST1 (*((volatile unsigned int*)(0x42A68A04UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST2 (*((volatile unsigned int*)(0x42A68A08UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST3 (*((volatile unsigned int*)(0x42A68A0CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST4 (*((volatile unsigned int*)(0x42A68A10UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST5 (*((volatile unsigned int*)(0x42A68A14UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST6 (*((volatile unsigned int*)(0x42A68A18UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST7 (*((volatile unsigned int*)(0x42A68A1CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST8 (*((volatile unsigned int*)(0x42A68A20UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST9 (*((volatile unsigned int*)(0x42A68A24UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST10 (*((volatile unsigned int*)(0x42A68A28UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST11 (*((volatile unsigned int*)(0x42A68A2CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST12 (*((volatile unsigned int*)(0x42A68A30UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST13 (*((volatile unsigned int*)(0x42A68A34UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST14 (*((volatile unsigned int*)(0x42A68A38UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST15 (*((volatile unsigned int*)(0x42A68A3CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST16 (*((volatile unsigned int*)(0x42A68A40UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST17 (*((volatile unsigned int*)(0x42A68A44UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST18 (*((volatile unsigned int*)(0x42A68A48UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST19 (*((volatile unsigned int*)(0x42A68A4CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB0 (*((volatile unsigned int*)(0x42A68A50UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB1 (*((volatile unsigned int*)(0x42A68A54UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB2 (*((volatile unsigned int*)(0x42A68A58UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB3 (*((volatile unsigned int*)(0x42A68A5CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB4 (*((volatile unsigned int*)(0x42A68A60UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB5 (*((volatile unsigned int*)(0x42A68A64UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB6 (*((volatile unsigned int*)(0x42A68A68UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB7 (*((volatile unsigned int*)(0x42A68A6CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB8 (*((volatile unsigned int*)(0x42A68A70UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB9 (*((volatile unsigned int*)(0x42A68A74UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB10 (*((volatile unsigned int*)(0x42A68A78UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB11 (*((volatile unsigned int*)(0x42A68A7CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A68A80UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A68A84UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A68A88UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A68A8CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A68A90UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A68A94UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A68A98UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A68A9CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A68AA0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A68AA4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A68AA8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A68AACUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A68AB0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A68AB4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A68AB8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A68ABCUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A68AC0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A68AC4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A68AC8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A68ACCUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A68AD0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A68AD4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A68AD8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A68ADCUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A68AE0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A68AE4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A68AE8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A68AECUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A68AF0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A68AF4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A68AF8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A68AFCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST0 (*((volatile unsigned int*)(0x42A68A80UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST1 (*((volatile unsigned int*)(0x42A68A84UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST2 (*((volatile unsigned int*)(0x42A68A88UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST3 (*((volatile unsigned int*)(0x42A68A8CUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST4 (*((volatile unsigned int*)(0x42A68A90UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST5 (*((volatile unsigned int*)(0x42A68A94UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST6 (*((volatile unsigned int*)(0x42A68A98UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST7 (*((volatile unsigned int*)(0x42A68A9CUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST8 (*((volatile unsigned int*)(0x42A68AA0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST9 (*((volatile unsigned int*)(0x42A68AA4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST10 (*((volatile unsigned int*)(0x42A68AA8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST11 (*((volatile unsigned int*)(0x42A68AACUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST12 (*((volatile unsigned int*)(0x42A68AB0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST13 (*((volatile unsigned int*)(0x42A68AB4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST14 (*((volatile unsigned int*)(0x42A68AB8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST15 (*((volatile unsigned int*)(0x42A68ABCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST16 (*((volatile unsigned int*)(0x42A68AC0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST17 (*((volatile unsigned int*)(0x42A68AC4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST18 (*((volatile unsigned int*)(0x42A68AC8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST19 (*((volatile unsigned int*)(0x42A68ACCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB0 (*((volatile unsigned int*)(0x42A68AD0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB1 (*((volatile unsigned int*)(0x42A68AD4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB2 (*((volatile unsigned int*)(0x42A68AD8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB3 (*((volatile unsigned int*)(0x42A68ADCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB4 (*((volatile unsigned int*)(0x42A68AE0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB5 (*((volatile unsigned int*)(0x42A68AE4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB6 (*((volatile unsigned int*)(0x42A68AE8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB7 (*((volatile unsigned int*)(0x42A68AECUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB8 (*((volatile unsigned int*)(0x42A68AF0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB9 (*((volatile unsigned int*)(0x42A68AF4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB10 (*((volatile unsigned int*)(0x42A68AF8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB11 (*((volatile unsigned int*)(0x42A68AFCUL))) +#define bM4_DMA2_LLP0_LLP0 (*((volatile unsigned int*)(0x42A68B08UL))) +#define bM4_DMA2_LLP0_LLP1 (*((volatile unsigned int*)(0x42A68B0CUL))) +#define bM4_DMA2_LLP0_LLP2 (*((volatile unsigned int*)(0x42A68B10UL))) +#define bM4_DMA2_LLP0_LLP3 (*((volatile unsigned int*)(0x42A68B14UL))) +#define bM4_DMA2_LLP0_LLP4 (*((volatile unsigned int*)(0x42A68B18UL))) +#define bM4_DMA2_LLP0_LLP5 (*((volatile unsigned int*)(0x42A68B1CUL))) +#define bM4_DMA2_LLP0_LLP6 (*((volatile unsigned int*)(0x42A68B20UL))) +#define bM4_DMA2_LLP0_LLP7 (*((volatile unsigned int*)(0x42A68B24UL))) +#define bM4_DMA2_LLP0_LLP8 (*((volatile unsigned int*)(0x42A68B28UL))) +#define bM4_DMA2_LLP0_LLP9 (*((volatile unsigned int*)(0x42A68B2CUL))) +#define bM4_DMA2_LLP0_LLP10 (*((volatile unsigned int*)(0x42A68B30UL))) +#define bM4_DMA2_LLP0_LLP11 (*((volatile unsigned int*)(0x42A68B34UL))) +#define bM4_DMA2_LLP0_LLP12 (*((volatile unsigned int*)(0x42A68B38UL))) +#define bM4_DMA2_LLP0_LLP13 (*((volatile unsigned int*)(0x42A68B3CUL))) +#define bM4_DMA2_LLP0_LLP14 (*((volatile unsigned int*)(0x42A68B40UL))) +#define bM4_DMA2_LLP0_LLP15 (*((volatile unsigned int*)(0x42A68B44UL))) +#define bM4_DMA2_LLP0_LLP16 (*((volatile unsigned int*)(0x42A68B48UL))) +#define bM4_DMA2_LLP0_LLP17 (*((volatile unsigned int*)(0x42A68B4CUL))) +#define bM4_DMA2_LLP0_LLP18 (*((volatile unsigned int*)(0x42A68B50UL))) +#define bM4_DMA2_LLP0_LLP19 (*((volatile unsigned int*)(0x42A68B54UL))) +#define bM4_DMA2_LLP0_LLP20 (*((volatile unsigned int*)(0x42A68B58UL))) +#define bM4_DMA2_LLP0_LLP21 (*((volatile unsigned int*)(0x42A68B5CUL))) +#define bM4_DMA2_LLP0_LLP22 (*((volatile unsigned int*)(0x42A68B60UL))) +#define bM4_DMA2_LLP0_LLP23 (*((volatile unsigned int*)(0x42A68B64UL))) +#define bM4_DMA2_LLP0_LLP24 (*((volatile unsigned int*)(0x42A68B68UL))) +#define bM4_DMA2_LLP0_LLP25 (*((volatile unsigned int*)(0x42A68B6CUL))) +#define bM4_DMA2_LLP0_LLP26 (*((volatile unsigned int*)(0x42A68B70UL))) +#define bM4_DMA2_LLP0_LLP27 (*((volatile unsigned int*)(0x42A68B74UL))) +#define bM4_DMA2_LLP0_LLP28 (*((volatile unsigned int*)(0x42A68B78UL))) +#define bM4_DMA2_LLP0_LLP29 (*((volatile unsigned int*)(0x42A68B7CUL))) +#define bM4_DMA2_CH0CTL_SINC0 (*((volatile unsigned int*)(0x42A68B80UL))) +#define bM4_DMA2_CH0CTL_SINC1 (*((volatile unsigned int*)(0x42A68B84UL))) +#define bM4_DMA2_CH0CTL_DINC0 (*((volatile unsigned int*)(0x42A68B88UL))) +#define bM4_DMA2_CH0CTL_DINC1 (*((volatile unsigned int*)(0x42A68B8CUL))) +#define bM4_DMA2_CH0CTL_SRPTEN (*((volatile unsigned int*)(0x42A68B90UL))) +#define bM4_DMA2_CH0CTL_DRPTEN (*((volatile unsigned int*)(0x42A68B94UL))) +#define bM4_DMA2_CH0CTL_SNSEQEN (*((volatile unsigned int*)(0x42A68B98UL))) +#define bM4_DMA2_CH0CTL_DNSEQEN (*((volatile unsigned int*)(0x42A68B9CUL))) +#define bM4_DMA2_CH0CTL_HSIZE0 (*((volatile unsigned int*)(0x42A68BA0UL))) +#define bM4_DMA2_CH0CTL_HSIZE1 (*((volatile unsigned int*)(0x42A68BA4UL))) +#define bM4_DMA2_CH0CTL_LLPEN (*((volatile unsigned int*)(0x42A68BA8UL))) +#define bM4_DMA2_CH0CTL_LLPRUN (*((volatile unsigned int*)(0x42A68BACUL))) +#define bM4_DMA2_CH0CTL_IE (*((volatile unsigned int*)(0x42A68BB0UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A68D00UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A68D04UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A68D08UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A68D0CUL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A68D10UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A68D14UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A68D18UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A68D1CUL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A68D20UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A68D24UL))) +#define bM4_DMA2_MONDTCTL0_CNT0 (*((volatile unsigned int*)(0x42A68D40UL))) +#define bM4_DMA2_MONDTCTL0_CNT1 (*((volatile unsigned int*)(0x42A68D44UL))) +#define bM4_DMA2_MONDTCTL0_CNT2 (*((volatile unsigned int*)(0x42A68D48UL))) +#define bM4_DMA2_MONDTCTL0_CNT3 (*((volatile unsigned int*)(0x42A68D4CUL))) +#define bM4_DMA2_MONDTCTL0_CNT4 (*((volatile unsigned int*)(0x42A68D50UL))) +#define bM4_DMA2_MONDTCTL0_CNT5 (*((volatile unsigned int*)(0x42A68D54UL))) +#define bM4_DMA2_MONDTCTL0_CNT6 (*((volatile unsigned int*)(0x42A68D58UL))) +#define bM4_DMA2_MONDTCTL0_CNT7 (*((volatile unsigned int*)(0x42A68D5CUL))) +#define bM4_DMA2_MONDTCTL0_CNT8 (*((volatile unsigned int*)(0x42A68D60UL))) +#define bM4_DMA2_MONDTCTL0_CNT9 (*((volatile unsigned int*)(0x42A68D64UL))) +#define bM4_DMA2_MONDTCTL0_CNT10 (*((volatile unsigned int*)(0x42A68D68UL))) +#define bM4_DMA2_MONDTCTL0_CNT11 (*((volatile unsigned int*)(0x42A68D6CUL))) +#define bM4_DMA2_MONDTCTL0_CNT12 (*((volatile unsigned int*)(0x42A68D70UL))) +#define bM4_DMA2_MONDTCTL0_CNT13 (*((volatile unsigned int*)(0x42A68D74UL))) +#define bM4_DMA2_MONDTCTL0_CNT14 (*((volatile unsigned int*)(0x42A68D78UL))) +#define bM4_DMA2_MONDTCTL0_CNT15 (*((volatile unsigned int*)(0x42A68D7CUL))) +#define bM4_DMA2_MONRPT0_SRPT0 (*((volatile unsigned int*)(0x42A68D80UL))) +#define bM4_DMA2_MONRPT0_SRPT1 (*((volatile unsigned int*)(0x42A68D84UL))) +#define bM4_DMA2_MONRPT0_SRPT2 (*((volatile unsigned int*)(0x42A68D88UL))) +#define bM4_DMA2_MONRPT0_SRPT3 (*((volatile unsigned int*)(0x42A68D8CUL))) +#define bM4_DMA2_MONRPT0_SRPT4 (*((volatile unsigned int*)(0x42A68D90UL))) +#define bM4_DMA2_MONRPT0_SRPT5 (*((volatile unsigned int*)(0x42A68D94UL))) +#define bM4_DMA2_MONRPT0_SRPT6 (*((volatile unsigned int*)(0x42A68D98UL))) +#define bM4_DMA2_MONRPT0_SRPT7 (*((volatile unsigned int*)(0x42A68D9CUL))) +#define bM4_DMA2_MONRPT0_SRPT8 (*((volatile unsigned int*)(0x42A68DA0UL))) +#define bM4_DMA2_MONRPT0_SRPT9 (*((volatile unsigned int*)(0x42A68DA4UL))) +#define bM4_DMA2_MONRPT0_DRPT0 (*((volatile unsigned int*)(0x42A68DC0UL))) +#define bM4_DMA2_MONRPT0_DRPT1 (*((volatile unsigned int*)(0x42A68DC4UL))) +#define bM4_DMA2_MONRPT0_DRPT2 (*((volatile unsigned int*)(0x42A68DC8UL))) +#define bM4_DMA2_MONRPT0_DRPT3 (*((volatile unsigned int*)(0x42A68DCCUL))) +#define bM4_DMA2_MONRPT0_DRPT4 (*((volatile unsigned int*)(0x42A68DD0UL))) +#define bM4_DMA2_MONRPT0_DRPT5 (*((volatile unsigned int*)(0x42A68DD4UL))) +#define bM4_DMA2_MONRPT0_DRPT6 (*((volatile unsigned int*)(0x42A68DD8UL))) +#define bM4_DMA2_MONRPT0_DRPT7 (*((volatile unsigned int*)(0x42A68DDCUL))) +#define bM4_DMA2_MONRPT0_DRPT8 (*((volatile unsigned int*)(0x42A68DE0UL))) +#define bM4_DMA2_MONRPT0_DRPT9 (*((volatile unsigned int*)(0x42A68DE4UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A68E00UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A68E04UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A68E08UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A68E0CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A68E10UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A68E14UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A68E18UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A68E1CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A68E20UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A68E24UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A68E28UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A68E2CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A68E30UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A68E34UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A68E38UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A68E3CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A68E40UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A68E44UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A68E48UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A68E4CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A68E50UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A68E54UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A68E58UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A68E5CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A68E60UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A68E64UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A68E68UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A68E6CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A68E70UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A68E74UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A68E78UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A68E7CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A68E80UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A68E84UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A68E88UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A68E8CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A68E90UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A68E94UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A68E98UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A68E9CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A68EA0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A68EA4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A68EA8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A68EACUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A68EB0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A68EB4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A68EB8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A68EBCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A68EC0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A68EC4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A68EC8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A68ECCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A68ED0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A68ED4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A68ED8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A68EDCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A68EE0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A68EE4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A68EE8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A68EECUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A68EF0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A68EF4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A68EF8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A68EFCUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A69100UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A69104UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A69108UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6910CUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A69110UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A69114UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A69118UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6911CUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A69120UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A69124UL))) +#define bM4_DMA2_DTCTL1_CNT0 (*((volatile unsigned int*)(0x42A69140UL))) +#define bM4_DMA2_DTCTL1_CNT1 (*((volatile unsigned int*)(0x42A69144UL))) +#define bM4_DMA2_DTCTL1_CNT2 (*((volatile unsigned int*)(0x42A69148UL))) +#define bM4_DMA2_DTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6914CUL))) +#define bM4_DMA2_DTCTL1_CNT4 (*((volatile unsigned int*)(0x42A69150UL))) +#define bM4_DMA2_DTCTL1_CNT5 (*((volatile unsigned int*)(0x42A69154UL))) +#define bM4_DMA2_DTCTL1_CNT6 (*((volatile unsigned int*)(0x42A69158UL))) +#define bM4_DMA2_DTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6915CUL))) +#define bM4_DMA2_DTCTL1_CNT8 (*((volatile unsigned int*)(0x42A69160UL))) +#define bM4_DMA2_DTCTL1_CNT9 (*((volatile unsigned int*)(0x42A69164UL))) +#define bM4_DMA2_DTCTL1_CNT10 (*((volatile unsigned int*)(0x42A69168UL))) +#define bM4_DMA2_DTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6916CUL))) +#define bM4_DMA2_DTCTL1_CNT12 (*((volatile unsigned int*)(0x42A69170UL))) +#define bM4_DMA2_DTCTL1_CNT13 (*((volatile unsigned int*)(0x42A69174UL))) +#define bM4_DMA2_DTCTL1_CNT14 (*((volatile unsigned int*)(0x42A69178UL))) +#define bM4_DMA2_DTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6917CUL))) +#define bM4_DMA2_RPT1_SRPT0 (*((volatile unsigned int*)(0x42A69180UL))) +#define bM4_DMA2_RPT1_SRPT1 (*((volatile unsigned int*)(0x42A69184UL))) +#define bM4_DMA2_RPT1_SRPT2 (*((volatile unsigned int*)(0x42A69188UL))) +#define bM4_DMA2_RPT1_SRPT3 (*((volatile unsigned int*)(0x42A6918CUL))) +#define bM4_DMA2_RPT1_SRPT4 (*((volatile unsigned int*)(0x42A69190UL))) +#define bM4_DMA2_RPT1_SRPT5 (*((volatile unsigned int*)(0x42A69194UL))) +#define bM4_DMA2_RPT1_SRPT6 (*((volatile unsigned int*)(0x42A69198UL))) +#define bM4_DMA2_RPT1_SRPT7 (*((volatile unsigned int*)(0x42A6919CUL))) +#define bM4_DMA2_RPT1_SRPT8 (*((volatile unsigned int*)(0x42A691A0UL))) +#define bM4_DMA2_RPT1_SRPT9 (*((volatile unsigned int*)(0x42A691A4UL))) +#define bM4_DMA2_RPT1_DRPT0 (*((volatile unsigned int*)(0x42A691C0UL))) +#define bM4_DMA2_RPT1_DRPT1 (*((volatile unsigned int*)(0x42A691C4UL))) +#define bM4_DMA2_RPT1_DRPT2 (*((volatile unsigned int*)(0x42A691C8UL))) +#define bM4_DMA2_RPT1_DRPT3 (*((volatile unsigned int*)(0x42A691CCUL))) +#define bM4_DMA2_RPT1_DRPT4 (*((volatile unsigned int*)(0x42A691D0UL))) +#define bM4_DMA2_RPT1_DRPT5 (*((volatile unsigned int*)(0x42A691D4UL))) +#define bM4_DMA2_RPT1_DRPT6 (*((volatile unsigned int*)(0x42A691D8UL))) +#define bM4_DMA2_RPT1_DRPT7 (*((volatile unsigned int*)(0x42A691DCUL))) +#define bM4_DMA2_RPT1_DRPT8 (*((volatile unsigned int*)(0x42A691E0UL))) +#define bM4_DMA2_RPT1_DRPT9 (*((volatile unsigned int*)(0x42A691E4UL))) +#define bM4_DMA2_RPTB1_SRPTB0 (*((volatile unsigned int*)(0x42A69180UL))) +#define bM4_DMA2_RPTB1_SRPTB1 (*((volatile unsigned int*)(0x42A69184UL))) +#define bM4_DMA2_RPTB1_SRPTB2 (*((volatile unsigned int*)(0x42A69188UL))) +#define bM4_DMA2_RPTB1_SRPTB3 (*((volatile unsigned int*)(0x42A6918CUL))) +#define bM4_DMA2_RPTB1_SRPTB4 (*((volatile unsigned int*)(0x42A69190UL))) +#define bM4_DMA2_RPTB1_SRPTB5 (*((volatile unsigned int*)(0x42A69194UL))) +#define bM4_DMA2_RPTB1_SRPTB6 (*((volatile unsigned int*)(0x42A69198UL))) +#define bM4_DMA2_RPTB1_SRPTB7 (*((volatile unsigned int*)(0x42A6919CUL))) +#define bM4_DMA2_RPTB1_SRPTB8 (*((volatile unsigned int*)(0x42A691A0UL))) +#define bM4_DMA2_RPTB1_SRPTB9 (*((volatile unsigned int*)(0x42A691A4UL))) +#define bM4_DMA2_RPTB1_DRPTB0 (*((volatile unsigned int*)(0x42A691C0UL))) +#define bM4_DMA2_RPTB1_DRPTB1 (*((volatile unsigned int*)(0x42A691C4UL))) +#define bM4_DMA2_RPTB1_DRPTB2 (*((volatile unsigned int*)(0x42A691C8UL))) +#define bM4_DMA2_RPTB1_DRPTB3 (*((volatile unsigned int*)(0x42A691CCUL))) +#define bM4_DMA2_RPTB1_DRPTB4 (*((volatile unsigned int*)(0x42A691D0UL))) +#define bM4_DMA2_RPTB1_DRPTB5 (*((volatile unsigned int*)(0x42A691D4UL))) +#define bM4_DMA2_RPTB1_DRPTB6 (*((volatile unsigned int*)(0x42A691D8UL))) +#define bM4_DMA2_RPTB1_DRPTB7 (*((volatile unsigned int*)(0x42A691DCUL))) +#define bM4_DMA2_RPTB1_DRPTB8 (*((volatile unsigned int*)(0x42A691E0UL))) +#define bM4_DMA2_RPTB1_DRPTB9 (*((volatile unsigned int*)(0x42A691E4UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A69200UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A69204UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A69208UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6920CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A69210UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A69214UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A69218UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6921CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A69220UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A69224UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A69228UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6922CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A69230UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A69234UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A69238UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6923CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A69240UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A69244UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A69248UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6924CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A69250UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A69254UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A69258UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6925CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A69260UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A69264UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A69268UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6926CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A69270UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A69274UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A69278UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6927CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST0 (*((volatile unsigned int*)(0x42A69200UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST1 (*((volatile unsigned int*)(0x42A69204UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST2 (*((volatile unsigned int*)(0x42A69208UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST3 (*((volatile unsigned int*)(0x42A6920CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST4 (*((volatile unsigned int*)(0x42A69210UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST5 (*((volatile unsigned int*)(0x42A69214UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST6 (*((volatile unsigned int*)(0x42A69218UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST7 (*((volatile unsigned int*)(0x42A6921CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST8 (*((volatile unsigned int*)(0x42A69220UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST9 (*((volatile unsigned int*)(0x42A69224UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST10 (*((volatile unsigned int*)(0x42A69228UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST11 (*((volatile unsigned int*)(0x42A6922CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST12 (*((volatile unsigned int*)(0x42A69230UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST13 (*((volatile unsigned int*)(0x42A69234UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST14 (*((volatile unsigned int*)(0x42A69238UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST15 (*((volatile unsigned int*)(0x42A6923CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST16 (*((volatile unsigned int*)(0x42A69240UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST17 (*((volatile unsigned int*)(0x42A69244UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST18 (*((volatile unsigned int*)(0x42A69248UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST19 (*((volatile unsigned int*)(0x42A6924CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB0 (*((volatile unsigned int*)(0x42A69250UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB1 (*((volatile unsigned int*)(0x42A69254UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB2 (*((volatile unsigned int*)(0x42A69258UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB3 (*((volatile unsigned int*)(0x42A6925CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB4 (*((volatile unsigned int*)(0x42A69260UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB5 (*((volatile unsigned int*)(0x42A69264UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB6 (*((volatile unsigned int*)(0x42A69268UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB7 (*((volatile unsigned int*)(0x42A6926CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB8 (*((volatile unsigned int*)(0x42A69270UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB9 (*((volatile unsigned int*)(0x42A69274UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB10 (*((volatile unsigned int*)(0x42A69278UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB11 (*((volatile unsigned int*)(0x42A6927CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A69280UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A69284UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A69288UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6928CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A69290UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A69294UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A69298UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6929CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A692A0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A692A4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A692A8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A692ACUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A692B0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A692B4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A692B8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A692BCUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A692C0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A692C4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A692C8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A692CCUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A692D0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A692D4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A692D8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A692DCUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A692E0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A692E4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A692E8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A692ECUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A692F0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A692F4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A692F8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A692FCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST0 (*((volatile unsigned int*)(0x42A69280UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST1 (*((volatile unsigned int*)(0x42A69284UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST2 (*((volatile unsigned int*)(0x42A69288UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST3 (*((volatile unsigned int*)(0x42A6928CUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST4 (*((volatile unsigned int*)(0x42A69290UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST5 (*((volatile unsigned int*)(0x42A69294UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST6 (*((volatile unsigned int*)(0x42A69298UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST7 (*((volatile unsigned int*)(0x42A6929CUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST8 (*((volatile unsigned int*)(0x42A692A0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST9 (*((volatile unsigned int*)(0x42A692A4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST10 (*((volatile unsigned int*)(0x42A692A8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST11 (*((volatile unsigned int*)(0x42A692ACUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST12 (*((volatile unsigned int*)(0x42A692B0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST13 (*((volatile unsigned int*)(0x42A692B4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST14 (*((volatile unsigned int*)(0x42A692B8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST15 (*((volatile unsigned int*)(0x42A692BCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST16 (*((volatile unsigned int*)(0x42A692C0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST17 (*((volatile unsigned int*)(0x42A692C4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST18 (*((volatile unsigned int*)(0x42A692C8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST19 (*((volatile unsigned int*)(0x42A692CCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB0 (*((volatile unsigned int*)(0x42A692D0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB1 (*((volatile unsigned int*)(0x42A692D4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB2 (*((volatile unsigned int*)(0x42A692D8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB3 (*((volatile unsigned int*)(0x42A692DCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB4 (*((volatile unsigned int*)(0x42A692E0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB5 (*((volatile unsigned int*)(0x42A692E4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB6 (*((volatile unsigned int*)(0x42A692E8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB7 (*((volatile unsigned int*)(0x42A692ECUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB8 (*((volatile unsigned int*)(0x42A692F0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB9 (*((volatile unsigned int*)(0x42A692F4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB10 (*((volatile unsigned int*)(0x42A692F8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB11 (*((volatile unsigned int*)(0x42A692FCUL))) +#define bM4_DMA2_LLP1_LLP0 (*((volatile unsigned int*)(0x42A69308UL))) +#define bM4_DMA2_LLP1_LLP1 (*((volatile unsigned int*)(0x42A6930CUL))) +#define bM4_DMA2_LLP1_LLP2 (*((volatile unsigned int*)(0x42A69310UL))) +#define bM4_DMA2_LLP1_LLP3 (*((volatile unsigned int*)(0x42A69314UL))) +#define bM4_DMA2_LLP1_LLP4 (*((volatile unsigned int*)(0x42A69318UL))) +#define bM4_DMA2_LLP1_LLP5 (*((volatile unsigned int*)(0x42A6931CUL))) +#define bM4_DMA2_LLP1_LLP6 (*((volatile unsigned int*)(0x42A69320UL))) +#define bM4_DMA2_LLP1_LLP7 (*((volatile unsigned int*)(0x42A69324UL))) +#define bM4_DMA2_LLP1_LLP8 (*((volatile unsigned int*)(0x42A69328UL))) +#define bM4_DMA2_LLP1_LLP9 (*((volatile unsigned int*)(0x42A6932CUL))) +#define bM4_DMA2_LLP1_LLP10 (*((volatile unsigned int*)(0x42A69330UL))) +#define bM4_DMA2_LLP1_LLP11 (*((volatile unsigned int*)(0x42A69334UL))) +#define bM4_DMA2_LLP1_LLP12 (*((volatile unsigned int*)(0x42A69338UL))) +#define bM4_DMA2_LLP1_LLP13 (*((volatile unsigned int*)(0x42A6933CUL))) +#define bM4_DMA2_LLP1_LLP14 (*((volatile unsigned int*)(0x42A69340UL))) +#define bM4_DMA2_LLP1_LLP15 (*((volatile unsigned int*)(0x42A69344UL))) +#define bM4_DMA2_LLP1_LLP16 (*((volatile unsigned int*)(0x42A69348UL))) +#define bM4_DMA2_LLP1_LLP17 (*((volatile unsigned int*)(0x42A6934CUL))) +#define bM4_DMA2_LLP1_LLP18 (*((volatile unsigned int*)(0x42A69350UL))) +#define bM4_DMA2_LLP1_LLP19 (*((volatile unsigned int*)(0x42A69354UL))) +#define bM4_DMA2_LLP1_LLP20 (*((volatile unsigned int*)(0x42A69358UL))) +#define bM4_DMA2_LLP1_LLP21 (*((volatile unsigned int*)(0x42A6935CUL))) +#define bM4_DMA2_LLP1_LLP22 (*((volatile unsigned int*)(0x42A69360UL))) +#define bM4_DMA2_LLP1_LLP23 (*((volatile unsigned int*)(0x42A69364UL))) +#define bM4_DMA2_LLP1_LLP24 (*((volatile unsigned int*)(0x42A69368UL))) +#define bM4_DMA2_LLP1_LLP25 (*((volatile unsigned int*)(0x42A6936CUL))) +#define bM4_DMA2_LLP1_LLP26 (*((volatile unsigned int*)(0x42A69370UL))) +#define bM4_DMA2_LLP1_LLP27 (*((volatile unsigned int*)(0x42A69374UL))) +#define bM4_DMA2_LLP1_LLP28 (*((volatile unsigned int*)(0x42A69378UL))) +#define bM4_DMA2_LLP1_LLP29 (*((volatile unsigned int*)(0x42A6937CUL))) +#define bM4_DMA2_CH1CTL_SINC0 (*((volatile unsigned int*)(0x42A69380UL))) +#define bM4_DMA2_CH1CTL_SINC1 (*((volatile unsigned int*)(0x42A69384UL))) +#define bM4_DMA2_CH1CTL_DINC0 (*((volatile unsigned int*)(0x42A69388UL))) +#define bM4_DMA2_CH1CTL_DINC1 (*((volatile unsigned int*)(0x42A6938CUL))) +#define bM4_DMA2_CH1CTL_SRPTEN (*((volatile unsigned int*)(0x42A69390UL))) +#define bM4_DMA2_CH1CTL_DRPTEN (*((volatile unsigned int*)(0x42A69394UL))) +#define bM4_DMA2_CH1CTL_SNSEQEN (*((volatile unsigned int*)(0x42A69398UL))) +#define bM4_DMA2_CH1CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6939CUL))) +#define bM4_DMA2_CH1CTL_HSIZE0 (*((volatile unsigned int*)(0x42A693A0UL))) +#define bM4_DMA2_CH1CTL_HSIZE1 (*((volatile unsigned int*)(0x42A693A4UL))) +#define bM4_DMA2_CH1CTL_LLPEN (*((volatile unsigned int*)(0x42A693A8UL))) +#define bM4_DMA2_CH1CTL_LLPRUN (*((volatile unsigned int*)(0x42A693ACUL))) +#define bM4_DMA2_CH1CTL_IE (*((volatile unsigned int*)(0x42A693B0UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A69500UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A69504UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A69508UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6950CUL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A69510UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A69514UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A69518UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6951CUL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A69520UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A69524UL))) +#define bM4_DMA2_MONDTCTL1_CNT0 (*((volatile unsigned int*)(0x42A69540UL))) +#define bM4_DMA2_MONDTCTL1_CNT1 (*((volatile unsigned int*)(0x42A69544UL))) +#define bM4_DMA2_MONDTCTL1_CNT2 (*((volatile unsigned int*)(0x42A69548UL))) +#define bM4_DMA2_MONDTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6954CUL))) +#define bM4_DMA2_MONDTCTL1_CNT4 (*((volatile unsigned int*)(0x42A69550UL))) +#define bM4_DMA2_MONDTCTL1_CNT5 (*((volatile unsigned int*)(0x42A69554UL))) +#define bM4_DMA2_MONDTCTL1_CNT6 (*((volatile unsigned int*)(0x42A69558UL))) +#define bM4_DMA2_MONDTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6955CUL))) +#define bM4_DMA2_MONDTCTL1_CNT8 (*((volatile unsigned int*)(0x42A69560UL))) +#define bM4_DMA2_MONDTCTL1_CNT9 (*((volatile unsigned int*)(0x42A69564UL))) +#define bM4_DMA2_MONDTCTL1_CNT10 (*((volatile unsigned int*)(0x42A69568UL))) +#define bM4_DMA2_MONDTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6956CUL))) +#define bM4_DMA2_MONDTCTL1_CNT12 (*((volatile unsigned int*)(0x42A69570UL))) +#define bM4_DMA2_MONDTCTL1_CNT13 (*((volatile unsigned int*)(0x42A69574UL))) +#define bM4_DMA2_MONDTCTL1_CNT14 (*((volatile unsigned int*)(0x42A69578UL))) +#define bM4_DMA2_MONDTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6957CUL))) +#define bM4_DMA2_MONRPT1_SRPT0 (*((volatile unsigned int*)(0x42A69580UL))) +#define bM4_DMA2_MONRPT1_SRPT1 (*((volatile unsigned int*)(0x42A69584UL))) +#define bM4_DMA2_MONRPT1_SRPT2 (*((volatile unsigned int*)(0x42A69588UL))) +#define bM4_DMA2_MONRPT1_SRPT3 (*((volatile unsigned int*)(0x42A6958CUL))) +#define bM4_DMA2_MONRPT1_SRPT4 (*((volatile unsigned int*)(0x42A69590UL))) +#define bM4_DMA2_MONRPT1_SRPT5 (*((volatile unsigned int*)(0x42A69594UL))) +#define bM4_DMA2_MONRPT1_SRPT6 (*((volatile unsigned int*)(0x42A69598UL))) +#define bM4_DMA2_MONRPT1_SRPT7 (*((volatile unsigned int*)(0x42A6959CUL))) +#define bM4_DMA2_MONRPT1_SRPT8 (*((volatile unsigned int*)(0x42A695A0UL))) +#define bM4_DMA2_MONRPT1_SRPT9 (*((volatile unsigned int*)(0x42A695A4UL))) +#define bM4_DMA2_MONRPT1_DRPT0 (*((volatile unsigned int*)(0x42A695C0UL))) +#define bM4_DMA2_MONRPT1_DRPT1 (*((volatile unsigned int*)(0x42A695C4UL))) +#define bM4_DMA2_MONRPT1_DRPT2 (*((volatile unsigned int*)(0x42A695C8UL))) +#define bM4_DMA2_MONRPT1_DRPT3 (*((volatile unsigned int*)(0x42A695CCUL))) +#define bM4_DMA2_MONRPT1_DRPT4 (*((volatile unsigned int*)(0x42A695D0UL))) +#define bM4_DMA2_MONRPT1_DRPT5 (*((volatile unsigned int*)(0x42A695D4UL))) +#define bM4_DMA2_MONRPT1_DRPT6 (*((volatile unsigned int*)(0x42A695D8UL))) +#define bM4_DMA2_MONRPT1_DRPT7 (*((volatile unsigned int*)(0x42A695DCUL))) +#define bM4_DMA2_MONRPT1_DRPT8 (*((volatile unsigned int*)(0x42A695E0UL))) +#define bM4_DMA2_MONRPT1_DRPT9 (*((volatile unsigned int*)(0x42A695E4UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A69600UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A69604UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A69608UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6960CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A69610UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A69614UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A69618UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6961CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A69620UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A69624UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A69628UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6962CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A69630UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A69634UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A69638UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6963CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A69640UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A69644UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A69648UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6964CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A69650UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A69654UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A69658UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6965CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A69660UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A69664UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A69668UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6966CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A69670UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A69674UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A69678UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6967CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A69680UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A69684UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A69688UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6968CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A69690UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A69694UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A69698UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6969CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A696A0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A696A4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A696A8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A696ACUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A696B0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A696B4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A696B8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A696BCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A696C0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A696C4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A696C8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A696CCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A696D0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A696D4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A696D8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A696DCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A696E0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A696E4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A696E8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A696ECUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A696F0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A696F4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A696F8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A696FCUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A69900UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A69904UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A69908UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A6990CUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A69910UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A69914UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A69918UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A6991CUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A69920UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A69924UL))) +#define bM4_DMA2_DTCTL2_CNT0 (*((volatile unsigned int*)(0x42A69940UL))) +#define bM4_DMA2_DTCTL2_CNT1 (*((volatile unsigned int*)(0x42A69944UL))) +#define bM4_DMA2_DTCTL2_CNT2 (*((volatile unsigned int*)(0x42A69948UL))) +#define bM4_DMA2_DTCTL2_CNT3 (*((volatile unsigned int*)(0x42A6994CUL))) +#define bM4_DMA2_DTCTL2_CNT4 (*((volatile unsigned int*)(0x42A69950UL))) +#define bM4_DMA2_DTCTL2_CNT5 (*((volatile unsigned int*)(0x42A69954UL))) +#define bM4_DMA2_DTCTL2_CNT6 (*((volatile unsigned int*)(0x42A69958UL))) +#define bM4_DMA2_DTCTL2_CNT7 (*((volatile unsigned int*)(0x42A6995CUL))) +#define bM4_DMA2_DTCTL2_CNT8 (*((volatile unsigned int*)(0x42A69960UL))) +#define bM4_DMA2_DTCTL2_CNT9 (*((volatile unsigned int*)(0x42A69964UL))) +#define bM4_DMA2_DTCTL2_CNT10 (*((volatile unsigned int*)(0x42A69968UL))) +#define bM4_DMA2_DTCTL2_CNT11 (*((volatile unsigned int*)(0x42A6996CUL))) +#define bM4_DMA2_DTCTL2_CNT12 (*((volatile unsigned int*)(0x42A69970UL))) +#define bM4_DMA2_DTCTL2_CNT13 (*((volatile unsigned int*)(0x42A69974UL))) +#define bM4_DMA2_DTCTL2_CNT14 (*((volatile unsigned int*)(0x42A69978UL))) +#define bM4_DMA2_DTCTL2_CNT15 (*((volatile unsigned int*)(0x42A6997CUL))) +#define bM4_DMA2_RPT2_SRPT0 (*((volatile unsigned int*)(0x42A69980UL))) +#define bM4_DMA2_RPT2_SRPT1 (*((volatile unsigned int*)(0x42A69984UL))) +#define bM4_DMA2_RPT2_SRPT2 (*((volatile unsigned int*)(0x42A69988UL))) +#define bM4_DMA2_RPT2_SRPT3 (*((volatile unsigned int*)(0x42A6998CUL))) +#define bM4_DMA2_RPT2_SRPT4 (*((volatile unsigned int*)(0x42A69990UL))) +#define bM4_DMA2_RPT2_SRPT5 (*((volatile unsigned int*)(0x42A69994UL))) +#define bM4_DMA2_RPT2_SRPT6 (*((volatile unsigned int*)(0x42A69998UL))) +#define bM4_DMA2_RPT2_SRPT7 (*((volatile unsigned int*)(0x42A6999CUL))) +#define bM4_DMA2_RPT2_SRPT8 (*((volatile unsigned int*)(0x42A699A0UL))) +#define bM4_DMA2_RPT2_SRPT9 (*((volatile unsigned int*)(0x42A699A4UL))) +#define bM4_DMA2_RPT2_DRPT0 (*((volatile unsigned int*)(0x42A699C0UL))) +#define bM4_DMA2_RPT2_DRPT1 (*((volatile unsigned int*)(0x42A699C4UL))) +#define bM4_DMA2_RPT2_DRPT2 (*((volatile unsigned int*)(0x42A699C8UL))) +#define bM4_DMA2_RPT2_DRPT3 (*((volatile unsigned int*)(0x42A699CCUL))) +#define bM4_DMA2_RPT2_DRPT4 (*((volatile unsigned int*)(0x42A699D0UL))) +#define bM4_DMA2_RPT2_DRPT5 (*((volatile unsigned int*)(0x42A699D4UL))) +#define bM4_DMA2_RPT2_DRPT6 (*((volatile unsigned int*)(0x42A699D8UL))) +#define bM4_DMA2_RPT2_DRPT7 (*((volatile unsigned int*)(0x42A699DCUL))) +#define bM4_DMA2_RPT2_DRPT8 (*((volatile unsigned int*)(0x42A699E0UL))) +#define bM4_DMA2_RPT2_DRPT9 (*((volatile unsigned int*)(0x42A699E4UL))) +#define bM4_DMA2_RPTB2_SRPTB0 (*((volatile unsigned int*)(0x42A69980UL))) +#define bM4_DMA2_RPTB2_SRPTB1 (*((volatile unsigned int*)(0x42A69984UL))) +#define bM4_DMA2_RPTB2_SRPTB2 (*((volatile unsigned int*)(0x42A69988UL))) +#define bM4_DMA2_RPTB2_SRPTB3 (*((volatile unsigned int*)(0x42A6998CUL))) +#define bM4_DMA2_RPTB2_SRPTB4 (*((volatile unsigned int*)(0x42A69990UL))) +#define bM4_DMA2_RPTB2_SRPTB5 (*((volatile unsigned int*)(0x42A69994UL))) +#define bM4_DMA2_RPTB2_SRPTB6 (*((volatile unsigned int*)(0x42A69998UL))) +#define bM4_DMA2_RPTB2_SRPTB7 (*((volatile unsigned int*)(0x42A6999CUL))) +#define bM4_DMA2_RPTB2_SRPTB8 (*((volatile unsigned int*)(0x42A699A0UL))) +#define bM4_DMA2_RPTB2_SRPTB9 (*((volatile unsigned int*)(0x42A699A4UL))) +#define bM4_DMA2_RPTB2_DRPTB0 (*((volatile unsigned int*)(0x42A699C0UL))) +#define bM4_DMA2_RPTB2_DRPTB1 (*((volatile unsigned int*)(0x42A699C4UL))) +#define bM4_DMA2_RPTB2_DRPTB2 (*((volatile unsigned int*)(0x42A699C8UL))) +#define bM4_DMA2_RPTB2_DRPTB3 (*((volatile unsigned int*)(0x42A699CCUL))) +#define bM4_DMA2_RPTB2_DRPTB4 (*((volatile unsigned int*)(0x42A699D0UL))) +#define bM4_DMA2_RPTB2_DRPTB5 (*((volatile unsigned int*)(0x42A699D4UL))) +#define bM4_DMA2_RPTB2_DRPTB6 (*((volatile unsigned int*)(0x42A699D8UL))) +#define bM4_DMA2_RPTB2_DRPTB7 (*((volatile unsigned int*)(0x42A699DCUL))) +#define bM4_DMA2_RPTB2_DRPTB8 (*((volatile unsigned int*)(0x42A699E0UL))) +#define bM4_DMA2_RPTB2_DRPTB9 (*((volatile unsigned int*)(0x42A699E4UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A69A00UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A69A04UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A69A08UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A69A0CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A69A10UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A69A14UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A69A18UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A69A1CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A69A20UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A69A24UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A69A28UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A69A2CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A69A30UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A69A34UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A69A38UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A69A3CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A69A40UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A69A44UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A69A48UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A69A4CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A69A50UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A69A54UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A69A58UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A69A5CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A69A60UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A69A64UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A69A68UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A69A6CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A69A70UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A69A74UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A69A78UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A69A7CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST0 (*((volatile unsigned int*)(0x42A69A00UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST1 (*((volatile unsigned int*)(0x42A69A04UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST2 (*((volatile unsigned int*)(0x42A69A08UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST3 (*((volatile unsigned int*)(0x42A69A0CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST4 (*((volatile unsigned int*)(0x42A69A10UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST5 (*((volatile unsigned int*)(0x42A69A14UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST6 (*((volatile unsigned int*)(0x42A69A18UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST7 (*((volatile unsigned int*)(0x42A69A1CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST8 (*((volatile unsigned int*)(0x42A69A20UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST9 (*((volatile unsigned int*)(0x42A69A24UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST10 (*((volatile unsigned int*)(0x42A69A28UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST11 (*((volatile unsigned int*)(0x42A69A2CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST12 (*((volatile unsigned int*)(0x42A69A30UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST13 (*((volatile unsigned int*)(0x42A69A34UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST14 (*((volatile unsigned int*)(0x42A69A38UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST15 (*((volatile unsigned int*)(0x42A69A3CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST16 (*((volatile unsigned int*)(0x42A69A40UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST17 (*((volatile unsigned int*)(0x42A69A44UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST18 (*((volatile unsigned int*)(0x42A69A48UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST19 (*((volatile unsigned int*)(0x42A69A4CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB0 (*((volatile unsigned int*)(0x42A69A50UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB1 (*((volatile unsigned int*)(0x42A69A54UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB2 (*((volatile unsigned int*)(0x42A69A58UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB3 (*((volatile unsigned int*)(0x42A69A5CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB4 (*((volatile unsigned int*)(0x42A69A60UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB5 (*((volatile unsigned int*)(0x42A69A64UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB6 (*((volatile unsigned int*)(0x42A69A68UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB7 (*((volatile unsigned int*)(0x42A69A6CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB8 (*((volatile unsigned int*)(0x42A69A70UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB9 (*((volatile unsigned int*)(0x42A69A74UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB10 (*((volatile unsigned int*)(0x42A69A78UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB11 (*((volatile unsigned int*)(0x42A69A7CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A69A80UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A69A84UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A69A88UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A69A8CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A69A90UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A69A94UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A69A98UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A69A9CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A69AA0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A69AA4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A69AA8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A69AACUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A69AB0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A69AB4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A69AB8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A69ABCUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A69AC0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A69AC4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A69AC8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A69ACCUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A69AD0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A69AD4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A69AD8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A69ADCUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A69AE0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A69AE4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A69AE8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A69AECUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A69AF0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A69AF4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A69AF8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A69AFCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST0 (*((volatile unsigned int*)(0x42A69A80UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST1 (*((volatile unsigned int*)(0x42A69A84UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST2 (*((volatile unsigned int*)(0x42A69A88UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST3 (*((volatile unsigned int*)(0x42A69A8CUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST4 (*((volatile unsigned int*)(0x42A69A90UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST5 (*((volatile unsigned int*)(0x42A69A94UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST6 (*((volatile unsigned int*)(0x42A69A98UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST7 (*((volatile unsigned int*)(0x42A69A9CUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST8 (*((volatile unsigned int*)(0x42A69AA0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST9 (*((volatile unsigned int*)(0x42A69AA4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST10 (*((volatile unsigned int*)(0x42A69AA8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST11 (*((volatile unsigned int*)(0x42A69AACUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST12 (*((volatile unsigned int*)(0x42A69AB0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST13 (*((volatile unsigned int*)(0x42A69AB4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST14 (*((volatile unsigned int*)(0x42A69AB8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST15 (*((volatile unsigned int*)(0x42A69ABCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST16 (*((volatile unsigned int*)(0x42A69AC0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST17 (*((volatile unsigned int*)(0x42A69AC4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST18 (*((volatile unsigned int*)(0x42A69AC8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST19 (*((volatile unsigned int*)(0x42A69ACCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB0 (*((volatile unsigned int*)(0x42A69AD0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB1 (*((volatile unsigned int*)(0x42A69AD4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB2 (*((volatile unsigned int*)(0x42A69AD8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB3 (*((volatile unsigned int*)(0x42A69ADCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB4 (*((volatile unsigned int*)(0x42A69AE0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB5 (*((volatile unsigned int*)(0x42A69AE4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB6 (*((volatile unsigned int*)(0x42A69AE8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB7 (*((volatile unsigned int*)(0x42A69AECUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB8 (*((volatile unsigned int*)(0x42A69AF0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB9 (*((volatile unsigned int*)(0x42A69AF4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB10 (*((volatile unsigned int*)(0x42A69AF8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB11 (*((volatile unsigned int*)(0x42A69AFCUL))) +#define bM4_DMA2_LLP2_LLP0 (*((volatile unsigned int*)(0x42A69B08UL))) +#define bM4_DMA2_LLP2_LLP1 (*((volatile unsigned int*)(0x42A69B0CUL))) +#define bM4_DMA2_LLP2_LLP2 (*((volatile unsigned int*)(0x42A69B10UL))) +#define bM4_DMA2_LLP2_LLP3 (*((volatile unsigned int*)(0x42A69B14UL))) +#define bM4_DMA2_LLP2_LLP4 (*((volatile unsigned int*)(0x42A69B18UL))) +#define bM4_DMA2_LLP2_LLP5 (*((volatile unsigned int*)(0x42A69B1CUL))) +#define bM4_DMA2_LLP2_LLP6 (*((volatile unsigned int*)(0x42A69B20UL))) +#define bM4_DMA2_LLP2_LLP7 (*((volatile unsigned int*)(0x42A69B24UL))) +#define bM4_DMA2_LLP2_LLP8 (*((volatile unsigned int*)(0x42A69B28UL))) +#define bM4_DMA2_LLP2_LLP9 (*((volatile unsigned int*)(0x42A69B2CUL))) +#define bM4_DMA2_LLP2_LLP10 (*((volatile unsigned int*)(0x42A69B30UL))) +#define bM4_DMA2_LLP2_LLP11 (*((volatile unsigned int*)(0x42A69B34UL))) +#define bM4_DMA2_LLP2_LLP12 (*((volatile unsigned int*)(0x42A69B38UL))) +#define bM4_DMA2_LLP2_LLP13 (*((volatile unsigned int*)(0x42A69B3CUL))) +#define bM4_DMA2_LLP2_LLP14 (*((volatile unsigned int*)(0x42A69B40UL))) +#define bM4_DMA2_LLP2_LLP15 (*((volatile unsigned int*)(0x42A69B44UL))) +#define bM4_DMA2_LLP2_LLP16 (*((volatile unsigned int*)(0x42A69B48UL))) +#define bM4_DMA2_LLP2_LLP17 (*((volatile unsigned int*)(0x42A69B4CUL))) +#define bM4_DMA2_LLP2_LLP18 (*((volatile unsigned int*)(0x42A69B50UL))) +#define bM4_DMA2_LLP2_LLP19 (*((volatile unsigned int*)(0x42A69B54UL))) +#define bM4_DMA2_LLP2_LLP20 (*((volatile unsigned int*)(0x42A69B58UL))) +#define bM4_DMA2_LLP2_LLP21 (*((volatile unsigned int*)(0x42A69B5CUL))) +#define bM4_DMA2_LLP2_LLP22 (*((volatile unsigned int*)(0x42A69B60UL))) +#define bM4_DMA2_LLP2_LLP23 (*((volatile unsigned int*)(0x42A69B64UL))) +#define bM4_DMA2_LLP2_LLP24 (*((volatile unsigned int*)(0x42A69B68UL))) +#define bM4_DMA2_LLP2_LLP25 (*((volatile unsigned int*)(0x42A69B6CUL))) +#define bM4_DMA2_LLP2_LLP26 (*((volatile unsigned int*)(0x42A69B70UL))) +#define bM4_DMA2_LLP2_LLP27 (*((volatile unsigned int*)(0x42A69B74UL))) +#define bM4_DMA2_LLP2_LLP28 (*((volatile unsigned int*)(0x42A69B78UL))) +#define bM4_DMA2_LLP2_LLP29 (*((volatile unsigned int*)(0x42A69B7CUL))) +#define bM4_DMA2_CH2CTL_SINC0 (*((volatile unsigned int*)(0x42A69B80UL))) +#define bM4_DMA2_CH2CTL_SINC1 (*((volatile unsigned int*)(0x42A69B84UL))) +#define bM4_DMA2_CH2CTL_DINC0 (*((volatile unsigned int*)(0x42A69B88UL))) +#define bM4_DMA2_CH2CTL_DINC1 (*((volatile unsigned int*)(0x42A69B8CUL))) +#define bM4_DMA2_CH2CTL_SRPTEN (*((volatile unsigned int*)(0x42A69B90UL))) +#define bM4_DMA2_CH2CTL_DRPTEN (*((volatile unsigned int*)(0x42A69B94UL))) +#define bM4_DMA2_CH2CTL_SNSEQEN (*((volatile unsigned int*)(0x42A69B98UL))) +#define bM4_DMA2_CH2CTL_DNSEQEN (*((volatile unsigned int*)(0x42A69B9CUL))) +#define bM4_DMA2_CH2CTL_HSIZE0 (*((volatile unsigned int*)(0x42A69BA0UL))) +#define bM4_DMA2_CH2CTL_HSIZE1 (*((volatile unsigned int*)(0x42A69BA4UL))) +#define bM4_DMA2_CH2CTL_LLPEN (*((volatile unsigned int*)(0x42A69BA8UL))) +#define bM4_DMA2_CH2CTL_LLPRUN (*((volatile unsigned int*)(0x42A69BACUL))) +#define bM4_DMA2_CH2CTL_IE (*((volatile unsigned int*)(0x42A69BB0UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A69D00UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A69D04UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A69D08UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A69D0CUL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A69D10UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A69D14UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A69D18UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A69D1CUL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A69D20UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A69D24UL))) +#define bM4_DMA2_MONDTCTL2_CNT0 (*((volatile unsigned int*)(0x42A69D40UL))) +#define bM4_DMA2_MONDTCTL2_CNT1 (*((volatile unsigned int*)(0x42A69D44UL))) +#define bM4_DMA2_MONDTCTL2_CNT2 (*((volatile unsigned int*)(0x42A69D48UL))) +#define bM4_DMA2_MONDTCTL2_CNT3 (*((volatile unsigned int*)(0x42A69D4CUL))) +#define bM4_DMA2_MONDTCTL2_CNT4 (*((volatile unsigned int*)(0x42A69D50UL))) +#define bM4_DMA2_MONDTCTL2_CNT5 (*((volatile unsigned int*)(0x42A69D54UL))) +#define bM4_DMA2_MONDTCTL2_CNT6 (*((volatile unsigned int*)(0x42A69D58UL))) +#define bM4_DMA2_MONDTCTL2_CNT7 (*((volatile unsigned int*)(0x42A69D5CUL))) +#define bM4_DMA2_MONDTCTL2_CNT8 (*((volatile unsigned int*)(0x42A69D60UL))) +#define bM4_DMA2_MONDTCTL2_CNT9 (*((volatile unsigned int*)(0x42A69D64UL))) +#define bM4_DMA2_MONDTCTL2_CNT10 (*((volatile unsigned int*)(0x42A69D68UL))) +#define bM4_DMA2_MONDTCTL2_CNT11 (*((volatile unsigned int*)(0x42A69D6CUL))) +#define bM4_DMA2_MONDTCTL2_CNT12 (*((volatile unsigned int*)(0x42A69D70UL))) +#define bM4_DMA2_MONDTCTL2_CNT13 (*((volatile unsigned int*)(0x42A69D74UL))) +#define bM4_DMA2_MONDTCTL2_CNT14 (*((volatile unsigned int*)(0x42A69D78UL))) +#define bM4_DMA2_MONDTCTL2_CNT15 (*((volatile unsigned int*)(0x42A69D7CUL))) +#define bM4_DMA2_MONRPT2_SRPT0 (*((volatile unsigned int*)(0x42A69D80UL))) +#define bM4_DMA2_MONRPT2_SRPT1 (*((volatile unsigned int*)(0x42A69D84UL))) +#define bM4_DMA2_MONRPT2_SRPT2 (*((volatile unsigned int*)(0x42A69D88UL))) +#define bM4_DMA2_MONRPT2_SRPT3 (*((volatile unsigned int*)(0x42A69D8CUL))) +#define bM4_DMA2_MONRPT2_SRPT4 (*((volatile unsigned int*)(0x42A69D90UL))) +#define bM4_DMA2_MONRPT2_SRPT5 (*((volatile unsigned int*)(0x42A69D94UL))) +#define bM4_DMA2_MONRPT2_SRPT6 (*((volatile unsigned int*)(0x42A69D98UL))) +#define bM4_DMA2_MONRPT2_SRPT7 (*((volatile unsigned int*)(0x42A69D9CUL))) +#define bM4_DMA2_MONRPT2_SRPT8 (*((volatile unsigned int*)(0x42A69DA0UL))) +#define bM4_DMA2_MONRPT2_SRPT9 (*((volatile unsigned int*)(0x42A69DA4UL))) +#define bM4_DMA2_MONRPT2_DRPT0 (*((volatile unsigned int*)(0x42A69DC0UL))) +#define bM4_DMA2_MONRPT2_DRPT1 (*((volatile unsigned int*)(0x42A69DC4UL))) +#define bM4_DMA2_MONRPT2_DRPT2 (*((volatile unsigned int*)(0x42A69DC8UL))) +#define bM4_DMA2_MONRPT2_DRPT3 (*((volatile unsigned int*)(0x42A69DCCUL))) +#define bM4_DMA2_MONRPT2_DRPT4 (*((volatile unsigned int*)(0x42A69DD0UL))) +#define bM4_DMA2_MONRPT2_DRPT5 (*((volatile unsigned int*)(0x42A69DD4UL))) +#define bM4_DMA2_MONRPT2_DRPT6 (*((volatile unsigned int*)(0x42A69DD8UL))) +#define bM4_DMA2_MONRPT2_DRPT7 (*((volatile unsigned int*)(0x42A69DDCUL))) +#define bM4_DMA2_MONRPT2_DRPT8 (*((volatile unsigned int*)(0x42A69DE0UL))) +#define bM4_DMA2_MONRPT2_DRPT9 (*((volatile unsigned int*)(0x42A69DE4UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A69E00UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A69E04UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A69E08UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A69E0CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A69E10UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A69E14UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A69E18UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A69E1CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A69E20UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A69E24UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A69E28UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A69E2CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A69E30UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A69E34UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A69E38UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A69E3CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A69E40UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A69E44UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A69E48UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A69E4CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A69E50UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A69E54UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A69E58UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A69E5CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A69E60UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A69E64UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A69E68UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A69E6CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A69E70UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A69E74UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A69E78UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A69E7CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A69E80UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A69E84UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A69E88UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A69E8CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A69E90UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A69E94UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A69E98UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A69E9CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A69EA0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A69EA4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A69EA8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A69EACUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A69EB0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A69EB4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A69EB8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A69EBCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A69EC0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A69EC4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A69EC8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A69ECCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A69ED0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A69ED4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A69ED8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A69EDCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A69EE0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A69EE4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A69EE8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A69EECUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A69EF0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A69EF4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A69EF8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A69EFCUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A6A100UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A6A104UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A6A108UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6A10CUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A6A110UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A6A114UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A6A118UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6A11CUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A6A120UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A6A124UL))) +#define bM4_DMA2_DTCTL3_CNT0 (*((volatile unsigned int*)(0x42A6A140UL))) +#define bM4_DMA2_DTCTL3_CNT1 (*((volatile unsigned int*)(0x42A6A144UL))) +#define bM4_DMA2_DTCTL3_CNT2 (*((volatile unsigned int*)(0x42A6A148UL))) +#define bM4_DMA2_DTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6A14CUL))) +#define bM4_DMA2_DTCTL3_CNT4 (*((volatile unsigned int*)(0x42A6A150UL))) +#define bM4_DMA2_DTCTL3_CNT5 (*((volatile unsigned int*)(0x42A6A154UL))) +#define bM4_DMA2_DTCTL3_CNT6 (*((volatile unsigned int*)(0x42A6A158UL))) +#define bM4_DMA2_DTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6A15CUL))) +#define bM4_DMA2_DTCTL3_CNT8 (*((volatile unsigned int*)(0x42A6A160UL))) +#define bM4_DMA2_DTCTL3_CNT9 (*((volatile unsigned int*)(0x42A6A164UL))) +#define bM4_DMA2_DTCTL3_CNT10 (*((volatile unsigned int*)(0x42A6A168UL))) +#define bM4_DMA2_DTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6A16CUL))) +#define bM4_DMA2_DTCTL3_CNT12 (*((volatile unsigned int*)(0x42A6A170UL))) +#define bM4_DMA2_DTCTL3_CNT13 (*((volatile unsigned int*)(0x42A6A174UL))) +#define bM4_DMA2_DTCTL3_CNT14 (*((volatile unsigned int*)(0x42A6A178UL))) +#define bM4_DMA2_DTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6A17CUL))) +#define bM4_DMA2_RPT3_SRPT0 (*((volatile unsigned int*)(0x42A6A180UL))) +#define bM4_DMA2_RPT3_SRPT1 (*((volatile unsigned int*)(0x42A6A184UL))) +#define bM4_DMA2_RPT3_SRPT2 (*((volatile unsigned int*)(0x42A6A188UL))) +#define bM4_DMA2_RPT3_SRPT3 (*((volatile unsigned int*)(0x42A6A18CUL))) +#define bM4_DMA2_RPT3_SRPT4 (*((volatile unsigned int*)(0x42A6A190UL))) +#define bM4_DMA2_RPT3_SRPT5 (*((volatile unsigned int*)(0x42A6A194UL))) +#define bM4_DMA2_RPT3_SRPT6 (*((volatile unsigned int*)(0x42A6A198UL))) +#define bM4_DMA2_RPT3_SRPT7 (*((volatile unsigned int*)(0x42A6A19CUL))) +#define bM4_DMA2_RPT3_SRPT8 (*((volatile unsigned int*)(0x42A6A1A0UL))) +#define bM4_DMA2_RPT3_SRPT9 (*((volatile unsigned int*)(0x42A6A1A4UL))) +#define bM4_DMA2_RPT3_DRPT0 (*((volatile unsigned int*)(0x42A6A1C0UL))) +#define bM4_DMA2_RPT3_DRPT1 (*((volatile unsigned int*)(0x42A6A1C4UL))) +#define bM4_DMA2_RPT3_DRPT2 (*((volatile unsigned int*)(0x42A6A1C8UL))) +#define bM4_DMA2_RPT3_DRPT3 (*((volatile unsigned int*)(0x42A6A1CCUL))) +#define bM4_DMA2_RPT3_DRPT4 (*((volatile unsigned int*)(0x42A6A1D0UL))) +#define bM4_DMA2_RPT3_DRPT5 (*((volatile unsigned int*)(0x42A6A1D4UL))) +#define bM4_DMA2_RPT3_DRPT6 (*((volatile unsigned int*)(0x42A6A1D8UL))) +#define bM4_DMA2_RPT3_DRPT7 (*((volatile unsigned int*)(0x42A6A1DCUL))) +#define bM4_DMA2_RPT3_DRPT8 (*((volatile unsigned int*)(0x42A6A1E0UL))) +#define bM4_DMA2_RPT3_DRPT9 (*((volatile unsigned int*)(0x42A6A1E4UL))) +#define bM4_DMA2_RPTB3_SRPTB0 (*((volatile unsigned int*)(0x42A6A180UL))) +#define bM4_DMA2_RPTB3_SRPTB1 (*((volatile unsigned int*)(0x42A6A184UL))) +#define bM4_DMA2_RPTB3_SRPTB2 (*((volatile unsigned int*)(0x42A6A188UL))) +#define bM4_DMA2_RPTB3_SRPTB3 (*((volatile unsigned int*)(0x42A6A18CUL))) +#define bM4_DMA2_RPTB3_SRPTB4 (*((volatile unsigned int*)(0x42A6A190UL))) +#define bM4_DMA2_RPTB3_SRPTB5 (*((volatile unsigned int*)(0x42A6A194UL))) +#define bM4_DMA2_RPTB3_SRPTB6 (*((volatile unsigned int*)(0x42A6A198UL))) +#define bM4_DMA2_RPTB3_SRPTB7 (*((volatile unsigned int*)(0x42A6A19CUL))) +#define bM4_DMA2_RPTB3_SRPTB8 (*((volatile unsigned int*)(0x42A6A1A0UL))) +#define bM4_DMA2_RPTB3_SRPTB9 (*((volatile unsigned int*)(0x42A6A1A4UL))) +#define bM4_DMA2_RPTB3_DRPTB0 (*((volatile unsigned int*)(0x42A6A1C0UL))) +#define bM4_DMA2_RPTB3_DRPTB1 (*((volatile unsigned int*)(0x42A6A1C4UL))) +#define bM4_DMA2_RPTB3_DRPTB2 (*((volatile unsigned int*)(0x42A6A1C8UL))) +#define bM4_DMA2_RPTB3_DRPTB3 (*((volatile unsigned int*)(0x42A6A1CCUL))) +#define bM4_DMA2_RPTB3_DRPTB4 (*((volatile unsigned int*)(0x42A6A1D0UL))) +#define bM4_DMA2_RPTB3_DRPTB5 (*((volatile unsigned int*)(0x42A6A1D4UL))) +#define bM4_DMA2_RPTB3_DRPTB6 (*((volatile unsigned int*)(0x42A6A1D8UL))) +#define bM4_DMA2_RPTB3_DRPTB7 (*((volatile unsigned int*)(0x42A6A1DCUL))) +#define bM4_DMA2_RPTB3_DRPTB8 (*((volatile unsigned int*)(0x42A6A1E0UL))) +#define bM4_DMA2_RPTB3_DRPTB9 (*((volatile unsigned int*)(0x42A6A1E4UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A6A200UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A6A204UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A6A208UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6A20CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A6A210UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A6A214UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A6A218UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6A21CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A6A220UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A6A224UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A6A228UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6A22CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A6A230UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A6A234UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A6A238UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6A23CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A6A240UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A6A244UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A6A248UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6A24CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A6A250UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A6A254UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A6A258UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6A25CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A6A260UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A6A264UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A6A268UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6A26CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A6A270UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A6A274UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A6A278UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6A27CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST0 (*((volatile unsigned int*)(0x42A6A200UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST1 (*((volatile unsigned int*)(0x42A6A204UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST2 (*((volatile unsigned int*)(0x42A6A208UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST3 (*((volatile unsigned int*)(0x42A6A20CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST4 (*((volatile unsigned int*)(0x42A6A210UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST5 (*((volatile unsigned int*)(0x42A6A214UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST6 (*((volatile unsigned int*)(0x42A6A218UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST7 (*((volatile unsigned int*)(0x42A6A21CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST8 (*((volatile unsigned int*)(0x42A6A220UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST9 (*((volatile unsigned int*)(0x42A6A224UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST10 (*((volatile unsigned int*)(0x42A6A228UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST11 (*((volatile unsigned int*)(0x42A6A22CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST12 (*((volatile unsigned int*)(0x42A6A230UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST13 (*((volatile unsigned int*)(0x42A6A234UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST14 (*((volatile unsigned int*)(0x42A6A238UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST15 (*((volatile unsigned int*)(0x42A6A23CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST16 (*((volatile unsigned int*)(0x42A6A240UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST17 (*((volatile unsigned int*)(0x42A6A244UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST18 (*((volatile unsigned int*)(0x42A6A248UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST19 (*((volatile unsigned int*)(0x42A6A24CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB0 (*((volatile unsigned int*)(0x42A6A250UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB1 (*((volatile unsigned int*)(0x42A6A254UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB2 (*((volatile unsigned int*)(0x42A6A258UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB3 (*((volatile unsigned int*)(0x42A6A25CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB4 (*((volatile unsigned int*)(0x42A6A260UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB5 (*((volatile unsigned int*)(0x42A6A264UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB6 (*((volatile unsigned int*)(0x42A6A268UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB7 (*((volatile unsigned int*)(0x42A6A26CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB8 (*((volatile unsigned int*)(0x42A6A270UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB9 (*((volatile unsigned int*)(0x42A6A274UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB10 (*((volatile unsigned int*)(0x42A6A278UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB11 (*((volatile unsigned int*)(0x42A6A27CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A6A280UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A6A284UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A6A288UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6A28CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A6A290UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A6A294UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A6A298UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6A29CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A6A2A0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A6A2A4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A6A2A8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A6A2ACUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A6A2B0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A6A2B4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A6A2B8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A6A2BCUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A6A2C0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A6A2C4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A6A2C8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A6A2CCUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A6A2D0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A6A2D4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A6A2D8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A6A2DCUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A6A2E0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A6A2E4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A6A2E8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A6A2ECUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A6A2F0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A6A2F4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A6A2F8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A6A2FCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST0 (*((volatile unsigned int*)(0x42A6A280UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST1 (*((volatile unsigned int*)(0x42A6A284UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST2 (*((volatile unsigned int*)(0x42A6A288UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST3 (*((volatile unsigned int*)(0x42A6A28CUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST4 (*((volatile unsigned int*)(0x42A6A290UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST5 (*((volatile unsigned int*)(0x42A6A294UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST6 (*((volatile unsigned int*)(0x42A6A298UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST7 (*((volatile unsigned int*)(0x42A6A29CUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST8 (*((volatile unsigned int*)(0x42A6A2A0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST9 (*((volatile unsigned int*)(0x42A6A2A4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST10 (*((volatile unsigned int*)(0x42A6A2A8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST11 (*((volatile unsigned int*)(0x42A6A2ACUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST12 (*((volatile unsigned int*)(0x42A6A2B0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST13 (*((volatile unsigned int*)(0x42A6A2B4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST14 (*((volatile unsigned int*)(0x42A6A2B8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST15 (*((volatile unsigned int*)(0x42A6A2BCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST16 (*((volatile unsigned int*)(0x42A6A2C0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST17 (*((volatile unsigned int*)(0x42A6A2C4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST18 (*((volatile unsigned int*)(0x42A6A2C8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST19 (*((volatile unsigned int*)(0x42A6A2CCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB0 (*((volatile unsigned int*)(0x42A6A2D0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB1 (*((volatile unsigned int*)(0x42A6A2D4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB2 (*((volatile unsigned int*)(0x42A6A2D8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB3 (*((volatile unsigned int*)(0x42A6A2DCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB4 (*((volatile unsigned int*)(0x42A6A2E0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB5 (*((volatile unsigned int*)(0x42A6A2E4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB6 (*((volatile unsigned int*)(0x42A6A2E8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB7 (*((volatile unsigned int*)(0x42A6A2ECUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB8 (*((volatile unsigned int*)(0x42A6A2F0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB9 (*((volatile unsigned int*)(0x42A6A2F4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB10 (*((volatile unsigned int*)(0x42A6A2F8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB11 (*((volatile unsigned int*)(0x42A6A2FCUL))) +#define bM4_DMA2_LLP3_LLP0 (*((volatile unsigned int*)(0x42A6A308UL))) +#define bM4_DMA2_LLP3_LLP1 (*((volatile unsigned int*)(0x42A6A30CUL))) +#define bM4_DMA2_LLP3_LLP2 (*((volatile unsigned int*)(0x42A6A310UL))) +#define bM4_DMA2_LLP3_LLP3 (*((volatile unsigned int*)(0x42A6A314UL))) +#define bM4_DMA2_LLP3_LLP4 (*((volatile unsigned int*)(0x42A6A318UL))) +#define bM4_DMA2_LLP3_LLP5 (*((volatile unsigned int*)(0x42A6A31CUL))) +#define bM4_DMA2_LLP3_LLP6 (*((volatile unsigned int*)(0x42A6A320UL))) +#define bM4_DMA2_LLP3_LLP7 (*((volatile unsigned int*)(0x42A6A324UL))) +#define bM4_DMA2_LLP3_LLP8 (*((volatile unsigned int*)(0x42A6A328UL))) +#define bM4_DMA2_LLP3_LLP9 (*((volatile unsigned int*)(0x42A6A32CUL))) +#define bM4_DMA2_LLP3_LLP10 (*((volatile unsigned int*)(0x42A6A330UL))) +#define bM4_DMA2_LLP3_LLP11 (*((volatile unsigned int*)(0x42A6A334UL))) +#define bM4_DMA2_LLP3_LLP12 (*((volatile unsigned int*)(0x42A6A338UL))) +#define bM4_DMA2_LLP3_LLP13 (*((volatile unsigned int*)(0x42A6A33CUL))) +#define bM4_DMA2_LLP3_LLP14 (*((volatile unsigned int*)(0x42A6A340UL))) +#define bM4_DMA2_LLP3_LLP15 (*((volatile unsigned int*)(0x42A6A344UL))) +#define bM4_DMA2_LLP3_LLP16 (*((volatile unsigned int*)(0x42A6A348UL))) +#define bM4_DMA2_LLP3_LLP17 (*((volatile unsigned int*)(0x42A6A34CUL))) +#define bM4_DMA2_LLP3_LLP18 (*((volatile unsigned int*)(0x42A6A350UL))) +#define bM4_DMA2_LLP3_LLP19 (*((volatile unsigned int*)(0x42A6A354UL))) +#define bM4_DMA2_LLP3_LLP20 (*((volatile unsigned int*)(0x42A6A358UL))) +#define bM4_DMA2_LLP3_LLP21 (*((volatile unsigned int*)(0x42A6A35CUL))) +#define bM4_DMA2_LLP3_LLP22 (*((volatile unsigned int*)(0x42A6A360UL))) +#define bM4_DMA2_LLP3_LLP23 (*((volatile unsigned int*)(0x42A6A364UL))) +#define bM4_DMA2_LLP3_LLP24 (*((volatile unsigned int*)(0x42A6A368UL))) +#define bM4_DMA2_LLP3_LLP25 (*((volatile unsigned int*)(0x42A6A36CUL))) +#define bM4_DMA2_LLP3_LLP26 (*((volatile unsigned int*)(0x42A6A370UL))) +#define bM4_DMA2_LLP3_LLP27 (*((volatile unsigned int*)(0x42A6A374UL))) +#define bM4_DMA2_LLP3_LLP28 (*((volatile unsigned int*)(0x42A6A378UL))) +#define bM4_DMA2_LLP3_LLP29 (*((volatile unsigned int*)(0x42A6A37CUL))) +#define bM4_DMA2_CH3CTL_SINC0 (*((volatile unsigned int*)(0x42A6A380UL))) +#define bM4_DMA2_CH3CTL_SINC1 (*((volatile unsigned int*)(0x42A6A384UL))) +#define bM4_DMA2_CH3CTL_DINC0 (*((volatile unsigned int*)(0x42A6A388UL))) +#define bM4_DMA2_CH3CTL_DINC1 (*((volatile unsigned int*)(0x42A6A38CUL))) +#define bM4_DMA2_CH3CTL_SRPTEN (*((volatile unsigned int*)(0x42A6A390UL))) +#define bM4_DMA2_CH3CTL_DRPTEN (*((volatile unsigned int*)(0x42A6A394UL))) +#define bM4_DMA2_CH3CTL_SNSEQEN (*((volatile unsigned int*)(0x42A6A398UL))) +#define bM4_DMA2_CH3CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6A39CUL))) +#define bM4_DMA2_CH3CTL_HSIZE0 (*((volatile unsigned int*)(0x42A6A3A0UL))) +#define bM4_DMA2_CH3CTL_HSIZE1 (*((volatile unsigned int*)(0x42A6A3A4UL))) +#define bM4_DMA2_CH3CTL_LLPEN (*((volatile unsigned int*)(0x42A6A3A8UL))) +#define bM4_DMA2_CH3CTL_LLPRUN (*((volatile unsigned int*)(0x42A6A3ACUL))) +#define bM4_DMA2_CH3CTL_IE (*((volatile unsigned int*)(0x42A6A3B0UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A6A500UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A6A504UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A6A508UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6A50CUL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A6A510UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A6A514UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A6A518UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6A51CUL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A6A520UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A6A524UL))) +#define bM4_DMA2_MONDTCTL3_CNT0 (*((volatile unsigned int*)(0x42A6A540UL))) +#define bM4_DMA2_MONDTCTL3_CNT1 (*((volatile unsigned int*)(0x42A6A544UL))) +#define bM4_DMA2_MONDTCTL3_CNT2 (*((volatile unsigned int*)(0x42A6A548UL))) +#define bM4_DMA2_MONDTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6A54CUL))) +#define bM4_DMA2_MONDTCTL3_CNT4 (*((volatile unsigned int*)(0x42A6A550UL))) +#define bM4_DMA2_MONDTCTL3_CNT5 (*((volatile unsigned int*)(0x42A6A554UL))) +#define bM4_DMA2_MONDTCTL3_CNT6 (*((volatile unsigned int*)(0x42A6A558UL))) +#define bM4_DMA2_MONDTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6A55CUL))) +#define bM4_DMA2_MONDTCTL3_CNT8 (*((volatile unsigned int*)(0x42A6A560UL))) +#define bM4_DMA2_MONDTCTL3_CNT9 (*((volatile unsigned int*)(0x42A6A564UL))) +#define bM4_DMA2_MONDTCTL3_CNT10 (*((volatile unsigned int*)(0x42A6A568UL))) +#define bM4_DMA2_MONDTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6A56CUL))) +#define bM4_DMA2_MONDTCTL3_CNT12 (*((volatile unsigned int*)(0x42A6A570UL))) +#define bM4_DMA2_MONDTCTL3_CNT13 (*((volatile unsigned int*)(0x42A6A574UL))) +#define bM4_DMA2_MONDTCTL3_CNT14 (*((volatile unsigned int*)(0x42A6A578UL))) +#define bM4_DMA2_MONDTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6A57CUL))) +#define bM4_DMA2_MONRPT3_SRPT0 (*((volatile unsigned int*)(0x42A6A580UL))) +#define bM4_DMA2_MONRPT3_SRPT1 (*((volatile unsigned int*)(0x42A6A584UL))) +#define bM4_DMA2_MONRPT3_SRPT2 (*((volatile unsigned int*)(0x42A6A588UL))) +#define bM4_DMA2_MONRPT3_SRPT3 (*((volatile unsigned int*)(0x42A6A58CUL))) +#define bM4_DMA2_MONRPT3_SRPT4 (*((volatile unsigned int*)(0x42A6A590UL))) +#define bM4_DMA2_MONRPT3_SRPT5 (*((volatile unsigned int*)(0x42A6A594UL))) +#define bM4_DMA2_MONRPT3_SRPT6 (*((volatile unsigned int*)(0x42A6A598UL))) +#define bM4_DMA2_MONRPT3_SRPT7 (*((volatile unsigned int*)(0x42A6A59CUL))) +#define bM4_DMA2_MONRPT3_SRPT8 (*((volatile unsigned int*)(0x42A6A5A0UL))) +#define bM4_DMA2_MONRPT3_SRPT9 (*((volatile unsigned int*)(0x42A6A5A4UL))) +#define bM4_DMA2_MONRPT3_DRPT0 (*((volatile unsigned int*)(0x42A6A5C0UL))) +#define bM4_DMA2_MONRPT3_DRPT1 (*((volatile unsigned int*)(0x42A6A5C4UL))) +#define bM4_DMA2_MONRPT3_DRPT2 (*((volatile unsigned int*)(0x42A6A5C8UL))) +#define bM4_DMA2_MONRPT3_DRPT3 (*((volatile unsigned int*)(0x42A6A5CCUL))) +#define bM4_DMA2_MONRPT3_DRPT4 (*((volatile unsigned int*)(0x42A6A5D0UL))) +#define bM4_DMA2_MONRPT3_DRPT5 (*((volatile unsigned int*)(0x42A6A5D4UL))) +#define bM4_DMA2_MONRPT3_DRPT6 (*((volatile unsigned int*)(0x42A6A5D8UL))) +#define bM4_DMA2_MONRPT3_DRPT7 (*((volatile unsigned int*)(0x42A6A5DCUL))) +#define bM4_DMA2_MONRPT3_DRPT8 (*((volatile unsigned int*)(0x42A6A5E0UL))) +#define bM4_DMA2_MONRPT3_DRPT9 (*((volatile unsigned int*)(0x42A6A5E4UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A6A600UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A6A604UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A6A608UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6A60CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A6A610UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A6A614UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A6A618UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6A61CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A6A620UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A6A624UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A6A628UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6A62CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A6A630UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A6A634UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A6A638UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6A63CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A6A640UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A6A644UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A6A648UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6A64CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A6A650UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A6A654UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A6A658UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6A65CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A6A660UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A6A664UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A6A668UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6A66CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A6A670UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A6A674UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A6A678UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6A67CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A6A680UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A6A684UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A6A688UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6A68CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A6A690UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A6A694UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A6A698UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6A69CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A6A6A0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A6A6A4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A6A6A8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A6A6ACUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A6A6B0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A6A6B4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A6A6B8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A6A6BCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A6A6C0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A6A6C4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A6A6C8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A6A6CCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A6A6D0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A6A6D4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A6A6D8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A6A6DCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A6A6E0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A6A6E4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A6A6E8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A6A6ECUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A6A6F0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A6A6F4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A6A6F8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A6A6FCUL))) +#define bM4_EFM_FAPRT_FAPRT0 (*((volatile unsigned int*)(0x42208000UL))) +#define bM4_EFM_FAPRT_FAPRT1 (*((volatile unsigned int*)(0x42208004UL))) +#define bM4_EFM_FAPRT_FAPRT2 (*((volatile unsigned int*)(0x42208008UL))) +#define bM4_EFM_FAPRT_FAPRT3 (*((volatile unsigned int*)(0x4220800CUL))) +#define bM4_EFM_FAPRT_FAPRT4 (*((volatile unsigned int*)(0x42208010UL))) +#define bM4_EFM_FAPRT_FAPRT5 (*((volatile unsigned int*)(0x42208014UL))) +#define bM4_EFM_FAPRT_FAPRT6 (*((volatile unsigned int*)(0x42208018UL))) +#define bM4_EFM_FAPRT_FAPRT7 (*((volatile unsigned int*)(0x4220801CUL))) +#define bM4_EFM_FAPRT_FAPRT8 (*((volatile unsigned int*)(0x42208020UL))) +#define bM4_EFM_FAPRT_FAPRT9 (*((volatile unsigned int*)(0x42208024UL))) +#define bM4_EFM_FAPRT_FAPRT10 (*((volatile unsigned int*)(0x42208028UL))) +#define bM4_EFM_FAPRT_FAPRT11 (*((volatile unsigned int*)(0x4220802CUL))) +#define bM4_EFM_FAPRT_FAPRT12 (*((volatile unsigned int*)(0x42208030UL))) +#define bM4_EFM_FAPRT_FAPRT13 (*((volatile unsigned int*)(0x42208034UL))) +#define bM4_EFM_FAPRT_FAPRT14 (*((volatile unsigned int*)(0x42208038UL))) +#define bM4_EFM_FAPRT_FAPRT15 (*((volatile unsigned int*)(0x4220803CUL))) +#define bM4_EFM_FSTP_FSTP (*((volatile unsigned int*)(0x42208080UL))) +#define bM4_EFM_FRMC_SLPMD (*((volatile unsigned int*)(0x42208100UL))) +#define bM4_EFM_FRMC_FLWT0 (*((volatile unsigned int*)(0x42208110UL))) +#define bM4_EFM_FRMC_FLWT1 (*((volatile unsigned int*)(0x42208114UL))) +#define bM4_EFM_FRMC_FLWT2 (*((volatile unsigned int*)(0x42208118UL))) +#define bM4_EFM_FRMC_FLWT3 (*((volatile unsigned int*)(0x4220811CUL))) +#define bM4_EFM_FRMC_LVM (*((volatile unsigned int*)(0x42208120UL))) +#define bM4_EFM_FRMC_CACHE (*((volatile unsigned int*)(0x42208140UL))) +#define bM4_EFM_FRMC_CRST (*((volatile unsigned int*)(0x42208160UL))) +#define bM4_EFM_FWMC_PEMODE (*((volatile unsigned int*)(0x42208180UL))) +#define bM4_EFM_FWMC_PEMOD0 (*((volatile unsigned int*)(0x42208190UL))) +#define bM4_EFM_FWMC_PEMOD1 (*((volatile unsigned int*)(0x42208194UL))) +#define bM4_EFM_FWMC_PEMOD2 (*((volatile unsigned int*)(0x42208198UL))) +#define bM4_EFM_FWMC_BUSHLDCTL (*((volatile unsigned int*)(0x422081A0UL))) +#define bM4_EFM_FSR_PEWERR (*((volatile unsigned int*)(0x42208200UL))) +#define bM4_EFM_FSR_PEPRTERR (*((volatile unsigned int*)(0x42208204UL))) +#define bM4_EFM_FSR_PGSZERR (*((volatile unsigned int*)(0x42208208UL))) +#define bM4_EFM_FSR_PGMISMTCH (*((volatile unsigned int*)(0x4220820CUL))) +#define bM4_EFM_FSR_OPTEND (*((volatile unsigned int*)(0x42208210UL))) +#define bM4_EFM_FSR_COLERR (*((volatile unsigned int*)(0x42208214UL))) +#define bM4_EFM_FSR_RDY (*((volatile unsigned int*)(0x42208220UL))) +#define bM4_EFM_FSCLR_PEWERRCLR (*((volatile unsigned int*)(0x42208280UL))) +#define bM4_EFM_FSCLR_PEPRTERRCLR (*((volatile unsigned int*)(0x42208284UL))) +#define bM4_EFM_FSCLR_PGSZERRCLR (*((volatile unsigned int*)(0x42208288UL))) +#define bM4_EFM_FSCLR_PGMISMTCHCLR (*((volatile unsigned int*)(0x4220828CUL))) +#define bM4_EFM_FSCLR_OPTENDCLR (*((volatile unsigned int*)(0x42208290UL))) +#define bM4_EFM_FSCLR_COLERRCLR (*((volatile unsigned int*)(0x42208294UL))) +#define bM4_EFM_FITE_PEERRITE (*((volatile unsigned int*)(0x42208300UL))) +#define bM4_EFM_FITE_OPTENDITE (*((volatile unsigned int*)(0x42208304UL))) +#define bM4_EFM_FITE_COLERRITE (*((volatile unsigned int*)(0x42208308UL))) +#define bM4_EFM_FSWP_FSWP (*((volatile unsigned int*)(0x42208380UL))) +#define bM4_EFM_FPMTSW_FPMTSW0 (*((volatile unsigned int*)(0x42208400UL))) +#define bM4_EFM_FPMTSW_FPMTSW1 (*((volatile unsigned int*)(0x42208404UL))) +#define bM4_EFM_FPMTSW_FPMTSW2 (*((volatile unsigned int*)(0x42208408UL))) +#define bM4_EFM_FPMTSW_FPMTSW3 (*((volatile unsigned int*)(0x4220840CUL))) +#define bM4_EFM_FPMTSW_FPMTSW4 (*((volatile unsigned int*)(0x42208410UL))) +#define bM4_EFM_FPMTSW_FPMTSW5 (*((volatile unsigned int*)(0x42208414UL))) +#define bM4_EFM_FPMTSW_FPMTSW6 (*((volatile unsigned int*)(0x42208418UL))) +#define bM4_EFM_FPMTSW_FPMTSW7 (*((volatile unsigned int*)(0x4220841CUL))) +#define bM4_EFM_FPMTSW_FPMTSW8 (*((volatile unsigned int*)(0x42208420UL))) +#define bM4_EFM_FPMTSW_FPMTSW9 (*((volatile unsigned int*)(0x42208424UL))) +#define bM4_EFM_FPMTSW_FPMTSW10 (*((volatile unsigned int*)(0x42208428UL))) +#define bM4_EFM_FPMTSW_FPMTSW11 (*((volatile unsigned int*)(0x4220842CUL))) +#define bM4_EFM_FPMTSW_FPMTSW12 (*((volatile unsigned int*)(0x42208430UL))) +#define bM4_EFM_FPMTSW_FPMTSW13 (*((volatile unsigned int*)(0x42208434UL))) +#define bM4_EFM_FPMTSW_FPMTSW14 (*((volatile unsigned int*)(0x42208438UL))) +#define bM4_EFM_FPMTSW_FPMTSW15 (*((volatile unsigned int*)(0x4220843CUL))) +#define bM4_EFM_FPMTSW_FPMTSW16 (*((volatile unsigned int*)(0x42208440UL))) +#define bM4_EFM_FPMTSW_FPMTSW17 (*((volatile unsigned int*)(0x42208444UL))) +#define bM4_EFM_FPMTSW_FPMTSW18 (*((volatile unsigned int*)(0x42208448UL))) +#define bM4_EFM_FPMTEW_FPMTEW0 (*((volatile unsigned int*)(0x42208480UL))) +#define bM4_EFM_FPMTEW_FPMTEW1 (*((volatile unsigned int*)(0x42208484UL))) +#define bM4_EFM_FPMTEW_FPMTEW2 (*((volatile unsigned int*)(0x42208488UL))) +#define bM4_EFM_FPMTEW_FPMTEW3 (*((volatile unsigned int*)(0x4220848CUL))) +#define bM4_EFM_FPMTEW_FPMTEW4 (*((volatile unsigned int*)(0x42208490UL))) +#define bM4_EFM_FPMTEW_FPMTEW5 (*((volatile unsigned int*)(0x42208494UL))) +#define bM4_EFM_FPMTEW_FPMTEW6 (*((volatile unsigned int*)(0x42208498UL))) +#define bM4_EFM_FPMTEW_FPMTEW7 (*((volatile unsigned int*)(0x4220849CUL))) +#define bM4_EFM_FPMTEW_FPMTEW8 (*((volatile unsigned int*)(0x422084A0UL))) +#define bM4_EFM_FPMTEW_FPMTEW9 (*((volatile unsigned int*)(0x422084A4UL))) +#define bM4_EFM_FPMTEW_FPMTEW10 (*((volatile unsigned int*)(0x422084A8UL))) +#define bM4_EFM_FPMTEW_FPMTEW11 (*((volatile unsigned int*)(0x422084ACUL))) +#define bM4_EFM_FPMTEW_FPMTEW12 (*((volatile unsigned int*)(0x422084B0UL))) +#define bM4_EFM_FPMTEW_FPMTEW13 (*((volatile unsigned int*)(0x422084B4UL))) +#define bM4_EFM_FPMTEW_FPMTEW14 (*((volatile unsigned int*)(0x422084B8UL))) +#define bM4_EFM_FPMTEW_FPMTEW15 (*((volatile unsigned int*)(0x422084BCUL))) +#define bM4_EFM_FPMTEW_FPMTEW16 (*((volatile unsigned int*)(0x422084C0UL))) +#define bM4_EFM_FPMTEW_FPMTEW17 (*((volatile unsigned int*)(0x422084C4UL))) +#define bM4_EFM_FPMTEW_FPMTEW18 (*((volatile unsigned int*)(0x422084C8UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT0 (*((volatile unsigned int*)(0x4220A000UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT1 (*((volatile unsigned int*)(0x4220A004UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT2 (*((volatile unsigned int*)(0x4220A008UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT3 (*((volatile unsigned int*)(0x4220A00CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT4 (*((volatile unsigned int*)(0x4220A010UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT5 (*((volatile unsigned int*)(0x4220A014UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT6 (*((volatile unsigned int*)(0x4220A018UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT7 (*((volatile unsigned int*)(0x4220A01CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT8 (*((volatile unsigned int*)(0x4220A020UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT9 (*((volatile unsigned int*)(0x4220A024UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT10 (*((volatile unsigned int*)(0x4220A028UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT11 (*((volatile unsigned int*)(0x4220A02CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT12 (*((volatile unsigned int*)(0x4220A030UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT13 (*((volatile unsigned int*)(0x4220A034UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT14 (*((volatile unsigned int*)(0x4220A038UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT15 (*((volatile unsigned int*)(0x4220A03CUL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE0 (*((volatile unsigned int*)(0x4220A080UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE1 (*((volatile unsigned int*)(0x4220A084UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE2 (*((volatile unsigned int*)(0x4220A088UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE3 (*((volatile unsigned int*)(0x4220A08CUL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE4 (*((volatile unsigned int*)(0x4220A090UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR0 (*((volatile unsigned int*)(0x4220A0B0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR1 (*((volatile unsigned int*)(0x4220A0B4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR2 (*((volatile unsigned int*)(0x4220A0B8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR3 (*((volatile unsigned int*)(0x4220A0BCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR4 (*((volatile unsigned int*)(0x4220A0C0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR5 (*((volatile unsigned int*)(0x4220A0C4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR6 (*((volatile unsigned int*)(0x4220A0C8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR7 (*((volatile unsigned int*)(0x4220A0CCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR8 (*((volatile unsigned int*)(0x4220A0D0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR9 (*((volatile unsigned int*)(0x4220A0D4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR10 (*((volatile unsigned int*)(0x4220A0D8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR11 (*((volatile unsigned int*)(0x4220A0DCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR12 (*((volatile unsigned int*)(0x4220A0E0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR13 (*((volatile unsigned int*)(0x4220A0E4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR14 (*((volatile unsigned int*)(0x4220A0E8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR15 (*((volatile unsigned int*)(0x4220A0ECUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR16 (*((volatile unsigned int*)(0x4220A0F0UL))) +#define bM4_EFM_MMF_REMCR0_EN0 (*((volatile unsigned int*)(0x4220A0FCUL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE0 (*((volatile unsigned int*)(0x4220A100UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE1 (*((volatile unsigned int*)(0x4220A104UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE2 (*((volatile unsigned int*)(0x4220A108UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE3 (*((volatile unsigned int*)(0x4220A10CUL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE4 (*((volatile unsigned int*)(0x4220A110UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR0 (*((volatile unsigned int*)(0x4220A130UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR1 (*((volatile unsigned int*)(0x4220A134UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR2 (*((volatile unsigned int*)(0x4220A138UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR3 (*((volatile unsigned int*)(0x4220A13CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR4 (*((volatile unsigned int*)(0x4220A140UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR5 (*((volatile unsigned int*)(0x4220A144UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR6 (*((volatile unsigned int*)(0x4220A148UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR7 (*((volatile unsigned int*)(0x4220A14CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR8 (*((volatile unsigned int*)(0x4220A150UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR9 (*((volatile unsigned int*)(0x4220A154UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR10 (*((volatile unsigned int*)(0x4220A158UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR11 (*((volatile unsigned int*)(0x4220A15CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR12 (*((volatile unsigned int*)(0x4220A160UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR13 (*((volatile unsigned int*)(0x4220A164UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR14 (*((volatile unsigned int*)(0x4220A168UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR15 (*((volatile unsigned int*)(0x4220A16CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR16 (*((volatile unsigned int*)(0x4220A170UL))) +#define bM4_EFM_MMF_REMCR1_EN1 (*((volatile unsigned int*)(0x4220A17CUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS0 (*((volatile unsigned int*)(0x4220C084UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS1 (*((volatile unsigned int*)(0x4220C088UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS2 (*((volatile unsigned int*)(0x4220C08CUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS3 (*((volatile unsigned int*)(0x4220C090UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS4 (*((volatile unsigned int*)(0x4220C094UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS5 (*((volatile unsigned int*)(0x4220C098UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS6 (*((volatile unsigned int*)(0x4220C09CUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS7 (*((volatile unsigned int*)(0x4220C0A0UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS8 (*((volatile unsigned int*)(0x4220C0A4UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS9 (*((volatile unsigned int*)(0x4220C0A8UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS10 (*((volatile unsigned int*)(0x4220C0ACUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS11 (*((volatile unsigned int*)(0x4220C0B0UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS12 (*((volatile unsigned int*)(0x4220C0B4UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS13 (*((volatile unsigned int*)(0x4220C0B8UL))) +#define bM4_EFM_EFM_FRANDS_FRANDFG (*((volatile unsigned int*)(0x4220C0C0UL))) +#define bM4_EMB1_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8000UL))) +#define bM4_EMB1_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8004UL))) +#define bM4_EMB1_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8008UL))) +#define bM4_EMB1_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F800CUL))) +#define bM4_EMB1_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8014UL))) +#define bM4_EMB1_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8018UL))) +#define bM4_EMB1_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F801CUL))) +#define bM4_EMB1_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8020UL))) +#define bM4_EMB1_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8070UL))) +#define bM4_EMB1_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8074UL))) +#define bM4_EMB1_CTL_NFEN (*((volatile unsigned int*)(0x422F8078UL))) +#define bM4_EMB1_CTL_INVSEL (*((volatile unsigned int*)(0x422F807CUL))) +#define bM4_EMB1_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8080UL))) +#define bM4_EMB1_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8084UL))) +#define bM4_EMB1_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8088UL))) +#define bM4_EMB1_SOE_SOE (*((volatile unsigned int*)(0x422F8100UL))) +#define bM4_EMB1_STAT_PORTINF (*((volatile unsigned int*)(0x422F8180UL))) +#define bM4_EMB1_STAT_PWMSF (*((volatile unsigned int*)(0x422F8184UL))) +#define bM4_EMB1_STAT_CMPF (*((volatile unsigned int*)(0x422F8188UL))) +#define bM4_EMB1_STAT_OSF (*((volatile unsigned int*)(0x422F818CUL))) +#define bM4_EMB1_STAT_PORTINST (*((volatile unsigned int*)(0x422F8190UL))) +#define bM4_EMB1_STAT_PWMST (*((volatile unsigned int*)(0x422F8194UL))) +#define bM4_EMB1_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8200UL))) +#define bM4_EMB1_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8204UL))) +#define bM4_EMB1_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8208UL))) +#define bM4_EMB1_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F820CUL))) +#define bM4_EMB1_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8280UL))) +#define bM4_EMB1_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8284UL))) +#define bM4_EMB1_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8288UL))) +#define bM4_EMB1_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F828CUL))) +#define bM4_EMB2_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8400UL))) +#define bM4_EMB2_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8404UL))) +#define bM4_EMB2_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8408UL))) +#define bM4_EMB2_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F840CUL))) +#define bM4_EMB2_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8414UL))) +#define bM4_EMB2_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8418UL))) +#define bM4_EMB2_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F841CUL))) +#define bM4_EMB2_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8420UL))) +#define bM4_EMB2_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8470UL))) +#define bM4_EMB2_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8474UL))) +#define bM4_EMB2_CTL_NFEN (*((volatile unsigned int*)(0x422F8478UL))) +#define bM4_EMB2_CTL_INVSEL (*((volatile unsigned int*)(0x422F847CUL))) +#define bM4_EMB2_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8480UL))) +#define bM4_EMB2_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8484UL))) +#define bM4_EMB2_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8488UL))) +#define bM4_EMB2_SOE_SOE (*((volatile unsigned int*)(0x422F8500UL))) +#define bM4_EMB2_STAT_PORTINF (*((volatile unsigned int*)(0x422F8580UL))) +#define bM4_EMB2_STAT_PWMSF (*((volatile unsigned int*)(0x422F8584UL))) +#define bM4_EMB2_STAT_CMPF (*((volatile unsigned int*)(0x422F8588UL))) +#define bM4_EMB2_STAT_OSF (*((volatile unsigned int*)(0x422F858CUL))) +#define bM4_EMB2_STAT_PORTINST (*((volatile unsigned int*)(0x422F8590UL))) +#define bM4_EMB2_STAT_PWMST (*((volatile unsigned int*)(0x422F8594UL))) +#define bM4_EMB2_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8600UL))) +#define bM4_EMB2_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8604UL))) +#define bM4_EMB2_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8608UL))) +#define bM4_EMB2_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F860CUL))) +#define bM4_EMB2_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8680UL))) +#define bM4_EMB2_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8684UL))) +#define bM4_EMB2_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8688UL))) +#define bM4_EMB2_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F868CUL))) +#define bM4_EMB3_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8800UL))) +#define bM4_EMB3_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8804UL))) +#define bM4_EMB3_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8808UL))) +#define bM4_EMB3_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F880CUL))) +#define bM4_EMB3_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8814UL))) +#define bM4_EMB3_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8818UL))) +#define bM4_EMB3_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F881CUL))) +#define bM4_EMB3_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8820UL))) +#define bM4_EMB3_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8870UL))) +#define bM4_EMB3_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8874UL))) +#define bM4_EMB3_CTL_NFEN (*((volatile unsigned int*)(0x422F8878UL))) +#define bM4_EMB3_CTL_INVSEL (*((volatile unsigned int*)(0x422F887CUL))) +#define bM4_EMB3_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8880UL))) +#define bM4_EMB3_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8884UL))) +#define bM4_EMB3_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8888UL))) +#define bM4_EMB3_SOE_SOE (*((volatile unsigned int*)(0x422F8900UL))) +#define bM4_EMB3_STAT_PORTINF (*((volatile unsigned int*)(0x422F8980UL))) +#define bM4_EMB3_STAT_PWMSF (*((volatile unsigned int*)(0x422F8984UL))) +#define bM4_EMB3_STAT_CMPF (*((volatile unsigned int*)(0x422F8988UL))) +#define bM4_EMB3_STAT_OSF (*((volatile unsigned int*)(0x422F898CUL))) +#define bM4_EMB3_STAT_PORTINST (*((volatile unsigned int*)(0x422F8990UL))) +#define bM4_EMB3_STAT_PWMST (*((volatile unsigned int*)(0x422F8994UL))) +#define bM4_EMB3_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8A00UL))) +#define bM4_EMB3_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8A04UL))) +#define bM4_EMB3_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8A08UL))) +#define bM4_EMB3_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F8A0CUL))) +#define bM4_EMB3_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8A80UL))) +#define bM4_EMB3_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8A84UL))) +#define bM4_EMB3_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8A88UL))) +#define bM4_EMB3_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F8A8CUL))) +#define bM4_EMB4_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8C00UL))) +#define bM4_EMB4_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8C04UL))) +#define bM4_EMB4_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8C08UL))) +#define bM4_EMB4_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F8C0CUL))) +#define bM4_EMB4_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8C14UL))) +#define bM4_EMB4_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8C18UL))) +#define bM4_EMB4_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F8C1CUL))) +#define bM4_EMB4_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8C20UL))) +#define bM4_EMB4_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8C70UL))) +#define bM4_EMB4_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8C74UL))) +#define bM4_EMB4_CTL_NFEN (*((volatile unsigned int*)(0x422F8C78UL))) +#define bM4_EMB4_CTL_INVSEL (*((volatile unsigned int*)(0x422F8C7CUL))) +#define bM4_EMB4_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8C80UL))) +#define bM4_EMB4_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8C84UL))) +#define bM4_EMB4_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8C88UL))) +#define bM4_EMB4_SOE_SOE (*((volatile unsigned int*)(0x422F8D00UL))) +#define bM4_EMB4_STAT_PORTINF (*((volatile unsigned int*)(0x422F8D80UL))) +#define bM4_EMB4_STAT_PWMSF (*((volatile unsigned int*)(0x422F8D84UL))) +#define bM4_EMB4_STAT_CMPF (*((volatile unsigned int*)(0x422F8D88UL))) +#define bM4_EMB4_STAT_OSF (*((volatile unsigned int*)(0x422F8D8CUL))) +#define bM4_EMB4_STAT_PORTINST (*((volatile unsigned int*)(0x422F8D90UL))) +#define bM4_EMB4_STAT_PWMST (*((volatile unsigned int*)(0x422F8D94UL))) +#define bM4_EMB4_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8E00UL))) +#define bM4_EMB4_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8E04UL))) +#define bM4_EMB4_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8E08UL))) +#define bM4_EMB4_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F8E0CUL))) +#define bM4_EMB4_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8E80UL))) +#define bM4_EMB4_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8E84UL))) +#define bM4_EMB4_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8E88UL))) +#define bM4_EMB4_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F8E8CUL))) +#define bM4_FCM_LVR_LVR0 (*((volatile unsigned int*)(0x42908000UL))) +#define bM4_FCM_LVR_LVR1 (*((volatile unsigned int*)(0x42908004UL))) +#define bM4_FCM_LVR_LVR2 (*((volatile unsigned int*)(0x42908008UL))) +#define bM4_FCM_LVR_LVR3 (*((volatile unsigned int*)(0x4290800CUL))) +#define bM4_FCM_LVR_LVR4 (*((volatile unsigned int*)(0x42908010UL))) +#define bM4_FCM_LVR_LVR5 (*((volatile unsigned int*)(0x42908014UL))) +#define bM4_FCM_LVR_LVR6 (*((volatile unsigned int*)(0x42908018UL))) +#define bM4_FCM_LVR_LVR7 (*((volatile unsigned int*)(0x4290801CUL))) +#define bM4_FCM_LVR_LVR8 (*((volatile unsigned int*)(0x42908020UL))) +#define bM4_FCM_LVR_LVR9 (*((volatile unsigned int*)(0x42908024UL))) +#define bM4_FCM_LVR_LVR10 (*((volatile unsigned int*)(0x42908028UL))) +#define bM4_FCM_LVR_LVR11 (*((volatile unsigned int*)(0x4290802CUL))) +#define bM4_FCM_LVR_LVR12 (*((volatile unsigned int*)(0x42908030UL))) +#define bM4_FCM_LVR_LVR13 (*((volatile unsigned int*)(0x42908034UL))) +#define bM4_FCM_LVR_LVR14 (*((volatile unsigned int*)(0x42908038UL))) +#define bM4_FCM_LVR_LVR15 (*((volatile unsigned int*)(0x4290803CUL))) +#define bM4_FCM_UVR_UVR0 (*((volatile unsigned int*)(0x42908080UL))) +#define bM4_FCM_UVR_UVR1 (*((volatile unsigned int*)(0x42908084UL))) +#define bM4_FCM_UVR_UVR2 (*((volatile unsigned int*)(0x42908088UL))) +#define bM4_FCM_UVR_UVR3 (*((volatile unsigned int*)(0x4290808CUL))) +#define bM4_FCM_UVR_UVR4 (*((volatile unsigned int*)(0x42908090UL))) +#define bM4_FCM_UVR_UVR5 (*((volatile unsigned int*)(0x42908094UL))) +#define bM4_FCM_UVR_UVR6 (*((volatile unsigned int*)(0x42908098UL))) +#define bM4_FCM_UVR_UVR7 (*((volatile unsigned int*)(0x4290809CUL))) +#define bM4_FCM_UVR_UVR8 (*((volatile unsigned int*)(0x429080A0UL))) +#define bM4_FCM_UVR_UVR9 (*((volatile unsigned int*)(0x429080A4UL))) +#define bM4_FCM_UVR_UVR10 (*((volatile unsigned int*)(0x429080A8UL))) +#define bM4_FCM_UVR_UVR11 (*((volatile unsigned int*)(0x429080ACUL))) +#define bM4_FCM_UVR_UVR12 (*((volatile unsigned int*)(0x429080B0UL))) +#define bM4_FCM_UVR_UVR13 (*((volatile unsigned int*)(0x429080B4UL))) +#define bM4_FCM_UVR_UVR14 (*((volatile unsigned int*)(0x429080B8UL))) +#define bM4_FCM_UVR_UVR15 (*((volatile unsigned int*)(0x429080BCUL))) +#define bM4_FCM_CNTR_CNTR0 (*((volatile unsigned int*)(0x42908100UL))) +#define bM4_FCM_CNTR_CNTR1 (*((volatile unsigned int*)(0x42908104UL))) +#define bM4_FCM_CNTR_CNTR2 (*((volatile unsigned int*)(0x42908108UL))) +#define bM4_FCM_CNTR_CNTR3 (*((volatile unsigned int*)(0x4290810CUL))) +#define bM4_FCM_CNTR_CNTR4 (*((volatile unsigned int*)(0x42908110UL))) +#define bM4_FCM_CNTR_CNTR5 (*((volatile unsigned int*)(0x42908114UL))) +#define bM4_FCM_CNTR_CNTR6 (*((volatile unsigned int*)(0x42908118UL))) +#define bM4_FCM_CNTR_CNTR7 (*((volatile unsigned int*)(0x4290811CUL))) +#define bM4_FCM_CNTR_CNTR8 (*((volatile unsigned int*)(0x42908120UL))) +#define bM4_FCM_CNTR_CNTR9 (*((volatile unsigned int*)(0x42908124UL))) +#define bM4_FCM_CNTR_CNTR10 (*((volatile unsigned int*)(0x42908128UL))) +#define bM4_FCM_CNTR_CNTR11 (*((volatile unsigned int*)(0x4290812CUL))) +#define bM4_FCM_CNTR_CNTR12 (*((volatile unsigned int*)(0x42908130UL))) +#define bM4_FCM_CNTR_CNTR13 (*((volatile unsigned int*)(0x42908134UL))) +#define bM4_FCM_CNTR_CNTR14 (*((volatile unsigned int*)(0x42908138UL))) +#define bM4_FCM_CNTR_CNTR15 (*((volatile unsigned int*)(0x4290813CUL))) +#define bM4_FCM_STR_START (*((volatile unsigned int*)(0x42908180UL))) +#define bM4_FCM_MCCR_MDIVS0 (*((volatile unsigned int*)(0x42908200UL))) +#define bM4_FCM_MCCR_MDIVS1 (*((volatile unsigned int*)(0x42908204UL))) +#define bM4_FCM_MCCR_MCKS0 (*((volatile unsigned int*)(0x42908210UL))) +#define bM4_FCM_MCCR_MCKS1 (*((volatile unsigned int*)(0x42908214UL))) +#define bM4_FCM_MCCR_MCKS2 (*((volatile unsigned int*)(0x42908218UL))) +#define bM4_FCM_MCCR_MCKS3 (*((volatile unsigned int*)(0x4290821CUL))) +#define bM4_FCM_RCCR_RDIVS0 (*((volatile unsigned int*)(0x42908280UL))) +#define bM4_FCM_RCCR_RDIVS1 (*((volatile unsigned int*)(0x42908284UL))) +#define bM4_FCM_RCCR_RCKS0 (*((volatile unsigned int*)(0x4290828CUL))) +#define bM4_FCM_RCCR_RCKS1 (*((volatile unsigned int*)(0x42908290UL))) +#define bM4_FCM_RCCR_RCKS2 (*((volatile unsigned int*)(0x42908294UL))) +#define bM4_FCM_RCCR_RCKS3 (*((volatile unsigned int*)(0x42908298UL))) +#define bM4_FCM_RCCR_INEXS (*((volatile unsigned int*)(0x4290829CUL))) +#define bM4_FCM_RCCR_DNFS0 (*((volatile unsigned int*)(0x429082A0UL))) +#define bM4_FCM_RCCR_DNFS1 (*((volatile unsigned int*)(0x429082A4UL))) +#define bM4_FCM_RCCR_EDGES0 (*((volatile unsigned int*)(0x429082B0UL))) +#define bM4_FCM_RCCR_EDGES1 (*((volatile unsigned int*)(0x429082B4UL))) +#define bM4_FCM_RCCR_EXREFE (*((volatile unsigned int*)(0x429082BCUL))) +#define bM4_FCM_RIER_ERRIE (*((volatile unsigned int*)(0x42908300UL))) +#define bM4_FCM_RIER_MENDIE (*((volatile unsigned int*)(0x42908304UL))) +#define bM4_FCM_RIER_OVFIE (*((volatile unsigned int*)(0x42908308UL))) +#define bM4_FCM_RIER_ERRINTRS (*((volatile unsigned int*)(0x42908310UL))) +#define bM4_FCM_RIER_ERRE (*((volatile unsigned int*)(0x4290831CUL))) +#define bM4_FCM_SR_ERRF (*((volatile unsigned int*)(0x42908380UL))) +#define bM4_FCM_SR_MENDF (*((volatile unsigned int*)(0x42908384UL))) +#define bM4_FCM_SR_OVF (*((volatile unsigned int*)(0x42908388UL))) +#define bM4_FCM_CLR_ERRFCLR (*((volatile unsigned int*)(0x42908400UL))) +#define bM4_FCM_CLR_MENDFCLR (*((volatile unsigned int*)(0x42908404UL))) +#define bM4_FCM_CLR_OVFCLR (*((volatile unsigned int*)(0x42908408UL))) +#define bM4_HASH_CR_START (*((volatile unsigned int*)(0x42108000UL))) +#define bM4_HASH_CR_FST_GRP (*((volatile unsigned int*)(0x42108004UL))) +#define bM4_I2C1_CR1_PE (*((volatile unsigned int*)(0x429C0000UL))) +#define bM4_I2C1_CR1_SMBUS (*((volatile unsigned int*)(0x429C0004UL))) +#define bM4_I2C1_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429C0008UL))) +#define bM4_I2C1_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429C000CUL))) +#define bM4_I2C1_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429C0010UL))) +#define bM4_I2C1_CR1_ENGC (*((volatile unsigned int*)(0x429C0018UL))) +#define bM4_I2C1_CR1_RESTART (*((volatile unsigned int*)(0x429C001CUL))) +#define bM4_I2C1_CR1_START (*((volatile unsigned int*)(0x429C0020UL))) +#define bM4_I2C1_CR1_STOP (*((volatile unsigned int*)(0x429C0024UL))) +#define bM4_I2C1_CR1_ACK (*((volatile unsigned int*)(0x429C0028UL))) +#define bM4_I2C1_CR1_SWRST (*((volatile unsigned int*)(0x429C003CUL))) +#define bM4_I2C1_CR2_STARTIE (*((volatile unsigned int*)(0x429C0080UL))) +#define bM4_I2C1_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429C0084UL))) +#define bM4_I2C1_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429C0088UL))) +#define bM4_I2C1_CR2_TENDIE (*((volatile unsigned int*)(0x429C008CUL))) +#define bM4_I2C1_CR2_STOPIE (*((volatile unsigned int*)(0x429C0090UL))) +#define bM4_I2C1_CR2_RFULLIE (*((volatile unsigned int*)(0x429C0098UL))) +#define bM4_I2C1_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429C009CUL))) +#define bM4_I2C1_CR2_ARLOIE (*((volatile unsigned int*)(0x429C00A4UL))) +#define bM4_I2C1_CR2_NACKIE (*((volatile unsigned int*)(0x429C00B0UL))) +#define bM4_I2C1_CR2_TMOUTIE (*((volatile unsigned int*)(0x429C00B8UL))) +#define bM4_I2C1_CR2_GENCALLIE (*((volatile unsigned int*)(0x429C00D0UL))) +#define bM4_I2C1_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429C00D4UL))) +#define bM4_I2C1_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429C00D8UL))) +#define bM4_I2C1_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429C00DCUL))) +#define bM4_I2C1_CR3_TMOUTEN (*((volatile unsigned int*)(0x429C0100UL))) +#define bM4_I2C1_CR3_LTMOUT (*((volatile unsigned int*)(0x429C0104UL))) +#define bM4_I2C1_CR3_HTMOUT (*((volatile unsigned int*)(0x429C0108UL))) +#define bM4_I2C1_CR3_FACKEN (*((volatile unsigned int*)(0x429C011CUL))) +#define bM4_I2C1_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429C0200UL))) +#define bM4_I2C1_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429C0204UL))) +#define bM4_I2C1_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429C0208UL))) +#define bM4_I2C1_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429C020CUL))) +#define bM4_I2C1_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429C0210UL))) +#define bM4_I2C1_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429C0214UL))) +#define bM4_I2C1_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429C0218UL))) +#define bM4_I2C1_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429C021CUL))) +#define bM4_I2C1_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429C0220UL))) +#define bM4_I2C1_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429C0224UL))) +#define bM4_I2C1_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429C0230UL))) +#define bM4_I2C1_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429C023CUL))) +#define bM4_I2C1_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429C0280UL))) +#define bM4_I2C1_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429C0284UL))) +#define bM4_I2C1_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429C0288UL))) +#define bM4_I2C1_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429C028CUL))) +#define bM4_I2C1_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429C0290UL))) +#define bM4_I2C1_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429C0294UL))) +#define bM4_I2C1_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429C0298UL))) +#define bM4_I2C1_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429C029CUL))) +#define bM4_I2C1_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429C02A0UL))) +#define bM4_I2C1_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429C02A4UL))) +#define bM4_I2C1_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429C02B0UL))) +#define bM4_I2C1_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429C02BCUL))) +#define bM4_I2C1_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429C0300UL))) +#define bM4_I2C1_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429C0304UL))) +#define bM4_I2C1_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429C0308UL))) +#define bM4_I2C1_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429C030CUL))) +#define bM4_I2C1_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429C0310UL))) +#define bM4_I2C1_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429C0314UL))) +#define bM4_I2C1_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429C0318UL))) +#define bM4_I2C1_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429C031CUL))) +#define bM4_I2C1_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429C0320UL))) +#define bM4_I2C1_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429C0324UL))) +#define bM4_I2C1_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429C0328UL))) +#define bM4_I2C1_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429C032CUL))) +#define bM4_I2C1_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429C0330UL))) +#define bM4_I2C1_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429C0334UL))) +#define bM4_I2C1_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429C0338UL))) +#define bM4_I2C1_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429C033CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429C0340UL))) +#define bM4_I2C1_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429C0344UL))) +#define bM4_I2C1_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429C0348UL))) +#define bM4_I2C1_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429C034CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429C0350UL))) +#define bM4_I2C1_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429C0354UL))) +#define bM4_I2C1_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429C0358UL))) +#define bM4_I2C1_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429C035CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429C0360UL))) +#define bM4_I2C1_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429C0364UL))) +#define bM4_I2C1_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429C0368UL))) +#define bM4_I2C1_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429C036CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429C0370UL))) +#define bM4_I2C1_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429C0374UL))) +#define bM4_I2C1_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429C0378UL))) +#define bM4_I2C1_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429C037CUL))) +#define bM4_I2C1_SR_STARTF (*((volatile unsigned int*)(0x429C0380UL))) +#define bM4_I2C1_SR_SLADDR0F (*((volatile unsigned int*)(0x429C0384UL))) +#define bM4_I2C1_SR_SLADDR1F (*((volatile unsigned int*)(0x429C0388UL))) +#define bM4_I2C1_SR_TENDF (*((volatile unsigned int*)(0x429C038CUL))) +#define bM4_I2C1_SR_STOPF (*((volatile unsigned int*)(0x429C0390UL))) +#define bM4_I2C1_SR_RFULLF (*((volatile unsigned int*)(0x429C0398UL))) +#define bM4_I2C1_SR_TEMPTYF (*((volatile unsigned int*)(0x429C039CUL))) +#define bM4_I2C1_SR_ARLOF (*((volatile unsigned int*)(0x429C03A4UL))) +#define bM4_I2C1_SR_ACKRF (*((volatile unsigned int*)(0x429C03A8UL))) +#define bM4_I2C1_SR_NACKF (*((volatile unsigned int*)(0x429C03B0UL))) +#define bM4_I2C1_SR_TMOUTF (*((volatile unsigned int*)(0x429C03B8UL))) +#define bM4_I2C1_SR_MSL (*((volatile unsigned int*)(0x429C03C0UL))) +#define bM4_I2C1_SR_BUSY (*((volatile unsigned int*)(0x429C03C4UL))) +#define bM4_I2C1_SR_TRA (*((volatile unsigned int*)(0x429C03C8UL))) +#define bM4_I2C1_SR_GENCALLF (*((volatile unsigned int*)(0x429C03D0UL))) +#define bM4_I2C1_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429C03D4UL))) +#define bM4_I2C1_SR_SMBHOSTF (*((volatile unsigned int*)(0x429C03D8UL))) +#define bM4_I2C1_SR_SMBALRTF (*((volatile unsigned int*)(0x429C03DCUL))) +#define bM4_I2C1_CLR_STARTFCLR (*((volatile unsigned int*)(0x429C0400UL))) +#define bM4_I2C1_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429C0404UL))) +#define bM4_I2C1_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429C0408UL))) +#define bM4_I2C1_CLR_TENDFCLR (*((volatile unsigned int*)(0x429C040CUL))) +#define bM4_I2C1_CLR_STOPFCLR (*((volatile unsigned int*)(0x429C0410UL))) +#define bM4_I2C1_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429C0418UL))) +#define bM4_I2C1_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429C041CUL))) +#define bM4_I2C1_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429C0424UL))) +#define bM4_I2C1_CLR_NACKFCLR (*((volatile unsigned int*)(0x429C0430UL))) +#define bM4_I2C1_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429C0438UL))) +#define bM4_I2C1_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429C0450UL))) +#define bM4_I2C1_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429C0454UL))) +#define bM4_I2C1_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429C0458UL))) +#define bM4_I2C1_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429C045CUL))) +#define bM4_I2C1_DTR_DT0 (*((volatile unsigned int*)(0x429C0480UL))) +#define bM4_I2C1_DTR_DT1 (*((volatile unsigned int*)(0x429C0484UL))) +#define bM4_I2C1_DTR_DT2 (*((volatile unsigned int*)(0x429C0488UL))) +#define bM4_I2C1_DTR_DT3 (*((volatile unsigned int*)(0x429C048CUL))) +#define bM4_I2C1_DTR_DT4 (*((volatile unsigned int*)(0x429C0490UL))) +#define bM4_I2C1_DTR_DT5 (*((volatile unsigned int*)(0x429C0494UL))) +#define bM4_I2C1_DTR_DT6 (*((volatile unsigned int*)(0x429C0498UL))) +#define bM4_I2C1_DTR_DT7 (*((volatile unsigned int*)(0x429C049CUL))) +#define bM4_I2C1_DRR_DR0 (*((volatile unsigned int*)(0x429C0500UL))) +#define bM4_I2C1_DRR_DR1 (*((volatile unsigned int*)(0x429C0504UL))) +#define bM4_I2C1_DRR_DR2 (*((volatile unsigned int*)(0x429C0508UL))) +#define bM4_I2C1_DRR_DR3 (*((volatile unsigned int*)(0x429C050CUL))) +#define bM4_I2C1_DRR_DR4 (*((volatile unsigned int*)(0x429C0510UL))) +#define bM4_I2C1_DRR_DR5 (*((volatile unsigned int*)(0x429C0514UL))) +#define bM4_I2C1_DRR_DR6 (*((volatile unsigned int*)(0x429C0518UL))) +#define bM4_I2C1_DRR_DR7 (*((volatile unsigned int*)(0x429C051CUL))) +#define bM4_I2C1_CCR_SLOWW0 (*((volatile unsigned int*)(0x429C0580UL))) +#define bM4_I2C1_CCR_SLOWW1 (*((volatile unsigned int*)(0x429C0584UL))) +#define bM4_I2C1_CCR_SLOWW2 (*((volatile unsigned int*)(0x429C0588UL))) +#define bM4_I2C1_CCR_SLOWW3 (*((volatile unsigned int*)(0x429C058CUL))) +#define bM4_I2C1_CCR_SLOWW4 (*((volatile unsigned int*)(0x429C0590UL))) +#define bM4_I2C1_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429C05A0UL))) +#define bM4_I2C1_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429C05A4UL))) +#define bM4_I2C1_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429C05A8UL))) +#define bM4_I2C1_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429C05ACUL))) +#define bM4_I2C1_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429C05B0UL))) +#define bM4_I2C1_CCR_FREQ0 (*((volatile unsigned int*)(0x429C05C0UL))) +#define bM4_I2C1_CCR_FREQ1 (*((volatile unsigned int*)(0x429C05C4UL))) +#define bM4_I2C1_CCR_FREQ2 (*((volatile unsigned int*)(0x429C05C8UL))) +#define bM4_I2C1_FLTR_DNF0 (*((volatile unsigned int*)(0x429C0600UL))) +#define bM4_I2C1_FLTR_DNF1 (*((volatile unsigned int*)(0x429C0604UL))) +#define bM4_I2C1_FLTR_DNFEN (*((volatile unsigned int*)(0x429C0610UL))) +#define bM4_I2C1_FLTR_ANFEN (*((volatile unsigned int*)(0x429C0614UL))) +#define bM4_I2C2_CR1_PE (*((volatile unsigned int*)(0x429C8000UL))) +#define bM4_I2C2_CR1_SMBUS (*((volatile unsigned int*)(0x429C8004UL))) +#define bM4_I2C2_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429C8008UL))) +#define bM4_I2C2_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429C800CUL))) +#define bM4_I2C2_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429C8010UL))) +#define bM4_I2C2_CR1_ENGC (*((volatile unsigned int*)(0x429C8018UL))) +#define bM4_I2C2_CR1_RESTART (*((volatile unsigned int*)(0x429C801CUL))) +#define bM4_I2C2_CR1_START (*((volatile unsigned int*)(0x429C8020UL))) +#define bM4_I2C2_CR1_STOP (*((volatile unsigned int*)(0x429C8024UL))) +#define bM4_I2C2_CR1_ACK (*((volatile unsigned int*)(0x429C8028UL))) +#define bM4_I2C2_CR1_SWRST (*((volatile unsigned int*)(0x429C803CUL))) +#define bM4_I2C2_CR2_STARTIE (*((volatile unsigned int*)(0x429C8080UL))) +#define bM4_I2C2_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429C8084UL))) +#define bM4_I2C2_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429C8088UL))) +#define bM4_I2C2_CR2_TENDIE (*((volatile unsigned int*)(0x429C808CUL))) +#define bM4_I2C2_CR2_STOPIE (*((volatile unsigned int*)(0x429C8090UL))) +#define bM4_I2C2_CR2_RFULLIE (*((volatile unsigned int*)(0x429C8098UL))) +#define bM4_I2C2_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429C809CUL))) +#define bM4_I2C2_CR2_ARLOIE (*((volatile unsigned int*)(0x429C80A4UL))) +#define bM4_I2C2_CR2_NACKIE (*((volatile unsigned int*)(0x429C80B0UL))) +#define bM4_I2C2_CR2_TMOUTIE (*((volatile unsigned int*)(0x429C80B8UL))) +#define bM4_I2C2_CR2_GENCALLIE (*((volatile unsigned int*)(0x429C80D0UL))) +#define bM4_I2C2_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429C80D4UL))) +#define bM4_I2C2_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429C80D8UL))) +#define bM4_I2C2_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429C80DCUL))) +#define bM4_I2C2_CR3_TMOUTEN (*((volatile unsigned int*)(0x429C8100UL))) +#define bM4_I2C2_CR3_LTMOUT (*((volatile unsigned int*)(0x429C8104UL))) +#define bM4_I2C2_CR3_HTMOUT (*((volatile unsigned int*)(0x429C8108UL))) +#define bM4_I2C2_CR3_FACKEN (*((volatile unsigned int*)(0x429C811CUL))) +#define bM4_I2C2_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429C8200UL))) +#define bM4_I2C2_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429C8204UL))) +#define bM4_I2C2_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429C8208UL))) +#define bM4_I2C2_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429C820CUL))) +#define bM4_I2C2_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429C8210UL))) +#define bM4_I2C2_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429C8214UL))) +#define bM4_I2C2_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429C8218UL))) +#define bM4_I2C2_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429C821CUL))) +#define bM4_I2C2_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429C8220UL))) +#define bM4_I2C2_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429C8224UL))) +#define bM4_I2C2_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429C8230UL))) +#define bM4_I2C2_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429C823CUL))) +#define bM4_I2C2_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429C8280UL))) +#define bM4_I2C2_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429C8284UL))) +#define bM4_I2C2_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429C8288UL))) +#define bM4_I2C2_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429C828CUL))) +#define bM4_I2C2_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429C8290UL))) +#define bM4_I2C2_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429C8294UL))) +#define bM4_I2C2_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429C8298UL))) +#define bM4_I2C2_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429C829CUL))) +#define bM4_I2C2_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429C82A0UL))) +#define bM4_I2C2_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429C82A4UL))) +#define bM4_I2C2_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429C82B0UL))) +#define bM4_I2C2_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429C82BCUL))) +#define bM4_I2C2_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429C8300UL))) +#define bM4_I2C2_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429C8304UL))) +#define bM4_I2C2_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429C8308UL))) +#define bM4_I2C2_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429C830CUL))) +#define bM4_I2C2_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429C8310UL))) +#define bM4_I2C2_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429C8314UL))) +#define bM4_I2C2_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429C8318UL))) +#define bM4_I2C2_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429C831CUL))) +#define bM4_I2C2_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429C8320UL))) +#define bM4_I2C2_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429C8324UL))) +#define bM4_I2C2_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429C8328UL))) +#define bM4_I2C2_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429C832CUL))) +#define bM4_I2C2_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429C8330UL))) +#define bM4_I2C2_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429C8334UL))) +#define bM4_I2C2_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429C8338UL))) +#define bM4_I2C2_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429C833CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429C8340UL))) +#define bM4_I2C2_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429C8344UL))) +#define bM4_I2C2_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429C8348UL))) +#define bM4_I2C2_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429C834CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429C8350UL))) +#define bM4_I2C2_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429C8354UL))) +#define bM4_I2C2_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429C8358UL))) +#define bM4_I2C2_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429C835CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429C8360UL))) +#define bM4_I2C2_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429C8364UL))) +#define bM4_I2C2_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429C8368UL))) +#define bM4_I2C2_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429C836CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429C8370UL))) +#define bM4_I2C2_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429C8374UL))) +#define bM4_I2C2_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429C8378UL))) +#define bM4_I2C2_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429C837CUL))) +#define bM4_I2C2_SR_STARTF (*((volatile unsigned int*)(0x429C8380UL))) +#define bM4_I2C2_SR_SLADDR0F (*((volatile unsigned int*)(0x429C8384UL))) +#define bM4_I2C2_SR_SLADDR1F (*((volatile unsigned int*)(0x429C8388UL))) +#define bM4_I2C2_SR_TENDF (*((volatile unsigned int*)(0x429C838CUL))) +#define bM4_I2C2_SR_STOPF (*((volatile unsigned int*)(0x429C8390UL))) +#define bM4_I2C2_SR_RFULLF (*((volatile unsigned int*)(0x429C8398UL))) +#define bM4_I2C2_SR_TEMPTYF (*((volatile unsigned int*)(0x429C839CUL))) +#define bM4_I2C2_SR_ARLOF (*((volatile unsigned int*)(0x429C83A4UL))) +#define bM4_I2C2_SR_ACKRF (*((volatile unsigned int*)(0x429C83A8UL))) +#define bM4_I2C2_SR_NACKF (*((volatile unsigned int*)(0x429C83B0UL))) +#define bM4_I2C2_SR_TMOUTF (*((volatile unsigned int*)(0x429C83B8UL))) +#define bM4_I2C2_SR_MSL (*((volatile unsigned int*)(0x429C83C0UL))) +#define bM4_I2C2_SR_BUSY (*((volatile unsigned int*)(0x429C83C4UL))) +#define bM4_I2C2_SR_TRA (*((volatile unsigned int*)(0x429C83C8UL))) +#define bM4_I2C2_SR_GENCALLF (*((volatile unsigned int*)(0x429C83D0UL))) +#define bM4_I2C2_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429C83D4UL))) +#define bM4_I2C2_SR_SMBHOSTF (*((volatile unsigned int*)(0x429C83D8UL))) +#define bM4_I2C2_SR_SMBALRTF (*((volatile unsigned int*)(0x429C83DCUL))) +#define bM4_I2C2_CLR_STARTFCLR (*((volatile unsigned int*)(0x429C8400UL))) +#define bM4_I2C2_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429C8404UL))) +#define bM4_I2C2_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429C8408UL))) +#define bM4_I2C2_CLR_TENDFCLR (*((volatile unsigned int*)(0x429C840CUL))) +#define bM4_I2C2_CLR_STOPFCLR (*((volatile unsigned int*)(0x429C8410UL))) +#define bM4_I2C2_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429C8418UL))) +#define bM4_I2C2_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429C841CUL))) +#define bM4_I2C2_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429C8424UL))) +#define bM4_I2C2_CLR_NACKFCLR (*((volatile unsigned int*)(0x429C8430UL))) +#define bM4_I2C2_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429C8438UL))) +#define bM4_I2C2_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429C8450UL))) +#define bM4_I2C2_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429C8454UL))) +#define bM4_I2C2_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429C8458UL))) +#define bM4_I2C2_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429C845CUL))) +#define bM4_I2C2_DTR_DT0 (*((volatile unsigned int*)(0x429C8480UL))) +#define bM4_I2C2_DTR_DT1 (*((volatile unsigned int*)(0x429C8484UL))) +#define bM4_I2C2_DTR_DT2 (*((volatile unsigned int*)(0x429C8488UL))) +#define bM4_I2C2_DTR_DT3 (*((volatile unsigned int*)(0x429C848CUL))) +#define bM4_I2C2_DTR_DT4 (*((volatile unsigned int*)(0x429C8490UL))) +#define bM4_I2C2_DTR_DT5 (*((volatile unsigned int*)(0x429C8494UL))) +#define bM4_I2C2_DTR_DT6 (*((volatile unsigned int*)(0x429C8498UL))) +#define bM4_I2C2_DTR_DT7 (*((volatile unsigned int*)(0x429C849CUL))) +#define bM4_I2C2_DRR_DR0 (*((volatile unsigned int*)(0x429C8500UL))) +#define bM4_I2C2_DRR_DR1 (*((volatile unsigned int*)(0x429C8504UL))) +#define bM4_I2C2_DRR_DR2 (*((volatile unsigned int*)(0x429C8508UL))) +#define bM4_I2C2_DRR_DR3 (*((volatile unsigned int*)(0x429C850CUL))) +#define bM4_I2C2_DRR_DR4 (*((volatile unsigned int*)(0x429C8510UL))) +#define bM4_I2C2_DRR_DR5 (*((volatile unsigned int*)(0x429C8514UL))) +#define bM4_I2C2_DRR_DR6 (*((volatile unsigned int*)(0x429C8518UL))) +#define bM4_I2C2_DRR_DR7 (*((volatile unsigned int*)(0x429C851CUL))) +#define bM4_I2C2_CCR_SLOWW0 (*((volatile unsigned int*)(0x429C8580UL))) +#define bM4_I2C2_CCR_SLOWW1 (*((volatile unsigned int*)(0x429C8584UL))) +#define bM4_I2C2_CCR_SLOWW2 (*((volatile unsigned int*)(0x429C8588UL))) +#define bM4_I2C2_CCR_SLOWW3 (*((volatile unsigned int*)(0x429C858CUL))) +#define bM4_I2C2_CCR_SLOWW4 (*((volatile unsigned int*)(0x429C8590UL))) +#define bM4_I2C2_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429C85A0UL))) +#define bM4_I2C2_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429C85A4UL))) +#define bM4_I2C2_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429C85A8UL))) +#define bM4_I2C2_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429C85ACUL))) +#define bM4_I2C2_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429C85B0UL))) +#define bM4_I2C2_CCR_FREQ0 (*((volatile unsigned int*)(0x429C85C0UL))) +#define bM4_I2C2_CCR_FREQ1 (*((volatile unsigned int*)(0x429C85C4UL))) +#define bM4_I2C2_CCR_FREQ2 (*((volatile unsigned int*)(0x429C85C8UL))) +#define bM4_I2C2_FLTR_DNF0 (*((volatile unsigned int*)(0x429C8600UL))) +#define bM4_I2C2_FLTR_DNF1 (*((volatile unsigned int*)(0x429C8604UL))) +#define bM4_I2C2_FLTR_DNFEN (*((volatile unsigned int*)(0x429C8610UL))) +#define bM4_I2C2_FLTR_ANFEN (*((volatile unsigned int*)(0x429C8614UL))) +#define bM4_I2C3_CR1_PE (*((volatile unsigned int*)(0x429D0000UL))) +#define bM4_I2C3_CR1_SMBUS (*((volatile unsigned int*)(0x429D0004UL))) +#define bM4_I2C3_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429D0008UL))) +#define bM4_I2C3_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429D000CUL))) +#define bM4_I2C3_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429D0010UL))) +#define bM4_I2C3_CR1_ENGC (*((volatile unsigned int*)(0x429D0018UL))) +#define bM4_I2C3_CR1_RESTART (*((volatile unsigned int*)(0x429D001CUL))) +#define bM4_I2C3_CR1_START (*((volatile unsigned int*)(0x429D0020UL))) +#define bM4_I2C3_CR1_STOP (*((volatile unsigned int*)(0x429D0024UL))) +#define bM4_I2C3_CR1_ACK (*((volatile unsigned int*)(0x429D0028UL))) +#define bM4_I2C3_CR1_SWRST (*((volatile unsigned int*)(0x429D003CUL))) +#define bM4_I2C3_CR2_STARTIE (*((volatile unsigned int*)(0x429D0080UL))) +#define bM4_I2C3_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429D0084UL))) +#define bM4_I2C3_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429D0088UL))) +#define bM4_I2C3_CR2_TENDIE (*((volatile unsigned int*)(0x429D008CUL))) +#define bM4_I2C3_CR2_STOPIE (*((volatile unsigned int*)(0x429D0090UL))) +#define bM4_I2C3_CR2_RFULLIE (*((volatile unsigned int*)(0x429D0098UL))) +#define bM4_I2C3_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429D009CUL))) +#define bM4_I2C3_CR2_ARLOIE (*((volatile unsigned int*)(0x429D00A4UL))) +#define bM4_I2C3_CR2_NACKIE (*((volatile unsigned int*)(0x429D00B0UL))) +#define bM4_I2C3_CR2_TMOUTIE (*((volatile unsigned int*)(0x429D00B8UL))) +#define bM4_I2C3_CR2_GENCALLIE (*((volatile unsigned int*)(0x429D00D0UL))) +#define bM4_I2C3_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429D00D4UL))) +#define bM4_I2C3_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429D00D8UL))) +#define bM4_I2C3_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429D00DCUL))) +#define bM4_I2C3_CR3_TMOUTEN (*((volatile unsigned int*)(0x429D0100UL))) +#define bM4_I2C3_CR3_LTMOUT (*((volatile unsigned int*)(0x429D0104UL))) +#define bM4_I2C3_CR3_HTMOUT (*((volatile unsigned int*)(0x429D0108UL))) +#define bM4_I2C3_CR3_FACKEN (*((volatile unsigned int*)(0x429D011CUL))) +#define bM4_I2C3_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429D0200UL))) +#define bM4_I2C3_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429D0204UL))) +#define bM4_I2C3_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429D0208UL))) +#define bM4_I2C3_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429D020CUL))) +#define bM4_I2C3_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429D0210UL))) +#define bM4_I2C3_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429D0214UL))) +#define bM4_I2C3_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429D0218UL))) +#define bM4_I2C3_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429D021CUL))) +#define bM4_I2C3_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429D0220UL))) +#define bM4_I2C3_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429D0224UL))) +#define bM4_I2C3_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429D0230UL))) +#define bM4_I2C3_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429D023CUL))) +#define bM4_I2C3_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429D0280UL))) +#define bM4_I2C3_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429D0284UL))) +#define bM4_I2C3_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429D0288UL))) +#define bM4_I2C3_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429D028CUL))) +#define bM4_I2C3_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429D0290UL))) +#define bM4_I2C3_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429D0294UL))) +#define bM4_I2C3_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429D0298UL))) +#define bM4_I2C3_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429D029CUL))) +#define bM4_I2C3_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429D02A0UL))) +#define bM4_I2C3_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429D02A4UL))) +#define bM4_I2C3_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429D02B0UL))) +#define bM4_I2C3_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429D02BCUL))) +#define bM4_I2C3_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429D0300UL))) +#define bM4_I2C3_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429D0304UL))) +#define bM4_I2C3_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429D0308UL))) +#define bM4_I2C3_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429D030CUL))) +#define bM4_I2C3_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429D0310UL))) +#define bM4_I2C3_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429D0314UL))) +#define bM4_I2C3_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429D0318UL))) +#define bM4_I2C3_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429D031CUL))) +#define bM4_I2C3_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429D0320UL))) +#define bM4_I2C3_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429D0324UL))) +#define bM4_I2C3_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429D0328UL))) +#define bM4_I2C3_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429D032CUL))) +#define bM4_I2C3_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429D0330UL))) +#define bM4_I2C3_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429D0334UL))) +#define bM4_I2C3_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429D0338UL))) +#define bM4_I2C3_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429D033CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429D0340UL))) +#define bM4_I2C3_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429D0344UL))) +#define bM4_I2C3_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429D0348UL))) +#define bM4_I2C3_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429D034CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429D0350UL))) +#define bM4_I2C3_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429D0354UL))) +#define bM4_I2C3_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429D0358UL))) +#define bM4_I2C3_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429D035CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429D0360UL))) +#define bM4_I2C3_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429D0364UL))) +#define bM4_I2C3_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429D0368UL))) +#define bM4_I2C3_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429D036CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429D0370UL))) +#define bM4_I2C3_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429D0374UL))) +#define bM4_I2C3_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429D0378UL))) +#define bM4_I2C3_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429D037CUL))) +#define bM4_I2C3_SR_STARTF (*((volatile unsigned int*)(0x429D0380UL))) +#define bM4_I2C3_SR_SLADDR0F (*((volatile unsigned int*)(0x429D0384UL))) +#define bM4_I2C3_SR_SLADDR1F (*((volatile unsigned int*)(0x429D0388UL))) +#define bM4_I2C3_SR_TENDF (*((volatile unsigned int*)(0x429D038CUL))) +#define bM4_I2C3_SR_STOPF (*((volatile unsigned int*)(0x429D0390UL))) +#define bM4_I2C3_SR_RFULLF (*((volatile unsigned int*)(0x429D0398UL))) +#define bM4_I2C3_SR_TEMPTYF (*((volatile unsigned int*)(0x429D039CUL))) +#define bM4_I2C3_SR_ARLOF (*((volatile unsigned int*)(0x429D03A4UL))) +#define bM4_I2C3_SR_ACKRF (*((volatile unsigned int*)(0x429D03A8UL))) +#define bM4_I2C3_SR_NACKF (*((volatile unsigned int*)(0x429D03B0UL))) +#define bM4_I2C3_SR_TMOUTF (*((volatile unsigned int*)(0x429D03B8UL))) +#define bM4_I2C3_SR_MSL (*((volatile unsigned int*)(0x429D03C0UL))) +#define bM4_I2C3_SR_BUSY (*((volatile unsigned int*)(0x429D03C4UL))) +#define bM4_I2C3_SR_TRA (*((volatile unsigned int*)(0x429D03C8UL))) +#define bM4_I2C3_SR_GENCALLF (*((volatile unsigned int*)(0x429D03D0UL))) +#define bM4_I2C3_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429D03D4UL))) +#define bM4_I2C3_SR_SMBHOSTF (*((volatile unsigned int*)(0x429D03D8UL))) +#define bM4_I2C3_SR_SMBALRTF (*((volatile unsigned int*)(0x429D03DCUL))) +#define bM4_I2C3_CLR_STARTFCLR (*((volatile unsigned int*)(0x429D0400UL))) +#define bM4_I2C3_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429D0404UL))) +#define bM4_I2C3_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429D0408UL))) +#define bM4_I2C3_CLR_TENDFCLR (*((volatile unsigned int*)(0x429D040CUL))) +#define bM4_I2C3_CLR_STOPFCLR (*((volatile unsigned int*)(0x429D0410UL))) +#define bM4_I2C3_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429D0418UL))) +#define bM4_I2C3_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429D041CUL))) +#define bM4_I2C3_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429D0424UL))) +#define bM4_I2C3_CLR_NACKFCLR (*((volatile unsigned int*)(0x429D0430UL))) +#define bM4_I2C3_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429D0438UL))) +#define bM4_I2C3_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429D0450UL))) +#define bM4_I2C3_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429D0454UL))) +#define bM4_I2C3_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429D0458UL))) +#define bM4_I2C3_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429D045CUL))) +#define bM4_I2C3_DTR_DT0 (*((volatile unsigned int*)(0x429D0480UL))) +#define bM4_I2C3_DTR_DT1 (*((volatile unsigned int*)(0x429D0484UL))) +#define bM4_I2C3_DTR_DT2 (*((volatile unsigned int*)(0x429D0488UL))) +#define bM4_I2C3_DTR_DT3 (*((volatile unsigned int*)(0x429D048CUL))) +#define bM4_I2C3_DTR_DT4 (*((volatile unsigned int*)(0x429D0490UL))) +#define bM4_I2C3_DTR_DT5 (*((volatile unsigned int*)(0x429D0494UL))) +#define bM4_I2C3_DTR_DT6 (*((volatile unsigned int*)(0x429D0498UL))) +#define bM4_I2C3_DTR_DT7 (*((volatile unsigned int*)(0x429D049CUL))) +#define bM4_I2C3_DRR_DR0 (*((volatile unsigned int*)(0x429D0500UL))) +#define bM4_I2C3_DRR_DR1 (*((volatile unsigned int*)(0x429D0504UL))) +#define bM4_I2C3_DRR_DR2 (*((volatile unsigned int*)(0x429D0508UL))) +#define bM4_I2C3_DRR_DR3 (*((volatile unsigned int*)(0x429D050CUL))) +#define bM4_I2C3_DRR_DR4 (*((volatile unsigned int*)(0x429D0510UL))) +#define bM4_I2C3_DRR_DR5 (*((volatile unsigned int*)(0x429D0514UL))) +#define bM4_I2C3_DRR_DR6 (*((volatile unsigned int*)(0x429D0518UL))) +#define bM4_I2C3_DRR_DR7 (*((volatile unsigned int*)(0x429D051CUL))) +#define bM4_I2C3_CCR_SLOWW0 (*((volatile unsigned int*)(0x429D0580UL))) +#define bM4_I2C3_CCR_SLOWW1 (*((volatile unsigned int*)(0x429D0584UL))) +#define bM4_I2C3_CCR_SLOWW2 (*((volatile unsigned int*)(0x429D0588UL))) +#define bM4_I2C3_CCR_SLOWW3 (*((volatile unsigned int*)(0x429D058CUL))) +#define bM4_I2C3_CCR_SLOWW4 (*((volatile unsigned int*)(0x429D0590UL))) +#define bM4_I2C3_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429D05A0UL))) +#define bM4_I2C3_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429D05A4UL))) +#define bM4_I2C3_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429D05A8UL))) +#define bM4_I2C3_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429D05ACUL))) +#define bM4_I2C3_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429D05B0UL))) +#define bM4_I2C3_CCR_FREQ0 (*((volatile unsigned int*)(0x429D05C0UL))) +#define bM4_I2C3_CCR_FREQ1 (*((volatile unsigned int*)(0x429D05C4UL))) +#define bM4_I2C3_CCR_FREQ2 (*((volatile unsigned int*)(0x429D05C8UL))) +#define bM4_I2C3_FLTR_DNF0 (*((volatile unsigned int*)(0x429D0600UL))) +#define bM4_I2C3_FLTR_DNF1 (*((volatile unsigned int*)(0x429D0604UL))) +#define bM4_I2C3_FLTR_DNFEN (*((volatile unsigned int*)(0x429D0610UL))) +#define bM4_I2C3_FLTR_ANFEN (*((volatile unsigned int*)(0x429D0614UL))) +#define bM4_I2S1_CTRL_TXE (*((volatile unsigned int*)(0x423C0000UL))) +#define bM4_I2S1_CTRL_TXIE (*((volatile unsigned int*)(0x423C0004UL))) +#define bM4_I2S1_CTRL_RXE (*((volatile unsigned int*)(0x423C0008UL))) +#define bM4_I2S1_CTRL_RXIE (*((volatile unsigned int*)(0x423C000CUL))) +#define bM4_I2S1_CTRL_EIE (*((volatile unsigned int*)(0x423C0010UL))) +#define bM4_I2S1_CTRL_WMS (*((volatile unsigned int*)(0x423C0014UL))) +#define bM4_I2S1_CTRL_ODD (*((volatile unsigned int*)(0x423C0018UL))) +#define bM4_I2S1_CTRL_MCKOE (*((volatile unsigned int*)(0x423C001CUL))) +#define bM4_I2S1_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x423C0020UL))) +#define bM4_I2S1_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x423C0024UL))) +#define bM4_I2S1_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x423C0028UL))) +#define bM4_I2S1_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x423C0030UL))) +#define bM4_I2S1_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x423C0034UL))) +#define bM4_I2S1_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x423C0038UL))) +#define bM4_I2S1_CTRL_FIFOR (*((volatile unsigned int*)(0x423C0040UL))) +#define bM4_I2S1_CTRL_CODECRC (*((volatile unsigned int*)(0x423C0044UL))) +#define bM4_I2S1_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x423C0048UL))) +#define bM4_I2S1_CTRL_SDOE (*((volatile unsigned int*)(0x423C004CUL))) +#define bM4_I2S1_CTRL_LRCKOE (*((volatile unsigned int*)(0x423C0050UL))) +#define bM4_I2S1_CTRL_CKOE (*((volatile unsigned int*)(0x423C0054UL))) +#define bM4_I2S1_CTRL_DUPLEX (*((volatile unsigned int*)(0x423C0058UL))) +#define bM4_I2S1_CTRL_CLKSEL (*((volatile unsigned int*)(0x423C005CUL))) +#define bM4_I2S1_SR_TXBA (*((volatile unsigned int*)(0x423C0080UL))) +#define bM4_I2S1_SR_RXBA (*((volatile unsigned int*)(0x423C0084UL))) +#define bM4_I2S1_SR_TXBE (*((volatile unsigned int*)(0x423C0088UL))) +#define bM4_I2S1_SR_TXBF (*((volatile unsigned int*)(0x423C008CUL))) +#define bM4_I2S1_SR_RXBE (*((volatile unsigned int*)(0x423C0090UL))) +#define bM4_I2S1_SR_RXBF (*((volatile unsigned int*)(0x423C0094UL))) +#define bM4_I2S1_ER_TXERR (*((volatile unsigned int*)(0x423C0100UL))) +#define bM4_I2S1_ER_RXERR (*((volatile unsigned int*)(0x423C0104UL))) +#define bM4_I2S1_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x423C0180UL))) +#define bM4_I2S1_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x423C0184UL))) +#define bM4_I2S1_CFGR_DATLEN0 (*((volatile unsigned int*)(0x423C0188UL))) +#define bM4_I2S1_CFGR_DATLEN1 (*((volatile unsigned int*)(0x423C018CUL))) +#define bM4_I2S1_CFGR_CHLEN (*((volatile unsigned int*)(0x423C0190UL))) +#define bM4_I2S1_CFGR_PCMSYNC (*((volatile unsigned int*)(0x423C0194UL))) +#define bM4_I2S1_PR_I2SDIV0 (*((volatile unsigned int*)(0x423C0300UL))) +#define bM4_I2S1_PR_I2SDIV1 (*((volatile unsigned int*)(0x423C0304UL))) +#define bM4_I2S1_PR_I2SDIV2 (*((volatile unsigned int*)(0x423C0308UL))) +#define bM4_I2S1_PR_I2SDIV3 (*((volatile unsigned int*)(0x423C030CUL))) +#define bM4_I2S1_PR_I2SDIV4 (*((volatile unsigned int*)(0x423C0310UL))) +#define bM4_I2S1_PR_I2SDIV5 (*((volatile unsigned int*)(0x423C0314UL))) +#define bM4_I2S1_PR_I2SDIV6 (*((volatile unsigned int*)(0x423C0318UL))) +#define bM4_I2S1_PR_I2SDIV7 (*((volatile unsigned int*)(0x423C031CUL))) +#define bM4_I2S2_CTRL_TXE (*((volatile unsigned int*)(0x423C8000UL))) +#define bM4_I2S2_CTRL_TXIE (*((volatile unsigned int*)(0x423C8004UL))) +#define bM4_I2S2_CTRL_RXE (*((volatile unsigned int*)(0x423C8008UL))) +#define bM4_I2S2_CTRL_RXIE (*((volatile unsigned int*)(0x423C800CUL))) +#define bM4_I2S2_CTRL_EIE (*((volatile unsigned int*)(0x423C8010UL))) +#define bM4_I2S2_CTRL_WMS (*((volatile unsigned int*)(0x423C8014UL))) +#define bM4_I2S2_CTRL_ODD (*((volatile unsigned int*)(0x423C8018UL))) +#define bM4_I2S2_CTRL_MCKOE (*((volatile unsigned int*)(0x423C801CUL))) +#define bM4_I2S2_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x423C8020UL))) +#define bM4_I2S2_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x423C8024UL))) +#define bM4_I2S2_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x423C8028UL))) +#define bM4_I2S2_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x423C8030UL))) +#define bM4_I2S2_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x423C8034UL))) +#define bM4_I2S2_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x423C8038UL))) +#define bM4_I2S2_CTRL_FIFOR (*((volatile unsigned int*)(0x423C8040UL))) +#define bM4_I2S2_CTRL_CODECRC (*((volatile unsigned int*)(0x423C8044UL))) +#define bM4_I2S2_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x423C8048UL))) +#define bM4_I2S2_CTRL_SDOE (*((volatile unsigned int*)(0x423C804CUL))) +#define bM4_I2S2_CTRL_LRCKOE (*((volatile unsigned int*)(0x423C8050UL))) +#define bM4_I2S2_CTRL_CKOE (*((volatile unsigned int*)(0x423C8054UL))) +#define bM4_I2S2_CTRL_DUPLEX (*((volatile unsigned int*)(0x423C8058UL))) +#define bM4_I2S2_CTRL_CLKSEL (*((volatile unsigned int*)(0x423C805CUL))) +#define bM4_I2S2_SR_TXBA (*((volatile unsigned int*)(0x423C8080UL))) +#define bM4_I2S2_SR_RXBA (*((volatile unsigned int*)(0x423C8084UL))) +#define bM4_I2S2_SR_TXBE (*((volatile unsigned int*)(0x423C8088UL))) +#define bM4_I2S2_SR_TXBF (*((volatile unsigned int*)(0x423C808CUL))) +#define bM4_I2S2_SR_RXBE (*((volatile unsigned int*)(0x423C8090UL))) +#define bM4_I2S2_SR_RXBF (*((volatile unsigned int*)(0x423C8094UL))) +#define bM4_I2S2_ER_TXERR (*((volatile unsigned int*)(0x423C8100UL))) +#define bM4_I2S2_ER_RXERR (*((volatile unsigned int*)(0x423C8104UL))) +#define bM4_I2S2_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x423C8180UL))) +#define bM4_I2S2_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x423C8184UL))) +#define bM4_I2S2_CFGR_DATLEN0 (*((volatile unsigned int*)(0x423C8188UL))) +#define bM4_I2S2_CFGR_DATLEN1 (*((volatile unsigned int*)(0x423C818CUL))) +#define bM4_I2S2_CFGR_CHLEN (*((volatile unsigned int*)(0x423C8190UL))) +#define bM4_I2S2_CFGR_PCMSYNC (*((volatile unsigned int*)(0x423C8194UL))) +#define bM4_I2S2_PR_I2SDIV0 (*((volatile unsigned int*)(0x423C8300UL))) +#define bM4_I2S2_PR_I2SDIV1 (*((volatile unsigned int*)(0x423C8304UL))) +#define bM4_I2S2_PR_I2SDIV2 (*((volatile unsigned int*)(0x423C8308UL))) +#define bM4_I2S2_PR_I2SDIV3 (*((volatile unsigned int*)(0x423C830CUL))) +#define bM4_I2S2_PR_I2SDIV4 (*((volatile unsigned int*)(0x423C8310UL))) +#define bM4_I2S2_PR_I2SDIV5 (*((volatile unsigned int*)(0x423C8314UL))) +#define bM4_I2S2_PR_I2SDIV6 (*((volatile unsigned int*)(0x423C8318UL))) +#define bM4_I2S2_PR_I2SDIV7 (*((volatile unsigned int*)(0x423C831CUL))) +#define bM4_I2S3_CTRL_TXE (*((volatile unsigned int*)(0x42440000UL))) +#define bM4_I2S3_CTRL_TXIE (*((volatile unsigned int*)(0x42440004UL))) +#define bM4_I2S3_CTRL_RXE (*((volatile unsigned int*)(0x42440008UL))) +#define bM4_I2S3_CTRL_RXIE (*((volatile unsigned int*)(0x4244000CUL))) +#define bM4_I2S3_CTRL_EIE (*((volatile unsigned int*)(0x42440010UL))) +#define bM4_I2S3_CTRL_WMS (*((volatile unsigned int*)(0x42440014UL))) +#define bM4_I2S3_CTRL_ODD (*((volatile unsigned int*)(0x42440018UL))) +#define bM4_I2S3_CTRL_MCKOE (*((volatile unsigned int*)(0x4244001CUL))) +#define bM4_I2S3_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x42440020UL))) +#define bM4_I2S3_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x42440024UL))) +#define bM4_I2S3_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x42440028UL))) +#define bM4_I2S3_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x42440030UL))) +#define bM4_I2S3_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x42440034UL))) +#define bM4_I2S3_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x42440038UL))) +#define bM4_I2S3_CTRL_FIFOR (*((volatile unsigned int*)(0x42440040UL))) +#define bM4_I2S3_CTRL_CODECRC (*((volatile unsigned int*)(0x42440044UL))) +#define bM4_I2S3_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x42440048UL))) +#define bM4_I2S3_CTRL_SDOE (*((volatile unsigned int*)(0x4244004CUL))) +#define bM4_I2S3_CTRL_LRCKOE (*((volatile unsigned int*)(0x42440050UL))) +#define bM4_I2S3_CTRL_CKOE (*((volatile unsigned int*)(0x42440054UL))) +#define bM4_I2S3_CTRL_DUPLEX (*((volatile unsigned int*)(0x42440058UL))) +#define bM4_I2S3_CTRL_CLKSEL (*((volatile unsigned int*)(0x4244005CUL))) +#define bM4_I2S3_SR_TXBA (*((volatile unsigned int*)(0x42440080UL))) +#define bM4_I2S3_SR_RXBA (*((volatile unsigned int*)(0x42440084UL))) +#define bM4_I2S3_SR_TXBE (*((volatile unsigned int*)(0x42440088UL))) +#define bM4_I2S3_SR_TXBF (*((volatile unsigned int*)(0x4244008CUL))) +#define bM4_I2S3_SR_RXBE (*((volatile unsigned int*)(0x42440090UL))) +#define bM4_I2S3_SR_RXBF (*((volatile unsigned int*)(0x42440094UL))) +#define bM4_I2S3_ER_TXERR (*((volatile unsigned int*)(0x42440100UL))) +#define bM4_I2S3_ER_RXERR (*((volatile unsigned int*)(0x42440104UL))) +#define bM4_I2S3_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x42440180UL))) +#define bM4_I2S3_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x42440184UL))) +#define bM4_I2S3_CFGR_DATLEN0 (*((volatile unsigned int*)(0x42440188UL))) +#define bM4_I2S3_CFGR_DATLEN1 (*((volatile unsigned int*)(0x4244018CUL))) +#define bM4_I2S3_CFGR_CHLEN (*((volatile unsigned int*)(0x42440190UL))) +#define bM4_I2S3_CFGR_PCMSYNC (*((volatile unsigned int*)(0x42440194UL))) +#define bM4_I2S3_PR_I2SDIV0 (*((volatile unsigned int*)(0x42440300UL))) +#define bM4_I2S3_PR_I2SDIV1 (*((volatile unsigned int*)(0x42440304UL))) +#define bM4_I2S3_PR_I2SDIV2 (*((volatile unsigned int*)(0x42440308UL))) +#define bM4_I2S3_PR_I2SDIV3 (*((volatile unsigned int*)(0x4244030CUL))) +#define bM4_I2S3_PR_I2SDIV4 (*((volatile unsigned int*)(0x42440310UL))) +#define bM4_I2S3_PR_I2SDIV5 (*((volatile unsigned int*)(0x42440314UL))) +#define bM4_I2S3_PR_I2SDIV6 (*((volatile unsigned int*)(0x42440318UL))) +#define bM4_I2S3_PR_I2SDIV7 (*((volatile unsigned int*)(0x4244031CUL))) +#define bM4_I2S4_CTRL_TXE (*((volatile unsigned int*)(0x42448000UL))) +#define bM4_I2S4_CTRL_TXIE (*((volatile unsigned int*)(0x42448004UL))) +#define bM4_I2S4_CTRL_RXE (*((volatile unsigned int*)(0x42448008UL))) +#define bM4_I2S4_CTRL_RXIE (*((volatile unsigned int*)(0x4244800CUL))) +#define bM4_I2S4_CTRL_EIE (*((volatile unsigned int*)(0x42448010UL))) +#define bM4_I2S4_CTRL_WMS (*((volatile unsigned int*)(0x42448014UL))) +#define bM4_I2S4_CTRL_ODD (*((volatile unsigned int*)(0x42448018UL))) +#define bM4_I2S4_CTRL_MCKOE (*((volatile unsigned int*)(0x4244801CUL))) +#define bM4_I2S4_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x42448020UL))) +#define bM4_I2S4_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x42448024UL))) +#define bM4_I2S4_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x42448028UL))) +#define bM4_I2S4_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x42448030UL))) +#define bM4_I2S4_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x42448034UL))) +#define bM4_I2S4_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x42448038UL))) +#define bM4_I2S4_CTRL_FIFOR (*((volatile unsigned int*)(0x42448040UL))) +#define bM4_I2S4_CTRL_CODECRC (*((volatile unsigned int*)(0x42448044UL))) +#define bM4_I2S4_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x42448048UL))) +#define bM4_I2S4_CTRL_SDOE (*((volatile unsigned int*)(0x4244804CUL))) +#define bM4_I2S4_CTRL_LRCKOE (*((volatile unsigned int*)(0x42448050UL))) +#define bM4_I2S4_CTRL_CKOE (*((volatile unsigned int*)(0x42448054UL))) +#define bM4_I2S4_CTRL_DUPLEX (*((volatile unsigned int*)(0x42448058UL))) +#define bM4_I2S4_CTRL_CLKSEL (*((volatile unsigned int*)(0x4244805CUL))) +#define bM4_I2S4_SR_TXBA (*((volatile unsigned int*)(0x42448080UL))) +#define bM4_I2S4_SR_RXBA (*((volatile unsigned int*)(0x42448084UL))) +#define bM4_I2S4_SR_TXBE (*((volatile unsigned int*)(0x42448088UL))) +#define bM4_I2S4_SR_TXBF (*((volatile unsigned int*)(0x4244808CUL))) +#define bM4_I2S4_SR_RXBE (*((volatile unsigned int*)(0x42448090UL))) +#define bM4_I2S4_SR_RXBF (*((volatile unsigned int*)(0x42448094UL))) +#define bM4_I2S4_ER_TXERR (*((volatile unsigned int*)(0x42448100UL))) +#define bM4_I2S4_ER_RXERR (*((volatile unsigned int*)(0x42448104UL))) +#define bM4_I2S4_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x42448180UL))) +#define bM4_I2S4_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x42448184UL))) +#define bM4_I2S4_CFGR_DATLEN0 (*((volatile unsigned int*)(0x42448188UL))) +#define bM4_I2S4_CFGR_DATLEN1 (*((volatile unsigned int*)(0x4244818CUL))) +#define bM4_I2S4_CFGR_CHLEN (*((volatile unsigned int*)(0x42448190UL))) +#define bM4_I2S4_CFGR_PCMSYNC (*((volatile unsigned int*)(0x42448194UL))) +#define bM4_I2S4_PR_I2SDIV0 (*((volatile unsigned int*)(0x42448300UL))) +#define bM4_I2S4_PR_I2SDIV1 (*((volatile unsigned int*)(0x42448304UL))) +#define bM4_I2S4_PR_I2SDIV2 (*((volatile unsigned int*)(0x42448308UL))) +#define bM4_I2S4_PR_I2SDIV3 (*((volatile unsigned int*)(0x4244830CUL))) +#define bM4_I2S4_PR_I2SDIV4 (*((volatile unsigned int*)(0x42448310UL))) +#define bM4_I2S4_PR_I2SDIV5 (*((volatile unsigned int*)(0x42448314UL))) +#define bM4_I2S4_PR_I2SDIV6 (*((volatile unsigned int*)(0x42448318UL))) +#define bM4_I2S4_PR_I2SDIV7 (*((volatile unsigned int*)(0x4244831CUL))) +#define bM4_INTC_NMICR_NMITRG (*((volatile unsigned int*)(0x42A20000UL))) +#define bM4_INTC_NMICR_NSMPCLK0 (*((volatile unsigned int*)(0x42A20010UL))) +#define bM4_INTC_NMICR_NSMPCLK1 (*((volatile unsigned int*)(0x42A20014UL))) +#define bM4_INTC_NMICR_NFEN (*((volatile unsigned int*)(0x42A2001CUL))) +#define bM4_INTC_NMIENR_NMIENR (*((volatile unsigned int*)(0x42A20080UL))) +#define bM4_INTC_NMIENR_SWDTENR (*((volatile unsigned int*)(0x42A20084UL))) +#define bM4_INTC_NMIENR_PVD1ENR (*((volatile unsigned int*)(0x42A20088UL))) +#define bM4_INTC_NMIENR_PVD2ENR (*((volatile unsigned int*)(0x42A2008CUL))) +#define bM4_INTC_NMIENR_XTALSTPENR (*((volatile unsigned int*)(0x42A20094UL))) +#define bM4_INTC_NMIENR_REPENR (*((volatile unsigned int*)(0x42A200A0UL))) +#define bM4_INTC_NMIENR_RECCENR (*((volatile unsigned int*)(0x42A200A4UL))) +#define bM4_INTC_NMIENR_BUSMENR (*((volatile unsigned int*)(0x42A200A8UL))) +#define bM4_INTC_NMIENR_WDTENR (*((volatile unsigned int*)(0x42A200ACUL))) +#define bM4_INTC_NMIFR_NMIFR (*((volatile unsigned int*)(0x42A20100UL))) +#define bM4_INTC_NMIFR_SWDTFR (*((volatile unsigned int*)(0x42A20104UL))) +#define bM4_INTC_NMIFR_PVD1FR (*((volatile unsigned int*)(0x42A20108UL))) +#define bM4_INTC_NMIFR_PVD2FR (*((volatile unsigned int*)(0x42A2010CUL))) +#define bM4_INTC_NMIFR_XTALSTPFR (*((volatile unsigned int*)(0x42A20114UL))) +#define bM4_INTC_NMIFR_REPFR (*((volatile unsigned int*)(0x42A20120UL))) +#define bM4_INTC_NMIFR_RECCFR (*((volatile unsigned int*)(0x42A20124UL))) +#define bM4_INTC_NMIFR_BUSMFR (*((volatile unsigned int*)(0x42A20128UL))) +#define bM4_INTC_NMIFR_WDTFR (*((volatile unsigned int*)(0x42A2012CUL))) +#define bM4_INTC_NMICFR_NMICFR (*((volatile unsigned int*)(0x42A20180UL))) +#define bM4_INTC_NMICFR_SWDTCFR (*((volatile unsigned int*)(0x42A20184UL))) +#define bM4_INTC_NMICFR_PVD1CFR (*((volatile unsigned int*)(0x42A20188UL))) +#define bM4_INTC_NMICFR_PVD2CFR (*((volatile unsigned int*)(0x42A2018CUL))) +#define bM4_INTC_NMICFR_XTALSTPCFR (*((volatile unsigned int*)(0x42A20194UL))) +#define bM4_INTC_NMICFR_REPCFR (*((volatile unsigned int*)(0x42A201A0UL))) +#define bM4_INTC_NMICFR_RECCCFR (*((volatile unsigned int*)(0x42A201A4UL))) +#define bM4_INTC_NMICFR_BUSMCFR (*((volatile unsigned int*)(0x42A201A8UL))) +#define bM4_INTC_NMICFR_WDTCFR (*((volatile unsigned int*)(0x42A201ACUL))) +#define bM4_INTC_EIRQCR0_EIRQTRG0 (*((volatile unsigned int*)(0x42A20200UL))) +#define bM4_INTC_EIRQCR0_EIRQTRG1 (*((volatile unsigned int*)(0x42A20204UL))) +#define bM4_INTC_EIRQCR0_EISMPCLK0 (*((volatile unsigned int*)(0x42A20210UL))) +#define bM4_INTC_EIRQCR0_EISMPCLK1 (*((volatile unsigned int*)(0x42A20214UL))) +#define bM4_INTC_EIRQCR0_EFEN (*((volatile unsigned int*)(0x42A2021CUL))) +#define bM4_INTC_EIRQCR1_EIRQTRG0 (*((volatile unsigned int*)(0x42A20280UL))) +#define bM4_INTC_EIRQCR1_EIRQTRG1 (*((volatile unsigned int*)(0x42A20284UL))) +#define bM4_INTC_EIRQCR1_EISMPCLK0 (*((volatile unsigned int*)(0x42A20290UL))) +#define bM4_INTC_EIRQCR1_EISMPCLK1 (*((volatile unsigned int*)(0x42A20294UL))) +#define bM4_INTC_EIRQCR1_EFEN (*((volatile unsigned int*)(0x42A2029CUL))) +#define bM4_INTC_EIRQCR2_EIRQTRG0 (*((volatile unsigned int*)(0x42A20300UL))) +#define bM4_INTC_EIRQCR2_EIRQTRG1 (*((volatile unsigned int*)(0x42A20304UL))) +#define bM4_INTC_EIRQCR2_EISMPCLK0 (*((volatile unsigned int*)(0x42A20310UL))) +#define bM4_INTC_EIRQCR2_EISMPCLK1 (*((volatile unsigned int*)(0x42A20314UL))) +#define bM4_INTC_EIRQCR2_EFEN (*((volatile unsigned int*)(0x42A2031CUL))) +#define bM4_INTC_EIRQCR3_EIRQTRG0 (*((volatile unsigned int*)(0x42A20380UL))) +#define bM4_INTC_EIRQCR3_EIRQTRG1 (*((volatile unsigned int*)(0x42A20384UL))) +#define bM4_INTC_EIRQCR3_EISMPCLK0 (*((volatile unsigned int*)(0x42A20390UL))) +#define bM4_INTC_EIRQCR3_EISMPCLK1 (*((volatile unsigned int*)(0x42A20394UL))) +#define bM4_INTC_EIRQCR3_EFEN (*((volatile unsigned int*)(0x42A2039CUL))) +#define bM4_INTC_EIRQCR4_EIRQTRG0 (*((volatile unsigned int*)(0x42A20400UL))) +#define bM4_INTC_EIRQCR4_EIRQTRG1 (*((volatile unsigned int*)(0x42A20404UL))) +#define bM4_INTC_EIRQCR4_EISMPCLK0 (*((volatile unsigned int*)(0x42A20410UL))) +#define bM4_INTC_EIRQCR4_EISMPCLK1 (*((volatile unsigned int*)(0x42A20414UL))) +#define bM4_INTC_EIRQCR4_EFEN (*((volatile unsigned int*)(0x42A2041CUL))) +#define bM4_INTC_EIRQCR5_EIRQTRG0 (*((volatile unsigned int*)(0x42A20480UL))) +#define bM4_INTC_EIRQCR5_EIRQTRG1 (*((volatile unsigned int*)(0x42A20484UL))) +#define bM4_INTC_EIRQCR5_EISMPCLK0 (*((volatile unsigned int*)(0x42A20490UL))) +#define bM4_INTC_EIRQCR5_EISMPCLK1 (*((volatile unsigned int*)(0x42A20494UL))) +#define bM4_INTC_EIRQCR5_EFEN (*((volatile unsigned int*)(0x42A2049CUL))) +#define bM4_INTC_EIRQCR6_EIRQTRG0 (*((volatile unsigned int*)(0x42A20500UL))) +#define bM4_INTC_EIRQCR6_EIRQTRG1 (*((volatile unsigned int*)(0x42A20504UL))) +#define bM4_INTC_EIRQCR6_EISMPCLK0 (*((volatile unsigned int*)(0x42A20510UL))) +#define bM4_INTC_EIRQCR6_EISMPCLK1 (*((volatile unsigned int*)(0x42A20514UL))) +#define bM4_INTC_EIRQCR6_EFEN (*((volatile unsigned int*)(0x42A2051CUL))) +#define bM4_INTC_EIRQCR7_EIRQTRG0 (*((volatile unsigned int*)(0x42A20580UL))) +#define bM4_INTC_EIRQCR7_EIRQTRG1 (*((volatile unsigned int*)(0x42A20584UL))) +#define bM4_INTC_EIRQCR7_EISMPCLK0 (*((volatile unsigned int*)(0x42A20590UL))) +#define bM4_INTC_EIRQCR7_EISMPCLK1 (*((volatile unsigned int*)(0x42A20594UL))) +#define bM4_INTC_EIRQCR7_EFEN (*((volatile unsigned int*)(0x42A2059CUL))) +#define bM4_INTC_EIRQCR8_EIRQTRG0 (*((volatile unsigned int*)(0x42A20600UL))) +#define bM4_INTC_EIRQCR8_EIRQTRG1 (*((volatile unsigned int*)(0x42A20604UL))) +#define bM4_INTC_EIRQCR8_EISMPCLK0 (*((volatile unsigned int*)(0x42A20610UL))) +#define bM4_INTC_EIRQCR8_EISMPCLK1 (*((volatile unsigned int*)(0x42A20614UL))) +#define bM4_INTC_EIRQCR8_EFEN (*((volatile unsigned int*)(0x42A2061CUL))) +#define bM4_INTC_EIRQCR9_EIRQTRG0 (*((volatile unsigned int*)(0x42A20680UL))) +#define bM4_INTC_EIRQCR9_EIRQTRG1 (*((volatile unsigned int*)(0x42A20684UL))) +#define bM4_INTC_EIRQCR9_EISMPCLK0 (*((volatile unsigned int*)(0x42A20690UL))) +#define bM4_INTC_EIRQCR9_EISMPCLK1 (*((volatile unsigned int*)(0x42A20694UL))) +#define bM4_INTC_EIRQCR9_EFEN (*((volatile unsigned int*)(0x42A2069CUL))) +#define bM4_INTC_EIRQCR10_EIRQTRG0 (*((volatile unsigned int*)(0x42A20700UL))) +#define bM4_INTC_EIRQCR10_EIRQTRG1 (*((volatile unsigned int*)(0x42A20704UL))) +#define bM4_INTC_EIRQCR10_EISMPCLK0 (*((volatile unsigned int*)(0x42A20710UL))) +#define bM4_INTC_EIRQCR10_EISMPCLK1 (*((volatile unsigned int*)(0x42A20714UL))) +#define bM4_INTC_EIRQCR10_EFEN (*((volatile unsigned int*)(0x42A2071CUL))) +#define bM4_INTC_EIRQCR11_EIRQTRG0 (*((volatile unsigned int*)(0x42A20780UL))) +#define bM4_INTC_EIRQCR11_EIRQTRG1 (*((volatile unsigned int*)(0x42A20784UL))) +#define bM4_INTC_EIRQCR11_EISMPCLK0 (*((volatile unsigned int*)(0x42A20790UL))) +#define bM4_INTC_EIRQCR11_EISMPCLK1 (*((volatile unsigned int*)(0x42A20794UL))) +#define bM4_INTC_EIRQCR11_EFEN (*((volatile unsigned int*)(0x42A2079CUL))) +#define bM4_INTC_EIRQCR12_EIRQTRG0 (*((volatile unsigned int*)(0x42A20800UL))) +#define bM4_INTC_EIRQCR12_EIRQTRG1 (*((volatile unsigned int*)(0x42A20804UL))) +#define bM4_INTC_EIRQCR12_EISMPCLK0 (*((volatile unsigned int*)(0x42A20810UL))) +#define bM4_INTC_EIRQCR12_EISMPCLK1 (*((volatile unsigned int*)(0x42A20814UL))) +#define bM4_INTC_EIRQCR12_EFEN (*((volatile unsigned int*)(0x42A2081CUL))) +#define bM4_INTC_EIRQCR13_EIRQTRG0 (*((volatile unsigned int*)(0x42A20880UL))) +#define bM4_INTC_EIRQCR13_EIRQTRG1 (*((volatile unsigned int*)(0x42A20884UL))) +#define bM4_INTC_EIRQCR13_EISMPCLK0 (*((volatile unsigned int*)(0x42A20890UL))) +#define bM4_INTC_EIRQCR13_EISMPCLK1 (*((volatile unsigned int*)(0x42A20894UL))) +#define bM4_INTC_EIRQCR13_EFEN (*((volatile unsigned int*)(0x42A2089CUL))) +#define bM4_INTC_EIRQCR14_EIRQTRG0 (*((volatile unsigned int*)(0x42A20900UL))) +#define bM4_INTC_EIRQCR14_EIRQTRG1 (*((volatile unsigned int*)(0x42A20904UL))) +#define bM4_INTC_EIRQCR14_EISMPCLK0 (*((volatile unsigned int*)(0x42A20910UL))) +#define bM4_INTC_EIRQCR14_EISMPCLK1 (*((volatile unsigned int*)(0x42A20914UL))) +#define bM4_INTC_EIRQCR14_EFEN (*((volatile unsigned int*)(0x42A2091CUL))) +#define bM4_INTC_EIRQCR15_EIRQTRG0 (*((volatile unsigned int*)(0x42A20980UL))) +#define bM4_INTC_EIRQCR15_EIRQTRG1 (*((volatile unsigned int*)(0x42A20984UL))) +#define bM4_INTC_EIRQCR15_EISMPCLK0 (*((volatile unsigned int*)(0x42A20990UL))) +#define bM4_INTC_EIRQCR15_EISMPCLK1 (*((volatile unsigned int*)(0x42A20994UL))) +#define bM4_INTC_EIRQCR15_EFEN (*((volatile unsigned int*)(0x42A2099CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN0 (*((volatile unsigned int*)(0x42A20A00UL))) +#define bM4_INTC_WUPEN_EIRQWUEN1 (*((volatile unsigned int*)(0x42A20A04UL))) +#define bM4_INTC_WUPEN_EIRQWUEN2 (*((volatile unsigned int*)(0x42A20A08UL))) +#define bM4_INTC_WUPEN_EIRQWUEN3 (*((volatile unsigned int*)(0x42A20A0CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN4 (*((volatile unsigned int*)(0x42A20A10UL))) +#define bM4_INTC_WUPEN_EIRQWUEN5 (*((volatile unsigned int*)(0x42A20A14UL))) +#define bM4_INTC_WUPEN_EIRQWUEN6 (*((volatile unsigned int*)(0x42A20A18UL))) +#define bM4_INTC_WUPEN_EIRQWUEN7 (*((volatile unsigned int*)(0x42A20A1CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN8 (*((volatile unsigned int*)(0x42A20A20UL))) +#define bM4_INTC_WUPEN_EIRQWUEN9 (*((volatile unsigned int*)(0x42A20A24UL))) +#define bM4_INTC_WUPEN_EIRQWUEN10 (*((volatile unsigned int*)(0x42A20A28UL))) +#define bM4_INTC_WUPEN_EIRQWUEN11 (*((volatile unsigned int*)(0x42A20A2CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN12 (*((volatile unsigned int*)(0x42A20A30UL))) +#define bM4_INTC_WUPEN_EIRQWUEN13 (*((volatile unsigned int*)(0x42A20A34UL))) +#define bM4_INTC_WUPEN_EIRQWUEN14 (*((volatile unsigned int*)(0x42A20A38UL))) +#define bM4_INTC_WUPEN_EIRQWUEN15 (*((volatile unsigned int*)(0x42A20A3CUL))) +#define bM4_INTC_WUPEN_SWDTWUEN (*((volatile unsigned int*)(0x42A20A40UL))) +#define bM4_INTC_WUPEN_PVD1WUEN (*((volatile unsigned int*)(0x42A20A44UL))) +#define bM4_INTC_WUPEN_PVD2WUEN (*((volatile unsigned int*)(0x42A20A48UL))) +#define bM4_INTC_WUPEN_CMPI0WUEN (*((volatile unsigned int*)(0x42A20A4CUL))) +#define bM4_INTC_WUPEN_WKTMWUEN (*((volatile unsigned int*)(0x42A20A50UL))) +#define bM4_INTC_WUPEN_RTCALMWUEN (*((volatile unsigned int*)(0x42A20A54UL))) +#define bM4_INTC_WUPEN_RTCPRDWUEN (*((volatile unsigned int*)(0x42A20A58UL))) +#define bM4_INTC_WUPEN_TMR0WUEN (*((volatile unsigned int*)(0x42A20A5CUL))) +#define bM4_INTC_WUPEN_RXWUEN (*((volatile unsigned int*)(0x42A20A64UL))) +#define bM4_INTC_EIFR_EIFR0 (*((volatile unsigned int*)(0x42A20A80UL))) +#define bM4_INTC_EIFR_EIFR1 (*((volatile unsigned int*)(0x42A20A84UL))) +#define bM4_INTC_EIFR_EIFR2 (*((volatile unsigned int*)(0x42A20A88UL))) +#define bM4_INTC_EIFR_EIFR3 (*((volatile unsigned int*)(0x42A20A8CUL))) +#define bM4_INTC_EIFR_EIFR4 (*((volatile unsigned int*)(0x42A20A90UL))) +#define bM4_INTC_EIFR_EIFR5 (*((volatile unsigned int*)(0x42A20A94UL))) +#define bM4_INTC_EIFR_EIFR6 (*((volatile unsigned int*)(0x42A20A98UL))) +#define bM4_INTC_EIFR_EIFR7 (*((volatile unsigned int*)(0x42A20A9CUL))) +#define bM4_INTC_EIFR_EIFR8 (*((volatile unsigned int*)(0x42A20AA0UL))) +#define bM4_INTC_EIFR_EIFR9 (*((volatile unsigned int*)(0x42A20AA4UL))) +#define bM4_INTC_EIFR_EIFR10 (*((volatile unsigned int*)(0x42A20AA8UL))) +#define bM4_INTC_EIFR_EIFR11 (*((volatile unsigned int*)(0x42A20AACUL))) +#define bM4_INTC_EIFR_EIFR12 (*((volatile unsigned int*)(0x42A20AB0UL))) +#define bM4_INTC_EIFR_EIFR13 (*((volatile unsigned int*)(0x42A20AB4UL))) +#define bM4_INTC_EIFR_EIFR14 (*((volatile unsigned int*)(0x42A20AB8UL))) +#define bM4_INTC_EIFR_EIFR15 (*((volatile unsigned int*)(0x42A20ABCUL))) +#define bM4_INTC_EICFR_EICFR0 (*((volatile unsigned int*)(0x42A20B00UL))) +#define bM4_INTC_EICFR_EICFR1 (*((volatile unsigned int*)(0x42A20B04UL))) +#define bM4_INTC_EICFR_EICFR2 (*((volatile unsigned int*)(0x42A20B08UL))) +#define bM4_INTC_EICFR_EICFR3 (*((volatile unsigned int*)(0x42A20B0CUL))) +#define bM4_INTC_EICFR_EICFR4 (*((volatile unsigned int*)(0x42A20B10UL))) +#define bM4_INTC_EICFR_EICFR5 (*((volatile unsigned int*)(0x42A20B14UL))) +#define bM4_INTC_EICFR_EICFR6 (*((volatile unsigned int*)(0x42A20B18UL))) +#define bM4_INTC_EICFR_EICFR7 (*((volatile unsigned int*)(0x42A20B1CUL))) +#define bM4_INTC_EICFR_EICFR8 (*((volatile unsigned int*)(0x42A20B20UL))) +#define bM4_INTC_EICFR_EICFR9 (*((volatile unsigned int*)(0x42A20B24UL))) +#define bM4_INTC_EICFR_EICFR10 (*((volatile unsigned int*)(0x42A20B28UL))) +#define bM4_INTC_EICFR_EICFR11 (*((volatile unsigned int*)(0x42A20B2CUL))) +#define bM4_INTC_EICFR_EICFR12 (*((volatile unsigned int*)(0x42A20B30UL))) +#define bM4_INTC_EICFR_EICFR13 (*((volatile unsigned int*)(0x42A20B34UL))) +#define bM4_INTC_EICFR_EICFR14 (*((volatile unsigned int*)(0x42A20B38UL))) +#define bM4_INTC_EICFR_EICFR15 (*((volatile unsigned int*)(0x42A20B3CUL))) +#define bM4_INTC_SEL0_INTSEL0 (*((volatile unsigned int*)(0x42A20B80UL))) +#define bM4_INTC_SEL0_INTSEL1 (*((volatile unsigned int*)(0x42A20B84UL))) +#define bM4_INTC_SEL0_INTSEL2 (*((volatile unsigned int*)(0x42A20B88UL))) +#define bM4_INTC_SEL0_INTSEL3 (*((volatile unsigned int*)(0x42A20B8CUL))) +#define bM4_INTC_SEL0_INTSEL4 (*((volatile unsigned int*)(0x42A20B90UL))) +#define bM4_INTC_SEL0_INTSEL5 (*((volatile unsigned int*)(0x42A20B94UL))) +#define bM4_INTC_SEL0_INTSEL6 (*((volatile unsigned int*)(0x42A20B98UL))) +#define bM4_INTC_SEL0_INTSEL7 (*((volatile unsigned int*)(0x42A20B9CUL))) +#define bM4_INTC_SEL0_INTSEL8 (*((volatile unsigned int*)(0x42A20BA0UL))) +#define bM4_INTC_SEL1_INTSEL0 (*((volatile unsigned int*)(0x42A20C00UL))) +#define bM4_INTC_SEL1_INTSEL1 (*((volatile unsigned int*)(0x42A20C04UL))) +#define bM4_INTC_SEL1_INTSEL2 (*((volatile unsigned int*)(0x42A20C08UL))) +#define bM4_INTC_SEL1_INTSEL3 (*((volatile unsigned int*)(0x42A20C0CUL))) +#define bM4_INTC_SEL1_INTSEL4 (*((volatile unsigned int*)(0x42A20C10UL))) +#define bM4_INTC_SEL1_INTSEL5 (*((volatile unsigned int*)(0x42A20C14UL))) +#define bM4_INTC_SEL1_INTSEL6 (*((volatile unsigned int*)(0x42A20C18UL))) +#define bM4_INTC_SEL1_INTSEL7 (*((volatile unsigned int*)(0x42A20C1CUL))) +#define bM4_INTC_SEL1_INTSEL8 (*((volatile unsigned int*)(0x42A20C20UL))) +#define bM4_INTC_SEL2_INTSEL0 (*((volatile unsigned int*)(0x42A20C80UL))) +#define bM4_INTC_SEL2_INTSEL1 (*((volatile unsigned int*)(0x42A20C84UL))) +#define bM4_INTC_SEL2_INTSEL2 (*((volatile unsigned int*)(0x42A20C88UL))) +#define bM4_INTC_SEL2_INTSEL3 (*((volatile unsigned int*)(0x42A20C8CUL))) +#define bM4_INTC_SEL2_INTSEL4 (*((volatile unsigned int*)(0x42A20C90UL))) +#define bM4_INTC_SEL2_INTSEL5 (*((volatile unsigned int*)(0x42A20C94UL))) +#define bM4_INTC_SEL2_INTSEL6 (*((volatile unsigned int*)(0x42A20C98UL))) +#define bM4_INTC_SEL2_INTSEL7 (*((volatile unsigned int*)(0x42A20C9CUL))) +#define bM4_INTC_SEL2_INTSEL8 (*((volatile unsigned int*)(0x42A20CA0UL))) +#define bM4_INTC_SEL3_INTSEL0 (*((volatile unsigned int*)(0x42A20D00UL))) +#define bM4_INTC_SEL3_INTSEL1 (*((volatile unsigned int*)(0x42A20D04UL))) +#define bM4_INTC_SEL3_INTSEL2 (*((volatile unsigned int*)(0x42A20D08UL))) +#define bM4_INTC_SEL3_INTSEL3 (*((volatile unsigned int*)(0x42A20D0CUL))) +#define bM4_INTC_SEL3_INTSEL4 (*((volatile unsigned int*)(0x42A20D10UL))) +#define bM4_INTC_SEL3_INTSEL5 (*((volatile unsigned int*)(0x42A20D14UL))) +#define bM4_INTC_SEL3_INTSEL6 (*((volatile unsigned int*)(0x42A20D18UL))) +#define bM4_INTC_SEL3_INTSEL7 (*((volatile unsigned int*)(0x42A20D1CUL))) +#define bM4_INTC_SEL3_INTSEL8 (*((volatile unsigned int*)(0x42A20D20UL))) +#define bM4_INTC_SEL4_INTSEL0 (*((volatile unsigned int*)(0x42A20D80UL))) +#define bM4_INTC_SEL4_INTSEL1 (*((volatile unsigned int*)(0x42A20D84UL))) +#define bM4_INTC_SEL4_INTSEL2 (*((volatile unsigned int*)(0x42A20D88UL))) +#define bM4_INTC_SEL4_INTSEL3 (*((volatile unsigned int*)(0x42A20D8CUL))) +#define bM4_INTC_SEL4_INTSEL4 (*((volatile unsigned int*)(0x42A20D90UL))) +#define bM4_INTC_SEL4_INTSEL5 (*((volatile unsigned int*)(0x42A20D94UL))) +#define bM4_INTC_SEL4_INTSEL6 (*((volatile unsigned int*)(0x42A20D98UL))) +#define bM4_INTC_SEL4_INTSEL7 (*((volatile unsigned int*)(0x42A20D9CUL))) +#define bM4_INTC_SEL4_INTSEL8 (*((volatile unsigned int*)(0x42A20DA0UL))) +#define bM4_INTC_SEL5_INTSEL0 (*((volatile unsigned int*)(0x42A20E00UL))) +#define bM4_INTC_SEL5_INTSEL1 (*((volatile unsigned int*)(0x42A20E04UL))) +#define bM4_INTC_SEL5_INTSEL2 (*((volatile unsigned int*)(0x42A20E08UL))) +#define bM4_INTC_SEL5_INTSEL3 (*((volatile unsigned int*)(0x42A20E0CUL))) +#define bM4_INTC_SEL5_INTSEL4 (*((volatile unsigned int*)(0x42A20E10UL))) +#define bM4_INTC_SEL5_INTSEL5 (*((volatile unsigned int*)(0x42A20E14UL))) +#define bM4_INTC_SEL5_INTSEL6 (*((volatile unsigned int*)(0x42A20E18UL))) +#define bM4_INTC_SEL5_INTSEL7 (*((volatile unsigned int*)(0x42A20E1CUL))) +#define bM4_INTC_SEL5_INTSEL8 (*((volatile unsigned int*)(0x42A20E20UL))) +#define bM4_INTC_SEL6_INTSEL0 (*((volatile unsigned int*)(0x42A20E80UL))) +#define bM4_INTC_SEL6_INTSEL1 (*((volatile unsigned int*)(0x42A20E84UL))) +#define bM4_INTC_SEL6_INTSEL2 (*((volatile unsigned int*)(0x42A20E88UL))) +#define bM4_INTC_SEL6_INTSEL3 (*((volatile unsigned int*)(0x42A20E8CUL))) +#define bM4_INTC_SEL6_INTSEL4 (*((volatile unsigned int*)(0x42A20E90UL))) +#define bM4_INTC_SEL6_INTSEL5 (*((volatile unsigned int*)(0x42A20E94UL))) +#define bM4_INTC_SEL6_INTSEL6 (*((volatile unsigned int*)(0x42A20E98UL))) +#define bM4_INTC_SEL6_INTSEL7 (*((volatile unsigned int*)(0x42A20E9CUL))) +#define bM4_INTC_SEL6_INTSEL8 (*((volatile unsigned int*)(0x42A20EA0UL))) +#define bM4_INTC_SEL7_INTSEL0 (*((volatile unsigned int*)(0x42A20F00UL))) +#define bM4_INTC_SEL7_INTSEL1 (*((volatile unsigned int*)(0x42A20F04UL))) +#define bM4_INTC_SEL7_INTSEL2 (*((volatile unsigned int*)(0x42A20F08UL))) +#define bM4_INTC_SEL7_INTSEL3 (*((volatile unsigned int*)(0x42A20F0CUL))) +#define bM4_INTC_SEL7_INTSEL4 (*((volatile unsigned int*)(0x42A20F10UL))) +#define bM4_INTC_SEL7_INTSEL5 (*((volatile unsigned int*)(0x42A20F14UL))) +#define bM4_INTC_SEL7_INTSEL6 (*((volatile unsigned int*)(0x42A20F18UL))) +#define bM4_INTC_SEL7_INTSEL7 (*((volatile unsigned int*)(0x42A20F1CUL))) +#define bM4_INTC_SEL7_INTSEL8 (*((volatile unsigned int*)(0x42A20F20UL))) +#define bM4_INTC_SEL8_INTSEL0 (*((volatile unsigned int*)(0x42A20F80UL))) +#define bM4_INTC_SEL8_INTSEL1 (*((volatile unsigned int*)(0x42A20F84UL))) +#define bM4_INTC_SEL8_INTSEL2 (*((volatile unsigned int*)(0x42A20F88UL))) +#define bM4_INTC_SEL8_INTSEL3 (*((volatile unsigned int*)(0x42A20F8CUL))) +#define bM4_INTC_SEL8_INTSEL4 (*((volatile unsigned int*)(0x42A20F90UL))) +#define bM4_INTC_SEL8_INTSEL5 (*((volatile unsigned int*)(0x42A20F94UL))) +#define bM4_INTC_SEL8_INTSEL6 (*((volatile unsigned int*)(0x42A20F98UL))) +#define bM4_INTC_SEL8_INTSEL7 (*((volatile unsigned int*)(0x42A20F9CUL))) +#define bM4_INTC_SEL8_INTSEL8 (*((volatile unsigned int*)(0x42A20FA0UL))) +#define bM4_INTC_SEL9_INTSEL0 (*((volatile unsigned int*)(0x42A21000UL))) +#define bM4_INTC_SEL9_INTSEL1 (*((volatile unsigned int*)(0x42A21004UL))) +#define bM4_INTC_SEL9_INTSEL2 (*((volatile unsigned int*)(0x42A21008UL))) +#define bM4_INTC_SEL9_INTSEL3 (*((volatile unsigned int*)(0x42A2100CUL))) +#define bM4_INTC_SEL9_INTSEL4 (*((volatile unsigned int*)(0x42A21010UL))) +#define bM4_INTC_SEL9_INTSEL5 (*((volatile unsigned int*)(0x42A21014UL))) +#define bM4_INTC_SEL9_INTSEL6 (*((volatile unsigned int*)(0x42A21018UL))) +#define bM4_INTC_SEL9_INTSEL7 (*((volatile unsigned int*)(0x42A2101CUL))) +#define bM4_INTC_SEL9_INTSEL8 (*((volatile unsigned int*)(0x42A21020UL))) +#define bM4_INTC_SEL10_INTSEL0 (*((volatile unsigned int*)(0x42A21080UL))) +#define bM4_INTC_SEL10_INTSEL1 (*((volatile unsigned int*)(0x42A21084UL))) +#define bM4_INTC_SEL10_INTSEL2 (*((volatile unsigned int*)(0x42A21088UL))) +#define bM4_INTC_SEL10_INTSEL3 (*((volatile unsigned int*)(0x42A2108CUL))) +#define bM4_INTC_SEL10_INTSEL4 (*((volatile unsigned int*)(0x42A21090UL))) +#define bM4_INTC_SEL10_INTSEL5 (*((volatile unsigned int*)(0x42A21094UL))) +#define bM4_INTC_SEL10_INTSEL6 (*((volatile unsigned int*)(0x42A21098UL))) +#define bM4_INTC_SEL10_INTSEL7 (*((volatile unsigned int*)(0x42A2109CUL))) +#define bM4_INTC_SEL10_INTSEL8 (*((volatile unsigned int*)(0x42A210A0UL))) +#define bM4_INTC_SEL11_INTSEL0 (*((volatile unsigned int*)(0x42A21100UL))) +#define bM4_INTC_SEL11_INTSEL1 (*((volatile unsigned int*)(0x42A21104UL))) +#define bM4_INTC_SEL11_INTSEL2 (*((volatile unsigned int*)(0x42A21108UL))) +#define bM4_INTC_SEL11_INTSEL3 (*((volatile unsigned int*)(0x42A2110CUL))) +#define bM4_INTC_SEL11_INTSEL4 (*((volatile unsigned int*)(0x42A21110UL))) +#define bM4_INTC_SEL11_INTSEL5 (*((volatile unsigned int*)(0x42A21114UL))) +#define bM4_INTC_SEL11_INTSEL6 (*((volatile unsigned int*)(0x42A21118UL))) +#define bM4_INTC_SEL11_INTSEL7 (*((volatile unsigned int*)(0x42A2111CUL))) +#define bM4_INTC_SEL11_INTSEL8 (*((volatile unsigned int*)(0x42A21120UL))) +#define bM4_INTC_SEL12_INTSEL0 (*((volatile unsigned int*)(0x42A21180UL))) +#define bM4_INTC_SEL12_INTSEL1 (*((volatile unsigned int*)(0x42A21184UL))) +#define bM4_INTC_SEL12_INTSEL2 (*((volatile unsigned int*)(0x42A21188UL))) +#define bM4_INTC_SEL12_INTSEL3 (*((volatile unsigned int*)(0x42A2118CUL))) +#define bM4_INTC_SEL12_INTSEL4 (*((volatile unsigned int*)(0x42A21190UL))) +#define bM4_INTC_SEL12_INTSEL5 (*((volatile unsigned int*)(0x42A21194UL))) +#define bM4_INTC_SEL12_INTSEL6 (*((volatile unsigned int*)(0x42A21198UL))) +#define bM4_INTC_SEL12_INTSEL7 (*((volatile unsigned int*)(0x42A2119CUL))) +#define bM4_INTC_SEL12_INTSEL8 (*((volatile unsigned int*)(0x42A211A0UL))) +#define bM4_INTC_SEL13_INTSEL0 (*((volatile unsigned int*)(0x42A21200UL))) +#define bM4_INTC_SEL13_INTSEL1 (*((volatile unsigned int*)(0x42A21204UL))) +#define bM4_INTC_SEL13_INTSEL2 (*((volatile unsigned int*)(0x42A21208UL))) +#define bM4_INTC_SEL13_INTSEL3 (*((volatile unsigned int*)(0x42A2120CUL))) +#define bM4_INTC_SEL13_INTSEL4 (*((volatile unsigned int*)(0x42A21210UL))) +#define bM4_INTC_SEL13_INTSEL5 (*((volatile unsigned int*)(0x42A21214UL))) +#define bM4_INTC_SEL13_INTSEL6 (*((volatile unsigned int*)(0x42A21218UL))) +#define bM4_INTC_SEL13_INTSEL7 (*((volatile unsigned int*)(0x42A2121CUL))) +#define bM4_INTC_SEL13_INTSEL8 (*((volatile unsigned int*)(0x42A21220UL))) +#define bM4_INTC_SEL14_INTSEL0 (*((volatile unsigned int*)(0x42A21280UL))) +#define bM4_INTC_SEL14_INTSEL1 (*((volatile unsigned int*)(0x42A21284UL))) +#define bM4_INTC_SEL14_INTSEL2 (*((volatile unsigned int*)(0x42A21288UL))) +#define bM4_INTC_SEL14_INTSEL3 (*((volatile unsigned int*)(0x42A2128CUL))) +#define bM4_INTC_SEL14_INTSEL4 (*((volatile unsigned int*)(0x42A21290UL))) +#define bM4_INTC_SEL14_INTSEL5 (*((volatile unsigned int*)(0x42A21294UL))) +#define bM4_INTC_SEL14_INTSEL6 (*((volatile unsigned int*)(0x42A21298UL))) +#define bM4_INTC_SEL14_INTSEL7 (*((volatile unsigned int*)(0x42A2129CUL))) +#define bM4_INTC_SEL14_INTSEL8 (*((volatile unsigned int*)(0x42A212A0UL))) +#define bM4_INTC_SEL15_INTSEL0 (*((volatile unsigned int*)(0x42A21300UL))) +#define bM4_INTC_SEL15_INTSEL1 (*((volatile unsigned int*)(0x42A21304UL))) +#define bM4_INTC_SEL15_INTSEL2 (*((volatile unsigned int*)(0x42A21308UL))) +#define bM4_INTC_SEL15_INTSEL3 (*((volatile unsigned int*)(0x42A2130CUL))) +#define bM4_INTC_SEL15_INTSEL4 (*((volatile unsigned int*)(0x42A21310UL))) +#define bM4_INTC_SEL15_INTSEL5 (*((volatile unsigned int*)(0x42A21314UL))) +#define bM4_INTC_SEL15_INTSEL6 (*((volatile unsigned int*)(0x42A21318UL))) +#define bM4_INTC_SEL15_INTSEL7 (*((volatile unsigned int*)(0x42A2131CUL))) +#define bM4_INTC_SEL15_INTSEL8 (*((volatile unsigned int*)(0x42A21320UL))) +#define bM4_INTC_SEL16_INTSEL0 (*((volatile unsigned int*)(0x42A21380UL))) +#define bM4_INTC_SEL16_INTSEL1 (*((volatile unsigned int*)(0x42A21384UL))) +#define bM4_INTC_SEL16_INTSEL2 (*((volatile unsigned int*)(0x42A21388UL))) +#define bM4_INTC_SEL16_INTSEL3 (*((volatile unsigned int*)(0x42A2138CUL))) +#define bM4_INTC_SEL16_INTSEL4 (*((volatile unsigned int*)(0x42A21390UL))) +#define bM4_INTC_SEL16_INTSEL5 (*((volatile unsigned int*)(0x42A21394UL))) +#define bM4_INTC_SEL16_INTSEL6 (*((volatile unsigned int*)(0x42A21398UL))) +#define bM4_INTC_SEL16_INTSEL7 (*((volatile unsigned int*)(0x42A2139CUL))) +#define bM4_INTC_SEL16_INTSEL8 (*((volatile unsigned int*)(0x42A213A0UL))) +#define bM4_INTC_SEL17_INTSEL0 (*((volatile unsigned int*)(0x42A21400UL))) +#define bM4_INTC_SEL17_INTSEL1 (*((volatile unsigned int*)(0x42A21404UL))) +#define bM4_INTC_SEL17_INTSEL2 (*((volatile unsigned int*)(0x42A21408UL))) +#define bM4_INTC_SEL17_INTSEL3 (*((volatile unsigned int*)(0x42A2140CUL))) +#define bM4_INTC_SEL17_INTSEL4 (*((volatile unsigned int*)(0x42A21410UL))) +#define bM4_INTC_SEL17_INTSEL5 (*((volatile unsigned int*)(0x42A21414UL))) +#define bM4_INTC_SEL17_INTSEL6 (*((volatile unsigned int*)(0x42A21418UL))) +#define bM4_INTC_SEL17_INTSEL7 (*((volatile unsigned int*)(0x42A2141CUL))) +#define bM4_INTC_SEL17_INTSEL8 (*((volatile unsigned int*)(0x42A21420UL))) +#define bM4_INTC_SEL18_INTSEL0 (*((volatile unsigned int*)(0x42A21480UL))) +#define bM4_INTC_SEL18_INTSEL1 (*((volatile unsigned int*)(0x42A21484UL))) +#define bM4_INTC_SEL18_INTSEL2 (*((volatile unsigned int*)(0x42A21488UL))) +#define bM4_INTC_SEL18_INTSEL3 (*((volatile unsigned int*)(0x42A2148CUL))) +#define bM4_INTC_SEL18_INTSEL4 (*((volatile unsigned int*)(0x42A21490UL))) +#define bM4_INTC_SEL18_INTSEL5 (*((volatile unsigned int*)(0x42A21494UL))) +#define bM4_INTC_SEL18_INTSEL6 (*((volatile unsigned int*)(0x42A21498UL))) +#define bM4_INTC_SEL18_INTSEL7 (*((volatile unsigned int*)(0x42A2149CUL))) +#define bM4_INTC_SEL18_INTSEL8 (*((volatile unsigned int*)(0x42A214A0UL))) +#define bM4_INTC_SEL19_INTSEL0 (*((volatile unsigned int*)(0x42A21500UL))) +#define bM4_INTC_SEL19_INTSEL1 (*((volatile unsigned int*)(0x42A21504UL))) +#define bM4_INTC_SEL19_INTSEL2 (*((volatile unsigned int*)(0x42A21508UL))) +#define bM4_INTC_SEL19_INTSEL3 (*((volatile unsigned int*)(0x42A2150CUL))) +#define bM4_INTC_SEL19_INTSEL4 (*((volatile unsigned int*)(0x42A21510UL))) +#define bM4_INTC_SEL19_INTSEL5 (*((volatile unsigned int*)(0x42A21514UL))) +#define bM4_INTC_SEL19_INTSEL6 (*((volatile unsigned int*)(0x42A21518UL))) +#define bM4_INTC_SEL19_INTSEL7 (*((volatile unsigned int*)(0x42A2151CUL))) +#define bM4_INTC_SEL19_INTSEL8 (*((volatile unsigned int*)(0x42A21520UL))) +#define bM4_INTC_SEL20_INTSEL0 (*((volatile unsigned int*)(0x42A21580UL))) +#define bM4_INTC_SEL20_INTSEL1 (*((volatile unsigned int*)(0x42A21584UL))) +#define bM4_INTC_SEL20_INTSEL2 (*((volatile unsigned int*)(0x42A21588UL))) +#define bM4_INTC_SEL20_INTSEL3 (*((volatile unsigned int*)(0x42A2158CUL))) +#define bM4_INTC_SEL20_INTSEL4 (*((volatile unsigned int*)(0x42A21590UL))) +#define bM4_INTC_SEL20_INTSEL5 (*((volatile unsigned int*)(0x42A21594UL))) +#define bM4_INTC_SEL20_INTSEL6 (*((volatile unsigned int*)(0x42A21598UL))) +#define bM4_INTC_SEL20_INTSEL7 (*((volatile unsigned int*)(0x42A2159CUL))) +#define bM4_INTC_SEL20_INTSEL8 (*((volatile unsigned int*)(0x42A215A0UL))) +#define bM4_INTC_SEL21_INTSEL0 (*((volatile unsigned int*)(0x42A21600UL))) +#define bM4_INTC_SEL21_INTSEL1 (*((volatile unsigned int*)(0x42A21604UL))) +#define bM4_INTC_SEL21_INTSEL2 (*((volatile unsigned int*)(0x42A21608UL))) +#define bM4_INTC_SEL21_INTSEL3 (*((volatile unsigned int*)(0x42A2160CUL))) +#define bM4_INTC_SEL21_INTSEL4 (*((volatile unsigned int*)(0x42A21610UL))) +#define bM4_INTC_SEL21_INTSEL5 (*((volatile unsigned int*)(0x42A21614UL))) +#define bM4_INTC_SEL21_INTSEL6 (*((volatile unsigned int*)(0x42A21618UL))) +#define bM4_INTC_SEL21_INTSEL7 (*((volatile unsigned int*)(0x42A2161CUL))) +#define bM4_INTC_SEL21_INTSEL8 (*((volatile unsigned int*)(0x42A21620UL))) +#define bM4_INTC_SEL22_INTSEL0 (*((volatile unsigned int*)(0x42A21680UL))) +#define bM4_INTC_SEL22_INTSEL1 (*((volatile unsigned int*)(0x42A21684UL))) +#define bM4_INTC_SEL22_INTSEL2 (*((volatile unsigned int*)(0x42A21688UL))) +#define bM4_INTC_SEL22_INTSEL3 (*((volatile unsigned int*)(0x42A2168CUL))) +#define bM4_INTC_SEL22_INTSEL4 (*((volatile unsigned int*)(0x42A21690UL))) +#define bM4_INTC_SEL22_INTSEL5 (*((volatile unsigned int*)(0x42A21694UL))) +#define bM4_INTC_SEL22_INTSEL6 (*((volatile unsigned int*)(0x42A21698UL))) +#define bM4_INTC_SEL22_INTSEL7 (*((volatile unsigned int*)(0x42A2169CUL))) +#define bM4_INTC_SEL22_INTSEL8 (*((volatile unsigned int*)(0x42A216A0UL))) +#define bM4_INTC_SEL23_INTSEL0 (*((volatile unsigned int*)(0x42A21700UL))) +#define bM4_INTC_SEL23_INTSEL1 (*((volatile unsigned int*)(0x42A21704UL))) +#define bM4_INTC_SEL23_INTSEL2 (*((volatile unsigned int*)(0x42A21708UL))) +#define bM4_INTC_SEL23_INTSEL3 (*((volatile unsigned int*)(0x42A2170CUL))) +#define bM4_INTC_SEL23_INTSEL4 (*((volatile unsigned int*)(0x42A21710UL))) +#define bM4_INTC_SEL23_INTSEL5 (*((volatile unsigned int*)(0x42A21714UL))) +#define bM4_INTC_SEL23_INTSEL6 (*((volatile unsigned int*)(0x42A21718UL))) +#define bM4_INTC_SEL23_INTSEL7 (*((volatile unsigned int*)(0x42A2171CUL))) +#define bM4_INTC_SEL23_INTSEL8 (*((volatile unsigned int*)(0x42A21720UL))) +#define bM4_INTC_SEL24_INTSEL0 (*((volatile unsigned int*)(0x42A21780UL))) +#define bM4_INTC_SEL24_INTSEL1 (*((volatile unsigned int*)(0x42A21784UL))) +#define bM4_INTC_SEL24_INTSEL2 (*((volatile unsigned int*)(0x42A21788UL))) +#define bM4_INTC_SEL24_INTSEL3 (*((volatile unsigned int*)(0x42A2178CUL))) +#define bM4_INTC_SEL24_INTSEL4 (*((volatile unsigned int*)(0x42A21790UL))) +#define bM4_INTC_SEL24_INTSEL5 (*((volatile unsigned int*)(0x42A21794UL))) +#define bM4_INTC_SEL24_INTSEL6 (*((volatile unsigned int*)(0x42A21798UL))) +#define bM4_INTC_SEL24_INTSEL7 (*((volatile unsigned int*)(0x42A2179CUL))) +#define bM4_INTC_SEL24_INTSEL8 (*((volatile unsigned int*)(0x42A217A0UL))) +#define bM4_INTC_SEL25_INTSEL0 (*((volatile unsigned int*)(0x42A21800UL))) +#define bM4_INTC_SEL25_INTSEL1 (*((volatile unsigned int*)(0x42A21804UL))) +#define bM4_INTC_SEL25_INTSEL2 (*((volatile unsigned int*)(0x42A21808UL))) +#define bM4_INTC_SEL25_INTSEL3 (*((volatile unsigned int*)(0x42A2180CUL))) +#define bM4_INTC_SEL25_INTSEL4 (*((volatile unsigned int*)(0x42A21810UL))) +#define bM4_INTC_SEL25_INTSEL5 (*((volatile unsigned int*)(0x42A21814UL))) +#define bM4_INTC_SEL25_INTSEL6 (*((volatile unsigned int*)(0x42A21818UL))) +#define bM4_INTC_SEL25_INTSEL7 (*((volatile unsigned int*)(0x42A2181CUL))) +#define bM4_INTC_SEL25_INTSEL8 (*((volatile unsigned int*)(0x42A21820UL))) +#define bM4_INTC_SEL26_INTSEL0 (*((volatile unsigned int*)(0x42A21880UL))) +#define bM4_INTC_SEL26_INTSEL1 (*((volatile unsigned int*)(0x42A21884UL))) +#define bM4_INTC_SEL26_INTSEL2 (*((volatile unsigned int*)(0x42A21888UL))) +#define bM4_INTC_SEL26_INTSEL3 (*((volatile unsigned int*)(0x42A2188CUL))) +#define bM4_INTC_SEL26_INTSEL4 (*((volatile unsigned int*)(0x42A21890UL))) +#define bM4_INTC_SEL26_INTSEL5 (*((volatile unsigned int*)(0x42A21894UL))) +#define bM4_INTC_SEL26_INTSEL6 (*((volatile unsigned int*)(0x42A21898UL))) +#define bM4_INTC_SEL26_INTSEL7 (*((volatile unsigned int*)(0x42A2189CUL))) +#define bM4_INTC_SEL26_INTSEL8 (*((volatile unsigned int*)(0x42A218A0UL))) +#define bM4_INTC_SEL27_INTSEL0 (*((volatile unsigned int*)(0x42A21900UL))) +#define bM4_INTC_SEL27_INTSEL1 (*((volatile unsigned int*)(0x42A21904UL))) +#define bM4_INTC_SEL27_INTSEL2 (*((volatile unsigned int*)(0x42A21908UL))) +#define bM4_INTC_SEL27_INTSEL3 (*((volatile unsigned int*)(0x42A2190CUL))) +#define bM4_INTC_SEL27_INTSEL4 (*((volatile unsigned int*)(0x42A21910UL))) +#define bM4_INTC_SEL27_INTSEL5 (*((volatile unsigned int*)(0x42A21914UL))) +#define bM4_INTC_SEL27_INTSEL6 (*((volatile unsigned int*)(0x42A21918UL))) +#define bM4_INTC_SEL27_INTSEL7 (*((volatile unsigned int*)(0x42A2191CUL))) +#define bM4_INTC_SEL27_INTSEL8 (*((volatile unsigned int*)(0x42A21920UL))) +#define bM4_INTC_SEL28_INTSEL0 (*((volatile unsigned int*)(0x42A21980UL))) +#define bM4_INTC_SEL28_INTSEL1 (*((volatile unsigned int*)(0x42A21984UL))) +#define bM4_INTC_SEL28_INTSEL2 (*((volatile unsigned int*)(0x42A21988UL))) +#define bM4_INTC_SEL28_INTSEL3 (*((volatile unsigned int*)(0x42A2198CUL))) +#define bM4_INTC_SEL28_INTSEL4 (*((volatile unsigned int*)(0x42A21990UL))) +#define bM4_INTC_SEL28_INTSEL5 (*((volatile unsigned int*)(0x42A21994UL))) +#define bM4_INTC_SEL28_INTSEL6 (*((volatile unsigned int*)(0x42A21998UL))) +#define bM4_INTC_SEL28_INTSEL7 (*((volatile unsigned int*)(0x42A2199CUL))) +#define bM4_INTC_SEL28_INTSEL8 (*((volatile unsigned int*)(0x42A219A0UL))) +#define bM4_INTC_SEL29_INTSEL0 (*((volatile unsigned int*)(0x42A21A00UL))) +#define bM4_INTC_SEL29_INTSEL1 (*((volatile unsigned int*)(0x42A21A04UL))) +#define bM4_INTC_SEL29_INTSEL2 (*((volatile unsigned int*)(0x42A21A08UL))) +#define bM4_INTC_SEL29_INTSEL3 (*((volatile unsigned int*)(0x42A21A0CUL))) +#define bM4_INTC_SEL29_INTSEL4 (*((volatile unsigned int*)(0x42A21A10UL))) +#define bM4_INTC_SEL29_INTSEL5 (*((volatile unsigned int*)(0x42A21A14UL))) +#define bM4_INTC_SEL29_INTSEL6 (*((volatile unsigned int*)(0x42A21A18UL))) +#define bM4_INTC_SEL29_INTSEL7 (*((volatile unsigned int*)(0x42A21A1CUL))) +#define bM4_INTC_SEL29_INTSEL8 (*((volatile unsigned int*)(0x42A21A20UL))) +#define bM4_INTC_SEL30_INTSEL0 (*((volatile unsigned int*)(0x42A21A80UL))) +#define bM4_INTC_SEL30_INTSEL1 (*((volatile unsigned int*)(0x42A21A84UL))) +#define bM4_INTC_SEL30_INTSEL2 (*((volatile unsigned int*)(0x42A21A88UL))) +#define bM4_INTC_SEL30_INTSEL3 (*((volatile unsigned int*)(0x42A21A8CUL))) +#define bM4_INTC_SEL30_INTSEL4 (*((volatile unsigned int*)(0x42A21A90UL))) +#define bM4_INTC_SEL30_INTSEL5 (*((volatile unsigned int*)(0x42A21A94UL))) +#define bM4_INTC_SEL30_INTSEL6 (*((volatile unsigned int*)(0x42A21A98UL))) +#define bM4_INTC_SEL30_INTSEL7 (*((volatile unsigned int*)(0x42A21A9CUL))) +#define bM4_INTC_SEL30_INTSEL8 (*((volatile unsigned int*)(0x42A21AA0UL))) +#define bM4_INTC_SEL31_INTSEL0 (*((volatile unsigned int*)(0x42A21B00UL))) +#define bM4_INTC_SEL31_INTSEL1 (*((volatile unsigned int*)(0x42A21B04UL))) +#define bM4_INTC_SEL31_INTSEL2 (*((volatile unsigned int*)(0x42A21B08UL))) +#define bM4_INTC_SEL31_INTSEL3 (*((volatile unsigned int*)(0x42A21B0CUL))) +#define bM4_INTC_SEL31_INTSEL4 (*((volatile unsigned int*)(0x42A21B10UL))) +#define bM4_INTC_SEL31_INTSEL5 (*((volatile unsigned int*)(0x42A21B14UL))) +#define bM4_INTC_SEL31_INTSEL6 (*((volatile unsigned int*)(0x42A21B18UL))) +#define bM4_INTC_SEL31_INTSEL7 (*((volatile unsigned int*)(0x42A21B1CUL))) +#define bM4_INTC_SEL31_INTSEL8 (*((volatile unsigned int*)(0x42A21B20UL))) +#define bM4_INTC_SEL32_INTSEL0 (*((volatile unsigned int*)(0x42A21B80UL))) +#define bM4_INTC_SEL32_INTSEL1 (*((volatile unsigned int*)(0x42A21B84UL))) +#define bM4_INTC_SEL32_INTSEL2 (*((volatile unsigned int*)(0x42A21B88UL))) +#define bM4_INTC_SEL32_INTSEL3 (*((volatile unsigned int*)(0x42A21B8CUL))) +#define bM4_INTC_SEL32_INTSEL4 (*((volatile unsigned int*)(0x42A21B90UL))) +#define bM4_INTC_SEL32_INTSEL5 (*((volatile unsigned int*)(0x42A21B94UL))) +#define bM4_INTC_SEL32_INTSEL6 (*((volatile unsigned int*)(0x42A21B98UL))) +#define bM4_INTC_SEL32_INTSEL7 (*((volatile unsigned int*)(0x42A21B9CUL))) +#define bM4_INTC_SEL32_INTSEL8 (*((volatile unsigned int*)(0x42A21BA0UL))) +#define bM4_INTC_SEL33_INTSEL0 (*((volatile unsigned int*)(0x42A21C00UL))) +#define bM4_INTC_SEL33_INTSEL1 (*((volatile unsigned int*)(0x42A21C04UL))) +#define bM4_INTC_SEL33_INTSEL2 (*((volatile unsigned int*)(0x42A21C08UL))) +#define bM4_INTC_SEL33_INTSEL3 (*((volatile unsigned int*)(0x42A21C0CUL))) +#define bM4_INTC_SEL33_INTSEL4 (*((volatile unsigned int*)(0x42A21C10UL))) +#define bM4_INTC_SEL33_INTSEL5 (*((volatile unsigned int*)(0x42A21C14UL))) +#define bM4_INTC_SEL33_INTSEL6 (*((volatile unsigned int*)(0x42A21C18UL))) +#define bM4_INTC_SEL33_INTSEL7 (*((volatile unsigned int*)(0x42A21C1CUL))) +#define bM4_INTC_SEL33_INTSEL8 (*((volatile unsigned int*)(0x42A21C20UL))) +#define bM4_INTC_SEL34_INTSEL0 (*((volatile unsigned int*)(0x42A21C80UL))) +#define bM4_INTC_SEL34_INTSEL1 (*((volatile unsigned int*)(0x42A21C84UL))) +#define bM4_INTC_SEL34_INTSEL2 (*((volatile unsigned int*)(0x42A21C88UL))) +#define bM4_INTC_SEL34_INTSEL3 (*((volatile unsigned int*)(0x42A21C8CUL))) +#define bM4_INTC_SEL34_INTSEL4 (*((volatile unsigned int*)(0x42A21C90UL))) +#define bM4_INTC_SEL34_INTSEL5 (*((volatile unsigned int*)(0x42A21C94UL))) +#define bM4_INTC_SEL34_INTSEL6 (*((volatile unsigned int*)(0x42A21C98UL))) +#define bM4_INTC_SEL34_INTSEL7 (*((volatile unsigned int*)(0x42A21C9CUL))) +#define bM4_INTC_SEL34_INTSEL8 (*((volatile unsigned int*)(0x42A21CA0UL))) +#define bM4_INTC_SEL35_INTSEL0 (*((volatile unsigned int*)(0x42A21D00UL))) +#define bM4_INTC_SEL35_INTSEL1 (*((volatile unsigned int*)(0x42A21D04UL))) +#define bM4_INTC_SEL35_INTSEL2 (*((volatile unsigned int*)(0x42A21D08UL))) +#define bM4_INTC_SEL35_INTSEL3 (*((volatile unsigned int*)(0x42A21D0CUL))) +#define bM4_INTC_SEL35_INTSEL4 (*((volatile unsigned int*)(0x42A21D10UL))) +#define bM4_INTC_SEL35_INTSEL5 (*((volatile unsigned int*)(0x42A21D14UL))) +#define bM4_INTC_SEL35_INTSEL6 (*((volatile unsigned int*)(0x42A21D18UL))) +#define bM4_INTC_SEL35_INTSEL7 (*((volatile unsigned int*)(0x42A21D1CUL))) +#define bM4_INTC_SEL35_INTSEL8 (*((volatile unsigned int*)(0x42A21D20UL))) +#define bM4_INTC_SEL36_INTSEL0 (*((volatile unsigned int*)(0x42A21D80UL))) +#define bM4_INTC_SEL36_INTSEL1 (*((volatile unsigned int*)(0x42A21D84UL))) +#define bM4_INTC_SEL36_INTSEL2 (*((volatile unsigned int*)(0x42A21D88UL))) +#define bM4_INTC_SEL36_INTSEL3 (*((volatile unsigned int*)(0x42A21D8CUL))) +#define bM4_INTC_SEL36_INTSEL4 (*((volatile unsigned int*)(0x42A21D90UL))) +#define bM4_INTC_SEL36_INTSEL5 (*((volatile unsigned int*)(0x42A21D94UL))) +#define bM4_INTC_SEL36_INTSEL6 (*((volatile unsigned int*)(0x42A21D98UL))) +#define bM4_INTC_SEL36_INTSEL7 (*((volatile unsigned int*)(0x42A21D9CUL))) +#define bM4_INTC_SEL36_INTSEL8 (*((volatile unsigned int*)(0x42A21DA0UL))) +#define bM4_INTC_SEL37_INTSEL0 (*((volatile unsigned int*)(0x42A21E00UL))) +#define bM4_INTC_SEL37_INTSEL1 (*((volatile unsigned int*)(0x42A21E04UL))) +#define bM4_INTC_SEL37_INTSEL2 (*((volatile unsigned int*)(0x42A21E08UL))) +#define bM4_INTC_SEL37_INTSEL3 (*((volatile unsigned int*)(0x42A21E0CUL))) +#define bM4_INTC_SEL37_INTSEL4 (*((volatile unsigned int*)(0x42A21E10UL))) +#define bM4_INTC_SEL37_INTSEL5 (*((volatile unsigned int*)(0x42A21E14UL))) +#define bM4_INTC_SEL37_INTSEL6 (*((volatile unsigned int*)(0x42A21E18UL))) +#define bM4_INTC_SEL37_INTSEL7 (*((volatile unsigned int*)(0x42A21E1CUL))) +#define bM4_INTC_SEL37_INTSEL8 (*((volatile unsigned int*)(0x42A21E20UL))) +#define bM4_INTC_SEL38_INTSEL0 (*((volatile unsigned int*)(0x42A21E80UL))) +#define bM4_INTC_SEL38_INTSEL1 (*((volatile unsigned int*)(0x42A21E84UL))) +#define bM4_INTC_SEL38_INTSEL2 (*((volatile unsigned int*)(0x42A21E88UL))) +#define bM4_INTC_SEL38_INTSEL3 (*((volatile unsigned int*)(0x42A21E8CUL))) +#define bM4_INTC_SEL38_INTSEL4 (*((volatile unsigned int*)(0x42A21E90UL))) +#define bM4_INTC_SEL38_INTSEL5 (*((volatile unsigned int*)(0x42A21E94UL))) +#define bM4_INTC_SEL38_INTSEL6 (*((volatile unsigned int*)(0x42A21E98UL))) +#define bM4_INTC_SEL38_INTSEL7 (*((volatile unsigned int*)(0x42A21E9CUL))) +#define bM4_INTC_SEL38_INTSEL8 (*((volatile unsigned int*)(0x42A21EA0UL))) +#define bM4_INTC_SEL39_INTSEL0 (*((volatile unsigned int*)(0x42A21F00UL))) +#define bM4_INTC_SEL39_INTSEL1 (*((volatile unsigned int*)(0x42A21F04UL))) +#define bM4_INTC_SEL39_INTSEL2 (*((volatile unsigned int*)(0x42A21F08UL))) +#define bM4_INTC_SEL39_INTSEL3 (*((volatile unsigned int*)(0x42A21F0CUL))) +#define bM4_INTC_SEL39_INTSEL4 (*((volatile unsigned int*)(0x42A21F10UL))) +#define bM4_INTC_SEL39_INTSEL5 (*((volatile unsigned int*)(0x42A21F14UL))) +#define bM4_INTC_SEL39_INTSEL6 (*((volatile unsigned int*)(0x42A21F18UL))) +#define bM4_INTC_SEL39_INTSEL7 (*((volatile unsigned int*)(0x42A21F1CUL))) +#define bM4_INTC_SEL39_INTSEL8 (*((volatile unsigned int*)(0x42A21F20UL))) +#define bM4_INTC_SEL40_INTSEL0 (*((volatile unsigned int*)(0x42A21F80UL))) +#define bM4_INTC_SEL40_INTSEL1 (*((volatile unsigned int*)(0x42A21F84UL))) +#define bM4_INTC_SEL40_INTSEL2 (*((volatile unsigned int*)(0x42A21F88UL))) +#define bM4_INTC_SEL40_INTSEL3 (*((volatile unsigned int*)(0x42A21F8CUL))) +#define bM4_INTC_SEL40_INTSEL4 (*((volatile unsigned int*)(0x42A21F90UL))) +#define bM4_INTC_SEL40_INTSEL5 (*((volatile unsigned int*)(0x42A21F94UL))) +#define bM4_INTC_SEL40_INTSEL6 (*((volatile unsigned int*)(0x42A21F98UL))) +#define bM4_INTC_SEL40_INTSEL7 (*((volatile unsigned int*)(0x42A21F9CUL))) +#define bM4_INTC_SEL40_INTSEL8 (*((volatile unsigned int*)(0x42A21FA0UL))) +#define bM4_INTC_SEL41_INTSEL0 (*((volatile unsigned int*)(0x42A22000UL))) +#define bM4_INTC_SEL41_INTSEL1 (*((volatile unsigned int*)(0x42A22004UL))) +#define bM4_INTC_SEL41_INTSEL2 (*((volatile unsigned int*)(0x42A22008UL))) +#define bM4_INTC_SEL41_INTSEL3 (*((volatile unsigned int*)(0x42A2200CUL))) +#define bM4_INTC_SEL41_INTSEL4 (*((volatile unsigned int*)(0x42A22010UL))) +#define bM4_INTC_SEL41_INTSEL5 (*((volatile unsigned int*)(0x42A22014UL))) +#define bM4_INTC_SEL41_INTSEL6 (*((volatile unsigned int*)(0x42A22018UL))) +#define bM4_INTC_SEL41_INTSEL7 (*((volatile unsigned int*)(0x42A2201CUL))) +#define bM4_INTC_SEL41_INTSEL8 (*((volatile unsigned int*)(0x42A22020UL))) +#define bM4_INTC_SEL42_INTSEL0 (*((volatile unsigned int*)(0x42A22080UL))) +#define bM4_INTC_SEL42_INTSEL1 (*((volatile unsigned int*)(0x42A22084UL))) +#define bM4_INTC_SEL42_INTSEL2 (*((volatile unsigned int*)(0x42A22088UL))) +#define bM4_INTC_SEL42_INTSEL3 (*((volatile unsigned int*)(0x42A2208CUL))) +#define bM4_INTC_SEL42_INTSEL4 (*((volatile unsigned int*)(0x42A22090UL))) +#define bM4_INTC_SEL42_INTSEL5 (*((volatile unsigned int*)(0x42A22094UL))) +#define bM4_INTC_SEL42_INTSEL6 (*((volatile unsigned int*)(0x42A22098UL))) +#define bM4_INTC_SEL42_INTSEL7 (*((volatile unsigned int*)(0x42A2209CUL))) +#define bM4_INTC_SEL42_INTSEL8 (*((volatile unsigned int*)(0x42A220A0UL))) +#define bM4_INTC_SEL43_INTSEL0 (*((volatile unsigned int*)(0x42A22100UL))) +#define bM4_INTC_SEL43_INTSEL1 (*((volatile unsigned int*)(0x42A22104UL))) +#define bM4_INTC_SEL43_INTSEL2 (*((volatile unsigned int*)(0x42A22108UL))) +#define bM4_INTC_SEL43_INTSEL3 (*((volatile unsigned int*)(0x42A2210CUL))) +#define bM4_INTC_SEL43_INTSEL4 (*((volatile unsigned int*)(0x42A22110UL))) +#define bM4_INTC_SEL43_INTSEL5 (*((volatile unsigned int*)(0x42A22114UL))) +#define bM4_INTC_SEL43_INTSEL6 (*((volatile unsigned int*)(0x42A22118UL))) +#define bM4_INTC_SEL43_INTSEL7 (*((volatile unsigned int*)(0x42A2211CUL))) +#define bM4_INTC_SEL43_INTSEL8 (*((volatile unsigned int*)(0x42A22120UL))) +#define bM4_INTC_SEL44_INTSEL0 (*((volatile unsigned int*)(0x42A22180UL))) +#define bM4_INTC_SEL44_INTSEL1 (*((volatile unsigned int*)(0x42A22184UL))) +#define bM4_INTC_SEL44_INTSEL2 (*((volatile unsigned int*)(0x42A22188UL))) +#define bM4_INTC_SEL44_INTSEL3 (*((volatile unsigned int*)(0x42A2218CUL))) +#define bM4_INTC_SEL44_INTSEL4 (*((volatile unsigned int*)(0x42A22190UL))) +#define bM4_INTC_SEL44_INTSEL5 (*((volatile unsigned int*)(0x42A22194UL))) +#define bM4_INTC_SEL44_INTSEL6 (*((volatile unsigned int*)(0x42A22198UL))) +#define bM4_INTC_SEL44_INTSEL7 (*((volatile unsigned int*)(0x42A2219CUL))) +#define bM4_INTC_SEL44_INTSEL8 (*((volatile unsigned int*)(0x42A221A0UL))) +#define bM4_INTC_SEL45_INTSEL0 (*((volatile unsigned int*)(0x42A22200UL))) +#define bM4_INTC_SEL45_INTSEL1 (*((volatile unsigned int*)(0x42A22204UL))) +#define bM4_INTC_SEL45_INTSEL2 (*((volatile unsigned int*)(0x42A22208UL))) +#define bM4_INTC_SEL45_INTSEL3 (*((volatile unsigned int*)(0x42A2220CUL))) +#define bM4_INTC_SEL45_INTSEL4 (*((volatile unsigned int*)(0x42A22210UL))) +#define bM4_INTC_SEL45_INTSEL5 (*((volatile unsigned int*)(0x42A22214UL))) +#define bM4_INTC_SEL45_INTSEL6 (*((volatile unsigned int*)(0x42A22218UL))) +#define bM4_INTC_SEL45_INTSEL7 (*((volatile unsigned int*)(0x42A2221CUL))) +#define bM4_INTC_SEL45_INTSEL8 (*((volatile unsigned int*)(0x42A22220UL))) +#define bM4_INTC_SEL46_INTSEL0 (*((volatile unsigned int*)(0x42A22280UL))) +#define bM4_INTC_SEL46_INTSEL1 (*((volatile unsigned int*)(0x42A22284UL))) +#define bM4_INTC_SEL46_INTSEL2 (*((volatile unsigned int*)(0x42A22288UL))) +#define bM4_INTC_SEL46_INTSEL3 (*((volatile unsigned int*)(0x42A2228CUL))) +#define bM4_INTC_SEL46_INTSEL4 (*((volatile unsigned int*)(0x42A22290UL))) +#define bM4_INTC_SEL46_INTSEL5 (*((volatile unsigned int*)(0x42A22294UL))) +#define bM4_INTC_SEL46_INTSEL6 (*((volatile unsigned int*)(0x42A22298UL))) +#define bM4_INTC_SEL46_INTSEL7 (*((volatile unsigned int*)(0x42A2229CUL))) +#define bM4_INTC_SEL46_INTSEL8 (*((volatile unsigned int*)(0x42A222A0UL))) +#define bM4_INTC_SEL47_INTSEL0 (*((volatile unsigned int*)(0x42A22300UL))) +#define bM4_INTC_SEL47_INTSEL1 (*((volatile unsigned int*)(0x42A22304UL))) +#define bM4_INTC_SEL47_INTSEL2 (*((volatile unsigned int*)(0x42A22308UL))) +#define bM4_INTC_SEL47_INTSEL3 (*((volatile unsigned int*)(0x42A2230CUL))) +#define bM4_INTC_SEL47_INTSEL4 (*((volatile unsigned int*)(0x42A22310UL))) +#define bM4_INTC_SEL47_INTSEL5 (*((volatile unsigned int*)(0x42A22314UL))) +#define bM4_INTC_SEL47_INTSEL6 (*((volatile unsigned int*)(0x42A22318UL))) +#define bM4_INTC_SEL47_INTSEL7 (*((volatile unsigned int*)(0x42A2231CUL))) +#define bM4_INTC_SEL47_INTSEL8 (*((volatile unsigned int*)(0x42A22320UL))) +#define bM4_INTC_SEL48_INTSEL0 (*((volatile unsigned int*)(0x42A22380UL))) +#define bM4_INTC_SEL48_INTSEL1 (*((volatile unsigned int*)(0x42A22384UL))) +#define bM4_INTC_SEL48_INTSEL2 (*((volatile unsigned int*)(0x42A22388UL))) +#define bM4_INTC_SEL48_INTSEL3 (*((volatile unsigned int*)(0x42A2238CUL))) +#define bM4_INTC_SEL48_INTSEL4 (*((volatile unsigned int*)(0x42A22390UL))) +#define bM4_INTC_SEL48_INTSEL5 (*((volatile unsigned int*)(0x42A22394UL))) +#define bM4_INTC_SEL48_INTSEL6 (*((volatile unsigned int*)(0x42A22398UL))) +#define bM4_INTC_SEL48_INTSEL7 (*((volatile unsigned int*)(0x42A2239CUL))) +#define bM4_INTC_SEL48_INTSEL8 (*((volatile unsigned int*)(0x42A223A0UL))) +#define bM4_INTC_SEL49_INTSEL0 (*((volatile unsigned int*)(0x42A22400UL))) +#define bM4_INTC_SEL49_INTSEL1 (*((volatile unsigned int*)(0x42A22404UL))) +#define bM4_INTC_SEL49_INTSEL2 (*((volatile unsigned int*)(0x42A22408UL))) +#define bM4_INTC_SEL49_INTSEL3 (*((volatile unsigned int*)(0x42A2240CUL))) +#define bM4_INTC_SEL49_INTSEL4 (*((volatile unsigned int*)(0x42A22410UL))) +#define bM4_INTC_SEL49_INTSEL5 (*((volatile unsigned int*)(0x42A22414UL))) +#define bM4_INTC_SEL49_INTSEL6 (*((volatile unsigned int*)(0x42A22418UL))) +#define bM4_INTC_SEL49_INTSEL7 (*((volatile unsigned int*)(0x42A2241CUL))) +#define bM4_INTC_SEL49_INTSEL8 (*((volatile unsigned int*)(0x42A22420UL))) +#define bM4_INTC_SEL50_INTSEL0 (*((volatile unsigned int*)(0x42A22480UL))) +#define bM4_INTC_SEL50_INTSEL1 (*((volatile unsigned int*)(0x42A22484UL))) +#define bM4_INTC_SEL50_INTSEL2 (*((volatile unsigned int*)(0x42A22488UL))) +#define bM4_INTC_SEL50_INTSEL3 (*((volatile unsigned int*)(0x42A2248CUL))) +#define bM4_INTC_SEL50_INTSEL4 (*((volatile unsigned int*)(0x42A22490UL))) +#define bM4_INTC_SEL50_INTSEL5 (*((volatile unsigned int*)(0x42A22494UL))) +#define bM4_INTC_SEL50_INTSEL6 (*((volatile unsigned int*)(0x42A22498UL))) +#define bM4_INTC_SEL50_INTSEL7 (*((volatile unsigned int*)(0x42A2249CUL))) +#define bM4_INTC_SEL50_INTSEL8 (*((volatile unsigned int*)(0x42A224A0UL))) +#define bM4_INTC_SEL51_INTSEL0 (*((volatile unsigned int*)(0x42A22500UL))) +#define bM4_INTC_SEL51_INTSEL1 (*((volatile unsigned int*)(0x42A22504UL))) +#define bM4_INTC_SEL51_INTSEL2 (*((volatile unsigned int*)(0x42A22508UL))) +#define bM4_INTC_SEL51_INTSEL3 (*((volatile unsigned int*)(0x42A2250CUL))) +#define bM4_INTC_SEL51_INTSEL4 (*((volatile unsigned int*)(0x42A22510UL))) +#define bM4_INTC_SEL51_INTSEL5 (*((volatile unsigned int*)(0x42A22514UL))) +#define bM4_INTC_SEL51_INTSEL6 (*((volatile unsigned int*)(0x42A22518UL))) +#define bM4_INTC_SEL51_INTSEL7 (*((volatile unsigned int*)(0x42A2251CUL))) +#define bM4_INTC_SEL51_INTSEL8 (*((volatile unsigned int*)(0x42A22520UL))) +#define bM4_INTC_SEL52_INTSEL0 (*((volatile unsigned int*)(0x42A22580UL))) +#define bM4_INTC_SEL52_INTSEL1 (*((volatile unsigned int*)(0x42A22584UL))) +#define bM4_INTC_SEL52_INTSEL2 (*((volatile unsigned int*)(0x42A22588UL))) +#define bM4_INTC_SEL52_INTSEL3 (*((volatile unsigned int*)(0x42A2258CUL))) +#define bM4_INTC_SEL52_INTSEL4 (*((volatile unsigned int*)(0x42A22590UL))) +#define bM4_INTC_SEL52_INTSEL5 (*((volatile unsigned int*)(0x42A22594UL))) +#define bM4_INTC_SEL52_INTSEL6 (*((volatile unsigned int*)(0x42A22598UL))) +#define bM4_INTC_SEL52_INTSEL7 (*((volatile unsigned int*)(0x42A2259CUL))) +#define bM4_INTC_SEL52_INTSEL8 (*((volatile unsigned int*)(0x42A225A0UL))) +#define bM4_INTC_SEL53_INTSEL0 (*((volatile unsigned int*)(0x42A22600UL))) +#define bM4_INTC_SEL53_INTSEL1 (*((volatile unsigned int*)(0x42A22604UL))) +#define bM4_INTC_SEL53_INTSEL2 (*((volatile unsigned int*)(0x42A22608UL))) +#define bM4_INTC_SEL53_INTSEL3 (*((volatile unsigned int*)(0x42A2260CUL))) +#define bM4_INTC_SEL53_INTSEL4 (*((volatile unsigned int*)(0x42A22610UL))) +#define bM4_INTC_SEL53_INTSEL5 (*((volatile unsigned int*)(0x42A22614UL))) +#define bM4_INTC_SEL53_INTSEL6 (*((volatile unsigned int*)(0x42A22618UL))) +#define bM4_INTC_SEL53_INTSEL7 (*((volatile unsigned int*)(0x42A2261CUL))) +#define bM4_INTC_SEL53_INTSEL8 (*((volatile unsigned int*)(0x42A22620UL))) +#define bM4_INTC_SEL54_INTSEL0 (*((volatile unsigned int*)(0x42A22680UL))) +#define bM4_INTC_SEL54_INTSEL1 (*((volatile unsigned int*)(0x42A22684UL))) +#define bM4_INTC_SEL54_INTSEL2 (*((volatile unsigned int*)(0x42A22688UL))) +#define bM4_INTC_SEL54_INTSEL3 (*((volatile unsigned int*)(0x42A2268CUL))) +#define bM4_INTC_SEL54_INTSEL4 (*((volatile unsigned int*)(0x42A22690UL))) +#define bM4_INTC_SEL54_INTSEL5 (*((volatile unsigned int*)(0x42A22694UL))) +#define bM4_INTC_SEL54_INTSEL6 (*((volatile unsigned int*)(0x42A22698UL))) +#define bM4_INTC_SEL54_INTSEL7 (*((volatile unsigned int*)(0x42A2269CUL))) +#define bM4_INTC_SEL54_INTSEL8 (*((volatile unsigned int*)(0x42A226A0UL))) +#define bM4_INTC_SEL55_INTSEL0 (*((volatile unsigned int*)(0x42A22700UL))) +#define bM4_INTC_SEL55_INTSEL1 (*((volatile unsigned int*)(0x42A22704UL))) +#define bM4_INTC_SEL55_INTSEL2 (*((volatile unsigned int*)(0x42A22708UL))) +#define bM4_INTC_SEL55_INTSEL3 (*((volatile unsigned int*)(0x42A2270CUL))) +#define bM4_INTC_SEL55_INTSEL4 (*((volatile unsigned int*)(0x42A22710UL))) +#define bM4_INTC_SEL55_INTSEL5 (*((volatile unsigned int*)(0x42A22714UL))) +#define bM4_INTC_SEL55_INTSEL6 (*((volatile unsigned int*)(0x42A22718UL))) +#define bM4_INTC_SEL55_INTSEL7 (*((volatile unsigned int*)(0x42A2271CUL))) +#define bM4_INTC_SEL55_INTSEL8 (*((volatile unsigned int*)(0x42A22720UL))) +#define bM4_INTC_SEL56_INTSEL0 (*((volatile unsigned int*)(0x42A22780UL))) +#define bM4_INTC_SEL56_INTSEL1 (*((volatile unsigned int*)(0x42A22784UL))) +#define bM4_INTC_SEL56_INTSEL2 (*((volatile unsigned int*)(0x42A22788UL))) +#define bM4_INTC_SEL56_INTSEL3 (*((volatile unsigned int*)(0x42A2278CUL))) +#define bM4_INTC_SEL56_INTSEL4 (*((volatile unsigned int*)(0x42A22790UL))) +#define bM4_INTC_SEL56_INTSEL5 (*((volatile unsigned int*)(0x42A22794UL))) +#define bM4_INTC_SEL56_INTSEL6 (*((volatile unsigned int*)(0x42A22798UL))) +#define bM4_INTC_SEL56_INTSEL7 (*((volatile unsigned int*)(0x42A2279CUL))) +#define bM4_INTC_SEL56_INTSEL8 (*((volatile unsigned int*)(0x42A227A0UL))) +#define bM4_INTC_SEL57_INTSEL0 (*((volatile unsigned int*)(0x42A22800UL))) +#define bM4_INTC_SEL57_INTSEL1 (*((volatile unsigned int*)(0x42A22804UL))) +#define bM4_INTC_SEL57_INTSEL2 (*((volatile unsigned int*)(0x42A22808UL))) +#define bM4_INTC_SEL57_INTSEL3 (*((volatile unsigned int*)(0x42A2280CUL))) +#define bM4_INTC_SEL57_INTSEL4 (*((volatile unsigned int*)(0x42A22810UL))) +#define bM4_INTC_SEL57_INTSEL5 (*((volatile unsigned int*)(0x42A22814UL))) +#define bM4_INTC_SEL57_INTSEL6 (*((volatile unsigned int*)(0x42A22818UL))) +#define bM4_INTC_SEL57_INTSEL7 (*((volatile unsigned int*)(0x42A2281CUL))) +#define bM4_INTC_SEL57_INTSEL8 (*((volatile unsigned int*)(0x42A22820UL))) +#define bM4_INTC_SEL58_INTSEL0 (*((volatile unsigned int*)(0x42A22880UL))) +#define bM4_INTC_SEL58_INTSEL1 (*((volatile unsigned int*)(0x42A22884UL))) +#define bM4_INTC_SEL58_INTSEL2 (*((volatile unsigned int*)(0x42A22888UL))) +#define bM4_INTC_SEL58_INTSEL3 (*((volatile unsigned int*)(0x42A2288CUL))) +#define bM4_INTC_SEL58_INTSEL4 (*((volatile unsigned int*)(0x42A22890UL))) +#define bM4_INTC_SEL58_INTSEL5 (*((volatile unsigned int*)(0x42A22894UL))) +#define bM4_INTC_SEL58_INTSEL6 (*((volatile unsigned int*)(0x42A22898UL))) +#define bM4_INTC_SEL58_INTSEL7 (*((volatile unsigned int*)(0x42A2289CUL))) +#define bM4_INTC_SEL58_INTSEL8 (*((volatile unsigned int*)(0x42A228A0UL))) +#define bM4_INTC_SEL59_INTSEL0 (*((volatile unsigned int*)(0x42A22900UL))) +#define bM4_INTC_SEL59_INTSEL1 (*((volatile unsigned int*)(0x42A22904UL))) +#define bM4_INTC_SEL59_INTSEL2 (*((volatile unsigned int*)(0x42A22908UL))) +#define bM4_INTC_SEL59_INTSEL3 (*((volatile unsigned int*)(0x42A2290CUL))) +#define bM4_INTC_SEL59_INTSEL4 (*((volatile unsigned int*)(0x42A22910UL))) +#define bM4_INTC_SEL59_INTSEL5 (*((volatile unsigned int*)(0x42A22914UL))) +#define bM4_INTC_SEL59_INTSEL6 (*((volatile unsigned int*)(0x42A22918UL))) +#define bM4_INTC_SEL59_INTSEL7 (*((volatile unsigned int*)(0x42A2291CUL))) +#define bM4_INTC_SEL59_INTSEL8 (*((volatile unsigned int*)(0x42A22920UL))) +#define bM4_INTC_SEL60_INTSEL0 (*((volatile unsigned int*)(0x42A22980UL))) +#define bM4_INTC_SEL60_INTSEL1 (*((volatile unsigned int*)(0x42A22984UL))) +#define bM4_INTC_SEL60_INTSEL2 (*((volatile unsigned int*)(0x42A22988UL))) +#define bM4_INTC_SEL60_INTSEL3 (*((volatile unsigned int*)(0x42A2298CUL))) +#define bM4_INTC_SEL60_INTSEL4 (*((volatile unsigned int*)(0x42A22990UL))) +#define bM4_INTC_SEL60_INTSEL5 (*((volatile unsigned int*)(0x42A22994UL))) +#define bM4_INTC_SEL60_INTSEL6 (*((volatile unsigned int*)(0x42A22998UL))) +#define bM4_INTC_SEL60_INTSEL7 (*((volatile unsigned int*)(0x42A2299CUL))) +#define bM4_INTC_SEL60_INTSEL8 (*((volatile unsigned int*)(0x42A229A0UL))) +#define bM4_INTC_SEL61_INTSEL0 (*((volatile unsigned int*)(0x42A22A00UL))) +#define bM4_INTC_SEL61_INTSEL1 (*((volatile unsigned int*)(0x42A22A04UL))) +#define bM4_INTC_SEL61_INTSEL2 (*((volatile unsigned int*)(0x42A22A08UL))) +#define bM4_INTC_SEL61_INTSEL3 (*((volatile unsigned int*)(0x42A22A0CUL))) +#define bM4_INTC_SEL61_INTSEL4 (*((volatile unsigned int*)(0x42A22A10UL))) +#define bM4_INTC_SEL61_INTSEL5 (*((volatile unsigned int*)(0x42A22A14UL))) +#define bM4_INTC_SEL61_INTSEL6 (*((volatile unsigned int*)(0x42A22A18UL))) +#define bM4_INTC_SEL61_INTSEL7 (*((volatile unsigned int*)(0x42A22A1CUL))) +#define bM4_INTC_SEL61_INTSEL8 (*((volatile unsigned int*)(0x42A22A20UL))) +#define bM4_INTC_SEL62_INTSEL0 (*((volatile unsigned int*)(0x42A22A80UL))) +#define bM4_INTC_SEL62_INTSEL1 (*((volatile unsigned int*)(0x42A22A84UL))) +#define bM4_INTC_SEL62_INTSEL2 (*((volatile unsigned int*)(0x42A22A88UL))) +#define bM4_INTC_SEL62_INTSEL3 (*((volatile unsigned int*)(0x42A22A8CUL))) +#define bM4_INTC_SEL62_INTSEL4 (*((volatile unsigned int*)(0x42A22A90UL))) +#define bM4_INTC_SEL62_INTSEL5 (*((volatile unsigned int*)(0x42A22A94UL))) +#define bM4_INTC_SEL62_INTSEL6 (*((volatile unsigned int*)(0x42A22A98UL))) +#define bM4_INTC_SEL62_INTSEL7 (*((volatile unsigned int*)(0x42A22A9CUL))) +#define bM4_INTC_SEL62_INTSEL8 (*((volatile unsigned int*)(0x42A22AA0UL))) +#define bM4_INTC_SEL63_INTSEL0 (*((volatile unsigned int*)(0x42A22B00UL))) +#define bM4_INTC_SEL63_INTSEL1 (*((volatile unsigned int*)(0x42A22B04UL))) +#define bM4_INTC_SEL63_INTSEL2 (*((volatile unsigned int*)(0x42A22B08UL))) +#define bM4_INTC_SEL63_INTSEL3 (*((volatile unsigned int*)(0x42A22B0CUL))) +#define bM4_INTC_SEL63_INTSEL4 (*((volatile unsigned int*)(0x42A22B10UL))) +#define bM4_INTC_SEL63_INTSEL5 (*((volatile unsigned int*)(0x42A22B14UL))) +#define bM4_INTC_SEL63_INTSEL6 (*((volatile unsigned int*)(0x42A22B18UL))) +#define bM4_INTC_SEL63_INTSEL7 (*((volatile unsigned int*)(0x42A22B1CUL))) +#define bM4_INTC_SEL63_INTSEL8 (*((volatile unsigned int*)(0x42A22B20UL))) +#define bM4_INTC_SEL64_INTSEL0 (*((volatile unsigned int*)(0x42A22B80UL))) +#define bM4_INTC_SEL64_INTSEL1 (*((volatile unsigned int*)(0x42A22B84UL))) +#define bM4_INTC_SEL64_INTSEL2 (*((volatile unsigned int*)(0x42A22B88UL))) +#define bM4_INTC_SEL64_INTSEL3 (*((volatile unsigned int*)(0x42A22B8CUL))) +#define bM4_INTC_SEL64_INTSEL4 (*((volatile unsigned int*)(0x42A22B90UL))) +#define bM4_INTC_SEL64_INTSEL5 (*((volatile unsigned int*)(0x42A22B94UL))) +#define bM4_INTC_SEL64_INTSEL6 (*((volatile unsigned int*)(0x42A22B98UL))) +#define bM4_INTC_SEL64_INTSEL7 (*((volatile unsigned int*)(0x42A22B9CUL))) +#define bM4_INTC_SEL64_INTSEL8 (*((volatile unsigned int*)(0x42A22BA0UL))) +#define bM4_INTC_SEL65_INTSEL0 (*((volatile unsigned int*)(0x42A22C00UL))) +#define bM4_INTC_SEL65_INTSEL1 (*((volatile unsigned int*)(0x42A22C04UL))) +#define bM4_INTC_SEL65_INTSEL2 (*((volatile unsigned int*)(0x42A22C08UL))) +#define bM4_INTC_SEL65_INTSEL3 (*((volatile unsigned int*)(0x42A22C0CUL))) +#define bM4_INTC_SEL65_INTSEL4 (*((volatile unsigned int*)(0x42A22C10UL))) +#define bM4_INTC_SEL65_INTSEL5 (*((volatile unsigned int*)(0x42A22C14UL))) +#define bM4_INTC_SEL65_INTSEL6 (*((volatile unsigned int*)(0x42A22C18UL))) +#define bM4_INTC_SEL65_INTSEL7 (*((volatile unsigned int*)(0x42A22C1CUL))) +#define bM4_INTC_SEL65_INTSEL8 (*((volatile unsigned int*)(0x42A22C20UL))) +#define bM4_INTC_SEL66_INTSEL0 (*((volatile unsigned int*)(0x42A22C80UL))) +#define bM4_INTC_SEL66_INTSEL1 (*((volatile unsigned int*)(0x42A22C84UL))) +#define bM4_INTC_SEL66_INTSEL2 (*((volatile unsigned int*)(0x42A22C88UL))) +#define bM4_INTC_SEL66_INTSEL3 (*((volatile unsigned int*)(0x42A22C8CUL))) +#define bM4_INTC_SEL66_INTSEL4 (*((volatile unsigned int*)(0x42A22C90UL))) +#define bM4_INTC_SEL66_INTSEL5 (*((volatile unsigned int*)(0x42A22C94UL))) +#define bM4_INTC_SEL66_INTSEL6 (*((volatile unsigned int*)(0x42A22C98UL))) +#define bM4_INTC_SEL66_INTSEL7 (*((volatile unsigned int*)(0x42A22C9CUL))) +#define bM4_INTC_SEL66_INTSEL8 (*((volatile unsigned int*)(0x42A22CA0UL))) +#define bM4_INTC_SEL67_INTSEL0 (*((volatile unsigned int*)(0x42A22D00UL))) +#define bM4_INTC_SEL67_INTSEL1 (*((volatile unsigned int*)(0x42A22D04UL))) +#define bM4_INTC_SEL67_INTSEL2 (*((volatile unsigned int*)(0x42A22D08UL))) +#define bM4_INTC_SEL67_INTSEL3 (*((volatile unsigned int*)(0x42A22D0CUL))) +#define bM4_INTC_SEL67_INTSEL4 (*((volatile unsigned int*)(0x42A22D10UL))) +#define bM4_INTC_SEL67_INTSEL5 (*((volatile unsigned int*)(0x42A22D14UL))) +#define bM4_INTC_SEL67_INTSEL6 (*((volatile unsigned int*)(0x42A22D18UL))) +#define bM4_INTC_SEL67_INTSEL7 (*((volatile unsigned int*)(0x42A22D1CUL))) +#define bM4_INTC_SEL67_INTSEL8 (*((volatile unsigned int*)(0x42A22D20UL))) +#define bM4_INTC_SEL68_INTSEL0 (*((volatile unsigned int*)(0x42A22D80UL))) +#define bM4_INTC_SEL68_INTSEL1 (*((volatile unsigned int*)(0x42A22D84UL))) +#define bM4_INTC_SEL68_INTSEL2 (*((volatile unsigned int*)(0x42A22D88UL))) +#define bM4_INTC_SEL68_INTSEL3 (*((volatile unsigned int*)(0x42A22D8CUL))) +#define bM4_INTC_SEL68_INTSEL4 (*((volatile unsigned int*)(0x42A22D90UL))) +#define bM4_INTC_SEL68_INTSEL5 (*((volatile unsigned int*)(0x42A22D94UL))) +#define bM4_INTC_SEL68_INTSEL6 (*((volatile unsigned int*)(0x42A22D98UL))) +#define bM4_INTC_SEL68_INTSEL7 (*((volatile unsigned int*)(0x42A22D9CUL))) +#define bM4_INTC_SEL68_INTSEL8 (*((volatile unsigned int*)(0x42A22DA0UL))) +#define bM4_INTC_SEL69_INTSEL0 (*((volatile unsigned int*)(0x42A22E00UL))) +#define bM4_INTC_SEL69_INTSEL1 (*((volatile unsigned int*)(0x42A22E04UL))) +#define bM4_INTC_SEL69_INTSEL2 (*((volatile unsigned int*)(0x42A22E08UL))) +#define bM4_INTC_SEL69_INTSEL3 (*((volatile unsigned int*)(0x42A22E0CUL))) +#define bM4_INTC_SEL69_INTSEL4 (*((volatile unsigned int*)(0x42A22E10UL))) +#define bM4_INTC_SEL69_INTSEL5 (*((volatile unsigned int*)(0x42A22E14UL))) +#define bM4_INTC_SEL69_INTSEL6 (*((volatile unsigned int*)(0x42A22E18UL))) +#define bM4_INTC_SEL69_INTSEL7 (*((volatile unsigned int*)(0x42A22E1CUL))) +#define bM4_INTC_SEL69_INTSEL8 (*((volatile unsigned int*)(0x42A22E20UL))) +#define bM4_INTC_SEL70_INTSEL0 (*((volatile unsigned int*)(0x42A22E80UL))) +#define bM4_INTC_SEL70_INTSEL1 (*((volatile unsigned int*)(0x42A22E84UL))) +#define bM4_INTC_SEL70_INTSEL2 (*((volatile unsigned int*)(0x42A22E88UL))) +#define bM4_INTC_SEL70_INTSEL3 (*((volatile unsigned int*)(0x42A22E8CUL))) +#define bM4_INTC_SEL70_INTSEL4 (*((volatile unsigned int*)(0x42A22E90UL))) +#define bM4_INTC_SEL70_INTSEL5 (*((volatile unsigned int*)(0x42A22E94UL))) +#define bM4_INTC_SEL70_INTSEL6 (*((volatile unsigned int*)(0x42A22E98UL))) +#define bM4_INTC_SEL70_INTSEL7 (*((volatile unsigned int*)(0x42A22E9CUL))) +#define bM4_INTC_SEL70_INTSEL8 (*((volatile unsigned int*)(0x42A22EA0UL))) +#define bM4_INTC_SEL71_INTSEL0 (*((volatile unsigned int*)(0x42A22F00UL))) +#define bM4_INTC_SEL71_INTSEL1 (*((volatile unsigned int*)(0x42A22F04UL))) +#define bM4_INTC_SEL71_INTSEL2 (*((volatile unsigned int*)(0x42A22F08UL))) +#define bM4_INTC_SEL71_INTSEL3 (*((volatile unsigned int*)(0x42A22F0CUL))) +#define bM4_INTC_SEL71_INTSEL4 (*((volatile unsigned int*)(0x42A22F10UL))) +#define bM4_INTC_SEL71_INTSEL5 (*((volatile unsigned int*)(0x42A22F14UL))) +#define bM4_INTC_SEL71_INTSEL6 (*((volatile unsigned int*)(0x42A22F18UL))) +#define bM4_INTC_SEL71_INTSEL7 (*((volatile unsigned int*)(0x42A22F1CUL))) +#define bM4_INTC_SEL71_INTSEL8 (*((volatile unsigned int*)(0x42A22F20UL))) +#define bM4_INTC_SEL72_INTSEL0 (*((volatile unsigned int*)(0x42A22F80UL))) +#define bM4_INTC_SEL72_INTSEL1 (*((volatile unsigned int*)(0x42A22F84UL))) +#define bM4_INTC_SEL72_INTSEL2 (*((volatile unsigned int*)(0x42A22F88UL))) +#define bM4_INTC_SEL72_INTSEL3 (*((volatile unsigned int*)(0x42A22F8CUL))) +#define bM4_INTC_SEL72_INTSEL4 (*((volatile unsigned int*)(0x42A22F90UL))) +#define bM4_INTC_SEL72_INTSEL5 (*((volatile unsigned int*)(0x42A22F94UL))) +#define bM4_INTC_SEL72_INTSEL6 (*((volatile unsigned int*)(0x42A22F98UL))) +#define bM4_INTC_SEL72_INTSEL7 (*((volatile unsigned int*)(0x42A22F9CUL))) +#define bM4_INTC_SEL72_INTSEL8 (*((volatile unsigned int*)(0x42A22FA0UL))) +#define bM4_INTC_SEL73_INTSEL0 (*((volatile unsigned int*)(0x42A23000UL))) +#define bM4_INTC_SEL73_INTSEL1 (*((volatile unsigned int*)(0x42A23004UL))) +#define bM4_INTC_SEL73_INTSEL2 (*((volatile unsigned int*)(0x42A23008UL))) +#define bM4_INTC_SEL73_INTSEL3 (*((volatile unsigned int*)(0x42A2300CUL))) +#define bM4_INTC_SEL73_INTSEL4 (*((volatile unsigned int*)(0x42A23010UL))) +#define bM4_INTC_SEL73_INTSEL5 (*((volatile unsigned int*)(0x42A23014UL))) +#define bM4_INTC_SEL73_INTSEL6 (*((volatile unsigned int*)(0x42A23018UL))) +#define bM4_INTC_SEL73_INTSEL7 (*((volatile unsigned int*)(0x42A2301CUL))) +#define bM4_INTC_SEL73_INTSEL8 (*((volatile unsigned int*)(0x42A23020UL))) +#define bM4_INTC_SEL74_INTSEL0 (*((volatile unsigned int*)(0x42A23080UL))) +#define bM4_INTC_SEL74_INTSEL1 (*((volatile unsigned int*)(0x42A23084UL))) +#define bM4_INTC_SEL74_INTSEL2 (*((volatile unsigned int*)(0x42A23088UL))) +#define bM4_INTC_SEL74_INTSEL3 (*((volatile unsigned int*)(0x42A2308CUL))) +#define bM4_INTC_SEL74_INTSEL4 (*((volatile unsigned int*)(0x42A23090UL))) +#define bM4_INTC_SEL74_INTSEL5 (*((volatile unsigned int*)(0x42A23094UL))) +#define bM4_INTC_SEL74_INTSEL6 (*((volatile unsigned int*)(0x42A23098UL))) +#define bM4_INTC_SEL74_INTSEL7 (*((volatile unsigned int*)(0x42A2309CUL))) +#define bM4_INTC_SEL74_INTSEL8 (*((volatile unsigned int*)(0x42A230A0UL))) +#define bM4_INTC_SEL75_INTSEL0 (*((volatile unsigned int*)(0x42A23100UL))) +#define bM4_INTC_SEL75_INTSEL1 (*((volatile unsigned int*)(0x42A23104UL))) +#define bM4_INTC_SEL75_INTSEL2 (*((volatile unsigned int*)(0x42A23108UL))) +#define bM4_INTC_SEL75_INTSEL3 (*((volatile unsigned int*)(0x42A2310CUL))) +#define bM4_INTC_SEL75_INTSEL4 (*((volatile unsigned int*)(0x42A23110UL))) +#define bM4_INTC_SEL75_INTSEL5 (*((volatile unsigned int*)(0x42A23114UL))) +#define bM4_INTC_SEL75_INTSEL6 (*((volatile unsigned int*)(0x42A23118UL))) +#define bM4_INTC_SEL75_INTSEL7 (*((volatile unsigned int*)(0x42A2311CUL))) +#define bM4_INTC_SEL75_INTSEL8 (*((volatile unsigned int*)(0x42A23120UL))) +#define bM4_INTC_SEL76_INTSEL0 (*((volatile unsigned int*)(0x42A23180UL))) +#define bM4_INTC_SEL76_INTSEL1 (*((volatile unsigned int*)(0x42A23184UL))) +#define bM4_INTC_SEL76_INTSEL2 (*((volatile unsigned int*)(0x42A23188UL))) +#define bM4_INTC_SEL76_INTSEL3 (*((volatile unsigned int*)(0x42A2318CUL))) +#define bM4_INTC_SEL76_INTSEL4 (*((volatile unsigned int*)(0x42A23190UL))) +#define bM4_INTC_SEL76_INTSEL5 (*((volatile unsigned int*)(0x42A23194UL))) +#define bM4_INTC_SEL76_INTSEL6 (*((volatile unsigned int*)(0x42A23198UL))) +#define bM4_INTC_SEL76_INTSEL7 (*((volatile unsigned int*)(0x42A2319CUL))) +#define bM4_INTC_SEL76_INTSEL8 (*((volatile unsigned int*)(0x42A231A0UL))) +#define bM4_INTC_SEL77_INTSEL0 (*((volatile unsigned int*)(0x42A23200UL))) +#define bM4_INTC_SEL77_INTSEL1 (*((volatile unsigned int*)(0x42A23204UL))) +#define bM4_INTC_SEL77_INTSEL2 (*((volatile unsigned int*)(0x42A23208UL))) +#define bM4_INTC_SEL77_INTSEL3 (*((volatile unsigned int*)(0x42A2320CUL))) +#define bM4_INTC_SEL77_INTSEL4 (*((volatile unsigned int*)(0x42A23210UL))) +#define bM4_INTC_SEL77_INTSEL5 (*((volatile unsigned int*)(0x42A23214UL))) +#define bM4_INTC_SEL77_INTSEL6 (*((volatile unsigned int*)(0x42A23218UL))) +#define bM4_INTC_SEL77_INTSEL7 (*((volatile unsigned int*)(0x42A2321CUL))) +#define bM4_INTC_SEL77_INTSEL8 (*((volatile unsigned int*)(0x42A23220UL))) +#define bM4_INTC_SEL78_INTSEL0 (*((volatile unsigned int*)(0x42A23280UL))) +#define bM4_INTC_SEL78_INTSEL1 (*((volatile unsigned int*)(0x42A23284UL))) +#define bM4_INTC_SEL78_INTSEL2 (*((volatile unsigned int*)(0x42A23288UL))) +#define bM4_INTC_SEL78_INTSEL3 (*((volatile unsigned int*)(0x42A2328CUL))) +#define bM4_INTC_SEL78_INTSEL4 (*((volatile unsigned int*)(0x42A23290UL))) +#define bM4_INTC_SEL78_INTSEL5 (*((volatile unsigned int*)(0x42A23294UL))) +#define bM4_INTC_SEL78_INTSEL6 (*((volatile unsigned int*)(0x42A23298UL))) +#define bM4_INTC_SEL78_INTSEL7 (*((volatile unsigned int*)(0x42A2329CUL))) +#define bM4_INTC_SEL78_INTSEL8 (*((volatile unsigned int*)(0x42A232A0UL))) +#define bM4_INTC_SEL79_INTSEL0 (*((volatile unsigned int*)(0x42A23300UL))) +#define bM4_INTC_SEL79_INTSEL1 (*((volatile unsigned int*)(0x42A23304UL))) +#define bM4_INTC_SEL79_INTSEL2 (*((volatile unsigned int*)(0x42A23308UL))) +#define bM4_INTC_SEL79_INTSEL3 (*((volatile unsigned int*)(0x42A2330CUL))) +#define bM4_INTC_SEL79_INTSEL4 (*((volatile unsigned int*)(0x42A23310UL))) +#define bM4_INTC_SEL79_INTSEL5 (*((volatile unsigned int*)(0x42A23314UL))) +#define bM4_INTC_SEL79_INTSEL6 (*((volatile unsigned int*)(0x42A23318UL))) +#define bM4_INTC_SEL79_INTSEL7 (*((volatile unsigned int*)(0x42A2331CUL))) +#define bM4_INTC_SEL79_INTSEL8 (*((volatile unsigned int*)(0x42A23320UL))) +#define bM4_INTC_SEL80_INTSEL0 (*((volatile unsigned int*)(0x42A23380UL))) +#define bM4_INTC_SEL80_INTSEL1 (*((volatile unsigned int*)(0x42A23384UL))) +#define bM4_INTC_SEL80_INTSEL2 (*((volatile unsigned int*)(0x42A23388UL))) +#define bM4_INTC_SEL80_INTSEL3 (*((volatile unsigned int*)(0x42A2338CUL))) +#define bM4_INTC_SEL80_INTSEL4 (*((volatile unsigned int*)(0x42A23390UL))) +#define bM4_INTC_SEL80_INTSEL5 (*((volatile unsigned int*)(0x42A23394UL))) +#define bM4_INTC_SEL80_INTSEL6 (*((volatile unsigned int*)(0x42A23398UL))) +#define bM4_INTC_SEL80_INTSEL7 (*((volatile unsigned int*)(0x42A2339CUL))) +#define bM4_INTC_SEL80_INTSEL8 (*((volatile unsigned int*)(0x42A233A0UL))) +#define bM4_INTC_SEL81_INTSEL0 (*((volatile unsigned int*)(0x42A23400UL))) +#define bM4_INTC_SEL81_INTSEL1 (*((volatile unsigned int*)(0x42A23404UL))) +#define bM4_INTC_SEL81_INTSEL2 (*((volatile unsigned int*)(0x42A23408UL))) +#define bM4_INTC_SEL81_INTSEL3 (*((volatile unsigned int*)(0x42A2340CUL))) +#define bM4_INTC_SEL81_INTSEL4 (*((volatile unsigned int*)(0x42A23410UL))) +#define bM4_INTC_SEL81_INTSEL5 (*((volatile unsigned int*)(0x42A23414UL))) +#define bM4_INTC_SEL81_INTSEL6 (*((volatile unsigned int*)(0x42A23418UL))) +#define bM4_INTC_SEL81_INTSEL7 (*((volatile unsigned int*)(0x42A2341CUL))) +#define bM4_INTC_SEL81_INTSEL8 (*((volatile unsigned int*)(0x42A23420UL))) +#define bM4_INTC_SEL82_INTSEL0 (*((volatile unsigned int*)(0x42A23480UL))) +#define bM4_INTC_SEL82_INTSEL1 (*((volatile unsigned int*)(0x42A23484UL))) +#define bM4_INTC_SEL82_INTSEL2 (*((volatile unsigned int*)(0x42A23488UL))) +#define bM4_INTC_SEL82_INTSEL3 (*((volatile unsigned int*)(0x42A2348CUL))) +#define bM4_INTC_SEL82_INTSEL4 (*((volatile unsigned int*)(0x42A23490UL))) +#define bM4_INTC_SEL82_INTSEL5 (*((volatile unsigned int*)(0x42A23494UL))) +#define bM4_INTC_SEL82_INTSEL6 (*((volatile unsigned int*)(0x42A23498UL))) +#define bM4_INTC_SEL82_INTSEL7 (*((volatile unsigned int*)(0x42A2349CUL))) +#define bM4_INTC_SEL82_INTSEL8 (*((volatile unsigned int*)(0x42A234A0UL))) +#define bM4_INTC_SEL83_INTSEL0 (*((volatile unsigned int*)(0x42A23500UL))) +#define bM4_INTC_SEL83_INTSEL1 (*((volatile unsigned int*)(0x42A23504UL))) +#define bM4_INTC_SEL83_INTSEL2 (*((volatile unsigned int*)(0x42A23508UL))) +#define bM4_INTC_SEL83_INTSEL3 (*((volatile unsigned int*)(0x42A2350CUL))) +#define bM4_INTC_SEL83_INTSEL4 (*((volatile unsigned int*)(0x42A23510UL))) +#define bM4_INTC_SEL83_INTSEL5 (*((volatile unsigned int*)(0x42A23514UL))) +#define bM4_INTC_SEL83_INTSEL6 (*((volatile unsigned int*)(0x42A23518UL))) +#define bM4_INTC_SEL83_INTSEL7 (*((volatile unsigned int*)(0x42A2351CUL))) +#define bM4_INTC_SEL83_INTSEL8 (*((volatile unsigned int*)(0x42A23520UL))) +#define bM4_INTC_SEL84_INTSEL0 (*((volatile unsigned int*)(0x42A23580UL))) +#define bM4_INTC_SEL84_INTSEL1 (*((volatile unsigned int*)(0x42A23584UL))) +#define bM4_INTC_SEL84_INTSEL2 (*((volatile unsigned int*)(0x42A23588UL))) +#define bM4_INTC_SEL84_INTSEL3 (*((volatile unsigned int*)(0x42A2358CUL))) +#define bM4_INTC_SEL84_INTSEL4 (*((volatile unsigned int*)(0x42A23590UL))) +#define bM4_INTC_SEL84_INTSEL5 (*((volatile unsigned int*)(0x42A23594UL))) +#define bM4_INTC_SEL84_INTSEL6 (*((volatile unsigned int*)(0x42A23598UL))) +#define bM4_INTC_SEL84_INTSEL7 (*((volatile unsigned int*)(0x42A2359CUL))) +#define bM4_INTC_SEL84_INTSEL8 (*((volatile unsigned int*)(0x42A235A0UL))) +#define bM4_INTC_SEL85_INTSEL0 (*((volatile unsigned int*)(0x42A23600UL))) +#define bM4_INTC_SEL85_INTSEL1 (*((volatile unsigned int*)(0x42A23604UL))) +#define bM4_INTC_SEL85_INTSEL2 (*((volatile unsigned int*)(0x42A23608UL))) +#define bM4_INTC_SEL85_INTSEL3 (*((volatile unsigned int*)(0x42A2360CUL))) +#define bM4_INTC_SEL85_INTSEL4 (*((volatile unsigned int*)(0x42A23610UL))) +#define bM4_INTC_SEL85_INTSEL5 (*((volatile unsigned int*)(0x42A23614UL))) +#define bM4_INTC_SEL85_INTSEL6 (*((volatile unsigned int*)(0x42A23618UL))) +#define bM4_INTC_SEL85_INTSEL7 (*((volatile unsigned int*)(0x42A2361CUL))) +#define bM4_INTC_SEL85_INTSEL8 (*((volatile unsigned int*)(0x42A23620UL))) +#define bM4_INTC_SEL86_INTSEL0 (*((volatile unsigned int*)(0x42A23680UL))) +#define bM4_INTC_SEL86_INTSEL1 (*((volatile unsigned int*)(0x42A23684UL))) +#define bM4_INTC_SEL86_INTSEL2 (*((volatile unsigned int*)(0x42A23688UL))) +#define bM4_INTC_SEL86_INTSEL3 (*((volatile unsigned int*)(0x42A2368CUL))) +#define bM4_INTC_SEL86_INTSEL4 (*((volatile unsigned int*)(0x42A23690UL))) +#define bM4_INTC_SEL86_INTSEL5 (*((volatile unsigned int*)(0x42A23694UL))) +#define bM4_INTC_SEL86_INTSEL6 (*((volatile unsigned int*)(0x42A23698UL))) +#define bM4_INTC_SEL86_INTSEL7 (*((volatile unsigned int*)(0x42A2369CUL))) +#define bM4_INTC_SEL86_INTSEL8 (*((volatile unsigned int*)(0x42A236A0UL))) +#define bM4_INTC_SEL87_INTSEL0 (*((volatile unsigned int*)(0x42A23700UL))) +#define bM4_INTC_SEL87_INTSEL1 (*((volatile unsigned int*)(0x42A23704UL))) +#define bM4_INTC_SEL87_INTSEL2 (*((volatile unsigned int*)(0x42A23708UL))) +#define bM4_INTC_SEL87_INTSEL3 (*((volatile unsigned int*)(0x42A2370CUL))) +#define bM4_INTC_SEL87_INTSEL4 (*((volatile unsigned int*)(0x42A23710UL))) +#define bM4_INTC_SEL87_INTSEL5 (*((volatile unsigned int*)(0x42A23714UL))) +#define bM4_INTC_SEL87_INTSEL6 (*((volatile unsigned int*)(0x42A23718UL))) +#define bM4_INTC_SEL87_INTSEL7 (*((volatile unsigned int*)(0x42A2371CUL))) +#define bM4_INTC_SEL87_INTSEL8 (*((volatile unsigned int*)(0x42A23720UL))) +#define bM4_INTC_SEL88_INTSEL0 (*((volatile unsigned int*)(0x42A23780UL))) +#define bM4_INTC_SEL88_INTSEL1 (*((volatile unsigned int*)(0x42A23784UL))) +#define bM4_INTC_SEL88_INTSEL2 (*((volatile unsigned int*)(0x42A23788UL))) +#define bM4_INTC_SEL88_INTSEL3 (*((volatile unsigned int*)(0x42A2378CUL))) +#define bM4_INTC_SEL88_INTSEL4 (*((volatile unsigned int*)(0x42A23790UL))) +#define bM4_INTC_SEL88_INTSEL5 (*((volatile unsigned int*)(0x42A23794UL))) +#define bM4_INTC_SEL88_INTSEL6 (*((volatile unsigned int*)(0x42A23798UL))) +#define bM4_INTC_SEL88_INTSEL7 (*((volatile unsigned int*)(0x42A2379CUL))) +#define bM4_INTC_SEL88_INTSEL8 (*((volatile unsigned int*)(0x42A237A0UL))) +#define bM4_INTC_SEL89_INTSEL0 (*((volatile unsigned int*)(0x42A23800UL))) +#define bM4_INTC_SEL89_INTSEL1 (*((volatile unsigned int*)(0x42A23804UL))) +#define bM4_INTC_SEL89_INTSEL2 (*((volatile unsigned int*)(0x42A23808UL))) +#define bM4_INTC_SEL89_INTSEL3 (*((volatile unsigned int*)(0x42A2380CUL))) +#define bM4_INTC_SEL89_INTSEL4 (*((volatile unsigned int*)(0x42A23810UL))) +#define bM4_INTC_SEL89_INTSEL5 (*((volatile unsigned int*)(0x42A23814UL))) +#define bM4_INTC_SEL89_INTSEL6 (*((volatile unsigned int*)(0x42A23818UL))) +#define bM4_INTC_SEL89_INTSEL7 (*((volatile unsigned int*)(0x42A2381CUL))) +#define bM4_INTC_SEL89_INTSEL8 (*((volatile unsigned int*)(0x42A23820UL))) +#define bM4_INTC_SEL90_INTSEL0 (*((volatile unsigned int*)(0x42A23880UL))) +#define bM4_INTC_SEL90_INTSEL1 (*((volatile unsigned int*)(0x42A23884UL))) +#define bM4_INTC_SEL90_INTSEL2 (*((volatile unsigned int*)(0x42A23888UL))) +#define bM4_INTC_SEL90_INTSEL3 (*((volatile unsigned int*)(0x42A2388CUL))) +#define bM4_INTC_SEL90_INTSEL4 (*((volatile unsigned int*)(0x42A23890UL))) +#define bM4_INTC_SEL90_INTSEL5 (*((volatile unsigned int*)(0x42A23894UL))) +#define bM4_INTC_SEL90_INTSEL6 (*((volatile unsigned int*)(0x42A23898UL))) +#define bM4_INTC_SEL90_INTSEL7 (*((volatile unsigned int*)(0x42A2389CUL))) +#define bM4_INTC_SEL90_INTSEL8 (*((volatile unsigned int*)(0x42A238A0UL))) +#define bM4_INTC_SEL91_INTSEL0 (*((volatile unsigned int*)(0x42A23900UL))) +#define bM4_INTC_SEL91_INTSEL1 (*((volatile unsigned int*)(0x42A23904UL))) +#define bM4_INTC_SEL91_INTSEL2 (*((volatile unsigned int*)(0x42A23908UL))) +#define bM4_INTC_SEL91_INTSEL3 (*((volatile unsigned int*)(0x42A2390CUL))) +#define bM4_INTC_SEL91_INTSEL4 (*((volatile unsigned int*)(0x42A23910UL))) +#define bM4_INTC_SEL91_INTSEL5 (*((volatile unsigned int*)(0x42A23914UL))) +#define bM4_INTC_SEL91_INTSEL6 (*((volatile unsigned int*)(0x42A23918UL))) +#define bM4_INTC_SEL91_INTSEL7 (*((volatile unsigned int*)(0x42A2391CUL))) +#define bM4_INTC_SEL91_INTSEL8 (*((volatile unsigned int*)(0x42A23920UL))) +#define bM4_INTC_SEL92_INTSEL0 (*((volatile unsigned int*)(0x42A23980UL))) +#define bM4_INTC_SEL92_INTSEL1 (*((volatile unsigned int*)(0x42A23984UL))) +#define bM4_INTC_SEL92_INTSEL2 (*((volatile unsigned int*)(0x42A23988UL))) +#define bM4_INTC_SEL92_INTSEL3 (*((volatile unsigned int*)(0x42A2398CUL))) +#define bM4_INTC_SEL92_INTSEL4 (*((volatile unsigned int*)(0x42A23990UL))) +#define bM4_INTC_SEL92_INTSEL5 (*((volatile unsigned int*)(0x42A23994UL))) +#define bM4_INTC_SEL92_INTSEL6 (*((volatile unsigned int*)(0x42A23998UL))) +#define bM4_INTC_SEL92_INTSEL7 (*((volatile unsigned int*)(0x42A2399CUL))) +#define bM4_INTC_SEL92_INTSEL8 (*((volatile unsigned int*)(0x42A239A0UL))) +#define bM4_INTC_SEL93_INTSEL0 (*((volatile unsigned int*)(0x42A23A00UL))) +#define bM4_INTC_SEL93_INTSEL1 (*((volatile unsigned int*)(0x42A23A04UL))) +#define bM4_INTC_SEL93_INTSEL2 (*((volatile unsigned int*)(0x42A23A08UL))) +#define bM4_INTC_SEL93_INTSEL3 (*((volatile unsigned int*)(0x42A23A0CUL))) +#define bM4_INTC_SEL93_INTSEL4 (*((volatile unsigned int*)(0x42A23A10UL))) +#define bM4_INTC_SEL93_INTSEL5 (*((volatile unsigned int*)(0x42A23A14UL))) +#define bM4_INTC_SEL93_INTSEL6 (*((volatile unsigned int*)(0x42A23A18UL))) +#define bM4_INTC_SEL93_INTSEL7 (*((volatile unsigned int*)(0x42A23A1CUL))) +#define bM4_INTC_SEL93_INTSEL8 (*((volatile unsigned int*)(0x42A23A20UL))) +#define bM4_INTC_SEL94_INTSEL0 (*((volatile unsigned int*)(0x42A23A80UL))) +#define bM4_INTC_SEL94_INTSEL1 (*((volatile unsigned int*)(0x42A23A84UL))) +#define bM4_INTC_SEL94_INTSEL2 (*((volatile unsigned int*)(0x42A23A88UL))) +#define bM4_INTC_SEL94_INTSEL3 (*((volatile unsigned int*)(0x42A23A8CUL))) +#define bM4_INTC_SEL94_INTSEL4 (*((volatile unsigned int*)(0x42A23A90UL))) +#define bM4_INTC_SEL94_INTSEL5 (*((volatile unsigned int*)(0x42A23A94UL))) +#define bM4_INTC_SEL94_INTSEL6 (*((volatile unsigned int*)(0x42A23A98UL))) +#define bM4_INTC_SEL94_INTSEL7 (*((volatile unsigned int*)(0x42A23A9CUL))) +#define bM4_INTC_SEL94_INTSEL8 (*((volatile unsigned int*)(0x42A23AA0UL))) +#define bM4_INTC_SEL95_INTSEL0 (*((volatile unsigned int*)(0x42A23B00UL))) +#define bM4_INTC_SEL95_INTSEL1 (*((volatile unsigned int*)(0x42A23B04UL))) +#define bM4_INTC_SEL95_INTSEL2 (*((volatile unsigned int*)(0x42A23B08UL))) +#define bM4_INTC_SEL95_INTSEL3 (*((volatile unsigned int*)(0x42A23B0CUL))) +#define bM4_INTC_SEL95_INTSEL4 (*((volatile unsigned int*)(0x42A23B10UL))) +#define bM4_INTC_SEL95_INTSEL5 (*((volatile unsigned int*)(0x42A23B14UL))) +#define bM4_INTC_SEL95_INTSEL6 (*((volatile unsigned int*)(0x42A23B18UL))) +#define bM4_INTC_SEL95_INTSEL7 (*((volatile unsigned int*)(0x42A23B1CUL))) +#define bM4_INTC_SEL95_INTSEL8 (*((volatile unsigned int*)(0x42A23B20UL))) +#define bM4_INTC_SEL96_INTSEL0 (*((volatile unsigned int*)(0x42A23B80UL))) +#define bM4_INTC_SEL96_INTSEL1 (*((volatile unsigned int*)(0x42A23B84UL))) +#define bM4_INTC_SEL96_INTSEL2 (*((volatile unsigned int*)(0x42A23B88UL))) +#define bM4_INTC_SEL96_INTSEL3 (*((volatile unsigned int*)(0x42A23B8CUL))) +#define bM4_INTC_SEL96_INTSEL4 (*((volatile unsigned int*)(0x42A23B90UL))) +#define bM4_INTC_SEL96_INTSEL5 (*((volatile unsigned int*)(0x42A23B94UL))) +#define bM4_INTC_SEL96_INTSEL6 (*((volatile unsigned int*)(0x42A23B98UL))) +#define bM4_INTC_SEL96_INTSEL7 (*((volatile unsigned int*)(0x42A23B9CUL))) +#define bM4_INTC_SEL96_INTSEL8 (*((volatile unsigned int*)(0x42A23BA0UL))) +#define bM4_INTC_SEL97_INTSEL0 (*((volatile unsigned int*)(0x42A23C00UL))) +#define bM4_INTC_SEL97_INTSEL1 (*((volatile unsigned int*)(0x42A23C04UL))) +#define bM4_INTC_SEL97_INTSEL2 (*((volatile unsigned int*)(0x42A23C08UL))) +#define bM4_INTC_SEL97_INTSEL3 (*((volatile unsigned int*)(0x42A23C0CUL))) +#define bM4_INTC_SEL97_INTSEL4 (*((volatile unsigned int*)(0x42A23C10UL))) +#define bM4_INTC_SEL97_INTSEL5 (*((volatile unsigned int*)(0x42A23C14UL))) +#define bM4_INTC_SEL97_INTSEL6 (*((volatile unsigned int*)(0x42A23C18UL))) +#define bM4_INTC_SEL97_INTSEL7 (*((volatile unsigned int*)(0x42A23C1CUL))) +#define bM4_INTC_SEL97_INTSEL8 (*((volatile unsigned int*)(0x42A23C20UL))) +#define bM4_INTC_SEL98_INTSEL0 (*((volatile unsigned int*)(0x42A23C80UL))) +#define bM4_INTC_SEL98_INTSEL1 (*((volatile unsigned int*)(0x42A23C84UL))) +#define bM4_INTC_SEL98_INTSEL2 (*((volatile unsigned int*)(0x42A23C88UL))) +#define bM4_INTC_SEL98_INTSEL3 (*((volatile unsigned int*)(0x42A23C8CUL))) +#define bM4_INTC_SEL98_INTSEL4 (*((volatile unsigned int*)(0x42A23C90UL))) +#define bM4_INTC_SEL98_INTSEL5 (*((volatile unsigned int*)(0x42A23C94UL))) +#define bM4_INTC_SEL98_INTSEL6 (*((volatile unsigned int*)(0x42A23C98UL))) +#define bM4_INTC_SEL98_INTSEL7 (*((volatile unsigned int*)(0x42A23C9CUL))) +#define bM4_INTC_SEL98_INTSEL8 (*((volatile unsigned int*)(0x42A23CA0UL))) +#define bM4_INTC_SEL99_INTSEL0 (*((volatile unsigned int*)(0x42A23D00UL))) +#define bM4_INTC_SEL99_INTSEL1 (*((volatile unsigned int*)(0x42A23D04UL))) +#define bM4_INTC_SEL99_INTSEL2 (*((volatile unsigned int*)(0x42A23D08UL))) +#define bM4_INTC_SEL99_INTSEL3 (*((volatile unsigned int*)(0x42A23D0CUL))) +#define bM4_INTC_SEL99_INTSEL4 (*((volatile unsigned int*)(0x42A23D10UL))) +#define bM4_INTC_SEL99_INTSEL5 (*((volatile unsigned int*)(0x42A23D14UL))) +#define bM4_INTC_SEL99_INTSEL6 (*((volatile unsigned int*)(0x42A23D18UL))) +#define bM4_INTC_SEL99_INTSEL7 (*((volatile unsigned int*)(0x42A23D1CUL))) +#define bM4_INTC_SEL99_INTSEL8 (*((volatile unsigned int*)(0x42A23D20UL))) +#define bM4_INTC_SEL100_INTSEL0 (*((volatile unsigned int*)(0x42A23D80UL))) +#define bM4_INTC_SEL100_INTSEL1 (*((volatile unsigned int*)(0x42A23D84UL))) +#define bM4_INTC_SEL100_INTSEL2 (*((volatile unsigned int*)(0x42A23D88UL))) +#define bM4_INTC_SEL100_INTSEL3 (*((volatile unsigned int*)(0x42A23D8CUL))) +#define bM4_INTC_SEL100_INTSEL4 (*((volatile unsigned int*)(0x42A23D90UL))) +#define bM4_INTC_SEL100_INTSEL5 (*((volatile unsigned int*)(0x42A23D94UL))) +#define bM4_INTC_SEL100_INTSEL6 (*((volatile unsigned int*)(0x42A23D98UL))) +#define bM4_INTC_SEL100_INTSEL7 (*((volatile unsigned int*)(0x42A23D9CUL))) +#define bM4_INTC_SEL100_INTSEL8 (*((volatile unsigned int*)(0x42A23DA0UL))) +#define bM4_INTC_SEL101_INTSEL0 (*((volatile unsigned int*)(0x42A23E00UL))) +#define bM4_INTC_SEL101_INTSEL1 (*((volatile unsigned int*)(0x42A23E04UL))) +#define bM4_INTC_SEL101_INTSEL2 (*((volatile unsigned int*)(0x42A23E08UL))) +#define bM4_INTC_SEL101_INTSEL3 (*((volatile unsigned int*)(0x42A23E0CUL))) +#define bM4_INTC_SEL101_INTSEL4 (*((volatile unsigned int*)(0x42A23E10UL))) +#define bM4_INTC_SEL101_INTSEL5 (*((volatile unsigned int*)(0x42A23E14UL))) +#define bM4_INTC_SEL101_INTSEL6 (*((volatile unsigned int*)(0x42A23E18UL))) +#define bM4_INTC_SEL101_INTSEL7 (*((volatile unsigned int*)(0x42A23E1CUL))) +#define bM4_INTC_SEL101_INTSEL8 (*((volatile unsigned int*)(0x42A23E20UL))) +#define bM4_INTC_SEL102_INTSEL0 (*((volatile unsigned int*)(0x42A23E80UL))) +#define bM4_INTC_SEL102_INTSEL1 (*((volatile unsigned int*)(0x42A23E84UL))) +#define bM4_INTC_SEL102_INTSEL2 (*((volatile unsigned int*)(0x42A23E88UL))) +#define bM4_INTC_SEL102_INTSEL3 (*((volatile unsigned int*)(0x42A23E8CUL))) +#define bM4_INTC_SEL102_INTSEL4 (*((volatile unsigned int*)(0x42A23E90UL))) +#define bM4_INTC_SEL102_INTSEL5 (*((volatile unsigned int*)(0x42A23E94UL))) +#define bM4_INTC_SEL102_INTSEL6 (*((volatile unsigned int*)(0x42A23E98UL))) +#define bM4_INTC_SEL102_INTSEL7 (*((volatile unsigned int*)(0x42A23E9CUL))) +#define bM4_INTC_SEL102_INTSEL8 (*((volatile unsigned int*)(0x42A23EA0UL))) +#define bM4_INTC_SEL103_INTSEL0 (*((volatile unsigned int*)(0x42A23F00UL))) +#define bM4_INTC_SEL103_INTSEL1 (*((volatile unsigned int*)(0x42A23F04UL))) +#define bM4_INTC_SEL103_INTSEL2 (*((volatile unsigned int*)(0x42A23F08UL))) +#define bM4_INTC_SEL103_INTSEL3 (*((volatile unsigned int*)(0x42A23F0CUL))) +#define bM4_INTC_SEL103_INTSEL4 (*((volatile unsigned int*)(0x42A23F10UL))) +#define bM4_INTC_SEL103_INTSEL5 (*((volatile unsigned int*)(0x42A23F14UL))) +#define bM4_INTC_SEL103_INTSEL6 (*((volatile unsigned int*)(0x42A23F18UL))) +#define bM4_INTC_SEL103_INTSEL7 (*((volatile unsigned int*)(0x42A23F1CUL))) +#define bM4_INTC_SEL103_INTSEL8 (*((volatile unsigned int*)(0x42A23F20UL))) +#define bM4_INTC_SEL104_INTSEL0 (*((volatile unsigned int*)(0x42A23F80UL))) +#define bM4_INTC_SEL104_INTSEL1 (*((volatile unsigned int*)(0x42A23F84UL))) +#define bM4_INTC_SEL104_INTSEL2 (*((volatile unsigned int*)(0x42A23F88UL))) +#define bM4_INTC_SEL104_INTSEL3 (*((volatile unsigned int*)(0x42A23F8CUL))) +#define bM4_INTC_SEL104_INTSEL4 (*((volatile unsigned int*)(0x42A23F90UL))) +#define bM4_INTC_SEL104_INTSEL5 (*((volatile unsigned int*)(0x42A23F94UL))) +#define bM4_INTC_SEL104_INTSEL6 (*((volatile unsigned int*)(0x42A23F98UL))) +#define bM4_INTC_SEL104_INTSEL7 (*((volatile unsigned int*)(0x42A23F9CUL))) +#define bM4_INTC_SEL104_INTSEL8 (*((volatile unsigned int*)(0x42A23FA0UL))) +#define bM4_INTC_SEL105_INTSEL0 (*((volatile unsigned int*)(0x42A24000UL))) +#define bM4_INTC_SEL105_INTSEL1 (*((volatile unsigned int*)(0x42A24004UL))) +#define bM4_INTC_SEL105_INTSEL2 (*((volatile unsigned int*)(0x42A24008UL))) +#define bM4_INTC_SEL105_INTSEL3 (*((volatile unsigned int*)(0x42A2400CUL))) +#define bM4_INTC_SEL105_INTSEL4 (*((volatile unsigned int*)(0x42A24010UL))) +#define bM4_INTC_SEL105_INTSEL5 (*((volatile unsigned int*)(0x42A24014UL))) +#define bM4_INTC_SEL105_INTSEL6 (*((volatile unsigned int*)(0x42A24018UL))) +#define bM4_INTC_SEL105_INTSEL7 (*((volatile unsigned int*)(0x42A2401CUL))) +#define bM4_INTC_SEL105_INTSEL8 (*((volatile unsigned int*)(0x42A24020UL))) +#define bM4_INTC_SEL106_INTSEL0 (*((volatile unsigned int*)(0x42A24080UL))) +#define bM4_INTC_SEL106_INTSEL1 (*((volatile unsigned int*)(0x42A24084UL))) +#define bM4_INTC_SEL106_INTSEL2 (*((volatile unsigned int*)(0x42A24088UL))) +#define bM4_INTC_SEL106_INTSEL3 (*((volatile unsigned int*)(0x42A2408CUL))) +#define bM4_INTC_SEL106_INTSEL4 (*((volatile unsigned int*)(0x42A24090UL))) +#define bM4_INTC_SEL106_INTSEL5 (*((volatile unsigned int*)(0x42A24094UL))) +#define bM4_INTC_SEL106_INTSEL6 (*((volatile unsigned int*)(0x42A24098UL))) +#define bM4_INTC_SEL106_INTSEL7 (*((volatile unsigned int*)(0x42A2409CUL))) +#define bM4_INTC_SEL106_INTSEL8 (*((volatile unsigned int*)(0x42A240A0UL))) +#define bM4_INTC_SEL107_INTSEL0 (*((volatile unsigned int*)(0x42A24100UL))) +#define bM4_INTC_SEL107_INTSEL1 (*((volatile unsigned int*)(0x42A24104UL))) +#define bM4_INTC_SEL107_INTSEL2 (*((volatile unsigned int*)(0x42A24108UL))) +#define bM4_INTC_SEL107_INTSEL3 (*((volatile unsigned int*)(0x42A2410CUL))) +#define bM4_INTC_SEL107_INTSEL4 (*((volatile unsigned int*)(0x42A24110UL))) +#define bM4_INTC_SEL107_INTSEL5 (*((volatile unsigned int*)(0x42A24114UL))) +#define bM4_INTC_SEL107_INTSEL6 (*((volatile unsigned int*)(0x42A24118UL))) +#define bM4_INTC_SEL107_INTSEL7 (*((volatile unsigned int*)(0x42A2411CUL))) +#define bM4_INTC_SEL107_INTSEL8 (*((volatile unsigned int*)(0x42A24120UL))) +#define bM4_INTC_SEL108_INTSEL0 (*((volatile unsigned int*)(0x42A24180UL))) +#define bM4_INTC_SEL108_INTSEL1 (*((volatile unsigned int*)(0x42A24184UL))) +#define bM4_INTC_SEL108_INTSEL2 (*((volatile unsigned int*)(0x42A24188UL))) +#define bM4_INTC_SEL108_INTSEL3 (*((volatile unsigned int*)(0x42A2418CUL))) +#define bM4_INTC_SEL108_INTSEL4 (*((volatile unsigned int*)(0x42A24190UL))) +#define bM4_INTC_SEL108_INTSEL5 (*((volatile unsigned int*)(0x42A24194UL))) +#define bM4_INTC_SEL108_INTSEL6 (*((volatile unsigned int*)(0x42A24198UL))) +#define bM4_INTC_SEL108_INTSEL7 (*((volatile unsigned int*)(0x42A2419CUL))) +#define bM4_INTC_SEL108_INTSEL8 (*((volatile unsigned int*)(0x42A241A0UL))) +#define bM4_INTC_SEL109_INTSEL0 (*((volatile unsigned int*)(0x42A24200UL))) +#define bM4_INTC_SEL109_INTSEL1 (*((volatile unsigned int*)(0x42A24204UL))) +#define bM4_INTC_SEL109_INTSEL2 (*((volatile unsigned int*)(0x42A24208UL))) +#define bM4_INTC_SEL109_INTSEL3 (*((volatile unsigned int*)(0x42A2420CUL))) +#define bM4_INTC_SEL109_INTSEL4 (*((volatile unsigned int*)(0x42A24210UL))) +#define bM4_INTC_SEL109_INTSEL5 (*((volatile unsigned int*)(0x42A24214UL))) +#define bM4_INTC_SEL109_INTSEL6 (*((volatile unsigned int*)(0x42A24218UL))) +#define bM4_INTC_SEL109_INTSEL7 (*((volatile unsigned int*)(0x42A2421CUL))) +#define bM4_INTC_SEL109_INTSEL8 (*((volatile unsigned int*)(0x42A24220UL))) +#define bM4_INTC_SEL110_INTSEL0 (*((volatile unsigned int*)(0x42A24280UL))) +#define bM4_INTC_SEL110_INTSEL1 (*((volatile unsigned int*)(0x42A24284UL))) +#define bM4_INTC_SEL110_INTSEL2 (*((volatile unsigned int*)(0x42A24288UL))) +#define bM4_INTC_SEL110_INTSEL3 (*((volatile unsigned int*)(0x42A2428CUL))) +#define bM4_INTC_SEL110_INTSEL4 (*((volatile unsigned int*)(0x42A24290UL))) +#define bM4_INTC_SEL110_INTSEL5 (*((volatile unsigned int*)(0x42A24294UL))) +#define bM4_INTC_SEL110_INTSEL6 (*((volatile unsigned int*)(0x42A24298UL))) +#define bM4_INTC_SEL110_INTSEL7 (*((volatile unsigned int*)(0x42A2429CUL))) +#define bM4_INTC_SEL110_INTSEL8 (*((volatile unsigned int*)(0x42A242A0UL))) +#define bM4_INTC_SEL111_INTSEL0 (*((volatile unsigned int*)(0x42A24300UL))) +#define bM4_INTC_SEL111_INTSEL1 (*((volatile unsigned int*)(0x42A24304UL))) +#define bM4_INTC_SEL111_INTSEL2 (*((volatile unsigned int*)(0x42A24308UL))) +#define bM4_INTC_SEL111_INTSEL3 (*((volatile unsigned int*)(0x42A2430CUL))) +#define bM4_INTC_SEL111_INTSEL4 (*((volatile unsigned int*)(0x42A24310UL))) +#define bM4_INTC_SEL111_INTSEL5 (*((volatile unsigned int*)(0x42A24314UL))) +#define bM4_INTC_SEL111_INTSEL6 (*((volatile unsigned int*)(0x42A24318UL))) +#define bM4_INTC_SEL111_INTSEL7 (*((volatile unsigned int*)(0x42A2431CUL))) +#define bM4_INTC_SEL111_INTSEL8 (*((volatile unsigned int*)(0x42A24320UL))) +#define bM4_INTC_SEL112_INTSEL0 (*((volatile unsigned int*)(0x42A24380UL))) +#define bM4_INTC_SEL112_INTSEL1 (*((volatile unsigned int*)(0x42A24384UL))) +#define bM4_INTC_SEL112_INTSEL2 (*((volatile unsigned int*)(0x42A24388UL))) +#define bM4_INTC_SEL112_INTSEL3 (*((volatile unsigned int*)(0x42A2438CUL))) +#define bM4_INTC_SEL112_INTSEL4 (*((volatile unsigned int*)(0x42A24390UL))) +#define bM4_INTC_SEL112_INTSEL5 (*((volatile unsigned int*)(0x42A24394UL))) +#define bM4_INTC_SEL112_INTSEL6 (*((volatile unsigned int*)(0x42A24398UL))) +#define bM4_INTC_SEL112_INTSEL7 (*((volatile unsigned int*)(0x42A2439CUL))) +#define bM4_INTC_SEL112_INTSEL8 (*((volatile unsigned int*)(0x42A243A0UL))) +#define bM4_INTC_SEL113_INTSEL0 (*((volatile unsigned int*)(0x42A24400UL))) +#define bM4_INTC_SEL113_INTSEL1 (*((volatile unsigned int*)(0x42A24404UL))) +#define bM4_INTC_SEL113_INTSEL2 (*((volatile unsigned int*)(0x42A24408UL))) +#define bM4_INTC_SEL113_INTSEL3 (*((volatile unsigned int*)(0x42A2440CUL))) +#define bM4_INTC_SEL113_INTSEL4 (*((volatile unsigned int*)(0x42A24410UL))) +#define bM4_INTC_SEL113_INTSEL5 (*((volatile unsigned int*)(0x42A24414UL))) +#define bM4_INTC_SEL113_INTSEL6 (*((volatile unsigned int*)(0x42A24418UL))) +#define bM4_INTC_SEL113_INTSEL7 (*((volatile unsigned int*)(0x42A2441CUL))) +#define bM4_INTC_SEL113_INTSEL8 (*((volatile unsigned int*)(0x42A24420UL))) +#define bM4_INTC_SEL114_INTSEL0 (*((volatile unsigned int*)(0x42A24480UL))) +#define bM4_INTC_SEL114_INTSEL1 (*((volatile unsigned int*)(0x42A24484UL))) +#define bM4_INTC_SEL114_INTSEL2 (*((volatile unsigned int*)(0x42A24488UL))) +#define bM4_INTC_SEL114_INTSEL3 (*((volatile unsigned int*)(0x42A2448CUL))) +#define bM4_INTC_SEL114_INTSEL4 (*((volatile unsigned int*)(0x42A24490UL))) +#define bM4_INTC_SEL114_INTSEL5 (*((volatile unsigned int*)(0x42A24494UL))) +#define bM4_INTC_SEL114_INTSEL6 (*((volatile unsigned int*)(0x42A24498UL))) +#define bM4_INTC_SEL114_INTSEL7 (*((volatile unsigned int*)(0x42A2449CUL))) +#define bM4_INTC_SEL114_INTSEL8 (*((volatile unsigned int*)(0x42A244A0UL))) +#define bM4_INTC_SEL115_INTSEL0 (*((volatile unsigned int*)(0x42A24500UL))) +#define bM4_INTC_SEL115_INTSEL1 (*((volatile unsigned int*)(0x42A24504UL))) +#define bM4_INTC_SEL115_INTSEL2 (*((volatile unsigned int*)(0x42A24508UL))) +#define bM4_INTC_SEL115_INTSEL3 (*((volatile unsigned int*)(0x42A2450CUL))) +#define bM4_INTC_SEL115_INTSEL4 (*((volatile unsigned int*)(0x42A24510UL))) +#define bM4_INTC_SEL115_INTSEL5 (*((volatile unsigned int*)(0x42A24514UL))) +#define bM4_INTC_SEL115_INTSEL6 (*((volatile unsigned int*)(0x42A24518UL))) +#define bM4_INTC_SEL115_INTSEL7 (*((volatile unsigned int*)(0x42A2451CUL))) +#define bM4_INTC_SEL115_INTSEL8 (*((volatile unsigned int*)(0x42A24520UL))) +#define bM4_INTC_SEL116_INTSEL0 (*((volatile unsigned int*)(0x42A24580UL))) +#define bM4_INTC_SEL116_INTSEL1 (*((volatile unsigned int*)(0x42A24584UL))) +#define bM4_INTC_SEL116_INTSEL2 (*((volatile unsigned int*)(0x42A24588UL))) +#define bM4_INTC_SEL116_INTSEL3 (*((volatile unsigned int*)(0x42A2458CUL))) +#define bM4_INTC_SEL116_INTSEL4 (*((volatile unsigned int*)(0x42A24590UL))) +#define bM4_INTC_SEL116_INTSEL5 (*((volatile unsigned int*)(0x42A24594UL))) +#define bM4_INTC_SEL116_INTSEL6 (*((volatile unsigned int*)(0x42A24598UL))) +#define bM4_INTC_SEL116_INTSEL7 (*((volatile unsigned int*)(0x42A2459CUL))) +#define bM4_INTC_SEL116_INTSEL8 (*((volatile unsigned int*)(0x42A245A0UL))) +#define bM4_INTC_SEL117_INTSEL0 (*((volatile unsigned int*)(0x42A24600UL))) +#define bM4_INTC_SEL117_INTSEL1 (*((volatile unsigned int*)(0x42A24604UL))) +#define bM4_INTC_SEL117_INTSEL2 (*((volatile unsigned int*)(0x42A24608UL))) +#define bM4_INTC_SEL117_INTSEL3 (*((volatile unsigned int*)(0x42A2460CUL))) +#define bM4_INTC_SEL117_INTSEL4 (*((volatile unsigned int*)(0x42A24610UL))) +#define bM4_INTC_SEL117_INTSEL5 (*((volatile unsigned int*)(0x42A24614UL))) +#define bM4_INTC_SEL117_INTSEL6 (*((volatile unsigned int*)(0x42A24618UL))) +#define bM4_INTC_SEL117_INTSEL7 (*((volatile unsigned int*)(0x42A2461CUL))) +#define bM4_INTC_SEL117_INTSEL8 (*((volatile unsigned int*)(0x42A24620UL))) +#define bM4_INTC_SEL118_INTSEL0 (*((volatile unsigned int*)(0x42A24680UL))) +#define bM4_INTC_SEL118_INTSEL1 (*((volatile unsigned int*)(0x42A24684UL))) +#define bM4_INTC_SEL118_INTSEL2 (*((volatile unsigned int*)(0x42A24688UL))) +#define bM4_INTC_SEL118_INTSEL3 (*((volatile unsigned int*)(0x42A2468CUL))) +#define bM4_INTC_SEL118_INTSEL4 (*((volatile unsigned int*)(0x42A24690UL))) +#define bM4_INTC_SEL118_INTSEL5 (*((volatile unsigned int*)(0x42A24694UL))) +#define bM4_INTC_SEL118_INTSEL6 (*((volatile unsigned int*)(0x42A24698UL))) +#define bM4_INTC_SEL118_INTSEL7 (*((volatile unsigned int*)(0x42A2469CUL))) +#define bM4_INTC_SEL118_INTSEL8 (*((volatile unsigned int*)(0x42A246A0UL))) +#define bM4_INTC_SEL119_INTSEL0 (*((volatile unsigned int*)(0x42A24700UL))) +#define bM4_INTC_SEL119_INTSEL1 (*((volatile unsigned int*)(0x42A24704UL))) +#define bM4_INTC_SEL119_INTSEL2 (*((volatile unsigned int*)(0x42A24708UL))) +#define bM4_INTC_SEL119_INTSEL3 (*((volatile unsigned int*)(0x42A2470CUL))) +#define bM4_INTC_SEL119_INTSEL4 (*((volatile unsigned int*)(0x42A24710UL))) +#define bM4_INTC_SEL119_INTSEL5 (*((volatile unsigned int*)(0x42A24714UL))) +#define bM4_INTC_SEL119_INTSEL6 (*((volatile unsigned int*)(0x42A24718UL))) +#define bM4_INTC_SEL119_INTSEL7 (*((volatile unsigned int*)(0x42A2471CUL))) +#define bM4_INTC_SEL119_INTSEL8 (*((volatile unsigned int*)(0x42A24720UL))) +#define bM4_INTC_SEL120_INTSEL0 (*((volatile unsigned int*)(0x42A24780UL))) +#define bM4_INTC_SEL120_INTSEL1 (*((volatile unsigned int*)(0x42A24784UL))) +#define bM4_INTC_SEL120_INTSEL2 (*((volatile unsigned int*)(0x42A24788UL))) +#define bM4_INTC_SEL120_INTSEL3 (*((volatile unsigned int*)(0x42A2478CUL))) +#define bM4_INTC_SEL120_INTSEL4 (*((volatile unsigned int*)(0x42A24790UL))) +#define bM4_INTC_SEL120_INTSEL5 (*((volatile unsigned int*)(0x42A24794UL))) +#define bM4_INTC_SEL120_INTSEL6 (*((volatile unsigned int*)(0x42A24798UL))) +#define bM4_INTC_SEL120_INTSEL7 (*((volatile unsigned int*)(0x42A2479CUL))) +#define bM4_INTC_SEL120_INTSEL8 (*((volatile unsigned int*)(0x42A247A0UL))) +#define bM4_INTC_SEL121_INTSEL0 (*((volatile unsigned int*)(0x42A24800UL))) +#define bM4_INTC_SEL121_INTSEL1 (*((volatile unsigned int*)(0x42A24804UL))) +#define bM4_INTC_SEL121_INTSEL2 (*((volatile unsigned int*)(0x42A24808UL))) +#define bM4_INTC_SEL121_INTSEL3 (*((volatile unsigned int*)(0x42A2480CUL))) +#define bM4_INTC_SEL121_INTSEL4 (*((volatile unsigned int*)(0x42A24810UL))) +#define bM4_INTC_SEL121_INTSEL5 (*((volatile unsigned int*)(0x42A24814UL))) +#define bM4_INTC_SEL121_INTSEL6 (*((volatile unsigned int*)(0x42A24818UL))) +#define bM4_INTC_SEL121_INTSEL7 (*((volatile unsigned int*)(0x42A2481CUL))) +#define bM4_INTC_SEL121_INTSEL8 (*((volatile unsigned int*)(0x42A24820UL))) +#define bM4_INTC_SEL122_INTSEL0 (*((volatile unsigned int*)(0x42A24880UL))) +#define bM4_INTC_SEL122_INTSEL1 (*((volatile unsigned int*)(0x42A24884UL))) +#define bM4_INTC_SEL122_INTSEL2 (*((volatile unsigned int*)(0x42A24888UL))) +#define bM4_INTC_SEL122_INTSEL3 (*((volatile unsigned int*)(0x42A2488CUL))) +#define bM4_INTC_SEL122_INTSEL4 (*((volatile unsigned int*)(0x42A24890UL))) +#define bM4_INTC_SEL122_INTSEL5 (*((volatile unsigned int*)(0x42A24894UL))) +#define bM4_INTC_SEL122_INTSEL6 (*((volatile unsigned int*)(0x42A24898UL))) +#define bM4_INTC_SEL122_INTSEL7 (*((volatile unsigned int*)(0x42A2489CUL))) +#define bM4_INTC_SEL122_INTSEL8 (*((volatile unsigned int*)(0x42A248A0UL))) +#define bM4_INTC_SEL123_INTSEL0 (*((volatile unsigned int*)(0x42A24900UL))) +#define bM4_INTC_SEL123_INTSEL1 (*((volatile unsigned int*)(0x42A24904UL))) +#define bM4_INTC_SEL123_INTSEL2 (*((volatile unsigned int*)(0x42A24908UL))) +#define bM4_INTC_SEL123_INTSEL3 (*((volatile unsigned int*)(0x42A2490CUL))) +#define bM4_INTC_SEL123_INTSEL4 (*((volatile unsigned int*)(0x42A24910UL))) +#define bM4_INTC_SEL123_INTSEL5 (*((volatile unsigned int*)(0x42A24914UL))) +#define bM4_INTC_SEL123_INTSEL6 (*((volatile unsigned int*)(0x42A24918UL))) +#define bM4_INTC_SEL123_INTSEL7 (*((volatile unsigned int*)(0x42A2491CUL))) +#define bM4_INTC_SEL123_INTSEL8 (*((volatile unsigned int*)(0x42A24920UL))) +#define bM4_INTC_SEL124_INTSEL0 (*((volatile unsigned int*)(0x42A24980UL))) +#define bM4_INTC_SEL124_INTSEL1 (*((volatile unsigned int*)(0x42A24984UL))) +#define bM4_INTC_SEL124_INTSEL2 (*((volatile unsigned int*)(0x42A24988UL))) +#define bM4_INTC_SEL124_INTSEL3 (*((volatile unsigned int*)(0x42A2498CUL))) +#define bM4_INTC_SEL124_INTSEL4 (*((volatile unsigned int*)(0x42A24990UL))) +#define bM4_INTC_SEL124_INTSEL5 (*((volatile unsigned int*)(0x42A24994UL))) +#define bM4_INTC_SEL124_INTSEL6 (*((volatile unsigned int*)(0x42A24998UL))) +#define bM4_INTC_SEL124_INTSEL7 (*((volatile unsigned int*)(0x42A2499CUL))) +#define bM4_INTC_SEL124_INTSEL8 (*((volatile unsigned int*)(0x42A249A0UL))) +#define bM4_INTC_SEL125_INTSEL0 (*((volatile unsigned int*)(0x42A24A00UL))) +#define bM4_INTC_SEL125_INTSEL1 (*((volatile unsigned int*)(0x42A24A04UL))) +#define bM4_INTC_SEL125_INTSEL2 (*((volatile unsigned int*)(0x42A24A08UL))) +#define bM4_INTC_SEL125_INTSEL3 (*((volatile unsigned int*)(0x42A24A0CUL))) +#define bM4_INTC_SEL125_INTSEL4 (*((volatile unsigned int*)(0x42A24A10UL))) +#define bM4_INTC_SEL125_INTSEL5 (*((volatile unsigned int*)(0x42A24A14UL))) +#define bM4_INTC_SEL125_INTSEL6 (*((volatile unsigned int*)(0x42A24A18UL))) +#define bM4_INTC_SEL125_INTSEL7 (*((volatile unsigned int*)(0x42A24A1CUL))) +#define bM4_INTC_SEL125_INTSEL8 (*((volatile unsigned int*)(0x42A24A20UL))) +#define bM4_INTC_SEL126_INTSEL0 (*((volatile unsigned int*)(0x42A24A80UL))) +#define bM4_INTC_SEL126_INTSEL1 (*((volatile unsigned int*)(0x42A24A84UL))) +#define bM4_INTC_SEL126_INTSEL2 (*((volatile unsigned int*)(0x42A24A88UL))) +#define bM4_INTC_SEL126_INTSEL3 (*((volatile unsigned int*)(0x42A24A8CUL))) +#define bM4_INTC_SEL126_INTSEL4 (*((volatile unsigned int*)(0x42A24A90UL))) +#define bM4_INTC_SEL126_INTSEL5 (*((volatile unsigned int*)(0x42A24A94UL))) +#define bM4_INTC_SEL126_INTSEL6 (*((volatile unsigned int*)(0x42A24A98UL))) +#define bM4_INTC_SEL126_INTSEL7 (*((volatile unsigned int*)(0x42A24A9CUL))) +#define bM4_INTC_SEL126_INTSEL8 (*((volatile unsigned int*)(0x42A24AA0UL))) +#define bM4_INTC_SEL127_INTSEL0 (*((volatile unsigned int*)(0x42A24B00UL))) +#define bM4_INTC_SEL127_INTSEL1 (*((volatile unsigned int*)(0x42A24B04UL))) +#define bM4_INTC_SEL127_INTSEL2 (*((volatile unsigned int*)(0x42A24B08UL))) +#define bM4_INTC_SEL127_INTSEL3 (*((volatile unsigned int*)(0x42A24B0CUL))) +#define bM4_INTC_SEL127_INTSEL4 (*((volatile unsigned int*)(0x42A24B10UL))) +#define bM4_INTC_SEL127_INTSEL5 (*((volatile unsigned int*)(0x42A24B14UL))) +#define bM4_INTC_SEL127_INTSEL6 (*((volatile unsigned int*)(0x42A24B18UL))) +#define bM4_INTC_SEL127_INTSEL7 (*((volatile unsigned int*)(0x42A24B1CUL))) +#define bM4_INTC_SEL127_INTSEL8 (*((volatile unsigned int*)(0x42A24B20UL))) +#define bM4_INTC_VSSEL128_VSEL0 (*((volatile unsigned int*)(0x42A24B80UL))) +#define bM4_INTC_VSSEL128_VSEL1 (*((volatile unsigned int*)(0x42A24B84UL))) +#define bM4_INTC_VSSEL128_VSEL2 (*((volatile unsigned int*)(0x42A24B88UL))) +#define bM4_INTC_VSSEL128_VSEL3 (*((volatile unsigned int*)(0x42A24B8CUL))) +#define bM4_INTC_VSSEL128_VSEL4 (*((volatile unsigned int*)(0x42A24B90UL))) +#define bM4_INTC_VSSEL128_VSEL5 (*((volatile unsigned int*)(0x42A24B94UL))) +#define bM4_INTC_VSSEL128_VSEL6 (*((volatile unsigned int*)(0x42A24B98UL))) +#define bM4_INTC_VSSEL128_VSEL7 (*((volatile unsigned int*)(0x42A24B9CUL))) +#define bM4_INTC_VSSEL128_VSEL8 (*((volatile unsigned int*)(0x42A24BA0UL))) +#define bM4_INTC_VSSEL128_VSEL9 (*((volatile unsigned int*)(0x42A24BA4UL))) +#define bM4_INTC_VSSEL128_VSEL10 (*((volatile unsigned int*)(0x42A24BA8UL))) +#define bM4_INTC_VSSEL128_VSEL11 (*((volatile unsigned int*)(0x42A24BACUL))) +#define bM4_INTC_VSSEL128_VSEL12 (*((volatile unsigned int*)(0x42A24BB0UL))) +#define bM4_INTC_VSSEL128_VSEL13 (*((volatile unsigned int*)(0x42A24BB4UL))) +#define bM4_INTC_VSSEL128_VSEL14 (*((volatile unsigned int*)(0x42A24BB8UL))) +#define bM4_INTC_VSSEL128_VSEL15 (*((volatile unsigned int*)(0x42A24BBCUL))) +#define bM4_INTC_VSSEL128_VSEL16 (*((volatile unsigned int*)(0x42A24BC0UL))) +#define bM4_INTC_VSSEL128_VSEL17 (*((volatile unsigned int*)(0x42A24BC4UL))) +#define bM4_INTC_VSSEL128_VSEL18 (*((volatile unsigned int*)(0x42A24BC8UL))) +#define bM4_INTC_VSSEL128_VSEL19 (*((volatile unsigned int*)(0x42A24BCCUL))) +#define bM4_INTC_VSSEL128_VSEL20 (*((volatile unsigned int*)(0x42A24BD0UL))) +#define bM4_INTC_VSSEL128_VSEL21 (*((volatile unsigned int*)(0x42A24BD4UL))) +#define bM4_INTC_VSSEL128_VSEL22 (*((volatile unsigned int*)(0x42A24BD8UL))) +#define bM4_INTC_VSSEL128_VSEL23 (*((volatile unsigned int*)(0x42A24BDCUL))) +#define bM4_INTC_VSSEL128_VSEL24 (*((volatile unsigned int*)(0x42A24BE0UL))) +#define bM4_INTC_VSSEL128_VSEL25 (*((volatile unsigned int*)(0x42A24BE4UL))) +#define bM4_INTC_VSSEL128_VSEL26 (*((volatile unsigned int*)(0x42A24BE8UL))) +#define bM4_INTC_VSSEL128_VSEL27 (*((volatile unsigned int*)(0x42A24BECUL))) +#define bM4_INTC_VSSEL128_VSEL28 (*((volatile unsigned int*)(0x42A24BF0UL))) +#define bM4_INTC_VSSEL128_VSEL29 (*((volatile unsigned int*)(0x42A24BF4UL))) +#define bM4_INTC_VSSEL128_VSEL30 (*((volatile unsigned int*)(0x42A24BF8UL))) +#define bM4_INTC_VSSEL128_VSEL31 (*((volatile unsigned int*)(0x42A24BFCUL))) +#define bM4_INTC_VSSEL129_VSEL0 (*((volatile unsigned int*)(0x42A24C00UL))) +#define bM4_INTC_VSSEL129_VSEL1 (*((volatile unsigned int*)(0x42A24C04UL))) +#define bM4_INTC_VSSEL129_VSEL2 (*((volatile unsigned int*)(0x42A24C08UL))) +#define bM4_INTC_VSSEL129_VSEL3 (*((volatile unsigned int*)(0x42A24C0CUL))) +#define bM4_INTC_VSSEL129_VSEL4 (*((volatile unsigned int*)(0x42A24C10UL))) +#define bM4_INTC_VSSEL129_VSEL5 (*((volatile unsigned int*)(0x42A24C14UL))) +#define bM4_INTC_VSSEL129_VSEL6 (*((volatile unsigned int*)(0x42A24C18UL))) +#define bM4_INTC_VSSEL129_VSEL7 (*((volatile unsigned int*)(0x42A24C1CUL))) +#define bM4_INTC_VSSEL129_VSEL8 (*((volatile unsigned int*)(0x42A24C20UL))) +#define bM4_INTC_VSSEL129_VSEL9 (*((volatile unsigned int*)(0x42A24C24UL))) +#define bM4_INTC_VSSEL129_VSEL10 (*((volatile unsigned int*)(0x42A24C28UL))) +#define bM4_INTC_VSSEL129_VSEL11 (*((volatile unsigned int*)(0x42A24C2CUL))) +#define bM4_INTC_VSSEL129_VSEL12 (*((volatile unsigned int*)(0x42A24C30UL))) +#define bM4_INTC_VSSEL129_VSEL13 (*((volatile unsigned int*)(0x42A24C34UL))) +#define bM4_INTC_VSSEL129_VSEL14 (*((volatile unsigned int*)(0x42A24C38UL))) +#define bM4_INTC_VSSEL129_VSEL15 (*((volatile unsigned int*)(0x42A24C3CUL))) +#define bM4_INTC_VSSEL129_VSEL16 (*((volatile unsigned int*)(0x42A24C40UL))) +#define bM4_INTC_VSSEL129_VSEL17 (*((volatile unsigned int*)(0x42A24C44UL))) +#define bM4_INTC_VSSEL129_VSEL18 (*((volatile unsigned int*)(0x42A24C48UL))) +#define bM4_INTC_VSSEL129_VSEL19 (*((volatile unsigned int*)(0x42A24C4CUL))) +#define bM4_INTC_VSSEL129_VSEL20 (*((volatile unsigned int*)(0x42A24C50UL))) +#define bM4_INTC_VSSEL129_VSEL21 (*((volatile unsigned int*)(0x42A24C54UL))) +#define bM4_INTC_VSSEL129_VSEL22 (*((volatile unsigned int*)(0x42A24C58UL))) +#define bM4_INTC_VSSEL129_VSEL23 (*((volatile unsigned int*)(0x42A24C5CUL))) +#define bM4_INTC_VSSEL129_VSEL24 (*((volatile unsigned int*)(0x42A24C60UL))) +#define bM4_INTC_VSSEL129_VSEL25 (*((volatile unsigned int*)(0x42A24C64UL))) +#define bM4_INTC_VSSEL129_VSEL26 (*((volatile unsigned int*)(0x42A24C68UL))) +#define bM4_INTC_VSSEL129_VSEL27 (*((volatile unsigned int*)(0x42A24C6CUL))) +#define bM4_INTC_VSSEL129_VSEL28 (*((volatile unsigned int*)(0x42A24C70UL))) +#define bM4_INTC_VSSEL129_VSEL29 (*((volatile unsigned int*)(0x42A24C74UL))) +#define bM4_INTC_VSSEL129_VSEL30 (*((volatile unsigned int*)(0x42A24C78UL))) +#define bM4_INTC_VSSEL129_VSEL31 (*((volatile unsigned int*)(0x42A24C7CUL))) +#define bM4_INTC_VSSEL130_VSEL0 (*((volatile unsigned int*)(0x42A24C80UL))) +#define bM4_INTC_VSSEL130_VSEL1 (*((volatile unsigned int*)(0x42A24C84UL))) +#define bM4_INTC_VSSEL130_VSEL2 (*((volatile unsigned int*)(0x42A24C88UL))) +#define bM4_INTC_VSSEL130_VSEL3 (*((volatile unsigned int*)(0x42A24C8CUL))) +#define bM4_INTC_VSSEL130_VSEL4 (*((volatile unsigned int*)(0x42A24C90UL))) +#define bM4_INTC_VSSEL130_VSEL5 (*((volatile unsigned int*)(0x42A24C94UL))) +#define bM4_INTC_VSSEL130_VSEL6 (*((volatile unsigned int*)(0x42A24C98UL))) +#define bM4_INTC_VSSEL130_VSEL7 (*((volatile unsigned int*)(0x42A24C9CUL))) +#define bM4_INTC_VSSEL130_VSEL8 (*((volatile unsigned int*)(0x42A24CA0UL))) +#define bM4_INTC_VSSEL130_VSEL9 (*((volatile unsigned int*)(0x42A24CA4UL))) +#define bM4_INTC_VSSEL130_VSEL10 (*((volatile unsigned int*)(0x42A24CA8UL))) +#define bM4_INTC_VSSEL130_VSEL11 (*((volatile unsigned int*)(0x42A24CACUL))) +#define bM4_INTC_VSSEL130_VSEL12 (*((volatile unsigned int*)(0x42A24CB0UL))) +#define bM4_INTC_VSSEL130_VSEL13 (*((volatile unsigned int*)(0x42A24CB4UL))) +#define bM4_INTC_VSSEL130_VSEL14 (*((volatile unsigned int*)(0x42A24CB8UL))) +#define bM4_INTC_VSSEL130_VSEL15 (*((volatile unsigned int*)(0x42A24CBCUL))) +#define bM4_INTC_VSSEL130_VSEL16 (*((volatile unsigned int*)(0x42A24CC0UL))) +#define bM4_INTC_VSSEL130_VSEL17 (*((volatile unsigned int*)(0x42A24CC4UL))) +#define bM4_INTC_VSSEL130_VSEL18 (*((volatile unsigned int*)(0x42A24CC8UL))) +#define bM4_INTC_VSSEL130_VSEL19 (*((volatile unsigned int*)(0x42A24CCCUL))) +#define bM4_INTC_VSSEL130_VSEL20 (*((volatile unsigned int*)(0x42A24CD0UL))) +#define bM4_INTC_VSSEL130_VSEL21 (*((volatile unsigned int*)(0x42A24CD4UL))) +#define bM4_INTC_VSSEL130_VSEL22 (*((volatile unsigned int*)(0x42A24CD8UL))) +#define bM4_INTC_VSSEL130_VSEL23 (*((volatile unsigned int*)(0x42A24CDCUL))) +#define bM4_INTC_VSSEL130_VSEL24 (*((volatile unsigned int*)(0x42A24CE0UL))) +#define bM4_INTC_VSSEL130_VSEL25 (*((volatile unsigned int*)(0x42A24CE4UL))) +#define bM4_INTC_VSSEL130_VSEL26 (*((volatile unsigned int*)(0x42A24CE8UL))) +#define bM4_INTC_VSSEL130_VSEL27 (*((volatile unsigned int*)(0x42A24CECUL))) +#define bM4_INTC_VSSEL130_VSEL28 (*((volatile unsigned int*)(0x42A24CF0UL))) +#define bM4_INTC_VSSEL130_VSEL29 (*((volatile unsigned int*)(0x42A24CF4UL))) +#define bM4_INTC_VSSEL130_VSEL30 (*((volatile unsigned int*)(0x42A24CF8UL))) +#define bM4_INTC_VSSEL130_VSEL31 (*((volatile unsigned int*)(0x42A24CFCUL))) +#define bM4_INTC_VSSEL131_VSEL0 (*((volatile unsigned int*)(0x42A24D00UL))) +#define bM4_INTC_VSSEL131_VSEL1 (*((volatile unsigned int*)(0x42A24D04UL))) +#define bM4_INTC_VSSEL131_VSEL2 (*((volatile unsigned int*)(0x42A24D08UL))) +#define bM4_INTC_VSSEL131_VSEL3 (*((volatile unsigned int*)(0x42A24D0CUL))) +#define bM4_INTC_VSSEL131_VSEL4 (*((volatile unsigned int*)(0x42A24D10UL))) +#define bM4_INTC_VSSEL131_VSEL5 (*((volatile unsigned int*)(0x42A24D14UL))) +#define bM4_INTC_VSSEL131_VSEL6 (*((volatile unsigned int*)(0x42A24D18UL))) +#define bM4_INTC_VSSEL131_VSEL7 (*((volatile unsigned int*)(0x42A24D1CUL))) +#define bM4_INTC_VSSEL131_VSEL8 (*((volatile unsigned int*)(0x42A24D20UL))) +#define bM4_INTC_VSSEL131_VSEL9 (*((volatile unsigned int*)(0x42A24D24UL))) +#define bM4_INTC_VSSEL131_VSEL10 (*((volatile unsigned int*)(0x42A24D28UL))) +#define bM4_INTC_VSSEL131_VSEL11 (*((volatile unsigned int*)(0x42A24D2CUL))) +#define bM4_INTC_VSSEL131_VSEL12 (*((volatile unsigned int*)(0x42A24D30UL))) +#define bM4_INTC_VSSEL131_VSEL13 (*((volatile unsigned int*)(0x42A24D34UL))) +#define bM4_INTC_VSSEL131_VSEL14 (*((volatile unsigned int*)(0x42A24D38UL))) +#define bM4_INTC_VSSEL131_VSEL15 (*((volatile unsigned int*)(0x42A24D3CUL))) +#define bM4_INTC_VSSEL131_VSEL16 (*((volatile unsigned int*)(0x42A24D40UL))) +#define bM4_INTC_VSSEL131_VSEL17 (*((volatile unsigned int*)(0x42A24D44UL))) +#define bM4_INTC_VSSEL131_VSEL18 (*((volatile unsigned int*)(0x42A24D48UL))) +#define bM4_INTC_VSSEL131_VSEL19 (*((volatile unsigned int*)(0x42A24D4CUL))) +#define bM4_INTC_VSSEL131_VSEL20 (*((volatile unsigned int*)(0x42A24D50UL))) +#define bM4_INTC_VSSEL131_VSEL21 (*((volatile unsigned int*)(0x42A24D54UL))) +#define bM4_INTC_VSSEL131_VSEL22 (*((volatile unsigned int*)(0x42A24D58UL))) +#define bM4_INTC_VSSEL131_VSEL23 (*((volatile unsigned int*)(0x42A24D5CUL))) +#define bM4_INTC_VSSEL131_VSEL24 (*((volatile unsigned int*)(0x42A24D60UL))) +#define bM4_INTC_VSSEL131_VSEL25 (*((volatile unsigned int*)(0x42A24D64UL))) +#define bM4_INTC_VSSEL131_VSEL26 (*((volatile unsigned int*)(0x42A24D68UL))) +#define bM4_INTC_VSSEL131_VSEL27 (*((volatile unsigned int*)(0x42A24D6CUL))) +#define bM4_INTC_VSSEL131_VSEL28 (*((volatile unsigned int*)(0x42A24D70UL))) +#define bM4_INTC_VSSEL131_VSEL29 (*((volatile unsigned int*)(0x42A24D74UL))) +#define bM4_INTC_VSSEL131_VSEL30 (*((volatile unsigned int*)(0x42A24D78UL))) +#define bM4_INTC_VSSEL131_VSEL31 (*((volatile unsigned int*)(0x42A24D7CUL))) +#define bM4_INTC_VSSEL132_VSEL0 (*((volatile unsigned int*)(0x42A24D80UL))) +#define bM4_INTC_VSSEL132_VSEL1 (*((volatile unsigned int*)(0x42A24D84UL))) +#define bM4_INTC_VSSEL132_VSEL2 (*((volatile unsigned int*)(0x42A24D88UL))) +#define bM4_INTC_VSSEL132_VSEL3 (*((volatile unsigned int*)(0x42A24D8CUL))) +#define bM4_INTC_VSSEL132_VSEL4 (*((volatile unsigned int*)(0x42A24D90UL))) +#define bM4_INTC_VSSEL132_VSEL5 (*((volatile unsigned int*)(0x42A24D94UL))) +#define bM4_INTC_VSSEL132_VSEL6 (*((volatile unsigned int*)(0x42A24D98UL))) +#define bM4_INTC_VSSEL132_VSEL7 (*((volatile unsigned int*)(0x42A24D9CUL))) +#define bM4_INTC_VSSEL132_VSEL8 (*((volatile unsigned int*)(0x42A24DA0UL))) +#define bM4_INTC_VSSEL132_VSEL9 (*((volatile unsigned int*)(0x42A24DA4UL))) +#define bM4_INTC_VSSEL132_VSEL10 (*((volatile unsigned int*)(0x42A24DA8UL))) +#define bM4_INTC_VSSEL132_VSEL11 (*((volatile unsigned int*)(0x42A24DACUL))) +#define bM4_INTC_VSSEL132_VSEL12 (*((volatile unsigned int*)(0x42A24DB0UL))) +#define bM4_INTC_VSSEL132_VSEL13 (*((volatile unsigned int*)(0x42A24DB4UL))) +#define bM4_INTC_VSSEL132_VSEL14 (*((volatile unsigned int*)(0x42A24DB8UL))) +#define bM4_INTC_VSSEL132_VSEL15 (*((volatile unsigned int*)(0x42A24DBCUL))) +#define bM4_INTC_VSSEL132_VSEL16 (*((volatile unsigned int*)(0x42A24DC0UL))) +#define bM4_INTC_VSSEL132_VSEL17 (*((volatile unsigned int*)(0x42A24DC4UL))) +#define bM4_INTC_VSSEL132_VSEL18 (*((volatile unsigned int*)(0x42A24DC8UL))) +#define bM4_INTC_VSSEL132_VSEL19 (*((volatile unsigned int*)(0x42A24DCCUL))) +#define bM4_INTC_VSSEL132_VSEL20 (*((volatile unsigned int*)(0x42A24DD0UL))) +#define bM4_INTC_VSSEL132_VSEL21 (*((volatile unsigned int*)(0x42A24DD4UL))) +#define bM4_INTC_VSSEL132_VSEL22 (*((volatile unsigned int*)(0x42A24DD8UL))) +#define bM4_INTC_VSSEL132_VSEL23 (*((volatile unsigned int*)(0x42A24DDCUL))) +#define bM4_INTC_VSSEL132_VSEL24 (*((volatile unsigned int*)(0x42A24DE0UL))) +#define bM4_INTC_VSSEL132_VSEL25 (*((volatile unsigned int*)(0x42A24DE4UL))) +#define bM4_INTC_VSSEL132_VSEL26 (*((volatile unsigned int*)(0x42A24DE8UL))) +#define bM4_INTC_VSSEL132_VSEL27 (*((volatile unsigned int*)(0x42A24DECUL))) +#define bM4_INTC_VSSEL132_VSEL28 (*((volatile unsigned int*)(0x42A24DF0UL))) +#define bM4_INTC_VSSEL132_VSEL29 (*((volatile unsigned int*)(0x42A24DF4UL))) +#define bM4_INTC_VSSEL132_VSEL30 (*((volatile unsigned int*)(0x42A24DF8UL))) +#define bM4_INTC_VSSEL132_VSEL31 (*((volatile unsigned int*)(0x42A24DFCUL))) +#define bM4_INTC_VSSEL133_VSEL0 (*((volatile unsigned int*)(0x42A24E00UL))) +#define bM4_INTC_VSSEL133_VSEL1 (*((volatile unsigned int*)(0x42A24E04UL))) +#define bM4_INTC_VSSEL133_VSEL2 (*((volatile unsigned int*)(0x42A24E08UL))) +#define bM4_INTC_VSSEL133_VSEL3 (*((volatile unsigned int*)(0x42A24E0CUL))) +#define bM4_INTC_VSSEL133_VSEL4 (*((volatile unsigned int*)(0x42A24E10UL))) +#define bM4_INTC_VSSEL133_VSEL5 (*((volatile unsigned int*)(0x42A24E14UL))) +#define bM4_INTC_VSSEL133_VSEL6 (*((volatile unsigned int*)(0x42A24E18UL))) +#define bM4_INTC_VSSEL133_VSEL7 (*((volatile unsigned int*)(0x42A24E1CUL))) +#define bM4_INTC_VSSEL133_VSEL8 (*((volatile unsigned int*)(0x42A24E20UL))) +#define bM4_INTC_VSSEL133_VSEL9 (*((volatile unsigned int*)(0x42A24E24UL))) +#define bM4_INTC_VSSEL133_VSEL10 (*((volatile unsigned int*)(0x42A24E28UL))) +#define bM4_INTC_VSSEL133_VSEL11 (*((volatile unsigned int*)(0x42A24E2CUL))) +#define bM4_INTC_VSSEL133_VSEL12 (*((volatile unsigned int*)(0x42A24E30UL))) +#define bM4_INTC_VSSEL133_VSEL13 (*((volatile unsigned int*)(0x42A24E34UL))) +#define bM4_INTC_VSSEL133_VSEL14 (*((volatile unsigned int*)(0x42A24E38UL))) +#define bM4_INTC_VSSEL133_VSEL15 (*((volatile unsigned int*)(0x42A24E3CUL))) +#define bM4_INTC_VSSEL133_VSEL16 (*((volatile unsigned int*)(0x42A24E40UL))) +#define bM4_INTC_VSSEL133_VSEL17 (*((volatile unsigned int*)(0x42A24E44UL))) +#define bM4_INTC_VSSEL133_VSEL18 (*((volatile unsigned int*)(0x42A24E48UL))) +#define bM4_INTC_VSSEL133_VSEL19 (*((volatile unsigned int*)(0x42A24E4CUL))) +#define bM4_INTC_VSSEL133_VSEL20 (*((volatile unsigned int*)(0x42A24E50UL))) +#define bM4_INTC_VSSEL133_VSEL21 (*((volatile unsigned int*)(0x42A24E54UL))) +#define bM4_INTC_VSSEL133_VSEL22 (*((volatile unsigned int*)(0x42A24E58UL))) +#define bM4_INTC_VSSEL133_VSEL23 (*((volatile unsigned int*)(0x42A24E5CUL))) +#define bM4_INTC_VSSEL133_VSEL24 (*((volatile unsigned int*)(0x42A24E60UL))) +#define bM4_INTC_VSSEL133_VSEL25 (*((volatile unsigned int*)(0x42A24E64UL))) +#define bM4_INTC_VSSEL133_VSEL26 (*((volatile unsigned int*)(0x42A24E68UL))) +#define bM4_INTC_VSSEL133_VSEL27 (*((volatile unsigned int*)(0x42A24E6CUL))) +#define bM4_INTC_VSSEL133_VSEL28 (*((volatile unsigned int*)(0x42A24E70UL))) +#define bM4_INTC_VSSEL133_VSEL29 (*((volatile unsigned int*)(0x42A24E74UL))) +#define bM4_INTC_VSSEL133_VSEL30 (*((volatile unsigned int*)(0x42A24E78UL))) +#define bM4_INTC_VSSEL133_VSEL31 (*((volatile unsigned int*)(0x42A24E7CUL))) +#define bM4_INTC_VSSEL134_VSEL0 (*((volatile unsigned int*)(0x42A24E80UL))) +#define bM4_INTC_VSSEL134_VSEL1 (*((volatile unsigned int*)(0x42A24E84UL))) +#define bM4_INTC_VSSEL134_VSEL2 (*((volatile unsigned int*)(0x42A24E88UL))) +#define bM4_INTC_VSSEL134_VSEL3 (*((volatile unsigned int*)(0x42A24E8CUL))) +#define bM4_INTC_VSSEL134_VSEL4 (*((volatile unsigned int*)(0x42A24E90UL))) +#define bM4_INTC_VSSEL134_VSEL5 (*((volatile unsigned int*)(0x42A24E94UL))) +#define bM4_INTC_VSSEL134_VSEL6 (*((volatile unsigned int*)(0x42A24E98UL))) +#define bM4_INTC_VSSEL134_VSEL7 (*((volatile unsigned int*)(0x42A24E9CUL))) +#define bM4_INTC_VSSEL134_VSEL8 (*((volatile unsigned int*)(0x42A24EA0UL))) +#define bM4_INTC_VSSEL134_VSEL9 (*((volatile unsigned int*)(0x42A24EA4UL))) +#define bM4_INTC_VSSEL134_VSEL10 (*((volatile unsigned int*)(0x42A24EA8UL))) +#define bM4_INTC_VSSEL134_VSEL11 (*((volatile unsigned int*)(0x42A24EACUL))) +#define bM4_INTC_VSSEL134_VSEL12 (*((volatile unsigned int*)(0x42A24EB0UL))) +#define bM4_INTC_VSSEL134_VSEL13 (*((volatile unsigned int*)(0x42A24EB4UL))) +#define bM4_INTC_VSSEL134_VSEL14 (*((volatile unsigned int*)(0x42A24EB8UL))) +#define bM4_INTC_VSSEL134_VSEL15 (*((volatile unsigned int*)(0x42A24EBCUL))) +#define bM4_INTC_VSSEL134_VSEL16 (*((volatile unsigned int*)(0x42A24EC0UL))) +#define bM4_INTC_VSSEL134_VSEL17 (*((volatile unsigned int*)(0x42A24EC4UL))) +#define bM4_INTC_VSSEL134_VSEL18 (*((volatile unsigned int*)(0x42A24EC8UL))) +#define bM4_INTC_VSSEL134_VSEL19 (*((volatile unsigned int*)(0x42A24ECCUL))) +#define bM4_INTC_VSSEL134_VSEL20 (*((volatile unsigned int*)(0x42A24ED0UL))) +#define bM4_INTC_VSSEL134_VSEL21 (*((volatile unsigned int*)(0x42A24ED4UL))) +#define bM4_INTC_VSSEL134_VSEL22 (*((volatile unsigned int*)(0x42A24ED8UL))) +#define bM4_INTC_VSSEL134_VSEL23 (*((volatile unsigned int*)(0x42A24EDCUL))) +#define bM4_INTC_VSSEL134_VSEL24 (*((volatile unsigned int*)(0x42A24EE0UL))) +#define bM4_INTC_VSSEL134_VSEL25 (*((volatile unsigned int*)(0x42A24EE4UL))) +#define bM4_INTC_VSSEL134_VSEL26 (*((volatile unsigned int*)(0x42A24EE8UL))) +#define bM4_INTC_VSSEL134_VSEL27 (*((volatile unsigned int*)(0x42A24EECUL))) +#define bM4_INTC_VSSEL134_VSEL28 (*((volatile unsigned int*)(0x42A24EF0UL))) +#define bM4_INTC_VSSEL134_VSEL29 (*((volatile unsigned int*)(0x42A24EF4UL))) +#define bM4_INTC_VSSEL134_VSEL30 (*((volatile unsigned int*)(0x42A24EF8UL))) +#define bM4_INTC_VSSEL134_VSEL31 (*((volatile unsigned int*)(0x42A24EFCUL))) +#define bM4_INTC_VSSEL135_VSEL0 (*((volatile unsigned int*)(0x42A24F00UL))) +#define bM4_INTC_VSSEL135_VSEL1 (*((volatile unsigned int*)(0x42A24F04UL))) +#define bM4_INTC_VSSEL135_VSEL2 (*((volatile unsigned int*)(0x42A24F08UL))) +#define bM4_INTC_VSSEL135_VSEL3 (*((volatile unsigned int*)(0x42A24F0CUL))) +#define bM4_INTC_VSSEL135_VSEL4 (*((volatile unsigned int*)(0x42A24F10UL))) +#define bM4_INTC_VSSEL135_VSEL5 (*((volatile unsigned int*)(0x42A24F14UL))) +#define bM4_INTC_VSSEL135_VSEL6 (*((volatile unsigned int*)(0x42A24F18UL))) +#define bM4_INTC_VSSEL135_VSEL7 (*((volatile unsigned int*)(0x42A24F1CUL))) +#define bM4_INTC_VSSEL135_VSEL8 (*((volatile unsigned int*)(0x42A24F20UL))) +#define bM4_INTC_VSSEL135_VSEL9 (*((volatile unsigned int*)(0x42A24F24UL))) +#define bM4_INTC_VSSEL135_VSEL10 (*((volatile unsigned int*)(0x42A24F28UL))) +#define bM4_INTC_VSSEL135_VSEL11 (*((volatile unsigned int*)(0x42A24F2CUL))) +#define bM4_INTC_VSSEL135_VSEL12 (*((volatile unsigned int*)(0x42A24F30UL))) +#define bM4_INTC_VSSEL135_VSEL13 (*((volatile unsigned int*)(0x42A24F34UL))) +#define bM4_INTC_VSSEL135_VSEL14 (*((volatile unsigned int*)(0x42A24F38UL))) +#define bM4_INTC_VSSEL135_VSEL15 (*((volatile unsigned int*)(0x42A24F3CUL))) +#define bM4_INTC_VSSEL135_VSEL16 (*((volatile unsigned int*)(0x42A24F40UL))) +#define bM4_INTC_VSSEL135_VSEL17 (*((volatile unsigned int*)(0x42A24F44UL))) +#define bM4_INTC_VSSEL135_VSEL18 (*((volatile unsigned int*)(0x42A24F48UL))) +#define bM4_INTC_VSSEL135_VSEL19 (*((volatile unsigned int*)(0x42A24F4CUL))) +#define bM4_INTC_VSSEL135_VSEL20 (*((volatile unsigned int*)(0x42A24F50UL))) +#define bM4_INTC_VSSEL135_VSEL21 (*((volatile unsigned int*)(0x42A24F54UL))) +#define bM4_INTC_VSSEL135_VSEL22 (*((volatile unsigned int*)(0x42A24F58UL))) +#define bM4_INTC_VSSEL135_VSEL23 (*((volatile unsigned int*)(0x42A24F5CUL))) +#define bM4_INTC_VSSEL135_VSEL24 (*((volatile unsigned int*)(0x42A24F60UL))) +#define bM4_INTC_VSSEL135_VSEL25 (*((volatile unsigned int*)(0x42A24F64UL))) +#define bM4_INTC_VSSEL135_VSEL26 (*((volatile unsigned int*)(0x42A24F68UL))) +#define bM4_INTC_VSSEL135_VSEL27 (*((volatile unsigned int*)(0x42A24F6CUL))) +#define bM4_INTC_VSSEL135_VSEL28 (*((volatile unsigned int*)(0x42A24F70UL))) +#define bM4_INTC_VSSEL135_VSEL29 (*((volatile unsigned int*)(0x42A24F74UL))) +#define bM4_INTC_VSSEL135_VSEL30 (*((volatile unsigned int*)(0x42A24F78UL))) +#define bM4_INTC_VSSEL135_VSEL31 (*((volatile unsigned int*)(0x42A24F7CUL))) +#define bM4_INTC_VSSEL136_VSEL0 (*((volatile unsigned int*)(0x42A24F80UL))) +#define bM4_INTC_VSSEL136_VSEL1 (*((volatile unsigned int*)(0x42A24F84UL))) +#define bM4_INTC_VSSEL136_VSEL2 (*((volatile unsigned int*)(0x42A24F88UL))) +#define bM4_INTC_VSSEL136_VSEL3 (*((volatile unsigned int*)(0x42A24F8CUL))) +#define bM4_INTC_VSSEL136_VSEL4 (*((volatile unsigned int*)(0x42A24F90UL))) +#define bM4_INTC_VSSEL136_VSEL5 (*((volatile unsigned int*)(0x42A24F94UL))) +#define bM4_INTC_VSSEL136_VSEL6 (*((volatile unsigned int*)(0x42A24F98UL))) +#define bM4_INTC_VSSEL136_VSEL7 (*((volatile unsigned int*)(0x42A24F9CUL))) +#define bM4_INTC_VSSEL136_VSEL8 (*((volatile unsigned int*)(0x42A24FA0UL))) +#define bM4_INTC_VSSEL136_VSEL9 (*((volatile unsigned int*)(0x42A24FA4UL))) +#define bM4_INTC_VSSEL136_VSEL10 (*((volatile unsigned int*)(0x42A24FA8UL))) +#define bM4_INTC_VSSEL136_VSEL11 (*((volatile unsigned int*)(0x42A24FACUL))) +#define bM4_INTC_VSSEL136_VSEL12 (*((volatile unsigned int*)(0x42A24FB0UL))) +#define bM4_INTC_VSSEL136_VSEL13 (*((volatile unsigned int*)(0x42A24FB4UL))) +#define bM4_INTC_VSSEL136_VSEL14 (*((volatile unsigned int*)(0x42A24FB8UL))) +#define bM4_INTC_VSSEL136_VSEL15 (*((volatile unsigned int*)(0x42A24FBCUL))) +#define bM4_INTC_VSSEL136_VSEL16 (*((volatile unsigned int*)(0x42A24FC0UL))) +#define bM4_INTC_VSSEL136_VSEL17 (*((volatile unsigned int*)(0x42A24FC4UL))) +#define bM4_INTC_VSSEL136_VSEL18 (*((volatile unsigned int*)(0x42A24FC8UL))) +#define bM4_INTC_VSSEL136_VSEL19 (*((volatile unsigned int*)(0x42A24FCCUL))) +#define bM4_INTC_VSSEL136_VSEL20 (*((volatile unsigned int*)(0x42A24FD0UL))) +#define bM4_INTC_VSSEL136_VSEL21 (*((volatile unsigned int*)(0x42A24FD4UL))) +#define bM4_INTC_VSSEL136_VSEL22 (*((volatile unsigned int*)(0x42A24FD8UL))) +#define bM4_INTC_VSSEL136_VSEL23 (*((volatile unsigned int*)(0x42A24FDCUL))) +#define bM4_INTC_VSSEL136_VSEL24 (*((volatile unsigned int*)(0x42A24FE0UL))) +#define bM4_INTC_VSSEL136_VSEL25 (*((volatile unsigned int*)(0x42A24FE4UL))) +#define bM4_INTC_VSSEL136_VSEL26 (*((volatile unsigned int*)(0x42A24FE8UL))) +#define bM4_INTC_VSSEL136_VSEL27 (*((volatile unsigned int*)(0x42A24FECUL))) +#define bM4_INTC_VSSEL136_VSEL28 (*((volatile unsigned int*)(0x42A24FF0UL))) +#define bM4_INTC_VSSEL136_VSEL29 (*((volatile unsigned int*)(0x42A24FF4UL))) +#define bM4_INTC_VSSEL136_VSEL30 (*((volatile unsigned int*)(0x42A24FF8UL))) +#define bM4_INTC_VSSEL136_VSEL31 (*((volatile unsigned int*)(0x42A24FFCUL))) +#define bM4_INTC_VSSEL137_VSEL0 (*((volatile unsigned int*)(0x42A25000UL))) +#define bM4_INTC_VSSEL137_VSEL1 (*((volatile unsigned int*)(0x42A25004UL))) +#define bM4_INTC_VSSEL137_VSEL2 (*((volatile unsigned int*)(0x42A25008UL))) +#define bM4_INTC_VSSEL137_VSEL3 (*((volatile unsigned int*)(0x42A2500CUL))) +#define bM4_INTC_VSSEL137_VSEL4 (*((volatile unsigned int*)(0x42A25010UL))) +#define bM4_INTC_VSSEL137_VSEL5 (*((volatile unsigned int*)(0x42A25014UL))) +#define bM4_INTC_VSSEL137_VSEL6 (*((volatile unsigned int*)(0x42A25018UL))) +#define bM4_INTC_VSSEL137_VSEL7 (*((volatile unsigned int*)(0x42A2501CUL))) +#define bM4_INTC_VSSEL137_VSEL8 (*((volatile unsigned int*)(0x42A25020UL))) +#define bM4_INTC_VSSEL137_VSEL9 (*((volatile unsigned int*)(0x42A25024UL))) +#define bM4_INTC_VSSEL137_VSEL10 (*((volatile unsigned int*)(0x42A25028UL))) +#define bM4_INTC_VSSEL137_VSEL11 (*((volatile unsigned int*)(0x42A2502CUL))) +#define bM4_INTC_VSSEL137_VSEL12 (*((volatile unsigned int*)(0x42A25030UL))) +#define bM4_INTC_VSSEL137_VSEL13 (*((volatile unsigned int*)(0x42A25034UL))) +#define bM4_INTC_VSSEL137_VSEL14 (*((volatile unsigned int*)(0x42A25038UL))) +#define bM4_INTC_VSSEL137_VSEL15 (*((volatile unsigned int*)(0x42A2503CUL))) +#define bM4_INTC_VSSEL137_VSEL16 (*((volatile unsigned int*)(0x42A25040UL))) +#define bM4_INTC_VSSEL137_VSEL17 (*((volatile unsigned int*)(0x42A25044UL))) +#define bM4_INTC_VSSEL137_VSEL18 (*((volatile unsigned int*)(0x42A25048UL))) +#define bM4_INTC_VSSEL137_VSEL19 (*((volatile unsigned int*)(0x42A2504CUL))) +#define bM4_INTC_VSSEL137_VSEL20 (*((volatile unsigned int*)(0x42A25050UL))) +#define bM4_INTC_VSSEL137_VSEL21 (*((volatile unsigned int*)(0x42A25054UL))) +#define bM4_INTC_VSSEL137_VSEL22 (*((volatile unsigned int*)(0x42A25058UL))) +#define bM4_INTC_VSSEL137_VSEL23 (*((volatile unsigned int*)(0x42A2505CUL))) +#define bM4_INTC_VSSEL137_VSEL24 (*((volatile unsigned int*)(0x42A25060UL))) +#define bM4_INTC_VSSEL137_VSEL25 (*((volatile unsigned int*)(0x42A25064UL))) +#define bM4_INTC_VSSEL137_VSEL26 (*((volatile unsigned int*)(0x42A25068UL))) +#define bM4_INTC_VSSEL137_VSEL27 (*((volatile unsigned int*)(0x42A2506CUL))) +#define bM4_INTC_VSSEL137_VSEL28 (*((volatile unsigned int*)(0x42A25070UL))) +#define bM4_INTC_VSSEL137_VSEL29 (*((volatile unsigned int*)(0x42A25074UL))) +#define bM4_INTC_VSSEL137_VSEL30 (*((volatile unsigned int*)(0x42A25078UL))) +#define bM4_INTC_VSSEL137_VSEL31 (*((volatile unsigned int*)(0x42A2507CUL))) +#define bM4_INTC_VSSEL138_VSEL0 (*((volatile unsigned int*)(0x42A25080UL))) +#define bM4_INTC_VSSEL138_VSEL1 (*((volatile unsigned int*)(0x42A25084UL))) +#define bM4_INTC_VSSEL138_VSEL2 (*((volatile unsigned int*)(0x42A25088UL))) +#define bM4_INTC_VSSEL138_VSEL3 (*((volatile unsigned int*)(0x42A2508CUL))) +#define bM4_INTC_VSSEL138_VSEL4 (*((volatile unsigned int*)(0x42A25090UL))) +#define bM4_INTC_VSSEL138_VSEL5 (*((volatile unsigned int*)(0x42A25094UL))) +#define bM4_INTC_VSSEL138_VSEL6 (*((volatile unsigned int*)(0x42A25098UL))) +#define bM4_INTC_VSSEL138_VSEL7 (*((volatile unsigned int*)(0x42A2509CUL))) +#define bM4_INTC_VSSEL138_VSEL8 (*((volatile unsigned int*)(0x42A250A0UL))) +#define bM4_INTC_VSSEL138_VSEL9 (*((volatile unsigned int*)(0x42A250A4UL))) +#define bM4_INTC_VSSEL138_VSEL10 (*((volatile unsigned int*)(0x42A250A8UL))) +#define bM4_INTC_VSSEL138_VSEL11 (*((volatile unsigned int*)(0x42A250ACUL))) +#define bM4_INTC_VSSEL138_VSEL12 (*((volatile unsigned int*)(0x42A250B0UL))) +#define bM4_INTC_VSSEL138_VSEL13 (*((volatile unsigned int*)(0x42A250B4UL))) +#define bM4_INTC_VSSEL138_VSEL14 (*((volatile unsigned int*)(0x42A250B8UL))) +#define bM4_INTC_VSSEL138_VSEL15 (*((volatile unsigned int*)(0x42A250BCUL))) +#define bM4_INTC_VSSEL138_VSEL16 (*((volatile unsigned int*)(0x42A250C0UL))) +#define bM4_INTC_VSSEL138_VSEL17 (*((volatile unsigned int*)(0x42A250C4UL))) +#define bM4_INTC_VSSEL138_VSEL18 (*((volatile unsigned int*)(0x42A250C8UL))) +#define bM4_INTC_VSSEL138_VSEL19 (*((volatile unsigned int*)(0x42A250CCUL))) +#define bM4_INTC_VSSEL138_VSEL20 (*((volatile unsigned int*)(0x42A250D0UL))) +#define bM4_INTC_VSSEL138_VSEL21 (*((volatile unsigned int*)(0x42A250D4UL))) +#define bM4_INTC_VSSEL138_VSEL22 (*((volatile unsigned int*)(0x42A250D8UL))) +#define bM4_INTC_VSSEL138_VSEL23 (*((volatile unsigned int*)(0x42A250DCUL))) +#define bM4_INTC_VSSEL138_VSEL24 (*((volatile unsigned int*)(0x42A250E0UL))) +#define bM4_INTC_VSSEL138_VSEL25 (*((volatile unsigned int*)(0x42A250E4UL))) +#define bM4_INTC_VSSEL138_VSEL26 (*((volatile unsigned int*)(0x42A250E8UL))) +#define bM4_INTC_VSSEL138_VSEL27 (*((volatile unsigned int*)(0x42A250ECUL))) +#define bM4_INTC_VSSEL138_VSEL28 (*((volatile unsigned int*)(0x42A250F0UL))) +#define bM4_INTC_VSSEL138_VSEL29 (*((volatile unsigned int*)(0x42A250F4UL))) +#define bM4_INTC_VSSEL138_VSEL30 (*((volatile unsigned int*)(0x42A250F8UL))) +#define bM4_INTC_VSSEL138_VSEL31 (*((volatile unsigned int*)(0x42A250FCUL))) +#define bM4_INTC_VSSEL139_VSEL0 (*((volatile unsigned int*)(0x42A25100UL))) +#define bM4_INTC_VSSEL139_VSEL1 (*((volatile unsigned int*)(0x42A25104UL))) +#define bM4_INTC_VSSEL139_VSEL2 (*((volatile unsigned int*)(0x42A25108UL))) +#define bM4_INTC_VSSEL139_VSEL3 (*((volatile unsigned int*)(0x42A2510CUL))) +#define bM4_INTC_VSSEL139_VSEL4 (*((volatile unsigned int*)(0x42A25110UL))) +#define bM4_INTC_VSSEL139_VSEL5 (*((volatile unsigned int*)(0x42A25114UL))) +#define bM4_INTC_VSSEL139_VSEL6 (*((volatile unsigned int*)(0x42A25118UL))) +#define bM4_INTC_VSSEL139_VSEL7 (*((volatile unsigned int*)(0x42A2511CUL))) +#define bM4_INTC_VSSEL139_VSEL8 (*((volatile unsigned int*)(0x42A25120UL))) +#define bM4_INTC_VSSEL139_VSEL9 (*((volatile unsigned int*)(0x42A25124UL))) +#define bM4_INTC_VSSEL139_VSEL10 (*((volatile unsigned int*)(0x42A25128UL))) +#define bM4_INTC_VSSEL139_VSEL11 (*((volatile unsigned int*)(0x42A2512CUL))) +#define bM4_INTC_VSSEL139_VSEL12 (*((volatile unsigned int*)(0x42A25130UL))) +#define bM4_INTC_VSSEL139_VSEL13 (*((volatile unsigned int*)(0x42A25134UL))) +#define bM4_INTC_VSSEL139_VSEL14 (*((volatile unsigned int*)(0x42A25138UL))) +#define bM4_INTC_VSSEL139_VSEL15 (*((volatile unsigned int*)(0x42A2513CUL))) +#define bM4_INTC_VSSEL139_VSEL16 (*((volatile unsigned int*)(0x42A25140UL))) +#define bM4_INTC_VSSEL139_VSEL17 (*((volatile unsigned int*)(0x42A25144UL))) +#define bM4_INTC_VSSEL139_VSEL18 (*((volatile unsigned int*)(0x42A25148UL))) +#define bM4_INTC_VSSEL139_VSEL19 (*((volatile unsigned int*)(0x42A2514CUL))) +#define bM4_INTC_VSSEL139_VSEL20 (*((volatile unsigned int*)(0x42A25150UL))) +#define bM4_INTC_VSSEL139_VSEL21 (*((volatile unsigned int*)(0x42A25154UL))) +#define bM4_INTC_VSSEL139_VSEL22 (*((volatile unsigned int*)(0x42A25158UL))) +#define bM4_INTC_VSSEL139_VSEL23 (*((volatile unsigned int*)(0x42A2515CUL))) +#define bM4_INTC_VSSEL139_VSEL24 (*((volatile unsigned int*)(0x42A25160UL))) +#define bM4_INTC_VSSEL139_VSEL25 (*((volatile unsigned int*)(0x42A25164UL))) +#define bM4_INTC_VSSEL139_VSEL26 (*((volatile unsigned int*)(0x42A25168UL))) +#define bM4_INTC_VSSEL139_VSEL27 (*((volatile unsigned int*)(0x42A2516CUL))) +#define bM4_INTC_VSSEL139_VSEL28 (*((volatile unsigned int*)(0x42A25170UL))) +#define bM4_INTC_VSSEL139_VSEL29 (*((volatile unsigned int*)(0x42A25174UL))) +#define bM4_INTC_VSSEL139_VSEL30 (*((volatile unsigned int*)(0x42A25178UL))) +#define bM4_INTC_VSSEL139_VSEL31 (*((volatile unsigned int*)(0x42A2517CUL))) +#define bM4_INTC_VSSEL140_VSEL0 (*((volatile unsigned int*)(0x42A25180UL))) +#define bM4_INTC_VSSEL140_VSEL1 (*((volatile unsigned int*)(0x42A25184UL))) +#define bM4_INTC_VSSEL140_VSEL2 (*((volatile unsigned int*)(0x42A25188UL))) +#define bM4_INTC_VSSEL140_VSEL3 (*((volatile unsigned int*)(0x42A2518CUL))) +#define bM4_INTC_VSSEL140_VSEL4 (*((volatile unsigned int*)(0x42A25190UL))) +#define bM4_INTC_VSSEL140_VSEL5 (*((volatile unsigned int*)(0x42A25194UL))) +#define bM4_INTC_VSSEL140_VSEL6 (*((volatile unsigned int*)(0x42A25198UL))) +#define bM4_INTC_VSSEL140_VSEL7 (*((volatile unsigned int*)(0x42A2519CUL))) +#define bM4_INTC_VSSEL140_VSEL8 (*((volatile unsigned int*)(0x42A251A0UL))) +#define bM4_INTC_VSSEL140_VSEL9 (*((volatile unsigned int*)(0x42A251A4UL))) +#define bM4_INTC_VSSEL140_VSEL10 (*((volatile unsigned int*)(0x42A251A8UL))) +#define bM4_INTC_VSSEL140_VSEL11 (*((volatile unsigned int*)(0x42A251ACUL))) +#define bM4_INTC_VSSEL140_VSEL12 (*((volatile unsigned int*)(0x42A251B0UL))) +#define bM4_INTC_VSSEL140_VSEL13 (*((volatile unsigned int*)(0x42A251B4UL))) +#define bM4_INTC_VSSEL140_VSEL14 (*((volatile unsigned int*)(0x42A251B8UL))) +#define bM4_INTC_VSSEL140_VSEL15 (*((volatile unsigned int*)(0x42A251BCUL))) +#define bM4_INTC_VSSEL140_VSEL16 (*((volatile unsigned int*)(0x42A251C0UL))) +#define bM4_INTC_VSSEL140_VSEL17 (*((volatile unsigned int*)(0x42A251C4UL))) +#define bM4_INTC_VSSEL140_VSEL18 (*((volatile unsigned int*)(0x42A251C8UL))) +#define bM4_INTC_VSSEL140_VSEL19 (*((volatile unsigned int*)(0x42A251CCUL))) +#define bM4_INTC_VSSEL140_VSEL20 (*((volatile unsigned int*)(0x42A251D0UL))) +#define bM4_INTC_VSSEL140_VSEL21 (*((volatile unsigned int*)(0x42A251D4UL))) +#define bM4_INTC_VSSEL140_VSEL22 (*((volatile unsigned int*)(0x42A251D8UL))) +#define bM4_INTC_VSSEL140_VSEL23 (*((volatile unsigned int*)(0x42A251DCUL))) +#define bM4_INTC_VSSEL140_VSEL24 (*((volatile unsigned int*)(0x42A251E0UL))) +#define bM4_INTC_VSSEL140_VSEL25 (*((volatile unsigned int*)(0x42A251E4UL))) +#define bM4_INTC_VSSEL140_VSEL26 (*((volatile unsigned int*)(0x42A251E8UL))) +#define bM4_INTC_VSSEL140_VSEL27 (*((volatile unsigned int*)(0x42A251ECUL))) +#define bM4_INTC_VSSEL140_VSEL28 (*((volatile unsigned int*)(0x42A251F0UL))) +#define bM4_INTC_VSSEL140_VSEL29 (*((volatile unsigned int*)(0x42A251F4UL))) +#define bM4_INTC_VSSEL140_VSEL30 (*((volatile unsigned int*)(0x42A251F8UL))) +#define bM4_INTC_VSSEL140_VSEL31 (*((volatile unsigned int*)(0x42A251FCUL))) +#define bM4_INTC_VSSEL141_VSEL0 (*((volatile unsigned int*)(0x42A25200UL))) +#define bM4_INTC_VSSEL141_VSEL1 (*((volatile unsigned int*)(0x42A25204UL))) +#define bM4_INTC_VSSEL141_VSEL2 (*((volatile unsigned int*)(0x42A25208UL))) +#define bM4_INTC_VSSEL141_VSEL3 (*((volatile unsigned int*)(0x42A2520CUL))) +#define bM4_INTC_VSSEL141_VSEL4 (*((volatile unsigned int*)(0x42A25210UL))) +#define bM4_INTC_VSSEL141_VSEL5 (*((volatile unsigned int*)(0x42A25214UL))) +#define bM4_INTC_VSSEL141_VSEL6 (*((volatile unsigned int*)(0x42A25218UL))) +#define bM4_INTC_VSSEL141_VSEL7 (*((volatile unsigned int*)(0x42A2521CUL))) +#define bM4_INTC_VSSEL141_VSEL8 (*((volatile unsigned int*)(0x42A25220UL))) +#define bM4_INTC_VSSEL141_VSEL9 (*((volatile unsigned int*)(0x42A25224UL))) +#define bM4_INTC_VSSEL141_VSEL10 (*((volatile unsigned int*)(0x42A25228UL))) +#define bM4_INTC_VSSEL141_VSEL11 (*((volatile unsigned int*)(0x42A2522CUL))) +#define bM4_INTC_VSSEL141_VSEL12 (*((volatile unsigned int*)(0x42A25230UL))) +#define bM4_INTC_VSSEL141_VSEL13 (*((volatile unsigned int*)(0x42A25234UL))) +#define bM4_INTC_VSSEL141_VSEL14 (*((volatile unsigned int*)(0x42A25238UL))) +#define bM4_INTC_VSSEL141_VSEL15 (*((volatile unsigned int*)(0x42A2523CUL))) +#define bM4_INTC_VSSEL141_VSEL16 (*((volatile unsigned int*)(0x42A25240UL))) +#define bM4_INTC_VSSEL141_VSEL17 (*((volatile unsigned int*)(0x42A25244UL))) +#define bM4_INTC_VSSEL141_VSEL18 (*((volatile unsigned int*)(0x42A25248UL))) +#define bM4_INTC_VSSEL141_VSEL19 (*((volatile unsigned int*)(0x42A2524CUL))) +#define bM4_INTC_VSSEL141_VSEL20 (*((volatile unsigned int*)(0x42A25250UL))) +#define bM4_INTC_VSSEL141_VSEL21 (*((volatile unsigned int*)(0x42A25254UL))) +#define bM4_INTC_VSSEL141_VSEL22 (*((volatile unsigned int*)(0x42A25258UL))) +#define bM4_INTC_VSSEL141_VSEL23 (*((volatile unsigned int*)(0x42A2525CUL))) +#define bM4_INTC_VSSEL141_VSEL24 (*((volatile unsigned int*)(0x42A25260UL))) +#define bM4_INTC_VSSEL141_VSEL25 (*((volatile unsigned int*)(0x42A25264UL))) +#define bM4_INTC_VSSEL141_VSEL26 (*((volatile unsigned int*)(0x42A25268UL))) +#define bM4_INTC_VSSEL141_VSEL27 (*((volatile unsigned int*)(0x42A2526CUL))) +#define bM4_INTC_VSSEL141_VSEL28 (*((volatile unsigned int*)(0x42A25270UL))) +#define bM4_INTC_VSSEL141_VSEL29 (*((volatile unsigned int*)(0x42A25274UL))) +#define bM4_INTC_VSSEL141_VSEL30 (*((volatile unsigned int*)(0x42A25278UL))) +#define bM4_INTC_VSSEL141_VSEL31 (*((volatile unsigned int*)(0x42A2527CUL))) +#define bM4_INTC_VSSEL142_VSEL0 (*((volatile unsigned int*)(0x42A25280UL))) +#define bM4_INTC_VSSEL142_VSEL1 (*((volatile unsigned int*)(0x42A25284UL))) +#define bM4_INTC_VSSEL142_VSEL2 (*((volatile unsigned int*)(0x42A25288UL))) +#define bM4_INTC_VSSEL142_VSEL3 (*((volatile unsigned int*)(0x42A2528CUL))) +#define bM4_INTC_VSSEL142_VSEL4 (*((volatile unsigned int*)(0x42A25290UL))) +#define bM4_INTC_VSSEL142_VSEL5 (*((volatile unsigned int*)(0x42A25294UL))) +#define bM4_INTC_VSSEL142_VSEL6 (*((volatile unsigned int*)(0x42A25298UL))) +#define bM4_INTC_VSSEL142_VSEL7 (*((volatile unsigned int*)(0x42A2529CUL))) +#define bM4_INTC_VSSEL142_VSEL8 (*((volatile unsigned int*)(0x42A252A0UL))) +#define bM4_INTC_VSSEL142_VSEL9 (*((volatile unsigned int*)(0x42A252A4UL))) +#define bM4_INTC_VSSEL142_VSEL10 (*((volatile unsigned int*)(0x42A252A8UL))) +#define bM4_INTC_VSSEL142_VSEL11 (*((volatile unsigned int*)(0x42A252ACUL))) +#define bM4_INTC_VSSEL142_VSEL12 (*((volatile unsigned int*)(0x42A252B0UL))) +#define bM4_INTC_VSSEL142_VSEL13 (*((volatile unsigned int*)(0x42A252B4UL))) +#define bM4_INTC_VSSEL142_VSEL14 (*((volatile unsigned int*)(0x42A252B8UL))) +#define bM4_INTC_VSSEL142_VSEL15 (*((volatile unsigned int*)(0x42A252BCUL))) +#define bM4_INTC_VSSEL142_VSEL16 (*((volatile unsigned int*)(0x42A252C0UL))) +#define bM4_INTC_VSSEL142_VSEL17 (*((volatile unsigned int*)(0x42A252C4UL))) +#define bM4_INTC_VSSEL142_VSEL18 (*((volatile unsigned int*)(0x42A252C8UL))) +#define bM4_INTC_VSSEL142_VSEL19 (*((volatile unsigned int*)(0x42A252CCUL))) +#define bM4_INTC_VSSEL142_VSEL20 (*((volatile unsigned int*)(0x42A252D0UL))) +#define bM4_INTC_VSSEL142_VSEL21 (*((volatile unsigned int*)(0x42A252D4UL))) +#define bM4_INTC_VSSEL142_VSEL22 (*((volatile unsigned int*)(0x42A252D8UL))) +#define bM4_INTC_VSSEL142_VSEL23 (*((volatile unsigned int*)(0x42A252DCUL))) +#define bM4_INTC_VSSEL142_VSEL24 (*((volatile unsigned int*)(0x42A252E0UL))) +#define bM4_INTC_VSSEL142_VSEL25 (*((volatile unsigned int*)(0x42A252E4UL))) +#define bM4_INTC_VSSEL142_VSEL26 (*((volatile unsigned int*)(0x42A252E8UL))) +#define bM4_INTC_VSSEL142_VSEL27 (*((volatile unsigned int*)(0x42A252ECUL))) +#define bM4_INTC_VSSEL142_VSEL28 (*((volatile unsigned int*)(0x42A252F0UL))) +#define bM4_INTC_VSSEL142_VSEL29 (*((volatile unsigned int*)(0x42A252F4UL))) +#define bM4_INTC_VSSEL142_VSEL30 (*((volatile unsigned int*)(0x42A252F8UL))) +#define bM4_INTC_VSSEL142_VSEL31 (*((volatile unsigned int*)(0x42A252FCUL))) +#define bM4_INTC_VSSEL143_VSEL0 (*((volatile unsigned int*)(0x42A25300UL))) +#define bM4_INTC_VSSEL143_VSEL1 (*((volatile unsigned int*)(0x42A25304UL))) +#define bM4_INTC_VSSEL143_VSEL2 (*((volatile unsigned int*)(0x42A25308UL))) +#define bM4_INTC_VSSEL143_VSEL3 (*((volatile unsigned int*)(0x42A2530CUL))) +#define bM4_INTC_VSSEL143_VSEL4 (*((volatile unsigned int*)(0x42A25310UL))) +#define bM4_INTC_VSSEL143_VSEL5 (*((volatile unsigned int*)(0x42A25314UL))) +#define bM4_INTC_VSSEL143_VSEL6 (*((volatile unsigned int*)(0x42A25318UL))) +#define bM4_INTC_VSSEL143_VSEL7 (*((volatile unsigned int*)(0x42A2531CUL))) +#define bM4_INTC_VSSEL143_VSEL8 (*((volatile unsigned int*)(0x42A25320UL))) +#define bM4_INTC_VSSEL143_VSEL9 (*((volatile unsigned int*)(0x42A25324UL))) +#define bM4_INTC_VSSEL143_VSEL10 (*((volatile unsigned int*)(0x42A25328UL))) +#define bM4_INTC_VSSEL143_VSEL11 (*((volatile unsigned int*)(0x42A2532CUL))) +#define bM4_INTC_VSSEL143_VSEL12 (*((volatile unsigned int*)(0x42A25330UL))) +#define bM4_INTC_VSSEL143_VSEL13 (*((volatile unsigned int*)(0x42A25334UL))) +#define bM4_INTC_VSSEL143_VSEL14 (*((volatile unsigned int*)(0x42A25338UL))) +#define bM4_INTC_VSSEL143_VSEL15 (*((volatile unsigned int*)(0x42A2533CUL))) +#define bM4_INTC_VSSEL143_VSEL16 (*((volatile unsigned int*)(0x42A25340UL))) +#define bM4_INTC_VSSEL143_VSEL17 (*((volatile unsigned int*)(0x42A25344UL))) +#define bM4_INTC_VSSEL143_VSEL18 (*((volatile unsigned int*)(0x42A25348UL))) +#define bM4_INTC_VSSEL143_VSEL19 (*((volatile unsigned int*)(0x42A2534CUL))) +#define bM4_INTC_VSSEL143_VSEL20 (*((volatile unsigned int*)(0x42A25350UL))) +#define bM4_INTC_VSSEL143_VSEL21 (*((volatile unsigned int*)(0x42A25354UL))) +#define bM4_INTC_VSSEL143_VSEL22 (*((volatile unsigned int*)(0x42A25358UL))) +#define bM4_INTC_VSSEL143_VSEL23 (*((volatile unsigned int*)(0x42A2535CUL))) +#define bM4_INTC_VSSEL143_VSEL24 (*((volatile unsigned int*)(0x42A25360UL))) +#define bM4_INTC_VSSEL143_VSEL25 (*((volatile unsigned int*)(0x42A25364UL))) +#define bM4_INTC_VSSEL143_VSEL26 (*((volatile unsigned int*)(0x42A25368UL))) +#define bM4_INTC_VSSEL143_VSEL27 (*((volatile unsigned int*)(0x42A2536CUL))) +#define bM4_INTC_VSSEL143_VSEL28 (*((volatile unsigned int*)(0x42A25370UL))) +#define bM4_INTC_VSSEL143_VSEL29 (*((volatile unsigned int*)(0x42A25374UL))) +#define bM4_INTC_VSSEL143_VSEL30 (*((volatile unsigned int*)(0x42A25378UL))) +#define bM4_INTC_VSSEL143_VSEL31 (*((volatile unsigned int*)(0x42A2537CUL))) +#define bM4_INTC_SWIER_SWIE0 (*((volatile unsigned int*)(0x42A25380UL))) +#define bM4_INTC_SWIER_SWIE1 (*((volatile unsigned int*)(0x42A25384UL))) +#define bM4_INTC_SWIER_SWIE2 (*((volatile unsigned int*)(0x42A25388UL))) +#define bM4_INTC_SWIER_SWIE3 (*((volatile unsigned int*)(0x42A2538CUL))) +#define bM4_INTC_SWIER_SWIE4 (*((volatile unsigned int*)(0x42A25390UL))) +#define bM4_INTC_SWIER_SWIE5 (*((volatile unsigned int*)(0x42A25394UL))) +#define bM4_INTC_SWIER_SWIE6 (*((volatile unsigned int*)(0x42A25398UL))) +#define bM4_INTC_SWIER_SWIE7 (*((volatile unsigned int*)(0x42A2539CUL))) +#define bM4_INTC_SWIER_SWIE8 (*((volatile unsigned int*)(0x42A253A0UL))) +#define bM4_INTC_SWIER_SWIE9 (*((volatile unsigned int*)(0x42A253A4UL))) +#define bM4_INTC_SWIER_SWIE10 (*((volatile unsigned int*)(0x42A253A8UL))) +#define bM4_INTC_SWIER_SWIE11 (*((volatile unsigned int*)(0x42A253ACUL))) +#define bM4_INTC_SWIER_SWIE12 (*((volatile unsigned int*)(0x42A253B0UL))) +#define bM4_INTC_SWIER_SWIE13 (*((volatile unsigned int*)(0x42A253B4UL))) +#define bM4_INTC_SWIER_SWIE14 (*((volatile unsigned int*)(0x42A253B8UL))) +#define bM4_INTC_SWIER_SWIE15 (*((volatile unsigned int*)(0x42A253BCUL))) +#define bM4_INTC_SWIER_SWIE16 (*((volatile unsigned int*)(0x42A253C0UL))) +#define bM4_INTC_SWIER_SWIE17 (*((volatile unsigned int*)(0x42A253C4UL))) +#define bM4_INTC_SWIER_SWIE18 (*((volatile unsigned int*)(0x42A253C8UL))) +#define bM4_INTC_SWIER_SWIE19 (*((volatile unsigned int*)(0x42A253CCUL))) +#define bM4_INTC_SWIER_SWIE20 (*((volatile unsigned int*)(0x42A253D0UL))) +#define bM4_INTC_SWIER_SWIE21 (*((volatile unsigned int*)(0x42A253D4UL))) +#define bM4_INTC_SWIER_SWIE22 (*((volatile unsigned int*)(0x42A253D8UL))) +#define bM4_INTC_SWIER_SWIE23 (*((volatile unsigned int*)(0x42A253DCUL))) +#define bM4_INTC_SWIER_SWIE24 (*((volatile unsigned int*)(0x42A253E0UL))) +#define bM4_INTC_SWIER_SWIE25 (*((volatile unsigned int*)(0x42A253E4UL))) +#define bM4_INTC_SWIER_SWIE26 (*((volatile unsigned int*)(0x42A253E8UL))) +#define bM4_INTC_SWIER_SWIE27 (*((volatile unsigned int*)(0x42A253ECUL))) +#define bM4_INTC_SWIER_SWIE28 (*((volatile unsigned int*)(0x42A253F0UL))) +#define bM4_INTC_SWIER_SWIE29 (*((volatile unsigned int*)(0x42A253F4UL))) +#define bM4_INTC_SWIER_SWIE30 (*((volatile unsigned int*)(0x42A253F8UL))) +#define bM4_INTC_SWIER_SWIE31 (*((volatile unsigned int*)(0x42A253FCUL))) +#define bM4_INTC_EVTER_EVTE0 (*((volatile unsigned int*)(0x42A25400UL))) +#define bM4_INTC_EVTER_EVTE1 (*((volatile unsigned int*)(0x42A25404UL))) +#define bM4_INTC_EVTER_EVTE2 (*((volatile unsigned int*)(0x42A25408UL))) +#define bM4_INTC_EVTER_EVTE3 (*((volatile unsigned int*)(0x42A2540CUL))) +#define bM4_INTC_EVTER_EVTE4 (*((volatile unsigned int*)(0x42A25410UL))) +#define bM4_INTC_EVTER_EVTE5 (*((volatile unsigned int*)(0x42A25414UL))) +#define bM4_INTC_EVTER_EVTE6 (*((volatile unsigned int*)(0x42A25418UL))) +#define bM4_INTC_EVTER_EVTE7 (*((volatile unsigned int*)(0x42A2541CUL))) +#define bM4_INTC_EVTER_EVTE8 (*((volatile unsigned int*)(0x42A25420UL))) +#define bM4_INTC_EVTER_EVTE9 (*((volatile unsigned int*)(0x42A25424UL))) +#define bM4_INTC_EVTER_EVTE10 (*((volatile unsigned int*)(0x42A25428UL))) +#define bM4_INTC_EVTER_EVTE11 (*((volatile unsigned int*)(0x42A2542CUL))) +#define bM4_INTC_EVTER_EVTE12 (*((volatile unsigned int*)(0x42A25430UL))) +#define bM4_INTC_EVTER_EVTE13 (*((volatile unsigned int*)(0x42A25434UL))) +#define bM4_INTC_EVTER_EVTE14 (*((volatile unsigned int*)(0x42A25438UL))) +#define bM4_INTC_EVTER_EVTE15 (*((volatile unsigned int*)(0x42A2543CUL))) +#define bM4_INTC_EVTER_EVTE16 (*((volatile unsigned int*)(0x42A25440UL))) +#define bM4_INTC_EVTER_EVTE17 (*((volatile unsigned int*)(0x42A25444UL))) +#define bM4_INTC_EVTER_EVTE18 (*((volatile unsigned int*)(0x42A25448UL))) +#define bM4_INTC_EVTER_EVTE19 (*((volatile unsigned int*)(0x42A2544CUL))) +#define bM4_INTC_EVTER_EVTE20 (*((volatile unsigned int*)(0x42A25450UL))) +#define bM4_INTC_EVTER_EVTE21 (*((volatile unsigned int*)(0x42A25454UL))) +#define bM4_INTC_EVTER_EVTE22 (*((volatile unsigned int*)(0x42A25458UL))) +#define bM4_INTC_EVTER_EVTE23 (*((volatile unsigned int*)(0x42A2545CUL))) +#define bM4_INTC_EVTER_EVTE24 (*((volatile unsigned int*)(0x42A25460UL))) +#define bM4_INTC_EVTER_EVTE25 (*((volatile unsigned int*)(0x42A25464UL))) +#define bM4_INTC_EVTER_EVTE26 (*((volatile unsigned int*)(0x42A25468UL))) +#define bM4_INTC_EVTER_EVTE27 (*((volatile unsigned int*)(0x42A2546CUL))) +#define bM4_INTC_EVTER_EVTE28 (*((volatile unsigned int*)(0x42A25470UL))) +#define bM4_INTC_EVTER_EVTE29 (*((volatile unsigned int*)(0x42A25474UL))) +#define bM4_INTC_EVTER_EVTE30 (*((volatile unsigned int*)(0x42A25478UL))) +#define bM4_INTC_EVTER_EVTE31 (*((volatile unsigned int*)(0x42A2547CUL))) +#define bM4_INTC_IER_IER0 (*((volatile unsigned int*)(0x42A25480UL))) +#define bM4_INTC_IER_IER1 (*((volatile unsigned int*)(0x42A25484UL))) +#define bM4_INTC_IER_IER2 (*((volatile unsigned int*)(0x42A25488UL))) +#define bM4_INTC_IER_IER3 (*((volatile unsigned int*)(0x42A2548CUL))) +#define bM4_INTC_IER_IER4 (*((volatile unsigned int*)(0x42A25490UL))) +#define bM4_INTC_IER_IER5 (*((volatile unsigned int*)(0x42A25494UL))) +#define bM4_INTC_IER_IER6 (*((volatile unsigned int*)(0x42A25498UL))) +#define bM4_INTC_IER_IER7 (*((volatile unsigned int*)(0x42A2549CUL))) +#define bM4_INTC_IER_IER8 (*((volatile unsigned int*)(0x42A254A0UL))) +#define bM4_INTC_IER_IER9 (*((volatile unsigned int*)(0x42A254A4UL))) +#define bM4_INTC_IER_IER10 (*((volatile unsigned int*)(0x42A254A8UL))) +#define bM4_INTC_IER_IER11 (*((volatile unsigned int*)(0x42A254ACUL))) +#define bM4_INTC_IER_IER12 (*((volatile unsigned int*)(0x42A254B0UL))) +#define bM4_INTC_IER_IER13 (*((volatile unsigned int*)(0x42A254B4UL))) +#define bM4_INTC_IER_IER14 (*((volatile unsigned int*)(0x42A254B8UL))) +#define bM4_INTC_IER_IER15 (*((volatile unsigned int*)(0x42A254BCUL))) +#define bM4_INTC_IER_IER16 (*((volatile unsigned int*)(0x42A254C0UL))) +#define bM4_INTC_IER_IER17 (*((volatile unsigned int*)(0x42A254C4UL))) +#define bM4_INTC_IER_IER18 (*((volatile unsigned int*)(0x42A254C8UL))) +#define bM4_INTC_IER_IER19 (*((volatile unsigned int*)(0x42A254CCUL))) +#define bM4_INTC_IER_IER20 (*((volatile unsigned int*)(0x42A254D0UL))) +#define bM4_INTC_IER_IER21 (*((volatile unsigned int*)(0x42A254D4UL))) +#define bM4_INTC_IER_IER22 (*((volatile unsigned int*)(0x42A254D8UL))) +#define bM4_INTC_IER_IER23 (*((volatile unsigned int*)(0x42A254DCUL))) +#define bM4_INTC_IER_IER24 (*((volatile unsigned int*)(0x42A254E0UL))) +#define bM4_INTC_IER_IER25 (*((volatile unsigned int*)(0x42A254E4UL))) +#define bM4_INTC_IER_IER26 (*((volatile unsigned int*)(0x42A254E8UL))) +#define bM4_INTC_IER_IER27 (*((volatile unsigned int*)(0x42A254ECUL))) +#define bM4_INTC_IER_IER28 (*((volatile unsigned int*)(0x42A254F0UL))) +#define bM4_INTC_IER_IER29 (*((volatile unsigned int*)(0x42A254F4UL))) +#define bM4_INTC_IER_IER30 (*((volatile unsigned int*)(0x42A254F8UL))) +#define bM4_INTC_IER_IER31 (*((volatile unsigned int*)(0x42A254FCUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL0 (*((volatile unsigned int*)(0x42A18000UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL1 (*((volatile unsigned int*)(0x42A18004UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL2 (*((volatile unsigned int*)(0x42A18008UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL3 (*((volatile unsigned int*)(0x42A1800CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL4 (*((volatile unsigned int*)(0x42A18010UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL5 (*((volatile unsigned int*)(0x42A18014UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL6 (*((volatile unsigned int*)(0x42A18018UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL7 (*((volatile unsigned int*)(0x42A1801CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL8 (*((volatile unsigned int*)(0x42A18020UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL9 (*((volatile unsigned int*)(0x42A18024UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL10 (*((volatile unsigned int*)(0x42A18028UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL11 (*((volatile unsigned int*)(0x42A1802CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL12 (*((volatile unsigned int*)(0x42A18030UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL13 (*((volatile unsigned int*)(0x42A18034UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL14 (*((volatile unsigned int*)(0x42A18038UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL15 (*((volatile unsigned int*)(0x42A1803CUL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL0 (*((volatile unsigned int*)(0x42A18040UL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL1 (*((volatile unsigned int*)(0x42A18044UL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL2 (*((volatile unsigned int*)(0x42A18048UL))) +#define bM4_KEYSCAN_SCR_CKSEL0 (*((volatile unsigned int*)(0x42A18050UL))) +#define bM4_KEYSCAN_SCR_CKSEL1 (*((volatile unsigned int*)(0x42A18054UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL0 (*((volatile unsigned int*)(0x42A18060UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL1 (*((volatile unsigned int*)(0x42A18064UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL2 (*((volatile unsigned int*)(0x42A18068UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL3 (*((volatile unsigned int*)(0x42A1806CUL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL4 (*((volatile unsigned int*)(0x42A18070UL))) +#define bM4_KEYSCAN_SCR_T_HIZ0 (*((volatile unsigned int*)(0x42A18074UL))) +#define bM4_KEYSCAN_SCR_T_HIZ1 (*((volatile unsigned int*)(0x42A18078UL))) +#define bM4_KEYSCAN_SCR_T_HIZ2 (*((volatile unsigned int*)(0x42A1807CUL))) +#define bM4_KEYSCAN_SER_SEN (*((volatile unsigned int*)(0x42A18080UL))) +#define bM4_KEYSCAN_SSR_INDEX0 (*((volatile unsigned int*)(0x42A18100UL))) +#define bM4_KEYSCAN_SSR_INDEX1 (*((volatile unsigned int*)(0x42A18104UL))) +#define bM4_KEYSCAN_SSR_INDEX2 (*((volatile unsigned int*)(0x42A18108UL))) +#define bM4_MPU_RGD0_MPURG0SIZE0 (*((volatile unsigned int*)(0x42A00000UL))) +#define bM4_MPU_RGD0_MPURG0SIZE1 (*((volatile unsigned int*)(0x42A00004UL))) +#define bM4_MPU_RGD0_MPURG0SIZE2 (*((volatile unsigned int*)(0x42A00008UL))) +#define bM4_MPU_RGD0_MPURG0SIZE3 (*((volatile unsigned int*)(0x42A0000CUL))) +#define bM4_MPU_RGD0_MPURG0SIZE4 (*((volatile unsigned int*)(0x42A00010UL))) +#define bM4_MPU_RGD0_MPURG0ADDR0 (*((volatile unsigned int*)(0x42A00014UL))) +#define bM4_MPU_RGD0_MPURG0ADDR1 (*((volatile unsigned int*)(0x42A00018UL))) +#define bM4_MPU_RGD0_MPURG0ADDR2 (*((volatile unsigned int*)(0x42A0001CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR3 (*((volatile unsigned int*)(0x42A00020UL))) +#define bM4_MPU_RGD0_MPURG0ADDR4 (*((volatile unsigned int*)(0x42A00024UL))) +#define bM4_MPU_RGD0_MPURG0ADDR5 (*((volatile unsigned int*)(0x42A00028UL))) +#define bM4_MPU_RGD0_MPURG0ADDR6 (*((volatile unsigned int*)(0x42A0002CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR7 (*((volatile unsigned int*)(0x42A00030UL))) +#define bM4_MPU_RGD0_MPURG0ADDR8 (*((volatile unsigned int*)(0x42A00034UL))) +#define bM4_MPU_RGD0_MPURG0ADDR9 (*((volatile unsigned int*)(0x42A00038UL))) +#define bM4_MPU_RGD0_MPURG0ADDR10 (*((volatile unsigned int*)(0x42A0003CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR11 (*((volatile unsigned int*)(0x42A00040UL))) +#define bM4_MPU_RGD0_MPURG0ADDR12 (*((volatile unsigned int*)(0x42A00044UL))) +#define bM4_MPU_RGD0_MPURG0ADDR13 (*((volatile unsigned int*)(0x42A00048UL))) +#define bM4_MPU_RGD0_MPURG0ADDR14 (*((volatile unsigned int*)(0x42A0004CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR15 (*((volatile unsigned int*)(0x42A00050UL))) +#define bM4_MPU_RGD0_MPURG0ADDR16 (*((volatile unsigned int*)(0x42A00054UL))) +#define bM4_MPU_RGD0_MPURG0ADDR17 (*((volatile unsigned int*)(0x42A00058UL))) +#define bM4_MPU_RGD0_MPURG0ADDR18 (*((volatile unsigned int*)(0x42A0005CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR19 (*((volatile unsigned int*)(0x42A00060UL))) +#define bM4_MPU_RGD0_MPURG0ADDR20 (*((volatile unsigned int*)(0x42A00064UL))) +#define bM4_MPU_RGD0_MPURG0ADDR21 (*((volatile unsigned int*)(0x42A00068UL))) +#define bM4_MPU_RGD0_MPURG0ADDR22 (*((volatile unsigned int*)(0x42A0006CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR23 (*((volatile unsigned int*)(0x42A00070UL))) +#define bM4_MPU_RGD0_MPURG0ADDR24 (*((volatile unsigned int*)(0x42A00074UL))) +#define bM4_MPU_RGD0_MPURG0ADDR25 (*((volatile unsigned int*)(0x42A00078UL))) +#define bM4_MPU_RGD0_MPURG0ADDR26 (*((volatile unsigned int*)(0x42A0007CUL))) +#define bM4_MPU_RGD1_MPURG1SIZE0 (*((volatile unsigned int*)(0x42A00080UL))) +#define bM4_MPU_RGD1_MPURG1SIZE1 (*((volatile unsigned int*)(0x42A00084UL))) +#define bM4_MPU_RGD1_MPURG1SIZE2 (*((volatile unsigned int*)(0x42A00088UL))) +#define bM4_MPU_RGD1_MPURG1SIZE3 (*((volatile unsigned int*)(0x42A0008CUL))) +#define bM4_MPU_RGD1_MPURG1SIZE4 (*((volatile unsigned int*)(0x42A00090UL))) +#define bM4_MPU_RGD1_MPURG1ADDR0 (*((volatile unsigned int*)(0x42A00094UL))) +#define bM4_MPU_RGD1_MPURG1ADDR1 (*((volatile unsigned int*)(0x42A00098UL))) +#define bM4_MPU_RGD1_MPURG1ADDR2 (*((volatile unsigned int*)(0x42A0009CUL))) +#define bM4_MPU_RGD1_MPURG1ADDR3 (*((volatile unsigned int*)(0x42A000A0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR4 (*((volatile unsigned int*)(0x42A000A4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR5 (*((volatile unsigned int*)(0x42A000A8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR6 (*((volatile unsigned int*)(0x42A000ACUL))) +#define bM4_MPU_RGD1_MPURG1ADDR7 (*((volatile unsigned int*)(0x42A000B0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR8 (*((volatile unsigned int*)(0x42A000B4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR9 (*((volatile unsigned int*)(0x42A000B8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR10 (*((volatile unsigned int*)(0x42A000BCUL))) +#define bM4_MPU_RGD1_MPURG1ADDR11 (*((volatile unsigned int*)(0x42A000C0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR12 (*((volatile unsigned int*)(0x42A000C4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR13 (*((volatile unsigned int*)(0x42A000C8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR14 (*((volatile unsigned int*)(0x42A000CCUL))) +#define bM4_MPU_RGD1_MPURG1ADDR15 (*((volatile unsigned int*)(0x42A000D0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR16 (*((volatile unsigned int*)(0x42A000D4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR17 (*((volatile unsigned int*)(0x42A000D8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR18 (*((volatile unsigned int*)(0x42A000DCUL))) +#define bM4_MPU_RGD1_MPURG1ADDR19 (*((volatile unsigned int*)(0x42A000E0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR20 (*((volatile unsigned int*)(0x42A000E4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR21 (*((volatile unsigned int*)(0x42A000E8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR22 (*((volatile unsigned int*)(0x42A000ECUL))) +#define bM4_MPU_RGD1_MPURG1ADDR23 (*((volatile unsigned int*)(0x42A000F0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR24 (*((volatile unsigned int*)(0x42A000F4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR25 (*((volatile unsigned int*)(0x42A000F8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR26 (*((volatile unsigned int*)(0x42A000FCUL))) +#define bM4_MPU_RGD2_MPURG2SIZE0 (*((volatile unsigned int*)(0x42A00100UL))) +#define bM4_MPU_RGD2_MPURG2SIZE1 (*((volatile unsigned int*)(0x42A00104UL))) +#define bM4_MPU_RGD2_MPURG2SIZE2 (*((volatile unsigned int*)(0x42A00108UL))) +#define bM4_MPU_RGD2_MPURG2SIZE3 (*((volatile unsigned int*)(0x42A0010CUL))) +#define bM4_MPU_RGD2_MPURG2SIZE4 (*((volatile unsigned int*)(0x42A00110UL))) +#define bM4_MPU_RGD2_MPURG2ADDR0 (*((volatile unsigned int*)(0x42A00114UL))) +#define bM4_MPU_RGD2_MPURG2ADDR1 (*((volatile unsigned int*)(0x42A00118UL))) +#define bM4_MPU_RGD2_MPURG2ADDR2 (*((volatile unsigned int*)(0x42A0011CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR3 (*((volatile unsigned int*)(0x42A00120UL))) +#define bM4_MPU_RGD2_MPURG2ADDR4 (*((volatile unsigned int*)(0x42A00124UL))) +#define bM4_MPU_RGD2_MPURG2ADDR5 (*((volatile unsigned int*)(0x42A00128UL))) +#define bM4_MPU_RGD2_MPURG2ADDR6 (*((volatile unsigned int*)(0x42A0012CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR7 (*((volatile unsigned int*)(0x42A00130UL))) +#define bM4_MPU_RGD2_MPURG2ADDR8 (*((volatile unsigned int*)(0x42A00134UL))) +#define bM4_MPU_RGD2_MPURG2ADDR9 (*((volatile unsigned int*)(0x42A00138UL))) +#define bM4_MPU_RGD2_MPURG2ADDR10 (*((volatile unsigned int*)(0x42A0013CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR11 (*((volatile unsigned int*)(0x42A00140UL))) +#define bM4_MPU_RGD2_MPURG2ADDR12 (*((volatile unsigned int*)(0x42A00144UL))) +#define bM4_MPU_RGD2_MPURG2ADDR13 (*((volatile unsigned int*)(0x42A00148UL))) +#define bM4_MPU_RGD2_MPURG2ADDR14 (*((volatile unsigned int*)(0x42A0014CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR15 (*((volatile unsigned int*)(0x42A00150UL))) +#define bM4_MPU_RGD2_MPURG2ADDR16 (*((volatile unsigned int*)(0x42A00154UL))) +#define bM4_MPU_RGD2_MPURG2ADDR17 (*((volatile unsigned int*)(0x42A00158UL))) +#define bM4_MPU_RGD2_MPURG2ADDR18 (*((volatile unsigned int*)(0x42A0015CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR19 (*((volatile unsigned int*)(0x42A00160UL))) +#define bM4_MPU_RGD2_MPURG2ADDR20 (*((volatile unsigned int*)(0x42A00164UL))) +#define bM4_MPU_RGD2_MPURG2ADDR21 (*((volatile unsigned int*)(0x42A00168UL))) +#define bM4_MPU_RGD2_MPURG2ADDR22 (*((volatile unsigned int*)(0x42A0016CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR23 (*((volatile unsigned int*)(0x42A00170UL))) +#define bM4_MPU_RGD2_MPURG2ADDR24 (*((volatile unsigned int*)(0x42A00174UL))) +#define bM4_MPU_RGD2_MPURG2ADDR25 (*((volatile unsigned int*)(0x42A00178UL))) +#define bM4_MPU_RGD2_MPURG2ADDR26 (*((volatile unsigned int*)(0x42A0017CUL))) +#define bM4_MPU_RGD3_MPURG3SIZE0 (*((volatile unsigned int*)(0x42A00180UL))) +#define bM4_MPU_RGD3_MPURG3SIZE1 (*((volatile unsigned int*)(0x42A00184UL))) +#define bM4_MPU_RGD3_MPURG3SIZE2 (*((volatile unsigned int*)(0x42A00188UL))) +#define bM4_MPU_RGD3_MPURG3SIZE3 (*((volatile unsigned int*)(0x42A0018CUL))) +#define bM4_MPU_RGD3_MPURG3SIZE4 (*((volatile unsigned int*)(0x42A00190UL))) +#define bM4_MPU_RGD3_MPURG3ADDR0 (*((volatile unsigned int*)(0x42A00194UL))) +#define bM4_MPU_RGD3_MPURG3ADDR1 (*((volatile unsigned int*)(0x42A00198UL))) +#define bM4_MPU_RGD3_MPURG3ADDR2 (*((volatile unsigned int*)(0x42A0019CUL))) +#define bM4_MPU_RGD3_MPURG3ADDR3 (*((volatile unsigned int*)(0x42A001A0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR4 (*((volatile unsigned int*)(0x42A001A4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR5 (*((volatile unsigned int*)(0x42A001A8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR6 (*((volatile unsigned int*)(0x42A001ACUL))) +#define bM4_MPU_RGD3_MPURG3ADDR7 (*((volatile unsigned int*)(0x42A001B0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR8 (*((volatile unsigned int*)(0x42A001B4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR9 (*((volatile unsigned int*)(0x42A001B8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR10 (*((volatile unsigned int*)(0x42A001BCUL))) +#define bM4_MPU_RGD3_MPURG3ADDR11 (*((volatile unsigned int*)(0x42A001C0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR12 (*((volatile unsigned int*)(0x42A001C4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR13 (*((volatile unsigned int*)(0x42A001C8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR14 (*((volatile unsigned int*)(0x42A001CCUL))) +#define bM4_MPU_RGD3_MPURG3ADDR15 (*((volatile unsigned int*)(0x42A001D0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR16 (*((volatile unsigned int*)(0x42A001D4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR17 (*((volatile unsigned int*)(0x42A001D8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR18 (*((volatile unsigned int*)(0x42A001DCUL))) +#define bM4_MPU_RGD3_MPURG3ADDR19 (*((volatile unsigned int*)(0x42A001E0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR20 (*((volatile unsigned int*)(0x42A001E4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR21 (*((volatile unsigned int*)(0x42A001E8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR22 (*((volatile unsigned int*)(0x42A001ECUL))) +#define bM4_MPU_RGD3_MPURG3ADDR23 (*((volatile unsigned int*)(0x42A001F0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR24 (*((volatile unsigned int*)(0x42A001F4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR25 (*((volatile unsigned int*)(0x42A001F8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR26 (*((volatile unsigned int*)(0x42A001FCUL))) +#define bM4_MPU_RGD4_MPURG4SIZE0 (*((volatile unsigned int*)(0x42A00200UL))) +#define bM4_MPU_RGD4_MPURG4SIZE1 (*((volatile unsigned int*)(0x42A00204UL))) +#define bM4_MPU_RGD4_MPURG4SIZE2 (*((volatile unsigned int*)(0x42A00208UL))) +#define bM4_MPU_RGD4_MPURG4SIZE3 (*((volatile unsigned int*)(0x42A0020CUL))) +#define bM4_MPU_RGD4_MPURG4SIZE4 (*((volatile unsigned int*)(0x42A00210UL))) +#define bM4_MPU_RGD4_MPURG4ADDR0 (*((volatile unsigned int*)(0x42A00214UL))) +#define bM4_MPU_RGD4_MPURG4ADDR1 (*((volatile unsigned int*)(0x42A00218UL))) +#define bM4_MPU_RGD4_MPURG4ADDR2 (*((volatile unsigned int*)(0x42A0021CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR3 (*((volatile unsigned int*)(0x42A00220UL))) +#define bM4_MPU_RGD4_MPURG4ADDR4 (*((volatile unsigned int*)(0x42A00224UL))) +#define bM4_MPU_RGD4_MPURG4ADDR5 (*((volatile unsigned int*)(0x42A00228UL))) +#define bM4_MPU_RGD4_MPURG4ADDR6 (*((volatile unsigned int*)(0x42A0022CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR7 (*((volatile unsigned int*)(0x42A00230UL))) +#define bM4_MPU_RGD4_MPURG4ADDR8 (*((volatile unsigned int*)(0x42A00234UL))) +#define bM4_MPU_RGD4_MPURG4ADDR9 (*((volatile unsigned int*)(0x42A00238UL))) +#define bM4_MPU_RGD4_MPURG4ADDR10 (*((volatile unsigned int*)(0x42A0023CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR11 (*((volatile unsigned int*)(0x42A00240UL))) +#define bM4_MPU_RGD4_MPURG4ADDR12 (*((volatile unsigned int*)(0x42A00244UL))) +#define bM4_MPU_RGD4_MPURG4ADDR13 (*((volatile unsigned int*)(0x42A00248UL))) +#define bM4_MPU_RGD4_MPURG4ADDR14 (*((volatile unsigned int*)(0x42A0024CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR15 (*((volatile unsigned int*)(0x42A00250UL))) +#define bM4_MPU_RGD4_MPURG4ADDR16 (*((volatile unsigned int*)(0x42A00254UL))) +#define bM4_MPU_RGD4_MPURG4ADDR17 (*((volatile unsigned int*)(0x42A00258UL))) +#define bM4_MPU_RGD4_MPURG4ADDR18 (*((volatile unsigned int*)(0x42A0025CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR19 (*((volatile unsigned int*)(0x42A00260UL))) +#define bM4_MPU_RGD4_MPURG4ADDR20 (*((volatile unsigned int*)(0x42A00264UL))) +#define bM4_MPU_RGD4_MPURG4ADDR21 (*((volatile unsigned int*)(0x42A00268UL))) +#define bM4_MPU_RGD4_MPURG4ADDR22 (*((volatile unsigned int*)(0x42A0026CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR23 (*((volatile unsigned int*)(0x42A00270UL))) +#define bM4_MPU_RGD4_MPURG4ADDR24 (*((volatile unsigned int*)(0x42A00274UL))) +#define bM4_MPU_RGD4_MPURG4ADDR25 (*((volatile unsigned int*)(0x42A00278UL))) +#define bM4_MPU_RGD4_MPURG4ADDR26 (*((volatile unsigned int*)(0x42A0027CUL))) +#define bM4_MPU_RGD5_MPURG5SIZE0 (*((volatile unsigned int*)(0x42A00280UL))) +#define bM4_MPU_RGD5_MPURG5SIZE1 (*((volatile unsigned int*)(0x42A00284UL))) +#define bM4_MPU_RGD5_MPURG5SIZE2 (*((volatile unsigned int*)(0x42A00288UL))) +#define bM4_MPU_RGD5_MPURG5SIZE3 (*((volatile unsigned int*)(0x42A0028CUL))) +#define bM4_MPU_RGD5_MPURG5SIZE4 (*((volatile unsigned int*)(0x42A00290UL))) +#define bM4_MPU_RGD5_MPURG5ADDR0 (*((volatile unsigned int*)(0x42A00294UL))) +#define bM4_MPU_RGD5_MPURG5ADDR1 (*((volatile unsigned int*)(0x42A00298UL))) +#define bM4_MPU_RGD5_MPURG5ADDR2 (*((volatile unsigned int*)(0x42A0029CUL))) +#define bM4_MPU_RGD5_MPURG5ADDR3 (*((volatile unsigned int*)(0x42A002A0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR4 (*((volatile unsigned int*)(0x42A002A4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR5 (*((volatile unsigned int*)(0x42A002A8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR6 (*((volatile unsigned int*)(0x42A002ACUL))) +#define bM4_MPU_RGD5_MPURG5ADDR7 (*((volatile unsigned int*)(0x42A002B0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR8 (*((volatile unsigned int*)(0x42A002B4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR9 (*((volatile unsigned int*)(0x42A002B8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR10 (*((volatile unsigned int*)(0x42A002BCUL))) +#define bM4_MPU_RGD5_MPURG5ADDR11 (*((volatile unsigned int*)(0x42A002C0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR12 (*((volatile unsigned int*)(0x42A002C4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR13 (*((volatile unsigned int*)(0x42A002C8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR14 (*((volatile unsigned int*)(0x42A002CCUL))) +#define bM4_MPU_RGD5_MPURG5ADDR15 (*((volatile unsigned int*)(0x42A002D0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR16 (*((volatile unsigned int*)(0x42A002D4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR17 (*((volatile unsigned int*)(0x42A002D8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR18 (*((volatile unsigned int*)(0x42A002DCUL))) +#define bM4_MPU_RGD5_MPURG5ADDR19 (*((volatile unsigned int*)(0x42A002E0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR20 (*((volatile unsigned int*)(0x42A002E4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR21 (*((volatile unsigned int*)(0x42A002E8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR22 (*((volatile unsigned int*)(0x42A002ECUL))) +#define bM4_MPU_RGD5_MPURG5ADDR23 (*((volatile unsigned int*)(0x42A002F0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR24 (*((volatile unsigned int*)(0x42A002F4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR25 (*((volatile unsigned int*)(0x42A002F8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR26 (*((volatile unsigned int*)(0x42A002FCUL))) +#define bM4_MPU_RGD6_MPURG6SIZE0 (*((volatile unsigned int*)(0x42A00300UL))) +#define bM4_MPU_RGD6_MPURG6SIZE1 (*((volatile unsigned int*)(0x42A00304UL))) +#define bM4_MPU_RGD6_MPURG6SIZE2 (*((volatile unsigned int*)(0x42A00308UL))) +#define bM4_MPU_RGD6_MPURG6SIZE3 (*((volatile unsigned int*)(0x42A0030CUL))) +#define bM4_MPU_RGD6_MPURG6SIZE4 (*((volatile unsigned int*)(0x42A00310UL))) +#define bM4_MPU_RGD6_MPURG6ADDR0 (*((volatile unsigned int*)(0x42A00314UL))) +#define bM4_MPU_RGD6_MPURG6ADDR1 (*((volatile unsigned int*)(0x42A00318UL))) +#define bM4_MPU_RGD6_MPURG6ADDR2 (*((volatile unsigned int*)(0x42A0031CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR3 (*((volatile unsigned int*)(0x42A00320UL))) +#define bM4_MPU_RGD6_MPURG6ADDR4 (*((volatile unsigned int*)(0x42A00324UL))) +#define bM4_MPU_RGD6_MPURG6ADDR5 (*((volatile unsigned int*)(0x42A00328UL))) +#define bM4_MPU_RGD6_MPURG6ADDR6 (*((volatile unsigned int*)(0x42A0032CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR7 (*((volatile unsigned int*)(0x42A00330UL))) +#define bM4_MPU_RGD6_MPURG6ADDR8 (*((volatile unsigned int*)(0x42A00334UL))) +#define bM4_MPU_RGD6_MPURG6ADDR9 (*((volatile unsigned int*)(0x42A00338UL))) +#define bM4_MPU_RGD6_MPURG6ADDR10 (*((volatile unsigned int*)(0x42A0033CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR11 (*((volatile unsigned int*)(0x42A00340UL))) +#define bM4_MPU_RGD6_MPURG6ADDR12 (*((volatile unsigned int*)(0x42A00344UL))) +#define bM4_MPU_RGD6_MPURG6ADDR13 (*((volatile unsigned int*)(0x42A00348UL))) +#define bM4_MPU_RGD6_MPURG6ADDR14 (*((volatile unsigned int*)(0x42A0034CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR15 (*((volatile unsigned int*)(0x42A00350UL))) +#define bM4_MPU_RGD6_MPURG6ADDR16 (*((volatile unsigned int*)(0x42A00354UL))) +#define bM4_MPU_RGD6_MPURG6ADDR17 (*((volatile unsigned int*)(0x42A00358UL))) +#define bM4_MPU_RGD6_MPURG6ADDR18 (*((volatile unsigned int*)(0x42A0035CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR19 (*((volatile unsigned int*)(0x42A00360UL))) +#define bM4_MPU_RGD6_MPURG6ADDR20 (*((volatile unsigned int*)(0x42A00364UL))) +#define bM4_MPU_RGD6_MPURG6ADDR21 (*((volatile unsigned int*)(0x42A00368UL))) +#define bM4_MPU_RGD6_MPURG6ADDR22 (*((volatile unsigned int*)(0x42A0036CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR23 (*((volatile unsigned int*)(0x42A00370UL))) +#define bM4_MPU_RGD6_MPURG6ADDR24 (*((volatile unsigned int*)(0x42A00374UL))) +#define bM4_MPU_RGD6_MPURG6ADDR25 (*((volatile unsigned int*)(0x42A00378UL))) +#define bM4_MPU_RGD6_MPURG6ADDR26 (*((volatile unsigned int*)(0x42A0037CUL))) +#define bM4_MPU_RGD7_MPURG7SIZE0 (*((volatile unsigned int*)(0x42A00380UL))) +#define bM4_MPU_RGD7_MPURG7SIZE1 (*((volatile unsigned int*)(0x42A00384UL))) +#define bM4_MPU_RGD7_MPURG7SIZE2 (*((volatile unsigned int*)(0x42A00388UL))) +#define bM4_MPU_RGD7_MPURG7SIZE3 (*((volatile unsigned int*)(0x42A0038CUL))) +#define bM4_MPU_RGD7_MPURG7SIZE4 (*((volatile unsigned int*)(0x42A00390UL))) +#define bM4_MPU_RGD7_MPURG7ADDR0 (*((volatile unsigned int*)(0x42A00394UL))) +#define bM4_MPU_RGD7_MPURG7ADDR1 (*((volatile unsigned int*)(0x42A00398UL))) +#define bM4_MPU_RGD7_MPURG7ADDR2 (*((volatile unsigned int*)(0x42A0039CUL))) +#define bM4_MPU_RGD7_MPURG7ADDR3 (*((volatile unsigned int*)(0x42A003A0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR4 (*((volatile unsigned int*)(0x42A003A4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR5 (*((volatile unsigned int*)(0x42A003A8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR6 (*((volatile unsigned int*)(0x42A003ACUL))) +#define bM4_MPU_RGD7_MPURG7ADDR7 (*((volatile unsigned int*)(0x42A003B0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR8 (*((volatile unsigned int*)(0x42A003B4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR9 (*((volatile unsigned int*)(0x42A003B8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR10 (*((volatile unsigned int*)(0x42A003BCUL))) +#define bM4_MPU_RGD7_MPURG7ADDR11 (*((volatile unsigned int*)(0x42A003C0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR12 (*((volatile unsigned int*)(0x42A003C4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR13 (*((volatile unsigned int*)(0x42A003C8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR14 (*((volatile unsigned int*)(0x42A003CCUL))) +#define bM4_MPU_RGD7_MPURG7ADDR15 (*((volatile unsigned int*)(0x42A003D0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR16 (*((volatile unsigned int*)(0x42A003D4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR17 (*((volatile unsigned int*)(0x42A003D8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR18 (*((volatile unsigned int*)(0x42A003DCUL))) +#define bM4_MPU_RGD7_MPURG7ADDR19 (*((volatile unsigned int*)(0x42A003E0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR20 (*((volatile unsigned int*)(0x42A003E4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR21 (*((volatile unsigned int*)(0x42A003E8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR22 (*((volatile unsigned int*)(0x42A003ECUL))) +#define bM4_MPU_RGD7_MPURG7ADDR23 (*((volatile unsigned int*)(0x42A003F0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR24 (*((volatile unsigned int*)(0x42A003F4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR25 (*((volatile unsigned int*)(0x42A003F8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR26 (*((volatile unsigned int*)(0x42A003FCUL))) +#define bM4_MPU_RGD8_MPURG8SIZE0 (*((volatile unsigned int*)(0x42A00400UL))) +#define bM4_MPU_RGD8_MPURG8SIZE1 (*((volatile unsigned int*)(0x42A00404UL))) +#define bM4_MPU_RGD8_MPURG8SIZE2 (*((volatile unsigned int*)(0x42A00408UL))) +#define bM4_MPU_RGD8_MPURG8SIZE3 (*((volatile unsigned int*)(0x42A0040CUL))) +#define bM4_MPU_RGD8_MPURG8SIZE4 (*((volatile unsigned int*)(0x42A00410UL))) +#define bM4_MPU_RGD8_MPURG8ADDR0 (*((volatile unsigned int*)(0x42A00414UL))) +#define bM4_MPU_RGD8_MPURG8ADDR1 (*((volatile unsigned int*)(0x42A00418UL))) +#define bM4_MPU_RGD8_MPURG8ADDR2 (*((volatile unsigned int*)(0x42A0041CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR3 (*((volatile unsigned int*)(0x42A00420UL))) +#define bM4_MPU_RGD8_MPURG8ADDR4 (*((volatile unsigned int*)(0x42A00424UL))) +#define bM4_MPU_RGD8_MPURG8ADDR5 (*((volatile unsigned int*)(0x42A00428UL))) +#define bM4_MPU_RGD8_MPURG8ADDR6 (*((volatile unsigned int*)(0x42A0042CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR7 (*((volatile unsigned int*)(0x42A00430UL))) +#define bM4_MPU_RGD8_MPURG8ADDR8 (*((volatile unsigned int*)(0x42A00434UL))) +#define bM4_MPU_RGD8_MPURG8ADDR9 (*((volatile unsigned int*)(0x42A00438UL))) +#define bM4_MPU_RGD8_MPURG8ADDR10 (*((volatile unsigned int*)(0x42A0043CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR11 (*((volatile unsigned int*)(0x42A00440UL))) +#define bM4_MPU_RGD8_MPURG8ADDR12 (*((volatile unsigned int*)(0x42A00444UL))) +#define bM4_MPU_RGD8_MPURG8ADDR13 (*((volatile unsigned int*)(0x42A00448UL))) +#define bM4_MPU_RGD8_MPURG8ADDR14 (*((volatile unsigned int*)(0x42A0044CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR15 (*((volatile unsigned int*)(0x42A00450UL))) +#define bM4_MPU_RGD8_MPURG8ADDR16 (*((volatile unsigned int*)(0x42A00454UL))) +#define bM4_MPU_RGD8_MPURG8ADDR17 (*((volatile unsigned int*)(0x42A00458UL))) +#define bM4_MPU_RGD8_MPURG8ADDR18 (*((volatile unsigned int*)(0x42A0045CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR19 (*((volatile unsigned int*)(0x42A00460UL))) +#define bM4_MPU_RGD8_MPURG8ADDR20 (*((volatile unsigned int*)(0x42A00464UL))) +#define bM4_MPU_RGD8_MPURG8ADDR21 (*((volatile unsigned int*)(0x42A00468UL))) +#define bM4_MPU_RGD8_MPURG8ADDR22 (*((volatile unsigned int*)(0x42A0046CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR23 (*((volatile unsigned int*)(0x42A00470UL))) +#define bM4_MPU_RGD8_MPURG8ADDR24 (*((volatile unsigned int*)(0x42A00474UL))) +#define bM4_MPU_RGD8_MPURG8ADDR25 (*((volatile unsigned int*)(0x42A00478UL))) +#define bM4_MPU_RGD8_MPURG8ADDR26 (*((volatile unsigned int*)(0x42A0047CUL))) +#define bM4_MPU_RGD9_MPURG9SIZE0 (*((volatile unsigned int*)(0x42A00480UL))) +#define bM4_MPU_RGD9_MPURG9SIZE1 (*((volatile unsigned int*)(0x42A00484UL))) +#define bM4_MPU_RGD9_MPURG9SIZE2 (*((volatile unsigned int*)(0x42A00488UL))) +#define bM4_MPU_RGD9_MPURG9SIZE3 (*((volatile unsigned int*)(0x42A0048CUL))) +#define bM4_MPU_RGD9_MPURG9SIZE4 (*((volatile unsigned int*)(0x42A00490UL))) +#define bM4_MPU_RGD9_MPURG9ADDR0 (*((volatile unsigned int*)(0x42A00494UL))) +#define bM4_MPU_RGD9_MPURG9ADDR1 (*((volatile unsigned int*)(0x42A00498UL))) +#define bM4_MPU_RGD9_MPURG9ADDR2 (*((volatile unsigned int*)(0x42A0049CUL))) +#define bM4_MPU_RGD9_MPURG9ADDR3 (*((volatile unsigned int*)(0x42A004A0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR4 (*((volatile unsigned int*)(0x42A004A4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR5 (*((volatile unsigned int*)(0x42A004A8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR6 (*((volatile unsigned int*)(0x42A004ACUL))) +#define bM4_MPU_RGD9_MPURG9ADDR7 (*((volatile unsigned int*)(0x42A004B0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR8 (*((volatile unsigned int*)(0x42A004B4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR9 (*((volatile unsigned int*)(0x42A004B8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR10 (*((volatile unsigned int*)(0x42A004BCUL))) +#define bM4_MPU_RGD9_MPURG9ADDR11 (*((volatile unsigned int*)(0x42A004C0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR12 (*((volatile unsigned int*)(0x42A004C4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR13 (*((volatile unsigned int*)(0x42A004C8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR14 (*((volatile unsigned int*)(0x42A004CCUL))) +#define bM4_MPU_RGD9_MPURG9ADDR15 (*((volatile unsigned int*)(0x42A004D0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR16 (*((volatile unsigned int*)(0x42A004D4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR17 (*((volatile unsigned int*)(0x42A004D8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR18 (*((volatile unsigned int*)(0x42A004DCUL))) +#define bM4_MPU_RGD9_MPURG9ADDR19 (*((volatile unsigned int*)(0x42A004E0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR20 (*((volatile unsigned int*)(0x42A004E4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR21 (*((volatile unsigned int*)(0x42A004E8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR22 (*((volatile unsigned int*)(0x42A004ECUL))) +#define bM4_MPU_RGD9_MPURG9ADDR23 (*((volatile unsigned int*)(0x42A004F0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR24 (*((volatile unsigned int*)(0x42A004F4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR25 (*((volatile unsigned int*)(0x42A004F8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR26 (*((volatile unsigned int*)(0x42A004FCUL))) +#define bM4_MPU_RGD10_MPURG10SIZE0 (*((volatile unsigned int*)(0x42A00500UL))) +#define bM4_MPU_RGD10_MPURG10SIZE1 (*((volatile unsigned int*)(0x42A00504UL))) +#define bM4_MPU_RGD10_MPURG10SIZE2 (*((volatile unsigned int*)(0x42A00508UL))) +#define bM4_MPU_RGD10_MPURG10SIZE3 (*((volatile unsigned int*)(0x42A0050CUL))) +#define bM4_MPU_RGD10_MPURG10SIZE4 (*((volatile unsigned int*)(0x42A00510UL))) +#define bM4_MPU_RGD10_MPURG10ADDR0 (*((volatile unsigned int*)(0x42A00514UL))) +#define bM4_MPU_RGD10_MPURG10ADDR1 (*((volatile unsigned int*)(0x42A00518UL))) +#define bM4_MPU_RGD10_MPURG10ADDR2 (*((volatile unsigned int*)(0x42A0051CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR3 (*((volatile unsigned int*)(0x42A00520UL))) +#define bM4_MPU_RGD10_MPURG10ADDR4 (*((volatile unsigned int*)(0x42A00524UL))) +#define bM4_MPU_RGD10_MPURG10ADDR5 (*((volatile unsigned int*)(0x42A00528UL))) +#define bM4_MPU_RGD10_MPURG10ADDR6 (*((volatile unsigned int*)(0x42A0052CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR7 (*((volatile unsigned int*)(0x42A00530UL))) +#define bM4_MPU_RGD10_MPURG10ADDR8 (*((volatile unsigned int*)(0x42A00534UL))) +#define bM4_MPU_RGD10_MPURG10ADDR9 (*((volatile unsigned int*)(0x42A00538UL))) +#define bM4_MPU_RGD10_MPURG10ADDR10 (*((volatile unsigned int*)(0x42A0053CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR11 (*((volatile unsigned int*)(0x42A00540UL))) +#define bM4_MPU_RGD10_MPURG10ADDR12 (*((volatile unsigned int*)(0x42A00544UL))) +#define bM4_MPU_RGD10_MPURG10ADDR13 (*((volatile unsigned int*)(0x42A00548UL))) +#define bM4_MPU_RGD10_MPURG10ADDR14 (*((volatile unsigned int*)(0x42A0054CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR15 (*((volatile unsigned int*)(0x42A00550UL))) +#define bM4_MPU_RGD10_MPURG10ADDR16 (*((volatile unsigned int*)(0x42A00554UL))) +#define bM4_MPU_RGD10_MPURG10ADDR17 (*((volatile unsigned int*)(0x42A00558UL))) +#define bM4_MPU_RGD10_MPURG10ADDR18 (*((volatile unsigned int*)(0x42A0055CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR19 (*((volatile unsigned int*)(0x42A00560UL))) +#define bM4_MPU_RGD10_MPURG10ADDR20 (*((volatile unsigned int*)(0x42A00564UL))) +#define bM4_MPU_RGD10_MPURG10ADDR21 (*((volatile unsigned int*)(0x42A00568UL))) +#define bM4_MPU_RGD10_MPURG10ADDR22 (*((volatile unsigned int*)(0x42A0056CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR23 (*((volatile unsigned int*)(0x42A00570UL))) +#define bM4_MPU_RGD10_MPURG10ADDR24 (*((volatile unsigned int*)(0x42A00574UL))) +#define bM4_MPU_RGD10_MPURG10ADDR25 (*((volatile unsigned int*)(0x42A00578UL))) +#define bM4_MPU_RGD10_MPURG10ADDR26 (*((volatile unsigned int*)(0x42A0057CUL))) +#define bM4_MPU_RGD11_MPURG11SIZE0 (*((volatile unsigned int*)(0x42A00580UL))) +#define bM4_MPU_RGD11_MPURG11SIZE1 (*((volatile unsigned int*)(0x42A00584UL))) +#define bM4_MPU_RGD11_MPURG11SIZE2 (*((volatile unsigned int*)(0x42A00588UL))) +#define bM4_MPU_RGD11_MPURG11SIZE3 (*((volatile unsigned int*)(0x42A0058CUL))) +#define bM4_MPU_RGD11_MPURG11SIZE4 (*((volatile unsigned int*)(0x42A00590UL))) +#define bM4_MPU_RGD11_MPURG11ADDR0 (*((volatile unsigned int*)(0x42A00594UL))) +#define bM4_MPU_RGD11_MPURG11ADDR1 (*((volatile unsigned int*)(0x42A00598UL))) +#define bM4_MPU_RGD11_MPURG11ADDR2 (*((volatile unsigned int*)(0x42A0059CUL))) +#define bM4_MPU_RGD11_MPURG11ADDR3 (*((volatile unsigned int*)(0x42A005A0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR4 (*((volatile unsigned int*)(0x42A005A4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR5 (*((volatile unsigned int*)(0x42A005A8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR6 (*((volatile unsigned int*)(0x42A005ACUL))) +#define bM4_MPU_RGD11_MPURG11ADDR7 (*((volatile unsigned int*)(0x42A005B0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR8 (*((volatile unsigned int*)(0x42A005B4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR9 (*((volatile unsigned int*)(0x42A005B8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR10 (*((volatile unsigned int*)(0x42A005BCUL))) +#define bM4_MPU_RGD11_MPURG11ADDR11 (*((volatile unsigned int*)(0x42A005C0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR12 (*((volatile unsigned int*)(0x42A005C4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR13 (*((volatile unsigned int*)(0x42A005C8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR14 (*((volatile unsigned int*)(0x42A005CCUL))) +#define bM4_MPU_RGD11_MPURG11ADDR15 (*((volatile unsigned int*)(0x42A005D0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR16 (*((volatile unsigned int*)(0x42A005D4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR17 (*((volatile unsigned int*)(0x42A005D8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR18 (*((volatile unsigned int*)(0x42A005DCUL))) +#define bM4_MPU_RGD11_MPURG11ADDR19 (*((volatile unsigned int*)(0x42A005E0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR20 (*((volatile unsigned int*)(0x42A005E4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR21 (*((volatile unsigned int*)(0x42A005E8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR22 (*((volatile unsigned int*)(0x42A005ECUL))) +#define bM4_MPU_RGD11_MPURG11ADDR23 (*((volatile unsigned int*)(0x42A005F0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR24 (*((volatile unsigned int*)(0x42A005F4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR25 (*((volatile unsigned int*)(0x42A005F8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR26 (*((volatile unsigned int*)(0x42A005FCUL))) +#define bM4_MPU_RGD12_MPURG12SIZE0 (*((volatile unsigned int*)(0x42A00600UL))) +#define bM4_MPU_RGD12_MPURG12SIZE1 (*((volatile unsigned int*)(0x42A00604UL))) +#define bM4_MPU_RGD12_MPURG12SIZE2 (*((volatile unsigned int*)(0x42A00608UL))) +#define bM4_MPU_RGD12_MPURG12SIZE3 (*((volatile unsigned int*)(0x42A0060CUL))) +#define bM4_MPU_RGD12_MPURG12SIZE4 (*((volatile unsigned int*)(0x42A00610UL))) +#define bM4_MPU_RGD12_MPURG12ADDR0 (*((volatile unsigned int*)(0x42A00614UL))) +#define bM4_MPU_RGD12_MPURG12ADDR1 (*((volatile unsigned int*)(0x42A00618UL))) +#define bM4_MPU_RGD12_MPURG12ADDR2 (*((volatile unsigned int*)(0x42A0061CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR3 (*((volatile unsigned int*)(0x42A00620UL))) +#define bM4_MPU_RGD12_MPURG12ADDR4 (*((volatile unsigned int*)(0x42A00624UL))) +#define bM4_MPU_RGD12_MPURG12ADDR5 (*((volatile unsigned int*)(0x42A00628UL))) +#define bM4_MPU_RGD12_MPURG12ADDR6 (*((volatile unsigned int*)(0x42A0062CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR7 (*((volatile unsigned int*)(0x42A00630UL))) +#define bM4_MPU_RGD12_MPURG12ADDR8 (*((volatile unsigned int*)(0x42A00634UL))) +#define bM4_MPU_RGD12_MPURG12ADDR9 (*((volatile unsigned int*)(0x42A00638UL))) +#define bM4_MPU_RGD12_MPURG12ADDR10 (*((volatile unsigned int*)(0x42A0063CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR11 (*((volatile unsigned int*)(0x42A00640UL))) +#define bM4_MPU_RGD12_MPURG12ADDR12 (*((volatile unsigned int*)(0x42A00644UL))) +#define bM4_MPU_RGD12_MPURG12ADDR13 (*((volatile unsigned int*)(0x42A00648UL))) +#define bM4_MPU_RGD12_MPURG12ADDR14 (*((volatile unsigned int*)(0x42A0064CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR15 (*((volatile unsigned int*)(0x42A00650UL))) +#define bM4_MPU_RGD12_MPURG12ADDR16 (*((volatile unsigned int*)(0x42A00654UL))) +#define bM4_MPU_RGD12_MPURG12ADDR17 (*((volatile unsigned int*)(0x42A00658UL))) +#define bM4_MPU_RGD12_MPURG12ADDR18 (*((volatile unsigned int*)(0x42A0065CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR19 (*((volatile unsigned int*)(0x42A00660UL))) +#define bM4_MPU_RGD12_MPURG12ADDR20 (*((volatile unsigned int*)(0x42A00664UL))) +#define bM4_MPU_RGD12_MPURG12ADDR21 (*((volatile unsigned int*)(0x42A00668UL))) +#define bM4_MPU_RGD12_MPURG12ADDR22 (*((volatile unsigned int*)(0x42A0066CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR23 (*((volatile unsigned int*)(0x42A00670UL))) +#define bM4_MPU_RGD12_MPURG12ADDR24 (*((volatile unsigned int*)(0x42A00674UL))) +#define bM4_MPU_RGD12_MPURG12ADDR25 (*((volatile unsigned int*)(0x42A00678UL))) +#define bM4_MPU_RGD12_MPURG12ADDR26 (*((volatile unsigned int*)(0x42A0067CUL))) +#define bM4_MPU_RGD13_MPURG13SIZE0 (*((volatile unsigned int*)(0x42A00680UL))) +#define bM4_MPU_RGD13_MPURG13SIZE1 (*((volatile unsigned int*)(0x42A00684UL))) +#define bM4_MPU_RGD13_MPURG13SIZE2 (*((volatile unsigned int*)(0x42A00688UL))) +#define bM4_MPU_RGD13_MPURG13SIZE3 (*((volatile unsigned int*)(0x42A0068CUL))) +#define bM4_MPU_RGD13_MPURG13SIZE4 (*((volatile unsigned int*)(0x42A00690UL))) +#define bM4_MPU_RGD13_MPURG13ADDR0 (*((volatile unsigned int*)(0x42A00694UL))) +#define bM4_MPU_RGD13_MPURG13ADDR1 (*((volatile unsigned int*)(0x42A00698UL))) +#define bM4_MPU_RGD13_MPURG13ADDR2 (*((volatile unsigned int*)(0x42A0069CUL))) +#define bM4_MPU_RGD13_MPURG13ADDR3 (*((volatile unsigned int*)(0x42A006A0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR4 (*((volatile unsigned int*)(0x42A006A4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR5 (*((volatile unsigned int*)(0x42A006A8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR6 (*((volatile unsigned int*)(0x42A006ACUL))) +#define bM4_MPU_RGD13_MPURG13ADDR7 (*((volatile unsigned int*)(0x42A006B0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR8 (*((volatile unsigned int*)(0x42A006B4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR9 (*((volatile unsigned int*)(0x42A006B8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR10 (*((volatile unsigned int*)(0x42A006BCUL))) +#define bM4_MPU_RGD13_MPURG13ADDR11 (*((volatile unsigned int*)(0x42A006C0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR12 (*((volatile unsigned int*)(0x42A006C4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR13 (*((volatile unsigned int*)(0x42A006C8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR14 (*((volatile unsigned int*)(0x42A006CCUL))) +#define bM4_MPU_RGD13_MPURG13ADDR15 (*((volatile unsigned int*)(0x42A006D0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR16 (*((volatile unsigned int*)(0x42A006D4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR17 (*((volatile unsigned int*)(0x42A006D8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR18 (*((volatile unsigned int*)(0x42A006DCUL))) +#define bM4_MPU_RGD13_MPURG13ADDR19 (*((volatile unsigned int*)(0x42A006E0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR20 (*((volatile unsigned int*)(0x42A006E4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR21 (*((volatile unsigned int*)(0x42A006E8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR22 (*((volatile unsigned int*)(0x42A006ECUL))) +#define bM4_MPU_RGD13_MPURG13ADDR23 (*((volatile unsigned int*)(0x42A006F0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR24 (*((volatile unsigned int*)(0x42A006F4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR25 (*((volatile unsigned int*)(0x42A006F8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR26 (*((volatile unsigned int*)(0x42A006FCUL))) +#define bM4_MPU_RGD14_MPURG14SIZE0 (*((volatile unsigned int*)(0x42A00700UL))) +#define bM4_MPU_RGD14_MPURG14SIZE1 (*((volatile unsigned int*)(0x42A00704UL))) +#define bM4_MPU_RGD14_MPURG14SIZE2 (*((volatile unsigned int*)(0x42A00708UL))) +#define bM4_MPU_RGD14_MPURG14SIZE3 (*((volatile unsigned int*)(0x42A0070CUL))) +#define bM4_MPU_RGD14_MPURG14SIZE4 (*((volatile unsigned int*)(0x42A00710UL))) +#define bM4_MPU_RGD14_MPURG14ADDR0 (*((volatile unsigned int*)(0x42A00714UL))) +#define bM4_MPU_RGD14_MPURG14ADDR1 (*((volatile unsigned int*)(0x42A00718UL))) +#define bM4_MPU_RGD14_MPURG14ADDR2 (*((volatile unsigned int*)(0x42A0071CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR3 (*((volatile unsigned int*)(0x42A00720UL))) +#define bM4_MPU_RGD14_MPURG14ADDR4 (*((volatile unsigned int*)(0x42A00724UL))) +#define bM4_MPU_RGD14_MPURG14ADDR5 (*((volatile unsigned int*)(0x42A00728UL))) +#define bM4_MPU_RGD14_MPURG14ADDR6 (*((volatile unsigned int*)(0x42A0072CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR7 (*((volatile unsigned int*)(0x42A00730UL))) +#define bM4_MPU_RGD14_MPURG14ADDR8 (*((volatile unsigned int*)(0x42A00734UL))) +#define bM4_MPU_RGD14_MPURG14ADDR9 (*((volatile unsigned int*)(0x42A00738UL))) +#define bM4_MPU_RGD14_MPURG14ADDR10 (*((volatile unsigned int*)(0x42A0073CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR11 (*((volatile unsigned int*)(0x42A00740UL))) +#define bM4_MPU_RGD14_MPURG14ADDR12 (*((volatile unsigned int*)(0x42A00744UL))) +#define bM4_MPU_RGD14_MPURG14ADDR13 (*((volatile unsigned int*)(0x42A00748UL))) +#define bM4_MPU_RGD14_MPURG14ADDR14 (*((volatile unsigned int*)(0x42A0074CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR15 (*((volatile unsigned int*)(0x42A00750UL))) +#define bM4_MPU_RGD14_MPURG14ADDR16 (*((volatile unsigned int*)(0x42A00754UL))) +#define bM4_MPU_RGD14_MPURG14ADDR17 (*((volatile unsigned int*)(0x42A00758UL))) +#define bM4_MPU_RGD14_MPURG14ADDR18 (*((volatile unsigned int*)(0x42A0075CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR19 (*((volatile unsigned int*)(0x42A00760UL))) +#define bM4_MPU_RGD14_MPURG14ADDR20 (*((volatile unsigned int*)(0x42A00764UL))) +#define bM4_MPU_RGD14_MPURG14ADDR21 (*((volatile unsigned int*)(0x42A00768UL))) +#define bM4_MPU_RGD14_MPURG14ADDR22 (*((volatile unsigned int*)(0x42A0076CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR23 (*((volatile unsigned int*)(0x42A00770UL))) +#define bM4_MPU_RGD14_MPURG14ADDR24 (*((volatile unsigned int*)(0x42A00774UL))) +#define bM4_MPU_RGD14_MPURG14ADDR25 (*((volatile unsigned int*)(0x42A00778UL))) +#define bM4_MPU_RGD14_MPURG14ADDR26 (*((volatile unsigned int*)(0x42A0077CUL))) +#define bM4_MPU_RGD15_MPURG15SIZE0 (*((volatile unsigned int*)(0x42A00780UL))) +#define bM4_MPU_RGD15_MPURG15SIZE1 (*((volatile unsigned int*)(0x42A00784UL))) +#define bM4_MPU_RGD15_MPURG15SIZE2 (*((volatile unsigned int*)(0x42A00788UL))) +#define bM4_MPU_RGD15_MPURG15SIZE3 (*((volatile unsigned int*)(0x42A0078CUL))) +#define bM4_MPU_RGD15_MPURG15SIZE4 (*((volatile unsigned int*)(0x42A00790UL))) +#define bM4_MPU_RGD15_MPURG15ADDR0 (*((volatile unsigned int*)(0x42A00794UL))) +#define bM4_MPU_RGD15_MPURG15ADDR1 (*((volatile unsigned int*)(0x42A00798UL))) +#define bM4_MPU_RGD15_MPURG15ADDR2 (*((volatile unsigned int*)(0x42A0079CUL))) +#define bM4_MPU_RGD15_MPURG15ADDR3 (*((volatile unsigned int*)(0x42A007A0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR4 (*((volatile unsigned int*)(0x42A007A4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR5 (*((volatile unsigned int*)(0x42A007A8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR6 (*((volatile unsigned int*)(0x42A007ACUL))) +#define bM4_MPU_RGD15_MPURG15ADDR7 (*((volatile unsigned int*)(0x42A007B0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR8 (*((volatile unsigned int*)(0x42A007B4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR9 (*((volatile unsigned int*)(0x42A007B8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR10 (*((volatile unsigned int*)(0x42A007BCUL))) +#define bM4_MPU_RGD15_MPURG15ADDR11 (*((volatile unsigned int*)(0x42A007C0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR12 (*((volatile unsigned int*)(0x42A007C4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR13 (*((volatile unsigned int*)(0x42A007C8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR14 (*((volatile unsigned int*)(0x42A007CCUL))) +#define bM4_MPU_RGD15_MPURG15ADDR15 (*((volatile unsigned int*)(0x42A007D0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR16 (*((volatile unsigned int*)(0x42A007D4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR17 (*((volatile unsigned int*)(0x42A007D8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR18 (*((volatile unsigned int*)(0x42A007DCUL))) +#define bM4_MPU_RGD15_MPURG15ADDR19 (*((volatile unsigned int*)(0x42A007E0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR20 (*((volatile unsigned int*)(0x42A007E4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR21 (*((volatile unsigned int*)(0x42A007E8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR22 (*((volatile unsigned int*)(0x42A007ECUL))) +#define bM4_MPU_RGD15_MPURG15ADDR23 (*((volatile unsigned int*)(0x42A007F0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR24 (*((volatile unsigned int*)(0x42A007F4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR25 (*((volatile unsigned int*)(0x42A007F8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR26 (*((volatile unsigned int*)(0x42A007FCUL))) +#define bM4_MPU_RGCR0_S2RG0RP (*((volatile unsigned int*)(0x42A00800UL))) +#define bM4_MPU_RGCR0_S2RG0WP (*((volatile unsigned int*)(0x42A00804UL))) +#define bM4_MPU_RGCR0_S2RG0E (*((volatile unsigned int*)(0x42A0081CUL))) +#define bM4_MPU_RGCR0_S1RG0RP (*((volatile unsigned int*)(0x42A00820UL))) +#define bM4_MPU_RGCR0_S1RG0WP (*((volatile unsigned int*)(0x42A00824UL))) +#define bM4_MPU_RGCR0_S1RG0E (*((volatile unsigned int*)(0x42A0083CUL))) +#define bM4_MPU_RGCR0_FRG0RP (*((volatile unsigned int*)(0x42A00840UL))) +#define bM4_MPU_RGCR0_FRG0WP (*((volatile unsigned int*)(0x42A00844UL))) +#define bM4_MPU_RGCR0_FRG0E (*((volatile unsigned int*)(0x42A0085CUL))) +#define bM4_MPU_RGCR1_S2RG1RP (*((volatile unsigned int*)(0x42A00880UL))) +#define bM4_MPU_RGCR1_S2RG1WP (*((volatile unsigned int*)(0x42A00884UL))) +#define bM4_MPU_RGCR1_S2RG1E (*((volatile unsigned int*)(0x42A0089CUL))) +#define bM4_MPU_RGCR1_S1RG1RP (*((volatile unsigned int*)(0x42A008A0UL))) +#define bM4_MPU_RGCR1_S1RG1WP (*((volatile unsigned int*)(0x42A008A4UL))) +#define bM4_MPU_RGCR1_S1RG1E (*((volatile unsigned int*)(0x42A008BCUL))) +#define bM4_MPU_RGCR1_FRG1RP (*((volatile unsigned int*)(0x42A008C0UL))) +#define bM4_MPU_RGCR1_FRG1WP (*((volatile unsigned int*)(0x42A008C4UL))) +#define bM4_MPU_RGCR1_FRG1E (*((volatile unsigned int*)(0x42A008DCUL))) +#define bM4_MPU_RGCR2_S2RG2RP (*((volatile unsigned int*)(0x42A00900UL))) +#define bM4_MPU_RGCR2_S2RG2WP (*((volatile unsigned int*)(0x42A00904UL))) +#define bM4_MPU_RGCR2_S2RG2E (*((volatile unsigned int*)(0x42A0091CUL))) +#define bM4_MPU_RGCR2_S1RG2RP (*((volatile unsigned int*)(0x42A00920UL))) +#define bM4_MPU_RGCR2_S1RG2WP (*((volatile unsigned int*)(0x42A00924UL))) +#define bM4_MPU_RGCR2_S1RG2E (*((volatile unsigned int*)(0x42A0093CUL))) +#define bM4_MPU_RGCR2_FRG2RP (*((volatile unsigned int*)(0x42A00940UL))) +#define bM4_MPU_RGCR2_FRG2WP (*((volatile unsigned int*)(0x42A00944UL))) +#define bM4_MPU_RGCR2_FRG2E (*((volatile unsigned int*)(0x42A0095CUL))) +#define bM4_MPU_RGCR3_S2RG3RP (*((volatile unsigned int*)(0x42A00980UL))) +#define bM4_MPU_RGCR3_S2RG3WP (*((volatile unsigned int*)(0x42A00984UL))) +#define bM4_MPU_RGCR3_S2RG3E (*((volatile unsigned int*)(0x42A0099CUL))) +#define bM4_MPU_RGCR3_S1RG3RP (*((volatile unsigned int*)(0x42A009A0UL))) +#define bM4_MPU_RGCR3_S1RG3WP (*((volatile unsigned int*)(0x42A009A4UL))) +#define bM4_MPU_RGCR3_S1RG3E (*((volatile unsigned int*)(0x42A009BCUL))) +#define bM4_MPU_RGCR3_FRG3RP (*((volatile unsigned int*)(0x42A009C0UL))) +#define bM4_MPU_RGCR3_FRG3WP (*((volatile unsigned int*)(0x42A009C4UL))) +#define bM4_MPU_RGCR3_FRG3E (*((volatile unsigned int*)(0x42A009DCUL))) +#define bM4_MPU_RGCR4_S2RG4RP (*((volatile unsigned int*)(0x42A00A00UL))) +#define bM4_MPU_RGCR4_S2RG4WP (*((volatile unsigned int*)(0x42A00A04UL))) +#define bM4_MPU_RGCR4_S2RG4E (*((volatile unsigned int*)(0x42A00A1CUL))) +#define bM4_MPU_RGCR4_S1RG4RP (*((volatile unsigned int*)(0x42A00A20UL))) +#define bM4_MPU_RGCR4_S1RG4WP (*((volatile unsigned int*)(0x42A00A24UL))) +#define bM4_MPU_RGCR4_S1RG4E (*((volatile unsigned int*)(0x42A00A3CUL))) +#define bM4_MPU_RGCR4_FRG4RP (*((volatile unsigned int*)(0x42A00A40UL))) +#define bM4_MPU_RGCR4_FRG4WP (*((volatile unsigned int*)(0x42A00A44UL))) +#define bM4_MPU_RGCR4_FRG4E (*((volatile unsigned int*)(0x42A00A5CUL))) +#define bM4_MPU_RGCR5_S2RG5RP (*((volatile unsigned int*)(0x42A00A80UL))) +#define bM4_MPU_RGCR5_S2RG5WP (*((volatile unsigned int*)(0x42A00A84UL))) +#define bM4_MPU_RGCR5_S2RG5E (*((volatile unsigned int*)(0x42A00A9CUL))) +#define bM4_MPU_RGCR5_S1RG5RP (*((volatile unsigned int*)(0x42A00AA0UL))) +#define bM4_MPU_RGCR5_S1RG5WP (*((volatile unsigned int*)(0x42A00AA4UL))) +#define bM4_MPU_RGCR5_S1RG5E (*((volatile unsigned int*)(0x42A00ABCUL))) +#define bM4_MPU_RGCR5_FRG5RP (*((volatile unsigned int*)(0x42A00AC0UL))) +#define bM4_MPU_RGCR5_FRG5WP (*((volatile unsigned int*)(0x42A00AC4UL))) +#define bM4_MPU_RGCR5_FRG5E (*((volatile unsigned int*)(0x42A00ADCUL))) +#define bM4_MPU_RGCR6_S2RG6RP (*((volatile unsigned int*)(0x42A00B00UL))) +#define bM4_MPU_RGCR6_S2RG6WP (*((volatile unsigned int*)(0x42A00B04UL))) +#define bM4_MPU_RGCR6_S2RG6E (*((volatile unsigned int*)(0x42A00B1CUL))) +#define bM4_MPU_RGCR6_S1RG6RP (*((volatile unsigned int*)(0x42A00B20UL))) +#define bM4_MPU_RGCR6_S1RG6WP (*((volatile unsigned int*)(0x42A00B24UL))) +#define bM4_MPU_RGCR6_S1RG6E (*((volatile unsigned int*)(0x42A00B3CUL))) +#define bM4_MPU_RGCR6_FRG6RP (*((volatile unsigned int*)(0x42A00B40UL))) +#define bM4_MPU_RGCR6_FRG6WP (*((volatile unsigned int*)(0x42A00B44UL))) +#define bM4_MPU_RGCR6_FRG6E (*((volatile unsigned int*)(0x42A00B5CUL))) +#define bM4_MPU_RGCR7_S2RG7RP (*((volatile unsigned int*)(0x42A00B80UL))) +#define bM4_MPU_RGCR7_S2RG7WP (*((volatile unsigned int*)(0x42A00B84UL))) +#define bM4_MPU_RGCR7_S2RG7E (*((volatile unsigned int*)(0x42A00B9CUL))) +#define bM4_MPU_RGCR7_S1RG7RP (*((volatile unsigned int*)(0x42A00BA0UL))) +#define bM4_MPU_RGCR7_S1RG7WP (*((volatile unsigned int*)(0x42A00BA4UL))) +#define bM4_MPU_RGCR7_S1RG7E (*((volatile unsigned int*)(0x42A00BBCUL))) +#define bM4_MPU_RGCR7_FRG7RP (*((volatile unsigned int*)(0x42A00BC0UL))) +#define bM4_MPU_RGCR7_FRG7WP (*((volatile unsigned int*)(0x42A00BC4UL))) +#define bM4_MPU_RGCR7_FRG7E (*((volatile unsigned int*)(0x42A00BDCUL))) +#define bM4_MPU_RGCR8_S2RG8RP (*((volatile unsigned int*)(0x42A00C00UL))) +#define bM4_MPU_RGCR8_S2RG8WP (*((volatile unsigned int*)(0x42A00C04UL))) +#define bM4_MPU_RGCR8_S2RG8E (*((volatile unsigned int*)(0x42A00C1CUL))) +#define bM4_MPU_RGCR8_S1RG8RP (*((volatile unsigned int*)(0x42A00C20UL))) +#define bM4_MPU_RGCR8_S1RG8WP (*((volatile unsigned int*)(0x42A00C24UL))) +#define bM4_MPU_RGCR8_S1RG8E (*((volatile unsigned int*)(0x42A00C3CUL))) +#define bM4_MPU_RGCR9_S2RG9RP (*((volatile unsigned int*)(0x42A00C80UL))) +#define bM4_MPU_RGCR9_S2RG9WP (*((volatile unsigned int*)(0x42A00C84UL))) +#define bM4_MPU_RGCR9_S2RG9E (*((volatile unsigned int*)(0x42A00C9CUL))) +#define bM4_MPU_RGCR9_S1RG9RP (*((volatile unsigned int*)(0x42A00CA0UL))) +#define bM4_MPU_RGCR9_S1RG9WP (*((volatile unsigned int*)(0x42A00CA4UL))) +#define bM4_MPU_RGCR9_S1RG9E (*((volatile unsigned int*)(0x42A00CBCUL))) +#define bM4_MPU_RGCR10_S2RG10RP (*((volatile unsigned int*)(0x42A00D00UL))) +#define bM4_MPU_RGCR10_S2RG10WP (*((volatile unsigned int*)(0x42A00D04UL))) +#define bM4_MPU_RGCR10_S2RG10E (*((volatile unsigned int*)(0x42A00D1CUL))) +#define bM4_MPU_RGCR10_S1RG10RP (*((volatile unsigned int*)(0x42A00D20UL))) +#define bM4_MPU_RGCR10_S1RG10WP (*((volatile unsigned int*)(0x42A00D24UL))) +#define bM4_MPU_RGCR10_S1RG10E (*((volatile unsigned int*)(0x42A00D3CUL))) +#define bM4_MPU_RGCR11_S2RG11RP (*((volatile unsigned int*)(0x42A00D80UL))) +#define bM4_MPU_RGCR11_S2RG11WP (*((volatile unsigned int*)(0x42A00D84UL))) +#define bM4_MPU_RGCR11_S2RG11E (*((volatile unsigned int*)(0x42A00D9CUL))) +#define bM4_MPU_RGCR11_S1RG11RP (*((volatile unsigned int*)(0x42A00DA0UL))) +#define bM4_MPU_RGCR11_S1RG11WP (*((volatile unsigned int*)(0x42A00DA4UL))) +#define bM4_MPU_RGCR11_S1RG11E (*((volatile unsigned int*)(0x42A00DBCUL))) +#define bM4_MPU_RGCR12_S2RG12RP (*((volatile unsigned int*)(0x42A00E00UL))) +#define bM4_MPU_RGCR12_S2RG12WP (*((volatile unsigned int*)(0x42A00E04UL))) +#define bM4_MPU_RGCR12_S2RG12E (*((volatile unsigned int*)(0x42A00E1CUL))) +#define bM4_MPU_RGCR12_S1RG12RP (*((volatile unsigned int*)(0x42A00E20UL))) +#define bM4_MPU_RGCR12_S1RG12WP (*((volatile unsigned int*)(0x42A00E24UL))) +#define bM4_MPU_RGCR12_S1RG12E (*((volatile unsigned int*)(0x42A00E3CUL))) +#define bM4_MPU_RGCR13_S2RG13RP (*((volatile unsigned int*)(0x42A00E80UL))) +#define bM4_MPU_RGCR13_S2RG13WP (*((volatile unsigned int*)(0x42A00E84UL))) +#define bM4_MPU_RGCR13_S2RG13E (*((volatile unsigned int*)(0x42A00E9CUL))) +#define bM4_MPU_RGCR13_S1RG13RP (*((volatile unsigned int*)(0x42A00EA0UL))) +#define bM4_MPU_RGCR13_S1RG13WP (*((volatile unsigned int*)(0x42A00EA4UL))) +#define bM4_MPU_RGCR13_S1RG13E (*((volatile unsigned int*)(0x42A00EBCUL))) +#define bM4_MPU_RGCR14_S2RG14RP (*((volatile unsigned int*)(0x42A00F00UL))) +#define bM4_MPU_RGCR14_S2RG14WP (*((volatile unsigned int*)(0x42A00F04UL))) +#define bM4_MPU_RGCR14_S2RG14E (*((volatile unsigned int*)(0x42A00F1CUL))) +#define bM4_MPU_RGCR14_S1RG14RP (*((volatile unsigned int*)(0x42A00F20UL))) +#define bM4_MPU_RGCR14_S1RG14WP (*((volatile unsigned int*)(0x42A00F24UL))) +#define bM4_MPU_RGCR14_S1RG14E (*((volatile unsigned int*)(0x42A00F3CUL))) +#define bM4_MPU_RGCR15_S2RG15RP (*((volatile unsigned int*)(0x42A00F80UL))) +#define bM4_MPU_RGCR15_S2RG15WP (*((volatile unsigned int*)(0x42A00F84UL))) +#define bM4_MPU_RGCR15_S2RG15E (*((volatile unsigned int*)(0x42A00F9CUL))) +#define bM4_MPU_RGCR15_S1RG15RP (*((volatile unsigned int*)(0x42A00FA0UL))) +#define bM4_MPU_RGCR15_S1RG15WP (*((volatile unsigned int*)(0x42A00FA4UL))) +#define bM4_MPU_RGCR15_S1RG15E (*((volatile unsigned int*)(0x42A00FBCUL))) +#define bM4_MPU_CR_SMPU2BRP (*((volatile unsigned int*)(0x42A01000UL))) +#define bM4_MPU_CR_SMPU2BWP (*((volatile unsigned int*)(0x42A01004UL))) +#define bM4_MPU_CR_SMPU2ACT0 (*((volatile unsigned int*)(0x42A01008UL))) +#define bM4_MPU_CR_SMPU2ACT1 (*((volatile unsigned int*)(0x42A0100CUL))) +#define bM4_MPU_CR_SMPU2E (*((volatile unsigned int*)(0x42A0101CUL))) +#define bM4_MPU_CR_SMPU1BRP (*((volatile unsigned int*)(0x42A01020UL))) +#define bM4_MPU_CR_SMPU1BWP (*((volatile unsigned int*)(0x42A01024UL))) +#define bM4_MPU_CR_SMPU1ACT0 (*((volatile unsigned int*)(0x42A01028UL))) +#define bM4_MPU_CR_SMPU1ACT1 (*((volatile unsigned int*)(0x42A0102CUL))) +#define bM4_MPU_CR_SMPU1E (*((volatile unsigned int*)(0x42A0103CUL))) +#define bM4_MPU_CR_FMPUBRP (*((volatile unsigned int*)(0x42A01040UL))) +#define bM4_MPU_CR_FMPUBWP (*((volatile unsigned int*)(0x42A01044UL))) +#define bM4_MPU_CR_FMPUACT0 (*((volatile unsigned int*)(0x42A01048UL))) +#define bM4_MPU_CR_FMPUACT1 (*((volatile unsigned int*)(0x42A0104CUL))) +#define bM4_MPU_CR_FMPUE (*((volatile unsigned int*)(0x42A0105CUL))) +#define bM4_MPU_SR_SMPU2EAF (*((volatile unsigned int*)(0x42A01080UL))) +#define bM4_MPU_SR_SMPU1EAF (*((volatile unsigned int*)(0x42A010A0UL))) +#define bM4_MPU_SR_FMPUEAF (*((volatile unsigned int*)(0x42A010C0UL))) +#define bM4_MPU_ECLR_SMPU2ECLR (*((volatile unsigned int*)(0x42A01100UL))) +#define bM4_MPU_ECLR_SMPU1ECLR (*((volatile unsigned int*)(0x42A01120UL))) +#define bM4_MPU_ECLR_FMPUECLR (*((volatile unsigned int*)(0x42A01140UL))) +#define bM4_MPU_WP_MPUWE (*((volatile unsigned int*)(0x42A01180UL))) +#define bM4_MPU_WP_WKEY0 (*((volatile unsigned int*)(0x42A01184UL))) +#define bM4_MPU_WP_WKEY1 (*((volatile unsigned int*)(0x42A01188UL))) +#define bM4_MPU_WP_WKEY2 (*((volatile unsigned int*)(0x42A0118CUL))) +#define bM4_MPU_WP_WKEY3 (*((volatile unsigned int*)(0x42A01190UL))) +#define bM4_MPU_WP_WKEY4 (*((volatile unsigned int*)(0x42A01194UL))) +#define bM4_MPU_WP_WKEY5 (*((volatile unsigned int*)(0x42A01198UL))) +#define bM4_MPU_WP_WKEY6 (*((volatile unsigned int*)(0x42A0119CUL))) +#define bM4_MPU_WP_WKEY7 (*((volatile unsigned int*)(0x42A011A0UL))) +#define bM4_MPU_WP_WKEY8 (*((volatile unsigned int*)(0x42A011A4UL))) +#define bM4_MPU_WP_WKEY9 (*((volatile unsigned int*)(0x42A011A8UL))) +#define bM4_MPU_WP_WKEY10 (*((volatile unsigned int*)(0x42A011ACUL))) +#define bM4_MPU_WP_WKEY11 (*((volatile unsigned int*)(0x42A011B0UL))) +#define bM4_MPU_WP_WKEY12 (*((volatile unsigned int*)(0x42A011B4UL))) +#define bM4_MPU_WP_WKEY13 (*((volatile unsigned int*)(0x42A011B8UL))) +#define bM4_MPU_WP_WKEY14 (*((volatile unsigned int*)(0x42A011BCUL))) +#define bM4_MSTP_FCG0_SRAMH (*((volatile unsigned int*)(0x42900000UL))) +#define bM4_MSTP_FCG0_SRAM12 (*((volatile unsigned int*)(0x42900010UL))) +#define bM4_MSTP_FCG0_SRAM3 (*((volatile unsigned int*)(0x42900020UL))) +#define bM4_MSTP_FCG0_SRAMRET (*((volatile unsigned int*)(0x42900028UL))) +#define bM4_MSTP_FCG0_DMA1 (*((volatile unsigned int*)(0x42900038UL))) +#define bM4_MSTP_FCG0_DMA2 (*((volatile unsigned int*)(0x4290003CUL))) +#define bM4_MSTP_FCG0_FCM (*((volatile unsigned int*)(0x42900040UL))) +#define bM4_MSTP_FCG0_AOS (*((volatile unsigned int*)(0x42900044UL))) +#define bM4_MSTP_FCG0_AES (*((volatile unsigned int*)(0x42900050UL))) +#define bM4_MSTP_FCG0_HASH (*((volatile unsigned int*)(0x42900054UL))) +#define bM4_MSTP_FCG0_TRNG (*((volatile unsigned int*)(0x42900058UL))) +#define bM4_MSTP_FCG0_CRC (*((volatile unsigned int*)(0x4290005CUL))) +#define bM4_MSTP_FCG0_DCU1 (*((volatile unsigned int*)(0x42900060UL))) +#define bM4_MSTP_FCG0_DCU2 (*((volatile unsigned int*)(0x42900064UL))) +#define bM4_MSTP_FCG0_DCU3 (*((volatile unsigned int*)(0x42900068UL))) +#define bM4_MSTP_FCG0_DCU4 (*((volatile unsigned int*)(0x4290006CUL))) +#define bM4_MSTP_FCG0_KEY (*((volatile unsigned int*)(0x4290007CUL))) +#define bM4_MSTP_FCG1_CAN (*((volatile unsigned int*)(0x42900080UL))) +#define bM4_MSTP_FCG1_QSPI (*((volatile unsigned int*)(0x4290008CUL))) +#define bM4_MSTP_FCG1_IIC1 (*((volatile unsigned int*)(0x42900090UL))) +#define bM4_MSTP_FCG1_IIC2 (*((volatile unsigned int*)(0x42900094UL))) +#define bM4_MSTP_FCG1_IIC3 (*((volatile unsigned int*)(0x42900098UL))) +#define bM4_MSTP_FCG1_USBFS (*((volatile unsigned int*)(0x429000A0UL))) +#define bM4_MSTP_FCG1_SDIOC1 (*((volatile unsigned int*)(0x429000A8UL))) +#define bM4_MSTP_FCG1_SDIOC2 (*((volatile unsigned int*)(0x429000ACUL))) +#define bM4_MSTP_FCG1_I2S1 (*((volatile unsigned int*)(0x429000B0UL))) +#define bM4_MSTP_FCG1_I2S2 (*((volatile unsigned int*)(0x429000B4UL))) +#define bM4_MSTP_FCG1_I2S3 (*((volatile unsigned int*)(0x429000B8UL))) +#define bM4_MSTP_FCG1_I2S4 (*((volatile unsigned int*)(0x429000BCUL))) +#define bM4_MSTP_FCG1_SPI1 (*((volatile unsigned int*)(0x429000C0UL))) +#define bM4_MSTP_FCG1_SPI2 (*((volatile unsigned int*)(0x429000C4UL))) +#define bM4_MSTP_FCG1_SPI3 (*((volatile unsigned int*)(0x429000C8UL))) +#define bM4_MSTP_FCG1_SPI4 (*((volatile unsigned int*)(0x429000CCUL))) +#define bM4_MSTP_FCG1_USART1 (*((volatile unsigned int*)(0x429000E0UL))) +#define bM4_MSTP_FCG1_USART2 (*((volatile unsigned int*)(0x429000E4UL))) +#define bM4_MSTP_FCG1_USART3 (*((volatile unsigned int*)(0x429000E8UL))) +#define bM4_MSTP_FCG1_USART4 (*((volatile unsigned int*)(0x429000ECUL))) +#define bM4_MSTP_FCG2_TIMER0_1 (*((volatile unsigned int*)(0x42900100UL))) +#define bM4_MSTP_FCG2_TIMER0_2 (*((volatile unsigned int*)(0x42900104UL))) +#define bM4_MSTP_FCG2_TIMERA_1 (*((volatile unsigned int*)(0x42900108UL))) +#define bM4_MSTP_FCG2_TIMERA_2 (*((volatile unsigned int*)(0x4290010CUL))) +#define bM4_MSTP_FCG2_TIMERA_3 (*((volatile unsigned int*)(0x42900110UL))) +#define bM4_MSTP_FCG2_TIMERA_4 (*((volatile unsigned int*)(0x42900114UL))) +#define bM4_MSTP_FCG2_TIMERA_5 (*((volatile unsigned int*)(0x42900118UL))) +#define bM4_MSTP_FCG2_TIMERA_6 (*((volatile unsigned int*)(0x4290011CUL))) +#define bM4_MSTP_FCG2_TIMER4_1 (*((volatile unsigned int*)(0x42900120UL))) +#define bM4_MSTP_FCG2_TIMER4_2 (*((volatile unsigned int*)(0x42900124UL))) +#define bM4_MSTP_FCG2_TIMER4_3 (*((volatile unsigned int*)(0x42900128UL))) +#define bM4_MSTP_FCG2_EMB (*((volatile unsigned int*)(0x4290013CUL))) +#define bM4_MSTP_FCG2_TIMER6_1 (*((volatile unsigned int*)(0x42900140UL))) +#define bM4_MSTP_FCG2_TIMER6_2 (*((volatile unsigned int*)(0x42900144UL))) +#define bM4_MSTP_FCG2_TIMER6_3 (*((volatile unsigned int*)(0x42900148UL))) +#define bM4_MSTP_FCG3_ADC1 (*((volatile unsigned int*)(0x42900180UL))) +#define bM4_MSTP_FCG3_ADC2 (*((volatile unsigned int*)(0x42900184UL))) +#define bM4_MSTP_FCG3_CMP (*((volatile unsigned int*)(0x429001A0UL))) +#define bM4_MSTP_FCG3_OTS (*((volatile unsigned int*)(0x429001B0UL))) +#define bM4_MSTP_FCG0PC_PRT0 (*((volatile unsigned int*)(0x42900200UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE0 (*((volatile unsigned int*)(0x42900240UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE1 (*((volatile unsigned int*)(0x42900244UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE2 (*((volatile unsigned int*)(0x42900248UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE3 (*((volatile unsigned int*)(0x4290024CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE4 (*((volatile unsigned int*)(0x42900250UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE5 (*((volatile unsigned int*)(0x42900254UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE6 (*((volatile unsigned int*)(0x42900258UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE7 (*((volatile unsigned int*)(0x4290025CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE8 (*((volatile unsigned int*)(0x42900260UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE9 (*((volatile unsigned int*)(0x42900264UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE10 (*((volatile unsigned int*)(0x42900268UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE11 (*((volatile unsigned int*)(0x4290026CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE12 (*((volatile unsigned int*)(0x42900270UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE13 (*((volatile unsigned int*)(0x42900274UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE14 (*((volatile unsigned int*)(0x42900278UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE15 (*((volatile unsigned int*)(0x4290027CUL))) +#define bM4_OTS_CTL_OTSST (*((volatile unsigned int*)(0x42948000UL))) +#define bM4_OTS_CTL_OTSCK (*((volatile unsigned int*)(0x42948004UL))) +#define bM4_OTS_CTL_OTSIE (*((volatile unsigned int*)(0x42948008UL))) +#define bM4_OTS_CTL_TSSTP (*((volatile unsigned int*)(0x4294800CUL))) +#define bM4_OTS_LPR_TSOFS0 (*((volatile unsigned int*)(0x42948100UL))) +#define bM4_OTS_LPR_TSOFS1 (*((volatile unsigned int*)(0x42948104UL))) +#define bM4_OTS_LPR_TSOFS2 (*((volatile unsigned int*)(0x42948108UL))) +#define bM4_OTS_LPR_TSOFS3 (*((volatile unsigned int*)(0x4294810CUL))) +#define bM4_OTS_LPR_TSOFS4 (*((volatile unsigned int*)(0x42948110UL))) +#define bM4_OTS_LPR_TSOFS5 (*((volatile unsigned int*)(0x42948114UL))) +#define bM4_OTS_LPR_TSOFS6 (*((volatile unsigned int*)(0x42948118UL))) +#define bM4_OTS_LPR_TSOFS7 (*((volatile unsigned int*)(0x4294811CUL))) +#define bM4_OTS_LPR_TSSLP0 (*((volatile unsigned int*)(0x42948120UL))) +#define bM4_OTS_LPR_TSSLP1 (*((volatile unsigned int*)(0x42948124UL))) +#define bM4_OTS_LPR_TSSLP2 (*((volatile unsigned int*)(0x42948128UL))) +#define bM4_OTS_LPR_TSSLP3 (*((volatile unsigned int*)(0x4294812CUL))) +#define bM4_OTS_LPR_TSSLP4 (*((volatile unsigned int*)(0x42948130UL))) +#define bM4_OTS_LPR_TSSLP5 (*((volatile unsigned int*)(0x42948134UL))) +#define bM4_OTS_LPR_TSSLP6 (*((volatile unsigned int*)(0x42948138UL))) +#define bM4_OTS_LPR_TSSLP7 (*((volatile unsigned int*)(0x4294813CUL))) +#define bM4_OTS_LPR_TSSLP8 (*((volatile unsigned int*)(0x42948140UL))) +#define bM4_OTS_LPR_TSSLP9 (*((volatile unsigned int*)(0x42948144UL))) +#define bM4_OTS_LPR_TSSLP10 (*((volatile unsigned int*)(0x42948148UL))) +#define bM4_OTS_LPR_TSSLP11 (*((volatile unsigned int*)(0x4294814CUL))) +#define bM4_OTS_LPR_TSSLP12 (*((volatile unsigned int*)(0x42948150UL))) +#define bM4_OTS_LPR_TSSLP13 (*((volatile unsigned int*)(0x42948154UL))) +#define bM4_OTS_LPR_TSSLP14 (*((volatile unsigned int*)(0x42948158UL))) +#define bM4_OTS_LPR_TSSLP15 (*((volatile unsigned int*)(0x4294815CUL))) +#define bM4_OTS_LPR_TSSLP16 (*((volatile unsigned int*)(0x42948160UL))) +#define bM4_OTS_LPR_TSSLP17 (*((volatile unsigned int*)(0x42948164UL))) +#define bM4_OTS_LPR_TSSLP18 (*((volatile unsigned int*)(0x42948168UL))) +#define bM4_OTS_LPR_TSSLP19 (*((volatile unsigned int*)(0x4294816CUL))) +#define bM4_OTS_LPR_TSSLP20 (*((volatile unsigned int*)(0x42948170UL))) +#define bM4_OTS_LPR_TSSLP21 (*((volatile unsigned int*)(0x42948174UL))) +#define bM4_OTS_LPR_TSSLP22 (*((volatile unsigned int*)(0x42948178UL))) +#define bM4_OTS_LPR_TSSLP23 (*((volatile unsigned int*)(0x4294817CUL))) +#define bM4_PERIC_USBFS_SYCTLREG_DFB (*((volatile unsigned int*)(0x42AA8000UL))) +#define bM4_PERIC_USBFS_SYCTLREG_SOFEN (*((volatile unsigned int*)(0x42AA8004UL))) +#define bM4_PERIC_SDIOC_SYCTLREG_SELMMC1 (*((volatile unsigned int*)(0x42AA8084UL))) +#define bM4_PERIC_SDIOC_SYCTLREG_SELMMC2 (*((volatile unsigned int*)(0x42AA808CUL))) +#define bM4_PORT_PIDRA_PIN00 (*((volatile unsigned int*)(0x42A70000UL))) +#define bM4_PORT_PIDRA_PIN01 (*((volatile unsigned int*)(0x42A70004UL))) +#define bM4_PORT_PIDRA_PIN02 (*((volatile unsigned int*)(0x42A70008UL))) +#define bM4_PORT_PIDRA_PIN03 (*((volatile unsigned int*)(0x42A7000CUL))) +#define bM4_PORT_PIDRA_PIN04 (*((volatile unsigned int*)(0x42A70010UL))) +#define bM4_PORT_PIDRA_PIN05 (*((volatile unsigned int*)(0x42A70014UL))) +#define bM4_PORT_PIDRA_PIN06 (*((volatile unsigned int*)(0x42A70018UL))) +#define bM4_PORT_PIDRA_PIN07 (*((volatile unsigned int*)(0x42A7001CUL))) +#define bM4_PORT_PIDRA_PIN08 (*((volatile unsigned int*)(0x42A70020UL))) +#define bM4_PORT_PIDRA_PIN09 (*((volatile unsigned int*)(0x42A70024UL))) +#define bM4_PORT_PIDRA_PIN10 (*((volatile unsigned int*)(0x42A70028UL))) +#define bM4_PORT_PIDRA_PIN11 (*((volatile unsigned int*)(0x42A7002CUL))) +#define bM4_PORT_PIDRA_PIN12 (*((volatile unsigned int*)(0x42A70030UL))) +#define bM4_PORT_PIDRA_PIN13 (*((volatile unsigned int*)(0x42A70034UL))) +#define bM4_PORT_PIDRA_PIN14 (*((volatile unsigned int*)(0x42A70038UL))) +#define bM4_PORT_PIDRA_PIN15 (*((volatile unsigned int*)(0x42A7003CUL))) +#define bM4_PORT_PODRA_POUT00 (*((volatile unsigned int*)(0x42A70080UL))) +#define bM4_PORT_PODRA_POUT01 (*((volatile unsigned int*)(0x42A70084UL))) +#define bM4_PORT_PODRA_POUT02 (*((volatile unsigned int*)(0x42A70088UL))) +#define bM4_PORT_PODRA_POUT03 (*((volatile unsigned int*)(0x42A7008CUL))) +#define bM4_PORT_PODRA_POUT04 (*((volatile unsigned int*)(0x42A70090UL))) +#define bM4_PORT_PODRA_POUT05 (*((volatile unsigned int*)(0x42A70094UL))) +#define bM4_PORT_PODRA_POUT06 (*((volatile unsigned int*)(0x42A70098UL))) +#define bM4_PORT_PODRA_POUT07 (*((volatile unsigned int*)(0x42A7009CUL))) +#define bM4_PORT_PODRA_POUT08 (*((volatile unsigned int*)(0x42A700A0UL))) +#define bM4_PORT_PODRA_POUT09 (*((volatile unsigned int*)(0x42A700A4UL))) +#define bM4_PORT_PODRA_POUT10 (*((volatile unsigned int*)(0x42A700A8UL))) +#define bM4_PORT_PODRA_POUT11 (*((volatile unsigned int*)(0x42A700ACUL))) +#define bM4_PORT_PODRA_POUT12 (*((volatile unsigned int*)(0x42A700B0UL))) +#define bM4_PORT_PODRA_POUT13 (*((volatile unsigned int*)(0x42A700B4UL))) +#define bM4_PORT_PODRA_POUT14 (*((volatile unsigned int*)(0x42A700B8UL))) +#define bM4_PORT_PODRA_POUT15 (*((volatile unsigned int*)(0x42A700BCUL))) +#define bM4_PORT_POERA_POUTE00 (*((volatile unsigned int*)(0x42A700C0UL))) +#define bM4_PORT_POERA_POUTE01 (*((volatile unsigned int*)(0x42A700C4UL))) +#define bM4_PORT_POERA_POUTE02 (*((volatile unsigned int*)(0x42A700C8UL))) +#define bM4_PORT_POERA_POUTE03 (*((volatile unsigned int*)(0x42A700CCUL))) +#define bM4_PORT_POERA_POUTE04 (*((volatile unsigned int*)(0x42A700D0UL))) +#define bM4_PORT_POERA_POUTE05 (*((volatile unsigned int*)(0x42A700D4UL))) +#define bM4_PORT_POERA_POUTE06 (*((volatile unsigned int*)(0x42A700D8UL))) +#define bM4_PORT_POERA_POUTE07 (*((volatile unsigned int*)(0x42A700DCUL))) +#define bM4_PORT_POERA_POUTE08 (*((volatile unsigned int*)(0x42A700E0UL))) +#define bM4_PORT_POERA_POUTE09 (*((volatile unsigned int*)(0x42A700E4UL))) +#define bM4_PORT_POERA_POUTE10 (*((volatile unsigned int*)(0x42A700E8UL))) +#define bM4_PORT_POERA_POUTE11 (*((volatile unsigned int*)(0x42A700ECUL))) +#define bM4_PORT_POERA_POUTE12 (*((volatile unsigned int*)(0x42A700F0UL))) +#define bM4_PORT_POERA_POUTE13 (*((volatile unsigned int*)(0x42A700F4UL))) +#define bM4_PORT_POERA_POUTE14 (*((volatile unsigned int*)(0x42A700F8UL))) +#define bM4_PORT_POERA_POUTE15 (*((volatile unsigned int*)(0x42A700FCUL))) +#define bM4_PORT_POSRA_POS00 (*((volatile unsigned int*)(0x42A70100UL))) +#define bM4_PORT_POSRA_POS01 (*((volatile unsigned int*)(0x42A70104UL))) +#define bM4_PORT_POSRA_POS02 (*((volatile unsigned int*)(0x42A70108UL))) +#define bM4_PORT_POSRA_POS03 (*((volatile unsigned int*)(0x42A7010CUL))) +#define bM4_PORT_POSRA_POS04 (*((volatile unsigned int*)(0x42A70110UL))) +#define bM4_PORT_POSRA_POS05 (*((volatile unsigned int*)(0x42A70114UL))) +#define bM4_PORT_POSRA_POS06 (*((volatile unsigned int*)(0x42A70118UL))) +#define bM4_PORT_POSRA_POS07 (*((volatile unsigned int*)(0x42A7011CUL))) +#define bM4_PORT_POSRA_POS08 (*((volatile unsigned int*)(0x42A70120UL))) +#define bM4_PORT_POSRA_POS09 (*((volatile unsigned int*)(0x42A70124UL))) +#define bM4_PORT_POSRA_POS10 (*((volatile unsigned int*)(0x42A70128UL))) +#define bM4_PORT_POSRA_POS11 (*((volatile unsigned int*)(0x42A7012CUL))) +#define bM4_PORT_POSRA_POS12 (*((volatile unsigned int*)(0x42A70130UL))) +#define bM4_PORT_POSRA_POS13 (*((volatile unsigned int*)(0x42A70134UL))) +#define bM4_PORT_POSRA_POS14 (*((volatile unsigned int*)(0x42A70138UL))) +#define bM4_PORT_POSRA_POS15 (*((volatile unsigned int*)(0x42A7013CUL))) +#define bM4_PORT_PORRA_POR00 (*((volatile unsigned int*)(0x42A70140UL))) +#define bM4_PORT_PORRA_POR01 (*((volatile unsigned int*)(0x42A70144UL))) +#define bM4_PORT_PORRA_POR02 (*((volatile unsigned int*)(0x42A70148UL))) +#define bM4_PORT_PORRA_POR03 (*((volatile unsigned int*)(0x42A7014CUL))) +#define bM4_PORT_PORRA_POR04 (*((volatile unsigned int*)(0x42A70150UL))) +#define bM4_PORT_PORRA_POR05 (*((volatile unsigned int*)(0x42A70154UL))) +#define bM4_PORT_PORRA_POR06 (*((volatile unsigned int*)(0x42A70158UL))) +#define bM4_PORT_PORRA_POR07 (*((volatile unsigned int*)(0x42A7015CUL))) +#define bM4_PORT_PORRA_POR08 (*((volatile unsigned int*)(0x42A70160UL))) +#define bM4_PORT_PORRA_POR09 (*((volatile unsigned int*)(0x42A70164UL))) +#define bM4_PORT_PORRA_POR10 (*((volatile unsigned int*)(0x42A70168UL))) +#define bM4_PORT_PORRA_POR11 (*((volatile unsigned int*)(0x42A7016CUL))) +#define bM4_PORT_PORRA_POR12 (*((volatile unsigned int*)(0x42A70170UL))) +#define bM4_PORT_PORRA_POR13 (*((volatile unsigned int*)(0x42A70174UL))) +#define bM4_PORT_PORRA_POR14 (*((volatile unsigned int*)(0x42A70178UL))) +#define bM4_PORT_PORRA_POR15 (*((volatile unsigned int*)(0x42A7017CUL))) +#define bM4_PORT_POTRA_POT00 (*((volatile unsigned int*)(0x42A70180UL))) +#define bM4_PORT_POTRA_POT01 (*((volatile unsigned int*)(0x42A70184UL))) +#define bM4_PORT_POTRA_POT02 (*((volatile unsigned int*)(0x42A70188UL))) +#define bM4_PORT_POTRA_POT03 (*((volatile unsigned int*)(0x42A7018CUL))) +#define bM4_PORT_POTRA_POT04 (*((volatile unsigned int*)(0x42A70190UL))) +#define bM4_PORT_POTRA_POT05 (*((volatile unsigned int*)(0x42A70194UL))) +#define bM4_PORT_POTRA_POT06 (*((volatile unsigned int*)(0x42A70198UL))) +#define bM4_PORT_POTRA_POT07 (*((volatile unsigned int*)(0x42A7019CUL))) +#define bM4_PORT_POTRA_POT08 (*((volatile unsigned int*)(0x42A701A0UL))) +#define bM4_PORT_POTRA_POT09 (*((volatile unsigned int*)(0x42A701A4UL))) +#define bM4_PORT_POTRA_POT10 (*((volatile unsigned int*)(0x42A701A8UL))) +#define bM4_PORT_POTRA_POT11 (*((volatile unsigned int*)(0x42A701ACUL))) +#define bM4_PORT_POTRA_POT12 (*((volatile unsigned int*)(0x42A701B0UL))) +#define bM4_PORT_POTRA_POT13 (*((volatile unsigned int*)(0x42A701B4UL))) +#define bM4_PORT_POTRA_POT14 (*((volatile unsigned int*)(0x42A701B8UL))) +#define bM4_PORT_POTRA_POT15 (*((volatile unsigned int*)(0x42A701BCUL))) +#define bM4_PORT_PIDRB_PIN00 (*((volatile unsigned int*)(0x42A70200UL))) +#define bM4_PORT_PIDRB_PIN01 (*((volatile unsigned int*)(0x42A70204UL))) +#define bM4_PORT_PIDRB_PIN02 (*((volatile unsigned int*)(0x42A70208UL))) +#define bM4_PORT_PIDRB_PIN03 (*((volatile unsigned int*)(0x42A7020CUL))) +#define bM4_PORT_PIDRB_PIN04 (*((volatile unsigned int*)(0x42A70210UL))) +#define bM4_PORT_PIDRB_PIN05 (*((volatile unsigned int*)(0x42A70214UL))) +#define bM4_PORT_PIDRB_PIN06 (*((volatile unsigned int*)(0x42A70218UL))) +#define bM4_PORT_PIDRB_PIN07 (*((volatile unsigned int*)(0x42A7021CUL))) +#define bM4_PORT_PIDRB_PIN08 (*((volatile unsigned int*)(0x42A70220UL))) +#define bM4_PORT_PIDRB_PIN09 (*((volatile unsigned int*)(0x42A70224UL))) +#define bM4_PORT_PIDRB_PIN10 (*((volatile unsigned int*)(0x42A70228UL))) +#define bM4_PORT_PIDRB_PIN11 (*((volatile unsigned int*)(0x42A7022CUL))) +#define bM4_PORT_PIDRB_PIN12 (*((volatile unsigned int*)(0x42A70230UL))) +#define bM4_PORT_PIDRB_PIN13 (*((volatile unsigned int*)(0x42A70234UL))) +#define bM4_PORT_PIDRB_PIN14 (*((volatile unsigned int*)(0x42A70238UL))) +#define bM4_PORT_PIDRB_PIN15 (*((volatile unsigned int*)(0x42A7023CUL))) +#define bM4_PORT_PODRB_POUT00 (*((volatile unsigned int*)(0x42A70280UL))) +#define bM4_PORT_PODRB_POUT01 (*((volatile unsigned int*)(0x42A70284UL))) +#define bM4_PORT_PODRB_POUT02 (*((volatile unsigned int*)(0x42A70288UL))) +#define bM4_PORT_PODRB_POUT03 (*((volatile unsigned int*)(0x42A7028CUL))) +#define bM4_PORT_PODRB_POUT04 (*((volatile unsigned int*)(0x42A70290UL))) +#define bM4_PORT_PODRB_POUT05 (*((volatile unsigned int*)(0x42A70294UL))) +#define bM4_PORT_PODRB_POUT06 (*((volatile unsigned int*)(0x42A70298UL))) +#define bM4_PORT_PODRB_POUT07 (*((volatile unsigned int*)(0x42A7029CUL))) +#define bM4_PORT_PODRB_POUT08 (*((volatile unsigned int*)(0x42A702A0UL))) +#define bM4_PORT_PODRB_POUT09 (*((volatile unsigned int*)(0x42A702A4UL))) +#define bM4_PORT_PODRB_POUT10 (*((volatile unsigned int*)(0x42A702A8UL))) +#define bM4_PORT_PODRB_POUT11 (*((volatile unsigned int*)(0x42A702ACUL))) +#define bM4_PORT_PODRB_POUT12 (*((volatile unsigned int*)(0x42A702B0UL))) +#define bM4_PORT_PODRB_POUT13 (*((volatile unsigned int*)(0x42A702B4UL))) +#define bM4_PORT_PODRB_POUT14 (*((volatile unsigned int*)(0x42A702B8UL))) +#define bM4_PORT_PODRB_POUT15 (*((volatile unsigned int*)(0x42A702BCUL))) +#define bM4_PORT_POERB_POUTE00 (*((volatile unsigned int*)(0x42A702C0UL))) +#define bM4_PORT_POERB_POUTE01 (*((volatile unsigned int*)(0x42A702C4UL))) +#define bM4_PORT_POERB_POUTE02 (*((volatile unsigned int*)(0x42A702C8UL))) +#define bM4_PORT_POERB_POUTE03 (*((volatile unsigned int*)(0x42A702CCUL))) +#define bM4_PORT_POERB_POUTE04 (*((volatile unsigned int*)(0x42A702D0UL))) +#define bM4_PORT_POERB_POUTE05 (*((volatile unsigned int*)(0x42A702D4UL))) +#define bM4_PORT_POERB_POUTE06 (*((volatile unsigned int*)(0x42A702D8UL))) +#define bM4_PORT_POERB_POUTE07 (*((volatile unsigned int*)(0x42A702DCUL))) +#define bM4_PORT_POERB_POUTE08 (*((volatile unsigned int*)(0x42A702E0UL))) +#define bM4_PORT_POERB_POUTE09 (*((volatile unsigned int*)(0x42A702E4UL))) +#define bM4_PORT_POERB_POUTE10 (*((volatile unsigned int*)(0x42A702E8UL))) +#define bM4_PORT_POERB_POUTE11 (*((volatile unsigned int*)(0x42A702ECUL))) +#define bM4_PORT_POERB_POUTE12 (*((volatile unsigned int*)(0x42A702F0UL))) +#define bM4_PORT_POERB_POUTE13 (*((volatile unsigned int*)(0x42A702F4UL))) +#define bM4_PORT_POERB_POUTE14 (*((volatile unsigned int*)(0x42A702F8UL))) +#define bM4_PORT_POERB_POUTE15 (*((volatile unsigned int*)(0x42A702FCUL))) +#define bM4_PORT_POSRB_POS00 (*((volatile unsigned int*)(0x42A70300UL))) +#define bM4_PORT_POSRB_POS01 (*((volatile unsigned int*)(0x42A70304UL))) +#define bM4_PORT_POSRB_POS02 (*((volatile unsigned int*)(0x42A70308UL))) +#define bM4_PORT_POSRB_POS03 (*((volatile unsigned int*)(0x42A7030CUL))) +#define bM4_PORT_POSRB_POS04 (*((volatile unsigned int*)(0x42A70310UL))) +#define bM4_PORT_POSRB_POS05 (*((volatile unsigned int*)(0x42A70314UL))) +#define bM4_PORT_POSRB_POS06 (*((volatile unsigned int*)(0x42A70318UL))) +#define bM4_PORT_POSRB_POS07 (*((volatile unsigned int*)(0x42A7031CUL))) +#define bM4_PORT_POSRB_POS08 (*((volatile unsigned int*)(0x42A70320UL))) +#define bM4_PORT_POSRB_POS09 (*((volatile unsigned int*)(0x42A70324UL))) +#define bM4_PORT_POSRB_POS10 (*((volatile unsigned int*)(0x42A70328UL))) +#define bM4_PORT_POSRB_POS11 (*((volatile unsigned int*)(0x42A7032CUL))) +#define bM4_PORT_POSRB_POS12 (*((volatile unsigned int*)(0x42A70330UL))) +#define bM4_PORT_POSRB_POS13 (*((volatile unsigned int*)(0x42A70334UL))) +#define bM4_PORT_POSRB_POS14 (*((volatile unsigned int*)(0x42A70338UL))) +#define bM4_PORT_POSRB_POS15 (*((volatile unsigned int*)(0x42A7033CUL))) +#define bM4_PORT_PORRB_POR00 (*((volatile unsigned int*)(0x42A70340UL))) +#define bM4_PORT_PORRB_POR01 (*((volatile unsigned int*)(0x42A70344UL))) +#define bM4_PORT_PORRB_POR02 (*((volatile unsigned int*)(0x42A70348UL))) +#define bM4_PORT_PORRB_POR03 (*((volatile unsigned int*)(0x42A7034CUL))) +#define bM4_PORT_PORRB_POR04 (*((volatile unsigned int*)(0x42A70350UL))) +#define bM4_PORT_PORRB_POR05 (*((volatile unsigned int*)(0x42A70354UL))) +#define bM4_PORT_PORRB_POR06 (*((volatile unsigned int*)(0x42A70358UL))) +#define bM4_PORT_PORRB_POR07 (*((volatile unsigned int*)(0x42A7035CUL))) +#define bM4_PORT_PORRB_POR08 (*((volatile unsigned int*)(0x42A70360UL))) +#define bM4_PORT_PORRB_POR09 (*((volatile unsigned int*)(0x42A70364UL))) +#define bM4_PORT_PORRB_POR10 (*((volatile unsigned int*)(0x42A70368UL))) +#define bM4_PORT_PORRB_POR11 (*((volatile unsigned int*)(0x42A7036CUL))) +#define bM4_PORT_PORRB_POR12 (*((volatile unsigned int*)(0x42A70370UL))) +#define bM4_PORT_PORRB_POR13 (*((volatile unsigned int*)(0x42A70374UL))) +#define bM4_PORT_PORRB_POR14 (*((volatile unsigned int*)(0x42A70378UL))) +#define bM4_PORT_PORRB_POR15 (*((volatile unsigned int*)(0x42A7037CUL))) +#define bM4_PORT_POTRB_POT00 (*((volatile unsigned int*)(0x42A70380UL))) +#define bM4_PORT_POTRB_POT01 (*((volatile unsigned int*)(0x42A70384UL))) +#define bM4_PORT_POTRB_POT02 (*((volatile unsigned int*)(0x42A70388UL))) +#define bM4_PORT_POTRB_POT03 (*((volatile unsigned int*)(0x42A7038CUL))) +#define bM4_PORT_POTRB_POT04 (*((volatile unsigned int*)(0x42A70390UL))) +#define bM4_PORT_POTRB_POT05 (*((volatile unsigned int*)(0x42A70394UL))) +#define bM4_PORT_POTRB_POT06 (*((volatile unsigned int*)(0x42A70398UL))) +#define bM4_PORT_POTRB_POT07 (*((volatile unsigned int*)(0x42A7039CUL))) +#define bM4_PORT_POTRB_POT08 (*((volatile unsigned int*)(0x42A703A0UL))) +#define bM4_PORT_POTRB_POT09 (*((volatile unsigned int*)(0x42A703A4UL))) +#define bM4_PORT_POTRB_POT10 (*((volatile unsigned int*)(0x42A703A8UL))) +#define bM4_PORT_POTRB_POT11 (*((volatile unsigned int*)(0x42A703ACUL))) +#define bM4_PORT_POTRB_POT12 (*((volatile unsigned int*)(0x42A703B0UL))) +#define bM4_PORT_POTRB_POT13 (*((volatile unsigned int*)(0x42A703B4UL))) +#define bM4_PORT_POTRB_POT14 (*((volatile unsigned int*)(0x42A703B8UL))) +#define bM4_PORT_POTRB_POT15 (*((volatile unsigned int*)(0x42A703BCUL))) +#define bM4_PORT_PIDRC_PIN00 (*((volatile unsigned int*)(0x42A70400UL))) +#define bM4_PORT_PIDRC_PIN01 (*((volatile unsigned int*)(0x42A70404UL))) +#define bM4_PORT_PIDRC_PIN02 (*((volatile unsigned int*)(0x42A70408UL))) +#define bM4_PORT_PIDRC_PIN03 (*((volatile unsigned int*)(0x42A7040CUL))) +#define bM4_PORT_PIDRC_PIN04 (*((volatile unsigned int*)(0x42A70410UL))) +#define bM4_PORT_PIDRC_PIN05 (*((volatile unsigned int*)(0x42A70414UL))) +#define bM4_PORT_PIDRC_PIN06 (*((volatile unsigned int*)(0x42A70418UL))) +#define bM4_PORT_PIDRC_PIN07 (*((volatile unsigned int*)(0x42A7041CUL))) +#define bM4_PORT_PIDRC_PIN08 (*((volatile unsigned int*)(0x42A70420UL))) +#define bM4_PORT_PIDRC_PIN09 (*((volatile unsigned int*)(0x42A70424UL))) +#define bM4_PORT_PIDRC_PIN10 (*((volatile unsigned int*)(0x42A70428UL))) +#define bM4_PORT_PIDRC_PIN11 (*((volatile unsigned int*)(0x42A7042CUL))) +#define bM4_PORT_PIDRC_PIN12 (*((volatile unsigned int*)(0x42A70430UL))) +#define bM4_PORT_PIDRC_PIN13 (*((volatile unsigned int*)(0x42A70434UL))) +#define bM4_PORT_PIDRC_PIN14 (*((volatile unsigned int*)(0x42A70438UL))) +#define bM4_PORT_PIDRC_PIN15 (*((volatile unsigned int*)(0x42A7043CUL))) +#define bM4_PORT_PODRC_POUT00 (*((volatile unsigned int*)(0x42A70480UL))) +#define bM4_PORT_PODRC_POUT01 (*((volatile unsigned int*)(0x42A70484UL))) +#define bM4_PORT_PODRC_POUT02 (*((volatile unsigned int*)(0x42A70488UL))) +#define bM4_PORT_PODRC_POUT03 (*((volatile unsigned int*)(0x42A7048CUL))) +#define bM4_PORT_PODRC_POUT04 (*((volatile unsigned int*)(0x42A70490UL))) +#define bM4_PORT_PODRC_POUT05 (*((volatile unsigned int*)(0x42A70494UL))) +#define bM4_PORT_PODRC_POUT06 (*((volatile unsigned int*)(0x42A70498UL))) +#define bM4_PORT_PODRC_POUT07 (*((volatile unsigned int*)(0x42A7049CUL))) +#define bM4_PORT_PODRC_POUT08 (*((volatile unsigned int*)(0x42A704A0UL))) +#define bM4_PORT_PODRC_POUT09 (*((volatile unsigned int*)(0x42A704A4UL))) +#define bM4_PORT_PODRC_POUT10 (*((volatile unsigned int*)(0x42A704A8UL))) +#define bM4_PORT_PODRC_POUT11 (*((volatile unsigned int*)(0x42A704ACUL))) +#define bM4_PORT_PODRC_POUT12 (*((volatile unsigned int*)(0x42A704B0UL))) +#define bM4_PORT_PODRC_POUT13 (*((volatile unsigned int*)(0x42A704B4UL))) +#define bM4_PORT_PODRC_POUT14 (*((volatile unsigned int*)(0x42A704B8UL))) +#define bM4_PORT_PODRC_POUT15 (*((volatile unsigned int*)(0x42A704BCUL))) +#define bM4_PORT_POERC_POUTE00 (*((volatile unsigned int*)(0x42A704C0UL))) +#define bM4_PORT_POERC_POUTE01 (*((volatile unsigned int*)(0x42A704C4UL))) +#define bM4_PORT_POERC_POUTE02 (*((volatile unsigned int*)(0x42A704C8UL))) +#define bM4_PORT_POERC_POUTE03 (*((volatile unsigned int*)(0x42A704CCUL))) +#define bM4_PORT_POERC_POUTE04 (*((volatile unsigned int*)(0x42A704D0UL))) +#define bM4_PORT_POERC_POUTE05 (*((volatile unsigned int*)(0x42A704D4UL))) +#define bM4_PORT_POERC_POUTE06 (*((volatile unsigned int*)(0x42A704D8UL))) +#define bM4_PORT_POERC_POUTE07 (*((volatile unsigned int*)(0x42A704DCUL))) +#define bM4_PORT_POERC_POUTE08 (*((volatile unsigned int*)(0x42A704E0UL))) +#define bM4_PORT_POERC_POUTE09 (*((volatile unsigned int*)(0x42A704E4UL))) +#define bM4_PORT_POERC_POUTE10 (*((volatile unsigned int*)(0x42A704E8UL))) +#define bM4_PORT_POERC_POUTE11 (*((volatile unsigned int*)(0x42A704ECUL))) +#define bM4_PORT_POERC_POUTE12 (*((volatile unsigned int*)(0x42A704F0UL))) +#define bM4_PORT_POERC_POUTE13 (*((volatile unsigned int*)(0x42A704F4UL))) +#define bM4_PORT_POERC_POUTE14 (*((volatile unsigned int*)(0x42A704F8UL))) +#define bM4_PORT_POERC_POUTE15 (*((volatile unsigned int*)(0x42A704FCUL))) +#define bM4_PORT_POSRC_POS00 (*((volatile unsigned int*)(0x42A70500UL))) +#define bM4_PORT_POSRC_POS01 (*((volatile unsigned int*)(0x42A70504UL))) +#define bM4_PORT_POSRC_POS02 (*((volatile unsigned int*)(0x42A70508UL))) +#define bM4_PORT_POSRC_POS03 (*((volatile unsigned int*)(0x42A7050CUL))) +#define bM4_PORT_POSRC_POS04 (*((volatile unsigned int*)(0x42A70510UL))) +#define bM4_PORT_POSRC_POS05 (*((volatile unsigned int*)(0x42A70514UL))) +#define bM4_PORT_POSRC_POS06 (*((volatile unsigned int*)(0x42A70518UL))) +#define bM4_PORT_POSRC_POS07 (*((volatile unsigned int*)(0x42A7051CUL))) +#define bM4_PORT_POSRC_POS08 (*((volatile unsigned int*)(0x42A70520UL))) +#define bM4_PORT_POSRC_POS09 (*((volatile unsigned int*)(0x42A70524UL))) +#define bM4_PORT_POSRC_POS10 (*((volatile unsigned int*)(0x42A70528UL))) +#define bM4_PORT_POSRC_POS11 (*((volatile unsigned int*)(0x42A7052CUL))) +#define bM4_PORT_POSRC_POS12 (*((volatile unsigned int*)(0x42A70530UL))) +#define bM4_PORT_POSRC_POS13 (*((volatile unsigned int*)(0x42A70534UL))) +#define bM4_PORT_POSRC_POS14 (*((volatile unsigned int*)(0x42A70538UL))) +#define bM4_PORT_POSRC_POS15 (*((volatile unsigned int*)(0x42A7053CUL))) +#define bM4_PORT_PORRC_POR00 (*((volatile unsigned int*)(0x42A70540UL))) +#define bM4_PORT_PORRC_POR01 (*((volatile unsigned int*)(0x42A70544UL))) +#define bM4_PORT_PORRC_POR02 (*((volatile unsigned int*)(0x42A70548UL))) +#define bM4_PORT_PORRC_POR03 (*((volatile unsigned int*)(0x42A7054CUL))) +#define bM4_PORT_PORRC_POR04 (*((volatile unsigned int*)(0x42A70550UL))) +#define bM4_PORT_PORRC_POR05 (*((volatile unsigned int*)(0x42A70554UL))) +#define bM4_PORT_PORRC_POR06 (*((volatile unsigned int*)(0x42A70558UL))) +#define bM4_PORT_PORRC_POR07 (*((volatile unsigned int*)(0x42A7055CUL))) +#define bM4_PORT_PORRC_POR08 (*((volatile unsigned int*)(0x42A70560UL))) +#define bM4_PORT_PORRC_POR09 (*((volatile unsigned int*)(0x42A70564UL))) +#define bM4_PORT_PORRC_POR10 (*((volatile unsigned int*)(0x42A70568UL))) +#define bM4_PORT_PORRC_POR11 (*((volatile unsigned int*)(0x42A7056CUL))) +#define bM4_PORT_PORRC_POR12 (*((volatile unsigned int*)(0x42A70570UL))) +#define bM4_PORT_PORRC_POR13 (*((volatile unsigned int*)(0x42A70574UL))) +#define bM4_PORT_PORRC_POR14 (*((volatile unsigned int*)(0x42A70578UL))) +#define bM4_PORT_PORRC_POR15 (*((volatile unsigned int*)(0x42A7057CUL))) +#define bM4_PORT_POTRC_POT00 (*((volatile unsigned int*)(0x42A70580UL))) +#define bM4_PORT_POTRC_POT01 (*((volatile unsigned int*)(0x42A70584UL))) +#define bM4_PORT_POTRC_POT02 (*((volatile unsigned int*)(0x42A70588UL))) +#define bM4_PORT_POTRC_POT03 (*((volatile unsigned int*)(0x42A7058CUL))) +#define bM4_PORT_POTRC_POT04 (*((volatile unsigned int*)(0x42A70590UL))) +#define bM4_PORT_POTRC_POT05 (*((volatile unsigned int*)(0x42A70594UL))) +#define bM4_PORT_POTRC_POT06 (*((volatile unsigned int*)(0x42A70598UL))) +#define bM4_PORT_POTRC_POT07 (*((volatile unsigned int*)(0x42A7059CUL))) +#define bM4_PORT_POTRC_POT08 (*((volatile unsigned int*)(0x42A705A0UL))) +#define bM4_PORT_POTRC_POT09 (*((volatile unsigned int*)(0x42A705A4UL))) +#define bM4_PORT_POTRC_POT10 (*((volatile unsigned int*)(0x42A705A8UL))) +#define bM4_PORT_POTRC_POT11 (*((volatile unsigned int*)(0x42A705ACUL))) +#define bM4_PORT_POTRC_POT12 (*((volatile unsigned int*)(0x42A705B0UL))) +#define bM4_PORT_POTRC_POT13 (*((volatile unsigned int*)(0x42A705B4UL))) +#define bM4_PORT_POTRC_POT14 (*((volatile unsigned int*)(0x42A705B8UL))) +#define bM4_PORT_POTRC_POT15 (*((volatile unsigned int*)(0x42A705BCUL))) +#define bM4_PORT_PIDRD_PIN00 (*((volatile unsigned int*)(0x42A70600UL))) +#define bM4_PORT_PIDRD_PIN01 (*((volatile unsigned int*)(0x42A70604UL))) +#define bM4_PORT_PIDRD_PIN02 (*((volatile unsigned int*)(0x42A70608UL))) +#define bM4_PORT_PIDRD_PIN03 (*((volatile unsigned int*)(0x42A7060CUL))) +#define bM4_PORT_PIDRD_PIN04 (*((volatile unsigned int*)(0x42A70610UL))) +#define bM4_PORT_PIDRD_PIN05 (*((volatile unsigned int*)(0x42A70614UL))) +#define bM4_PORT_PIDRD_PIN06 (*((volatile unsigned int*)(0x42A70618UL))) +#define bM4_PORT_PIDRD_PIN07 (*((volatile unsigned int*)(0x42A7061CUL))) +#define bM4_PORT_PIDRD_PIN08 (*((volatile unsigned int*)(0x42A70620UL))) +#define bM4_PORT_PIDRD_PIN09 (*((volatile unsigned int*)(0x42A70624UL))) +#define bM4_PORT_PIDRD_PIN10 (*((volatile unsigned int*)(0x42A70628UL))) +#define bM4_PORT_PIDRD_PIN11 (*((volatile unsigned int*)(0x42A7062CUL))) +#define bM4_PORT_PIDRD_PIN12 (*((volatile unsigned int*)(0x42A70630UL))) +#define bM4_PORT_PIDRD_PIN13 (*((volatile unsigned int*)(0x42A70634UL))) +#define bM4_PORT_PIDRD_PIN14 (*((volatile unsigned int*)(0x42A70638UL))) +#define bM4_PORT_PIDRD_PIN15 (*((volatile unsigned int*)(0x42A7063CUL))) +#define bM4_PORT_PODRD_POUT00 (*((volatile unsigned int*)(0x42A70680UL))) +#define bM4_PORT_PODRD_POUT01 (*((volatile unsigned int*)(0x42A70684UL))) +#define bM4_PORT_PODRD_POUT02 (*((volatile unsigned int*)(0x42A70688UL))) +#define bM4_PORT_PODRD_POUT03 (*((volatile unsigned int*)(0x42A7068CUL))) +#define bM4_PORT_PODRD_POUT04 (*((volatile unsigned int*)(0x42A70690UL))) +#define bM4_PORT_PODRD_POUT05 (*((volatile unsigned int*)(0x42A70694UL))) +#define bM4_PORT_PODRD_POUT06 (*((volatile unsigned int*)(0x42A70698UL))) +#define bM4_PORT_PODRD_POUT07 (*((volatile unsigned int*)(0x42A7069CUL))) +#define bM4_PORT_PODRD_POUT08 (*((volatile unsigned int*)(0x42A706A0UL))) +#define bM4_PORT_PODRD_POUT09 (*((volatile unsigned int*)(0x42A706A4UL))) +#define bM4_PORT_PODRD_POUT10 (*((volatile unsigned int*)(0x42A706A8UL))) +#define bM4_PORT_PODRD_POUT11 (*((volatile unsigned int*)(0x42A706ACUL))) +#define bM4_PORT_PODRD_POUT12 (*((volatile unsigned int*)(0x42A706B0UL))) +#define bM4_PORT_PODRD_POUT13 (*((volatile unsigned int*)(0x42A706B4UL))) +#define bM4_PORT_PODRD_POUT14 (*((volatile unsigned int*)(0x42A706B8UL))) +#define bM4_PORT_PODRD_POUT15 (*((volatile unsigned int*)(0x42A706BCUL))) +#define bM4_PORT_POERD_POUTE00 (*((volatile unsigned int*)(0x42A706C0UL))) +#define bM4_PORT_POERD_POUTE01 (*((volatile unsigned int*)(0x42A706C4UL))) +#define bM4_PORT_POERD_POUTE02 (*((volatile unsigned int*)(0x42A706C8UL))) +#define bM4_PORT_POERD_POUTE03 (*((volatile unsigned int*)(0x42A706CCUL))) +#define bM4_PORT_POERD_POUTE04 (*((volatile unsigned int*)(0x42A706D0UL))) +#define bM4_PORT_POERD_POUTE05 (*((volatile unsigned int*)(0x42A706D4UL))) +#define bM4_PORT_POERD_POUTE06 (*((volatile unsigned int*)(0x42A706D8UL))) +#define bM4_PORT_POERD_POUTE07 (*((volatile unsigned int*)(0x42A706DCUL))) +#define bM4_PORT_POERD_POUTE08 (*((volatile unsigned int*)(0x42A706E0UL))) +#define bM4_PORT_POERD_POUTE09 (*((volatile unsigned int*)(0x42A706E4UL))) +#define bM4_PORT_POERD_POUTE10 (*((volatile unsigned int*)(0x42A706E8UL))) +#define bM4_PORT_POERD_POUTE11 (*((volatile unsigned int*)(0x42A706ECUL))) +#define bM4_PORT_POERD_POUTE12 (*((volatile unsigned int*)(0x42A706F0UL))) +#define bM4_PORT_POERD_POUTE13 (*((volatile unsigned int*)(0x42A706F4UL))) +#define bM4_PORT_POERD_POUTE14 (*((volatile unsigned int*)(0x42A706F8UL))) +#define bM4_PORT_POERD_POUTE15 (*((volatile unsigned int*)(0x42A706FCUL))) +#define bM4_PORT_POSRD_POS00 (*((volatile unsigned int*)(0x42A70700UL))) +#define bM4_PORT_POSRD_POS01 (*((volatile unsigned int*)(0x42A70704UL))) +#define bM4_PORT_POSRD_POS02 (*((volatile unsigned int*)(0x42A70708UL))) +#define bM4_PORT_POSRD_POS03 (*((volatile unsigned int*)(0x42A7070CUL))) +#define bM4_PORT_POSRD_POS04 (*((volatile unsigned int*)(0x42A70710UL))) +#define bM4_PORT_POSRD_POS05 (*((volatile unsigned int*)(0x42A70714UL))) +#define bM4_PORT_POSRD_POS06 (*((volatile unsigned int*)(0x42A70718UL))) +#define bM4_PORT_POSRD_POS07 (*((volatile unsigned int*)(0x42A7071CUL))) +#define bM4_PORT_POSRD_POS08 (*((volatile unsigned int*)(0x42A70720UL))) +#define bM4_PORT_POSRD_POS09 (*((volatile unsigned int*)(0x42A70724UL))) +#define bM4_PORT_POSRD_POS10 (*((volatile unsigned int*)(0x42A70728UL))) +#define bM4_PORT_POSRD_POS11 (*((volatile unsigned int*)(0x42A7072CUL))) +#define bM4_PORT_POSRD_POS12 (*((volatile unsigned int*)(0x42A70730UL))) +#define bM4_PORT_POSRD_POS13 (*((volatile unsigned int*)(0x42A70734UL))) +#define bM4_PORT_POSRD_POS14 (*((volatile unsigned int*)(0x42A70738UL))) +#define bM4_PORT_POSRD_POS15 (*((volatile unsigned int*)(0x42A7073CUL))) +#define bM4_PORT_PORRD_POR00 (*((volatile unsigned int*)(0x42A70740UL))) +#define bM4_PORT_PORRD_POR01 (*((volatile unsigned int*)(0x42A70744UL))) +#define bM4_PORT_PORRD_POR02 (*((volatile unsigned int*)(0x42A70748UL))) +#define bM4_PORT_PORRD_POR03 (*((volatile unsigned int*)(0x42A7074CUL))) +#define bM4_PORT_PORRD_POR04 (*((volatile unsigned int*)(0x42A70750UL))) +#define bM4_PORT_PORRD_POR05 (*((volatile unsigned int*)(0x42A70754UL))) +#define bM4_PORT_PORRD_POR06 (*((volatile unsigned int*)(0x42A70758UL))) +#define bM4_PORT_PORRD_POR07 (*((volatile unsigned int*)(0x42A7075CUL))) +#define bM4_PORT_PORRD_POR08 (*((volatile unsigned int*)(0x42A70760UL))) +#define bM4_PORT_PORRD_POR09 (*((volatile unsigned int*)(0x42A70764UL))) +#define bM4_PORT_PORRD_POR10 (*((volatile unsigned int*)(0x42A70768UL))) +#define bM4_PORT_PORRD_POR11 (*((volatile unsigned int*)(0x42A7076CUL))) +#define bM4_PORT_PORRD_POR12 (*((volatile unsigned int*)(0x42A70770UL))) +#define bM4_PORT_PORRD_POR13 (*((volatile unsigned int*)(0x42A70774UL))) +#define bM4_PORT_PORRD_POR14 (*((volatile unsigned int*)(0x42A70778UL))) +#define bM4_PORT_PORRD_POR15 (*((volatile unsigned int*)(0x42A7077CUL))) +#define bM4_PORT_POTRD_POT00 (*((volatile unsigned int*)(0x42A70780UL))) +#define bM4_PORT_POTRD_POT01 (*((volatile unsigned int*)(0x42A70784UL))) +#define bM4_PORT_POTRD_POT02 (*((volatile unsigned int*)(0x42A70788UL))) +#define bM4_PORT_POTRD_POT03 (*((volatile unsigned int*)(0x42A7078CUL))) +#define bM4_PORT_POTRD_POT04 (*((volatile unsigned int*)(0x42A70790UL))) +#define bM4_PORT_POTRD_POT05 (*((volatile unsigned int*)(0x42A70794UL))) +#define bM4_PORT_POTRD_POT06 (*((volatile unsigned int*)(0x42A70798UL))) +#define bM4_PORT_POTRD_POT07 (*((volatile unsigned int*)(0x42A7079CUL))) +#define bM4_PORT_POTRD_POT08 (*((volatile unsigned int*)(0x42A707A0UL))) +#define bM4_PORT_POTRD_POT09 (*((volatile unsigned int*)(0x42A707A4UL))) +#define bM4_PORT_POTRD_POT10 (*((volatile unsigned int*)(0x42A707A8UL))) +#define bM4_PORT_POTRD_POT11 (*((volatile unsigned int*)(0x42A707ACUL))) +#define bM4_PORT_POTRD_POT12 (*((volatile unsigned int*)(0x42A707B0UL))) +#define bM4_PORT_POTRD_POT13 (*((volatile unsigned int*)(0x42A707B4UL))) +#define bM4_PORT_POTRD_POT14 (*((volatile unsigned int*)(0x42A707B8UL))) +#define bM4_PORT_POTRD_POT15 (*((volatile unsigned int*)(0x42A707BCUL))) +#define bM4_PORT_PIDRE_PIN00 (*((volatile unsigned int*)(0x42A70800UL))) +#define bM4_PORT_PIDRE_PIN01 (*((volatile unsigned int*)(0x42A70804UL))) +#define bM4_PORT_PIDRE_PIN02 (*((volatile unsigned int*)(0x42A70808UL))) +#define bM4_PORT_PIDRE_PIN03 (*((volatile unsigned int*)(0x42A7080CUL))) +#define bM4_PORT_PIDRE_PIN04 (*((volatile unsigned int*)(0x42A70810UL))) +#define bM4_PORT_PIDRE_PIN05 (*((volatile unsigned int*)(0x42A70814UL))) +#define bM4_PORT_PIDRE_PIN06 (*((volatile unsigned int*)(0x42A70818UL))) +#define bM4_PORT_PIDRE_PIN07 (*((volatile unsigned int*)(0x42A7081CUL))) +#define bM4_PORT_PIDRE_PIN08 (*((volatile unsigned int*)(0x42A70820UL))) +#define bM4_PORT_PIDRE_PIN09 (*((volatile unsigned int*)(0x42A70824UL))) +#define bM4_PORT_PIDRE_PIN10 (*((volatile unsigned int*)(0x42A70828UL))) +#define bM4_PORT_PIDRE_PIN11 (*((volatile unsigned int*)(0x42A7082CUL))) +#define bM4_PORT_PIDRE_PIN12 (*((volatile unsigned int*)(0x42A70830UL))) +#define bM4_PORT_PIDRE_PIN13 (*((volatile unsigned int*)(0x42A70834UL))) +#define bM4_PORT_PIDRE_PIN14 (*((volatile unsigned int*)(0x42A70838UL))) +#define bM4_PORT_PIDRE_PIN15 (*((volatile unsigned int*)(0x42A7083CUL))) +#define bM4_PORT_PODRE_POUT00 (*((volatile unsigned int*)(0x42A70880UL))) +#define bM4_PORT_PODRE_POUT01 (*((volatile unsigned int*)(0x42A70884UL))) +#define bM4_PORT_PODRE_POUT02 (*((volatile unsigned int*)(0x42A70888UL))) +#define bM4_PORT_PODRE_POUT03 (*((volatile unsigned int*)(0x42A7088CUL))) +#define bM4_PORT_PODRE_POUT04 (*((volatile unsigned int*)(0x42A70890UL))) +#define bM4_PORT_PODRE_POUT05 (*((volatile unsigned int*)(0x42A70894UL))) +#define bM4_PORT_PODRE_POUT06 (*((volatile unsigned int*)(0x42A70898UL))) +#define bM4_PORT_PODRE_POUT07 (*((volatile unsigned int*)(0x42A7089CUL))) +#define bM4_PORT_PODRE_POUT08 (*((volatile unsigned int*)(0x42A708A0UL))) +#define bM4_PORT_PODRE_POUT09 (*((volatile unsigned int*)(0x42A708A4UL))) +#define bM4_PORT_PODRE_POUT10 (*((volatile unsigned int*)(0x42A708A8UL))) +#define bM4_PORT_PODRE_POUT11 (*((volatile unsigned int*)(0x42A708ACUL))) +#define bM4_PORT_PODRE_POUT12 (*((volatile unsigned int*)(0x42A708B0UL))) +#define bM4_PORT_PODRE_POUT13 (*((volatile unsigned int*)(0x42A708B4UL))) +#define bM4_PORT_PODRE_POUT14 (*((volatile unsigned int*)(0x42A708B8UL))) +#define bM4_PORT_PODRE_POUT15 (*((volatile unsigned int*)(0x42A708BCUL))) +#define bM4_PORT_POERE_POUTE00 (*((volatile unsigned int*)(0x42A708C0UL))) +#define bM4_PORT_POERE_POUTE01 (*((volatile unsigned int*)(0x42A708C4UL))) +#define bM4_PORT_POERE_POUTE02 (*((volatile unsigned int*)(0x42A708C8UL))) +#define bM4_PORT_POERE_POUTE03 (*((volatile unsigned int*)(0x42A708CCUL))) +#define bM4_PORT_POERE_POUTE04 (*((volatile unsigned int*)(0x42A708D0UL))) +#define bM4_PORT_POERE_POUTE05 (*((volatile unsigned int*)(0x42A708D4UL))) +#define bM4_PORT_POERE_POUTE06 (*((volatile unsigned int*)(0x42A708D8UL))) +#define bM4_PORT_POERE_POUTE07 (*((volatile unsigned int*)(0x42A708DCUL))) +#define bM4_PORT_POERE_POUTE08 (*((volatile unsigned int*)(0x42A708E0UL))) +#define bM4_PORT_POERE_POUTE09 (*((volatile unsigned int*)(0x42A708E4UL))) +#define bM4_PORT_POERE_POUTE10 (*((volatile unsigned int*)(0x42A708E8UL))) +#define bM4_PORT_POERE_POUTE11 (*((volatile unsigned int*)(0x42A708ECUL))) +#define bM4_PORT_POERE_POUTE12 (*((volatile unsigned int*)(0x42A708F0UL))) +#define bM4_PORT_POERE_POUTE13 (*((volatile unsigned int*)(0x42A708F4UL))) +#define bM4_PORT_POERE_POUTE14 (*((volatile unsigned int*)(0x42A708F8UL))) +#define bM4_PORT_POERE_POUTE15 (*((volatile unsigned int*)(0x42A708FCUL))) +#define bM4_PORT_POSRE_POS00 (*((volatile unsigned int*)(0x42A70900UL))) +#define bM4_PORT_POSRE_POS01 (*((volatile unsigned int*)(0x42A70904UL))) +#define bM4_PORT_POSRE_POS02 (*((volatile unsigned int*)(0x42A70908UL))) +#define bM4_PORT_POSRE_POS03 (*((volatile unsigned int*)(0x42A7090CUL))) +#define bM4_PORT_POSRE_POS04 (*((volatile unsigned int*)(0x42A70910UL))) +#define bM4_PORT_POSRE_POS05 (*((volatile unsigned int*)(0x42A70914UL))) +#define bM4_PORT_POSRE_POS06 (*((volatile unsigned int*)(0x42A70918UL))) +#define bM4_PORT_POSRE_POS07 (*((volatile unsigned int*)(0x42A7091CUL))) +#define bM4_PORT_POSRE_POS08 (*((volatile unsigned int*)(0x42A70920UL))) +#define bM4_PORT_POSRE_POS09 (*((volatile unsigned int*)(0x42A70924UL))) +#define bM4_PORT_POSRE_POS10 (*((volatile unsigned int*)(0x42A70928UL))) +#define bM4_PORT_POSRE_POS11 (*((volatile unsigned int*)(0x42A7092CUL))) +#define bM4_PORT_POSRE_POS12 (*((volatile unsigned int*)(0x42A70930UL))) +#define bM4_PORT_POSRE_POS13 (*((volatile unsigned int*)(0x42A70934UL))) +#define bM4_PORT_POSRE_POS14 (*((volatile unsigned int*)(0x42A70938UL))) +#define bM4_PORT_POSRE_POS15 (*((volatile unsigned int*)(0x42A7093CUL))) +#define bM4_PORT_PORRE_POR00 (*((volatile unsigned int*)(0x42A70940UL))) +#define bM4_PORT_PORRE_POR01 (*((volatile unsigned int*)(0x42A70944UL))) +#define bM4_PORT_PORRE_POR02 (*((volatile unsigned int*)(0x42A70948UL))) +#define bM4_PORT_PORRE_POR03 (*((volatile unsigned int*)(0x42A7094CUL))) +#define bM4_PORT_PORRE_POR04 (*((volatile unsigned int*)(0x42A70950UL))) +#define bM4_PORT_PORRE_POR05 (*((volatile unsigned int*)(0x42A70954UL))) +#define bM4_PORT_PORRE_POR06 (*((volatile unsigned int*)(0x42A70958UL))) +#define bM4_PORT_PORRE_POR07 (*((volatile unsigned int*)(0x42A7095CUL))) +#define bM4_PORT_PORRE_POR08 (*((volatile unsigned int*)(0x42A70960UL))) +#define bM4_PORT_PORRE_POR09 (*((volatile unsigned int*)(0x42A70964UL))) +#define bM4_PORT_PORRE_POR10 (*((volatile unsigned int*)(0x42A70968UL))) +#define bM4_PORT_PORRE_POR11 (*((volatile unsigned int*)(0x42A7096CUL))) +#define bM4_PORT_PORRE_POR12 (*((volatile unsigned int*)(0x42A70970UL))) +#define bM4_PORT_PORRE_POR13 (*((volatile unsigned int*)(0x42A70974UL))) +#define bM4_PORT_PORRE_POR14 (*((volatile unsigned int*)(0x42A70978UL))) +#define bM4_PORT_PORRE_POR15 (*((volatile unsigned int*)(0x42A7097CUL))) +#define bM4_PORT_POTRE_POT00 (*((volatile unsigned int*)(0x42A70980UL))) +#define bM4_PORT_POTRE_POT01 (*((volatile unsigned int*)(0x42A70984UL))) +#define bM4_PORT_POTRE_POT02 (*((volatile unsigned int*)(0x42A70988UL))) +#define bM4_PORT_POTRE_POT03 (*((volatile unsigned int*)(0x42A7098CUL))) +#define bM4_PORT_POTRE_POT04 (*((volatile unsigned int*)(0x42A70990UL))) +#define bM4_PORT_POTRE_POT05 (*((volatile unsigned int*)(0x42A70994UL))) +#define bM4_PORT_POTRE_POT06 (*((volatile unsigned int*)(0x42A70998UL))) +#define bM4_PORT_POTRE_POT07 (*((volatile unsigned int*)(0x42A7099CUL))) +#define bM4_PORT_POTRE_POT08 (*((volatile unsigned int*)(0x42A709A0UL))) +#define bM4_PORT_POTRE_POT09 (*((volatile unsigned int*)(0x42A709A4UL))) +#define bM4_PORT_POTRE_POT10 (*((volatile unsigned int*)(0x42A709A8UL))) +#define bM4_PORT_POTRE_POT11 (*((volatile unsigned int*)(0x42A709ACUL))) +#define bM4_PORT_POTRE_POT12 (*((volatile unsigned int*)(0x42A709B0UL))) +#define bM4_PORT_POTRE_POT13 (*((volatile unsigned int*)(0x42A709B4UL))) +#define bM4_PORT_POTRE_POT14 (*((volatile unsigned int*)(0x42A709B8UL))) +#define bM4_PORT_POTRE_POT15 (*((volatile unsigned int*)(0x42A709BCUL))) +#define bM4_PORT_PIDRH_PIN00 (*((volatile unsigned int*)(0x42A70A00UL))) +#define bM4_PORT_PIDRH_PIN01 (*((volatile unsigned int*)(0x42A70A04UL))) +#define bM4_PORT_PIDRH_PIN02 (*((volatile unsigned int*)(0x42A70A08UL))) +#define bM4_PORT_PODRH_POUT00 (*((volatile unsigned int*)(0x42A70A80UL))) +#define bM4_PORT_PODRH_POUT01 (*((volatile unsigned int*)(0x42A70A84UL))) +#define bM4_PORT_PODRH_POUT02 (*((volatile unsigned int*)(0x42A70A88UL))) +#define bM4_PORT_POERH_POUTE00 (*((volatile unsigned int*)(0x42A70AC0UL))) +#define bM4_PORT_POERH_POUTE01 (*((volatile unsigned int*)(0x42A70AC4UL))) +#define bM4_PORT_POERH_POUTE02 (*((volatile unsigned int*)(0x42A70AC8UL))) +#define bM4_PORT_POSRH_POS00 (*((volatile unsigned int*)(0x42A70B00UL))) +#define bM4_PORT_POSRH_POS01 (*((volatile unsigned int*)(0x42A70B04UL))) +#define bM4_PORT_POSRH_POS02 (*((volatile unsigned int*)(0x42A70B08UL))) +#define bM4_PORT_PORRH_POR00 (*((volatile unsigned int*)(0x42A70B40UL))) +#define bM4_PORT_PORRH_POR01 (*((volatile unsigned int*)(0x42A70B44UL))) +#define bM4_PORT_PORRH_POR02 (*((volatile unsigned int*)(0x42A70B48UL))) +#define bM4_PORT_POTRH_POT00 (*((volatile unsigned int*)(0x42A70B80UL))) +#define bM4_PORT_POTRH_POT01 (*((volatile unsigned int*)(0x42A70B84UL))) +#define bM4_PORT_POTRH_POT02 (*((volatile unsigned int*)(0x42A70B88UL))) +#define bM4_PORT_PSPCR_SPFE0 (*((volatile unsigned int*)(0x42A77E80UL))) +#define bM4_PORT_PSPCR_SPFE1 (*((volatile unsigned int*)(0x42A77E84UL))) +#define bM4_PORT_PSPCR_SPFE2 (*((volatile unsigned int*)(0x42A77E88UL))) +#define bM4_PORT_PSPCR_SPFE3 (*((volatile unsigned int*)(0x42A77E8CUL))) +#define bM4_PORT_PSPCR_SPFE4 (*((volatile unsigned int*)(0x42A77E90UL))) +#define bM4_PORT_PCCR_BFSEL0 (*((volatile unsigned int*)(0x42A77F00UL))) +#define bM4_PORT_PCCR_BFSEL1 (*((volatile unsigned int*)(0x42A77F04UL))) +#define bM4_PORT_PCCR_BFSEL2 (*((volatile unsigned int*)(0x42A77F08UL))) +#define bM4_PORT_PCCR_BFSEL3 (*((volatile unsigned int*)(0x42A77F0CUL))) +#define bM4_PORT_PCCR_RDWT0 (*((volatile unsigned int*)(0x42A77F38UL))) +#define bM4_PORT_PCCR_RDWT1 (*((volatile unsigned int*)(0x42A77F3CUL))) +#define bM4_PORT_PINAER_PINAE0 (*((volatile unsigned int*)(0x42A77F40UL))) +#define bM4_PORT_PINAER_PINAE1 (*((volatile unsigned int*)(0x42A77F44UL))) +#define bM4_PORT_PINAER_PINAE2 (*((volatile unsigned int*)(0x42A77F48UL))) +#define bM4_PORT_PINAER_PINAE3 (*((volatile unsigned int*)(0x42A77F4CUL))) +#define bM4_PORT_PINAER_PINAE4 (*((volatile unsigned int*)(0x42A77F50UL))) +#define bM4_PORT_PINAER_PINAE5 (*((volatile unsigned int*)(0x42A77F54UL))) +#define bM4_PORT_PWPR_WE (*((volatile unsigned int*)(0x42A77F80UL))) +#define bM4_PORT_PWPR_WP0 (*((volatile unsigned int*)(0x42A77FA0UL))) +#define bM4_PORT_PWPR_WP1 (*((volatile unsigned int*)(0x42A77FA4UL))) +#define bM4_PORT_PWPR_WP2 (*((volatile unsigned int*)(0x42A77FA8UL))) +#define bM4_PORT_PWPR_WP3 (*((volatile unsigned int*)(0x42A77FACUL))) +#define bM4_PORT_PWPR_WP4 (*((volatile unsigned int*)(0x42A77FB0UL))) +#define bM4_PORT_PWPR_WP5 (*((volatile unsigned int*)(0x42A77FB4UL))) +#define bM4_PORT_PWPR_WP6 (*((volatile unsigned int*)(0x42A77FB8UL))) +#define bM4_PORT_PWPR_WP7 (*((volatile unsigned int*)(0x42A77FBCUL))) +#define bM4_PORT_PCRA0_POUT (*((volatile unsigned int*)(0x42A78000UL))) +#define bM4_PORT_PCRA0_POUTE (*((volatile unsigned int*)(0x42A78004UL))) +#define bM4_PORT_PCRA0_NOD (*((volatile unsigned int*)(0x42A78008UL))) +#define bM4_PORT_PCRA0_DRV0 (*((volatile unsigned int*)(0x42A78010UL))) +#define bM4_PORT_PCRA0_DRV1 (*((volatile unsigned int*)(0x42A78014UL))) +#define bM4_PORT_PCRA0_PUU (*((volatile unsigned int*)(0x42A78018UL))) +#define bM4_PORT_PCRA0_PIN (*((volatile unsigned int*)(0x42A78020UL))) +#define bM4_PORT_PCRA0_INVE (*((volatile unsigned int*)(0x42A78024UL))) +#define bM4_PORT_PCRA0_INTE (*((volatile unsigned int*)(0x42A78030UL))) +#define bM4_PORT_PCRA0_LTE (*((volatile unsigned int*)(0x42A78038UL))) +#define bM4_PORT_PCRA0_DDIS (*((volatile unsigned int*)(0x42A7803CUL))) +#define bM4_PORT_PFSRA0_FSEL0 (*((volatile unsigned int*)(0x42A78040UL))) +#define bM4_PORT_PFSRA0_FSEL1 (*((volatile unsigned int*)(0x42A78044UL))) +#define bM4_PORT_PFSRA0_FSEL2 (*((volatile unsigned int*)(0x42A78048UL))) +#define bM4_PORT_PFSRA0_FSEL3 (*((volatile unsigned int*)(0x42A7804CUL))) +#define bM4_PORT_PFSRA0_FSEL4 (*((volatile unsigned int*)(0x42A78050UL))) +#define bM4_PORT_PFSRA0_FSEL5 (*((volatile unsigned int*)(0x42A78054UL))) +#define bM4_PORT_PFSRA0_BFE (*((volatile unsigned int*)(0x42A78060UL))) +#define bM4_PORT_PCRA1_POUT (*((volatile unsigned int*)(0x42A78080UL))) +#define bM4_PORT_PCRA1_POUTE (*((volatile unsigned int*)(0x42A78084UL))) +#define bM4_PORT_PCRA1_NOD (*((volatile unsigned int*)(0x42A78088UL))) +#define bM4_PORT_PCRA1_DRV0 (*((volatile unsigned int*)(0x42A78090UL))) +#define bM4_PORT_PCRA1_DRV1 (*((volatile unsigned int*)(0x42A78094UL))) +#define bM4_PORT_PCRA1_PUU (*((volatile unsigned int*)(0x42A78098UL))) +#define bM4_PORT_PCRA1_PIN (*((volatile unsigned int*)(0x42A780A0UL))) +#define bM4_PORT_PCRA1_INVE (*((volatile unsigned int*)(0x42A780A4UL))) +#define bM4_PORT_PCRA1_INTE (*((volatile unsigned int*)(0x42A780B0UL))) +#define bM4_PORT_PCRA1_LTE (*((volatile unsigned int*)(0x42A780B8UL))) +#define bM4_PORT_PCRA1_DDIS (*((volatile unsigned int*)(0x42A780BCUL))) +#define bM4_PORT_PFSRA1_FSEL0 (*((volatile unsigned int*)(0x42A780C0UL))) +#define bM4_PORT_PFSRA1_FSEL1 (*((volatile unsigned int*)(0x42A780C4UL))) +#define bM4_PORT_PFSRA1_FSEL2 (*((volatile unsigned int*)(0x42A780C8UL))) +#define bM4_PORT_PFSRA1_FSEL3 (*((volatile unsigned int*)(0x42A780CCUL))) +#define bM4_PORT_PFSRA1_FSEL4 (*((volatile unsigned int*)(0x42A780D0UL))) +#define bM4_PORT_PFSRA1_FSEL5 (*((volatile unsigned int*)(0x42A780D4UL))) +#define bM4_PORT_PFSRA1_BFE (*((volatile unsigned int*)(0x42A780E0UL))) +#define bM4_PORT_PCRA2_POUT (*((volatile unsigned int*)(0x42A78100UL))) +#define bM4_PORT_PCRA2_POUTE (*((volatile unsigned int*)(0x42A78104UL))) +#define bM4_PORT_PCRA2_NOD (*((volatile unsigned int*)(0x42A78108UL))) +#define bM4_PORT_PCRA2_DRV0 (*((volatile unsigned int*)(0x42A78110UL))) +#define bM4_PORT_PCRA2_DRV1 (*((volatile unsigned int*)(0x42A78114UL))) +#define bM4_PORT_PCRA2_PUU (*((volatile unsigned int*)(0x42A78118UL))) +#define bM4_PORT_PCRA2_PIN (*((volatile unsigned int*)(0x42A78120UL))) +#define bM4_PORT_PCRA2_INVE (*((volatile unsigned int*)(0x42A78124UL))) +#define bM4_PORT_PCRA2_INTE (*((volatile unsigned int*)(0x42A78130UL))) +#define bM4_PORT_PCRA2_LTE (*((volatile unsigned int*)(0x42A78138UL))) +#define bM4_PORT_PCRA2_DDIS (*((volatile unsigned int*)(0x42A7813CUL))) +#define bM4_PORT_PFSRA2_FSEL0 (*((volatile unsigned int*)(0x42A78140UL))) +#define bM4_PORT_PFSRA2_FSEL1 (*((volatile unsigned int*)(0x42A78144UL))) +#define bM4_PORT_PFSRA2_FSEL2 (*((volatile unsigned int*)(0x42A78148UL))) +#define bM4_PORT_PFSRA2_FSEL3 (*((volatile unsigned int*)(0x42A7814CUL))) +#define bM4_PORT_PFSRA2_FSEL4 (*((volatile unsigned int*)(0x42A78150UL))) +#define bM4_PORT_PFSRA2_FSEL5 (*((volatile unsigned int*)(0x42A78154UL))) +#define bM4_PORT_PFSRA2_BFE (*((volatile unsigned int*)(0x42A78160UL))) +#define bM4_PORT_PCRA3_POUT (*((volatile unsigned int*)(0x42A78180UL))) +#define bM4_PORT_PCRA3_POUTE (*((volatile unsigned int*)(0x42A78184UL))) +#define bM4_PORT_PCRA3_NOD (*((volatile unsigned int*)(0x42A78188UL))) +#define bM4_PORT_PCRA3_DRV0 (*((volatile unsigned int*)(0x42A78190UL))) +#define bM4_PORT_PCRA3_DRV1 (*((volatile unsigned int*)(0x42A78194UL))) +#define bM4_PORT_PCRA3_PUU (*((volatile unsigned int*)(0x42A78198UL))) +#define bM4_PORT_PCRA3_PIN (*((volatile unsigned int*)(0x42A781A0UL))) +#define bM4_PORT_PCRA3_INVE (*((volatile unsigned int*)(0x42A781A4UL))) +#define bM4_PORT_PCRA3_INTE (*((volatile unsigned int*)(0x42A781B0UL))) +#define bM4_PORT_PCRA3_LTE (*((volatile unsigned int*)(0x42A781B8UL))) +#define bM4_PORT_PCRA3_DDIS (*((volatile unsigned int*)(0x42A781BCUL))) +#define bM4_PORT_PFSRA3_FSEL0 (*((volatile unsigned int*)(0x42A781C0UL))) +#define bM4_PORT_PFSRA3_FSEL1 (*((volatile unsigned int*)(0x42A781C4UL))) +#define bM4_PORT_PFSRA3_FSEL2 (*((volatile unsigned int*)(0x42A781C8UL))) +#define bM4_PORT_PFSRA3_FSEL3 (*((volatile unsigned int*)(0x42A781CCUL))) +#define bM4_PORT_PFSRA3_FSEL4 (*((volatile unsigned int*)(0x42A781D0UL))) +#define bM4_PORT_PFSRA3_FSEL5 (*((volatile unsigned int*)(0x42A781D4UL))) +#define bM4_PORT_PFSRA3_BFE (*((volatile unsigned int*)(0x42A781E0UL))) +#define bM4_PORT_PCRA4_POUT (*((volatile unsigned int*)(0x42A78200UL))) +#define bM4_PORT_PCRA4_POUTE (*((volatile unsigned int*)(0x42A78204UL))) +#define bM4_PORT_PCRA4_NOD (*((volatile unsigned int*)(0x42A78208UL))) +#define bM4_PORT_PCRA4_DRV0 (*((volatile unsigned int*)(0x42A78210UL))) +#define bM4_PORT_PCRA4_DRV1 (*((volatile unsigned int*)(0x42A78214UL))) +#define bM4_PORT_PCRA4_PUU (*((volatile unsigned int*)(0x42A78218UL))) +#define bM4_PORT_PCRA4_PIN (*((volatile unsigned int*)(0x42A78220UL))) +#define bM4_PORT_PCRA4_INVE (*((volatile unsigned int*)(0x42A78224UL))) +#define bM4_PORT_PCRA4_INTE (*((volatile unsigned int*)(0x42A78230UL))) +#define bM4_PORT_PCRA4_LTE (*((volatile unsigned int*)(0x42A78238UL))) +#define bM4_PORT_PCRA4_DDIS (*((volatile unsigned int*)(0x42A7823CUL))) +#define bM4_PORT_PFSRA4_FSEL0 (*((volatile unsigned int*)(0x42A78240UL))) +#define bM4_PORT_PFSRA4_FSEL1 (*((volatile unsigned int*)(0x42A78244UL))) +#define bM4_PORT_PFSRA4_FSEL2 (*((volatile unsigned int*)(0x42A78248UL))) +#define bM4_PORT_PFSRA4_FSEL3 (*((volatile unsigned int*)(0x42A7824CUL))) +#define bM4_PORT_PFSRA4_FSEL4 (*((volatile unsigned int*)(0x42A78250UL))) +#define bM4_PORT_PFSRA4_FSEL5 (*((volatile unsigned int*)(0x42A78254UL))) +#define bM4_PORT_PFSRA4_BFE (*((volatile unsigned int*)(0x42A78260UL))) +#define bM4_PORT_PCRA5_POUT (*((volatile unsigned int*)(0x42A78280UL))) +#define bM4_PORT_PCRA5_POUTE (*((volatile unsigned int*)(0x42A78284UL))) +#define bM4_PORT_PCRA5_NOD (*((volatile unsigned int*)(0x42A78288UL))) +#define bM4_PORT_PCRA5_DRV0 (*((volatile unsigned int*)(0x42A78290UL))) +#define bM4_PORT_PCRA5_DRV1 (*((volatile unsigned int*)(0x42A78294UL))) +#define bM4_PORT_PCRA5_PUU (*((volatile unsigned int*)(0x42A78298UL))) +#define bM4_PORT_PCRA5_PIN (*((volatile unsigned int*)(0x42A782A0UL))) +#define bM4_PORT_PCRA5_INVE (*((volatile unsigned int*)(0x42A782A4UL))) +#define bM4_PORT_PCRA5_INTE (*((volatile unsigned int*)(0x42A782B0UL))) +#define bM4_PORT_PCRA5_LTE (*((volatile unsigned int*)(0x42A782B8UL))) +#define bM4_PORT_PCRA5_DDIS (*((volatile unsigned int*)(0x42A782BCUL))) +#define bM4_PORT_PFSRA5_FSEL0 (*((volatile unsigned int*)(0x42A782C0UL))) +#define bM4_PORT_PFSRA5_FSEL1 (*((volatile unsigned int*)(0x42A782C4UL))) +#define bM4_PORT_PFSRA5_FSEL2 (*((volatile unsigned int*)(0x42A782C8UL))) +#define bM4_PORT_PFSRA5_FSEL3 (*((volatile unsigned int*)(0x42A782CCUL))) +#define bM4_PORT_PFSRA5_FSEL4 (*((volatile unsigned int*)(0x42A782D0UL))) +#define bM4_PORT_PFSRA5_FSEL5 (*((volatile unsigned int*)(0x42A782D4UL))) +#define bM4_PORT_PFSRA5_BFE (*((volatile unsigned int*)(0x42A782E0UL))) +#define bM4_PORT_PCRA6_POUT (*((volatile unsigned int*)(0x42A78300UL))) +#define bM4_PORT_PCRA6_POUTE (*((volatile unsigned int*)(0x42A78304UL))) +#define bM4_PORT_PCRA6_NOD (*((volatile unsigned int*)(0x42A78308UL))) +#define bM4_PORT_PCRA6_DRV0 (*((volatile unsigned int*)(0x42A78310UL))) +#define bM4_PORT_PCRA6_DRV1 (*((volatile unsigned int*)(0x42A78314UL))) +#define bM4_PORT_PCRA6_PUU (*((volatile unsigned int*)(0x42A78318UL))) +#define bM4_PORT_PCRA6_PIN (*((volatile unsigned int*)(0x42A78320UL))) +#define bM4_PORT_PCRA6_INVE (*((volatile unsigned int*)(0x42A78324UL))) +#define bM4_PORT_PCRA6_INTE (*((volatile unsigned int*)(0x42A78330UL))) +#define bM4_PORT_PCRA6_LTE (*((volatile unsigned int*)(0x42A78338UL))) +#define bM4_PORT_PCRA6_DDIS (*((volatile unsigned int*)(0x42A7833CUL))) +#define bM4_PORT_PFSRA6_FSEL0 (*((volatile unsigned int*)(0x42A78340UL))) +#define bM4_PORT_PFSRA6_FSEL1 (*((volatile unsigned int*)(0x42A78344UL))) +#define bM4_PORT_PFSRA6_FSEL2 (*((volatile unsigned int*)(0x42A78348UL))) +#define bM4_PORT_PFSRA6_FSEL3 (*((volatile unsigned int*)(0x42A7834CUL))) +#define bM4_PORT_PFSRA6_FSEL4 (*((volatile unsigned int*)(0x42A78350UL))) +#define bM4_PORT_PFSRA6_FSEL5 (*((volatile unsigned int*)(0x42A78354UL))) +#define bM4_PORT_PFSRA6_BFE (*((volatile unsigned int*)(0x42A78360UL))) +#define bM4_PORT_PCRA7_POUT (*((volatile unsigned int*)(0x42A78380UL))) +#define bM4_PORT_PCRA7_POUTE (*((volatile unsigned int*)(0x42A78384UL))) +#define bM4_PORT_PCRA7_NOD (*((volatile unsigned int*)(0x42A78388UL))) +#define bM4_PORT_PCRA7_DRV0 (*((volatile unsigned int*)(0x42A78390UL))) +#define bM4_PORT_PCRA7_DRV1 (*((volatile unsigned int*)(0x42A78394UL))) +#define bM4_PORT_PCRA7_PUU (*((volatile unsigned int*)(0x42A78398UL))) +#define bM4_PORT_PCRA7_PIN (*((volatile unsigned int*)(0x42A783A0UL))) +#define bM4_PORT_PCRA7_INVE (*((volatile unsigned int*)(0x42A783A4UL))) +#define bM4_PORT_PCRA7_INTE (*((volatile unsigned int*)(0x42A783B0UL))) +#define bM4_PORT_PCRA7_LTE (*((volatile unsigned int*)(0x42A783B8UL))) +#define bM4_PORT_PCRA7_DDIS (*((volatile unsigned int*)(0x42A783BCUL))) +#define bM4_PORT_PFSRA7_FSEL0 (*((volatile unsigned int*)(0x42A783C0UL))) +#define bM4_PORT_PFSRA7_FSEL1 (*((volatile unsigned int*)(0x42A783C4UL))) +#define bM4_PORT_PFSRA7_FSEL2 (*((volatile unsigned int*)(0x42A783C8UL))) +#define bM4_PORT_PFSRA7_FSEL3 (*((volatile unsigned int*)(0x42A783CCUL))) +#define bM4_PORT_PFSRA7_FSEL4 (*((volatile unsigned int*)(0x42A783D0UL))) +#define bM4_PORT_PFSRA7_FSEL5 (*((volatile unsigned int*)(0x42A783D4UL))) +#define bM4_PORT_PFSRA7_BFE (*((volatile unsigned int*)(0x42A783E0UL))) +#define bM4_PORT_PCRA8_POUT (*((volatile unsigned int*)(0x42A78400UL))) +#define bM4_PORT_PCRA8_POUTE (*((volatile unsigned int*)(0x42A78404UL))) +#define bM4_PORT_PCRA8_NOD (*((volatile unsigned int*)(0x42A78408UL))) +#define bM4_PORT_PCRA8_DRV0 (*((volatile unsigned int*)(0x42A78410UL))) +#define bM4_PORT_PCRA8_DRV1 (*((volatile unsigned int*)(0x42A78414UL))) +#define bM4_PORT_PCRA8_PUU (*((volatile unsigned int*)(0x42A78418UL))) +#define bM4_PORT_PCRA8_PIN (*((volatile unsigned int*)(0x42A78420UL))) +#define bM4_PORT_PCRA8_INVE (*((volatile unsigned int*)(0x42A78424UL))) +#define bM4_PORT_PCRA8_INTE (*((volatile unsigned int*)(0x42A78430UL))) +#define bM4_PORT_PCRA8_LTE (*((volatile unsigned int*)(0x42A78438UL))) +#define bM4_PORT_PCRA8_DDIS (*((volatile unsigned int*)(0x42A7843CUL))) +#define bM4_PORT_PFSRA8_FSEL0 (*((volatile unsigned int*)(0x42A78440UL))) +#define bM4_PORT_PFSRA8_FSEL1 (*((volatile unsigned int*)(0x42A78444UL))) +#define bM4_PORT_PFSRA8_FSEL2 (*((volatile unsigned int*)(0x42A78448UL))) +#define bM4_PORT_PFSRA8_FSEL3 (*((volatile unsigned int*)(0x42A7844CUL))) +#define bM4_PORT_PFSRA8_FSEL4 (*((volatile unsigned int*)(0x42A78450UL))) +#define bM4_PORT_PFSRA8_FSEL5 (*((volatile unsigned int*)(0x42A78454UL))) +#define bM4_PORT_PFSRA8_BFE (*((volatile unsigned int*)(0x42A78460UL))) +#define bM4_PORT_PCRA9_POUT (*((volatile unsigned int*)(0x42A78480UL))) +#define bM4_PORT_PCRA9_POUTE (*((volatile unsigned int*)(0x42A78484UL))) +#define bM4_PORT_PCRA9_NOD (*((volatile unsigned int*)(0x42A78488UL))) +#define bM4_PORT_PCRA9_DRV0 (*((volatile unsigned int*)(0x42A78490UL))) +#define bM4_PORT_PCRA9_DRV1 (*((volatile unsigned int*)(0x42A78494UL))) +#define bM4_PORT_PCRA9_PUU (*((volatile unsigned int*)(0x42A78498UL))) +#define bM4_PORT_PCRA9_PIN (*((volatile unsigned int*)(0x42A784A0UL))) +#define bM4_PORT_PCRA9_INVE (*((volatile unsigned int*)(0x42A784A4UL))) +#define bM4_PORT_PCRA9_INTE (*((volatile unsigned int*)(0x42A784B0UL))) +#define bM4_PORT_PCRA9_LTE (*((volatile unsigned int*)(0x42A784B8UL))) +#define bM4_PORT_PCRA9_DDIS (*((volatile unsigned int*)(0x42A784BCUL))) +#define bM4_PORT_PFSRA9_FSEL0 (*((volatile unsigned int*)(0x42A784C0UL))) +#define bM4_PORT_PFSRA9_FSEL1 (*((volatile unsigned int*)(0x42A784C4UL))) +#define bM4_PORT_PFSRA9_FSEL2 (*((volatile unsigned int*)(0x42A784C8UL))) +#define bM4_PORT_PFSRA9_FSEL3 (*((volatile unsigned int*)(0x42A784CCUL))) +#define bM4_PORT_PFSRA9_FSEL4 (*((volatile unsigned int*)(0x42A784D0UL))) +#define bM4_PORT_PFSRA9_FSEL5 (*((volatile unsigned int*)(0x42A784D4UL))) +#define bM4_PORT_PFSRA9_BFE (*((volatile unsigned int*)(0x42A784E0UL))) +#define bM4_PORT_PCRA10_POUT (*((volatile unsigned int*)(0x42A78500UL))) +#define bM4_PORT_PCRA10_POUTE (*((volatile unsigned int*)(0x42A78504UL))) +#define bM4_PORT_PCRA10_NOD (*((volatile unsigned int*)(0x42A78508UL))) +#define bM4_PORT_PCRA10_DRV0 (*((volatile unsigned int*)(0x42A78510UL))) +#define bM4_PORT_PCRA10_DRV1 (*((volatile unsigned int*)(0x42A78514UL))) +#define bM4_PORT_PCRA10_PUU (*((volatile unsigned int*)(0x42A78518UL))) +#define bM4_PORT_PCRA10_PIN (*((volatile unsigned int*)(0x42A78520UL))) +#define bM4_PORT_PCRA10_INVE (*((volatile unsigned int*)(0x42A78524UL))) +#define bM4_PORT_PCRA10_INTE (*((volatile unsigned int*)(0x42A78530UL))) +#define bM4_PORT_PCRA10_LTE (*((volatile unsigned int*)(0x42A78538UL))) +#define bM4_PORT_PCRA10_DDIS (*((volatile unsigned int*)(0x42A7853CUL))) +#define bM4_PORT_PFSRA10_FSEL0 (*((volatile unsigned int*)(0x42A78540UL))) +#define bM4_PORT_PFSRA10_FSEL1 (*((volatile unsigned int*)(0x42A78544UL))) +#define bM4_PORT_PFSRA10_FSEL2 (*((volatile unsigned int*)(0x42A78548UL))) +#define bM4_PORT_PFSRA10_FSEL3 (*((volatile unsigned int*)(0x42A7854CUL))) +#define bM4_PORT_PFSRA10_FSEL4 (*((volatile unsigned int*)(0x42A78550UL))) +#define bM4_PORT_PFSRA10_FSEL5 (*((volatile unsigned int*)(0x42A78554UL))) +#define bM4_PORT_PFSRA10_BFE (*((volatile unsigned int*)(0x42A78560UL))) +#define bM4_PORT_PCRA11_POUT (*((volatile unsigned int*)(0x42A78580UL))) +#define bM4_PORT_PCRA11_POUTE (*((volatile unsigned int*)(0x42A78584UL))) +#define bM4_PORT_PCRA11_NOD (*((volatile unsigned int*)(0x42A78588UL))) +#define bM4_PORT_PCRA11_DRV0 (*((volatile unsigned int*)(0x42A78590UL))) +#define bM4_PORT_PCRA11_DRV1 (*((volatile unsigned int*)(0x42A78594UL))) +#define bM4_PORT_PCRA11_PUU (*((volatile unsigned int*)(0x42A78598UL))) +#define bM4_PORT_PCRA11_PIN (*((volatile unsigned int*)(0x42A785A0UL))) +#define bM4_PORT_PCRA11_INVE (*((volatile unsigned int*)(0x42A785A4UL))) +#define bM4_PORT_PCRA11_INTE (*((volatile unsigned int*)(0x42A785B0UL))) +#define bM4_PORT_PCRA11_LTE (*((volatile unsigned int*)(0x42A785B8UL))) +#define bM4_PORT_PCRA11_DDIS (*((volatile unsigned int*)(0x42A785BCUL))) +#define bM4_PORT_PFSRA11_FSEL0 (*((volatile unsigned int*)(0x42A785C0UL))) +#define bM4_PORT_PFSRA11_FSEL1 (*((volatile unsigned int*)(0x42A785C4UL))) +#define bM4_PORT_PFSRA11_FSEL2 (*((volatile unsigned int*)(0x42A785C8UL))) +#define bM4_PORT_PFSRA11_FSEL3 (*((volatile unsigned int*)(0x42A785CCUL))) +#define bM4_PORT_PFSRA11_FSEL4 (*((volatile unsigned int*)(0x42A785D0UL))) +#define bM4_PORT_PFSRA11_FSEL5 (*((volatile unsigned int*)(0x42A785D4UL))) +#define bM4_PORT_PFSRA11_BFE (*((volatile unsigned int*)(0x42A785E0UL))) +#define bM4_PORT_PCRA12_POUT (*((volatile unsigned int*)(0x42A78600UL))) +#define bM4_PORT_PCRA12_POUTE (*((volatile unsigned int*)(0x42A78604UL))) +#define bM4_PORT_PCRA12_NOD (*((volatile unsigned int*)(0x42A78608UL))) +#define bM4_PORT_PCRA12_DRV0 (*((volatile unsigned int*)(0x42A78610UL))) +#define bM4_PORT_PCRA12_DRV1 (*((volatile unsigned int*)(0x42A78614UL))) +#define bM4_PORT_PCRA12_PUU (*((volatile unsigned int*)(0x42A78618UL))) +#define bM4_PORT_PCRA12_PIN (*((volatile unsigned int*)(0x42A78620UL))) +#define bM4_PORT_PCRA12_INVE (*((volatile unsigned int*)(0x42A78624UL))) +#define bM4_PORT_PCRA12_INTE (*((volatile unsigned int*)(0x42A78630UL))) +#define bM4_PORT_PCRA12_LTE (*((volatile unsigned int*)(0x42A78638UL))) +#define bM4_PORT_PCRA12_DDIS (*((volatile unsigned int*)(0x42A7863CUL))) +#define bM4_PORT_PFSRA12_FSEL0 (*((volatile unsigned int*)(0x42A78640UL))) +#define bM4_PORT_PFSRA12_FSEL1 (*((volatile unsigned int*)(0x42A78644UL))) +#define bM4_PORT_PFSRA12_FSEL2 (*((volatile unsigned int*)(0x42A78648UL))) +#define bM4_PORT_PFSRA12_FSEL3 (*((volatile unsigned int*)(0x42A7864CUL))) +#define bM4_PORT_PFSRA12_FSEL4 (*((volatile unsigned int*)(0x42A78650UL))) +#define bM4_PORT_PFSRA12_FSEL5 (*((volatile unsigned int*)(0x42A78654UL))) +#define bM4_PORT_PFSRA12_BFE (*((volatile unsigned int*)(0x42A78660UL))) +#define bM4_PORT_PCRA13_POUT (*((volatile unsigned int*)(0x42A78680UL))) +#define bM4_PORT_PCRA13_POUTE (*((volatile unsigned int*)(0x42A78684UL))) +#define bM4_PORT_PCRA13_NOD (*((volatile unsigned int*)(0x42A78688UL))) +#define bM4_PORT_PCRA13_DRV0 (*((volatile unsigned int*)(0x42A78690UL))) +#define bM4_PORT_PCRA13_DRV1 (*((volatile unsigned int*)(0x42A78694UL))) +#define bM4_PORT_PCRA13_PUU (*((volatile unsigned int*)(0x42A78698UL))) +#define bM4_PORT_PCRA13_PIN (*((volatile unsigned int*)(0x42A786A0UL))) +#define bM4_PORT_PCRA13_INVE (*((volatile unsigned int*)(0x42A786A4UL))) +#define bM4_PORT_PCRA13_INTE (*((volatile unsigned int*)(0x42A786B0UL))) +#define bM4_PORT_PCRA13_LTE (*((volatile unsigned int*)(0x42A786B8UL))) +#define bM4_PORT_PCRA13_DDIS (*((volatile unsigned int*)(0x42A786BCUL))) +#define bM4_PORT_PFSRA13_FSEL0 (*((volatile unsigned int*)(0x42A786C0UL))) +#define bM4_PORT_PFSRA13_FSEL1 (*((volatile unsigned int*)(0x42A786C4UL))) +#define bM4_PORT_PFSRA13_FSEL2 (*((volatile unsigned int*)(0x42A786C8UL))) +#define bM4_PORT_PFSRA13_FSEL3 (*((volatile unsigned int*)(0x42A786CCUL))) +#define bM4_PORT_PFSRA13_FSEL4 (*((volatile unsigned int*)(0x42A786D0UL))) +#define bM4_PORT_PFSRA13_FSEL5 (*((volatile unsigned int*)(0x42A786D4UL))) +#define bM4_PORT_PFSRA13_BFE (*((volatile unsigned int*)(0x42A786E0UL))) +#define bM4_PORT_PCRA14_POUT (*((volatile unsigned int*)(0x42A78700UL))) +#define bM4_PORT_PCRA14_POUTE (*((volatile unsigned int*)(0x42A78704UL))) +#define bM4_PORT_PCRA14_NOD (*((volatile unsigned int*)(0x42A78708UL))) +#define bM4_PORT_PCRA14_DRV0 (*((volatile unsigned int*)(0x42A78710UL))) +#define bM4_PORT_PCRA14_DRV1 (*((volatile unsigned int*)(0x42A78714UL))) +#define bM4_PORT_PCRA14_PUU (*((volatile unsigned int*)(0x42A78718UL))) +#define bM4_PORT_PCRA14_PIN (*((volatile unsigned int*)(0x42A78720UL))) +#define bM4_PORT_PCRA14_INVE (*((volatile unsigned int*)(0x42A78724UL))) +#define bM4_PORT_PCRA14_INTE (*((volatile unsigned int*)(0x42A78730UL))) +#define bM4_PORT_PCRA14_LTE (*((volatile unsigned int*)(0x42A78738UL))) +#define bM4_PORT_PCRA14_DDIS (*((volatile unsigned int*)(0x42A7873CUL))) +#define bM4_PORT_PFSRA14_FSEL0 (*((volatile unsigned int*)(0x42A78740UL))) +#define bM4_PORT_PFSRA14_FSEL1 (*((volatile unsigned int*)(0x42A78744UL))) +#define bM4_PORT_PFSRA14_FSEL2 (*((volatile unsigned int*)(0x42A78748UL))) +#define bM4_PORT_PFSRA14_FSEL3 (*((volatile unsigned int*)(0x42A7874CUL))) +#define bM4_PORT_PFSRA14_FSEL4 (*((volatile unsigned int*)(0x42A78750UL))) +#define bM4_PORT_PFSRA14_FSEL5 (*((volatile unsigned int*)(0x42A78754UL))) +#define bM4_PORT_PFSRA14_BFE (*((volatile unsigned int*)(0x42A78760UL))) +#define bM4_PORT_PCRA15_POUT (*((volatile unsigned int*)(0x42A78780UL))) +#define bM4_PORT_PCRA15_POUTE (*((volatile unsigned int*)(0x42A78784UL))) +#define bM4_PORT_PCRA15_NOD (*((volatile unsigned int*)(0x42A78788UL))) +#define bM4_PORT_PCRA15_DRV0 (*((volatile unsigned int*)(0x42A78790UL))) +#define bM4_PORT_PCRA15_DRV1 (*((volatile unsigned int*)(0x42A78794UL))) +#define bM4_PORT_PCRA15_PUU (*((volatile unsigned int*)(0x42A78798UL))) +#define bM4_PORT_PCRA15_PIN (*((volatile unsigned int*)(0x42A787A0UL))) +#define bM4_PORT_PCRA15_INVE (*((volatile unsigned int*)(0x42A787A4UL))) +#define bM4_PORT_PCRA15_INTE (*((volatile unsigned int*)(0x42A787B0UL))) +#define bM4_PORT_PCRA15_LTE (*((volatile unsigned int*)(0x42A787B8UL))) +#define bM4_PORT_PCRA15_DDIS (*((volatile unsigned int*)(0x42A787BCUL))) +#define bM4_PORT_PFSRA15_FSEL0 (*((volatile unsigned int*)(0x42A787C0UL))) +#define bM4_PORT_PFSRA15_FSEL1 (*((volatile unsigned int*)(0x42A787C4UL))) +#define bM4_PORT_PFSRA15_FSEL2 (*((volatile unsigned int*)(0x42A787C8UL))) +#define bM4_PORT_PFSRA15_FSEL3 (*((volatile unsigned int*)(0x42A787CCUL))) +#define bM4_PORT_PFSRA15_FSEL4 (*((volatile unsigned int*)(0x42A787D0UL))) +#define bM4_PORT_PFSRA15_FSEL5 (*((volatile unsigned int*)(0x42A787D4UL))) +#define bM4_PORT_PFSRA15_BFE (*((volatile unsigned int*)(0x42A787E0UL))) +#define bM4_PORT_PCRB0_POUT (*((volatile unsigned int*)(0x42A78800UL))) +#define bM4_PORT_PCRB0_POUTE (*((volatile unsigned int*)(0x42A78804UL))) +#define bM4_PORT_PCRB0_NOD (*((volatile unsigned int*)(0x42A78808UL))) +#define bM4_PORT_PCRB0_DRV0 (*((volatile unsigned int*)(0x42A78810UL))) +#define bM4_PORT_PCRB0_DRV1 (*((volatile unsigned int*)(0x42A78814UL))) +#define bM4_PORT_PCRB0_PUU (*((volatile unsigned int*)(0x42A78818UL))) +#define bM4_PORT_PCRB0_PIN (*((volatile unsigned int*)(0x42A78820UL))) +#define bM4_PORT_PCRB0_INVE (*((volatile unsigned int*)(0x42A78824UL))) +#define bM4_PORT_PCRB0_INTE (*((volatile unsigned int*)(0x42A78830UL))) +#define bM4_PORT_PCRB0_LTE (*((volatile unsigned int*)(0x42A78838UL))) +#define bM4_PORT_PCRB0_DDIS (*((volatile unsigned int*)(0x42A7883CUL))) +#define bM4_PORT_PFSRB0_FSEL0 (*((volatile unsigned int*)(0x42A78840UL))) +#define bM4_PORT_PFSRB0_FSEL1 (*((volatile unsigned int*)(0x42A78844UL))) +#define bM4_PORT_PFSRB0_FSEL2 (*((volatile unsigned int*)(0x42A78848UL))) +#define bM4_PORT_PFSRB0_FSEL3 (*((volatile unsigned int*)(0x42A7884CUL))) +#define bM4_PORT_PFSRB0_FSEL4 (*((volatile unsigned int*)(0x42A78850UL))) +#define bM4_PORT_PFSRB0_FSEL5 (*((volatile unsigned int*)(0x42A78854UL))) +#define bM4_PORT_PFSRB0_BFE (*((volatile unsigned int*)(0x42A78860UL))) +#define bM4_PORT_PCRB1_POUT (*((volatile unsigned int*)(0x42A78880UL))) +#define bM4_PORT_PCRB1_POUTE (*((volatile unsigned int*)(0x42A78884UL))) +#define bM4_PORT_PCRB1_NOD (*((volatile unsigned int*)(0x42A78888UL))) +#define bM4_PORT_PCRB1_DRV0 (*((volatile unsigned int*)(0x42A78890UL))) +#define bM4_PORT_PCRB1_DRV1 (*((volatile unsigned int*)(0x42A78894UL))) +#define bM4_PORT_PCRB1_PUU (*((volatile unsigned int*)(0x42A78898UL))) +#define bM4_PORT_PCRB1_PIN (*((volatile unsigned int*)(0x42A788A0UL))) +#define bM4_PORT_PCRB1_INVE (*((volatile unsigned int*)(0x42A788A4UL))) +#define bM4_PORT_PCRB1_INTE (*((volatile unsigned int*)(0x42A788B0UL))) +#define bM4_PORT_PCRB1_LTE (*((volatile unsigned int*)(0x42A788B8UL))) +#define bM4_PORT_PCRB1_DDIS (*((volatile unsigned int*)(0x42A788BCUL))) +#define bM4_PORT_PFSRB1_FSEL0 (*((volatile unsigned int*)(0x42A788C0UL))) +#define bM4_PORT_PFSRB1_FSEL1 (*((volatile unsigned int*)(0x42A788C4UL))) +#define bM4_PORT_PFSRB1_FSEL2 (*((volatile unsigned int*)(0x42A788C8UL))) +#define bM4_PORT_PFSRB1_FSEL3 (*((volatile unsigned int*)(0x42A788CCUL))) +#define bM4_PORT_PFSRB1_FSEL4 (*((volatile unsigned int*)(0x42A788D0UL))) +#define bM4_PORT_PFSRB1_FSEL5 (*((volatile unsigned int*)(0x42A788D4UL))) +#define bM4_PORT_PFSRB1_BFE (*((volatile unsigned int*)(0x42A788E0UL))) +#define bM4_PORT_PCRB2_POUT (*((volatile unsigned int*)(0x42A78900UL))) +#define bM4_PORT_PCRB2_POUTE (*((volatile unsigned int*)(0x42A78904UL))) +#define bM4_PORT_PCRB2_NOD (*((volatile unsigned int*)(0x42A78908UL))) +#define bM4_PORT_PCRB2_DRV0 (*((volatile unsigned int*)(0x42A78910UL))) +#define bM4_PORT_PCRB2_DRV1 (*((volatile unsigned int*)(0x42A78914UL))) +#define bM4_PORT_PCRB2_PUU (*((volatile unsigned int*)(0x42A78918UL))) +#define bM4_PORT_PCRB2_PIN (*((volatile unsigned int*)(0x42A78920UL))) +#define bM4_PORT_PCRB2_INVE (*((volatile unsigned int*)(0x42A78924UL))) +#define bM4_PORT_PCRB2_INTE (*((volatile unsigned int*)(0x42A78930UL))) +#define bM4_PORT_PCRB2_LTE (*((volatile unsigned int*)(0x42A78938UL))) +#define bM4_PORT_PCRB2_DDIS (*((volatile unsigned int*)(0x42A7893CUL))) +#define bM4_PORT_PFSRB2_FSEL0 (*((volatile unsigned int*)(0x42A78940UL))) +#define bM4_PORT_PFSRB2_FSEL1 (*((volatile unsigned int*)(0x42A78944UL))) +#define bM4_PORT_PFSRB2_FSEL2 (*((volatile unsigned int*)(0x42A78948UL))) +#define bM4_PORT_PFSRB2_FSEL3 (*((volatile unsigned int*)(0x42A7894CUL))) +#define bM4_PORT_PFSRB2_FSEL4 (*((volatile unsigned int*)(0x42A78950UL))) +#define bM4_PORT_PFSRB2_FSEL5 (*((volatile unsigned int*)(0x42A78954UL))) +#define bM4_PORT_PFSRB2_BFE (*((volatile unsigned int*)(0x42A78960UL))) +#define bM4_PORT_PCRB3_POUT (*((volatile unsigned int*)(0x42A78980UL))) +#define bM4_PORT_PCRB3_POUTE (*((volatile unsigned int*)(0x42A78984UL))) +#define bM4_PORT_PCRB3_NOD (*((volatile unsigned int*)(0x42A78988UL))) +#define bM4_PORT_PCRB3_DRV0 (*((volatile unsigned int*)(0x42A78990UL))) +#define bM4_PORT_PCRB3_DRV1 (*((volatile unsigned int*)(0x42A78994UL))) +#define bM4_PORT_PCRB3_PUU (*((volatile unsigned int*)(0x42A78998UL))) +#define bM4_PORT_PCRB3_PIN (*((volatile unsigned int*)(0x42A789A0UL))) +#define bM4_PORT_PCRB3_INVE (*((volatile unsigned int*)(0x42A789A4UL))) +#define bM4_PORT_PCRB3_INTE (*((volatile unsigned int*)(0x42A789B0UL))) +#define bM4_PORT_PCRB3_LTE (*((volatile unsigned int*)(0x42A789B8UL))) +#define bM4_PORT_PCRB3_DDIS (*((volatile unsigned int*)(0x42A789BCUL))) +#define bM4_PORT_PFSRB3_FSEL0 (*((volatile unsigned int*)(0x42A789C0UL))) +#define bM4_PORT_PFSRB3_FSEL1 (*((volatile unsigned int*)(0x42A789C4UL))) +#define bM4_PORT_PFSRB3_FSEL2 (*((volatile unsigned int*)(0x42A789C8UL))) +#define bM4_PORT_PFSRB3_FSEL3 (*((volatile unsigned int*)(0x42A789CCUL))) +#define bM4_PORT_PFSRB3_FSEL4 (*((volatile unsigned int*)(0x42A789D0UL))) +#define bM4_PORT_PFSRB3_FSEL5 (*((volatile unsigned int*)(0x42A789D4UL))) +#define bM4_PORT_PFSRB3_BFE (*((volatile unsigned int*)(0x42A789E0UL))) +#define bM4_PORT_PCRB4_POUT (*((volatile unsigned int*)(0x42A78A00UL))) +#define bM4_PORT_PCRB4_POUTE (*((volatile unsigned int*)(0x42A78A04UL))) +#define bM4_PORT_PCRB4_NOD (*((volatile unsigned int*)(0x42A78A08UL))) +#define bM4_PORT_PCRB4_DRV0 (*((volatile unsigned int*)(0x42A78A10UL))) +#define bM4_PORT_PCRB4_DRV1 (*((volatile unsigned int*)(0x42A78A14UL))) +#define bM4_PORT_PCRB4_PUU (*((volatile unsigned int*)(0x42A78A18UL))) +#define bM4_PORT_PCRB4_PIN (*((volatile unsigned int*)(0x42A78A20UL))) +#define bM4_PORT_PCRB4_INVE (*((volatile unsigned int*)(0x42A78A24UL))) +#define bM4_PORT_PCRB4_INTE (*((volatile unsigned int*)(0x42A78A30UL))) +#define bM4_PORT_PCRB4_LTE (*((volatile unsigned int*)(0x42A78A38UL))) +#define bM4_PORT_PCRB4_DDIS (*((volatile unsigned int*)(0x42A78A3CUL))) +#define bM4_PORT_PFSRB4_FSEL0 (*((volatile unsigned int*)(0x42A78A40UL))) +#define bM4_PORT_PFSRB4_FSEL1 (*((volatile unsigned int*)(0x42A78A44UL))) +#define bM4_PORT_PFSRB4_FSEL2 (*((volatile unsigned int*)(0x42A78A48UL))) +#define bM4_PORT_PFSRB4_FSEL3 (*((volatile unsigned int*)(0x42A78A4CUL))) +#define bM4_PORT_PFSRB4_FSEL4 (*((volatile unsigned int*)(0x42A78A50UL))) +#define bM4_PORT_PFSRB4_FSEL5 (*((volatile unsigned int*)(0x42A78A54UL))) +#define bM4_PORT_PFSRB4_BFE (*((volatile unsigned int*)(0x42A78A60UL))) +#define bM4_PORT_PCRB5_POUT (*((volatile unsigned int*)(0x42A78A80UL))) +#define bM4_PORT_PCRB5_POUTE (*((volatile unsigned int*)(0x42A78A84UL))) +#define bM4_PORT_PCRB5_NOD (*((volatile unsigned int*)(0x42A78A88UL))) +#define bM4_PORT_PCRB5_DRV0 (*((volatile unsigned int*)(0x42A78A90UL))) +#define bM4_PORT_PCRB5_DRV1 (*((volatile unsigned int*)(0x42A78A94UL))) +#define bM4_PORT_PCRB5_PUU (*((volatile unsigned int*)(0x42A78A98UL))) +#define bM4_PORT_PCRB5_PIN (*((volatile unsigned int*)(0x42A78AA0UL))) +#define bM4_PORT_PCRB5_INVE (*((volatile unsigned int*)(0x42A78AA4UL))) +#define bM4_PORT_PCRB5_INTE (*((volatile unsigned int*)(0x42A78AB0UL))) +#define bM4_PORT_PCRB5_LTE (*((volatile unsigned int*)(0x42A78AB8UL))) +#define bM4_PORT_PCRB5_DDIS (*((volatile unsigned int*)(0x42A78ABCUL))) +#define bM4_PORT_PFSRB5_FSEL0 (*((volatile unsigned int*)(0x42A78AC0UL))) +#define bM4_PORT_PFSRB5_FSEL1 (*((volatile unsigned int*)(0x42A78AC4UL))) +#define bM4_PORT_PFSRB5_FSEL2 (*((volatile unsigned int*)(0x42A78AC8UL))) +#define bM4_PORT_PFSRB5_FSEL3 (*((volatile unsigned int*)(0x42A78ACCUL))) +#define bM4_PORT_PFSRB5_FSEL4 (*((volatile unsigned int*)(0x42A78AD0UL))) +#define bM4_PORT_PFSRB5_FSEL5 (*((volatile unsigned int*)(0x42A78AD4UL))) +#define bM4_PORT_PFSRB5_BFE (*((volatile unsigned int*)(0x42A78AE0UL))) +#define bM4_PORT_PCRB6_POUT (*((volatile unsigned int*)(0x42A78B00UL))) +#define bM4_PORT_PCRB6_POUTE (*((volatile unsigned int*)(0x42A78B04UL))) +#define bM4_PORT_PCRB6_NOD (*((volatile unsigned int*)(0x42A78B08UL))) +#define bM4_PORT_PCRB6_DRV0 (*((volatile unsigned int*)(0x42A78B10UL))) +#define bM4_PORT_PCRB6_DRV1 (*((volatile unsigned int*)(0x42A78B14UL))) +#define bM4_PORT_PCRB6_PUU (*((volatile unsigned int*)(0x42A78B18UL))) +#define bM4_PORT_PCRB6_PIN (*((volatile unsigned int*)(0x42A78B20UL))) +#define bM4_PORT_PCRB6_INVE (*((volatile unsigned int*)(0x42A78B24UL))) +#define bM4_PORT_PCRB6_INTE (*((volatile unsigned int*)(0x42A78B30UL))) +#define bM4_PORT_PCRB6_LTE (*((volatile unsigned int*)(0x42A78B38UL))) +#define bM4_PORT_PCRB6_DDIS (*((volatile unsigned int*)(0x42A78B3CUL))) +#define bM4_PORT_PFSRB6_FSEL0 (*((volatile unsigned int*)(0x42A78B40UL))) +#define bM4_PORT_PFSRB6_FSEL1 (*((volatile unsigned int*)(0x42A78B44UL))) +#define bM4_PORT_PFSRB6_FSEL2 (*((volatile unsigned int*)(0x42A78B48UL))) +#define bM4_PORT_PFSRB6_FSEL3 (*((volatile unsigned int*)(0x42A78B4CUL))) +#define bM4_PORT_PFSRB6_FSEL4 (*((volatile unsigned int*)(0x42A78B50UL))) +#define bM4_PORT_PFSRB6_FSEL5 (*((volatile unsigned int*)(0x42A78B54UL))) +#define bM4_PORT_PFSRB6_BFE (*((volatile unsigned int*)(0x42A78B60UL))) +#define bM4_PORT_PCRB7_POUT (*((volatile unsigned int*)(0x42A78B80UL))) +#define bM4_PORT_PCRB7_POUTE (*((volatile unsigned int*)(0x42A78B84UL))) +#define bM4_PORT_PCRB7_NOD (*((volatile unsigned int*)(0x42A78B88UL))) +#define bM4_PORT_PCRB7_DRV0 (*((volatile unsigned int*)(0x42A78B90UL))) +#define bM4_PORT_PCRB7_DRV1 (*((volatile unsigned int*)(0x42A78B94UL))) +#define bM4_PORT_PCRB7_PUU (*((volatile unsigned int*)(0x42A78B98UL))) +#define bM4_PORT_PCRB7_PIN (*((volatile unsigned int*)(0x42A78BA0UL))) +#define bM4_PORT_PCRB7_INVE (*((volatile unsigned int*)(0x42A78BA4UL))) +#define bM4_PORT_PCRB7_INTE (*((volatile unsigned int*)(0x42A78BB0UL))) +#define bM4_PORT_PCRB7_LTE (*((volatile unsigned int*)(0x42A78BB8UL))) +#define bM4_PORT_PCRB7_DDIS (*((volatile unsigned int*)(0x42A78BBCUL))) +#define bM4_PORT_PFSRB7_FSEL0 (*((volatile unsigned int*)(0x42A78BC0UL))) +#define bM4_PORT_PFSRB7_FSEL1 (*((volatile unsigned int*)(0x42A78BC4UL))) +#define bM4_PORT_PFSRB7_FSEL2 (*((volatile unsigned int*)(0x42A78BC8UL))) +#define bM4_PORT_PFSRB7_FSEL3 (*((volatile unsigned int*)(0x42A78BCCUL))) +#define bM4_PORT_PFSRB7_FSEL4 (*((volatile unsigned int*)(0x42A78BD0UL))) +#define bM4_PORT_PFSRB7_FSEL5 (*((volatile unsigned int*)(0x42A78BD4UL))) +#define bM4_PORT_PFSRB7_BFE (*((volatile unsigned int*)(0x42A78BE0UL))) +#define bM4_PORT_PCRB8_POUT (*((volatile unsigned int*)(0x42A78C00UL))) +#define bM4_PORT_PCRB8_POUTE (*((volatile unsigned int*)(0x42A78C04UL))) +#define bM4_PORT_PCRB8_NOD (*((volatile unsigned int*)(0x42A78C08UL))) +#define bM4_PORT_PCRB8_DRV0 (*((volatile unsigned int*)(0x42A78C10UL))) +#define bM4_PORT_PCRB8_DRV1 (*((volatile unsigned int*)(0x42A78C14UL))) +#define bM4_PORT_PCRB8_PUU (*((volatile unsigned int*)(0x42A78C18UL))) +#define bM4_PORT_PCRB8_PIN (*((volatile unsigned int*)(0x42A78C20UL))) +#define bM4_PORT_PCRB8_INVE (*((volatile unsigned int*)(0x42A78C24UL))) +#define bM4_PORT_PCRB8_INTE (*((volatile unsigned int*)(0x42A78C30UL))) +#define bM4_PORT_PCRB8_LTE (*((volatile unsigned int*)(0x42A78C38UL))) +#define bM4_PORT_PCRB8_DDIS (*((volatile unsigned int*)(0x42A78C3CUL))) +#define bM4_PORT_PFSRB8_FSEL0 (*((volatile unsigned int*)(0x42A78C40UL))) +#define bM4_PORT_PFSRB8_FSEL1 (*((volatile unsigned int*)(0x42A78C44UL))) +#define bM4_PORT_PFSRB8_FSEL2 (*((volatile unsigned int*)(0x42A78C48UL))) +#define bM4_PORT_PFSRB8_FSEL3 (*((volatile unsigned int*)(0x42A78C4CUL))) +#define bM4_PORT_PFSRB8_FSEL4 (*((volatile unsigned int*)(0x42A78C50UL))) +#define bM4_PORT_PFSRB8_FSEL5 (*((volatile unsigned int*)(0x42A78C54UL))) +#define bM4_PORT_PFSRB8_BFE (*((volatile unsigned int*)(0x42A78C60UL))) +#define bM4_PORT_PCRB9_POUT (*((volatile unsigned int*)(0x42A78C80UL))) +#define bM4_PORT_PCRB9_POUTE (*((volatile unsigned int*)(0x42A78C84UL))) +#define bM4_PORT_PCRB9_NOD (*((volatile unsigned int*)(0x42A78C88UL))) +#define bM4_PORT_PCRB9_DRV0 (*((volatile unsigned int*)(0x42A78C90UL))) +#define bM4_PORT_PCRB9_DRV1 (*((volatile unsigned int*)(0x42A78C94UL))) +#define bM4_PORT_PCRB9_PUU (*((volatile unsigned int*)(0x42A78C98UL))) +#define bM4_PORT_PCRB9_PIN (*((volatile unsigned int*)(0x42A78CA0UL))) +#define bM4_PORT_PCRB9_INVE (*((volatile unsigned int*)(0x42A78CA4UL))) +#define bM4_PORT_PCRB9_INTE (*((volatile unsigned int*)(0x42A78CB0UL))) +#define bM4_PORT_PCRB9_LTE (*((volatile unsigned int*)(0x42A78CB8UL))) +#define bM4_PORT_PCRB9_DDIS (*((volatile unsigned int*)(0x42A78CBCUL))) +#define bM4_PORT_PFSRB9_FSEL0 (*((volatile unsigned int*)(0x42A78CC0UL))) +#define bM4_PORT_PFSRB9_FSEL1 (*((volatile unsigned int*)(0x42A78CC4UL))) +#define bM4_PORT_PFSRB9_FSEL2 (*((volatile unsigned int*)(0x42A78CC8UL))) +#define bM4_PORT_PFSRB9_FSEL3 (*((volatile unsigned int*)(0x42A78CCCUL))) +#define bM4_PORT_PFSRB9_FSEL4 (*((volatile unsigned int*)(0x42A78CD0UL))) +#define bM4_PORT_PFSRB9_FSEL5 (*((volatile unsigned int*)(0x42A78CD4UL))) +#define bM4_PORT_PFSRB9_BFE (*((volatile unsigned int*)(0x42A78CE0UL))) +#define bM4_PORT_PCRB10_POUT (*((volatile unsigned int*)(0x42A78D00UL))) +#define bM4_PORT_PCRB10_POUTE (*((volatile unsigned int*)(0x42A78D04UL))) +#define bM4_PORT_PCRB10_NOD (*((volatile unsigned int*)(0x42A78D08UL))) +#define bM4_PORT_PCRB10_DRV0 (*((volatile unsigned int*)(0x42A78D10UL))) +#define bM4_PORT_PCRB10_DRV1 (*((volatile unsigned int*)(0x42A78D14UL))) +#define bM4_PORT_PCRB10_PUU (*((volatile unsigned int*)(0x42A78D18UL))) +#define bM4_PORT_PCRB10_PIN (*((volatile unsigned int*)(0x42A78D20UL))) +#define bM4_PORT_PCRB10_INVE (*((volatile unsigned int*)(0x42A78D24UL))) +#define bM4_PORT_PCRB10_INTE (*((volatile unsigned int*)(0x42A78D30UL))) +#define bM4_PORT_PCRB10_LTE (*((volatile unsigned int*)(0x42A78D38UL))) +#define bM4_PORT_PCRB10_DDIS (*((volatile unsigned int*)(0x42A78D3CUL))) +#define bM4_PORT_PFSRB10_FSEL0 (*((volatile unsigned int*)(0x42A78D40UL))) +#define bM4_PORT_PFSRB10_FSEL1 (*((volatile unsigned int*)(0x42A78D44UL))) +#define bM4_PORT_PFSRB10_FSEL2 (*((volatile unsigned int*)(0x42A78D48UL))) +#define bM4_PORT_PFSRB10_FSEL3 (*((volatile unsigned int*)(0x42A78D4CUL))) +#define bM4_PORT_PFSRB10_FSEL4 (*((volatile unsigned int*)(0x42A78D50UL))) +#define bM4_PORT_PFSRB10_FSEL5 (*((volatile unsigned int*)(0x42A78D54UL))) +#define bM4_PORT_PFSRB10_BFE (*((volatile unsigned int*)(0x42A78D60UL))) +#define bM4_PORT_PCRB11_POUT (*((volatile unsigned int*)(0x42A78D80UL))) +#define bM4_PORT_PCRB11_POUTE (*((volatile unsigned int*)(0x42A78D84UL))) +#define bM4_PORT_PCRB11_NOD (*((volatile unsigned int*)(0x42A78D88UL))) +#define bM4_PORT_PCRB11_DRV0 (*((volatile unsigned int*)(0x42A78D90UL))) +#define bM4_PORT_PCRB11_DRV1 (*((volatile unsigned int*)(0x42A78D94UL))) +#define bM4_PORT_PCRB11_PUU (*((volatile unsigned int*)(0x42A78D98UL))) +#define bM4_PORT_PCRB11_PIN (*((volatile unsigned int*)(0x42A78DA0UL))) +#define bM4_PORT_PCRB11_INVE (*((volatile unsigned int*)(0x42A78DA4UL))) +#define bM4_PORT_PCRB11_INTE (*((volatile unsigned int*)(0x42A78DB0UL))) +#define bM4_PORT_PCRB11_LTE (*((volatile unsigned int*)(0x42A78DB8UL))) +#define bM4_PORT_PCRB11_DDIS (*((volatile unsigned int*)(0x42A78DBCUL))) +#define bM4_PORT_PFSRB11_FSEL0 (*((volatile unsigned int*)(0x42A78DC0UL))) +#define bM4_PORT_PFSRB11_FSEL1 (*((volatile unsigned int*)(0x42A78DC4UL))) +#define bM4_PORT_PFSRB11_FSEL2 (*((volatile unsigned int*)(0x42A78DC8UL))) +#define bM4_PORT_PFSRB11_FSEL3 (*((volatile unsigned int*)(0x42A78DCCUL))) +#define bM4_PORT_PFSRB11_FSEL4 (*((volatile unsigned int*)(0x42A78DD0UL))) +#define bM4_PORT_PFSRB11_FSEL5 (*((volatile unsigned int*)(0x42A78DD4UL))) +#define bM4_PORT_PFSRB11_BFE (*((volatile unsigned int*)(0x42A78DE0UL))) +#define bM4_PORT_PCRB12_POUT (*((volatile unsigned int*)(0x42A78E00UL))) +#define bM4_PORT_PCRB12_POUTE (*((volatile unsigned int*)(0x42A78E04UL))) +#define bM4_PORT_PCRB12_NOD (*((volatile unsigned int*)(0x42A78E08UL))) +#define bM4_PORT_PCRB12_DRV0 (*((volatile unsigned int*)(0x42A78E10UL))) +#define bM4_PORT_PCRB12_DRV1 (*((volatile unsigned int*)(0x42A78E14UL))) +#define bM4_PORT_PCRB12_PUU (*((volatile unsigned int*)(0x42A78E18UL))) +#define bM4_PORT_PCRB12_PIN (*((volatile unsigned int*)(0x42A78E20UL))) +#define bM4_PORT_PCRB12_INVE (*((volatile unsigned int*)(0x42A78E24UL))) +#define bM4_PORT_PCRB12_INTE (*((volatile unsigned int*)(0x42A78E30UL))) +#define bM4_PORT_PCRB12_LTE (*((volatile unsigned int*)(0x42A78E38UL))) +#define bM4_PORT_PCRB12_DDIS (*((volatile unsigned int*)(0x42A78E3CUL))) +#define bM4_PORT_PFSRB12_FSEL0 (*((volatile unsigned int*)(0x42A78E40UL))) +#define bM4_PORT_PFSRB12_FSEL1 (*((volatile unsigned int*)(0x42A78E44UL))) +#define bM4_PORT_PFSRB12_FSEL2 (*((volatile unsigned int*)(0x42A78E48UL))) +#define bM4_PORT_PFSRB12_FSEL3 (*((volatile unsigned int*)(0x42A78E4CUL))) +#define bM4_PORT_PFSRB12_FSEL4 (*((volatile unsigned int*)(0x42A78E50UL))) +#define bM4_PORT_PFSRB12_FSEL5 (*((volatile unsigned int*)(0x42A78E54UL))) +#define bM4_PORT_PFSRB12_BFE (*((volatile unsigned int*)(0x42A78E60UL))) +#define bM4_PORT_PCRB13_POUT (*((volatile unsigned int*)(0x42A78E80UL))) +#define bM4_PORT_PCRB13_POUTE (*((volatile unsigned int*)(0x42A78E84UL))) +#define bM4_PORT_PCRB13_NOD (*((volatile unsigned int*)(0x42A78E88UL))) +#define bM4_PORT_PCRB13_DRV0 (*((volatile unsigned int*)(0x42A78E90UL))) +#define bM4_PORT_PCRB13_DRV1 (*((volatile unsigned int*)(0x42A78E94UL))) +#define bM4_PORT_PCRB13_PUU (*((volatile unsigned int*)(0x42A78E98UL))) +#define bM4_PORT_PCRB13_PIN (*((volatile unsigned int*)(0x42A78EA0UL))) +#define bM4_PORT_PCRB13_INVE (*((volatile unsigned int*)(0x42A78EA4UL))) +#define bM4_PORT_PCRB13_INTE (*((volatile unsigned int*)(0x42A78EB0UL))) +#define bM4_PORT_PCRB13_LTE (*((volatile unsigned int*)(0x42A78EB8UL))) +#define bM4_PORT_PCRB13_DDIS (*((volatile unsigned int*)(0x42A78EBCUL))) +#define bM4_PORT_PFSRB13_FSEL0 (*((volatile unsigned int*)(0x42A78EC0UL))) +#define bM4_PORT_PFSRB13_FSEL1 (*((volatile unsigned int*)(0x42A78EC4UL))) +#define bM4_PORT_PFSRB13_FSEL2 (*((volatile unsigned int*)(0x42A78EC8UL))) +#define bM4_PORT_PFSRB13_FSEL3 (*((volatile unsigned int*)(0x42A78ECCUL))) +#define bM4_PORT_PFSRB13_FSEL4 (*((volatile unsigned int*)(0x42A78ED0UL))) +#define bM4_PORT_PFSRB13_FSEL5 (*((volatile unsigned int*)(0x42A78ED4UL))) +#define bM4_PORT_PFSRB13_BFE (*((volatile unsigned int*)(0x42A78EE0UL))) +#define bM4_PORT_PCRB14_POUT (*((volatile unsigned int*)(0x42A78F00UL))) +#define bM4_PORT_PCRB14_POUTE (*((volatile unsigned int*)(0x42A78F04UL))) +#define bM4_PORT_PCRB14_NOD (*((volatile unsigned int*)(0x42A78F08UL))) +#define bM4_PORT_PCRB14_DRV0 (*((volatile unsigned int*)(0x42A78F10UL))) +#define bM4_PORT_PCRB14_DRV1 (*((volatile unsigned int*)(0x42A78F14UL))) +#define bM4_PORT_PCRB14_PUU (*((volatile unsigned int*)(0x42A78F18UL))) +#define bM4_PORT_PCRB14_PIN (*((volatile unsigned int*)(0x42A78F20UL))) +#define bM4_PORT_PCRB14_INVE (*((volatile unsigned int*)(0x42A78F24UL))) +#define bM4_PORT_PCRB14_INTE (*((volatile unsigned int*)(0x42A78F30UL))) +#define bM4_PORT_PCRB14_LTE (*((volatile unsigned int*)(0x42A78F38UL))) +#define bM4_PORT_PCRB14_DDIS (*((volatile unsigned int*)(0x42A78F3CUL))) +#define bM4_PORT_PFSRB14_FSEL0 (*((volatile unsigned int*)(0x42A78F40UL))) +#define bM4_PORT_PFSRB14_FSEL1 (*((volatile unsigned int*)(0x42A78F44UL))) +#define bM4_PORT_PFSRB14_FSEL2 (*((volatile unsigned int*)(0x42A78F48UL))) +#define bM4_PORT_PFSRB14_FSEL3 (*((volatile unsigned int*)(0x42A78F4CUL))) +#define bM4_PORT_PFSRB14_FSEL4 (*((volatile unsigned int*)(0x42A78F50UL))) +#define bM4_PORT_PFSRB14_FSEL5 (*((volatile unsigned int*)(0x42A78F54UL))) +#define bM4_PORT_PFSRB14_BFE (*((volatile unsigned int*)(0x42A78F60UL))) +#define bM4_PORT_PCRB15_POUT (*((volatile unsigned int*)(0x42A78F80UL))) +#define bM4_PORT_PCRB15_POUTE (*((volatile unsigned int*)(0x42A78F84UL))) +#define bM4_PORT_PCRB15_NOD (*((volatile unsigned int*)(0x42A78F88UL))) +#define bM4_PORT_PCRB15_DRV0 (*((volatile unsigned int*)(0x42A78F90UL))) +#define bM4_PORT_PCRB15_DRV1 (*((volatile unsigned int*)(0x42A78F94UL))) +#define bM4_PORT_PCRB15_PUU (*((volatile unsigned int*)(0x42A78F98UL))) +#define bM4_PORT_PCRB15_PIN (*((volatile unsigned int*)(0x42A78FA0UL))) +#define bM4_PORT_PCRB15_INVE (*((volatile unsigned int*)(0x42A78FA4UL))) +#define bM4_PORT_PCRB15_INTE (*((volatile unsigned int*)(0x42A78FB0UL))) +#define bM4_PORT_PCRB15_LTE (*((volatile unsigned int*)(0x42A78FB8UL))) +#define bM4_PORT_PCRB15_DDIS (*((volatile unsigned int*)(0x42A78FBCUL))) +#define bM4_PORT_PFSRB15_FSEL0 (*((volatile unsigned int*)(0x42A78FC0UL))) +#define bM4_PORT_PFSRB15_FSEL1 (*((volatile unsigned int*)(0x42A78FC4UL))) +#define bM4_PORT_PFSRB15_FSEL2 (*((volatile unsigned int*)(0x42A78FC8UL))) +#define bM4_PORT_PFSRB15_FSEL3 (*((volatile unsigned int*)(0x42A78FCCUL))) +#define bM4_PORT_PFSRB15_FSEL4 (*((volatile unsigned int*)(0x42A78FD0UL))) +#define bM4_PORT_PFSRB15_FSEL5 (*((volatile unsigned int*)(0x42A78FD4UL))) +#define bM4_PORT_PFSRB15_BFE (*((volatile unsigned int*)(0x42A78FE0UL))) +#define bM4_PORT_PCRC0_POUT (*((volatile unsigned int*)(0x42A79000UL))) +#define bM4_PORT_PCRC0_POUTE (*((volatile unsigned int*)(0x42A79004UL))) +#define bM4_PORT_PCRC0_NOD (*((volatile unsigned int*)(0x42A79008UL))) +#define bM4_PORT_PCRC0_DRV0 (*((volatile unsigned int*)(0x42A79010UL))) +#define bM4_PORT_PCRC0_DRV1 (*((volatile unsigned int*)(0x42A79014UL))) +#define bM4_PORT_PCRC0_PUU (*((volatile unsigned int*)(0x42A79018UL))) +#define bM4_PORT_PCRC0_PIN (*((volatile unsigned int*)(0x42A79020UL))) +#define bM4_PORT_PCRC0_INVE (*((volatile unsigned int*)(0x42A79024UL))) +#define bM4_PORT_PCRC0_INTE (*((volatile unsigned int*)(0x42A79030UL))) +#define bM4_PORT_PCRC0_LTE (*((volatile unsigned int*)(0x42A79038UL))) +#define bM4_PORT_PCRC0_DDIS (*((volatile unsigned int*)(0x42A7903CUL))) +#define bM4_PORT_PFSRC0_FSEL0 (*((volatile unsigned int*)(0x42A79040UL))) +#define bM4_PORT_PFSRC0_FSEL1 (*((volatile unsigned int*)(0x42A79044UL))) +#define bM4_PORT_PFSRC0_FSEL2 (*((volatile unsigned int*)(0x42A79048UL))) +#define bM4_PORT_PFSRC0_FSEL3 (*((volatile unsigned int*)(0x42A7904CUL))) +#define bM4_PORT_PFSRC0_FSEL4 (*((volatile unsigned int*)(0x42A79050UL))) +#define bM4_PORT_PFSRC0_FSEL5 (*((volatile unsigned int*)(0x42A79054UL))) +#define bM4_PORT_PFSRC0_BFE (*((volatile unsigned int*)(0x42A79060UL))) +#define bM4_PORT_PCRC1_POUT (*((volatile unsigned int*)(0x42A79080UL))) +#define bM4_PORT_PCRC1_POUTE (*((volatile unsigned int*)(0x42A79084UL))) +#define bM4_PORT_PCRC1_NOD (*((volatile unsigned int*)(0x42A79088UL))) +#define bM4_PORT_PCRC1_DRV0 (*((volatile unsigned int*)(0x42A79090UL))) +#define bM4_PORT_PCRC1_DRV1 (*((volatile unsigned int*)(0x42A79094UL))) +#define bM4_PORT_PCRC1_PUU (*((volatile unsigned int*)(0x42A79098UL))) +#define bM4_PORT_PCRC1_PIN (*((volatile unsigned int*)(0x42A790A0UL))) +#define bM4_PORT_PCRC1_INVE (*((volatile unsigned int*)(0x42A790A4UL))) +#define bM4_PORT_PCRC1_INTE (*((volatile unsigned int*)(0x42A790B0UL))) +#define bM4_PORT_PCRC1_LTE (*((volatile unsigned int*)(0x42A790B8UL))) +#define bM4_PORT_PCRC1_DDIS (*((volatile unsigned int*)(0x42A790BCUL))) +#define bM4_PORT_PFSRC1_FSEL0 (*((volatile unsigned int*)(0x42A790C0UL))) +#define bM4_PORT_PFSRC1_FSEL1 (*((volatile unsigned int*)(0x42A790C4UL))) +#define bM4_PORT_PFSRC1_FSEL2 (*((volatile unsigned int*)(0x42A790C8UL))) +#define bM4_PORT_PFSRC1_FSEL3 (*((volatile unsigned int*)(0x42A790CCUL))) +#define bM4_PORT_PFSRC1_FSEL4 (*((volatile unsigned int*)(0x42A790D0UL))) +#define bM4_PORT_PFSRC1_FSEL5 (*((volatile unsigned int*)(0x42A790D4UL))) +#define bM4_PORT_PFSRC1_BFE (*((volatile unsigned int*)(0x42A790E0UL))) +#define bM4_PORT_PCRC2_POUT (*((volatile unsigned int*)(0x42A79100UL))) +#define bM4_PORT_PCRC2_POUTE (*((volatile unsigned int*)(0x42A79104UL))) +#define bM4_PORT_PCRC2_NOD (*((volatile unsigned int*)(0x42A79108UL))) +#define bM4_PORT_PCRC2_DRV0 (*((volatile unsigned int*)(0x42A79110UL))) +#define bM4_PORT_PCRC2_DRV1 (*((volatile unsigned int*)(0x42A79114UL))) +#define bM4_PORT_PCRC2_PUU (*((volatile unsigned int*)(0x42A79118UL))) +#define bM4_PORT_PCRC2_PIN (*((volatile unsigned int*)(0x42A79120UL))) +#define bM4_PORT_PCRC2_INVE (*((volatile unsigned int*)(0x42A79124UL))) +#define bM4_PORT_PCRC2_INTE (*((volatile unsigned int*)(0x42A79130UL))) +#define bM4_PORT_PCRC2_LTE (*((volatile unsigned int*)(0x42A79138UL))) +#define bM4_PORT_PCRC2_DDIS (*((volatile unsigned int*)(0x42A7913CUL))) +#define bM4_PORT_PFSRC2_FSEL0 (*((volatile unsigned int*)(0x42A79140UL))) +#define bM4_PORT_PFSRC2_FSEL1 (*((volatile unsigned int*)(0x42A79144UL))) +#define bM4_PORT_PFSRC2_FSEL2 (*((volatile unsigned int*)(0x42A79148UL))) +#define bM4_PORT_PFSRC2_FSEL3 (*((volatile unsigned int*)(0x42A7914CUL))) +#define bM4_PORT_PFSRC2_FSEL4 (*((volatile unsigned int*)(0x42A79150UL))) +#define bM4_PORT_PFSRC2_FSEL5 (*((volatile unsigned int*)(0x42A79154UL))) +#define bM4_PORT_PFSRC2_BFE (*((volatile unsigned int*)(0x42A79160UL))) +#define bM4_PORT_PCRC3_POUT (*((volatile unsigned int*)(0x42A79180UL))) +#define bM4_PORT_PCRC3_POUTE (*((volatile unsigned int*)(0x42A79184UL))) +#define bM4_PORT_PCRC3_NOD (*((volatile unsigned int*)(0x42A79188UL))) +#define bM4_PORT_PCRC3_DRV0 (*((volatile unsigned int*)(0x42A79190UL))) +#define bM4_PORT_PCRC3_DRV1 (*((volatile unsigned int*)(0x42A79194UL))) +#define bM4_PORT_PCRC3_PUU (*((volatile unsigned int*)(0x42A79198UL))) +#define bM4_PORT_PCRC3_PIN (*((volatile unsigned int*)(0x42A791A0UL))) +#define bM4_PORT_PCRC3_INVE (*((volatile unsigned int*)(0x42A791A4UL))) +#define bM4_PORT_PCRC3_INTE (*((volatile unsigned int*)(0x42A791B0UL))) +#define bM4_PORT_PCRC3_LTE (*((volatile unsigned int*)(0x42A791B8UL))) +#define bM4_PORT_PCRC3_DDIS (*((volatile unsigned int*)(0x42A791BCUL))) +#define bM4_PORT_PFSRC3_FSEL0 (*((volatile unsigned int*)(0x42A791C0UL))) +#define bM4_PORT_PFSRC3_FSEL1 (*((volatile unsigned int*)(0x42A791C4UL))) +#define bM4_PORT_PFSRC3_FSEL2 (*((volatile unsigned int*)(0x42A791C8UL))) +#define bM4_PORT_PFSRC3_FSEL3 (*((volatile unsigned int*)(0x42A791CCUL))) +#define bM4_PORT_PFSRC3_FSEL4 (*((volatile unsigned int*)(0x42A791D0UL))) +#define bM4_PORT_PFSRC3_FSEL5 (*((volatile unsigned int*)(0x42A791D4UL))) +#define bM4_PORT_PFSRC3_BFE (*((volatile unsigned int*)(0x42A791E0UL))) +#define bM4_PORT_PCRC4_POUT (*((volatile unsigned int*)(0x42A79200UL))) +#define bM4_PORT_PCRC4_POUTE (*((volatile unsigned int*)(0x42A79204UL))) +#define bM4_PORT_PCRC4_NOD (*((volatile unsigned int*)(0x42A79208UL))) +#define bM4_PORT_PCRC4_DRV0 (*((volatile unsigned int*)(0x42A79210UL))) +#define bM4_PORT_PCRC4_DRV1 (*((volatile unsigned int*)(0x42A79214UL))) +#define bM4_PORT_PCRC4_PUU (*((volatile unsigned int*)(0x42A79218UL))) +#define bM4_PORT_PCRC4_PIN (*((volatile unsigned int*)(0x42A79220UL))) +#define bM4_PORT_PCRC4_INVE (*((volatile unsigned int*)(0x42A79224UL))) +#define bM4_PORT_PCRC4_INTE (*((volatile unsigned int*)(0x42A79230UL))) +#define bM4_PORT_PCRC4_LTE (*((volatile unsigned int*)(0x42A79238UL))) +#define bM4_PORT_PCRC4_DDIS (*((volatile unsigned int*)(0x42A7923CUL))) +#define bM4_PORT_PFSRC4_FSEL0 (*((volatile unsigned int*)(0x42A79240UL))) +#define bM4_PORT_PFSRC4_FSEL1 (*((volatile unsigned int*)(0x42A79244UL))) +#define bM4_PORT_PFSRC4_FSEL2 (*((volatile unsigned int*)(0x42A79248UL))) +#define bM4_PORT_PFSRC4_FSEL3 (*((volatile unsigned int*)(0x42A7924CUL))) +#define bM4_PORT_PFSRC4_FSEL4 (*((volatile unsigned int*)(0x42A79250UL))) +#define bM4_PORT_PFSRC4_FSEL5 (*((volatile unsigned int*)(0x42A79254UL))) +#define bM4_PORT_PFSRC4_BFE (*((volatile unsigned int*)(0x42A79260UL))) +#define bM4_PORT_PCRC5_POUT (*((volatile unsigned int*)(0x42A79280UL))) +#define bM4_PORT_PCRC5_POUTE (*((volatile unsigned int*)(0x42A79284UL))) +#define bM4_PORT_PCRC5_NOD (*((volatile unsigned int*)(0x42A79288UL))) +#define bM4_PORT_PCRC5_DRV0 (*((volatile unsigned int*)(0x42A79290UL))) +#define bM4_PORT_PCRC5_DRV1 (*((volatile unsigned int*)(0x42A79294UL))) +#define bM4_PORT_PCRC5_PUU (*((volatile unsigned int*)(0x42A79298UL))) +#define bM4_PORT_PCRC5_PIN (*((volatile unsigned int*)(0x42A792A0UL))) +#define bM4_PORT_PCRC5_INVE (*((volatile unsigned int*)(0x42A792A4UL))) +#define bM4_PORT_PCRC5_INTE (*((volatile unsigned int*)(0x42A792B0UL))) +#define bM4_PORT_PCRC5_LTE (*((volatile unsigned int*)(0x42A792B8UL))) +#define bM4_PORT_PCRC5_DDIS (*((volatile unsigned int*)(0x42A792BCUL))) +#define bM4_PORT_PFSRC5_FSEL0 (*((volatile unsigned int*)(0x42A792C0UL))) +#define bM4_PORT_PFSRC5_FSEL1 (*((volatile unsigned int*)(0x42A792C4UL))) +#define bM4_PORT_PFSRC5_FSEL2 (*((volatile unsigned int*)(0x42A792C8UL))) +#define bM4_PORT_PFSRC5_FSEL3 (*((volatile unsigned int*)(0x42A792CCUL))) +#define bM4_PORT_PFSRC5_FSEL4 (*((volatile unsigned int*)(0x42A792D0UL))) +#define bM4_PORT_PFSRC5_FSEL5 (*((volatile unsigned int*)(0x42A792D4UL))) +#define bM4_PORT_PFSRC5_BFE (*((volatile unsigned int*)(0x42A792E0UL))) +#define bM4_PORT_PCRC6_POUT (*((volatile unsigned int*)(0x42A79300UL))) +#define bM4_PORT_PCRC6_POUTE (*((volatile unsigned int*)(0x42A79304UL))) +#define bM4_PORT_PCRC6_NOD (*((volatile unsigned int*)(0x42A79308UL))) +#define bM4_PORT_PCRC6_DRV0 (*((volatile unsigned int*)(0x42A79310UL))) +#define bM4_PORT_PCRC6_DRV1 (*((volatile unsigned int*)(0x42A79314UL))) +#define bM4_PORT_PCRC6_PUU (*((volatile unsigned int*)(0x42A79318UL))) +#define bM4_PORT_PCRC6_PIN (*((volatile unsigned int*)(0x42A79320UL))) +#define bM4_PORT_PCRC6_INVE (*((volatile unsigned int*)(0x42A79324UL))) +#define bM4_PORT_PCRC6_INTE (*((volatile unsigned int*)(0x42A79330UL))) +#define bM4_PORT_PCRC6_LTE (*((volatile unsigned int*)(0x42A79338UL))) +#define bM4_PORT_PCRC6_DDIS (*((volatile unsigned int*)(0x42A7933CUL))) +#define bM4_PORT_PFSRC6_FSEL0 (*((volatile unsigned int*)(0x42A79340UL))) +#define bM4_PORT_PFSRC6_FSEL1 (*((volatile unsigned int*)(0x42A79344UL))) +#define bM4_PORT_PFSRC6_FSEL2 (*((volatile unsigned int*)(0x42A79348UL))) +#define bM4_PORT_PFSRC6_FSEL3 (*((volatile unsigned int*)(0x42A7934CUL))) +#define bM4_PORT_PFSRC6_FSEL4 (*((volatile unsigned int*)(0x42A79350UL))) +#define bM4_PORT_PFSRC6_FSEL5 (*((volatile unsigned int*)(0x42A79354UL))) +#define bM4_PORT_PFSRC6_BFE (*((volatile unsigned int*)(0x42A79360UL))) +#define bM4_PORT_PCRC7_POUT (*((volatile unsigned int*)(0x42A79380UL))) +#define bM4_PORT_PCRC7_POUTE (*((volatile unsigned int*)(0x42A79384UL))) +#define bM4_PORT_PCRC7_NOD (*((volatile unsigned int*)(0x42A79388UL))) +#define bM4_PORT_PCRC7_DRV0 (*((volatile unsigned int*)(0x42A79390UL))) +#define bM4_PORT_PCRC7_DRV1 (*((volatile unsigned int*)(0x42A79394UL))) +#define bM4_PORT_PCRC7_PUU (*((volatile unsigned int*)(0x42A79398UL))) +#define bM4_PORT_PCRC7_PIN (*((volatile unsigned int*)(0x42A793A0UL))) +#define bM4_PORT_PCRC7_INVE (*((volatile unsigned int*)(0x42A793A4UL))) +#define bM4_PORT_PCRC7_INTE (*((volatile unsigned int*)(0x42A793B0UL))) +#define bM4_PORT_PCRC7_LTE (*((volatile unsigned int*)(0x42A793B8UL))) +#define bM4_PORT_PCRC7_DDIS (*((volatile unsigned int*)(0x42A793BCUL))) +#define bM4_PORT_PFSRC7_FSEL0 (*((volatile unsigned int*)(0x42A793C0UL))) +#define bM4_PORT_PFSRC7_FSEL1 (*((volatile unsigned int*)(0x42A793C4UL))) +#define bM4_PORT_PFSRC7_FSEL2 (*((volatile unsigned int*)(0x42A793C8UL))) +#define bM4_PORT_PFSRC7_FSEL3 (*((volatile unsigned int*)(0x42A793CCUL))) +#define bM4_PORT_PFSRC7_FSEL4 (*((volatile unsigned int*)(0x42A793D0UL))) +#define bM4_PORT_PFSRC7_FSEL5 (*((volatile unsigned int*)(0x42A793D4UL))) +#define bM4_PORT_PFSRC7_BFE (*((volatile unsigned int*)(0x42A793E0UL))) +#define bM4_PORT_PCRC8_POUT (*((volatile unsigned int*)(0x42A79400UL))) +#define bM4_PORT_PCRC8_POUTE (*((volatile unsigned int*)(0x42A79404UL))) +#define bM4_PORT_PCRC8_NOD (*((volatile unsigned int*)(0x42A79408UL))) +#define bM4_PORT_PCRC8_DRV0 (*((volatile unsigned int*)(0x42A79410UL))) +#define bM4_PORT_PCRC8_DRV1 (*((volatile unsigned int*)(0x42A79414UL))) +#define bM4_PORT_PCRC8_PUU (*((volatile unsigned int*)(0x42A79418UL))) +#define bM4_PORT_PCRC8_PIN (*((volatile unsigned int*)(0x42A79420UL))) +#define bM4_PORT_PCRC8_INVE (*((volatile unsigned int*)(0x42A79424UL))) +#define bM4_PORT_PCRC8_INTE (*((volatile unsigned int*)(0x42A79430UL))) +#define bM4_PORT_PCRC8_LTE (*((volatile unsigned int*)(0x42A79438UL))) +#define bM4_PORT_PCRC8_DDIS (*((volatile unsigned int*)(0x42A7943CUL))) +#define bM4_PORT_PFSRC8_FSEL0 (*((volatile unsigned int*)(0x42A79440UL))) +#define bM4_PORT_PFSRC8_FSEL1 (*((volatile unsigned int*)(0x42A79444UL))) +#define bM4_PORT_PFSRC8_FSEL2 (*((volatile unsigned int*)(0x42A79448UL))) +#define bM4_PORT_PFSRC8_FSEL3 (*((volatile unsigned int*)(0x42A7944CUL))) +#define bM4_PORT_PFSRC8_FSEL4 (*((volatile unsigned int*)(0x42A79450UL))) +#define bM4_PORT_PFSRC8_FSEL5 (*((volatile unsigned int*)(0x42A79454UL))) +#define bM4_PORT_PFSRC8_BFE (*((volatile unsigned int*)(0x42A79460UL))) +#define bM4_PORT_PCRC9_POUT (*((volatile unsigned int*)(0x42A79480UL))) +#define bM4_PORT_PCRC9_POUTE (*((volatile unsigned int*)(0x42A79484UL))) +#define bM4_PORT_PCRC9_NOD (*((volatile unsigned int*)(0x42A79488UL))) +#define bM4_PORT_PCRC9_DRV0 (*((volatile unsigned int*)(0x42A79490UL))) +#define bM4_PORT_PCRC9_DRV1 (*((volatile unsigned int*)(0x42A79494UL))) +#define bM4_PORT_PCRC9_PUU (*((volatile unsigned int*)(0x42A79498UL))) +#define bM4_PORT_PCRC9_PIN (*((volatile unsigned int*)(0x42A794A0UL))) +#define bM4_PORT_PCRC9_INVE (*((volatile unsigned int*)(0x42A794A4UL))) +#define bM4_PORT_PCRC9_INTE (*((volatile unsigned int*)(0x42A794B0UL))) +#define bM4_PORT_PCRC9_LTE (*((volatile unsigned int*)(0x42A794B8UL))) +#define bM4_PORT_PCRC9_DDIS (*((volatile unsigned int*)(0x42A794BCUL))) +#define bM4_PORT_PFSRC9_FSEL0 (*((volatile unsigned int*)(0x42A794C0UL))) +#define bM4_PORT_PFSRC9_FSEL1 (*((volatile unsigned int*)(0x42A794C4UL))) +#define bM4_PORT_PFSRC9_FSEL2 (*((volatile unsigned int*)(0x42A794C8UL))) +#define bM4_PORT_PFSRC9_FSEL3 (*((volatile unsigned int*)(0x42A794CCUL))) +#define bM4_PORT_PFSRC9_FSEL4 (*((volatile unsigned int*)(0x42A794D0UL))) +#define bM4_PORT_PFSRC9_FSEL5 (*((volatile unsigned int*)(0x42A794D4UL))) +#define bM4_PORT_PFSRC9_BFE (*((volatile unsigned int*)(0x42A794E0UL))) +#define bM4_PORT_PCRC10_POUT (*((volatile unsigned int*)(0x42A79500UL))) +#define bM4_PORT_PCRC10_POUTE (*((volatile unsigned int*)(0x42A79504UL))) +#define bM4_PORT_PCRC10_NOD (*((volatile unsigned int*)(0x42A79508UL))) +#define bM4_PORT_PCRC10_DRV0 (*((volatile unsigned int*)(0x42A79510UL))) +#define bM4_PORT_PCRC10_DRV1 (*((volatile unsigned int*)(0x42A79514UL))) +#define bM4_PORT_PCRC10_PUU (*((volatile unsigned int*)(0x42A79518UL))) +#define bM4_PORT_PCRC10_PIN (*((volatile unsigned int*)(0x42A79520UL))) +#define bM4_PORT_PCRC10_INVE (*((volatile unsigned int*)(0x42A79524UL))) +#define bM4_PORT_PCRC10_INTE (*((volatile unsigned int*)(0x42A79530UL))) +#define bM4_PORT_PCRC10_LTE (*((volatile unsigned int*)(0x42A79538UL))) +#define bM4_PORT_PCRC10_DDIS (*((volatile unsigned int*)(0x42A7953CUL))) +#define bM4_PORT_PFSRC10_FSEL0 (*((volatile unsigned int*)(0x42A79540UL))) +#define bM4_PORT_PFSRC10_FSEL1 (*((volatile unsigned int*)(0x42A79544UL))) +#define bM4_PORT_PFSRC10_FSEL2 (*((volatile unsigned int*)(0x42A79548UL))) +#define bM4_PORT_PFSRC10_FSEL3 (*((volatile unsigned int*)(0x42A7954CUL))) +#define bM4_PORT_PFSRC10_FSEL4 (*((volatile unsigned int*)(0x42A79550UL))) +#define bM4_PORT_PFSRC10_FSEL5 (*((volatile unsigned int*)(0x42A79554UL))) +#define bM4_PORT_PFSRC10_BFE (*((volatile unsigned int*)(0x42A79560UL))) +#define bM4_PORT_PCRC11_POUT (*((volatile unsigned int*)(0x42A79580UL))) +#define bM4_PORT_PCRC11_POUTE (*((volatile unsigned int*)(0x42A79584UL))) +#define bM4_PORT_PCRC11_NOD (*((volatile unsigned int*)(0x42A79588UL))) +#define bM4_PORT_PCRC11_DRV0 (*((volatile unsigned int*)(0x42A79590UL))) +#define bM4_PORT_PCRC11_DRV1 (*((volatile unsigned int*)(0x42A79594UL))) +#define bM4_PORT_PCRC11_PUU (*((volatile unsigned int*)(0x42A79598UL))) +#define bM4_PORT_PCRC11_PIN (*((volatile unsigned int*)(0x42A795A0UL))) +#define bM4_PORT_PCRC11_INVE (*((volatile unsigned int*)(0x42A795A4UL))) +#define bM4_PORT_PCRC11_INTE (*((volatile unsigned int*)(0x42A795B0UL))) +#define bM4_PORT_PCRC11_LTE (*((volatile unsigned int*)(0x42A795B8UL))) +#define bM4_PORT_PCRC11_DDIS (*((volatile unsigned int*)(0x42A795BCUL))) +#define bM4_PORT_PFSRC11_FSEL0 (*((volatile unsigned int*)(0x42A795C0UL))) +#define bM4_PORT_PFSRC11_FSEL1 (*((volatile unsigned int*)(0x42A795C4UL))) +#define bM4_PORT_PFSRC11_FSEL2 (*((volatile unsigned int*)(0x42A795C8UL))) +#define bM4_PORT_PFSRC11_FSEL3 (*((volatile unsigned int*)(0x42A795CCUL))) +#define bM4_PORT_PFSRC11_FSEL4 (*((volatile unsigned int*)(0x42A795D0UL))) +#define bM4_PORT_PFSRC11_FSEL5 (*((volatile unsigned int*)(0x42A795D4UL))) +#define bM4_PORT_PFSRC11_BFE (*((volatile unsigned int*)(0x42A795E0UL))) +#define bM4_PORT_PCRC12_POUT (*((volatile unsigned int*)(0x42A79600UL))) +#define bM4_PORT_PCRC12_POUTE (*((volatile unsigned int*)(0x42A79604UL))) +#define bM4_PORT_PCRC12_NOD (*((volatile unsigned int*)(0x42A79608UL))) +#define bM4_PORT_PCRC12_DRV0 (*((volatile unsigned int*)(0x42A79610UL))) +#define bM4_PORT_PCRC12_DRV1 (*((volatile unsigned int*)(0x42A79614UL))) +#define bM4_PORT_PCRC12_PUU (*((volatile unsigned int*)(0x42A79618UL))) +#define bM4_PORT_PCRC12_PIN (*((volatile unsigned int*)(0x42A79620UL))) +#define bM4_PORT_PCRC12_INVE (*((volatile unsigned int*)(0x42A79624UL))) +#define bM4_PORT_PCRC12_INTE (*((volatile unsigned int*)(0x42A79630UL))) +#define bM4_PORT_PCRC12_LTE (*((volatile unsigned int*)(0x42A79638UL))) +#define bM4_PORT_PCRC12_DDIS (*((volatile unsigned int*)(0x42A7963CUL))) +#define bM4_PORT_PFSRC12_FSEL0 (*((volatile unsigned int*)(0x42A79640UL))) +#define bM4_PORT_PFSRC12_FSEL1 (*((volatile unsigned int*)(0x42A79644UL))) +#define bM4_PORT_PFSRC12_FSEL2 (*((volatile unsigned int*)(0x42A79648UL))) +#define bM4_PORT_PFSRC12_FSEL3 (*((volatile unsigned int*)(0x42A7964CUL))) +#define bM4_PORT_PFSRC12_FSEL4 (*((volatile unsigned int*)(0x42A79650UL))) +#define bM4_PORT_PFSRC12_FSEL5 (*((volatile unsigned int*)(0x42A79654UL))) +#define bM4_PORT_PFSRC12_BFE (*((volatile unsigned int*)(0x42A79660UL))) +#define bM4_PORT_PCRC13_POUT (*((volatile unsigned int*)(0x42A79680UL))) +#define bM4_PORT_PCRC13_POUTE (*((volatile unsigned int*)(0x42A79684UL))) +#define bM4_PORT_PCRC13_NOD (*((volatile unsigned int*)(0x42A79688UL))) +#define bM4_PORT_PCRC13_DRV0 (*((volatile unsigned int*)(0x42A79690UL))) +#define bM4_PORT_PCRC13_DRV1 (*((volatile unsigned int*)(0x42A79694UL))) +#define bM4_PORT_PCRC13_PUU (*((volatile unsigned int*)(0x42A79698UL))) +#define bM4_PORT_PCRC13_PIN (*((volatile unsigned int*)(0x42A796A0UL))) +#define bM4_PORT_PCRC13_INVE (*((volatile unsigned int*)(0x42A796A4UL))) +#define bM4_PORT_PCRC13_INTE (*((volatile unsigned int*)(0x42A796B0UL))) +#define bM4_PORT_PCRC13_LTE (*((volatile unsigned int*)(0x42A796B8UL))) +#define bM4_PORT_PCRC13_DDIS (*((volatile unsigned int*)(0x42A796BCUL))) +#define bM4_PORT_PFSRC13_FSEL0 (*((volatile unsigned int*)(0x42A796C0UL))) +#define bM4_PORT_PFSRC13_FSEL1 (*((volatile unsigned int*)(0x42A796C4UL))) +#define bM4_PORT_PFSRC13_FSEL2 (*((volatile unsigned int*)(0x42A796C8UL))) +#define bM4_PORT_PFSRC13_FSEL3 (*((volatile unsigned int*)(0x42A796CCUL))) +#define bM4_PORT_PFSRC13_FSEL4 (*((volatile unsigned int*)(0x42A796D0UL))) +#define bM4_PORT_PFSRC13_FSEL5 (*((volatile unsigned int*)(0x42A796D4UL))) +#define bM4_PORT_PFSRC13_BFE (*((volatile unsigned int*)(0x42A796E0UL))) +#define bM4_PORT_PCRC14_POUT (*((volatile unsigned int*)(0x42A79700UL))) +#define bM4_PORT_PCRC14_POUTE (*((volatile unsigned int*)(0x42A79704UL))) +#define bM4_PORT_PCRC14_NOD (*((volatile unsigned int*)(0x42A79708UL))) +#define bM4_PORT_PCRC14_DRV0 (*((volatile unsigned int*)(0x42A79710UL))) +#define bM4_PORT_PCRC14_DRV1 (*((volatile unsigned int*)(0x42A79714UL))) +#define bM4_PORT_PCRC14_PUU (*((volatile unsigned int*)(0x42A79718UL))) +#define bM4_PORT_PCRC14_PIN (*((volatile unsigned int*)(0x42A79720UL))) +#define bM4_PORT_PCRC14_INVE (*((volatile unsigned int*)(0x42A79724UL))) +#define bM4_PORT_PCRC14_INTE (*((volatile unsigned int*)(0x42A79730UL))) +#define bM4_PORT_PCRC14_LTE (*((volatile unsigned int*)(0x42A79738UL))) +#define bM4_PORT_PCRC14_DDIS (*((volatile unsigned int*)(0x42A7973CUL))) +#define bM4_PORT_PFSRC14_FSEL0 (*((volatile unsigned int*)(0x42A79740UL))) +#define bM4_PORT_PFSRC14_FSEL1 (*((volatile unsigned int*)(0x42A79744UL))) +#define bM4_PORT_PFSRC14_FSEL2 (*((volatile unsigned int*)(0x42A79748UL))) +#define bM4_PORT_PFSRC14_FSEL3 (*((volatile unsigned int*)(0x42A7974CUL))) +#define bM4_PORT_PFSRC14_FSEL4 (*((volatile unsigned int*)(0x42A79750UL))) +#define bM4_PORT_PFSRC14_FSEL5 (*((volatile unsigned int*)(0x42A79754UL))) +#define bM4_PORT_PFSRC14_BFE (*((volatile unsigned int*)(0x42A79760UL))) +#define bM4_PORT_PCRC15_POUT (*((volatile unsigned int*)(0x42A79780UL))) +#define bM4_PORT_PCRC15_POUTE (*((volatile unsigned int*)(0x42A79784UL))) +#define bM4_PORT_PCRC15_NOD (*((volatile unsigned int*)(0x42A79788UL))) +#define bM4_PORT_PCRC15_DRV0 (*((volatile unsigned int*)(0x42A79790UL))) +#define bM4_PORT_PCRC15_DRV1 (*((volatile unsigned int*)(0x42A79794UL))) +#define bM4_PORT_PCRC15_PUU (*((volatile unsigned int*)(0x42A79798UL))) +#define bM4_PORT_PCRC15_PIN (*((volatile unsigned int*)(0x42A797A0UL))) +#define bM4_PORT_PCRC15_INVE (*((volatile unsigned int*)(0x42A797A4UL))) +#define bM4_PORT_PCRC15_INTE (*((volatile unsigned int*)(0x42A797B0UL))) +#define bM4_PORT_PCRC15_LTE (*((volatile unsigned int*)(0x42A797B8UL))) +#define bM4_PORT_PCRC15_DDIS (*((volatile unsigned int*)(0x42A797BCUL))) +#define bM4_PORT_PFSRC15_FSEL0 (*((volatile unsigned int*)(0x42A797C0UL))) +#define bM4_PORT_PFSRC15_FSEL1 (*((volatile unsigned int*)(0x42A797C4UL))) +#define bM4_PORT_PFSRC15_FSEL2 (*((volatile unsigned int*)(0x42A797C8UL))) +#define bM4_PORT_PFSRC15_FSEL3 (*((volatile unsigned int*)(0x42A797CCUL))) +#define bM4_PORT_PFSRC15_FSEL4 (*((volatile unsigned int*)(0x42A797D0UL))) +#define bM4_PORT_PFSRC15_FSEL5 (*((volatile unsigned int*)(0x42A797D4UL))) +#define bM4_PORT_PFSRC15_BFE (*((volatile unsigned int*)(0x42A797E0UL))) +#define bM4_PORT_PCRD0_POUT (*((volatile unsigned int*)(0x42A79800UL))) +#define bM4_PORT_PCRD0_POUTE (*((volatile unsigned int*)(0x42A79804UL))) +#define bM4_PORT_PCRD0_NOD (*((volatile unsigned int*)(0x42A79808UL))) +#define bM4_PORT_PCRD0_DRV0 (*((volatile unsigned int*)(0x42A79810UL))) +#define bM4_PORT_PCRD0_DRV1 (*((volatile unsigned int*)(0x42A79814UL))) +#define bM4_PORT_PCRD0_PUU (*((volatile unsigned int*)(0x42A79818UL))) +#define bM4_PORT_PCRD0_PIN (*((volatile unsigned int*)(0x42A79820UL))) +#define bM4_PORT_PCRD0_INVE (*((volatile unsigned int*)(0x42A79824UL))) +#define bM4_PORT_PCRD0_INTE (*((volatile unsigned int*)(0x42A79830UL))) +#define bM4_PORT_PCRD0_LTE (*((volatile unsigned int*)(0x42A79838UL))) +#define bM4_PORT_PCRD0_DDIS (*((volatile unsigned int*)(0x42A7983CUL))) +#define bM4_PORT_PFSRD0_FSEL0 (*((volatile unsigned int*)(0x42A79840UL))) +#define bM4_PORT_PFSRD0_FSEL1 (*((volatile unsigned int*)(0x42A79844UL))) +#define bM4_PORT_PFSRD0_FSEL2 (*((volatile unsigned int*)(0x42A79848UL))) +#define bM4_PORT_PFSRD0_FSEL3 (*((volatile unsigned int*)(0x42A7984CUL))) +#define bM4_PORT_PFSRD0_FSEL4 (*((volatile unsigned int*)(0x42A79850UL))) +#define bM4_PORT_PFSRD0_FSEL5 (*((volatile unsigned int*)(0x42A79854UL))) +#define bM4_PORT_PFSRD0_BFE (*((volatile unsigned int*)(0x42A79860UL))) +#define bM4_PORT_PCRD1_POUT (*((volatile unsigned int*)(0x42A79880UL))) +#define bM4_PORT_PCRD1_POUTE (*((volatile unsigned int*)(0x42A79884UL))) +#define bM4_PORT_PCRD1_NOD (*((volatile unsigned int*)(0x42A79888UL))) +#define bM4_PORT_PCRD1_DRV0 (*((volatile unsigned int*)(0x42A79890UL))) +#define bM4_PORT_PCRD1_DRV1 (*((volatile unsigned int*)(0x42A79894UL))) +#define bM4_PORT_PCRD1_PUU (*((volatile unsigned int*)(0x42A79898UL))) +#define bM4_PORT_PCRD1_PIN (*((volatile unsigned int*)(0x42A798A0UL))) +#define bM4_PORT_PCRD1_INVE (*((volatile unsigned int*)(0x42A798A4UL))) +#define bM4_PORT_PCRD1_INTE (*((volatile unsigned int*)(0x42A798B0UL))) +#define bM4_PORT_PCRD1_LTE (*((volatile unsigned int*)(0x42A798B8UL))) +#define bM4_PORT_PCRD1_DDIS (*((volatile unsigned int*)(0x42A798BCUL))) +#define bM4_PORT_PFSRD1_FSEL0 (*((volatile unsigned int*)(0x42A798C0UL))) +#define bM4_PORT_PFSRD1_FSEL1 (*((volatile unsigned int*)(0x42A798C4UL))) +#define bM4_PORT_PFSRD1_FSEL2 (*((volatile unsigned int*)(0x42A798C8UL))) +#define bM4_PORT_PFSRD1_FSEL3 (*((volatile unsigned int*)(0x42A798CCUL))) +#define bM4_PORT_PFSRD1_FSEL4 (*((volatile unsigned int*)(0x42A798D0UL))) +#define bM4_PORT_PFSRD1_FSEL5 (*((volatile unsigned int*)(0x42A798D4UL))) +#define bM4_PORT_PFSRD1_BFE (*((volatile unsigned int*)(0x42A798E0UL))) +#define bM4_PORT_PCRD2_POUT (*((volatile unsigned int*)(0x42A79900UL))) +#define bM4_PORT_PCRD2_POUTE (*((volatile unsigned int*)(0x42A79904UL))) +#define bM4_PORT_PCRD2_NOD (*((volatile unsigned int*)(0x42A79908UL))) +#define bM4_PORT_PCRD2_DRV0 (*((volatile unsigned int*)(0x42A79910UL))) +#define bM4_PORT_PCRD2_DRV1 (*((volatile unsigned int*)(0x42A79914UL))) +#define bM4_PORT_PCRD2_PUU (*((volatile unsigned int*)(0x42A79918UL))) +#define bM4_PORT_PCRD2_PIN (*((volatile unsigned int*)(0x42A79920UL))) +#define bM4_PORT_PCRD2_INVE (*((volatile unsigned int*)(0x42A79924UL))) +#define bM4_PORT_PCRD2_INTE (*((volatile unsigned int*)(0x42A79930UL))) +#define bM4_PORT_PCRD2_LTE (*((volatile unsigned int*)(0x42A79938UL))) +#define bM4_PORT_PCRD2_DDIS (*((volatile unsigned int*)(0x42A7993CUL))) +#define bM4_PORT_PFSRD2_FSEL0 (*((volatile unsigned int*)(0x42A79940UL))) +#define bM4_PORT_PFSRD2_FSEL1 (*((volatile unsigned int*)(0x42A79944UL))) +#define bM4_PORT_PFSRD2_FSEL2 (*((volatile unsigned int*)(0x42A79948UL))) +#define bM4_PORT_PFSRD2_FSEL3 (*((volatile unsigned int*)(0x42A7994CUL))) +#define bM4_PORT_PFSRD2_FSEL4 (*((volatile unsigned int*)(0x42A79950UL))) +#define bM4_PORT_PFSRD2_FSEL5 (*((volatile unsigned int*)(0x42A79954UL))) +#define bM4_PORT_PFSRD2_BFE (*((volatile unsigned int*)(0x42A79960UL))) +#define bM4_PORT_PCRD3_POUT (*((volatile unsigned int*)(0x42A79980UL))) +#define bM4_PORT_PCRD3_POUTE (*((volatile unsigned int*)(0x42A79984UL))) +#define bM4_PORT_PCRD3_NOD (*((volatile unsigned int*)(0x42A79988UL))) +#define bM4_PORT_PCRD3_DRV0 (*((volatile unsigned int*)(0x42A79990UL))) +#define bM4_PORT_PCRD3_DRV1 (*((volatile unsigned int*)(0x42A79994UL))) +#define bM4_PORT_PCRD3_PUU (*((volatile unsigned int*)(0x42A79998UL))) +#define bM4_PORT_PCRD3_PIN (*((volatile unsigned int*)(0x42A799A0UL))) +#define bM4_PORT_PCRD3_INVE (*((volatile unsigned int*)(0x42A799A4UL))) +#define bM4_PORT_PCRD3_INTE (*((volatile unsigned int*)(0x42A799B0UL))) +#define bM4_PORT_PCRD3_LTE (*((volatile unsigned int*)(0x42A799B8UL))) +#define bM4_PORT_PCRD3_DDIS (*((volatile unsigned int*)(0x42A799BCUL))) +#define bM4_PORT_PFSRD3_FSEL0 (*((volatile unsigned int*)(0x42A799C0UL))) +#define bM4_PORT_PFSRD3_FSEL1 (*((volatile unsigned int*)(0x42A799C4UL))) +#define bM4_PORT_PFSRD3_FSEL2 (*((volatile unsigned int*)(0x42A799C8UL))) +#define bM4_PORT_PFSRD3_FSEL3 (*((volatile unsigned int*)(0x42A799CCUL))) +#define bM4_PORT_PFSRD3_FSEL4 (*((volatile unsigned int*)(0x42A799D0UL))) +#define bM4_PORT_PFSRD3_FSEL5 (*((volatile unsigned int*)(0x42A799D4UL))) +#define bM4_PORT_PFSRD3_BFE (*((volatile unsigned int*)(0x42A799E0UL))) +#define bM4_PORT_PCRD4_POUT (*((volatile unsigned int*)(0x42A79A00UL))) +#define bM4_PORT_PCRD4_POUTE (*((volatile unsigned int*)(0x42A79A04UL))) +#define bM4_PORT_PCRD4_NOD (*((volatile unsigned int*)(0x42A79A08UL))) +#define bM4_PORT_PCRD4_DRV0 (*((volatile unsigned int*)(0x42A79A10UL))) +#define bM4_PORT_PCRD4_DRV1 (*((volatile unsigned int*)(0x42A79A14UL))) +#define bM4_PORT_PCRD4_PUU (*((volatile unsigned int*)(0x42A79A18UL))) +#define bM4_PORT_PCRD4_PIN (*((volatile unsigned int*)(0x42A79A20UL))) +#define bM4_PORT_PCRD4_INVE (*((volatile unsigned int*)(0x42A79A24UL))) +#define bM4_PORT_PCRD4_INTE (*((volatile unsigned int*)(0x42A79A30UL))) +#define bM4_PORT_PCRD4_LTE (*((volatile unsigned int*)(0x42A79A38UL))) +#define bM4_PORT_PCRD4_DDIS (*((volatile unsigned int*)(0x42A79A3CUL))) +#define bM4_PORT_PFSRD4_FSEL0 (*((volatile unsigned int*)(0x42A79A40UL))) +#define bM4_PORT_PFSRD4_FSEL1 (*((volatile unsigned int*)(0x42A79A44UL))) +#define bM4_PORT_PFSRD4_FSEL2 (*((volatile unsigned int*)(0x42A79A48UL))) +#define bM4_PORT_PFSRD4_FSEL3 (*((volatile unsigned int*)(0x42A79A4CUL))) +#define bM4_PORT_PFSRD4_FSEL4 (*((volatile unsigned int*)(0x42A79A50UL))) +#define bM4_PORT_PFSRD4_FSEL5 (*((volatile unsigned int*)(0x42A79A54UL))) +#define bM4_PORT_PFSRD4_BFE (*((volatile unsigned int*)(0x42A79A60UL))) +#define bM4_PORT_PCRD5_POUT (*((volatile unsigned int*)(0x42A79A80UL))) +#define bM4_PORT_PCRD5_POUTE (*((volatile unsigned int*)(0x42A79A84UL))) +#define bM4_PORT_PCRD5_NOD (*((volatile unsigned int*)(0x42A79A88UL))) +#define bM4_PORT_PCRD5_DRV0 (*((volatile unsigned int*)(0x42A79A90UL))) +#define bM4_PORT_PCRD5_DRV1 (*((volatile unsigned int*)(0x42A79A94UL))) +#define bM4_PORT_PCRD5_PUU (*((volatile unsigned int*)(0x42A79A98UL))) +#define bM4_PORT_PCRD5_PIN (*((volatile unsigned int*)(0x42A79AA0UL))) +#define bM4_PORT_PCRD5_INVE (*((volatile unsigned int*)(0x42A79AA4UL))) +#define bM4_PORT_PCRD5_INTE (*((volatile unsigned int*)(0x42A79AB0UL))) +#define bM4_PORT_PCRD5_LTE (*((volatile unsigned int*)(0x42A79AB8UL))) +#define bM4_PORT_PCRD5_DDIS (*((volatile unsigned int*)(0x42A79ABCUL))) +#define bM4_PORT_PFSRD5_FSEL0 (*((volatile unsigned int*)(0x42A79AC0UL))) +#define bM4_PORT_PFSRD5_FSEL1 (*((volatile unsigned int*)(0x42A79AC4UL))) +#define bM4_PORT_PFSRD5_FSEL2 (*((volatile unsigned int*)(0x42A79AC8UL))) +#define bM4_PORT_PFSRD5_FSEL3 (*((volatile unsigned int*)(0x42A79ACCUL))) +#define bM4_PORT_PFSRD5_FSEL4 (*((volatile unsigned int*)(0x42A79AD0UL))) +#define bM4_PORT_PFSRD5_FSEL5 (*((volatile unsigned int*)(0x42A79AD4UL))) +#define bM4_PORT_PFSRD5_BFE (*((volatile unsigned int*)(0x42A79AE0UL))) +#define bM4_PORT_PCRD6_POUT (*((volatile unsigned int*)(0x42A79B00UL))) +#define bM4_PORT_PCRD6_POUTE (*((volatile unsigned int*)(0x42A79B04UL))) +#define bM4_PORT_PCRD6_NOD (*((volatile unsigned int*)(0x42A79B08UL))) +#define bM4_PORT_PCRD6_DRV0 (*((volatile unsigned int*)(0x42A79B10UL))) +#define bM4_PORT_PCRD6_DRV1 (*((volatile unsigned int*)(0x42A79B14UL))) +#define bM4_PORT_PCRD6_PUU (*((volatile unsigned int*)(0x42A79B18UL))) +#define bM4_PORT_PCRD6_PIN (*((volatile unsigned int*)(0x42A79B20UL))) +#define bM4_PORT_PCRD6_INVE (*((volatile unsigned int*)(0x42A79B24UL))) +#define bM4_PORT_PCRD6_INTE (*((volatile unsigned int*)(0x42A79B30UL))) +#define bM4_PORT_PCRD6_LTE (*((volatile unsigned int*)(0x42A79B38UL))) +#define bM4_PORT_PCRD6_DDIS (*((volatile unsigned int*)(0x42A79B3CUL))) +#define bM4_PORT_PFSRD6_FSEL0 (*((volatile unsigned int*)(0x42A79B40UL))) +#define bM4_PORT_PFSRD6_FSEL1 (*((volatile unsigned int*)(0x42A79B44UL))) +#define bM4_PORT_PFSRD6_FSEL2 (*((volatile unsigned int*)(0x42A79B48UL))) +#define bM4_PORT_PFSRD6_FSEL3 (*((volatile unsigned int*)(0x42A79B4CUL))) +#define bM4_PORT_PFSRD6_FSEL4 (*((volatile unsigned int*)(0x42A79B50UL))) +#define bM4_PORT_PFSRD6_FSEL5 (*((volatile unsigned int*)(0x42A79B54UL))) +#define bM4_PORT_PFSRD6_BFE (*((volatile unsigned int*)(0x42A79B60UL))) +#define bM4_PORT_PCRD7_POUT (*((volatile unsigned int*)(0x42A79B80UL))) +#define bM4_PORT_PCRD7_POUTE (*((volatile unsigned int*)(0x42A79B84UL))) +#define bM4_PORT_PCRD7_NOD (*((volatile unsigned int*)(0x42A79B88UL))) +#define bM4_PORT_PCRD7_DRV0 (*((volatile unsigned int*)(0x42A79B90UL))) +#define bM4_PORT_PCRD7_DRV1 (*((volatile unsigned int*)(0x42A79B94UL))) +#define bM4_PORT_PCRD7_PUU (*((volatile unsigned int*)(0x42A79B98UL))) +#define bM4_PORT_PCRD7_PIN (*((volatile unsigned int*)(0x42A79BA0UL))) +#define bM4_PORT_PCRD7_INVE (*((volatile unsigned int*)(0x42A79BA4UL))) +#define bM4_PORT_PCRD7_INTE (*((volatile unsigned int*)(0x42A79BB0UL))) +#define bM4_PORT_PCRD7_LTE (*((volatile unsigned int*)(0x42A79BB8UL))) +#define bM4_PORT_PCRD7_DDIS (*((volatile unsigned int*)(0x42A79BBCUL))) +#define bM4_PORT_PFSRD7_FSEL0 (*((volatile unsigned int*)(0x42A79BC0UL))) +#define bM4_PORT_PFSRD7_FSEL1 (*((volatile unsigned int*)(0x42A79BC4UL))) +#define bM4_PORT_PFSRD7_FSEL2 (*((volatile unsigned int*)(0x42A79BC8UL))) +#define bM4_PORT_PFSRD7_FSEL3 (*((volatile unsigned int*)(0x42A79BCCUL))) +#define bM4_PORT_PFSRD7_FSEL4 (*((volatile unsigned int*)(0x42A79BD0UL))) +#define bM4_PORT_PFSRD7_FSEL5 (*((volatile unsigned int*)(0x42A79BD4UL))) +#define bM4_PORT_PFSRD7_BFE (*((volatile unsigned int*)(0x42A79BE0UL))) +#define bM4_PORT_PCRD8_POUT (*((volatile unsigned int*)(0x42A79C00UL))) +#define bM4_PORT_PCRD8_POUTE (*((volatile unsigned int*)(0x42A79C04UL))) +#define bM4_PORT_PCRD8_NOD (*((volatile unsigned int*)(0x42A79C08UL))) +#define bM4_PORT_PCRD8_DRV0 (*((volatile unsigned int*)(0x42A79C10UL))) +#define bM4_PORT_PCRD8_DRV1 (*((volatile unsigned int*)(0x42A79C14UL))) +#define bM4_PORT_PCRD8_PUU (*((volatile unsigned int*)(0x42A79C18UL))) +#define bM4_PORT_PCRD8_PIN (*((volatile unsigned int*)(0x42A79C20UL))) +#define bM4_PORT_PCRD8_INVE (*((volatile unsigned int*)(0x42A79C24UL))) +#define bM4_PORT_PCRD8_INTE (*((volatile unsigned int*)(0x42A79C30UL))) +#define bM4_PORT_PCRD8_LTE (*((volatile unsigned int*)(0x42A79C38UL))) +#define bM4_PORT_PCRD8_DDIS (*((volatile unsigned int*)(0x42A79C3CUL))) +#define bM4_PORT_PFSRD8_FSEL0 (*((volatile unsigned int*)(0x42A79C40UL))) +#define bM4_PORT_PFSRD8_FSEL1 (*((volatile unsigned int*)(0x42A79C44UL))) +#define bM4_PORT_PFSRD8_FSEL2 (*((volatile unsigned int*)(0x42A79C48UL))) +#define bM4_PORT_PFSRD8_FSEL3 (*((volatile unsigned int*)(0x42A79C4CUL))) +#define bM4_PORT_PFSRD8_FSEL4 (*((volatile unsigned int*)(0x42A79C50UL))) +#define bM4_PORT_PFSRD8_FSEL5 (*((volatile unsigned int*)(0x42A79C54UL))) +#define bM4_PORT_PFSRD8_BFE (*((volatile unsigned int*)(0x42A79C60UL))) +#define bM4_PORT_PCRD9_POUT (*((volatile unsigned int*)(0x42A79C80UL))) +#define bM4_PORT_PCRD9_POUTE (*((volatile unsigned int*)(0x42A79C84UL))) +#define bM4_PORT_PCRD9_NOD (*((volatile unsigned int*)(0x42A79C88UL))) +#define bM4_PORT_PCRD9_DRV0 (*((volatile unsigned int*)(0x42A79C90UL))) +#define bM4_PORT_PCRD9_DRV1 (*((volatile unsigned int*)(0x42A79C94UL))) +#define bM4_PORT_PCRD9_PUU (*((volatile unsigned int*)(0x42A79C98UL))) +#define bM4_PORT_PCRD9_PIN (*((volatile unsigned int*)(0x42A79CA0UL))) +#define bM4_PORT_PCRD9_INVE (*((volatile unsigned int*)(0x42A79CA4UL))) +#define bM4_PORT_PCRD9_INTE (*((volatile unsigned int*)(0x42A79CB0UL))) +#define bM4_PORT_PCRD9_LTE (*((volatile unsigned int*)(0x42A79CB8UL))) +#define bM4_PORT_PCRD9_DDIS (*((volatile unsigned int*)(0x42A79CBCUL))) +#define bM4_PORT_PFSRD9_FSEL0 (*((volatile unsigned int*)(0x42A79CC0UL))) +#define bM4_PORT_PFSRD9_FSEL1 (*((volatile unsigned int*)(0x42A79CC4UL))) +#define bM4_PORT_PFSRD9_FSEL2 (*((volatile unsigned int*)(0x42A79CC8UL))) +#define bM4_PORT_PFSRD9_FSEL3 (*((volatile unsigned int*)(0x42A79CCCUL))) +#define bM4_PORT_PFSRD9_FSEL4 (*((volatile unsigned int*)(0x42A79CD0UL))) +#define bM4_PORT_PFSRD9_FSEL5 (*((volatile unsigned int*)(0x42A79CD4UL))) +#define bM4_PORT_PFSRD9_BFE (*((volatile unsigned int*)(0x42A79CE0UL))) +#define bM4_PORT_PCRD10_POUT (*((volatile unsigned int*)(0x42A79D00UL))) +#define bM4_PORT_PCRD10_POUTE (*((volatile unsigned int*)(0x42A79D04UL))) +#define bM4_PORT_PCRD10_NOD (*((volatile unsigned int*)(0x42A79D08UL))) +#define bM4_PORT_PCRD10_DRV0 (*((volatile unsigned int*)(0x42A79D10UL))) +#define bM4_PORT_PCRD10_DRV1 (*((volatile unsigned int*)(0x42A79D14UL))) +#define bM4_PORT_PCRD10_PUU (*((volatile unsigned int*)(0x42A79D18UL))) +#define bM4_PORT_PCRD10_PIN (*((volatile unsigned int*)(0x42A79D20UL))) +#define bM4_PORT_PCRD10_INVE (*((volatile unsigned int*)(0x42A79D24UL))) +#define bM4_PORT_PCRD10_INTE (*((volatile unsigned int*)(0x42A79D30UL))) +#define bM4_PORT_PCRD10_LTE (*((volatile unsigned int*)(0x42A79D38UL))) +#define bM4_PORT_PCRD10_DDIS (*((volatile unsigned int*)(0x42A79D3CUL))) +#define bM4_PORT_PFSRD10_FSEL0 (*((volatile unsigned int*)(0x42A79D40UL))) +#define bM4_PORT_PFSRD10_FSEL1 (*((volatile unsigned int*)(0x42A79D44UL))) +#define bM4_PORT_PFSRD10_FSEL2 (*((volatile unsigned int*)(0x42A79D48UL))) +#define bM4_PORT_PFSRD10_FSEL3 (*((volatile unsigned int*)(0x42A79D4CUL))) +#define bM4_PORT_PFSRD10_FSEL4 (*((volatile unsigned int*)(0x42A79D50UL))) +#define bM4_PORT_PFSRD10_FSEL5 (*((volatile unsigned int*)(0x42A79D54UL))) +#define bM4_PORT_PFSRD10_BFE (*((volatile unsigned int*)(0x42A79D60UL))) +#define bM4_PORT_PCRD11_POUT (*((volatile unsigned int*)(0x42A79D80UL))) +#define bM4_PORT_PCRD11_POUTE (*((volatile unsigned int*)(0x42A79D84UL))) +#define bM4_PORT_PCRD11_NOD (*((volatile unsigned int*)(0x42A79D88UL))) +#define bM4_PORT_PCRD11_DRV0 (*((volatile unsigned int*)(0x42A79D90UL))) +#define bM4_PORT_PCRD11_DRV1 (*((volatile unsigned int*)(0x42A79D94UL))) +#define bM4_PORT_PCRD11_PUU (*((volatile unsigned int*)(0x42A79D98UL))) +#define bM4_PORT_PCRD11_PIN (*((volatile unsigned int*)(0x42A79DA0UL))) +#define bM4_PORT_PCRD11_INVE (*((volatile unsigned int*)(0x42A79DA4UL))) +#define bM4_PORT_PCRD11_INTE (*((volatile unsigned int*)(0x42A79DB0UL))) +#define bM4_PORT_PCRD11_LTE (*((volatile unsigned int*)(0x42A79DB8UL))) +#define bM4_PORT_PCRD11_DDIS (*((volatile unsigned int*)(0x42A79DBCUL))) +#define bM4_PORT_PFSRD11_FSEL0 (*((volatile unsigned int*)(0x42A79DC0UL))) +#define bM4_PORT_PFSRD11_FSEL1 (*((volatile unsigned int*)(0x42A79DC4UL))) +#define bM4_PORT_PFSRD11_FSEL2 (*((volatile unsigned int*)(0x42A79DC8UL))) +#define bM4_PORT_PFSRD11_FSEL3 (*((volatile unsigned int*)(0x42A79DCCUL))) +#define bM4_PORT_PFSRD11_FSEL4 (*((volatile unsigned int*)(0x42A79DD0UL))) +#define bM4_PORT_PFSRD11_FSEL5 (*((volatile unsigned int*)(0x42A79DD4UL))) +#define bM4_PORT_PFSRD11_BFE (*((volatile unsigned int*)(0x42A79DE0UL))) +#define bM4_PORT_PCRD12_POUT (*((volatile unsigned int*)(0x42A79E00UL))) +#define bM4_PORT_PCRD12_POUTE (*((volatile unsigned int*)(0x42A79E04UL))) +#define bM4_PORT_PCRD12_NOD (*((volatile unsigned int*)(0x42A79E08UL))) +#define bM4_PORT_PCRD12_DRV0 (*((volatile unsigned int*)(0x42A79E10UL))) +#define bM4_PORT_PCRD12_DRV1 (*((volatile unsigned int*)(0x42A79E14UL))) +#define bM4_PORT_PCRD12_PUU (*((volatile unsigned int*)(0x42A79E18UL))) +#define bM4_PORT_PCRD12_PIN (*((volatile unsigned int*)(0x42A79E20UL))) +#define bM4_PORT_PCRD12_INVE (*((volatile unsigned int*)(0x42A79E24UL))) +#define bM4_PORT_PCRD12_INTE (*((volatile unsigned int*)(0x42A79E30UL))) +#define bM4_PORT_PCRD12_LTE (*((volatile unsigned int*)(0x42A79E38UL))) +#define bM4_PORT_PCRD12_DDIS (*((volatile unsigned int*)(0x42A79E3CUL))) +#define bM4_PORT_PFSRD12_FSEL0 (*((volatile unsigned int*)(0x42A79E40UL))) +#define bM4_PORT_PFSRD12_FSEL1 (*((volatile unsigned int*)(0x42A79E44UL))) +#define bM4_PORT_PFSRD12_FSEL2 (*((volatile unsigned int*)(0x42A79E48UL))) +#define bM4_PORT_PFSRD12_FSEL3 (*((volatile unsigned int*)(0x42A79E4CUL))) +#define bM4_PORT_PFSRD12_FSEL4 (*((volatile unsigned int*)(0x42A79E50UL))) +#define bM4_PORT_PFSRD12_FSEL5 (*((volatile unsigned int*)(0x42A79E54UL))) +#define bM4_PORT_PFSRD12_BFE (*((volatile unsigned int*)(0x42A79E60UL))) +#define bM4_PORT_PCRD13_POUT (*((volatile unsigned int*)(0x42A79E80UL))) +#define bM4_PORT_PCRD13_POUTE (*((volatile unsigned int*)(0x42A79E84UL))) +#define bM4_PORT_PCRD13_NOD (*((volatile unsigned int*)(0x42A79E88UL))) +#define bM4_PORT_PCRD13_DRV0 (*((volatile unsigned int*)(0x42A79E90UL))) +#define bM4_PORT_PCRD13_DRV1 (*((volatile unsigned int*)(0x42A79E94UL))) +#define bM4_PORT_PCRD13_PUU (*((volatile unsigned int*)(0x42A79E98UL))) +#define bM4_PORT_PCRD13_PIN (*((volatile unsigned int*)(0x42A79EA0UL))) +#define bM4_PORT_PCRD13_INVE (*((volatile unsigned int*)(0x42A79EA4UL))) +#define bM4_PORT_PCRD13_INTE (*((volatile unsigned int*)(0x42A79EB0UL))) +#define bM4_PORT_PCRD13_LTE (*((volatile unsigned int*)(0x42A79EB8UL))) +#define bM4_PORT_PCRD13_DDIS (*((volatile unsigned int*)(0x42A79EBCUL))) +#define bM4_PORT_PFSRD13_FSEL0 (*((volatile unsigned int*)(0x42A79EC0UL))) +#define bM4_PORT_PFSRD13_FSEL1 (*((volatile unsigned int*)(0x42A79EC4UL))) +#define bM4_PORT_PFSRD13_FSEL2 (*((volatile unsigned int*)(0x42A79EC8UL))) +#define bM4_PORT_PFSRD13_FSEL3 (*((volatile unsigned int*)(0x42A79ECCUL))) +#define bM4_PORT_PFSRD13_FSEL4 (*((volatile unsigned int*)(0x42A79ED0UL))) +#define bM4_PORT_PFSRD13_FSEL5 (*((volatile unsigned int*)(0x42A79ED4UL))) +#define bM4_PORT_PFSRD13_BFE (*((volatile unsigned int*)(0x42A79EE0UL))) +#define bM4_PORT_PCRD14_POUT (*((volatile unsigned int*)(0x42A79F00UL))) +#define bM4_PORT_PCRD14_POUTE (*((volatile unsigned int*)(0x42A79F04UL))) +#define bM4_PORT_PCRD14_NOD (*((volatile unsigned int*)(0x42A79F08UL))) +#define bM4_PORT_PCRD14_DRV0 (*((volatile unsigned int*)(0x42A79F10UL))) +#define bM4_PORT_PCRD14_DRV1 (*((volatile unsigned int*)(0x42A79F14UL))) +#define bM4_PORT_PCRD14_PUU (*((volatile unsigned int*)(0x42A79F18UL))) +#define bM4_PORT_PCRD14_PIN (*((volatile unsigned int*)(0x42A79F20UL))) +#define bM4_PORT_PCRD14_INVE (*((volatile unsigned int*)(0x42A79F24UL))) +#define bM4_PORT_PCRD14_INTE (*((volatile unsigned int*)(0x42A79F30UL))) +#define bM4_PORT_PCRD14_LTE (*((volatile unsigned int*)(0x42A79F38UL))) +#define bM4_PORT_PCRD14_DDIS (*((volatile unsigned int*)(0x42A79F3CUL))) +#define bM4_PORT_PFSRD14_FSEL0 (*((volatile unsigned int*)(0x42A79F40UL))) +#define bM4_PORT_PFSRD14_FSEL1 (*((volatile unsigned int*)(0x42A79F44UL))) +#define bM4_PORT_PFSRD14_FSEL2 (*((volatile unsigned int*)(0x42A79F48UL))) +#define bM4_PORT_PFSRD14_FSEL3 (*((volatile unsigned int*)(0x42A79F4CUL))) +#define bM4_PORT_PFSRD14_FSEL4 (*((volatile unsigned int*)(0x42A79F50UL))) +#define bM4_PORT_PFSRD14_FSEL5 (*((volatile unsigned int*)(0x42A79F54UL))) +#define bM4_PORT_PFSRD14_BFE (*((volatile unsigned int*)(0x42A79F60UL))) +#define bM4_PORT_PCRD15_POUT (*((volatile unsigned int*)(0x42A79F80UL))) +#define bM4_PORT_PCRD15_POUTE (*((volatile unsigned int*)(0x42A79F84UL))) +#define bM4_PORT_PCRD15_NOD (*((volatile unsigned int*)(0x42A79F88UL))) +#define bM4_PORT_PCRD15_DRV0 (*((volatile unsigned int*)(0x42A79F90UL))) +#define bM4_PORT_PCRD15_DRV1 (*((volatile unsigned int*)(0x42A79F94UL))) +#define bM4_PORT_PCRD15_PUU (*((volatile unsigned int*)(0x42A79F98UL))) +#define bM4_PORT_PCRD15_PIN (*((volatile unsigned int*)(0x42A79FA0UL))) +#define bM4_PORT_PCRD15_INVE (*((volatile unsigned int*)(0x42A79FA4UL))) +#define bM4_PORT_PCRD15_INTE (*((volatile unsigned int*)(0x42A79FB0UL))) +#define bM4_PORT_PCRD15_LTE (*((volatile unsigned int*)(0x42A79FB8UL))) +#define bM4_PORT_PCRD15_DDIS (*((volatile unsigned int*)(0x42A79FBCUL))) +#define bM4_PORT_PFSRD15_FSEL0 (*((volatile unsigned int*)(0x42A79FC0UL))) +#define bM4_PORT_PFSRD15_FSEL1 (*((volatile unsigned int*)(0x42A79FC4UL))) +#define bM4_PORT_PFSRD15_FSEL2 (*((volatile unsigned int*)(0x42A79FC8UL))) +#define bM4_PORT_PFSRD15_FSEL3 (*((volatile unsigned int*)(0x42A79FCCUL))) +#define bM4_PORT_PFSRD15_FSEL4 (*((volatile unsigned int*)(0x42A79FD0UL))) +#define bM4_PORT_PFSRD15_FSEL5 (*((volatile unsigned int*)(0x42A79FD4UL))) +#define bM4_PORT_PFSRD15_BFE (*((volatile unsigned int*)(0x42A79FE0UL))) +#define bM4_PORT_PCRE0_POUT (*((volatile unsigned int*)(0x42A7A000UL))) +#define bM4_PORT_PCRE0_POUTE (*((volatile unsigned int*)(0x42A7A004UL))) +#define bM4_PORT_PCRE0_NOD (*((volatile unsigned int*)(0x42A7A008UL))) +#define bM4_PORT_PCRE0_DRV0 (*((volatile unsigned int*)(0x42A7A010UL))) +#define bM4_PORT_PCRE0_DRV1 (*((volatile unsigned int*)(0x42A7A014UL))) +#define bM4_PORT_PCRE0_PUU (*((volatile unsigned int*)(0x42A7A018UL))) +#define bM4_PORT_PCRE0_PIN (*((volatile unsigned int*)(0x42A7A020UL))) +#define bM4_PORT_PCRE0_INVE (*((volatile unsigned int*)(0x42A7A024UL))) +#define bM4_PORT_PCRE0_INTE (*((volatile unsigned int*)(0x42A7A030UL))) +#define bM4_PORT_PCRE0_LTE (*((volatile unsigned int*)(0x42A7A038UL))) +#define bM4_PORT_PCRE0_DDIS (*((volatile unsigned int*)(0x42A7A03CUL))) +#define bM4_PORT_PFSRE0_FSEL0 (*((volatile unsigned int*)(0x42A7A040UL))) +#define bM4_PORT_PFSRE0_FSEL1 (*((volatile unsigned int*)(0x42A7A044UL))) +#define bM4_PORT_PFSRE0_FSEL2 (*((volatile unsigned int*)(0x42A7A048UL))) +#define bM4_PORT_PFSRE0_FSEL3 (*((volatile unsigned int*)(0x42A7A04CUL))) +#define bM4_PORT_PFSRE0_FSEL4 (*((volatile unsigned int*)(0x42A7A050UL))) +#define bM4_PORT_PFSRE0_FSEL5 (*((volatile unsigned int*)(0x42A7A054UL))) +#define bM4_PORT_PFSRE0_BFE (*((volatile unsigned int*)(0x42A7A060UL))) +#define bM4_PORT_PCRE1_POUT (*((volatile unsigned int*)(0x42A7A080UL))) +#define bM4_PORT_PCRE1_POUTE (*((volatile unsigned int*)(0x42A7A084UL))) +#define bM4_PORT_PCRE1_NOD (*((volatile unsigned int*)(0x42A7A088UL))) +#define bM4_PORT_PCRE1_DRV0 (*((volatile unsigned int*)(0x42A7A090UL))) +#define bM4_PORT_PCRE1_DRV1 (*((volatile unsigned int*)(0x42A7A094UL))) +#define bM4_PORT_PCRE1_PUU (*((volatile unsigned int*)(0x42A7A098UL))) +#define bM4_PORT_PCRE1_PIN (*((volatile unsigned int*)(0x42A7A0A0UL))) +#define bM4_PORT_PCRE1_INVE (*((volatile unsigned int*)(0x42A7A0A4UL))) +#define bM4_PORT_PCRE1_INTE (*((volatile unsigned int*)(0x42A7A0B0UL))) +#define bM4_PORT_PCRE1_LTE (*((volatile unsigned int*)(0x42A7A0B8UL))) +#define bM4_PORT_PCRE1_DDIS (*((volatile unsigned int*)(0x42A7A0BCUL))) +#define bM4_PORT_PFSRE1_FSEL0 (*((volatile unsigned int*)(0x42A7A0C0UL))) +#define bM4_PORT_PFSRE1_FSEL1 (*((volatile unsigned int*)(0x42A7A0C4UL))) +#define bM4_PORT_PFSRE1_FSEL2 (*((volatile unsigned int*)(0x42A7A0C8UL))) +#define bM4_PORT_PFSRE1_FSEL3 (*((volatile unsigned int*)(0x42A7A0CCUL))) +#define bM4_PORT_PFSRE1_FSEL4 (*((volatile unsigned int*)(0x42A7A0D0UL))) +#define bM4_PORT_PFSRE1_FSEL5 (*((volatile unsigned int*)(0x42A7A0D4UL))) +#define bM4_PORT_PFSRE1_BFE (*((volatile unsigned int*)(0x42A7A0E0UL))) +#define bM4_PORT_PCRE2_POUT (*((volatile unsigned int*)(0x42A7A100UL))) +#define bM4_PORT_PCRE2_POUTE (*((volatile unsigned int*)(0x42A7A104UL))) +#define bM4_PORT_PCRE2_NOD (*((volatile unsigned int*)(0x42A7A108UL))) +#define bM4_PORT_PCRE2_DRV0 (*((volatile unsigned int*)(0x42A7A110UL))) +#define bM4_PORT_PCRE2_DRV1 (*((volatile unsigned int*)(0x42A7A114UL))) +#define bM4_PORT_PCRE2_PUU (*((volatile unsigned int*)(0x42A7A118UL))) +#define bM4_PORT_PCRE2_PIN (*((volatile unsigned int*)(0x42A7A120UL))) +#define bM4_PORT_PCRE2_INVE (*((volatile unsigned int*)(0x42A7A124UL))) +#define bM4_PORT_PCRE2_INTE (*((volatile unsigned int*)(0x42A7A130UL))) +#define bM4_PORT_PCRE2_LTE (*((volatile unsigned int*)(0x42A7A138UL))) +#define bM4_PORT_PCRE2_DDIS (*((volatile unsigned int*)(0x42A7A13CUL))) +#define bM4_PORT_PFSRE2_FSEL0 (*((volatile unsigned int*)(0x42A7A140UL))) +#define bM4_PORT_PFSRE2_FSEL1 (*((volatile unsigned int*)(0x42A7A144UL))) +#define bM4_PORT_PFSRE2_FSEL2 (*((volatile unsigned int*)(0x42A7A148UL))) +#define bM4_PORT_PFSRE2_FSEL3 (*((volatile unsigned int*)(0x42A7A14CUL))) +#define bM4_PORT_PFSRE2_FSEL4 (*((volatile unsigned int*)(0x42A7A150UL))) +#define bM4_PORT_PFSRE2_FSEL5 (*((volatile unsigned int*)(0x42A7A154UL))) +#define bM4_PORT_PFSRE2_BFE (*((volatile unsigned int*)(0x42A7A160UL))) +#define bM4_PORT_PCRE3_POUT (*((volatile unsigned int*)(0x42A7A180UL))) +#define bM4_PORT_PCRE3_POUTE (*((volatile unsigned int*)(0x42A7A184UL))) +#define bM4_PORT_PCRE3_NOD (*((volatile unsigned int*)(0x42A7A188UL))) +#define bM4_PORT_PCRE3_DRV0 (*((volatile unsigned int*)(0x42A7A190UL))) +#define bM4_PORT_PCRE3_DRV1 (*((volatile unsigned int*)(0x42A7A194UL))) +#define bM4_PORT_PCRE3_PUU (*((volatile unsigned int*)(0x42A7A198UL))) +#define bM4_PORT_PCRE3_PIN (*((volatile unsigned int*)(0x42A7A1A0UL))) +#define bM4_PORT_PCRE3_INVE (*((volatile unsigned int*)(0x42A7A1A4UL))) +#define bM4_PORT_PCRE3_INTE (*((volatile unsigned int*)(0x42A7A1B0UL))) +#define bM4_PORT_PCRE3_LTE (*((volatile unsigned int*)(0x42A7A1B8UL))) +#define bM4_PORT_PCRE3_DDIS (*((volatile unsigned int*)(0x42A7A1BCUL))) +#define bM4_PORT_PFSRE3_FSEL0 (*((volatile unsigned int*)(0x42A7A1C0UL))) +#define bM4_PORT_PFSRE3_FSEL1 (*((volatile unsigned int*)(0x42A7A1C4UL))) +#define bM4_PORT_PFSRE3_FSEL2 (*((volatile unsigned int*)(0x42A7A1C8UL))) +#define bM4_PORT_PFSRE3_FSEL3 (*((volatile unsigned int*)(0x42A7A1CCUL))) +#define bM4_PORT_PFSRE3_FSEL4 (*((volatile unsigned int*)(0x42A7A1D0UL))) +#define bM4_PORT_PFSRE3_FSEL5 (*((volatile unsigned int*)(0x42A7A1D4UL))) +#define bM4_PORT_PFSRE3_BFE (*((volatile unsigned int*)(0x42A7A1E0UL))) +#define bM4_PORT_PCRE4_POUT (*((volatile unsigned int*)(0x42A7A200UL))) +#define bM4_PORT_PCRE4_POUTE (*((volatile unsigned int*)(0x42A7A204UL))) +#define bM4_PORT_PCRE4_NOD (*((volatile unsigned int*)(0x42A7A208UL))) +#define bM4_PORT_PCRE4_DRV0 (*((volatile unsigned int*)(0x42A7A210UL))) +#define bM4_PORT_PCRE4_DRV1 (*((volatile unsigned int*)(0x42A7A214UL))) +#define bM4_PORT_PCRE4_PUU (*((volatile unsigned int*)(0x42A7A218UL))) +#define bM4_PORT_PCRE4_PIN (*((volatile unsigned int*)(0x42A7A220UL))) +#define bM4_PORT_PCRE4_INVE (*((volatile unsigned int*)(0x42A7A224UL))) +#define bM4_PORT_PCRE4_INTE (*((volatile unsigned int*)(0x42A7A230UL))) +#define bM4_PORT_PCRE4_LTE (*((volatile unsigned int*)(0x42A7A238UL))) +#define bM4_PORT_PCRE4_DDIS (*((volatile unsigned int*)(0x42A7A23CUL))) +#define bM4_PORT_PFSRE4_FSEL0 (*((volatile unsigned int*)(0x42A7A240UL))) +#define bM4_PORT_PFSRE4_FSEL1 (*((volatile unsigned int*)(0x42A7A244UL))) +#define bM4_PORT_PFSRE4_FSEL2 (*((volatile unsigned int*)(0x42A7A248UL))) +#define bM4_PORT_PFSRE4_FSEL3 (*((volatile unsigned int*)(0x42A7A24CUL))) +#define bM4_PORT_PFSRE4_FSEL4 (*((volatile unsigned int*)(0x42A7A250UL))) +#define bM4_PORT_PFSRE4_FSEL5 (*((volatile unsigned int*)(0x42A7A254UL))) +#define bM4_PORT_PFSRE4_BFE (*((volatile unsigned int*)(0x42A7A260UL))) +#define bM4_PORT_PCRE5_POUT (*((volatile unsigned int*)(0x42A7A280UL))) +#define bM4_PORT_PCRE5_POUTE (*((volatile unsigned int*)(0x42A7A284UL))) +#define bM4_PORT_PCRE5_NOD (*((volatile unsigned int*)(0x42A7A288UL))) +#define bM4_PORT_PCRE5_DRV0 (*((volatile unsigned int*)(0x42A7A290UL))) +#define bM4_PORT_PCRE5_DRV1 (*((volatile unsigned int*)(0x42A7A294UL))) +#define bM4_PORT_PCRE5_PUU (*((volatile unsigned int*)(0x42A7A298UL))) +#define bM4_PORT_PCRE5_PIN (*((volatile unsigned int*)(0x42A7A2A0UL))) +#define bM4_PORT_PCRE5_INVE (*((volatile unsigned int*)(0x42A7A2A4UL))) +#define bM4_PORT_PCRE5_INTE (*((volatile unsigned int*)(0x42A7A2B0UL))) +#define bM4_PORT_PCRE5_LTE (*((volatile unsigned int*)(0x42A7A2B8UL))) +#define bM4_PORT_PCRE5_DDIS (*((volatile unsigned int*)(0x42A7A2BCUL))) +#define bM4_PORT_PFSRE5_FSEL0 (*((volatile unsigned int*)(0x42A7A2C0UL))) +#define bM4_PORT_PFSRE5_FSEL1 (*((volatile unsigned int*)(0x42A7A2C4UL))) +#define bM4_PORT_PFSRE5_FSEL2 (*((volatile unsigned int*)(0x42A7A2C8UL))) +#define bM4_PORT_PFSRE5_FSEL3 (*((volatile unsigned int*)(0x42A7A2CCUL))) +#define bM4_PORT_PFSRE5_FSEL4 (*((volatile unsigned int*)(0x42A7A2D0UL))) +#define bM4_PORT_PFSRE5_FSEL5 (*((volatile unsigned int*)(0x42A7A2D4UL))) +#define bM4_PORT_PFSRE5_BFE (*((volatile unsigned int*)(0x42A7A2E0UL))) +#define bM4_PORT_PCRE6_POUT (*((volatile unsigned int*)(0x42A7A300UL))) +#define bM4_PORT_PCRE6_POUTE (*((volatile unsigned int*)(0x42A7A304UL))) +#define bM4_PORT_PCRE6_NOD (*((volatile unsigned int*)(0x42A7A308UL))) +#define bM4_PORT_PCRE6_DRV0 (*((volatile unsigned int*)(0x42A7A310UL))) +#define bM4_PORT_PCRE6_DRV1 (*((volatile unsigned int*)(0x42A7A314UL))) +#define bM4_PORT_PCRE6_PUU (*((volatile unsigned int*)(0x42A7A318UL))) +#define bM4_PORT_PCRE6_PIN (*((volatile unsigned int*)(0x42A7A320UL))) +#define bM4_PORT_PCRE6_INVE (*((volatile unsigned int*)(0x42A7A324UL))) +#define bM4_PORT_PCRE6_INTE (*((volatile unsigned int*)(0x42A7A330UL))) +#define bM4_PORT_PCRE6_LTE (*((volatile unsigned int*)(0x42A7A338UL))) +#define bM4_PORT_PCRE6_DDIS (*((volatile unsigned int*)(0x42A7A33CUL))) +#define bM4_PORT_PFSRE6_FSEL0 (*((volatile unsigned int*)(0x42A7A340UL))) +#define bM4_PORT_PFSRE6_FSEL1 (*((volatile unsigned int*)(0x42A7A344UL))) +#define bM4_PORT_PFSRE6_FSEL2 (*((volatile unsigned int*)(0x42A7A348UL))) +#define bM4_PORT_PFSRE6_FSEL3 (*((volatile unsigned int*)(0x42A7A34CUL))) +#define bM4_PORT_PFSRE6_FSEL4 (*((volatile unsigned int*)(0x42A7A350UL))) +#define bM4_PORT_PFSRE6_FSEL5 (*((volatile unsigned int*)(0x42A7A354UL))) +#define bM4_PORT_PFSRE6_BFE (*((volatile unsigned int*)(0x42A7A360UL))) +#define bM4_PORT_PCRE7_POUT (*((volatile unsigned int*)(0x42A7A380UL))) +#define bM4_PORT_PCRE7_POUTE (*((volatile unsigned int*)(0x42A7A384UL))) +#define bM4_PORT_PCRE7_NOD (*((volatile unsigned int*)(0x42A7A388UL))) +#define bM4_PORT_PCRE7_DRV0 (*((volatile unsigned int*)(0x42A7A390UL))) +#define bM4_PORT_PCRE7_DRV1 (*((volatile unsigned int*)(0x42A7A394UL))) +#define bM4_PORT_PCRE7_PUU (*((volatile unsigned int*)(0x42A7A398UL))) +#define bM4_PORT_PCRE7_PIN (*((volatile unsigned int*)(0x42A7A3A0UL))) +#define bM4_PORT_PCRE7_INVE (*((volatile unsigned int*)(0x42A7A3A4UL))) +#define bM4_PORT_PCRE7_INTE (*((volatile unsigned int*)(0x42A7A3B0UL))) +#define bM4_PORT_PCRE7_LTE (*((volatile unsigned int*)(0x42A7A3B8UL))) +#define bM4_PORT_PCRE7_DDIS (*((volatile unsigned int*)(0x42A7A3BCUL))) +#define bM4_PORT_PFSRE7_FSEL0 (*((volatile unsigned int*)(0x42A7A3C0UL))) +#define bM4_PORT_PFSRE7_FSEL1 (*((volatile unsigned int*)(0x42A7A3C4UL))) +#define bM4_PORT_PFSRE7_FSEL2 (*((volatile unsigned int*)(0x42A7A3C8UL))) +#define bM4_PORT_PFSRE7_FSEL3 (*((volatile unsigned int*)(0x42A7A3CCUL))) +#define bM4_PORT_PFSRE7_FSEL4 (*((volatile unsigned int*)(0x42A7A3D0UL))) +#define bM4_PORT_PFSRE7_FSEL5 (*((volatile unsigned int*)(0x42A7A3D4UL))) +#define bM4_PORT_PFSRE7_BFE (*((volatile unsigned int*)(0x42A7A3E0UL))) +#define bM4_PORT_PCRE8_POUT (*((volatile unsigned int*)(0x42A7A400UL))) +#define bM4_PORT_PCRE8_POUTE (*((volatile unsigned int*)(0x42A7A404UL))) +#define bM4_PORT_PCRE8_NOD (*((volatile unsigned int*)(0x42A7A408UL))) +#define bM4_PORT_PCRE8_DRV0 (*((volatile unsigned int*)(0x42A7A410UL))) +#define bM4_PORT_PCRE8_DRV1 (*((volatile unsigned int*)(0x42A7A414UL))) +#define bM4_PORT_PCRE8_PUU (*((volatile unsigned int*)(0x42A7A418UL))) +#define bM4_PORT_PCRE8_PIN (*((volatile unsigned int*)(0x42A7A420UL))) +#define bM4_PORT_PCRE8_INVE (*((volatile unsigned int*)(0x42A7A424UL))) +#define bM4_PORT_PCRE8_INTE (*((volatile unsigned int*)(0x42A7A430UL))) +#define bM4_PORT_PCRE8_LTE (*((volatile unsigned int*)(0x42A7A438UL))) +#define bM4_PORT_PCRE8_DDIS (*((volatile unsigned int*)(0x42A7A43CUL))) +#define bM4_PORT_PFSRE8_FSEL0 (*((volatile unsigned int*)(0x42A7A440UL))) +#define bM4_PORT_PFSRE8_FSEL1 (*((volatile unsigned int*)(0x42A7A444UL))) +#define bM4_PORT_PFSRE8_FSEL2 (*((volatile unsigned int*)(0x42A7A448UL))) +#define bM4_PORT_PFSRE8_FSEL3 (*((volatile unsigned int*)(0x42A7A44CUL))) +#define bM4_PORT_PFSRE8_FSEL4 (*((volatile unsigned int*)(0x42A7A450UL))) +#define bM4_PORT_PFSRE8_FSEL5 (*((volatile unsigned int*)(0x42A7A454UL))) +#define bM4_PORT_PFSRE8_BFE (*((volatile unsigned int*)(0x42A7A460UL))) +#define bM4_PORT_PCRE9_POUT (*((volatile unsigned int*)(0x42A7A480UL))) +#define bM4_PORT_PCRE9_POUTE (*((volatile unsigned int*)(0x42A7A484UL))) +#define bM4_PORT_PCRE9_NOD (*((volatile unsigned int*)(0x42A7A488UL))) +#define bM4_PORT_PCRE9_DRV0 (*((volatile unsigned int*)(0x42A7A490UL))) +#define bM4_PORT_PCRE9_DRV1 (*((volatile unsigned int*)(0x42A7A494UL))) +#define bM4_PORT_PCRE9_PUU (*((volatile unsigned int*)(0x42A7A498UL))) +#define bM4_PORT_PCRE9_PIN (*((volatile unsigned int*)(0x42A7A4A0UL))) +#define bM4_PORT_PCRE9_INVE (*((volatile unsigned int*)(0x42A7A4A4UL))) +#define bM4_PORT_PCRE9_INTE (*((volatile unsigned int*)(0x42A7A4B0UL))) +#define bM4_PORT_PCRE9_LTE (*((volatile unsigned int*)(0x42A7A4B8UL))) +#define bM4_PORT_PCRE9_DDIS (*((volatile unsigned int*)(0x42A7A4BCUL))) +#define bM4_PORT_PFSRE9_FSEL0 (*((volatile unsigned int*)(0x42A7A4C0UL))) +#define bM4_PORT_PFSRE9_FSEL1 (*((volatile unsigned int*)(0x42A7A4C4UL))) +#define bM4_PORT_PFSRE9_FSEL2 (*((volatile unsigned int*)(0x42A7A4C8UL))) +#define bM4_PORT_PFSRE9_FSEL3 (*((volatile unsigned int*)(0x42A7A4CCUL))) +#define bM4_PORT_PFSRE9_FSEL4 (*((volatile unsigned int*)(0x42A7A4D0UL))) +#define bM4_PORT_PFSRE9_FSEL5 (*((volatile unsigned int*)(0x42A7A4D4UL))) +#define bM4_PORT_PFSRE9_BFE (*((volatile unsigned int*)(0x42A7A4E0UL))) +#define bM4_PORT_PCRE10_POUT (*((volatile unsigned int*)(0x42A7A500UL))) +#define bM4_PORT_PCRE10_POUTE (*((volatile unsigned int*)(0x42A7A504UL))) +#define bM4_PORT_PCRE10_NOD (*((volatile unsigned int*)(0x42A7A508UL))) +#define bM4_PORT_PCRE10_DRV0 (*((volatile unsigned int*)(0x42A7A510UL))) +#define bM4_PORT_PCRE10_DRV1 (*((volatile unsigned int*)(0x42A7A514UL))) +#define bM4_PORT_PCRE10_PUU (*((volatile unsigned int*)(0x42A7A518UL))) +#define bM4_PORT_PCRE10_PIN (*((volatile unsigned int*)(0x42A7A520UL))) +#define bM4_PORT_PCRE10_INVE (*((volatile unsigned int*)(0x42A7A524UL))) +#define bM4_PORT_PCRE10_INTE (*((volatile unsigned int*)(0x42A7A530UL))) +#define bM4_PORT_PCRE10_LTE (*((volatile unsigned int*)(0x42A7A538UL))) +#define bM4_PORT_PCRE10_DDIS (*((volatile unsigned int*)(0x42A7A53CUL))) +#define bM4_PORT_PFSRE10_FSEL0 (*((volatile unsigned int*)(0x42A7A540UL))) +#define bM4_PORT_PFSRE10_FSEL1 (*((volatile unsigned int*)(0x42A7A544UL))) +#define bM4_PORT_PFSRE10_FSEL2 (*((volatile unsigned int*)(0x42A7A548UL))) +#define bM4_PORT_PFSRE10_FSEL3 (*((volatile unsigned int*)(0x42A7A54CUL))) +#define bM4_PORT_PFSRE10_FSEL4 (*((volatile unsigned int*)(0x42A7A550UL))) +#define bM4_PORT_PFSRE10_FSEL5 (*((volatile unsigned int*)(0x42A7A554UL))) +#define bM4_PORT_PFSRE10_BFE (*((volatile unsigned int*)(0x42A7A560UL))) +#define bM4_PORT_PCRE11_POUT (*((volatile unsigned int*)(0x42A7A580UL))) +#define bM4_PORT_PCRE11_POUTE (*((volatile unsigned int*)(0x42A7A584UL))) +#define bM4_PORT_PCRE11_NOD (*((volatile unsigned int*)(0x42A7A588UL))) +#define bM4_PORT_PCRE11_DRV0 (*((volatile unsigned int*)(0x42A7A590UL))) +#define bM4_PORT_PCRE11_DRV1 (*((volatile unsigned int*)(0x42A7A594UL))) +#define bM4_PORT_PCRE11_PUU (*((volatile unsigned int*)(0x42A7A598UL))) +#define bM4_PORT_PCRE11_PIN (*((volatile unsigned int*)(0x42A7A5A0UL))) +#define bM4_PORT_PCRE11_INVE (*((volatile unsigned int*)(0x42A7A5A4UL))) +#define bM4_PORT_PCRE11_INTE (*((volatile unsigned int*)(0x42A7A5B0UL))) +#define bM4_PORT_PCRE11_LTE (*((volatile unsigned int*)(0x42A7A5B8UL))) +#define bM4_PORT_PCRE11_DDIS (*((volatile unsigned int*)(0x42A7A5BCUL))) +#define bM4_PORT_PFSRE11_FSEL0 (*((volatile unsigned int*)(0x42A7A5C0UL))) +#define bM4_PORT_PFSRE11_FSEL1 (*((volatile unsigned int*)(0x42A7A5C4UL))) +#define bM4_PORT_PFSRE11_FSEL2 (*((volatile unsigned int*)(0x42A7A5C8UL))) +#define bM4_PORT_PFSRE11_FSEL3 (*((volatile unsigned int*)(0x42A7A5CCUL))) +#define bM4_PORT_PFSRE11_FSEL4 (*((volatile unsigned int*)(0x42A7A5D0UL))) +#define bM4_PORT_PFSRE11_FSEL5 (*((volatile unsigned int*)(0x42A7A5D4UL))) +#define bM4_PORT_PFSRE11_BFE (*((volatile unsigned int*)(0x42A7A5E0UL))) +#define bM4_PORT_PCRE12_POUT (*((volatile unsigned int*)(0x42A7A600UL))) +#define bM4_PORT_PCRE12_POUTE (*((volatile unsigned int*)(0x42A7A604UL))) +#define bM4_PORT_PCRE12_NOD (*((volatile unsigned int*)(0x42A7A608UL))) +#define bM4_PORT_PCRE12_DRV0 (*((volatile unsigned int*)(0x42A7A610UL))) +#define bM4_PORT_PCRE12_DRV1 (*((volatile unsigned int*)(0x42A7A614UL))) +#define bM4_PORT_PCRE12_PUU (*((volatile unsigned int*)(0x42A7A618UL))) +#define bM4_PORT_PCRE12_PIN (*((volatile unsigned int*)(0x42A7A620UL))) +#define bM4_PORT_PCRE12_INVE (*((volatile unsigned int*)(0x42A7A624UL))) +#define bM4_PORT_PCRE12_INTE (*((volatile unsigned int*)(0x42A7A630UL))) +#define bM4_PORT_PCRE12_LTE (*((volatile unsigned int*)(0x42A7A638UL))) +#define bM4_PORT_PCRE12_DDIS (*((volatile unsigned int*)(0x42A7A63CUL))) +#define bM4_PORT_PFSRE12_FSEL0 (*((volatile unsigned int*)(0x42A7A640UL))) +#define bM4_PORT_PFSRE12_FSEL1 (*((volatile unsigned int*)(0x42A7A644UL))) +#define bM4_PORT_PFSRE12_FSEL2 (*((volatile unsigned int*)(0x42A7A648UL))) +#define bM4_PORT_PFSRE12_FSEL3 (*((volatile unsigned int*)(0x42A7A64CUL))) +#define bM4_PORT_PFSRE12_FSEL4 (*((volatile unsigned int*)(0x42A7A650UL))) +#define bM4_PORT_PFSRE12_FSEL5 (*((volatile unsigned int*)(0x42A7A654UL))) +#define bM4_PORT_PFSRE12_BFE (*((volatile unsigned int*)(0x42A7A660UL))) +#define bM4_PORT_PCRE13_POUT (*((volatile unsigned int*)(0x42A7A680UL))) +#define bM4_PORT_PCRE13_POUTE (*((volatile unsigned int*)(0x42A7A684UL))) +#define bM4_PORT_PCRE13_NOD (*((volatile unsigned int*)(0x42A7A688UL))) +#define bM4_PORT_PCRE13_DRV0 (*((volatile unsigned int*)(0x42A7A690UL))) +#define bM4_PORT_PCRE13_DRV1 (*((volatile unsigned int*)(0x42A7A694UL))) +#define bM4_PORT_PCRE13_PUU (*((volatile unsigned int*)(0x42A7A698UL))) +#define bM4_PORT_PCRE13_PIN (*((volatile unsigned int*)(0x42A7A6A0UL))) +#define bM4_PORT_PCRE13_INVE (*((volatile unsigned int*)(0x42A7A6A4UL))) +#define bM4_PORT_PCRE13_INTE (*((volatile unsigned int*)(0x42A7A6B0UL))) +#define bM4_PORT_PCRE13_LTE (*((volatile unsigned int*)(0x42A7A6B8UL))) +#define bM4_PORT_PCRE13_DDIS (*((volatile unsigned int*)(0x42A7A6BCUL))) +#define bM4_PORT_PFSRE13_FSEL0 (*((volatile unsigned int*)(0x42A7A6C0UL))) +#define bM4_PORT_PFSRE13_FSEL1 (*((volatile unsigned int*)(0x42A7A6C4UL))) +#define bM4_PORT_PFSRE13_FSEL2 (*((volatile unsigned int*)(0x42A7A6C8UL))) +#define bM4_PORT_PFSRE13_FSEL3 (*((volatile unsigned int*)(0x42A7A6CCUL))) +#define bM4_PORT_PFSRE13_FSEL4 (*((volatile unsigned int*)(0x42A7A6D0UL))) +#define bM4_PORT_PFSRE13_FSEL5 (*((volatile unsigned int*)(0x42A7A6D4UL))) +#define bM4_PORT_PFSRE13_BFE (*((volatile unsigned int*)(0x42A7A6E0UL))) +#define bM4_PORT_PCRE14_POUT (*((volatile unsigned int*)(0x42A7A700UL))) +#define bM4_PORT_PCRE14_POUTE (*((volatile unsigned int*)(0x42A7A704UL))) +#define bM4_PORT_PCRE14_NOD (*((volatile unsigned int*)(0x42A7A708UL))) +#define bM4_PORT_PCRE14_DRV0 (*((volatile unsigned int*)(0x42A7A710UL))) +#define bM4_PORT_PCRE14_DRV1 (*((volatile unsigned int*)(0x42A7A714UL))) +#define bM4_PORT_PCRE14_PUU (*((volatile unsigned int*)(0x42A7A718UL))) +#define bM4_PORT_PCRE14_PIN (*((volatile unsigned int*)(0x42A7A720UL))) +#define bM4_PORT_PCRE14_INVE (*((volatile unsigned int*)(0x42A7A724UL))) +#define bM4_PORT_PCRE14_INTE (*((volatile unsigned int*)(0x42A7A730UL))) +#define bM4_PORT_PCRE14_LTE (*((volatile unsigned int*)(0x42A7A738UL))) +#define bM4_PORT_PCRE14_DDIS (*((volatile unsigned int*)(0x42A7A73CUL))) +#define bM4_PORT_PFSRE14_FSEL0 (*((volatile unsigned int*)(0x42A7A740UL))) +#define bM4_PORT_PFSRE14_FSEL1 (*((volatile unsigned int*)(0x42A7A744UL))) +#define bM4_PORT_PFSRE14_FSEL2 (*((volatile unsigned int*)(0x42A7A748UL))) +#define bM4_PORT_PFSRE14_FSEL3 (*((volatile unsigned int*)(0x42A7A74CUL))) +#define bM4_PORT_PFSRE14_FSEL4 (*((volatile unsigned int*)(0x42A7A750UL))) +#define bM4_PORT_PFSRE14_FSEL5 (*((volatile unsigned int*)(0x42A7A754UL))) +#define bM4_PORT_PFSRE14_BFE (*((volatile unsigned int*)(0x42A7A760UL))) +#define bM4_PORT_PCRE15_POUT (*((volatile unsigned int*)(0x42A7A780UL))) +#define bM4_PORT_PCRE15_POUTE (*((volatile unsigned int*)(0x42A7A784UL))) +#define bM4_PORT_PCRE15_NOD (*((volatile unsigned int*)(0x42A7A788UL))) +#define bM4_PORT_PCRE15_DRV0 (*((volatile unsigned int*)(0x42A7A790UL))) +#define bM4_PORT_PCRE15_DRV1 (*((volatile unsigned int*)(0x42A7A794UL))) +#define bM4_PORT_PCRE15_PUU (*((volatile unsigned int*)(0x42A7A798UL))) +#define bM4_PORT_PCRE15_PIN (*((volatile unsigned int*)(0x42A7A7A0UL))) +#define bM4_PORT_PCRE15_INVE (*((volatile unsigned int*)(0x42A7A7A4UL))) +#define bM4_PORT_PCRE15_INTE (*((volatile unsigned int*)(0x42A7A7B0UL))) +#define bM4_PORT_PCRE15_LTE (*((volatile unsigned int*)(0x42A7A7B8UL))) +#define bM4_PORT_PCRE15_DDIS (*((volatile unsigned int*)(0x42A7A7BCUL))) +#define bM4_PORT_PFSRE15_FSEL0 (*((volatile unsigned int*)(0x42A7A7C0UL))) +#define bM4_PORT_PFSRE15_FSEL1 (*((volatile unsigned int*)(0x42A7A7C4UL))) +#define bM4_PORT_PFSRE15_FSEL2 (*((volatile unsigned int*)(0x42A7A7C8UL))) +#define bM4_PORT_PFSRE15_FSEL3 (*((volatile unsigned int*)(0x42A7A7CCUL))) +#define bM4_PORT_PFSRE15_FSEL4 (*((volatile unsigned int*)(0x42A7A7D0UL))) +#define bM4_PORT_PFSRE15_FSEL5 (*((volatile unsigned int*)(0x42A7A7D4UL))) +#define bM4_PORT_PFSRE15_BFE (*((volatile unsigned int*)(0x42A7A7E0UL))) +#define bM4_PORT_PCRH0_POUT (*((volatile unsigned int*)(0x42A7A800UL))) +#define bM4_PORT_PCRH0_POUTE (*((volatile unsigned int*)(0x42A7A804UL))) +#define bM4_PORT_PCRH0_NOD (*((volatile unsigned int*)(0x42A7A808UL))) +#define bM4_PORT_PCRH0_DRV0 (*((volatile unsigned int*)(0x42A7A810UL))) +#define bM4_PORT_PCRH0_DRV1 (*((volatile unsigned int*)(0x42A7A814UL))) +#define bM4_PORT_PCRH0_PUU (*((volatile unsigned int*)(0x42A7A818UL))) +#define bM4_PORT_PCRH0_PIN (*((volatile unsigned int*)(0x42A7A820UL))) +#define bM4_PORT_PCRH0_INVE (*((volatile unsigned int*)(0x42A7A824UL))) +#define bM4_PORT_PCRH0_INTE (*((volatile unsigned int*)(0x42A7A830UL))) +#define bM4_PORT_PCRH0_LTE (*((volatile unsigned int*)(0x42A7A838UL))) +#define bM4_PORT_PCRH0_DDIS (*((volatile unsigned int*)(0x42A7A83CUL))) +#define bM4_PORT_PFSRH0_FSEL0 (*((volatile unsigned int*)(0x42A7A840UL))) +#define bM4_PORT_PFSRH0_FSEL1 (*((volatile unsigned int*)(0x42A7A844UL))) +#define bM4_PORT_PFSRH0_FSEL2 (*((volatile unsigned int*)(0x42A7A848UL))) +#define bM4_PORT_PFSRH0_FSEL3 (*((volatile unsigned int*)(0x42A7A84CUL))) +#define bM4_PORT_PFSRH0_FSEL4 (*((volatile unsigned int*)(0x42A7A850UL))) +#define bM4_PORT_PFSRH0_FSEL5 (*((volatile unsigned int*)(0x42A7A854UL))) +#define bM4_PORT_PFSRH0_BFE (*((volatile unsigned int*)(0x42A7A860UL))) +#define bM4_PORT_PCRH1_POUT (*((volatile unsigned int*)(0x42A7A880UL))) +#define bM4_PORT_PCRH1_POUTE (*((volatile unsigned int*)(0x42A7A884UL))) +#define bM4_PORT_PCRH1_NOD (*((volatile unsigned int*)(0x42A7A888UL))) +#define bM4_PORT_PCRH1_DRV0 (*((volatile unsigned int*)(0x42A7A890UL))) +#define bM4_PORT_PCRH1_DRV1 (*((volatile unsigned int*)(0x42A7A894UL))) +#define bM4_PORT_PCRH1_PUU (*((volatile unsigned int*)(0x42A7A898UL))) +#define bM4_PORT_PCRH1_PIN (*((volatile unsigned int*)(0x42A7A8A0UL))) +#define bM4_PORT_PCRH1_INVE (*((volatile unsigned int*)(0x42A7A8A4UL))) +#define bM4_PORT_PCRH1_INTE (*((volatile unsigned int*)(0x42A7A8B0UL))) +#define bM4_PORT_PCRH1_LTE (*((volatile unsigned int*)(0x42A7A8B8UL))) +#define bM4_PORT_PCRH1_DDIS (*((volatile unsigned int*)(0x42A7A8BCUL))) +#define bM4_PORT_PFSRH1_FSEL0 (*((volatile unsigned int*)(0x42A7A8C0UL))) +#define bM4_PORT_PFSRH1_FSEL1 (*((volatile unsigned int*)(0x42A7A8C4UL))) +#define bM4_PORT_PFSRH1_FSEL2 (*((volatile unsigned int*)(0x42A7A8C8UL))) +#define bM4_PORT_PFSRH1_FSEL3 (*((volatile unsigned int*)(0x42A7A8CCUL))) +#define bM4_PORT_PFSRH1_FSEL4 (*((volatile unsigned int*)(0x42A7A8D0UL))) +#define bM4_PORT_PFSRH1_FSEL5 (*((volatile unsigned int*)(0x42A7A8D4UL))) +#define bM4_PORT_PFSRH1_BFE (*((volatile unsigned int*)(0x42A7A8E0UL))) +#define bM4_PORT_PCRH2_POUT (*((volatile unsigned int*)(0x42A7A900UL))) +#define bM4_PORT_PCRH2_POUTE (*((volatile unsigned int*)(0x42A7A904UL))) +#define bM4_PORT_PCRH2_NOD (*((volatile unsigned int*)(0x42A7A908UL))) +#define bM4_PORT_PCRH2_DRV0 (*((volatile unsigned int*)(0x42A7A910UL))) +#define bM4_PORT_PCRH2_DRV1 (*((volatile unsigned int*)(0x42A7A914UL))) +#define bM4_PORT_PCRH2_PUU (*((volatile unsigned int*)(0x42A7A918UL))) +#define bM4_PORT_PCRH2_PIN (*((volatile unsigned int*)(0x42A7A920UL))) +#define bM4_PORT_PCRH2_INVE (*((volatile unsigned int*)(0x42A7A924UL))) +#define bM4_PORT_PCRH2_INTE (*((volatile unsigned int*)(0x42A7A930UL))) +#define bM4_PORT_PCRH2_LTE (*((volatile unsigned int*)(0x42A7A938UL))) +#define bM4_PORT_PCRH2_DDIS (*((volatile unsigned int*)(0x42A7A93CUL))) +#define bM4_PORT_PFSRH2_FSEL0 (*((volatile unsigned int*)(0x42A7A940UL))) +#define bM4_PORT_PFSRH2_FSEL1 (*((volatile unsigned int*)(0x42A7A944UL))) +#define bM4_PORT_PFSRH2_FSEL2 (*((volatile unsigned int*)(0x42A7A948UL))) +#define bM4_PORT_PFSRH2_FSEL3 (*((volatile unsigned int*)(0x42A7A94CUL))) +#define bM4_PORT_PFSRH2_FSEL4 (*((volatile unsigned int*)(0x42A7A950UL))) +#define bM4_PORT_PFSRH2_FSEL5 (*((volatile unsigned int*)(0x42A7A954UL))) +#define bM4_PORT_PFSRH2_BFE (*((volatile unsigned int*)(0x42A7A960UL))) +#define bM4_RTC_CR0_RESET (*((volatile unsigned int*)(0x42980000UL))) +#define bM4_RTC_CR1_PRDS0 (*((volatile unsigned int*)(0x42980080UL))) +#define bM4_RTC_CR1_PRDS1 (*((volatile unsigned int*)(0x42980084UL))) +#define bM4_RTC_CR1_PRDS2 (*((volatile unsigned int*)(0x42980088UL))) +#define bM4_RTC_CR1_AMPM (*((volatile unsigned int*)(0x4298008CUL))) +#define bM4_RTC_CR1_ALMFCLR (*((volatile unsigned int*)(0x42980090UL))) +#define bM4_RTC_CR1_ONEHZOE (*((volatile unsigned int*)(0x42980094UL))) +#define bM4_RTC_CR1_ONEHZSEL (*((volatile unsigned int*)(0x42980098UL))) +#define bM4_RTC_CR1_START (*((volatile unsigned int*)(0x4298009CUL))) +#define bM4_RTC_CR2_RWREQ (*((volatile unsigned int*)(0x42980100UL))) +#define bM4_RTC_CR2_RWEN (*((volatile unsigned int*)(0x42980104UL))) +#define bM4_RTC_CR2_ALMF (*((volatile unsigned int*)(0x4298010CUL))) +#define bM4_RTC_CR2_PRDIE (*((volatile unsigned int*)(0x42980114UL))) +#define bM4_RTC_CR2_ALMIE (*((volatile unsigned int*)(0x42980118UL))) +#define bM4_RTC_CR2_ALME (*((volatile unsigned int*)(0x4298011CUL))) +#define bM4_RTC_CR3_LRCEN (*((volatile unsigned int*)(0x42980190UL))) +#define bM4_RTC_CR3_RCKSEL (*((volatile unsigned int*)(0x4298019CUL))) +#define bM4_RTC_SEC_SECU0 (*((volatile unsigned int*)(0x42980200UL))) +#define bM4_RTC_SEC_SECU1 (*((volatile unsigned int*)(0x42980204UL))) +#define bM4_RTC_SEC_SECU2 (*((volatile unsigned int*)(0x42980208UL))) +#define bM4_RTC_SEC_SECU3 (*((volatile unsigned int*)(0x4298020CUL))) +#define bM4_RTC_SEC_SECD0 (*((volatile unsigned int*)(0x42980210UL))) +#define bM4_RTC_SEC_SECD1 (*((volatile unsigned int*)(0x42980214UL))) +#define bM4_RTC_SEC_SECD2 (*((volatile unsigned int*)(0x42980218UL))) +#define bM4_RTC_MIN_MINU0 (*((volatile unsigned int*)(0x42980280UL))) +#define bM4_RTC_MIN_MINU1 (*((volatile unsigned int*)(0x42980284UL))) +#define bM4_RTC_MIN_MINU2 (*((volatile unsigned int*)(0x42980288UL))) +#define bM4_RTC_MIN_MINU3 (*((volatile unsigned int*)(0x4298028CUL))) +#define bM4_RTC_MIN_MIND0 (*((volatile unsigned int*)(0x42980290UL))) +#define bM4_RTC_MIN_MIND1 (*((volatile unsigned int*)(0x42980294UL))) +#define bM4_RTC_MIN_MIND2 (*((volatile unsigned int*)(0x42980298UL))) +#define bM4_RTC_HOUR_HOURU0 (*((volatile unsigned int*)(0x42980300UL))) +#define bM4_RTC_HOUR_HOURU1 (*((volatile unsigned int*)(0x42980304UL))) +#define bM4_RTC_HOUR_HOURU2 (*((volatile unsigned int*)(0x42980308UL))) +#define bM4_RTC_HOUR_HOURU3 (*((volatile unsigned int*)(0x4298030CUL))) +#define bM4_RTC_HOUR_HOURD0 (*((volatile unsigned int*)(0x42980310UL))) +#define bM4_RTC_HOUR_HOURD1 (*((volatile unsigned int*)(0x42980314UL))) +#define bM4_RTC_WEEK_WEEK0 (*((volatile unsigned int*)(0x42980380UL))) +#define bM4_RTC_WEEK_WEEK1 (*((volatile unsigned int*)(0x42980384UL))) +#define bM4_RTC_WEEK_WEEK2 (*((volatile unsigned int*)(0x42980388UL))) +#define bM4_RTC_DAY_DAYU0 (*((volatile unsigned int*)(0x42980400UL))) +#define bM4_RTC_DAY_DAYU1 (*((volatile unsigned int*)(0x42980404UL))) +#define bM4_RTC_DAY_DAYU2 (*((volatile unsigned int*)(0x42980408UL))) +#define bM4_RTC_DAY_DAYU3 (*((volatile unsigned int*)(0x4298040CUL))) +#define bM4_RTC_DAY_DAYD0 (*((volatile unsigned int*)(0x42980410UL))) +#define bM4_RTC_DAY_DAYD1 (*((volatile unsigned int*)(0x42980414UL))) +#define bM4_RTC_MON_MON0 (*((volatile unsigned int*)(0x42980480UL))) +#define bM4_RTC_MON_MON1 (*((volatile unsigned int*)(0x42980484UL))) +#define bM4_RTC_MON_MON2 (*((volatile unsigned int*)(0x42980488UL))) +#define bM4_RTC_MON_MON3 (*((volatile unsigned int*)(0x4298048CUL))) +#define bM4_RTC_MON_MON4 (*((volatile unsigned int*)(0x42980490UL))) +#define bM4_RTC_YEAR_YEARU0 (*((volatile unsigned int*)(0x42980500UL))) +#define bM4_RTC_YEAR_YEARU1 (*((volatile unsigned int*)(0x42980504UL))) +#define bM4_RTC_YEAR_YEARU2 (*((volatile unsigned int*)(0x42980508UL))) +#define bM4_RTC_YEAR_YEARU3 (*((volatile unsigned int*)(0x4298050CUL))) +#define bM4_RTC_YEAR_YEARD0 (*((volatile unsigned int*)(0x42980510UL))) +#define bM4_RTC_YEAR_YEARD1 (*((volatile unsigned int*)(0x42980514UL))) +#define bM4_RTC_YEAR_YEARD2 (*((volatile unsigned int*)(0x42980518UL))) +#define bM4_RTC_YEAR_YEARD3 (*((volatile unsigned int*)(0x4298051CUL))) +#define bM4_RTC_ALMMIN_ALMMINU0 (*((volatile unsigned int*)(0x42980580UL))) +#define bM4_RTC_ALMMIN_ALMMINU1 (*((volatile unsigned int*)(0x42980584UL))) +#define bM4_RTC_ALMMIN_ALMMINU2 (*((volatile unsigned int*)(0x42980588UL))) +#define bM4_RTC_ALMMIN_ALMMINU3 (*((volatile unsigned int*)(0x4298058CUL))) +#define bM4_RTC_ALMMIN_ALMMIND0 (*((volatile unsigned int*)(0x42980590UL))) +#define bM4_RTC_ALMMIN_ALMMIND1 (*((volatile unsigned int*)(0x42980594UL))) +#define bM4_RTC_ALMMIN_ALMMIND2 (*((volatile unsigned int*)(0x42980598UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU0 (*((volatile unsigned int*)(0x42980600UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU1 (*((volatile unsigned int*)(0x42980604UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU2 (*((volatile unsigned int*)(0x42980608UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU3 (*((volatile unsigned int*)(0x4298060CUL))) +#define bM4_RTC_ALMHOUR_ALMHOURD0 (*((volatile unsigned int*)(0x42980610UL))) +#define bM4_RTC_ALMHOUR_ALMHOURD1 (*((volatile unsigned int*)(0x42980614UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK0 (*((volatile unsigned int*)(0x42980680UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK1 (*((volatile unsigned int*)(0x42980684UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK2 (*((volatile unsigned int*)(0x42980688UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK3 (*((volatile unsigned int*)(0x4298068CUL))) +#define bM4_RTC_ALMWEEK_ALMWEEK4 (*((volatile unsigned int*)(0x42980690UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK5 (*((volatile unsigned int*)(0x42980694UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK6 (*((volatile unsigned int*)(0x42980698UL))) +#define bM4_RTC_ERRCRH_COMP8 (*((volatile unsigned int*)(0x42980700UL))) +#define bM4_RTC_ERRCRH_COMPEN (*((volatile unsigned int*)(0x4298071CUL))) +#define bM4_RTC_ERRCRL_COMP0 (*((volatile unsigned int*)(0x42980780UL))) +#define bM4_RTC_ERRCRL_COMP1 (*((volatile unsigned int*)(0x42980784UL))) +#define bM4_RTC_ERRCRL_COMP2 (*((volatile unsigned int*)(0x42980788UL))) +#define bM4_RTC_ERRCRL_COMP3 (*((volatile unsigned int*)(0x4298078CUL))) +#define bM4_RTC_ERRCRL_COMP4 (*((volatile unsigned int*)(0x42980790UL))) +#define bM4_RTC_ERRCRL_COMP5 (*((volatile unsigned int*)(0x42980794UL))) +#define bM4_RTC_ERRCRL_COMP6 (*((volatile unsigned int*)(0x42980798UL))) +#define bM4_RTC_ERRCRL_COMP7 (*((volatile unsigned int*)(0x4298079CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS0 (*((volatile unsigned int*)(0x42DF8080UL))) +#define bM4_SDIOC1_BLKSIZE_TBS1 (*((volatile unsigned int*)(0x42DF8084UL))) +#define bM4_SDIOC1_BLKSIZE_TBS2 (*((volatile unsigned int*)(0x42DF8088UL))) +#define bM4_SDIOC1_BLKSIZE_TBS3 (*((volatile unsigned int*)(0x42DF808CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS4 (*((volatile unsigned int*)(0x42DF8090UL))) +#define bM4_SDIOC1_BLKSIZE_TBS5 (*((volatile unsigned int*)(0x42DF8094UL))) +#define bM4_SDIOC1_BLKSIZE_TBS6 (*((volatile unsigned int*)(0x42DF8098UL))) +#define bM4_SDIOC1_BLKSIZE_TBS7 (*((volatile unsigned int*)(0x42DF809CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS8 (*((volatile unsigned int*)(0x42DF80A0UL))) +#define bM4_SDIOC1_BLKSIZE_TBS9 (*((volatile unsigned int*)(0x42DF80A4UL))) +#define bM4_SDIOC1_BLKSIZE_TBS10 (*((volatile unsigned int*)(0x42DF80A8UL))) +#define bM4_SDIOC1_BLKSIZE_TBS11 (*((volatile unsigned int*)(0x42DF80ACUL))) +#define bM4_SDIOC1_TRANSMODE_BCE (*((volatile unsigned int*)(0x42DF8184UL))) +#define bM4_SDIOC1_TRANSMODE_ATCEN0 (*((volatile unsigned int*)(0x42DF8188UL))) +#define bM4_SDIOC1_TRANSMODE_ATCEN1 (*((volatile unsigned int*)(0x42DF818CUL))) +#define bM4_SDIOC1_TRANSMODE_DDIR (*((volatile unsigned int*)(0x42DF8190UL))) +#define bM4_SDIOC1_TRANSMODE_MULB (*((volatile unsigned int*)(0x42DF8194UL))) +#define bM4_SDIOC1_CMD_RESTYP0 (*((volatile unsigned int*)(0x42DF81C0UL))) +#define bM4_SDIOC1_CMD_RESTYP1 (*((volatile unsigned int*)(0x42DF81C4UL))) +#define bM4_SDIOC1_CMD_CCE (*((volatile unsigned int*)(0x42DF81CCUL))) +#define bM4_SDIOC1_CMD_ICE (*((volatile unsigned int*)(0x42DF81D0UL))) +#define bM4_SDIOC1_CMD_DAT (*((volatile unsigned int*)(0x42DF81D4UL))) +#define bM4_SDIOC1_CMD_TYP0 (*((volatile unsigned int*)(0x42DF81D8UL))) +#define bM4_SDIOC1_CMD_TYP1 (*((volatile unsigned int*)(0x42DF81DCUL))) +#define bM4_SDIOC1_CMD_IDX0 (*((volatile unsigned int*)(0x42DF81E0UL))) +#define bM4_SDIOC1_CMD_IDX1 (*((volatile unsigned int*)(0x42DF81E4UL))) +#define bM4_SDIOC1_CMD_IDX2 (*((volatile unsigned int*)(0x42DF81E8UL))) +#define bM4_SDIOC1_CMD_IDX3 (*((volatile unsigned int*)(0x42DF81ECUL))) +#define bM4_SDIOC1_CMD_IDX4 (*((volatile unsigned int*)(0x42DF81F0UL))) +#define bM4_SDIOC1_CMD_IDX5 (*((volatile unsigned int*)(0x42DF81F4UL))) +#define bM4_SDIOC1_PSTAT_CIC (*((volatile unsigned int*)(0x42DF8480UL))) +#define bM4_SDIOC1_PSTAT_CID (*((volatile unsigned int*)(0x42DF8484UL))) +#define bM4_SDIOC1_PSTAT_DA (*((volatile unsigned int*)(0x42DF8488UL))) +#define bM4_SDIOC1_PSTAT_WTA (*((volatile unsigned int*)(0x42DF84A0UL))) +#define bM4_SDIOC1_PSTAT_RTA (*((volatile unsigned int*)(0x42DF84A4UL))) +#define bM4_SDIOC1_PSTAT_BWE (*((volatile unsigned int*)(0x42DF84A8UL))) +#define bM4_SDIOC1_PSTAT_BRE (*((volatile unsigned int*)(0x42DF84ACUL))) +#define bM4_SDIOC1_PSTAT_CIN (*((volatile unsigned int*)(0x42DF84C0UL))) +#define bM4_SDIOC1_PSTAT_CSS (*((volatile unsigned int*)(0x42DF84C4UL))) +#define bM4_SDIOC1_PSTAT_CDL (*((volatile unsigned int*)(0x42DF84C8UL))) +#define bM4_SDIOC1_PSTAT_WPL (*((volatile unsigned int*)(0x42DF84CCUL))) +#define bM4_SDIOC1_PSTAT_DATL0 (*((volatile unsigned int*)(0x42DF84D0UL))) +#define bM4_SDIOC1_PSTAT_DATL1 (*((volatile unsigned int*)(0x42DF84D4UL))) +#define bM4_SDIOC1_PSTAT_DATL2 (*((volatile unsigned int*)(0x42DF84D8UL))) +#define bM4_SDIOC1_PSTAT_DATL3 (*((volatile unsigned int*)(0x42DF84DCUL))) +#define bM4_SDIOC1_PSTAT_CMDL (*((volatile unsigned int*)(0x42DF84E0UL))) +#define bM4_SDIOC1_HOSTCON_DW (*((volatile unsigned int*)(0x42DF8504UL))) +#define bM4_SDIOC1_HOSTCON_HSEN (*((volatile unsigned int*)(0x42DF8508UL))) +#define bM4_SDIOC1_HOSTCON_EXDW (*((volatile unsigned int*)(0x42DF8514UL))) +#define bM4_SDIOC1_HOSTCON_CDTL (*((volatile unsigned int*)(0x42DF8518UL))) +#define bM4_SDIOC1_HOSTCON_CDSS (*((volatile unsigned int*)(0x42DF851CUL))) +#define bM4_SDIOC1_PWRCON_PWON (*((volatile unsigned int*)(0x42DF8520UL))) +#define bM4_SDIOC1_BLKGPCON_SABGR (*((volatile unsigned int*)(0x42DF8540UL))) +#define bM4_SDIOC1_BLKGPCON_CR (*((volatile unsigned int*)(0x42DF8544UL))) +#define bM4_SDIOC1_BLKGPCON_RWC (*((volatile unsigned int*)(0x42DF8548UL))) +#define bM4_SDIOC1_BLKGPCON_IABG (*((volatile unsigned int*)(0x42DF854CUL))) +#define bM4_SDIOC1_CLKCON_ICE (*((volatile unsigned int*)(0x42DF8580UL))) +#define bM4_SDIOC1_CLKCON_CE (*((volatile unsigned int*)(0x42DF8588UL))) +#define bM4_SDIOC1_CLKCON_FS0 (*((volatile unsigned int*)(0x42DF85A0UL))) +#define bM4_SDIOC1_CLKCON_FS1 (*((volatile unsigned int*)(0x42DF85A4UL))) +#define bM4_SDIOC1_CLKCON_FS2 (*((volatile unsigned int*)(0x42DF85A8UL))) +#define bM4_SDIOC1_CLKCON_FS3 (*((volatile unsigned int*)(0x42DF85ACUL))) +#define bM4_SDIOC1_CLKCON_FS4 (*((volatile unsigned int*)(0x42DF85B0UL))) +#define bM4_SDIOC1_CLKCON_FS5 (*((volatile unsigned int*)(0x42DF85B4UL))) +#define bM4_SDIOC1_CLKCON_FS6 (*((volatile unsigned int*)(0x42DF85B8UL))) +#define bM4_SDIOC1_CLKCON_FS7 (*((volatile unsigned int*)(0x42DF85BCUL))) +#define bM4_SDIOC1_TOUTCON_DTO0 (*((volatile unsigned int*)(0x42DF85C0UL))) +#define bM4_SDIOC1_TOUTCON_DTO1 (*((volatile unsigned int*)(0x42DF85C4UL))) +#define bM4_SDIOC1_TOUTCON_DTO2 (*((volatile unsigned int*)(0x42DF85C8UL))) +#define bM4_SDIOC1_TOUTCON_DTO3 (*((volatile unsigned int*)(0x42DF85CCUL))) +#define bM4_SDIOC1_SFTRST_RSTA (*((volatile unsigned int*)(0x42DF85E0UL))) +#define bM4_SDIOC1_SFTRST_RSTC (*((volatile unsigned int*)(0x42DF85E4UL))) +#define bM4_SDIOC1_SFTRST_RSTD (*((volatile unsigned int*)(0x42DF85E8UL))) +#define bM4_SDIOC1_NORINTST_CC (*((volatile unsigned int*)(0x42DF8600UL))) +#define bM4_SDIOC1_NORINTST_TC (*((volatile unsigned int*)(0x42DF8604UL))) +#define bM4_SDIOC1_NORINTST_BGE (*((volatile unsigned int*)(0x42DF8608UL))) +#define bM4_SDIOC1_NORINTST_BWR (*((volatile unsigned int*)(0x42DF8610UL))) +#define bM4_SDIOC1_NORINTST_BRR (*((volatile unsigned int*)(0x42DF8614UL))) +#define bM4_SDIOC1_NORINTST_CIST (*((volatile unsigned int*)(0x42DF8618UL))) +#define bM4_SDIOC1_NORINTST_CRM (*((volatile unsigned int*)(0x42DF861CUL))) +#define bM4_SDIOC1_NORINTST_CINT (*((volatile unsigned int*)(0x42DF8620UL))) +#define bM4_SDIOC1_NORINTST_EI (*((volatile unsigned int*)(0x42DF863CUL))) +#define bM4_SDIOC1_ERRINTST_CTOE (*((volatile unsigned int*)(0x42DF8640UL))) +#define bM4_SDIOC1_ERRINTST_CCE (*((volatile unsigned int*)(0x42DF8644UL))) +#define bM4_SDIOC1_ERRINTST_CEBE (*((volatile unsigned int*)(0x42DF8648UL))) +#define bM4_SDIOC1_ERRINTST_CIE (*((volatile unsigned int*)(0x42DF864CUL))) +#define bM4_SDIOC1_ERRINTST_DTOE (*((volatile unsigned int*)(0x42DF8650UL))) +#define bM4_SDIOC1_ERRINTST_DCE (*((volatile unsigned int*)(0x42DF8654UL))) +#define bM4_SDIOC1_ERRINTST_DEBE (*((volatile unsigned int*)(0x42DF8658UL))) +#define bM4_SDIOC1_ERRINTST_ACE (*((volatile unsigned int*)(0x42DF8660UL))) +#define bM4_SDIOC1_NORINTSTEN_CCEN (*((volatile unsigned int*)(0x42DF8680UL))) +#define bM4_SDIOC1_NORINTSTEN_TCEN (*((volatile unsigned int*)(0x42DF8684UL))) +#define bM4_SDIOC1_NORINTSTEN_BGEEN (*((volatile unsigned int*)(0x42DF8688UL))) +#define bM4_SDIOC1_NORINTSTEN_BWREN (*((volatile unsigned int*)(0x42DF8690UL))) +#define bM4_SDIOC1_NORINTSTEN_BRREN (*((volatile unsigned int*)(0x42DF8694UL))) +#define bM4_SDIOC1_NORINTSTEN_CISTEN (*((volatile unsigned int*)(0x42DF8698UL))) +#define bM4_SDIOC1_NORINTSTEN_CRMEN (*((volatile unsigned int*)(0x42DF869CUL))) +#define bM4_SDIOC1_NORINTSTEN_CINTEN (*((volatile unsigned int*)(0x42DF86A0UL))) +#define bM4_SDIOC1_ERRINTSTEN_CTOEEN (*((volatile unsigned int*)(0x42DF86C0UL))) +#define bM4_SDIOC1_ERRINTSTEN_CCEEN (*((volatile unsigned int*)(0x42DF86C4UL))) +#define bM4_SDIOC1_ERRINTSTEN_CEBEEN (*((volatile unsigned int*)(0x42DF86C8UL))) +#define bM4_SDIOC1_ERRINTSTEN_CIEEN (*((volatile unsigned int*)(0x42DF86CCUL))) +#define bM4_SDIOC1_ERRINTSTEN_DTOEEN (*((volatile unsigned int*)(0x42DF86D0UL))) +#define bM4_SDIOC1_ERRINTSTEN_DCEEN (*((volatile unsigned int*)(0x42DF86D4UL))) +#define bM4_SDIOC1_ERRINTSTEN_DEBEEN (*((volatile unsigned int*)(0x42DF86D8UL))) +#define bM4_SDIOC1_ERRINTSTEN_ACEEN (*((volatile unsigned int*)(0x42DF86E0UL))) +#define bM4_SDIOC1_NORINTSGEN_CCSEN (*((volatile unsigned int*)(0x42DF8700UL))) +#define bM4_SDIOC1_NORINTSGEN_TCSEN (*((volatile unsigned int*)(0x42DF8704UL))) +#define bM4_SDIOC1_NORINTSGEN_BGESEN (*((volatile unsigned int*)(0x42DF8708UL))) +#define bM4_SDIOC1_NORINTSGEN_BWRSEN (*((volatile unsigned int*)(0x42DF8710UL))) +#define bM4_SDIOC1_NORINTSGEN_BRRSEN (*((volatile unsigned int*)(0x42DF8714UL))) +#define bM4_SDIOC1_NORINTSGEN_CISTSEN (*((volatile unsigned int*)(0x42DF8718UL))) +#define bM4_SDIOC1_NORINTSGEN_CRMSEN (*((volatile unsigned int*)(0x42DF871CUL))) +#define bM4_SDIOC1_NORINTSGEN_CINTSEN (*((volatile unsigned int*)(0x42DF8720UL))) +#define bM4_SDIOC1_ERRINTSGEN_CTOESEN (*((volatile unsigned int*)(0x42DF8740UL))) +#define bM4_SDIOC1_ERRINTSGEN_CCESEN (*((volatile unsigned int*)(0x42DF8744UL))) +#define bM4_SDIOC1_ERRINTSGEN_CEBESEN (*((volatile unsigned int*)(0x42DF8748UL))) +#define bM4_SDIOC1_ERRINTSGEN_CIESEN (*((volatile unsigned int*)(0x42DF874CUL))) +#define bM4_SDIOC1_ERRINTSGEN_DTOESEN (*((volatile unsigned int*)(0x42DF8750UL))) +#define bM4_SDIOC1_ERRINTSGEN_DCESEN (*((volatile unsigned int*)(0x42DF8754UL))) +#define bM4_SDIOC1_ERRINTSGEN_DEBESEN (*((volatile unsigned int*)(0x42DF8758UL))) +#define bM4_SDIOC1_ERRINTSGEN_ACESEN (*((volatile unsigned int*)(0x42DF8760UL))) +#define bM4_SDIOC1_ATCERRST_NE (*((volatile unsigned int*)(0x42DF8780UL))) +#define bM4_SDIOC1_ATCERRST_TOE (*((volatile unsigned int*)(0x42DF8784UL))) +#define bM4_SDIOC1_ATCERRST_CE (*((volatile unsigned int*)(0x42DF8788UL))) +#define bM4_SDIOC1_ATCERRST_EBE (*((volatile unsigned int*)(0x42DF878CUL))) +#define bM4_SDIOC1_ATCERRST_IE (*((volatile unsigned int*)(0x42DF8790UL))) +#define bM4_SDIOC1_ATCERRST_CMDE (*((volatile unsigned int*)(0x42DF879CUL))) +#define bM4_SDIOC1_FEA_FNE (*((volatile unsigned int*)(0x42DF8A00UL))) +#define bM4_SDIOC1_FEA_FTOE (*((volatile unsigned int*)(0x42DF8A04UL))) +#define bM4_SDIOC1_FEA_FCE (*((volatile unsigned int*)(0x42DF8A08UL))) +#define bM4_SDIOC1_FEA_FEBE (*((volatile unsigned int*)(0x42DF8A0CUL))) +#define bM4_SDIOC1_FEA_FIE (*((volatile unsigned int*)(0x42DF8A10UL))) +#define bM4_SDIOC1_FEA_FCMDE (*((volatile unsigned int*)(0x42DF8A1CUL))) +#define bM4_SDIOC1_FEE_FCTOE (*((volatile unsigned int*)(0x42DF8A40UL))) +#define bM4_SDIOC1_FEE_FCCE (*((volatile unsigned int*)(0x42DF8A44UL))) +#define bM4_SDIOC1_FEE_FCEBE (*((volatile unsigned int*)(0x42DF8A48UL))) +#define bM4_SDIOC1_FEE_FCIE (*((volatile unsigned int*)(0x42DF8A4CUL))) +#define bM4_SDIOC1_FEE_FDTOE (*((volatile unsigned int*)(0x42DF8A50UL))) +#define bM4_SDIOC1_FEE_FDCE (*((volatile unsigned int*)(0x42DF8A54UL))) +#define bM4_SDIOC1_FEE_FDEBE (*((volatile unsigned int*)(0x42DF8A58UL))) +#define bM4_SDIOC1_FEE_FACE (*((volatile unsigned int*)(0x42DF8A60UL))) +#define bM4_SDIOC2_BLKSIZE_TBS0 (*((volatile unsigned int*)(0x42E00080UL))) +#define bM4_SDIOC2_BLKSIZE_TBS1 (*((volatile unsigned int*)(0x42E00084UL))) +#define bM4_SDIOC2_BLKSIZE_TBS2 (*((volatile unsigned int*)(0x42E00088UL))) +#define bM4_SDIOC2_BLKSIZE_TBS3 (*((volatile unsigned int*)(0x42E0008CUL))) +#define bM4_SDIOC2_BLKSIZE_TBS4 (*((volatile unsigned int*)(0x42E00090UL))) +#define bM4_SDIOC2_BLKSIZE_TBS5 (*((volatile unsigned int*)(0x42E00094UL))) +#define bM4_SDIOC2_BLKSIZE_TBS6 (*((volatile unsigned int*)(0x42E00098UL))) +#define bM4_SDIOC2_BLKSIZE_TBS7 (*((volatile unsigned int*)(0x42E0009CUL))) +#define bM4_SDIOC2_BLKSIZE_TBS8 (*((volatile unsigned int*)(0x42E000A0UL))) +#define bM4_SDIOC2_BLKSIZE_TBS9 (*((volatile unsigned int*)(0x42E000A4UL))) +#define bM4_SDIOC2_BLKSIZE_TBS10 (*((volatile unsigned int*)(0x42E000A8UL))) +#define bM4_SDIOC2_BLKSIZE_TBS11 (*((volatile unsigned int*)(0x42E000ACUL))) +#define bM4_SDIOC2_TRANSMODE_BCE (*((volatile unsigned int*)(0x42E00184UL))) +#define bM4_SDIOC2_TRANSMODE_ATCEN0 (*((volatile unsigned int*)(0x42E00188UL))) +#define bM4_SDIOC2_TRANSMODE_ATCEN1 (*((volatile unsigned int*)(0x42E0018CUL))) +#define bM4_SDIOC2_TRANSMODE_DDIR (*((volatile unsigned int*)(0x42E00190UL))) +#define bM4_SDIOC2_TRANSMODE_MULB (*((volatile unsigned int*)(0x42E00194UL))) +#define bM4_SDIOC2_CMD_RESTYP0 (*((volatile unsigned int*)(0x42E001C0UL))) +#define bM4_SDIOC2_CMD_RESTYP1 (*((volatile unsigned int*)(0x42E001C4UL))) +#define bM4_SDIOC2_CMD_CCE (*((volatile unsigned int*)(0x42E001CCUL))) +#define bM4_SDIOC2_CMD_ICE (*((volatile unsigned int*)(0x42E001D0UL))) +#define bM4_SDIOC2_CMD_DAT (*((volatile unsigned int*)(0x42E001D4UL))) +#define bM4_SDIOC2_CMD_TYP0 (*((volatile unsigned int*)(0x42E001D8UL))) +#define bM4_SDIOC2_CMD_TYP1 (*((volatile unsigned int*)(0x42E001DCUL))) +#define bM4_SDIOC2_CMD_IDX0 (*((volatile unsigned int*)(0x42E001E0UL))) +#define bM4_SDIOC2_CMD_IDX1 (*((volatile unsigned int*)(0x42E001E4UL))) +#define bM4_SDIOC2_CMD_IDX2 (*((volatile unsigned int*)(0x42E001E8UL))) +#define bM4_SDIOC2_CMD_IDX3 (*((volatile unsigned int*)(0x42E001ECUL))) +#define bM4_SDIOC2_CMD_IDX4 (*((volatile unsigned int*)(0x42E001F0UL))) +#define bM4_SDIOC2_CMD_IDX5 (*((volatile unsigned int*)(0x42E001F4UL))) +#define bM4_SDIOC2_PSTAT_CIC (*((volatile unsigned int*)(0x42E00480UL))) +#define bM4_SDIOC2_PSTAT_CID (*((volatile unsigned int*)(0x42E00484UL))) +#define bM4_SDIOC2_PSTAT_DA (*((volatile unsigned int*)(0x42E00488UL))) +#define bM4_SDIOC2_PSTAT_WTA (*((volatile unsigned int*)(0x42E004A0UL))) +#define bM4_SDIOC2_PSTAT_RTA (*((volatile unsigned int*)(0x42E004A4UL))) +#define bM4_SDIOC2_PSTAT_BWE (*((volatile unsigned int*)(0x42E004A8UL))) +#define bM4_SDIOC2_PSTAT_BRE (*((volatile unsigned int*)(0x42E004ACUL))) +#define bM4_SDIOC2_PSTAT_CIN (*((volatile unsigned int*)(0x42E004C0UL))) +#define bM4_SDIOC2_PSTAT_CSS (*((volatile unsigned int*)(0x42E004C4UL))) +#define bM4_SDIOC2_PSTAT_CDL (*((volatile unsigned int*)(0x42E004C8UL))) +#define bM4_SDIOC2_PSTAT_WPL (*((volatile unsigned int*)(0x42E004CCUL))) +#define bM4_SDIOC2_PSTAT_DATL0 (*((volatile unsigned int*)(0x42E004D0UL))) +#define bM4_SDIOC2_PSTAT_DATL1 (*((volatile unsigned int*)(0x42E004D4UL))) +#define bM4_SDIOC2_PSTAT_DATL2 (*((volatile unsigned int*)(0x42E004D8UL))) +#define bM4_SDIOC2_PSTAT_DATL3 (*((volatile unsigned int*)(0x42E004DCUL))) +#define bM4_SDIOC2_PSTAT_CMDL (*((volatile unsigned int*)(0x42E004E0UL))) +#define bM4_SDIOC2_HOSTCON_DW (*((volatile unsigned int*)(0x42E00504UL))) +#define bM4_SDIOC2_HOSTCON_HSEN (*((volatile unsigned int*)(0x42E00508UL))) +#define bM4_SDIOC2_HOSTCON_EXDW (*((volatile unsigned int*)(0x42E00514UL))) +#define bM4_SDIOC2_HOSTCON_CDTL (*((volatile unsigned int*)(0x42E00518UL))) +#define bM4_SDIOC2_HOSTCON_CDSS (*((volatile unsigned int*)(0x42E0051CUL))) +#define bM4_SDIOC2_PWRCON_PWON (*((volatile unsigned int*)(0x42E00520UL))) +#define bM4_SDIOC2_BLKGPCON_SABGR (*((volatile unsigned int*)(0x42E00540UL))) +#define bM4_SDIOC2_BLKGPCON_CR (*((volatile unsigned int*)(0x42E00544UL))) +#define bM4_SDIOC2_BLKGPCON_RWC (*((volatile unsigned int*)(0x42E00548UL))) +#define bM4_SDIOC2_BLKGPCON_IABG (*((volatile unsigned int*)(0x42E0054CUL))) +#define bM4_SDIOC2_CLKCON_ICE (*((volatile unsigned int*)(0x42E00580UL))) +#define bM4_SDIOC2_CLKCON_CE (*((volatile unsigned int*)(0x42E00588UL))) +#define bM4_SDIOC2_CLKCON_FS0 (*((volatile unsigned int*)(0x42E005A0UL))) +#define bM4_SDIOC2_CLKCON_FS1 (*((volatile unsigned int*)(0x42E005A4UL))) +#define bM4_SDIOC2_CLKCON_FS2 (*((volatile unsigned int*)(0x42E005A8UL))) +#define bM4_SDIOC2_CLKCON_FS3 (*((volatile unsigned int*)(0x42E005ACUL))) +#define bM4_SDIOC2_CLKCON_FS4 (*((volatile unsigned int*)(0x42E005B0UL))) +#define bM4_SDIOC2_CLKCON_FS5 (*((volatile unsigned int*)(0x42E005B4UL))) +#define bM4_SDIOC2_CLKCON_FS6 (*((volatile unsigned int*)(0x42E005B8UL))) +#define bM4_SDIOC2_CLKCON_FS7 (*((volatile unsigned int*)(0x42E005BCUL))) +#define bM4_SDIOC2_TOUTCON_DTO0 (*((volatile unsigned int*)(0x42E005C0UL))) +#define bM4_SDIOC2_TOUTCON_DTO1 (*((volatile unsigned int*)(0x42E005C4UL))) +#define bM4_SDIOC2_TOUTCON_DTO2 (*((volatile unsigned int*)(0x42E005C8UL))) +#define bM4_SDIOC2_TOUTCON_DTO3 (*((volatile unsigned int*)(0x42E005CCUL))) +#define bM4_SDIOC2_SFTRST_RSTA (*((volatile unsigned int*)(0x42E005E0UL))) +#define bM4_SDIOC2_SFTRST_RSTC (*((volatile unsigned int*)(0x42E005E4UL))) +#define bM4_SDIOC2_SFTRST_RSTD (*((volatile unsigned int*)(0x42E005E8UL))) +#define bM4_SDIOC2_NORINTST_CC (*((volatile unsigned int*)(0x42E00600UL))) +#define bM4_SDIOC2_NORINTST_TC (*((volatile unsigned int*)(0x42E00604UL))) +#define bM4_SDIOC2_NORINTST_BGE (*((volatile unsigned int*)(0x42E00608UL))) +#define bM4_SDIOC2_NORINTST_BWR (*((volatile unsigned int*)(0x42E00610UL))) +#define bM4_SDIOC2_NORINTST_BRR (*((volatile unsigned int*)(0x42E00614UL))) +#define bM4_SDIOC2_NORINTST_CIST (*((volatile unsigned int*)(0x42E00618UL))) +#define bM4_SDIOC2_NORINTST_CRM (*((volatile unsigned int*)(0x42E0061CUL))) +#define bM4_SDIOC2_NORINTST_CINT (*((volatile unsigned int*)(0x42E00620UL))) +#define bM4_SDIOC2_NORINTST_EI (*((volatile unsigned int*)(0x42E0063CUL))) +#define bM4_SDIOC2_ERRINTST_CTOE (*((volatile unsigned int*)(0x42E00640UL))) +#define bM4_SDIOC2_ERRINTST_CCE (*((volatile unsigned int*)(0x42E00644UL))) +#define bM4_SDIOC2_ERRINTST_CEBE (*((volatile unsigned int*)(0x42E00648UL))) +#define bM4_SDIOC2_ERRINTST_CIE (*((volatile unsigned int*)(0x42E0064CUL))) +#define bM4_SDIOC2_ERRINTST_DTOE (*((volatile unsigned int*)(0x42E00650UL))) +#define bM4_SDIOC2_ERRINTST_DCE (*((volatile unsigned int*)(0x42E00654UL))) +#define bM4_SDIOC2_ERRINTST_DEBE (*((volatile unsigned int*)(0x42E00658UL))) +#define bM4_SDIOC2_ERRINTST_ACE (*((volatile unsigned int*)(0x42E00660UL))) +#define bM4_SDIOC2_NORINTSTEN_CCEN (*((volatile unsigned int*)(0x42E00680UL))) +#define bM4_SDIOC2_NORINTSTEN_TCEN (*((volatile unsigned int*)(0x42E00684UL))) +#define bM4_SDIOC2_NORINTSTEN_BGEEN (*((volatile unsigned int*)(0x42E00688UL))) +#define bM4_SDIOC2_NORINTSTEN_BWREN (*((volatile unsigned int*)(0x42E00690UL))) +#define bM4_SDIOC2_NORINTSTEN_BRREN (*((volatile unsigned int*)(0x42E00694UL))) +#define bM4_SDIOC2_NORINTSTEN_CISTEN (*((volatile unsigned int*)(0x42E00698UL))) +#define bM4_SDIOC2_NORINTSTEN_CRMEN (*((volatile unsigned int*)(0x42E0069CUL))) +#define bM4_SDIOC2_NORINTSTEN_CINTEN (*((volatile unsigned int*)(0x42E006A0UL))) +#define bM4_SDIOC2_ERRINTSTEN_CTOEEN (*((volatile unsigned int*)(0x42E006C0UL))) +#define bM4_SDIOC2_ERRINTSTEN_CCEEN (*((volatile unsigned int*)(0x42E006C4UL))) +#define bM4_SDIOC2_ERRINTSTEN_CEBEEN (*((volatile unsigned int*)(0x42E006C8UL))) +#define bM4_SDIOC2_ERRINTSTEN_CIEEN (*((volatile unsigned int*)(0x42E006CCUL))) +#define bM4_SDIOC2_ERRINTSTEN_DTOEEN (*((volatile unsigned int*)(0x42E006D0UL))) +#define bM4_SDIOC2_ERRINTSTEN_DCEEN (*((volatile unsigned int*)(0x42E006D4UL))) +#define bM4_SDIOC2_ERRINTSTEN_DEBEEN (*((volatile unsigned int*)(0x42E006D8UL))) +#define bM4_SDIOC2_ERRINTSTEN_ACEEN (*((volatile unsigned int*)(0x42E006E0UL))) +#define bM4_SDIOC2_NORINTSGEN_CCSEN (*((volatile unsigned int*)(0x42E00700UL))) +#define bM4_SDIOC2_NORINTSGEN_TCSEN (*((volatile unsigned int*)(0x42E00704UL))) +#define bM4_SDIOC2_NORINTSGEN_BGESEN (*((volatile unsigned int*)(0x42E00708UL))) +#define bM4_SDIOC2_NORINTSGEN_BWRSEN (*((volatile unsigned int*)(0x42E00710UL))) +#define bM4_SDIOC2_NORINTSGEN_BRRSEN (*((volatile unsigned int*)(0x42E00714UL))) +#define bM4_SDIOC2_NORINTSGEN_CISTSEN (*((volatile unsigned int*)(0x42E00718UL))) +#define bM4_SDIOC2_NORINTSGEN_CRMSEN (*((volatile unsigned int*)(0x42E0071CUL))) +#define bM4_SDIOC2_NORINTSGEN_CINTSEN (*((volatile unsigned int*)(0x42E00720UL))) +#define bM4_SDIOC2_ERRINTSGEN_CTOESEN (*((volatile unsigned int*)(0x42E00740UL))) +#define bM4_SDIOC2_ERRINTSGEN_CCESEN (*((volatile unsigned int*)(0x42E00744UL))) +#define bM4_SDIOC2_ERRINTSGEN_CEBESEN (*((volatile unsigned int*)(0x42E00748UL))) +#define bM4_SDIOC2_ERRINTSGEN_CIESEN (*((volatile unsigned int*)(0x42E0074CUL))) +#define bM4_SDIOC2_ERRINTSGEN_DTOESEN (*((volatile unsigned int*)(0x42E00750UL))) +#define bM4_SDIOC2_ERRINTSGEN_DCESEN (*((volatile unsigned int*)(0x42E00754UL))) +#define bM4_SDIOC2_ERRINTSGEN_DEBESEN (*((volatile unsigned int*)(0x42E00758UL))) +#define bM4_SDIOC2_ERRINTSGEN_ACESEN (*((volatile unsigned int*)(0x42E00760UL))) +#define bM4_SDIOC2_ATCERRST_NE (*((volatile unsigned int*)(0x42E00780UL))) +#define bM4_SDIOC2_ATCERRST_TOE (*((volatile unsigned int*)(0x42E00784UL))) +#define bM4_SDIOC2_ATCERRST_CE (*((volatile unsigned int*)(0x42E00788UL))) +#define bM4_SDIOC2_ATCERRST_EBE (*((volatile unsigned int*)(0x42E0078CUL))) +#define bM4_SDIOC2_ATCERRST_IE (*((volatile unsigned int*)(0x42E00790UL))) +#define bM4_SDIOC2_ATCERRST_CMDE (*((volatile unsigned int*)(0x42E0079CUL))) +#define bM4_SDIOC2_FEA_FNE (*((volatile unsigned int*)(0x42E00A00UL))) +#define bM4_SDIOC2_FEA_FTOE (*((volatile unsigned int*)(0x42E00A04UL))) +#define bM4_SDIOC2_FEA_FCE (*((volatile unsigned int*)(0x42E00A08UL))) +#define bM4_SDIOC2_FEA_FEBE (*((volatile unsigned int*)(0x42E00A0CUL))) +#define bM4_SDIOC2_FEA_FIE (*((volatile unsigned int*)(0x42E00A10UL))) +#define bM4_SDIOC2_FEA_FCMDE (*((volatile unsigned int*)(0x42E00A1CUL))) +#define bM4_SDIOC2_FEE_FCTOE (*((volatile unsigned int*)(0x42E00A40UL))) +#define bM4_SDIOC2_FEE_FCCE (*((volatile unsigned int*)(0x42E00A44UL))) +#define bM4_SDIOC2_FEE_FCEBE (*((volatile unsigned int*)(0x42E00A48UL))) +#define bM4_SDIOC2_FEE_FCIE (*((volatile unsigned int*)(0x42E00A4CUL))) +#define bM4_SDIOC2_FEE_FDTOE (*((volatile unsigned int*)(0x42E00A50UL))) +#define bM4_SDIOC2_FEE_FDCE (*((volatile unsigned int*)(0x42E00A54UL))) +#define bM4_SDIOC2_FEE_FDEBE (*((volatile unsigned int*)(0x42E00A58UL))) +#define bM4_SDIOC2_FEE_FACE (*((volatile unsigned int*)(0x42E00A60UL))) +#define bM4_SPI1_CR1_SPIMDS (*((volatile unsigned int*)(0x42380080UL))) +#define bM4_SPI1_CR1_TXMDS (*((volatile unsigned int*)(0x42380084UL))) +#define bM4_SPI1_CR1_MSTR (*((volatile unsigned int*)(0x4238008CUL))) +#define bM4_SPI1_CR1_SPLPBK (*((volatile unsigned int*)(0x42380090UL))) +#define bM4_SPI1_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42380094UL))) +#define bM4_SPI1_CR1_SPE (*((volatile unsigned int*)(0x42380098UL))) +#define bM4_SPI1_CR1_CSUSPE (*((volatile unsigned int*)(0x4238009CUL))) +#define bM4_SPI1_CR1_EIE (*((volatile unsigned int*)(0x423800A0UL))) +#define bM4_SPI1_CR1_TXIE (*((volatile unsigned int*)(0x423800A4UL))) +#define bM4_SPI1_CR1_RXIE (*((volatile unsigned int*)(0x423800A8UL))) +#define bM4_SPI1_CR1_IDIE (*((volatile unsigned int*)(0x423800ACUL))) +#define bM4_SPI1_CR1_MODFE (*((volatile unsigned int*)(0x423800B0UL))) +#define bM4_SPI1_CR1_PATE (*((volatile unsigned int*)(0x423800B4UL))) +#define bM4_SPI1_CR1_PAOE (*((volatile unsigned int*)(0x423800B8UL))) +#define bM4_SPI1_CR1_PAE (*((volatile unsigned int*)(0x423800BCUL))) +#define bM4_SPI1_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42380180UL))) +#define bM4_SPI1_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42380184UL))) +#define bM4_SPI1_CFG1_SPRDTD (*((volatile unsigned int*)(0x42380198UL))) +#define bM4_SPI1_CFG1_SS0PV (*((volatile unsigned int*)(0x423801A0UL))) +#define bM4_SPI1_CFG1_SS1PV (*((volatile unsigned int*)(0x423801A4UL))) +#define bM4_SPI1_CFG1_SS2PV (*((volatile unsigned int*)(0x423801A8UL))) +#define bM4_SPI1_CFG1_SS3PV (*((volatile unsigned int*)(0x423801ACUL))) +#define bM4_SPI1_CFG1_MSSI0 (*((volatile unsigned int*)(0x423801D0UL))) +#define bM4_SPI1_CFG1_MSSI1 (*((volatile unsigned int*)(0x423801D4UL))) +#define bM4_SPI1_CFG1_MSSI2 (*((volatile unsigned int*)(0x423801D8UL))) +#define bM4_SPI1_CFG1_MSSDL0 (*((volatile unsigned int*)(0x423801E0UL))) +#define bM4_SPI1_CFG1_MSSDL1 (*((volatile unsigned int*)(0x423801E4UL))) +#define bM4_SPI1_CFG1_MSSDL2 (*((volatile unsigned int*)(0x423801E8UL))) +#define bM4_SPI1_CFG1_MIDI0 (*((volatile unsigned int*)(0x423801F0UL))) +#define bM4_SPI1_CFG1_MIDI1 (*((volatile unsigned int*)(0x423801F4UL))) +#define bM4_SPI1_CFG1_MIDI2 (*((volatile unsigned int*)(0x423801F8UL))) +#define bM4_SPI1_SR_OVRERF (*((volatile unsigned int*)(0x42380280UL))) +#define bM4_SPI1_SR_IDLNF (*((volatile unsigned int*)(0x42380284UL))) +#define bM4_SPI1_SR_MODFERF (*((volatile unsigned int*)(0x42380288UL))) +#define bM4_SPI1_SR_PERF (*((volatile unsigned int*)(0x4238028CUL))) +#define bM4_SPI1_SR_UDRERF (*((volatile unsigned int*)(0x42380290UL))) +#define bM4_SPI1_SR_TDEF (*((volatile unsigned int*)(0x42380294UL))) +#define bM4_SPI1_SR_RDFF (*((volatile unsigned int*)(0x4238029CUL))) +#define bM4_SPI1_CFG2_CPHA (*((volatile unsigned int*)(0x42380300UL))) +#define bM4_SPI1_CFG2_CPOL (*((volatile unsigned int*)(0x42380304UL))) +#define bM4_SPI1_CFG2_MBR0 (*((volatile unsigned int*)(0x42380308UL))) +#define bM4_SPI1_CFG2_MBR1 (*((volatile unsigned int*)(0x4238030CUL))) +#define bM4_SPI1_CFG2_MBR2 (*((volatile unsigned int*)(0x42380310UL))) +#define bM4_SPI1_CFG2_SSA0 (*((volatile unsigned int*)(0x42380314UL))) +#define bM4_SPI1_CFG2_SSA1 (*((volatile unsigned int*)(0x42380318UL))) +#define bM4_SPI1_CFG2_SSA2 (*((volatile unsigned int*)(0x4238031CUL))) +#define bM4_SPI1_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42380320UL))) +#define bM4_SPI1_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42380324UL))) +#define bM4_SPI1_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42380328UL))) +#define bM4_SPI1_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4238032CUL))) +#define bM4_SPI1_CFG2_LSBF (*((volatile unsigned int*)(0x42380330UL))) +#define bM4_SPI1_CFG2_MIDIE (*((volatile unsigned int*)(0x42380334UL))) +#define bM4_SPI1_CFG2_MSSDLE (*((volatile unsigned int*)(0x42380338UL))) +#define bM4_SPI1_CFG2_MSSIE (*((volatile unsigned int*)(0x4238033CUL))) +#define bM4_SPI2_CR1_SPIMDS (*((volatile unsigned int*)(0x42388080UL))) +#define bM4_SPI2_CR1_TXMDS (*((volatile unsigned int*)(0x42388084UL))) +#define bM4_SPI2_CR1_MSTR (*((volatile unsigned int*)(0x4238808CUL))) +#define bM4_SPI2_CR1_SPLPBK (*((volatile unsigned int*)(0x42388090UL))) +#define bM4_SPI2_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42388094UL))) +#define bM4_SPI2_CR1_SPE (*((volatile unsigned int*)(0x42388098UL))) +#define bM4_SPI2_CR1_CSUSPE (*((volatile unsigned int*)(0x4238809CUL))) +#define bM4_SPI2_CR1_EIE (*((volatile unsigned int*)(0x423880A0UL))) +#define bM4_SPI2_CR1_TXIE (*((volatile unsigned int*)(0x423880A4UL))) +#define bM4_SPI2_CR1_RXIE (*((volatile unsigned int*)(0x423880A8UL))) +#define bM4_SPI2_CR1_IDIE (*((volatile unsigned int*)(0x423880ACUL))) +#define bM4_SPI2_CR1_MODFE (*((volatile unsigned int*)(0x423880B0UL))) +#define bM4_SPI2_CR1_PATE (*((volatile unsigned int*)(0x423880B4UL))) +#define bM4_SPI2_CR1_PAOE (*((volatile unsigned int*)(0x423880B8UL))) +#define bM4_SPI2_CR1_PAE (*((volatile unsigned int*)(0x423880BCUL))) +#define bM4_SPI2_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42388180UL))) +#define bM4_SPI2_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42388184UL))) +#define bM4_SPI2_CFG1_SPRDTD (*((volatile unsigned int*)(0x42388198UL))) +#define bM4_SPI2_CFG1_SS0PV (*((volatile unsigned int*)(0x423881A0UL))) +#define bM4_SPI2_CFG1_SS1PV (*((volatile unsigned int*)(0x423881A4UL))) +#define bM4_SPI2_CFG1_SS2PV (*((volatile unsigned int*)(0x423881A8UL))) +#define bM4_SPI2_CFG1_SS3PV (*((volatile unsigned int*)(0x423881ACUL))) +#define bM4_SPI2_CFG1_MSSI0 (*((volatile unsigned int*)(0x423881D0UL))) +#define bM4_SPI2_CFG1_MSSI1 (*((volatile unsigned int*)(0x423881D4UL))) +#define bM4_SPI2_CFG1_MSSI2 (*((volatile unsigned int*)(0x423881D8UL))) +#define bM4_SPI2_CFG1_MSSDL0 (*((volatile unsigned int*)(0x423881E0UL))) +#define bM4_SPI2_CFG1_MSSDL1 (*((volatile unsigned int*)(0x423881E4UL))) +#define bM4_SPI2_CFG1_MSSDL2 (*((volatile unsigned int*)(0x423881E8UL))) +#define bM4_SPI2_CFG1_MIDI0 (*((volatile unsigned int*)(0x423881F0UL))) +#define bM4_SPI2_CFG1_MIDI1 (*((volatile unsigned int*)(0x423881F4UL))) +#define bM4_SPI2_CFG1_MIDI2 (*((volatile unsigned int*)(0x423881F8UL))) +#define bM4_SPI2_SR_OVRERF (*((volatile unsigned int*)(0x42388280UL))) +#define bM4_SPI2_SR_IDLNF (*((volatile unsigned int*)(0x42388284UL))) +#define bM4_SPI2_SR_MODFERF (*((volatile unsigned int*)(0x42388288UL))) +#define bM4_SPI2_SR_PERF (*((volatile unsigned int*)(0x4238828CUL))) +#define bM4_SPI2_SR_UDRERF (*((volatile unsigned int*)(0x42388290UL))) +#define bM4_SPI2_SR_TDEF (*((volatile unsigned int*)(0x42388294UL))) +#define bM4_SPI2_SR_RDFF (*((volatile unsigned int*)(0x4238829CUL))) +#define bM4_SPI2_CFG2_CPHA (*((volatile unsigned int*)(0x42388300UL))) +#define bM4_SPI2_CFG2_CPOL (*((volatile unsigned int*)(0x42388304UL))) +#define bM4_SPI2_CFG2_MBR0 (*((volatile unsigned int*)(0x42388308UL))) +#define bM4_SPI2_CFG2_MBR1 (*((volatile unsigned int*)(0x4238830CUL))) +#define bM4_SPI2_CFG2_MBR2 (*((volatile unsigned int*)(0x42388310UL))) +#define bM4_SPI2_CFG2_SSA0 (*((volatile unsigned int*)(0x42388314UL))) +#define bM4_SPI2_CFG2_SSA1 (*((volatile unsigned int*)(0x42388318UL))) +#define bM4_SPI2_CFG2_SSA2 (*((volatile unsigned int*)(0x4238831CUL))) +#define bM4_SPI2_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42388320UL))) +#define bM4_SPI2_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42388324UL))) +#define bM4_SPI2_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42388328UL))) +#define bM4_SPI2_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4238832CUL))) +#define bM4_SPI2_CFG2_LSBF (*((volatile unsigned int*)(0x42388330UL))) +#define bM4_SPI2_CFG2_MIDIE (*((volatile unsigned int*)(0x42388334UL))) +#define bM4_SPI2_CFG2_MSSDLE (*((volatile unsigned int*)(0x42388338UL))) +#define bM4_SPI2_CFG2_MSSIE (*((volatile unsigned int*)(0x4238833CUL))) +#define bM4_SPI3_CR1_SPIMDS (*((volatile unsigned int*)(0x42400080UL))) +#define bM4_SPI3_CR1_TXMDS (*((volatile unsigned int*)(0x42400084UL))) +#define bM4_SPI3_CR1_MSTR (*((volatile unsigned int*)(0x4240008CUL))) +#define bM4_SPI3_CR1_SPLPBK (*((volatile unsigned int*)(0x42400090UL))) +#define bM4_SPI3_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42400094UL))) +#define bM4_SPI3_CR1_SPE (*((volatile unsigned int*)(0x42400098UL))) +#define bM4_SPI3_CR1_CSUSPE (*((volatile unsigned int*)(0x4240009CUL))) +#define bM4_SPI3_CR1_EIE (*((volatile unsigned int*)(0x424000A0UL))) +#define bM4_SPI3_CR1_TXIE (*((volatile unsigned int*)(0x424000A4UL))) +#define bM4_SPI3_CR1_RXIE (*((volatile unsigned int*)(0x424000A8UL))) +#define bM4_SPI3_CR1_IDIE (*((volatile unsigned int*)(0x424000ACUL))) +#define bM4_SPI3_CR1_MODFE (*((volatile unsigned int*)(0x424000B0UL))) +#define bM4_SPI3_CR1_PATE (*((volatile unsigned int*)(0x424000B4UL))) +#define bM4_SPI3_CR1_PAOE (*((volatile unsigned int*)(0x424000B8UL))) +#define bM4_SPI3_CR1_PAE (*((volatile unsigned int*)(0x424000BCUL))) +#define bM4_SPI3_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42400180UL))) +#define bM4_SPI3_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42400184UL))) +#define bM4_SPI3_CFG1_SPRDTD (*((volatile unsigned int*)(0x42400198UL))) +#define bM4_SPI3_CFG1_SS0PV (*((volatile unsigned int*)(0x424001A0UL))) +#define bM4_SPI3_CFG1_SS1PV (*((volatile unsigned int*)(0x424001A4UL))) +#define bM4_SPI3_CFG1_SS2PV (*((volatile unsigned int*)(0x424001A8UL))) +#define bM4_SPI3_CFG1_SS3PV (*((volatile unsigned int*)(0x424001ACUL))) +#define bM4_SPI3_CFG1_MSSI0 (*((volatile unsigned int*)(0x424001D0UL))) +#define bM4_SPI3_CFG1_MSSI1 (*((volatile unsigned int*)(0x424001D4UL))) +#define bM4_SPI3_CFG1_MSSI2 (*((volatile unsigned int*)(0x424001D8UL))) +#define bM4_SPI3_CFG1_MSSDL0 (*((volatile unsigned int*)(0x424001E0UL))) +#define bM4_SPI3_CFG1_MSSDL1 (*((volatile unsigned int*)(0x424001E4UL))) +#define bM4_SPI3_CFG1_MSSDL2 (*((volatile unsigned int*)(0x424001E8UL))) +#define bM4_SPI3_CFG1_MIDI0 (*((volatile unsigned int*)(0x424001F0UL))) +#define bM4_SPI3_CFG1_MIDI1 (*((volatile unsigned int*)(0x424001F4UL))) +#define bM4_SPI3_CFG1_MIDI2 (*((volatile unsigned int*)(0x424001F8UL))) +#define bM4_SPI3_SR_OVRERF (*((volatile unsigned int*)(0x42400280UL))) +#define bM4_SPI3_SR_IDLNF (*((volatile unsigned int*)(0x42400284UL))) +#define bM4_SPI3_SR_MODFERF (*((volatile unsigned int*)(0x42400288UL))) +#define bM4_SPI3_SR_PERF (*((volatile unsigned int*)(0x4240028CUL))) +#define bM4_SPI3_SR_UDRERF (*((volatile unsigned int*)(0x42400290UL))) +#define bM4_SPI3_SR_TDEF (*((volatile unsigned int*)(0x42400294UL))) +#define bM4_SPI3_SR_RDFF (*((volatile unsigned int*)(0x4240029CUL))) +#define bM4_SPI3_CFG2_CPHA (*((volatile unsigned int*)(0x42400300UL))) +#define bM4_SPI3_CFG2_CPOL (*((volatile unsigned int*)(0x42400304UL))) +#define bM4_SPI3_CFG2_MBR0 (*((volatile unsigned int*)(0x42400308UL))) +#define bM4_SPI3_CFG2_MBR1 (*((volatile unsigned int*)(0x4240030CUL))) +#define bM4_SPI3_CFG2_MBR2 (*((volatile unsigned int*)(0x42400310UL))) +#define bM4_SPI3_CFG2_SSA0 (*((volatile unsigned int*)(0x42400314UL))) +#define bM4_SPI3_CFG2_SSA1 (*((volatile unsigned int*)(0x42400318UL))) +#define bM4_SPI3_CFG2_SSA2 (*((volatile unsigned int*)(0x4240031CUL))) +#define bM4_SPI3_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42400320UL))) +#define bM4_SPI3_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42400324UL))) +#define bM4_SPI3_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42400328UL))) +#define bM4_SPI3_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4240032CUL))) +#define bM4_SPI3_CFG2_LSBF (*((volatile unsigned int*)(0x42400330UL))) +#define bM4_SPI3_CFG2_MIDIE (*((volatile unsigned int*)(0x42400334UL))) +#define bM4_SPI3_CFG2_MSSDLE (*((volatile unsigned int*)(0x42400338UL))) +#define bM4_SPI3_CFG2_MSSIE (*((volatile unsigned int*)(0x4240033CUL))) +#define bM4_SPI4_CR1_SPIMDS (*((volatile unsigned int*)(0x42408080UL))) +#define bM4_SPI4_CR1_TXMDS (*((volatile unsigned int*)(0x42408084UL))) +#define bM4_SPI4_CR1_MSTR (*((volatile unsigned int*)(0x4240808CUL))) +#define bM4_SPI4_CR1_SPLPBK (*((volatile unsigned int*)(0x42408090UL))) +#define bM4_SPI4_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42408094UL))) +#define bM4_SPI4_CR1_SPE (*((volatile unsigned int*)(0x42408098UL))) +#define bM4_SPI4_CR1_CSUSPE (*((volatile unsigned int*)(0x4240809CUL))) +#define bM4_SPI4_CR1_EIE (*((volatile unsigned int*)(0x424080A0UL))) +#define bM4_SPI4_CR1_TXIE (*((volatile unsigned int*)(0x424080A4UL))) +#define bM4_SPI4_CR1_RXIE (*((volatile unsigned int*)(0x424080A8UL))) +#define bM4_SPI4_CR1_IDIE (*((volatile unsigned int*)(0x424080ACUL))) +#define bM4_SPI4_CR1_MODFE (*((volatile unsigned int*)(0x424080B0UL))) +#define bM4_SPI4_CR1_PATE (*((volatile unsigned int*)(0x424080B4UL))) +#define bM4_SPI4_CR1_PAOE (*((volatile unsigned int*)(0x424080B8UL))) +#define bM4_SPI4_CR1_PAE (*((volatile unsigned int*)(0x424080BCUL))) +#define bM4_SPI4_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42408180UL))) +#define bM4_SPI4_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42408184UL))) +#define bM4_SPI4_CFG1_SPRDTD (*((volatile unsigned int*)(0x42408198UL))) +#define bM4_SPI4_CFG1_SS0PV (*((volatile unsigned int*)(0x424081A0UL))) +#define bM4_SPI4_CFG1_SS1PV (*((volatile unsigned int*)(0x424081A4UL))) +#define bM4_SPI4_CFG1_SS2PV (*((volatile unsigned int*)(0x424081A8UL))) +#define bM4_SPI4_CFG1_SS3PV (*((volatile unsigned int*)(0x424081ACUL))) +#define bM4_SPI4_CFG1_MSSI0 (*((volatile unsigned int*)(0x424081D0UL))) +#define bM4_SPI4_CFG1_MSSI1 (*((volatile unsigned int*)(0x424081D4UL))) +#define bM4_SPI4_CFG1_MSSI2 (*((volatile unsigned int*)(0x424081D8UL))) +#define bM4_SPI4_CFG1_MSSDL0 (*((volatile unsigned int*)(0x424081E0UL))) +#define bM4_SPI4_CFG1_MSSDL1 (*((volatile unsigned int*)(0x424081E4UL))) +#define bM4_SPI4_CFG1_MSSDL2 (*((volatile unsigned int*)(0x424081E8UL))) +#define bM4_SPI4_CFG1_MIDI0 (*((volatile unsigned int*)(0x424081F0UL))) +#define bM4_SPI4_CFG1_MIDI1 (*((volatile unsigned int*)(0x424081F4UL))) +#define bM4_SPI4_CFG1_MIDI2 (*((volatile unsigned int*)(0x424081F8UL))) +#define bM4_SPI4_SR_OVRERF (*((volatile unsigned int*)(0x42408280UL))) +#define bM4_SPI4_SR_IDLNF (*((volatile unsigned int*)(0x42408284UL))) +#define bM4_SPI4_SR_MODFERF (*((volatile unsigned int*)(0x42408288UL))) +#define bM4_SPI4_SR_PERF (*((volatile unsigned int*)(0x4240828CUL))) +#define bM4_SPI4_SR_UDRERF (*((volatile unsigned int*)(0x42408290UL))) +#define bM4_SPI4_SR_TDEF (*((volatile unsigned int*)(0x42408294UL))) +#define bM4_SPI4_SR_RDFF (*((volatile unsigned int*)(0x4240829CUL))) +#define bM4_SPI4_CFG2_CPHA (*((volatile unsigned int*)(0x42408300UL))) +#define bM4_SPI4_CFG2_CPOL (*((volatile unsigned int*)(0x42408304UL))) +#define bM4_SPI4_CFG2_MBR0 (*((volatile unsigned int*)(0x42408308UL))) +#define bM4_SPI4_CFG2_MBR1 (*((volatile unsigned int*)(0x4240830CUL))) +#define bM4_SPI4_CFG2_MBR2 (*((volatile unsigned int*)(0x42408310UL))) +#define bM4_SPI4_CFG2_SSA0 (*((volatile unsigned int*)(0x42408314UL))) +#define bM4_SPI4_CFG2_SSA1 (*((volatile unsigned int*)(0x42408318UL))) +#define bM4_SPI4_CFG2_SSA2 (*((volatile unsigned int*)(0x4240831CUL))) +#define bM4_SPI4_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42408320UL))) +#define bM4_SPI4_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42408324UL))) +#define bM4_SPI4_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42408328UL))) +#define bM4_SPI4_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4240832CUL))) +#define bM4_SPI4_CFG2_LSBF (*((volatile unsigned int*)(0x42408330UL))) +#define bM4_SPI4_CFG2_MIDIE (*((volatile unsigned int*)(0x42408334UL))) +#define bM4_SPI4_CFG2_MSSDLE (*((volatile unsigned int*)(0x42408338UL))) +#define bM4_SPI4_CFG2_MSSIE (*((volatile unsigned int*)(0x4240833CUL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT0 (*((volatile unsigned int*)(0x42A10000UL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT1 (*((volatile unsigned int*)(0x42A10004UL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT2 (*((volatile unsigned int*)(0x42A10008UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT0 (*((volatile unsigned int*)(0x42A10010UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT1 (*((volatile unsigned int*)(0x42A10014UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT2 (*((volatile unsigned int*)(0x42A10018UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT0 (*((volatile unsigned int*)(0x42A10020UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT1 (*((volatile unsigned int*)(0x42A10024UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT2 (*((volatile unsigned int*)(0x42A10028UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT0 (*((volatile unsigned int*)(0x42A10030UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT1 (*((volatile unsigned int*)(0x42A10034UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT2 (*((volatile unsigned int*)(0x42A10038UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT0 (*((volatile unsigned int*)(0x42A10040UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT1 (*((volatile unsigned int*)(0x42A10044UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT2 (*((volatile unsigned int*)(0x42A10048UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT0 (*((volatile unsigned int*)(0x42A10050UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT1 (*((volatile unsigned int*)(0x42A10054UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT2 (*((volatile unsigned int*)(0x42A10058UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT0 (*((volatile unsigned int*)(0x42A10060UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT1 (*((volatile unsigned int*)(0x42A10064UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT2 (*((volatile unsigned int*)(0x42A10068UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT0 (*((volatile unsigned int*)(0x42A10070UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT1 (*((volatile unsigned int*)(0x42A10074UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT2 (*((volatile unsigned int*)(0x42A10078UL))) +#define bM4_SRAMC_WTPR_WTPRC (*((volatile unsigned int*)(0x42A10080UL))) +#define bM4_SRAMC_WTPR_WTPRKW0 (*((volatile unsigned int*)(0x42A10084UL))) +#define bM4_SRAMC_WTPR_WTPRKW1 (*((volatile unsigned int*)(0x42A10088UL))) +#define bM4_SRAMC_WTPR_WTPRKW2 (*((volatile unsigned int*)(0x42A1008CUL))) +#define bM4_SRAMC_WTPR_WTPRKW3 (*((volatile unsigned int*)(0x42A10090UL))) +#define bM4_SRAMC_WTPR_WTPRKW4 (*((volatile unsigned int*)(0x42A10094UL))) +#define bM4_SRAMC_WTPR_WTPRKW5 (*((volatile unsigned int*)(0x42A10098UL))) +#define bM4_SRAMC_WTPR_WTPRKW6 (*((volatile unsigned int*)(0x42A1009CUL))) +#define bM4_SRAMC_CKCR_PYOAD (*((volatile unsigned int*)(0x42A10100UL))) +#define bM4_SRAMC_CKCR_ECCOAD (*((volatile unsigned int*)(0x42A10140UL))) +#define bM4_SRAMC_CKCR_ECCMOD0 (*((volatile unsigned int*)(0x42A10160UL))) +#define bM4_SRAMC_CKCR_ECCMOD1 (*((volatile unsigned int*)(0x42A10164UL))) +#define bM4_SRAMC_CKPR_CKPRC (*((volatile unsigned int*)(0x42A10180UL))) +#define bM4_SRAMC_CKPR_CKPRKW0 (*((volatile unsigned int*)(0x42A10184UL))) +#define bM4_SRAMC_CKPR_CKPRKW1 (*((volatile unsigned int*)(0x42A10188UL))) +#define bM4_SRAMC_CKPR_CKPRKW2 (*((volatile unsigned int*)(0x42A1018CUL))) +#define bM4_SRAMC_CKPR_CKPRKW3 (*((volatile unsigned int*)(0x42A10190UL))) +#define bM4_SRAMC_CKPR_CKPRKW4 (*((volatile unsigned int*)(0x42A10194UL))) +#define bM4_SRAMC_CKPR_CKPRKW5 (*((volatile unsigned int*)(0x42A10198UL))) +#define bM4_SRAMC_CKPR_CKPRKW6 (*((volatile unsigned int*)(0x42A1019CUL))) +#define bM4_SRAMC_CKSR_SRAM3_1ERR (*((volatile unsigned int*)(0x42A10200UL))) +#define bM4_SRAMC_CKSR_SRAM3_2ERR (*((volatile unsigned int*)(0x42A10204UL))) +#define bM4_SRAMC_CKSR_SRAM12_PYERR (*((volatile unsigned int*)(0x42A10208UL))) +#define bM4_SRAMC_CKSR_SRAMH_PYERR (*((volatile unsigned int*)(0x42A1020CUL))) +#define bM4_SRAMC_CKSR_SRAMR_PYERR (*((volatile unsigned int*)(0x42A10210UL))) +#define bM4_SWDT_SR_CNT0 (*((volatile unsigned int*)(0x42928080UL))) +#define bM4_SWDT_SR_CNT1 (*((volatile unsigned int*)(0x42928084UL))) +#define bM4_SWDT_SR_CNT2 (*((volatile unsigned int*)(0x42928088UL))) +#define bM4_SWDT_SR_CNT3 (*((volatile unsigned int*)(0x4292808CUL))) +#define bM4_SWDT_SR_CNT4 (*((volatile unsigned int*)(0x42928090UL))) +#define bM4_SWDT_SR_CNT5 (*((volatile unsigned int*)(0x42928094UL))) +#define bM4_SWDT_SR_CNT6 (*((volatile unsigned int*)(0x42928098UL))) +#define bM4_SWDT_SR_CNT7 (*((volatile unsigned int*)(0x4292809CUL))) +#define bM4_SWDT_SR_CNT8 (*((volatile unsigned int*)(0x429280A0UL))) +#define bM4_SWDT_SR_CNT9 (*((volatile unsigned int*)(0x429280A4UL))) +#define bM4_SWDT_SR_CNT10 (*((volatile unsigned int*)(0x429280A8UL))) +#define bM4_SWDT_SR_CNT11 (*((volatile unsigned int*)(0x429280ACUL))) +#define bM4_SWDT_SR_CNT12 (*((volatile unsigned int*)(0x429280B0UL))) +#define bM4_SWDT_SR_CNT13 (*((volatile unsigned int*)(0x429280B4UL))) +#define bM4_SWDT_SR_CNT14 (*((volatile unsigned int*)(0x429280B8UL))) +#define bM4_SWDT_SR_CNT15 (*((volatile unsigned int*)(0x429280BCUL))) +#define bM4_SWDT_SR_UDF (*((volatile unsigned int*)(0x429280C0UL))) +#define bM4_SWDT_SR_REF (*((volatile unsigned int*)(0x429280C4UL))) +#define bM4_SWDT_RR_RF0 (*((volatile unsigned int*)(0x42928100UL))) +#define bM4_SWDT_RR_RF1 (*((volatile unsigned int*)(0x42928104UL))) +#define bM4_SWDT_RR_RF2 (*((volatile unsigned int*)(0x42928108UL))) +#define bM4_SWDT_RR_RF3 (*((volatile unsigned int*)(0x4292810CUL))) +#define bM4_SWDT_RR_RF4 (*((volatile unsigned int*)(0x42928110UL))) +#define bM4_SWDT_RR_RF5 (*((volatile unsigned int*)(0x42928114UL))) +#define bM4_SWDT_RR_RF6 (*((volatile unsigned int*)(0x42928118UL))) +#define bM4_SWDT_RR_RF7 (*((volatile unsigned int*)(0x4292811CUL))) +#define bM4_SWDT_RR_RF8 (*((volatile unsigned int*)(0x42928120UL))) +#define bM4_SWDT_RR_RF9 (*((volatile unsigned int*)(0x42928124UL))) +#define bM4_SWDT_RR_RF10 (*((volatile unsigned int*)(0x42928128UL))) +#define bM4_SWDT_RR_RF11 (*((volatile unsigned int*)(0x4292812CUL))) +#define bM4_SWDT_RR_RF12 (*((volatile unsigned int*)(0x42928130UL))) +#define bM4_SWDT_RR_RF13 (*((volatile unsigned int*)(0x42928134UL))) +#define bM4_SWDT_RR_RF14 (*((volatile unsigned int*)(0x42928138UL))) +#define bM4_SWDT_RR_RF15 (*((volatile unsigned int*)(0x4292813CUL))) +#define bM4_SYSREG_PWR_STPMCR_FLNWT (*((volatile unsigned int*)(0x42A80180UL))) +#define bM4_SYSREG_PWR_STPMCR_CKSMRC (*((volatile unsigned int*)(0x42A80184UL))) +#define bM4_SYSREG_PWR_STPMCR_STOP (*((volatile unsigned int*)(0x42A801BCUL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL0 (*((volatile unsigned int*)(0x42A80200UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL1 (*((volatile unsigned int*)(0x42A80204UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL2 (*((volatile unsigned int*)(0x42A80208UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL3 (*((volatile unsigned int*)(0x42A8020CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL0 (*((volatile unsigned int*)(0x42A80240UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL1 (*((volatile unsigned int*)(0x42A80244UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL2 (*((volatile unsigned int*)(0x42A80248UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL3 (*((volatile unsigned int*)(0x42A8024CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL0 (*((volatile unsigned int*)(0x42A80250UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL1 (*((volatile unsigned int*)(0x42A80254UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL2 (*((volatile unsigned int*)(0x42A80258UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL3 (*((volatile unsigned int*)(0x42A8025CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL0 (*((volatile unsigned int*)(0x42A80260UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL1 (*((volatile unsigned int*)(0x42A80264UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL2 (*((volatile unsigned int*)(0x42A80268UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL3 (*((volatile unsigned int*)(0x42A8026CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL0 (*((volatile unsigned int*)(0x42A80270UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL1 (*((volatile unsigned int*)(0x42A80274UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL2 (*((volatile unsigned int*)(0x42A80278UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL3 (*((volatile unsigned int*)(0x42A8027CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC0 (*((volatile unsigned int*)(0x42A80280UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC1 (*((volatile unsigned int*)(0x42A80284UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC2 (*((volatile unsigned int*)(0x42A80288UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC3 (*((volatile unsigned int*)(0x42A8028CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC4 (*((volatile unsigned int*)(0x42A80290UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC5 (*((volatile unsigned int*)(0x42A80294UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC6 (*((volatile unsigned int*)(0x42A80298UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC7 (*((volatile unsigned int*)(0x42A8029CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC8 (*((volatile unsigned int*)(0x42A802A0UL))) +#define bM4_SYSREG_MPU_IPPR_AESRDP (*((volatile unsigned int*)(0x42A80380UL))) +#define bM4_SYSREG_MPU_IPPR_AESWRP (*((volatile unsigned int*)(0x42A80384UL))) +#define bM4_SYSREG_MPU_IPPR_HASHRDP (*((volatile unsigned int*)(0x42A80388UL))) +#define bM4_SYSREG_MPU_IPPR_HASHWRP (*((volatile unsigned int*)(0x42A8038CUL))) +#define bM4_SYSREG_MPU_IPPR_TRNGRDP (*((volatile unsigned int*)(0x42A80390UL))) +#define bM4_SYSREG_MPU_IPPR_TRNGWRP (*((volatile unsigned int*)(0x42A80394UL))) +#define bM4_SYSREG_MPU_IPPR_CRCRDP (*((volatile unsigned int*)(0x42A80398UL))) +#define bM4_SYSREG_MPU_IPPR_CRCWRP (*((volatile unsigned int*)(0x42A8039CUL))) +#define bM4_SYSREG_MPU_IPPR_FMCRDP (*((volatile unsigned int*)(0x42A803A0UL))) +#define bM4_SYSREG_MPU_IPPR_FMCWRP (*((volatile unsigned int*)(0x42A803A4UL))) +#define bM4_SYSREG_MPU_IPPR_WDTRDP (*((volatile unsigned int*)(0x42A803B0UL))) +#define bM4_SYSREG_MPU_IPPR_WDTWRP (*((volatile unsigned int*)(0x42A803B4UL))) +#define bM4_SYSREG_MPU_IPPR_SWDTRDP (*((volatile unsigned int*)(0x42A803B8UL))) +#define bM4_SYSREG_MPU_IPPR_SWDTWRP (*((volatile unsigned int*)(0x42A803BCUL))) +#define bM4_SYSREG_MPU_IPPR_BKSRAMRDP (*((volatile unsigned int*)(0x42A803C0UL))) +#define bM4_SYSREG_MPU_IPPR_BKSRAMWRP (*((volatile unsigned int*)(0x42A803C4UL))) +#define bM4_SYSREG_MPU_IPPR_RTCRDP (*((volatile unsigned int*)(0x42A803C8UL))) +#define bM4_SYSREG_MPU_IPPR_RTCWRP (*((volatile unsigned int*)(0x42A803CCUL))) +#define bM4_SYSREG_MPU_IPPR_DMPURDP (*((volatile unsigned int*)(0x42A803D0UL))) +#define bM4_SYSREG_MPU_IPPR_DMPUWRP (*((volatile unsigned int*)(0x42A803D4UL))) +#define bM4_SYSREG_MPU_IPPR_SRAMCRDP (*((volatile unsigned int*)(0x42A803D8UL))) +#define bM4_SYSREG_MPU_IPPR_SRAMCWRP (*((volatile unsigned int*)(0x42A803DCUL))) +#define bM4_SYSREG_MPU_IPPR_INTCRDP (*((volatile unsigned int*)(0x42A803E0UL))) +#define bM4_SYSREG_MPU_IPPR_INTCWRP (*((volatile unsigned int*)(0x42A803E4UL))) +#define bM4_SYSREG_MPU_IPPR_SYSCRDP (*((volatile unsigned int*)(0x42A803E8UL))) +#define bM4_SYSREG_MPU_IPPR_SYSCWRP (*((volatile unsigned int*)(0x42A803ECUL))) +#define bM4_SYSREG_MPU_IPPR_MSTPRDP (*((volatile unsigned int*)(0x42A803F0UL))) +#define bM4_SYSREG_MPU_IPPR_MSTPWRP (*((volatile unsigned int*)(0x42A803F4UL))) +#define bM4_SYSREG_MPU_IPPR_BUSERRE (*((volatile unsigned int*)(0x42A803FCUL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S0 (*((volatile unsigned int*)(0x42A80400UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S1 (*((volatile unsigned int*)(0x42A80404UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S2 (*((volatile unsigned int*)(0x42A80408UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S0 (*((volatile unsigned int*)(0x42A80410UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S1 (*((volatile unsigned int*)(0x42A80414UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S2 (*((volatile unsigned int*)(0x42A80418UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S0 (*((volatile unsigned int*)(0x42A80420UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S1 (*((volatile unsigned int*)(0x42A80424UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S2 (*((volatile unsigned int*)(0x42A80428UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S0 (*((volatile unsigned int*)(0x42A80430UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S1 (*((volatile unsigned int*)(0x42A80434UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S2 (*((volatile unsigned int*)(0x42A80438UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S0 (*((volatile unsigned int*)(0x42A80440UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S1 (*((volatile unsigned int*)(0x42A80444UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S2 (*((volatile unsigned int*)(0x42A80448UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS0 (*((volatile unsigned int*)(0x42A80450UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS1 (*((volatile unsigned int*)(0x42A80454UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS2 (*((volatile unsigned int*)(0x42A80458UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS0 (*((volatile unsigned int*)(0x42A80460UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS1 (*((volatile unsigned int*)(0x42A80464UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS2 (*((volatile unsigned int*)(0x42A80468UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS0 (*((volatile unsigned int*)(0x42A80490UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS1 (*((volatile unsigned int*)(0x42A80494UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS2 (*((volatile unsigned int*)(0x42A80498UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS3 (*((volatile unsigned int*)(0x42A8049CUL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW0 (*((volatile unsigned int*)(0x42A804C0UL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW1 (*((volatile unsigned int*)(0x42A804C4UL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW2 (*((volatile unsigned int*)(0x42A804C8UL))) +#define bM4_SYSREG_CMU_PLLCR_MPLLOFF (*((volatile unsigned int*)(0x42A80540UL))) +#define bM4_SYSREG_CMU_UPLLCR_UPLLOFF (*((volatile unsigned int*)(0x42A805C0UL))) +#define bM4_SYSREG_CMU_XTALCR_XTALSTP (*((volatile unsigned int*)(0x42A80640UL))) +#define bM4_SYSREG_CMU_HRCCR_HRCSTP (*((volatile unsigned int*)(0x42A806C0UL))) +#define bM4_SYSREG_CMU_MRCCR_MRCSTP (*((volatile unsigned int*)(0x42A80700UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_HRCSTBF (*((volatile unsigned int*)(0x42A80780UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_XTALSTBF (*((volatile unsigned int*)(0x42A8078CUL))) +#define bM4_SYSREG_CMU_OSCSTBSR_MPLLSTBF (*((volatile unsigned int*)(0x42A80794UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_UPLLSTBF (*((volatile unsigned int*)(0x42A80798UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL0 (*((volatile unsigned int*)(0x42A807A0UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL1 (*((volatile unsigned int*)(0x42A807A4UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL2 (*((volatile unsigned int*)(0x42A807A8UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL3 (*((volatile unsigned int*)(0x42A807ACUL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV0 (*((volatile unsigned int*)(0x42A807B0UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV1 (*((volatile unsigned int*)(0x42A807B4UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV2 (*((volatile unsigned int*)(0x42A807B8UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1EN (*((volatile unsigned int*)(0x42A807BCUL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL0 (*((volatile unsigned int*)(0x42A807C0UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL1 (*((volatile unsigned int*)(0x42A807C4UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL2 (*((volatile unsigned int*)(0x42A807C8UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL3 (*((volatile unsigned int*)(0x42A807CCUL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV0 (*((volatile unsigned int*)(0x42A807D0UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV1 (*((volatile unsigned int*)(0x42A807D4UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV2 (*((volatile unsigned int*)(0x42A807D8UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2EN (*((volatile unsigned int*)(0x42A807DCUL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKS0 (*((volatile unsigned int*)(0x42A807E0UL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKS1 (*((volatile unsigned int*)(0x42A807E4UL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKOE (*((volatile unsigned int*)(0x42A807FCUL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDIE (*((volatile unsigned int*)(0x42A80800UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDRE (*((volatile unsigned int*)(0x42A80804UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDRIS (*((volatile unsigned int*)(0x42A80808UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDE (*((volatile unsigned int*)(0x42A8081CUL))) +#define bM4_SYSREG_CMU_XTALSTDSR_XTALSTDF (*((volatile unsigned int*)(0x42A80820UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB0 (*((volatile unsigned int*)(0x42A81440UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB1 (*((volatile unsigned int*)(0x42A81444UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB2 (*((volatile unsigned int*)(0x42A81448UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB3 (*((volatile unsigned int*)(0x42A8144CUL))) +#define bM4_SYSREG_RMU_RSTF0_PORF (*((volatile unsigned int*)(0x42A81800UL))) +#define bM4_SYSREG_RMU_RSTF0_PINRF (*((volatile unsigned int*)(0x42A81804UL))) +#define bM4_SYSREG_RMU_RSTF0_BORF (*((volatile unsigned int*)(0x42A81808UL))) +#define bM4_SYSREG_RMU_RSTF0_PVD1RF (*((volatile unsigned int*)(0x42A8180CUL))) +#define bM4_SYSREG_RMU_RSTF0_PVD2RF (*((volatile unsigned int*)(0x42A81810UL))) +#define bM4_SYSREG_RMU_RSTF0_WDRF (*((volatile unsigned int*)(0x42A81814UL))) +#define bM4_SYSREG_RMU_RSTF0_SWDRF (*((volatile unsigned int*)(0x42A81818UL))) +#define bM4_SYSREG_RMU_RSTF0_PDRF (*((volatile unsigned int*)(0x42A8181CUL))) +#define bM4_SYSREG_RMU_RSTF0_SWRF (*((volatile unsigned int*)(0x42A81820UL))) +#define bM4_SYSREG_RMU_RSTF0_MPUERF (*((volatile unsigned int*)(0x42A81824UL))) +#define bM4_SYSREG_RMU_RSTF0_RAPERF (*((volatile unsigned int*)(0x42A81828UL))) +#define bM4_SYSREG_RMU_RSTF0_RAECRF (*((volatile unsigned int*)(0x42A8182CUL))) +#define bM4_SYSREG_RMU_RSTF0_CKFERF (*((volatile unsigned int*)(0x42A81830UL))) +#define bM4_SYSREG_RMU_RSTF0_XTALERF (*((volatile unsigned int*)(0x42A81834UL))) +#define bM4_SYSREG_RMU_RSTF0_MULTIRF (*((volatile unsigned int*)(0x42A81838UL))) +#define bM4_SYSREG_RMU_RSTF0_CLRF (*((volatile unsigned int*)(0x42A8183CUL))) +#define bM4_SYSREG_PWR_PVDICR_PVD1NMIS (*((volatile unsigned int*)(0x42A81C00UL))) +#define bM4_SYSREG_PWR_PVDICR_PVD2NMIS (*((volatile unsigned int*)(0x42A81C10UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD1MON (*((volatile unsigned int*)(0x42A81C20UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD1DETFLG (*((volatile unsigned int*)(0x42A81C24UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD2MON (*((volatile unsigned int*)(0x42A81C30UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD2DETFLG (*((volatile unsigned int*)(0x42A81C34UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM0 (*((volatile unsigned int*)(0x42A82000UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM1 (*((volatile unsigned int*)(0x42A82004UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM2 (*((volatile unsigned int*)(0x42A82008UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM3 (*((volatile unsigned int*)(0x42A8200CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM4 (*((volatile unsigned int*)(0x42A82010UL))) +#define bM4_SYSREG_CMU_PLLCFGR_PLLSRC (*((volatile unsigned int*)(0x42A8201CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN0 (*((volatile unsigned int*)(0x42A82020UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN1 (*((volatile unsigned int*)(0x42A82024UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN2 (*((volatile unsigned int*)(0x42A82028UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN3 (*((volatile unsigned int*)(0x42A8202CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN4 (*((volatile unsigned int*)(0x42A82030UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN5 (*((volatile unsigned int*)(0x42A82034UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN6 (*((volatile unsigned int*)(0x42A82038UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN7 (*((volatile unsigned int*)(0x42A8203CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN8 (*((volatile unsigned int*)(0x42A82040UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR0 (*((volatile unsigned int*)(0x42A82050UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR1 (*((volatile unsigned int*)(0x42A82054UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR2 (*((volatile unsigned int*)(0x42A82058UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR3 (*((volatile unsigned int*)(0x42A8205CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ0 (*((volatile unsigned int*)(0x42A82060UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ1 (*((volatile unsigned int*)(0x42A82064UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ2 (*((volatile unsigned int*)(0x42A82068UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ3 (*((volatile unsigned int*)(0x42A8206CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP0 (*((volatile unsigned int*)(0x42A82070UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP1 (*((volatile unsigned int*)(0x42A82074UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP2 (*((volatile unsigned int*)(0x42A82078UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP3 (*((volatile unsigned int*)(0x42A8207CUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM0 (*((volatile unsigned int*)(0x42A82080UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM1 (*((volatile unsigned int*)(0x42A82084UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM2 (*((volatile unsigned int*)(0x42A82088UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM3 (*((volatile unsigned int*)(0x42A8208CUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM4 (*((volatile unsigned int*)(0x42A82090UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN0 (*((volatile unsigned int*)(0x42A820A0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN1 (*((volatile unsigned int*)(0x42A820A4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN2 (*((volatile unsigned int*)(0x42A820A8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN3 (*((volatile unsigned int*)(0x42A820ACUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN4 (*((volatile unsigned int*)(0x42A820B0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN5 (*((volatile unsigned int*)(0x42A820B4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN6 (*((volatile unsigned int*)(0x42A820B8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN7 (*((volatile unsigned int*)(0x42A820BCUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN8 (*((volatile unsigned int*)(0x42A820C0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR0 (*((volatile unsigned int*)(0x42A820D0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR1 (*((volatile unsigned int*)(0x42A820D4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR2 (*((volatile unsigned int*)(0x42A820D8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR3 (*((volatile unsigned int*)(0x42A820DCUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ0 (*((volatile unsigned int*)(0x42A820E0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ1 (*((volatile unsigned int*)(0x42A820E4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ2 (*((volatile unsigned int*)(0x42A820E8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ3 (*((volatile unsigned int*)(0x42A820ECUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP0 (*((volatile unsigned int*)(0x42A820F0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP1 (*((volatile unsigned int*)(0x42A820F4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP2 (*((volatile unsigned int*)(0x42A820F8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP3 (*((volatile unsigned int*)(0x42A820FCUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB0 (*((volatile unsigned int*)(0x42A87FC0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB1 (*((volatile unsigned int*)(0x42A87FC4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB2 (*((volatile unsigned int*)(0x42A87FC8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB3 (*((volatile unsigned int*)(0x42A87FCCUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE0 (*((volatile unsigned int*)(0x42A87FE0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE1 (*((volatile unsigned int*)(0x42A87FE4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE2 (*((volatile unsigned int*)(0x42A87FE8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE3 (*((volatile unsigned int*)(0x42A87FECUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE4 (*((volatile unsigned int*)(0x42A87FF0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE5 (*((volatile unsigned int*)(0x42A87FF4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE6 (*((volatile unsigned int*)(0x42A87FF8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE7 (*((volatile unsigned int*)(0x42A87FFCUL))) +#define bM4_SYSREG_PWR_PWRC0_PDMDS0 (*((volatile unsigned int*)(0x42A88000UL))) +#define bM4_SYSREG_PWR_PWRC0_PDMDS1 (*((volatile unsigned int*)(0x42A88004UL))) +#define bM4_SYSREG_PWR_PWRC0_VVDRSD (*((volatile unsigned int*)(0x42A88008UL))) +#define bM4_SYSREG_PWR_PWRC0_RETRAMSD (*((volatile unsigned int*)(0x42A8800CUL))) +#define bM4_SYSREG_PWR_PWRC0_IORTN0 (*((volatile unsigned int*)(0x42A88010UL))) +#define bM4_SYSREG_PWR_PWRC0_IORTN1 (*((volatile unsigned int*)(0x42A88014UL))) +#define bM4_SYSREG_PWR_PWRC0_PWDN (*((volatile unsigned int*)(0x42A8801CUL))) +#define bM4_SYSREG_PWR_PWRC1_VPLLSD (*((volatile unsigned int*)(0x42A88020UL))) +#define bM4_SYSREG_PWR_PWRC1_VHRCSD (*((volatile unsigned int*)(0x42A88024UL))) +#define bM4_SYSREG_PWR_PWRC1_STPDAS0 (*((volatile unsigned int*)(0x42A88038UL))) +#define bM4_SYSREG_PWR_PWRC1_STPDAS1 (*((volatile unsigned int*)(0x42A8803CUL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS0 (*((volatile unsigned int*)(0x42A88040UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS1 (*((volatile unsigned int*)(0x42A88044UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS2 (*((volatile unsigned int*)(0x42A88048UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS3 (*((volatile unsigned int*)(0x42A8804CUL))) +#define bM4_SYSREG_PWR_PWRC2_DVS0 (*((volatile unsigned int*)(0x42A88050UL))) +#define bM4_SYSREG_PWR_PWRC2_DVS1 (*((volatile unsigned int*)(0x42A88054UL))) +#define bM4_SYSREG_PWR_PWRC3_PDTS (*((volatile unsigned int*)(0x42A88068UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE00 (*((volatile unsigned int*)(0x42A88080UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE01 (*((volatile unsigned int*)(0x42A88084UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE02 (*((volatile unsigned int*)(0x42A88088UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE03 (*((volatile unsigned int*)(0x42A8808CUL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE10 (*((volatile unsigned int*)(0x42A88090UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE11 (*((volatile unsigned int*)(0x42A88094UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE12 (*((volatile unsigned int*)(0x42A88098UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE13 (*((volatile unsigned int*)(0x42A8809CUL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE20 (*((volatile unsigned int*)(0x42A880A0UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE21 (*((volatile unsigned int*)(0x42A880A4UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE22 (*((volatile unsigned int*)(0x42A880A8UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE23 (*((volatile unsigned int*)(0x42A880ACUL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE30 (*((volatile unsigned int*)(0x42A880B0UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE31 (*((volatile unsigned int*)(0x42A880B4UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE32 (*((volatile unsigned int*)(0x42A880B8UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE33 (*((volatile unsigned int*)(0x42A880BCUL))) +#define bM4_SYSREG_PWR_PDWKE2_VD1WKE (*((volatile unsigned int*)(0x42A880C0UL))) +#define bM4_SYSREG_PWR_PDWKE2_VD2WKE (*((volatile unsigned int*)(0x42A880C4UL))) +#define bM4_SYSREG_PWR_PDWKE2_NMIWKE (*((volatile unsigned int*)(0x42A880C8UL))) +#define bM4_SYSREG_PWR_PDWKE2_RTCPRDWKE (*((volatile unsigned int*)(0x42A880D0UL))) +#define bM4_SYSREG_PWR_PDWKE2_RTCALMWKE (*((volatile unsigned int*)(0x42A880D4UL))) +#define bM4_SYSREG_PWR_PDWKE2_WKTMWKE (*((volatile unsigned int*)(0x42A880DCUL))) +#define bM4_SYSREG_PWR_PDWKES_WK0EGS (*((volatile unsigned int*)(0x42A880E0UL))) +#define bM4_SYSREG_PWR_PDWKES_WK1EGS (*((volatile unsigned int*)(0x42A880E4UL))) +#define bM4_SYSREG_PWR_PDWKES_WK2EGS (*((volatile unsigned int*)(0x42A880E8UL))) +#define bM4_SYSREG_PWR_PDWKES_WK3EGS (*((volatile unsigned int*)(0x42A880ECUL))) +#define bM4_SYSREG_PWR_PDWKES_VD1EGS (*((volatile unsigned int*)(0x42A880F0UL))) +#define bM4_SYSREG_PWR_PDWKES_VD2EGS (*((volatile unsigned int*)(0x42A880F4UL))) +#define bM4_SYSREG_PWR_PDWKES_NMIEGS (*((volatile unsigned int*)(0x42A880F8UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK0F (*((volatile unsigned int*)(0x42A88100UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK1F (*((volatile unsigned int*)(0x42A88104UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK2F (*((volatile unsigned int*)(0x42A88108UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK3F (*((volatile unsigned int*)(0x42A8810CUL))) +#define bM4_SYSREG_PWR_PDWKF0_VD1WKF (*((volatile unsigned int*)(0x42A88110UL))) +#define bM4_SYSREG_PWR_PDWKF0_VD2WKF (*((volatile unsigned int*)(0x42A88114UL))) +#define bM4_SYSREG_PWR_PDWKF0_NMIWKF (*((volatile unsigned int*)(0x42A88118UL))) +#define bM4_SYSREG_PWR_PDWKF1_RTCPRDWKF (*((volatile unsigned int*)(0x42A88130UL))) +#define bM4_SYSREG_PWR_PDWKF1_RTCALMWKF (*((volatile unsigned int*)(0x42A88134UL))) +#define bM4_SYSREG_PWR_PDWKF1_WKTMWKF (*((volatile unsigned int*)(0x42A8813CUL))) +#define bM4_SYSREG_PWR_PWCMR_ADBUFE (*((volatile unsigned int*)(0x42A8815CUL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALDRV0 (*((volatile unsigned int*)(0x42A88210UL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALDRV1 (*((volatile unsigned int*)(0x42A88214UL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALMS (*((volatile unsigned int*)(0x42A88218UL))) +#define bM4_SYSREG_CMU_XTALCFGR_SUPDRV (*((volatile unsigned int*)(0x42A8821CUL))) +#define bM4_SYSREG_PWR_PVDCR0_EXVCCINEN (*((volatile unsigned int*)(0x42A88240UL))) +#define bM4_SYSREG_PWR_PVDCR0_PVD1EN (*((volatile unsigned int*)(0x42A88254UL))) +#define bM4_SYSREG_PWR_PVDCR0_PVD2EN (*((volatile unsigned int*)(0x42A88258UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1IRE (*((volatile unsigned int*)(0x42A88260UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1IRS (*((volatile unsigned int*)(0x42A88264UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1CMPOE (*((volatile unsigned int*)(0x42A88268UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2IRE (*((volatile unsigned int*)(0x42A88270UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2IRS (*((volatile unsigned int*)(0x42A88274UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2CMPOE (*((volatile unsigned int*)(0x42A88278UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFDIS (*((volatile unsigned int*)(0x42A88280UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFCKS0 (*((volatile unsigned int*)(0x42A88284UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFCKS1 (*((volatile unsigned int*)(0x42A88288UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFDIS (*((volatile unsigned int*)(0x42A88290UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFCKS0 (*((volatile unsigned int*)(0x42A88294UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFCKS1 (*((volatile unsigned int*)(0x42A88298UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL0 (*((volatile unsigned int*)(0x42A882A0UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL1 (*((volatile unsigned int*)(0x42A882A4UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL2 (*((volatile unsigned int*)(0x42A882A8UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL0 (*((volatile unsigned int*)(0x42A882B0UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL1 (*((volatile unsigned int*)(0x42A882B4UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL2 (*((volatile unsigned int*)(0x42A882B8UL))) +#define bM4_SYSREG_CMU_XTAL32CR_XTAL32STP (*((volatile unsigned int*)(0x42A88400UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV0 (*((volatile unsigned int*)(0x42A88420UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV1 (*((volatile unsigned int*)(0x42A88424UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV2 (*((volatile unsigned int*)(0x42A88428UL))) +#define bM4_SYSREG_CMU_XTAL32NFR_XTAL32NF0 (*((volatile unsigned int*)(0x42A884A0UL))) +#define bM4_SYSREG_CMU_XTAL32NFR_XTAL32NF1 (*((volatile unsigned int*)(0x42A884A4UL))) +#define bM4_SYSREG_CMU_LRCCR_LRCSTP (*((volatile unsigned int*)(0x42A884E0UL))) +#define bM4_SYSREG_PWR_XTAL32CS_CSDIS (*((volatile unsigned int*)(0x42A8857CUL))) +#define bM4_TMR01_CNTAR_CNTA0 (*((volatile unsigned int*)(0x42480000UL))) +#define bM4_TMR01_CNTAR_CNTA1 (*((volatile unsigned int*)(0x42480004UL))) +#define bM4_TMR01_CNTAR_CNTA2 (*((volatile unsigned int*)(0x42480008UL))) +#define bM4_TMR01_CNTAR_CNTA3 (*((volatile unsigned int*)(0x4248000CUL))) +#define bM4_TMR01_CNTAR_CNTA4 (*((volatile unsigned int*)(0x42480010UL))) +#define bM4_TMR01_CNTAR_CNTA5 (*((volatile unsigned int*)(0x42480014UL))) +#define bM4_TMR01_CNTAR_CNTA6 (*((volatile unsigned int*)(0x42480018UL))) +#define bM4_TMR01_CNTAR_CNTA7 (*((volatile unsigned int*)(0x4248001CUL))) +#define bM4_TMR01_CNTAR_CNTA8 (*((volatile unsigned int*)(0x42480020UL))) +#define bM4_TMR01_CNTAR_CNTA9 (*((volatile unsigned int*)(0x42480024UL))) +#define bM4_TMR01_CNTAR_CNTA10 (*((volatile unsigned int*)(0x42480028UL))) +#define bM4_TMR01_CNTAR_CNTA11 (*((volatile unsigned int*)(0x4248002CUL))) +#define bM4_TMR01_CNTAR_CNTA12 (*((volatile unsigned int*)(0x42480030UL))) +#define bM4_TMR01_CNTAR_CNTA13 (*((volatile unsigned int*)(0x42480034UL))) +#define bM4_TMR01_CNTAR_CNTA14 (*((volatile unsigned int*)(0x42480038UL))) +#define bM4_TMR01_CNTAR_CNTA15 (*((volatile unsigned int*)(0x4248003CUL))) +#define bM4_TMR01_CNTBR_CNTB0 (*((volatile unsigned int*)(0x42480080UL))) +#define bM4_TMR01_CNTBR_CNTB1 (*((volatile unsigned int*)(0x42480084UL))) +#define bM4_TMR01_CNTBR_CNTB2 (*((volatile unsigned int*)(0x42480088UL))) +#define bM4_TMR01_CNTBR_CNTB3 (*((volatile unsigned int*)(0x4248008CUL))) +#define bM4_TMR01_CNTBR_CNTB4 (*((volatile unsigned int*)(0x42480090UL))) +#define bM4_TMR01_CNTBR_CNTB5 (*((volatile unsigned int*)(0x42480094UL))) +#define bM4_TMR01_CNTBR_CNTB6 (*((volatile unsigned int*)(0x42480098UL))) +#define bM4_TMR01_CNTBR_CNTB7 (*((volatile unsigned int*)(0x4248009CUL))) +#define bM4_TMR01_CNTBR_CNTB8 (*((volatile unsigned int*)(0x424800A0UL))) +#define bM4_TMR01_CNTBR_CNTB9 (*((volatile unsigned int*)(0x424800A4UL))) +#define bM4_TMR01_CNTBR_CNTB10 (*((volatile unsigned int*)(0x424800A8UL))) +#define bM4_TMR01_CNTBR_CNTB11 (*((volatile unsigned int*)(0x424800ACUL))) +#define bM4_TMR01_CNTBR_CNTB12 (*((volatile unsigned int*)(0x424800B0UL))) +#define bM4_TMR01_CNTBR_CNTB13 (*((volatile unsigned int*)(0x424800B4UL))) +#define bM4_TMR01_CNTBR_CNTB14 (*((volatile unsigned int*)(0x424800B8UL))) +#define bM4_TMR01_CNTBR_CNTB15 (*((volatile unsigned int*)(0x424800BCUL))) +#define bM4_TMR01_CMPAR_CMPA0 (*((volatile unsigned int*)(0x42480100UL))) +#define bM4_TMR01_CMPAR_CMPA1 (*((volatile unsigned int*)(0x42480104UL))) +#define bM4_TMR01_CMPAR_CMPA2 (*((volatile unsigned int*)(0x42480108UL))) +#define bM4_TMR01_CMPAR_CMPA3 (*((volatile unsigned int*)(0x4248010CUL))) +#define bM4_TMR01_CMPAR_CMPA4 (*((volatile unsigned int*)(0x42480110UL))) +#define bM4_TMR01_CMPAR_CMPA5 (*((volatile unsigned int*)(0x42480114UL))) +#define bM4_TMR01_CMPAR_CMPA6 (*((volatile unsigned int*)(0x42480118UL))) +#define bM4_TMR01_CMPAR_CMPA7 (*((volatile unsigned int*)(0x4248011CUL))) +#define bM4_TMR01_CMPAR_CMPA8 (*((volatile unsigned int*)(0x42480120UL))) +#define bM4_TMR01_CMPAR_CMPA9 (*((volatile unsigned int*)(0x42480124UL))) +#define bM4_TMR01_CMPAR_CMPA10 (*((volatile unsigned int*)(0x42480128UL))) +#define bM4_TMR01_CMPAR_CMPA11 (*((volatile unsigned int*)(0x4248012CUL))) +#define bM4_TMR01_CMPAR_CMPA12 (*((volatile unsigned int*)(0x42480130UL))) +#define bM4_TMR01_CMPAR_CMPA13 (*((volatile unsigned int*)(0x42480134UL))) +#define bM4_TMR01_CMPAR_CMPA14 (*((volatile unsigned int*)(0x42480138UL))) +#define bM4_TMR01_CMPAR_CMPA15 (*((volatile unsigned int*)(0x4248013CUL))) +#define bM4_TMR01_CMPBR_CMPB0 (*((volatile unsigned int*)(0x42480180UL))) +#define bM4_TMR01_CMPBR_CMPB1 (*((volatile unsigned int*)(0x42480184UL))) +#define bM4_TMR01_CMPBR_CMPB2 (*((volatile unsigned int*)(0x42480188UL))) +#define bM4_TMR01_CMPBR_CMPB3 (*((volatile unsigned int*)(0x4248018CUL))) +#define bM4_TMR01_CMPBR_CMPB4 (*((volatile unsigned int*)(0x42480190UL))) +#define bM4_TMR01_CMPBR_CMPB5 (*((volatile unsigned int*)(0x42480194UL))) +#define bM4_TMR01_CMPBR_CMPB6 (*((volatile unsigned int*)(0x42480198UL))) +#define bM4_TMR01_CMPBR_CMPB7 (*((volatile unsigned int*)(0x4248019CUL))) +#define bM4_TMR01_CMPBR_CMPB8 (*((volatile unsigned int*)(0x424801A0UL))) +#define bM4_TMR01_CMPBR_CMPB9 (*((volatile unsigned int*)(0x424801A4UL))) +#define bM4_TMR01_CMPBR_CMPB10 (*((volatile unsigned int*)(0x424801A8UL))) +#define bM4_TMR01_CMPBR_CMPB11 (*((volatile unsigned int*)(0x424801ACUL))) +#define bM4_TMR01_CMPBR_CMPB12 (*((volatile unsigned int*)(0x424801B0UL))) +#define bM4_TMR01_CMPBR_CMPB13 (*((volatile unsigned int*)(0x424801B4UL))) +#define bM4_TMR01_CMPBR_CMPB14 (*((volatile unsigned int*)(0x424801B8UL))) +#define bM4_TMR01_CMPBR_CMPB15 (*((volatile unsigned int*)(0x424801BCUL))) +#define bM4_TMR01_BCONR_CSTA (*((volatile unsigned int*)(0x42480200UL))) +#define bM4_TMR01_BCONR_CAPMDA (*((volatile unsigned int*)(0x42480204UL))) +#define bM4_TMR01_BCONR_INTENA (*((volatile unsigned int*)(0x42480208UL))) +#define bM4_TMR01_BCONR_CKDIVA0 (*((volatile unsigned int*)(0x42480210UL))) +#define bM4_TMR01_BCONR_CKDIVA1 (*((volatile unsigned int*)(0x42480214UL))) +#define bM4_TMR01_BCONR_CKDIVA2 (*((volatile unsigned int*)(0x42480218UL))) +#define bM4_TMR01_BCONR_CKDIVA3 (*((volatile unsigned int*)(0x4248021CUL))) +#define bM4_TMR01_BCONR_SYNSA (*((volatile unsigned int*)(0x42480220UL))) +#define bM4_TMR01_BCONR_SYNCLKA (*((volatile unsigned int*)(0x42480224UL))) +#define bM4_TMR01_BCONR_ASYNCLKA (*((volatile unsigned int*)(0x42480228UL))) +#define bM4_TMR01_BCONR_HSTAA (*((volatile unsigned int*)(0x42480230UL))) +#define bM4_TMR01_BCONR_HSTPA (*((volatile unsigned int*)(0x42480234UL))) +#define bM4_TMR01_BCONR_HCLEA (*((volatile unsigned int*)(0x42480238UL))) +#define bM4_TMR01_BCONR_HICPA (*((volatile unsigned int*)(0x4248023CUL))) +#define bM4_TMR01_BCONR_CSTB (*((volatile unsigned int*)(0x42480240UL))) +#define bM4_TMR01_BCONR_CAPMDB (*((volatile unsigned int*)(0x42480244UL))) +#define bM4_TMR01_BCONR_INTENB (*((volatile unsigned int*)(0x42480248UL))) +#define bM4_TMR01_BCONR_CKDIVB0 (*((volatile unsigned int*)(0x42480250UL))) +#define bM4_TMR01_BCONR_CKDIVB1 (*((volatile unsigned int*)(0x42480254UL))) +#define bM4_TMR01_BCONR_CKDIVB2 (*((volatile unsigned int*)(0x42480258UL))) +#define bM4_TMR01_BCONR_CKDIVB3 (*((volatile unsigned int*)(0x4248025CUL))) +#define bM4_TMR01_BCONR_SYNSB (*((volatile unsigned int*)(0x42480260UL))) +#define bM4_TMR01_BCONR_SYNCLKB (*((volatile unsigned int*)(0x42480264UL))) +#define bM4_TMR01_BCONR_ASYNCLKB (*((volatile unsigned int*)(0x42480268UL))) +#define bM4_TMR01_BCONR_HSTAB (*((volatile unsigned int*)(0x42480270UL))) +#define bM4_TMR01_BCONR_HSTPB (*((volatile unsigned int*)(0x42480274UL))) +#define bM4_TMR01_BCONR_HCLEB (*((volatile unsigned int*)(0x42480278UL))) +#define bM4_TMR01_BCONR_HICPB (*((volatile unsigned int*)(0x4248027CUL))) +#define bM4_TMR01_STFLR_CMAF (*((volatile unsigned int*)(0x42480280UL))) +#define bM4_TMR01_STFLR_CMBF (*((volatile unsigned int*)(0x424802C0UL))) +#define bM4_TMR02_CNTAR_CNTA0 (*((volatile unsigned int*)(0x42488000UL))) +#define bM4_TMR02_CNTAR_CNTA1 (*((volatile unsigned int*)(0x42488004UL))) +#define bM4_TMR02_CNTAR_CNTA2 (*((volatile unsigned int*)(0x42488008UL))) +#define bM4_TMR02_CNTAR_CNTA3 (*((volatile unsigned int*)(0x4248800CUL))) +#define bM4_TMR02_CNTAR_CNTA4 (*((volatile unsigned int*)(0x42488010UL))) +#define bM4_TMR02_CNTAR_CNTA5 (*((volatile unsigned int*)(0x42488014UL))) +#define bM4_TMR02_CNTAR_CNTA6 (*((volatile unsigned int*)(0x42488018UL))) +#define bM4_TMR02_CNTAR_CNTA7 (*((volatile unsigned int*)(0x4248801CUL))) +#define bM4_TMR02_CNTAR_CNTA8 (*((volatile unsigned int*)(0x42488020UL))) +#define bM4_TMR02_CNTAR_CNTA9 (*((volatile unsigned int*)(0x42488024UL))) +#define bM4_TMR02_CNTAR_CNTA10 (*((volatile unsigned int*)(0x42488028UL))) +#define bM4_TMR02_CNTAR_CNTA11 (*((volatile unsigned int*)(0x4248802CUL))) +#define bM4_TMR02_CNTAR_CNTA12 (*((volatile unsigned int*)(0x42488030UL))) +#define bM4_TMR02_CNTAR_CNTA13 (*((volatile unsigned int*)(0x42488034UL))) +#define bM4_TMR02_CNTAR_CNTA14 (*((volatile unsigned int*)(0x42488038UL))) +#define bM4_TMR02_CNTAR_CNTA15 (*((volatile unsigned int*)(0x4248803CUL))) +#define bM4_TMR02_CNTBR_CNTB0 (*((volatile unsigned int*)(0x42488080UL))) +#define bM4_TMR02_CNTBR_CNTB1 (*((volatile unsigned int*)(0x42488084UL))) +#define bM4_TMR02_CNTBR_CNTB2 (*((volatile unsigned int*)(0x42488088UL))) +#define bM4_TMR02_CNTBR_CNTB3 (*((volatile unsigned int*)(0x4248808CUL))) +#define bM4_TMR02_CNTBR_CNTB4 (*((volatile unsigned int*)(0x42488090UL))) +#define bM4_TMR02_CNTBR_CNTB5 (*((volatile unsigned int*)(0x42488094UL))) +#define bM4_TMR02_CNTBR_CNTB6 (*((volatile unsigned int*)(0x42488098UL))) +#define bM4_TMR02_CNTBR_CNTB7 (*((volatile unsigned int*)(0x4248809CUL))) +#define bM4_TMR02_CNTBR_CNTB8 (*((volatile unsigned int*)(0x424880A0UL))) +#define bM4_TMR02_CNTBR_CNTB9 (*((volatile unsigned int*)(0x424880A4UL))) +#define bM4_TMR02_CNTBR_CNTB10 (*((volatile unsigned int*)(0x424880A8UL))) +#define bM4_TMR02_CNTBR_CNTB11 (*((volatile unsigned int*)(0x424880ACUL))) +#define bM4_TMR02_CNTBR_CNTB12 (*((volatile unsigned int*)(0x424880B0UL))) +#define bM4_TMR02_CNTBR_CNTB13 (*((volatile unsigned int*)(0x424880B4UL))) +#define bM4_TMR02_CNTBR_CNTB14 (*((volatile unsigned int*)(0x424880B8UL))) +#define bM4_TMR02_CNTBR_CNTB15 (*((volatile unsigned int*)(0x424880BCUL))) +#define bM4_TMR02_CMPAR_CMPA0 (*((volatile unsigned int*)(0x42488100UL))) +#define bM4_TMR02_CMPAR_CMPA1 (*((volatile unsigned int*)(0x42488104UL))) +#define bM4_TMR02_CMPAR_CMPA2 (*((volatile unsigned int*)(0x42488108UL))) +#define bM4_TMR02_CMPAR_CMPA3 (*((volatile unsigned int*)(0x4248810CUL))) +#define bM4_TMR02_CMPAR_CMPA4 (*((volatile unsigned int*)(0x42488110UL))) +#define bM4_TMR02_CMPAR_CMPA5 (*((volatile unsigned int*)(0x42488114UL))) +#define bM4_TMR02_CMPAR_CMPA6 (*((volatile unsigned int*)(0x42488118UL))) +#define bM4_TMR02_CMPAR_CMPA7 (*((volatile unsigned int*)(0x4248811CUL))) +#define bM4_TMR02_CMPAR_CMPA8 (*((volatile unsigned int*)(0x42488120UL))) +#define bM4_TMR02_CMPAR_CMPA9 (*((volatile unsigned int*)(0x42488124UL))) +#define bM4_TMR02_CMPAR_CMPA10 (*((volatile unsigned int*)(0x42488128UL))) +#define bM4_TMR02_CMPAR_CMPA11 (*((volatile unsigned int*)(0x4248812CUL))) +#define bM4_TMR02_CMPAR_CMPA12 (*((volatile unsigned int*)(0x42488130UL))) +#define bM4_TMR02_CMPAR_CMPA13 (*((volatile unsigned int*)(0x42488134UL))) +#define bM4_TMR02_CMPAR_CMPA14 (*((volatile unsigned int*)(0x42488138UL))) +#define bM4_TMR02_CMPAR_CMPA15 (*((volatile unsigned int*)(0x4248813CUL))) +#define bM4_TMR02_CMPBR_CMPB0 (*((volatile unsigned int*)(0x42488180UL))) +#define bM4_TMR02_CMPBR_CMPB1 (*((volatile unsigned int*)(0x42488184UL))) +#define bM4_TMR02_CMPBR_CMPB2 (*((volatile unsigned int*)(0x42488188UL))) +#define bM4_TMR02_CMPBR_CMPB3 (*((volatile unsigned int*)(0x4248818CUL))) +#define bM4_TMR02_CMPBR_CMPB4 (*((volatile unsigned int*)(0x42488190UL))) +#define bM4_TMR02_CMPBR_CMPB5 (*((volatile unsigned int*)(0x42488194UL))) +#define bM4_TMR02_CMPBR_CMPB6 (*((volatile unsigned int*)(0x42488198UL))) +#define bM4_TMR02_CMPBR_CMPB7 (*((volatile unsigned int*)(0x4248819CUL))) +#define bM4_TMR02_CMPBR_CMPB8 (*((volatile unsigned int*)(0x424881A0UL))) +#define bM4_TMR02_CMPBR_CMPB9 (*((volatile unsigned int*)(0x424881A4UL))) +#define bM4_TMR02_CMPBR_CMPB10 (*((volatile unsigned int*)(0x424881A8UL))) +#define bM4_TMR02_CMPBR_CMPB11 (*((volatile unsigned int*)(0x424881ACUL))) +#define bM4_TMR02_CMPBR_CMPB12 (*((volatile unsigned int*)(0x424881B0UL))) +#define bM4_TMR02_CMPBR_CMPB13 (*((volatile unsigned int*)(0x424881B4UL))) +#define bM4_TMR02_CMPBR_CMPB14 (*((volatile unsigned int*)(0x424881B8UL))) +#define bM4_TMR02_CMPBR_CMPB15 (*((volatile unsigned int*)(0x424881BCUL))) +#define bM4_TMR02_BCONR_CSTA (*((volatile unsigned int*)(0x42488200UL))) +#define bM4_TMR02_BCONR_CAPMDA (*((volatile unsigned int*)(0x42488204UL))) +#define bM4_TMR02_BCONR_INTENA (*((volatile unsigned int*)(0x42488208UL))) +#define bM4_TMR02_BCONR_CKDIVA0 (*((volatile unsigned int*)(0x42488210UL))) +#define bM4_TMR02_BCONR_CKDIVA1 (*((volatile unsigned int*)(0x42488214UL))) +#define bM4_TMR02_BCONR_CKDIVA2 (*((volatile unsigned int*)(0x42488218UL))) +#define bM4_TMR02_BCONR_CKDIVA3 (*((volatile unsigned int*)(0x4248821CUL))) +#define bM4_TMR02_BCONR_SYNSA (*((volatile unsigned int*)(0x42488220UL))) +#define bM4_TMR02_BCONR_SYNCLKA (*((volatile unsigned int*)(0x42488224UL))) +#define bM4_TMR02_BCONR_ASYNCLKA (*((volatile unsigned int*)(0x42488228UL))) +#define bM4_TMR02_BCONR_HSTAA (*((volatile unsigned int*)(0x42488230UL))) +#define bM4_TMR02_BCONR_HSTPA (*((volatile unsigned int*)(0x42488234UL))) +#define bM4_TMR02_BCONR_HCLEA (*((volatile unsigned int*)(0x42488238UL))) +#define bM4_TMR02_BCONR_HICPA (*((volatile unsigned int*)(0x4248823CUL))) +#define bM4_TMR02_BCONR_CSTB (*((volatile unsigned int*)(0x42488240UL))) +#define bM4_TMR02_BCONR_CAPMDB (*((volatile unsigned int*)(0x42488244UL))) +#define bM4_TMR02_BCONR_INTENB (*((volatile unsigned int*)(0x42488248UL))) +#define bM4_TMR02_BCONR_CKDIVB0 (*((volatile unsigned int*)(0x42488250UL))) +#define bM4_TMR02_BCONR_CKDIVB1 (*((volatile unsigned int*)(0x42488254UL))) +#define bM4_TMR02_BCONR_CKDIVB2 (*((volatile unsigned int*)(0x42488258UL))) +#define bM4_TMR02_BCONR_CKDIVB3 (*((volatile unsigned int*)(0x4248825CUL))) +#define bM4_TMR02_BCONR_SYNSB (*((volatile unsigned int*)(0x42488260UL))) +#define bM4_TMR02_BCONR_SYNCLKB (*((volatile unsigned int*)(0x42488264UL))) +#define bM4_TMR02_BCONR_ASYNCLKB (*((volatile unsigned int*)(0x42488268UL))) +#define bM4_TMR02_BCONR_HSTAB (*((volatile unsigned int*)(0x42488270UL))) +#define bM4_TMR02_BCONR_HSTPB (*((volatile unsigned int*)(0x42488274UL))) +#define bM4_TMR02_BCONR_HCLEB (*((volatile unsigned int*)(0x42488278UL))) +#define bM4_TMR02_BCONR_HICPB (*((volatile unsigned int*)(0x4248827CUL))) +#define bM4_TMR02_STFLR_CMAF (*((volatile unsigned int*)(0x42488280UL))) +#define bM4_TMR02_STFLR_CMBF (*((volatile unsigned int*)(0x424882C0UL))) +#define bM4_TMR41_OCSRU_OCEH (*((volatile unsigned int*)(0x422E0300UL))) +#define bM4_TMR41_OCSRU_OCEL (*((volatile unsigned int*)(0x422E0304UL))) +#define bM4_TMR41_OCSRU_OCPH (*((volatile unsigned int*)(0x422E0308UL))) +#define bM4_TMR41_OCSRU_OCPL (*((volatile unsigned int*)(0x422E030CUL))) +#define bM4_TMR41_OCSRU_OCIEH (*((volatile unsigned int*)(0x422E0310UL))) +#define bM4_TMR41_OCSRU_OCIEL (*((volatile unsigned int*)(0x422E0314UL))) +#define bM4_TMR41_OCSRU_OCFH (*((volatile unsigned int*)(0x422E0318UL))) +#define bM4_TMR41_OCSRU_OCFL (*((volatile unsigned int*)(0x422E031CUL))) +#define bM4_TMR41_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x422E0340UL))) +#define bM4_TMR41_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x422E0344UL))) +#define bM4_TMR41_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x422E0348UL))) +#define bM4_TMR41_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x422E034CUL))) +#define bM4_TMR41_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x422E0350UL))) +#define bM4_TMR41_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x422E0354UL))) +#define bM4_TMR41_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x422E0358UL))) +#define bM4_TMR41_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x422E035CUL))) +#define bM4_TMR41_OCERU_LMCH (*((volatile unsigned int*)(0x422E0360UL))) +#define bM4_TMR41_OCERU_LMCL (*((volatile unsigned int*)(0x422E0364UL))) +#define bM4_TMR41_OCERU_LMMH (*((volatile unsigned int*)(0x422E0368UL))) +#define bM4_TMR41_OCERU_LMML (*((volatile unsigned int*)(0x422E036CUL))) +#define bM4_TMR41_OCERU_MCECH (*((volatile unsigned int*)(0x422E0370UL))) +#define bM4_TMR41_OCERU_MCECL (*((volatile unsigned int*)(0x422E0374UL))) +#define bM4_TMR41_OCSRV_OCEH (*((volatile unsigned int*)(0x422E0380UL))) +#define bM4_TMR41_OCSRV_OCEL (*((volatile unsigned int*)(0x422E0384UL))) +#define bM4_TMR41_OCSRV_OCPH (*((volatile unsigned int*)(0x422E0388UL))) +#define bM4_TMR41_OCSRV_OCPL (*((volatile unsigned int*)(0x422E038CUL))) +#define bM4_TMR41_OCSRV_OCIEH (*((volatile unsigned int*)(0x422E0390UL))) +#define bM4_TMR41_OCSRV_OCIEL (*((volatile unsigned int*)(0x422E0394UL))) +#define bM4_TMR41_OCSRV_OCFH (*((volatile unsigned int*)(0x422E0398UL))) +#define bM4_TMR41_OCSRV_OCFL (*((volatile unsigned int*)(0x422E039CUL))) +#define bM4_TMR41_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x422E03C0UL))) +#define bM4_TMR41_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x422E03C4UL))) +#define bM4_TMR41_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x422E03C8UL))) +#define bM4_TMR41_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x422E03CCUL))) +#define bM4_TMR41_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x422E03D0UL))) +#define bM4_TMR41_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x422E03D4UL))) +#define bM4_TMR41_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x422E03D8UL))) +#define bM4_TMR41_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x422E03DCUL))) +#define bM4_TMR41_OCERV_LMCH (*((volatile unsigned int*)(0x422E03E0UL))) +#define bM4_TMR41_OCERV_LMCL (*((volatile unsigned int*)(0x422E03E4UL))) +#define bM4_TMR41_OCERV_LMMH (*((volatile unsigned int*)(0x422E03E8UL))) +#define bM4_TMR41_OCERV_LMML (*((volatile unsigned int*)(0x422E03ECUL))) +#define bM4_TMR41_OCERV_MCECH (*((volatile unsigned int*)(0x422E03F0UL))) +#define bM4_TMR41_OCERV_MCECL (*((volatile unsigned int*)(0x422E03F4UL))) +#define bM4_TMR41_OCSRW_OCEH (*((volatile unsigned int*)(0x422E0400UL))) +#define bM4_TMR41_OCSRW_OCEL (*((volatile unsigned int*)(0x422E0404UL))) +#define bM4_TMR41_OCSRW_OCPH (*((volatile unsigned int*)(0x422E0408UL))) +#define bM4_TMR41_OCSRW_OCPL (*((volatile unsigned int*)(0x422E040CUL))) +#define bM4_TMR41_OCSRW_OCIEH (*((volatile unsigned int*)(0x422E0410UL))) +#define bM4_TMR41_OCSRW_OCIEL (*((volatile unsigned int*)(0x422E0414UL))) +#define bM4_TMR41_OCSRW_OCFH (*((volatile unsigned int*)(0x422E0418UL))) +#define bM4_TMR41_OCSRW_OCFL (*((volatile unsigned int*)(0x422E041CUL))) +#define bM4_TMR41_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x422E0440UL))) +#define bM4_TMR41_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x422E0444UL))) +#define bM4_TMR41_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x422E0448UL))) +#define bM4_TMR41_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x422E044CUL))) +#define bM4_TMR41_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x422E0450UL))) +#define bM4_TMR41_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x422E0454UL))) +#define bM4_TMR41_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x422E0458UL))) +#define bM4_TMR41_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x422E045CUL))) +#define bM4_TMR41_OCERW_LMCH (*((volatile unsigned int*)(0x422E0460UL))) +#define bM4_TMR41_OCERW_LMCL (*((volatile unsigned int*)(0x422E0464UL))) +#define bM4_TMR41_OCERW_LMMH (*((volatile unsigned int*)(0x422E0468UL))) +#define bM4_TMR41_OCERW_LMML (*((volatile unsigned int*)(0x422E046CUL))) +#define bM4_TMR41_OCERW_MCECH (*((volatile unsigned int*)(0x422E0470UL))) +#define bM4_TMR41_OCERW_MCECL (*((volatile unsigned int*)(0x422E0474UL))) +#define bM4_TMR41_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x422E0480UL))) +#define bM4_TMR41_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x422E0484UL))) +#define bM4_TMR41_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x422E0488UL))) +#define bM4_TMR41_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x422E048CUL))) +#define bM4_TMR41_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x422E0490UL))) +#define bM4_TMR41_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x422E0494UL))) +#define bM4_TMR41_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x422E0498UL))) +#define bM4_TMR41_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x422E049CUL))) +#define bM4_TMR41_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x422E04A0UL))) +#define bM4_TMR41_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x422E04A4UL))) +#define bM4_TMR41_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x422E04A8UL))) +#define bM4_TMR41_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x422E04ACUL))) +#define bM4_TMR41_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x422E04B0UL))) +#define bM4_TMR41_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x422E04B4UL))) +#define bM4_TMR41_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x422E04B8UL))) +#define bM4_TMR41_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x422E04BCUL))) +#define bM4_TMR41_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x422E0500UL))) +#define bM4_TMR41_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x422E0504UL))) +#define bM4_TMR41_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x422E0508UL))) +#define bM4_TMR41_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x422E050CUL))) +#define bM4_TMR41_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x422E0510UL))) +#define bM4_TMR41_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x422E0514UL))) +#define bM4_TMR41_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x422E0518UL))) +#define bM4_TMR41_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x422E051CUL))) +#define bM4_TMR41_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x422E0520UL))) +#define bM4_TMR41_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x422E0524UL))) +#define bM4_TMR41_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x422E0528UL))) +#define bM4_TMR41_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x422E052CUL))) +#define bM4_TMR41_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x422E0530UL))) +#define bM4_TMR41_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x422E0534UL))) +#define bM4_TMR41_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x422E0538UL))) +#define bM4_TMR41_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x422E053CUL))) +#define bM4_TMR41_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0540UL))) +#define bM4_TMR41_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0544UL))) +#define bM4_TMR41_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0548UL))) +#define bM4_TMR41_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x422E054CUL))) +#define bM4_TMR41_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x422E0550UL))) +#define bM4_TMR41_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x422E0554UL))) +#define bM4_TMR41_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x422E0558UL))) +#define bM4_TMR41_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x422E055CUL))) +#define bM4_TMR41_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x422E0560UL))) +#define bM4_TMR41_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x422E0564UL))) +#define bM4_TMR41_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x422E0568UL))) +#define bM4_TMR41_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x422E056CUL))) +#define bM4_TMR41_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0570UL))) +#define bM4_TMR41_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0574UL))) +#define bM4_TMR41_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0578UL))) +#define bM4_TMR41_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x422E057CUL))) +#define bM4_TMR41_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x422E0580UL))) +#define bM4_TMR41_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x422E0584UL))) +#define bM4_TMR41_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x422E0588UL))) +#define bM4_TMR41_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x422E058CUL))) +#define bM4_TMR41_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x422E0590UL))) +#define bM4_TMR41_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x422E0594UL))) +#define bM4_TMR41_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x422E0598UL))) +#define bM4_TMR41_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x422E059CUL))) +#define bM4_TMR41_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x422E05A0UL))) +#define bM4_TMR41_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x422E05A4UL))) +#define bM4_TMR41_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x422E05A8UL))) +#define bM4_TMR41_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x422E05ACUL))) +#define bM4_TMR41_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x422E05B0UL))) +#define bM4_TMR41_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x422E05B4UL))) +#define bM4_TMR41_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x422E05B8UL))) +#define bM4_TMR41_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x422E05BCUL))) +#define bM4_TMR41_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x422E0600UL))) +#define bM4_TMR41_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x422E0604UL))) +#define bM4_TMR41_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x422E0608UL))) +#define bM4_TMR41_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x422E060CUL))) +#define bM4_TMR41_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x422E0610UL))) +#define bM4_TMR41_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x422E0614UL))) +#define bM4_TMR41_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x422E0618UL))) +#define bM4_TMR41_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x422E061CUL))) +#define bM4_TMR41_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x422E0620UL))) +#define bM4_TMR41_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x422E0624UL))) +#define bM4_TMR41_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x422E0628UL))) +#define bM4_TMR41_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x422E062CUL))) +#define bM4_TMR41_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x422E0630UL))) +#define bM4_TMR41_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x422E0634UL))) +#define bM4_TMR41_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x422E0638UL))) +#define bM4_TMR41_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x422E063CUL))) +#define bM4_TMR41_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0640UL))) +#define bM4_TMR41_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0644UL))) +#define bM4_TMR41_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0648UL))) +#define bM4_TMR41_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x422E064CUL))) +#define bM4_TMR41_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x422E0650UL))) +#define bM4_TMR41_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x422E0654UL))) +#define bM4_TMR41_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x422E0658UL))) +#define bM4_TMR41_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x422E065CUL))) +#define bM4_TMR41_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x422E0660UL))) +#define bM4_TMR41_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x422E0664UL))) +#define bM4_TMR41_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x422E0668UL))) +#define bM4_TMR41_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x422E066CUL))) +#define bM4_TMR41_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0670UL))) +#define bM4_TMR41_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0674UL))) +#define bM4_TMR41_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0678UL))) +#define bM4_TMR41_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x422E067CUL))) +#define bM4_TMR41_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x422E0680UL))) +#define bM4_TMR41_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x422E0684UL))) +#define bM4_TMR41_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x422E0688UL))) +#define bM4_TMR41_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x422E068CUL))) +#define bM4_TMR41_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x422E0690UL))) +#define bM4_TMR41_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x422E0694UL))) +#define bM4_TMR41_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x422E0698UL))) +#define bM4_TMR41_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x422E069CUL))) +#define bM4_TMR41_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x422E06A0UL))) +#define bM4_TMR41_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x422E06A4UL))) +#define bM4_TMR41_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x422E06A8UL))) +#define bM4_TMR41_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x422E06ACUL))) +#define bM4_TMR41_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x422E06B0UL))) +#define bM4_TMR41_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x422E06B4UL))) +#define bM4_TMR41_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x422E06B8UL))) +#define bM4_TMR41_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x422E06BCUL))) +#define bM4_TMR41_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x422E0700UL))) +#define bM4_TMR41_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x422E0704UL))) +#define bM4_TMR41_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x422E0708UL))) +#define bM4_TMR41_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x422E070CUL))) +#define bM4_TMR41_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x422E0710UL))) +#define bM4_TMR41_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x422E0714UL))) +#define bM4_TMR41_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x422E0718UL))) +#define bM4_TMR41_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x422E071CUL))) +#define bM4_TMR41_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x422E0720UL))) +#define bM4_TMR41_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x422E0724UL))) +#define bM4_TMR41_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x422E0728UL))) +#define bM4_TMR41_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x422E072CUL))) +#define bM4_TMR41_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x422E0730UL))) +#define bM4_TMR41_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x422E0734UL))) +#define bM4_TMR41_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x422E0738UL))) +#define bM4_TMR41_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x422E073CUL))) +#define bM4_TMR41_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0740UL))) +#define bM4_TMR41_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0744UL))) +#define bM4_TMR41_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0748UL))) +#define bM4_TMR41_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x422E074CUL))) +#define bM4_TMR41_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x422E0750UL))) +#define bM4_TMR41_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x422E0754UL))) +#define bM4_TMR41_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x422E0758UL))) +#define bM4_TMR41_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x422E075CUL))) +#define bM4_TMR41_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x422E0760UL))) +#define bM4_TMR41_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x422E0764UL))) +#define bM4_TMR41_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x422E0768UL))) +#define bM4_TMR41_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x422E076CUL))) +#define bM4_TMR41_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0770UL))) +#define bM4_TMR41_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0774UL))) +#define bM4_TMR41_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0778UL))) +#define bM4_TMR41_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x422E077CUL))) +#define bM4_TMR41_CCSR_CKDIV0 (*((volatile unsigned int*)(0x422E0900UL))) +#define bM4_TMR41_CCSR_CKDIV1 (*((volatile unsigned int*)(0x422E0904UL))) +#define bM4_TMR41_CCSR_CKDIV2 (*((volatile unsigned int*)(0x422E0908UL))) +#define bM4_TMR41_CCSR_CKDIV3 (*((volatile unsigned int*)(0x422E090CUL))) +#define bM4_TMR41_CCSR_CLEAR (*((volatile unsigned int*)(0x422E0910UL))) +#define bM4_TMR41_CCSR_MODE (*((volatile unsigned int*)(0x422E0914UL))) +#define bM4_TMR41_CCSR_STOP (*((volatile unsigned int*)(0x422E0918UL))) +#define bM4_TMR41_CCSR_BUFEN (*((volatile unsigned int*)(0x422E091CUL))) +#define bM4_TMR41_CCSR_IRQPEN (*((volatile unsigned int*)(0x422E0920UL))) +#define bM4_TMR41_CCSR_IRQPF (*((volatile unsigned int*)(0x422E0924UL))) +#define bM4_TMR41_CCSR_IRQZEN (*((volatile unsigned int*)(0x422E0934UL))) +#define bM4_TMR41_CCSR_IRQZF (*((volatile unsigned int*)(0x422E0938UL))) +#define bM4_TMR41_CCSR_ECKEN (*((volatile unsigned int*)(0x422E093CUL))) +#define bM4_TMR41_CVPR_ZIM0 (*((volatile unsigned int*)(0x422E0940UL))) +#define bM4_TMR41_CVPR_ZIM1 (*((volatile unsigned int*)(0x422E0944UL))) +#define bM4_TMR41_CVPR_ZIM2 (*((volatile unsigned int*)(0x422E0948UL))) +#define bM4_TMR41_CVPR_ZIM3 (*((volatile unsigned int*)(0x422E094CUL))) +#define bM4_TMR41_CVPR_PIM0 (*((volatile unsigned int*)(0x422E0950UL))) +#define bM4_TMR41_CVPR_PIM1 (*((volatile unsigned int*)(0x422E0954UL))) +#define bM4_TMR41_CVPR_PIM2 (*((volatile unsigned int*)(0x422E0958UL))) +#define bM4_TMR41_CVPR_PIM3 (*((volatile unsigned int*)(0x422E095CUL))) +#define bM4_TMR41_CVPR_ZIC0 (*((volatile unsigned int*)(0x422E0960UL))) +#define bM4_TMR41_CVPR_ZIC1 (*((volatile unsigned int*)(0x422E0964UL))) +#define bM4_TMR41_CVPR_ZIC2 (*((volatile unsigned int*)(0x422E0968UL))) +#define bM4_TMR41_CVPR_ZIC3 (*((volatile unsigned int*)(0x422E096CUL))) +#define bM4_TMR41_CVPR_PIC0 (*((volatile unsigned int*)(0x422E0970UL))) +#define bM4_TMR41_CVPR_PIC1 (*((volatile unsigned int*)(0x422E0974UL))) +#define bM4_TMR41_CVPR_PIC2 (*((volatile unsigned int*)(0x422E0978UL))) +#define bM4_TMR41_CVPR_PIC3 (*((volatile unsigned int*)(0x422E097CUL))) +#define bM4_TMR41_POCRU_DIVCK0 (*((volatile unsigned int*)(0x422E1300UL))) +#define bM4_TMR41_POCRU_DIVCK1 (*((volatile unsigned int*)(0x422E1304UL))) +#define bM4_TMR41_POCRU_DIVCK2 (*((volatile unsigned int*)(0x422E1308UL))) +#define bM4_TMR41_POCRU_DIVCK3 (*((volatile unsigned int*)(0x422E130CUL))) +#define bM4_TMR41_POCRU_PWMMD0 (*((volatile unsigned int*)(0x422E1310UL))) +#define bM4_TMR41_POCRU_PWMMD1 (*((volatile unsigned int*)(0x422E1314UL))) +#define bM4_TMR41_POCRU_LVLS0 (*((volatile unsigned int*)(0x422E1318UL))) +#define bM4_TMR41_POCRU_LVLS1 (*((volatile unsigned int*)(0x422E131CUL))) +#define bM4_TMR41_POCRV_DIVCK0 (*((volatile unsigned int*)(0x422E1380UL))) +#define bM4_TMR41_POCRV_DIVCK1 (*((volatile unsigned int*)(0x422E1384UL))) +#define bM4_TMR41_POCRV_DIVCK2 (*((volatile unsigned int*)(0x422E1388UL))) +#define bM4_TMR41_POCRV_DIVCK3 (*((volatile unsigned int*)(0x422E138CUL))) +#define bM4_TMR41_POCRV_PWMMD0 (*((volatile unsigned int*)(0x422E1390UL))) +#define bM4_TMR41_POCRV_PWMMD1 (*((volatile unsigned int*)(0x422E1394UL))) +#define bM4_TMR41_POCRV_LVLS0 (*((volatile unsigned int*)(0x422E1398UL))) +#define bM4_TMR41_POCRV_LVLS1 (*((volatile unsigned int*)(0x422E139CUL))) +#define bM4_TMR41_POCRW_DIVCK0 (*((volatile unsigned int*)(0x422E1400UL))) +#define bM4_TMR41_POCRW_DIVCK1 (*((volatile unsigned int*)(0x422E1404UL))) +#define bM4_TMR41_POCRW_DIVCK2 (*((volatile unsigned int*)(0x422E1408UL))) +#define bM4_TMR41_POCRW_DIVCK3 (*((volatile unsigned int*)(0x422E140CUL))) +#define bM4_TMR41_POCRW_PWMMD0 (*((volatile unsigned int*)(0x422E1410UL))) +#define bM4_TMR41_POCRW_PWMMD1 (*((volatile unsigned int*)(0x422E1414UL))) +#define bM4_TMR41_POCRW_LVLS0 (*((volatile unsigned int*)(0x422E1418UL))) +#define bM4_TMR41_POCRW_LVLS1 (*((volatile unsigned int*)(0x422E141CUL))) +#define bM4_TMR41_RCSR_RTIDU (*((volatile unsigned int*)(0x422E1480UL))) +#define bM4_TMR41_RCSR_RTIDV (*((volatile unsigned int*)(0x422E1484UL))) +#define bM4_TMR41_RCSR_RTIDW (*((volatile unsigned int*)(0x422E1488UL))) +#define bM4_TMR41_RCSR_RTIFU (*((volatile unsigned int*)(0x422E1490UL))) +#define bM4_TMR41_RCSR_RTICU (*((volatile unsigned int*)(0x422E1494UL))) +#define bM4_TMR41_RCSR_RTEU (*((volatile unsigned int*)(0x422E1498UL))) +#define bM4_TMR41_RCSR_RTSU (*((volatile unsigned int*)(0x422E149CUL))) +#define bM4_TMR41_RCSR_RTIFV (*((volatile unsigned int*)(0x422E14A0UL))) +#define bM4_TMR41_RCSR_RTICV (*((volatile unsigned int*)(0x422E14A4UL))) +#define bM4_TMR41_RCSR_RTEV (*((volatile unsigned int*)(0x422E14A8UL))) +#define bM4_TMR41_RCSR_RTSV (*((volatile unsigned int*)(0x422E14ACUL))) +#define bM4_TMR41_RCSR_RTIFW (*((volatile unsigned int*)(0x422E14B0UL))) +#define bM4_TMR41_RCSR_RTICW (*((volatile unsigned int*)(0x422E14B4UL))) +#define bM4_TMR41_RCSR_RTEW (*((volatile unsigned int*)(0x422E14B8UL))) +#define bM4_TMR41_RCSR_RTSW (*((volatile unsigned int*)(0x422E14BCUL))) +#define bM4_TMR41_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x422E1900UL))) +#define bM4_TMR41_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x422E1904UL))) +#define bM4_TMR41_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x422E1908UL))) +#define bM4_TMR41_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x422E190CUL))) +#define bM4_TMR41_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x422E1910UL))) +#define bM4_TMR41_SCSRUH_LMC (*((volatile unsigned int*)(0x422E1914UL))) +#define bM4_TMR41_SCSRUH_EVTMS (*((volatile unsigned int*)(0x422E1920UL))) +#define bM4_TMR41_SCSRUH_EVTDS (*((volatile unsigned int*)(0x422E1924UL))) +#define bM4_TMR41_SCSRUH_DEN (*((volatile unsigned int*)(0x422E1930UL))) +#define bM4_TMR41_SCSRUH_PEN (*((volatile unsigned int*)(0x422E1934UL))) +#define bM4_TMR41_SCSRUH_UEN (*((volatile unsigned int*)(0x422E1938UL))) +#define bM4_TMR41_SCSRUH_ZEN (*((volatile unsigned int*)(0x422E193CUL))) +#define bM4_TMR41_SCMRUH_AMC0 (*((volatile unsigned int*)(0x422E1940UL))) +#define bM4_TMR41_SCMRUH_AMC1 (*((volatile unsigned int*)(0x422E1944UL))) +#define bM4_TMR41_SCMRUH_AMC2 (*((volatile unsigned int*)(0x422E1948UL))) +#define bM4_TMR41_SCMRUH_AMC3 (*((volatile unsigned int*)(0x422E194CUL))) +#define bM4_TMR41_SCMRUH_MZCE (*((volatile unsigned int*)(0x422E1958UL))) +#define bM4_TMR41_SCMRUH_MPCE (*((volatile unsigned int*)(0x422E195CUL))) +#define bM4_TMR41_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x422E1980UL))) +#define bM4_TMR41_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x422E1984UL))) +#define bM4_TMR41_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x422E1988UL))) +#define bM4_TMR41_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x422E198CUL))) +#define bM4_TMR41_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x422E1990UL))) +#define bM4_TMR41_SCSRUL_LMC (*((volatile unsigned int*)(0x422E1994UL))) +#define bM4_TMR41_SCSRUL_EVTMS (*((volatile unsigned int*)(0x422E19A0UL))) +#define bM4_TMR41_SCSRUL_EVTDS (*((volatile unsigned int*)(0x422E19A4UL))) +#define bM4_TMR41_SCSRUL_DEN (*((volatile unsigned int*)(0x422E19B0UL))) +#define bM4_TMR41_SCSRUL_PEN (*((volatile unsigned int*)(0x422E19B4UL))) +#define bM4_TMR41_SCSRUL_UEN (*((volatile unsigned int*)(0x422E19B8UL))) +#define bM4_TMR41_SCSRUL_ZEN (*((volatile unsigned int*)(0x422E19BCUL))) +#define bM4_TMR41_SCMRUL_AMC0 (*((volatile unsigned int*)(0x422E19C0UL))) +#define bM4_TMR41_SCMRUL_AMC1 (*((volatile unsigned int*)(0x422E19C4UL))) +#define bM4_TMR41_SCMRUL_AMC2 (*((volatile unsigned int*)(0x422E19C8UL))) +#define bM4_TMR41_SCMRUL_AMC3 (*((volatile unsigned int*)(0x422E19CCUL))) +#define bM4_TMR41_SCMRUL_MZCE (*((volatile unsigned int*)(0x422E19D8UL))) +#define bM4_TMR41_SCMRUL_MPCE (*((volatile unsigned int*)(0x422E19DCUL))) +#define bM4_TMR41_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x422E1A00UL))) +#define bM4_TMR41_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x422E1A04UL))) +#define bM4_TMR41_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x422E1A08UL))) +#define bM4_TMR41_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x422E1A0CUL))) +#define bM4_TMR41_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x422E1A10UL))) +#define bM4_TMR41_SCSRVH_LMC (*((volatile unsigned int*)(0x422E1A14UL))) +#define bM4_TMR41_SCSRVH_EVTMS (*((volatile unsigned int*)(0x422E1A20UL))) +#define bM4_TMR41_SCSRVH_EVTDS (*((volatile unsigned int*)(0x422E1A24UL))) +#define bM4_TMR41_SCSRVH_DEN (*((volatile unsigned int*)(0x422E1A30UL))) +#define bM4_TMR41_SCSRVH_PEN (*((volatile unsigned int*)(0x422E1A34UL))) +#define bM4_TMR41_SCSRVH_UEN (*((volatile unsigned int*)(0x422E1A38UL))) +#define bM4_TMR41_SCSRVH_ZEN (*((volatile unsigned int*)(0x422E1A3CUL))) +#define bM4_TMR41_SCMRVH_AMC0 (*((volatile unsigned int*)(0x422E1A40UL))) +#define bM4_TMR41_SCMRVH_AMC1 (*((volatile unsigned int*)(0x422E1A44UL))) +#define bM4_TMR41_SCMRVH_AMC2 (*((volatile unsigned int*)(0x422E1A48UL))) +#define bM4_TMR41_SCMRVH_AMC3 (*((volatile unsigned int*)(0x422E1A4CUL))) +#define bM4_TMR41_SCMRVH_MZCE (*((volatile unsigned int*)(0x422E1A58UL))) +#define bM4_TMR41_SCMRVH_MPCE (*((volatile unsigned int*)(0x422E1A5CUL))) +#define bM4_TMR41_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x422E1A80UL))) +#define bM4_TMR41_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x422E1A84UL))) +#define bM4_TMR41_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x422E1A88UL))) +#define bM4_TMR41_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x422E1A8CUL))) +#define bM4_TMR41_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x422E1A90UL))) +#define bM4_TMR41_SCSRVL_LMC (*((volatile unsigned int*)(0x422E1A94UL))) +#define bM4_TMR41_SCSRVL_EVTMS (*((volatile unsigned int*)(0x422E1AA0UL))) +#define bM4_TMR41_SCSRVL_EVTDS (*((volatile unsigned int*)(0x422E1AA4UL))) +#define bM4_TMR41_SCSRVL_DEN (*((volatile unsigned int*)(0x422E1AB0UL))) +#define bM4_TMR41_SCSRVL_PEN (*((volatile unsigned int*)(0x422E1AB4UL))) +#define bM4_TMR41_SCSRVL_UEN (*((volatile unsigned int*)(0x422E1AB8UL))) +#define bM4_TMR41_SCSRVL_ZEN (*((volatile unsigned int*)(0x422E1ABCUL))) +#define bM4_TMR41_SCMRVL_AMC0 (*((volatile unsigned int*)(0x422E1AC0UL))) +#define bM4_TMR41_SCMRVL_AMC1 (*((volatile unsigned int*)(0x422E1AC4UL))) +#define bM4_TMR41_SCMRVL_AMC2 (*((volatile unsigned int*)(0x422E1AC8UL))) +#define bM4_TMR41_SCMRVL_AMC3 (*((volatile unsigned int*)(0x422E1ACCUL))) +#define bM4_TMR41_SCMRVL_MZCE (*((volatile unsigned int*)(0x422E1AD8UL))) +#define bM4_TMR41_SCMRVL_MPCE (*((volatile unsigned int*)(0x422E1ADCUL))) +#define bM4_TMR41_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x422E1B00UL))) +#define bM4_TMR41_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x422E1B04UL))) +#define bM4_TMR41_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x422E1B08UL))) +#define bM4_TMR41_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x422E1B0CUL))) +#define bM4_TMR41_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x422E1B10UL))) +#define bM4_TMR41_SCSRWH_LMC (*((volatile unsigned int*)(0x422E1B14UL))) +#define bM4_TMR41_SCSRWH_EVTMS (*((volatile unsigned int*)(0x422E1B20UL))) +#define bM4_TMR41_SCSRWH_EVTDS (*((volatile unsigned int*)(0x422E1B24UL))) +#define bM4_TMR41_SCSRWH_DEN (*((volatile unsigned int*)(0x422E1B30UL))) +#define bM4_TMR41_SCSRWH_PEN (*((volatile unsigned int*)(0x422E1B34UL))) +#define bM4_TMR41_SCSRWH_UEN (*((volatile unsigned int*)(0x422E1B38UL))) +#define bM4_TMR41_SCSRWH_ZEN (*((volatile unsigned int*)(0x422E1B3CUL))) +#define bM4_TMR41_SCMRWH_AMC0 (*((volatile unsigned int*)(0x422E1B40UL))) +#define bM4_TMR41_SCMRWH_AMC1 (*((volatile unsigned int*)(0x422E1B44UL))) +#define bM4_TMR41_SCMRWH_AMC2 (*((volatile unsigned int*)(0x422E1B48UL))) +#define bM4_TMR41_SCMRWH_AMC3 (*((volatile unsigned int*)(0x422E1B4CUL))) +#define bM4_TMR41_SCMRWH_MZCE (*((volatile unsigned int*)(0x422E1B58UL))) +#define bM4_TMR41_SCMRWH_MPCE (*((volatile unsigned int*)(0x422E1B5CUL))) +#define bM4_TMR41_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x422E1B80UL))) +#define bM4_TMR41_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x422E1B84UL))) +#define bM4_TMR41_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x422E1B88UL))) +#define bM4_TMR41_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x422E1B8CUL))) +#define bM4_TMR41_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x422E1B90UL))) +#define bM4_TMR41_SCSRWL_LMC (*((volatile unsigned int*)(0x422E1B94UL))) +#define bM4_TMR41_SCSRWL_EVTMS (*((volatile unsigned int*)(0x422E1BA0UL))) +#define bM4_TMR41_SCSRWL_EVTDS (*((volatile unsigned int*)(0x422E1BA4UL))) +#define bM4_TMR41_SCSRWL_DEN (*((volatile unsigned int*)(0x422E1BB0UL))) +#define bM4_TMR41_SCSRWL_PEN (*((volatile unsigned int*)(0x422E1BB4UL))) +#define bM4_TMR41_SCSRWL_UEN (*((volatile unsigned int*)(0x422E1BB8UL))) +#define bM4_TMR41_SCSRWL_ZEN (*((volatile unsigned int*)(0x422E1BBCUL))) +#define bM4_TMR41_SCMRWL_AMC0 (*((volatile unsigned int*)(0x422E1BC0UL))) +#define bM4_TMR41_SCMRWL_AMC1 (*((volatile unsigned int*)(0x422E1BC4UL))) +#define bM4_TMR41_SCMRWL_AMC2 (*((volatile unsigned int*)(0x422E1BC8UL))) +#define bM4_TMR41_SCMRWL_AMC3 (*((volatile unsigned int*)(0x422E1BCCUL))) +#define bM4_TMR41_SCMRWL_MZCE (*((volatile unsigned int*)(0x422E1BD8UL))) +#define bM4_TMR41_SCMRWL_MPCE (*((volatile unsigned int*)(0x422E1BDCUL))) +#define bM4_TMR41_ECSR_HOLD (*((volatile unsigned int*)(0x422E1E1CUL))) +#define bM4_TMR42_OCSRU_OCEH (*((volatile unsigned int*)(0x42490300UL))) +#define bM4_TMR42_OCSRU_OCEL (*((volatile unsigned int*)(0x42490304UL))) +#define bM4_TMR42_OCSRU_OCPH (*((volatile unsigned int*)(0x42490308UL))) +#define bM4_TMR42_OCSRU_OCPL (*((volatile unsigned int*)(0x4249030CUL))) +#define bM4_TMR42_OCSRU_OCIEH (*((volatile unsigned int*)(0x42490310UL))) +#define bM4_TMR42_OCSRU_OCIEL (*((volatile unsigned int*)(0x42490314UL))) +#define bM4_TMR42_OCSRU_OCFH (*((volatile unsigned int*)(0x42490318UL))) +#define bM4_TMR42_OCSRU_OCFL (*((volatile unsigned int*)(0x4249031CUL))) +#define bM4_TMR42_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x42490340UL))) +#define bM4_TMR42_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x42490344UL))) +#define bM4_TMR42_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x42490348UL))) +#define bM4_TMR42_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x4249034CUL))) +#define bM4_TMR42_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x42490350UL))) +#define bM4_TMR42_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x42490354UL))) +#define bM4_TMR42_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x42490358UL))) +#define bM4_TMR42_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x4249035CUL))) +#define bM4_TMR42_OCERU_LMCH (*((volatile unsigned int*)(0x42490360UL))) +#define bM4_TMR42_OCERU_LMCL (*((volatile unsigned int*)(0x42490364UL))) +#define bM4_TMR42_OCERU_LMMH (*((volatile unsigned int*)(0x42490368UL))) +#define bM4_TMR42_OCERU_LMML (*((volatile unsigned int*)(0x4249036CUL))) +#define bM4_TMR42_OCERU_MCECH (*((volatile unsigned int*)(0x42490370UL))) +#define bM4_TMR42_OCERU_MCECL (*((volatile unsigned int*)(0x42490374UL))) +#define bM4_TMR42_OCSRV_OCEH (*((volatile unsigned int*)(0x42490380UL))) +#define bM4_TMR42_OCSRV_OCEL (*((volatile unsigned int*)(0x42490384UL))) +#define bM4_TMR42_OCSRV_OCPH (*((volatile unsigned int*)(0x42490388UL))) +#define bM4_TMR42_OCSRV_OCPL (*((volatile unsigned int*)(0x4249038CUL))) +#define bM4_TMR42_OCSRV_OCIEH (*((volatile unsigned int*)(0x42490390UL))) +#define bM4_TMR42_OCSRV_OCIEL (*((volatile unsigned int*)(0x42490394UL))) +#define bM4_TMR42_OCSRV_OCFH (*((volatile unsigned int*)(0x42490398UL))) +#define bM4_TMR42_OCSRV_OCFL (*((volatile unsigned int*)(0x4249039CUL))) +#define bM4_TMR42_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x424903C0UL))) +#define bM4_TMR42_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x424903C4UL))) +#define bM4_TMR42_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x424903C8UL))) +#define bM4_TMR42_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x424903CCUL))) +#define bM4_TMR42_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x424903D0UL))) +#define bM4_TMR42_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x424903D4UL))) +#define bM4_TMR42_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x424903D8UL))) +#define bM4_TMR42_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x424903DCUL))) +#define bM4_TMR42_OCERV_LMCH (*((volatile unsigned int*)(0x424903E0UL))) +#define bM4_TMR42_OCERV_LMCL (*((volatile unsigned int*)(0x424903E4UL))) +#define bM4_TMR42_OCERV_LMMH (*((volatile unsigned int*)(0x424903E8UL))) +#define bM4_TMR42_OCERV_LMML (*((volatile unsigned int*)(0x424903ECUL))) +#define bM4_TMR42_OCERV_MCECH (*((volatile unsigned int*)(0x424903F0UL))) +#define bM4_TMR42_OCERV_MCECL (*((volatile unsigned int*)(0x424903F4UL))) +#define bM4_TMR42_OCSRW_OCEH (*((volatile unsigned int*)(0x42490400UL))) +#define bM4_TMR42_OCSRW_OCEL (*((volatile unsigned int*)(0x42490404UL))) +#define bM4_TMR42_OCSRW_OCPH (*((volatile unsigned int*)(0x42490408UL))) +#define bM4_TMR42_OCSRW_OCPL (*((volatile unsigned int*)(0x4249040CUL))) +#define bM4_TMR42_OCSRW_OCIEH (*((volatile unsigned int*)(0x42490410UL))) +#define bM4_TMR42_OCSRW_OCIEL (*((volatile unsigned int*)(0x42490414UL))) +#define bM4_TMR42_OCSRW_OCFH (*((volatile unsigned int*)(0x42490418UL))) +#define bM4_TMR42_OCSRW_OCFL (*((volatile unsigned int*)(0x4249041CUL))) +#define bM4_TMR42_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x42490440UL))) +#define bM4_TMR42_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x42490444UL))) +#define bM4_TMR42_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x42490448UL))) +#define bM4_TMR42_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x4249044CUL))) +#define bM4_TMR42_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x42490450UL))) +#define bM4_TMR42_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x42490454UL))) +#define bM4_TMR42_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x42490458UL))) +#define bM4_TMR42_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x4249045CUL))) +#define bM4_TMR42_OCERW_LMCH (*((volatile unsigned int*)(0x42490460UL))) +#define bM4_TMR42_OCERW_LMCL (*((volatile unsigned int*)(0x42490464UL))) +#define bM4_TMR42_OCERW_LMMH (*((volatile unsigned int*)(0x42490468UL))) +#define bM4_TMR42_OCERW_LMML (*((volatile unsigned int*)(0x4249046CUL))) +#define bM4_TMR42_OCERW_MCECH (*((volatile unsigned int*)(0x42490470UL))) +#define bM4_TMR42_OCERW_MCECL (*((volatile unsigned int*)(0x42490474UL))) +#define bM4_TMR42_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x42490480UL))) +#define bM4_TMR42_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x42490484UL))) +#define bM4_TMR42_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x42490488UL))) +#define bM4_TMR42_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x4249048CUL))) +#define bM4_TMR42_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x42490490UL))) +#define bM4_TMR42_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x42490494UL))) +#define bM4_TMR42_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x42490498UL))) +#define bM4_TMR42_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x4249049CUL))) +#define bM4_TMR42_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x424904A0UL))) +#define bM4_TMR42_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x424904A4UL))) +#define bM4_TMR42_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x424904A8UL))) +#define bM4_TMR42_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x424904ACUL))) +#define bM4_TMR42_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x424904B0UL))) +#define bM4_TMR42_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x424904B4UL))) +#define bM4_TMR42_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x424904B8UL))) +#define bM4_TMR42_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x424904BCUL))) +#define bM4_TMR42_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x42490500UL))) +#define bM4_TMR42_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x42490504UL))) +#define bM4_TMR42_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x42490508UL))) +#define bM4_TMR42_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x4249050CUL))) +#define bM4_TMR42_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x42490510UL))) +#define bM4_TMR42_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x42490514UL))) +#define bM4_TMR42_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x42490518UL))) +#define bM4_TMR42_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x4249051CUL))) +#define bM4_TMR42_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x42490520UL))) +#define bM4_TMR42_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x42490524UL))) +#define bM4_TMR42_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x42490528UL))) +#define bM4_TMR42_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x4249052CUL))) +#define bM4_TMR42_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x42490530UL))) +#define bM4_TMR42_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x42490534UL))) +#define bM4_TMR42_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x42490538UL))) +#define bM4_TMR42_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x4249053CUL))) +#define bM4_TMR42_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x42490540UL))) +#define bM4_TMR42_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x42490544UL))) +#define bM4_TMR42_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x42490548UL))) +#define bM4_TMR42_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x4249054CUL))) +#define bM4_TMR42_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x42490550UL))) +#define bM4_TMR42_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x42490554UL))) +#define bM4_TMR42_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x42490558UL))) +#define bM4_TMR42_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x4249055CUL))) +#define bM4_TMR42_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x42490560UL))) +#define bM4_TMR42_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x42490564UL))) +#define bM4_TMR42_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x42490568UL))) +#define bM4_TMR42_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x4249056CUL))) +#define bM4_TMR42_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x42490570UL))) +#define bM4_TMR42_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x42490574UL))) +#define bM4_TMR42_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x42490578UL))) +#define bM4_TMR42_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x4249057CUL))) +#define bM4_TMR42_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x42490580UL))) +#define bM4_TMR42_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x42490584UL))) +#define bM4_TMR42_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x42490588UL))) +#define bM4_TMR42_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x4249058CUL))) +#define bM4_TMR42_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x42490590UL))) +#define bM4_TMR42_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x42490594UL))) +#define bM4_TMR42_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x42490598UL))) +#define bM4_TMR42_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x4249059CUL))) +#define bM4_TMR42_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x424905A0UL))) +#define bM4_TMR42_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x424905A4UL))) +#define bM4_TMR42_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x424905A8UL))) +#define bM4_TMR42_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x424905ACUL))) +#define bM4_TMR42_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x424905B0UL))) +#define bM4_TMR42_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x424905B4UL))) +#define bM4_TMR42_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x424905B8UL))) +#define bM4_TMR42_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x424905BCUL))) +#define bM4_TMR42_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x42490600UL))) +#define bM4_TMR42_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x42490604UL))) +#define bM4_TMR42_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x42490608UL))) +#define bM4_TMR42_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x4249060CUL))) +#define bM4_TMR42_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x42490610UL))) +#define bM4_TMR42_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x42490614UL))) +#define bM4_TMR42_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x42490618UL))) +#define bM4_TMR42_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x4249061CUL))) +#define bM4_TMR42_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x42490620UL))) +#define bM4_TMR42_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x42490624UL))) +#define bM4_TMR42_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x42490628UL))) +#define bM4_TMR42_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x4249062CUL))) +#define bM4_TMR42_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x42490630UL))) +#define bM4_TMR42_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x42490634UL))) +#define bM4_TMR42_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x42490638UL))) +#define bM4_TMR42_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x4249063CUL))) +#define bM4_TMR42_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x42490640UL))) +#define bM4_TMR42_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x42490644UL))) +#define bM4_TMR42_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x42490648UL))) +#define bM4_TMR42_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x4249064CUL))) +#define bM4_TMR42_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x42490650UL))) +#define bM4_TMR42_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x42490654UL))) +#define bM4_TMR42_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x42490658UL))) +#define bM4_TMR42_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x4249065CUL))) +#define bM4_TMR42_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x42490660UL))) +#define bM4_TMR42_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x42490664UL))) +#define bM4_TMR42_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x42490668UL))) +#define bM4_TMR42_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x4249066CUL))) +#define bM4_TMR42_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x42490670UL))) +#define bM4_TMR42_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x42490674UL))) +#define bM4_TMR42_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x42490678UL))) +#define bM4_TMR42_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x4249067CUL))) +#define bM4_TMR42_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x42490680UL))) +#define bM4_TMR42_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x42490684UL))) +#define bM4_TMR42_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x42490688UL))) +#define bM4_TMR42_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x4249068CUL))) +#define bM4_TMR42_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x42490690UL))) +#define bM4_TMR42_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x42490694UL))) +#define bM4_TMR42_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x42490698UL))) +#define bM4_TMR42_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x4249069CUL))) +#define bM4_TMR42_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x424906A0UL))) +#define bM4_TMR42_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x424906A4UL))) +#define bM4_TMR42_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x424906A8UL))) +#define bM4_TMR42_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x424906ACUL))) +#define bM4_TMR42_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x424906B0UL))) +#define bM4_TMR42_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x424906B4UL))) +#define bM4_TMR42_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x424906B8UL))) +#define bM4_TMR42_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x424906BCUL))) +#define bM4_TMR42_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x42490700UL))) +#define bM4_TMR42_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x42490704UL))) +#define bM4_TMR42_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x42490708UL))) +#define bM4_TMR42_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x4249070CUL))) +#define bM4_TMR42_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x42490710UL))) +#define bM4_TMR42_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x42490714UL))) +#define bM4_TMR42_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x42490718UL))) +#define bM4_TMR42_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x4249071CUL))) +#define bM4_TMR42_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x42490720UL))) +#define bM4_TMR42_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x42490724UL))) +#define bM4_TMR42_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x42490728UL))) +#define bM4_TMR42_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x4249072CUL))) +#define bM4_TMR42_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x42490730UL))) +#define bM4_TMR42_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x42490734UL))) +#define bM4_TMR42_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x42490738UL))) +#define bM4_TMR42_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x4249073CUL))) +#define bM4_TMR42_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x42490740UL))) +#define bM4_TMR42_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x42490744UL))) +#define bM4_TMR42_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x42490748UL))) +#define bM4_TMR42_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x4249074CUL))) +#define bM4_TMR42_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x42490750UL))) +#define bM4_TMR42_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x42490754UL))) +#define bM4_TMR42_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x42490758UL))) +#define bM4_TMR42_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x4249075CUL))) +#define bM4_TMR42_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x42490760UL))) +#define bM4_TMR42_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x42490764UL))) +#define bM4_TMR42_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x42490768UL))) +#define bM4_TMR42_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x4249076CUL))) +#define bM4_TMR42_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x42490770UL))) +#define bM4_TMR42_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x42490774UL))) +#define bM4_TMR42_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x42490778UL))) +#define bM4_TMR42_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x4249077CUL))) +#define bM4_TMR42_CCSR_CKDIV0 (*((volatile unsigned int*)(0x42490900UL))) +#define bM4_TMR42_CCSR_CKDIV1 (*((volatile unsigned int*)(0x42490904UL))) +#define bM4_TMR42_CCSR_CKDIV2 (*((volatile unsigned int*)(0x42490908UL))) +#define bM4_TMR42_CCSR_CKDIV3 (*((volatile unsigned int*)(0x4249090CUL))) +#define bM4_TMR42_CCSR_CLEAR (*((volatile unsigned int*)(0x42490910UL))) +#define bM4_TMR42_CCSR_MODE (*((volatile unsigned int*)(0x42490914UL))) +#define bM4_TMR42_CCSR_STOP (*((volatile unsigned int*)(0x42490918UL))) +#define bM4_TMR42_CCSR_BUFEN (*((volatile unsigned int*)(0x4249091CUL))) +#define bM4_TMR42_CCSR_IRQPEN (*((volatile unsigned int*)(0x42490920UL))) +#define bM4_TMR42_CCSR_IRQPF (*((volatile unsigned int*)(0x42490924UL))) +#define bM4_TMR42_CCSR_IRQZEN (*((volatile unsigned int*)(0x42490934UL))) +#define bM4_TMR42_CCSR_IRQZF (*((volatile unsigned int*)(0x42490938UL))) +#define bM4_TMR42_CCSR_ECKEN (*((volatile unsigned int*)(0x4249093CUL))) +#define bM4_TMR42_CVPR_ZIM0 (*((volatile unsigned int*)(0x42490940UL))) +#define bM4_TMR42_CVPR_ZIM1 (*((volatile unsigned int*)(0x42490944UL))) +#define bM4_TMR42_CVPR_ZIM2 (*((volatile unsigned int*)(0x42490948UL))) +#define bM4_TMR42_CVPR_ZIM3 (*((volatile unsigned int*)(0x4249094CUL))) +#define bM4_TMR42_CVPR_PIM0 (*((volatile unsigned int*)(0x42490950UL))) +#define bM4_TMR42_CVPR_PIM1 (*((volatile unsigned int*)(0x42490954UL))) +#define bM4_TMR42_CVPR_PIM2 (*((volatile unsigned int*)(0x42490958UL))) +#define bM4_TMR42_CVPR_PIM3 (*((volatile unsigned int*)(0x4249095CUL))) +#define bM4_TMR42_CVPR_ZIC0 (*((volatile unsigned int*)(0x42490960UL))) +#define bM4_TMR42_CVPR_ZIC1 (*((volatile unsigned int*)(0x42490964UL))) +#define bM4_TMR42_CVPR_ZIC2 (*((volatile unsigned int*)(0x42490968UL))) +#define bM4_TMR42_CVPR_ZIC3 (*((volatile unsigned int*)(0x4249096CUL))) +#define bM4_TMR42_CVPR_PIC0 (*((volatile unsigned int*)(0x42490970UL))) +#define bM4_TMR42_CVPR_PIC1 (*((volatile unsigned int*)(0x42490974UL))) +#define bM4_TMR42_CVPR_PIC2 (*((volatile unsigned int*)(0x42490978UL))) +#define bM4_TMR42_CVPR_PIC3 (*((volatile unsigned int*)(0x4249097CUL))) +#define bM4_TMR42_POCRU_DIVCK0 (*((volatile unsigned int*)(0x42491300UL))) +#define bM4_TMR42_POCRU_DIVCK1 (*((volatile unsigned int*)(0x42491304UL))) +#define bM4_TMR42_POCRU_DIVCK2 (*((volatile unsigned int*)(0x42491308UL))) +#define bM4_TMR42_POCRU_DIVCK3 (*((volatile unsigned int*)(0x4249130CUL))) +#define bM4_TMR42_POCRU_PWMMD0 (*((volatile unsigned int*)(0x42491310UL))) +#define bM4_TMR42_POCRU_PWMMD1 (*((volatile unsigned int*)(0x42491314UL))) +#define bM4_TMR42_POCRU_LVLS0 (*((volatile unsigned int*)(0x42491318UL))) +#define bM4_TMR42_POCRU_LVLS1 (*((volatile unsigned int*)(0x4249131CUL))) +#define bM4_TMR42_POCRV_DIVCK0 (*((volatile unsigned int*)(0x42491380UL))) +#define bM4_TMR42_POCRV_DIVCK1 (*((volatile unsigned int*)(0x42491384UL))) +#define bM4_TMR42_POCRV_DIVCK2 (*((volatile unsigned int*)(0x42491388UL))) +#define bM4_TMR42_POCRV_DIVCK3 (*((volatile unsigned int*)(0x4249138CUL))) +#define bM4_TMR42_POCRV_PWMMD0 (*((volatile unsigned int*)(0x42491390UL))) +#define bM4_TMR42_POCRV_PWMMD1 (*((volatile unsigned int*)(0x42491394UL))) +#define bM4_TMR42_POCRV_LVLS0 (*((volatile unsigned int*)(0x42491398UL))) +#define bM4_TMR42_POCRV_LVLS1 (*((volatile unsigned int*)(0x4249139CUL))) +#define bM4_TMR42_POCRW_DIVCK0 (*((volatile unsigned int*)(0x42491400UL))) +#define bM4_TMR42_POCRW_DIVCK1 (*((volatile unsigned int*)(0x42491404UL))) +#define bM4_TMR42_POCRW_DIVCK2 (*((volatile unsigned int*)(0x42491408UL))) +#define bM4_TMR42_POCRW_DIVCK3 (*((volatile unsigned int*)(0x4249140CUL))) +#define bM4_TMR42_POCRW_PWMMD0 (*((volatile unsigned int*)(0x42491410UL))) +#define bM4_TMR42_POCRW_PWMMD1 (*((volatile unsigned int*)(0x42491414UL))) +#define bM4_TMR42_POCRW_LVLS0 (*((volatile unsigned int*)(0x42491418UL))) +#define bM4_TMR42_POCRW_LVLS1 (*((volatile unsigned int*)(0x4249141CUL))) +#define bM4_TMR42_RCSR_RTIDU (*((volatile unsigned int*)(0x42491480UL))) +#define bM4_TMR42_RCSR_RTIDV (*((volatile unsigned int*)(0x42491484UL))) +#define bM4_TMR42_RCSR_RTIDW (*((volatile unsigned int*)(0x42491488UL))) +#define bM4_TMR42_RCSR_RTIFU (*((volatile unsigned int*)(0x42491490UL))) +#define bM4_TMR42_RCSR_RTICU (*((volatile unsigned int*)(0x42491494UL))) +#define bM4_TMR42_RCSR_RTEU (*((volatile unsigned int*)(0x42491498UL))) +#define bM4_TMR42_RCSR_RTSU (*((volatile unsigned int*)(0x4249149CUL))) +#define bM4_TMR42_RCSR_RTIFV (*((volatile unsigned int*)(0x424914A0UL))) +#define bM4_TMR42_RCSR_RTICV (*((volatile unsigned int*)(0x424914A4UL))) +#define bM4_TMR42_RCSR_RTEV (*((volatile unsigned int*)(0x424914A8UL))) +#define bM4_TMR42_RCSR_RTSV (*((volatile unsigned int*)(0x424914ACUL))) +#define bM4_TMR42_RCSR_RTIFW (*((volatile unsigned int*)(0x424914B0UL))) +#define bM4_TMR42_RCSR_RTICW (*((volatile unsigned int*)(0x424914B4UL))) +#define bM4_TMR42_RCSR_RTEW (*((volatile unsigned int*)(0x424914B8UL))) +#define bM4_TMR42_RCSR_RTSW (*((volatile unsigned int*)(0x424914BCUL))) +#define bM4_TMR42_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x42491900UL))) +#define bM4_TMR42_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x42491904UL))) +#define bM4_TMR42_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x42491908UL))) +#define bM4_TMR42_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x4249190CUL))) +#define bM4_TMR42_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x42491910UL))) +#define bM4_TMR42_SCSRUH_LMC (*((volatile unsigned int*)(0x42491914UL))) +#define bM4_TMR42_SCSRUH_EVTMS (*((volatile unsigned int*)(0x42491920UL))) +#define bM4_TMR42_SCSRUH_EVTDS (*((volatile unsigned int*)(0x42491924UL))) +#define bM4_TMR42_SCSRUH_DEN (*((volatile unsigned int*)(0x42491930UL))) +#define bM4_TMR42_SCSRUH_PEN (*((volatile unsigned int*)(0x42491934UL))) +#define bM4_TMR42_SCSRUH_UEN (*((volatile unsigned int*)(0x42491938UL))) +#define bM4_TMR42_SCSRUH_ZEN (*((volatile unsigned int*)(0x4249193CUL))) +#define bM4_TMR42_SCMRUH_AMC0 (*((volatile unsigned int*)(0x42491940UL))) +#define bM4_TMR42_SCMRUH_AMC1 (*((volatile unsigned int*)(0x42491944UL))) +#define bM4_TMR42_SCMRUH_AMC2 (*((volatile unsigned int*)(0x42491948UL))) +#define bM4_TMR42_SCMRUH_AMC3 (*((volatile unsigned int*)(0x4249194CUL))) +#define bM4_TMR42_SCMRUH_MZCE (*((volatile unsigned int*)(0x42491958UL))) +#define bM4_TMR42_SCMRUH_MPCE (*((volatile unsigned int*)(0x4249195CUL))) +#define bM4_TMR42_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x42491980UL))) +#define bM4_TMR42_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x42491984UL))) +#define bM4_TMR42_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x42491988UL))) +#define bM4_TMR42_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x4249198CUL))) +#define bM4_TMR42_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x42491990UL))) +#define bM4_TMR42_SCSRUL_LMC (*((volatile unsigned int*)(0x42491994UL))) +#define bM4_TMR42_SCSRUL_EVTMS (*((volatile unsigned int*)(0x424919A0UL))) +#define bM4_TMR42_SCSRUL_EVTDS (*((volatile unsigned int*)(0x424919A4UL))) +#define bM4_TMR42_SCSRUL_DEN (*((volatile unsigned int*)(0x424919B0UL))) +#define bM4_TMR42_SCSRUL_PEN (*((volatile unsigned int*)(0x424919B4UL))) +#define bM4_TMR42_SCSRUL_UEN (*((volatile unsigned int*)(0x424919B8UL))) +#define bM4_TMR42_SCSRUL_ZEN (*((volatile unsigned int*)(0x424919BCUL))) +#define bM4_TMR42_SCMRUL_AMC0 (*((volatile unsigned int*)(0x424919C0UL))) +#define bM4_TMR42_SCMRUL_AMC1 (*((volatile unsigned int*)(0x424919C4UL))) +#define bM4_TMR42_SCMRUL_AMC2 (*((volatile unsigned int*)(0x424919C8UL))) +#define bM4_TMR42_SCMRUL_AMC3 (*((volatile unsigned int*)(0x424919CCUL))) +#define bM4_TMR42_SCMRUL_MZCE (*((volatile unsigned int*)(0x424919D8UL))) +#define bM4_TMR42_SCMRUL_MPCE (*((volatile unsigned int*)(0x424919DCUL))) +#define bM4_TMR42_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x42491A00UL))) +#define bM4_TMR42_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x42491A04UL))) +#define bM4_TMR42_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x42491A08UL))) +#define bM4_TMR42_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x42491A0CUL))) +#define bM4_TMR42_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x42491A10UL))) +#define bM4_TMR42_SCSRVH_LMC (*((volatile unsigned int*)(0x42491A14UL))) +#define bM4_TMR42_SCSRVH_EVTMS (*((volatile unsigned int*)(0x42491A20UL))) +#define bM4_TMR42_SCSRVH_EVTDS (*((volatile unsigned int*)(0x42491A24UL))) +#define bM4_TMR42_SCSRVH_DEN (*((volatile unsigned int*)(0x42491A30UL))) +#define bM4_TMR42_SCSRVH_PEN (*((volatile unsigned int*)(0x42491A34UL))) +#define bM4_TMR42_SCSRVH_UEN (*((volatile unsigned int*)(0x42491A38UL))) +#define bM4_TMR42_SCSRVH_ZEN (*((volatile unsigned int*)(0x42491A3CUL))) +#define bM4_TMR42_SCMRVH_AMC0 (*((volatile unsigned int*)(0x42491A40UL))) +#define bM4_TMR42_SCMRVH_AMC1 (*((volatile unsigned int*)(0x42491A44UL))) +#define bM4_TMR42_SCMRVH_AMC2 (*((volatile unsigned int*)(0x42491A48UL))) +#define bM4_TMR42_SCMRVH_AMC3 (*((volatile unsigned int*)(0x42491A4CUL))) +#define bM4_TMR42_SCMRVH_MZCE (*((volatile unsigned int*)(0x42491A58UL))) +#define bM4_TMR42_SCMRVH_MPCE (*((volatile unsigned int*)(0x42491A5CUL))) +#define bM4_TMR42_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x42491A80UL))) +#define bM4_TMR42_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x42491A84UL))) +#define bM4_TMR42_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x42491A88UL))) +#define bM4_TMR42_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x42491A8CUL))) +#define bM4_TMR42_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x42491A90UL))) +#define bM4_TMR42_SCSRVL_LMC (*((volatile unsigned int*)(0x42491A94UL))) +#define bM4_TMR42_SCSRVL_EVTMS (*((volatile unsigned int*)(0x42491AA0UL))) +#define bM4_TMR42_SCSRVL_EVTDS (*((volatile unsigned int*)(0x42491AA4UL))) +#define bM4_TMR42_SCSRVL_DEN (*((volatile unsigned int*)(0x42491AB0UL))) +#define bM4_TMR42_SCSRVL_PEN (*((volatile unsigned int*)(0x42491AB4UL))) +#define bM4_TMR42_SCSRVL_UEN (*((volatile unsigned int*)(0x42491AB8UL))) +#define bM4_TMR42_SCSRVL_ZEN (*((volatile unsigned int*)(0x42491ABCUL))) +#define bM4_TMR42_SCMRVL_AMC0 (*((volatile unsigned int*)(0x42491AC0UL))) +#define bM4_TMR42_SCMRVL_AMC1 (*((volatile unsigned int*)(0x42491AC4UL))) +#define bM4_TMR42_SCMRVL_AMC2 (*((volatile unsigned int*)(0x42491AC8UL))) +#define bM4_TMR42_SCMRVL_AMC3 (*((volatile unsigned int*)(0x42491ACCUL))) +#define bM4_TMR42_SCMRVL_MZCE (*((volatile unsigned int*)(0x42491AD8UL))) +#define bM4_TMR42_SCMRVL_MPCE (*((volatile unsigned int*)(0x42491ADCUL))) +#define bM4_TMR42_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x42491B00UL))) +#define bM4_TMR42_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x42491B04UL))) +#define bM4_TMR42_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x42491B08UL))) +#define bM4_TMR42_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x42491B0CUL))) +#define bM4_TMR42_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x42491B10UL))) +#define bM4_TMR42_SCSRWH_LMC (*((volatile unsigned int*)(0x42491B14UL))) +#define bM4_TMR42_SCSRWH_EVTMS (*((volatile unsigned int*)(0x42491B20UL))) +#define bM4_TMR42_SCSRWH_EVTDS (*((volatile unsigned int*)(0x42491B24UL))) +#define bM4_TMR42_SCSRWH_DEN (*((volatile unsigned int*)(0x42491B30UL))) +#define bM4_TMR42_SCSRWH_PEN (*((volatile unsigned int*)(0x42491B34UL))) +#define bM4_TMR42_SCSRWH_UEN (*((volatile unsigned int*)(0x42491B38UL))) +#define bM4_TMR42_SCSRWH_ZEN (*((volatile unsigned int*)(0x42491B3CUL))) +#define bM4_TMR42_SCMRWH_AMC0 (*((volatile unsigned int*)(0x42491B40UL))) +#define bM4_TMR42_SCMRWH_AMC1 (*((volatile unsigned int*)(0x42491B44UL))) +#define bM4_TMR42_SCMRWH_AMC2 (*((volatile unsigned int*)(0x42491B48UL))) +#define bM4_TMR42_SCMRWH_AMC3 (*((volatile unsigned int*)(0x42491B4CUL))) +#define bM4_TMR42_SCMRWH_MZCE (*((volatile unsigned int*)(0x42491B58UL))) +#define bM4_TMR42_SCMRWH_MPCE (*((volatile unsigned int*)(0x42491B5CUL))) +#define bM4_TMR42_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x42491B80UL))) +#define bM4_TMR42_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x42491B84UL))) +#define bM4_TMR42_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x42491B88UL))) +#define bM4_TMR42_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x42491B8CUL))) +#define bM4_TMR42_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x42491B90UL))) +#define bM4_TMR42_SCSRWL_LMC (*((volatile unsigned int*)(0x42491B94UL))) +#define bM4_TMR42_SCSRWL_EVTMS (*((volatile unsigned int*)(0x42491BA0UL))) +#define bM4_TMR42_SCSRWL_EVTDS (*((volatile unsigned int*)(0x42491BA4UL))) +#define bM4_TMR42_SCSRWL_DEN (*((volatile unsigned int*)(0x42491BB0UL))) +#define bM4_TMR42_SCSRWL_PEN (*((volatile unsigned int*)(0x42491BB4UL))) +#define bM4_TMR42_SCSRWL_UEN (*((volatile unsigned int*)(0x42491BB8UL))) +#define bM4_TMR42_SCSRWL_ZEN (*((volatile unsigned int*)(0x42491BBCUL))) +#define bM4_TMR42_SCMRWL_AMC0 (*((volatile unsigned int*)(0x42491BC0UL))) +#define bM4_TMR42_SCMRWL_AMC1 (*((volatile unsigned int*)(0x42491BC4UL))) +#define bM4_TMR42_SCMRWL_AMC2 (*((volatile unsigned int*)(0x42491BC8UL))) +#define bM4_TMR42_SCMRWL_AMC3 (*((volatile unsigned int*)(0x42491BCCUL))) +#define bM4_TMR42_SCMRWL_MZCE (*((volatile unsigned int*)(0x42491BD8UL))) +#define bM4_TMR42_SCMRWL_MPCE (*((volatile unsigned int*)(0x42491BDCUL))) +#define bM4_TMR42_ECSR_HOLD (*((volatile unsigned int*)(0x42491E1CUL))) +#define bM4_TMR43_OCSRU_OCEH (*((volatile unsigned int*)(0x42498300UL))) +#define bM4_TMR43_OCSRU_OCEL (*((volatile unsigned int*)(0x42498304UL))) +#define bM4_TMR43_OCSRU_OCPH (*((volatile unsigned int*)(0x42498308UL))) +#define bM4_TMR43_OCSRU_OCPL (*((volatile unsigned int*)(0x4249830CUL))) +#define bM4_TMR43_OCSRU_OCIEH (*((volatile unsigned int*)(0x42498310UL))) +#define bM4_TMR43_OCSRU_OCIEL (*((volatile unsigned int*)(0x42498314UL))) +#define bM4_TMR43_OCSRU_OCFH (*((volatile unsigned int*)(0x42498318UL))) +#define bM4_TMR43_OCSRU_OCFL (*((volatile unsigned int*)(0x4249831CUL))) +#define bM4_TMR43_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x42498340UL))) +#define bM4_TMR43_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x42498344UL))) +#define bM4_TMR43_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x42498348UL))) +#define bM4_TMR43_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x4249834CUL))) +#define bM4_TMR43_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x42498350UL))) +#define bM4_TMR43_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x42498354UL))) +#define bM4_TMR43_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x42498358UL))) +#define bM4_TMR43_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x4249835CUL))) +#define bM4_TMR43_OCERU_LMCH (*((volatile unsigned int*)(0x42498360UL))) +#define bM4_TMR43_OCERU_LMCL (*((volatile unsigned int*)(0x42498364UL))) +#define bM4_TMR43_OCERU_LMMH (*((volatile unsigned int*)(0x42498368UL))) +#define bM4_TMR43_OCERU_LMML (*((volatile unsigned int*)(0x4249836CUL))) +#define bM4_TMR43_OCERU_MCECH (*((volatile unsigned int*)(0x42498370UL))) +#define bM4_TMR43_OCERU_MCECL (*((volatile unsigned int*)(0x42498374UL))) +#define bM4_TMR43_OCSRV_OCEH (*((volatile unsigned int*)(0x42498380UL))) +#define bM4_TMR43_OCSRV_OCEL (*((volatile unsigned int*)(0x42498384UL))) +#define bM4_TMR43_OCSRV_OCPH (*((volatile unsigned int*)(0x42498388UL))) +#define bM4_TMR43_OCSRV_OCPL (*((volatile unsigned int*)(0x4249838CUL))) +#define bM4_TMR43_OCSRV_OCIEH (*((volatile unsigned int*)(0x42498390UL))) +#define bM4_TMR43_OCSRV_OCIEL (*((volatile unsigned int*)(0x42498394UL))) +#define bM4_TMR43_OCSRV_OCFH (*((volatile unsigned int*)(0x42498398UL))) +#define bM4_TMR43_OCSRV_OCFL (*((volatile unsigned int*)(0x4249839CUL))) +#define bM4_TMR43_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x424983C0UL))) +#define bM4_TMR43_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x424983C4UL))) +#define bM4_TMR43_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x424983C8UL))) +#define bM4_TMR43_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x424983CCUL))) +#define bM4_TMR43_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x424983D0UL))) +#define bM4_TMR43_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x424983D4UL))) +#define bM4_TMR43_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x424983D8UL))) +#define bM4_TMR43_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x424983DCUL))) +#define bM4_TMR43_OCERV_LMCH (*((volatile unsigned int*)(0x424983E0UL))) +#define bM4_TMR43_OCERV_LMCL (*((volatile unsigned int*)(0x424983E4UL))) +#define bM4_TMR43_OCERV_LMMH (*((volatile unsigned int*)(0x424983E8UL))) +#define bM4_TMR43_OCERV_LMML (*((volatile unsigned int*)(0x424983ECUL))) +#define bM4_TMR43_OCERV_MCECH (*((volatile unsigned int*)(0x424983F0UL))) +#define bM4_TMR43_OCERV_MCECL (*((volatile unsigned int*)(0x424983F4UL))) +#define bM4_TMR43_OCSRW_OCEH (*((volatile unsigned int*)(0x42498400UL))) +#define bM4_TMR43_OCSRW_OCEL (*((volatile unsigned int*)(0x42498404UL))) +#define bM4_TMR43_OCSRW_OCPH (*((volatile unsigned int*)(0x42498408UL))) +#define bM4_TMR43_OCSRW_OCPL (*((volatile unsigned int*)(0x4249840CUL))) +#define bM4_TMR43_OCSRW_OCIEH (*((volatile unsigned int*)(0x42498410UL))) +#define bM4_TMR43_OCSRW_OCIEL (*((volatile unsigned int*)(0x42498414UL))) +#define bM4_TMR43_OCSRW_OCFH (*((volatile unsigned int*)(0x42498418UL))) +#define bM4_TMR43_OCSRW_OCFL (*((volatile unsigned int*)(0x4249841CUL))) +#define bM4_TMR43_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x42498440UL))) +#define bM4_TMR43_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x42498444UL))) +#define bM4_TMR43_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x42498448UL))) +#define bM4_TMR43_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x4249844CUL))) +#define bM4_TMR43_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x42498450UL))) +#define bM4_TMR43_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x42498454UL))) +#define bM4_TMR43_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x42498458UL))) +#define bM4_TMR43_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x4249845CUL))) +#define bM4_TMR43_OCERW_LMCH (*((volatile unsigned int*)(0x42498460UL))) +#define bM4_TMR43_OCERW_LMCL (*((volatile unsigned int*)(0x42498464UL))) +#define bM4_TMR43_OCERW_LMMH (*((volatile unsigned int*)(0x42498468UL))) +#define bM4_TMR43_OCERW_LMML (*((volatile unsigned int*)(0x4249846CUL))) +#define bM4_TMR43_OCERW_MCECH (*((volatile unsigned int*)(0x42498470UL))) +#define bM4_TMR43_OCERW_MCECL (*((volatile unsigned int*)(0x42498474UL))) +#define bM4_TMR43_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x42498480UL))) +#define bM4_TMR43_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x42498484UL))) +#define bM4_TMR43_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x42498488UL))) +#define bM4_TMR43_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x4249848CUL))) +#define bM4_TMR43_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x42498490UL))) +#define bM4_TMR43_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x42498494UL))) +#define bM4_TMR43_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x42498498UL))) +#define bM4_TMR43_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x4249849CUL))) +#define bM4_TMR43_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x424984A0UL))) +#define bM4_TMR43_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x424984A4UL))) +#define bM4_TMR43_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x424984A8UL))) +#define bM4_TMR43_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x424984ACUL))) +#define bM4_TMR43_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x424984B0UL))) +#define bM4_TMR43_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x424984B4UL))) +#define bM4_TMR43_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x424984B8UL))) +#define bM4_TMR43_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x424984BCUL))) +#define bM4_TMR43_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x42498500UL))) +#define bM4_TMR43_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x42498504UL))) +#define bM4_TMR43_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x42498508UL))) +#define bM4_TMR43_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x4249850CUL))) +#define bM4_TMR43_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x42498510UL))) +#define bM4_TMR43_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x42498514UL))) +#define bM4_TMR43_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x42498518UL))) +#define bM4_TMR43_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x4249851CUL))) +#define bM4_TMR43_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x42498520UL))) +#define bM4_TMR43_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x42498524UL))) +#define bM4_TMR43_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x42498528UL))) +#define bM4_TMR43_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x4249852CUL))) +#define bM4_TMR43_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x42498530UL))) +#define bM4_TMR43_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x42498534UL))) +#define bM4_TMR43_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x42498538UL))) +#define bM4_TMR43_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x4249853CUL))) +#define bM4_TMR43_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x42498540UL))) +#define bM4_TMR43_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x42498544UL))) +#define bM4_TMR43_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x42498548UL))) +#define bM4_TMR43_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x4249854CUL))) +#define bM4_TMR43_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x42498550UL))) +#define bM4_TMR43_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x42498554UL))) +#define bM4_TMR43_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x42498558UL))) +#define bM4_TMR43_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x4249855CUL))) +#define bM4_TMR43_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x42498560UL))) +#define bM4_TMR43_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x42498564UL))) +#define bM4_TMR43_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x42498568UL))) +#define bM4_TMR43_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x4249856CUL))) +#define bM4_TMR43_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x42498570UL))) +#define bM4_TMR43_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x42498574UL))) +#define bM4_TMR43_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x42498578UL))) +#define bM4_TMR43_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x4249857CUL))) +#define bM4_TMR43_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x42498580UL))) +#define bM4_TMR43_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x42498584UL))) +#define bM4_TMR43_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x42498588UL))) +#define bM4_TMR43_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x4249858CUL))) +#define bM4_TMR43_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x42498590UL))) +#define bM4_TMR43_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x42498594UL))) +#define bM4_TMR43_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x42498598UL))) +#define bM4_TMR43_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x4249859CUL))) +#define bM4_TMR43_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x424985A0UL))) +#define bM4_TMR43_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x424985A4UL))) +#define bM4_TMR43_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x424985A8UL))) +#define bM4_TMR43_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x424985ACUL))) +#define bM4_TMR43_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x424985B0UL))) +#define bM4_TMR43_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x424985B4UL))) +#define bM4_TMR43_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x424985B8UL))) +#define bM4_TMR43_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x424985BCUL))) +#define bM4_TMR43_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x42498600UL))) +#define bM4_TMR43_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x42498604UL))) +#define bM4_TMR43_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x42498608UL))) +#define bM4_TMR43_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x4249860CUL))) +#define bM4_TMR43_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x42498610UL))) +#define bM4_TMR43_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x42498614UL))) +#define bM4_TMR43_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x42498618UL))) +#define bM4_TMR43_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x4249861CUL))) +#define bM4_TMR43_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x42498620UL))) +#define bM4_TMR43_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x42498624UL))) +#define bM4_TMR43_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x42498628UL))) +#define bM4_TMR43_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x4249862CUL))) +#define bM4_TMR43_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x42498630UL))) +#define bM4_TMR43_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x42498634UL))) +#define bM4_TMR43_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x42498638UL))) +#define bM4_TMR43_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x4249863CUL))) +#define bM4_TMR43_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x42498640UL))) +#define bM4_TMR43_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x42498644UL))) +#define bM4_TMR43_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x42498648UL))) +#define bM4_TMR43_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x4249864CUL))) +#define bM4_TMR43_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x42498650UL))) +#define bM4_TMR43_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x42498654UL))) +#define bM4_TMR43_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x42498658UL))) +#define bM4_TMR43_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x4249865CUL))) +#define bM4_TMR43_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x42498660UL))) +#define bM4_TMR43_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x42498664UL))) +#define bM4_TMR43_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x42498668UL))) +#define bM4_TMR43_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x4249866CUL))) +#define bM4_TMR43_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x42498670UL))) +#define bM4_TMR43_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x42498674UL))) +#define bM4_TMR43_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x42498678UL))) +#define bM4_TMR43_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x4249867CUL))) +#define bM4_TMR43_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x42498680UL))) +#define bM4_TMR43_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x42498684UL))) +#define bM4_TMR43_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x42498688UL))) +#define bM4_TMR43_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x4249868CUL))) +#define bM4_TMR43_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x42498690UL))) +#define bM4_TMR43_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x42498694UL))) +#define bM4_TMR43_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x42498698UL))) +#define bM4_TMR43_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x4249869CUL))) +#define bM4_TMR43_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x424986A0UL))) +#define bM4_TMR43_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x424986A4UL))) +#define bM4_TMR43_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x424986A8UL))) +#define bM4_TMR43_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x424986ACUL))) +#define bM4_TMR43_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x424986B0UL))) +#define bM4_TMR43_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x424986B4UL))) +#define bM4_TMR43_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x424986B8UL))) +#define bM4_TMR43_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x424986BCUL))) +#define bM4_TMR43_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x42498700UL))) +#define bM4_TMR43_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x42498704UL))) +#define bM4_TMR43_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x42498708UL))) +#define bM4_TMR43_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x4249870CUL))) +#define bM4_TMR43_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x42498710UL))) +#define bM4_TMR43_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x42498714UL))) +#define bM4_TMR43_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x42498718UL))) +#define bM4_TMR43_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x4249871CUL))) +#define bM4_TMR43_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x42498720UL))) +#define bM4_TMR43_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x42498724UL))) +#define bM4_TMR43_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x42498728UL))) +#define bM4_TMR43_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x4249872CUL))) +#define bM4_TMR43_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x42498730UL))) +#define bM4_TMR43_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x42498734UL))) +#define bM4_TMR43_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x42498738UL))) +#define bM4_TMR43_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x4249873CUL))) +#define bM4_TMR43_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x42498740UL))) +#define bM4_TMR43_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x42498744UL))) +#define bM4_TMR43_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x42498748UL))) +#define bM4_TMR43_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x4249874CUL))) +#define bM4_TMR43_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x42498750UL))) +#define bM4_TMR43_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x42498754UL))) +#define bM4_TMR43_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x42498758UL))) +#define bM4_TMR43_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x4249875CUL))) +#define bM4_TMR43_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x42498760UL))) +#define bM4_TMR43_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x42498764UL))) +#define bM4_TMR43_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x42498768UL))) +#define bM4_TMR43_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x4249876CUL))) +#define bM4_TMR43_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x42498770UL))) +#define bM4_TMR43_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x42498774UL))) +#define bM4_TMR43_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x42498778UL))) +#define bM4_TMR43_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x4249877CUL))) +#define bM4_TMR43_CCSR_CKDIV0 (*((volatile unsigned int*)(0x42498900UL))) +#define bM4_TMR43_CCSR_CKDIV1 (*((volatile unsigned int*)(0x42498904UL))) +#define bM4_TMR43_CCSR_CKDIV2 (*((volatile unsigned int*)(0x42498908UL))) +#define bM4_TMR43_CCSR_CKDIV3 (*((volatile unsigned int*)(0x4249890CUL))) +#define bM4_TMR43_CCSR_CLEAR (*((volatile unsigned int*)(0x42498910UL))) +#define bM4_TMR43_CCSR_MODE (*((volatile unsigned int*)(0x42498914UL))) +#define bM4_TMR43_CCSR_STOP (*((volatile unsigned int*)(0x42498918UL))) +#define bM4_TMR43_CCSR_BUFEN (*((volatile unsigned int*)(0x4249891CUL))) +#define bM4_TMR43_CCSR_IRQPEN (*((volatile unsigned int*)(0x42498920UL))) +#define bM4_TMR43_CCSR_IRQPF (*((volatile unsigned int*)(0x42498924UL))) +#define bM4_TMR43_CCSR_IRQZEN (*((volatile unsigned int*)(0x42498934UL))) +#define bM4_TMR43_CCSR_IRQZF (*((volatile unsigned int*)(0x42498938UL))) +#define bM4_TMR43_CCSR_ECKEN (*((volatile unsigned int*)(0x4249893CUL))) +#define bM4_TMR43_CVPR_ZIM0 (*((volatile unsigned int*)(0x42498940UL))) +#define bM4_TMR43_CVPR_ZIM1 (*((volatile unsigned int*)(0x42498944UL))) +#define bM4_TMR43_CVPR_ZIM2 (*((volatile unsigned int*)(0x42498948UL))) +#define bM4_TMR43_CVPR_ZIM3 (*((volatile unsigned int*)(0x4249894CUL))) +#define bM4_TMR43_CVPR_PIM0 (*((volatile unsigned int*)(0x42498950UL))) +#define bM4_TMR43_CVPR_PIM1 (*((volatile unsigned int*)(0x42498954UL))) +#define bM4_TMR43_CVPR_PIM2 (*((volatile unsigned int*)(0x42498958UL))) +#define bM4_TMR43_CVPR_PIM3 (*((volatile unsigned int*)(0x4249895CUL))) +#define bM4_TMR43_CVPR_ZIC0 (*((volatile unsigned int*)(0x42498960UL))) +#define bM4_TMR43_CVPR_ZIC1 (*((volatile unsigned int*)(0x42498964UL))) +#define bM4_TMR43_CVPR_ZIC2 (*((volatile unsigned int*)(0x42498968UL))) +#define bM4_TMR43_CVPR_ZIC3 (*((volatile unsigned int*)(0x4249896CUL))) +#define bM4_TMR43_CVPR_PIC0 (*((volatile unsigned int*)(0x42498970UL))) +#define bM4_TMR43_CVPR_PIC1 (*((volatile unsigned int*)(0x42498974UL))) +#define bM4_TMR43_CVPR_PIC2 (*((volatile unsigned int*)(0x42498978UL))) +#define bM4_TMR43_CVPR_PIC3 (*((volatile unsigned int*)(0x4249897CUL))) +#define bM4_TMR43_POCRU_DIVCK0 (*((volatile unsigned int*)(0x42499300UL))) +#define bM4_TMR43_POCRU_DIVCK1 (*((volatile unsigned int*)(0x42499304UL))) +#define bM4_TMR43_POCRU_DIVCK2 (*((volatile unsigned int*)(0x42499308UL))) +#define bM4_TMR43_POCRU_DIVCK3 (*((volatile unsigned int*)(0x4249930CUL))) +#define bM4_TMR43_POCRU_PWMMD0 (*((volatile unsigned int*)(0x42499310UL))) +#define bM4_TMR43_POCRU_PWMMD1 (*((volatile unsigned int*)(0x42499314UL))) +#define bM4_TMR43_POCRU_LVLS0 (*((volatile unsigned int*)(0x42499318UL))) +#define bM4_TMR43_POCRU_LVLS1 (*((volatile unsigned int*)(0x4249931CUL))) +#define bM4_TMR43_POCRV_DIVCK0 (*((volatile unsigned int*)(0x42499380UL))) +#define bM4_TMR43_POCRV_DIVCK1 (*((volatile unsigned int*)(0x42499384UL))) +#define bM4_TMR43_POCRV_DIVCK2 (*((volatile unsigned int*)(0x42499388UL))) +#define bM4_TMR43_POCRV_DIVCK3 (*((volatile unsigned int*)(0x4249938CUL))) +#define bM4_TMR43_POCRV_PWMMD0 (*((volatile unsigned int*)(0x42499390UL))) +#define bM4_TMR43_POCRV_PWMMD1 (*((volatile unsigned int*)(0x42499394UL))) +#define bM4_TMR43_POCRV_LVLS0 (*((volatile unsigned int*)(0x42499398UL))) +#define bM4_TMR43_POCRV_LVLS1 (*((volatile unsigned int*)(0x4249939CUL))) +#define bM4_TMR43_POCRW_DIVCK0 (*((volatile unsigned int*)(0x42499400UL))) +#define bM4_TMR43_POCRW_DIVCK1 (*((volatile unsigned int*)(0x42499404UL))) +#define bM4_TMR43_POCRW_DIVCK2 (*((volatile unsigned int*)(0x42499408UL))) +#define bM4_TMR43_POCRW_DIVCK3 (*((volatile unsigned int*)(0x4249940CUL))) +#define bM4_TMR43_POCRW_PWMMD0 (*((volatile unsigned int*)(0x42499410UL))) +#define bM4_TMR43_POCRW_PWMMD1 (*((volatile unsigned int*)(0x42499414UL))) +#define bM4_TMR43_POCRW_LVLS0 (*((volatile unsigned int*)(0x42499418UL))) +#define bM4_TMR43_POCRW_LVLS1 (*((volatile unsigned int*)(0x4249941CUL))) +#define bM4_TMR43_RCSR_RTIDU (*((volatile unsigned int*)(0x42499480UL))) +#define bM4_TMR43_RCSR_RTIDV (*((volatile unsigned int*)(0x42499484UL))) +#define bM4_TMR43_RCSR_RTIDW (*((volatile unsigned int*)(0x42499488UL))) +#define bM4_TMR43_RCSR_RTIFU (*((volatile unsigned int*)(0x42499490UL))) +#define bM4_TMR43_RCSR_RTICU (*((volatile unsigned int*)(0x42499494UL))) +#define bM4_TMR43_RCSR_RTEU (*((volatile unsigned int*)(0x42499498UL))) +#define bM4_TMR43_RCSR_RTSU (*((volatile unsigned int*)(0x4249949CUL))) +#define bM4_TMR43_RCSR_RTIFV (*((volatile unsigned int*)(0x424994A0UL))) +#define bM4_TMR43_RCSR_RTICV (*((volatile unsigned int*)(0x424994A4UL))) +#define bM4_TMR43_RCSR_RTEV (*((volatile unsigned int*)(0x424994A8UL))) +#define bM4_TMR43_RCSR_RTSV (*((volatile unsigned int*)(0x424994ACUL))) +#define bM4_TMR43_RCSR_RTIFW (*((volatile unsigned int*)(0x424994B0UL))) +#define bM4_TMR43_RCSR_RTICW (*((volatile unsigned int*)(0x424994B4UL))) +#define bM4_TMR43_RCSR_RTEW (*((volatile unsigned int*)(0x424994B8UL))) +#define bM4_TMR43_RCSR_RTSW (*((volatile unsigned int*)(0x424994BCUL))) +#define bM4_TMR43_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x42499900UL))) +#define bM4_TMR43_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x42499904UL))) +#define bM4_TMR43_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x42499908UL))) +#define bM4_TMR43_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x4249990CUL))) +#define bM4_TMR43_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x42499910UL))) +#define bM4_TMR43_SCSRUH_LMC (*((volatile unsigned int*)(0x42499914UL))) +#define bM4_TMR43_SCSRUH_EVTMS (*((volatile unsigned int*)(0x42499920UL))) +#define bM4_TMR43_SCSRUH_EVTDS (*((volatile unsigned int*)(0x42499924UL))) +#define bM4_TMR43_SCSRUH_DEN (*((volatile unsigned int*)(0x42499930UL))) +#define bM4_TMR43_SCSRUH_PEN (*((volatile unsigned int*)(0x42499934UL))) +#define bM4_TMR43_SCSRUH_UEN (*((volatile unsigned int*)(0x42499938UL))) +#define bM4_TMR43_SCSRUH_ZEN (*((volatile unsigned int*)(0x4249993CUL))) +#define bM4_TMR43_SCMRUH_AMC0 (*((volatile unsigned int*)(0x42499940UL))) +#define bM4_TMR43_SCMRUH_AMC1 (*((volatile unsigned int*)(0x42499944UL))) +#define bM4_TMR43_SCMRUH_AMC2 (*((volatile unsigned int*)(0x42499948UL))) +#define bM4_TMR43_SCMRUH_AMC3 (*((volatile unsigned int*)(0x4249994CUL))) +#define bM4_TMR43_SCMRUH_MZCE (*((volatile unsigned int*)(0x42499958UL))) +#define bM4_TMR43_SCMRUH_MPCE (*((volatile unsigned int*)(0x4249995CUL))) +#define bM4_TMR43_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x42499980UL))) +#define bM4_TMR43_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x42499984UL))) +#define bM4_TMR43_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x42499988UL))) +#define bM4_TMR43_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x4249998CUL))) +#define bM4_TMR43_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x42499990UL))) +#define bM4_TMR43_SCSRUL_LMC (*((volatile unsigned int*)(0x42499994UL))) +#define bM4_TMR43_SCSRUL_EVTMS (*((volatile unsigned int*)(0x424999A0UL))) +#define bM4_TMR43_SCSRUL_EVTDS (*((volatile unsigned int*)(0x424999A4UL))) +#define bM4_TMR43_SCSRUL_DEN (*((volatile unsigned int*)(0x424999B0UL))) +#define bM4_TMR43_SCSRUL_PEN (*((volatile unsigned int*)(0x424999B4UL))) +#define bM4_TMR43_SCSRUL_UEN (*((volatile unsigned int*)(0x424999B8UL))) +#define bM4_TMR43_SCSRUL_ZEN (*((volatile unsigned int*)(0x424999BCUL))) +#define bM4_TMR43_SCMRUL_AMC0 (*((volatile unsigned int*)(0x424999C0UL))) +#define bM4_TMR43_SCMRUL_AMC1 (*((volatile unsigned int*)(0x424999C4UL))) +#define bM4_TMR43_SCMRUL_AMC2 (*((volatile unsigned int*)(0x424999C8UL))) +#define bM4_TMR43_SCMRUL_AMC3 (*((volatile unsigned int*)(0x424999CCUL))) +#define bM4_TMR43_SCMRUL_MZCE (*((volatile unsigned int*)(0x424999D8UL))) +#define bM4_TMR43_SCMRUL_MPCE (*((volatile unsigned int*)(0x424999DCUL))) +#define bM4_TMR43_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x42499A00UL))) +#define bM4_TMR43_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x42499A04UL))) +#define bM4_TMR43_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x42499A08UL))) +#define bM4_TMR43_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x42499A0CUL))) +#define bM4_TMR43_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x42499A10UL))) +#define bM4_TMR43_SCSRVH_LMC (*((volatile unsigned int*)(0x42499A14UL))) +#define bM4_TMR43_SCSRVH_EVTMS (*((volatile unsigned int*)(0x42499A20UL))) +#define bM4_TMR43_SCSRVH_EVTDS (*((volatile unsigned int*)(0x42499A24UL))) +#define bM4_TMR43_SCSRVH_DEN (*((volatile unsigned int*)(0x42499A30UL))) +#define bM4_TMR43_SCSRVH_PEN (*((volatile unsigned int*)(0x42499A34UL))) +#define bM4_TMR43_SCSRVH_UEN (*((volatile unsigned int*)(0x42499A38UL))) +#define bM4_TMR43_SCSRVH_ZEN (*((volatile unsigned int*)(0x42499A3CUL))) +#define bM4_TMR43_SCMRVH_AMC0 (*((volatile unsigned int*)(0x42499A40UL))) +#define bM4_TMR43_SCMRVH_AMC1 (*((volatile unsigned int*)(0x42499A44UL))) +#define bM4_TMR43_SCMRVH_AMC2 (*((volatile unsigned int*)(0x42499A48UL))) +#define bM4_TMR43_SCMRVH_AMC3 (*((volatile unsigned int*)(0x42499A4CUL))) +#define bM4_TMR43_SCMRVH_MZCE (*((volatile unsigned int*)(0x42499A58UL))) +#define bM4_TMR43_SCMRVH_MPCE (*((volatile unsigned int*)(0x42499A5CUL))) +#define bM4_TMR43_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x42499A80UL))) +#define bM4_TMR43_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x42499A84UL))) +#define bM4_TMR43_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x42499A88UL))) +#define bM4_TMR43_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x42499A8CUL))) +#define bM4_TMR43_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x42499A90UL))) +#define bM4_TMR43_SCSRVL_LMC (*((volatile unsigned int*)(0x42499A94UL))) +#define bM4_TMR43_SCSRVL_EVTMS (*((volatile unsigned int*)(0x42499AA0UL))) +#define bM4_TMR43_SCSRVL_EVTDS (*((volatile unsigned int*)(0x42499AA4UL))) +#define bM4_TMR43_SCSRVL_DEN (*((volatile unsigned int*)(0x42499AB0UL))) +#define bM4_TMR43_SCSRVL_PEN (*((volatile unsigned int*)(0x42499AB4UL))) +#define bM4_TMR43_SCSRVL_UEN (*((volatile unsigned int*)(0x42499AB8UL))) +#define bM4_TMR43_SCSRVL_ZEN (*((volatile unsigned int*)(0x42499ABCUL))) +#define bM4_TMR43_SCMRVL_AMC0 (*((volatile unsigned int*)(0x42499AC0UL))) +#define bM4_TMR43_SCMRVL_AMC1 (*((volatile unsigned int*)(0x42499AC4UL))) +#define bM4_TMR43_SCMRVL_AMC2 (*((volatile unsigned int*)(0x42499AC8UL))) +#define bM4_TMR43_SCMRVL_AMC3 (*((volatile unsigned int*)(0x42499ACCUL))) +#define bM4_TMR43_SCMRVL_MZCE (*((volatile unsigned int*)(0x42499AD8UL))) +#define bM4_TMR43_SCMRVL_MPCE (*((volatile unsigned int*)(0x42499ADCUL))) +#define bM4_TMR43_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x42499B00UL))) +#define bM4_TMR43_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x42499B04UL))) +#define bM4_TMR43_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x42499B08UL))) +#define bM4_TMR43_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x42499B0CUL))) +#define bM4_TMR43_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x42499B10UL))) +#define bM4_TMR43_SCSRWH_LMC (*((volatile unsigned int*)(0x42499B14UL))) +#define bM4_TMR43_SCSRWH_EVTMS (*((volatile unsigned int*)(0x42499B20UL))) +#define bM4_TMR43_SCSRWH_EVTDS (*((volatile unsigned int*)(0x42499B24UL))) +#define bM4_TMR43_SCSRWH_DEN (*((volatile unsigned int*)(0x42499B30UL))) +#define bM4_TMR43_SCSRWH_PEN (*((volatile unsigned int*)(0x42499B34UL))) +#define bM4_TMR43_SCSRWH_UEN (*((volatile unsigned int*)(0x42499B38UL))) +#define bM4_TMR43_SCSRWH_ZEN (*((volatile unsigned int*)(0x42499B3CUL))) +#define bM4_TMR43_SCMRWH_AMC0 (*((volatile unsigned int*)(0x42499B40UL))) +#define bM4_TMR43_SCMRWH_AMC1 (*((volatile unsigned int*)(0x42499B44UL))) +#define bM4_TMR43_SCMRWH_AMC2 (*((volatile unsigned int*)(0x42499B48UL))) +#define bM4_TMR43_SCMRWH_AMC3 (*((volatile unsigned int*)(0x42499B4CUL))) +#define bM4_TMR43_SCMRWH_MZCE (*((volatile unsigned int*)(0x42499B58UL))) +#define bM4_TMR43_SCMRWH_MPCE (*((volatile unsigned int*)(0x42499B5CUL))) +#define bM4_TMR43_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x42499B80UL))) +#define bM4_TMR43_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x42499B84UL))) +#define bM4_TMR43_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x42499B88UL))) +#define bM4_TMR43_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x42499B8CUL))) +#define bM4_TMR43_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x42499B90UL))) +#define bM4_TMR43_SCSRWL_LMC (*((volatile unsigned int*)(0x42499B94UL))) +#define bM4_TMR43_SCSRWL_EVTMS (*((volatile unsigned int*)(0x42499BA0UL))) +#define bM4_TMR43_SCSRWL_EVTDS (*((volatile unsigned int*)(0x42499BA4UL))) +#define bM4_TMR43_SCSRWL_DEN (*((volatile unsigned int*)(0x42499BB0UL))) +#define bM4_TMR43_SCSRWL_PEN (*((volatile unsigned int*)(0x42499BB4UL))) +#define bM4_TMR43_SCSRWL_UEN (*((volatile unsigned int*)(0x42499BB8UL))) +#define bM4_TMR43_SCSRWL_ZEN (*((volatile unsigned int*)(0x42499BBCUL))) +#define bM4_TMR43_SCMRWL_AMC0 (*((volatile unsigned int*)(0x42499BC0UL))) +#define bM4_TMR43_SCMRWL_AMC1 (*((volatile unsigned int*)(0x42499BC4UL))) +#define bM4_TMR43_SCMRWL_AMC2 (*((volatile unsigned int*)(0x42499BC8UL))) +#define bM4_TMR43_SCMRWL_AMC3 (*((volatile unsigned int*)(0x42499BCCUL))) +#define bM4_TMR43_SCMRWL_MZCE (*((volatile unsigned int*)(0x42499BD8UL))) +#define bM4_TMR43_SCMRWL_MPCE (*((volatile unsigned int*)(0x42499BDCUL))) +#define bM4_TMR43_ECSR_HOLD (*((volatile unsigned int*)(0x42499E1CUL))) +#define bM4_TMR4_CR_ECER1_EMBVAL0 (*((volatile unsigned int*)(0x42AA8100UL))) +#define bM4_TMR4_CR_ECER1_EMBVAL1 (*((volatile unsigned int*)(0x42AA8104UL))) +#define bM4_TMR4_CR_ECER2_EMBVAL0 (*((volatile unsigned int*)(0x42AA8180UL))) +#define bM4_TMR4_CR_ECER2_EMBVAL1 (*((volatile unsigned int*)(0x42AA8184UL))) +#define bM4_TMR4_CR_ECER3_EMBVAL0 (*((volatile unsigned int*)(0x42AA8200UL))) +#define bM4_TMR4_CR_ECER3_EMBVAL1 (*((volatile unsigned int*)(0x42AA8204UL))) +#define bM4_TMR61_CNTER_CNT0 (*((volatile unsigned int*)(0x42300000UL))) +#define bM4_TMR61_CNTER_CNT1 (*((volatile unsigned int*)(0x42300004UL))) +#define bM4_TMR61_CNTER_CNT2 (*((volatile unsigned int*)(0x42300008UL))) +#define bM4_TMR61_CNTER_CNT3 (*((volatile unsigned int*)(0x4230000CUL))) +#define bM4_TMR61_CNTER_CNT4 (*((volatile unsigned int*)(0x42300010UL))) +#define bM4_TMR61_CNTER_CNT5 (*((volatile unsigned int*)(0x42300014UL))) +#define bM4_TMR61_CNTER_CNT6 (*((volatile unsigned int*)(0x42300018UL))) +#define bM4_TMR61_CNTER_CNT7 (*((volatile unsigned int*)(0x4230001CUL))) +#define bM4_TMR61_CNTER_CNT8 (*((volatile unsigned int*)(0x42300020UL))) +#define bM4_TMR61_CNTER_CNT9 (*((volatile unsigned int*)(0x42300024UL))) +#define bM4_TMR61_CNTER_CNT10 (*((volatile unsigned int*)(0x42300028UL))) +#define bM4_TMR61_CNTER_CNT11 (*((volatile unsigned int*)(0x4230002CUL))) +#define bM4_TMR61_CNTER_CNT12 (*((volatile unsigned int*)(0x42300030UL))) +#define bM4_TMR61_CNTER_CNT13 (*((volatile unsigned int*)(0x42300034UL))) +#define bM4_TMR61_CNTER_CNT14 (*((volatile unsigned int*)(0x42300038UL))) +#define bM4_TMR61_CNTER_CNT15 (*((volatile unsigned int*)(0x4230003CUL))) +#define bM4_TMR61_PERAR_PERA0 (*((volatile unsigned int*)(0x42300080UL))) +#define bM4_TMR61_PERAR_PERA1 (*((volatile unsigned int*)(0x42300084UL))) +#define bM4_TMR61_PERAR_PERA2 (*((volatile unsigned int*)(0x42300088UL))) +#define bM4_TMR61_PERAR_PERA3 (*((volatile unsigned int*)(0x4230008CUL))) +#define bM4_TMR61_PERAR_PERA4 (*((volatile unsigned int*)(0x42300090UL))) +#define bM4_TMR61_PERAR_PERA5 (*((volatile unsigned int*)(0x42300094UL))) +#define bM4_TMR61_PERAR_PERA6 (*((volatile unsigned int*)(0x42300098UL))) +#define bM4_TMR61_PERAR_PERA7 (*((volatile unsigned int*)(0x4230009CUL))) +#define bM4_TMR61_PERAR_PERA8 (*((volatile unsigned int*)(0x423000A0UL))) +#define bM4_TMR61_PERAR_PERA9 (*((volatile unsigned int*)(0x423000A4UL))) +#define bM4_TMR61_PERAR_PERA10 (*((volatile unsigned int*)(0x423000A8UL))) +#define bM4_TMR61_PERAR_PERA11 (*((volatile unsigned int*)(0x423000ACUL))) +#define bM4_TMR61_PERAR_PERA12 (*((volatile unsigned int*)(0x423000B0UL))) +#define bM4_TMR61_PERAR_PERA13 (*((volatile unsigned int*)(0x423000B4UL))) +#define bM4_TMR61_PERAR_PERA14 (*((volatile unsigned int*)(0x423000B8UL))) +#define bM4_TMR61_PERAR_PERA15 (*((volatile unsigned int*)(0x423000BCUL))) +#define bM4_TMR61_PERBR_PERB0 (*((volatile unsigned int*)(0x42300100UL))) +#define bM4_TMR61_PERBR_PERB1 (*((volatile unsigned int*)(0x42300104UL))) +#define bM4_TMR61_PERBR_PERB2 (*((volatile unsigned int*)(0x42300108UL))) +#define bM4_TMR61_PERBR_PERB3 (*((volatile unsigned int*)(0x4230010CUL))) +#define bM4_TMR61_PERBR_PERB4 (*((volatile unsigned int*)(0x42300110UL))) +#define bM4_TMR61_PERBR_PERB5 (*((volatile unsigned int*)(0x42300114UL))) +#define bM4_TMR61_PERBR_PERB6 (*((volatile unsigned int*)(0x42300118UL))) +#define bM4_TMR61_PERBR_PERB7 (*((volatile unsigned int*)(0x4230011CUL))) +#define bM4_TMR61_PERBR_PERB8 (*((volatile unsigned int*)(0x42300120UL))) +#define bM4_TMR61_PERBR_PERB9 (*((volatile unsigned int*)(0x42300124UL))) +#define bM4_TMR61_PERBR_PERB10 (*((volatile unsigned int*)(0x42300128UL))) +#define bM4_TMR61_PERBR_PERB11 (*((volatile unsigned int*)(0x4230012CUL))) +#define bM4_TMR61_PERBR_PERB12 (*((volatile unsigned int*)(0x42300130UL))) +#define bM4_TMR61_PERBR_PERB13 (*((volatile unsigned int*)(0x42300134UL))) +#define bM4_TMR61_PERBR_PERB14 (*((volatile unsigned int*)(0x42300138UL))) +#define bM4_TMR61_PERBR_PERB15 (*((volatile unsigned int*)(0x4230013CUL))) +#define bM4_TMR61_PERCR_PERC0 (*((volatile unsigned int*)(0x42300180UL))) +#define bM4_TMR61_PERCR_PERC1 (*((volatile unsigned int*)(0x42300184UL))) +#define bM4_TMR61_PERCR_PERC2 (*((volatile unsigned int*)(0x42300188UL))) +#define bM4_TMR61_PERCR_PERC3 (*((volatile unsigned int*)(0x4230018CUL))) +#define bM4_TMR61_PERCR_PERC4 (*((volatile unsigned int*)(0x42300190UL))) +#define bM4_TMR61_PERCR_PERC5 (*((volatile unsigned int*)(0x42300194UL))) +#define bM4_TMR61_PERCR_PERC6 (*((volatile unsigned int*)(0x42300198UL))) +#define bM4_TMR61_PERCR_PERC7 (*((volatile unsigned int*)(0x4230019CUL))) +#define bM4_TMR61_PERCR_PERC8 (*((volatile unsigned int*)(0x423001A0UL))) +#define bM4_TMR61_PERCR_PERC9 (*((volatile unsigned int*)(0x423001A4UL))) +#define bM4_TMR61_PERCR_PERC10 (*((volatile unsigned int*)(0x423001A8UL))) +#define bM4_TMR61_PERCR_PERC11 (*((volatile unsigned int*)(0x423001ACUL))) +#define bM4_TMR61_PERCR_PERC12 (*((volatile unsigned int*)(0x423001B0UL))) +#define bM4_TMR61_PERCR_PERC13 (*((volatile unsigned int*)(0x423001B4UL))) +#define bM4_TMR61_PERCR_PERC14 (*((volatile unsigned int*)(0x423001B8UL))) +#define bM4_TMR61_PERCR_PERC15 (*((volatile unsigned int*)(0x423001BCUL))) +#define bM4_TMR61_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42300200UL))) +#define bM4_TMR61_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42300204UL))) +#define bM4_TMR61_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42300208UL))) +#define bM4_TMR61_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4230020CUL))) +#define bM4_TMR61_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42300210UL))) +#define bM4_TMR61_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42300214UL))) +#define bM4_TMR61_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42300218UL))) +#define bM4_TMR61_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4230021CUL))) +#define bM4_TMR61_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42300220UL))) +#define bM4_TMR61_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42300224UL))) +#define bM4_TMR61_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42300228UL))) +#define bM4_TMR61_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4230022CUL))) +#define bM4_TMR61_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42300230UL))) +#define bM4_TMR61_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42300234UL))) +#define bM4_TMR61_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42300238UL))) +#define bM4_TMR61_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4230023CUL))) +#define bM4_TMR61_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42300280UL))) +#define bM4_TMR61_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42300284UL))) +#define bM4_TMR61_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42300288UL))) +#define bM4_TMR61_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4230028CUL))) +#define bM4_TMR61_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42300290UL))) +#define bM4_TMR61_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42300294UL))) +#define bM4_TMR61_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42300298UL))) +#define bM4_TMR61_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4230029CUL))) +#define bM4_TMR61_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423002A0UL))) +#define bM4_TMR61_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423002A4UL))) +#define bM4_TMR61_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423002A8UL))) +#define bM4_TMR61_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423002ACUL))) +#define bM4_TMR61_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423002B0UL))) +#define bM4_TMR61_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423002B4UL))) +#define bM4_TMR61_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423002B8UL))) +#define bM4_TMR61_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423002BCUL))) +#define bM4_TMR61_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42300300UL))) +#define bM4_TMR61_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42300304UL))) +#define bM4_TMR61_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42300308UL))) +#define bM4_TMR61_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4230030CUL))) +#define bM4_TMR61_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42300310UL))) +#define bM4_TMR61_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42300314UL))) +#define bM4_TMR61_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42300318UL))) +#define bM4_TMR61_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4230031CUL))) +#define bM4_TMR61_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42300320UL))) +#define bM4_TMR61_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42300324UL))) +#define bM4_TMR61_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42300328UL))) +#define bM4_TMR61_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4230032CUL))) +#define bM4_TMR61_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42300330UL))) +#define bM4_TMR61_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42300334UL))) +#define bM4_TMR61_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42300338UL))) +#define bM4_TMR61_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4230033CUL))) +#define bM4_TMR61_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42300380UL))) +#define bM4_TMR61_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42300384UL))) +#define bM4_TMR61_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42300388UL))) +#define bM4_TMR61_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4230038CUL))) +#define bM4_TMR61_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42300390UL))) +#define bM4_TMR61_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42300394UL))) +#define bM4_TMR61_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42300398UL))) +#define bM4_TMR61_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4230039CUL))) +#define bM4_TMR61_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423003A0UL))) +#define bM4_TMR61_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423003A4UL))) +#define bM4_TMR61_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423003A8UL))) +#define bM4_TMR61_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423003ACUL))) +#define bM4_TMR61_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423003B0UL))) +#define bM4_TMR61_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423003B4UL))) +#define bM4_TMR61_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423003B8UL))) +#define bM4_TMR61_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423003BCUL))) +#define bM4_TMR61_GCMER_GCME0 (*((volatile unsigned int*)(0x42300400UL))) +#define bM4_TMR61_GCMER_GCME1 (*((volatile unsigned int*)(0x42300404UL))) +#define bM4_TMR61_GCMER_GCME2 (*((volatile unsigned int*)(0x42300408UL))) +#define bM4_TMR61_GCMER_GCME3 (*((volatile unsigned int*)(0x4230040CUL))) +#define bM4_TMR61_GCMER_GCME4 (*((volatile unsigned int*)(0x42300410UL))) +#define bM4_TMR61_GCMER_GCME5 (*((volatile unsigned int*)(0x42300414UL))) +#define bM4_TMR61_GCMER_GCME6 (*((volatile unsigned int*)(0x42300418UL))) +#define bM4_TMR61_GCMER_GCME7 (*((volatile unsigned int*)(0x4230041CUL))) +#define bM4_TMR61_GCMER_GCME8 (*((volatile unsigned int*)(0x42300420UL))) +#define bM4_TMR61_GCMER_GCME9 (*((volatile unsigned int*)(0x42300424UL))) +#define bM4_TMR61_GCMER_GCME10 (*((volatile unsigned int*)(0x42300428UL))) +#define bM4_TMR61_GCMER_GCME11 (*((volatile unsigned int*)(0x4230042CUL))) +#define bM4_TMR61_GCMER_GCME12 (*((volatile unsigned int*)(0x42300430UL))) +#define bM4_TMR61_GCMER_GCME13 (*((volatile unsigned int*)(0x42300434UL))) +#define bM4_TMR61_GCMER_GCME14 (*((volatile unsigned int*)(0x42300438UL))) +#define bM4_TMR61_GCMER_GCME15 (*((volatile unsigned int*)(0x4230043CUL))) +#define bM4_TMR61_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42300480UL))) +#define bM4_TMR61_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42300484UL))) +#define bM4_TMR61_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42300488UL))) +#define bM4_TMR61_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4230048CUL))) +#define bM4_TMR61_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42300490UL))) +#define bM4_TMR61_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42300494UL))) +#define bM4_TMR61_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42300498UL))) +#define bM4_TMR61_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4230049CUL))) +#define bM4_TMR61_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423004A0UL))) +#define bM4_TMR61_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423004A4UL))) +#define bM4_TMR61_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423004A8UL))) +#define bM4_TMR61_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423004ACUL))) +#define bM4_TMR61_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423004B0UL))) +#define bM4_TMR61_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423004B4UL))) +#define bM4_TMR61_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423004B8UL))) +#define bM4_TMR61_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423004BCUL))) +#define bM4_TMR61_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42300500UL))) +#define bM4_TMR61_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42300504UL))) +#define bM4_TMR61_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42300508UL))) +#define bM4_TMR61_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4230050CUL))) +#define bM4_TMR61_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42300510UL))) +#define bM4_TMR61_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42300514UL))) +#define bM4_TMR61_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42300518UL))) +#define bM4_TMR61_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4230051CUL))) +#define bM4_TMR61_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42300520UL))) +#define bM4_TMR61_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42300524UL))) +#define bM4_TMR61_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42300528UL))) +#define bM4_TMR61_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4230052CUL))) +#define bM4_TMR61_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42300530UL))) +#define bM4_TMR61_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42300534UL))) +#define bM4_TMR61_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42300538UL))) +#define bM4_TMR61_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4230053CUL))) +#define bM4_TMR61_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42300580UL))) +#define bM4_TMR61_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42300584UL))) +#define bM4_TMR61_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42300588UL))) +#define bM4_TMR61_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4230058CUL))) +#define bM4_TMR61_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42300590UL))) +#define bM4_TMR61_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42300594UL))) +#define bM4_TMR61_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42300598UL))) +#define bM4_TMR61_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4230059CUL))) +#define bM4_TMR61_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423005A0UL))) +#define bM4_TMR61_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423005A4UL))) +#define bM4_TMR61_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423005A8UL))) +#define bM4_TMR61_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423005ACUL))) +#define bM4_TMR61_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423005B0UL))) +#define bM4_TMR61_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423005B4UL))) +#define bM4_TMR61_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423005B8UL))) +#define bM4_TMR61_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423005BCUL))) +#define bM4_TMR61_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42300600UL))) +#define bM4_TMR61_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42300604UL))) +#define bM4_TMR61_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42300608UL))) +#define bM4_TMR61_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4230060CUL))) +#define bM4_TMR61_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42300610UL))) +#define bM4_TMR61_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42300614UL))) +#define bM4_TMR61_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42300618UL))) +#define bM4_TMR61_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4230061CUL))) +#define bM4_TMR61_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42300620UL))) +#define bM4_TMR61_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42300624UL))) +#define bM4_TMR61_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42300628UL))) +#define bM4_TMR61_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4230062CUL))) +#define bM4_TMR61_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42300630UL))) +#define bM4_TMR61_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42300634UL))) +#define bM4_TMR61_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42300638UL))) +#define bM4_TMR61_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4230063CUL))) +#define bM4_TMR61_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42300680UL))) +#define bM4_TMR61_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42300684UL))) +#define bM4_TMR61_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42300688UL))) +#define bM4_TMR61_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4230068CUL))) +#define bM4_TMR61_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42300690UL))) +#define bM4_TMR61_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42300694UL))) +#define bM4_TMR61_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42300698UL))) +#define bM4_TMR61_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4230069CUL))) +#define bM4_TMR61_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423006A0UL))) +#define bM4_TMR61_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423006A4UL))) +#define bM4_TMR61_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423006A8UL))) +#define bM4_TMR61_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423006ACUL))) +#define bM4_TMR61_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423006B0UL))) +#define bM4_TMR61_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423006B4UL))) +#define bM4_TMR61_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423006B8UL))) +#define bM4_TMR61_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423006BCUL))) +#define bM4_TMR61_SCMER_SCME0 (*((volatile unsigned int*)(0x42300700UL))) +#define bM4_TMR61_SCMER_SCME1 (*((volatile unsigned int*)(0x42300704UL))) +#define bM4_TMR61_SCMER_SCME2 (*((volatile unsigned int*)(0x42300708UL))) +#define bM4_TMR61_SCMER_SCME3 (*((volatile unsigned int*)(0x4230070CUL))) +#define bM4_TMR61_SCMER_SCME4 (*((volatile unsigned int*)(0x42300710UL))) +#define bM4_TMR61_SCMER_SCME5 (*((volatile unsigned int*)(0x42300714UL))) +#define bM4_TMR61_SCMER_SCME6 (*((volatile unsigned int*)(0x42300718UL))) +#define bM4_TMR61_SCMER_SCME7 (*((volatile unsigned int*)(0x4230071CUL))) +#define bM4_TMR61_SCMER_SCME8 (*((volatile unsigned int*)(0x42300720UL))) +#define bM4_TMR61_SCMER_SCME9 (*((volatile unsigned int*)(0x42300724UL))) +#define bM4_TMR61_SCMER_SCME10 (*((volatile unsigned int*)(0x42300728UL))) +#define bM4_TMR61_SCMER_SCME11 (*((volatile unsigned int*)(0x4230072CUL))) +#define bM4_TMR61_SCMER_SCME12 (*((volatile unsigned int*)(0x42300730UL))) +#define bM4_TMR61_SCMER_SCME13 (*((volatile unsigned int*)(0x42300734UL))) +#define bM4_TMR61_SCMER_SCME14 (*((volatile unsigned int*)(0x42300738UL))) +#define bM4_TMR61_SCMER_SCME15 (*((volatile unsigned int*)(0x4230073CUL))) +#define bM4_TMR61_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42300780UL))) +#define bM4_TMR61_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42300784UL))) +#define bM4_TMR61_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42300788UL))) +#define bM4_TMR61_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4230078CUL))) +#define bM4_TMR61_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42300790UL))) +#define bM4_TMR61_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42300794UL))) +#define bM4_TMR61_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42300798UL))) +#define bM4_TMR61_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4230079CUL))) +#define bM4_TMR61_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423007A0UL))) +#define bM4_TMR61_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423007A4UL))) +#define bM4_TMR61_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423007A8UL))) +#define bM4_TMR61_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423007ACUL))) +#define bM4_TMR61_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423007B0UL))) +#define bM4_TMR61_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423007B4UL))) +#define bM4_TMR61_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423007B8UL))) +#define bM4_TMR61_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423007BCUL))) +#define bM4_TMR61_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42300800UL))) +#define bM4_TMR61_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42300804UL))) +#define bM4_TMR61_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42300808UL))) +#define bM4_TMR61_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4230080CUL))) +#define bM4_TMR61_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42300810UL))) +#define bM4_TMR61_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42300814UL))) +#define bM4_TMR61_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42300818UL))) +#define bM4_TMR61_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4230081CUL))) +#define bM4_TMR61_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42300820UL))) +#define bM4_TMR61_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42300824UL))) +#define bM4_TMR61_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42300828UL))) +#define bM4_TMR61_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4230082CUL))) +#define bM4_TMR61_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42300830UL))) +#define bM4_TMR61_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42300834UL))) +#define bM4_TMR61_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42300838UL))) +#define bM4_TMR61_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4230083CUL))) +#define bM4_TMR61_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42300880UL))) +#define bM4_TMR61_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42300884UL))) +#define bM4_TMR61_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42300888UL))) +#define bM4_TMR61_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4230088CUL))) +#define bM4_TMR61_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42300890UL))) +#define bM4_TMR61_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42300894UL))) +#define bM4_TMR61_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42300898UL))) +#define bM4_TMR61_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4230089CUL))) +#define bM4_TMR61_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423008A0UL))) +#define bM4_TMR61_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423008A4UL))) +#define bM4_TMR61_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423008A8UL))) +#define bM4_TMR61_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423008ACUL))) +#define bM4_TMR61_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423008B0UL))) +#define bM4_TMR61_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423008B4UL))) +#define bM4_TMR61_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423008B8UL))) +#define bM4_TMR61_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423008BCUL))) +#define bM4_TMR61_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42300900UL))) +#define bM4_TMR61_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42300904UL))) +#define bM4_TMR61_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42300908UL))) +#define bM4_TMR61_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4230090CUL))) +#define bM4_TMR61_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42300910UL))) +#define bM4_TMR61_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42300914UL))) +#define bM4_TMR61_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42300918UL))) +#define bM4_TMR61_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4230091CUL))) +#define bM4_TMR61_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42300920UL))) +#define bM4_TMR61_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42300924UL))) +#define bM4_TMR61_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42300928UL))) +#define bM4_TMR61_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4230092CUL))) +#define bM4_TMR61_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42300930UL))) +#define bM4_TMR61_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42300934UL))) +#define bM4_TMR61_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42300938UL))) +#define bM4_TMR61_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4230093CUL))) +#define bM4_TMR61_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42300980UL))) +#define bM4_TMR61_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42300984UL))) +#define bM4_TMR61_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42300988UL))) +#define bM4_TMR61_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4230098CUL))) +#define bM4_TMR61_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42300990UL))) +#define bM4_TMR61_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42300994UL))) +#define bM4_TMR61_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42300998UL))) +#define bM4_TMR61_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4230099CUL))) +#define bM4_TMR61_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423009A0UL))) +#define bM4_TMR61_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423009A4UL))) +#define bM4_TMR61_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423009A8UL))) +#define bM4_TMR61_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423009ACUL))) +#define bM4_TMR61_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423009B0UL))) +#define bM4_TMR61_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423009B4UL))) +#define bM4_TMR61_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423009B8UL))) +#define bM4_TMR61_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423009BCUL))) +#define bM4_TMR61_GCONR_START (*((volatile unsigned int*)(0x42300A00UL))) +#define bM4_TMR61_GCONR_MODE0 (*((volatile unsigned int*)(0x42300A04UL))) +#define bM4_TMR61_GCONR_MODE1 (*((volatile unsigned int*)(0x42300A08UL))) +#define bM4_TMR61_GCONR_MODE2 (*((volatile unsigned int*)(0x42300A0CUL))) +#define bM4_TMR61_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42300A10UL))) +#define bM4_TMR61_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42300A14UL))) +#define bM4_TMR61_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42300A18UL))) +#define bM4_TMR61_GCONR_DIR (*((volatile unsigned int*)(0x42300A20UL))) +#define bM4_TMR61_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42300A40UL))) +#define bM4_TMR61_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42300A44UL))) +#define bM4_TMR61_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42300A48UL))) +#define bM4_TMR61_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42300A4CUL))) +#define bM4_TMR61_ICONR_INTENA (*((volatile unsigned int*)(0x42300A80UL))) +#define bM4_TMR61_ICONR_INTENB (*((volatile unsigned int*)(0x42300A84UL))) +#define bM4_TMR61_ICONR_INTENC (*((volatile unsigned int*)(0x42300A88UL))) +#define bM4_TMR61_ICONR_INTEND (*((volatile unsigned int*)(0x42300A8CUL))) +#define bM4_TMR61_ICONR_INTENE (*((volatile unsigned int*)(0x42300A90UL))) +#define bM4_TMR61_ICONR_INTENF (*((volatile unsigned int*)(0x42300A94UL))) +#define bM4_TMR61_ICONR_INTENOVF (*((volatile unsigned int*)(0x42300A98UL))) +#define bM4_TMR61_ICONR_INTENUDF (*((volatile unsigned int*)(0x42300A9CUL))) +#define bM4_TMR61_ICONR_INTENDTE (*((volatile unsigned int*)(0x42300AA0UL))) +#define bM4_TMR61_ICONR_INTENSAU (*((volatile unsigned int*)(0x42300AC0UL))) +#define bM4_TMR61_ICONR_INTENSAD (*((volatile unsigned int*)(0x42300AC4UL))) +#define bM4_TMR61_ICONR_INTENSBU (*((volatile unsigned int*)(0x42300AC8UL))) +#define bM4_TMR61_ICONR_INTENSBD (*((volatile unsigned int*)(0x42300ACCUL))) +#define bM4_TMR61_PCONR_CAPMDA (*((volatile unsigned int*)(0x42300B00UL))) +#define bM4_TMR61_PCONR_STACA (*((volatile unsigned int*)(0x42300B04UL))) +#define bM4_TMR61_PCONR_STPCA (*((volatile unsigned int*)(0x42300B08UL))) +#define bM4_TMR61_PCONR_STASTPSA (*((volatile unsigned int*)(0x42300B0CUL))) +#define bM4_TMR61_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42300B10UL))) +#define bM4_TMR61_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42300B14UL))) +#define bM4_TMR61_PCONR_PERCA0 (*((volatile unsigned int*)(0x42300B18UL))) +#define bM4_TMR61_PCONR_PERCA1 (*((volatile unsigned int*)(0x42300B1CUL))) +#define bM4_TMR61_PCONR_OUTENA (*((volatile unsigned int*)(0x42300B20UL))) +#define bM4_TMR61_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42300B2CUL))) +#define bM4_TMR61_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42300B30UL))) +#define bM4_TMR61_PCONR_CAPMDB (*((volatile unsigned int*)(0x42300B40UL))) +#define bM4_TMR61_PCONR_STACB (*((volatile unsigned int*)(0x42300B44UL))) +#define bM4_TMR61_PCONR_STPCB (*((volatile unsigned int*)(0x42300B48UL))) +#define bM4_TMR61_PCONR_STASTPSB (*((volatile unsigned int*)(0x42300B4CUL))) +#define bM4_TMR61_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42300B50UL))) +#define bM4_TMR61_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42300B54UL))) +#define bM4_TMR61_PCONR_PERCB0 (*((volatile unsigned int*)(0x42300B58UL))) +#define bM4_TMR61_PCONR_PERCB1 (*((volatile unsigned int*)(0x42300B5CUL))) +#define bM4_TMR61_PCONR_OUTENB (*((volatile unsigned int*)(0x42300B60UL))) +#define bM4_TMR61_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42300B6CUL))) +#define bM4_TMR61_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42300B70UL))) +#define bM4_TMR61_BCONR_BENA (*((volatile unsigned int*)(0x42300B80UL))) +#define bM4_TMR61_BCONR_BSEA (*((volatile unsigned int*)(0x42300B84UL))) +#define bM4_TMR61_BCONR_BENB (*((volatile unsigned int*)(0x42300B88UL))) +#define bM4_TMR61_BCONR_BSEB (*((volatile unsigned int*)(0x42300B8CUL))) +#define bM4_TMR61_BCONR_BENP (*((volatile unsigned int*)(0x42300BA0UL))) +#define bM4_TMR61_BCONR_BSEP (*((volatile unsigned int*)(0x42300BA4UL))) +#define bM4_TMR61_BCONR_BENSPA (*((volatile unsigned int*)(0x42300BC0UL))) +#define bM4_TMR61_BCONR_BSESPA (*((volatile unsigned int*)(0x42300BC4UL))) +#define bM4_TMR61_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42300BD0UL))) +#define bM4_TMR61_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42300BD4UL))) +#define bM4_TMR61_BCONR_BENSPB (*((volatile unsigned int*)(0x42300BE0UL))) +#define bM4_TMR61_BCONR_BSESPB (*((volatile unsigned int*)(0x42300BE4UL))) +#define bM4_TMR61_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42300BF0UL))) +#define bM4_TMR61_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42300BF4UL))) +#define bM4_TMR61_DCONR_DTCEN (*((volatile unsigned int*)(0x42300C00UL))) +#define bM4_TMR61_DCONR_DTBENU (*((volatile unsigned int*)(0x42300C10UL))) +#define bM4_TMR61_DCONR_DTBEND (*((volatile unsigned int*)(0x42300C14UL))) +#define bM4_TMR61_DCONR_SEPA (*((volatile unsigned int*)(0x42300C20UL))) +#define bM4_TMR61_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42300D00UL))) +#define bM4_TMR61_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42300D04UL))) +#define bM4_TMR61_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42300D08UL))) +#define bM4_TMR61_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42300D10UL))) +#define bM4_TMR61_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42300D14UL))) +#define bM4_TMR61_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42300D18UL))) +#define bM4_TMR61_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42300D40UL))) +#define bM4_TMR61_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42300D44UL))) +#define bM4_TMR61_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42300D48UL))) +#define bM4_TMR61_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42300D50UL))) +#define bM4_TMR61_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42300D54UL))) +#define bM4_TMR61_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42300D58UL))) +#define bM4_TMR61_VPERR_SPPERIA (*((volatile unsigned int*)(0x42300DA0UL))) +#define bM4_TMR61_VPERR_SPPERIB (*((volatile unsigned int*)(0x42300DA4UL))) +#define bM4_TMR61_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42300DC0UL))) +#define bM4_TMR61_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42300DC4UL))) +#define bM4_TMR61_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42300DC8UL))) +#define bM4_TMR61_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42300DCCUL))) +#define bM4_TMR61_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42300DD0UL))) +#define bM4_TMR61_STFLR_CMAF (*((volatile unsigned int*)(0x42300E00UL))) +#define bM4_TMR61_STFLR_CMBF (*((volatile unsigned int*)(0x42300E04UL))) +#define bM4_TMR61_STFLR_CMCF (*((volatile unsigned int*)(0x42300E08UL))) +#define bM4_TMR61_STFLR_CMDF (*((volatile unsigned int*)(0x42300E0CUL))) +#define bM4_TMR61_STFLR_CMEF (*((volatile unsigned int*)(0x42300E10UL))) +#define bM4_TMR61_STFLR_CMFF (*((volatile unsigned int*)(0x42300E14UL))) +#define bM4_TMR61_STFLR_OVFF (*((volatile unsigned int*)(0x42300E18UL))) +#define bM4_TMR61_STFLR_UDFF (*((volatile unsigned int*)(0x42300E1CUL))) +#define bM4_TMR61_STFLR_DTEF (*((volatile unsigned int*)(0x42300E20UL))) +#define bM4_TMR61_STFLR_CMSAUF (*((volatile unsigned int*)(0x42300E24UL))) +#define bM4_TMR61_STFLR_CMSADF (*((volatile unsigned int*)(0x42300E28UL))) +#define bM4_TMR61_STFLR_CMSBUF (*((volatile unsigned int*)(0x42300E2CUL))) +#define bM4_TMR61_STFLR_CMSBDF (*((volatile unsigned int*)(0x42300E30UL))) +#define bM4_TMR61_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42300E54UL))) +#define bM4_TMR61_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42300E58UL))) +#define bM4_TMR61_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42300E5CUL))) +#define bM4_TMR61_STFLR_DIRF (*((volatile unsigned int*)(0x42300E7CUL))) +#define bM4_TMR61_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42300E80UL))) +#define bM4_TMR61_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42300E84UL))) +#define bM4_TMR61_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42300E90UL))) +#define bM4_TMR61_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42300E94UL))) +#define bM4_TMR61_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42300E98UL))) +#define bM4_TMR61_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42300E9CUL))) +#define bM4_TMR61_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42300EA0UL))) +#define bM4_TMR61_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42300EA4UL))) +#define bM4_TMR61_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42300EA8UL))) +#define bM4_TMR61_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42300EACUL))) +#define bM4_TMR61_HSTAR_STARTS (*((volatile unsigned int*)(0x42300EFCUL))) +#define bM4_TMR61_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42300F00UL))) +#define bM4_TMR61_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42300F04UL))) +#define bM4_TMR61_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42300F10UL))) +#define bM4_TMR61_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42300F14UL))) +#define bM4_TMR61_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42300F18UL))) +#define bM4_TMR61_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42300F1CUL))) +#define bM4_TMR61_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42300F20UL))) +#define bM4_TMR61_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42300F24UL))) +#define bM4_TMR61_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42300F28UL))) +#define bM4_TMR61_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42300F2CUL))) +#define bM4_TMR61_HSTPR_STOPS (*((volatile unsigned int*)(0x42300F7CUL))) +#define bM4_TMR61_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42300F80UL))) +#define bM4_TMR61_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42300F84UL))) +#define bM4_TMR61_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42300F90UL))) +#define bM4_TMR61_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42300F94UL))) +#define bM4_TMR61_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42300F98UL))) +#define bM4_TMR61_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42300F9CUL))) +#define bM4_TMR61_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42300FA0UL))) +#define bM4_TMR61_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42300FA4UL))) +#define bM4_TMR61_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42300FA8UL))) +#define bM4_TMR61_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42300FACUL))) +#define bM4_TMR61_HCLRR_CLEARS (*((volatile unsigned int*)(0x42300FFCUL))) +#define bM4_TMR61_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42301000UL))) +#define bM4_TMR61_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42301004UL))) +#define bM4_TMR61_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42301010UL))) +#define bM4_TMR61_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42301014UL))) +#define bM4_TMR61_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42301018UL))) +#define bM4_TMR61_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4230101CUL))) +#define bM4_TMR61_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42301020UL))) +#define bM4_TMR61_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42301024UL))) +#define bM4_TMR61_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42301028UL))) +#define bM4_TMR61_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4230102CUL))) +#define bM4_TMR61_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42301080UL))) +#define bM4_TMR61_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42301084UL))) +#define bM4_TMR61_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42301090UL))) +#define bM4_TMR61_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42301094UL))) +#define bM4_TMR61_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42301098UL))) +#define bM4_TMR61_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4230109CUL))) +#define bM4_TMR61_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423010A0UL))) +#define bM4_TMR61_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423010A4UL))) +#define bM4_TMR61_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423010A8UL))) +#define bM4_TMR61_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423010ACUL))) +#define bM4_TMR61_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42301100UL))) +#define bM4_TMR61_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42301104UL))) +#define bM4_TMR61_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42301108UL))) +#define bM4_TMR61_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4230110CUL))) +#define bM4_TMR61_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42301110UL))) +#define bM4_TMR61_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42301114UL))) +#define bM4_TMR61_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42301118UL))) +#define bM4_TMR61_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4230111CUL))) +#define bM4_TMR61_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42301120UL))) +#define bM4_TMR61_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42301124UL))) +#define bM4_TMR61_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42301128UL))) +#define bM4_TMR61_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4230112CUL))) +#define bM4_TMR61_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42301140UL))) +#define bM4_TMR61_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42301144UL))) +#define bM4_TMR61_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42301180UL))) +#define bM4_TMR61_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42301184UL))) +#define bM4_TMR61_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42301188UL))) +#define bM4_TMR61_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4230118CUL))) +#define bM4_TMR61_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42301190UL))) +#define bM4_TMR61_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42301194UL))) +#define bM4_TMR61_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42301198UL))) +#define bM4_TMR61_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4230119CUL))) +#define bM4_TMR61_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423011A0UL))) +#define bM4_TMR61_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423011A4UL))) +#define bM4_TMR61_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423011A8UL))) +#define bM4_TMR61_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423011ACUL))) +#define bM4_TMR61_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423011C0UL))) +#define bM4_TMR61_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423011C4UL))) +#define bM4_TMR62_CNTER_CNT0 (*((volatile unsigned int*)(0x42308000UL))) +#define bM4_TMR62_CNTER_CNT1 (*((volatile unsigned int*)(0x42308004UL))) +#define bM4_TMR62_CNTER_CNT2 (*((volatile unsigned int*)(0x42308008UL))) +#define bM4_TMR62_CNTER_CNT3 (*((volatile unsigned int*)(0x4230800CUL))) +#define bM4_TMR62_CNTER_CNT4 (*((volatile unsigned int*)(0x42308010UL))) +#define bM4_TMR62_CNTER_CNT5 (*((volatile unsigned int*)(0x42308014UL))) +#define bM4_TMR62_CNTER_CNT6 (*((volatile unsigned int*)(0x42308018UL))) +#define bM4_TMR62_CNTER_CNT7 (*((volatile unsigned int*)(0x4230801CUL))) +#define bM4_TMR62_CNTER_CNT8 (*((volatile unsigned int*)(0x42308020UL))) +#define bM4_TMR62_CNTER_CNT9 (*((volatile unsigned int*)(0x42308024UL))) +#define bM4_TMR62_CNTER_CNT10 (*((volatile unsigned int*)(0x42308028UL))) +#define bM4_TMR62_CNTER_CNT11 (*((volatile unsigned int*)(0x4230802CUL))) +#define bM4_TMR62_CNTER_CNT12 (*((volatile unsigned int*)(0x42308030UL))) +#define bM4_TMR62_CNTER_CNT13 (*((volatile unsigned int*)(0x42308034UL))) +#define bM4_TMR62_CNTER_CNT14 (*((volatile unsigned int*)(0x42308038UL))) +#define bM4_TMR62_CNTER_CNT15 (*((volatile unsigned int*)(0x4230803CUL))) +#define bM4_TMR62_PERAR_PERA0 (*((volatile unsigned int*)(0x42308080UL))) +#define bM4_TMR62_PERAR_PERA1 (*((volatile unsigned int*)(0x42308084UL))) +#define bM4_TMR62_PERAR_PERA2 (*((volatile unsigned int*)(0x42308088UL))) +#define bM4_TMR62_PERAR_PERA3 (*((volatile unsigned int*)(0x4230808CUL))) +#define bM4_TMR62_PERAR_PERA4 (*((volatile unsigned int*)(0x42308090UL))) +#define bM4_TMR62_PERAR_PERA5 (*((volatile unsigned int*)(0x42308094UL))) +#define bM4_TMR62_PERAR_PERA6 (*((volatile unsigned int*)(0x42308098UL))) +#define bM4_TMR62_PERAR_PERA7 (*((volatile unsigned int*)(0x4230809CUL))) +#define bM4_TMR62_PERAR_PERA8 (*((volatile unsigned int*)(0x423080A0UL))) +#define bM4_TMR62_PERAR_PERA9 (*((volatile unsigned int*)(0x423080A4UL))) +#define bM4_TMR62_PERAR_PERA10 (*((volatile unsigned int*)(0x423080A8UL))) +#define bM4_TMR62_PERAR_PERA11 (*((volatile unsigned int*)(0x423080ACUL))) +#define bM4_TMR62_PERAR_PERA12 (*((volatile unsigned int*)(0x423080B0UL))) +#define bM4_TMR62_PERAR_PERA13 (*((volatile unsigned int*)(0x423080B4UL))) +#define bM4_TMR62_PERAR_PERA14 (*((volatile unsigned int*)(0x423080B8UL))) +#define bM4_TMR62_PERAR_PERA15 (*((volatile unsigned int*)(0x423080BCUL))) +#define bM4_TMR62_PERBR_PERB0 (*((volatile unsigned int*)(0x42308100UL))) +#define bM4_TMR62_PERBR_PERB1 (*((volatile unsigned int*)(0x42308104UL))) +#define bM4_TMR62_PERBR_PERB2 (*((volatile unsigned int*)(0x42308108UL))) +#define bM4_TMR62_PERBR_PERB3 (*((volatile unsigned int*)(0x4230810CUL))) +#define bM4_TMR62_PERBR_PERB4 (*((volatile unsigned int*)(0x42308110UL))) +#define bM4_TMR62_PERBR_PERB5 (*((volatile unsigned int*)(0x42308114UL))) +#define bM4_TMR62_PERBR_PERB6 (*((volatile unsigned int*)(0x42308118UL))) +#define bM4_TMR62_PERBR_PERB7 (*((volatile unsigned int*)(0x4230811CUL))) +#define bM4_TMR62_PERBR_PERB8 (*((volatile unsigned int*)(0x42308120UL))) +#define bM4_TMR62_PERBR_PERB9 (*((volatile unsigned int*)(0x42308124UL))) +#define bM4_TMR62_PERBR_PERB10 (*((volatile unsigned int*)(0x42308128UL))) +#define bM4_TMR62_PERBR_PERB11 (*((volatile unsigned int*)(0x4230812CUL))) +#define bM4_TMR62_PERBR_PERB12 (*((volatile unsigned int*)(0x42308130UL))) +#define bM4_TMR62_PERBR_PERB13 (*((volatile unsigned int*)(0x42308134UL))) +#define bM4_TMR62_PERBR_PERB14 (*((volatile unsigned int*)(0x42308138UL))) +#define bM4_TMR62_PERBR_PERB15 (*((volatile unsigned int*)(0x4230813CUL))) +#define bM4_TMR62_PERCR_PERC0 (*((volatile unsigned int*)(0x42308180UL))) +#define bM4_TMR62_PERCR_PERC1 (*((volatile unsigned int*)(0x42308184UL))) +#define bM4_TMR62_PERCR_PERC2 (*((volatile unsigned int*)(0x42308188UL))) +#define bM4_TMR62_PERCR_PERC3 (*((volatile unsigned int*)(0x4230818CUL))) +#define bM4_TMR62_PERCR_PERC4 (*((volatile unsigned int*)(0x42308190UL))) +#define bM4_TMR62_PERCR_PERC5 (*((volatile unsigned int*)(0x42308194UL))) +#define bM4_TMR62_PERCR_PERC6 (*((volatile unsigned int*)(0x42308198UL))) +#define bM4_TMR62_PERCR_PERC7 (*((volatile unsigned int*)(0x4230819CUL))) +#define bM4_TMR62_PERCR_PERC8 (*((volatile unsigned int*)(0x423081A0UL))) +#define bM4_TMR62_PERCR_PERC9 (*((volatile unsigned int*)(0x423081A4UL))) +#define bM4_TMR62_PERCR_PERC10 (*((volatile unsigned int*)(0x423081A8UL))) +#define bM4_TMR62_PERCR_PERC11 (*((volatile unsigned int*)(0x423081ACUL))) +#define bM4_TMR62_PERCR_PERC12 (*((volatile unsigned int*)(0x423081B0UL))) +#define bM4_TMR62_PERCR_PERC13 (*((volatile unsigned int*)(0x423081B4UL))) +#define bM4_TMR62_PERCR_PERC14 (*((volatile unsigned int*)(0x423081B8UL))) +#define bM4_TMR62_PERCR_PERC15 (*((volatile unsigned int*)(0x423081BCUL))) +#define bM4_TMR62_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42308200UL))) +#define bM4_TMR62_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42308204UL))) +#define bM4_TMR62_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42308208UL))) +#define bM4_TMR62_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4230820CUL))) +#define bM4_TMR62_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42308210UL))) +#define bM4_TMR62_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42308214UL))) +#define bM4_TMR62_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42308218UL))) +#define bM4_TMR62_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4230821CUL))) +#define bM4_TMR62_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42308220UL))) +#define bM4_TMR62_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42308224UL))) +#define bM4_TMR62_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42308228UL))) +#define bM4_TMR62_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4230822CUL))) +#define bM4_TMR62_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42308230UL))) +#define bM4_TMR62_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42308234UL))) +#define bM4_TMR62_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42308238UL))) +#define bM4_TMR62_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4230823CUL))) +#define bM4_TMR62_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42308280UL))) +#define bM4_TMR62_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42308284UL))) +#define bM4_TMR62_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42308288UL))) +#define bM4_TMR62_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4230828CUL))) +#define bM4_TMR62_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42308290UL))) +#define bM4_TMR62_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42308294UL))) +#define bM4_TMR62_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42308298UL))) +#define bM4_TMR62_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4230829CUL))) +#define bM4_TMR62_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423082A0UL))) +#define bM4_TMR62_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423082A4UL))) +#define bM4_TMR62_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423082A8UL))) +#define bM4_TMR62_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423082ACUL))) +#define bM4_TMR62_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423082B0UL))) +#define bM4_TMR62_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423082B4UL))) +#define bM4_TMR62_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423082B8UL))) +#define bM4_TMR62_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423082BCUL))) +#define bM4_TMR62_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42308300UL))) +#define bM4_TMR62_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42308304UL))) +#define bM4_TMR62_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42308308UL))) +#define bM4_TMR62_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4230830CUL))) +#define bM4_TMR62_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42308310UL))) +#define bM4_TMR62_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42308314UL))) +#define bM4_TMR62_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42308318UL))) +#define bM4_TMR62_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4230831CUL))) +#define bM4_TMR62_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42308320UL))) +#define bM4_TMR62_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42308324UL))) +#define bM4_TMR62_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42308328UL))) +#define bM4_TMR62_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4230832CUL))) +#define bM4_TMR62_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42308330UL))) +#define bM4_TMR62_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42308334UL))) +#define bM4_TMR62_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42308338UL))) +#define bM4_TMR62_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4230833CUL))) +#define bM4_TMR62_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42308380UL))) +#define bM4_TMR62_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42308384UL))) +#define bM4_TMR62_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42308388UL))) +#define bM4_TMR62_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4230838CUL))) +#define bM4_TMR62_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42308390UL))) +#define bM4_TMR62_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42308394UL))) +#define bM4_TMR62_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42308398UL))) +#define bM4_TMR62_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4230839CUL))) +#define bM4_TMR62_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423083A0UL))) +#define bM4_TMR62_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423083A4UL))) +#define bM4_TMR62_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423083A8UL))) +#define bM4_TMR62_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423083ACUL))) +#define bM4_TMR62_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423083B0UL))) +#define bM4_TMR62_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423083B4UL))) +#define bM4_TMR62_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423083B8UL))) +#define bM4_TMR62_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423083BCUL))) +#define bM4_TMR62_GCMER_GCME0 (*((volatile unsigned int*)(0x42308400UL))) +#define bM4_TMR62_GCMER_GCME1 (*((volatile unsigned int*)(0x42308404UL))) +#define bM4_TMR62_GCMER_GCME2 (*((volatile unsigned int*)(0x42308408UL))) +#define bM4_TMR62_GCMER_GCME3 (*((volatile unsigned int*)(0x4230840CUL))) +#define bM4_TMR62_GCMER_GCME4 (*((volatile unsigned int*)(0x42308410UL))) +#define bM4_TMR62_GCMER_GCME5 (*((volatile unsigned int*)(0x42308414UL))) +#define bM4_TMR62_GCMER_GCME6 (*((volatile unsigned int*)(0x42308418UL))) +#define bM4_TMR62_GCMER_GCME7 (*((volatile unsigned int*)(0x4230841CUL))) +#define bM4_TMR62_GCMER_GCME8 (*((volatile unsigned int*)(0x42308420UL))) +#define bM4_TMR62_GCMER_GCME9 (*((volatile unsigned int*)(0x42308424UL))) +#define bM4_TMR62_GCMER_GCME10 (*((volatile unsigned int*)(0x42308428UL))) +#define bM4_TMR62_GCMER_GCME11 (*((volatile unsigned int*)(0x4230842CUL))) +#define bM4_TMR62_GCMER_GCME12 (*((volatile unsigned int*)(0x42308430UL))) +#define bM4_TMR62_GCMER_GCME13 (*((volatile unsigned int*)(0x42308434UL))) +#define bM4_TMR62_GCMER_GCME14 (*((volatile unsigned int*)(0x42308438UL))) +#define bM4_TMR62_GCMER_GCME15 (*((volatile unsigned int*)(0x4230843CUL))) +#define bM4_TMR62_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42308480UL))) +#define bM4_TMR62_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42308484UL))) +#define bM4_TMR62_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42308488UL))) +#define bM4_TMR62_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4230848CUL))) +#define bM4_TMR62_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42308490UL))) +#define bM4_TMR62_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42308494UL))) +#define bM4_TMR62_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42308498UL))) +#define bM4_TMR62_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4230849CUL))) +#define bM4_TMR62_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423084A0UL))) +#define bM4_TMR62_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423084A4UL))) +#define bM4_TMR62_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423084A8UL))) +#define bM4_TMR62_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423084ACUL))) +#define bM4_TMR62_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423084B0UL))) +#define bM4_TMR62_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423084B4UL))) +#define bM4_TMR62_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423084B8UL))) +#define bM4_TMR62_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423084BCUL))) +#define bM4_TMR62_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42308500UL))) +#define bM4_TMR62_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42308504UL))) +#define bM4_TMR62_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42308508UL))) +#define bM4_TMR62_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4230850CUL))) +#define bM4_TMR62_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42308510UL))) +#define bM4_TMR62_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42308514UL))) +#define bM4_TMR62_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42308518UL))) +#define bM4_TMR62_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4230851CUL))) +#define bM4_TMR62_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42308520UL))) +#define bM4_TMR62_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42308524UL))) +#define bM4_TMR62_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42308528UL))) +#define bM4_TMR62_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4230852CUL))) +#define bM4_TMR62_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42308530UL))) +#define bM4_TMR62_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42308534UL))) +#define bM4_TMR62_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42308538UL))) +#define bM4_TMR62_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4230853CUL))) +#define bM4_TMR62_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42308580UL))) +#define bM4_TMR62_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42308584UL))) +#define bM4_TMR62_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42308588UL))) +#define bM4_TMR62_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4230858CUL))) +#define bM4_TMR62_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42308590UL))) +#define bM4_TMR62_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42308594UL))) +#define bM4_TMR62_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42308598UL))) +#define bM4_TMR62_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4230859CUL))) +#define bM4_TMR62_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423085A0UL))) +#define bM4_TMR62_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423085A4UL))) +#define bM4_TMR62_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423085A8UL))) +#define bM4_TMR62_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423085ACUL))) +#define bM4_TMR62_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423085B0UL))) +#define bM4_TMR62_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423085B4UL))) +#define bM4_TMR62_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423085B8UL))) +#define bM4_TMR62_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423085BCUL))) +#define bM4_TMR62_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42308600UL))) +#define bM4_TMR62_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42308604UL))) +#define bM4_TMR62_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42308608UL))) +#define bM4_TMR62_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4230860CUL))) +#define bM4_TMR62_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42308610UL))) +#define bM4_TMR62_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42308614UL))) +#define bM4_TMR62_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42308618UL))) +#define bM4_TMR62_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4230861CUL))) +#define bM4_TMR62_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42308620UL))) +#define bM4_TMR62_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42308624UL))) +#define bM4_TMR62_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42308628UL))) +#define bM4_TMR62_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4230862CUL))) +#define bM4_TMR62_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42308630UL))) +#define bM4_TMR62_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42308634UL))) +#define bM4_TMR62_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42308638UL))) +#define bM4_TMR62_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4230863CUL))) +#define bM4_TMR62_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42308680UL))) +#define bM4_TMR62_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42308684UL))) +#define bM4_TMR62_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42308688UL))) +#define bM4_TMR62_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4230868CUL))) +#define bM4_TMR62_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42308690UL))) +#define bM4_TMR62_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42308694UL))) +#define bM4_TMR62_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42308698UL))) +#define bM4_TMR62_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4230869CUL))) +#define bM4_TMR62_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423086A0UL))) +#define bM4_TMR62_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423086A4UL))) +#define bM4_TMR62_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423086A8UL))) +#define bM4_TMR62_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423086ACUL))) +#define bM4_TMR62_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423086B0UL))) +#define bM4_TMR62_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423086B4UL))) +#define bM4_TMR62_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423086B8UL))) +#define bM4_TMR62_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423086BCUL))) +#define bM4_TMR62_SCMER_SCME0 (*((volatile unsigned int*)(0x42308700UL))) +#define bM4_TMR62_SCMER_SCME1 (*((volatile unsigned int*)(0x42308704UL))) +#define bM4_TMR62_SCMER_SCME2 (*((volatile unsigned int*)(0x42308708UL))) +#define bM4_TMR62_SCMER_SCME3 (*((volatile unsigned int*)(0x4230870CUL))) +#define bM4_TMR62_SCMER_SCME4 (*((volatile unsigned int*)(0x42308710UL))) +#define bM4_TMR62_SCMER_SCME5 (*((volatile unsigned int*)(0x42308714UL))) +#define bM4_TMR62_SCMER_SCME6 (*((volatile unsigned int*)(0x42308718UL))) +#define bM4_TMR62_SCMER_SCME7 (*((volatile unsigned int*)(0x4230871CUL))) +#define bM4_TMR62_SCMER_SCME8 (*((volatile unsigned int*)(0x42308720UL))) +#define bM4_TMR62_SCMER_SCME9 (*((volatile unsigned int*)(0x42308724UL))) +#define bM4_TMR62_SCMER_SCME10 (*((volatile unsigned int*)(0x42308728UL))) +#define bM4_TMR62_SCMER_SCME11 (*((volatile unsigned int*)(0x4230872CUL))) +#define bM4_TMR62_SCMER_SCME12 (*((volatile unsigned int*)(0x42308730UL))) +#define bM4_TMR62_SCMER_SCME13 (*((volatile unsigned int*)(0x42308734UL))) +#define bM4_TMR62_SCMER_SCME14 (*((volatile unsigned int*)(0x42308738UL))) +#define bM4_TMR62_SCMER_SCME15 (*((volatile unsigned int*)(0x4230873CUL))) +#define bM4_TMR62_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42308780UL))) +#define bM4_TMR62_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42308784UL))) +#define bM4_TMR62_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42308788UL))) +#define bM4_TMR62_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4230878CUL))) +#define bM4_TMR62_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42308790UL))) +#define bM4_TMR62_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42308794UL))) +#define bM4_TMR62_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42308798UL))) +#define bM4_TMR62_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4230879CUL))) +#define bM4_TMR62_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423087A0UL))) +#define bM4_TMR62_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423087A4UL))) +#define bM4_TMR62_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423087A8UL))) +#define bM4_TMR62_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423087ACUL))) +#define bM4_TMR62_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423087B0UL))) +#define bM4_TMR62_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423087B4UL))) +#define bM4_TMR62_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423087B8UL))) +#define bM4_TMR62_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423087BCUL))) +#define bM4_TMR62_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42308800UL))) +#define bM4_TMR62_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42308804UL))) +#define bM4_TMR62_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42308808UL))) +#define bM4_TMR62_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4230880CUL))) +#define bM4_TMR62_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42308810UL))) +#define bM4_TMR62_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42308814UL))) +#define bM4_TMR62_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42308818UL))) +#define bM4_TMR62_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4230881CUL))) +#define bM4_TMR62_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42308820UL))) +#define bM4_TMR62_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42308824UL))) +#define bM4_TMR62_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42308828UL))) +#define bM4_TMR62_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4230882CUL))) +#define bM4_TMR62_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42308830UL))) +#define bM4_TMR62_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42308834UL))) +#define bM4_TMR62_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42308838UL))) +#define bM4_TMR62_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4230883CUL))) +#define bM4_TMR62_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42308880UL))) +#define bM4_TMR62_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42308884UL))) +#define bM4_TMR62_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42308888UL))) +#define bM4_TMR62_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4230888CUL))) +#define bM4_TMR62_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42308890UL))) +#define bM4_TMR62_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42308894UL))) +#define bM4_TMR62_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42308898UL))) +#define bM4_TMR62_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4230889CUL))) +#define bM4_TMR62_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423088A0UL))) +#define bM4_TMR62_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423088A4UL))) +#define bM4_TMR62_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423088A8UL))) +#define bM4_TMR62_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423088ACUL))) +#define bM4_TMR62_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423088B0UL))) +#define bM4_TMR62_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423088B4UL))) +#define bM4_TMR62_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423088B8UL))) +#define bM4_TMR62_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423088BCUL))) +#define bM4_TMR62_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42308900UL))) +#define bM4_TMR62_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42308904UL))) +#define bM4_TMR62_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42308908UL))) +#define bM4_TMR62_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4230890CUL))) +#define bM4_TMR62_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42308910UL))) +#define bM4_TMR62_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42308914UL))) +#define bM4_TMR62_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42308918UL))) +#define bM4_TMR62_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4230891CUL))) +#define bM4_TMR62_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42308920UL))) +#define bM4_TMR62_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42308924UL))) +#define bM4_TMR62_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42308928UL))) +#define bM4_TMR62_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4230892CUL))) +#define bM4_TMR62_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42308930UL))) +#define bM4_TMR62_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42308934UL))) +#define bM4_TMR62_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42308938UL))) +#define bM4_TMR62_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4230893CUL))) +#define bM4_TMR62_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42308980UL))) +#define bM4_TMR62_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42308984UL))) +#define bM4_TMR62_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42308988UL))) +#define bM4_TMR62_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4230898CUL))) +#define bM4_TMR62_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42308990UL))) +#define bM4_TMR62_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42308994UL))) +#define bM4_TMR62_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42308998UL))) +#define bM4_TMR62_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4230899CUL))) +#define bM4_TMR62_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423089A0UL))) +#define bM4_TMR62_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423089A4UL))) +#define bM4_TMR62_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423089A8UL))) +#define bM4_TMR62_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423089ACUL))) +#define bM4_TMR62_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423089B0UL))) +#define bM4_TMR62_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423089B4UL))) +#define bM4_TMR62_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423089B8UL))) +#define bM4_TMR62_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423089BCUL))) +#define bM4_TMR62_GCONR_START (*((volatile unsigned int*)(0x42308A00UL))) +#define bM4_TMR62_GCONR_MODE0 (*((volatile unsigned int*)(0x42308A04UL))) +#define bM4_TMR62_GCONR_MODE1 (*((volatile unsigned int*)(0x42308A08UL))) +#define bM4_TMR62_GCONR_MODE2 (*((volatile unsigned int*)(0x42308A0CUL))) +#define bM4_TMR62_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42308A10UL))) +#define bM4_TMR62_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42308A14UL))) +#define bM4_TMR62_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42308A18UL))) +#define bM4_TMR62_GCONR_DIR (*((volatile unsigned int*)(0x42308A20UL))) +#define bM4_TMR62_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42308A40UL))) +#define bM4_TMR62_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42308A44UL))) +#define bM4_TMR62_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42308A48UL))) +#define bM4_TMR62_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42308A4CUL))) +#define bM4_TMR62_ICONR_INTENA (*((volatile unsigned int*)(0x42308A80UL))) +#define bM4_TMR62_ICONR_INTENB (*((volatile unsigned int*)(0x42308A84UL))) +#define bM4_TMR62_ICONR_INTENC (*((volatile unsigned int*)(0x42308A88UL))) +#define bM4_TMR62_ICONR_INTEND (*((volatile unsigned int*)(0x42308A8CUL))) +#define bM4_TMR62_ICONR_INTENE (*((volatile unsigned int*)(0x42308A90UL))) +#define bM4_TMR62_ICONR_INTENF (*((volatile unsigned int*)(0x42308A94UL))) +#define bM4_TMR62_ICONR_INTENOVF (*((volatile unsigned int*)(0x42308A98UL))) +#define bM4_TMR62_ICONR_INTENUDF (*((volatile unsigned int*)(0x42308A9CUL))) +#define bM4_TMR62_ICONR_INTENDTE (*((volatile unsigned int*)(0x42308AA0UL))) +#define bM4_TMR62_ICONR_INTENSAU (*((volatile unsigned int*)(0x42308AC0UL))) +#define bM4_TMR62_ICONR_INTENSAD (*((volatile unsigned int*)(0x42308AC4UL))) +#define bM4_TMR62_ICONR_INTENSBU (*((volatile unsigned int*)(0x42308AC8UL))) +#define bM4_TMR62_ICONR_INTENSBD (*((volatile unsigned int*)(0x42308ACCUL))) +#define bM4_TMR62_PCONR_CAPMDA (*((volatile unsigned int*)(0x42308B00UL))) +#define bM4_TMR62_PCONR_STACA (*((volatile unsigned int*)(0x42308B04UL))) +#define bM4_TMR62_PCONR_STPCA (*((volatile unsigned int*)(0x42308B08UL))) +#define bM4_TMR62_PCONR_STASTPSA (*((volatile unsigned int*)(0x42308B0CUL))) +#define bM4_TMR62_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42308B10UL))) +#define bM4_TMR62_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42308B14UL))) +#define bM4_TMR62_PCONR_PERCA0 (*((volatile unsigned int*)(0x42308B18UL))) +#define bM4_TMR62_PCONR_PERCA1 (*((volatile unsigned int*)(0x42308B1CUL))) +#define bM4_TMR62_PCONR_OUTENA (*((volatile unsigned int*)(0x42308B20UL))) +#define bM4_TMR62_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42308B2CUL))) +#define bM4_TMR62_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42308B30UL))) +#define bM4_TMR62_PCONR_CAPMDB (*((volatile unsigned int*)(0x42308B40UL))) +#define bM4_TMR62_PCONR_STACB (*((volatile unsigned int*)(0x42308B44UL))) +#define bM4_TMR62_PCONR_STPCB (*((volatile unsigned int*)(0x42308B48UL))) +#define bM4_TMR62_PCONR_STASTPSB (*((volatile unsigned int*)(0x42308B4CUL))) +#define bM4_TMR62_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42308B50UL))) +#define bM4_TMR62_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42308B54UL))) +#define bM4_TMR62_PCONR_PERCB0 (*((volatile unsigned int*)(0x42308B58UL))) +#define bM4_TMR62_PCONR_PERCB1 (*((volatile unsigned int*)(0x42308B5CUL))) +#define bM4_TMR62_PCONR_OUTENB (*((volatile unsigned int*)(0x42308B60UL))) +#define bM4_TMR62_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42308B6CUL))) +#define bM4_TMR62_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42308B70UL))) +#define bM4_TMR62_BCONR_BENA (*((volatile unsigned int*)(0x42308B80UL))) +#define bM4_TMR62_BCONR_BSEA (*((volatile unsigned int*)(0x42308B84UL))) +#define bM4_TMR62_BCONR_BENB (*((volatile unsigned int*)(0x42308B88UL))) +#define bM4_TMR62_BCONR_BSEB (*((volatile unsigned int*)(0x42308B8CUL))) +#define bM4_TMR62_BCONR_BENP (*((volatile unsigned int*)(0x42308BA0UL))) +#define bM4_TMR62_BCONR_BSEP (*((volatile unsigned int*)(0x42308BA4UL))) +#define bM4_TMR62_BCONR_BENSPA (*((volatile unsigned int*)(0x42308BC0UL))) +#define bM4_TMR62_BCONR_BSESPA (*((volatile unsigned int*)(0x42308BC4UL))) +#define bM4_TMR62_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42308BD0UL))) +#define bM4_TMR62_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42308BD4UL))) +#define bM4_TMR62_BCONR_BENSPB (*((volatile unsigned int*)(0x42308BE0UL))) +#define bM4_TMR62_BCONR_BSESPB (*((volatile unsigned int*)(0x42308BE4UL))) +#define bM4_TMR62_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42308BF0UL))) +#define bM4_TMR62_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42308BF4UL))) +#define bM4_TMR62_DCONR_DTCEN (*((volatile unsigned int*)(0x42308C00UL))) +#define bM4_TMR62_DCONR_DTBENU (*((volatile unsigned int*)(0x42308C10UL))) +#define bM4_TMR62_DCONR_DTBEND (*((volatile unsigned int*)(0x42308C14UL))) +#define bM4_TMR62_DCONR_SEPA (*((volatile unsigned int*)(0x42308C20UL))) +#define bM4_TMR62_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42308D00UL))) +#define bM4_TMR62_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42308D04UL))) +#define bM4_TMR62_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42308D08UL))) +#define bM4_TMR62_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42308D10UL))) +#define bM4_TMR62_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42308D14UL))) +#define bM4_TMR62_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42308D18UL))) +#define bM4_TMR62_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42308D40UL))) +#define bM4_TMR62_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42308D44UL))) +#define bM4_TMR62_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42308D48UL))) +#define bM4_TMR62_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42308D50UL))) +#define bM4_TMR62_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42308D54UL))) +#define bM4_TMR62_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42308D58UL))) +#define bM4_TMR62_VPERR_SPPERIA (*((volatile unsigned int*)(0x42308DA0UL))) +#define bM4_TMR62_VPERR_SPPERIB (*((volatile unsigned int*)(0x42308DA4UL))) +#define bM4_TMR62_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42308DC0UL))) +#define bM4_TMR62_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42308DC4UL))) +#define bM4_TMR62_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42308DC8UL))) +#define bM4_TMR62_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42308DCCUL))) +#define bM4_TMR62_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42308DD0UL))) +#define bM4_TMR62_STFLR_CMAF (*((volatile unsigned int*)(0x42308E00UL))) +#define bM4_TMR62_STFLR_CMBF (*((volatile unsigned int*)(0x42308E04UL))) +#define bM4_TMR62_STFLR_CMCF (*((volatile unsigned int*)(0x42308E08UL))) +#define bM4_TMR62_STFLR_CMDF (*((volatile unsigned int*)(0x42308E0CUL))) +#define bM4_TMR62_STFLR_CMEF (*((volatile unsigned int*)(0x42308E10UL))) +#define bM4_TMR62_STFLR_CMFF (*((volatile unsigned int*)(0x42308E14UL))) +#define bM4_TMR62_STFLR_OVFF (*((volatile unsigned int*)(0x42308E18UL))) +#define bM4_TMR62_STFLR_UDFF (*((volatile unsigned int*)(0x42308E1CUL))) +#define bM4_TMR62_STFLR_DTEF (*((volatile unsigned int*)(0x42308E20UL))) +#define bM4_TMR62_STFLR_CMSAUF (*((volatile unsigned int*)(0x42308E24UL))) +#define bM4_TMR62_STFLR_CMSADF (*((volatile unsigned int*)(0x42308E28UL))) +#define bM4_TMR62_STFLR_CMSBUF (*((volatile unsigned int*)(0x42308E2CUL))) +#define bM4_TMR62_STFLR_CMSBDF (*((volatile unsigned int*)(0x42308E30UL))) +#define bM4_TMR62_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42308E54UL))) +#define bM4_TMR62_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42308E58UL))) +#define bM4_TMR62_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42308E5CUL))) +#define bM4_TMR62_STFLR_DIRF (*((volatile unsigned int*)(0x42308E7CUL))) +#define bM4_TMR62_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42308E80UL))) +#define bM4_TMR62_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42308E84UL))) +#define bM4_TMR62_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42308E90UL))) +#define bM4_TMR62_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42308E94UL))) +#define bM4_TMR62_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42308E98UL))) +#define bM4_TMR62_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42308E9CUL))) +#define bM4_TMR62_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42308EA0UL))) +#define bM4_TMR62_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42308EA4UL))) +#define bM4_TMR62_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42308EA8UL))) +#define bM4_TMR62_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42308EACUL))) +#define bM4_TMR62_HSTAR_STARTS (*((volatile unsigned int*)(0x42308EFCUL))) +#define bM4_TMR62_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42308F00UL))) +#define bM4_TMR62_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42308F04UL))) +#define bM4_TMR62_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42308F10UL))) +#define bM4_TMR62_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42308F14UL))) +#define bM4_TMR62_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42308F18UL))) +#define bM4_TMR62_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42308F1CUL))) +#define bM4_TMR62_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42308F20UL))) +#define bM4_TMR62_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42308F24UL))) +#define bM4_TMR62_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42308F28UL))) +#define bM4_TMR62_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42308F2CUL))) +#define bM4_TMR62_HSTPR_STOPS (*((volatile unsigned int*)(0x42308F7CUL))) +#define bM4_TMR62_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42308F80UL))) +#define bM4_TMR62_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42308F84UL))) +#define bM4_TMR62_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42308F90UL))) +#define bM4_TMR62_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42308F94UL))) +#define bM4_TMR62_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42308F98UL))) +#define bM4_TMR62_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42308F9CUL))) +#define bM4_TMR62_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42308FA0UL))) +#define bM4_TMR62_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42308FA4UL))) +#define bM4_TMR62_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42308FA8UL))) +#define bM4_TMR62_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42308FACUL))) +#define bM4_TMR62_HCLRR_CLEARS (*((volatile unsigned int*)(0x42308FFCUL))) +#define bM4_TMR62_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42309000UL))) +#define bM4_TMR62_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42309004UL))) +#define bM4_TMR62_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42309010UL))) +#define bM4_TMR62_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42309014UL))) +#define bM4_TMR62_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42309018UL))) +#define bM4_TMR62_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4230901CUL))) +#define bM4_TMR62_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42309020UL))) +#define bM4_TMR62_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42309024UL))) +#define bM4_TMR62_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42309028UL))) +#define bM4_TMR62_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4230902CUL))) +#define bM4_TMR62_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42309080UL))) +#define bM4_TMR62_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42309084UL))) +#define bM4_TMR62_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42309090UL))) +#define bM4_TMR62_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42309094UL))) +#define bM4_TMR62_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42309098UL))) +#define bM4_TMR62_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4230909CUL))) +#define bM4_TMR62_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423090A0UL))) +#define bM4_TMR62_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423090A4UL))) +#define bM4_TMR62_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423090A8UL))) +#define bM4_TMR62_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423090ACUL))) +#define bM4_TMR62_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42309100UL))) +#define bM4_TMR62_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42309104UL))) +#define bM4_TMR62_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42309108UL))) +#define bM4_TMR62_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4230910CUL))) +#define bM4_TMR62_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42309110UL))) +#define bM4_TMR62_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42309114UL))) +#define bM4_TMR62_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42309118UL))) +#define bM4_TMR62_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4230911CUL))) +#define bM4_TMR62_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42309120UL))) +#define bM4_TMR62_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42309124UL))) +#define bM4_TMR62_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42309128UL))) +#define bM4_TMR62_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4230912CUL))) +#define bM4_TMR62_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42309140UL))) +#define bM4_TMR62_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42309144UL))) +#define bM4_TMR62_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42309180UL))) +#define bM4_TMR62_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42309184UL))) +#define bM4_TMR62_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42309188UL))) +#define bM4_TMR62_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4230918CUL))) +#define bM4_TMR62_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42309190UL))) +#define bM4_TMR62_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42309194UL))) +#define bM4_TMR62_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42309198UL))) +#define bM4_TMR62_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4230919CUL))) +#define bM4_TMR62_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423091A0UL))) +#define bM4_TMR62_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423091A4UL))) +#define bM4_TMR62_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423091A8UL))) +#define bM4_TMR62_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423091ACUL))) +#define bM4_TMR62_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423091C0UL))) +#define bM4_TMR62_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423091C4UL))) +#define bM4_TMR63_CNTER_CNT0 (*((volatile unsigned int*)(0x42310000UL))) +#define bM4_TMR63_CNTER_CNT1 (*((volatile unsigned int*)(0x42310004UL))) +#define bM4_TMR63_CNTER_CNT2 (*((volatile unsigned int*)(0x42310008UL))) +#define bM4_TMR63_CNTER_CNT3 (*((volatile unsigned int*)(0x4231000CUL))) +#define bM4_TMR63_CNTER_CNT4 (*((volatile unsigned int*)(0x42310010UL))) +#define bM4_TMR63_CNTER_CNT5 (*((volatile unsigned int*)(0x42310014UL))) +#define bM4_TMR63_CNTER_CNT6 (*((volatile unsigned int*)(0x42310018UL))) +#define bM4_TMR63_CNTER_CNT7 (*((volatile unsigned int*)(0x4231001CUL))) +#define bM4_TMR63_CNTER_CNT8 (*((volatile unsigned int*)(0x42310020UL))) +#define bM4_TMR63_CNTER_CNT9 (*((volatile unsigned int*)(0x42310024UL))) +#define bM4_TMR63_CNTER_CNT10 (*((volatile unsigned int*)(0x42310028UL))) +#define bM4_TMR63_CNTER_CNT11 (*((volatile unsigned int*)(0x4231002CUL))) +#define bM4_TMR63_CNTER_CNT12 (*((volatile unsigned int*)(0x42310030UL))) +#define bM4_TMR63_CNTER_CNT13 (*((volatile unsigned int*)(0x42310034UL))) +#define bM4_TMR63_CNTER_CNT14 (*((volatile unsigned int*)(0x42310038UL))) +#define bM4_TMR63_CNTER_CNT15 (*((volatile unsigned int*)(0x4231003CUL))) +#define bM4_TMR63_PERAR_PERA0 (*((volatile unsigned int*)(0x42310080UL))) +#define bM4_TMR63_PERAR_PERA1 (*((volatile unsigned int*)(0x42310084UL))) +#define bM4_TMR63_PERAR_PERA2 (*((volatile unsigned int*)(0x42310088UL))) +#define bM4_TMR63_PERAR_PERA3 (*((volatile unsigned int*)(0x4231008CUL))) +#define bM4_TMR63_PERAR_PERA4 (*((volatile unsigned int*)(0x42310090UL))) +#define bM4_TMR63_PERAR_PERA5 (*((volatile unsigned int*)(0x42310094UL))) +#define bM4_TMR63_PERAR_PERA6 (*((volatile unsigned int*)(0x42310098UL))) +#define bM4_TMR63_PERAR_PERA7 (*((volatile unsigned int*)(0x4231009CUL))) +#define bM4_TMR63_PERAR_PERA8 (*((volatile unsigned int*)(0x423100A0UL))) +#define bM4_TMR63_PERAR_PERA9 (*((volatile unsigned int*)(0x423100A4UL))) +#define bM4_TMR63_PERAR_PERA10 (*((volatile unsigned int*)(0x423100A8UL))) +#define bM4_TMR63_PERAR_PERA11 (*((volatile unsigned int*)(0x423100ACUL))) +#define bM4_TMR63_PERAR_PERA12 (*((volatile unsigned int*)(0x423100B0UL))) +#define bM4_TMR63_PERAR_PERA13 (*((volatile unsigned int*)(0x423100B4UL))) +#define bM4_TMR63_PERAR_PERA14 (*((volatile unsigned int*)(0x423100B8UL))) +#define bM4_TMR63_PERAR_PERA15 (*((volatile unsigned int*)(0x423100BCUL))) +#define bM4_TMR63_PERBR_PERB0 (*((volatile unsigned int*)(0x42310100UL))) +#define bM4_TMR63_PERBR_PERB1 (*((volatile unsigned int*)(0x42310104UL))) +#define bM4_TMR63_PERBR_PERB2 (*((volatile unsigned int*)(0x42310108UL))) +#define bM4_TMR63_PERBR_PERB3 (*((volatile unsigned int*)(0x4231010CUL))) +#define bM4_TMR63_PERBR_PERB4 (*((volatile unsigned int*)(0x42310110UL))) +#define bM4_TMR63_PERBR_PERB5 (*((volatile unsigned int*)(0x42310114UL))) +#define bM4_TMR63_PERBR_PERB6 (*((volatile unsigned int*)(0x42310118UL))) +#define bM4_TMR63_PERBR_PERB7 (*((volatile unsigned int*)(0x4231011CUL))) +#define bM4_TMR63_PERBR_PERB8 (*((volatile unsigned int*)(0x42310120UL))) +#define bM4_TMR63_PERBR_PERB9 (*((volatile unsigned int*)(0x42310124UL))) +#define bM4_TMR63_PERBR_PERB10 (*((volatile unsigned int*)(0x42310128UL))) +#define bM4_TMR63_PERBR_PERB11 (*((volatile unsigned int*)(0x4231012CUL))) +#define bM4_TMR63_PERBR_PERB12 (*((volatile unsigned int*)(0x42310130UL))) +#define bM4_TMR63_PERBR_PERB13 (*((volatile unsigned int*)(0x42310134UL))) +#define bM4_TMR63_PERBR_PERB14 (*((volatile unsigned int*)(0x42310138UL))) +#define bM4_TMR63_PERBR_PERB15 (*((volatile unsigned int*)(0x4231013CUL))) +#define bM4_TMR63_PERCR_PERC0 (*((volatile unsigned int*)(0x42310180UL))) +#define bM4_TMR63_PERCR_PERC1 (*((volatile unsigned int*)(0x42310184UL))) +#define bM4_TMR63_PERCR_PERC2 (*((volatile unsigned int*)(0x42310188UL))) +#define bM4_TMR63_PERCR_PERC3 (*((volatile unsigned int*)(0x4231018CUL))) +#define bM4_TMR63_PERCR_PERC4 (*((volatile unsigned int*)(0x42310190UL))) +#define bM4_TMR63_PERCR_PERC5 (*((volatile unsigned int*)(0x42310194UL))) +#define bM4_TMR63_PERCR_PERC6 (*((volatile unsigned int*)(0x42310198UL))) +#define bM4_TMR63_PERCR_PERC7 (*((volatile unsigned int*)(0x4231019CUL))) +#define bM4_TMR63_PERCR_PERC8 (*((volatile unsigned int*)(0x423101A0UL))) +#define bM4_TMR63_PERCR_PERC9 (*((volatile unsigned int*)(0x423101A4UL))) +#define bM4_TMR63_PERCR_PERC10 (*((volatile unsigned int*)(0x423101A8UL))) +#define bM4_TMR63_PERCR_PERC11 (*((volatile unsigned int*)(0x423101ACUL))) +#define bM4_TMR63_PERCR_PERC12 (*((volatile unsigned int*)(0x423101B0UL))) +#define bM4_TMR63_PERCR_PERC13 (*((volatile unsigned int*)(0x423101B4UL))) +#define bM4_TMR63_PERCR_PERC14 (*((volatile unsigned int*)(0x423101B8UL))) +#define bM4_TMR63_PERCR_PERC15 (*((volatile unsigned int*)(0x423101BCUL))) +#define bM4_TMR63_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42310200UL))) +#define bM4_TMR63_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42310204UL))) +#define bM4_TMR63_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42310208UL))) +#define bM4_TMR63_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4231020CUL))) +#define bM4_TMR63_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42310210UL))) +#define bM4_TMR63_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42310214UL))) +#define bM4_TMR63_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42310218UL))) +#define bM4_TMR63_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4231021CUL))) +#define bM4_TMR63_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42310220UL))) +#define bM4_TMR63_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42310224UL))) +#define bM4_TMR63_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42310228UL))) +#define bM4_TMR63_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4231022CUL))) +#define bM4_TMR63_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42310230UL))) +#define bM4_TMR63_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42310234UL))) +#define bM4_TMR63_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42310238UL))) +#define bM4_TMR63_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4231023CUL))) +#define bM4_TMR63_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42310280UL))) +#define bM4_TMR63_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42310284UL))) +#define bM4_TMR63_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42310288UL))) +#define bM4_TMR63_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4231028CUL))) +#define bM4_TMR63_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42310290UL))) +#define bM4_TMR63_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42310294UL))) +#define bM4_TMR63_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42310298UL))) +#define bM4_TMR63_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4231029CUL))) +#define bM4_TMR63_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423102A0UL))) +#define bM4_TMR63_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423102A4UL))) +#define bM4_TMR63_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423102A8UL))) +#define bM4_TMR63_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423102ACUL))) +#define bM4_TMR63_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423102B0UL))) +#define bM4_TMR63_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423102B4UL))) +#define bM4_TMR63_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423102B8UL))) +#define bM4_TMR63_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423102BCUL))) +#define bM4_TMR63_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42310300UL))) +#define bM4_TMR63_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42310304UL))) +#define bM4_TMR63_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42310308UL))) +#define bM4_TMR63_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4231030CUL))) +#define bM4_TMR63_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42310310UL))) +#define bM4_TMR63_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42310314UL))) +#define bM4_TMR63_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42310318UL))) +#define bM4_TMR63_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4231031CUL))) +#define bM4_TMR63_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42310320UL))) +#define bM4_TMR63_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42310324UL))) +#define bM4_TMR63_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42310328UL))) +#define bM4_TMR63_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4231032CUL))) +#define bM4_TMR63_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42310330UL))) +#define bM4_TMR63_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42310334UL))) +#define bM4_TMR63_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42310338UL))) +#define bM4_TMR63_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4231033CUL))) +#define bM4_TMR63_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42310380UL))) +#define bM4_TMR63_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42310384UL))) +#define bM4_TMR63_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42310388UL))) +#define bM4_TMR63_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4231038CUL))) +#define bM4_TMR63_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42310390UL))) +#define bM4_TMR63_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42310394UL))) +#define bM4_TMR63_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42310398UL))) +#define bM4_TMR63_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4231039CUL))) +#define bM4_TMR63_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423103A0UL))) +#define bM4_TMR63_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423103A4UL))) +#define bM4_TMR63_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423103A8UL))) +#define bM4_TMR63_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423103ACUL))) +#define bM4_TMR63_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423103B0UL))) +#define bM4_TMR63_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423103B4UL))) +#define bM4_TMR63_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423103B8UL))) +#define bM4_TMR63_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423103BCUL))) +#define bM4_TMR63_GCMER_GCME0 (*((volatile unsigned int*)(0x42310400UL))) +#define bM4_TMR63_GCMER_GCME1 (*((volatile unsigned int*)(0x42310404UL))) +#define bM4_TMR63_GCMER_GCME2 (*((volatile unsigned int*)(0x42310408UL))) +#define bM4_TMR63_GCMER_GCME3 (*((volatile unsigned int*)(0x4231040CUL))) +#define bM4_TMR63_GCMER_GCME4 (*((volatile unsigned int*)(0x42310410UL))) +#define bM4_TMR63_GCMER_GCME5 (*((volatile unsigned int*)(0x42310414UL))) +#define bM4_TMR63_GCMER_GCME6 (*((volatile unsigned int*)(0x42310418UL))) +#define bM4_TMR63_GCMER_GCME7 (*((volatile unsigned int*)(0x4231041CUL))) +#define bM4_TMR63_GCMER_GCME8 (*((volatile unsigned int*)(0x42310420UL))) +#define bM4_TMR63_GCMER_GCME9 (*((volatile unsigned int*)(0x42310424UL))) +#define bM4_TMR63_GCMER_GCME10 (*((volatile unsigned int*)(0x42310428UL))) +#define bM4_TMR63_GCMER_GCME11 (*((volatile unsigned int*)(0x4231042CUL))) +#define bM4_TMR63_GCMER_GCME12 (*((volatile unsigned int*)(0x42310430UL))) +#define bM4_TMR63_GCMER_GCME13 (*((volatile unsigned int*)(0x42310434UL))) +#define bM4_TMR63_GCMER_GCME14 (*((volatile unsigned int*)(0x42310438UL))) +#define bM4_TMR63_GCMER_GCME15 (*((volatile unsigned int*)(0x4231043CUL))) +#define bM4_TMR63_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42310480UL))) +#define bM4_TMR63_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42310484UL))) +#define bM4_TMR63_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42310488UL))) +#define bM4_TMR63_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4231048CUL))) +#define bM4_TMR63_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42310490UL))) +#define bM4_TMR63_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42310494UL))) +#define bM4_TMR63_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42310498UL))) +#define bM4_TMR63_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4231049CUL))) +#define bM4_TMR63_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423104A0UL))) +#define bM4_TMR63_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423104A4UL))) +#define bM4_TMR63_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423104A8UL))) +#define bM4_TMR63_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423104ACUL))) +#define bM4_TMR63_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423104B0UL))) +#define bM4_TMR63_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423104B4UL))) +#define bM4_TMR63_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423104B8UL))) +#define bM4_TMR63_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423104BCUL))) +#define bM4_TMR63_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42310500UL))) +#define bM4_TMR63_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42310504UL))) +#define bM4_TMR63_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42310508UL))) +#define bM4_TMR63_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4231050CUL))) +#define bM4_TMR63_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42310510UL))) +#define bM4_TMR63_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42310514UL))) +#define bM4_TMR63_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42310518UL))) +#define bM4_TMR63_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4231051CUL))) +#define bM4_TMR63_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42310520UL))) +#define bM4_TMR63_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42310524UL))) +#define bM4_TMR63_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42310528UL))) +#define bM4_TMR63_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4231052CUL))) +#define bM4_TMR63_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42310530UL))) +#define bM4_TMR63_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42310534UL))) +#define bM4_TMR63_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42310538UL))) +#define bM4_TMR63_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4231053CUL))) +#define bM4_TMR63_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42310580UL))) +#define bM4_TMR63_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42310584UL))) +#define bM4_TMR63_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42310588UL))) +#define bM4_TMR63_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4231058CUL))) +#define bM4_TMR63_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42310590UL))) +#define bM4_TMR63_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42310594UL))) +#define bM4_TMR63_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42310598UL))) +#define bM4_TMR63_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4231059CUL))) +#define bM4_TMR63_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423105A0UL))) +#define bM4_TMR63_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423105A4UL))) +#define bM4_TMR63_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423105A8UL))) +#define bM4_TMR63_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423105ACUL))) +#define bM4_TMR63_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423105B0UL))) +#define bM4_TMR63_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423105B4UL))) +#define bM4_TMR63_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423105B8UL))) +#define bM4_TMR63_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423105BCUL))) +#define bM4_TMR63_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42310600UL))) +#define bM4_TMR63_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42310604UL))) +#define bM4_TMR63_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42310608UL))) +#define bM4_TMR63_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4231060CUL))) +#define bM4_TMR63_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42310610UL))) +#define bM4_TMR63_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42310614UL))) +#define bM4_TMR63_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42310618UL))) +#define bM4_TMR63_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4231061CUL))) +#define bM4_TMR63_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42310620UL))) +#define bM4_TMR63_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42310624UL))) +#define bM4_TMR63_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42310628UL))) +#define bM4_TMR63_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4231062CUL))) +#define bM4_TMR63_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42310630UL))) +#define bM4_TMR63_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42310634UL))) +#define bM4_TMR63_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42310638UL))) +#define bM4_TMR63_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4231063CUL))) +#define bM4_TMR63_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42310680UL))) +#define bM4_TMR63_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42310684UL))) +#define bM4_TMR63_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42310688UL))) +#define bM4_TMR63_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4231068CUL))) +#define bM4_TMR63_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42310690UL))) +#define bM4_TMR63_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42310694UL))) +#define bM4_TMR63_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42310698UL))) +#define bM4_TMR63_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4231069CUL))) +#define bM4_TMR63_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423106A0UL))) +#define bM4_TMR63_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423106A4UL))) +#define bM4_TMR63_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423106A8UL))) +#define bM4_TMR63_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423106ACUL))) +#define bM4_TMR63_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423106B0UL))) +#define bM4_TMR63_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423106B4UL))) +#define bM4_TMR63_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423106B8UL))) +#define bM4_TMR63_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423106BCUL))) +#define bM4_TMR63_SCMER_SCME0 (*((volatile unsigned int*)(0x42310700UL))) +#define bM4_TMR63_SCMER_SCME1 (*((volatile unsigned int*)(0x42310704UL))) +#define bM4_TMR63_SCMER_SCME2 (*((volatile unsigned int*)(0x42310708UL))) +#define bM4_TMR63_SCMER_SCME3 (*((volatile unsigned int*)(0x4231070CUL))) +#define bM4_TMR63_SCMER_SCME4 (*((volatile unsigned int*)(0x42310710UL))) +#define bM4_TMR63_SCMER_SCME5 (*((volatile unsigned int*)(0x42310714UL))) +#define bM4_TMR63_SCMER_SCME6 (*((volatile unsigned int*)(0x42310718UL))) +#define bM4_TMR63_SCMER_SCME7 (*((volatile unsigned int*)(0x4231071CUL))) +#define bM4_TMR63_SCMER_SCME8 (*((volatile unsigned int*)(0x42310720UL))) +#define bM4_TMR63_SCMER_SCME9 (*((volatile unsigned int*)(0x42310724UL))) +#define bM4_TMR63_SCMER_SCME10 (*((volatile unsigned int*)(0x42310728UL))) +#define bM4_TMR63_SCMER_SCME11 (*((volatile unsigned int*)(0x4231072CUL))) +#define bM4_TMR63_SCMER_SCME12 (*((volatile unsigned int*)(0x42310730UL))) +#define bM4_TMR63_SCMER_SCME13 (*((volatile unsigned int*)(0x42310734UL))) +#define bM4_TMR63_SCMER_SCME14 (*((volatile unsigned int*)(0x42310738UL))) +#define bM4_TMR63_SCMER_SCME15 (*((volatile unsigned int*)(0x4231073CUL))) +#define bM4_TMR63_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42310780UL))) +#define bM4_TMR63_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42310784UL))) +#define bM4_TMR63_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42310788UL))) +#define bM4_TMR63_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4231078CUL))) +#define bM4_TMR63_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42310790UL))) +#define bM4_TMR63_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42310794UL))) +#define bM4_TMR63_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42310798UL))) +#define bM4_TMR63_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4231079CUL))) +#define bM4_TMR63_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423107A0UL))) +#define bM4_TMR63_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423107A4UL))) +#define bM4_TMR63_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423107A8UL))) +#define bM4_TMR63_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423107ACUL))) +#define bM4_TMR63_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423107B0UL))) +#define bM4_TMR63_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423107B4UL))) +#define bM4_TMR63_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423107B8UL))) +#define bM4_TMR63_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423107BCUL))) +#define bM4_TMR63_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42310800UL))) +#define bM4_TMR63_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42310804UL))) +#define bM4_TMR63_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42310808UL))) +#define bM4_TMR63_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4231080CUL))) +#define bM4_TMR63_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42310810UL))) +#define bM4_TMR63_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42310814UL))) +#define bM4_TMR63_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42310818UL))) +#define bM4_TMR63_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4231081CUL))) +#define bM4_TMR63_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42310820UL))) +#define bM4_TMR63_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42310824UL))) +#define bM4_TMR63_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42310828UL))) +#define bM4_TMR63_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4231082CUL))) +#define bM4_TMR63_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42310830UL))) +#define bM4_TMR63_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42310834UL))) +#define bM4_TMR63_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42310838UL))) +#define bM4_TMR63_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4231083CUL))) +#define bM4_TMR63_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42310880UL))) +#define bM4_TMR63_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42310884UL))) +#define bM4_TMR63_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42310888UL))) +#define bM4_TMR63_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4231088CUL))) +#define bM4_TMR63_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42310890UL))) +#define bM4_TMR63_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42310894UL))) +#define bM4_TMR63_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42310898UL))) +#define bM4_TMR63_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4231089CUL))) +#define bM4_TMR63_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423108A0UL))) +#define bM4_TMR63_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423108A4UL))) +#define bM4_TMR63_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423108A8UL))) +#define bM4_TMR63_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423108ACUL))) +#define bM4_TMR63_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423108B0UL))) +#define bM4_TMR63_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423108B4UL))) +#define bM4_TMR63_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423108B8UL))) +#define bM4_TMR63_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423108BCUL))) +#define bM4_TMR63_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42310900UL))) +#define bM4_TMR63_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42310904UL))) +#define bM4_TMR63_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42310908UL))) +#define bM4_TMR63_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4231090CUL))) +#define bM4_TMR63_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42310910UL))) +#define bM4_TMR63_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42310914UL))) +#define bM4_TMR63_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42310918UL))) +#define bM4_TMR63_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4231091CUL))) +#define bM4_TMR63_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42310920UL))) +#define bM4_TMR63_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42310924UL))) +#define bM4_TMR63_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42310928UL))) +#define bM4_TMR63_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4231092CUL))) +#define bM4_TMR63_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42310930UL))) +#define bM4_TMR63_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42310934UL))) +#define bM4_TMR63_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42310938UL))) +#define bM4_TMR63_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4231093CUL))) +#define bM4_TMR63_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42310980UL))) +#define bM4_TMR63_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42310984UL))) +#define bM4_TMR63_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42310988UL))) +#define bM4_TMR63_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4231098CUL))) +#define bM4_TMR63_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42310990UL))) +#define bM4_TMR63_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42310994UL))) +#define bM4_TMR63_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42310998UL))) +#define bM4_TMR63_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4231099CUL))) +#define bM4_TMR63_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423109A0UL))) +#define bM4_TMR63_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423109A4UL))) +#define bM4_TMR63_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423109A8UL))) +#define bM4_TMR63_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423109ACUL))) +#define bM4_TMR63_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423109B0UL))) +#define bM4_TMR63_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423109B4UL))) +#define bM4_TMR63_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423109B8UL))) +#define bM4_TMR63_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423109BCUL))) +#define bM4_TMR63_GCONR_START (*((volatile unsigned int*)(0x42310A00UL))) +#define bM4_TMR63_GCONR_MODE0 (*((volatile unsigned int*)(0x42310A04UL))) +#define bM4_TMR63_GCONR_MODE1 (*((volatile unsigned int*)(0x42310A08UL))) +#define bM4_TMR63_GCONR_MODE2 (*((volatile unsigned int*)(0x42310A0CUL))) +#define bM4_TMR63_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42310A10UL))) +#define bM4_TMR63_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42310A14UL))) +#define bM4_TMR63_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42310A18UL))) +#define bM4_TMR63_GCONR_DIR (*((volatile unsigned int*)(0x42310A20UL))) +#define bM4_TMR63_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42310A40UL))) +#define bM4_TMR63_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42310A44UL))) +#define bM4_TMR63_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42310A48UL))) +#define bM4_TMR63_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42310A4CUL))) +#define bM4_TMR63_ICONR_INTENA (*((volatile unsigned int*)(0x42310A80UL))) +#define bM4_TMR63_ICONR_INTENB (*((volatile unsigned int*)(0x42310A84UL))) +#define bM4_TMR63_ICONR_INTENC (*((volatile unsigned int*)(0x42310A88UL))) +#define bM4_TMR63_ICONR_INTEND (*((volatile unsigned int*)(0x42310A8CUL))) +#define bM4_TMR63_ICONR_INTENE (*((volatile unsigned int*)(0x42310A90UL))) +#define bM4_TMR63_ICONR_INTENF (*((volatile unsigned int*)(0x42310A94UL))) +#define bM4_TMR63_ICONR_INTENOVF (*((volatile unsigned int*)(0x42310A98UL))) +#define bM4_TMR63_ICONR_INTENUDF (*((volatile unsigned int*)(0x42310A9CUL))) +#define bM4_TMR63_ICONR_INTENDTE (*((volatile unsigned int*)(0x42310AA0UL))) +#define bM4_TMR63_ICONR_INTENSAU (*((volatile unsigned int*)(0x42310AC0UL))) +#define bM4_TMR63_ICONR_INTENSAD (*((volatile unsigned int*)(0x42310AC4UL))) +#define bM4_TMR63_ICONR_INTENSBU (*((volatile unsigned int*)(0x42310AC8UL))) +#define bM4_TMR63_ICONR_INTENSBD (*((volatile unsigned int*)(0x42310ACCUL))) +#define bM4_TMR63_PCONR_CAPMDA (*((volatile unsigned int*)(0x42310B00UL))) +#define bM4_TMR63_PCONR_STACA (*((volatile unsigned int*)(0x42310B04UL))) +#define bM4_TMR63_PCONR_STPCA (*((volatile unsigned int*)(0x42310B08UL))) +#define bM4_TMR63_PCONR_STASTPSA (*((volatile unsigned int*)(0x42310B0CUL))) +#define bM4_TMR63_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42310B10UL))) +#define bM4_TMR63_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42310B14UL))) +#define bM4_TMR63_PCONR_PERCA0 (*((volatile unsigned int*)(0x42310B18UL))) +#define bM4_TMR63_PCONR_PERCA1 (*((volatile unsigned int*)(0x42310B1CUL))) +#define bM4_TMR63_PCONR_OUTENA (*((volatile unsigned int*)(0x42310B20UL))) +#define bM4_TMR63_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42310B2CUL))) +#define bM4_TMR63_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42310B30UL))) +#define bM4_TMR63_PCONR_CAPMDB (*((volatile unsigned int*)(0x42310B40UL))) +#define bM4_TMR63_PCONR_STACB (*((volatile unsigned int*)(0x42310B44UL))) +#define bM4_TMR63_PCONR_STPCB (*((volatile unsigned int*)(0x42310B48UL))) +#define bM4_TMR63_PCONR_STASTPSB (*((volatile unsigned int*)(0x42310B4CUL))) +#define bM4_TMR63_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42310B50UL))) +#define bM4_TMR63_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42310B54UL))) +#define bM4_TMR63_PCONR_PERCB0 (*((volatile unsigned int*)(0x42310B58UL))) +#define bM4_TMR63_PCONR_PERCB1 (*((volatile unsigned int*)(0x42310B5CUL))) +#define bM4_TMR63_PCONR_OUTENB (*((volatile unsigned int*)(0x42310B60UL))) +#define bM4_TMR63_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42310B6CUL))) +#define bM4_TMR63_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42310B70UL))) +#define bM4_TMR63_BCONR_BENA (*((volatile unsigned int*)(0x42310B80UL))) +#define bM4_TMR63_BCONR_BSEA (*((volatile unsigned int*)(0x42310B84UL))) +#define bM4_TMR63_BCONR_BENB (*((volatile unsigned int*)(0x42310B88UL))) +#define bM4_TMR63_BCONR_BSEB (*((volatile unsigned int*)(0x42310B8CUL))) +#define bM4_TMR63_BCONR_BENP (*((volatile unsigned int*)(0x42310BA0UL))) +#define bM4_TMR63_BCONR_BSEP (*((volatile unsigned int*)(0x42310BA4UL))) +#define bM4_TMR63_BCONR_BENSPA (*((volatile unsigned int*)(0x42310BC0UL))) +#define bM4_TMR63_BCONR_BSESPA (*((volatile unsigned int*)(0x42310BC4UL))) +#define bM4_TMR63_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42310BD0UL))) +#define bM4_TMR63_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42310BD4UL))) +#define bM4_TMR63_BCONR_BENSPB (*((volatile unsigned int*)(0x42310BE0UL))) +#define bM4_TMR63_BCONR_BSESPB (*((volatile unsigned int*)(0x42310BE4UL))) +#define bM4_TMR63_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42310BF0UL))) +#define bM4_TMR63_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42310BF4UL))) +#define bM4_TMR63_DCONR_DTCEN (*((volatile unsigned int*)(0x42310C00UL))) +#define bM4_TMR63_DCONR_DTBENU (*((volatile unsigned int*)(0x42310C10UL))) +#define bM4_TMR63_DCONR_DTBEND (*((volatile unsigned int*)(0x42310C14UL))) +#define bM4_TMR63_DCONR_SEPA (*((volatile unsigned int*)(0x42310C20UL))) +#define bM4_TMR63_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42310D00UL))) +#define bM4_TMR63_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42310D04UL))) +#define bM4_TMR63_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42310D08UL))) +#define bM4_TMR63_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42310D10UL))) +#define bM4_TMR63_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42310D14UL))) +#define bM4_TMR63_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42310D18UL))) +#define bM4_TMR63_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42310D40UL))) +#define bM4_TMR63_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42310D44UL))) +#define bM4_TMR63_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42310D48UL))) +#define bM4_TMR63_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42310D50UL))) +#define bM4_TMR63_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42310D54UL))) +#define bM4_TMR63_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42310D58UL))) +#define bM4_TMR63_VPERR_SPPERIA (*((volatile unsigned int*)(0x42310DA0UL))) +#define bM4_TMR63_VPERR_SPPERIB (*((volatile unsigned int*)(0x42310DA4UL))) +#define bM4_TMR63_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42310DC0UL))) +#define bM4_TMR63_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42310DC4UL))) +#define bM4_TMR63_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42310DC8UL))) +#define bM4_TMR63_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42310DCCUL))) +#define bM4_TMR63_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42310DD0UL))) +#define bM4_TMR63_STFLR_CMAF (*((volatile unsigned int*)(0x42310E00UL))) +#define bM4_TMR63_STFLR_CMBF (*((volatile unsigned int*)(0x42310E04UL))) +#define bM4_TMR63_STFLR_CMCF (*((volatile unsigned int*)(0x42310E08UL))) +#define bM4_TMR63_STFLR_CMDF (*((volatile unsigned int*)(0x42310E0CUL))) +#define bM4_TMR63_STFLR_CMEF (*((volatile unsigned int*)(0x42310E10UL))) +#define bM4_TMR63_STFLR_CMFF (*((volatile unsigned int*)(0x42310E14UL))) +#define bM4_TMR63_STFLR_OVFF (*((volatile unsigned int*)(0x42310E18UL))) +#define bM4_TMR63_STFLR_UDFF (*((volatile unsigned int*)(0x42310E1CUL))) +#define bM4_TMR63_STFLR_DTEF (*((volatile unsigned int*)(0x42310E20UL))) +#define bM4_TMR63_STFLR_CMSAUF (*((volatile unsigned int*)(0x42310E24UL))) +#define bM4_TMR63_STFLR_CMSADF (*((volatile unsigned int*)(0x42310E28UL))) +#define bM4_TMR63_STFLR_CMSBUF (*((volatile unsigned int*)(0x42310E2CUL))) +#define bM4_TMR63_STFLR_CMSBDF (*((volatile unsigned int*)(0x42310E30UL))) +#define bM4_TMR63_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42310E54UL))) +#define bM4_TMR63_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42310E58UL))) +#define bM4_TMR63_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42310E5CUL))) +#define bM4_TMR63_STFLR_DIRF (*((volatile unsigned int*)(0x42310E7CUL))) +#define bM4_TMR63_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42310E80UL))) +#define bM4_TMR63_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42310E84UL))) +#define bM4_TMR63_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42310E90UL))) +#define bM4_TMR63_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42310E94UL))) +#define bM4_TMR63_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42310E98UL))) +#define bM4_TMR63_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42310E9CUL))) +#define bM4_TMR63_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42310EA0UL))) +#define bM4_TMR63_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42310EA4UL))) +#define bM4_TMR63_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42310EA8UL))) +#define bM4_TMR63_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42310EACUL))) +#define bM4_TMR63_HSTAR_STARTS (*((volatile unsigned int*)(0x42310EFCUL))) +#define bM4_TMR63_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42310F00UL))) +#define bM4_TMR63_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42310F04UL))) +#define bM4_TMR63_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42310F10UL))) +#define bM4_TMR63_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42310F14UL))) +#define bM4_TMR63_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42310F18UL))) +#define bM4_TMR63_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42310F1CUL))) +#define bM4_TMR63_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42310F20UL))) +#define bM4_TMR63_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42310F24UL))) +#define bM4_TMR63_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42310F28UL))) +#define bM4_TMR63_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42310F2CUL))) +#define bM4_TMR63_HSTPR_STOPS (*((volatile unsigned int*)(0x42310F7CUL))) +#define bM4_TMR63_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42310F80UL))) +#define bM4_TMR63_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42310F84UL))) +#define bM4_TMR63_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42310F90UL))) +#define bM4_TMR63_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42310F94UL))) +#define bM4_TMR63_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42310F98UL))) +#define bM4_TMR63_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42310F9CUL))) +#define bM4_TMR63_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42310FA0UL))) +#define bM4_TMR63_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42310FA4UL))) +#define bM4_TMR63_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42310FA8UL))) +#define bM4_TMR63_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42310FACUL))) +#define bM4_TMR63_HCLRR_CLEARS (*((volatile unsigned int*)(0x42310FFCUL))) +#define bM4_TMR63_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42311000UL))) +#define bM4_TMR63_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42311004UL))) +#define bM4_TMR63_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42311010UL))) +#define bM4_TMR63_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42311014UL))) +#define bM4_TMR63_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42311018UL))) +#define bM4_TMR63_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4231101CUL))) +#define bM4_TMR63_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42311020UL))) +#define bM4_TMR63_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42311024UL))) +#define bM4_TMR63_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42311028UL))) +#define bM4_TMR63_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4231102CUL))) +#define bM4_TMR63_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42311080UL))) +#define bM4_TMR63_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42311084UL))) +#define bM4_TMR63_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42311090UL))) +#define bM4_TMR63_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42311094UL))) +#define bM4_TMR63_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42311098UL))) +#define bM4_TMR63_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4231109CUL))) +#define bM4_TMR63_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423110A0UL))) +#define bM4_TMR63_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423110A4UL))) +#define bM4_TMR63_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423110A8UL))) +#define bM4_TMR63_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423110ACUL))) +#define bM4_TMR63_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42311100UL))) +#define bM4_TMR63_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42311104UL))) +#define bM4_TMR63_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42311108UL))) +#define bM4_TMR63_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4231110CUL))) +#define bM4_TMR63_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42311110UL))) +#define bM4_TMR63_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42311114UL))) +#define bM4_TMR63_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42311118UL))) +#define bM4_TMR63_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4231111CUL))) +#define bM4_TMR63_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42311120UL))) +#define bM4_TMR63_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42311124UL))) +#define bM4_TMR63_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42311128UL))) +#define bM4_TMR63_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4231112CUL))) +#define bM4_TMR63_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42311140UL))) +#define bM4_TMR63_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42311144UL))) +#define bM4_TMR63_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42311180UL))) +#define bM4_TMR63_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42311184UL))) +#define bM4_TMR63_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42311188UL))) +#define bM4_TMR63_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4231118CUL))) +#define bM4_TMR63_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42311190UL))) +#define bM4_TMR63_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42311194UL))) +#define bM4_TMR63_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42311198UL))) +#define bM4_TMR63_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4231119CUL))) +#define bM4_TMR63_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423111A0UL))) +#define bM4_TMR63_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423111A4UL))) +#define bM4_TMR63_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423111A8UL))) +#define bM4_TMR63_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423111ACUL))) +#define bM4_TMR63_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423111C0UL))) +#define bM4_TMR63_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423111C4UL))) +#define bM4_TMR6_CR_SSTAR_SSTA1 (*((volatile unsigned int*)(0x42307E80UL))) +#define bM4_TMR6_CR_SSTAR_SSTA2 (*((volatile unsigned int*)(0x42307E84UL))) +#define bM4_TMR6_CR_SSTAR_SSTA3 (*((volatile unsigned int*)(0x42307E88UL))) +#define bM4_TMR6_CR_SSTAR_RESV0 (*((volatile unsigned int*)(0x42307EC0UL))) +#define bM4_TMR6_CR_SSTAR_RESV (*((volatile unsigned int*)(0x42307EE0UL))) +#define bM4_TMR6_CR_SSTPR_SSTP1 (*((volatile unsigned int*)(0x42307F00UL))) +#define bM4_TMR6_CR_SSTPR_SSTP2 (*((volatile unsigned int*)(0x42307F04UL))) +#define bM4_TMR6_CR_SSTPR_SSTP3 (*((volatile unsigned int*)(0x42307F08UL))) +#define bM4_TMR6_CR_SCLRR_SCLE1 (*((volatile unsigned int*)(0x42307F80UL))) +#define bM4_TMR6_CR_SCLRR_SCLE2 (*((volatile unsigned int*)(0x42307F84UL))) +#define bM4_TMR6_CR_SCLRR_SCLE3 (*((volatile unsigned int*)(0x42307F88UL))) +#define bM4_TMRA1_CNTER_CNT0 (*((volatile unsigned int*)(0x422A0000UL))) +#define bM4_TMRA1_CNTER_CNT1 (*((volatile unsigned int*)(0x422A0004UL))) +#define bM4_TMRA1_CNTER_CNT2 (*((volatile unsigned int*)(0x422A0008UL))) +#define bM4_TMRA1_CNTER_CNT3 (*((volatile unsigned int*)(0x422A000CUL))) +#define bM4_TMRA1_CNTER_CNT4 (*((volatile unsigned int*)(0x422A0010UL))) +#define bM4_TMRA1_CNTER_CNT5 (*((volatile unsigned int*)(0x422A0014UL))) +#define bM4_TMRA1_CNTER_CNT6 (*((volatile unsigned int*)(0x422A0018UL))) +#define bM4_TMRA1_CNTER_CNT7 (*((volatile unsigned int*)(0x422A001CUL))) +#define bM4_TMRA1_CNTER_CNT8 (*((volatile unsigned int*)(0x422A0020UL))) +#define bM4_TMRA1_CNTER_CNT9 (*((volatile unsigned int*)(0x422A0024UL))) +#define bM4_TMRA1_CNTER_CNT10 (*((volatile unsigned int*)(0x422A0028UL))) +#define bM4_TMRA1_CNTER_CNT11 (*((volatile unsigned int*)(0x422A002CUL))) +#define bM4_TMRA1_CNTER_CNT12 (*((volatile unsigned int*)(0x422A0030UL))) +#define bM4_TMRA1_CNTER_CNT13 (*((volatile unsigned int*)(0x422A0034UL))) +#define bM4_TMRA1_CNTER_CNT14 (*((volatile unsigned int*)(0x422A0038UL))) +#define bM4_TMRA1_CNTER_CNT15 (*((volatile unsigned int*)(0x422A003CUL))) +#define bM4_TMRA1_PERAR_PER0 (*((volatile unsigned int*)(0x422A0080UL))) +#define bM4_TMRA1_PERAR_PER1 (*((volatile unsigned int*)(0x422A0084UL))) +#define bM4_TMRA1_PERAR_PER2 (*((volatile unsigned int*)(0x422A0088UL))) +#define bM4_TMRA1_PERAR_PER3 (*((volatile unsigned int*)(0x422A008CUL))) +#define bM4_TMRA1_PERAR_PER4 (*((volatile unsigned int*)(0x422A0090UL))) +#define bM4_TMRA1_PERAR_PER5 (*((volatile unsigned int*)(0x422A0094UL))) +#define bM4_TMRA1_PERAR_PER6 (*((volatile unsigned int*)(0x422A0098UL))) +#define bM4_TMRA1_PERAR_PER7 (*((volatile unsigned int*)(0x422A009CUL))) +#define bM4_TMRA1_PERAR_PER8 (*((volatile unsigned int*)(0x422A00A0UL))) +#define bM4_TMRA1_PERAR_PER9 (*((volatile unsigned int*)(0x422A00A4UL))) +#define bM4_TMRA1_PERAR_PER10 (*((volatile unsigned int*)(0x422A00A8UL))) +#define bM4_TMRA1_PERAR_PER11 (*((volatile unsigned int*)(0x422A00ACUL))) +#define bM4_TMRA1_PERAR_PER12 (*((volatile unsigned int*)(0x422A00B0UL))) +#define bM4_TMRA1_PERAR_PER13 (*((volatile unsigned int*)(0x422A00B4UL))) +#define bM4_TMRA1_PERAR_PER14 (*((volatile unsigned int*)(0x422A00B8UL))) +#define bM4_TMRA1_PERAR_PER15 (*((volatile unsigned int*)(0x422A00BCUL))) +#define bM4_TMRA1_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422A0800UL))) +#define bM4_TMRA1_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422A0804UL))) +#define bM4_TMRA1_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422A0808UL))) +#define bM4_TMRA1_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422A080CUL))) +#define bM4_TMRA1_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422A0810UL))) +#define bM4_TMRA1_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422A0814UL))) +#define bM4_TMRA1_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422A0818UL))) +#define bM4_TMRA1_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422A081CUL))) +#define bM4_TMRA1_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422A0820UL))) +#define bM4_TMRA1_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422A0824UL))) +#define bM4_TMRA1_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422A0828UL))) +#define bM4_TMRA1_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422A082CUL))) +#define bM4_TMRA1_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422A0830UL))) +#define bM4_TMRA1_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422A0834UL))) +#define bM4_TMRA1_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422A0838UL))) +#define bM4_TMRA1_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422A083CUL))) +#define bM4_TMRA1_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422A0880UL))) +#define bM4_TMRA1_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422A0884UL))) +#define bM4_TMRA1_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422A0888UL))) +#define bM4_TMRA1_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422A088CUL))) +#define bM4_TMRA1_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422A0890UL))) +#define bM4_TMRA1_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422A0894UL))) +#define bM4_TMRA1_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422A0898UL))) +#define bM4_TMRA1_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422A089CUL))) +#define bM4_TMRA1_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422A08A0UL))) +#define bM4_TMRA1_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422A08A4UL))) +#define bM4_TMRA1_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422A08A8UL))) +#define bM4_TMRA1_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422A08ACUL))) +#define bM4_TMRA1_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422A08B0UL))) +#define bM4_TMRA1_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422A08B4UL))) +#define bM4_TMRA1_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422A08B8UL))) +#define bM4_TMRA1_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422A08BCUL))) +#define bM4_TMRA1_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422A0900UL))) +#define bM4_TMRA1_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422A0904UL))) +#define bM4_TMRA1_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422A0908UL))) +#define bM4_TMRA1_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422A090CUL))) +#define bM4_TMRA1_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422A0910UL))) +#define bM4_TMRA1_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422A0914UL))) +#define bM4_TMRA1_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422A0918UL))) +#define bM4_TMRA1_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422A091CUL))) +#define bM4_TMRA1_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422A0920UL))) +#define bM4_TMRA1_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422A0924UL))) +#define bM4_TMRA1_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422A0928UL))) +#define bM4_TMRA1_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422A092CUL))) +#define bM4_TMRA1_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422A0930UL))) +#define bM4_TMRA1_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422A0934UL))) +#define bM4_TMRA1_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422A0938UL))) +#define bM4_TMRA1_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422A093CUL))) +#define bM4_TMRA1_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422A0980UL))) +#define bM4_TMRA1_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422A0984UL))) +#define bM4_TMRA1_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422A0988UL))) +#define bM4_TMRA1_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422A098CUL))) +#define bM4_TMRA1_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422A0990UL))) +#define bM4_TMRA1_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422A0994UL))) +#define bM4_TMRA1_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422A0998UL))) +#define bM4_TMRA1_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422A099CUL))) +#define bM4_TMRA1_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422A09A0UL))) +#define bM4_TMRA1_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422A09A4UL))) +#define bM4_TMRA1_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422A09A8UL))) +#define bM4_TMRA1_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422A09ACUL))) +#define bM4_TMRA1_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422A09B0UL))) +#define bM4_TMRA1_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422A09B4UL))) +#define bM4_TMRA1_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422A09B8UL))) +#define bM4_TMRA1_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422A09BCUL))) +#define bM4_TMRA1_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422A0A00UL))) +#define bM4_TMRA1_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422A0A04UL))) +#define bM4_TMRA1_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422A0A08UL))) +#define bM4_TMRA1_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422A0A0CUL))) +#define bM4_TMRA1_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422A0A10UL))) +#define bM4_TMRA1_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422A0A14UL))) +#define bM4_TMRA1_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422A0A18UL))) +#define bM4_TMRA1_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422A0A1CUL))) +#define bM4_TMRA1_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422A0A20UL))) +#define bM4_TMRA1_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422A0A24UL))) +#define bM4_TMRA1_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422A0A28UL))) +#define bM4_TMRA1_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422A0A2CUL))) +#define bM4_TMRA1_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422A0A30UL))) +#define bM4_TMRA1_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422A0A34UL))) +#define bM4_TMRA1_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422A0A38UL))) +#define bM4_TMRA1_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422A0A3CUL))) +#define bM4_TMRA1_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422A0A80UL))) +#define bM4_TMRA1_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422A0A84UL))) +#define bM4_TMRA1_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422A0A88UL))) +#define bM4_TMRA1_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422A0A8CUL))) +#define bM4_TMRA1_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422A0A90UL))) +#define bM4_TMRA1_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422A0A94UL))) +#define bM4_TMRA1_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422A0A98UL))) +#define bM4_TMRA1_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422A0A9CUL))) +#define bM4_TMRA1_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422A0AA0UL))) +#define bM4_TMRA1_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422A0AA4UL))) +#define bM4_TMRA1_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422A0AA8UL))) +#define bM4_TMRA1_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422A0AACUL))) +#define bM4_TMRA1_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422A0AB0UL))) +#define bM4_TMRA1_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422A0AB4UL))) +#define bM4_TMRA1_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422A0AB8UL))) +#define bM4_TMRA1_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422A0ABCUL))) +#define bM4_TMRA1_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422A0B00UL))) +#define bM4_TMRA1_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422A0B04UL))) +#define bM4_TMRA1_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422A0B08UL))) +#define bM4_TMRA1_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422A0B0CUL))) +#define bM4_TMRA1_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422A0B10UL))) +#define bM4_TMRA1_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422A0B14UL))) +#define bM4_TMRA1_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422A0B18UL))) +#define bM4_TMRA1_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422A0B1CUL))) +#define bM4_TMRA1_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422A0B20UL))) +#define bM4_TMRA1_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422A0B24UL))) +#define bM4_TMRA1_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422A0B28UL))) +#define bM4_TMRA1_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422A0B2CUL))) +#define bM4_TMRA1_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422A0B30UL))) +#define bM4_TMRA1_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422A0B34UL))) +#define bM4_TMRA1_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422A0B38UL))) +#define bM4_TMRA1_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422A0B3CUL))) +#define bM4_TMRA1_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422A0B80UL))) +#define bM4_TMRA1_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422A0B84UL))) +#define bM4_TMRA1_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422A0B88UL))) +#define bM4_TMRA1_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422A0B8CUL))) +#define bM4_TMRA1_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422A0B90UL))) +#define bM4_TMRA1_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422A0B94UL))) +#define bM4_TMRA1_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422A0B98UL))) +#define bM4_TMRA1_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422A0B9CUL))) +#define bM4_TMRA1_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422A0BA0UL))) +#define bM4_TMRA1_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422A0BA4UL))) +#define bM4_TMRA1_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422A0BA8UL))) +#define bM4_TMRA1_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422A0BACUL))) +#define bM4_TMRA1_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422A0BB0UL))) +#define bM4_TMRA1_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422A0BB4UL))) +#define bM4_TMRA1_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422A0BB8UL))) +#define bM4_TMRA1_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422A0BBCUL))) +#define bM4_TMRA1_BCSTR_START (*((volatile unsigned int*)(0x422A1000UL))) +#define bM4_TMRA1_BCSTR_DIR (*((volatile unsigned int*)(0x422A1004UL))) +#define bM4_TMRA1_BCSTR_MODE (*((volatile unsigned int*)(0x422A1008UL))) +#define bM4_TMRA1_BCSTR_SYNST (*((volatile unsigned int*)(0x422A100CUL))) +#define bM4_TMRA1_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422A1010UL))) +#define bM4_TMRA1_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422A1014UL))) +#define bM4_TMRA1_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422A1018UL))) +#define bM4_TMRA1_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422A101CUL))) +#define bM4_TMRA1_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422A1030UL))) +#define bM4_TMRA1_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422A1034UL))) +#define bM4_TMRA1_BCSTR_OVFF (*((volatile unsigned int*)(0x422A1038UL))) +#define bM4_TMRA1_BCSTR_UDFF (*((volatile unsigned int*)(0x422A103CUL))) +#define bM4_TMRA1_HCONR_HSTA0 (*((volatile unsigned int*)(0x422A1080UL))) +#define bM4_TMRA1_HCONR_HSTA1 (*((volatile unsigned int*)(0x422A1084UL))) +#define bM4_TMRA1_HCONR_HSTA2 (*((volatile unsigned int*)(0x422A1088UL))) +#define bM4_TMRA1_HCONR_HSTP0 (*((volatile unsigned int*)(0x422A1090UL))) +#define bM4_TMRA1_HCONR_HSTP1 (*((volatile unsigned int*)(0x422A1094UL))) +#define bM4_TMRA1_HCONR_HSTP2 (*((volatile unsigned int*)(0x422A1098UL))) +#define bM4_TMRA1_HCONR_HCLE0 (*((volatile unsigned int*)(0x422A10A0UL))) +#define bM4_TMRA1_HCONR_HCLE1 (*((volatile unsigned int*)(0x422A10A4UL))) +#define bM4_TMRA1_HCONR_HCLE2 (*((volatile unsigned int*)(0x422A10A8UL))) +#define bM4_TMRA1_HCONR_HCLE3 (*((volatile unsigned int*)(0x422A10B0UL))) +#define bM4_TMRA1_HCONR_HCLE4 (*((volatile unsigned int*)(0x422A10B4UL))) +#define bM4_TMRA1_HCONR_HCLE5 (*((volatile unsigned int*)(0x422A10B8UL))) +#define bM4_TMRA1_HCONR_HCLE6 (*((volatile unsigned int*)(0x422A10BCUL))) +#define bM4_TMRA1_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422A1100UL))) +#define bM4_TMRA1_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422A1104UL))) +#define bM4_TMRA1_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422A1108UL))) +#define bM4_TMRA1_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422A110CUL))) +#define bM4_TMRA1_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422A1110UL))) +#define bM4_TMRA1_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422A1114UL))) +#define bM4_TMRA1_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422A1118UL))) +#define bM4_TMRA1_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422A111CUL))) +#define bM4_TMRA1_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422A1120UL))) +#define bM4_TMRA1_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422A1124UL))) +#define bM4_TMRA1_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422A1128UL))) +#define bM4_TMRA1_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422A112CUL))) +#define bM4_TMRA1_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422A1130UL))) +#define bM4_TMRA1_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422A1180UL))) +#define bM4_TMRA1_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422A1184UL))) +#define bM4_TMRA1_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422A1188UL))) +#define bM4_TMRA1_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422A118CUL))) +#define bM4_TMRA1_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422A1190UL))) +#define bM4_TMRA1_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422A1194UL))) +#define bM4_TMRA1_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422A1198UL))) +#define bM4_TMRA1_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422A119CUL))) +#define bM4_TMRA1_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422A11A0UL))) +#define bM4_TMRA1_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422A11A4UL))) +#define bM4_TMRA1_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422A11A8UL))) +#define bM4_TMRA1_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422A11ACUL))) +#define bM4_TMRA1_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422A11B0UL))) +#define bM4_TMRA1_ICONR_ITEN1 (*((volatile unsigned int*)(0x422A1200UL))) +#define bM4_TMRA1_ICONR_ITEN2 (*((volatile unsigned int*)(0x422A1204UL))) +#define bM4_TMRA1_ICONR_ITEN3 (*((volatile unsigned int*)(0x422A1208UL))) +#define bM4_TMRA1_ICONR_ITEN4 (*((volatile unsigned int*)(0x422A120CUL))) +#define bM4_TMRA1_ICONR_ITEN5 (*((volatile unsigned int*)(0x422A1210UL))) +#define bM4_TMRA1_ICONR_ITEN6 (*((volatile unsigned int*)(0x422A1214UL))) +#define bM4_TMRA1_ICONR_ITEN7 (*((volatile unsigned int*)(0x422A1218UL))) +#define bM4_TMRA1_ICONR_ITEN8 (*((volatile unsigned int*)(0x422A121CUL))) +#define bM4_TMRA1_ECONR_ETEN1 (*((volatile unsigned int*)(0x422A1280UL))) +#define bM4_TMRA1_ECONR_ETEN2 (*((volatile unsigned int*)(0x422A1284UL))) +#define bM4_TMRA1_ECONR_ETEN3 (*((volatile unsigned int*)(0x422A1288UL))) +#define bM4_TMRA1_ECONR_ETEN4 (*((volatile unsigned int*)(0x422A128CUL))) +#define bM4_TMRA1_ECONR_ETEN5 (*((volatile unsigned int*)(0x422A1290UL))) +#define bM4_TMRA1_ECONR_ETEN6 (*((volatile unsigned int*)(0x422A1294UL))) +#define bM4_TMRA1_ECONR_ETEN7 (*((volatile unsigned int*)(0x422A1298UL))) +#define bM4_TMRA1_ECONR_ETEN8 (*((volatile unsigned int*)(0x422A129CUL))) +#define bM4_TMRA1_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422A1300UL))) +#define bM4_TMRA1_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422A1304UL))) +#define bM4_TMRA1_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422A1308UL))) +#define bM4_TMRA1_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422A1320UL))) +#define bM4_TMRA1_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422A1324UL))) +#define bM4_TMRA1_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422A1328UL))) +#define bM4_TMRA1_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422A1330UL))) +#define bM4_TMRA1_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422A1334UL))) +#define bM4_TMRA1_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422A1338UL))) +#define bM4_TMRA1_STFLR_CMPF1 (*((volatile unsigned int*)(0x422A1380UL))) +#define bM4_TMRA1_STFLR_CMPF2 (*((volatile unsigned int*)(0x422A1384UL))) +#define bM4_TMRA1_STFLR_CMPF3 (*((volatile unsigned int*)(0x422A1388UL))) +#define bM4_TMRA1_STFLR_CMPF4 (*((volatile unsigned int*)(0x422A138CUL))) +#define bM4_TMRA1_STFLR_CMPF5 (*((volatile unsigned int*)(0x422A1390UL))) +#define bM4_TMRA1_STFLR_CMPF6 (*((volatile unsigned int*)(0x422A1394UL))) +#define bM4_TMRA1_STFLR_CMPF7 (*((volatile unsigned int*)(0x422A1398UL))) +#define bM4_TMRA1_STFLR_CMPF8 (*((volatile unsigned int*)(0x422A139CUL))) +#define bM4_TMRA1_BCONR1_BEN (*((volatile unsigned int*)(0x422A1800UL))) +#define bM4_TMRA1_BCONR1_BSE0 (*((volatile unsigned int*)(0x422A1804UL))) +#define bM4_TMRA1_BCONR1_BSE1 (*((volatile unsigned int*)(0x422A1808UL))) +#define bM4_TMRA1_BCONR2_BEN (*((volatile unsigned int*)(0x422A1900UL))) +#define bM4_TMRA1_BCONR2_BSE0 (*((volatile unsigned int*)(0x422A1904UL))) +#define bM4_TMRA1_BCONR2_BSE1 (*((volatile unsigned int*)(0x422A1908UL))) +#define bM4_TMRA1_BCONR3_BEN (*((volatile unsigned int*)(0x422A1A00UL))) +#define bM4_TMRA1_BCONR3_BSE0 (*((volatile unsigned int*)(0x422A1A04UL))) +#define bM4_TMRA1_BCONR3_BSE1 (*((volatile unsigned int*)(0x422A1A08UL))) +#define bM4_TMRA1_BCONR4_BEN (*((volatile unsigned int*)(0x422A1B00UL))) +#define bM4_TMRA1_BCONR4_BSE0 (*((volatile unsigned int*)(0x422A1B04UL))) +#define bM4_TMRA1_BCONR4_BSE1 (*((volatile unsigned int*)(0x422A1B08UL))) +#define bM4_TMRA1_CCONR1_CAPMD (*((volatile unsigned int*)(0x422A2000UL))) +#define bM4_TMRA1_CCONR1_HICP0 (*((volatile unsigned int*)(0x422A2010UL))) +#define bM4_TMRA1_CCONR1_HICP1 (*((volatile unsigned int*)(0x422A2014UL))) +#define bM4_TMRA1_CCONR1_HICP2 (*((volatile unsigned int*)(0x422A2018UL))) +#define bM4_TMRA1_CCONR1_HICP3 (*((volatile unsigned int*)(0x422A2020UL))) +#define bM4_TMRA1_CCONR1_HICP4 (*((volatile unsigned int*)(0x422A2024UL))) +#define bM4_TMRA1_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422A2030UL))) +#define bM4_TMRA1_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422A2034UL))) +#define bM4_TMRA1_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422A2038UL))) +#define bM4_TMRA1_CCONR2_CAPMD (*((volatile unsigned int*)(0x422A2080UL))) +#define bM4_TMRA1_CCONR2_HICP0 (*((volatile unsigned int*)(0x422A2090UL))) +#define bM4_TMRA1_CCONR2_HICP1 (*((volatile unsigned int*)(0x422A2094UL))) +#define bM4_TMRA1_CCONR2_HICP2 (*((volatile unsigned int*)(0x422A2098UL))) +#define bM4_TMRA1_CCONR2_HICP3 (*((volatile unsigned int*)(0x422A20A0UL))) +#define bM4_TMRA1_CCONR2_HICP4 (*((volatile unsigned int*)(0x422A20A4UL))) +#define bM4_TMRA1_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422A20B0UL))) +#define bM4_TMRA1_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422A20B4UL))) +#define bM4_TMRA1_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422A20B8UL))) +#define bM4_TMRA1_CCONR3_CAPMD (*((volatile unsigned int*)(0x422A2100UL))) +#define bM4_TMRA1_CCONR3_HICP0 (*((volatile unsigned int*)(0x422A2110UL))) +#define bM4_TMRA1_CCONR3_HICP1 (*((volatile unsigned int*)(0x422A2114UL))) +#define bM4_TMRA1_CCONR3_HICP2 (*((volatile unsigned int*)(0x422A2118UL))) +#define bM4_TMRA1_CCONR3_HICP3 (*((volatile unsigned int*)(0x422A2120UL))) +#define bM4_TMRA1_CCONR3_HICP4 (*((volatile unsigned int*)(0x422A2124UL))) +#define bM4_TMRA1_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422A2130UL))) +#define bM4_TMRA1_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422A2134UL))) +#define bM4_TMRA1_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422A2138UL))) +#define bM4_TMRA1_CCONR4_CAPMD (*((volatile unsigned int*)(0x422A2180UL))) +#define bM4_TMRA1_CCONR4_HICP0 (*((volatile unsigned int*)(0x422A2190UL))) +#define bM4_TMRA1_CCONR4_HICP1 (*((volatile unsigned int*)(0x422A2194UL))) +#define bM4_TMRA1_CCONR4_HICP2 (*((volatile unsigned int*)(0x422A2198UL))) +#define bM4_TMRA1_CCONR4_HICP3 (*((volatile unsigned int*)(0x422A21A0UL))) +#define bM4_TMRA1_CCONR4_HICP4 (*((volatile unsigned int*)(0x422A21A4UL))) +#define bM4_TMRA1_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422A21B0UL))) +#define bM4_TMRA1_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422A21B4UL))) +#define bM4_TMRA1_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422A21B8UL))) +#define bM4_TMRA1_CCONR5_CAPMD (*((volatile unsigned int*)(0x422A2200UL))) +#define bM4_TMRA1_CCONR5_HICP0 (*((volatile unsigned int*)(0x422A2210UL))) +#define bM4_TMRA1_CCONR5_HICP1 (*((volatile unsigned int*)(0x422A2214UL))) +#define bM4_TMRA1_CCONR5_HICP2 (*((volatile unsigned int*)(0x422A2218UL))) +#define bM4_TMRA1_CCONR5_HICP3 (*((volatile unsigned int*)(0x422A2220UL))) +#define bM4_TMRA1_CCONR5_HICP4 (*((volatile unsigned int*)(0x422A2224UL))) +#define bM4_TMRA1_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422A2230UL))) +#define bM4_TMRA1_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422A2234UL))) +#define bM4_TMRA1_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422A2238UL))) +#define bM4_TMRA1_CCONR6_CAPMD (*((volatile unsigned int*)(0x422A2280UL))) +#define bM4_TMRA1_CCONR6_HICP0 (*((volatile unsigned int*)(0x422A2290UL))) +#define bM4_TMRA1_CCONR6_HICP1 (*((volatile unsigned int*)(0x422A2294UL))) +#define bM4_TMRA1_CCONR6_HICP2 (*((volatile unsigned int*)(0x422A2298UL))) +#define bM4_TMRA1_CCONR6_HICP3 (*((volatile unsigned int*)(0x422A22A0UL))) +#define bM4_TMRA1_CCONR6_HICP4 (*((volatile unsigned int*)(0x422A22A4UL))) +#define bM4_TMRA1_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422A22B0UL))) +#define bM4_TMRA1_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422A22B4UL))) +#define bM4_TMRA1_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422A22B8UL))) +#define bM4_TMRA1_CCONR7_CAPMD (*((volatile unsigned int*)(0x422A2300UL))) +#define bM4_TMRA1_CCONR7_HICP0 (*((volatile unsigned int*)(0x422A2310UL))) +#define bM4_TMRA1_CCONR7_HICP1 (*((volatile unsigned int*)(0x422A2314UL))) +#define bM4_TMRA1_CCONR7_HICP2 (*((volatile unsigned int*)(0x422A2318UL))) +#define bM4_TMRA1_CCONR7_HICP3 (*((volatile unsigned int*)(0x422A2320UL))) +#define bM4_TMRA1_CCONR7_HICP4 (*((volatile unsigned int*)(0x422A2324UL))) +#define bM4_TMRA1_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422A2330UL))) +#define bM4_TMRA1_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422A2334UL))) +#define bM4_TMRA1_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422A2338UL))) +#define bM4_TMRA1_CCONR8_CAPMD (*((volatile unsigned int*)(0x422A2380UL))) +#define bM4_TMRA1_CCONR8_HICP0 (*((volatile unsigned int*)(0x422A2390UL))) +#define bM4_TMRA1_CCONR8_HICP1 (*((volatile unsigned int*)(0x422A2394UL))) +#define bM4_TMRA1_CCONR8_HICP2 (*((volatile unsigned int*)(0x422A2398UL))) +#define bM4_TMRA1_CCONR8_HICP3 (*((volatile unsigned int*)(0x422A23A0UL))) +#define bM4_TMRA1_CCONR8_HICP4 (*((volatile unsigned int*)(0x422A23A4UL))) +#define bM4_TMRA1_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422A23B0UL))) +#define bM4_TMRA1_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422A23B4UL))) +#define bM4_TMRA1_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422A23B8UL))) +#define bM4_TMRA1_PCONR1_STAC0 (*((volatile unsigned int*)(0x422A2800UL))) +#define bM4_TMRA1_PCONR1_STAC1 (*((volatile unsigned int*)(0x422A2804UL))) +#define bM4_TMRA1_PCONR1_STPC0 (*((volatile unsigned int*)(0x422A2808UL))) +#define bM4_TMRA1_PCONR1_STPC1 (*((volatile unsigned int*)(0x422A280CUL))) +#define bM4_TMRA1_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422A2810UL))) +#define bM4_TMRA1_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422A2814UL))) +#define bM4_TMRA1_PCONR1_PERC0 (*((volatile unsigned int*)(0x422A2818UL))) +#define bM4_TMRA1_PCONR1_PERC1 (*((volatile unsigned int*)(0x422A281CUL))) +#define bM4_TMRA1_PCONR1_FORC0 (*((volatile unsigned int*)(0x422A2820UL))) +#define bM4_TMRA1_PCONR1_FORC1 (*((volatile unsigned int*)(0x422A2824UL))) +#define bM4_TMRA1_PCONR1_OUTEN (*((volatile unsigned int*)(0x422A2830UL))) +#define bM4_TMRA1_PCONR2_STAC0 (*((volatile unsigned int*)(0x422A2880UL))) +#define bM4_TMRA1_PCONR2_STAC1 (*((volatile unsigned int*)(0x422A2884UL))) +#define bM4_TMRA1_PCONR2_STPC0 (*((volatile unsigned int*)(0x422A2888UL))) +#define bM4_TMRA1_PCONR2_STPC1 (*((volatile unsigned int*)(0x422A288CUL))) +#define bM4_TMRA1_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422A2890UL))) +#define bM4_TMRA1_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422A2894UL))) +#define bM4_TMRA1_PCONR2_PERC0 (*((volatile unsigned int*)(0x422A2898UL))) +#define bM4_TMRA1_PCONR2_PERC1 (*((volatile unsigned int*)(0x422A289CUL))) +#define bM4_TMRA1_PCONR2_FORC0 (*((volatile unsigned int*)(0x422A28A0UL))) +#define bM4_TMRA1_PCONR2_FORC1 (*((volatile unsigned int*)(0x422A28A4UL))) +#define bM4_TMRA1_PCONR2_OUTEN (*((volatile unsigned int*)(0x422A28B0UL))) +#define bM4_TMRA1_PCONR3_STAC0 (*((volatile unsigned int*)(0x422A2900UL))) +#define bM4_TMRA1_PCONR3_STAC1 (*((volatile unsigned int*)(0x422A2904UL))) +#define bM4_TMRA1_PCONR3_STPC0 (*((volatile unsigned int*)(0x422A2908UL))) +#define bM4_TMRA1_PCONR3_STPC1 (*((volatile unsigned int*)(0x422A290CUL))) +#define bM4_TMRA1_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422A2910UL))) +#define bM4_TMRA1_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422A2914UL))) +#define bM4_TMRA1_PCONR3_PERC0 (*((volatile unsigned int*)(0x422A2918UL))) +#define bM4_TMRA1_PCONR3_PERC1 (*((volatile unsigned int*)(0x422A291CUL))) +#define bM4_TMRA1_PCONR3_FORC0 (*((volatile unsigned int*)(0x422A2920UL))) +#define bM4_TMRA1_PCONR3_FORC1 (*((volatile unsigned int*)(0x422A2924UL))) +#define bM4_TMRA1_PCONR3_OUTEN (*((volatile unsigned int*)(0x422A2930UL))) +#define bM4_TMRA1_PCONR4_STAC0 (*((volatile unsigned int*)(0x422A2980UL))) +#define bM4_TMRA1_PCONR4_STAC1 (*((volatile unsigned int*)(0x422A2984UL))) +#define bM4_TMRA1_PCONR4_STPC0 (*((volatile unsigned int*)(0x422A2988UL))) +#define bM4_TMRA1_PCONR4_STPC1 (*((volatile unsigned int*)(0x422A298CUL))) +#define bM4_TMRA1_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422A2990UL))) +#define bM4_TMRA1_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422A2994UL))) +#define bM4_TMRA1_PCONR4_PERC0 (*((volatile unsigned int*)(0x422A2998UL))) +#define bM4_TMRA1_PCONR4_PERC1 (*((volatile unsigned int*)(0x422A299CUL))) +#define bM4_TMRA1_PCONR4_FORC0 (*((volatile unsigned int*)(0x422A29A0UL))) +#define bM4_TMRA1_PCONR4_FORC1 (*((volatile unsigned int*)(0x422A29A4UL))) +#define bM4_TMRA1_PCONR4_OUTEN (*((volatile unsigned int*)(0x422A29B0UL))) +#define bM4_TMRA1_PCONR5_STAC0 (*((volatile unsigned int*)(0x422A2A00UL))) +#define bM4_TMRA1_PCONR5_STAC1 (*((volatile unsigned int*)(0x422A2A04UL))) +#define bM4_TMRA1_PCONR5_STPC0 (*((volatile unsigned int*)(0x422A2A08UL))) +#define bM4_TMRA1_PCONR5_STPC1 (*((volatile unsigned int*)(0x422A2A0CUL))) +#define bM4_TMRA1_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422A2A10UL))) +#define bM4_TMRA1_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422A2A14UL))) +#define bM4_TMRA1_PCONR5_PERC0 (*((volatile unsigned int*)(0x422A2A18UL))) +#define bM4_TMRA1_PCONR5_PERC1 (*((volatile unsigned int*)(0x422A2A1CUL))) +#define bM4_TMRA1_PCONR5_FORC0 (*((volatile unsigned int*)(0x422A2A20UL))) +#define bM4_TMRA1_PCONR5_FORC1 (*((volatile unsigned int*)(0x422A2A24UL))) +#define bM4_TMRA1_PCONR5_OUTEN (*((volatile unsigned int*)(0x422A2A30UL))) +#define bM4_TMRA1_PCONR6_STAC0 (*((volatile unsigned int*)(0x422A2A80UL))) +#define bM4_TMRA1_PCONR6_STAC1 (*((volatile unsigned int*)(0x422A2A84UL))) +#define bM4_TMRA1_PCONR6_STPC0 (*((volatile unsigned int*)(0x422A2A88UL))) +#define bM4_TMRA1_PCONR6_STPC1 (*((volatile unsigned int*)(0x422A2A8CUL))) +#define bM4_TMRA1_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422A2A90UL))) +#define bM4_TMRA1_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422A2A94UL))) +#define bM4_TMRA1_PCONR6_PERC0 (*((volatile unsigned int*)(0x422A2A98UL))) +#define bM4_TMRA1_PCONR6_PERC1 (*((volatile unsigned int*)(0x422A2A9CUL))) +#define bM4_TMRA1_PCONR6_FORC0 (*((volatile unsigned int*)(0x422A2AA0UL))) +#define bM4_TMRA1_PCONR6_FORC1 (*((volatile unsigned int*)(0x422A2AA4UL))) +#define bM4_TMRA1_PCONR6_OUTEN (*((volatile unsigned int*)(0x422A2AB0UL))) +#define bM4_TMRA1_PCONR7_STAC0 (*((volatile unsigned int*)(0x422A2B00UL))) +#define bM4_TMRA1_PCONR7_STAC1 (*((volatile unsigned int*)(0x422A2B04UL))) +#define bM4_TMRA1_PCONR7_STPC0 (*((volatile unsigned int*)(0x422A2B08UL))) +#define bM4_TMRA1_PCONR7_STPC1 (*((volatile unsigned int*)(0x422A2B0CUL))) +#define bM4_TMRA1_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422A2B10UL))) +#define bM4_TMRA1_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422A2B14UL))) +#define bM4_TMRA1_PCONR7_PERC0 (*((volatile unsigned int*)(0x422A2B18UL))) +#define bM4_TMRA1_PCONR7_PERC1 (*((volatile unsigned int*)(0x422A2B1CUL))) +#define bM4_TMRA1_PCONR7_FORC0 (*((volatile unsigned int*)(0x422A2B20UL))) +#define bM4_TMRA1_PCONR7_FORC1 (*((volatile unsigned int*)(0x422A2B24UL))) +#define bM4_TMRA1_PCONR7_OUTEN (*((volatile unsigned int*)(0x422A2B30UL))) +#define bM4_TMRA1_PCONR8_STAC0 (*((volatile unsigned int*)(0x422A2B80UL))) +#define bM4_TMRA1_PCONR8_STAC1 (*((volatile unsigned int*)(0x422A2B84UL))) +#define bM4_TMRA1_PCONR8_STPC0 (*((volatile unsigned int*)(0x422A2B88UL))) +#define bM4_TMRA1_PCONR8_STPC1 (*((volatile unsigned int*)(0x422A2B8CUL))) +#define bM4_TMRA1_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422A2B90UL))) +#define bM4_TMRA1_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422A2B94UL))) +#define bM4_TMRA1_PCONR8_PERC0 (*((volatile unsigned int*)(0x422A2B98UL))) +#define bM4_TMRA1_PCONR8_PERC1 (*((volatile unsigned int*)(0x422A2B9CUL))) +#define bM4_TMRA1_PCONR8_FORC0 (*((volatile unsigned int*)(0x422A2BA0UL))) +#define bM4_TMRA1_PCONR8_FORC1 (*((volatile unsigned int*)(0x422A2BA4UL))) +#define bM4_TMRA1_PCONR8_OUTEN (*((volatile unsigned int*)(0x422A2BB0UL))) +#define bM4_TMRA2_CNTER_CNT0 (*((volatile unsigned int*)(0x422A8000UL))) +#define bM4_TMRA2_CNTER_CNT1 (*((volatile unsigned int*)(0x422A8004UL))) +#define bM4_TMRA2_CNTER_CNT2 (*((volatile unsigned int*)(0x422A8008UL))) +#define bM4_TMRA2_CNTER_CNT3 (*((volatile unsigned int*)(0x422A800CUL))) +#define bM4_TMRA2_CNTER_CNT4 (*((volatile unsigned int*)(0x422A8010UL))) +#define bM4_TMRA2_CNTER_CNT5 (*((volatile unsigned int*)(0x422A8014UL))) +#define bM4_TMRA2_CNTER_CNT6 (*((volatile unsigned int*)(0x422A8018UL))) +#define bM4_TMRA2_CNTER_CNT7 (*((volatile unsigned int*)(0x422A801CUL))) +#define bM4_TMRA2_CNTER_CNT8 (*((volatile unsigned int*)(0x422A8020UL))) +#define bM4_TMRA2_CNTER_CNT9 (*((volatile unsigned int*)(0x422A8024UL))) +#define bM4_TMRA2_CNTER_CNT10 (*((volatile unsigned int*)(0x422A8028UL))) +#define bM4_TMRA2_CNTER_CNT11 (*((volatile unsigned int*)(0x422A802CUL))) +#define bM4_TMRA2_CNTER_CNT12 (*((volatile unsigned int*)(0x422A8030UL))) +#define bM4_TMRA2_CNTER_CNT13 (*((volatile unsigned int*)(0x422A8034UL))) +#define bM4_TMRA2_CNTER_CNT14 (*((volatile unsigned int*)(0x422A8038UL))) +#define bM4_TMRA2_CNTER_CNT15 (*((volatile unsigned int*)(0x422A803CUL))) +#define bM4_TMRA2_PERAR_PER0 (*((volatile unsigned int*)(0x422A8080UL))) +#define bM4_TMRA2_PERAR_PER1 (*((volatile unsigned int*)(0x422A8084UL))) +#define bM4_TMRA2_PERAR_PER2 (*((volatile unsigned int*)(0x422A8088UL))) +#define bM4_TMRA2_PERAR_PER3 (*((volatile unsigned int*)(0x422A808CUL))) +#define bM4_TMRA2_PERAR_PER4 (*((volatile unsigned int*)(0x422A8090UL))) +#define bM4_TMRA2_PERAR_PER5 (*((volatile unsigned int*)(0x422A8094UL))) +#define bM4_TMRA2_PERAR_PER6 (*((volatile unsigned int*)(0x422A8098UL))) +#define bM4_TMRA2_PERAR_PER7 (*((volatile unsigned int*)(0x422A809CUL))) +#define bM4_TMRA2_PERAR_PER8 (*((volatile unsigned int*)(0x422A80A0UL))) +#define bM4_TMRA2_PERAR_PER9 (*((volatile unsigned int*)(0x422A80A4UL))) +#define bM4_TMRA2_PERAR_PER10 (*((volatile unsigned int*)(0x422A80A8UL))) +#define bM4_TMRA2_PERAR_PER11 (*((volatile unsigned int*)(0x422A80ACUL))) +#define bM4_TMRA2_PERAR_PER12 (*((volatile unsigned int*)(0x422A80B0UL))) +#define bM4_TMRA2_PERAR_PER13 (*((volatile unsigned int*)(0x422A80B4UL))) +#define bM4_TMRA2_PERAR_PER14 (*((volatile unsigned int*)(0x422A80B8UL))) +#define bM4_TMRA2_PERAR_PER15 (*((volatile unsigned int*)(0x422A80BCUL))) +#define bM4_TMRA2_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422A8800UL))) +#define bM4_TMRA2_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422A8804UL))) +#define bM4_TMRA2_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422A8808UL))) +#define bM4_TMRA2_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422A880CUL))) +#define bM4_TMRA2_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422A8810UL))) +#define bM4_TMRA2_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422A8814UL))) +#define bM4_TMRA2_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422A8818UL))) +#define bM4_TMRA2_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422A881CUL))) +#define bM4_TMRA2_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422A8820UL))) +#define bM4_TMRA2_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422A8824UL))) +#define bM4_TMRA2_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422A8828UL))) +#define bM4_TMRA2_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422A882CUL))) +#define bM4_TMRA2_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422A8830UL))) +#define bM4_TMRA2_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422A8834UL))) +#define bM4_TMRA2_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422A8838UL))) +#define bM4_TMRA2_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422A883CUL))) +#define bM4_TMRA2_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422A8880UL))) +#define bM4_TMRA2_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422A8884UL))) +#define bM4_TMRA2_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422A8888UL))) +#define bM4_TMRA2_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422A888CUL))) +#define bM4_TMRA2_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422A8890UL))) +#define bM4_TMRA2_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422A8894UL))) +#define bM4_TMRA2_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422A8898UL))) +#define bM4_TMRA2_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422A889CUL))) +#define bM4_TMRA2_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422A88A0UL))) +#define bM4_TMRA2_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422A88A4UL))) +#define bM4_TMRA2_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422A88A8UL))) +#define bM4_TMRA2_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422A88ACUL))) +#define bM4_TMRA2_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422A88B0UL))) +#define bM4_TMRA2_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422A88B4UL))) +#define bM4_TMRA2_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422A88B8UL))) +#define bM4_TMRA2_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422A88BCUL))) +#define bM4_TMRA2_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422A8900UL))) +#define bM4_TMRA2_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422A8904UL))) +#define bM4_TMRA2_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422A8908UL))) +#define bM4_TMRA2_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422A890CUL))) +#define bM4_TMRA2_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422A8910UL))) +#define bM4_TMRA2_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422A8914UL))) +#define bM4_TMRA2_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422A8918UL))) +#define bM4_TMRA2_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422A891CUL))) +#define bM4_TMRA2_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422A8920UL))) +#define bM4_TMRA2_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422A8924UL))) +#define bM4_TMRA2_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422A8928UL))) +#define bM4_TMRA2_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422A892CUL))) +#define bM4_TMRA2_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422A8930UL))) +#define bM4_TMRA2_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422A8934UL))) +#define bM4_TMRA2_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422A8938UL))) +#define bM4_TMRA2_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422A893CUL))) +#define bM4_TMRA2_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422A8980UL))) +#define bM4_TMRA2_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422A8984UL))) +#define bM4_TMRA2_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422A8988UL))) +#define bM4_TMRA2_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422A898CUL))) +#define bM4_TMRA2_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422A8990UL))) +#define bM4_TMRA2_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422A8994UL))) +#define bM4_TMRA2_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422A8998UL))) +#define bM4_TMRA2_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422A899CUL))) +#define bM4_TMRA2_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422A89A0UL))) +#define bM4_TMRA2_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422A89A4UL))) +#define bM4_TMRA2_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422A89A8UL))) +#define bM4_TMRA2_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422A89ACUL))) +#define bM4_TMRA2_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422A89B0UL))) +#define bM4_TMRA2_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422A89B4UL))) +#define bM4_TMRA2_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422A89B8UL))) +#define bM4_TMRA2_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422A89BCUL))) +#define bM4_TMRA2_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422A8A00UL))) +#define bM4_TMRA2_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422A8A04UL))) +#define bM4_TMRA2_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422A8A08UL))) +#define bM4_TMRA2_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422A8A0CUL))) +#define bM4_TMRA2_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422A8A10UL))) +#define bM4_TMRA2_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422A8A14UL))) +#define bM4_TMRA2_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422A8A18UL))) +#define bM4_TMRA2_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422A8A1CUL))) +#define bM4_TMRA2_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422A8A20UL))) +#define bM4_TMRA2_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422A8A24UL))) +#define bM4_TMRA2_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422A8A28UL))) +#define bM4_TMRA2_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422A8A2CUL))) +#define bM4_TMRA2_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422A8A30UL))) +#define bM4_TMRA2_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422A8A34UL))) +#define bM4_TMRA2_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422A8A38UL))) +#define bM4_TMRA2_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422A8A3CUL))) +#define bM4_TMRA2_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422A8A80UL))) +#define bM4_TMRA2_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422A8A84UL))) +#define bM4_TMRA2_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422A8A88UL))) +#define bM4_TMRA2_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422A8A8CUL))) +#define bM4_TMRA2_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422A8A90UL))) +#define bM4_TMRA2_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422A8A94UL))) +#define bM4_TMRA2_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422A8A98UL))) +#define bM4_TMRA2_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422A8A9CUL))) +#define bM4_TMRA2_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422A8AA0UL))) +#define bM4_TMRA2_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422A8AA4UL))) +#define bM4_TMRA2_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422A8AA8UL))) +#define bM4_TMRA2_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422A8AACUL))) +#define bM4_TMRA2_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422A8AB0UL))) +#define bM4_TMRA2_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422A8AB4UL))) +#define bM4_TMRA2_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422A8AB8UL))) +#define bM4_TMRA2_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422A8ABCUL))) +#define bM4_TMRA2_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422A8B00UL))) +#define bM4_TMRA2_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422A8B04UL))) +#define bM4_TMRA2_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422A8B08UL))) +#define bM4_TMRA2_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422A8B0CUL))) +#define bM4_TMRA2_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422A8B10UL))) +#define bM4_TMRA2_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422A8B14UL))) +#define bM4_TMRA2_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422A8B18UL))) +#define bM4_TMRA2_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422A8B1CUL))) +#define bM4_TMRA2_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422A8B20UL))) +#define bM4_TMRA2_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422A8B24UL))) +#define bM4_TMRA2_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422A8B28UL))) +#define bM4_TMRA2_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422A8B2CUL))) +#define bM4_TMRA2_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422A8B30UL))) +#define bM4_TMRA2_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422A8B34UL))) +#define bM4_TMRA2_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422A8B38UL))) +#define bM4_TMRA2_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422A8B3CUL))) +#define bM4_TMRA2_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422A8B80UL))) +#define bM4_TMRA2_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422A8B84UL))) +#define bM4_TMRA2_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422A8B88UL))) +#define bM4_TMRA2_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422A8B8CUL))) +#define bM4_TMRA2_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422A8B90UL))) +#define bM4_TMRA2_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422A8B94UL))) +#define bM4_TMRA2_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422A8B98UL))) +#define bM4_TMRA2_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422A8B9CUL))) +#define bM4_TMRA2_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422A8BA0UL))) +#define bM4_TMRA2_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422A8BA4UL))) +#define bM4_TMRA2_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422A8BA8UL))) +#define bM4_TMRA2_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422A8BACUL))) +#define bM4_TMRA2_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422A8BB0UL))) +#define bM4_TMRA2_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422A8BB4UL))) +#define bM4_TMRA2_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422A8BB8UL))) +#define bM4_TMRA2_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422A8BBCUL))) +#define bM4_TMRA2_BCSTR_START (*((volatile unsigned int*)(0x422A9000UL))) +#define bM4_TMRA2_BCSTR_DIR (*((volatile unsigned int*)(0x422A9004UL))) +#define bM4_TMRA2_BCSTR_MODE (*((volatile unsigned int*)(0x422A9008UL))) +#define bM4_TMRA2_BCSTR_SYNST (*((volatile unsigned int*)(0x422A900CUL))) +#define bM4_TMRA2_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422A9010UL))) +#define bM4_TMRA2_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422A9014UL))) +#define bM4_TMRA2_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422A9018UL))) +#define bM4_TMRA2_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422A901CUL))) +#define bM4_TMRA2_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422A9030UL))) +#define bM4_TMRA2_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422A9034UL))) +#define bM4_TMRA2_BCSTR_OVFF (*((volatile unsigned int*)(0x422A9038UL))) +#define bM4_TMRA2_BCSTR_UDFF (*((volatile unsigned int*)(0x422A903CUL))) +#define bM4_TMRA2_HCONR_HSTA0 (*((volatile unsigned int*)(0x422A9080UL))) +#define bM4_TMRA2_HCONR_HSTA1 (*((volatile unsigned int*)(0x422A9084UL))) +#define bM4_TMRA2_HCONR_HSTA2 (*((volatile unsigned int*)(0x422A9088UL))) +#define bM4_TMRA2_HCONR_HSTP0 (*((volatile unsigned int*)(0x422A9090UL))) +#define bM4_TMRA2_HCONR_HSTP1 (*((volatile unsigned int*)(0x422A9094UL))) +#define bM4_TMRA2_HCONR_HSTP2 (*((volatile unsigned int*)(0x422A9098UL))) +#define bM4_TMRA2_HCONR_HCLE0 (*((volatile unsigned int*)(0x422A90A0UL))) +#define bM4_TMRA2_HCONR_HCLE1 (*((volatile unsigned int*)(0x422A90A4UL))) +#define bM4_TMRA2_HCONR_HCLE2 (*((volatile unsigned int*)(0x422A90A8UL))) +#define bM4_TMRA2_HCONR_HCLE3 (*((volatile unsigned int*)(0x422A90B0UL))) +#define bM4_TMRA2_HCONR_HCLE4 (*((volatile unsigned int*)(0x422A90B4UL))) +#define bM4_TMRA2_HCONR_HCLE5 (*((volatile unsigned int*)(0x422A90B8UL))) +#define bM4_TMRA2_HCONR_HCLE6 (*((volatile unsigned int*)(0x422A90BCUL))) +#define bM4_TMRA2_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422A9100UL))) +#define bM4_TMRA2_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422A9104UL))) +#define bM4_TMRA2_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422A9108UL))) +#define bM4_TMRA2_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422A910CUL))) +#define bM4_TMRA2_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422A9110UL))) +#define bM4_TMRA2_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422A9114UL))) +#define bM4_TMRA2_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422A9118UL))) +#define bM4_TMRA2_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422A911CUL))) +#define bM4_TMRA2_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422A9120UL))) +#define bM4_TMRA2_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422A9124UL))) +#define bM4_TMRA2_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422A9128UL))) +#define bM4_TMRA2_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422A912CUL))) +#define bM4_TMRA2_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422A9130UL))) +#define bM4_TMRA2_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422A9180UL))) +#define bM4_TMRA2_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422A9184UL))) +#define bM4_TMRA2_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422A9188UL))) +#define bM4_TMRA2_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422A918CUL))) +#define bM4_TMRA2_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422A9190UL))) +#define bM4_TMRA2_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422A9194UL))) +#define bM4_TMRA2_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422A9198UL))) +#define bM4_TMRA2_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422A919CUL))) +#define bM4_TMRA2_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422A91A0UL))) +#define bM4_TMRA2_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422A91A4UL))) +#define bM4_TMRA2_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422A91A8UL))) +#define bM4_TMRA2_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422A91ACUL))) +#define bM4_TMRA2_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422A91B0UL))) +#define bM4_TMRA2_ICONR_ITEN1 (*((volatile unsigned int*)(0x422A9200UL))) +#define bM4_TMRA2_ICONR_ITEN2 (*((volatile unsigned int*)(0x422A9204UL))) +#define bM4_TMRA2_ICONR_ITEN3 (*((volatile unsigned int*)(0x422A9208UL))) +#define bM4_TMRA2_ICONR_ITEN4 (*((volatile unsigned int*)(0x422A920CUL))) +#define bM4_TMRA2_ICONR_ITEN5 (*((volatile unsigned int*)(0x422A9210UL))) +#define bM4_TMRA2_ICONR_ITEN6 (*((volatile unsigned int*)(0x422A9214UL))) +#define bM4_TMRA2_ICONR_ITEN7 (*((volatile unsigned int*)(0x422A9218UL))) +#define bM4_TMRA2_ICONR_ITEN8 (*((volatile unsigned int*)(0x422A921CUL))) +#define bM4_TMRA2_ECONR_ETEN1 (*((volatile unsigned int*)(0x422A9280UL))) +#define bM4_TMRA2_ECONR_ETEN2 (*((volatile unsigned int*)(0x422A9284UL))) +#define bM4_TMRA2_ECONR_ETEN3 (*((volatile unsigned int*)(0x422A9288UL))) +#define bM4_TMRA2_ECONR_ETEN4 (*((volatile unsigned int*)(0x422A928CUL))) +#define bM4_TMRA2_ECONR_ETEN5 (*((volatile unsigned int*)(0x422A9290UL))) +#define bM4_TMRA2_ECONR_ETEN6 (*((volatile unsigned int*)(0x422A9294UL))) +#define bM4_TMRA2_ECONR_ETEN7 (*((volatile unsigned int*)(0x422A9298UL))) +#define bM4_TMRA2_ECONR_ETEN8 (*((volatile unsigned int*)(0x422A929CUL))) +#define bM4_TMRA2_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422A9300UL))) +#define bM4_TMRA2_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422A9304UL))) +#define bM4_TMRA2_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422A9308UL))) +#define bM4_TMRA2_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422A9320UL))) +#define bM4_TMRA2_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422A9324UL))) +#define bM4_TMRA2_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422A9328UL))) +#define bM4_TMRA2_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422A9330UL))) +#define bM4_TMRA2_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422A9334UL))) +#define bM4_TMRA2_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422A9338UL))) +#define bM4_TMRA2_STFLR_CMPF1 (*((volatile unsigned int*)(0x422A9380UL))) +#define bM4_TMRA2_STFLR_CMPF2 (*((volatile unsigned int*)(0x422A9384UL))) +#define bM4_TMRA2_STFLR_CMPF3 (*((volatile unsigned int*)(0x422A9388UL))) +#define bM4_TMRA2_STFLR_CMPF4 (*((volatile unsigned int*)(0x422A938CUL))) +#define bM4_TMRA2_STFLR_CMPF5 (*((volatile unsigned int*)(0x422A9390UL))) +#define bM4_TMRA2_STFLR_CMPF6 (*((volatile unsigned int*)(0x422A9394UL))) +#define bM4_TMRA2_STFLR_CMPF7 (*((volatile unsigned int*)(0x422A9398UL))) +#define bM4_TMRA2_STFLR_CMPF8 (*((volatile unsigned int*)(0x422A939CUL))) +#define bM4_TMRA2_BCONR1_BEN (*((volatile unsigned int*)(0x422A9800UL))) +#define bM4_TMRA2_BCONR1_BSE0 (*((volatile unsigned int*)(0x422A9804UL))) +#define bM4_TMRA2_BCONR1_BSE1 (*((volatile unsigned int*)(0x422A9808UL))) +#define bM4_TMRA2_BCONR2_BEN (*((volatile unsigned int*)(0x422A9900UL))) +#define bM4_TMRA2_BCONR2_BSE0 (*((volatile unsigned int*)(0x422A9904UL))) +#define bM4_TMRA2_BCONR2_BSE1 (*((volatile unsigned int*)(0x422A9908UL))) +#define bM4_TMRA2_BCONR3_BEN (*((volatile unsigned int*)(0x422A9A00UL))) +#define bM4_TMRA2_BCONR3_BSE0 (*((volatile unsigned int*)(0x422A9A04UL))) +#define bM4_TMRA2_BCONR3_BSE1 (*((volatile unsigned int*)(0x422A9A08UL))) +#define bM4_TMRA2_BCONR4_BEN (*((volatile unsigned int*)(0x422A9B00UL))) +#define bM4_TMRA2_BCONR4_BSE0 (*((volatile unsigned int*)(0x422A9B04UL))) +#define bM4_TMRA2_BCONR4_BSE1 (*((volatile unsigned int*)(0x422A9B08UL))) +#define bM4_TMRA2_CCONR1_CAPMD (*((volatile unsigned int*)(0x422AA000UL))) +#define bM4_TMRA2_CCONR1_HICP0 (*((volatile unsigned int*)(0x422AA010UL))) +#define bM4_TMRA2_CCONR1_HICP1 (*((volatile unsigned int*)(0x422AA014UL))) +#define bM4_TMRA2_CCONR1_HICP2 (*((volatile unsigned int*)(0x422AA018UL))) +#define bM4_TMRA2_CCONR1_HICP3 (*((volatile unsigned int*)(0x422AA020UL))) +#define bM4_TMRA2_CCONR1_HICP4 (*((volatile unsigned int*)(0x422AA024UL))) +#define bM4_TMRA2_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422AA030UL))) +#define bM4_TMRA2_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422AA034UL))) +#define bM4_TMRA2_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422AA038UL))) +#define bM4_TMRA2_CCONR2_CAPMD (*((volatile unsigned int*)(0x422AA080UL))) +#define bM4_TMRA2_CCONR2_HICP0 (*((volatile unsigned int*)(0x422AA090UL))) +#define bM4_TMRA2_CCONR2_HICP1 (*((volatile unsigned int*)(0x422AA094UL))) +#define bM4_TMRA2_CCONR2_HICP2 (*((volatile unsigned int*)(0x422AA098UL))) +#define bM4_TMRA2_CCONR2_HICP3 (*((volatile unsigned int*)(0x422AA0A0UL))) +#define bM4_TMRA2_CCONR2_HICP4 (*((volatile unsigned int*)(0x422AA0A4UL))) +#define bM4_TMRA2_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422AA0B0UL))) +#define bM4_TMRA2_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422AA0B4UL))) +#define bM4_TMRA2_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422AA0B8UL))) +#define bM4_TMRA2_CCONR3_CAPMD (*((volatile unsigned int*)(0x422AA100UL))) +#define bM4_TMRA2_CCONR3_HICP0 (*((volatile unsigned int*)(0x422AA110UL))) +#define bM4_TMRA2_CCONR3_HICP1 (*((volatile unsigned int*)(0x422AA114UL))) +#define bM4_TMRA2_CCONR3_HICP2 (*((volatile unsigned int*)(0x422AA118UL))) +#define bM4_TMRA2_CCONR3_HICP3 (*((volatile unsigned int*)(0x422AA120UL))) +#define bM4_TMRA2_CCONR3_HICP4 (*((volatile unsigned int*)(0x422AA124UL))) +#define bM4_TMRA2_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422AA130UL))) +#define bM4_TMRA2_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422AA134UL))) +#define bM4_TMRA2_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422AA138UL))) +#define bM4_TMRA2_CCONR4_CAPMD (*((volatile unsigned int*)(0x422AA180UL))) +#define bM4_TMRA2_CCONR4_HICP0 (*((volatile unsigned int*)(0x422AA190UL))) +#define bM4_TMRA2_CCONR4_HICP1 (*((volatile unsigned int*)(0x422AA194UL))) +#define bM4_TMRA2_CCONR4_HICP2 (*((volatile unsigned int*)(0x422AA198UL))) +#define bM4_TMRA2_CCONR4_HICP3 (*((volatile unsigned int*)(0x422AA1A0UL))) +#define bM4_TMRA2_CCONR4_HICP4 (*((volatile unsigned int*)(0x422AA1A4UL))) +#define bM4_TMRA2_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422AA1B0UL))) +#define bM4_TMRA2_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422AA1B4UL))) +#define bM4_TMRA2_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422AA1B8UL))) +#define bM4_TMRA2_CCONR5_CAPMD (*((volatile unsigned int*)(0x422AA200UL))) +#define bM4_TMRA2_CCONR5_HICP0 (*((volatile unsigned int*)(0x422AA210UL))) +#define bM4_TMRA2_CCONR5_HICP1 (*((volatile unsigned int*)(0x422AA214UL))) +#define bM4_TMRA2_CCONR5_HICP2 (*((volatile unsigned int*)(0x422AA218UL))) +#define bM4_TMRA2_CCONR5_HICP3 (*((volatile unsigned int*)(0x422AA220UL))) +#define bM4_TMRA2_CCONR5_HICP4 (*((volatile unsigned int*)(0x422AA224UL))) +#define bM4_TMRA2_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422AA230UL))) +#define bM4_TMRA2_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422AA234UL))) +#define bM4_TMRA2_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422AA238UL))) +#define bM4_TMRA2_CCONR6_CAPMD (*((volatile unsigned int*)(0x422AA280UL))) +#define bM4_TMRA2_CCONR6_HICP0 (*((volatile unsigned int*)(0x422AA290UL))) +#define bM4_TMRA2_CCONR6_HICP1 (*((volatile unsigned int*)(0x422AA294UL))) +#define bM4_TMRA2_CCONR6_HICP2 (*((volatile unsigned int*)(0x422AA298UL))) +#define bM4_TMRA2_CCONR6_HICP3 (*((volatile unsigned int*)(0x422AA2A0UL))) +#define bM4_TMRA2_CCONR6_HICP4 (*((volatile unsigned int*)(0x422AA2A4UL))) +#define bM4_TMRA2_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422AA2B0UL))) +#define bM4_TMRA2_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422AA2B4UL))) +#define bM4_TMRA2_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422AA2B8UL))) +#define bM4_TMRA2_CCONR7_CAPMD (*((volatile unsigned int*)(0x422AA300UL))) +#define bM4_TMRA2_CCONR7_HICP0 (*((volatile unsigned int*)(0x422AA310UL))) +#define bM4_TMRA2_CCONR7_HICP1 (*((volatile unsigned int*)(0x422AA314UL))) +#define bM4_TMRA2_CCONR7_HICP2 (*((volatile unsigned int*)(0x422AA318UL))) +#define bM4_TMRA2_CCONR7_HICP3 (*((volatile unsigned int*)(0x422AA320UL))) +#define bM4_TMRA2_CCONR7_HICP4 (*((volatile unsigned int*)(0x422AA324UL))) +#define bM4_TMRA2_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422AA330UL))) +#define bM4_TMRA2_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422AA334UL))) +#define bM4_TMRA2_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422AA338UL))) +#define bM4_TMRA2_CCONR8_CAPMD (*((volatile unsigned int*)(0x422AA380UL))) +#define bM4_TMRA2_CCONR8_HICP0 (*((volatile unsigned int*)(0x422AA390UL))) +#define bM4_TMRA2_CCONR8_HICP1 (*((volatile unsigned int*)(0x422AA394UL))) +#define bM4_TMRA2_CCONR8_HICP2 (*((volatile unsigned int*)(0x422AA398UL))) +#define bM4_TMRA2_CCONR8_HICP3 (*((volatile unsigned int*)(0x422AA3A0UL))) +#define bM4_TMRA2_CCONR8_HICP4 (*((volatile unsigned int*)(0x422AA3A4UL))) +#define bM4_TMRA2_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422AA3B0UL))) +#define bM4_TMRA2_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422AA3B4UL))) +#define bM4_TMRA2_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422AA3B8UL))) +#define bM4_TMRA2_PCONR1_STAC0 (*((volatile unsigned int*)(0x422AA800UL))) +#define bM4_TMRA2_PCONR1_STAC1 (*((volatile unsigned int*)(0x422AA804UL))) +#define bM4_TMRA2_PCONR1_STPC0 (*((volatile unsigned int*)(0x422AA808UL))) +#define bM4_TMRA2_PCONR1_STPC1 (*((volatile unsigned int*)(0x422AA80CUL))) +#define bM4_TMRA2_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422AA810UL))) +#define bM4_TMRA2_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422AA814UL))) +#define bM4_TMRA2_PCONR1_PERC0 (*((volatile unsigned int*)(0x422AA818UL))) +#define bM4_TMRA2_PCONR1_PERC1 (*((volatile unsigned int*)(0x422AA81CUL))) +#define bM4_TMRA2_PCONR1_FORC0 (*((volatile unsigned int*)(0x422AA820UL))) +#define bM4_TMRA2_PCONR1_FORC1 (*((volatile unsigned int*)(0x422AA824UL))) +#define bM4_TMRA2_PCONR1_OUTEN (*((volatile unsigned int*)(0x422AA830UL))) +#define bM4_TMRA2_PCONR2_STAC0 (*((volatile unsigned int*)(0x422AA880UL))) +#define bM4_TMRA2_PCONR2_STAC1 (*((volatile unsigned int*)(0x422AA884UL))) +#define bM4_TMRA2_PCONR2_STPC0 (*((volatile unsigned int*)(0x422AA888UL))) +#define bM4_TMRA2_PCONR2_STPC1 (*((volatile unsigned int*)(0x422AA88CUL))) +#define bM4_TMRA2_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422AA890UL))) +#define bM4_TMRA2_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422AA894UL))) +#define bM4_TMRA2_PCONR2_PERC0 (*((volatile unsigned int*)(0x422AA898UL))) +#define bM4_TMRA2_PCONR2_PERC1 (*((volatile unsigned int*)(0x422AA89CUL))) +#define bM4_TMRA2_PCONR2_FORC0 (*((volatile unsigned int*)(0x422AA8A0UL))) +#define bM4_TMRA2_PCONR2_FORC1 (*((volatile unsigned int*)(0x422AA8A4UL))) +#define bM4_TMRA2_PCONR2_OUTEN (*((volatile unsigned int*)(0x422AA8B0UL))) +#define bM4_TMRA2_PCONR3_STAC0 (*((volatile unsigned int*)(0x422AA900UL))) +#define bM4_TMRA2_PCONR3_STAC1 (*((volatile unsigned int*)(0x422AA904UL))) +#define bM4_TMRA2_PCONR3_STPC0 (*((volatile unsigned int*)(0x422AA908UL))) +#define bM4_TMRA2_PCONR3_STPC1 (*((volatile unsigned int*)(0x422AA90CUL))) +#define bM4_TMRA2_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422AA910UL))) +#define bM4_TMRA2_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422AA914UL))) +#define bM4_TMRA2_PCONR3_PERC0 (*((volatile unsigned int*)(0x422AA918UL))) +#define bM4_TMRA2_PCONR3_PERC1 (*((volatile unsigned int*)(0x422AA91CUL))) +#define bM4_TMRA2_PCONR3_FORC0 (*((volatile unsigned int*)(0x422AA920UL))) +#define bM4_TMRA2_PCONR3_FORC1 (*((volatile unsigned int*)(0x422AA924UL))) +#define bM4_TMRA2_PCONR3_OUTEN (*((volatile unsigned int*)(0x422AA930UL))) +#define bM4_TMRA2_PCONR4_STAC0 (*((volatile unsigned int*)(0x422AA980UL))) +#define bM4_TMRA2_PCONR4_STAC1 (*((volatile unsigned int*)(0x422AA984UL))) +#define bM4_TMRA2_PCONR4_STPC0 (*((volatile unsigned int*)(0x422AA988UL))) +#define bM4_TMRA2_PCONR4_STPC1 (*((volatile unsigned int*)(0x422AA98CUL))) +#define bM4_TMRA2_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422AA990UL))) +#define bM4_TMRA2_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422AA994UL))) +#define bM4_TMRA2_PCONR4_PERC0 (*((volatile unsigned int*)(0x422AA998UL))) +#define bM4_TMRA2_PCONR4_PERC1 (*((volatile unsigned int*)(0x422AA99CUL))) +#define bM4_TMRA2_PCONR4_FORC0 (*((volatile unsigned int*)(0x422AA9A0UL))) +#define bM4_TMRA2_PCONR4_FORC1 (*((volatile unsigned int*)(0x422AA9A4UL))) +#define bM4_TMRA2_PCONR4_OUTEN (*((volatile unsigned int*)(0x422AA9B0UL))) +#define bM4_TMRA2_PCONR5_STAC0 (*((volatile unsigned int*)(0x422AAA00UL))) +#define bM4_TMRA2_PCONR5_STAC1 (*((volatile unsigned int*)(0x422AAA04UL))) +#define bM4_TMRA2_PCONR5_STPC0 (*((volatile unsigned int*)(0x422AAA08UL))) +#define bM4_TMRA2_PCONR5_STPC1 (*((volatile unsigned int*)(0x422AAA0CUL))) +#define bM4_TMRA2_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422AAA10UL))) +#define bM4_TMRA2_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422AAA14UL))) +#define bM4_TMRA2_PCONR5_PERC0 (*((volatile unsigned int*)(0x422AAA18UL))) +#define bM4_TMRA2_PCONR5_PERC1 (*((volatile unsigned int*)(0x422AAA1CUL))) +#define bM4_TMRA2_PCONR5_FORC0 (*((volatile unsigned int*)(0x422AAA20UL))) +#define bM4_TMRA2_PCONR5_FORC1 (*((volatile unsigned int*)(0x422AAA24UL))) +#define bM4_TMRA2_PCONR5_OUTEN (*((volatile unsigned int*)(0x422AAA30UL))) +#define bM4_TMRA2_PCONR6_STAC0 (*((volatile unsigned int*)(0x422AAA80UL))) +#define bM4_TMRA2_PCONR6_STAC1 (*((volatile unsigned int*)(0x422AAA84UL))) +#define bM4_TMRA2_PCONR6_STPC0 (*((volatile unsigned int*)(0x422AAA88UL))) +#define bM4_TMRA2_PCONR6_STPC1 (*((volatile unsigned int*)(0x422AAA8CUL))) +#define bM4_TMRA2_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422AAA90UL))) +#define bM4_TMRA2_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422AAA94UL))) +#define bM4_TMRA2_PCONR6_PERC0 (*((volatile unsigned int*)(0x422AAA98UL))) +#define bM4_TMRA2_PCONR6_PERC1 (*((volatile unsigned int*)(0x422AAA9CUL))) +#define bM4_TMRA2_PCONR6_FORC0 (*((volatile unsigned int*)(0x422AAAA0UL))) +#define bM4_TMRA2_PCONR6_FORC1 (*((volatile unsigned int*)(0x422AAAA4UL))) +#define bM4_TMRA2_PCONR6_OUTEN (*((volatile unsigned int*)(0x422AAAB0UL))) +#define bM4_TMRA2_PCONR7_STAC0 (*((volatile unsigned int*)(0x422AAB00UL))) +#define bM4_TMRA2_PCONR7_STAC1 (*((volatile unsigned int*)(0x422AAB04UL))) +#define bM4_TMRA2_PCONR7_STPC0 (*((volatile unsigned int*)(0x422AAB08UL))) +#define bM4_TMRA2_PCONR7_STPC1 (*((volatile unsigned int*)(0x422AAB0CUL))) +#define bM4_TMRA2_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422AAB10UL))) +#define bM4_TMRA2_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422AAB14UL))) +#define bM4_TMRA2_PCONR7_PERC0 (*((volatile unsigned int*)(0x422AAB18UL))) +#define bM4_TMRA2_PCONR7_PERC1 (*((volatile unsigned int*)(0x422AAB1CUL))) +#define bM4_TMRA2_PCONR7_FORC0 (*((volatile unsigned int*)(0x422AAB20UL))) +#define bM4_TMRA2_PCONR7_FORC1 (*((volatile unsigned int*)(0x422AAB24UL))) +#define bM4_TMRA2_PCONR7_OUTEN (*((volatile unsigned int*)(0x422AAB30UL))) +#define bM4_TMRA2_PCONR8_STAC0 (*((volatile unsigned int*)(0x422AAB80UL))) +#define bM4_TMRA2_PCONR8_STAC1 (*((volatile unsigned int*)(0x422AAB84UL))) +#define bM4_TMRA2_PCONR8_STPC0 (*((volatile unsigned int*)(0x422AAB88UL))) +#define bM4_TMRA2_PCONR8_STPC1 (*((volatile unsigned int*)(0x422AAB8CUL))) +#define bM4_TMRA2_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422AAB90UL))) +#define bM4_TMRA2_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422AAB94UL))) +#define bM4_TMRA2_PCONR8_PERC0 (*((volatile unsigned int*)(0x422AAB98UL))) +#define bM4_TMRA2_PCONR8_PERC1 (*((volatile unsigned int*)(0x422AAB9CUL))) +#define bM4_TMRA2_PCONR8_FORC0 (*((volatile unsigned int*)(0x422AABA0UL))) +#define bM4_TMRA2_PCONR8_FORC1 (*((volatile unsigned int*)(0x422AABA4UL))) +#define bM4_TMRA2_PCONR8_OUTEN (*((volatile unsigned int*)(0x422AABB0UL))) +#define bM4_TMRA3_CNTER_CNT0 (*((volatile unsigned int*)(0x422B0000UL))) +#define bM4_TMRA3_CNTER_CNT1 (*((volatile unsigned int*)(0x422B0004UL))) +#define bM4_TMRA3_CNTER_CNT2 (*((volatile unsigned int*)(0x422B0008UL))) +#define bM4_TMRA3_CNTER_CNT3 (*((volatile unsigned int*)(0x422B000CUL))) +#define bM4_TMRA3_CNTER_CNT4 (*((volatile unsigned int*)(0x422B0010UL))) +#define bM4_TMRA3_CNTER_CNT5 (*((volatile unsigned int*)(0x422B0014UL))) +#define bM4_TMRA3_CNTER_CNT6 (*((volatile unsigned int*)(0x422B0018UL))) +#define bM4_TMRA3_CNTER_CNT7 (*((volatile unsigned int*)(0x422B001CUL))) +#define bM4_TMRA3_CNTER_CNT8 (*((volatile unsigned int*)(0x422B0020UL))) +#define bM4_TMRA3_CNTER_CNT9 (*((volatile unsigned int*)(0x422B0024UL))) +#define bM4_TMRA3_CNTER_CNT10 (*((volatile unsigned int*)(0x422B0028UL))) +#define bM4_TMRA3_CNTER_CNT11 (*((volatile unsigned int*)(0x422B002CUL))) +#define bM4_TMRA3_CNTER_CNT12 (*((volatile unsigned int*)(0x422B0030UL))) +#define bM4_TMRA3_CNTER_CNT13 (*((volatile unsigned int*)(0x422B0034UL))) +#define bM4_TMRA3_CNTER_CNT14 (*((volatile unsigned int*)(0x422B0038UL))) +#define bM4_TMRA3_CNTER_CNT15 (*((volatile unsigned int*)(0x422B003CUL))) +#define bM4_TMRA3_PERAR_PER0 (*((volatile unsigned int*)(0x422B0080UL))) +#define bM4_TMRA3_PERAR_PER1 (*((volatile unsigned int*)(0x422B0084UL))) +#define bM4_TMRA3_PERAR_PER2 (*((volatile unsigned int*)(0x422B0088UL))) +#define bM4_TMRA3_PERAR_PER3 (*((volatile unsigned int*)(0x422B008CUL))) +#define bM4_TMRA3_PERAR_PER4 (*((volatile unsigned int*)(0x422B0090UL))) +#define bM4_TMRA3_PERAR_PER5 (*((volatile unsigned int*)(0x422B0094UL))) +#define bM4_TMRA3_PERAR_PER6 (*((volatile unsigned int*)(0x422B0098UL))) +#define bM4_TMRA3_PERAR_PER7 (*((volatile unsigned int*)(0x422B009CUL))) +#define bM4_TMRA3_PERAR_PER8 (*((volatile unsigned int*)(0x422B00A0UL))) +#define bM4_TMRA3_PERAR_PER9 (*((volatile unsigned int*)(0x422B00A4UL))) +#define bM4_TMRA3_PERAR_PER10 (*((volatile unsigned int*)(0x422B00A8UL))) +#define bM4_TMRA3_PERAR_PER11 (*((volatile unsigned int*)(0x422B00ACUL))) +#define bM4_TMRA3_PERAR_PER12 (*((volatile unsigned int*)(0x422B00B0UL))) +#define bM4_TMRA3_PERAR_PER13 (*((volatile unsigned int*)(0x422B00B4UL))) +#define bM4_TMRA3_PERAR_PER14 (*((volatile unsigned int*)(0x422B00B8UL))) +#define bM4_TMRA3_PERAR_PER15 (*((volatile unsigned int*)(0x422B00BCUL))) +#define bM4_TMRA3_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422B0800UL))) +#define bM4_TMRA3_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422B0804UL))) +#define bM4_TMRA3_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422B0808UL))) +#define bM4_TMRA3_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422B080CUL))) +#define bM4_TMRA3_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422B0810UL))) +#define bM4_TMRA3_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422B0814UL))) +#define bM4_TMRA3_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422B0818UL))) +#define bM4_TMRA3_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422B081CUL))) +#define bM4_TMRA3_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422B0820UL))) +#define bM4_TMRA3_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422B0824UL))) +#define bM4_TMRA3_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422B0828UL))) +#define bM4_TMRA3_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422B082CUL))) +#define bM4_TMRA3_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422B0830UL))) +#define bM4_TMRA3_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422B0834UL))) +#define bM4_TMRA3_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422B0838UL))) +#define bM4_TMRA3_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422B083CUL))) +#define bM4_TMRA3_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422B0880UL))) +#define bM4_TMRA3_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422B0884UL))) +#define bM4_TMRA3_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422B0888UL))) +#define bM4_TMRA3_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422B088CUL))) +#define bM4_TMRA3_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422B0890UL))) +#define bM4_TMRA3_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422B0894UL))) +#define bM4_TMRA3_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422B0898UL))) +#define bM4_TMRA3_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422B089CUL))) +#define bM4_TMRA3_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422B08A0UL))) +#define bM4_TMRA3_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422B08A4UL))) +#define bM4_TMRA3_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422B08A8UL))) +#define bM4_TMRA3_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422B08ACUL))) +#define bM4_TMRA3_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422B08B0UL))) +#define bM4_TMRA3_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422B08B4UL))) +#define bM4_TMRA3_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422B08B8UL))) +#define bM4_TMRA3_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422B08BCUL))) +#define bM4_TMRA3_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422B0900UL))) +#define bM4_TMRA3_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422B0904UL))) +#define bM4_TMRA3_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422B0908UL))) +#define bM4_TMRA3_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422B090CUL))) +#define bM4_TMRA3_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422B0910UL))) +#define bM4_TMRA3_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422B0914UL))) +#define bM4_TMRA3_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422B0918UL))) +#define bM4_TMRA3_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422B091CUL))) +#define bM4_TMRA3_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422B0920UL))) +#define bM4_TMRA3_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422B0924UL))) +#define bM4_TMRA3_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422B0928UL))) +#define bM4_TMRA3_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422B092CUL))) +#define bM4_TMRA3_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422B0930UL))) +#define bM4_TMRA3_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422B0934UL))) +#define bM4_TMRA3_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422B0938UL))) +#define bM4_TMRA3_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422B093CUL))) +#define bM4_TMRA3_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422B0980UL))) +#define bM4_TMRA3_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422B0984UL))) +#define bM4_TMRA3_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422B0988UL))) +#define bM4_TMRA3_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422B098CUL))) +#define bM4_TMRA3_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422B0990UL))) +#define bM4_TMRA3_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422B0994UL))) +#define bM4_TMRA3_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422B0998UL))) +#define bM4_TMRA3_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422B099CUL))) +#define bM4_TMRA3_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422B09A0UL))) +#define bM4_TMRA3_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422B09A4UL))) +#define bM4_TMRA3_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422B09A8UL))) +#define bM4_TMRA3_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422B09ACUL))) +#define bM4_TMRA3_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422B09B0UL))) +#define bM4_TMRA3_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422B09B4UL))) +#define bM4_TMRA3_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422B09B8UL))) +#define bM4_TMRA3_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422B09BCUL))) +#define bM4_TMRA3_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422B0A00UL))) +#define bM4_TMRA3_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422B0A04UL))) +#define bM4_TMRA3_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422B0A08UL))) +#define bM4_TMRA3_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422B0A0CUL))) +#define bM4_TMRA3_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422B0A10UL))) +#define bM4_TMRA3_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422B0A14UL))) +#define bM4_TMRA3_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422B0A18UL))) +#define bM4_TMRA3_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422B0A1CUL))) +#define bM4_TMRA3_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422B0A20UL))) +#define bM4_TMRA3_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422B0A24UL))) +#define bM4_TMRA3_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422B0A28UL))) +#define bM4_TMRA3_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422B0A2CUL))) +#define bM4_TMRA3_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422B0A30UL))) +#define bM4_TMRA3_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422B0A34UL))) +#define bM4_TMRA3_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422B0A38UL))) +#define bM4_TMRA3_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422B0A3CUL))) +#define bM4_TMRA3_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422B0A80UL))) +#define bM4_TMRA3_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422B0A84UL))) +#define bM4_TMRA3_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422B0A88UL))) +#define bM4_TMRA3_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422B0A8CUL))) +#define bM4_TMRA3_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422B0A90UL))) +#define bM4_TMRA3_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422B0A94UL))) +#define bM4_TMRA3_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422B0A98UL))) +#define bM4_TMRA3_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422B0A9CUL))) +#define bM4_TMRA3_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422B0AA0UL))) +#define bM4_TMRA3_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422B0AA4UL))) +#define bM4_TMRA3_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422B0AA8UL))) +#define bM4_TMRA3_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422B0AACUL))) +#define bM4_TMRA3_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422B0AB0UL))) +#define bM4_TMRA3_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422B0AB4UL))) +#define bM4_TMRA3_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422B0AB8UL))) +#define bM4_TMRA3_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422B0ABCUL))) +#define bM4_TMRA3_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422B0B00UL))) +#define bM4_TMRA3_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422B0B04UL))) +#define bM4_TMRA3_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422B0B08UL))) +#define bM4_TMRA3_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422B0B0CUL))) +#define bM4_TMRA3_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422B0B10UL))) +#define bM4_TMRA3_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422B0B14UL))) +#define bM4_TMRA3_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422B0B18UL))) +#define bM4_TMRA3_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422B0B1CUL))) +#define bM4_TMRA3_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422B0B20UL))) +#define bM4_TMRA3_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422B0B24UL))) +#define bM4_TMRA3_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422B0B28UL))) +#define bM4_TMRA3_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422B0B2CUL))) +#define bM4_TMRA3_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422B0B30UL))) +#define bM4_TMRA3_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422B0B34UL))) +#define bM4_TMRA3_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422B0B38UL))) +#define bM4_TMRA3_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422B0B3CUL))) +#define bM4_TMRA3_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422B0B80UL))) +#define bM4_TMRA3_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422B0B84UL))) +#define bM4_TMRA3_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422B0B88UL))) +#define bM4_TMRA3_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422B0B8CUL))) +#define bM4_TMRA3_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422B0B90UL))) +#define bM4_TMRA3_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422B0B94UL))) +#define bM4_TMRA3_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422B0B98UL))) +#define bM4_TMRA3_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422B0B9CUL))) +#define bM4_TMRA3_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422B0BA0UL))) +#define bM4_TMRA3_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422B0BA4UL))) +#define bM4_TMRA3_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422B0BA8UL))) +#define bM4_TMRA3_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422B0BACUL))) +#define bM4_TMRA3_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422B0BB0UL))) +#define bM4_TMRA3_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422B0BB4UL))) +#define bM4_TMRA3_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422B0BB8UL))) +#define bM4_TMRA3_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422B0BBCUL))) +#define bM4_TMRA3_BCSTR_START (*((volatile unsigned int*)(0x422B1000UL))) +#define bM4_TMRA3_BCSTR_DIR (*((volatile unsigned int*)(0x422B1004UL))) +#define bM4_TMRA3_BCSTR_MODE (*((volatile unsigned int*)(0x422B1008UL))) +#define bM4_TMRA3_BCSTR_SYNST (*((volatile unsigned int*)(0x422B100CUL))) +#define bM4_TMRA3_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422B1010UL))) +#define bM4_TMRA3_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422B1014UL))) +#define bM4_TMRA3_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422B1018UL))) +#define bM4_TMRA3_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422B101CUL))) +#define bM4_TMRA3_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422B1030UL))) +#define bM4_TMRA3_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422B1034UL))) +#define bM4_TMRA3_BCSTR_OVFF (*((volatile unsigned int*)(0x422B1038UL))) +#define bM4_TMRA3_BCSTR_UDFF (*((volatile unsigned int*)(0x422B103CUL))) +#define bM4_TMRA3_HCONR_HSTA0 (*((volatile unsigned int*)(0x422B1080UL))) +#define bM4_TMRA3_HCONR_HSTA1 (*((volatile unsigned int*)(0x422B1084UL))) +#define bM4_TMRA3_HCONR_HSTA2 (*((volatile unsigned int*)(0x422B1088UL))) +#define bM4_TMRA3_HCONR_HSTP0 (*((volatile unsigned int*)(0x422B1090UL))) +#define bM4_TMRA3_HCONR_HSTP1 (*((volatile unsigned int*)(0x422B1094UL))) +#define bM4_TMRA3_HCONR_HSTP2 (*((volatile unsigned int*)(0x422B1098UL))) +#define bM4_TMRA3_HCONR_HCLE0 (*((volatile unsigned int*)(0x422B10A0UL))) +#define bM4_TMRA3_HCONR_HCLE1 (*((volatile unsigned int*)(0x422B10A4UL))) +#define bM4_TMRA3_HCONR_HCLE2 (*((volatile unsigned int*)(0x422B10A8UL))) +#define bM4_TMRA3_HCONR_HCLE3 (*((volatile unsigned int*)(0x422B10B0UL))) +#define bM4_TMRA3_HCONR_HCLE4 (*((volatile unsigned int*)(0x422B10B4UL))) +#define bM4_TMRA3_HCONR_HCLE5 (*((volatile unsigned int*)(0x422B10B8UL))) +#define bM4_TMRA3_HCONR_HCLE6 (*((volatile unsigned int*)(0x422B10BCUL))) +#define bM4_TMRA3_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422B1100UL))) +#define bM4_TMRA3_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422B1104UL))) +#define bM4_TMRA3_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422B1108UL))) +#define bM4_TMRA3_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422B110CUL))) +#define bM4_TMRA3_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422B1110UL))) +#define bM4_TMRA3_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422B1114UL))) +#define bM4_TMRA3_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422B1118UL))) +#define bM4_TMRA3_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422B111CUL))) +#define bM4_TMRA3_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422B1120UL))) +#define bM4_TMRA3_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422B1124UL))) +#define bM4_TMRA3_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422B1128UL))) +#define bM4_TMRA3_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422B112CUL))) +#define bM4_TMRA3_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422B1130UL))) +#define bM4_TMRA3_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422B1180UL))) +#define bM4_TMRA3_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422B1184UL))) +#define bM4_TMRA3_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422B1188UL))) +#define bM4_TMRA3_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422B118CUL))) +#define bM4_TMRA3_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422B1190UL))) +#define bM4_TMRA3_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422B1194UL))) +#define bM4_TMRA3_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422B1198UL))) +#define bM4_TMRA3_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422B119CUL))) +#define bM4_TMRA3_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422B11A0UL))) +#define bM4_TMRA3_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422B11A4UL))) +#define bM4_TMRA3_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422B11A8UL))) +#define bM4_TMRA3_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422B11ACUL))) +#define bM4_TMRA3_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422B11B0UL))) +#define bM4_TMRA3_ICONR_ITEN1 (*((volatile unsigned int*)(0x422B1200UL))) +#define bM4_TMRA3_ICONR_ITEN2 (*((volatile unsigned int*)(0x422B1204UL))) +#define bM4_TMRA3_ICONR_ITEN3 (*((volatile unsigned int*)(0x422B1208UL))) +#define bM4_TMRA3_ICONR_ITEN4 (*((volatile unsigned int*)(0x422B120CUL))) +#define bM4_TMRA3_ICONR_ITEN5 (*((volatile unsigned int*)(0x422B1210UL))) +#define bM4_TMRA3_ICONR_ITEN6 (*((volatile unsigned int*)(0x422B1214UL))) +#define bM4_TMRA3_ICONR_ITEN7 (*((volatile unsigned int*)(0x422B1218UL))) +#define bM4_TMRA3_ICONR_ITEN8 (*((volatile unsigned int*)(0x422B121CUL))) +#define bM4_TMRA3_ECONR_ETEN1 (*((volatile unsigned int*)(0x422B1280UL))) +#define bM4_TMRA3_ECONR_ETEN2 (*((volatile unsigned int*)(0x422B1284UL))) +#define bM4_TMRA3_ECONR_ETEN3 (*((volatile unsigned int*)(0x422B1288UL))) +#define bM4_TMRA3_ECONR_ETEN4 (*((volatile unsigned int*)(0x422B128CUL))) +#define bM4_TMRA3_ECONR_ETEN5 (*((volatile unsigned int*)(0x422B1290UL))) +#define bM4_TMRA3_ECONR_ETEN6 (*((volatile unsigned int*)(0x422B1294UL))) +#define bM4_TMRA3_ECONR_ETEN7 (*((volatile unsigned int*)(0x422B1298UL))) +#define bM4_TMRA3_ECONR_ETEN8 (*((volatile unsigned int*)(0x422B129CUL))) +#define bM4_TMRA3_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422B1300UL))) +#define bM4_TMRA3_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422B1304UL))) +#define bM4_TMRA3_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422B1308UL))) +#define bM4_TMRA3_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422B1320UL))) +#define bM4_TMRA3_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422B1324UL))) +#define bM4_TMRA3_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422B1328UL))) +#define bM4_TMRA3_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422B1330UL))) +#define bM4_TMRA3_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422B1334UL))) +#define bM4_TMRA3_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422B1338UL))) +#define bM4_TMRA3_STFLR_CMPF1 (*((volatile unsigned int*)(0x422B1380UL))) +#define bM4_TMRA3_STFLR_CMPF2 (*((volatile unsigned int*)(0x422B1384UL))) +#define bM4_TMRA3_STFLR_CMPF3 (*((volatile unsigned int*)(0x422B1388UL))) +#define bM4_TMRA3_STFLR_CMPF4 (*((volatile unsigned int*)(0x422B138CUL))) +#define bM4_TMRA3_STFLR_CMPF5 (*((volatile unsigned int*)(0x422B1390UL))) +#define bM4_TMRA3_STFLR_CMPF6 (*((volatile unsigned int*)(0x422B1394UL))) +#define bM4_TMRA3_STFLR_CMPF7 (*((volatile unsigned int*)(0x422B1398UL))) +#define bM4_TMRA3_STFLR_CMPF8 (*((volatile unsigned int*)(0x422B139CUL))) +#define bM4_TMRA3_BCONR1_BEN (*((volatile unsigned int*)(0x422B1800UL))) +#define bM4_TMRA3_BCONR1_BSE0 (*((volatile unsigned int*)(0x422B1804UL))) +#define bM4_TMRA3_BCONR1_BSE1 (*((volatile unsigned int*)(0x422B1808UL))) +#define bM4_TMRA3_BCONR2_BEN (*((volatile unsigned int*)(0x422B1900UL))) +#define bM4_TMRA3_BCONR2_BSE0 (*((volatile unsigned int*)(0x422B1904UL))) +#define bM4_TMRA3_BCONR2_BSE1 (*((volatile unsigned int*)(0x422B1908UL))) +#define bM4_TMRA3_BCONR3_BEN (*((volatile unsigned int*)(0x422B1A00UL))) +#define bM4_TMRA3_BCONR3_BSE0 (*((volatile unsigned int*)(0x422B1A04UL))) +#define bM4_TMRA3_BCONR3_BSE1 (*((volatile unsigned int*)(0x422B1A08UL))) +#define bM4_TMRA3_BCONR4_BEN (*((volatile unsigned int*)(0x422B1B00UL))) +#define bM4_TMRA3_BCONR4_BSE0 (*((volatile unsigned int*)(0x422B1B04UL))) +#define bM4_TMRA3_BCONR4_BSE1 (*((volatile unsigned int*)(0x422B1B08UL))) +#define bM4_TMRA3_CCONR1_CAPMD (*((volatile unsigned int*)(0x422B2000UL))) +#define bM4_TMRA3_CCONR1_HICP0 (*((volatile unsigned int*)(0x422B2010UL))) +#define bM4_TMRA3_CCONR1_HICP1 (*((volatile unsigned int*)(0x422B2014UL))) +#define bM4_TMRA3_CCONR1_HICP2 (*((volatile unsigned int*)(0x422B2018UL))) +#define bM4_TMRA3_CCONR1_HICP3 (*((volatile unsigned int*)(0x422B2020UL))) +#define bM4_TMRA3_CCONR1_HICP4 (*((volatile unsigned int*)(0x422B2024UL))) +#define bM4_TMRA3_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422B2030UL))) +#define bM4_TMRA3_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422B2034UL))) +#define bM4_TMRA3_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422B2038UL))) +#define bM4_TMRA3_CCONR2_CAPMD (*((volatile unsigned int*)(0x422B2080UL))) +#define bM4_TMRA3_CCONR2_HICP0 (*((volatile unsigned int*)(0x422B2090UL))) +#define bM4_TMRA3_CCONR2_HICP1 (*((volatile unsigned int*)(0x422B2094UL))) +#define bM4_TMRA3_CCONR2_HICP2 (*((volatile unsigned int*)(0x422B2098UL))) +#define bM4_TMRA3_CCONR2_HICP3 (*((volatile unsigned int*)(0x422B20A0UL))) +#define bM4_TMRA3_CCONR2_HICP4 (*((volatile unsigned int*)(0x422B20A4UL))) +#define bM4_TMRA3_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422B20B0UL))) +#define bM4_TMRA3_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422B20B4UL))) +#define bM4_TMRA3_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422B20B8UL))) +#define bM4_TMRA3_CCONR3_CAPMD (*((volatile unsigned int*)(0x422B2100UL))) +#define bM4_TMRA3_CCONR3_HICP0 (*((volatile unsigned int*)(0x422B2110UL))) +#define bM4_TMRA3_CCONR3_HICP1 (*((volatile unsigned int*)(0x422B2114UL))) +#define bM4_TMRA3_CCONR3_HICP2 (*((volatile unsigned int*)(0x422B2118UL))) +#define bM4_TMRA3_CCONR3_HICP3 (*((volatile unsigned int*)(0x422B2120UL))) +#define bM4_TMRA3_CCONR3_HICP4 (*((volatile unsigned int*)(0x422B2124UL))) +#define bM4_TMRA3_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422B2130UL))) +#define bM4_TMRA3_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422B2134UL))) +#define bM4_TMRA3_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422B2138UL))) +#define bM4_TMRA3_CCONR4_CAPMD (*((volatile unsigned int*)(0x422B2180UL))) +#define bM4_TMRA3_CCONR4_HICP0 (*((volatile unsigned int*)(0x422B2190UL))) +#define bM4_TMRA3_CCONR4_HICP1 (*((volatile unsigned int*)(0x422B2194UL))) +#define bM4_TMRA3_CCONR4_HICP2 (*((volatile unsigned int*)(0x422B2198UL))) +#define bM4_TMRA3_CCONR4_HICP3 (*((volatile unsigned int*)(0x422B21A0UL))) +#define bM4_TMRA3_CCONR4_HICP4 (*((volatile unsigned int*)(0x422B21A4UL))) +#define bM4_TMRA3_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422B21B0UL))) +#define bM4_TMRA3_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422B21B4UL))) +#define bM4_TMRA3_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422B21B8UL))) +#define bM4_TMRA3_CCONR5_CAPMD (*((volatile unsigned int*)(0x422B2200UL))) +#define bM4_TMRA3_CCONR5_HICP0 (*((volatile unsigned int*)(0x422B2210UL))) +#define bM4_TMRA3_CCONR5_HICP1 (*((volatile unsigned int*)(0x422B2214UL))) +#define bM4_TMRA3_CCONR5_HICP2 (*((volatile unsigned int*)(0x422B2218UL))) +#define bM4_TMRA3_CCONR5_HICP3 (*((volatile unsigned int*)(0x422B2220UL))) +#define bM4_TMRA3_CCONR5_HICP4 (*((volatile unsigned int*)(0x422B2224UL))) +#define bM4_TMRA3_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422B2230UL))) +#define bM4_TMRA3_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422B2234UL))) +#define bM4_TMRA3_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422B2238UL))) +#define bM4_TMRA3_CCONR6_CAPMD (*((volatile unsigned int*)(0x422B2280UL))) +#define bM4_TMRA3_CCONR6_HICP0 (*((volatile unsigned int*)(0x422B2290UL))) +#define bM4_TMRA3_CCONR6_HICP1 (*((volatile unsigned int*)(0x422B2294UL))) +#define bM4_TMRA3_CCONR6_HICP2 (*((volatile unsigned int*)(0x422B2298UL))) +#define bM4_TMRA3_CCONR6_HICP3 (*((volatile unsigned int*)(0x422B22A0UL))) +#define bM4_TMRA3_CCONR6_HICP4 (*((volatile unsigned int*)(0x422B22A4UL))) +#define bM4_TMRA3_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422B22B0UL))) +#define bM4_TMRA3_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422B22B4UL))) +#define bM4_TMRA3_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422B22B8UL))) +#define bM4_TMRA3_CCONR7_CAPMD (*((volatile unsigned int*)(0x422B2300UL))) +#define bM4_TMRA3_CCONR7_HICP0 (*((volatile unsigned int*)(0x422B2310UL))) +#define bM4_TMRA3_CCONR7_HICP1 (*((volatile unsigned int*)(0x422B2314UL))) +#define bM4_TMRA3_CCONR7_HICP2 (*((volatile unsigned int*)(0x422B2318UL))) +#define bM4_TMRA3_CCONR7_HICP3 (*((volatile unsigned int*)(0x422B2320UL))) +#define bM4_TMRA3_CCONR7_HICP4 (*((volatile unsigned int*)(0x422B2324UL))) +#define bM4_TMRA3_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422B2330UL))) +#define bM4_TMRA3_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422B2334UL))) +#define bM4_TMRA3_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422B2338UL))) +#define bM4_TMRA3_CCONR8_CAPMD (*((volatile unsigned int*)(0x422B2380UL))) +#define bM4_TMRA3_CCONR8_HICP0 (*((volatile unsigned int*)(0x422B2390UL))) +#define bM4_TMRA3_CCONR8_HICP1 (*((volatile unsigned int*)(0x422B2394UL))) +#define bM4_TMRA3_CCONR8_HICP2 (*((volatile unsigned int*)(0x422B2398UL))) +#define bM4_TMRA3_CCONR8_HICP3 (*((volatile unsigned int*)(0x422B23A0UL))) +#define bM4_TMRA3_CCONR8_HICP4 (*((volatile unsigned int*)(0x422B23A4UL))) +#define bM4_TMRA3_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422B23B0UL))) +#define bM4_TMRA3_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422B23B4UL))) +#define bM4_TMRA3_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422B23B8UL))) +#define bM4_TMRA3_PCONR1_STAC0 (*((volatile unsigned int*)(0x422B2800UL))) +#define bM4_TMRA3_PCONR1_STAC1 (*((volatile unsigned int*)(0x422B2804UL))) +#define bM4_TMRA3_PCONR1_STPC0 (*((volatile unsigned int*)(0x422B2808UL))) +#define bM4_TMRA3_PCONR1_STPC1 (*((volatile unsigned int*)(0x422B280CUL))) +#define bM4_TMRA3_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422B2810UL))) +#define bM4_TMRA3_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422B2814UL))) +#define bM4_TMRA3_PCONR1_PERC0 (*((volatile unsigned int*)(0x422B2818UL))) +#define bM4_TMRA3_PCONR1_PERC1 (*((volatile unsigned int*)(0x422B281CUL))) +#define bM4_TMRA3_PCONR1_FORC0 (*((volatile unsigned int*)(0x422B2820UL))) +#define bM4_TMRA3_PCONR1_FORC1 (*((volatile unsigned int*)(0x422B2824UL))) +#define bM4_TMRA3_PCONR1_OUTEN (*((volatile unsigned int*)(0x422B2830UL))) +#define bM4_TMRA3_PCONR2_STAC0 (*((volatile unsigned int*)(0x422B2880UL))) +#define bM4_TMRA3_PCONR2_STAC1 (*((volatile unsigned int*)(0x422B2884UL))) +#define bM4_TMRA3_PCONR2_STPC0 (*((volatile unsigned int*)(0x422B2888UL))) +#define bM4_TMRA3_PCONR2_STPC1 (*((volatile unsigned int*)(0x422B288CUL))) +#define bM4_TMRA3_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422B2890UL))) +#define bM4_TMRA3_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422B2894UL))) +#define bM4_TMRA3_PCONR2_PERC0 (*((volatile unsigned int*)(0x422B2898UL))) +#define bM4_TMRA3_PCONR2_PERC1 (*((volatile unsigned int*)(0x422B289CUL))) +#define bM4_TMRA3_PCONR2_FORC0 (*((volatile unsigned int*)(0x422B28A0UL))) +#define bM4_TMRA3_PCONR2_FORC1 (*((volatile unsigned int*)(0x422B28A4UL))) +#define bM4_TMRA3_PCONR2_OUTEN (*((volatile unsigned int*)(0x422B28B0UL))) +#define bM4_TMRA3_PCONR3_STAC0 (*((volatile unsigned int*)(0x422B2900UL))) +#define bM4_TMRA3_PCONR3_STAC1 (*((volatile unsigned int*)(0x422B2904UL))) +#define bM4_TMRA3_PCONR3_STPC0 (*((volatile unsigned int*)(0x422B2908UL))) +#define bM4_TMRA3_PCONR3_STPC1 (*((volatile unsigned int*)(0x422B290CUL))) +#define bM4_TMRA3_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422B2910UL))) +#define bM4_TMRA3_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422B2914UL))) +#define bM4_TMRA3_PCONR3_PERC0 (*((volatile unsigned int*)(0x422B2918UL))) +#define bM4_TMRA3_PCONR3_PERC1 (*((volatile unsigned int*)(0x422B291CUL))) +#define bM4_TMRA3_PCONR3_FORC0 (*((volatile unsigned int*)(0x422B2920UL))) +#define bM4_TMRA3_PCONR3_FORC1 (*((volatile unsigned int*)(0x422B2924UL))) +#define bM4_TMRA3_PCONR3_OUTEN (*((volatile unsigned int*)(0x422B2930UL))) +#define bM4_TMRA3_PCONR4_STAC0 (*((volatile unsigned int*)(0x422B2980UL))) +#define bM4_TMRA3_PCONR4_STAC1 (*((volatile unsigned int*)(0x422B2984UL))) +#define bM4_TMRA3_PCONR4_STPC0 (*((volatile unsigned int*)(0x422B2988UL))) +#define bM4_TMRA3_PCONR4_STPC1 (*((volatile unsigned int*)(0x422B298CUL))) +#define bM4_TMRA3_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422B2990UL))) +#define bM4_TMRA3_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422B2994UL))) +#define bM4_TMRA3_PCONR4_PERC0 (*((volatile unsigned int*)(0x422B2998UL))) +#define bM4_TMRA3_PCONR4_PERC1 (*((volatile unsigned int*)(0x422B299CUL))) +#define bM4_TMRA3_PCONR4_FORC0 (*((volatile unsigned int*)(0x422B29A0UL))) +#define bM4_TMRA3_PCONR4_FORC1 (*((volatile unsigned int*)(0x422B29A4UL))) +#define bM4_TMRA3_PCONR4_OUTEN (*((volatile unsigned int*)(0x422B29B0UL))) +#define bM4_TMRA3_PCONR5_STAC0 (*((volatile unsigned int*)(0x422B2A00UL))) +#define bM4_TMRA3_PCONR5_STAC1 (*((volatile unsigned int*)(0x422B2A04UL))) +#define bM4_TMRA3_PCONR5_STPC0 (*((volatile unsigned int*)(0x422B2A08UL))) +#define bM4_TMRA3_PCONR5_STPC1 (*((volatile unsigned int*)(0x422B2A0CUL))) +#define bM4_TMRA3_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422B2A10UL))) +#define bM4_TMRA3_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422B2A14UL))) +#define bM4_TMRA3_PCONR5_PERC0 (*((volatile unsigned int*)(0x422B2A18UL))) +#define bM4_TMRA3_PCONR5_PERC1 (*((volatile unsigned int*)(0x422B2A1CUL))) +#define bM4_TMRA3_PCONR5_FORC0 (*((volatile unsigned int*)(0x422B2A20UL))) +#define bM4_TMRA3_PCONR5_FORC1 (*((volatile unsigned int*)(0x422B2A24UL))) +#define bM4_TMRA3_PCONR5_OUTEN (*((volatile unsigned int*)(0x422B2A30UL))) +#define bM4_TMRA3_PCONR6_STAC0 (*((volatile unsigned int*)(0x422B2A80UL))) +#define bM4_TMRA3_PCONR6_STAC1 (*((volatile unsigned int*)(0x422B2A84UL))) +#define bM4_TMRA3_PCONR6_STPC0 (*((volatile unsigned int*)(0x422B2A88UL))) +#define bM4_TMRA3_PCONR6_STPC1 (*((volatile unsigned int*)(0x422B2A8CUL))) +#define bM4_TMRA3_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422B2A90UL))) +#define bM4_TMRA3_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422B2A94UL))) +#define bM4_TMRA3_PCONR6_PERC0 (*((volatile unsigned int*)(0x422B2A98UL))) +#define bM4_TMRA3_PCONR6_PERC1 (*((volatile unsigned int*)(0x422B2A9CUL))) +#define bM4_TMRA3_PCONR6_FORC0 (*((volatile unsigned int*)(0x422B2AA0UL))) +#define bM4_TMRA3_PCONR6_FORC1 (*((volatile unsigned int*)(0x422B2AA4UL))) +#define bM4_TMRA3_PCONR6_OUTEN (*((volatile unsigned int*)(0x422B2AB0UL))) +#define bM4_TMRA3_PCONR7_STAC0 (*((volatile unsigned int*)(0x422B2B00UL))) +#define bM4_TMRA3_PCONR7_STAC1 (*((volatile unsigned int*)(0x422B2B04UL))) +#define bM4_TMRA3_PCONR7_STPC0 (*((volatile unsigned int*)(0x422B2B08UL))) +#define bM4_TMRA3_PCONR7_STPC1 (*((volatile unsigned int*)(0x422B2B0CUL))) +#define bM4_TMRA3_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422B2B10UL))) +#define bM4_TMRA3_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422B2B14UL))) +#define bM4_TMRA3_PCONR7_PERC0 (*((volatile unsigned int*)(0x422B2B18UL))) +#define bM4_TMRA3_PCONR7_PERC1 (*((volatile unsigned int*)(0x422B2B1CUL))) +#define bM4_TMRA3_PCONR7_FORC0 (*((volatile unsigned int*)(0x422B2B20UL))) +#define bM4_TMRA3_PCONR7_FORC1 (*((volatile unsigned int*)(0x422B2B24UL))) +#define bM4_TMRA3_PCONR7_OUTEN (*((volatile unsigned int*)(0x422B2B30UL))) +#define bM4_TMRA3_PCONR8_STAC0 (*((volatile unsigned int*)(0x422B2B80UL))) +#define bM4_TMRA3_PCONR8_STAC1 (*((volatile unsigned int*)(0x422B2B84UL))) +#define bM4_TMRA3_PCONR8_STPC0 (*((volatile unsigned int*)(0x422B2B88UL))) +#define bM4_TMRA3_PCONR8_STPC1 (*((volatile unsigned int*)(0x422B2B8CUL))) +#define bM4_TMRA3_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422B2B90UL))) +#define bM4_TMRA3_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422B2B94UL))) +#define bM4_TMRA3_PCONR8_PERC0 (*((volatile unsigned int*)(0x422B2B98UL))) +#define bM4_TMRA3_PCONR8_PERC1 (*((volatile unsigned int*)(0x422B2B9CUL))) +#define bM4_TMRA3_PCONR8_FORC0 (*((volatile unsigned int*)(0x422B2BA0UL))) +#define bM4_TMRA3_PCONR8_FORC1 (*((volatile unsigned int*)(0x422B2BA4UL))) +#define bM4_TMRA3_PCONR8_OUTEN (*((volatile unsigned int*)(0x422B2BB0UL))) +#define bM4_TMRA4_CNTER_CNT0 (*((volatile unsigned int*)(0x422B8000UL))) +#define bM4_TMRA4_CNTER_CNT1 (*((volatile unsigned int*)(0x422B8004UL))) +#define bM4_TMRA4_CNTER_CNT2 (*((volatile unsigned int*)(0x422B8008UL))) +#define bM4_TMRA4_CNTER_CNT3 (*((volatile unsigned int*)(0x422B800CUL))) +#define bM4_TMRA4_CNTER_CNT4 (*((volatile unsigned int*)(0x422B8010UL))) +#define bM4_TMRA4_CNTER_CNT5 (*((volatile unsigned int*)(0x422B8014UL))) +#define bM4_TMRA4_CNTER_CNT6 (*((volatile unsigned int*)(0x422B8018UL))) +#define bM4_TMRA4_CNTER_CNT7 (*((volatile unsigned int*)(0x422B801CUL))) +#define bM4_TMRA4_CNTER_CNT8 (*((volatile unsigned int*)(0x422B8020UL))) +#define bM4_TMRA4_CNTER_CNT9 (*((volatile unsigned int*)(0x422B8024UL))) +#define bM4_TMRA4_CNTER_CNT10 (*((volatile unsigned int*)(0x422B8028UL))) +#define bM4_TMRA4_CNTER_CNT11 (*((volatile unsigned int*)(0x422B802CUL))) +#define bM4_TMRA4_CNTER_CNT12 (*((volatile unsigned int*)(0x422B8030UL))) +#define bM4_TMRA4_CNTER_CNT13 (*((volatile unsigned int*)(0x422B8034UL))) +#define bM4_TMRA4_CNTER_CNT14 (*((volatile unsigned int*)(0x422B8038UL))) +#define bM4_TMRA4_CNTER_CNT15 (*((volatile unsigned int*)(0x422B803CUL))) +#define bM4_TMRA4_PERAR_PER0 (*((volatile unsigned int*)(0x422B8080UL))) +#define bM4_TMRA4_PERAR_PER1 (*((volatile unsigned int*)(0x422B8084UL))) +#define bM4_TMRA4_PERAR_PER2 (*((volatile unsigned int*)(0x422B8088UL))) +#define bM4_TMRA4_PERAR_PER3 (*((volatile unsigned int*)(0x422B808CUL))) +#define bM4_TMRA4_PERAR_PER4 (*((volatile unsigned int*)(0x422B8090UL))) +#define bM4_TMRA4_PERAR_PER5 (*((volatile unsigned int*)(0x422B8094UL))) +#define bM4_TMRA4_PERAR_PER6 (*((volatile unsigned int*)(0x422B8098UL))) +#define bM4_TMRA4_PERAR_PER7 (*((volatile unsigned int*)(0x422B809CUL))) +#define bM4_TMRA4_PERAR_PER8 (*((volatile unsigned int*)(0x422B80A0UL))) +#define bM4_TMRA4_PERAR_PER9 (*((volatile unsigned int*)(0x422B80A4UL))) +#define bM4_TMRA4_PERAR_PER10 (*((volatile unsigned int*)(0x422B80A8UL))) +#define bM4_TMRA4_PERAR_PER11 (*((volatile unsigned int*)(0x422B80ACUL))) +#define bM4_TMRA4_PERAR_PER12 (*((volatile unsigned int*)(0x422B80B0UL))) +#define bM4_TMRA4_PERAR_PER13 (*((volatile unsigned int*)(0x422B80B4UL))) +#define bM4_TMRA4_PERAR_PER14 (*((volatile unsigned int*)(0x422B80B8UL))) +#define bM4_TMRA4_PERAR_PER15 (*((volatile unsigned int*)(0x422B80BCUL))) +#define bM4_TMRA4_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422B8800UL))) +#define bM4_TMRA4_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422B8804UL))) +#define bM4_TMRA4_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422B8808UL))) +#define bM4_TMRA4_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422B880CUL))) +#define bM4_TMRA4_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422B8810UL))) +#define bM4_TMRA4_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422B8814UL))) +#define bM4_TMRA4_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422B8818UL))) +#define bM4_TMRA4_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422B881CUL))) +#define bM4_TMRA4_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422B8820UL))) +#define bM4_TMRA4_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422B8824UL))) +#define bM4_TMRA4_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422B8828UL))) +#define bM4_TMRA4_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422B882CUL))) +#define bM4_TMRA4_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422B8830UL))) +#define bM4_TMRA4_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422B8834UL))) +#define bM4_TMRA4_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422B8838UL))) +#define bM4_TMRA4_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422B883CUL))) +#define bM4_TMRA4_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422B8880UL))) +#define bM4_TMRA4_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422B8884UL))) +#define bM4_TMRA4_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422B8888UL))) +#define bM4_TMRA4_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422B888CUL))) +#define bM4_TMRA4_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422B8890UL))) +#define bM4_TMRA4_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422B8894UL))) +#define bM4_TMRA4_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422B8898UL))) +#define bM4_TMRA4_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422B889CUL))) +#define bM4_TMRA4_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422B88A0UL))) +#define bM4_TMRA4_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422B88A4UL))) +#define bM4_TMRA4_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422B88A8UL))) +#define bM4_TMRA4_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422B88ACUL))) +#define bM4_TMRA4_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422B88B0UL))) +#define bM4_TMRA4_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422B88B4UL))) +#define bM4_TMRA4_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422B88B8UL))) +#define bM4_TMRA4_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422B88BCUL))) +#define bM4_TMRA4_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422B8900UL))) +#define bM4_TMRA4_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422B8904UL))) +#define bM4_TMRA4_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422B8908UL))) +#define bM4_TMRA4_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422B890CUL))) +#define bM4_TMRA4_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422B8910UL))) +#define bM4_TMRA4_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422B8914UL))) +#define bM4_TMRA4_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422B8918UL))) +#define bM4_TMRA4_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422B891CUL))) +#define bM4_TMRA4_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422B8920UL))) +#define bM4_TMRA4_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422B8924UL))) +#define bM4_TMRA4_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422B8928UL))) +#define bM4_TMRA4_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422B892CUL))) +#define bM4_TMRA4_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422B8930UL))) +#define bM4_TMRA4_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422B8934UL))) +#define bM4_TMRA4_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422B8938UL))) +#define bM4_TMRA4_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422B893CUL))) +#define bM4_TMRA4_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422B8980UL))) +#define bM4_TMRA4_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422B8984UL))) +#define bM4_TMRA4_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422B8988UL))) +#define bM4_TMRA4_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422B898CUL))) +#define bM4_TMRA4_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422B8990UL))) +#define bM4_TMRA4_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422B8994UL))) +#define bM4_TMRA4_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422B8998UL))) +#define bM4_TMRA4_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422B899CUL))) +#define bM4_TMRA4_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422B89A0UL))) +#define bM4_TMRA4_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422B89A4UL))) +#define bM4_TMRA4_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422B89A8UL))) +#define bM4_TMRA4_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422B89ACUL))) +#define bM4_TMRA4_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422B89B0UL))) +#define bM4_TMRA4_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422B89B4UL))) +#define bM4_TMRA4_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422B89B8UL))) +#define bM4_TMRA4_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422B89BCUL))) +#define bM4_TMRA4_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422B8A00UL))) +#define bM4_TMRA4_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422B8A04UL))) +#define bM4_TMRA4_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422B8A08UL))) +#define bM4_TMRA4_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422B8A0CUL))) +#define bM4_TMRA4_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422B8A10UL))) +#define bM4_TMRA4_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422B8A14UL))) +#define bM4_TMRA4_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422B8A18UL))) +#define bM4_TMRA4_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422B8A1CUL))) +#define bM4_TMRA4_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422B8A20UL))) +#define bM4_TMRA4_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422B8A24UL))) +#define bM4_TMRA4_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422B8A28UL))) +#define bM4_TMRA4_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422B8A2CUL))) +#define bM4_TMRA4_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422B8A30UL))) +#define bM4_TMRA4_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422B8A34UL))) +#define bM4_TMRA4_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422B8A38UL))) +#define bM4_TMRA4_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422B8A3CUL))) +#define bM4_TMRA4_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422B8A80UL))) +#define bM4_TMRA4_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422B8A84UL))) +#define bM4_TMRA4_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422B8A88UL))) +#define bM4_TMRA4_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422B8A8CUL))) +#define bM4_TMRA4_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422B8A90UL))) +#define bM4_TMRA4_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422B8A94UL))) +#define bM4_TMRA4_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422B8A98UL))) +#define bM4_TMRA4_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422B8A9CUL))) +#define bM4_TMRA4_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422B8AA0UL))) +#define bM4_TMRA4_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422B8AA4UL))) +#define bM4_TMRA4_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422B8AA8UL))) +#define bM4_TMRA4_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422B8AACUL))) +#define bM4_TMRA4_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422B8AB0UL))) +#define bM4_TMRA4_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422B8AB4UL))) +#define bM4_TMRA4_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422B8AB8UL))) +#define bM4_TMRA4_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422B8ABCUL))) +#define bM4_TMRA4_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422B8B00UL))) +#define bM4_TMRA4_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422B8B04UL))) +#define bM4_TMRA4_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422B8B08UL))) +#define bM4_TMRA4_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422B8B0CUL))) +#define bM4_TMRA4_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422B8B10UL))) +#define bM4_TMRA4_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422B8B14UL))) +#define bM4_TMRA4_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422B8B18UL))) +#define bM4_TMRA4_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422B8B1CUL))) +#define bM4_TMRA4_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422B8B20UL))) +#define bM4_TMRA4_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422B8B24UL))) +#define bM4_TMRA4_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422B8B28UL))) +#define bM4_TMRA4_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422B8B2CUL))) +#define bM4_TMRA4_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422B8B30UL))) +#define bM4_TMRA4_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422B8B34UL))) +#define bM4_TMRA4_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422B8B38UL))) +#define bM4_TMRA4_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422B8B3CUL))) +#define bM4_TMRA4_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422B8B80UL))) +#define bM4_TMRA4_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422B8B84UL))) +#define bM4_TMRA4_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422B8B88UL))) +#define bM4_TMRA4_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422B8B8CUL))) +#define bM4_TMRA4_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422B8B90UL))) +#define bM4_TMRA4_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422B8B94UL))) +#define bM4_TMRA4_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422B8B98UL))) +#define bM4_TMRA4_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422B8B9CUL))) +#define bM4_TMRA4_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422B8BA0UL))) +#define bM4_TMRA4_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422B8BA4UL))) +#define bM4_TMRA4_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422B8BA8UL))) +#define bM4_TMRA4_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422B8BACUL))) +#define bM4_TMRA4_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422B8BB0UL))) +#define bM4_TMRA4_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422B8BB4UL))) +#define bM4_TMRA4_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422B8BB8UL))) +#define bM4_TMRA4_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422B8BBCUL))) +#define bM4_TMRA4_BCSTR_START (*((volatile unsigned int*)(0x422B9000UL))) +#define bM4_TMRA4_BCSTR_DIR (*((volatile unsigned int*)(0x422B9004UL))) +#define bM4_TMRA4_BCSTR_MODE (*((volatile unsigned int*)(0x422B9008UL))) +#define bM4_TMRA4_BCSTR_SYNST (*((volatile unsigned int*)(0x422B900CUL))) +#define bM4_TMRA4_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422B9010UL))) +#define bM4_TMRA4_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422B9014UL))) +#define bM4_TMRA4_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422B9018UL))) +#define bM4_TMRA4_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422B901CUL))) +#define bM4_TMRA4_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422B9030UL))) +#define bM4_TMRA4_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422B9034UL))) +#define bM4_TMRA4_BCSTR_OVFF (*((volatile unsigned int*)(0x422B9038UL))) +#define bM4_TMRA4_BCSTR_UDFF (*((volatile unsigned int*)(0x422B903CUL))) +#define bM4_TMRA4_HCONR_HSTA0 (*((volatile unsigned int*)(0x422B9080UL))) +#define bM4_TMRA4_HCONR_HSTA1 (*((volatile unsigned int*)(0x422B9084UL))) +#define bM4_TMRA4_HCONR_HSTA2 (*((volatile unsigned int*)(0x422B9088UL))) +#define bM4_TMRA4_HCONR_HSTP0 (*((volatile unsigned int*)(0x422B9090UL))) +#define bM4_TMRA4_HCONR_HSTP1 (*((volatile unsigned int*)(0x422B9094UL))) +#define bM4_TMRA4_HCONR_HSTP2 (*((volatile unsigned int*)(0x422B9098UL))) +#define bM4_TMRA4_HCONR_HCLE0 (*((volatile unsigned int*)(0x422B90A0UL))) +#define bM4_TMRA4_HCONR_HCLE1 (*((volatile unsigned int*)(0x422B90A4UL))) +#define bM4_TMRA4_HCONR_HCLE2 (*((volatile unsigned int*)(0x422B90A8UL))) +#define bM4_TMRA4_HCONR_HCLE3 (*((volatile unsigned int*)(0x422B90B0UL))) +#define bM4_TMRA4_HCONR_HCLE4 (*((volatile unsigned int*)(0x422B90B4UL))) +#define bM4_TMRA4_HCONR_HCLE5 (*((volatile unsigned int*)(0x422B90B8UL))) +#define bM4_TMRA4_HCONR_HCLE6 (*((volatile unsigned int*)(0x422B90BCUL))) +#define bM4_TMRA4_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422B9100UL))) +#define bM4_TMRA4_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422B9104UL))) +#define bM4_TMRA4_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422B9108UL))) +#define bM4_TMRA4_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422B910CUL))) +#define bM4_TMRA4_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422B9110UL))) +#define bM4_TMRA4_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422B9114UL))) +#define bM4_TMRA4_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422B9118UL))) +#define bM4_TMRA4_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422B911CUL))) +#define bM4_TMRA4_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422B9120UL))) +#define bM4_TMRA4_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422B9124UL))) +#define bM4_TMRA4_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422B9128UL))) +#define bM4_TMRA4_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422B912CUL))) +#define bM4_TMRA4_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422B9130UL))) +#define bM4_TMRA4_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422B9180UL))) +#define bM4_TMRA4_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422B9184UL))) +#define bM4_TMRA4_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422B9188UL))) +#define bM4_TMRA4_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422B918CUL))) +#define bM4_TMRA4_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422B9190UL))) +#define bM4_TMRA4_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422B9194UL))) +#define bM4_TMRA4_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422B9198UL))) +#define bM4_TMRA4_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422B919CUL))) +#define bM4_TMRA4_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422B91A0UL))) +#define bM4_TMRA4_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422B91A4UL))) +#define bM4_TMRA4_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422B91A8UL))) +#define bM4_TMRA4_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422B91ACUL))) +#define bM4_TMRA4_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422B91B0UL))) +#define bM4_TMRA4_ICONR_ITEN1 (*((volatile unsigned int*)(0x422B9200UL))) +#define bM4_TMRA4_ICONR_ITEN2 (*((volatile unsigned int*)(0x422B9204UL))) +#define bM4_TMRA4_ICONR_ITEN3 (*((volatile unsigned int*)(0x422B9208UL))) +#define bM4_TMRA4_ICONR_ITEN4 (*((volatile unsigned int*)(0x422B920CUL))) +#define bM4_TMRA4_ICONR_ITEN5 (*((volatile unsigned int*)(0x422B9210UL))) +#define bM4_TMRA4_ICONR_ITEN6 (*((volatile unsigned int*)(0x422B9214UL))) +#define bM4_TMRA4_ICONR_ITEN7 (*((volatile unsigned int*)(0x422B9218UL))) +#define bM4_TMRA4_ICONR_ITEN8 (*((volatile unsigned int*)(0x422B921CUL))) +#define bM4_TMRA4_ECONR_ETEN1 (*((volatile unsigned int*)(0x422B9280UL))) +#define bM4_TMRA4_ECONR_ETEN2 (*((volatile unsigned int*)(0x422B9284UL))) +#define bM4_TMRA4_ECONR_ETEN3 (*((volatile unsigned int*)(0x422B9288UL))) +#define bM4_TMRA4_ECONR_ETEN4 (*((volatile unsigned int*)(0x422B928CUL))) +#define bM4_TMRA4_ECONR_ETEN5 (*((volatile unsigned int*)(0x422B9290UL))) +#define bM4_TMRA4_ECONR_ETEN6 (*((volatile unsigned int*)(0x422B9294UL))) +#define bM4_TMRA4_ECONR_ETEN7 (*((volatile unsigned int*)(0x422B9298UL))) +#define bM4_TMRA4_ECONR_ETEN8 (*((volatile unsigned int*)(0x422B929CUL))) +#define bM4_TMRA4_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422B9300UL))) +#define bM4_TMRA4_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422B9304UL))) +#define bM4_TMRA4_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422B9308UL))) +#define bM4_TMRA4_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422B9320UL))) +#define bM4_TMRA4_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422B9324UL))) +#define bM4_TMRA4_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422B9328UL))) +#define bM4_TMRA4_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422B9330UL))) +#define bM4_TMRA4_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422B9334UL))) +#define bM4_TMRA4_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422B9338UL))) +#define bM4_TMRA4_STFLR_CMPF1 (*((volatile unsigned int*)(0x422B9380UL))) +#define bM4_TMRA4_STFLR_CMPF2 (*((volatile unsigned int*)(0x422B9384UL))) +#define bM4_TMRA4_STFLR_CMPF3 (*((volatile unsigned int*)(0x422B9388UL))) +#define bM4_TMRA4_STFLR_CMPF4 (*((volatile unsigned int*)(0x422B938CUL))) +#define bM4_TMRA4_STFLR_CMPF5 (*((volatile unsigned int*)(0x422B9390UL))) +#define bM4_TMRA4_STFLR_CMPF6 (*((volatile unsigned int*)(0x422B9394UL))) +#define bM4_TMRA4_STFLR_CMPF7 (*((volatile unsigned int*)(0x422B9398UL))) +#define bM4_TMRA4_STFLR_CMPF8 (*((volatile unsigned int*)(0x422B939CUL))) +#define bM4_TMRA4_BCONR1_BEN (*((volatile unsigned int*)(0x422B9800UL))) +#define bM4_TMRA4_BCONR1_BSE0 (*((volatile unsigned int*)(0x422B9804UL))) +#define bM4_TMRA4_BCONR1_BSE1 (*((volatile unsigned int*)(0x422B9808UL))) +#define bM4_TMRA4_BCONR2_BEN (*((volatile unsigned int*)(0x422B9900UL))) +#define bM4_TMRA4_BCONR2_BSE0 (*((volatile unsigned int*)(0x422B9904UL))) +#define bM4_TMRA4_BCONR2_BSE1 (*((volatile unsigned int*)(0x422B9908UL))) +#define bM4_TMRA4_BCONR3_BEN (*((volatile unsigned int*)(0x422B9A00UL))) +#define bM4_TMRA4_BCONR3_BSE0 (*((volatile unsigned int*)(0x422B9A04UL))) +#define bM4_TMRA4_BCONR3_BSE1 (*((volatile unsigned int*)(0x422B9A08UL))) +#define bM4_TMRA4_BCONR4_BEN (*((volatile unsigned int*)(0x422B9B00UL))) +#define bM4_TMRA4_BCONR4_BSE0 (*((volatile unsigned int*)(0x422B9B04UL))) +#define bM4_TMRA4_BCONR4_BSE1 (*((volatile unsigned int*)(0x422B9B08UL))) +#define bM4_TMRA4_CCONR1_CAPMD (*((volatile unsigned int*)(0x422BA000UL))) +#define bM4_TMRA4_CCONR1_HICP0 (*((volatile unsigned int*)(0x422BA010UL))) +#define bM4_TMRA4_CCONR1_HICP1 (*((volatile unsigned int*)(0x422BA014UL))) +#define bM4_TMRA4_CCONR1_HICP2 (*((volatile unsigned int*)(0x422BA018UL))) +#define bM4_TMRA4_CCONR1_HICP3 (*((volatile unsigned int*)(0x422BA020UL))) +#define bM4_TMRA4_CCONR1_HICP4 (*((volatile unsigned int*)(0x422BA024UL))) +#define bM4_TMRA4_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422BA030UL))) +#define bM4_TMRA4_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422BA034UL))) +#define bM4_TMRA4_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422BA038UL))) +#define bM4_TMRA4_CCONR2_CAPMD (*((volatile unsigned int*)(0x422BA080UL))) +#define bM4_TMRA4_CCONR2_HICP0 (*((volatile unsigned int*)(0x422BA090UL))) +#define bM4_TMRA4_CCONR2_HICP1 (*((volatile unsigned int*)(0x422BA094UL))) +#define bM4_TMRA4_CCONR2_HICP2 (*((volatile unsigned int*)(0x422BA098UL))) +#define bM4_TMRA4_CCONR2_HICP3 (*((volatile unsigned int*)(0x422BA0A0UL))) +#define bM4_TMRA4_CCONR2_HICP4 (*((volatile unsigned int*)(0x422BA0A4UL))) +#define bM4_TMRA4_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422BA0B0UL))) +#define bM4_TMRA4_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422BA0B4UL))) +#define bM4_TMRA4_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422BA0B8UL))) +#define bM4_TMRA4_CCONR3_CAPMD (*((volatile unsigned int*)(0x422BA100UL))) +#define bM4_TMRA4_CCONR3_HICP0 (*((volatile unsigned int*)(0x422BA110UL))) +#define bM4_TMRA4_CCONR3_HICP1 (*((volatile unsigned int*)(0x422BA114UL))) +#define bM4_TMRA4_CCONR3_HICP2 (*((volatile unsigned int*)(0x422BA118UL))) +#define bM4_TMRA4_CCONR3_HICP3 (*((volatile unsigned int*)(0x422BA120UL))) +#define bM4_TMRA4_CCONR3_HICP4 (*((volatile unsigned int*)(0x422BA124UL))) +#define bM4_TMRA4_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422BA130UL))) +#define bM4_TMRA4_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422BA134UL))) +#define bM4_TMRA4_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422BA138UL))) +#define bM4_TMRA4_CCONR4_CAPMD (*((volatile unsigned int*)(0x422BA180UL))) +#define bM4_TMRA4_CCONR4_HICP0 (*((volatile unsigned int*)(0x422BA190UL))) +#define bM4_TMRA4_CCONR4_HICP1 (*((volatile unsigned int*)(0x422BA194UL))) +#define bM4_TMRA4_CCONR4_HICP2 (*((volatile unsigned int*)(0x422BA198UL))) +#define bM4_TMRA4_CCONR4_HICP3 (*((volatile unsigned int*)(0x422BA1A0UL))) +#define bM4_TMRA4_CCONR4_HICP4 (*((volatile unsigned int*)(0x422BA1A4UL))) +#define bM4_TMRA4_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422BA1B0UL))) +#define bM4_TMRA4_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422BA1B4UL))) +#define bM4_TMRA4_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422BA1B8UL))) +#define bM4_TMRA4_CCONR5_CAPMD (*((volatile unsigned int*)(0x422BA200UL))) +#define bM4_TMRA4_CCONR5_HICP0 (*((volatile unsigned int*)(0x422BA210UL))) +#define bM4_TMRA4_CCONR5_HICP1 (*((volatile unsigned int*)(0x422BA214UL))) +#define bM4_TMRA4_CCONR5_HICP2 (*((volatile unsigned int*)(0x422BA218UL))) +#define bM4_TMRA4_CCONR5_HICP3 (*((volatile unsigned int*)(0x422BA220UL))) +#define bM4_TMRA4_CCONR5_HICP4 (*((volatile unsigned int*)(0x422BA224UL))) +#define bM4_TMRA4_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422BA230UL))) +#define bM4_TMRA4_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422BA234UL))) +#define bM4_TMRA4_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422BA238UL))) +#define bM4_TMRA4_CCONR6_CAPMD (*((volatile unsigned int*)(0x422BA280UL))) +#define bM4_TMRA4_CCONR6_HICP0 (*((volatile unsigned int*)(0x422BA290UL))) +#define bM4_TMRA4_CCONR6_HICP1 (*((volatile unsigned int*)(0x422BA294UL))) +#define bM4_TMRA4_CCONR6_HICP2 (*((volatile unsigned int*)(0x422BA298UL))) +#define bM4_TMRA4_CCONR6_HICP3 (*((volatile unsigned int*)(0x422BA2A0UL))) +#define bM4_TMRA4_CCONR6_HICP4 (*((volatile unsigned int*)(0x422BA2A4UL))) +#define bM4_TMRA4_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422BA2B0UL))) +#define bM4_TMRA4_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422BA2B4UL))) +#define bM4_TMRA4_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422BA2B8UL))) +#define bM4_TMRA4_CCONR7_CAPMD (*((volatile unsigned int*)(0x422BA300UL))) +#define bM4_TMRA4_CCONR7_HICP0 (*((volatile unsigned int*)(0x422BA310UL))) +#define bM4_TMRA4_CCONR7_HICP1 (*((volatile unsigned int*)(0x422BA314UL))) +#define bM4_TMRA4_CCONR7_HICP2 (*((volatile unsigned int*)(0x422BA318UL))) +#define bM4_TMRA4_CCONR7_HICP3 (*((volatile unsigned int*)(0x422BA320UL))) +#define bM4_TMRA4_CCONR7_HICP4 (*((volatile unsigned int*)(0x422BA324UL))) +#define bM4_TMRA4_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422BA330UL))) +#define bM4_TMRA4_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422BA334UL))) +#define bM4_TMRA4_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422BA338UL))) +#define bM4_TMRA4_CCONR8_CAPMD (*((volatile unsigned int*)(0x422BA380UL))) +#define bM4_TMRA4_CCONR8_HICP0 (*((volatile unsigned int*)(0x422BA390UL))) +#define bM4_TMRA4_CCONR8_HICP1 (*((volatile unsigned int*)(0x422BA394UL))) +#define bM4_TMRA4_CCONR8_HICP2 (*((volatile unsigned int*)(0x422BA398UL))) +#define bM4_TMRA4_CCONR8_HICP3 (*((volatile unsigned int*)(0x422BA3A0UL))) +#define bM4_TMRA4_CCONR8_HICP4 (*((volatile unsigned int*)(0x422BA3A4UL))) +#define bM4_TMRA4_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422BA3B0UL))) +#define bM4_TMRA4_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422BA3B4UL))) +#define bM4_TMRA4_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422BA3B8UL))) +#define bM4_TMRA4_PCONR1_STAC0 (*((volatile unsigned int*)(0x422BA800UL))) +#define bM4_TMRA4_PCONR1_STAC1 (*((volatile unsigned int*)(0x422BA804UL))) +#define bM4_TMRA4_PCONR1_STPC0 (*((volatile unsigned int*)(0x422BA808UL))) +#define bM4_TMRA4_PCONR1_STPC1 (*((volatile unsigned int*)(0x422BA80CUL))) +#define bM4_TMRA4_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422BA810UL))) +#define bM4_TMRA4_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422BA814UL))) +#define bM4_TMRA4_PCONR1_PERC0 (*((volatile unsigned int*)(0x422BA818UL))) +#define bM4_TMRA4_PCONR1_PERC1 (*((volatile unsigned int*)(0x422BA81CUL))) +#define bM4_TMRA4_PCONR1_FORC0 (*((volatile unsigned int*)(0x422BA820UL))) +#define bM4_TMRA4_PCONR1_FORC1 (*((volatile unsigned int*)(0x422BA824UL))) +#define bM4_TMRA4_PCONR1_OUTEN (*((volatile unsigned int*)(0x422BA830UL))) +#define bM4_TMRA4_PCONR2_STAC0 (*((volatile unsigned int*)(0x422BA880UL))) +#define bM4_TMRA4_PCONR2_STAC1 (*((volatile unsigned int*)(0x422BA884UL))) +#define bM4_TMRA4_PCONR2_STPC0 (*((volatile unsigned int*)(0x422BA888UL))) +#define bM4_TMRA4_PCONR2_STPC1 (*((volatile unsigned int*)(0x422BA88CUL))) +#define bM4_TMRA4_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422BA890UL))) +#define bM4_TMRA4_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422BA894UL))) +#define bM4_TMRA4_PCONR2_PERC0 (*((volatile unsigned int*)(0x422BA898UL))) +#define bM4_TMRA4_PCONR2_PERC1 (*((volatile unsigned int*)(0x422BA89CUL))) +#define bM4_TMRA4_PCONR2_FORC0 (*((volatile unsigned int*)(0x422BA8A0UL))) +#define bM4_TMRA4_PCONR2_FORC1 (*((volatile unsigned int*)(0x422BA8A4UL))) +#define bM4_TMRA4_PCONR2_OUTEN (*((volatile unsigned int*)(0x422BA8B0UL))) +#define bM4_TMRA4_PCONR3_STAC0 (*((volatile unsigned int*)(0x422BA900UL))) +#define bM4_TMRA4_PCONR3_STAC1 (*((volatile unsigned int*)(0x422BA904UL))) +#define bM4_TMRA4_PCONR3_STPC0 (*((volatile unsigned int*)(0x422BA908UL))) +#define bM4_TMRA4_PCONR3_STPC1 (*((volatile unsigned int*)(0x422BA90CUL))) +#define bM4_TMRA4_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422BA910UL))) +#define bM4_TMRA4_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422BA914UL))) +#define bM4_TMRA4_PCONR3_PERC0 (*((volatile unsigned int*)(0x422BA918UL))) +#define bM4_TMRA4_PCONR3_PERC1 (*((volatile unsigned int*)(0x422BA91CUL))) +#define bM4_TMRA4_PCONR3_FORC0 (*((volatile unsigned int*)(0x422BA920UL))) +#define bM4_TMRA4_PCONR3_FORC1 (*((volatile unsigned int*)(0x422BA924UL))) +#define bM4_TMRA4_PCONR3_OUTEN (*((volatile unsigned int*)(0x422BA930UL))) +#define bM4_TMRA4_PCONR4_STAC0 (*((volatile unsigned int*)(0x422BA980UL))) +#define bM4_TMRA4_PCONR4_STAC1 (*((volatile unsigned int*)(0x422BA984UL))) +#define bM4_TMRA4_PCONR4_STPC0 (*((volatile unsigned int*)(0x422BA988UL))) +#define bM4_TMRA4_PCONR4_STPC1 (*((volatile unsigned int*)(0x422BA98CUL))) +#define bM4_TMRA4_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422BA990UL))) +#define bM4_TMRA4_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422BA994UL))) +#define bM4_TMRA4_PCONR4_PERC0 (*((volatile unsigned int*)(0x422BA998UL))) +#define bM4_TMRA4_PCONR4_PERC1 (*((volatile unsigned int*)(0x422BA99CUL))) +#define bM4_TMRA4_PCONR4_FORC0 (*((volatile unsigned int*)(0x422BA9A0UL))) +#define bM4_TMRA4_PCONR4_FORC1 (*((volatile unsigned int*)(0x422BA9A4UL))) +#define bM4_TMRA4_PCONR4_OUTEN (*((volatile unsigned int*)(0x422BA9B0UL))) +#define bM4_TMRA4_PCONR5_STAC0 (*((volatile unsigned int*)(0x422BAA00UL))) +#define bM4_TMRA4_PCONR5_STAC1 (*((volatile unsigned int*)(0x422BAA04UL))) +#define bM4_TMRA4_PCONR5_STPC0 (*((volatile unsigned int*)(0x422BAA08UL))) +#define bM4_TMRA4_PCONR5_STPC1 (*((volatile unsigned int*)(0x422BAA0CUL))) +#define bM4_TMRA4_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422BAA10UL))) +#define bM4_TMRA4_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422BAA14UL))) +#define bM4_TMRA4_PCONR5_PERC0 (*((volatile unsigned int*)(0x422BAA18UL))) +#define bM4_TMRA4_PCONR5_PERC1 (*((volatile unsigned int*)(0x422BAA1CUL))) +#define bM4_TMRA4_PCONR5_FORC0 (*((volatile unsigned int*)(0x422BAA20UL))) +#define bM4_TMRA4_PCONR5_FORC1 (*((volatile unsigned int*)(0x422BAA24UL))) +#define bM4_TMRA4_PCONR5_OUTEN (*((volatile unsigned int*)(0x422BAA30UL))) +#define bM4_TMRA4_PCONR6_STAC0 (*((volatile unsigned int*)(0x422BAA80UL))) +#define bM4_TMRA4_PCONR6_STAC1 (*((volatile unsigned int*)(0x422BAA84UL))) +#define bM4_TMRA4_PCONR6_STPC0 (*((volatile unsigned int*)(0x422BAA88UL))) +#define bM4_TMRA4_PCONR6_STPC1 (*((volatile unsigned int*)(0x422BAA8CUL))) +#define bM4_TMRA4_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422BAA90UL))) +#define bM4_TMRA4_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422BAA94UL))) +#define bM4_TMRA4_PCONR6_PERC0 (*((volatile unsigned int*)(0x422BAA98UL))) +#define bM4_TMRA4_PCONR6_PERC1 (*((volatile unsigned int*)(0x422BAA9CUL))) +#define bM4_TMRA4_PCONR6_FORC0 (*((volatile unsigned int*)(0x422BAAA0UL))) +#define bM4_TMRA4_PCONR6_FORC1 (*((volatile unsigned int*)(0x422BAAA4UL))) +#define bM4_TMRA4_PCONR6_OUTEN (*((volatile unsigned int*)(0x422BAAB0UL))) +#define bM4_TMRA4_PCONR7_STAC0 (*((volatile unsigned int*)(0x422BAB00UL))) +#define bM4_TMRA4_PCONR7_STAC1 (*((volatile unsigned int*)(0x422BAB04UL))) +#define bM4_TMRA4_PCONR7_STPC0 (*((volatile unsigned int*)(0x422BAB08UL))) +#define bM4_TMRA4_PCONR7_STPC1 (*((volatile unsigned int*)(0x422BAB0CUL))) +#define bM4_TMRA4_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422BAB10UL))) +#define bM4_TMRA4_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422BAB14UL))) +#define bM4_TMRA4_PCONR7_PERC0 (*((volatile unsigned int*)(0x422BAB18UL))) +#define bM4_TMRA4_PCONR7_PERC1 (*((volatile unsigned int*)(0x422BAB1CUL))) +#define bM4_TMRA4_PCONR7_FORC0 (*((volatile unsigned int*)(0x422BAB20UL))) +#define bM4_TMRA4_PCONR7_FORC1 (*((volatile unsigned int*)(0x422BAB24UL))) +#define bM4_TMRA4_PCONR7_OUTEN (*((volatile unsigned int*)(0x422BAB30UL))) +#define bM4_TMRA4_PCONR8_STAC0 (*((volatile unsigned int*)(0x422BAB80UL))) +#define bM4_TMRA4_PCONR8_STAC1 (*((volatile unsigned int*)(0x422BAB84UL))) +#define bM4_TMRA4_PCONR8_STPC0 (*((volatile unsigned int*)(0x422BAB88UL))) +#define bM4_TMRA4_PCONR8_STPC1 (*((volatile unsigned int*)(0x422BAB8CUL))) +#define bM4_TMRA4_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422BAB90UL))) +#define bM4_TMRA4_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422BAB94UL))) +#define bM4_TMRA4_PCONR8_PERC0 (*((volatile unsigned int*)(0x422BAB98UL))) +#define bM4_TMRA4_PCONR8_PERC1 (*((volatile unsigned int*)(0x422BAB9CUL))) +#define bM4_TMRA4_PCONR8_FORC0 (*((volatile unsigned int*)(0x422BABA0UL))) +#define bM4_TMRA4_PCONR8_FORC1 (*((volatile unsigned int*)(0x422BABA4UL))) +#define bM4_TMRA4_PCONR8_OUTEN (*((volatile unsigned int*)(0x422BABB0UL))) +#define bM4_TMRA5_CNTER_CNT0 (*((volatile unsigned int*)(0x422C0000UL))) +#define bM4_TMRA5_CNTER_CNT1 (*((volatile unsigned int*)(0x422C0004UL))) +#define bM4_TMRA5_CNTER_CNT2 (*((volatile unsigned int*)(0x422C0008UL))) +#define bM4_TMRA5_CNTER_CNT3 (*((volatile unsigned int*)(0x422C000CUL))) +#define bM4_TMRA5_CNTER_CNT4 (*((volatile unsigned int*)(0x422C0010UL))) +#define bM4_TMRA5_CNTER_CNT5 (*((volatile unsigned int*)(0x422C0014UL))) +#define bM4_TMRA5_CNTER_CNT6 (*((volatile unsigned int*)(0x422C0018UL))) +#define bM4_TMRA5_CNTER_CNT7 (*((volatile unsigned int*)(0x422C001CUL))) +#define bM4_TMRA5_CNTER_CNT8 (*((volatile unsigned int*)(0x422C0020UL))) +#define bM4_TMRA5_CNTER_CNT9 (*((volatile unsigned int*)(0x422C0024UL))) +#define bM4_TMRA5_CNTER_CNT10 (*((volatile unsigned int*)(0x422C0028UL))) +#define bM4_TMRA5_CNTER_CNT11 (*((volatile unsigned int*)(0x422C002CUL))) +#define bM4_TMRA5_CNTER_CNT12 (*((volatile unsigned int*)(0x422C0030UL))) +#define bM4_TMRA5_CNTER_CNT13 (*((volatile unsigned int*)(0x422C0034UL))) +#define bM4_TMRA5_CNTER_CNT14 (*((volatile unsigned int*)(0x422C0038UL))) +#define bM4_TMRA5_CNTER_CNT15 (*((volatile unsigned int*)(0x422C003CUL))) +#define bM4_TMRA5_PERAR_PER0 (*((volatile unsigned int*)(0x422C0080UL))) +#define bM4_TMRA5_PERAR_PER1 (*((volatile unsigned int*)(0x422C0084UL))) +#define bM4_TMRA5_PERAR_PER2 (*((volatile unsigned int*)(0x422C0088UL))) +#define bM4_TMRA5_PERAR_PER3 (*((volatile unsigned int*)(0x422C008CUL))) +#define bM4_TMRA5_PERAR_PER4 (*((volatile unsigned int*)(0x422C0090UL))) +#define bM4_TMRA5_PERAR_PER5 (*((volatile unsigned int*)(0x422C0094UL))) +#define bM4_TMRA5_PERAR_PER6 (*((volatile unsigned int*)(0x422C0098UL))) +#define bM4_TMRA5_PERAR_PER7 (*((volatile unsigned int*)(0x422C009CUL))) +#define bM4_TMRA5_PERAR_PER8 (*((volatile unsigned int*)(0x422C00A0UL))) +#define bM4_TMRA5_PERAR_PER9 (*((volatile unsigned int*)(0x422C00A4UL))) +#define bM4_TMRA5_PERAR_PER10 (*((volatile unsigned int*)(0x422C00A8UL))) +#define bM4_TMRA5_PERAR_PER11 (*((volatile unsigned int*)(0x422C00ACUL))) +#define bM4_TMRA5_PERAR_PER12 (*((volatile unsigned int*)(0x422C00B0UL))) +#define bM4_TMRA5_PERAR_PER13 (*((volatile unsigned int*)(0x422C00B4UL))) +#define bM4_TMRA5_PERAR_PER14 (*((volatile unsigned int*)(0x422C00B8UL))) +#define bM4_TMRA5_PERAR_PER15 (*((volatile unsigned int*)(0x422C00BCUL))) +#define bM4_TMRA5_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422C0800UL))) +#define bM4_TMRA5_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422C0804UL))) +#define bM4_TMRA5_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422C0808UL))) +#define bM4_TMRA5_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422C080CUL))) +#define bM4_TMRA5_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422C0810UL))) +#define bM4_TMRA5_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422C0814UL))) +#define bM4_TMRA5_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422C0818UL))) +#define bM4_TMRA5_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422C081CUL))) +#define bM4_TMRA5_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422C0820UL))) +#define bM4_TMRA5_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422C0824UL))) +#define bM4_TMRA5_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422C0828UL))) +#define bM4_TMRA5_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422C082CUL))) +#define bM4_TMRA5_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422C0830UL))) +#define bM4_TMRA5_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422C0834UL))) +#define bM4_TMRA5_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422C0838UL))) +#define bM4_TMRA5_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422C083CUL))) +#define bM4_TMRA5_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422C0880UL))) +#define bM4_TMRA5_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422C0884UL))) +#define bM4_TMRA5_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422C0888UL))) +#define bM4_TMRA5_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422C088CUL))) +#define bM4_TMRA5_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422C0890UL))) +#define bM4_TMRA5_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422C0894UL))) +#define bM4_TMRA5_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422C0898UL))) +#define bM4_TMRA5_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422C089CUL))) +#define bM4_TMRA5_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422C08A0UL))) +#define bM4_TMRA5_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422C08A4UL))) +#define bM4_TMRA5_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422C08A8UL))) +#define bM4_TMRA5_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422C08ACUL))) +#define bM4_TMRA5_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422C08B0UL))) +#define bM4_TMRA5_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422C08B4UL))) +#define bM4_TMRA5_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422C08B8UL))) +#define bM4_TMRA5_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422C08BCUL))) +#define bM4_TMRA5_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422C0900UL))) +#define bM4_TMRA5_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422C0904UL))) +#define bM4_TMRA5_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422C0908UL))) +#define bM4_TMRA5_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422C090CUL))) +#define bM4_TMRA5_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422C0910UL))) +#define bM4_TMRA5_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422C0914UL))) +#define bM4_TMRA5_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422C0918UL))) +#define bM4_TMRA5_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422C091CUL))) +#define bM4_TMRA5_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422C0920UL))) +#define bM4_TMRA5_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422C0924UL))) +#define bM4_TMRA5_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422C0928UL))) +#define bM4_TMRA5_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422C092CUL))) +#define bM4_TMRA5_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422C0930UL))) +#define bM4_TMRA5_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422C0934UL))) +#define bM4_TMRA5_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422C0938UL))) +#define bM4_TMRA5_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422C093CUL))) +#define bM4_TMRA5_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422C0980UL))) +#define bM4_TMRA5_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422C0984UL))) +#define bM4_TMRA5_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422C0988UL))) +#define bM4_TMRA5_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422C098CUL))) +#define bM4_TMRA5_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422C0990UL))) +#define bM4_TMRA5_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422C0994UL))) +#define bM4_TMRA5_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422C0998UL))) +#define bM4_TMRA5_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422C099CUL))) +#define bM4_TMRA5_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422C09A0UL))) +#define bM4_TMRA5_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422C09A4UL))) +#define bM4_TMRA5_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422C09A8UL))) +#define bM4_TMRA5_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422C09ACUL))) +#define bM4_TMRA5_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422C09B0UL))) +#define bM4_TMRA5_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422C09B4UL))) +#define bM4_TMRA5_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422C09B8UL))) +#define bM4_TMRA5_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422C09BCUL))) +#define bM4_TMRA5_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422C0A00UL))) +#define bM4_TMRA5_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422C0A04UL))) +#define bM4_TMRA5_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422C0A08UL))) +#define bM4_TMRA5_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422C0A0CUL))) +#define bM4_TMRA5_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422C0A10UL))) +#define bM4_TMRA5_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422C0A14UL))) +#define bM4_TMRA5_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422C0A18UL))) +#define bM4_TMRA5_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422C0A1CUL))) +#define bM4_TMRA5_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422C0A20UL))) +#define bM4_TMRA5_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422C0A24UL))) +#define bM4_TMRA5_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422C0A28UL))) +#define bM4_TMRA5_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422C0A2CUL))) +#define bM4_TMRA5_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422C0A30UL))) +#define bM4_TMRA5_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422C0A34UL))) +#define bM4_TMRA5_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422C0A38UL))) +#define bM4_TMRA5_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422C0A3CUL))) +#define bM4_TMRA5_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422C0A80UL))) +#define bM4_TMRA5_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422C0A84UL))) +#define bM4_TMRA5_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422C0A88UL))) +#define bM4_TMRA5_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422C0A8CUL))) +#define bM4_TMRA5_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422C0A90UL))) +#define bM4_TMRA5_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422C0A94UL))) +#define bM4_TMRA5_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422C0A98UL))) +#define bM4_TMRA5_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422C0A9CUL))) +#define bM4_TMRA5_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422C0AA0UL))) +#define bM4_TMRA5_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422C0AA4UL))) +#define bM4_TMRA5_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422C0AA8UL))) +#define bM4_TMRA5_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422C0AACUL))) +#define bM4_TMRA5_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422C0AB0UL))) +#define bM4_TMRA5_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422C0AB4UL))) +#define bM4_TMRA5_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422C0AB8UL))) +#define bM4_TMRA5_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422C0ABCUL))) +#define bM4_TMRA5_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422C0B00UL))) +#define bM4_TMRA5_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422C0B04UL))) +#define bM4_TMRA5_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422C0B08UL))) +#define bM4_TMRA5_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422C0B0CUL))) +#define bM4_TMRA5_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422C0B10UL))) +#define bM4_TMRA5_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422C0B14UL))) +#define bM4_TMRA5_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422C0B18UL))) +#define bM4_TMRA5_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422C0B1CUL))) +#define bM4_TMRA5_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422C0B20UL))) +#define bM4_TMRA5_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422C0B24UL))) +#define bM4_TMRA5_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422C0B28UL))) +#define bM4_TMRA5_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422C0B2CUL))) +#define bM4_TMRA5_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422C0B30UL))) +#define bM4_TMRA5_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422C0B34UL))) +#define bM4_TMRA5_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422C0B38UL))) +#define bM4_TMRA5_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422C0B3CUL))) +#define bM4_TMRA5_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422C0B80UL))) +#define bM4_TMRA5_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422C0B84UL))) +#define bM4_TMRA5_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422C0B88UL))) +#define bM4_TMRA5_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422C0B8CUL))) +#define bM4_TMRA5_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422C0B90UL))) +#define bM4_TMRA5_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422C0B94UL))) +#define bM4_TMRA5_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422C0B98UL))) +#define bM4_TMRA5_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422C0B9CUL))) +#define bM4_TMRA5_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422C0BA0UL))) +#define bM4_TMRA5_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422C0BA4UL))) +#define bM4_TMRA5_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422C0BA8UL))) +#define bM4_TMRA5_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422C0BACUL))) +#define bM4_TMRA5_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422C0BB0UL))) +#define bM4_TMRA5_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422C0BB4UL))) +#define bM4_TMRA5_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422C0BB8UL))) +#define bM4_TMRA5_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422C0BBCUL))) +#define bM4_TMRA5_BCSTR_START (*((volatile unsigned int*)(0x422C1000UL))) +#define bM4_TMRA5_BCSTR_DIR (*((volatile unsigned int*)(0x422C1004UL))) +#define bM4_TMRA5_BCSTR_MODE (*((volatile unsigned int*)(0x422C1008UL))) +#define bM4_TMRA5_BCSTR_SYNST (*((volatile unsigned int*)(0x422C100CUL))) +#define bM4_TMRA5_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422C1010UL))) +#define bM4_TMRA5_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422C1014UL))) +#define bM4_TMRA5_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422C1018UL))) +#define bM4_TMRA5_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422C101CUL))) +#define bM4_TMRA5_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422C1030UL))) +#define bM4_TMRA5_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422C1034UL))) +#define bM4_TMRA5_BCSTR_OVFF (*((volatile unsigned int*)(0x422C1038UL))) +#define bM4_TMRA5_BCSTR_UDFF (*((volatile unsigned int*)(0x422C103CUL))) +#define bM4_TMRA5_HCONR_HSTA0 (*((volatile unsigned int*)(0x422C1080UL))) +#define bM4_TMRA5_HCONR_HSTA1 (*((volatile unsigned int*)(0x422C1084UL))) +#define bM4_TMRA5_HCONR_HSTA2 (*((volatile unsigned int*)(0x422C1088UL))) +#define bM4_TMRA5_HCONR_HSTP0 (*((volatile unsigned int*)(0x422C1090UL))) +#define bM4_TMRA5_HCONR_HSTP1 (*((volatile unsigned int*)(0x422C1094UL))) +#define bM4_TMRA5_HCONR_HSTP2 (*((volatile unsigned int*)(0x422C1098UL))) +#define bM4_TMRA5_HCONR_HCLE0 (*((volatile unsigned int*)(0x422C10A0UL))) +#define bM4_TMRA5_HCONR_HCLE1 (*((volatile unsigned int*)(0x422C10A4UL))) +#define bM4_TMRA5_HCONR_HCLE2 (*((volatile unsigned int*)(0x422C10A8UL))) +#define bM4_TMRA5_HCONR_HCLE3 (*((volatile unsigned int*)(0x422C10B0UL))) +#define bM4_TMRA5_HCONR_HCLE4 (*((volatile unsigned int*)(0x422C10B4UL))) +#define bM4_TMRA5_HCONR_HCLE5 (*((volatile unsigned int*)(0x422C10B8UL))) +#define bM4_TMRA5_HCONR_HCLE6 (*((volatile unsigned int*)(0x422C10BCUL))) +#define bM4_TMRA5_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422C1100UL))) +#define bM4_TMRA5_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422C1104UL))) +#define bM4_TMRA5_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422C1108UL))) +#define bM4_TMRA5_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422C110CUL))) +#define bM4_TMRA5_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422C1110UL))) +#define bM4_TMRA5_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422C1114UL))) +#define bM4_TMRA5_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422C1118UL))) +#define bM4_TMRA5_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422C111CUL))) +#define bM4_TMRA5_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422C1120UL))) +#define bM4_TMRA5_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422C1124UL))) +#define bM4_TMRA5_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422C1128UL))) +#define bM4_TMRA5_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422C112CUL))) +#define bM4_TMRA5_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422C1130UL))) +#define bM4_TMRA5_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422C1180UL))) +#define bM4_TMRA5_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422C1184UL))) +#define bM4_TMRA5_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422C1188UL))) +#define bM4_TMRA5_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422C118CUL))) +#define bM4_TMRA5_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422C1190UL))) +#define bM4_TMRA5_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422C1194UL))) +#define bM4_TMRA5_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422C1198UL))) +#define bM4_TMRA5_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422C119CUL))) +#define bM4_TMRA5_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422C11A0UL))) +#define bM4_TMRA5_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422C11A4UL))) +#define bM4_TMRA5_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422C11A8UL))) +#define bM4_TMRA5_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422C11ACUL))) +#define bM4_TMRA5_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422C11B0UL))) +#define bM4_TMRA5_ICONR_ITEN1 (*((volatile unsigned int*)(0x422C1200UL))) +#define bM4_TMRA5_ICONR_ITEN2 (*((volatile unsigned int*)(0x422C1204UL))) +#define bM4_TMRA5_ICONR_ITEN3 (*((volatile unsigned int*)(0x422C1208UL))) +#define bM4_TMRA5_ICONR_ITEN4 (*((volatile unsigned int*)(0x422C120CUL))) +#define bM4_TMRA5_ICONR_ITEN5 (*((volatile unsigned int*)(0x422C1210UL))) +#define bM4_TMRA5_ICONR_ITEN6 (*((volatile unsigned int*)(0x422C1214UL))) +#define bM4_TMRA5_ICONR_ITEN7 (*((volatile unsigned int*)(0x422C1218UL))) +#define bM4_TMRA5_ICONR_ITEN8 (*((volatile unsigned int*)(0x422C121CUL))) +#define bM4_TMRA5_ECONR_ETEN1 (*((volatile unsigned int*)(0x422C1280UL))) +#define bM4_TMRA5_ECONR_ETEN2 (*((volatile unsigned int*)(0x422C1284UL))) +#define bM4_TMRA5_ECONR_ETEN3 (*((volatile unsigned int*)(0x422C1288UL))) +#define bM4_TMRA5_ECONR_ETEN4 (*((volatile unsigned int*)(0x422C128CUL))) +#define bM4_TMRA5_ECONR_ETEN5 (*((volatile unsigned int*)(0x422C1290UL))) +#define bM4_TMRA5_ECONR_ETEN6 (*((volatile unsigned int*)(0x422C1294UL))) +#define bM4_TMRA5_ECONR_ETEN7 (*((volatile unsigned int*)(0x422C1298UL))) +#define bM4_TMRA5_ECONR_ETEN8 (*((volatile unsigned int*)(0x422C129CUL))) +#define bM4_TMRA5_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422C1300UL))) +#define bM4_TMRA5_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422C1304UL))) +#define bM4_TMRA5_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422C1308UL))) +#define bM4_TMRA5_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422C1320UL))) +#define bM4_TMRA5_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422C1324UL))) +#define bM4_TMRA5_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422C1328UL))) +#define bM4_TMRA5_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422C1330UL))) +#define bM4_TMRA5_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422C1334UL))) +#define bM4_TMRA5_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422C1338UL))) +#define bM4_TMRA5_STFLR_CMPF1 (*((volatile unsigned int*)(0x422C1380UL))) +#define bM4_TMRA5_STFLR_CMPF2 (*((volatile unsigned int*)(0x422C1384UL))) +#define bM4_TMRA5_STFLR_CMPF3 (*((volatile unsigned int*)(0x422C1388UL))) +#define bM4_TMRA5_STFLR_CMPF4 (*((volatile unsigned int*)(0x422C138CUL))) +#define bM4_TMRA5_STFLR_CMPF5 (*((volatile unsigned int*)(0x422C1390UL))) +#define bM4_TMRA5_STFLR_CMPF6 (*((volatile unsigned int*)(0x422C1394UL))) +#define bM4_TMRA5_STFLR_CMPF7 (*((volatile unsigned int*)(0x422C1398UL))) +#define bM4_TMRA5_STFLR_CMPF8 (*((volatile unsigned int*)(0x422C139CUL))) +#define bM4_TMRA5_BCONR1_BEN (*((volatile unsigned int*)(0x422C1800UL))) +#define bM4_TMRA5_BCONR1_BSE0 (*((volatile unsigned int*)(0x422C1804UL))) +#define bM4_TMRA5_BCONR1_BSE1 (*((volatile unsigned int*)(0x422C1808UL))) +#define bM4_TMRA5_BCONR2_BEN (*((volatile unsigned int*)(0x422C1900UL))) +#define bM4_TMRA5_BCONR2_BSE0 (*((volatile unsigned int*)(0x422C1904UL))) +#define bM4_TMRA5_BCONR2_BSE1 (*((volatile unsigned int*)(0x422C1908UL))) +#define bM4_TMRA5_BCONR3_BEN (*((volatile unsigned int*)(0x422C1A00UL))) +#define bM4_TMRA5_BCONR3_BSE0 (*((volatile unsigned int*)(0x422C1A04UL))) +#define bM4_TMRA5_BCONR3_BSE1 (*((volatile unsigned int*)(0x422C1A08UL))) +#define bM4_TMRA5_BCONR4_BEN (*((volatile unsigned int*)(0x422C1B00UL))) +#define bM4_TMRA5_BCONR4_BSE0 (*((volatile unsigned int*)(0x422C1B04UL))) +#define bM4_TMRA5_BCONR4_BSE1 (*((volatile unsigned int*)(0x422C1B08UL))) +#define bM4_TMRA5_CCONR1_CAPMD (*((volatile unsigned int*)(0x422C2000UL))) +#define bM4_TMRA5_CCONR1_HICP0 (*((volatile unsigned int*)(0x422C2010UL))) +#define bM4_TMRA5_CCONR1_HICP1 (*((volatile unsigned int*)(0x422C2014UL))) +#define bM4_TMRA5_CCONR1_HICP2 (*((volatile unsigned int*)(0x422C2018UL))) +#define bM4_TMRA5_CCONR1_HICP3 (*((volatile unsigned int*)(0x422C2020UL))) +#define bM4_TMRA5_CCONR1_HICP4 (*((volatile unsigned int*)(0x422C2024UL))) +#define bM4_TMRA5_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422C2030UL))) +#define bM4_TMRA5_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422C2034UL))) +#define bM4_TMRA5_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422C2038UL))) +#define bM4_TMRA5_CCONR2_CAPMD (*((volatile unsigned int*)(0x422C2080UL))) +#define bM4_TMRA5_CCONR2_HICP0 (*((volatile unsigned int*)(0x422C2090UL))) +#define bM4_TMRA5_CCONR2_HICP1 (*((volatile unsigned int*)(0x422C2094UL))) +#define bM4_TMRA5_CCONR2_HICP2 (*((volatile unsigned int*)(0x422C2098UL))) +#define bM4_TMRA5_CCONR2_HICP3 (*((volatile unsigned int*)(0x422C20A0UL))) +#define bM4_TMRA5_CCONR2_HICP4 (*((volatile unsigned int*)(0x422C20A4UL))) +#define bM4_TMRA5_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422C20B0UL))) +#define bM4_TMRA5_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422C20B4UL))) +#define bM4_TMRA5_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422C20B8UL))) +#define bM4_TMRA5_CCONR3_CAPMD (*((volatile unsigned int*)(0x422C2100UL))) +#define bM4_TMRA5_CCONR3_HICP0 (*((volatile unsigned int*)(0x422C2110UL))) +#define bM4_TMRA5_CCONR3_HICP1 (*((volatile unsigned int*)(0x422C2114UL))) +#define bM4_TMRA5_CCONR3_HICP2 (*((volatile unsigned int*)(0x422C2118UL))) +#define bM4_TMRA5_CCONR3_HICP3 (*((volatile unsigned int*)(0x422C2120UL))) +#define bM4_TMRA5_CCONR3_HICP4 (*((volatile unsigned int*)(0x422C2124UL))) +#define bM4_TMRA5_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422C2130UL))) +#define bM4_TMRA5_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422C2134UL))) +#define bM4_TMRA5_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422C2138UL))) +#define bM4_TMRA5_CCONR4_CAPMD (*((volatile unsigned int*)(0x422C2180UL))) +#define bM4_TMRA5_CCONR4_HICP0 (*((volatile unsigned int*)(0x422C2190UL))) +#define bM4_TMRA5_CCONR4_HICP1 (*((volatile unsigned int*)(0x422C2194UL))) +#define bM4_TMRA5_CCONR4_HICP2 (*((volatile unsigned int*)(0x422C2198UL))) +#define bM4_TMRA5_CCONR4_HICP3 (*((volatile unsigned int*)(0x422C21A0UL))) +#define bM4_TMRA5_CCONR4_HICP4 (*((volatile unsigned int*)(0x422C21A4UL))) +#define bM4_TMRA5_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422C21B0UL))) +#define bM4_TMRA5_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422C21B4UL))) +#define bM4_TMRA5_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422C21B8UL))) +#define bM4_TMRA5_CCONR5_CAPMD (*((volatile unsigned int*)(0x422C2200UL))) +#define bM4_TMRA5_CCONR5_HICP0 (*((volatile unsigned int*)(0x422C2210UL))) +#define bM4_TMRA5_CCONR5_HICP1 (*((volatile unsigned int*)(0x422C2214UL))) +#define bM4_TMRA5_CCONR5_HICP2 (*((volatile unsigned int*)(0x422C2218UL))) +#define bM4_TMRA5_CCONR5_HICP3 (*((volatile unsigned int*)(0x422C2220UL))) +#define bM4_TMRA5_CCONR5_HICP4 (*((volatile unsigned int*)(0x422C2224UL))) +#define bM4_TMRA5_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422C2230UL))) +#define bM4_TMRA5_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422C2234UL))) +#define bM4_TMRA5_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422C2238UL))) +#define bM4_TMRA5_CCONR6_CAPMD (*((volatile unsigned int*)(0x422C2280UL))) +#define bM4_TMRA5_CCONR6_HICP0 (*((volatile unsigned int*)(0x422C2290UL))) +#define bM4_TMRA5_CCONR6_HICP1 (*((volatile unsigned int*)(0x422C2294UL))) +#define bM4_TMRA5_CCONR6_HICP2 (*((volatile unsigned int*)(0x422C2298UL))) +#define bM4_TMRA5_CCONR6_HICP3 (*((volatile unsigned int*)(0x422C22A0UL))) +#define bM4_TMRA5_CCONR6_HICP4 (*((volatile unsigned int*)(0x422C22A4UL))) +#define bM4_TMRA5_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422C22B0UL))) +#define bM4_TMRA5_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422C22B4UL))) +#define bM4_TMRA5_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422C22B8UL))) +#define bM4_TMRA5_CCONR7_CAPMD (*((volatile unsigned int*)(0x422C2300UL))) +#define bM4_TMRA5_CCONR7_HICP0 (*((volatile unsigned int*)(0x422C2310UL))) +#define bM4_TMRA5_CCONR7_HICP1 (*((volatile unsigned int*)(0x422C2314UL))) +#define bM4_TMRA5_CCONR7_HICP2 (*((volatile unsigned int*)(0x422C2318UL))) +#define bM4_TMRA5_CCONR7_HICP3 (*((volatile unsigned int*)(0x422C2320UL))) +#define bM4_TMRA5_CCONR7_HICP4 (*((volatile unsigned int*)(0x422C2324UL))) +#define bM4_TMRA5_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422C2330UL))) +#define bM4_TMRA5_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422C2334UL))) +#define bM4_TMRA5_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422C2338UL))) +#define bM4_TMRA5_CCONR8_CAPMD (*((volatile unsigned int*)(0x422C2380UL))) +#define bM4_TMRA5_CCONR8_HICP0 (*((volatile unsigned int*)(0x422C2390UL))) +#define bM4_TMRA5_CCONR8_HICP1 (*((volatile unsigned int*)(0x422C2394UL))) +#define bM4_TMRA5_CCONR8_HICP2 (*((volatile unsigned int*)(0x422C2398UL))) +#define bM4_TMRA5_CCONR8_HICP3 (*((volatile unsigned int*)(0x422C23A0UL))) +#define bM4_TMRA5_CCONR8_HICP4 (*((volatile unsigned int*)(0x422C23A4UL))) +#define bM4_TMRA5_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422C23B0UL))) +#define bM4_TMRA5_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422C23B4UL))) +#define bM4_TMRA5_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422C23B8UL))) +#define bM4_TMRA5_PCONR1_STAC0 (*((volatile unsigned int*)(0x422C2800UL))) +#define bM4_TMRA5_PCONR1_STAC1 (*((volatile unsigned int*)(0x422C2804UL))) +#define bM4_TMRA5_PCONR1_STPC0 (*((volatile unsigned int*)(0x422C2808UL))) +#define bM4_TMRA5_PCONR1_STPC1 (*((volatile unsigned int*)(0x422C280CUL))) +#define bM4_TMRA5_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422C2810UL))) +#define bM4_TMRA5_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422C2814UL))) +#define bM4_TMRA5_PCONR1_PERC0 (*((volatile unsigned int*)(0x422C2818UL))) +#define bM4_TMRA5_PCONR1_PERC1 (*((volatile unsigned int*)(0x422C281CUL))) +#define bM4_TMRA5_PCONR1_FORC0 (*((volatile unsigned int*)(0x422C2820UL))) +#define bM4_TMRA5_PCONR1_FORC1 (*((volatile unsigned int*)(0x422C2824UL))) +#define bM4_TMRA5_PCONR1_OUTEN (*((volatile unsigned int*)(0x422C2830UL))) +#define bM4_TMRA5_PCONR2_STAC0 (*((volatile unsigned int*)(0x422C2880UL))) +#define bM4_TMRA5_PCONR2_STAC1 (*((volatile unsigned int*)(0x422C2884UL))) +#define bM4_TMRA5_PCONR2_STPC0 (*((volatile unsigned int*)(0x422C2888UL))) +#define bM4_TMRA5_PCONR2_STPC1 (*((volatile unsigned int*)(0x422C288CUL))) +#define bM4_TMRA5_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422C2890UL))) +#define bM4_TMRA5_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422C2894UL))) +#define bM4_TMRA5_PCONR2_PERC0 (*((volatile unsigned int*)(0x422C2898UL))) +#define bM4_TMRA5_PCONR2_PERC1 (*((volatile unsigned int*)(0x422C289CUL))) +#define bM4_TMRA5_PCONR2_FORC0 (*((volatile unsigned int*)(0x422C28A0UL))) +#define bM4_TMRA5_PCONR2_FORC1 (*((volatile unsigned int*)(0x422C28A4UL))) +#define bM4_TMRA5_PCONR2_OUTEN (*((volatile unsigned int*)(0x422C28B0UL))) +#define bM4_TMRA5_PCONR3_STAC0 (*((volatile unsigned int*)(0x422C2900UL))) +#define bM4_TMRA5_PCONR3_STAC1 (*((volatile unsigned int*)(0x422C2904UL))) +#define bM4_TMRA5_PCONR3_STPC0 (*((volatile unsigned int*)(0x422C2908UL))) +#define bM4_TMRA5_PCONR3_STPC1 (*((volatile unsigned int*)(0x422C290CUL))) +#define bM4_TMRA5_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422C2910UL))) +#define bM4_TMRA5_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422C2914UL))) +#define bM4_TMRA5_PCONR3_PERC0 (*((volatile unsigned int*)(0x422C2918UL))) +#define bM4_TMRA5_PCONR3_PERC1 (*((volatile unsigned int*)(0x422C291CUL))) +#define bM4_TMRA5_PCONR3_FORC0 (*((volatile unsigned int*)(0x422C2920UL))) +#define bM4_TMRA5_PCONR3_FORC1 (*((volatile unsigned int*)(0x422C2924UL))) +#define bM4_TMRA5_PCONR3_OUTEN (*((volatile unsigned int*)(0x422C2930UL))) +#define bM4_TMRA5_PCONR4_STAC0 (*((volatile unsigned int*)(0x422C2980UL))) +#define bM4_TMRA5_PCONR4_STAC1 (*((volatile unsigned int*)(0x422C2984UL))) +#define bM4_TMRA5_PCONR4_STPC0 (*((volatile unsigned int*)(0x422C2988UL))) +#define bM4_TMRA5_PCONR4_STPC1 (*((volatile unsigned int*)(0x422C298CUL))) +#define bM4_TMRA5_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422C2990UL))) +#define bM4_TMRA5_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422C2994UL))) +#define bM4_TMRA5_PCONR4_PERC0 (*((volatile unsigned int*)(0x422C2998UL))) +#define bM4_TMRA5_PCONR4_PERC1 (*((volatile unsigned int*)(0x422C299CUL))) +#define bM4_TMRA5_PCONR4_FORC0 (*((volatile unsigned int*)(0x422C29A0UL))) +#define bM4_TMRA5_PCONR4_FORC1 (*((volatile unsigned int*)(0x422C29A4UL))) +#define bM4_TMRA5_PCONR4_OUTEN (*((volatile unsigned int*)(0x422C29B0UL))) +#define bM4_TMRA5_PCONR5_STAC0 (*((volatile unsigned int*)(0x422C2A00UL))) +#define bM4_TMRA5_PCONR5_STAC1 (*((volatile unsigned int*)(0x422C2A04UL))) +#define bM4_TMRA5_PCONR5_STPC0 (*((volatile unsigned int*)(0x422C2A08UL))) +#define bM4_TMRA5_PCONR5_STPC1 (*((volatile unsigned int*)(0x422C2A0CUL))) +#define bM4_TMRA5_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422C2A10UL))) +#define bM4_TMRA5_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422C2A14UL))) +#define bM4_TMRA5_PCONR5_PERC0 (*((volatile unsigned int*)(0x422C2A18UL))) +#define bM4_TMRA5_PCONR5_PERC1 (*((volatile unsigned int*)(0x422C2A1CUL))) +#define bM4_TMRA5_PCONR5_FORC0 (*((volatile unsigned int*)(0x422C2A20UL))) +#define bM4_TMRA5_PCONR5_FORC1 (*((volatile unsigned int*)(0x422C2A24UL))) +#define bM4_TMRA5_PCONR5_OUTEN (*((volatile unsigned int*)(0x422C2A30UL))) +#define bM4_TMRA5_PCONR6_STAC0 (*((volatile unsigned int*)(0x422C2A80UL))) +#define bM4_TMRA5_PCONR6_STAC1 (*((volatile unsigned int*)(0x422C2A84UL))) +#define bM4_TMRA5_PCONR6_STPC0 (*((volatile unsigned int*)(0x422C2A88UL))) +#define bM4_TMRA5_PCONR6_STPC1 (*((volatile unsigned int*)(0x422C2A8CUL))) +#define bM4_TMRA5_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422C2A90UL))) +#define bM4_TMRA5_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422C2A94UL))) +#define bM4_TMRA5_PCONR6_PERC0 (*((volatile unsigned int*)(0x422C2A98UL))) +#define bM4_TMRA5_PCONR6_PERC1 (*((volatile unsigned int*)(0x422C2A9CUL))) +#define bM4_TMRA5_PCONR6_FORC0 (*((volatile unsigned int*)(0x422C2AA0UL))) +#define bM4_TMRA5_PCONR6_FORC1 (*((volatile unsigned int*)(0x422C2AA4UL))) +#define bM4_TMRA5_PCONR6_OUTEN (*((volatile unsigned int*)(0x422C2AB0UL))) +#define bM4_TMRA5_PCONR7_STAC0 (*((volatile unsigned int*)(0x422C2B00UL))) +#define bM4_TMRA5_PCONR7_STAC1 (*((volatile unsigned int*)(0x422C2B04UL))) +#define bM4_TMRA5_PCONR7_STPC0 (*((volatile unsigned int*)(0x422C2B08UL))) +#define bM4_TMRA5_PCONR7_STPC1 (*((volatile unsigned int*)(0x422C2B0CUL))) +#define bM4_TMRA5_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422C2B10UL))) +#define bM4_TMRA5_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422C2B14UL))) +#define bM4_TMRA5_PCONR7_PERC0 (*((volatile unsigned int*)(0x422C2B18UL))) +#define bM4_TMRA5_PCONR7_PERC1 (*((volatile unsigned int*)(0x422C2B1CUL))) +#define bM4_TMRA5_PCONR7_FORC0 (*((volatile unsigned int*)(0x422C2B20UL))) +#define bM4_TMRA5_PCONR7_FORC1 (*((volatile unsigned int*)(0x422C2B24UL))) +#define bM4_TMRA5_PCONR7_OUTEN (*((volatile unsigned int*)(0x422C2B30UL))) +#define bM4_TMRA5_PCONR8_STAC0 (*((volatile unsigned int*)(0x422C2B80UL))) +#define bM4_TMRA5_PCONR8_STAC1 (*((volatile unsigned int*)(0x422C2B84UL))) +#define bM4_TMRA5_PCONR8_STPC0 (*((volatile unsigned int*)(0x422C2B88UL))) +#define bM4_TMRA5_PCONR8_STPC1 (*((volatile unsigned int*)(0x422C2B8CUL))) +#define bM4_TMRA5_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422C2B90UL))) +#define bM4_TMRA5_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422C2B94UL))) +#define bM4_TMRA5_PCONR8_PERC0 (*((volatile unsigned int*)(0x422C2B98UL))) +#define bM4_TMRA5_PCONR8_PERC1 (*((volatile unsigned int*)(0x422C2B9CUL))) +#define bM4_TMRA5_PCONR8_FORC0 (*((volatile unsigned int*)(0x422C2BA0UL))) +#define bM4_TMRA5_PCONR8_FORC1 (*((volatile unsigned int*)(0x422C2BA4UL))) +#define bM4_TMRA5_PCONR8_OUTEN (*((volatile unsigned int*)(0x422C2BB0UL))) +#define bM4_TMRA6_CNTER_CNT0 (*((volatile unsigned int*)(0x422C8000UL))) +#define bM4_TMRA6_CNTER_CNT1 (*((volatile unsigned int*)(0x422C8004UL))) +#define bM4_TMRA6_CNTER_CNT2 (*((volatile unsigned int*)(0x422C8008UL))) +#define bM4_TMRA6_CNTER_CNT3 (*((volatile unsigned int*)(0x422C800CUL))) +#define bM4_TMRA6_CNTER_CNT4 (*((volatile unsigned int*)(0x422C8010UL))) +#define bM4_TMRA6_CNTER_CNT5 (*((volatile unsigned int*)(0x422C8014UL))) +#define bM4_TMRA6_CNTER_CNT6 (*((volatile unsigned int*)(0x422C8018UL))) +#define bM4_TMRA6_CNTER_CNT7 (*((volatile unsigned int*)(0x422C801CUL))) +#define bM4_TMRA6_CNTER_CNT8 (*((volatile unsigned int*)(0x422C8020UL))) +#define bM4_TMRA6_CNTER_CNT9 (*((volatile unsigned int*)(0x422C8024UL))) +#define bM4_TMRA6_CNTER_CNT10 (*((volatile unsigned int*)(0x422C8028UL))) +#define bM4_TMRA6_CNTER_CNT11 (*((volatile unsigned int*)(0x422C802CUL))) +#define bM4_TMRA6_CNTER_CNT12 (*((volatile unsigned int*)(0x422C8030UL))) +#define bM4_TMRA6_CNTER_CNT13 (*((volatile unsigned int*)(0x422C8034UL))) +#define bM4_TMRA6_CNTER_CNT14 (*((volatile unsigned int*)(0x422C8038UL))) +#define bM4_TMRA6_CNTER_CNT15 (*((volatile unsigned int*)(0x422C803CUL))) +#define bM4_TMRA6_PERAR_PER0 (*((volatile unsigned int*)(0x422C8080UL))) +#define bM4_TMRA6_PERAR_PER1 (*((volatile unsigned int*)(0x422C8084UL))) +#define bM4_TMRA6_PERAR_PER2 (*((volatile unsigned int*)(0x422C8088UL))) +#define bM4_TMRA6_PERAR_PER3 (*((volatile unsigned int*)(0x422C808CUL))) +#define bM4_TMRA6_PERAR_PER4 (*((volatile unsigned int*)(0x422C8090UL))) +#define bM4_TMRA6_PERAR_PER5 (*((volatile unsigned int*)(0x422C8094UL))) +#define bM4_TMRA6_PERAR_PER6 (*((volatile unsigned int*)(0x422C8098UL))) +#define bM4_TMRA6_PERAR_PER7 (*((volatile unsigned int*)(0x422C809CUL))) +#define bM4_TMRA6_PERAR_PER8 (*((volatile unsigned int*)(0x422C80A0UL))) +#define bM4_TMRA6_PERAR_PER9 (*((volatile unsigned int*)(0x422C80A4UL))) +#define bM4_TMRA6_PERAR_PER10 (*((volatile unsigned int*)(0x422C80A8UL))) +#define bM4_TMRA6_PERAR_PER11 (*((volatile unsigned int*)(0x422C80ACUL))) +#define bM4_TMRA6_PERAR_PER12 (*((volatile unsigned int*)(0x422C80B0UL))) +#define bM4_TMRA6_PERAR_PER13 (*((volatile unsigned int*)(0x422C80B4UL))) +#define bM4_TMRA6_PERAR_PER14 (*((volatile unsigned int*)(0x422C80B8UL))) +#define bM4_TMRA6_PERAR_PER15 (*((volatile unsigned int*)(0x422C80BCUL))) +#define bM4_TMRA6_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422C8800UL))) +#define bM4_TMRA6_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422C8804UL))) +#define bM4_TMRA6_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422C8808UL))) +#define bM4_TMRA6_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422C880CUL))) +#define bM4_TMRA6_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422C8810UL))) +#define bM4_TMRA6_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422C8814UL))) +#define bM4_TMRA6_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422C8818UL))) +#define bM4_TMRA6_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422C881CUL))) +#define bM4_TMRA6_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422C8820UL))) +#define bM4_TMRA6_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422C8824UL))) +#define bM4_TMRA6_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422C8828UL))) +#define bM4_TMRA6_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422C882CUL))) +#define bM4_TMRA6_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422C8830UL))) +#define bM4_TMRA6_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422C8834UL))) +#define bM4_TMRA6_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422C8838UL))) +#define bM4_TMRA6_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422C883CUL))) +#define bM4_TMRA6_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422C8880UL))) +#define bM4_TMRA6_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422C8884UL))) +#define bM4_TMRA6_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422C8888UL))) +#define bM4_TMRA6_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422C888CUL))) +#define bM4_TMRA6_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422C8890UL))) +#define bM4_TMRA6_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422C8894UL))) +#define bM4_TMRA6_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422C8898UL))) +#define bM4_TMRA6_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422C889CUL))) +#define bM4_TMRA6_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422C88A0UL))) +#define bM4_TMRA6_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422C88A4UL))) +#define bM4_TMRA6_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422C88A8UL))) +#define bM4_TMRA6_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422C88ACUL))) +#define bM4_TMRA6_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422C88B0UL))) +#define bM4_TMRA6_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422C88B4UL))) +#define bM4_TMRA6_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422C88B8UL))) +#define bM4_TMRA6_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422C88BCUL))) +#define bM4_TMRA6_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422C8900UL))) +#define bM4_TMRA6_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422C8904UL))) +#define bM4_TMRA6_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422C8908UL))) +#define bM4_TMRA6_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422C890CUL))) +#define bM4_TMRA6_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422C8910UL))) +#define bM4_TMRA6_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422C8914UL))) +#define bM4_TMRA6_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422C8918UL))) +#define bM4_TMRA6_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422C891CUL))) +#define bM4_TMRA6_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422C8920UL))) +#define bM4_TMRA6_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422C8924UL))) +#define bM4_TMRA6_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422C8928UL))) +#define bM4_TMRA6_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422C892CUL))) +#define bM4_TMRA6_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422C8930UL))) +#define bM4_TMRA6_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422C8934UL))) +#define bM4_TMRA6_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422C8938UL))) +#define bM4_TMRA6_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422C893CUL))) +#define bM4_TMRA6_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422C8980UL))) +#define bM4_TMRA6_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422C8984UL))) +#define bM4_TMRA6_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422C8988UL))) +#define bM4_TMRA6_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422C898CUL))) +#define bM4_TMRA6_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422C8990UL))) +#define bM4_TMRA6_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422C8994UL))) +#define bM4_TMRA6_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422C8998UL))) +#define bM4_TMRA6_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422C899CUL))) +#define bM4_TMRA6_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422C89A0UL))) +#define bM4_TMRA6_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422C89A4UL))) +#define bM4_TMRA6_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422C89A8UL))) +#define bM4_TMRA6_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422C89ACUL))) +#define bM4_TMRA6_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422C89B0UL))) +#define bM4_TMRA6_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422C89B4UL))) +#define bM4_TMRA6_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422C89B8UL))) +#define bM4_TMRA6_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422C89BCUL))) +#define bM4_TMRA6_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422C8A00UL))) +#define bM4_TMRA6_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422C8A04UL))) +#define bM4_TMRA6_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422C8A08UL))) +#define bM4_TMRA6_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422C8A0CUL))) +#define bM4_TMRA6_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422C8A10UL))) +#define bM4_TMRA6_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422C8A14UL))) +#define bM4_TMRA6_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422C8A18UL))) +#define bM4_TMRA6_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422C8A1CUL))) +#define bM4_TMRA6_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422C8A20UL))) +#define bM4_TMRA6_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422C8A24UL))) +#define bM4_TMRA6_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422C8A28UL))) +#define bM4_TMRA6_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422C8A2CUL))) +#define bM4_TMRA6_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422C8A30UL))) +#define bM4_TMRA6_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422C8A34UL))) +#define bM4_TMRA6_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422C8A38UL))) +#define bM4_TMRA6_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422C8A3CUL))) +#define bM4_TMRA6_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422C8A80UL))) +#define bM4_TMRA6_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422C8A84UL))) +#define bM4_TMRA6_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422C8A88UL))) +#define bM4_TMRA6_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422C8A8CUL))) +#define bM4_TMRA6_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422C8A90UL))) +#define bM4_TMRA6_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422C8A94UL))) +#define bM4_TMRA6_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422C8A98UL))) +#define bM4_TMRA6_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422C8A9CUL))) +#define bM4_TMRA6_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422C8AA0UL))) +#define bM4_TMRA6_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422C8AA4UL))) +#define bM4_TMRA6_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422C8AA8UL))) +#define bM4_TMRA6_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422C8AACUL))) +#define bM4_TMRA6_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422C8AB0UL))) +#define bM4_TMRA6_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422C8AB4UL))) +#define bM4_TMRA6_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422C8AB8UL))) +#define bM4_TMRA6_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422C8ABCUL))) +#define bM4_TMRA6_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422C8B00UL))) +#define bM4_TMRA6_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422C8B04UL))) +#define bM4_TMRA6_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422C8B08UL))) +#define bM4_TMRA6_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422C8B0CUL))) +#define bM4_TMRA6_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422C8B10UL))) +#define bM4_TMRA6_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422C8B14UL))) +#define bM4_TMRA6_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422C8B18UL))) +#define bM4_TMRA6_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422C8B1CUL))) +#define bM4_TMRA6_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422C8B20UL))) +#define bM4_TMRA6_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422C8B24UL))) +#define bM4_TMRA6_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422C8B28UL))) +#define bM4_TMRA6_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422C8B2CUL))) +#define bM4_TMRA6_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422C8B30UL))) +#define bM4_TMRA6_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422C8B34UL))) +#define bM4_TMRA6_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422C8B38UL))) +#define bM4_TMRA6_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422C8B3CUL))) +#define bM4_TMRA6_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422C8B80UL))) +#define bM4_TMRA6_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422C8B84UL))) +#define bM4_TMRA6_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422C8B88UL))) +#define bM4_TMRA6_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422C8B8CUL))) +#define bM4_TMRA6_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422C8B90UL))) +#define bM4_TMRA6_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422C8B94UL))) +#define bM4_TMRA6_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422C8B98UL))) +#define bM4_TMRA6_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422C8B9CUL))) +#define bM4_TMRA6_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422C8BA0UL))) +#define bM4_TMRA6_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422C8BA4UL))) +#define bM4_TMRA6_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422C8BA8UL))) +#define bM4_TMRA6_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422C8BACUL))) +#define bM4_TMRA6_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422C8BB0UL))) +#define bM4_TMRA6_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422C8BB4UL))) +#define bM4_TMRA6_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422C8BB8UL))) +#define bM4_TMRA6_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422C8BBCUL))) +#define bM4_TMRA6_BCSTR_START (*((volatile unsigned int*)(0x422C9000UL))) +#define bM4_TMRA6_BCSTR_DIR (*((volatile unsigned int*)(0x422C9004UL))) +#define bM4_TMRA6_BCSTR_MODE (*((volatile unsigned int*)(0x422C9008UL))) +#define bM4_TMRA6_BCSTR_SYNST (*((volatile unsigned int*)(0x422C900CUL))) +#define bM4_TMRA6_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422C9010UL))) +#define bM4_TMRA6_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422C9014UL))) +#define bM4_TMRA6_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422C9018UL))) +#define bM4_TMRA6_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422C901CUL))) +#define bM4_TMRA6_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422C9030UL))) +#define bM4_TMRA6_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422C9034UL))) +#define bM4_TMRA6_BCSTR_OVFF (*((volatile unsigned int*)(0x422C9038UL))) +#define bM4_TMRA6_BCSTR_UDFF (*((volatile unsigned int*)(0x422C903CUL))) +#define bM4_TMRA6_HCONR_HSTA0 (*((volatile unsigned int*)(0x422C9080UL))) +#define bM4_TMRA6_HCONR_HSTA1 (*((volatile unsigned int*)(0x422C9084UL))) +#define bM4_TMRA6_HCONR_HSTA2 (*((volatile unsigned int*)(0x422C9088UL))) +#define bM4_TMRA6_HCONR_HSTP0 (*((volatile unsigned int*)(0x422C9090UL))) +#define bM4_TMRA6_HCONR_HSTP1 (*((volatile unsigned int*)(0x422C9094UL))) +#define bM4_TMRA6_HCONR_HSTP2 (*((volatile unsigned int*)(0x422C9098UL))) +#define bM4_TMRA6_HCONR_HCLE0 (*((volatile unsigned int*)(0x422C90A0UL))) +#define bM4_TMRA6_HCONR_HCLE1 (*((volatile unsigned int*)(0x422C90A4UL))) +#define bM4_TMRA6_HCONR_HCLE2 (*((volatile unsigned int*)(0x422C90A8UL))) +#define bM4_TMRA6_HCONR_HCLE3 (*((volatile unsigned int*)(0x422C90B0UL))) +#define bM4_TMRA6_HCONR_HCLE4 (*((volatile unsigned int*)(0x422C90B4UL))) +#define bM4_TMRA6_HCONR_HCLE5 (*((volatile unsigned int*)(0x422C90B8UL))) +#define bM4_TMRA6_HCONR_HCLE6 (*((volatile unsigned int*)(0x422C90BCUL))) +#define bM4_TMRA6_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422C9100UL))) +#define bM4_TMRA6_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422C9104UL))) +#define bM4_TMRA6_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422C9108UL))) +#define bM4_TMRA6_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422C910CUL))) +#define bM4_TMRA6_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422C9110UL))) +#define bM4_TMRA6_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422C9114UL))) +#define bM4_TMRA6_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422C9118UL))) +#define bM4_TMRA6_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422C911CUL))) +#define bM4_TMRA6_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422C9120UL))) +#define bM4_TMRA6_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422C9124UL))) +#define bM4_TMRA6_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422C9128UL))) +#define bM4_TMRA6_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422C912CUL))) +#define bM4_TMRA6_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422C9130UL))) +#define bM4_TMRA6_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422C9180UL))) +#define bM4_TMRA6_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422C9184UL))) +#define bM4_TMRA6_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422C9188UL))) +#define bM4_TMRA6_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422C918CUL))) +#define bM4_TMRA6_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422C9190UL))) +#define bM4_TMRA6_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422C9194UL))) +#define bM4_TMRA6_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422C9198UL))) +#define bM4_TMRA6_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422C919CUL))) +#define bM4_TMRA6_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422C91A0UL))) +#define bM4_TMRA6_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422C91A4UL))) +#define bM4_TMRA6_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422C91A8UL))) +#define bM4_TMRA6_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422C91ACUL))) +#define bM4_TMRA6_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422C91B0UL))) +#define bM4_TMRA6_ICONR_ITEN1 (*((volatile unsigned int*)(0x422C9200UL))) +#define bM4_TMRA6_ICONR_ITEN2 (*((volatile unsigned int*)(0x422C9204UL))) +#define bM4_TMRA6_ICONR_ITEN3 (*((volatile unsigned int*)(0x422C9208UL))) +#define bM4_TMRA6_ICONR_ITEN4 (*((volatile unsigned int*)(0x422C920CUL))) +#define bM4_TMRA6_ICONR_ITEN5 (*((volatile unsigned int*)(0x422C9210UL))) +#define bM4_TMRA6_ICONR_ITEN6 (*((volatile unsigned int*)(0x422C9214UL))) +#define bM4_TMRA6_ICONR_ITEN7 (*((volatile unsigned int*)(0x422C9218UL))) +#define bM4_TMRA6_ICONR_ITEN8 (*((volatile unsigned int*)(0x422C921CUL))) +#define bM4_TMRA6_ECONR_ETEN1 (*((volatile unsigned int*)(0x422C9280UL))) +#define bM4_TMRA6_ECONR_ETEN2 (*((volatile unsigned int*)(0x422C9284UL))) +#define bM4_TMRA6_ECONR_ETEN3 (*((volatile unsigned int*)(0x422C9288UL))) +#define bM4_TMRA6_ECONR_ETEN4 (*((volatile unsigned int*)(0x422C928CUL))) +#define bM4_TMRA6_ECONR_ETEN5 (*((volatile unsigned int*)(0x422C9290UL))) +#define bM4_TMRA6_ECONR_ETEN6 (*((volatile unsigned int*)(0x422C9294UL))) +#define bM4_TMRA6_ECONR_ETEN7 (*((volatile unsigned int*)(0x422C9298UL))) +#define bM4_TMRA6_ECONR_ETEN8 (*((volatile unsigned int*)(0x422C929CUL))) +#define bM4_TMRA6_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422C9300UL))) +#define bM4_TMRA6_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422C9304UL))) +#define bM4_TMRA6_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422C9308UL))) +#define bM4_TMRA6_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422C9320UL))) +#define bM4_TMRA6_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422C9324UL))) +#define bM4_TMRA6_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422C9328UL))) +#define bM4_TMRA6_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422C9330UL))) +#define bM4_TMRA6_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422C9334UL))) +#define bM4_TMRA6_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422C9338UL))) +#define bM4_TMRA6_STFLR_CMPF1 (*((volatile unsigned int*)(0x422C9380UL))) +#define bM4_TMRA6_STFLR_CMPF2 (*((volatile unsigned int*)(0x422C9384UL))) +#define bM4_TMRA6_STFLR_CMPF3 (*((volatile unsigned int*)(0x422C9388UL))) +#define bM4_TMRA6_STFLR_CMPF4 (*((volatile unsigned int*)(0x422C938CUL))) +#define bM4_TMRA6_STFLR_CMPF5 (*((volatile unsigned int*)(0x422C9390UL))) +#define bM4_TMRA6_STFLR_CMPF6 (*((volatile unsigned int*)(0x422C9394UL))) +#define bM4_TMRA6_STFLR_CMPF7 (*((volatile unsigned int*)(0x422C9398UL))) +#define bM4_TMRA6_STFLR_CMPF8 (*((volatile unsigned int*)(0x422C939CUL))) +#define bM4_TMRA6_BCONR1_BEN (*((volatile unsigned int*)(0x422C9800UL))) +#define bM4_TMRA6_BCONR1_BSE0 (*((volatile unsigned int*)(0x422C9804UL))) +#define bM4_TMRA6_BCONR1_BSE1 (*((volatile unsigned int*)(0x422C9808UL))) +#define bM4_TMRA6_BCONR2_BEN (*((volatile unsigned int*)(0x422C9900UL))) +#define bM4_TMRA6_BCONR2_BSE0 (*((volatile unsigned int*)(0x422C9904UL))) +#define bM4_TMRA6_BCONR2_BSE1 (*((volatile unsigned int*)(0x422C9908UL))) +#define bM4_TMRA6_BCONR3_BEN (*((volatile unsigned int*)(0x422C9A00UL))) +#define bM4_TMRA6_BCONR3_BSE0 (*((volatile unsigned int*)(0x422C9A04UL))) +#define bM4_TMRA6_BCONR3_BSE1 (*((volatile unsigned int*)(0x422C9A08UL))) +#define bM4_TMRA6_BCONR4_BEN (*((volatile unsigned int*)(0x422C9B00UL))) +#define bM4_TMRA6_BCONR4_BSE0 (*((volatile unsigned int*)(0x422C9B04UL))) +#define bM4_TMRA6_BCONR4_BSE1 (*((volatile unsigned int*)(0x422C9B08UL))) +#define bM4_TMRA6_CCONR1_CAPMD (*((volatile unsigned int*)(0x422CA000UL))) +#define bM4_TMRA6_CCONR1_HICP0 (*((volatile unsigned int*)(0x422CA010UL))) +#define bM4_TMRA6_CCONR1_HICP1 (*((volatile unsigned int*)(0x422CA014UL))) +#define bM4_TMRA6_CCONR1_HICP2 (*((volatile unsigned int*)(0x422CA018UL))) +#define bM4_TMRA6_CCONR1_HICP3 (*((volatile unsigned int*)(0x422CA020UL))) +#define bM4_TMRA6_CCONR1_HICP4 (*((volatile unsigned int*)(0x422CA024UL))) +#define bM4_TMRA6_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422CA030UL))) +#define bM4_TMRA6_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422CA034UL))) +#define bM4_TMRA6_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422CA038UL))) +#define bM4_TMRA6_CCONR2_CAPMD (*((volatile unsigned int*)(0x422CA080UL))) +#define bM4_TMRA6_CCONR2_HICP0 (*((volatile unsigned int*)(0x422CA090UL))) +#define bM4_TMRA6_CCONR2_HICP1 (*((volatile unsigned int*)(0x422CA094UL))) +#define bM4_TMRA6_CCONR2_HICP2 (*((volatile unsigned int*)(0x422CA098UL))) +#define bM4_TMRA6_CCONR2_HICP3 (*((volatile unsigned int*)(0x422CA0A0UL))) +#define bM4_TMRA6_CCONR2_HICP4 (*((volatile unsigned int*)(0x422CA0A4UL))) +#define bM4_TMRA6_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422CA0B0UL))) +#define bM4_TMRA6_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422CA0B4UL))) +#define bM4_TMRA6_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422CA0B8UL))) +#define bM4_TMRA6_CCONR3_CAPMD (*((volatile unsigned int*)(0x422CA100UL))) +#define bM4_TMRA6_CCONR3_HICP0 (*((volatile unsigned int*)(0x422CA110UL))) +#define bM4_TMRA6_CCONR3_HICP1 (*((volatile unsigned int*)(0x422CA114UL))) +#define bM4_TMRA6_CCONR3_HICP2 (*((volatile unsigned int*)(0x422CA118UL))) +#define bM4_TMRA6_CCONR3_HICP3 (*((volatile unsigned int*)(0x422CA120UL))) +#define bM4_TMRA6_CCONR3_HICP4 (*((volatile unsigned int*)(0x422CA124UL))) +#define bM4_TMRA6_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422CA130UL))) +#define bM4_TMRA6_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422CA134UL))) +#define bM4_TMRA6_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422CA138UL))) +#define bM4_TMRA6_CCONR4_CAPMD (*((volatile unsigned int*)(0x422CA180UL))) +#define bM4_TMRA6_CCONR4_HICP0 (*((volatile unsigned int*)(0x422CA190UL))) +#define bM4_TMRA6_CCONR4_HICP1 (*((volatile unsigned int*)(0x422CA194UL))) +#define bM4_TMRA6_CCONR4_HICP2 (*((volatile unsigned int*)(0x422CA198UL))) +#define bM4_TMRA6_CCONR4_HICP3 (*((volatile unsigned int*)(0x422CA1A0UL))) +#define bM4_TMRA6_CCONR4_HICP4 (*((volatile unsigned int*)(0x422CA1A4UL))) +#define bM4_TMRA6_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422CA1B0UL))) +#define bM4_TMRA6_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422CA1B4UL))) +#define bM4_TMRA6_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422CA1B8UL))) +#define bM4_TMRA6_CCONR5_CAPMD (*((volatile unsigned int*)(0x422CA200UL))) +#define bM4_TMRA6_CCONR5_HICP0 (*((volatile unsigned int*)(0x422CA210UL))) +#define bM4_TMRA6_CCONR5_HICP1 (*((volatile unsigned int*)(0x422CA214UL))) +#define bM4_TMRA6_CCONR5_HICP2 (*((volatile unsigned int*)(0x422CA218UL))) +#define bM4_TMRA6_CCONR5_HICP3 (*((volatile unsigned int*)(0x422CA220UL))) +#define bM4_TMRA6_CCONR5_HICP4 (*((volatile unsigned int*)(0x422CA224UL))) +#define bM4_TMRA6_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422CA230UL))) +#define bM4_TMRA6_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422CA234UL))) +#define bM4_TMRA6_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422CA238UL))) +#define bM4_TMRA6_CCONR6_CAPMD (*((volatile unsigned int*)(0x422CA280UL))) +#define bM4_TMRA6_CCONR6_HICP0 (*((volatile unsigned int*)(0x422CA290UL))) +#define bM4_TMRA6_CCONR6_HICP1 (*((volatile unsigned int*)(0x422CA294UL))) +#define bM4_TMRA6_CCONR6_HICP2 (*((volatile unsigned int*)(0x422CA298UL))) +#define bM4_TMRA6_CCONR6_HICP3 (*((volatile unsigned int*)(0x422CA2A0UL))) +#define bM4_TMRA6_CCONR6_HICP4 (*((volatile unsigned int*)(0x422CA2A4UL))) +#define bM4_TMRA6_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422CA2B0UL))) +#define bM4_TMRA6_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422CA2B4UL))) +#define bM4_TMRA6_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422CA2B8UL))) +#define bM4_TMRA6_CCONR7_CAPMD (*((volatile unsigned int*)(0x422CA300UL))) +#define bM4_TMRA6_CCONR7_HICP0 (*((volatile unsigned int*)(0x422CA310UL))) +#define bM4_TMRA6_CCONR7_HICP1 (*((volatile unsigned int*)(0x422CA314UL))) +#define bM4_TMRA6_CCONR7_HICP2 (*((volatile unsigned int*)(0x422CA318UL))) +#define bM4_TMRA6_CCONR7_HICP3 (*((volatile unsigned int*)(0x422CA320UL))) +#define bM4_TMRA6_CCONR7_HICP4 (*((volatile unsigned int*)(0x422CA324UL))) +#define bM4_TMRA6_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422CA330UL))) +#define bM4_TMRA6_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422CA334UL))) +#define bM4_TMRA6_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422CA338UL))) +#define bM4_TMRA6_CCONR8_CAPMD (*((volatile unsigned int*)(0x422CA380UL))) +#define bM4_TMRA6_CCONR8_HICP0 (*((volatile unsigned int*)(0x422CA390UL))) +#define bM4_TMRA6_CCONR8_HICP1 (*((volatile unsigned int*)(0x422CA394UL))) +#define bM4_TMRA6_CCONR8_HICP2 (*((volatile unsigned int*)(0x422CA398UL))) +#define bM4_TMRA6_CCONR8_HICP3 (*((volatile unsigned int*)(0x422CA3A0UL))) +#define bM4_TMRA6_CCONR8_HICP4 (*((volatile unsigned int*)(0x422CA3A4UL))) +#define bM4_TMRA6_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422CA3B0UL))) +#define bM4_TMRA6_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422CA3B4UL))) +#define bM4_TMRA6_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422CA3B8UL))) +#define bM4_TMRA6_PCONR1_STAC0 (*((volatile unsigned int*)(0x422CA800UL))) +#define bM4_TMRA6_PCONR1_STAC1 (*((volatile unsigned int*)(0x422CA804UL))) +#define bM4_TMRA6_PCONR1_STPC0 (*((volatile unsigned int*)(0x422CA808UL))) +#define bM4_TMRA6_PCONR1_STPC1 (*((volatile unsigned int*)(0x422CA80CUL))) +#define bM4_TMRA6_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422CA810UL))) +#define bM4_TMRA6_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422CA814UL))) +#define bM4_TMRA6_PCONR1_PERC0 (*((volatile unsigned int*)(0x422CA818UL))) +#define bM4_TMRA6_PCONR1_PERC1 (*((volatile unsigned int*)(0x422CA81CUL))) +#define bM4_TMRA6_PCONR1_FORC0 (*((volatile unsigned int*)(0x422CA820UL))) +#define bM4_TMRA6_PCONR1_FORC1 (*((volatile unsigned int*)(0x422CA824UL))) +#define bM4_TMRA6_PCONR1_OUTEN (*((volatile unsigned int*)(0x422CA830UL))) +#define bM4_TMRA6_PCONR2_STAC0 (*((volatile unsigned int*)(0x422CA880UL))) +#define bM4_TMRA6_PCONR2_STAC1 (*((volatile unsigned int*)(0x422CA884UL))) +#define bM4_TMRA6_PCONR2_STPC0 (*((volatile unsigned int*)(0x422CA888UL))) +#define bM4_TMRA6_PCONR2_STPC1 (*((volatile unsigned int*)(0x422CA88CUL))) +#define bM4_TMRA6_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422CA890UL))) +#define bM4_TMRA6_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422CA894UL))) +#define bM4_TMRA6_PCONR2_PERC0 (*((volatile unsigned int*)(0x422CA898UL))) +#define bM4_TMRA6_PCONR2_PERC1 (*((volatile unsigned int*)(0x422CA89CUL))) +#define bM4_TMRA6_PCONR2_FORC0 (*((volatile unsigned int*)(0x422CA8A0UL))) +#define bM4_TMRA6_PCONR2_FORC1 (*((volatile unsigned int*)(0x422CA8A4UL))) +#define bM4_TMRA6_PCONR2_OUTEN (*((volatile unsigned int*)(0x422CA8B0UL))) +#define bM4_TMRA6_PCONR3_STAC0 (*((volatile unsigned int*)(0x422CA900UL))) +#define bM4_TMRA6_PCONR3_STAC1 (*((volatile unsigned int*)(0x422CA904UL))) +#define bM4_TMRA6_PCONR3_STPC0 (*((volatile unsigned int*)(0x422CA908UL))) +#define bM4_TMRA6_PCONR3_STPC1 (*((volatile unsigned int*)(0x422CA90CUL))) +#define bM4_TMRA6_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422CA910UL))) +#define bM4_TMRA6_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422CA914UL))) +#define bM4_TMRA6_PCONR3_PERC0 (*((volatile unsigned int*)(0x422CA918UL))) +#define bM4_TMRA6_PCONR3_PERC1 (*((volatile unsigned int*)(0x422CA91CUL))) +#define bM4_TMRA6_PCONR3_FORC0 (*((volatile unsigned int*)(0x422CA920UL))) +#define bM4_TMRA6_PCONR3_FORC1 (*((volatile unsigned int*)(0x422CA924UL))) +#define bM4_TMRA6_PCONR3_OUTEN (*((volatile unsigned int*)(0x422CA930UL))) +#define bM4_TMRA6_PCONR4_STAC0 (*((volatile unsigned int*)(0x422CA980UL))) +#define bM4_TMRA6_PCONR4_STAC1 (*((volatile unsigned int*)(0x422CA984UL))) +#define bM4_TMRA6_PCONR4_STPC0 (*((volatile unsigned int*)(0x422CA988UL))) +#define bM4_TMRA6_PCONR4_STPC1 (*((volatile unsigned int*)(0x422CA98CUL))) +#define bM4_TMRA6_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422CA990UL))) +#define bM4_TMRA6_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422CA994UL))) +#define bM4_TMRA6_PCONR4_PERC0 (*((volatile unsigned int*)(0x422CA998UL))) +#define bM4_TMRA6_PCONR4_PERC1 (*((volatile unsigned int*)(0x422CA99CUL))) +#define bM4_TMRA6_PCONR4_FORC0 (*((volatile unsigned int*)(0x422CA9A0UL))) +#define bM4_TMRA6_PCONR4_FORC1 (*((volatile unsigned int*)(0x422CA9A4UL))) +#define bM4_TMRA6_PCONR4_OUTEN (*((volatile unsigned int*)(0x422CA9B0UL))) +#define bM4_TMRA6_PCONR5_STAC0 (*((volatile unsigned int*)(0x422CAA00UL))) +#define bM4_TMRA6_PCONR5_STAC1 (*((volatile unsigned int*)(0x422CAA04UL))) +#define bM4_TMRA6_PCONR5_STPC0 (*((volatile unsigned int*)(0x422CAA08UL))) +#define bM4_TMRA6_PCONR5_STPC1 (*((volatile unsigned int*)(0x422CAA0CUL))) +#define bM4_TMRA6_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422CAA10UL))) +#define bM4_TMRA6_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422CAA14UL))) +#define bM4_TMRA6_PCONR5_PERC0 (*((volatile unsigned int*)(0x422CAA18UL))) +#define bM4_TMRA6_PCONR5_PERC1 (*((volatile unsigned int*)(0x422CAA1CUL))) +#define bM4_TMRA6_PCONR5_FORC0 (*((volatile unsigned int*)(0x422CAA20UL))) +#define bM4_TMRA6_PCONR5_FORC1 (*((volatile unsigned int*)(0x422CAA24UL))) +#define bM4_TMRA6_PCONR5_OUTEN (*((volatile unsigned int*)(0x422CAA30UL))) +#define bM4_TMRA6_PCONR6_STAC0 (*((volatile unsigned int*)(0x422CAA80UL))) +#define bM4_TMRA6_PCONR6_STAC1 (*((volatile unsigned int*)(0x422CAA84UL))) +#define bM4_TMRA6_PCONR6_STPC0 (*((volatile unsigned int*)(0x422CAA88UL))) +#define bM4_TMRA6_PCONR6_STPC1 (*((volatile unsigned int*)(0x422CAA8CUL))) +#define bM4_TMRA6_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422CAA90UL))) +#define bM4_TMRA6_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422CAA94UL))) +#define bM4_TMRA6_PCONR6_PERC0 (*((volatile unsigned int*)(0x422CAA98UL))) +#define bM4_TMRA6_PCONR6_PERC1 (*((volatile unsigned int*)(0x422CAA9CUL))) +#define bM4_TMRA6_PCONR6_FORC0 (*((volatile unsigned int*)(0x422CAAA0UL))) +#define bM4_TMRA6_PCONR6_FORC1 (*((volatile unsigned int*)(0x422CAAA4UL))) +#define bM4_TMRA6_PCONR6_OUTEN (*((volatile unsigned int*)(0x422CAAB0UL))) +#define bM4_TMRA6_PCONR7_STAC0 (*((volatile unsigned int*)(0x422CAB00UL))) +#define bM4_TMRA6_PCONR7_STAC1 (*((volatile unsigned int*)(0x422CAB04UL))) +#define bM4_TMRA6_PCONR7_STPC0 (*((volatile unsigned int*)(0x422CAB08UL))) +#define bM4_TMRA6_PCONR7_STPC1 (*((volatile unsigned int*)(0x422CAB0CUL))) +#define bM4_TMRA6_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422CAB10UL))) +#define bM4_TMRA6_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422CAB14UL))) +#define bM4_TMRA6_PCONR7_PERC0 (*((volatile unsigned int*)(0x422CAB18UL))) +#define bM4_TMRA6_PCONR7_PERC1 (*((volatile unsigned int*)(0x422CAB1CUL))) +#define bM4_TMRA6_PCONR7_FORC0 (*((volatile unsigned int*)(0x422CAB20UL))) +#define bM4_TMRA6_PCONR7_FORC1 (*((volatile unsigned int*)(0x422CAB24UL))) +#define bM4_TMRA6_PCONR7_OUTEN (*((volatile unsigned int*)(0x422CAB30UL))) +#define bM4_TMRA6_PCONR8_STAC0 (*((volatile unsigned int*)(0x422CAB80UL))) +#define bM4_TMRA6_PCONR8_STAC1 (*((volatile unsigned int*)(0x422CAB84UL))) +#define bM4_TMRA6_PCONR8_STPC0 (*((volatile unsigned int*)(0x422CAB88UL))) +#define bM4_TMRA6_PCONR8_STPC1 (*((volatile unsigned int*)(0x422CAB8CUL))) +#define bM4_TMRA6_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422CAB90UL))) +#define bM4_TMRA6_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422CAB94UL))) +#define bM4_TMRA6_PCONR8_PERC0 (*((volatile unsigned int*)(0x422CAB98UL))) +#define bM4_TMRA6_PCONR8_PERC1 (*((volatile unsigned int*)(0x422CAB9CUL))) +#define bM4_TMRA6_PCONR8_FORC0 (*((volatile unsigned int*)(0x422CABA0UL))) +#define bM4_TMRA6_PCONR8_FORC1 (*((volatile unsigned int*)(0x422CABA4UL))) +#define bM4_TMRA6_PCONR8_OUTEN (*((volatile unsigned int*)(0x422CABB0UL))) +#define bM4_TRNG_CR_EN (*((volatile unsigned int*)(0x42820000UL))) +#define bM4_TRNG_CR_RUN (*((volatile unsigned int*)(0x42820004UL))) +#define bM4_TRNG_MR_LOAD (*((volatile unsigned int*)(0x42820080UL))) +#define bM4_TRNG_MR_CNT0 (*((volatile unsigned int*)(0x42820088UL))) +#define bM4_TRNG_MR_CNT1 (*((volatile unsigned int*)(0x4282008CUL))) +#define bM4_TRNG_MR_CNT2 (*((volatile unsigned int*)(0x42820090UL))) +#define bM4_USART1_SR_PE (*((volatile unsigned int*)(0x423A0000UL))) +#define bM4_USART1_SR_FE (*((volatile unsigned int*)(0x423A0004UL))) +#define bM4_USART1_SR_ORE (*((volatile unsigned int*)(0x423A000CUL))) +#define bM4_USART1_SR_RXNE (*((volatile unsigned int*)(0x423A0014UL))) +#define bM4_USART1_SR_TC (*((volatile unsigned int*)(0x423A0018UL))) +#define bM4_USART1_SR_TXE (*((volatile unsigned int*)(0x423A001CUL))) +#define bM4_USART1_SR_RTOF (*((volatile unsigned int*)(0x423A0020UL))) +#define bM4_USART1_SR_MPB (*((volatile unsigned int*)(0x423A0040UL))) +#define bM4_USART1_DR_TDR0 (*((volatile unsigned int*)(0x423A0080UL))) +#define bM4_USART1_DR_TDR1 (*((volatile unsigned int*)(0x423A0084UL))) +#define bM4_USART1_DR_TDR2 (*((volatile unsigned int*)(0x423A0088UL))) +#define bM4_USART1_DR_TDR3 (*((volatile unsigned int*)(0x423A008CUL))) +#define bM4_USART1_DR_TDR4 (*((volatile unsigned int*)(0x423A0090UL))) +#define bM4_USART1_DR_TDR5 (*((volatile unsigned int*)(0x423A0094UL))) +#define bM4_USART1_DR_TDR6 (*((volatile unsigned int*)(0x423A0098UL))) +#define bM4_USART1_DR_TDR7 (*((volatile unsigned int*)(0x423A009CUL))) +#define bM4_USART1_DR_TDR8 (*((volatile unsigned int*)(0x423A00A0UL))) +#define bM4_USART1_DR_MPID (*((volatile unsigned int*)(0x423A00A4UL))) +#define bM4_USART1_DR_RDR0 (*((volatile unsigned int*)(0x423A00C0UL))) +#define bM4_USART1_DR_RDR1 (*((volatile unsigned int*)(0x423A00C4UL))) +#define bM4_USART1_DR_RDR2 (*((volatile unsigned int*)(0x423A00C8UL))) +#define bM4_USART1_DR_RDR3 (*((volatile unsigned int*)(0x423A00CCUL))) +#define bM4_USART1_DR_RDR4 (*((volatile unsigned int*)(0x423A00D0UL))) +#define bM4_USART1_DR_RDR5 (*((volatile unsigned int*)(0x423A00D4UL))) +#define bM4_USART1_DR_RDR6 (*((volatile unsigned int*)(0x423A00D8UL))) +#define bM4_USART1_DR_RDR7 (*((volatile unsigned int*)(0x423A00DCUL))) +#define bM4_USART1_DR_RDR8 (*((volatile unsigned int*)(0x423A00E0UL))) +#define bM4_USART1_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x423A0100UL))) +#define bM4_USART1_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x423A0104UL))) +#define bM4_USART1_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x423A0108UL))) +#define bM4_USART1_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x423A010CUL))) +#define bM4_USART1_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x423A0110UL))) +#define bM4_USART1_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x423A0114UL))) +#define bM4_USART1_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x423A0118UL))) +#define bM4_USART1_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x423A0120UL))) +#define bM4_USART1_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x423A0124UL))) +#define bM4_USART1_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x423A0128UL))) +#define bM4_USART1_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x423A012CUL))) +#define bM4_USART1_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x423A0130UL))) +#define bM4_USART1_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x423A0134UL))) +#define bM4_USART1_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x423A0138UL))) +#define bM4_USART1_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x423A013CUL))) +#define bM4_USART1_CR1_RTOE (*((volatile unsigned int*)(0x423A0180UL))) +#define bM4_USART1_CR1_RTOIE (*((volatile unsigned int*)(0x423A0184UL))) +#define bM4_USART1_CR1_RE (*((volatile unsigned int*)(0x423A0188UL))) +#define bM4_USART1_CR1_TE (*((volatile unsigned int*)(0x423A018CUL))) +#define bM4_USART1_CR1_SLME (*((volatile unsigned int*)(0x423A0190UL))) +#define bM4_USART1_CR1_RIE (*((volatile unsigned int*)(0x423A0194UL))) +#define bM4_USART1_CR1_TCIE (*((volatile unsigned int*)(0x423A0198UL))) +#define bM4_USART1_CR1_TXEIE (*((volatile unsigned int*)(0x423A019CUL))) +#define bM4_USART1_CR1_PS (*((volatile unsigned int*)(0x423A01A4UL))) +#define bM4_USART1_CR1_PCE (*((volatile unsigned int*)(0x423A01A8UL))) +#define bM4_USART1_CR1_M (*((volatile unsigned int*)(0x423A01B0UL))) +#define bM4_USART1_CR1_OVER8 (*((volatile unsigned int*)(0x423A01BCUL))) +#define bM4_USART1_CR1_CPE (*((volatile unsigned int*)(0x423A01C0UL))) +#define bM4_USART1_CR1_CFE (*((volatile unsigned int*)(0x423A01C4UL))) +#define bM4_USART1_CR1_CORE (*((volatile unsigned int*)(0x423A01CCUL))) +#define bM4_USART1_CR1_CRTOF (*((volatile unsigned int*)(0x423A01D0UL))) +#define bM4_USART1_CR1_MS (*((volatile unsigned int*)(0x423A01E0UL))) +#define bM4_USART1_CR1_ML (*((volatile unsigned int*)(0x423A01F0UL))) +#define bM4_USART1_CR1_FBME (*((volatile unsigned int*)(0x423A01F4UL))) +#define bM4_USART1_CR1_NFE (*((volatile unsigned int*)(0x423A01F8UL))) +#define bM4_USART1_CR1_SBS (*((volatile unsigned int*)(0x423A01FCUL))) +#define bM4_USART1_CR2_MPE (*((volatile unsigned int*)(0x423A0200UL))) +#define bM4_USART1_CR2_CLKC0 (*((volatile unsigned int*)(0x423A022CUL))) +#define bM4_USART1_CR2_CLKC1 (*((volatile unsigned int*)(0x423A0230UL))) +#define bM4_USART1_CR2_STOP (*((volatile unsigned int*)(0x423A0234UL))) +#define bM4_USART1_CR3_SCEN (*((volatile unsigned int*)(0x423A0294UL))) +#define bM4_USART1_CR3_CTSE (*((volatile unsigned int*)(0x423A02A4UL))) +#define bM4_USART1_CR3_BCN0 (*((volatile unsigned int*)(0x423A02D4UL))) +#define bM4_USART1_CR3_BCN1 (*((volatile unsigned int*)(0x423A02D8UL))) +#define bM4_USART1_CR3_BCN2 (*((volatile unsigned int*)(0x423A02DCUL))) +#define bM4_USART1_PR_PSC0 (*((volatile unsigned int*)(0x423A0300UL))) +#define bM4_USART1_PR_PSC1 (*((volatile unsigned int*)(0x423A0304UL))) +#define bM4_USART2_SR_PE (*((volatile unsigned int*)(0x423A8000UL))) +#define bM4_USART2_SR_FE (*((volatile unsigned int*)(0x423A8004UL))) +#define bM4_USART2_SR_ORE (*((volatile unsigned int*)(0x423A800CUL))) +#define bM4_USART2_SR_RXNE (*((volatile unsigned int*)(0x423A8014UL))) +#define bM4_USART2_SR_TC (*((volatile unsigned int*)(0x423A8018UL))) +#define bM4_USART2_SR_TXE (*((volatile unsigned int*)(0x423A801CUL))) +#define bM4_USART2_SR_RTOF (*((volatile unsigned int*)(0x423A8020UL))) +#define bM4_USART2_SR_MPB (*((volatile unsigned int*)(0x423A8040UL))) +#define bM4_USART2_DR_TDR0 (*((volatile unsigned int*)(0x423A8080UL))) +#define bM4_USART2_DR_TDR1 (*((volatile unsigned int*)(0x423A8084UL))) +#define bM4_USART2_DR_TDR2 (*((volatile unsigned int*)(0x423A8088UL))) +#define bM4_USART2_DR_TDR3 (*((volatile unsigned int*)(0x423A808CUL))) +#define bM4_USART2_DR_TDR4 (*((volatile unsigned int*)(0x423A8090UL))) +#define bM4_USART2_DR_TDR5 (*((volatile unsigned int*)(0x423A8094UL))) +#define bM4_USART2_DR_TDR6 (*((volatile unsigned int*)(0x423A8098UL))) +#define bM4_USART2_DR_TDR7 (*((volatile unsigned int*)(0x423A809CUL))) +#define bM4_USART2_DR_TDR8 (*((volatile unsigned int*)(0x423A80A0UL))) +#define bM4_USART2_DR_MPID (*((volatile unsigned int*)(0x423A80A4UL))) +#define bM4_USART2_DR_RDR0 (*((volatile unsigned int*)(0x423A80C0UL))) +#define bM4_USART2_DR_RDR1 (*((volatile unsigned int*)(0x423A80C4UL))) +#define bM4_USART2_DR_RDR2 (*((volatile unsigned int*)(0x423A80C8UL))) +#define bM4_USART2_DR_RDR3 (*((volatile unsigned int*)(0x423A80CCUL))) +#define bM4_USART2_DR_RDR4 (*((volatile unsigned int*)(0x423A80D0UL))) +#define bM4_USART2_DR_RDR5 (*((volatile unsigned int*)(0x423A80D4UL))) +#define bM4_USART2_DR_RDR6 (*((volatile unsigned int*)(0x423A80D8UL))) +#define bM4_USART2_DR_RDR7 (*((volatile unsigned int*)(0x423A80DCUL))) +#define bM4_USART2_DR_RDR8 (*((volatile unsigned int*)(0x423A80E0UL))) +#define bM4_USART2_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x423A8100UL))) +#define bM4_USART2_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x423A8104UL))) +#define bM4_USART2_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x423A8108UL))) +#define bM4_USART2_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x423A810CUL))) +#define bM4_USART2_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x423A8110UL))) +#define bM4_USART2_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x423A8114UL))) +#define bM4_USART2_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x423A8118UL))) +#define bM4_USART2_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x423A8120UL))) +#define bM4_USART2_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x423A8124UL))) +#define bM4_USART2_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x423A8128UL))) +#define bM4_USART2_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x423A812CUL))) +#define bM4_USART2_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x423A8130UL))) +#define bM4_USART2_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x423A8134UL))) +#define bM4_USART2_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x423A8138UL))) +#define bM4_USART2_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x423A813CUL))) +#define bM4_USART2_CR1_RTOE (*((volatile unsigned int*)(0x423A8180UL))) +#define bM4_USART2_CR1_RTOIE (*((volatile unsigned int*)(0x423A8184UL))) +#define bM4_USART2_CR1_RE (*((volatile unsigned int*)(0x423A8188UL))) +#define bM4_USART2_CR1_TE (*((volatile unsigned int*)(0x423A818CUL))) +#define bM4_USART2_CR1_SLME (*((volatile unsigned int*)(0x423A8190UL))) +#define bM4_USART2_CR1_RIE (*((volatile unsigned int*)(0x423A8194UL))) +#define bM4_USART2_CR1_TCIE (*((volatile unsigned int*)(0x423A8198UL))) +#define bM4_USART2_CR1_TXEIE (*((volatile unsigned int*)(0x423A819CUL))) +#define bM4_USART2_CR1_PS (*((volatile unsigned int*)(0x423A81A4UL))) +#define bM4_USART2_CR1_PCE (*((volatile unsigned int*)(0x423A81A8UL))) +#define bM4_USART2_CR1_M (*((volatile unsigned int*)(0x423A81B0UL))) +#define bM4_USART2_CR1_OVER8 (*((volatile unsigned int*)(0x423A81BCUL))) +#define bM4_USART2_CR1_CPE (*((volatile unsigned int*)(0x423A81C0UL))) +#define bM4_USART2_CR1_CFE (*((volatile unsigned int*)(0x423A81C4UL))) +#define bM4_USART2_CR1_CORE (*((volatile unsigned int*)(0x423A81CCUL))) +#define bM4_USART2_CR1_CRTOF (*((volatile unsigned int*)(0x423A81D0UL))) +#define bM4_USART2_CR1_MS (*((volatile unsigned int*)(0x423A81E0UL))) +#define bM4_USART2_CR1_ML (*((volatile unsigned int*)(0x423A81F0UL))) +#define bM4_USART2_CR1_FBME (*((volatile unsigned int*)(0x423A81F4UL))) +#define bM4_USART2_CR1_NFE (*((volatile unsigned int*)(0x423A81F8UL))) +#define bM4_USART2_CR1_SBS (*((volatile unsigned int*)(0x423A81FCUL))) +#define bM4_USART2_CR2_MPE (*((volatile unsigned int*)(0x423A8200UL))) +#define bM4_USART2_CR2_CLKC0 (*((volatile unsigned int*)(0x423A822CUL))) +#define bM4_USART2_CR2_CLKC1 (*((volatile unsigned int*)(0x423A8230UL))) +#define bM4_USART2_CR2_STOP (*((volatile unsigned int*)(0x423A8234UL))) +#define bM4_USART2_CR3_SCEN (*((volatile unsigned int*)(0x423A8294UL))) +#define bM4_USART2_CR3_CTSE (*((volatile unsigned int*)(0x423A82A4UL))) +#define bM4_USART2_CR3_BCN0 (*((volatile unsigned int*)(0x423A82D4UL))) +#define bM4_USART2_CR3_BCN1 (*((volatile unsigned int*)(0x423A82D8UL))) +#define bM4_USART2_CR3_BCN2 (*((volatile unsigned int*)(0x423A82DCUL))) +#define bM4_USART2_PR_PSC0 (*((volatile unsigned int*)(0x423A8300UL))) +#define bM4_USART2_PR_PSC1 (*((volatile unsigned int*)(0x423A8304UL))) +#define bM4_USART3_SR_PE (*((volatile unsigned int*)(0x42420000UL))) +#define bM4_USART3_SR_FE (*((volatile unsigned int*)(0x42420004UL))) +#define bM4_USART3_SR_ORE (*((volatile unsigned int*)(0x4242000CUL))) +#define bM4_USART3_SR_RXNE (*((volatile unsigned int*)(0x42420014UL))) +#define bM4_USART3_SR_TC (*((volatile unsigned int*)(0x42420018UL))) +#define bM4_USART3_SR_TXE (*((volatile unsigned int*)(0x4242001CUL))) +#define bM4_USART3_SR_RTOF (*((volatile unsigned int*)(0x42420020UL))) +#define bM4_USART3_SR_MPB (*((volatile unsigned int*)(0x42420040UL))) +#define bM4_USART3_DR_TDR0 (*((volatile unsigned int*)(0x42420080UL))) +#define bM4_USART3_DR_TDR1 (*((volatile unsigned int*)(0x42420084UL))) +#define bM4_USART3_DR_TDR2 (*((volatile unsigned int*)(0x42420088UL))) +#define bM4_USART3_DR_TDR3 (*((volatile unsigned int*)(0x4242008CUL))) +#define bM4_USART3_DR_TDR4 (*((volatile unsigned int*)(0x42420090UL))) +#define bM4_USART3_DR_TDR5 (*((volatile unsigned int*)(0x42420094UL))) +#define bM4_USART3_DR_TDR6 (*((volatile unsigned int*)(0x42420098UL))) +#define bM4_USART3_DR_TDR7 (*((volatile unsigned int*)(0x4242009CUL))) +#define bM4_USART3_DR_TDR8 (*((volatile unsigned int*)(0x424200A0UL))) +#define bM4_USART3_DR_MPID (*((volatile unsigned int*)(0x424200A4UL))) +#define bM4_USART3_DR_RDR0 (*((volatile unsigned int*)(0x424200C0UL))) +#define bM4_USART3_DR_RDR1 (*((volatile unsigned int*)(0x424200C4UL))) +#define bM4_USART3_DR_RDR2 (*((volatile unsigned int*)(0x424200C8UL))) +#define bM4_USART3_DR_RDR3 (*((volatile unsigned int*)(0x424200CCUL))) +#define bM4_USART3_DR_RDR4 (*((volatile unsigned int*)(0x424200D0UL))) +#define bM4_USART3_DR_RDR5 (*((volatile unsigned int*)(0x424200D4UL))) +#define bM4_USART3_DR_RDR6 (*((volatile unsigned int*)(0x424200D8UL))) +#define bM4_USART3_DR_RDR7 (*((volatile unsigned int*)(0x424200DCUL))) +#define bM4_USART3_DR_RDR8 (*((volatile unsigned int*)(0x424200E0UL))) +#define bM4_USART3_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x42420100UL))) +#define bM4_USART3_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x42420104UL))) +#define bM4_USART3_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x42420108UL))) +#define bM4_USART3_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x4242010CUL))) +#define bM4_USART3_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x42420110UL))) +#define bM4_USART3_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x42420114UL))) +#define bM4_USART3_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x42420118UL))) +#define bM4_USART3_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x42420120UL))) +#define bM4_USART3_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x42420124UL))) +#define bM4_USART3_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x42420128UL))) +#define bM4_USART3_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x4242012CUL))) +#define bM4_USART3_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x42420130UL))) +#define bM4_USART3_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x42420134UL))) +#define bM4_USART3_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x42420138UL))) +#define bM4_USART3_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x4242013CUL))) +#define bM4_USART3_CR1_RTOE (*((volatile unsigned int*)(0x42420180UL))) +#define bM4_USART3_CR1_RTOIE (*((volatile unsigned int*)(0x42420184UL))) +#define bM4_USART3_CR1_RE (*((volatile unsigned int*)(0x42420188UL))) +#define bM4_USART3_CR1_TE (*((volatile unsigned int*)(0x4242018CUL))) +#define bM4_USART3_CR1_SLME (*((volatile unsigned int*)(0x42420190UL))) +#define bM4_USART3_CR1_RIE (*((volatile unsigned int*)(0x42420194UL))) +#define bM4_USART3_CR1_TCIE (*((volatile unsigned int*)(0x42420198UL))) +#define bM4_USART3_CR1_TXEIE (*((volatile unsigned int*)(0x4242019CUL))) +#define bM4_USART3_CR1_PS (*((volatile unsigned int*)(0x424201A4UL))) +#define bM4_USART3_CR1_PCE (*((volatile unsigned int*)(0x424201A8UL))) +#define bM4_USART3_CR1_M (*((volatile unsigned int*)(0x424201B0UL))) +#define bM4_USART3_CR1_OVER8 (*((volatile unsigned int*)(0x424201BCUL))) +#define bM4_USART3_CR1_CPE (*((volatile unsigned int*)(0x424201C0UL))) +#define bM4_USART3_CR1_CFE (*((volatile unsigned int*)(0x424201C4UL))) +#define bM4_USART3_CR1_CORE (*((volatile unsigned int*)(0x424201CCUL))) +#define bM4_USART3_CR1_CRTOF (*((volatile unsigned int*)(0x424201D0UL))) +#define bM4_USART3_CR1_MS (*((volatile unsigned int*)(0x424201E0UL))) +#define bM4_USART3_CR1_ML (*((volatile unsigned int*)(0x424201F0UL))) +#define bM4_USART3_CR1_FBME (*((volatile unsigned int*)(0x424201F4UL))) +#define bM4_USART3_CR1_NFE (*((volatile unsigned int*)(0x424201F8UL))) +#define bM4_USART3_CR1_SBS (*((volatile unsigned int*)(0x424201FCUL))) +#define bM4_USART3_CR2_MPE (*((volatile unsigned int*)(0x42420200UL))) +#define bM4_USART3_CR2_CLKC0 (*((volatile unsigned int*)(0x4242022CUL))) +#define bM4_USART3_CR2_CLKC1 (*((volatile unsigned int*)(0x42420230UL))) +#define bM4_USART3_CR2_STOP (*((volatile unsigned int*)(0x42420234UL))) +#define bM4_USART3_CR3_SCEN (*((volatile unsigned int*)(0x42420294UL))) +#define bM4_USART3_CR3_CTSE (*((volatile unsigned int*)(0x424202A4UL))) +#define bM4_USART3_CR3_BCN0 (*((volatile unsigned int*)(0x424202D4UL))) +#define bM4_USART3_CR3_BCN1 (*((volatile unsigned int*)(0x424202D8UL))) +#define bM4_USART3_CR3_BCN2 (*((volatile unsigned int*)(0x424202DCUL))) +#define bM4_USART3_PR_PSC0 (*((volatile unsigned int*)(0x42420300UL))) +#define bM4_USART3_PR_PSC1 (*((volatile unsigned int*)(0x42420304UL))) +#define bM4_USART4_SR_PE (*((volatile unsigned int*)(0x42428000UL))) +#define bM4_USART4_SR_FE (*((volatile unsigned int*)(0x42428004UL))) +#define bM4_USART4_SR_ORE (*((volatile unsigned int*)(0x4242800CUL))) +#define bM4_USART4_SR_RXNE (*((volatile unsigned int*)(0x42428014UL))) +#define bM4_USART4_SR_TC (*((volatile unsigned int*)(0x42428018UL))) +#define bM4_USART4_SR_TXE (*((volatile unsigned int*)(0x4242801CUL))) +#define bM4_USART4_SR_RTOF (*((volatile unsigned int*)(0x42428020UL))) +#define bM4_USART4_SR_MPB (*((volatile unsigned int*)(0x42428040UL))) +#define bM4_USART4_DR_TDR0 (*((volatile unsigned int*)(0x42428080UL))) +#define bM4_USART4_DR_TDR1 (*((volatile unsigned int*)(0x42428084UL))) +#define bM4_USART4_DR_TDR2 (*((volatile unsigned int*)(0x42428088UL))) +#define bM4_USART4_DR_TDR3 (*((volatile unsigned int*)(0x4242808CUL))) +#define bM4_USART4_DR_TDR4 (*((volatile unsigned int*)(0x42428090UL))) +#define bM4_USART4_DR_TDR5 (*((volatile unsigned int*)(0x42428094UL))) +#define bM4_USART4_DR_TDR6 (*((volatile unsigned int*)(0x42428098UL))) +#define bM4_USART4_DR_TDR7 (*((volatile unsigned int*)(0x4242809CUL))) +#define bM4_USART4_DR_TDR8 (*((volatile unsigned int*)(0x424280A0UL))) +#define bM4_USART4_DR_MPID (*((volatile unsigned int*)(0x424280A4UL))) +#define bM4_USART4_DR_RDR0 (*((volatile unsigned int*)(0x424280C0UL))) +#define bM4_USART4_DR_RDR1 (*((volatile unsigned int*)(0x424280C4UL))) +#define bM4_USART4_DR_RDR2 (*((volatile unsigned int*)(0x424280C8UL))) +#define bM4_USART4_DR_RDR3 (*((volatile unsigned int*)(0x424280CCUL))) +#define bM4_USART4_DR_RDR4 (*((volatile unsigned int*)(0x424280D0UL))) +#define bM4_USART4_DR_RDR5 (*((volatile unsigned int*)(0x424280D4UL))) +#define bM4_USART4_DR_RDR6 (*((volatile unsigned int*)(0x424280D8UL))) +#define bM4_USART4_DR_RDR7 (*((volatile unsigned int*)(0x424280DCUL))) +#define bM4_USART4_DR_RDR8 (*((volatile unsigned int*)(0x424280E0UL))) +#define bM4_USART4_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x42428100UL))) +#define bM4_USART4_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x42428104UL))) +#define bM4_USART4_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x42428108UL))) +#define bM4_USART4_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x4242810CUL))) +#define bM4_USART4_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x42428110UL))) +#define bM4_USART4_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x42428114UL))) +#define bM4_USART4_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x42428118UL))) +#define bM4_USART4_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x42428120UL))) +#define bM4_USART4_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x42428124UL))) +#define bM4_USART4_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x42428128UL))) +#define bM4_USART4_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x4242812CUL))) +#define bM4_USART4_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x42428130UL))) +#define bM4_USART4_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x42428134UL))) +#define bM4_USART4_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x42428138UL))) +#define bM4_USART4_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x4242813CUL))) +#define bM4_USART4_CR1_RTOE (*((volatile unsigned int*)(0x42428180UL))) +#define bM4_USART4_CR1_RTOIE (*((volatile unsigned int*)(0x42428184UL))) +#define bM4_USART4_CR1_RE (*((volatile unsigned int*)(0x42428188UL))) +#define bM4_USART4_CR1_TE (*((volatile unsigned int*)(0x4242818CUL))) +#define bM4_USART4_CR1_SLME (*((volatile unsigned int*)(0x42428190UL))) +#define bM4_USART4_CR1_RIE (*((volatile unsigned int*)(0x42428194UL))) +#define bM4_USART4_CR1_TCIE (*((volatile unsigned int*)(0x42428198UL))) +#define bM4_USART4_CR1_TXEIE (*((volatile unsigned int*)(0x4242819CUL))) +#define bM4_USART4_CR1_PS (*((volatile unsigned int*)(0x424281A4UL))) +#define bM4_USART4_CR1_PCE (*((volatile unsigned int*)(0x424281A8UL))) +#define bM4_USART4_CR1_M (*((volatile unsigned int*)(0x424281B0UL))) +#define bM4_USART4_CR1_OVER8 (*((volatile unsigned int*)(0x424281BCUL))) +#define bM4_USART4_CR1_CPE (*((volatile unsigned int*)(0x424281C0UL))) +#define bM4_USART4_CR1_CFE (*((volatile unsigned int*)(0x424281C4UL))) +#define bM4_USART4_CR1_CORE (*((volatile unsigned int*)(0x424281CCUL))) +#define bM4_USART4_CR1_CRTOF (*((volatile unsigned int*)(0x424281D0UL))) +#define bM4_USART4_CR1_MS (*((volatile unsigned int*)(0x424281E0UL))) +#define bM4_USART4_CR1_ML (*((volatile unsigned int*)(0x424281F0UL))) +#define bM4_USART4_CR1_FBME (*((volatile unsigned int*)(0x424281F4UL))) +#define bM4_USART4_CR1_NFE (*((volatile unsigned int*)(0x424281F8UL))) +#define bM4_USART4_CR1_SBS (*((volatile unsigned int*)(0x424281FCUL))) +#define bM4_USART4_CR2_MPE (*((volatile unsigned int*)(0x42428200UL))) +#define bM4_USART4_CR2_CLKC0 (*((volatile unsigned int*)(0x4242822CUL))) +#define bM4_USART4_CR2_CLKC1 (*((volatile unsigned int*)(0x42428230UL))) +#define bM4_USART4_CR2_STOP (*((volatile unsigned int*)(0x42428234UL))) +#define bM4_USART4_CR3_SCEN (*((volatile unsigned int*)(0x42428294UL))) +#define bM4_USART4_CR3_CTSE (*((volatile unsigned int*)(0x424282A4UL))) +#define bM4_USART4_CR3_BCN0 (*((volatile unsigned int*)(0x424282D4UL))) +#define bM4_USART4_CR3_BCN1 (*((volatile unsigned int*)(0x424282D8UL))) +#define bM4_USART4_CR3_BCN2 (*((volatile unsigned int*)(0x424282DCUL))) +#define bM4_USART4_PR_PSC0 (*((volatile unsigned int*)(0x42428300UL))) +#define bM4_USART4_PR_PSC1 (*((volatile unsigned int*)(0x42428304UL))) +#define bM4_USBFS_USBFS_GVBUSCFG_VBUSOVEN (*((volatile unsigned int*)(0x43800018UL))) +#define bM4_USBFS_USBFS_GVBUSCFG_VBUSVAL (*((volatile unsigned int*)(0x4380001CUL))) +#define bM4_USBFS_GAHBCFG_GINTMSK (*((volatile unsigned int*)(0x43800100UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN0 (*((volatile unsigned int*)(0x43800104UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN1 (*((volatile unsigned int*)(0x43800108UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN2 (*((volatile unsigned int*)(0x4380010CUL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN3 (*((volatile unsigned int*)(0x43800110UL))) +#define bM4_USBFS_GAHBCFG_DMAEN (*((volatile unsigned int*)(0x43800114UL))) +#define bM4_USBFS_GAHBCFG_TXFELVL (*((volatile unsigned int*)(0x4380011CUL))) +#define bM4_USBFS_GAHBCFG_PTXFELVL (*((volatile unsigned int*)(0x43800120UL))) +#define bM4_USBFS_GUSBCFG_TOCAL0 (*((volatile unsigned int*)(0x43800180UL))) +#define bM4_USBFS_GUSBCFG_TOCAL1 (*((volatile unsigned int*)(0x43800184UL))) +#define bM4_USBFS_GUSBCFG_TOCAL2 (*((volatile unsigned int*)(0x43800188UL))) +#define bM4_USBFS_GUSBCFG_PHYSEL (*((volatile unsigned int*)(0x43800198UL))) +#define bM4_USBFS_GUSBCFG_TRDT0 (*((volatile unsigned int*)(0x438001A8UL))) +#define bM4_USBFS_GUSBCFG_TRDT1 (*((volatile unsigned int*)(0x438001ACUL))) +#define bM4_USBFS_GUSBCFG_TRDT2 (*((volatile unsigned int*)(0x438001B0UL))) +#define bM4_USBFS_GUSBCFG_TRDT3 (*((volatile unsigned int*)(0x438001B4UL))) +#define bM4_USBFS_GUSBCFG_FHMOD (*((volatile unsigned int*)(0x438001F4UL))) +#define bM4_USBFS_GUSBCFG_FDMOD (*((volatile unsigned int*)(0x438001F8UL))) +#define bM4_USBFS_GRSTCTL_CSRST (*((volatile unsigned int*)(0x43800200UL))) +#define bM4_USBFS_GRSTCTL_HSRST (*((volatile unsigned int*)(0x43800204UL))) +#define bM4_USBFS_GRSTCTL_FCRST (*((volatile unsigned int*)(0x43800208UL))) +#define bM4_USBFS_GRSTCTL_RXFFLSH (*((volatile unsigned int*)(0x43800210UL))) +#define bM4_USBFS_GRSTCTL_TXFFLSH (*((volatile unsigned int*)(0x43800214UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM0 (*((volatile unsigned int*)(0x43800218UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM1 (*((volatile unsigned int*)(0x4380021CUL))) +#define bM4_USBFS_GRSTCTL_TXFNUM2 (*((volatile unsigned int*)(0x43800220UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM3 (*((volatile unsigned int*)(0x43800224UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM4 (*((volatile unsigned int*)(0x43800228UL))) +#define bM4_USBFS_GRSTCTL_DMAREQ (*((volatile unsigned int*)(0x43800278UL))) +#define bM4_USBFS_GRSTCTL_AHBIDL (*((volatile unsigned int*)(0x4380027CUL))) +#define bM4_USBFS_GINTSTS_CMOD (*((volatile unsigned int*)(0x43800280UL))) +#define bM4_USBFS_GINTSTS_MMIS (*((volatile unsigned int*)(0x43800284UL))) +#define bM4_USBFS_GINTSTS_SOF (*((volatile unsigned int*)(0x4380028CUL))) +#define bM4_USBFS_GINTSTS_RXFNE (*((volatile unsigned int*)(0x43800290UL))) +#define bM4_USBFS_GINTSTS_NPTXFE (*((volatile unsigned int*)(0x43800294UL))) +#define bM4_USBFS_GINTSTS_GINAKEFF (*((volatile unsigned int*)(0x43800298UL))) +#define bM4_USBFS_GINTSTS_GONAKEFF (*((volatile unsigned int*)(0x4380029CUL))) +#define bM4_USBFS_GINTSTS_ESUSP (*((volatile unsigned int*)(0x438002A8UL))) +#define bM4_USBFS_GINTSTS_USBSUSP (*((volatile unsigned int*)(0x438002ACUL))) +#define bM4_USBFS_GINTSTS_USBRST (*((volatile unsigned int*)(0x438002B0UL))) +#define bM4_USBFS_GINTSTS_ENUMDNE (*((volatile unsigned int*)(0x438002B4UL))) +#define bM4_USBFS_GINTSTS_ISOODRP (*((volatile unsigned int*)(0x438002B8UL))) +#define bM4_USBFS_GINTSTS_EOPF (*((volatile unsigned int*)(0x438002BCUL))) +#define bM4_USBFS_GINTSTS_IEPINT (*((volatile unsigned int*)(0x438002C8UL))) +#define bM4_USBFS_GINTSTS_OEPINT (*((volatile unsigned int*)(0x438002CCUL))) +#define bM4_USBFS_GINTSTS_IISOIXFR (*((volatile unsigned int*)(0x438002D0UL))) +#define bM4_USBFS_GINTSTS_IPXFR_INCOMPISOOUT (*((volatile unsigned int*)(0x438002D4UL))) +#define bM4_USBFS_GINTSTS_DATAFSUSP (*((volatile unsigned int*)(0x438002D8UL))) +#define bM4_USBFS_GINTSTS_HPRTINT (*((volatile unsigned int*)(0x438002E0UL))) +#define bM4_USBFS_GINTSTS_HCINT (*((volatile unsigned int*)(0x438002E4UL))) +#define bM4_USBFS_GINTSTS_PTXFE (*((volatile unsigned int*)(0x438002E8UL))) +#define bM4_USBFS_GINTSTS_CIDSCHG (*((volatile unsigned int*)(0x438002F0UL))) +#define bM4_USBFS_GINTSTS_DISCINT (*((volatile unsigned int*)(0x438002F4UL))) +#define bM4_USBFS_GINTSTS_VBUSVINT (*((volatile unsigned int*)(0x438002F8UL))) +#define bM4_USBFS_GINTSTS_WKUINT (*((volatile unsigned int*)(0x438002FCUL))) +#define bM4_USBFS_GINTMSK_MMISM (*((volatile unsigned int*)(0x43800304UL))) +#define bM4_USBFS_GINTMSK_SOFM (*((volatile unsigned int*)(0x4380030CUL))) +#define bM4_USBFS_GINTMSK_RXFNEM (*((volatile unsigned int*)(0x43800310UL))) +#define bM4_USBFS_GINTMSK_NPTXFEM (*((volatile unsigned int*)(0x43800314UL))) +#define bM4_USBFS_GINTMSK_GINAKEFFM (*((volatile unsigned int*)(0x43800318UL))) +#define bM4_USBFS_GINTMSK_GONAKEFFM (*((volatile unsigned int*)(0x4380031CUL))) +#define bM4_USBFS_GINTMSK_ESUSPM (*((volatile unsigned int*)(0x43800328UL))) +#define bM4_USBFS_GINTMSK_USBSUSPM (*((volatile unsigned int*)(0x4380032CUL))) +#define bM4_USBFS_GINTMSK_USBRSTM (*((volatile unsigned int*)(0x43800330UL))) +#define bM4_USBFS_GINTMSK_ENUMDNEM (*((volatile unsigned int*)(0x43800334UL))) +#define bM4_USBFS_GINTMSK_ISOODRPM (*((volatile unsigned int*)(0x43800338UL))) +#define bM4_USBFS_GINTMSK_EOPFM (*((volatile unsigned int*)(0x4380033CUL))) +#define bM4_USBFS_GINTMSK_IEPIM (*((volatile unsigned int*)(0x43800348UL))) +#define bM4_USBFS_GINTMSK_OEPIM (*((volatile unsigned int*)(0x4380034CUL))) +#define bM4_USBFS_GINTMSK_IISOIXFRM (*((volatile unsigned int*)(0x43800350UL))) +#define bM4_USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM (*((volatile unsigned int*)(0x43800354UL))) +#define bM4_USBFS_GINTMSK_DATAFSUSPM (*((volatile unsigned int*)(0x43800358UL))) +#define bM4_USBFS_GINTMSK_HPRTIM (*((volatile unsigned int*)(0x43800360UL))) +#define bM4_USBFS_GINTMSK_HCIM (*((volatile unsigned int*)(0x43800364UL))) +#define bM4_USBFS_GINTMSK_PTXFEM (*((volatile unsigned int*)(0x43800368UL))) +#define bM4_USBFS_GINTMSK_CIDSCHGM (*((volatile unsigned int*)(0x43800370UL))) +#define bM4_USBFS_GINTMSK_DISCIM (*((volatile unsigned int*)(0x43800374UL))) +#define bM4_USBFS_GINTMSK_VBUSVIM (*((volatile unsigned int*)(0x43800378UL))) +#define bM4_USBFS_GINTMSK_WKUIM (*((volatile unsigned int*)(0x4380037CUL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM0 (*((volatile unsigned int*)(0x43800380UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM1 (*((volatile unsigned int*)(0x43800384UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM2 (*((volatile unsigned int*)(0x43800388UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM3 (*((volatile unsigned int*)(0x4380038CUL))) +#define bM4_USBFS_GRXSTSR_BCNT0 (*((volatile unsigned int*)(0x43800390UL))) +#define bM4_USBFS_GRXSTSR_BCNT1 (*((volatile unsigned int*)(0x43800394UL))) +#define bM4_USBFS_GRXSTSR_BCNT2 (*((volatile unsigned int*)(0x43800398UL))) +#define bM4_USBFS_GRXSTSR_BCNT3 (*((volatile unsigned int*)(0x4380039CUL))) +#define bM4_USBFS_GRXSTSR_BCNT4 (*((volatile unsigned int*)(0x438003A0UL))) +#define bM4_USBFS_GRXSTSR_BCNT5 (*((volatile unsigned int*)(0x438003A4UL))) +#define bM4_USBFS_GRXSTSR_BCNT6 (*((volatile unsigned int*)(0x438003A8UL))) +#define bM4_USBFS_GRXSTSR_BCNT7 (*((volatile unsigned int*)(0x438003ACUL))) +#define bM4_USBFS_GRXSTSR_BCNT8 (*((volatile unsigned int*)(0x438003B0UL))) +#define bM4_USBFS_GRXSTSR_BCNT9 (*((volatile unsigned int*)(0x438003B4UL))) +#define bM4_USBFS_GRXSTSR_BCNT10 (*((volatile unsigned int*)(0x438003B8UL))) +#define bM4_USBFS_GRXSTSR_DPID0 (*((volatile unsigned int*)(0x438003BCUL))) +#define bM4_USBFS_GRXSTSR_DPID1 (*((volatile unsigned int*)(0x438003C0UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS0 (*((volatile unsigned int*)(0x438003C4UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS1 (*((volatile unsigned int*)(0x438003C8UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS2 (*((volatile unsigned int*)(0x438003CCUL))) +#define bM4_USBFS_GRXSTSR_PKTSTS3 (*((volatile unsigned int*)(0x438003D0UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM0 (*((volatile unsigned int*)(0x43800400UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM1 (*((volatile unsigned int*)(0x43800404UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM2 (*((volatile unsigned int*)(0x43800408UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM3 (*((volatile unsigned int*)(0x4380040CUL))) +#define bM4_USBFS_GRXSTSP_BCNT0 (*((volatile unsigned int*)(0x43800410UL))) +#define bM4_USBFS_GRXSTSP_BCNT1 (*((volatile unsigned int*)(0x43800414UL))) +#define bM4_USBFS_GRXSTSP_BCNT2 (*((volatile unsigned int*)(0x43800418UL))) +#define bM4_USBFS_GRXSTSP_BCNT3 (*((volatile unsigned int*)(0x4380041CUL))) +#define bM4_USBFS_GRXSTSP_BCNT4 (*((volatile unsigned int*)(0x43800420UL))) +#define bM4_USBFS_GRXSTSP_BCNT5 (*((volatile unsigned int*)(0x43800424UL))) +#define bM4_USBFS_GRXSTSP_BCNT6 (*((volatile unsigned int*)(0x43800428UL))) +#define bM4_USBFS_GRXSTSP_BCNT7 (*((volatile unsigned int*)(0x4380042CUL))) +#define bM4_USBFS_GRXSTSP_BCNT8 (*((volatile unsigned int*)(0x43800430UL))) +#define bM4_USBFS_GRXSTSP_BCNT9 (*((volatile unsigned int*)(0x43800434UL))) +#define bM4_USBFS_GRXSTSP_BCNT10 (*((volatile unsigned int*)(0x43800438UL))) +#define bM4_USBFS_GRXSTSP_DPID0 (*((volatile unsigned int*)(0x4380043CUL))) +#define bM4_USBFS_GRXSTSP_DPID1 (*((volatile unsigned int*)(0x43800440UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS0 (*((volatile unsigned int*)(0x43800444UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS1 (*((volatile unsigned int*)(0x43800448UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS2 (*((volatile unsigned int*)(0x4380044CUL))) +#define bM4_USBFS_GRXSTSP_PKTSTS3 (*((volatile unsigned int*)(0x43800450UL))) +#define bM4_USBFS_GRXFSIZ_RXFD0 (*((volatile unsigned int*)(0x43800480UL))) +#define bM4_USBFS_GRXFSIZ_RXFD1 (*((volatile unsigned int*)(0x43800484UL))) +#define bM4_USBFS_GRXFSIZ_RXFD2 (*((volatile unsigned int*)(0x43800488UL))) +#define bM4_USBFS_GRXFSIZ_RXFD3 (*((volatile unsigned int*)(0x4380048CUL))) +#define bM4_USBFS_GRXFSIZ_RXFD4 (*((volatile unsigned int*)(0x43800490UL))) +#define bM4_USBFS_GRXFSIZ_RXFD5 (*((volatile unsigned int*)(0x43800494UL))) +#define bM4_USBFS_GRXFSIZ_RXFD6 (*((volatile unsigned int*)(0x43800498UL))) +#define bM4_USBFS_GRXFSIZ_RXFD7 (*((volatile unsigned int*)(0x4380049CUL))) +#define bM4_USBFS_GRXFSIZ_RXFD8 (*((volatile unsigned int*)(0x438004A0UL))) +#define bM4_USBFS_GRXFSIZ_RXFD9 (*((volatile unsigned int*)(0x438004A4UL))) +#define bM4_USBFS_GRXFSIZ_RXFD10 (*((volatile unsigned int*)(0x438004A8UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA0 (*((volatile unsigned int*)(0x43800500UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA1 (*((volatile unsigned int*)(0x43800504UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA2 (*((volatile unsigned int*)(0x43800508UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA3 (*((volatile unsigned int*)(0x4380050CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA4 (*((volatile unsigned int*)(0x43800510UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA5 (*((volatile unsigned int*)(0x43800514UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA6 (*((volatile unsigned int*)(0x43800518UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA7 (*((volatile unsigned int*)(0x4380051CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA8 (*((volatile unsigned int*)(0x43800520UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA9 (*((volatile unsigned int*)(0x43800524UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA10 (*((volatile unsigned int*)(0x43800528UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA11 (*((volatile unsigned int*)(0x4380052CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA12 (*((volatile unsigned int*)(0x43800530UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA13 (*((volatile unsigned int*)(0x43800534UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA14 (*((volatile unsigned int*)(0x43800538UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA15 (*((volatile unsigned int*)(0x4380053CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD0 (*((volatile unsigned int*)(0x43800540UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD1 (*((volatile unsigned int*)(0x43800544UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD2 (*((volatile unsigned int*)(0x43800548UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD3 (*((volatile unsigned int*)(0x4380054CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD4 (*((volatile unsigned int*)(0x43800550UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD5 (*((volatile unsigned int*)(0x43800554UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD6 (*((volatile unsigned int*)(0x43800558UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD7 (*((volatile unsigned int*)(0x4380055CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD8 (*((volatile unsigned int*)(0x43800560UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD9 (*((volatile unsigned int*)(0x43800564UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD10 (*((volatile unsigned int*)(0x43800568UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD11 (*((volatile unsigned int*)(0x4380056CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD12 (*((volatile unsigned int*)(0x43800570UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD13 (*((volatile unsigned int*)(0x43800574UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD14 (*((volatile unsigned int*)(0x43800578UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD15 (*((volatile unsigned int*)(0x4380057CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV0 (*((volatile unsigned int*)(0x43800580UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV1 (*((volatile unsigned int*)(0x43800584UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV2 (*((volatile unsigned int*)(0x43800588UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV3 (*((volatile unsigned int*)(0x4380058CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV4 (*((volatile unsigned int*)(0x43800590UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV5 (*((volatile unsigned int*)(0x43800594UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV6 (*((volatile unsigned int*)(0x43800598UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV7 (*((volatile unsigned int*)(0x4380059CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV8 (*((volatile unsigned int*)(0x438005A0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV9 (*((volatile unsigned int*)(0x438005A4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV10 (*((volatile unsigned int*)(0x438005A8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV11 (*((volatile unsigned int*)(0x438005ACUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV12 (*((volatile unsigned int*)(0x438005B0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV13 (*((volatile unsigned int*)(0x438005B4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV14 (*((volatile unsigned int*)(0x438005B8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV15 (*((volatile unsigned int*)(0x438005BCUL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV0 (*((volatile unsigned int*)(0x438005C0UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV1 (*((volatile unsigned int*)(0x438005C4UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV2 (*((volatile unsigned int*)(0x438005C8UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV3 (*((volatile unsigned int*)(0x438005CCUL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV4 (*((volatile unsigned int*)(0x438005D0UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV5 (*((volatile unsigned int*)(0x438005D4UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV6 (*((volatile unsigned int*)(0x438005D8UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV7 (*((volatile unsigned int*)(0x438005DCUL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP0 (*((volatile unsigned int*)(0x438005E0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP1 (*((volatile unsigned int*)(0x438005E4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP2 (*((volatile unsigned int*)(0x438005E8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP3 (*((volatile unsigned int*)(0x438005ECUL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP4 (*((volatile unsigned int*)(0x438005F0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP5 (*((volatile unsigned int*)(0x438005F4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP6 (*((volatile unsigned int*)(0x438005F8UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA0 (*((volatile unsigned int*)(0x43802000UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA1 (*((volatile unsigned int*)(0x43802004UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA2 (*((volatile unsigned int*)(0x43802008UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA3 (*((volatile unsigned int*)(0x4380200CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA4 (*((volatile unsigned int*)(0x43802010UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA5 (*((volatile unsigned int*)(0x43802014UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA6 (*((volatile unsigned int*)(0x43802018UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA7 (*((volatile unsigned int*)(0x4380201CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA8 (*((volatile unsigned int*)(0x43802020UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA9 (*((volatile unsigned int*)(0x43802024UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA10 (*((volatile unsigned int*)(0x43802028UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA11 (*((volatile unsigned int*)(0x4380202CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD0 (*((volatile unsigned int*)(0x43802040UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD1 (*((volatile unsigned int*)(0x43802044UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD2 (*((volatile unsigned int*)(0x43802048UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD3 (*((volatile unsigned int*)(0x4380204CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD4 (*((volatile unsigned int*)(0x43802050UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD5 (*((volatile unsigned int*)(0x43802054UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD6 (*((volatile unsigned int*)(0x43802058UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD7 (*((volatile unsigned int*)(0x4380205CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD8 (*((volatile unsigned int*)(0x43802060UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD9 (*((volatile unsigned int*)(0x43802064UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD10 (*((volatile unsigned int*)(0x43802068UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA0 (*((volatile unsigned int*)(0x43802080UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA1 (*((volatile unsigned int*)(0x43802084UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA2 (*((volatile unsigned int*)(0x43802088UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA3 (*((volatile unsigned int*)(0x4380208CUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA4 (*((volatile unsigned int*)(0x43802090UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA5 (*((volatile unsigned int*)(0x43802094UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA6 (*((volatile unsigned int*)(0x43802098UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA7 (*((volatile unsigned int*)(0x4380209CUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA8 (*((volatile unsigned int*)(0x438020A0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA9 (*((volatile unsigned int*)(0x438020A4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA10 (*((volatile unsigned int*)(0x438020A8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA11 (*((volatile unsigned int*)(0x438020ACUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD0 (*((volatile unsigned int*)(0x438020C0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD1 (*((volatile unsigned int*)(0x438020C4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD2 (*((volatile unsigned int*)(0x438020C8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD3 (*((volatile unsigned int*)(0x438020CCUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD4 (*((volatile unsigned int*)(0x438020D0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD5 (*((volatile unsigned int*)(0x438020D4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD6 (*((volatile unsigned int*)(0x438020D8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD7 (*((volatile unsigned int*)(0x438020DCUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD8 (*((volatile unsigned int*)(0x438020E0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD9 (*((volatile unsigned int*)(0x438020E4UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA0 (*((volatile unsigned int*)(0x43802100UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA1 (*((volatile unsigned int*)(0x43802104UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA2 (*((volatile unsigned int*)(0x43802108UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA3 (*((volatile unsigned int*)(0x4380210CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA4 (*((volatile unsigned int*)(0x43802110UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA5 (*((volatile unsigned int*)(0x43802114UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA6 (*((volatile unsigned int*)(0x43802118UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA7 (*((volatile unsigned int*)(0x4380211CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA8 (*((volatile unsigned int*)(0x43802120UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA9 (*((volatile unsigned int*)(0x43802124UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA10 (*((volatile unsigned int*)(0x43802128UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA11 (*((volatile unsigned int*)(0x4380212CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD0 (*((volatile unsigned int*)(0x43802140UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD1 (*((volatile unsigned int*)(0x43802144UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD2 (*((volatile unsigned int*)(0x43802148UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD3 (*((volatile unsigned int*)(0x4380214CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD4 (*((volatile unsigned int*)(0x43802150UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD5 (*((volatile unsigned int*)(0x43802154UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD6 (*((volatile unsigned int*)(0x43802158UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD7 (*((volatile unsigned int*)(0x4380215CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD8 (*((volatile unsigned int*)(0x43802160UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD9 (*((volatile unsigned int*)(0x43802164UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA0 (*((volatile unsigned int*)(0x43802180UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA1 (*((volatile unsigned int*)(0x43802184UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA2 (*((volatile unsigned int*)(0x43802188UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA3 (*((volatile unsigned int*)(0x4380218CUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA4 (*((volatile unsigned int*)(0x43802190UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA5 (*((volatile unsigned int*)(0x43802194UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA6 (*((volatile unsigned int*)(0x43802198UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA7 (*((volatile unsigned int*)(0x4380219CUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA8 (*((volatile unsigned int*)(0x438021A0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA9 (*((volatile unsigned int*)(0x438021A4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA10 (*((volatile unsigned int*)(0x438021A8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA11 (*((volatile unsigned int*)(0x438021ACUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD0 (*((volatile unsigned int*)(0x438021C0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD1 (*((volatile unsigned int*)(0x438021C4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD2 (*((volatile unsigned int*)(0x438021C8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD3 (*((volatile unsigned int*)(0x438021CCUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD4 (*((volatile unsigned int*)(0x438021D0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD5 (*((volatile unsigned int*)(0x438021D4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD6 (*((volatile unsigned int*)(0x438021D8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD7 (*((volatile unsigned int*)(0x438021DCUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD8 (*((volatile unsigned int*)(0x438021E0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD9 (*((volatile unsigned int*)(0x438021E4UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA0 (*((volatile unsigned int*)(0x43802200UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA1 (*((volatile unsigned int*)(0x43802204UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA2 (*((volatile unsigned int*)(0x43802208UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA3 (*((volatile unsigned int*)(0x4380220CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA4 (*((volatile unsigned int*)(0x43802210UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA5 (*((volatile unsigned int*)(0x43802214UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA6 (*((volatile unsigned int*)(0x43802218UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA7 (*((volatile unsigned int*)(0x4380221CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA8 (*((volatile unsigned int*)(0x43802220UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA9 (*((volatile unsigned int*)(0x43802224UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA10 (*((volatile unsigned int*)(0x43802228UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA11 (*((volatile unsigned int*)(0x4380222CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD0 (*((volatile unsigned int*)(0x43802240UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD1 (*((volatile unsigned int*)(0x43802244UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD2 (*((volatile unsigned int*)(0x43802248UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD3 (*((volatile unsigned int*)(0x4380224CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD4 (*((volatile unsigned int*)(0x43802250UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD5 (*((volatile unsigned int*)(0x43802254UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD6 (*((volatile unsigned int*)(0x43802258UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD7 (*((volatile unsigned int*)(0x4380225CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD8 (*((volatile unsigned int*)(0x43802260UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD9 (*((volatile unsigned int*)(0x43802264UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA0 (*((volatile unsigned int*)(0x43802280UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA1 (*((volatile unsigned int*)(0x43802284UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA2 (*((volatile unsigned int*)(0x43802288UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA3 (*((volatile unsigned int*)(0x4380228CUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA4 (*((volatile unsigned int*)(0x43802290UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA5 (*((volatile unsigned int*)(0x43802294UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA6 (*((volatile unsigned int*)(0x43802298UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA7 (*((volatile unsigned int*)(0x4380229CUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA8 (*((volatile unsigned int*)(0x438022A0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA9 (*((volatile unsigned int*)(0x438022A4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA10 (*((volatile unsigned int*)(0x438022A8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA11 (*((volatile unsigned int*)(0x438022ACUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD0 (*((volatile unsigned int*)(0x438022C0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD1 (*((volatile unsigned int*)(0x438022C4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD2 (*((volatile unsigned int*)(0x438022C8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD3 (*((volatile unsigned int*)(0x438022CCUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD4 (*((volatile unsigned int*)(0x438022D0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD5 (*((volatile unsigned int*)(0x438022D4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD6 (*((volatile unsigned int*)(0x438022D8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD7 (*((volatile unsigned int*)(0x438022DCUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD8 (*((volatile unsigned int*)(0x438022E0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD9 (*((volatile unsigned int*)(0x438022E4UL))) +#define bM4_USBFS_HCFG_FSLSPCS0 (*((volatile unsigned int*)(0x43808000UL))) +#define bM4_USBFS_HCFG_FSLSPCS1 (*((volatile unsigned int*)(0x43808004UL))) +#define bM4_USBFS_HCFG_FSLSS (*((volatile unsigned int*)(0x43808008UL))) +#define bM4_USBFS_HFIR_FRIVL0 (*((volatile unsigned int*)(0x43808080UL))) +#define bM4_USBFS_HFIR_FRIVL1 (*((volatile unsigned int*)(0x43808084UL))) +#define bM4_USBFS_HFIR_FRIVL2 (*((volatile unsigned int*)(0x43808088UL))) +#define bM4_USBFS_HFIR_FRIVL3 (*((volatile unsigned int*)(0x4380808CUL))) +#define bM4_USBFS_HFIR_FRIVL4 (*((volatile unsigned int*)(0x43808090UL))) +#define bM4_USBFS_HFIR_FRIVL5 (*((volatile unsigned int*)(0x43808094UL))) +#define bM4_USBFS_HFIR_FRIVL6 (*((volatile unsigned int*)(0x43808098UL))) +#define bM4_USBFS_HFIR_FRIVL7 (*((volatile unsigned int*)(0x4380809CUL))) +#define bM4_USBFS_HFIR_FRIVL8 (*((volatile unsigned int*)(0x438080A0UL))) +#define bM4_USBFS_HFIR_FRIVL9 (*((volatile unsigned int*)(0x438080A4UL))) +#define bM4_USBFS_HFIR_FRIVL10 (*((volatile unsigned int*)(0x438080A8UL))) +#define bM4_USBFS_HFIR_FRIVL11 (*((volatile unsigned int*)(0x438080ACUL))) +#define bM4_USBFS_HFIR_FRIVL12 (*((volatile unsigned int*)(0x438080B0UL))) +#define bM4_USBFS_HFIR_FRIVL13 (*((volatile unsigned int*)(0x438080B4UL))) +#define bM4_USBFS_HFIR_FRIVL14 (*((volatile unsigned int*)(0x438080B8UL))) +#define bM4_USBFS_HFIR_FRIVL15 (*((volatile unsigned int*)(0x438080BCUL))) +#define bM4_USBFS_HFNUM_FRNUM0 (*((volatile unsigned int*)(0x43808100UL))) +#define bM4_USBFS_HFNUM_FRNUM1 (*((volatile unsigned int*)(0x43808104UL))) +#define bM4_USBFS_HFNUM_FRNUM2 (*((volatile unsigned int*)(0x43808108UL))) +#define bM4_USBFS_HFNUM_FRNUM3 (*((volatile unsigned int*)(0x4380810CUL))) +#define bM4_USBFS_HFNUM_FRNUM4 (*((volatile unsigned int*)(0x43808110UL))) +#define bM4_USBFS_HFNUM_FRNUM5 (*((volatile unsigned int*)(0x43808114UL))) +#define bM4_USBFS_HFNUM_FRNUM6 (*((volatile unsigned int*)(0x43808118UL))) +#define bM4_USBFS_HFNUM_FRNUM7 (*((volatile unsigned int*)(0x4380811CUL))) +#define bM4_USBFS_HFNUM_FRNUM8 (*((volatile unsigned int*)(0x43808120UL))) +#define bM4_USBFS_HFNUM_FRNUM9 (*((volatile unsigned int*)(0x43808124UL))) +#define bM4_USBFS_HFNUM_FRNUM10 (*((volatile unsigned int*)(0x43808128UL))) +#define bM4_USBFS_HFNUM_FRNUM11 (*((volatile unsigned int*)(0x4380812CUL))) +#define bM4_USBFS_HFNUM_FRNUM12 (*((volatile unsigned int*)(0x43808130UL))) +#define bM4_USBFS_HFNUM_FRNUM13 (*((volatile unsigned int*)(0x43808134UL))) +#define bM4_USBFS_HFNUM_FRNUM14 (*((volatile unsigned int*)(0x43808138UL))) +#define bM4_USBFS_HFNUM_FRNUM15 (*((volatile unsigned int*)(0x4380813CUL))) +#define bM4_USBFS_HFNUM_FTREM0 (*((volatile unsigned int*)(0x43808140UL))) +#define bM4_USBFS_HFNUM_FTREM1 (*((volatile unsigned int*)(0x43808144UL))) +#define bM4_USBFS_HFNUM_FTREM2 (*((volatile unsigned int*)(0x43808148UL))) +#define bM4_USBFS_HFNUM_FTREM3 (*((volatile unsigned int*)(0x4380814CUL))) +#define bM4_USBFS_HFNUM_FTREM4 (*((volatile unsigned int*)(0x43808150UL))) +#define bM4_USBFS_HFNUM_FTREM5 (*((volatile unsigned int*)(0x43808154UL))) +#define bM4_USBFS_HFNUM_FTREM6 (*((volatile unsigned int*)(0x43808158UL))) +#define bM4_USBFS_HFNUM_FTREM7 (*((volatile unsigned int*)(0x4380815CUL))) +#define bM4_USBFS_HFNUM_FTREM8 (*((volatile unsigned int*)(0x43808160UL))) +#define bM4_USBFS_HFNUM_FTREM9 (*((volatile unsigned int*)(0x43808164UL))) +#define bM4_USBFS_HFNUM_FTREM10 (*((volatile unsigned int*)(0x43808168UL))) +#define bM4_USBFS_HFNUM_FTREM11 (*((volatile unsigned int*)(0x4380816CUL))) +#define bM4_USBFS_HFNUM_FTREM12 (*((volatile unsigned int*)(0x43808170UL))) +#define bM4_USBFS_HFNUM_FTREM13 (*((volatile unsigned int*)(0x43808174UL))) +#define bM4_USBFS_HFNUM_FTREM14 (*((volatile unsigned int*)(0x43808178UL))) +#define bM4_USBFS_HFNUM_FTREM15 (*((volatile unsigned int*)(0x4380817CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL0 (*((volatile unsigned int*)(0x43808200UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL1 (*((volatile unsigned int*)(0x43808204UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL2 (*((volatile unsigned int*)(0x43808208UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL3 (*((volatile unsigned int*)(0x4380820CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL4 (*((volatile unsigned int*)(0x43808210UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL5 (*((volatile unsigned int*)(0x43808214UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL6 (*((volatile unsigned int*)(0x43808218UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL7 (*((volatile unsigned int*)(0x4380821CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL8 (*((volatile unsigned int*)(0x43808220UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL9 (*((volatile unsigned int*)(0x43808224UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL10 (*((volatile unsigned int*)(0x43808228UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL11 (*((volatile unsigned int*)(0x4380822CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL12 (*((volatile unsigned int*)(0x43808230UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL13 (*((volatile unsigned int*)(0x43808234UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL14 (*((volatile unsigned int*)(0x43808238UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL15 (*((volatile unsigned int*)(0x4380823CUL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV0 (*((volatile unsigned int*)(0x43808240UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV1 (*((volatile unsigned int*)(0x43808244UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV2 (*((volatile unsigned int*)(0x43808248UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV3 (*((volatile unsigned int*)(0x4380824CUL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV4 (*((volatile unsigned int*)(0x43808250UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV5 (*((volatile unsigned int*)(0x43808254UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV6 (*((volatile unsigned int*)(0x43808258UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV7 (*((volatile unsigned int*)(0x4380825CUL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP0 (*((volatile unsigned int*)(0x43808260UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP1 (*((volatile unsigned int*)(0x43808264UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP2 (*((volatile unsigned int*)(0x43808268UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP3 (*((volatile unsigned int*)(0x4380826CUL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP4 (*((volatile unsigned int*)(0x43808270UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP5 (*((volatile unsigned int*)(0x43808274UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP6 (*((volatile unsigned int*)(0x43808278UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP7 (*((volatile unsigned int*)(0x4380827CUL))) +#define bM4_USBFS_HAINT_HAINT0 (*((volatile unsigned int*)(0x43808280UL))) +#define bM4_USBFS_HAINT_HAINT1 (*((volatile unsigned int*)(0x43808284UL))) +#define bM4_USBFS_HAINT_HAINT2 (*((volatile unsigned int*)(0x43808288UL))) +#define bM4_USBFS_HAINT_HAINT3 (*((volatile unsigned int*)(0x4380828CUL))) +#define bM4_USBFS_HAINT_HAINT4 (*((volatile unsigned int*)(0x43808290UL))) +#define bM4_USBFS_HAINT_HAINT5 (*((volatile unsigned int*)(0x43808294UL))) +#define bM4_USBFS_HAINT_HAINT6 (*((volatile unsigned int*)(0x43808298UL))) +#define bM4_USBFS_HAINT_HAINT7 (*((volatile unsigned int*)(0x4380829CUL))) +#define bM4_USBFS_HAINT_HAINT8 (*((volatile unsigned int*)(0x438082A0UL))) +#define bM4_USBFS_HAINT_HAINT9 (*((volatile unsigned int*)(0x438082A4UL))) +#define bM4_USBFS_HAINT_HAINT10 (*((volatile unsigned int*)(0x438082A8UL))) +#define bM4_USBFS_HAINT_HAINT11 (*((volatile unsigned int*)(0x438082ACUL))) +#define bM4_USBFS_HAINTMSK_HAINTM0 (*((volatile unsigned int*)(0x43808300UL))) +#define bM4_USBFS_HAINTMSK_HAINTM1 (*((volatile unsigned int*)(0x43808304UL))) +#define bM4_USBFS_HAINTMSK_HAINTM2 (*((volatile unsigned int*)(0x43808308UL))) +#define bM4_USBFS_HAINTMSK_HAINTM3 (*((volatile unsigned int*)(0x4380830CUL))) +#define bM4_USBFS_HAINTMSK_HAINTM4 (*((volatile unsigned int*)(0x43808310UL))) +#define bM4_USBFS_HAINTMSK_HAINTM5 (*((volatile unsigned int*)(0x43808314UL))) +#define bM4_USBFS_HAINTMSK_HAINTM6 (*((volatile unsigned int*)(0x43808318UL))) +#define bM4_USBFS_HAINTMSK_HAINTM7 (*((volatile unsigned int*)(0x4380831CUL))) +#define bM4_USBFS_HAINTMSK_HAINTM8 (*((volatile unsigned int*)(0x43808320UL))) +#define bM4_USBFS_HAINTMSK_HAINTM9 (*((volatile unsigned int*)(0x43808324UL))) +#define bM4_USBFS_HAINTMSK_HAINTM10 (*((volatile unsigned int*)(0x43808328UL))) +#define bM4_USBFS_HAINTMSK_HAINTM11 (*((volatile unsigned int*)(0x4380832CUL))) +#define bM4_USBFS_HPRT_PCSTS (*((volatile unsigned int*)(0x43808800UL))) +#define bM4_USBFS_HPRT_PCDET (*((volatile unsigned int*)(0x43808804UL))) +#define bM4_USBFS_HPRT_PENA (*((volatile unsigned int*)(0x43808808UL))) +#define bM4_USBFS_HPRT_PENCHNG (*((volatile unsigned int*)(0x4380880CUL))) +#define bM4_USBFS_HPRT_PRES (*((volatile unsigned int*)(0x43808818UL))) +#define bM4_USBFS_HPRT_PSUSP (*((volatile unsigned int*)(0x4380881CUL))) +#define bM4_USBFS_HPRT_PRST (*((volatile unsigned int*)(0x43808820UL))) +#define bM4_USBFS_HPRT_PLSTS0 (*((volatile unsigned int*)(0x43808828UL))) +#define bM4_USBFS_HPRT_PLSTS1 (*((volatile unsigned int*)(0x4380882CUL))) +#define bM4_USBFS_HPRT_PWPR (*((volatile unsigned int*)(0x43808830UL))) +#define bM4_USBFS_HPRT_PSPD0 (*((volatile unsigned int*)(0x43808844UL))) +#define bM4_USBFS_HPRT_PSPD1 (*((volatile unsigned int*)(0x43808848UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ0 (*((volatile unsigned int*)(0x4380A000UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ1 (*((volatile unsigned int*)(0x4380A004UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ2 (*((volatile unsigned int*)(0x4380A008UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ3 (*((volatile unsigned int*)(0x4380A00CUL))) +#define bM4_USBFS_HCCHAR0_MPSIZ4 (*((volatile unsigned int*)(0x4380A010UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ5 (*((volatile unsigned int*)(0x4380A014UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ6 (*((volatile unsigned int*)(0x4380A018UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ7 (*((volatile unsigned int*)(0x4380A01CUL))) +#define bM4_USBFS_HCCHAR0_MPSIZ8 (*((volatile unsigned int*)(0x4380A020UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ9 (*((volatile unsigned int*)(0x4380A024UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ10 (*((volatile unsigned int*)(0x4380A028UL))) +#define bM4_USBFS_HCCHAR0_EPNUM0 (*((volatile unsigned int*)(0x4380A02CUL))) +#define bM4_USBFS_HCCHAR0_EPNUM1 (*((volatile unsigned int*)(0x4380A030UL))) +#define bM4_USBFS_HCCHAR0_EPNUM2 (*((volatile unsigned int*)(0x4380A034UL))) +#define bM4_USBFS_HCCHAR0_EPNUM3 (*((volatile unsigned int*)(0x4380A038UL))) +#define bM4_USBFS_HCCHAR0_EPDIR (*((volatile unsigned int*)(0x4380A03CUL))) +#define bM4_USBFS_HCCHAR0_LSDEV (*((volatile unsigned int*)(0x4380A044UL))) +#define bM4_USBFS_HCCHAR0_EPTYP0 (*((volatile unsigned int*)(0x4380A048UL))) +#define bM4_USBFS_HCCHAR0_EPTYP1 (*((volatile unsigned int*)(0x4380A04CUL))) +#define bM4_USBFS_HCCHAR0_DAD0 (*((volatile unsigned int*)(0x4380A058UL))) +#define bM4_USBFS_HCCHAR0_DAD1 (*((volatile unsigned int*)(0x4380A05CUL))) +#define bM4_USBFS_HCCHAR0_DAD2 (*((volatile unsigned int*)(0x4380A060UL))) +#define bM4_USBFS_HCCHAR0_DAD3 (*((volatile unsigned int*)(0x4380A064UL))) +#define bM4_USBFS_HCCHAR0_DAD4 (*((volatile unsigned int*)(0x4380A068UL))) +#define bM4_USBFS_HCCHAR0_DAD5 (*((volatile unsigned int*)(0x4380A06CUL))) +#define bM4_USBFS_HCCHAR0_DAD6 (*((volatile unsigned int*)(0x4380A070UL))) +#define bM4_USBFS_HCCHAR0_ODDFRM (*((volatile unsigned int*)(0x4380A074UL))) +#define bM4_USBFS_HCCHAR0_CHDIS (*((volatile unsigned int*)(0x4380A078UL))) +#define bM4_USBFS_HCCHAR0_CHENA (*((volatile unsigned int*)(0x4380A07CUL))) +#define bM4_USBFS_HCINT0_XFRC (*((volatile unsigned int*)(0x4380A100UL))) +#define bM4_USBFS_HCINT0_CHH (*((volatile unsigned int*)(0x4380A104UL))) +#define bM4_USBFS_HCINT0_STALL (*((volatile unsigned int*)(0x4380A10CUL))) +#define bM4_USBFS_HCINT0_NAK (*((volatile unsigned int*)(0x4380A110UL))) +#define bM4_USBFS_HCINT0_ACK (*((volatile unsigned int*)(0x4380A114UL))) +#define bM4_USBFS_HCINT0_TXERR (*((volatile unsigned int*)(0x4380A11CUL))) +#define bM4_USBFS_HCINT0_BBERR (*((volatile unsigned int*)(0x4380A120UL))) +#define bM4_USBFS_HCINT0_FRMOR (*((volatile unsigned int*)(0x4380A124UL))) +#define bM4_USBFS_HCINT0_DTERR (*((volatile unsigned int*)(0x4380A128UL))) +#define bM4_USBFS_HCINTMSK0_XFRCM (*((volatile unsigned int*)(0x4380A180UL))) +#define bM4_USBFS_HCINTMSK0_CHHM (*((volatile unsigned int*)(0x4380A184UL))) +#define bM4_USBFS_HCINTMSK0_STALLM (*((volatile unsigned int*)(0x4380A18CUL))) +#define bM4_USBFS_HCINTMSK0_NAKM (*((volatile unsigned int*)(0x4380A190UL))) +#define bM4_USBFS_HCINTMSK0_ACKM (*((volatile unsigned int*)(0x4380A194UL))) +#define bM4_USBFS_HCINTMSK0_TXERRM (*((volatile unsigned int*)(0x4380A19CUL))) +#define bM4_USBFS_HCINTMSK0_BBERRM (*((volatile unsigned int*)(0x4380A1A0UL))) +#define bM4_USBFS_HCINTMSK0_FRMORM (*((volatile unsigned int*)(0x4380A1A4UL))) +#define bM4_USBFS_HCINTMSK0_DTERRM (*((volatile unsigned int*)(0x4380A1A8UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x4380A200UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x4380A204UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x4380A208UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4380A20CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x4380A210UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x4380A214UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x4380A218UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ7 (*((volatile unsigned int*)(0x4380A21CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ8 (*((volatile unsigned int*)(0x4380A220UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ9 (*((volatile unsigned int*)(0x4380A224UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ10 (*((volatile unsigned int*)(0x4380A228UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ11 (*((volatile unsigned int*)(0x4380A22CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ12 (*((volatile unsigned int*)(0x4380A230UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ13 (*((volatile unsigned int*)(0x4380A234UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ14 (*((volatile unsigned int*)(0x4380A238UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ15 (*((volatile unsigned int*)(0x4380A23CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ16 (*((volatile unsigned int*)(0x4380A240UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ17 (*((volatile unsigned int*)(0x4380A244UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ18 (*((volatile unsigned int*)(0x4380A248UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT0 (*((volatile unsigned int*)(0x4380A24CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT1 (*((volatile unsigned int*)(0x4380A250UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT2 (*((volatile unsigned int*)(0x4380A254UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT3 (*((volatile unsigned int*)(0x4380A258UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT4 (*((volatile unsigned int*)(0x4380A25CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT5 (*((volatile unsigned int*)(0x4380A260UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT6 (*((volatile unsigned int*)(0x4380A264UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT7 (*((volatile unsigned int*)(0x4380A268UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT8 (*((volatile unsigned int*)(0x4380A26CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT9 (*((volatile unsigned int*)(0x4380A270UL))) +#define bM4_USBFS_HCTSIZ0_DPID0 (*((volatile unsigned int*)(0x4380A274UL))) +#define bM4_USBFS_HCTSIZ0_DPID1 (*((volatile unsigned int*)(0x4380A278UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ0 (*((volatile unsigned int*)(0x4380A400UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ1 (*((volatile unsigned int*)(0x4380A404UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ2 (*((volatile unsigned int*)(0x4380A408UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ3 (*((volatile unsigned int*)(0x4380A40CUL))) +#define bM4_USBFS_HCCHAR1_MPSIZ4 (*((volatile unsigned int*)(0x4380A410UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ5 (*((volatile unsigned int*)(0x4380A414UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ6 (*((volatile unsigned int*)(0x4380A418UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ7 (*((volatile unsigned int*)(0x4380A41CUL))) +#define bM4_USBFS_HCCHAR1_MPSIZ8 (*((volatile unsigned int*)(0x4380A420UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ9 (*((volatile unsigned int*)(0x4380A424UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ10 (*((volatile unsigned int*)(0x4380A428UL))) +#define bM4_USBFS_HCCHAR1_EPNUM0 (*((volatile unsigned int*)(0x4380A42CUL))) +#define bM4_USBFS_HCCHAR1_EPNUM1 (*((volatile unsigned int*)(0x4380A430UL))) +#define bM4_USBFS_HCCHAR1_EPNUM2 (*((volatile unsigned int*)(0x4380A434UL))) +#define bM4_USBFS_HCCHAR1_EPNUM3 (*((volatile unsigned int*)(0x4380A438UL))) +#define bM4_USBFS_HCCHAR1_EPDIR (*((volatile unsigned int*)(0x4380A43CUL))) +#define bM4_USBFS_HCCHAR1_LSDEV (*((volatile unsigned int*)(0x4380A444UL))) +#define bM4_USBFS_HCCHAR1_EPTYP0 (*((volatile unsigned int*)(0x4380A448UL))) +#define bM4_USBFS_HCCHAR1_EPTYP1 (*((volatile unsigned int*)(0x4380A44CUL))) +#define bM4_USBFS_HCCHAR1_DAD0 (*((volatile unsigned int*)(0x4380A458UL))) +#define bM4_USBFS_HCCHAR1_DAD1 (*((volatile unsigned int*)(0x4380A45CUL))) +#define bM4_USBFS_HCCHAR1_DAD2 (*((volatile unsigned int*)(0x4380A460UL))) +#define bM4_USBFS_HCCHAR1_DAD3 (*((volatile unsigned int*)(0x4380A464UL))) +#define bM4_USBFS_HCCHAR1_DAD4 (*((volatile unsigned int*)(0x4380A468UL))) +#define bM4_USBFS_HCCHAR1_DAD5 (*((volatile unsigned int*)(0x4380A46CUL))) +#define bM4_USBFS_HCCHAR1_DAD6 (*((volatile unsigned int*)(0x4380A470UL))) +#define bM4_USBFS_HCCHAR1_ODDFRM (*((volatile unsigned int*)(0x4380A474UL))) +#define bM4_USBFS_HCCHAR1_CHDIS (*((volatile unsigned int*)(0x4380A478UL))) +#define bM4_USBFS_HCCHAR1_CHENA (*((volatile unsigned int*)(0x4380A47CUL))) +#define bM4_USBFS_HCINT1_XFRC (*((volatile unsigned int*)(0x4380A500UL))) +#define bM4_USBFS_HCINT1_CHH (*((volatile unsigned int*)(0x4380A504UL))) +#define bM4_USBFS_HCINT1_STALL (*((volatile unsigned int*)(0x4380A50CUL))) +#define bM4_USBFS_HCINT1_NAK (*((volatile unsigned int*)(0x4380A510UL))) +#define bM4_USBFS_HCINT1_ACK (*((volatile unsigned int*)(0x4380A514UL))) +#define bM4_USBFS_HCINT1_TXERR (*((volatile unsigned int*)(0x4380A51CUL))) +#define bM4_USBFS_HCINT1_BBERR (*((volatile unsigned int*)(0x4380A520UL))) +#define bM4_USBFS_HCINT1_FRMOR (*((volatile unsigned int*)(0x4380A524UL))) +#define bM4_USBFS_HCINT1_DTERR (*((volatile unsigned int*)(0x4380A528UL))) +#define bM4_USBFS_HCINTMSK1_XFRCM (*((volatile unsigned int*)(0x4380A580UL))) +#define bM4_USBFS_HCINTMSK1_CHHM (*((volatile unsigned int*)(0x4380A584UL))) +#define bM4_USBFS_HCINTMSK1_STALLM (*((volatile unsigned int*)(0x4380A58CUL))) +#define bM4_USBFS_HCINTMSK1_NAKM (*((volatile unsigned int*)(0x4380A590UL))) +#define bM4_USBFS_HCINTMSK1_ACKM (*((volatile unsigned int*)(0x4380A594UL))) +#define bM4_USBFS_HCINTMSK1_TXERRM (*((volatile unsigned int*)(0x4380A59CUL))) +#define bM4_USBFS_HCINTMSK1_BBERRM (*((volatile unsigned int*)(0x4380A5A0UL))) +#define bM4_USBFS_HCINTMSK1_FRMORM (*((volatile unsigned int*)(0x4380A5A4UL))) +#define bM4_USBFS_HCINTMSK1_DTERRM (*((volatile unsigned int*)(0x4380A5A8UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x4380A600UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x4380A604UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x4380A608UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4380A60CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x4380A610UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x4380A614UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x4380A618UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4380A61CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x4380A620UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x4380A624UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x4380A628UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4380A62CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x4380A630UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x4380A634UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x4380A638UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4380A63CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x4380A640UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x4380A644UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x4380A648UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4380A64CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x4380A650UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x4380A654UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x4380A658UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4380A65CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x4380A660UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x4380A664UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x4380A668UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4380A66CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x4380A670UL))) +#define bM4_USBFS_HCTSIZ1_DPID0 (*((volatile unsigned int*)(0x4380A674UL))) +#define bM4_USBFS_HCTSIZ1_DPID1 (*((volatile unsigned int*)(0x4380A678UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ0 (*((volatile unsigned int*)(0x4380A800UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ1 (*((volatile unsigned int*)(0x4380A804UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ2 (*((volatile unsigned int*)(0x4380A808UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ3 (*((volatile unsigned int*)(0x4380A80CUL))) +#define bM4_USBFS_HCCHAR2_MPSIZ4 (*((volatile unsigned int*)(0x4380A810UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ5 (*((volatile unsigned int*)(0x4380A814UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ6 (*((volatile unsigned int*)(0x4380A818UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ7 (*((volatile unsigned int*)(0x4380A81CUL))) +#define bM4_USBFS_HCCHAR2_MPSIZ8 (*((volatile unsigned int*)(0x4380A820UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ9 (*((volatile unsigned int*)(0x4380A824UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ10 (*((volatile unsigned int*)(0x4380A828UL))) +#define bM4_USBFS_HCCHAR2_EPNUM0 (*((volatile unsigned int*)(0x4380A82CUL))) +#define bM4_USBFS_HCCHAR2_EPNUM1 (*((volatile unsigned int*)(0x4380A830UL))) +#define bM4_USBFS_HCCHAR2_EPNUM2 (*((volatile unsigned int*)(0x4380A834UL))) +#define bM4_USBFS_HCCHAR2_EPNUM3 (*((volatile unsigned int*)(0x4380A838UL))) +#define bM4_USBFS_HCCHAR2_EPDIR (*((volatile unsigned int*)(0x4380A83CUL))) +#define bM4_USBFS_HCCHAR2_LSDEV (*((volatile unsigned int*)(0x4380A844UL))) +#define bM4_USBFS_HCCHAR2_EPTYP0 (*((volatile unsigned int*)(0x4380A848UL))) +#define bM4_USBFS_HCCHAR2_EPTYP1 (*((volatile unsigned int*)(0x4380A84CUL))) +#define bM4_USBFS_HCCHAR2_DAD0 (*((volatile unsigned int*)(0x4380A858UL))) +#define bM4_USBFS_HCCHAR2_DAD1 (*((volatile unsigned int*)(0x4380A85CUL))) +#define bM4_USBFS_HCCHAR2_DAD2 (*((volatile unsigned int*)(0x4380A860UL))) +#define bM4_USBFS_HCCHAR2_DAD3 (*((volatile unsigned int*)(0x4380A864UL))) +#define bM4_USBFS_HCCHAR2_DAD4 (*((volatile unsigned int*)(0x4380A868UL))) +#define bM4_USBFS_HCCHAR2_DAD5 (*((volatile unsigned int*)(0x4380A86CUL))) +#define bM4_USBFS_HCCHAR2_DAD6 (*((volatile unsigned int*)(0x4380A870UL))) +#define bM4_USBFS_HCCHAR2_ODDFRM (*((volatile unsigned int*)(0x4380A874UL))) +#define bM4_USBFS_HCCHAR2_CHDIS (*((volatile unsigned int*)(0x4380A878UL))) +#define bM4_USBFS_HCCHAR2_CHENA (*((volatile unsigned int*)(0x4380A87CUL))) +#define bM4_USBFS_HCINT2_XFRC (*((volatile unsigned int*)(0x4380A900UL))) +#define bM4_USBFS_HCINT2_CHH (*((volatile unsigned int*)(0x4380A904UL))) +#define bM4_USBFS_HCINT2_STALL (*((volatile unsigned int*)(0x4380A90CUL))) +#define bM4_USBFS_HCINT2_NAK (*((volatile unsigned int*)(0x4380A910UL))) +#define bM4_USBFS_HCINT2_ACK (*((volatile unsigned int*)(0x4380A914UL))) +#define bM4_USBFS_HCINT2_TXERR (*((volatile unsigned int*)(0x4380A91CUL))) +#define bM4_USBFS_HCINT2_BBERR (*((volatile unsigned int*)(0x4380A920UL))) +#define bM4_USBFS_HCINT2_FRMOR (*((volatile unsigned int*)(0x4380A924UL))) +#define bM4_USBFS_HCINT2_DTERR (*((volatile unsigned int*)(0x4380A928UL))) +#define bM4_USBFS_HCINTMSK2_XFRCM (*((volatile unsigned int*)(0x4380A980UL))) +#define bM4_USBFS_HCINTMSK2_CHHM (*((volatile unsigned int*)(0x4380A984UL))) +#define bM4_USBFS_HCINTMSK2_STALLM (*((volatile unsigned int*)(0x4380A98CUL))) +#define bM4_USBFS_HCINTMSK2_NAKM (*((volatile unsigned int*)(0x4380A990UL))) +#define bM4_USBFS_HCINTMSK2_ACKM (*((volatile unsigned int*)(0x4380A994UL))) +#define bM4_USBFS_HCINTMSK2_TXERRM (*((volatile unsigned int*)(0x4380A99CUL))) +#define bM4_USBFS_HCINTMSK2_BBERRM (*((volatile unsigned int*)(0x4380A9A0UL))) +#define bM4_USBFS_HCINTMSK2_FRMORM (*((volatile unsigned int*)(0x4380A9A4UL))) +#define bM4_USBFS_HCINTMSK2_DTERRM (*((volatile unsigned int*)(0x4380A9A8UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x4380AA00UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x4380AA04UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x4380AA08UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x4380AA0CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x4380AA10UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x4380AA14UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x4380AA18UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x4380AA1CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x4380AA20UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x4380AA24UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x4380AA28UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x4380AA2CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x4380AA30UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x4380AA34UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x4380AA38UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x4380AA3CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x4380AA40UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x4380AA44UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x4380AA48UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x4380AA4CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x4380AA50UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x4380AA54UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x4380AA58UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x4380AA5CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x4380AA60UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x4380AA64UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x4380AA68UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x4380AA6CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x4380AA70UL))) +#define bM4_USBFS_HCTSIZ2_DPID0 (*((volatile unsigned int*)(0x4380AA74UL))) +#define bM4_USBFS_HCTSIZ2_DPID1 (*((volatile unsigned int*)(0x4380AA78UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ0 (*((volatile unsigned int*)(0x4380AC00UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ1 (*((volatile unsigned int*)(0x4380AC04UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ2 (*((volatile unsigned int*)(0x4380AC08UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ3 (*((volatile unsigned int*)(0x4380AC0CUL))) +#define bM4_USBFS_HCCHAR3_MPSIZ4 (*((volatile unsigned int*)(0x4380AC10UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ5 (*((volatile unsigned int*)(0x4380AC14UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ6 (*((volatile unsigned int*)(0x4380AC18UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ7 (*((volatile unsigned int*)(0x4380AC1CUL))) +#define bM4_USBFS_HCCHAR3_MPSIZ8 (*((volatile unsigned int*)(0x4380AC20UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ9 (*((volatile unsigned int*)(0x4380AC24UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ10 (*((volatile unsigned int*)(0x4380AC28UL))) +#define bM4_USBFS_HCCHAR3_EPNUM0 (*((volatile unsigned int*)(0x4380AC2CUL))) +#define bM4_USBFS_HCCHAR3_EPNUM1 (*((volatile unsigned int*)(0x4380AC30UL))) +#define bM4_USBFS_HCCHAR3_EPNUM2 (*((volatile unsigned int*)(0x4380AC34UL))) +#define bM4_USBFS_HCCHAR3_EPNUM3 (*((volatile unsigned int*)(0x4380AC38UL))) +#define bM4_USBFS_HCCHAR3_EPDIR (*((volatile unsigned int*)(0x4380AC3CUL))) +#define bM4_USBFS_HCCHAR3_LSDEV (*((volatile unsigned int*)(0x4380AC44UL))) +#define bM4_USBFS_HCCHAR3_EPTYP0 (*((volatile unsigned int*)(0x4380AC48UL))) +#define bM4_USBFS_HCCHAR3_EPTYP1 (*((volatile unsigned int*)(0x4380AC4CUL))) +#define bM4_USBFS_HCCHAR3_DAD0 (*((volatile unsigned int*)(0x4380AC58UL))) +#define bM4_USBFS_HCCHAR3_DAD1 (*((volatile unsigned int*)(0x4380AC5CUL))) +#define bM4_USBFS_HCCHAR3_DAD2 (*((volatile unsigned int*)(0x4380AC60UL))) +#define bM4_USBFS_HCCHAR3_DAD3 (*((volatile unsigned int*)(0x4380AC64UL))) +#define bM4_USBFS_HCCHAR3_DAD4 (*((volatile unsigned int*)(0x4380AC68UL))) +#define bM4_USBFS_HCCHAR3_DAD5 (*((volatile unsigned int*)(0x4380AC6CUL))) +#define bM4_USBFS_HCCHAR3_DAD6 (*((volatile unsigned int*)(0x4380AC70UL))) +#define bM4_USBFS_HCCHAR3_ODDFRM (*((volatile unsigned int*)(0x4380AC74UL))) +#define bM4_USBFS_HCCHAR3_CHDIS (*((volatile unsigned int*)(0x4380AC78UL))) +#define bM4_USBFS_HCCHAR3_CHENA (*((volatile unsigned int*)(0x4380AC7CUL))) +#define bM4_USBFS_HCINT3_XFRC (*((volatile unsigned int*)(0x4380AD00UL))) +#define bM4_USBFS_HCINT3_CHH (*((volatile unsigned int*)(0x4380AD04UL))) +#define bM4_USBFS_HCINT3_STALL (*((volatile unsigned int*)(0x4380AD0CUL))) +#define bM4_USBFS_HCINT3_NAK (*((volatile unsigned int*)(0x4380AD10UL))) +#define bM4_USBFS_HCINT3_ACK (*((volatile unsigned int*)(0x4380AD14UL))) +#define bM4_USBFS_HCINT3_TXERR (*((volatile unsigned int*)(0x4380AD1CUL))) +#define bM4_USBFS_HCINT3_BBERR (*((volatile unsigned int*)(0x4380AD20UL))) +#define bM4_USBFS_HCINT3_FRMOR (*((volatile unsigned int*)(0x4380AD24UL))) +#define bM4_USBFS_HCINT3_DTERR (*((volatile unsigned int*)(0x4380AD28UL))) +#define bM4_USBFS_HCINTMSK3_XFRCM (*((volatile unsigned int*)(0x4380AD80UL))) +#define bM4_USBFS_HCINTMSK3_CHHM (*((volatile unsigned int*)(0x4380AD84UL))) +#define bM4_USBFS_HCINTMSK3_STALLM (*((volatile unsigned int*)(0x4380AD8CUL))) +#define bM4_USBFS_HCINTMSK3_NAKM (*((volatile unsigned int*)(0x4380AD90UL))) +#define bM4_USBFS_HCINTMSK3_ACKM (*((volatile unsigned int*)(0x4380AD94UL))) +#define bM4_USBFS_HCINTMSK3_TXERRM (*((volatile unsigned int*)(0x4380AD9CUL))) +#define bM4_USBFS_HCINTMSK3_BBERRM (*((volatile unsigned int*)(0x4380ADA0UL))) +#define bM4_USBFS_HCINTMSK3_FRMORM (*((volatile unsigned int*)(0x4380ADA4UL))) +#define bM4_USBFS_HCINTMSK3_DTERRM (*((volatile unsigned int*)(0x4380ADA8UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x4380AE00UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x4380AE04UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x4380AE08UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x4380AE0CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x4380AE10UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x4380AE14UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x4380AE18UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x4380AE1CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x4380AE20UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x4380AE24UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x4380AE28UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x4380AE2CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x4380AE30UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x4380AE34UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x4380AE38UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x4380AE3CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x4380AE40UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x4380AE44UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x4380AE48UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x4380AE4CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x4380AE50UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x4380AE54UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x4380AE58UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x4380AE5CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x4380AE60UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x4380AE64UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x4380AE68UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x4380AE6CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x4380AE70UL))) +#define bM4_USBFS_HCTSIZ3_DPID0 (*((volatile unsigned int*)(0x4380AE74UL))) +#define bM4_USBFS_HCTSIZ3_DPID1 (*((volatile unsigned int*)(0x4380AE78UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ0 (*((volatile unsigned int*)(0x4380B000UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ1 (*((volatile unsigned int*)(0x4380B004UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ2 (*((volatile unsigned int*)(0x4380B008UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ3 (*((volatile unsigned int*)(0x4380B00CUL))) +#define bM4_USBFS_HCCHAR4_MPSIZ4 (*((volatile unsigned int*)(0x4380B010UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ5 (*((volatile unsigned int*)(0x4380B014UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ6 (*((volatile unsigned int*)(0x4380B018UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ7 (*((volatile unsigned int*)(0x4380B01CUL))) +#define bM4_USBFS_HCCHAR4_MPSIZ8 (*((volatile unsigned int*)(0x4380B020UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ9 (*((volatile unsigned int*)(0x4380B024UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ10 (*((volatile unsigned int*)(0x4380B028UL))) +#define bM4_USBFS_HCCHAR4_EPNUM0 (*((volatile unsigned int*)(0x4380B02CUL))) +#define bM4_USBFS_HCCHAR4_EPNUM1 (*((volatile unsigned int*)(0x4380B030UL))) +#define bM4_USBFS_HCCHAR4_EPNUM2 (*((volatile unsigned int*)(0x4380B034UL))) +#define bM4_USBFS_HCCHAR4_EPNUM3 (*((volatile unsigned int*)(0x4380B038UL))) +#define bM4_USBFS_HCCHAR4_EPDIR (*((volatile unsigned int*)(0x4380B03CUL))) +#define bM4_USBFS_HCCHAR4_LSDEV (*((volatile unsigned int*)(0x4380B044UL))) +#define bM4_USBFS_HCCHAR4_EPTYP0 (*((volatile unsigned int*)(0x4380B048UL))) +#define bM4_USBFS_HCCHAR4_EPTYP1 (*((volatile unsigned int*)(0x4380B04CUL))) +#define bM4_USBFS_HCCHAR4_DAD0 (*((volatile unsigned int*)(0x4380B058UL))) +#define bM4_USBFS_HCCHAR4_DAD1 (*((volatile unsigned int*)(0x4380B05CUL))) +#define bM4_USBFS_HCCHAR4_DAD2 (*((volatile unsigned int*)(0x4380B060UL))) +#define bM4_USBFS_HCCHAR4_DAD3 (*((volatile unsigned int*)(0x4380B064UL))) +#define bM4_USBFS_HCCHAR4_DAD4 (*((volatile unsigned int*)(0x4380B068UL))) +#define bM4_USBFS_HCCHAR4_DAD5 (*((volatile unsigned int*)(0x4380B06CUL))) +#define bM4_USBFS_HCCHAR4_DAD6 (*((volatile unsigned int*)(0x4380B070UL))) +#define bM4_USBFS_HCCHAR4_ODDFRM (*((volatile unsigned int*)(0x4380B074UL))) +#define bM4_USBFS_HCCHAR4_CHDIS (*((volatile unsigned int*)(0x4380B078UL))) +#define bM4_USBFS_HCCHAR4_CHENA (*((volatile unsigned int*)(0x4380B07CUL))) +#define bM4_USBFS_HCINT4_XFRC (*((volatile unsigned int*)(0x4380B100UL))) +#define bM4_USBFS_HCINT4_CHH (*((volatile unsigned int*)(0x4380B104UL))) +#define bM4_USBFS_HCINT4_STALL (*((volatile unsigned int*)(0x4380B10CUL))) +#define bM4_USBFS_HCINT4_NAK (*((volatile unsigned int*)(0x4380B110UL))) +#define bM4_USBFS_HCINT4_ACK (*((volatile unsigned int*)(0x4380B114UL))) +#define bM4_USBFS_HCINT4_TXERR (*((volatile unsigned int*)(0x4380B11CUL))) +#define bM4_USBFS_HCINT4_BBERR (*((volatile unsigned int*)(0x4380B120UL))) +#define bM4_USBFS_HCINT4_FRMOR (*((volatile unsigned int*)(0x4380B124UL))) +#define bM4_USBFS_HCINT4_DTERR (*((volatile unsigned int*)(0x4380B128UL))) +#define bM4_USBFS_HCINTMSK4_XFRCM (*((volatile unsigned int*)(0x4380B180UL))) +#define bM4_USBFS_HCINTMSK4_CHHM (*((volatile unsigned int*)(0x4380B184UL))) +#define bM4_USBFS_HCINTMSK4_STALLM (*((volatile unsigned int*)(0x4380B18CUL))) +#define bM4_USBFS_HCINTMSK4_NAKM (*((volatile unsigned int*)(0x4380B190UL))) +#define bM4_USBFS_HCINTMSK4_ACKM (*((volatile unsigned int*)(0x4380B194UL))) +#define bM4_USBFS_HCINTMSK4_TXERRM (*((volatile unsigned int*)(0x4380B19CUL))) +#define bM4_USBFS_HCINTMSK4_BBERRM (*((volatile unsigned int*)(0x4380B1A0UL))) +#define bM4_USBFS_HCINTMSK4_FRMORM (*((volatile unsigned int*)(0x4380B1A4UL))) +#define bM4_USBFS_HCINTMSK4_DTERRM (*((volatile unsigned int*)(0x4380B1A8UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x4380B200UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x4380B204UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x4380B208UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4380B20CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x4380B210UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x4380B214UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x4380B218UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4380B21CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x4380B220UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x4380B224UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x4380B228UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4380B22CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x4380B230UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x4380B234UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x4380B238UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4380B23CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x4380B240UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x4380B244UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x4380B248UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4380B24CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x4380B250UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x4380B254UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x4380B258UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4380B25CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x4380B260UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x4380B264UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x4380B268UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4380B26CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x4380B270UL))) +#define bM4_USBFS_HCTSIZ4_DPID0 (*((volatile unsigned int*)(0x4380B274UL))) +#define bM4_USBFS_HCTSIZ4_DPID1 (*((volatile unsigned int*)(0x4380B278UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ0 (*((volatile unsigned int*)(0x4380B400UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ1 (*((volatile unsigned int*)(0x4380B404UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ2 (*((volatile unsigned int*)(0x4380B408UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ3 (*((volatile unsigned int*)(0x4380B40CUL))) +#define bM4_USBFS_HCCHAR5_MPSIZ4 (*((volatile unsigned int*)(0x4380B410UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ5 (*((volatile unsigned int*)(0x4380B414UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ6 (*((volatile unsigned int*)(0x4380B418UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ7 (*((volatile unsigned int*)(0x4380B41CUL))) +#define bM4_USBFS_HCCHAR5_MPSIZ8 (*((volatile unsigned int*)(0x4380B420UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ9 (*((volatile unsigned int*)(0x4380B424UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ10 (*((volatile unsigned int*)(0x4380B428UL))) +#define bM4_USBFS_HCCHAR5_EPNUM0 (*((volatile unsigned int*)(0x4380B42CUL))) +#define bM4_USBFS_HCCHAR5_EPNUM1 (*((volatile unsigned int*)(0x4380B430UL))) +#define bM4_USBFS_HCCHAR5_EPNUM2 (*((volatile unsigned int*)(0x4380B434UL))) +#define bM4_USBFS_HCCHAR5_EPNUM3 (*((volatile unsigned int*)(0x4380B438UL))) +#define bM4_USBFS_HCCHAR5_EPDIR (*((volatile unsigned int*)(0x4380B43CUL))) +#define bM4_USBFS_HCCHAR5_LSDEV (*((volatile unsigned int*)(0x4380B444UL))) +#define bM4_USBFS_HCCHAR5_EPTYP0 (*((volatile unsigned int*)(0x4380B448UL))) +#define bM4_USBFS_HCCHAR5_EPTYP1 (*((volatile unsigned int*)(0x4380B44CUL))) +#define bM4_USBFS_HCCHAR5_DAD0 (*((volatile unsigned int*)(0x4380B458UL))) +#define bM4_USBFS_HCCHAR5_DAD1 (*((volatile unsigned int*)(0x4380B45CUL))) +#define bM4_USBFS_HCCHAR5_DAD2 (*((volatile unsigned int*)(0x4380B460UL))) +#define bM4_USBFS_HCCHAR5_DAD3 (*((volatile unsigned int*)(0x4380B464UL))) +#define bM4_USBFS_HCCHAR5_DAD4 (*((volatile unsigned int*)(0x4380B468UL))) +#define bM4_USBFS_HCCHAR5_DAD5 (*((volatile unsigned int*)(0x4380B46CUL))) +#define bM4_USBFS_HCCHAR5_DAD6 (*((volatile unsigned int*)(0x4380B470UL))) +#define bM4_USBFS_HCCHAR5_ODDFRM (*((volatile unsigned int*)(0x4380B474UL))) +#define bM4_USBFS_HCCHAR5_CHDIS (*((volatile unsigned int*)(0x4380B478UL))) +#define bM4_USBFS_HCCHAR5_CHENA (*((volatile unsigned int*)(0x4380B47CUL))) +#define bM4_USBFS_HCINT5_XFRC (*((volatile unsigned int*)(0x4380B500UL))) +#define bM4_USBFS_HCINT5_CHH (*((volatile unsigned int*)(0x4380B504UL))) +#define bM4_USBFS_HCINT5_STALL (*((volatile unsigned int*)(0x4380B50CUL))) +#define bM4_USBFS_HCINT5_NAK (*((volatile unsigned int*)(0x4380B510UL))) +#define bM4_USBFS_HCINT5_ACK (*((volatile unsigned int*)(0x4380B514UL))) +#define bM4_USBFS_HCINT5_TXERR (*((volatile unsigned int*)(0x4380B51CUL))) +#define bM4_USBFS_HCINT5_BBERR (*((volatile unsigned int*)(0x4380B520UL))) +#define bM4_USBFS_HCINT5_FRMOR (*((volatile unsigned int*)(0x4380B524UL))) +#define bM4_USBFS_HCINT5_DTERR (*((volatile unsigned int*)(0x4380B528UL))) +#define bM4_USBFS_HCINTMSK5_XFRCM (*((volatile unsigned int*)(0x4380B580UL))) +#define bM4_USBFS_HCINTMSK5_CHHM (*((volatile unsigned int*)(0x4380B584UL))) +#define bM4_USBFS_HCINTMSK5_STALLM (*((volatile unsigned int*)(0x4380B58CUL))) +#define bM4_USBFS_HCINTMSK5_NAKM (*((volatile unsigned int*)(0x4380B590UL))) +#define bM4_USBFS_HCINTMSK5_ACKM (*((volatile unsigned int*)(0x4380B594UL))) +#define bM4_USBFS_HCINTMSK5_TXERRM (*((volatile unsigned int*)(0x4380B59CUL))) +#define bM4_USBFS_HCINTMSK5_BBERRM (*((volatile unsigned int*)(0x4380B5A0UL))) +#define bM4_USBFS_HCINTMSK5_FRMORM (*((volatile unsigned int*)(0x4380B5A4UL))) +#define bM4_USBFS_HCINTMSK5_DTERRM (*((volatile unsigned int*)(0x4380B5A8UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x4380B600UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x4380B604UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x4380B608UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4380B60CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x4380B610UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x4380B614UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x4380B618UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4380B61CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x4380B620UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x4380B624UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x4380B628UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4380B62CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x4380B630UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x4380B634UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x4380B638UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4380B63CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x4380B640UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x4380B644UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x4380B648UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4380B64CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x4380B650UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x4380B654UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x4380B658UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4380B65CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x4380B660UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x4380B664UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x4380B668UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4380B66CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x4380B670UL))) +#define bM4_USBFS_HCTSIZ5_DPID0 (*((volatile unsigned int*)(0x4380B674UL))) +#define bM4_USBFS_HCTSIZ5_DPID1 (*((volatile unsigned int*)(0x4380B678UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ0 (*((volatile unsigned int*)(0x4380B800UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ1 (*((volatile unsigned int*)(0x4380B804UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ2 (*((volatile unsigned int*)(0x4380B808UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ3 (*((volatile unsigned int*)(0x4380B80CUL))) +#define bM4_USBFS_HCCHAR6_MPSIZ4 (*((volatile unsigned int*)(0x4380B810UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ5 (*((volatile unsigned int*)(0x4380B814UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ6 (*((volatile unsigned int*)(0x4380B818UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ7 (*((volatile unsigned int*)(0x4380B81CUL))) +#define bM4_USBFS_HCCHAR6_MPSIZ8 (*((volatile unsigned int*)(0x4380B820UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ9 (*((volatile unsigned int*)(0x4380B824UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ10 (*((volatile unsigned int*)(0x4380B828UL))) +#define bM4_USBFS_HCCHAR6_EPNUM0 (*((volatile unsigned int*)(0x4380B82CUL))) +#define bM4_USBFS_HCCHAR6_EPNUM1 (*((volatile unsigned int*)(0x4380B830UL))) +#define bM4_USBFS_HCCHAR6_EPNUM2 (*((volatile unsigned int*)(0x4380B834UL))) +#define bM4_USBFS_HCCHAR6_EPNUM3 (*((volatile unsigned int*)(0x4380B838UL))) +#define bM4_USBFS_HCCHAR6_EPDIR (*((volatile unsigned int*)(0x4380B83CUL))) +#define bM4_USBFS_HCCHAR6_LSDEV (*((volatile unsigned int*)(0x4380B844UL))) +#define bM4_USBFS_HCCHAR6_EPTYP0 (*((volatile unsigned int*)(0x4380B848UL))) +#define bM4_USBFS_HCCHAR6_EPTYP1 (*((volatile unsigned int*)(0x4380B84CUL))) +#define bM4_USBFS_HCCHAR6_DAD0 (*((volatile unsigned int*)(0x4380B858UL))) +#define bM4_USBFS_HCCHAR6_DAD1 (*((volatile unsigned int*)(0x4380B85CUL))) +#define bM4_USBFS_HCCHAR6_DAD2 (*((volatile unsigned int*)(0x4380B860UL))) +#define bM4_USBFS_HCCHAR6_DAD3 (*((volatile unsigned int*)(0x4380B864UL))) +#define bM4_USBFS_HCCHAR6_DAD4 (*((volatile unsigned int*)(0x4380B868UL))) +#define bM4_USBFS_HCCHAR6_DAD5 (*((volatile unsigned int*)(0x4380B86CUL))) +#define bM4_USBFS_HCCHAR6_DAD6 (*((volatile unsigned int*)(0x4380B870UL))) +#define bM4_USBFS_HCCHAR6_ODDFRM (*((volatile unsigned int*)(0x4380B874UL))) +#define bM4_USBFS_HCCHAR6_CHDIS (*((volatile unsigned int*)(0x4380B878UL))) +#define bM4_USBFS_HCCHAR6_CHENA (*((volatile unsigned int*)(0x4380B87CUL))) +#define bM4_USBFS_HCINT6_XFRC (*((volatile unsigned int*)(0x4380B900UL))) +#define bM4_USBFS_HCINT6_CHH (*((volatile unsigned int*)(0x4380B904UL))) +#define bM4_USBFS_HCINT6_STALL (*((volatile unsigned int*)(0x4380B90CUL))) +#define bM4_USBFS_HCINT6_NAK (*((volatile unsigned int*)(0x4380B910UL))) +#define bM4_USBFS_HCINT6_ACK (*((volatile unsigned int*)(0x4380B914UL))) +#define bM4_USBFS_HCINT6_TXERR (*((volatile unsigned int*)(0x4380B91CUL))) +#define bM4_USBFS_HCINT6_BBERR (*((volatile unsigned int*)(0x4380B920UL))) +#define bM4_USBFS_HCINT6_FRMOR (*((volatile unsigned int*)(0x4380B924UL))) +#define bM4_USBFS_HCINT6_DTERR (*((volatile unsigned int*)(0x4380B928UL))) +#define bM4_USBFS_HCINTMSK6_XFRCM (*((volatile unsigned int*)(0x4380B980UL))) +#define bM4_USBFS_HCINTMSK6_CHHM (*((volatile unsigned int*)(0x4380B984UL))) +#define bM4_USBFS_HCINTMSK6_STALLM (*((volatile unsigned int*)(0x4380B98CUL))) +#define bM4_USBFS_HCINTMSK6_NAKM (*((volatile unsigned int*)(0x4380B990UL))) +#define bM4_USBFS_HCINTMSK6_ACKM (*((volatile unsigned int*)(0x4380B994UL))) +#define bM4_USBFS_HCINTMSK6_TXERRM (*((volatile unsigned int*)(0x4380B99CUL))) +#define bM4_USBFS_HCINTMSK6_BBERRM (*((volatile unsigned int*)(0x4380B9A0UL))) +#define bM4_USBFS_HCINTMSK6_FRMORM (*((volatile unsigned int*)(0x4380B9A4UL))) +#define bM4_USBFS_HCINTMSK6_DTERRM (*((volatile unsigned int*)(0x4380B9A8UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ0 (*((volatile unsigned int*)(0x4380BA00UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ1 (*((volatile unsigned int*)(0x4380BA04UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ2 (*((volatile unsigned int*)(0x4380BA08UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ3 (*((volatile unsigned int*)(0x4380BA0CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ4 (*((volatile unsigned int*)(0x4380BA10UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ5 (*((volatile unsigned int*)(0x4380BA14UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ6 (*((volatile unsigned int*)(0x4380BA18UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ7 (*((volatile unsigned int*)(0x4380BA1CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ8 (*((volatile unsigned int*)(0x4380BA20UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ9 (*((volatile unsigned int*)(0x4380BA24UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ10 (*((volatile unsigned int*)(0x4380BA28UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ11 (*((volatile unsigned int*)(0x4380BA2CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ12 (*((volatile unsigned int*)(0x4380BA30UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ13 (*((volatile unsigned int*)(0x4380BA34UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ14 (*((volatile unsigned int*)(0x4380BA38UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ15 (*((volatile unsigned int*)(0x4380BA3CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ16 (*((volatile unsigned int*)(0x4380BA40UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ17 (*((volatile unsigned int*)(0x4380BA44UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ18 (*((volatile unsigned int*)(0x4380BA48UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT0 (*((volatile unsigned int*)(0x4380BA4CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT1 (*((volatile unsigned int*)(0x4380BA50UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT2 (*((volatile unsigned int*)(0x4380BA54UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT3 (*((volatile unsigned int*)(0x4380BA58UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT4 (*((volatile unsigned int*)(0x4380BA5CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT5 (*((volatile unsigned int*)(0x4380BA60UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT6 (*((volatile unsigned int*)(0x4380BA64UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT7 (*((volatile unsigned int*)(0x4380BA68UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT8 (*((volatile unsigned int*)(0x4380BA6CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT9 (*((volatile unsigned int*)(0x4380BA70UL))) +#define bM4_USBFS_HCTSIZ6_DPID0 (*((volatile unsigned int*)(0x4380BA74UL))) +#define bM4_USBFS_HCTSIZ6_DPID1 (*((volatile unsigned int*)(0x4380BA78UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ0 (*((volatile unsigned int*)(0x4380BC00UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ1 (*((volatile unsigned int*)(0x4380BC04UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ2 (*((volatile unsigned int*)(0x4380BC08UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ3 (*((volatile unsigned int*)(0x4380BC0CUL))) +#define bM4_USBFS_HCCHAR7_MPSIZ4 (*((volatile unsigned int*)(0x4380BC10UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ5 (*((volatile unsigned int*)(0x4380BC14UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ6 (*((volatile unsigned int*)(0x4380BC18UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ7 (*((volatile unsigned int*)(0x4380BC1CUL))) +#define bM4_USBFS_HCCHAR7_MPSIZ8 (*((volatile unsigned int*)(0x4380BC20UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ9 (*((volatile unsigned int*)(0x4380BC24UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ10 (*((volatile unsigned int*)(0x4380BC28UL))) +#define bM4_USBFS_HCCHAR7_EPNUM0 (*((volatile unsigned int*)(0x4380BC2CUL))) +#define bM4_USBFS_HCCHAR7_EPNUM1 (*((volatile unsigned int*)(0x4380BC30UL))) +#define bM4_USBFS_HCCHAR7_EPNUM2 (*((volatile unsigned int*)(0x4380BC34UL))) +#define bM4_USBFS_HCCHAR7_EPNUM3 (*((volatile unsigned int*)(0x4380BC38UL))) +#define bM4_USBFS_HCCHAR7_EPDIR (*((volatile unsigned int*)(0x4380BC3CUL))) +#define bM4_USBFS_HCCHAR7_LSDEV (*((volatile unsigned int*)(0x4380BC44UL))) +#define bM4_USBFS_HCCHAR7_EPTYP0 (*((volatile unsigned int*)(0x4380BC48UL))) +#define bM4_USBFS_HCCHAR7_EPTYP1 (*((volatile unsigned int*)(0x4380BC4CUL))) +#define bM4_USBFS_HCCHAR7_DAD0 (*((volatile unsigned int*)(0x4380BC58UL))) +#define bM4_USBFS_HCCHAR7_DAD1 (*((volatile unsigned int*)(0x4380BC5CUL))) +#define bM4_USBFS_HCCHAR7_DAD2 (*((volatile unsigned int*)(0x4380BC60UL))) +#define bM4_USBFS_HCCHAR7_DAD3 (*((volatile unsigned int*)(0x4380BC64UL))) +#define bM4_USBFS_HCCHAR7_DAD4 (*((volatile unsigned int*)(0x4380BC68UL))) +#define bM4_USBFS_HCCHAR7_DAD5 (*((volatile unsigned int*)(0x4380BC6CUL))) +#define bM4_USBFS_HCCHAR7_DAD6 (*((volatile unsigned int*)(0x4380BC70UL))) +#define bM4_USBFS_HCCHAR7_ODDFRM (*((volatile unsigned int*)(0x4380BC74UL))) +#define bM4_USBFS_HCCHAR7_CHDIS (*((volatile unsigned int*)(0x4380BC78UL))) +#define bM4_USBFS_HCCHAR7_CHENA (*((volatile unsigned int*)(0x4380BC7CUL))) +#define bM4_USBFS_HCINT7_XFRC (*((volatile unsigned int*)(0x4380BD00UL))) +#define bM4_USBFS_HCINT7_CHH (*((volatile unsigned int*)(0x4380BD04UL))) +#define bM4_USBFS_HCINT7_STALL (*((volatile unsigned int*)(0x4380BD0CUL))) +#define bM4_USBFS_HCINT7_NAK (*((volatile unsigned int*)(0x4380BD10UL))) +#define bM4_USBFS_HCINT7_ACK (*((volatile unsigned int*)(0x4380BD14UL))) +#define bM4_USBFS_HCINT7_TXERR (*((volatile unsigned int*)(0x4380BD1CUL))) +#define bM4_USBFS_HCINT7_BBERR (*((volatile unsigned int*)(0x4380BD20UL))) +#define bM4_USBFS_HCINT7_FRMOR (*((volatile unsigned int*)(0x4380BD24UL))) +#define bM4_USBFS_HCINT7_DTERR (*((volatile unsigned int*)(0x4380BD28UL))) +#define bM4_USBFS_HCINTMSK7_XFRCM (*((volatile unsigned int*)(0x4380BD80UL))) +#define bM4_USBFS_HCINTMSK7_CHHM (*((volatile unsigned int*)(0x4380BD84UL))) +#define bM4_USBFS_HCINTMSK7_STALLM (*((volatile unsigned int*)(0x4380BD8CUL))) +#define bM4_USBFS_HCINTMSK7_NAKM (*((volatile unsigned int*)(0x4380BD90UL))) +#define bM4_USBFS_HCINTMSK7_ACKM (*((volatile unsigned int*)(0x4380BD94UL))) +#define bM4_USBFS_HCINTMSK7_TXERRM (*((volatile unsigned int*)(0x4380BD9CUL))) +#define bM4_USBFS_HCINTMSK7_BBERRM (*((volatile unsigned int*)(0x4380BDA0UL))) +#define bM4_USBFS_HCINTMSK7_FRMORM (*((volatile unsigned int*)(0x4380BDA4UL))) +#define bM4_USBFS_HCINTMSK7_DTERRM (*((volatile unsigned int*)(0x4380BDA8UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ0 (*((volatile unsigned int*)(0x4380BE00UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ1 (*((volatile unsigned int*)(0x4380BE04UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ2 (*((volatile unsigned int*)(0x4380BE08UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ3 (*((volatile unsigned int*)(0x4380BE0CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ4 (*((volatile unsigned int*)(0x4380BE10UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ5 (*((volatile unsigned int*)(0x4380BE14UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ6 (*((volatile unsigned int*)(0x4380BE18UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ7 (*((volatile unsigned int*)(0x4380BE1CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ8 (*((volatile unsigned int*)(0x4380BE20UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ9 (*((volatile unsigned int*)(0x4380BE24UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ10 (*((volatile unsigned int*)(0x4380BE28UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ11 (*((volatile unsigned int*)(0x4380BE2CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ12 (*((volatile unsigned int*)(0x4380BE30UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ13 (*((volatile unsigned int*)(0x4380BE34UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ14 (*((volatile unsigned int*)(0x4380BE38UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ15 (*((volatile unsigned int*)(0x4380BE3CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ16 (*((volatile unsigned int*)(0x4380BE40UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ17 (*((volatile unsigned int*)(0x4380BE44UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ18 (*((volatile unsigned int*)(0x4380BE48UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT0 (*((volatile unsigned int*)(0x4380BE4CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT1 (*((volatile unsigned int*)(0x4380BE50UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT2 (*((volatile unsigned int*)(0x4380BE54UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT3 (*((volatile unsigned int*)(0x4380BE58UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT4 (*((volatile unsigned int*)(0x4380BE5CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT5 (*((volatile unsigned int*)(0x4380BE60UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT6 (*((volatile unsigned int*)(0x4380BE64UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT7 (*((volatile unsigned int*)(0x4380BE68UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT8 (*((volatile unsigned int*)(0x4380BE6CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT9 (*((volatile unsigned int*)(0x4380BE70UL))) +#define bM4_USBFS_HCTSIZ7_DPID0 (*((volatile unsigned int*)(0x4380BE74UL))) +#define bM4_USBFS_HCTSIZ7_DPID1 (*((volatile unsigned int*)(0x4380BE78UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ0 (*((volatile unsigned int*)(0x4380C000UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ1 (*((volatile unsigned int*)(0x4380C004UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ2 (*((volatile unsigned int*)(0x4380C008UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ3 (*((volatile unsigned int*)(0x4380C00CUL))) +#define bM4_USBFS_HCCHAR8_MPSIZ4 (*((volatile unsigned int*)(0x4380C010UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ5 (*((volatile unsigned int*)(0x4380C014UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ6 (*((volatile unsigned int*)(0x4380C018UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ7 (*((volatile unsigned int*)(0x4380C01CUL))) +#define bM4_USBFS_HCCHAR8_MPSIZ8 (*((volatile unsigned int*)(0x4380C020UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ9 (*((volatile unsigned int*)(0x4380C024UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ10 (*((volatile unsigned int*)(0x4380C028UL))) +#define bM4_USBFS_HCCHAR8_EPNUM0 (*((volatile unsigned int*)(0x4380C02CUL))) +#define bM4_USBFS_HCCHAR8_EPNUM1 (*((volatile unsigned int*)(0x4380C030UL))) +#define bM4_USBFS_HCCHAR8_EPNUM2 (*((volatile unsigned int*)(0x4380C034UL))) +#define bM4_USBFS_HCCHAR8_EPNUM3 (*((volatile unsigned int*)(0x4380C038UL))) +#define bM4_USBFS_HCCHAR8_EPDIR (*((volatile unsigned int*)(0x4380C03CUL))) +#define bM4_USBFS_HCCHAR8_LSDEV (*((volatile unsigned int*)(0x4380C044UL))) +#define bM4_USBFS_HCCHAR8_EPTYP0 (*((volatile unsigned int*)(0x4380C048UL))) +#define bM4_USBFS_HCCHAR8_EPTYP1 (*((volatile unsigned int*)(0x4380C04CUL))) +#define bM4_USBFS_HCCHAR8_DAD0 (*((volatile unsigned int*)(0x4380C058UL))) +#define bM4_USBFS_HCCHAR8_DAD1 (*((volatile unsigned int*)(0x4380C05CUL))) +#define bM4_USBFS_HCCHAR8_DAD2 (*((volatile unsigned int*)(0x4380C060UL))) +#define bM4_USBFS_HCCHAR8_DAD3 (*((volatile unsigned int*)(0x4380C064UL))) +#define bM4_USBFS_HCCHAR8_DAD4 (*((volatile unsigned int*)(0x4380C068UL))) +#define bM4_USBFS_HCCHAR8_DAD5 (*((volatile unsigned int*)(0x4380C06CUL))) +#define bM4_USBFS_HCCHAR8_DAD6 (*((volatile unsigned int*)(0x4380C070UL))) +#define bM4_USBFS_HCCHAR8_ODDFRM (*((volatile unsigned int*)(0x4380C074UL))) +#define bM4_USBFS_HCCHAR8_CHDIS (*((volatile unsigned int*)(0x4380C078UL))) +#define bM4_USBFS_HCCHAR8_CHENA (*((volatile unsigned int*)(0x4380C07CUL))) +#define bM4_USBFS_HCINT8_XFRC (*((volatile unsigned int*)(0x4380C100UL))) +#define bM4_USBFS_HCINT8_CHH (*((volatile unsigned int*)(0x4380C104UL))) +#define bM4_USBFS_HCINT8_STALL (*((volatile unsigned int*)(0x4380C10CUL))) +#define bM4_USBFS_HCINT8_NAK (*((volatile unsigned int*)(0x4380C110UL))) +#define bM4_USBFS_HCINT8_ACK (*((volatile unsigned int*)(0x4380C114UL))) +#define bM4_USBFS_HCINT8_TXERR (*((volatile unsigned int*)(0x4380C11CUL))) +#define bM4_USBFS_HCINT8_BBERR (*((volatile unsigned int*)(0x4380C120UL))) +#define bM4_USBFS_HCINT8_FRMOR (*((volatile unsigned int*)(0x4380C124UL))) +#define bM4_USBFS_HCINT8_DTERR (*((volatile unsigned int*)(0x4380C128UL))) +#define bM4_USBFS_HCINTMSK8_XFRCM (*((volatile unsigned int*)(0x4380C180UL))) +#define bM4_USBFS_HCINTMSK8_CHHM (*((volatile unsigned int*)(0x4380C184UL))) +#define bM4_USBFS_HCINTMSK8_STALLM (*((volatile unsigned int*)(0x4380C18CUL))) +#define bM4_USBFS_HCINTMSK8_NAKM (*((volatile unsigned int*)(0x4380C190UL))) +#define bM4_USBFS_HCINTMSK8_ACKM (*((volatile unsigned int*)(0x4380C194UL))) +#define bM4_USBFS_HCINTMSK8_TXERRM (*((volatile unsigned int*)(0x4380C19CUL))) +#define bM4_USBFS_HCINTMSK8_BBERRM (*((volatile unsigned int*)(0x4380C1A0UL))) +#define bM4_USBFS_HCINTMSK8_FRMORM (*((volatile unsigned int*)(0x4380C1A4UL))) +#define bM4_USBFS_HCINTMSK8_DTERRM (*((volatile unsigned int*)(0x4380C1A8UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ0 (*((volatile unsigned int*)(0x4380C200UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ1 (*((volatile unsigned int*)(0x4380C204UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ2 (*((volatile unsigned int*)(0x4380C208UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ3 (*((volatile unsigned int*)(0x4380C20CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ4 (*((volatile unsigned int*)(0x4380C210UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ5 (*((volatile unsigned int*)(0x4380C214UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ6 (*((volatile unsigned int*)(0x4380C218UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ7 (*((volatile unsigned int*)(0x4380C21CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ8 (*((volatile unsigned int*)(0x4380C220UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ9 (*((volatile unsigned int*)(0x4380C224UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ10 (*((volatile unsigned int*)(0x4380C228UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ11 (*((volatile unsigned int*)(0x4380C22CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ12 (*((volatile unsigned int*)(0x4380C230UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ13 (*((volatile unsigned int*)(0x4380C234UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ14 (*((volatile unsigned int*)(0x4380C238UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ15 (*((volatile unsigned int*)(0x4380C23CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ16 (*((volatile unsigned int*)(0x4380C240UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ17 (*((volatile unsigned int*)(0x4380C244UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ18 (*((volatile unsigned int*)(0x4380C248UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT0 (*((volatile unsigned int*)(0x4380C24CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT1 (*((volatile unsigned int*)(0x4380C250UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT2 (*((volatile unsigned int*)(0x4380C254UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT3 (*((volatile unsigned int*)(0x4380C258UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT4 (*((volatile unsigned int*)(0x4380C25CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT5 (*((volatile unsigned int*)(0x4380C260UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT6 (*((volatile unsigned int*)(0x4380C264UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT7 (*((volatile unsigned int*)(0x4380C268UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT8 (*((volatile unsigned int*)(0x4380C26CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT9 (*((volatile unsigned int*)(0x4380C270UL))) +#define bM4_USBFS_HCTSIZ8_DPID0 (*((volatile unsigned int*)(0x4380C274UL))) +#define bM4_USBFS_HCTSIZ8_DPID1 (*((volatile unsigned int*)(0x4380C278UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ0 (*((volatile unsigned int*)(0x4380C400UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ1 (*((volatile unsigned int*)(0x4380C404UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ2 (*((volatile unsigned int*)(0x4380C408UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ3 (*((volatile unsigned int*)(0x4380C40CUL))) +#define bM4_USBFS_HCCHAR9_MPSIZ4 (*((volatile unsigned int*)(0x4380C410UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ5 (*((volatile unsigned int*)(0x4380C414UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ6 (*((volatile unsigned int*)(0x4380C418UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ7 (*((volatile unsigned int*)(0x4380C41CUL))) +#define bM4_USBFS_HCCHAR9_MPSIZ8 (*((volatile unsigned int*)(0x4380C420UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ9 (*((volatile unsigned int*)(0x4380C424UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ10 (*((volatile unsigned int*)(0x4380C428UL))) +#define bM4_USBFS_HCCHAR9_EPNUM0 (*((volatile unsigned int*)(0x4380C42CUL))) +#define bM4_USBFS_HCCHAR9_EPNUM1 (*((volatile unsigned int*)(0x4380C430UL))) +#define bM4_USBFS_HCCHAR9_EPNUM2 (*((volatile unsigned int*)(0x4380C434UL))) +#define bM4_USBFS_HCCHAR9_EPNUM3 (*((volatile unsigned int*)(0x4380C438UL))) +#define bM4_USBFS_HCCHAR9_EPDIR (*((volatile unsigned int*)(0x4380C43CUL))) +#define bM4_USBFS_HCCHAR9_LSDEV (*((volatile unsigned int*)(0x4380C444UL))) +#define bM4_USBFS_HCCHAR9_EPTYP0 (*((volatile unsigned int*)(0x4380C448UL))) +#define bM4_USBFS_HCCHAR9_EPTYP1 (*((volatile unsigned int*)(0x4380C44CUL))) +#define bM4_USBFS_HCCHAR9_DAD0 (*((volatile unsigned int*)(0x4380C458UL))) +#define bM4_USBFS_HCCHAR9_DAD1 (*((volatile unsigned int*)(0x4380C45CUL))) +#define bM4_USBFS_HCCHAR9_DAD2 (*((volatile unsigned int*)(0x4380C460UL))) +#define bM4_USBFS_HCCHAR9_DAD3 (*((volatile unsigned int*)(0x4380C464UL))) +#define bM4_USBFS_HCCHAR9_DAD4 (*((volatile unsigned int*)(0x4380C468UL))) +#define bM4_USBFS_HCCHAR9_DAD5 (*((volatile unsigned int*)(0x4380C46CUL))) +#define bM4_USBFS_HCCHAR9_DAD6 (*((volatile unsigned int*)(0x4380C470UL))) +#define bM4_USBFS_HCCHAR9_ODDFRM (*((volatile unsigned int*)(0x4380C474UL))) +#define bM4_USBFS_HCCHAR9_CHDIS (*((volatile unsigned int*)(0x4380C478UL))) +#define bM4_USBFS_HCCHAR9_CHENA (*((volatile unsigned int*)(0x4380C47CUL))) +#define bM4_USBFS_HCINT9_XFRC (*((volatile unsigned int*)(0x4380C500UL))) +#define bM4_USBFS_HCINT9_CHH (*((volatile unsigned int*)(0x4380C504UL))) +#define bM4_USBFS_HCINT9_STALL (*((volatile unsigned int*)(0x4380C50CUL))) +#define bM4_USBFS_HCINT9_NAK (*((volatile unsigned int*)(0x4380C510UL))) +#define bM4_USBFS_HCINT9_ACK (*((volatile unsigned int*)(0x4380C514UL))) +#define bM4_USBFS_HCINT9_TXERR (*((volatile unsigned int*)(0x4380C51CUL))) +#define bM4_USBFS_HCINT9_BBERR (*((volatile unsigned int*)(0x4380C520UL))) +#define bM4_USBFS_HCINT9_FRMOR (*((volatile unsigned int*)(0x4380C524UL))) +#define bM4_USBFS_HCINT9_DTERR (*((volatile unsigned int*)(0x4380C528UL))) +#define bM4_USBFS_HCINTMSK9_XFRCM (*((volatile unsigned int*)(0x4380C580UL))) +#define bM4_USBFS_HCINTMSK9_CHHM (*((volatile unsigned int*)(0x4380C584UL))) +#define bM4_USBFS_HCINTMSK9_STALLM (*((volatile unsigned int*)(0x4380C58CUL))) +#define bM4_USBFS_HCINTMSK9_NAKM (*((volatile unsigned int*)(0x4380C590UL))) +#define bM4_USBFS_HCINTMSK9_ACKM (*((volatile unsigned int*)(0x4380C594UL))) +#define bM4_USBFS_HCINTMSK9_TXERRM (*((volatile unsigned int*)(0x4380C59CUL))) +#define bM4_USBFS_HCINTMSK9_BBERRM (*((volatile unsigned int*)(0x4380C5A0UL))) +#define bM4_USBFS_HCINTMSK9_FRMORM (*((volatile unsigned int*)(0x4380C5A4UL))) +#define bM4_USBFS_HCINTMSK9_DTERRM (*((volatile unsigned int*)(0x4380C5A8UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ0 (*((volatile unsigned int*)(0x4380C600UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ1 (*((volatile unsigned int*)(0x4380C604UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ2 (*((volatile unsigned int*)(0x4380C608UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ3 (*((volatile unsigned int*)(0x4380C60CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ4 (*((volatile unsigned int*)(0x4380C610UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ5 (*((volatile unsigned int*)(0x4380C614UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ6 (*((volatile unsigned int*)(0x4380C618UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ7 (*((volatile unsigned int*)(0x4380C61CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ8 (*((volatile unsigned int*)(0x4380C620UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ9 (*((volatile unsigned int*)(0x4380C624UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ10 (*((volatile unsigned int*)(0x4380C628UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ11 (*((volatile unsigned int*)(0x4380C62CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ12 (*((volatile unsigned int*)(0x4380C630UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ13 (*((volatile unsigned int*)(0x4380C634UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ14 (*((volatile unsigned int*)(0x4380C638UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ15 (*((volatile unsigned int*)(0x4380C63CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ16 (*((volatile unsigned int*)(0x4380C640UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ17 (*((volatile unsigned int*)(0x4380C644UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ18 (*((volatile unsigned int*)(0x4380C648UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT0 (*((volatile unsigned int*)(0x4380C64CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT1 (*((volatile unsigned int*)(0x4380C650UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT2 (*((volatile unsigned int*)(0x4380C654UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT3 (*((volatile unsigned int*)(0x4380C658UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT4 (*((volatile unsigned int*)(0x4380C65CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT5 (*((volatile unsigned int*)(0x4380C660UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT6 (*((volatile unsigned int*)(0x4380C664UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT7 (*((volatile unsigned int*)(0x4380C668UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT8 (*((volatile unsigned int*)(0x4380C66CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT9 (*((volatile unsigned int*)(0x4380C670UL))) +#define bM4_USBFS_HCTSIZ9_DPID0 (*((volatile unsigned int*)(0x4380C674UL))) +#define bM4_USBFS_HCTSIZ9_DPID1 (*((volatile unsigned int*)(0x4380C678UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ0 (*((volatile unsigned int*)(0x4380C800UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ1 (*((volatile unsigned int*)(0x4380C804UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ2 (*((volatile unsigned int*)(0x4380C808UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ3 (*((volatile unsigned int*)(0x4380C80CUL))) +#define bM4_USBFS_HCCHAR10_MPSIZ4 (*((volatile unsigned int*)(0x4380C810UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ5 (*((volatile unsigned int*)(0x4380C814UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ6 (*((volatile unsigned int*)(0x4380C818UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ7 (*((volatile unsigned int*)(0x4380C81CUL))) +#define bM4_USBFS_HCCHAR10_MPSIZ8 (*((volatile unsigned int*)(0x4380C820UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ9 (*((volatile unsigned int*)(0x4380C824UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ10 (*((volatile unsigned int*)(0x4380C828UL))) +#define bM4_USBFS_HCCHAR10_EPNUM0 (*((volatile unsigned int*)(0x4380C82CUL))) +#define bM4_USBFS_HCCHAR10_EPNUM1 (*((volatile unsigned int*)(0x4380C830UL))) +#define bM4_USBFS_HCCHAR10_EPNUM2 (*((volatile unsigned int*)(0x4380C834UL))) +#define bM4_USBFS_HCCHAR10_EPNUM3 (*((volatile unsigned int*)(0x4380C838UL))) +#define bM4_USBFS_HCCHAR10_EPDIR (*((volatile unsigned int*)(0x4380C83CUL))) +#define bM4_USBFS_HCCHAR10_LSDEV (*((volatile unsigned int*)(0x4380C844UL))) +#define bM4_USBFS_HCCHAR10_EPTYP0 (*((volatile unsigned int*)(0x4380C848UL))) +#define bM4_USBFS_HCCHAR10_EPTYP1 (*((volatile unsigned int*)(0x4380C84CUL))) +#define bM4_USBFS_HCCHAR10_DAD0 (*((volatile unsigned int*)(0x4380C858UL))) +#define bM4_USBFS_HCCHAR10_DAD1 (*((volatile unsigned int*)(0x4380C85CUL))) +#define bM4_USBFS_HCCHAR10_DAD2 (*((volatile unsigned int*)(0x4380C860UL))) +#define bM4_USBFS_HCCHAR10_DAD3 (*((volatile unsigned int*)(0x4380C864UL))) +#define bM4_USBFS_HCCHAR10_DAD4 (*((volatile unsigned int*)(0x4380C868UL))) +#define bM4_USBFS_HCCHAR10_DAD5 (*((volatile unsigned int*)(0x4380C86CUL))) +#define bM4_USBFS_HCCHAR10_DAD6 (*((volatile unsigned int*)(0x4380C870UL))) +#define bM4_USBFS_HCCHAR10_ODDFRM (*((volatile unsigned int*)(0x4380C874UL))) +#define bM4_USBFS_HCCHAR10_CHDIS (*((volatile unsigned int*)(0x4380C878UL))) +#define bM4_USBFS_HCCHAR10_CHENA (*((volatile unsigned int*)(0x4380C87CUL))) +#define bM4_USBFS_HCINT10_XFRC (*((volatile unsigned int*)(0x4380C900UL))) +#define bM4_USBFS_HCINT10_CHH (*((volatile unsigned int*)(0x4380C904UL))) +#define bM4_USBFS_HCINT10_STALL (*((volatile unsigned int*)(0x4380C90CUL))) +#define bM4_USBFS_HCINT10_NAK (*((volatile unsigned int*)(0x4380C910UL))) +#define bM4_USBFS_HCINT10_ACK (*((volatile unsigned int*)(0x4380C914UL))) +#define bM4_USBFS_HCINT10_TXERR (*((volatile unsigned int*)(0x4380C91CUL))) +#define bM4_USBFS_HCINT10_BBERR (*((volatile unsigned int*)(0x4380C920UL))) +#define bM4_USBFS_HCINT10_FRMOR (*((volatile unsigned int*)(0x4380C924UL))) +#define bM4_USBFS_HCINT10_DTERR (*((volatile unsigned int*)(0x4380C928UL))) +#define bM4_USBFS_HCINTMSK10_XFRCM (*((volatile unsigned int*)(0x4380C980UL))) +#define bM4_USBFS_HCINTMSK10_CHHM (*((volatile unsigned int*)(0x4380C984UL))) +#define bM4_USBFS_HCINTMSK10_STALLM (*((volatile unsigned int*)(0x4380C98CUL))) +#define bM4_USBFS_HCINTMSK10_NAKM (*((volatile unsigned int*)(0x4380C990UL))) +#define bM4_USBFS_HCINTMSK10_ACKM (*((volatile unsigned int*)(0x4380C994UL))) +#define bM4_USBFS_HCINTMSK10_TXERRM (*((volatile unsigned int*)(0x4380C99CUL))) +#define bM4_USBFS_HCINTMSK10_BBERRM (*((volatile unsigned int*)(0x4380C9A0UL))) +#define bM4_USBFS_HCINTMSK10_FRMORM (*((volatile unsigned int*)(0x4380C9A4UL))) +#define bM4_USBFS_HCINTMSK10_DTERRM (*((volatile unsigned int*)(0x4380C9A8UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ0 (*((volatile unsigned int*)(0x4380CA00UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ1 (*((volatile unsigned int*)(0x4380CA04UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ2 (*((volatile unsigned int*)(0x4380CA08UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ3 (*((volatile unsigned int*)(0x4380CA0CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ4 (*((volatile unsigned int*)(0x4380CA10UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ5 (*((volatile unsigned int*)(0x4380CA14UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ6 (*((volatile unsigned int*)(0x4380CA18UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ7 (*((volatile unsigned int*)(0x4380CA1CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ8 (*((volatile unsigned int*)(0x4380CA20UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ9 (*((volatile unsigned int*)(0x4380CA24UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ10 (*((volatile unsigned int*)(0x4380CA28UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ11 (*((volatile unsigned int*)(0x4380CA2CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ12 (*((volatile unsigned int*)(0x4380CA30UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ13 (*((volatile unsigned int*)(0x4380CA34UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ14 (*((volatile unsigned int*)(0x4380CA38UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ15 (*((volatile unsigned int*)(0x4380CA3CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ16 (*((volatile unsigned int*)(0x4380CA40UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ17 (*((volatile unsigned int*)(0x4380CA44UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ18 (*((volatile unsigned int*)(0x4380CA48UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT0 (*((volatile unsigned int*)(0x4380CA4CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT1 (*((volatile unsigned int*)(0x4380CA50UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT2 (*((volatile unsigned int*)(0x4380CA54UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT3 (*((volatile unsigned int*)(0x4380CA58UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT4 (*((volatile unsigned int*)(0x4380CA5CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT5 (*((volatile unsigned int*)(0x4380CA60UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT6 (*((volatile unsigned int*)(0x4380CA64UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT7 (*((volatile unsigned int*)(0x4380CA68UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT8 (*((volatile unsigned int*)(0x4380CA6CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT9 (*((volatile unsigned int*)(0x4380CA70UL))) +#define bM4_USBFS_HCTSIZ10_DPID0 (*((volatile unsigned int*)(0x4380CA74UL))) +#define bM4_USBFS_HCTSIZ10_DPID1 (*((volatile unsigned int*)(0x4380CA78UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ0 (*((volatile unsigned int*)(0x4380CC00UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ1 (*((volatile unsigned int*)(0x4380CC04UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ2 (*((volatile unsigned int*)(0x4380CC08UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ3 (*((volatile unsigned int*)(0x4380CC0CUL))) +#define bM4_USBFS_HCCHAR11_MPSIZ4 (*((volatile unsigned int*)(0x4380CC10UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ5 (*((volatile unsigned int*)(0x4380CC14UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ6 (*((volatile unsigned int*)(0x4380CC18UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ7 (*((volatile unsigned int*)(0x4380CC1CUL))) +#define bM4_USBFS_HCCHAR11_MPSIZ8 (*((volatile unsigned int*)(0x4380CC20UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ9 (*((volatile unsigned int*)(0x4380CC24UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ10 (*((volatile unsigned int*)(0x4380CC28UL))) +#define bM4_USBFS_HCCHAR11_EPNUM0 (*((volatile unsigned int*)(0x4380CC2CUL))) +#define bM4_USBFS_HCCHAR11_EPNUM1 (*((volatile unsigned int*)(0x4380CC30UL))) +#define bM4_USBFS_HCCHAR11_EPNUM2 (*((volatile unsigned int*)(0x4380CC34UL))) +#define bM4_USBFS_HCCHAR11_EPNUM3 (*((volatile unsigned int*)(0x4380CC38UL))) +#define bM4_USBFS_HCCHAR11_EPDIR (*((volatile unsigned int*)(0x4380CC3CUL))) +#define bM4_USBFS_HCCHAR11_LSDEV (*((volatile unsigned int*)(0x4380CC44UL))) +#define bM4_USBFS_HCCHAR11_EPTYP0 (*((volatile unsigned int*)(0x4380CC48UL))) +#define bM4_USBFS_HCCHAR11_EPTYP1 (*((volatile unsigned int*)(0x4380CC4CUL))) +#define bM4_USBFS_HCCHAR11_DAD0 (*((volatile unsigned int*)(0x4380CC58UL))) +#define bM4_USBFS_HCCHAR11_DAD1 (*((volatile unsigned int*)(0x4380CC5CUL))) +#define bM4_USBFS_HCCHAR11_DAD2 (*((volatile unsigned int*)(0x4380CC60UL))) +#define bM4_USBFS_HCCHAR11_DAD3 (*((volatile unsigned int*)(0x4380CC64UL))) +#define bM4_USBFS_HCCHAR11_DAD4 (*((volatile unsigned int*)(0x4380CC68UL))) +#define bM4_USBFS_HCCHAR11_DAD5 (*((volatile unsigned int*)(0x4380CC6CUL))) +#define bM4_USBFS_HCCHAR11_DAD6 (*((volatile unsigned int*)(0x4380CC70UL))) +#define bM4_USBFS_HCCHAR11_ODDFRM (*((volatile unsigned int*)(0x4380CC74UL))) +#define bM4_USBFS_HCCHAR11_CHDIS (*((volatile unsigned int*)(0x4380CC78UL))) +#define bM4_USBFS_HCCHAR11_CHENA (*((volatile unsigned int*)(0x4380CC7CUL))) +#define bM4_USBFS_HCINT11_XFRC (*((volatile unsigned int*)(0x4380CD00UL))) +#define bM4_USBFS_HCINT11_CHH (*((volatile unsigned int*)(0x4380CD04UL))) +#define bM4_USBFS_HCINT11_STALL (*((volatile unsigned int*)(0x4380CD0CUL))) +#define bM4_USBFS_HCINT11_NAK (*((volatile unsigned int*)(0x4380CD10UL))) +#define bM4_USBFS_HCINT11_ACK (*((volatile unsigned int*)(0x4380CD14UL))) +#define bM4_USBFS_HCINT11_TXERR (*((volatile unsigned int*)(0x4380CD1CUL))) +#define bM4_USBFS_HCINT11_BBERR (*((volatile unsigned int*)(0x4380CD20UL))) +#define bM4_USBFS_HCINT11_FRMOR (*((volatile unsigned int*)(0x4380CD24UL))) +#define bM4_USBFS_HCINT11_DTERR (*((volatile unsigned int*)(0x4380CD28UL))) +#define bM4_USBFS_HCINTMSK11_XFRCM (*((volatile unsigned int*)(0x4380CD80UL))) +#define bM4_USBFS_HCINTMSK11_CHHM (*((volatile unsigned int*)(0x4380CD84UL))) +#define bM4_USBFS_HCINTMSK11_STALLM (*((volatile unsigned int*)(0x4380CD8CUL))) +#define bM4_USBFS_HCINTMSK11_NAKM (*((volatile unsigned int*)(0x4380CD90UL))) +#define bM4_USBFS_HCINTMSK11_ACKM (*((volatile unsigned int*)(0x4380CD94UL))) +#define bM4_USBFS_HCINTMSK11_TXERRM (*((volatile unsigned int*)(0x4380CD9CUL))) +#define bM4_USBFS_HCINTMSK11_BBERRM (*((volatile unsigned int*)(0x4380CDA0UL))) +#define bM4_USBFS_HCINTMSK11_FRMORM (*((volatile unsigned int*)(0x4380CDA4UL))) +#define bM4_USBFS_HCINTMSK11_DTERRM (*((volatile unsigned int*)(0x4380CDA8UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ0 (*((volatile unsigned int*)(0x4380CE00UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ1 (*((volatile unsigned int*)(0x4380CE04UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ2 (*((volatile unsigned int*)(0x4380CE08UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ3 (*((volatile unsigned int*)(0x4380CE0CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ4 (*((volatile unsigned int*)(0x4380CE10UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ5 (*((volatile unsigned int*)(0x4380CE14UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ6 (*((volatile unsigned int*)(0x4380CE18UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ7 (*((volatile unsigned int*)(0x4380CE1CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ8 (*((volatile unsigned int*)(0x4380CE20UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ9 (*((volatile unsigned int*)(0x4380CE24UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ10 (*((volatile unsigned int*)(0x4380CE28UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ11 (*((volatile unsigned int*)(0x4380CE2CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ12 (*((volatile unsigned int*)(0x4380CE30UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ13 (*((volatile unsigned int*)(0x4380CE34UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ14 (*((volatile unsigned int*)(0x4380CE38UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ15 (*((volatile unsigned int*)(0x4380CE3CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ16 (*((volatile unsigned int*)(0x4380CE40UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ17 (*((volatile unsigned int*)(0x4380CE44UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ18 (*((volatile unsigned int*)(0x4380CE48UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT0 (*((volatile unsigned int*)(0x4380CE4CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT1 (*((volatile unsigned int*)(0x4380CE50UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT2 (*((volatile unsigned int*)(0x4380CE54UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT3 (*((volatile unsigned int*)(0x4380CE58UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT4 (*((volatile unsigned int*)(0x4380CE5CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT5 (*((volatile unsigned int*)(0x4380CE60UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT6 (*((volatile unsigned int*)(0x4380CE64UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT7 (*((volatile unsigned int*)(0x4380CE68UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT8 (*((volatile unsigned int*)(0x4380CE6CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT9 (*((volatile unsigned int*)(0x4380CE70UL))) +#define bM4_USBFS_HCTSIZ11_DPID0 (*((volatile unsigned int*)(0x4380CE74UL))) +#define bM4_USBFS_HCTSIZ11_DPID1 (*((volatile unsigned int*)(0x4380CE78UL))) +#define bM4_USBFS_DCFG_DSPD0 (*((volatile unsigned int*)(0x43810000UL))) +#define bM4_USBFS_DCFG_DSPD1 (*((volatile unsigned int*)(0x43810004UL))) +#define bM4_USBFS_DCFG_NZLSOHSK (*((volatile unsigned int*)(0x43810008UL))) +#define bM4_USBFS_DCFG_DAD0 (*((volatile unsigned int*)(0x43810010UL))) +#define bM4_USBFS_DCFG_DAD1 (*((volatile unsigned int*)(0x43810014UL))) +#define bM4_USBFS_DCFG_DAD2 (*((volatile unsigned int*)(0x43810018UL))) +#define bM4_USBFS_DCFG_DAD3 (*((volatile unsigned int*)(0x4381001CUL))) +#define bM4_USBFS_DCFG_DAD4 (*((volatile unsigned int*)(0x43810020UL))) +#define bM4_USBFS_DCFG_DAD5 (*((volatile unsigned int*)(0x43810024UL))) +#define bM4_USBFS_DCFG_DAD6 (*((volatile unsigned int*)(0x43810028UL))) +#define bM4_USBFS_DCFG_PFIVL0 (*((volatile unsigned int*)(0x4381002CUL))) +#define bM4_USBFS_DCFG_PFIVL1 (*((volatile unsigned int*)(0x43810030UL))) +#define bM4_USBFS_DCTL_RWUSIG (*((volatile unsigned int*)(0x43810080UL))) +#define bM4_USBFS_DCTL_SDIS (*((volatile unsigned int*)(0x43810084UL))) +#define bM4_USBFS_DCTL_GINSTS (*((volatile unsigned int*)(0x43810088UL))) +#define bM4_USBFS_DCTL_GONSTS (*((volatile unsigned int*)(0x4381008CUL))) +#define bM4_USBFS_DCTL_SGINAK (*((volatile unsigned int*)(0x4381009CUL))) +#define bM4_USBFS_DCTL_CGINAK (*((volatile unsigned int*)(0x438100A0UL))) +#define bM4_USBFS_DCTL_SGONAK (*((volatile unsigned int*)(0x438100A4UL))) +#define bM4_USBFS_DCTL_CGONAK (*((volatile unsigned int*)(0x438100A8UL))) +#define bM4_USBFS_DCTL_POPRGDNE (*((volatile unsigned int*)(0x438100ACUL))) +#define bM4_USBFS_DSTS_SUSPSTS (*((volatile unsigned int*)(0x43810100UL))) +#define bM4_USBFS_DSTS_ENUMSPD0 (*((volatile unsigned int*)(0x43810104UL))) +#define bM4_USBFS_DSTS_ENUMSPD1 (*((volatile unsigned int*)(0x43810108UL))) +#define bM4_USBFS_DSTS_EERR (*((volatile unsigned int*)(0x4381010CUL))) +#define bM4_USBFS_DSTS_FNSOF0 (*((volatile unsigned int*)(0x43810120UL))) +#define bM4_USBFS_DSTS_FNSOF1 (*((volatile unsigned int*)(0x43810124UL))) +#define bM4_USBFS_DSTS_FNSOF2 (*((volatile unsigned int*)(0x43810128UL))) +#define bM4_USBFS_DSTS_FNSOF3 (*((volatile unsigned int*)(0x4381012CUL))) +#define bM4_USBFS_DSTS_FNSOF4 (*((volatile unsigned int*)(0x43810130UL))) +#define bM4_USBFS_DSTS_FNSOF5 (*((volatile unsigned int*)(0x43810134UL))) +#define bM4_USBFS_DSTS_FNSOF6 (*((volatile unsigned int*)(0x43810138UL))) +#define bM4_USBFS_DSTS_FNSOF7 (*((volatile unsigned int*)(0x4381013CUL))) +#define bM4_USBFS_DSTS_FNSOF8 (*((volatile unsigned int*)(0x43810140UL))) +#define bM4_USBFS_DSTS_FNSOF9 (*((volatile unsigned int*)(0x43810144UL))) +#define bM4_USBFS_DSTS_FNSOF10 (*((volatile unsigned int*)(0x43810148UL))) +#define bM4_USBFS_DSTS_FNSOF11 (*((volatile unsigned int*)(0x4381014CUL))) +#define bM4_USBFS_DSTS_FNSOF12 (*((volatile unsigned int*)(0x43810150UL))) +#define bM4_USBFS_DSTS_FNSOF13 (*((volatile unsigned int*)(0x43810154UL))) +#define bM4_USBFS_DIEPMSK_XFRCM (*((volatile unsigned int*)(0x43810200UL))) +#define bM4_USBFS_DIEPMSK_EPDM (*((volatile unsigned int*)(0x43810204UL))) +#define bM4_USBFS_DIEPMSK_TOM (*((volatile unsigned int*)(0x4381020CUL))) +#define bM4_USBFS_DIEPMSK_ITTXFEMSK (*((volatile unsigned int*)(0x43810210UL))) +#define bM4_USBFS_DIEPMSK_INEPNMM (*((volatile unsigned int*)(0x43810214UL))) +#define bM4_USBFS_DIEPMSK_INEPNEM (*((volatile unsigned int*)(0x43810218UL))) +#define bM4_USBFS_DOEPMSK_XFRCM (*((volatile unsigned int*)(0x43810280UL))) +#define bM4_USBFS_DOEPMSK_EPDM (*((volatile unsigned int*)(0x43810284UL))) +#define bM4_USBFS_DOEPMSK_STUPM (*((volatile unsigned int*)(0x4381028CUL))) +#define bM4_USBFS_DOEPMSK_OTEPDM (*((volatile unsigned int*)(0x43810290UL))) +#define bM4_USBFS_DAINT_IEPINT0 (*((volatile unsigned int*)(0x43810300UL))) +#define bM4_USBFS_DAINT_IEPINT1 (*((volatile unsigned int*)(0x43810304UL))) +#define bM4_USBFS_DAINT_IEPINT2 (*((volatile unsigned int*)(0x43810308UL))) +#define bM4_USBFS_DAINT_IEPINT3 (*((volatile unsigned int*)(0x4381030CUL))) +#define bM4_USBFS_DAINT_IEPINT4 (*((volatile unsigned int*)(0x43810310UL))) +#define bM4_USBFS_DAINT_IEPINT5 (*((volatile unsigned int*)(0x43810314UL))) +#define bM4_USBFS_DAINT_OEPINT0 (*((volatile unsigned int*)(0x43810340UL))) +#define bM4_USBFS_DAINT_OEPINT1 (*((volatile unsigned int*)(0x43810344UL))) +#define bM4_USBFS_DAINT_OEPINT2 (*((volatile unsigned int*)(0x43810348UL))) +#define bM4_USBFS_DAINT_OEPINT3 (*((volatile unsigned int*)(0x4381034CUL))) +#define bM4_USBFS_DAINT_OEPINT4 (*((volatile unsigned int*)(0x43810350UL))) +#define bM4_USBFS_DAINT_OEPINT5 (*((volatile unsigned int*)(0x43810354UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM0 (*((volatile unsigned int*)(0x43810380UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM1 (*((volatile unsigned int*)(0x43810384UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM2 (*((volatile unsigned int*)(0x43810388UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM3 (*((volatile unsigned int*)(0x4381038CUL))) +#define bM4_USBFS_DAINTMSK_IEPINTM4 (*((volatile unsigned int*)(0x43810390UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM5 (*((volatile unsigned int*)(0x43810394UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM0 (*((volatile unsigned int*)(0x438103C0UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM1 (*((volatile unsigned int*)(0x438103C4UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM2 (*((volatile unsigned int*)(0x438103C8UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM3 (*((volatile unsigned int*)(0x438103CCUL))) +#define bM4_USBFS_DAINTMSK_OEPINTM4 (*((volatile unsigned int*)(0x438103D0UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM5 (*((volatile unsigned int*)(0x438103D4UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM0 (*((volatile unsigned int*)(0x43810680UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM1 (*((volatile unsigned int*)(0x43810684UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM2 (*((volatile unsigned int*)(0x43810688UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM3 (*((volatile unsigned int*)(0x4381068CUL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM4 (*((volatile unsigned int*)(0x43810690UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM5 (*((volatile unsigned int*)(0x43810694UL))) +#define bM4_USBFS_DIEPCTL0_MPSIZ0 (*((volatile unsigned int*)(0x43812000UL))) +#define bM4_USBFS_DIEPCTL0_MPSIZ1 (*((volatile unsigned int*)(0x43812004UL))) +#define bM4_USBFS_DIEPCTL0_USBAEP (*((volatile unsigned int*)(0x4381203CUL))) +#define bM4_USBFS_DIEPCTL0_NAKSTS (*((volatile unsigned int*)(0x43812044UL))) +#define bM4_USBFS_DIEPCTL0_EPTYP0 (*((volatile unsigned int*)(0x43812048UL))) +#define bM4_USBFS_DIEPCTL0_EPTYP1 (*((volatile unsigned int*)(0x4381204CUL))) +#define bM4_USBFS_DIEPCTL0_STALL (*((volatile unsigned int*)(0x43812054UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM0 (*((volatile unsigned int*)(0x43812058UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM1 (*((volatile unsigned int*)(0x4381205CUL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM2 (*((volatile unsigned int*)(0x43812060UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM3 (*((volatile unsigned int*)(0x43812064UL))) +#define bM4_USBFS_DIEPCTL0_CNAK (*((volatile unsigned int*)(0x43812068UL))) +#define bM4_USBFS_DIEPCTL0_SNAK (*((volatile unsigned int*)(0x4381206CUL))) +#define bM4_USBFS_DIEPCTL0_EPDIS (*((volatile unsigned int*)(0x43812078UL))) +#define bM4_USBFS_DIEPCTL0_EPENA (*((volatile unsigned int*)(0x4381207CUL))) +#define bM4_USBFS_DIEPINT0_XFRC (*((volatile unsigned int*)(0x43812100UL))) +#define bM4_USBFS_DIEPINT0_EPDISD (*((volatile unsigned int*)(0x43812104UL))) +#define bM4_USBFS_DIEPINT0_TOC (*((volatile unsigned int*)(0x4381210CUL))) +#define bM4_USBFS_DIEPINT0_TTXFE (*((volatile unsigned int*)(0x43812110UL))) +#define bM4_USBFS_DIEPINT0_INEPNE (*((volatile unsigned int*)(0x43812118UL))) +#define bM4_USBFS_DIEPINT0_TXFE (*((volatile unsigned int*)(0x4381211CUL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x43812200UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x43812204UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x43812208UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4381220CUL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x43812210UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x43812214UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x43812218UL))) +#define bM4_USBFS_DIEPTSIZ0_PKTCNT0 (*((volatile unsigned int*)(0x4381224CUL))) +#define bM4_USBFS_DIEPTSIZ0_PKTCNT1 (*((volatile unsigned int*)(0x43812250UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV0 (*((volatile unsigned int*)(0x43812300UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV1 (*((volatile unsigned int*)(0x43812304UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV2 (*((volatile unsigned int*)(0x43812308UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV3 (*((volatile unsigned int*)(0x4381230CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV4 (*((volatile unsigned int*)(0x43812310UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV5 (*((volatile unsigned int*)(0x43812314UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV6 (*((volatile unsigned int*)(0x43812318UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV7 (*((volatile unsigned int*)(0x4381231CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV8 (*((volatile unsigned int*)(0x43812320UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV9 (*((volatile unsigned int*)(0x43812324UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV10 (*((volatile unsigned int*)(0x43812328UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV11 (*((volatile unsigned int*)(0x4381232CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV12 (*((volatile unsigned int*)(0x43812330UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV13 (*((volatile unsigned int*)(0x43812334UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV14 (*((volatile unsigned int*)(0x43812338UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV15 (*((volatile unsigned int*)(0x4381233CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ0 (*((volatile unsigned int*)(0x43812400UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ1 (*((volatile unsigned int*)(0x43812404UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ2 (*((volatile unsigned int*)(0x43812408UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ3 (*((volatile unsigned int*)(0x4381240CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ4 (*((volatile unsigned int*)(0x43812410UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ5 (*((volatile unsigned int*)(0x43812414UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ6 (*((volatile unsigned int*)(0x43812418UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ7 (*((volatile unsigned int*)(0x4381241CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ8 (*((volatile unsigned int*)(0x43812420UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ9 (*((volatile unsigned int*)(0x43812424UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ10 (*((volatile unsigned int*)(0x43812428UL))) +#define bM4_USBFS_DIEPCTL1_USBAEP (*((volatile unsigned int*)(0x4381243CUL))) +#define bM4_USBFS_DIEPCTL1_EONUM_DPID (*((volatile unsigned int*)(0x43812440UL))) +#define bM4_USBFS_DIEPCTL1_NAKSTS (*((volatile unsigned int*)(0x43812444UL))) +#define bM4_USBFS_DIEPCTL1_EPTYP0 (*((volatile unsigned int*)(0x43812448UL))) +#define bM4_USBFS_DIEPCTL1_EPTYP1 (*((volatile unsigned int*)(0x4381244CUL))) +#define bM4_USBFS_DIEPCTL1_STALL (*((volatile unsigned int*)(0x43812454UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM0 (*((volatile unsigned int*)(0x43812458UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM1 (*((volatile unsigned int*)(0x4381245CUL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM2 (*((volatile unsigned int*)(0x43812460UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM3 (*((volatile unsigned int*)(0x43812464UL))) +#define bM4_USBFS_DIEPCTL1_CNAK (*((volatile unsigned int*)(0x43812468UL))) +#define bM4_USBFS_DIEPCTL1_SNAK (*((volatile unsigned int*)(0x4381246CUL))) +#define bM4_USBFS_DIEPCTL1_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812470UL))) +#define bM4_USBFS_DIEPCTL1_SODDFRM (*((volatile unsigned int*)(0x43812474UL))) +#define bM4_USBFS_DIEPCTL1_EPDIS (*((volatile unsigned int*)(0x43812478UL))) +#define bM4_USBFS_DIEPCTL1_EPENA (*((volatile unsigned int*)(0x4381247CUL))) +#define bM4_USBFS_DIEPINT1_XFRC (*((volatile unsigned int*)(0x43812500UL))) +#define bM4_USBFS_DIEPINT1_EPDISD (*((volatile unsigned int*)(0x43812504UL))) +#define bM4_USBFS_DIEPINT1_TOC (*((volatile unsigned int*)(0x4381250CUL))) +#define bM4_USBFS_DIEPINT1_TTXFE (*((volatile unsigned int*)(0x43812510UL))) +#define bM4_USBFS_DIEPINT1_INEPNE (*((volatile unsigned int*)(0x43812518UL))) +#define bM4_USBFS_DIEPINT1_TXFE (*((volatile unsigned int*)(0x4381251CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x43812600UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x43812604UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x43812608UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4381260CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x43812610UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x43812614UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x43812618UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4381261CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x43812620UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x43812624UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x43812628UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4381262CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x43812630UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x43812634UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x43812638UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4381263CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x43812640UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x43812644UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x43812648UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4381264CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x43812650UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x43812654UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x43812658UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4381265CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x43812660UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x43812664UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x43812668UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4381266CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x43812670UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV0 (*((volatile unsigned int*)(0x43812700UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV1 (*((volatile unsigned int*)(0x43812704UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV2 (*((volatile unsigned int*)(0x43812708UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV3 (*((volatile unsigned int*)(0x4381270CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV4 (*((volatile unsigned int*)(0x43812710UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV5 (*((volatile unsigned int*)(0x43812714UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV6 (*((volatile unsigned int*)(0x43812718UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV7 (*((volatile unsigned int*)(0x4381271CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV8 (*((volatile unsigned int*)(0x43812720UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV9 (*((volatile unsigned int*)(0x43812724UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV10 (*((volatile unsigned int*)(0x43812728UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV11 (*((volatile unsigned int*)(0x4381272CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV12 (*((volatile unsigned int*)(0x43812730UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV13 (*((volatile unsigned int*)(0x43812734UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV14 (*((volatile unsigned int*)(0x43812738UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV15 (*((volatile unsigned int*)(0x4381273CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ0 (*((volatile unsigned int*)(0x43812800UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ1 (*((volatile unsigned int*)(0x43812804UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ2 (*((volatile unsigned int*)(0x43812808UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ3 (*((volatile unsigned int*)(0x4381280CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ4 (*((volatile unsigned int*)(0x43812810UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ5 (*((volatile unsigned int*)(0x43812814UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ6 (*((volatile unsigned int*)(0x43812818UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ7 (*((volatile unsigned int*)(0x4381281CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ8 (*((volatile unsigned int*)(0x43812820UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ9 (*((volatile unsigned int*)(0x43812824UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ10 (*((volatile unsigned int*)(0x43812828UL))) +#define bM4_USBFS_DIEPCTL2_USBAEP (*((volatile unsigned int*)(0x4381283CUL))) +#define bM4_USBFS_DIEPCTL2_EONUM_DPID (*((volatile unsigned int*)(0x43812840UL))) +#define bM4_USBFS_DIEPCTL2_NAKSTS (*((volatile unsigned int*)(0x43812844UL))) +#define bM4_USBFS_DIEPCTL2_EPTYP0 (*((volatile unsigned int*)(0x43812848UL))) +#define bM4_USBFS_DIEPCTL2_EPTYP1 (*((volatile unsigned int*)(0x4381284CUL))) +#define bM4_USBFS_DIEPCTL2_STALL (*((volatile unsigned int*)(0x43812854UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM0 (*((volatile unsigned int*)(0x43812858UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM1 (*((volatile unsigned int*)(0x4381285CUL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM2 (*((volatile unsigned int*)(0x43812860UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM3 (*((volatile unsigned int*)(0x43812864UL))) +#define bM4_USBFS_DIEPCTL2_CNAK (*((volatile unsigned int*)(0x43812868UL))) +#define bM4_USBFS_DIEPCTL2_SNAK (*((volatile unsigned int*)(0x4381286CUL))) +#define bM4_USBFS_DIEPCTL2_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812870UL))) +#define bM4_USBFS_DIEPCTL2_SODDFRM (*((volatile unsigned int*)(0x43812874UL))) +#define bM4_USBFS_DIEPCTL2_EPDIS (*((volatile unsigned int*)(0x43812878UL))) +#define bM4_USBFS_DIEPCTL2_EPENA (*((volatile unsigned int*)(0x4381287CUL))) +#define bM4_USBFS_DIEPINT2_XFRC (*((volatile unsigned int*)(0x43812900UL))) +#define bM4_USBFS_DIEPINT2_EPDISD (*((volatile unsigned int*)(0x43812904UL))) +#define bM4_USBFS_DIEPINT2_TOC (*((volatile unsigned int*)(0x4381290CUL))) +#define bM4_USBFS_DIEPINT2_TTXFE (*((volatile unsigned int*)(0x43812910UL))) +#define bM4_USBFS_DIEPINT2_INEPNE (*((volatile unsigned int*)(0x43812918UL))) +#define bM4_USBFS_DIEPINT2_TXFE (*((volatile unsigned int*)(0x4381291CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x43812A00UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x43812A04UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x43812A08UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x43812A0CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x43812A10UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x43812A14UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x43812A18UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x43812A1CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x43812A20UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x43812A24UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x43812A28UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x43812A2CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x43812A30UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x43812A34UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x43812A38UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x43812A3CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x43812A40UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x43812A44UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x43812A48UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x43812A4CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x43812A50UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x43812A54UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x43812A58UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x43812A5CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x43812A60UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x43812A64UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x43812A68UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x43812A6CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x43812A70UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV0 (*((volatile unsigned int*)(0x43812B00UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV1 (*((volatile unsigned int*)(0x43812B04UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV2 (*((volatile unsigned int*)(0x43812B08UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV3 (*((volatile unsigned int*)(0x43812B0CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV4 (*((volatile unsigned int*)(0x43812B10UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV5 (*((volatile unsigned int*)(0x43812B14UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV6 (*((volatile unsigned int*)(0x43812B18UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV7 (*((volatile unsigned int*)(0x43812B1CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV8 (*((volatile unsigned int*)(0x43812B20UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV9 (*((volatile unsigned int*)(0x43812B24UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV10 (*((volatile unsigned int*)(0x43812B28UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV11 (*((volatile unsigned int*)(0x43812B2CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV12 (*((volatile unsigned int*)(0x43812B30UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV13 (*((volatile unsigned int*)(0x43812B34UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV14 (*((volatile unsigned int*)(0x43812B38UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV15 (*((volatile unsigned int*)(0x43812B3CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ0 (*((volatile unsigned int*)(0x43812C00UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ1 (*((volatile unsigned int*)(0x43812C04UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ2 (*((volatile unsigned int*)(0x43812C08UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ3 (*((volatile unsigned int*)(0x43812C0CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ4 (*((volatile unsigned int*)(0x43812C10UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ5 (*((volatile unsigned int*)(0x43812C14UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ6 (*((volatile unsigned int*)(0x43812C18UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ7 (*((volatile unsigned int*)(0x43812C1CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ8 (*((volatile unsigned int*)(0x43812C20UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ9 (*((volatile unsigned int*)(0x43812C24UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ10 (*((volatile unsigned int*)(0x43812C28UL))) +#define bM4_USBFS_DIEPCTL3_USBAEP (*((volatile unsigned int*)(0x43812C3CUL))) +#define bM4_USBFS_DIEPCTL3_EONUM_DPID (*((volatile unsigned int*)(0x43812C40UL))) +#define bM4_USBFS_DIEPCTL3_NAKSTS (*((volatile unsigned int*)(0x43812C44UL))) +#define bM4_USBFS_DIEPCTL3_EPTYP0 (*((volatile unsigned int*)(0x43812C48UL))) +#define bM4_USBFS_DIEPCTL3_EPTYP1 (*((volatile unsigned int*)(0x43812C4CUL))) +#define bM4_USBFS_DIEPCTL3_STALL (*((volatile unsigned int*)(0x43812C54UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM0 (*((volatile unsigned int*)(0x43812C58UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM1 (*((volatile unsigned int*)(0x43812C5CUL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM2 (*((volatile unsigned int*)(0x43812C60UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM3 (*((volatile unsigned int*)(0x43812C64UL))) +#define bM4_USBFS_DIEPCTL3_CNAK (*((volatile unsigned int*)(0x43812C68UL))) +#define bM4_USBFS_DIEPCTL3_SNAK (*((volatile unsigned int*)(0x43812C6CUL))) +#define bM4_USBFS_DIEPCTL3_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812C70UL))) +#define bM4_USBFS_DIEPCTL3_SODDFRM (*((volatile unsigned int*)(0x43812C74UL))) +#define bM4_USBFS_DIEPCTL3_EPDIS (*((volatile unsigned int*)(0x43812C78UL))) +#define bM4_USBFS_DIEPCTL3_EPENA (*((volatile unsigned int*)(0x43812C7CUL))) +#define bM4_USBFS_DIEPINT3_XFRC (*((volatile unsigned int*)(0x43812D00UL))) +#define bM4_USBFS_DIEPINT3_EPDISD (*((volatile unsigned int*)(0x43812D04UL))) +#define bM4_USBFS_DIEPINT3_TOC (*((volatile unsigned int*)(0x43812D0CUL))) +#define bM4_USBFS_DIEPINT3_TTXFE (*((volatile unsigned int*)(0x43812D10UL))) +#define bM4_USBFS_DIEPINT3_INEPNE (*((volatile unsigned int*)(0x43812D18UL))) +#define bM4_USBFS_DIEPINT3_TXFE (*((volatile unsigned int*)(0x43812D1CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x43812E00UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x43812E04UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x43812E08UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x43812E0CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x43812E10UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x43812E14UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x43812E18UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x43812E1CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x43812E20UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x43812E24UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x43812E28UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x43812E2CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x43812E30UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x43812E34UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x43812E38UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x43812E3CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x43812E40UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x43812E44UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x43812E48UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x43812E4CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x43812E50UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x43812E54UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x43812E58UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x43812E5CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x43812E60UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x43812E64UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x43812E68UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x43812E6CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x43812E70UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV0 (*((volatile unsigned int*)(0x43812F00UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV1 (*((volatile unsigned int*)(0x43812F04UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV2 (*((volatile unsigned int*)(0x43812F08UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV3 (*((volatile unsigned int*)(0x43812F0CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV4 (*((volatile unsigned int*)(0x43812F10UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV5 (*((volatile unsigned int*)(0x43812F14UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV6 (*((volatile unsigned int*)(0x43812F18UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV7 (*((volatile unsigned int*)(0x43812F1CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV8 (*((volatile unsigned int*)(0x43812F20UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV9 (*((volatile unsigned int*)(0x43812F24UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV10 (*((volatile unsigned int*)(0x43812F28UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV11 (*((volatile unsigned int*)(0x43812F2CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV12 (*((volatile unsigned int*)(0x43812F30UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV13 (*((volatile unsigned int*)(0x43812F34UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV14 (*((volatile unsigned int*)(0x43812F38UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV15 (*((volatile unsigned int*)(0x43812F3CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ0 (*((volatile unsigned int*)(0x43813000UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ1 (*((volatile unsigned int*)(0x43813004UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ2 (*((volatile unsigned int*)(0x43813008UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ3 (*((volatile unsigned int*)(0x4381300CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ4 (*((volatile unsigned int*)(0x43813010UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ5 (*((volatile unsigned int*)(0x43813014UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ6 (*((volatile unsigned int*)(0x43813018UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ7 (*((volatile unsigned int*)(0x4381301CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ8 (*((volatile unsigned int*)(0x43813020UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ9 (*((volatile unsigned int*)(0x43813024UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ10 (*((volatile unsigned int*)(0x43813028UL))) +#define bM4_USBFS_DIEPCTL4_USBAEP (*((volatile unsigned int*)(0x4381303CUL))) +#define bM4_USBFS_DIEPCTL4_EONUM_DPID (*((volatile unsigned int*)(0x43813040UL))) +#define bM4_USBFS_DIEPCTL4_NAKSTS (*((volatile unsigned int*)(0x43813044UL))) +#define bM4_USBFS_DIEPCTL4_EPTYP0 (*((volatile unsigned int*)(0x43813048UL))) +#define bM4_USBFS_DIEPCTL4_EPTYP1 (*((volatile unsigned int*)(0x4381304CUL))) +#define bM4_USBFS_DIEPCTL4_STALL (*((volatile unsigned int*)(0x43813054UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM0 (*((volatile unsigned int*)(0x43813058UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM1 (*((volatile unsigned int*)(0x4381305CUL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM2 (*((volatile unsigned int*)(0x43813060UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM3 (*((volatile unsigned int*)(0x43813064UL))) +#define bM4_USBFS_DIEPCTL4_CNAK (*((volatile unsigned int*)(0x43813068UL))) +#define bM4_USBFS_DIEPCTL4_SNAK (*((volatile unsigned int*)(0x4381306CUL))) +#define bM4_USBFS_DIEPCTL4_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43813070UL))) +#define bM4_USBFS_DIEPCTL4_SODDFRM (*((volatile unsigned int*)(0x43813074UL))) +#define bM4_USBFS_DIEPCTL4_EPDIS (*((volatile unsigned int*)(0x43813078UL))) +#define bM4_USBFS_DIEPCTL4_EPENA (*((volatile unsigned int*)(0x4381307CUL))) +#define bM4_USBFS_DIEPINT4_XFRC (*((volatile unsigned int*)(0x43813100UL))) +#define bM4_USBFS_DIEPINT4_EPDISD (*((volatile unsigned int*)(0x43813104UL))) +#define bM4_USBFS_DIEPINT4_TOC (*((volatile unsigned int*)(0x4381310CUL))) +#define bM4_USBFS_DIEPINT4_TTXFE (*((volatile unsigned int*)(0x43813110UL))) +#define bM4_USBFS_DIEPINT4_INEPNE (*((volatile unsigned int*)(0x43813118UL))) +#define bM4_USBFS_DIEPINT4_TXFE (*((volatile unsigned int*)(0x4381311CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x43813200UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x43813204UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x43813208UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4381320CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x43813210UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x43813214UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x43813218UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4381321CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x43813220UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x43813224UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x43813228UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4381322CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x43813230UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x43813234UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x43813238UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4381323CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x43813240UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x43813244UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x43813248UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4381324CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x43813250UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x43813254UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x43813258UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4381325CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x43813260UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x43813264UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x43813268UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4381326CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x43813270UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV0 (*((volatile unsigned int*)(0x43813300UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV1 (*((volatile unsigned int*)(0x43813304UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV2 (*((volatile unsigned int*)(0x43813308UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV3 (*((volatile unsigned int*)(0x4381330CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV4 (*((volatile unsigned int*)(0x43813310UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV5 (*((volatile unsigned int*)(0x43813314UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV6 (*((volatile unsigned int*)(0x43813318UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV7 (*((volatile unsigned int*)(0x4381331CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV8 (*((volatile unsigned int*)(0x43813320UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV9 (*((volatile unsigned int*)(0x43813324UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV10 (*((volatile unsigned int*)(0x43813328UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV11 (*((volatile unsigned int*)(0x4381332CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV12 (*((volatile unsigned int*)(0x43813330UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV13 (*((volatile unsigned int*)(0x43813334UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV14 (*((volatile unsigned int*)(0x43813338UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV15 (*((volatile unsigned int*)(0x4381333CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ0 (*((volatile unsigned int*)(0x43813400UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ1 (*((volatile unsigned int*)(0x43813404UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ2 (*((volatile unsigned int*)(0x43813408UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ3 (*((volatile unsigned int*)(0x4381340CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ4 (*((volatile unsigned int*)(0x43813410UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ5 (*((volatile unsigned int*)(0x43813414UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ6 (*((volatile unsigned int*)(0x43813418UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ7 (*((volatile unsigned int*)(0x4381341CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ8 (*((volatile unsigned int*)(0x43813420UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ9 (*((volatile unsigned int*)(0x43813424UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ10 (*((volatile unsigned int*)(0x43813428UL))) +#define bM4_USBFS_DIEPCTL5_USBAEP (*((volatile unsigned int*)(0x4381343CUL))) +#define bM4_USBFS_DIEPCTL5_EONUM_DPID (*((volatile unsigned int*)(0x43813440UL))) +#define bM4_USBFS_DIEPCTL5_NAKSTS (*((volatile unsigned int*)(0x43813444UL))) +#define bM4_USBFS_DIEPCTL5_EPTYP0 (*((volatile unsigned int*)(0x43813448UL))) +#define bM4_USBFS_DIEPCTL5_EPTYP1 (*((volatile unsigned int*)(0x4381344CUL))) +#define bM4_USBFS_DIEPCTL5_STALL (*((volatile unsigned int*)(0x43813454UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM0 (*((volatile unsigned int*)(0x43813458UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM1 (*((volatile unsigned int*)(0x4381345CUL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM2 (*((volatile unsigned int*)(0x43813460UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM3 (*((volatile unsigned int*)(0x43813464UL))) +#define bM4_USBFS_DIEPCTL5_CNAK (*((volatile unsigned int*)(0x43813468UL))) +#define bM4_USBFS_DIEPCTL5_SNAK (*((volatile unsigned int*)(0x4381346CUL))) +#define bM4_USBFS_DIEPCTL5_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43813470UL))) +#define bM4_USBFS_DIEPCTL5_SODDFRM (*((volatile unsigned int*)(0x43813474UL))) +#define bM4_USBFS_DIEPCTL5_EPDIS (*((volatile unsigned int*)(0x43813478UL))) +#define bM4_USBFS_DIEPCTL5_EPENA (*((volatile unsigned int*)(0x4381347CUL))) +#define bM4_USBFS_DIEPINT5_XFRC (*((volatile unsigned int*)(0x43813500UL))) +#define bM4_USBFS_DIEPINT5_EPDISD (*((volatile unsigned int*)(0x43813504UL))) +#define bM4_USBFS_DIEPINT5_TOC (*((volatile unsigned int*)(0x4381350CUL))) +#define bM4_USBFS_DIEPINT5_TTXFE (*((volatile unsigned int*)(0x43813510UL))) +#define bM4_USBFS_DIEPINT5_INEPNE (*((volatile unsigned int*)(0x43813518UL))) +#define bM4_USBFS_DIEPINT5_TXFE (*((volatile unsigned int*)(0x4381351CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x43813600UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x43813604UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x43813608UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4381360CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x43813610UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x43813614UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x43813618UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4381361CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x43813620UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x43813624UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x43813628UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4381362CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x43813630UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x43813634UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x43813638UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4381363CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x43813640UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x43813644UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x43813648UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4381364CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x43813650UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x43813654UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x43813658UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4381365CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x43813660UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x43813664UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x43813668UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4381366CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x43813670UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV0 (*((volatile unsigned int*)(0x43813700UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV1 (*((volatile unsigned int*)(0x43813704UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV2 (*((volatile unsigned int*)(0x43813708UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV3 (*((volatile unsigned int*)(0x4381370CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV4 (*((volatile unsigned int*)(0x43813710UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV5 (*((volatile unsigned int*)(0x43813714UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV6 (*((volatile unsigned int*)(0x43813718UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV7 (*((volatile unsigned int*)(0x4381371CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV8 (*((volatile unsigned int*)(0x43813720UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV9 (*((volatile unsigned int*)(0x43813724UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV10 (*((volatile unsigned int*)(0x43813728UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV11 (*((volatile unsigned int*)(0x4381372CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV12 (*((volatile unsigned int*)(0x43813730UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV13 (*((volatile unsigned int*)(0x43813734UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV14 (*((volatile unsigned int*)(0x43813738UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV15 (*((volatile unsigned int*)(0x4381373CUL))) +#define bM4_USBFS_DOEPCTL0_MPSIZ0 (*((volatile unsigned int*)(0x43816000UL))) +#define bM4_USBFS_DOEPCTL0_MPSIZ1 (*((volatile unsigned int*)(0x43816004UL))) +#define bM4_USBFS_DOEPCTL0_USBAEP (*((volatile unsigned int*)(0x4381603CUL))) +#define bM4_USBFS_DOEPCTL0_NAKSTS (*((volatile unsigned int*)(0x43816044UL))) +#define bM4_USBFS_DOEPCTL0_EPTYP0 (*((volatile unsigned int*)(0x43816048UL))) +#define bM4_USBFS_DOEPCTL0_EPTYP1 (*((volatile unsigned int*)(0x4381604CUL))) +#define bM4_USBFS_DOEPCTL0_SNPM (*((volatile unsigned int*)(0x43816050UL))) +#define bM4_USBFS_DOEPCTL0_STALL (*((volatile unsigned int*)(0x43816054UL))) +#define bM4_USBFS_DOEPCTL0_CNAK (*((volatile unsigned int*)(0x43816068UL))) +#define bM4_USBFS_DOEPCTL0_SNAK (*((volatile unsigned int*)(0x4381606CUL))) +#define bM4_USBFS_DOEPCTL0_EPDIS (*((volatile unsigned int*)(0x43816078UL))) +#define bM4_USBFS_DOEPCTL0_EPENA (*((volatile unsigned int*)(0x4381607CUL))) +#define bM4_USBFS_DOEPINT0_XFRC (*((volatile unsigned int*)(0x43816100UL))) +#define bM4_USBFS_DOEPINT0_EPDISD (*((volatile unsigned int*)(0x43816104UL))) +#define bM4_USBFS_DOEPINT0_STUP (*((volatile unsigned int*)(0x4381610CUL))) +#define bM4_USBFS_DOEPINT0_OTEPDIS (*((volatile unsigned int*)(0x43816110UL))) +#define bM4_USBFS_DOEPINT0_B2BSTUP (*((volatile unsigned int*)(0x43816118UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x43816200UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x43816204UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x43816208UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4381620CUL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x43816210UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x43816214UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x43816218UL))) +#define bM4_USBFS_DOEPTSIZ0_PKTCNT (*((volatile unsigned int*)(0x4381624CUL))) +#define bM4_USBFS_DOEPTSIZ0_STUPCNT0 (*((volatile unsigned int*)(0x43816274UL))) +#define bM4_USBFS_DOEPTSIZ0_STUPCNT1 (*((volatile unsigned int*)(0x43816278UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ0 (*((volatile unsigned int*)(0x43816400UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ1 (*((volatile unsigned int*)(0x43816404UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ2 (*((volatile unsigned int*)(0x43816408UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ3 (*((volatile unsigned int*)(0x4381640CUL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ4 (*((volatile unsigned int*)(0x43816410UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ5 (*((volatile unsigned int*)(0x43816414UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ6 (*((volatile unsigned int*)(0x43816418UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ7 (*((volatile unsigned int*)(0x4381641CUL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ8 (*((volatile unsigned int*)(0x43816420UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ9 (*((volatile unsigned int*)(0x43816424UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ10 (*((volatile unsigned int*)(0x43816428UL))) +#define bM4_USBFS_DOEPCTL1_USBAEP (*((volatile unsigned int*)(0x4381643CUL))) +#define bM4_USBFS_DOEPCTL1_DPID (*((volatile unsigned int*)(0x43816440UL))) +#define bM4_USBFS_DOEPCTL1_NAKSTS (*((volatile unsigned int*)(0x43816444UL))) +#define bM4_USBFS_DOEPCTL1_EPTYP0 (*((volatile unsigned int*)(0x43816448UL))) +#define bM4_USBFS_DOEPCTL1_EPTYP1 (*((volatile unsigned int*)(0x4381644CUL))) +#define bM4_USBFS_DOEPCTL1_SNPM (*((volatile unsigned int*)(0x43816450UL))) +#define bM4_USBFS_DOEPCTL1_STALL (*((volatile unsigned int*)(0x43816454UL))) +#define bM4_USBFS_DOEPCTL1_CNAK (*((volatile unsigned int*)(0x43816468UL))) +#define bM4_USBFS_DOEPCTL1_SNAK (*((volatile unsigned int*)(0x4381646CUL))) +#define bM4_USBFS_DOEPCTL1_SD0PID (*((volatile unsigned int*)(0x43816470UL))) +#define bM4_USBFS_DOEPCTL1_SD1PID (*((volatile unsigned int*)(0x43816474UL))) +#define bM4_USBFS_DOEPCTL1_EPDIS (*((volatile unsigned int*)(0x43816478UL))) +#define bM4_USBFS_DOEPCTL1_EPENA (*((volatile unsigned int*)(0x4381647CUL))) +#define bM4_USBFS_DOEPINT1_XFRC (*((volatile unsigned int*)(0x43816500UL))) +#define bM4_USBFS_DOEPINT1_EPDISD (*((volatile unsigned int*)(0x43816504UL))) +#define bM4_USBFS_DOEPINT1_STUP (*((volatile unsigned int*)(0x4381650CUL))) +#define bM4_USBFS_DOEPINT1_OTEPDIS (*((volatile unsigned int*)(0x43816510UL))) +#define bM4_USBFS_DOEPINT1_B2BSTUP (*((volatile unsigned int*)(0x43816518UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x43816600UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x43816604UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x43816608UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4381660CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x43816610UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x43816614UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x43816618UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4381661CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x43816620UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x43816624UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x43816628UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4381662CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x43816630UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x43816634UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x43816638UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4381663CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x43816640UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x43816644UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x43816648UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4381664CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x43816650UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x43816654UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x43816658UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4381665CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x43816660UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x43816664UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x43816668UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4381666CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x43816670UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ0 (*((volatile unsigned int*)(0x43816800UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ1 (*((volatile unsigned int*)(0x43816804UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ2 (*((volatile unsigned int*)(0x43816808UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ3 (*((volatile unsigned int*)(0x4381680CUL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ4 (*((volatile unsigned int*)(0x43816810UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ5 (*((volatile unsigned int*)(0x43816814UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ6 (*((volatile unsigned int*)(0x43816818UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ7 (*((volatile unsigned int*)(0x4381681CUL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ8 (*((volatile unsigned int*)(0x43816820UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ9 (*((volatile unsigned int*)(0x43816824UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ10 (*((volatile unsigned int*)(0x43816828UL))) +#define bM4_USBFS_DOEPCTL2_USBAEP (*((volatile unsigned int*)(0x4381683CUL))) +#define bM4_USBFS_DOEPCTL2_DPID (*((volatile unsigned int*)(0x43816840UL))) +#define bM4_USBFS_DOEPCTL2_NAKSTS (*((volatile unsigned int*)(0x43816844UL))) +#define bM4_USBFS_DOEPCTL2_EPTYP0 (*((volatile unsigned int*)(0x43816848UL))) +#define bM4_USBFS_DOEPCTL2_EPTYP1 (*((volatile unsigned int*)(0x4381684CUL))) +#define bM4_USBFS_DOEPCTL2_SNPM (*((volatile unsigned int*)(0x43816850UL))) +#define bM4_USBFS_DOEPCTL2_STALL (*((volatile unsigned int*)(0x43816854UL))) +#define bM4_USBFS_DOEPCTL2_CNAK (*((volatile unsigned int*)(0x43816868UL))) +#define bM4_USBFS_DOEPCTL2_SNAK (*((volatile unsigned int*)(0x4381686CUL))) +#define bM4_USBFS_DOEPCTL2_SD0PID (*((volatile unsigned int*)(0x43816870UL))) +#define bM4_USBFS_DOEPCTL2_SD1PID (*((volatile unsigned int*)(0x43816874UL))) +#define bM4_USBFS_DOEPCTL2_EPDIS (*((volatile unsigned int*)(0x43816878UL))) +#define bM4_USBFS_DOEPCTL2_EPENA (*((volatile unsigned int*)(0x4381687CUL))) +#define bM4_USBFS_DOEPINT2_XFRC (*((volatile unsigned int*)(0x43816900UL))) +#define bM4_USBFS_DOEPINT2_EPDISD (*((volatile unsigned int*)(0x43816904UL))) +#define bM4_USBFS_DOEPINT2_STUP (*((volatile unsigned int*)(0x4381690CUL))) +#define bM4_USBFS_DOEPINT2_OTEPDIS (*((volatile unsigned int*)(0x43816910UL))) +#define bM4_USBFS_DOEPINT2_B2BSTUP (*((volatile unsigned int*)(0x43816918UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x43816A00UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x43816A04UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x43816A08UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x43816A0CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x43816A10UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x43816A14UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x43816A18UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x43816A1CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x43816A20UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x43816A24UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x43816A28UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x43816A2CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x43816A30UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x43816A34UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x43816A38UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x43816A3CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x43816A40UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x43816A44UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x43816A48UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x43816A4CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x43816A50UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x43816A54UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x43816A58UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x43816A5CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x43816A60UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x43816A64UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x43816A68UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x43816A6CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x43816A70UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ0 (*((volatile unsigned int*)(0x43816C00UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ1 (*((volatile unsigned int*)(0x43816C04UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ2 (*((volatile unsigned int*)(0x43816C08UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ3 (*((volatile unsigned int*)(0x43816C0CUL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ4 (*((volatile unsigned int*)(0x43816C10UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ5 (*((volatile unsigned int*)(0x43816C14UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ6 (*((volatile unsigned int*)(0x43816C18UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ7 (*((volatile unsigned int*)(0x43816C1CUL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ8 (*((volatile unsigned int*)(0x43816C20UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ9 (*((volatile unsigned int*)(0x43816C24UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ10 (*((volatile unsigned int*)(0x43816C28UL))) +#define bM4_USBFS_DOEPCTL3_USBAEP (*((volatile unsigned int*)(0x43816C3CUL))) +#define bM4_USBFS_DOEPCTL3_DPID (*((volatile unsigned int*)(0x43816C40UL))) +#define bM4_USBFS_DOEPCTL3_NAKSTS (*((volatile unsigned int*)(0x43816C44UL))) +#define bM4_USBFS_DOEPCTL3_EPTYP0 (*((volatile unsigned int*)(0x43816C48UL))) +#define bM4_USBFS_DOEPCTL3_EPTYP1 (*((volatile unsigned int*)(0x43816C4CUL))) +#define bM4_USBFS_DOEPCTL3_SNPM (*((volatile unsigned int*)(0x43816C50UL))) +#define bM4_USBFS_DOEPCTL3_STALL (*((volatile unsigned int*)(0x43816C54UL))) +#define bM4_USBFS_DOEPCTL3_CNAK (*((volatile unsigned int*)(0x43816C68UL))) +#define bM4_USBFS_DOEPCTL3_SNAK (*((volatile unsigned int*)(0x43816C6CUL))) +#define bM4_USBFS_DOEPCTL3_SD0PID (*((volatile unsigned int*)(0x43816C70UL))) +#define bM4_USBFS_DOEPCTL3_SD1PID (*((volatile unsigned int*)(0x43816C74UL))) +#define bM4_USBFS_DOEPCTL3_EPDIS (*((volatile unsigned int*)(0x43816C78UL))) +#define bM4_USBFS_DOEPCTL3_EPENA (*((volatile unsigned int*)(0x43816C7CUL))) +#define bM4_USBFS_DOEPINT3_XFRC (*((volatile unsigned int*)(0x43816D00UL))) +#define bM4_USBFS_DOEPINT3_EPDISD (*((volatile unsigned int*)(0x43816D04UL))) +#define bM4_USBFS_DOEPINT3_STUP (*((volatile unsigned int*)(0x43816D0CUL))) +#define bM4_USBFS_DOEPINT3_OTEPDIS (*((volatile unsigned int*)(0x43816D10UL))) +#define bM4_USBFS_DOEPINT3_B2BSTUP (*((volatile unsigned int*)(0x43816D18UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x43816E00UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x43816E04UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x43816E08UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x43816E0CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x43816E10UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x43816E14UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x43816E18UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x43816E1CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x43816E20UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x43816E24UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x43816E28UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x43816E2CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x43816E30UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x43816E34UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x43816E38UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x43816E3CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x43816E40UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x43816E44UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x43816E48UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x43816E4CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x43816E50UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x43816E54UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x43816E58UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x43816E5CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x43816E60UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x43816E64UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x43816E68UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x43816E6CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x43816E70UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ0 (*((volatile unsigned int*)(0x43817000UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ1 (*((volatile unsigned int*)(0x43817004UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ2 (*((volatile unsigned int*)(0x43817008UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ3 (*((volatile unsigned int*)(0x4381700CUL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ4 (*((volatile unsigned int*)(0x43817010UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ5 (*((volatile unsigned int*)(0x43817014UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ6 (*((volatile unsigned int*)(0x43817018UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ7 (*((volatile unsigned int*)(0x4381701CUL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ8 (*((volatile unsigned int*)(0x43817020UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ9 (*((volatile unsigned int*)(0x43817024UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ10 (*((volatile unsigned int*)(0x43817028UL))) +#define bM4_USBFS_DOEPCTL4_USBAEP (*((volatile unsigned int*)(0x4381703CUL))) +#define bM4_USBFS_DOEPCTL4_DPID (*((volatile unsigned int*)(0x43817040UL))) +#define bM4_USBFS_DOEPCTL4_NAKSTS (*((volatile unsigned int*)(0x43817044UL))) +#define bM4_USBFS_DOEPCTL4_EPTYP0 (*((volatile unsigned int*)(0x43817048UL))) +#define bM4_USBFS_DOEPCTL4_EPTYP1 (*((volatile unsigned int*)(0x4381704CUL))) +#define bM4_USBFS_DOEPCTL4_SNPM (*((volatile unsigned int*)(0x43817050UL))) +#define bM4_USBFS_DOEPCTL4_STALL (*((volatile unsigned int*)(0x43817054UL))) +#define bM4_USBFS_DOEPCTL4_CNAK (*((volatile unsigned int*)(0x43817068UL))) +#define bM4_USBFS_DOEPCTL4_SNAK (*((volatile unsigned int*)(0x4381706CUL))) +#define bM4_USBFS_DOEPCTL4_SD0PID (*((volatile unsigned int*)(0x43817070UL))) +#define bM4_USBFS_DOEPCTL4_SD1PID (*((volatile unsigned int*)(0x43817074UL))) +#define bM4_USBFS_DOEPCTL4_EPDIS (*((volatile unsigned int*)(0x43817078UL))) +#define bM4_USBFS_DOEPCTL4_EPENA (*((volatile unsigned int*)(0x4381707CUL))) +#define bM4_USBFS_DOEPINT4_XFRC (*((volatile unsigned int*)(0x43817100UL))) +#define bM4_USBFS_DOEPINT4_EPDISD (*((volatile unsigned int*)(0x43817104UL))) +#define bM4_USBFS_DOEPINT4_STUP (*((volatile unsigned int*)(0x4381710CUL))) +#define bM4_USBFS_DOEPINT4_OTEPDIS (*((volatile unsigned int*)(0x43817110UL))) +#define bM4_USBFS_DOEPINT4_B2BSTUP (*((volatile unsigned int*)(0x43817118UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x43817200UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x43817204UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x43817208UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4381720CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x43817210UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x43817214UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x43817218UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4381721CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x43817220UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x43817224UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x43817228UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4381722CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x43817230UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x43817234UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x43817238UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4381723CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x43817240UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x43817244UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x43817248UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4381724CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x43817250UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x43817254UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x43817258UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4381725CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x43817260UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x43817264UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x43817268UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4381726CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x43817270UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ0 (*((volatile unsigned int*)(0x43817400UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ1 (*((volatile unsigned int*)(0x43817404UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ2 (*((volatile unsigned int*)(0x43817408UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ3 (*((volatile unsigned int*)(0x4381740CUL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ4 (*((volatile unsigned int*)(0x43817410UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ5 (*((volatile unsigned int*)(0x43817414UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ6 (*((volatile unsigned int*)(0x43817418UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ7 (*((volatile unsigned int*)(0x4381741CUL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ8 (*((volatile unsigned int*)(0x43817420UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ9 (*((volatile unsigned int*)(0x43817424UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ10 (*((volatile unsigned int*)(0x43817428UL))) +#define bM4_USBFS_DOEPCTL5_USBAEP (*((volatile unsigned int*)(0x4381743CUL))) +#define bM4_USBFS_DOEPCTL5_DPID (*((volatile unsigned int*)(0x43817440UL))) +#define bM4_USBFS_DOEPCTL5_NAKSTS (*((volatile unsigned int*)(0x43817444UL))) +#define bM4_USBFS_DOEPCTL5_EPTYP0 (*((volatile unsigned int*)(0x43817448UL))) +#define bM4_USBFS_DOEPCTL5_EPTYP1 (*((volatile unsigned int*)(0x4381744CUL))) +#define bM4_USBFS_DOEPCTL5_SNPM (*((volatile unsigned int*)(0x43817450UL))) +#define bM4_USBFS_DOEPCTL5_STALL (*((volatile unsigned int*)(0x43817454UL))) +#define bM4_USBFS_DOEPCTL5_CNAK (*((volatile unsigned int*)(0x43817468UL))) +#define bM4_USBFS_DOEPCTL5_SNAK (*((volatile unsigned int*)(0x4381746CUL))) +#define bM4_USBFS_DOEPCTL5_SD0PID (*((volatile unsigned int*)(0x43817470UL))) +#define bM4_USBFS_DOEPCTL5_SD1PID (*((volatile unsigned int*)(0x43817474UL))) +#define bM4_USBFS_DOEPCTL5_EPDIS (*((volatile unsigned int*)(0x43817478UL))) +#define bM4_USBFS_DOEPCTL5_EPENA (*((volatile unsigned int*)(0x4381747CUL))) +#define bM4_USBFS_DOEPINT5_XFRC (*((volatile unsigned int*)(0x43817500UL))) +#define bM4_USBFS_DOEPINT5_EPDISD (*((volatile unsigned int*)(0x43817504UL))) +#define bM4_USBFS_DOEPINT5_STUP (*((volatile unsigned int*)(0x4381750CUL))) +#define bM4_USBFS_DOEPINT5_OTEPDIS (*((volatile unsigned int*)(0x43817510UL))) +#define bM4_USBFS_DOEPINT5_B2BSTUP (*((volatile unsigned int*)(0x43817518UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x43817600UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x43817604UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x43817608UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4381760CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x43817610UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x43817614UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x43817618UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4381761CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x43817620UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x43817624UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x43817628UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4381762CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x43817630UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x43817634UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x43817638UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4381763CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x43817640UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x43817644UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x43817648UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4381764CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x43817650UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x43817654UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x43817658UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4381765CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x43817660UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x43817664UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x43817668UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4381766CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x43817670UL))) +#define bM4_USBFS_PCGCCTL_STPPCLK (*((volatile unsigned int*)(0x4381C000UL))) +#define bM4_USBFS_PCGCCTL_GATEHCLK (*((volatile unsigned int*)(0x4381C004UL))) +#define bM4_WDT_CR_PERI0 (*((volatile unsigned int*)(0x42920000UL))) +#define bM4_WDT_CR_PERI1 (*((volatile unsigned int*)(0x42920004UL))) +#define bM4_WDT_CR_CKS0 (*((volatile unsigned int*)(0x42920010UL))) +#define bM4_WDT_CR_CKS1 (*((volatile unsigned int*)(0x42920014UL))) +#define bM4_WDT_CR_CKS2 (*((volatile unsigned int*)(0x42920018UL))) +#define bM4_WDT_CR_CKS3 (*((volatile unsigned int*)(0x4292001CUL))) +#define bM4_WDT_CR_WDPT0 (*((volatile unsigned int*)(0x42920020UL))) +#define bM4_WDT_CR_WDPT1 (*((volatile unsigned int*)(0x42920024UL))) +#define bM4_WDT_CR_WDPT2 (*((volatile unsigned int*)(0x42920028UL))) +#define bM4_WDT_CR_WDPT3 (*((volatile unsigned int*)(0x4292002CUL))) +#define bM4_WDT_CR_SLPOFF (*((volatile unsigned int*)(0x42920040UL))) +#define bM4_WDT_CR_ITS (*((volatile unsigned int*)(0x4292007CUL))) +#define bM4_WDT_SR_CNT0 (*((volatile unsigned int*)(0x42920080UL))) +#define bM4_WDT_SR_CNT1 (*((volatile unsigned int*)(0x42920084UL))) +#define bM4_WDT_SR_CNT2 (*((volatile unsigned int*)(0x42920088UL))) +#define bM4_WDT_SR_CNT3 (*((volatile unsigned int*)(0x4292008CUL))) +#define bM4_WDT_SR_CNT4 (*((volatile unsigned int*)(0x42920090UL))) +#define bM4_WDT_SR_CNT5 (*((volatile unsigned int*)(0x42920094UL))) +#define bM4_WDT_SR_CNT6 (*((volatile unsigned int*)(0x42920098UL))) +#define bM4_WDT_SR_CNT7 (*((volatile unsigned int*)(0x4292009CUL))) +#define bM4_WDT_SR_CNT8 (*((volatile unsigned int*)(0x429200A0UL))) +#define bM4_WDT_SR_CNT9 (*((volatile unsigned int*)(0x429200A4UL))) +#define bM4_WDT_SR_CNT10 (*((volatile unsigned int*)(0x429200A8UL))) +#define bM4_WDT_SR_CNT11 (*((volatile unsigned int*)(0x429200ACUL))) +#define bM4_WDT_SR_CNT12 (*((volatile unsigned int*)(0x429200B0UL))) +#define bM4_WDT_SR_CNT13 (*((volatile unsigned int*)(0x429200B4UL))) +#define bM4_WDT_SR_CNT14 (*((volatile unsigned int*)(0x429200B8UL))) +#define bM4_WDT_SR_CNT15 (*((volatile unsigned int*)(0x429200BCUL))) +#define bM4_WDT_SR_UDF (*((volatile unsigned int*)(0x429200C0UL))) +#define bM4_WDT_SR_REF (*((volatile unsigned int*)(0x429200C4UL))) +#define bM4_WDT_RR_RF0 (*((volatile unsigned int*)(0x42920100UL))) +#define bM4_WDT_RR_RF1 (*((volatile unsigned int*)(0x42920104UL))) +#define bM4_WDT_RR_RF2 (*((volatile unsigned int*)(0x42920108UL))) +#define bM4_WDT_RR_RF3 (*((volatile unsigned int*)(0x4292010CUL))) +#define bM4_WDT_RR_RF4 (*((volatile unsigned int*)(0x42920110UL))) +#define bM4_WDT_RR_RF5 (*((volatile unsigned int*)(0x42920114UL))) +#define bM4_WDT_RR_RF6 (*((volatile unsigned int*)(0x42920118UL))) +#define bM4_WDT_RR_RF7 (*((volatile unsigned int*)(0x4292011CUL))) +#define bM4_WDT_RR_RF8 (*((volatile unsigned int*)(0x42920120UL))) +#define bM4_WDT_RR_RF9 (*((volatile unsigned int*)(0x42920124UL))) +#define bM4_WDT_RR_RF10 (*((volatile unsigned int*)(0x42920128UL))) +#define bM4_WDT_RR_RF11 (*((volatile unsigned int*)(0x4292012CUL))) +#define bM4_WDT_RR_RF12 (*((volatile unsigned int*)(0x42920130UL))) +#define bM4_WDT_RR_RF13 (*((volatile unsigned int*)(0x42920134UL))) +#define bM4_WDT_RR_RF14 (*((volatile unsigned int*)(0x42920138UL))) +#define bM4_WDT_RR_RF15 (*((volatile unsigned int*)(0x4292013CUL))) +#define bM4_WKTM_CR_WKTMCMP0 (*((volatile unsigned int*)(0x42988000UL))) +#define bM4_WKTM_CR_WKTMCMP1 (*((volatile unsigned int*)(0x42988004UL))) +#define bM4_WKTM_CR_WKTMCMP2 (*((volatile unsigned int*)(0x42988008UL))) +#define bM4_WKTM_CR_WKTMCMP3 (*((volatile unsigned int*)(0x4298800CUL))) +#define bM4_WKTM_CR_WKTMCMP4 (*((volatile unsigned int*)(0x42988010UL))) +#define bM4_WKTM_CR_WKTMCMP5 (*((volatile unsigned int*)(0x42988014UL))) +#define bM4_WKTM_CR_WKTMCMP6 (*((volatile unsigned int*)(0x42988018UL))) +#define bM4_WKTM_CR_WKTMCMP7 (*((volatile unsigned int*)(0x4298801CUL))) +#define bM4_WKTM_CR_WKTMCMP8 (*((volatile unsigned int*)(0x42988020UL))) +#define bM4_WKTM_CR_WKTMCMP9 (*((volatile unsigned int*)(0x42988024UL))) +#define bM4_WKTM_CR_WKTMCMP10 (*((volatile unsigned int*)(0x42988028UL))) +#define bM4_WKTM_CR_WKTMCMP11 (*((volatile unsigned int*)(0x4298802CUL))) +#define bM4_WKTM_CR_WKOVF (*((volatile unsigned int*)(0x42988030UL))) +#define bM4_WKTM_CR_WKCKS0 (*((volatile unsigned int*)(0x42988034UL))) +#define bM4_WKTM_CR_WKCKS1 (*((volatile unsigned int*)(0x42988038UL))) +#define bM4_WKTM_CR_WKTCE (*((volatile unsigned int*)(0x4298803CUL))) + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_H__ */ + diff --git a/mcu/common/system_hc32f460.c b/mcu/common/system_hc32f460.c new file mode 100644 index 0000000..4acff76 --- /dev/null +++ b/mcu/common/system_hc32f460.c @@ -0,0 +1,145 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file system_hc32f460.c + ** + ** A detailed description is available at + ** @link Hc32f460SystemGroup Hc32f460System description @endlink + ** + ** - 2018-10-15 CDT First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "bsp.h" + +/** + ******************************************************************************* + ** \addtogroup Hc32f460SystemGroup + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ + +//@{ + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t HRC_VALUE = HRC_16MHz_VALUE; +uint32_t SystemCoreClock = MRC_VALUE; + +//#ifdef USE_BOOTLOADER +//#define VECT_TAB_OFFSET (FLASH_BASE + APP_ADDRESS) +//#else +//#define VECT_TAB_OFFSET (0) +//#endif + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param None + ** \return None + **************************** + + + **************************************************/ +void SystemInit(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */ +#endif + + SystemCoreClockUpdate(); + +//#ifdef USE_BOOTLOADER +// SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation */ +//#endif + + + extern unsigned char Image$$ER_IROM1$$Base; + + uint32_t rom_base =0u; + + rom_base= (uint32_t)&Image$$ER_IROM1$$Base; + SCB->VTOR = rom_base; /* Vector Table Relocation */ + +} + +void SystemCoreClockUpdate(void) // Update SystemCoreClock variable +{ + uint8_t tmp = 0u; + uint32_t plln = 19u, pllp = 1u, pllm = 0u, pllsource = 0u; + + /* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */ + /* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */ + /* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */ + if (1UL == (HRC_FREQ_MON() & 1UL)) + { + HRC_VALUE = HRC_16MHz_VALUE; + } + else + { + HRC_VALUE = HRC_20MHz_VALUE; + } + + tmp = M4_SYSREG->CMU_CKSWR_f.CKSW; + switch (tmp) + { + case 0x00: /* use internal high speed RC */ + SystemCoreClock = HRC_VALUE; + break; + case 0x01: /* use internal middle speed RC */ + SystemCoreClock = MRC_VALUE; + break; + case 0x02: /* use internal low speed RC */ + SystemCoreClock = LRC_VALUE; + break; + case 0x03: /* use external high speed OSC */ + SystemCoreClock = XTAL_VALUE; + break; + case 0x04: /* use external low speed OSC */ + SystemCoreClock = XTAL32_VALUE; + break; + case 0x05: /* use MPLL */ + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + plln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + pllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + pllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + /* use exteranl high speed OSC as PLL source */ + if (0ul == pllsource) + { + SystemCoreClock = (XTAL_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul); + } + /* use interanl high RC as PLL source */ + else if (1ul == pllsource) + { + SystemCoreClock = (HRC_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul); + } + else + { + /* Reserved */ + } + break; + } +} + +//@} // UsartGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/common/system_hc32f460.h b/mcu/common/system_hc32f460.h new file mode 100644 index 0000000..506cf49 --- /dev/null +++ b/mcu/common/system_hc32f460.h @@ -0,0 +1,105 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file system_hc32f460.h + ** + ** A detailed description is available at + ** @link Hc32f460SystemGroup Hc32f460System description @endlink + ** + ** - 2018-10-15 CDT First version. + ** + ******************************************************************************/ +#ifndef __SYSTEM_HC32F460_H__ +#define __SYSTEM_HC32F460_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + ******************************************************************************* + ** \defgroup Hc32f460SystemGroup HC32F460 System Configure + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + +#define HRC_FREQ_MON() (*((volatile unsigned int*)(0x40010684UL))) + +#if !defined (HRC_16MHz_VALUE) + #define HRC_16MHz_VALUE ((uint32_t)16000000UL) /*!< Internal high speed RC freq.(16MHz) */ +#endif + +#if !defined (HRC_20MHz_VALUE) + #define HRC_20MHz_VALUE ((uint32_t)20000000UL) /*!< Internal high speed RC freq.(20MHz) */ +#endif + +#if !defined (MRC_VALUE) +#define MRC_VALUE ((uint32_t)8000000) /*!< Internal middle speed RC freq. */ +#endif + +#if !defined (LRC_VALUE) +#define LRC_VALUE ((uint32_t)32768) /*!< Internal low speed RC freq. */ +#endif + +#if !defined (XTAL_VALUE) +#define XTAL_VALUE ((uint32_t)16000000) /*!< External high speed OSC freq. */ +#endif + +#if !defined (XTAL32_VALUE) +#define XTAL32_VALUE ((uint32_t)32768) /*!< External low speed OSC freq. */ +#endif + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +extern uint32_t HRC_VALUE; // HRC Clock Frequency (Core Clock) +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit(void); // Initialize the system +extern void SystemCoreClockUpdate(void); // Update SystemCoreClock variable + +//@} // Hc32f460SystemGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32F460_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/version.txt b/version.txt new file mode 100644 index 0000000..3aad5d3 --- /dev/null +++ b/version.txt @@ -0,0 +1,267 @@ +version date comment +2.0.0 + Apr 16, 2021 1. Support new hardware: EV_F460_LQ100_V2; + 2. add USB lib and example. + +1.3.1 Apr 09, 2021 1. Add usb example usb_host_hid_msc. + +1.3.0 + Feb 04, 2021 1. Fixed a bug of API HASH_Start(). + 2. Bug Fixed for example clk_switch_sysclk.#PWC_HS2HP should be called before clock is ready. + 3. Add note for API(PWC_HP2LS etc) in pwc.c. + 4. Modified TBDs as 30us base 200Mhz in clk.c. + + Jan 25, 2021 1. Fix bug for usbd_hid_custom example(about windows 10). + + Jan 18, 2021 1. Modified function ADC_ChannleRemap(), from ADC_ChannleRemap() to ADC_ChannelRemap(). + 2. Fixed a bug of function ADC_PollingSa(). + +1.2.0 + Dec 16, 2020 1. Add API XXX_ComTriggerCmd() and modify XXX_SetTriggerSrc() (XXX=ADC/DCU/OTS/TimerA/Timer0/Timer6/EventPort/DMA). + + Dec 15, 2020 1. Fix bug for usbh_hid_core.c(The HID report data will not be decoded if the USBH_Process() not process in time). + 2. Add register AOS_COMTRG1/2 + + Dec 11, 2020 1. Modify define for USB_MAX_STR_DESC_SIZ. + 2. Fix bug for USB device USBD_GetDescriptor function. + + Dec 03, 2020 + 1. Fixed SysTick_Delay function overflow handling. + + Dec 02,2020 1. Modified func. CAN_IrqFlgClr() + 2. Add CLKInit() function (Config system clock as 200M) to example lpm_pwerdown_wakeup + + Nov 30,2020 1. Add lmp_lwp(lowest power) example to lpm. + 2. Modify PWC driver. + 3. Add example usbh_msc_mouse_kb and modify USB lib for PHY clock config. + + Nov 16,2020 1. Add communication function for I2C example. + Nov 10,2020 1. Revise I2C TxEmpty & Complete share IRQ handler entry. + 2. Revise SPI idle share IRQ handler flag judgment. + + Oct 30,2020 1. Rename register DMA_CHxCTL bit4 SRTPEN as SRPTEN +1.1.1 + Oct 27,2020 1. Modify I2C driver and I2C example. + Oct 19,2020 1. Modify USART UART/smartcard/clock-sync initialization function. + + Oct 13,2020 1. Modify PWC_WKTM_WKUPFLAG as 0x80. + 2. Remove definition PWC_RXD0_WKUPFLAG. + 3. Write 1 to bit14 in STPMCR. + + Sep 25,2020 1. Rename Interrupt/Event source in hc32f46x.h: INT_I2Cx_EE1 to INT_I2Cx_EEI, EVT_I2Cx_EE1 to EVT_I2Cx_EEI. + 2. Fixed some spelling mistakes. + + Sep 15,2020 1. Modify i2s driver for duplex mode and add example i2s_fullduplex. + 2. Modify i2s clock pclk source from pclk3 to pclk1. + 3. Add systick related function to the utility driver. + 4. Add systick example. + + Aug 28,2020 1. Fix bug for example usbd_mouse. + 2. Modify macro define in usb_conf.h file. + 3. Modify usbd_cdc_Setup() function for USBD CDC class. + 4. Update the drivers and examples based on the header file. + 5. Fix bug for i2c_slave_polling. + 6. Update headfile for i2c DTR and DRR register. + + Jul 31,2020 1. Synchronize driver register with chip manual. + + Jul 20,2020 1. Add wait RDY at begin of func. EFM_SetErasePgmMode(). + 2. Modified en_efm_erase_pgm_md_t as #define + + Jul 7,2020 1. Fixed a bug in spi_write_read_flash example. + 2. Remove register XTAL32CFGR XTAL32SUPDRV bit + 3. Modified func. DMA_ReConfig() function & add func. DMA_ReCfgLlp() + 4. Modified func. PWC_PdWakeupEvtEdgeCfg() & add func. PWC_ClearPvdFlag() + 5. Modified comment & spell error + + May 21,2020 1. unify EFM wait cycle for all examples + 2. KEYSCAN example refine + + Feb 27,2020 1. Driver refine for PWC/CLK + + Feb 14,2020 1. Logic error in timer4 reload share irq + + Jan 08,2020 1. Added GCC compiler support. + 2. Added Eclipse project files for each example project. + 3. Fixed a bug of IS_ADC_TRIG_SRC_EVENT in hc32f46x_adc.c. + 4. Fixed a bug of function AdcChannelConfig in ..\example\adc\adc_10_internal_channel\source\main.c. + + Jan 07,2020 1. Modify usbh_mouse_kb example for GCC compiler. + 2. Modify readme file for usbh_msc example. + + Jan 06,2020 1. Fixed a bug in example adc_10_internal_channel. + Turn on the clock of CMP while ADC input source is internal VREF. + + Jan 06,2020 1. Fix bug for CMP CMP_ADC_SetRefVoltPath function. + + Dec 30,2019 1. Set FPU function in system initialization stage. + + Dec 24,2019 1. Add USB host example -> HID mouse and Keyboard. + 2. Refine ext int example. + + Dec 13,2019 1. Modify media data for i2s_play_wm8731_44k and i2s_play_wm8731_exck_8k example. + + Dec 12,2019 1. Add AsyncDelay for timer0 driver. + 2. Check operation result when switch speed for SD midware. + 3. Remove limit of 4 bytes align for SD write/read buffer. + 4. Dmac.c typo + 5. Delete some duplicate files + + Dec 11,2019 1. Fix bug for TIMERA_OrthogonalCodingInit function. + + Dec 10,2019 1. Modify USBLIB for GCC compiler. + 2. Add Timeout function for timer0 driver. + + Dec 6,2019 1. Modify the wrong word of QSPI example. + + Dec 4,2019 1. Fix bug for TIMERA_HwTriggerInit and TIMERA_HwClearConfig Function. + + Nov 22,2019 1. Fix bug for I2C slave example: Clear STOP and NACK flag after address flag detected. + + Nov 19,2019 1. add hid_msc composite device demo + 2. MISRAC2004 for some source files + + Nov 11,2019 1. modify for USBLIB: Add IAD descriptor for VCP device. + + Nov 8,2019 1. Added support for GCC. + + Nov 5,2019 1. modify for USBLIB: re-open usb clock in DCD_SessionRequest_ISR function + 2. Fix bug for example i2c_slave_irq + + Nov 1,2019 1. Fix bug for mem_cmp function in ff.c. + 2. Correct access width from u32 to u16 of GPIO regs: PODR, POER, POSR, PORR, POTR + + Oct 30,2019 1. Fix bug for QSPI_PrefetchCmd Function. + + Oct 21,2019 1. Add function CLK_ClearXtalStdFlg to clk.c + 2. Modified function PWC_EnterPowerDownMd #add 30 clock cycle after set PWDN + 3. Fix bug for I2S_ClrErrFlag function + + Oct 10,2019 1. Move PWC_EnterPowerDownMd func to ran for IAR + + Oct 9, 2019 1. Modified Set function(transfer count, block size, src/dest address etc.) in dma.c + + Sept 27,2019 1. Fixed bug for function CLK_SysClkConfig # CMU_SCFGR register reserved bits 31~28 should be equal with bits 27~24 + + Sept 25,2019 1. Add examples of Timer6 module. + 2. Add Trigger source config API of Timer6 + +1.1.0 + Sept 16,2019 1. Modify startup file for KEIL project. + 2. Fix bug when using KEIL compiler.(USBFS Register GRXSTSP is read for multiple times.) + + Aug 29, 2019 1. modify DDL code for C-STAT and MISRA-2004 warning. + 2. add RAM3 wait-time in startup_hc32f46x.s + +1.0.4 + July 31, 2019 1. Fix bug for i2c_at24c02 example. + + July 29, 2019 1. modify for timer0 driver: timer0 UNIT1 channelA can't configured as synchronous mode. + 2. modify the port configuration for USB example. + + July 25, 2019 1. Modify usb_core.c, Configuration FIFO for each IN ENDPOINT. + 2. Add device class hid_custom. + Add device class composite device(HID + CDC) + 3. modify device class name from "hid" to "hid_mouse". + modify device class name from "vcp" to "cdc_vcp" + 4. Add example hid_custom. + Add example composite device cdc_hid + + July 16, 2019 1. modified CMP driver enumeration en_cmp_inp4_sel_t + 2. modify spelling mistake for "position" + 3. modify macro UART_DEBUG_PRINTF to hc32f46x_utility.h file + + July 2, 2019 1. modified SRAM_Init + 2. add SRAM_Init to clk_switch_sysclk sample, mainly setting sram + read/write cycle + + July 1, 2019 1. Fix bug for I2S_FuncCmd() function. + 2. Modify headfile hc32f46x.h for keyscan. + + June 19, 2019 1. dma.c & dma.h + add readback to ensure write correct to DMA DMA_SetXx fun. + add wait running channel disable before DMA_ChannelCmd. + modified the functions DMA_SetXx & DMA_ChannelCmd void as en_result_t + + Jun 6, 2019 1. add USB CDC VCP + 2. comment assert() in usart baudrate failure case + + Jun 3, 2019 1. modify MPU protection regions write/read permission functions + + May 29, 2019 1. Add comment to func CLK_GetI2sClkSource in hc32f46x_clk.c + 2. interrupt.c + SPI_SPEI and SPI_SPII bit position in share IRQ register of SPI.1~4 + + May 28, 2019 1. Fix bug for i2c_master_polling example. + 2. modifid PIDRH register + 3. delete setupxx at .mac file + + May 24, 2019 1. convert encoding to UTF-8 for readme.txt + 2. add clock division interface of SPI + 3. add clock division and WP_Pin level interface of QSPI + 4. modify some words to be misspelled + 5. add USB MSC device card reader + 6. add MW_W25QXX_ENABLE in all ddl_config.h + 7. modify comment for usb lib and example + 8. modify device PID and VID + 9. add CLK_GetPllClockFreq function + 10.add CLK_GetI2sClkSource function + 11.modify Timer4 pwm: POCR register channel offset + 12.fix bug for i2s slave mode + 13.add DAM MON_xx register + 14.modified ICG.HRCFREQSEL as 1 bit + 15.add RTC CR1.ALMFCLR, CR2.ALMF + 16.add EFM FRMC.LVM + 17.add alarm flag to RTC + 18.set USB 1st DeviceDescriptor len to 8 + 19.synchronize hc32f46x_ddl.chm version to 1.0.4 and update above + + 1.0.3 May 15, 2019 1. add EFM_ClearFlag at ahead of program & erase + 2. comment valid check in EFM_ClearFlag + + May 8, 2019 1. usb driver + use SPACE instead of TAB + 2. interrupt + typo + delete RTC interrupt ISR in share IRQ handler + EfmPageEraseErr_IrqHandler --> EfmPgmEraseErr_IrqHandler + 3. exint_nmi_swi + delete callback function pointer in exint init structure + + Apr 26, 2019 1. modified CMU_ClrResetFlag func. comment + + Apr 22, 2019 1. word spelling error + 2. upll setting for adc/usb/trng + + Apr 18, 2019 1. modify comments about OVER8 = 1 + 2. modify baudrate calculate + 3. delete duplicated semicolon + + Apr 9, 2019 1. modified IS_XTAL_STOP_VALID & IS_HRC_STOP_VALID + 2. add judge before IS_XXX_STOP_VALID + + Apr 4, 2019 1. recover IS_PLLQ_DIV_VALID, recover CLK_PLLM_MIN as 1u + 2. add IS_UPLLM_VALID because of upllm 2~24 and pllm 1~24 + 3. modified func CLK_UpllConfig , IS_PLLM_VALID as + IS_UPLLM_VALID and comment pllm between 1M and 24M + 4. modified CLK_PLLM_MIN as 2u, CLK_PLLN_MAX as 480u + 5. use IS_PLL_DIV_VALID instead of IS_PLLQ_DIV_VALID + 6. modified func CLK_MpllConfig comment, pllsource/pllm + is between 1MHz and 24MHz. + + Apr 1, 2019 1. add EP2 OUT function for HID device + + Mar 18, 2019 1. update chm file according to src updating + + Mar 15, 2019 1. add CRC driver & sample + 2. bug fix + ICG/PWC/CLK/I2C + + Mar 11, 2019 1. modify efm/rtc/clk/ driver & sample + 2. update SFR & SVD for IDE + 3. add 'ram.ini' for MDK RAM function + 4. add CRC pre-process + + Mar 7, 2019 1. first release on github.com + +EOF