diff --git a/MDK/EventRecorderStub.scvd b/MDK/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/MDK/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/MDK/JLinkSettings.ini b/MDK/JLinkSettings.ini new file mode 100644 index 0000000..79743a7 --- /dev/null +++ b/MDK/JLinkSettings.ini @@ -0,0 +1,35 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="Cortex-M0+" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/MDK/RTE/RTOS/board.c b/MDK/RTE/RTOS/board.c new file mode 100644 index 0000000..e45e75f --- /dev/null +++ b/MDK/RTE/RTOS/board.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-24 the first version + */ + +#include +#include + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) +/* + * Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP + * the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes + */ +#define RT_HEAP_SIZE (15*1024) +static rt_uint8_t rt_heap[RT_HEAP_SIZE]; + +RT_WEAK void *rt_heap_begin_get(void) +{ + return rt_heap; +} + +RT_WEAK void *rt_heap_end_get(void) +{ + return rt_heap + RT_HEAP_SIZE; +} +#endif + +void rt_os_tick_callback(void) +{ + rt_interrupt_enter(); + + rt_tick_increase(); + + rt_interrupt_leave(); +} + +/** + * This function will initial your board. + */ +void rt_hw_board_init(void) +{ +#error "TODO 1: OS Tick Configuration." + /* + * TODO 1: OS Tick Configuration + * Enable the hardware timer and call the rt_os_tick_callback function + * periodically with the frequency RT_TICK_PER_SECOND. + */ + + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get()); +#endif +} + +#ifdef RT_USING_CONSOLE + +static int uart_init(void) +{ +#error "TODO 2: Enable the hardware uart and config baudrate." + return 0; +} +INIT_BOARD_EXPORT(uart_init); + +void rt_hw_console_output(const char *str) +{ +#error "TODO 3: Output the string 'str' through the uart." +} + +#endif + diff --git a/MDK/RTE/RTOS/board.c.base@3.1.5 b/MDK/RTE/RTOS/board.c.base@3.1.5 new file mode 100644 index 0000000..e45e75f --- /dev/null +++ b/MDK/RTE/RTOS/board.c.base@3.1.5 @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-24 the first version + */ + +#include +#include + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) +/* + * Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP + * the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes + */ +#define RT_HEAP_SIZE (15*1024) +static rt_uint8_t rt_heap[RT_HEAP_SIZE]; + +RT_WEAK void *rt_heap_begin_get(void) +{ + return rt_heap; +} + +RT_WEAK void *rt_heap_end_get(void) +{ + return rt_heap + RT_HEAP_SIZE; +} +#endif + +void rt_os_tick_callback(void) +{ + rt_interrupt_enter(); + + rt_tick_increase(); + + rt_interrupt_leave(); +} + +/** + * This function will initial your board. + */ +void rt_hw_board_init(void) +{ +#error "TODO 1: OS Tick Configuration." + /* + * TODO 1: OS Tick Configuration + * Enable the hardware timer and call the rt_os_tick_callback function + * periodically with the frequency RT_TICK_PER_SECOND. + */ + + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get()); +#endif +} + +#ifdef RT_USING_CONSOLE + +static int uart_init(void) +{ +#error "TODO 2: Enable the hardware uart and config baudrate." + return 0; +} +INIT_BOARD_EXPORT(uart_init); + +void rt_hw_console_output(const char *str) +{ +#error "TODO 3: Output the string 'str' through the uart." +} + +#endif + diff --git a/MDK/RTE/RTOS/finsh_config.h b/MDK/RTE/RTOS/finsh_config.h new file mode 100644 index 0000000..a5a7340 --- /dev/null +++ b/MDK/RTE/RTOS/finsh_config.h @@ -0,0 +1,29 @@ +/* FinSH config file */ + +#ifndef __MSH_CFG_H__ +#define __MSH_CFG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_USING_MSH_ONLY +// FinSH Configuration +// the priority of finsh thread <1-30> +// the priority of finsh thread +// Default: 21 +#define FINSH_THREAD_PRIORITY 21 +// the stack of finsh thread <1-4096> +// the stack of finsh thread +// Default: 4096 (4096Byte) +#define FINSH_THREAD_STACK_SIZE 1024 + +#define FINSH_USING_SYMTAB +// Enable command description +// Enable command description +#define FINSH_USING_DESCRIPTION +// +// + +// <<< end of configuration section >>> +#endif + diff --git a/MDK/RTE/RTOS/finsh_config.h.base@3.1.5 b/MDK/RTE/RTOS/finsh_config.h.base@3.1.5 new file mode 100644 index 0000000..a5a7340 --- /dev/null +++ b/MDK/RTE/RTOS/finsh_config.h.base@3.1.5 @@ -0,0 +1,29 @@ +/* FinSH config file */ + +#ifndef __MSH_CFG_H__ +#define __MSH_CFG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_USING_MSH_ONLY +// FinSH Configuration +// the priority of finsh thread <1-30> +// the priority of finsh thread +// Default: 21 +#define FINSH_THREAD_PRIORITY 21 +// the stack of finsh thread <1-4096> +// the stack of finsh thread +// Default: 4096 (4096Byte) +#define FINSH_THREAD_STACK_SIZE 1024 + +#define FINSH_USING_SYMTAB +// Enable command description +// Enable command description +#define FINSH_USING_DESCRIPTION +// +// + +// <<< end of configuration section >>> +#endif + diff --git a/MDK/RTE/RTOS/finsh_port.c b/MDK/RTE/RTOS/finsh_port.c new file mode 100644 index 0000000..4e3f7ff --- /dev/null +++ b/MDK/RTE/RTOS/finsh_port.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include + +#ifndef RT_USING_FINSH +#error Please uncomment the line <#include "finsh_config.h"> in the rtconfig.h +#endif + +#ifdef RT_USING_FINSH + +RT_WEAK char rt_hw_console_getchar(void) +{ + /* Note: the initial value of ch must < 0 */ + int ch = -1; + +#error "TODO 4: Read a char from the uart and assign it to 'ch'." + + return ch; +} + +#endif /* RT_USING_FINSH */ + diff --git a/MDK/RTE/RTOS/finsh_port.c.base@3.1.5 b/MDK/RTE/RTOS/finsh_port.c.base@3.1.5 new file mode 100644 index 0000000..4e3f7ff --- /dev/null +++ b/MDK/RTE/RTOS/finsh_port.c.base@3.1.5 @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include + +#ifndef RT_USING_FINSH +#error Please uncomment the line <#include "finsh_config.h"> in the rtconfig.h +#endif + +#ifdef RT_USING_FINSH + +RT_WEAK char rt_hw_console_getchar(void) +{ + /* Note: the initial value of ch must < 0 */ + int ch = -1; + +#error "TODO 4: Read a char from the uart and assign it to 'ch'." + + return ch; +} + +#endif /* RT_USING_FINSH */ + diff --git a/MDK/RTE/RTOS/rtconfig.h b/MDK/RTE/RTOS/rtconfig.h new file mode 100644 index 0000000..5b54665 --- /dev/null +++ b/MDK/RTE/RTOS/rtconfig.h @@ -0,0 +1,139 @@ +/* RT-Thread config file */ + +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Configuration +// Maximal level of thread priority <8-256> +// Default: 32 +#define RT_THREAD_PRIORITY_MAX 32 +// OS tick per second +// Default: 1000 (1ms) +#define RT_TICK_PER_SECOND 1000 +// Alignment size for CPU architecture data access +// Default: 4 +#define RT_ALIGN_SIZE 4 +// the max length of object name<2-16> +// Default: 8 +#define RT_NAME_MAX 8 +// Using RT-Thread components initialization +// Using RT-Thread components initialization +#define RT_USING_COMPONENTS_INIT +// + +#define RT_USING_USER_MAIN + +// the stack size of main thread<1-4086> +// Default: 512 +#define RT_MAIN_THREAD_STACK_SIZE 256 + +// + +// Debug Configuration +// enable kernel debug configuration +// Default: enable kernel debug configuration +//#define RT_DEBUG +// +// enable components initialization debug configuration<0-1> +// Default: 0 +#define RT_DEBUG_INIT 0 +// thread stack over flow detect +// Diable Thread stack over flow detect +//#define RT_USING_OVERFLOW_CHECK +// +// + +// Hook Configuration +// using hook +// using hook +//#define RT_USING_HOOK +// +// using idle hook +// using idle hook +//#define RT_USING_IDLE_HOOK +// +// + +// Software timers Configuration +// Enables user timers +#define RT_USING_TIMER_SOFT 0 +#if RT_USING_TIMER_SOFT == 0 + #undef RT_USING_TIMER_SOFT +#endif +// The priority level of timer thread <0-31> +// Default: 4 +#define RT_TIMER_THREAD_PRIO 4 +// The stack size of timer thread <0-8192> +// Default: 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 +// + +// IPC(Inter-process communication) Configuration +// Using Semaphore +// Using Semaphore +#define RT_USING_SEMAPHORE +// +// Using Mutex +// Using Mutex +//#define RT_USING_MUTEX +// +// Using Event +// Using Event +//#define RT_USING_EVENT +// +// Using MailBox +// Using MailBox +#define RT_USING_MAILBOX +// +// Using Message Queue +// Using Message Queue +//#define RT_USING_MESSAGEQUEUE +// +// + +// Memory Management Configuration +// Memory Pool Management +// Memory Pool Management +//#define RT_USING_MEMPOOL +// +// Dynamic Heap Management(Algorithm: small memory ) +// Dynamic Heap Management +#define RT_USING_HEAP +#define RT_USING_SMALL_MEM +// +// using tiny size of memory +// using tiny size of memory +//#define RT_USING_TINY_SIZE +// +// + +// Console Configuration +// Using console +// Using console +//#define RT_USING_CONSOLE +// +// the buffer size of console <1-1024> +// the buffer size of console +// Default: 128 (128Byte) +#define RT_CONSOLEBUF_SIZE 256 +// + +// FinSH Configuration +// include finsh config +// Select this choice if you using FinSH +//#include "finsh_config.h" +// +// + +// Device Configuration +// using device framework +// using device framework +//#define RT_USING_DEVICE +// +// + +// <<< end of configuration section >>> + +#endif diff --git a/MDK/RTE/RTOS/rtconfig.h.base@3.1.5 b/MDK/RTE/RTOS/rtconfig.h.base@3.1.5 new file mode 100644 index 0000000..5b54665 --- /dev/null +++ b/MDK/RTE/RTOS/rtconfig.h.base@3.1.5 @@ -0,0 +1,139 @@ +/* RT-Thread config file */ + +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Configuration +// Maximal level of thread priority <8-256> +// Default: 32 +#define RT_THREAD_PRIORITY_MAX 32 +// OS tick per second +// Default: 1000 (1ms) +#define RT_TICK_PER_SECOND 1000 +// Alignment size for CPU architecture data access +// Default: 4 +#define RT_ALIGN_SIZE 4 +// the max length of object name<2-16> +// Default: 8 +#define RT_NAME_MAX 8 +// Using RT-Thread components initialization +// Using RT-Thread components initialization +#define RT_USING_COMPONENTS_INIT +// + +#define RT_USING_USER_MAIN + +// the stack size of main thread<1-4086> +// Default: 512 +#define RT_MAIN_THREAD_STACK_SIZE 256 + +// + +// Debug Configuration +// enable kernel debug configuration +// Default: enable kernel debug configuration +//#define RT_DEBUG +// +// enable components initialization debug configuration<0-1> +// Default: 0 +#define RT_DEBUG_INIT 0 +// thread stack over flow detect +// Diable Thread stack over flow detect +//#define RT_USING_OVERFLOW_CHECK +// +// + +// Hook Configuration +// using hook +// using hook +//#define RT_USING_HOOK +// +// using idle hook +// using idle hook +//#define RT_USING_IDLE_HOOK +// +// + +// Software timers Configuration +// Enables user timers +#define RT_USING_TIMER_SOFT 0 +#if RT_USING_TIMER_SOFT == 0 + #undef RT_USING_TIMER_SOFT +#endif +// The priority level of timer thread <0-31> +// Default: 4 +#define RT_TIMER_THREAD_PRIO 4 +// The stack size of timer thread <0-8192> +// Default: 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 +// + +// IPC(Inter-process communication) Configuration +// Using Semaphore +// Using Semaphore +#define RT_USING_SEMAPHORE +// +// Using Mutex +// Using Mutex +//#define RT_USING_MUTEX +// +// Using Event +// Using Event +//#define RT_USING_EVENT +// +// Using MailBox +// Using MailBox +#define RT_USING_MAILBOX +// +// Using Message Queue +// Using Message Queue +//#define RT_USING_MESSAGEQUEUE +// +// + +// Memory Management Configuration +// Memory Pool Management +// Memory Pool Management +//#define RT_USING_MEMPOOL +// +// Dynamic Heap Management(Algorithm: small memory ) +// Dynamic Heap Management +#define RT_USING_HEAP +#define RT_USING_SMALL_MEM +// +// using tiny size of memory +// using tiny size of memory +//#define RT_USING_TINY_SIZE +// +// + +// Console Configuration +// Using console +// Using console +//#define RT_USING_CONSOLE +// +// the buffer size of console <1-1024> +// the buffer size of console +// Default: 128 (128Byte) +#define RT_CONSOLEBUF_SIZE 256 +// + +// FinSH Configuration +// include finsh config +// Select this choice if you using FinSH +//#include "finsh_config.h" +// +// + +// Device Configuration +// using device framework +// using device framework +//#define RT_USING_DEVICE +// +// + +// <<< end of configuration section >>> + +#endif diff --git a/MDK/RTE/_HC32L17X/RTE_Components.h b/MDK/RTE/_HC32L17X/RTE_Components.h new file mode 100644 index 0000000..4e84c89 --- /dev/null +++ b/MDK/RTE/_HC32L17X/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'hc32l17x' + * Target: 'HC32L17X' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32L170JATA.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/MDK/RTE/__FEATURE__Release/RTE_Components.h b/MDK/RTE/__FEATURE__Release/RTE_Components.h new file mode 100644 index 0000000..a2dd5ef --- /dev/null +++ b/MDK/RTE/__FEATURE__Release/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'ddl_template' + * Target: '{FEATURE}_Release' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0plus.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/MDK/RTE/_template_Release/RTE_Components.h b/MDK/RTE/_template_Release/RTE_Components.h new file mode 100644 index 0000000..97bd6b0 --- /dev/null +++ b/MDK/RTE/_template_Release/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'hc32l17x' + * Target: 'template_Release' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0plus.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/MDK/hc32l17x.uvoptx b/MDK/hc32l17x.uvoptx new file mode 100644 index 0000000..942295c --- /dev/null +++ b/MDK/hc32l17x.uvoptx @@ -0,0 +1,798 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + HC32L17X + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\release\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L17X_128K.FLM -FS00 -FL020000 -FP0($$Device:HC32L170JATA$Flash\FlashHC32L17X_128K.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0FlashHC32L17X_128K -FL020000 -FS00 -FP0($$Device:HC32L170JATA$Flash\FlashHC32L17X_128K.FLM) + + + 0 + JL2CM3 + -U4294967295 -O78 -S1 -ZTIFSpeedSel10000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8027 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L17X_128K.FLM -FS00 -FL020000 -FP0($$Device:HC32L170JATA$Flash\FlashHC32L17X_128K.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + + + + 0 + 1 + App.Login2Min30SCount,0x0A + + + 1 + 1 + App.TD1mSDelayCnt,0x0A + + + 2 + 1 + App.Nonce,0x0A + + + 3 + 1 + App.RDStatus,0x0A + + + 4 + 1 + SGCP.TimingAcquisition + + + 5 + 1 + App.Para.Layout.CollectTime,0x0A + + + 6 + 1 + App.Para.Layout.ReportInterval,0x0A + + + 7 + 1 + App.Para.Layout.ERInterval,0x0A + + + 8 + 1 + App.Para.Layout.ERTime,0x0A + + + 9 + 1 + App.Para.Layout.TimeStamp,0x0A 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0 + 0 + 0 + ..\source\src\Algorithm.c + Algorithm.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\source\src\SGCP.c + SGCP.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\source\src\Update.c + Update.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 9 + 1 + 0 + 0 + 0 + ..\driver\src\dmac.c + dmac.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\driver\src\flash.c + flash.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\driver\src\gpio.c + gpio.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\driver\src\lpm.c + lpm.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\driver\src\lpuart.c + lpuart.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\driver\src\spi.c + spi.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\driver\src\uart.c + uart.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\driver\src\wdt.c + wdt.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\driver\src\ddl.c + ddl.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\driver\src\sysctrl.c + sysctrl.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\driver\src\reset.c + reset.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\driver\src\lptim.c + lptim.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\driver\src\rtc.c + rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\driver\src\trim.c + trim.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\driver\src\i2c.c + i2c.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\driver\src\bt.c + bt.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\driver\src\adc.c + adc.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\driver\src\bgr.c + bgr.c + 0 + 0 + + + + + Debug + 0 + 0 + 0 + 0 + + 4 + 27 + 1 + 0 + 0 + 0 + ..\Module\Debug\UartDebug.c + UartDebug.c + 0 + 0 + + + + + LSM6DSL + 1 + 0 + 0 + 0 + + 5 + 28 + 1 + 0 + 0 + 0 + ..\Module\lsm6dsl\lsm6dsl_reg.c + lsm6dsl_reg.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\Module\lsm6dsl\lsm6dsl_app.c + lsm6dsl_app.c + 0 + 0 + + + + + MMC5893 + 1 + 0 + 0 + 0 + + 6 + 30 + 1 + 0 + 0 + 0 + ..\Module\MMC5983\mmc5983.c + mmc5983.c + 0 + 0 + + + + + LORA + 1 + 0 + 0 + 0 + + 7 + 31 + 1 + 0 + 0 + 0 + ..\Module\LORA\sx127x.c + sx127x.c + 0 + 0 + + + + + Imu + 0 + 0 + 0 + 0 + + 8 + 32 + 1 + 0 + 0 + 0 + ..\Module\Imu\Imu.c + Imu.c + 0 + 0 + + + + + ReadMe + 1 + 0 + 0 + 0 + + 9 + 33 + 5 + 0 + 0 + 0 + ..\ReadMe.txt + ReadMe.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/MDK/hc32l17x.uvprojx b/MDK/hc32l17x.uvprojx new file mode 100644 index 0000000..8c21bb1 --- /dev/null +++ b/MDK/hc32l17x.uvprojx @@ -0,0 +1,650 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + HC32L17X + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 6160000::V6.16::ARMCLANG + 1 + + + HC32L170JATA + HDSC + HDSC.HC32L17X.1.0.1 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IRAM(0x20000000,0x4000) IROM(0x00000000,0x20000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L17X_128K -FS00 -FL020000 -FP0($$Device:HC32L170JATA$Flash\FlashHC32L17X_128K.FLM)) + 0 + $$Device:HC32L170JATA$Device\Include\HC32L170JATA.h + + + + + + + + + + $$Device:HC32L170JATA$SVD\HC32L170JATA.sfr + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\ + hc32l17x + 1 + 0 + 1 + 1 + 1 + .\output\release\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 1 + + D:\Keil5\ARM\ARMCC\bin\fromelf.exe --bin -o .\output\app.bin .\output\hc32l17x.axf + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x2a00 + 0x1d600 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 0 + 0 + 0 + 0 + 0 + + + + + ..\mcu\common;..\source;..\driver\inc;..\source\inc;..\Module\Debug;..\Module\lsm6dsl;..\Module\MMC5983;..\Module\LORA;..\Module\Imu + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + template.sct + + + --keep=*Handler + + + + + + + + common + + + startup_hc32l17x.s + 2 + .\startup_hc32l17x.s + + + system_hc32l17x.c + 1 + ..\mcu\common\system_hc32l17x.c + + + interrupts_hc32l17x.c + 1 + ..\mcu\common\interrupts_hc32l17x.c + + + + + source + + + main.c + 1 + ..\source\Src\main.c + + + bsp.c + 1 + ..\source\src\bsp.c + + + Algorithm.c + 1 + ..\source\src\Algorithm.c + + + SGCP.c + 1 + ..\source\src\SGCP.c + + + Update.c + 1 + ..\source\src\Update.c + + + + + driver + + + dmac.c + 1 + ..\driver\src\dmac.c + + + flash.c + 1 + ..\driver\src\flash.c + + + gpio.c + 1 + ..\driver\src\gpio.c + + + lpm.c + 1 + ..\driver\src\lpm.c + + + lpuart.c + 1 + ..\driver\src\lpuart.c + + + spi.c + 1 + ..\driver\src\spi.c + + + uart.c + 1 + ..\driver\src\uart.c + + + wdt.c + 1 + ..\driver\src\wdt.c + + + ddl.c + 1 + ..\driver\src\ddl.c + + + sysctrl.c + 1 + ..\driver\src\sysctrl.c + + + reset.c + 1 + ..\driver\src\reset.c + + + lptim.c + 1 + ..\driver\src\lptim.c + + + rtc.c + 1 + ..\driver\src\rtc.c + + + trim.c + 1 + ..\driver\src\trim.c + + + i2c.c + 1 + ..\driver\src\i2c.c + + + bt.c + 1 + ..\driver\src\bt.c + + + adc.c + 1 + ..\driver\src\adc.c + + + bgr.c + 1 + ..\driver\src\bgr.c + + + + + Debug + + + UartDebug.c + 1 + ..\Module\Debug\UartDebug.c + + + + + LSM6DSL + + + lsm6dsl_reg.c + 1 + ..\Module\lsm6dsl\lsm6dsl_reg.c + + + lsm6dsl_app.c + 1 + ..\Module\lsm6dsl\lsm6dsl_app.c + + + + + MMC5893 + + + mmc5983.c + 1 + ..\Module\MMC5983\mmc5983.c + + + + + LORA + + + sx127x.c + 1 + ..\Module\LORA\sx127x.c + + + + + Imu + + + Imu.c + 1 + ..\Module\Imu\Imu.c + + + + + ReadMe + + + ReadMe.txt + 5 + ..\ReadMe.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\RTOS\board.c + + + + + + RTE\RTOS\finsh_config.h + + + + + + RTE\RTOS\finsh_port.c + + + + + + RTE\RTOS\rtconfig.h + + + + + + + + + + + hc32l17x + 0 + 1 + + + + + diff --git a/MDK/output/hc32l17x.sct b/MDK/output/hc32l17x.sct new file mode 100644 index 0000000..cb5ea6a --- /dev/null +++ b/MDK/output/hc32l17x.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00002A00 0x0001D600 { ; load region size_region + ER_IROM1 0x00002A00 0x0001D600 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/MDK/startup_hc32l17x.s b/MDK/startup_hc32l17x.s new file mode 100644 index 0000000..75e56af --- /dev/null +++ b/MDK/startup_hc32l17x.s @@ -0,0 +1,301 @@ +;/****************************************************************************** +;* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +;* +;* This software is owned and published by: +;* Huada Semiconductor Co.,Ltd ("HDSC"). +;* +;* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +;* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +;* +;* This software contains source code for use with HDSC +;* components. This software is licensed by HDSC to be adapted only +;* for use in systems utilizing HDSC components. HDSC shall not be +;* responsible for misuse or illegal use of this software for devices not +;* supported herein. HDSC is providing this software "AS IS" and will +;* not be responsible for issues arising from incorrect user implementation +;* of the software. +;* +;* Disclaimer: +;* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +;* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +;* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +;* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +;* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +;* WARRANTY OF NONINFRINGEMENT. +;* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +;* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +;* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +;* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +;* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +;* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +;* SAVINGS OR PROFITS, +;* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +;* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +;* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +;* FROM, THE SOFTWARE. +;* +;* This software may be replicated in part or whole for the licensed use, +;* with the restriction that this Disclaimer and Copyright notice must be +;* included with each copy of this software, whether used in part or whole, +;* at all times. +;*/ +;/*****************************************************************************/ + +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2019-03-01 */ +;/* Target-mcu {MCU_PN_H} */ +;/*****************************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00002200 + +new_vect_table EQU 0x00002A00 ;中断向量偏移长度 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + + DCD PORTA_IRQHandler + DCD PORTB_IRQHandler + DCD PORTC_E_IRQHandler + DCD PORTD_F_IRQHandler + DCD DMAC_IRQHandler + DCD TIM3_IRQHandler + DCD UART0_2_IRQHandler + DCD UART1_3_IRQHandler + DCD LPUART0_IRQHandler + DCD LPUART1_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD I2C0_IRQHandler + DCD I2C1_IRQHandler + DCD TIM0_IRQHandler + DCD TIM1_IRQHandler + DCD TIM2_IRQHandler + DCD LPTIM0_1_IRQHandler + DCD TIM4_IRQHandler + DCD TIM5_IRQHandler + DCD TIM6_IRQHandler + DCD PCA_IRQHandler + DCD WDT_IRQHandler + DCD RTC_IRQHandler + DCD ADC_DAC_IRQHandler + DCD PCNT_IRQHandler + DCD VC0_IRQHandler + DCD VC1_2_IRQHandler + DCD LVD_IRQHandler + DCD LCD_IRQHandler + DCD FLASH_RAM_IRQHandler + DCD CLKTRIM_IRQHandler + + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ;reset NVIC if in rom debug + LDR R0, =0x20000000 + LDR R2, =0x0 + MOVS R1, #0 ; for warning, + ADD R1, PC,#0 ; for A1609W, + CMP R1, R0 + BLS RAMCODE + + ; ram code base address. + ADD R2, R0,R2 +RAMCODE + ; reset Vector table address. + LDR R0, =0xE000ED08 + LDR R2, =new_vect_table ;升级时打开 + STR R2, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + + +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_E_IRQHandler [WEAK] + EXPORT PORTD_F_IRQHandler [WEAK] + EXPORT DMAC_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT UART0_2_IRQHandler [WEAK] + EXPORT UART1_3_IRQHandler [WEAK] + EXPORT LPUART0_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM1_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT LPTIM0_1_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT PCA_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT ADC_DAC_IRQHandler [WEAK] + EXPORT PCNT_IRQHandler [WEAK] + EXPORT VC0_IRQHandler [WEAK] + EXPORT VC1_2_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT FLASH_RAM_IRQHandler [WEAK] + EXPORT CLKTRIM_IRQHandler [WEAK] +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_E_IRQHandler +PORTD_F_IRQHandler +DMAC_IRQHandler +TIM3_IRQHandler +UART0_2_IRQHandler +UART1_3_IRQHandler +LPUART0_IRQHandler +LPUART1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +TIM0_IRQHandler +TIM1_IRQHandler +TIM2_IRQHandler +LPTIM0_1_IRQHandler +TIM4_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +PCA_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +ADC_DAC_IRQHandler +PCNT_IRQHandler +VC0_IRQHandler +VC1_2_IRQHandler +LVD_IRQHandler +LCD_IRQHandler +FLASH_RAM_IRQHandler +CLKTRIM_IRQHandler + + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/Module/Imu/Imu.c b/Module/Imu/Imu.c new file mode 100644 index 0000000..79b428b --- /dev/null +++ b/Module/Imu/Imu.c @@ -0,0 +1,298 @@ +/************************************************************************************************ +* 程序版本：V3.0 +* 程序日期：2022-11-3 +* 程序作者： +************************************************************************************************/ +#include "Imu.h" +#include "main.h" + +#define Kp_New 0.9f //互补滤波当前数据的权重 +#define Kp_Old 0.1f //互补滤波历史数据的权重 +#define Acc_Gain 0.0001220f //加速度变成G (初始化加速度满量程-+4g LSBa = 2*4/65535.0) +#define Gyro_Gain 0.0609756f //角速度变成度 (初始化陀螺仪满量程+-2000 LSBg = 2*2000/65535.0) +#define Gyro_Gr 0.0010641f //角速度变成弧度(3.1415/180 * LSBg) + +//kp=ki=0 就是完全相信陀螺仪 +#define Kp 1.5f // proportional gain governs rate of convergence to accelerometer/magnetometer + //比例增益控制加速度计，磁力计的收敛速率 +#define Ki 0.005f // integral gain governs rate of convergence of gyroscope biases + //积分增益控制陀螺偏差的收敛速度 +#define halfT 0.005f // half the sample period 采样周期的一半 + +static volatile float q0 = 1, q1 = 0, q2 = 0, q3 = 0; // quaternion elements representing the estimated orientation +static volatile float exInt = 0, eyInt = 0, ezInt = 0; // scaled integral error + +/* +static float MedianValue(float *value_buf, unsigned int size) +{ + + unsigned int i,j; + float temp; + + //排序采用冒泡法 + for (j=0;j<=size;j++){ + for (i=0;i<=size-j;i++){ + if (value_buf[i] > value_buf[i+1]){ + temp = value_buf[i]; + value_buf[i] = value_buf[i+1]; + value_buf[i+1] = temp; + } + } + } + + return value_buf[(size-1)/2]; +} +*/ + +static float MedianValue(float *value_buf, unsigned int size) +{ + unsigned int i; + float temp = 0; + + for (i=0; i=Imu_AccFilterSize)cnt=0; + + return MedianValue(value_buf, Imu_AccFilterSize); +} + +static float Acc_Filter_Y(float in_data) +{ + static float value_buf[Imu_AccFilterSize] = {0}; + static unsigned char cnt = 0; + value_buf[cnt] = in_data; + cnt++; + if (cnt>=Imu_AccFilterSize)cnt=0; + + return MedianValue(value_buf, Imu_AccFilterSize); +} + +static float Acc_Filter_Z(float in_data) +{ + + static float value_buf[Imu_AccFilterSize] = {0}; + static unsigned char cnt = 0; + value_buf[cnt] = in_data; + cnt++; + if (cnt>=Imu_AccFilterSize)cnt=0; + + return MedianValue(value_buf, Imu_AccFilterSize); +} + + +static float Mag_Filter_X(float in_data) +{ + + static float value_buf[Imu_MagFilterSize] = {0}; + static unsigned char cnt = 0; + value_buf[cnt] = in_data; + cnt++; + if (cnt>=Imu_MagFilterSize)cnt=0; + + return MedianValue(value_buf, Imu_MagFilterSize); +} + +static float Mag_Filter_Y(float in_data) +{ + static float value_buf[Imu_MagFilterSize] = {0}; + static unsigned char cnt = 0; + value_buf[cnt] = in_data; + cnt++; + if (cnt>=Imu_MagFilterSize)cnt=0; + + return MedianValue(value_buf, Imu_MagFilterSize); +} + +static float Mag_Filter_Z(float in_data) +{ + + static float value_buf[Imu_MagFilterSize] = {0}; + static unsigned char cnt = 0; + value_buf[cnt] = in_data; + cnt++; + if (cnt>=Imu_MagFilterSize)cnt=0; + + return MedianValue(value_buf, Imu_MagFilterSize); +} + + + + +static float Gyro_Filter_X(float in_data) +{ + static float value_buf[Imu_GyroFilterSize] = {0}; + static unsigned char cnt = 0; + value_buf[cnt] = in_data; + cnt++; + if (cnt>=Imu_GyroFilterSize)cnt=0; + + return MedianValue(value_buf, Imu_GyroFilterSize); +} + +static float Gyro_Filter_Y(float in_data) +{ + static float value_buf[Imu_GyroFilterSize] = {0}; + static unsigned char cnt = 0; + value_buf[cnt] = in_data; + cnt++; + if (cnt>=Imu_GyroFilterSize)cnt=0; + + return MedianValue(value_buf, Imu_GyroFilterSize); +} + +static float Gyro_Filter_Z(float in_data) +{ + static float value_buf[Imu_GyroFilterSize] = {0}; + static unsigned char cnt = 0; + value_buf[cnt] = in_data; + cnt++; + if (cnt>=Imu_GyroFilterSize)cnt=0; + + return MedianValue(value_buf, Imu_GyroFilterSize); +} + + + +static float invSqrt(float x) { + float halfx = 0.5f * x; + float y = x; + long i = *(long*)&y; + i = 0x5f3759df - (i>>1); + y = *(float*)&i; + y = y * (1.5f - (halfx * y * y)); + return y; +} + +static void IMUupdate(float gx, float gy, float gz, float ax, float ay, float az) +{ + float vx, vy, vz; + float ex, ey, ez; + float norm; + + float q0q0 = q0*q0; + float q0q1 = q0*q1; + float q0q2 = q0*q2; + float q0q3 = q0*q3; + float q1q1 = q1*q1; + float q1q2 = q1*q2; + float q1q3 = q1*q3; + float q2q2 = q2*q2; + float q2q3 = q2*q3; + float q3q3 = q3*q3; + + if(ax*ay*az==0) + return; + + //加速度计<测量>的重力加速度向量(机体坐标系) + norm = invSqrt(ax*ax + ay*ay + az*az); + ax = ax * norm; + ay = ay * norm; + az = az * norm; +// printf("ax=%0.2f ay=%0.2f az=%0.2f\r\n",ax,ay,az); + + //陀螺仪积分<估计>重力向量(机体坐标系) + vx = 2*(q1q3 - q0q2); //矩阵(3,1)项 + vy = 2*(q0q1 + q2q3); //矩阵(3,2)项 + vz = q0q0 - q1q1 - q2q2 + q3q3 ; //矩阵(3,3)项 + + + //向量叉乘所得的值 + ex = (ay*vz - az*vy); + ey = (az*vx - ax*vz); + ez = (ax*vy - ay*vx); + + //用上面求出误差进行积分 + exInt = exInt + ex * Ki; + eyInt = eyInt + ey * Ki; + ezInt = ezInt + ez * Ki; + + //将误差PI后补偿到陀螺仪 + gx = gx + Kp*ex + exInt; + gy = gy + Kp*ey + eyInt; + gz = gz + Kp*ez + ezInt;//这里的gz由于没有观测者进行矫正会产生漂移，表现出来的就是积分自增或自减 + + //四元素的微分方程 + q0 = q0 + (-q1*gx - q2*gy - q3*gz)*halfT; + q1 = q1 + (q0*gx + q2*gz - q3*gy)*halfT; + q2 = q2 + (q0*gy - q1*gz + q3*gx)*halfT; + q3 = q3 + (q0*gz + q1*gy - q2*gx)*halfT; + + //单位化四元数 + norm = invSqrt(q0*q0 + q1*q1 + q2*q2 + q3*q3); + q0 = q0 * norm; + q1 = q1 * norm; + q2 = q2 * norm; + q3 = q3 * norm; + +// 矩阵表达式 +// matrix[0] = q0q0 + q1q1 - q2q2 - q3q3; // 11 +// matrix[1] = 2.f * (q1q2 + q0q3); // 12 +// matrix[2] = 2.f * (q1q3 - q0q2); // 13 +// matrix[3] = 2.f * (q1q2 - q0q3); // 21 +// matrix[4] = q0q0 - q1q1 + q2q2 - q3q3; // 22 +// matrix[5] = 2.f * (q2q3 + q0q1); // 23 +// matrix[6] = 2.f * (q1q3 + q0q2); // 31 +// matrix[7] = 2.f * (q2q3 - q0q1); // 32 +// matrix[8] = q0q0 - q1q1 - q2q2 + q3q3; // 33 + + //下一步是四元数转换成欧拉角(Z->Y->X) + +} + +#define ALPHA 0.01 +void IMU_Update(float *gy,float *acc, float *mag, RadDp Rad, DegDp Deg) +{ + static volatile double Phi,Theta, Psi, Gz2, By2, Bz2, Bx3; + volatile float Gyr[XYZ], Acc[XYZ], Mag[XYZ]; + + Gyr[X] = gy[X]; + Gyr[Y] = gy[Y]; + Gyr[Z] = gy[Z]; + + Acc[X] = acc[X]; + Acc[Y] = acc[Y]; + Acc[Z] = acc[Z]; + + Mag[X] = -mag[X]; + Mag[Y] = -mag[Y]; + Mag[Z] = -mag[Z]; + +// IMUupdate(Gyr[X], Gyr[Y], Gyr[Z], Acc[X], Acc[Y], Acc[Z]); + +// Phi = -atan2(2.f * q0*q1 + 2.f * q2*q3, 1 - 2.f * q1*q1 - 2.f * q2*q2); +// Theta = -asin(2.f * (q0*q2 - q1*q3)); + +// volatile float xh = Mag[0]*cos(Theta) + Mag[1]*sin(Phi)*sin(Theta) + Mag[2]*cos(Phi)*sin(Theta); +// volatile float yh = Mag[1]*cos(Phi) - Mag[2]*sin(Phi); +// Psi = atan2(yh, xh); + + Phi = atan2(Acc[Y], (Acc[Z] + Acc[X] * ALPHA)); + //Phi = atan2(Acc[Y], Acc[Z]); + Gz2 = Acc[Y] * sin(Phi) + Acc[Z] * cos(Phi); + Theta = atan(-Acc[X] / Gz2); + + By2 = Mag[Z] * sin(Phi) - Mag[Y] * cos(Phi); + Bz2 = Mag[Y] * sin(Phi) + Mag[Z] * cos(Phi); + Bx3 = Mag[X] * cos(Theta) + Bz2 * sin(Theta); + Psi = atan2(By2, Bx3); + + Rad->roll = Phi; + Rad->pitch = Theta; + Rad->yaw = Psi; + + Deg->roll = Rad->roll * RAD_TO_DEG; + Deg->pitch = Rad->pitch * RAD_TO_DEG; + Deg->yaw = Rad->yaw * RAD_TO_DEG; +} + diff --git a/Module/Imu/Imu.h b/Module/Imu/Imu.h new file mode 100644 index 0000000..3005d6f --- /dev/null +++ b/Module/Imu/Imu.h @@ -0,0 +1,24 @@ +#ifndef _IMU_H_ +#define _IMU_H_ +#include + +#define PI 3.14159265358979323846f +#define RAD_TO_DEG 57.2957795 // 弧度到度的转换系数 +#define DEG_TO_RAD 0.0174533 // 度到弧度的转换系数 + +// 定义欧拉角结构体 +typedef struct { + volatile float roll, pitch, yaw;//弧度 +}Rad_T, *RadDp; +typedef struct { + volatile float roll, pitch, yaw;//角度 +}Deg_T, *DegDp; + +#define Imu_AccFilterSize 10 +#define Imu_MagFilterSize 20 +#define Imu_GyroFilterSize 10 + +void IMU_Update(float *gy,float *acc, float *mag, RadDp Rad, DegDp Deg); + + +#endif diff --git a/Module/LORA/sx127x.c b/Module/LORA/sx127x.c new file mode 100644 index 0000000..e726f37 --- /dev/null +++ b/Module/LORA/sx127x.c @@ -0,0 +1,613 @@ +#include "sx127x.h" +#include "ddl.h" +#include "Debug.h" +#include "spi.h" +#include "bsp.h" + + +#define LORAChannel 8 +#define LORARegPreamble 10 + +#if (LORA_MODULE == SX1278W1) +Sx1276Type_t LoRaPara = { + .ucChannel = LORAChannel, //4 or 12 + .dwFreqHz = FREQ_CENT, + .ucPower = 20, + .SignalBw = SX1276_BW_250K, + .SpreadFactor = SX1276_SF_512, + .ErrorCoding = SX1276_EC_4_6, + .RegPreamble = LORARegPreamble,//10 or 16 + .ucOpModePrev = RFLR_OPMODE_STANDBY, + .bAntSwPrev = RF_ANT_RECEIVER, + .RegBuff = 0, + .State = SX1276_IDLE, + .ucRxPacketSize = 0, + .ucTxPacketSize = 0, + .RxCallBack = NULL, +}; + +void LoraReset(void) +{ + LORA_RESET_CLR(); + delay_ms(1); + LORA_RESET_SET(); +} + +///////////////////////////////////////////////// +void SX1276SetAntSw(Sx1276AntStatus_m Status) +{ + switch(Status){ + case RF_ANT_TRANSMITTER: + LORA_ANTTXEN(); + break; + case RF_ANT_RECEIVER: + LORA_ANTRXEN(); + break; + case RF_ANT_CLOSE: + LORA_ANTCLOSE(); + break; + } +} + +void SX1276ReadBuffer(uint8_t ucAddr, uint8_t *pucBuff, uint8_t ucLen) +{ + uint8_t ucCnt; + LORA_SPI_NSS_CLR(); + LORA_SPI_READ_WRITE(ucAddr & 0x7F); + for( ucCnt = 0; ucCnt < ucLen; ucCnt++ ){ + pucBuff[ucCnt] = LORA_SPI_READ_WRITE(0); + } + LORA_SPI_NSS_SET(); +} + +void SX1276WriteBuffer(uint8_t ucAddr, uint8_t *pucBuff, uint8_t ucLen) +{ + uint8_t ucCnt; + LORA_SPI_NSS_CLR(); + LORA_SPI_READ_WRITE(ucAddr | 0x80); + for( ucCnt = 0; ucCnt < ucLen; ucCnt++ ){ + LORA_SPI_READ_WRITE(pucBuff[ucCnt]); + } + LORA_SPI_NSS_SET(); +} +void SX1276Write(uint8_t ucAddr, uint8_t ucData) +{ + SX1276WriteBuffer(ucAddr, &ucData, 1); +} + +void SX1276Read(uint8_t ucAddr, uint8_t * pucData) +{ + SX1276ReadBuffer(ucAddr, pucData, 1); +} + +void SX1276WriteFifo(uint8_t *pucBuff, uint8_t ucLen) +{ + SX1276WriteBuffer(0, pucBuff, ucLen); +} + +void SX1276ReadFifo(uint8_t *pucBuff, uint8_t ucLen) +{ + SX1276ReadBuffer(0, pucBuff, ucLen); +} + +///////////////////////////////////////////////// +void SX1276LoRaSetNbTrigPeaks(uint8_t ucValue) +{ + SX1276Read(0x31, &(LoRaPara.RegBuff.RegTestReserved31)); + LoRaPara.RegBuff.RegTestReserved31 = (LoRaPara.RegBuff.RegTestReserved31 & 0xF8) | ucValue; + SX1276Write(0x31, LoRaPara.RegBuff.RegTestReserved31 ); +} + +void SX1276LoRaSetSignalBandwidth(Sx1276BwType Bw) +{ + SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1)); + LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_BW_MASK) | Bw; + SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1); + LoRaPara.SignalBw = Bw; +} + +void SX1276LoRaSetSpreadingFactor(Sx1276SpreadFactorType Factor) +{ + if (Factor > SX1276_SF_4096){ + Factor = SX1276_SF_4096; + } + else if (Factor < SX1276_SF_64){ + Factor = SX1276_SF_64; + } + if (Factor == SX1276_SF_64){ + SX1276LoRaSetNbTrigPeaks(5); + } + else{ + SX1276LoRaSetNbTrigPeaks(3); + } + SX1276Read(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2)); + LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SF_MASK ) | Factor; + SX1276Write(REG_LR_MODEMCONFIG2, LoRaPara.RegBuff.RegModemConfig2); + LoRaPara.SpreadFactor = Factor; +} + +void SX1276LoRaSetErrorCoding(Sx1276ErrorCodingType Value){ + SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1)); + LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_CODINGRATE_MASK ) | Value; + SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1 ); + LoRaPara.ErrorCoding = Value; +} + +void SX1276LoRaSetFreqHz(uint32_t dwFreqHz) +{ + LoRaPara.dwFreqHz = dwFreqHz; + dwFreqHz = ( uint32_t )( ( double )dwFreqHz / ( double )FREQ_STEP ); + LoRaPara.RegBuff.RegFrfMsb = ( uint8_t )( ( dwFreqHz >> 16 ) & 0xFF ); + LoRaPara.RegBuff.RegFrfMid = ( uint8_t )( ( dwFreqHz >> 8 ) & 0xFF ); + LoRaPara.RegBuff.RegFrfLsb = ( uint8_t )( dwFreqHz & 0xFF ); + SX1276WriteBuffer(REG_LR_FRFMSB, &(LoRaPara.RegBuff.RegFrfMsb), 3); +} + +void SX1276LoRaSetSymbTimeout(uint16_t ucValue) +{ + SX1276ReadBuffer(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2), 2); + LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK) | (( ucValue >> 8) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ); + LoRaPara.RegBuff.RegSymbTimeoutLsb = ucValue & 0xFF; + SX1276WriteBuffer(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2), 2); +} + +void SX1276LoRaSetLowDatarateOptimize(boolean_t bEnable) +{ + SX1276Read(REG_LR_MODEMCONFIG3, &(LoRaPara.RegBuff.RegModemConfig3)); + LoRaPara.RegBuff.RegModemConfig3 = (LoRaPara.RegBuff.RegModemConfig3 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) | ( bEnable << 3 ); + SX1276Write(REG_LR_MODEMCONFIG3, LoRaPara.RegBuff.RegModemConfig3); +} + +void SX1276LoRaSetPAOutput(uint8_t ucOutputPin) +{ + SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig)); + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_MASK ) | ucOutputPin; + SX1276Write(REG_LR_PACONFIG, LoRaPara.RegBuff.RegPaConfig ); +} + +void SX1276LoRaSetPa20dBm(boolean_t bEnable) +{ + SX1276Read(REG_LR_PADAC, &(LoRaPara.RegBuff.RegPaDac)); + SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig)); + if ((LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST ) { + if( bEnable == TRUE ){ + LoRaPara.RegBuff.RegPaDac = 0x87; + } + } + else{ + LoRaPara.RegBuff.RegPaDac = 0x84; + } + SX1276Write(REG_LR_PADAC, LoRaPara.RegBuff.RegPaDac ); +} + +void SX1276LoRaSetRfPower(int8_t sbPower) +{ + SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig)); + SX1276Read(REG_LR_PADAC, &(LoRaPara.RegBuff.RegPaDac)); + if ((LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST ) { + if ((LoRaPara.RegBuff.RegPaDac & 0x87) == 0x87){ + if( sbPower < 5 ){ + sbPower = 5; + } + if( sbPower > 20){ + sbPower = 20; + } + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70; + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | + ( uint8_t )( ( uint16_t )( sbPower - 5 ) & 0x0F ); + } + else{ + if( sbPower < 2){ + sbPower = 2; + } + if( sbPower > 17){ + sbPower = 17; + } + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70; + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | + ( uint8_t )( ( uint16_t )( sbPower - 2 ) & 0x0F ); + } + } + else{ + if( sbPower < -1){ + sbPower = -1; + } + if( sbPower > 14){ + sbPower = 14; + } + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70; + LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | + ( uint8_t )( ( uint16_t )( sbPower + 1 ) & 0x0F ); + } + SX1276Write(REG_LR_PACONFIG, LoRaPara.RegBuff.RegPaConfig); + LoRaPara.ucPower = sbPower; +} + +void SX1276LoRaSetOpMode(Sx1276OpModeType ucOpMode) +{ + Sx1276AntStatus_m bAntSwStatus = RF_ANT_RECEIVER; + LoRaPara.ucOpModePrev = LoRaPara.RegBuff.RegOpMode & ~RFLR_OPMODE_MASK; + if( ucOpMode != LoRaPara.ucOpModePrev){ + if(ucOpMode == RFLR_OPMODE_TRANSMITTER){ + + //CLR_LORA_RXEN(); + //SET_LORA_TXEN(); + + + bAntSwStatus = RF_ANT_TRANSMITTER; + } + else if(ucOpMode == RFLR_OPMODE_RECEIVER){ + bAntSwStatus = RF_ANT_RECEIVER; + + //CLR_LORA_TXEN(); + //SET_LORA_RXEN(); + } + else { + bAntSwStatus = RF_ANT_CLOSE; + } + if( bAntSwStatus != LoRaPara.bAntSwPrev ){ + LoRaPara.bAntSwPrev = bAntSwStatus; + SX1276SetAntSw(bAntSwStatus); + } + LoRaPara.RegBuff.RegOpMode = (LoRaPara.RegBuff.RegOpMode & RFLR_OPMODE_MASK ) | ucOpMode; + SX1276Write( REG_LR_OPMODE, LoRaPara.RegBuff.RegOpMode); + } +} +//////////////////////////////////////////////////////////////// + +void Sx1276LoRaEnterRx(void) +{ + uint8_t ucCnt; + SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY); + LoRaPara.RegBuff.RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | RFLR_IRQFLAGS_VALIDHEADER | RFLR_IRQFLAGS_TXDONE; + SX1276Write(REG_LR_IRQFLAGSMASK, LoRaPara.RegBuff.RegIrqFlagsMask); + LoRaPara.RegBuff.RegHopPeriod = 255; + SX1276Write(REG_LR_HOPPERIOD, LoRaPara.RegBuff.RegHopPeriod ); + // RxDone RxTimeout FhssChangeChannel ValidHeader + LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_01 | RFLR_DIOMAPPING1_DIO3_01; + // CadDetected ModeReady + LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00; + SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2); + LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoRxBaseAddr; + SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr); + SX1276LoRaSetOpMode(RFLR_OPMODE_RECEIVER); + for (ucCnt=0; ucCnt< LORA_BUFF_SIZE; ucCnt++){ + LoRaPara.RxTxBuff[ucCnt] = 0; + } + LoRaPara.State = SX1276_IDLE;//COMST_RX + uint8_t temp; + SX1276Read(REG_LR_IRQFLAGS, &temp); + + //设置接收模式 + LORA_ANTRXEN(); +} + +///////////////////////////////////////////////// +void Sx1276LoRaInit(void (*RxCallBack)(uint8_t *rBuff, uint8_t rlen)) +{ + if(RxCallBack != NULL) { + LoRaPara.RxCallBack = RxCallBack; + } + LoraReset(); + SX1276LoRaSetOpMode(RFLR_OPMODE_SLEEP); + LoRaPara.RegBuff.RegOpMode = (LoRaPara.RegBuff.RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON; + SX1276Write(REG_LR_OPMODE, LoRaPara.RegBuff.RegOpMode ); + SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY); + // RxDone RxTimeout FhssChangeChannel ValidHeader + LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_01; + // CadDetected ModeReady + LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00; + SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2 ); + SX1276ReadBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS); + LoRaPara.State = SX1276_BUSY; + SX1276Read(REG_LR_VERSION, &(LoRaPara.RegBuff.RegVersion)); + SX1276ReadBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS); + LoRaPara.RegBuff.RegLna = RFLR_LNA_GAIN_G1; + SX1276WriteBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS); + //set the RF settings + SX1276LoRaWriteChannel(LoRaPara.ucChannel); + //SX1276LoRaSetFreqHz(LoRaPara.dwFreqHz); + //REG_LR_MODEMCONFIG1 + SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1)); + //SignalBandwidth + LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_BW_MASK ) | LoRaPara.SignalBw; + //ErrorCoding + LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_CODINGRATE_MASK ) | LoRaPara.ErrorCoding; + //IMPLICITHEADER + LoRaPara.RegBuff.RegModemConfig1 = LoRaPara.RegBuff.RegModemConfig1 | RFLR_MODEMCONFIG1_IMPLICITHEADER_ON; + SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1); + //REG_LR_MODEMCONFIG2 + SX1276Read(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2)); + //SpreadingFactor + if( LoRaPara.SpreadFactor == SX1276_SF_64){ + SX1276LoRaSetNbTrigPeaks(5); + SX1276LoRaSetLowDatarateOptimize(TRUE); //低数据速率设置 + } + else{ + SX1276LoRaSetNbTrigPeaks(3); + SX1276LoRaSetLowDatarateOptimize(FALSE); //低数据速率设置 + } + LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SF_MASK ) | LoRaPara.SpreadFactor; + //PacketCrcOn + LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) | SX1276_CRC_ON; //SX1276_CRC_OFF + + //验证寄存器操作是否成功 + SX1276Write(REG_LR_MODEMCONFIG2, LoRaPara.RegBuff.RegModemConfig2); + LoRaPara.RegBuff.RegModemConfig2 = 0; + SX1276Read(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2)); + + SX1276LoRaSetSymbTimeout(0x3FF); + LoRaPara.RegBuff.RegPreambleMsb= (LoRaPara.RegPreamble >> 8) & 0x00ff; + LoRaPara.RegBuff.RegPreambleLsb= LoRaPara.RegPreamble & 0x00ff; + SX1276Write(REG_LR_PREAMBLEMSB, LoRaPara.RegBuff.RegPreambleMsb); + SX1276Write(REG_LR_PREAMBLELSB, LoRaPara.RegBuff.RegPreambleLsb); + SX1276Write(REG_LR_PAYLOADLENGTH, LORA_BUFF_SIZE); + SX1276Write(REG_LR_PAYLOADMAXLENGTH, LORA_BUFF_SIZE); + LoRaPara.RegBuff.RegPayloadLength = LORA_BUFF_SIZE; + + #ifndef USE_LORA_860_PA + if(LoRaPara.dwFreqHz > 860000000 ){ + SX1276LoRaSetPAOutput(RFLR_PACONFIG_PASELECT_RFO); + SX1276LoRaSetPa20dBm(FALSE); + LoRaPara.ucPower = 14; + } + else + #endif + { + SX1276LoRaSetPAOutput(RFLR_PACONFIG_PASELECT_PABOOST); + SX1276LoRaSetPa20dBm(TRUE); + LoRaPara.ucPower = 20; + } + SX1276LoRaSetRfPower(LoRaPara.ucPower); + SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY); + Sx1276LoRaEnterRx(); +} + +void IsrSx1276LoRaTxRx(void){ + switch (LoRaPara.State){ + case SX1276_IDLE: + case SX1276_RX: + // Clear Irq + //SET_LORA_RX_LED(); + do { + SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE); + SX1276Read(REG_LR_IRQFLAGS, &(LoRaPara.RegBuff.RegIrqFlags)); + if((LoRaPara.RegBuff.RegIrqFlags & RFLR_IRQFLAGS_RXDONE) != RFLR_IRQFLAGS_RXDONE) + break; + }while(1); + if((LoRaPara.RegBuff.RegIrqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR ) == RFLR_IRQFLAGS_PAYLOADCRCERROR) { + // Clear Irq + SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR); + LoRaPara.State = SX1276_IDLE; + break; + } + SX1276Read(REG_LR_PKTSNRVALUE, &(LoRaPara.RegBuff.RegPktSnrValue)); + SX1276Read(REG_LR_RSSIVALUE, &(LoRaPara.RegBuff.RegRssiValue)); + SX1276Read(REG_LR_PKTRSSIVALUE, &(LoRaPara.RegBuff.RegPktRssiValue)); + SX1276Read(REG_LR_FIFORXCURRENTADDR, &(LoRaPara.RegBuff.RegFifoRxCurrentAddr)); + SX1276Read(REG_LR_NBRXBYTES, &(LoRaPara.RegBuff.RegNbRxBytes)); + LoRaPara.ucRxPacketSize = LoRaPara.RegBuff.RegNbRxBytes; + LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoRxCurrentAddr; + SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr); + SX1276ReadFifo(LoRaPara.RxTxBuff, (LoRaPara.ucRxPacketSize > LORA_BUFF_SIZE) ? LORA_BUFF_SIZE : LoRaPara.ucRxPacketSize); + uint8_t ucLen; + if(LoRaPara.ucRxPacketSize < LORA_BUFF_SIZE) { + ucLen= LoRaPara.ucRxPacketSize; + } + else { + ucLen= LORA_BUFF_SIZE; + } + LoRaPara.RxTxBuff[ucLen] = 0; + if(LoRaPara.RxCallBack != NULL) + LoRaPara.RxCallBack(LoRaPara.RxTxBuff, ucLen); + + LoRaPara.ucRxPacketSize = 0; + LoRaPara.State = SX1276_IDLE; + //CLR_LORA_RX_LED(); + break; + case SX1276_TX: + // Clear Irq + SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE); + //LORA_TXLED_OFF(); + Sx1276LoRaEnterRx(); + break; + default: + break; + } +} + +void Sx1276LoRaLoopHandler(void) +{ + if(LORA_GETDIO0() > 0){ // RxDone or TxDone + IsrSx1276LoRaTxRx(); + } +} +void Sx1276LoRaSendBuffer(uint8_t* pucBuff, uint8_t ucLen) +{ + + //设置发送模式 + LORA_ANTTXEN(); + + LoRaPara.State = SX1276_BUSY; + if (ucLen > LORA_BUFF_SIZE){ + ucLen = LORA_BUFF_SIZE; + } + LoRaPara.ucTxPacketSize = ucLen; + while(ucLen--){ + LoRaPara.RxTxBuff[ucLen] = pucBuff[ucLen]; + }; + SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY); + LoRaPara.RegBuff.RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | RFLR_IRQFLAGS_RXDONE | RFLR_IRQFLAGS_PAYLOADCRCERROR | RFLR_IRQFLAGS_VALIDHEADER; + //LoRaPara.RegBuff.RegHopPeriod = 0; + //SX1276Write(REG_LR_HOPPERIOD, LoRaPara.RegBuff.RegHopPeriod); + SX1276Write(REG_LR_IRQFLAGSMASK, LoRaPara.RegBuff.RegIrqFlagsMask); + // Initializes the payload size + LoRaPara.RegBuff.RegPayloadLength = LoRaPara.ucTxPacketSize; + SX1276Write(REG_LR_PAYLOADLENGTH, LoRaPara.RegBuff.RegPayloadLength); + LoRaPara.RegBuff.RegFifoTxBaseAddr = 0x00; // Full buffer used for Tx + SX1276Write(REG_LR_FIFOTXBASEADDR, LoRaPara.RegBuff.RegFifoTxBaseAddr); + LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoTxBaseAddr; + SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr); + // Write payload buffer to LORA modem + SX1276WriteFifo(LoRaPara.RxTxBuff, LoRaPara.RegBuff.RegPayloadLength); + // TxDone RxTimeout FhssChangeChannel ValidHeader + LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_01; + // PllLock Mode Ready + LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_01 | RFLR_DIOMAPPING2_DIO5_00; + SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2); + SX1276LoRaSetOpMode(RFLR_OPMODE_TRANSMITTER); + uint8_t temp; + SX1276Read(REG_LR_IRQFLAGS, &temp); + //LORA_TXLED_ON(); + LoRaPara.State = SX1276_TX; +} + +void Sx1276LoRaSleep(void) +{ + SX1276LoRaSetOpMode(RFLR_OPMODE_SLEEP);//RFLR_OPMODE_STANDBY +} + +void Sx1276LoRaWakeup(void) +{ + Sx1276LoRaEnterRx(); +} + +//////////////////////////////////////// +//配置本层参数的函数 +//频道表 +const uint32_t gdwSx1276ChannelTbl[SX1276_CHANNEL_MAX]={ + FREQ_CENT-FREQ_DEV*8, FREQ_CENT-FREQ_DEV*7, FREQ_CENT-FREQ_DEV*6, FREQ_CENT-FREQ_DEV*5, + FREQ_CENT-FREQ_DEV*4, FREQ_CENT-FREQ_DEV*3, FREQ_CENT-FREQ_DEV*2, FREQ_CENT-FREQ_DEV*1, + FREQ_CENT+FREQ_DEV*0, FREQ_CENT+FREQ_DEV*1, FREQ_CENT+FREQ_DEV*2, FREQ_CENT+FREQ_DEV*3, + FREQ_CENT+FREQ_DEV*4, FREQ_CENT+FREQ_DEV*5, FREQ_CENT+FREQ_DEV*6, FREQ_CENT+FREQ_DEV*7, + FREQ_CENT+FREQ_DEV*8 +}; + +//LORAPT_CHANNEL +uint8_t SX1276LoRaReadChannel(void) +{ + return LoRaPara.ucChannel; +} + +boolean_t SX1276LoRaWriteChannel(uint8_t Channel) +{ + if(Channel > SX1276_CHANNEL_MAX) { + return FALSE; + } + + LoRaPara.dwFreqHz = gdwSx1276ChannelTbl[Channel]; + SX1276LoRaSetFreqHz(LoRaPara.dwFreqHz); + + return TRUE; +} + +//LORAPT_FREQ, +uint32_t SX1276LoRaReadFreq(void) +{ + return LoRaPara.dwFreqHz; +} + +void SX1276LoRaWriteFreq(uint32_t Freq) +{ + SX1276LoRaSetFreqHz(Freq); +} + +//LORAPT_BW, +uint32_t SX1276LoRaReadBw(void) +{ + return LoRaPara.SignalBw; +} + +void SX1276LoRaWriteBw(Sx1276BwType SignalBw) +{ + LoRaPara.SignalBw = SignalBw; + SX1276LoRaSetSignalBandwidth(SignalBw); +} + +//LORAPT_SF, +uint8_t SX1276LoRaReadSf(void) +{ + return LoRaPara.SpreadFactor; +} + +void SX1276LoRaWriteSf(Sx1276SpreadFactorType SpreadFactor) +{ + LoRaPara.SpreadFactor = SpreadFactor; + SX1276LoRaSetSpreadingFactor(LoRaPara.SpreadFactor); +} + +//LORAPT_EC, +uint8_t SX1276LoRaReadEc(void) +{ + return LoRaPara.ErrorCoding; +} + +void SX1276LoRaWriteEc(Sx1276ErrorCodingType ErrorCoding) +{ + LoRaPara.ErrorCoding = ErrorCoding; + SX1276LoRaSetErrorCoding(ErrorCoding); +} + +//LORAPT_RSSI, +uint32_t SX1276LoRaParaReadRssi(void) +{ + uint32_t rssi; + + SX1276Read(REG_LR_PKTRSSIVALUE, &(LoRaPara.RegBuff.RegPktRssiValue)); + SX1276Read(REG_LR_RSSIVALUE, &(LoRaPara.RegBuff.RegRssiValue)); + rssi = (uint16_t)(LoRaPara.RegBuff.RegPktSnrValue)<<16; + rssi |= (uint16_t)(LoRaPara.RegBuff.RegRssiValue)<<8; + rssi |= LoRaPara.RegBuff.RegPktRssiValue; + return rssi; +} + +uint8_t SX1276LoRaReadRssiPkt(void) +{ + uint8_t RssiPkt; + + SX1276Read(REG_LR_PKTRSSIVALUE, &LoRaPara.RegBuff.RegPktRssiValue); + RssiPkt = LoRaPara.RegBuff.RegPktRssiValue; + return RssiPkt; +} + +//LORAPT_POWER, +void SX1276LoRaWritePwr(int8_t Pwr) +{ + SX1276LoRaSetRfPower(Pwr); +} + +//LORAPT_SET_RX, +void SX1276LoRaWriteRx(void) +{ + Sx1276LoRaEnterRx(); +} + +//LORAPT_SET_SLEEP,true-Sleep, false-Wakeup +void SX1276LoRaWriteSleep(boolean_t Sleep) +{ + if(Sleep){ + Sx1276LoRaSleep(); + } + else { + Sx1276LoRaWakeup(); + } +} + +Sx1276StateType_t SX1276LoRaReadStatus(void) +{ + return LoRaPara.State; +} + +///////////////RSSI Calc/////////////// +void SX1276LoCalcRssiSnr(int8_t *pswRssi, int8_t *psbSnr) +{ + int8_t sbSnr= LoRaPara.RegBuff.RegPktSnrValue & 0x80 ? (-1)*((int8_t)(((~LoRaPara.RegBuff.RegPktSnrValue+ 1)& 0xFF)/4)): (~LoRaPara.RegBuff.RegPktSnrValue& 0xFF)/4; + if (sbSnr > 0) { + *pswRssi= RSSI_OFFSET_LF+ LoRaPara.RegBuff.RegPktRssiValue; + } + else { + *pswRssi= NOISE_ABSOLUTE_ZERO + 10 + SIGNAL_BW_LOG_125KHZ + NOISE_FIGURE_LF + sbSnr; + } + *psbSnr= sbSnr; +} +#endif diff --git a/Module/LORA/sx127x.h b/Module/LORA/sx127x.h new file mode 100644 index 0000000..e977a1a --- /dev/null +++ b/Module/LORA/sx127x.h @@ -0,0 +1,826 @@ +#ifndef __SX127X_H +#define __SX127X_H + +#include "bsp.h" + +//Constant values need to compute the RSSI value +#define RSSI_OFFSET_LF -155 +#define RSSI_OFFSET_HF -150 +#define NOISE_ABSOLUTE_ZERO -174 +#define NOISE_FIGURE_LF 4 +#define NOISE_FIGURE_HF 6 +#define SIGNAL_BW_LOG_125KHZ 5 + +//SX1276 definitions +#define XTAL_FREQ 32000000 +#define FREQ_STEP 61.03515625 + +//SX1276 Internal registers Address +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +#define REG_LR_BANDSETTING 0x04 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_NBRXBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_MODEMCONFIG3 0x26 +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_PLLHOP 0x44 +#define REG_LR_TCXO 0x4B +#define REG_LR_PADAC 0x4D +#define REG_LR_FORMERTEMP 0x5B +#define REG_LR_BITRATEFRAC 0x5D +#define REG_LR_AGCREF 0x61 +#define REG_LR_AGCTHRESH1 0x62 +#define REG_LR_AGCTHRESH2 0x63 +#define REG_LR_AGCTHRESH3 0x64 + +//RegOpMode +typedef enum{ + RFLR_OPMODE_LONGRANGEMODE_MASK =0x7F, + RFLR_OPMODE_LONGRANGEMODE_OFF =0x00, // Default + RFLR_OPMODE_LONGRANGEMODE_ON =0x80, + RFLR_OPMODE_ACCESSSHAREDREG_MASK =0xBF, + RFLR_OPMODE_ACCESSSHAREDREG_ENABLE =0x40, + RFLR_OPMODE_ACCESSSHAREDREG_DISABLE =0x00, // Default + RFLR_OPMODE_FREQMODE_ACCESS_MASK =0xF7, + RFLR_OPMODE_FREQMODE_ACCESS_LF =0x08, // Default + RFLR_OPMODE_FREQMODE_ACCESS_HF =0x00, + RFLR_OPMODE_MASK =0xF8, + RFLR_OPMODE_SLEEP =0x00, + RFLR_OPMODE_STANDBY =0x01, // Default + RFLR_OPMODE_SYNTHESIZER_TX =0x02, + RFLR_OPMODE_TRANSMITTER =0x03, + RFLR_OPMODE_SYNTHESIZER_RX =0x04, + RFLR_OPMODE_RECEIVER =0x05, + // LoRa specific modes + RFLR_OPMODE_RECEIVER_SINGLE =0x06, + RFLR_OPMODE_CAD =0x07 +}Sx1276OpModeType; + +//RegBandSetting +#define RFLR_BANDSETTING_MASK 0x3F +#define RFLR_BANDSETTING_AUTO 0x00 // Default +#define RFLR_BANDSETTING_DIV_BY_1 0x40 +#define RFLR_BANDSETTING_DIV_BY_2 0x80 +#define RFLR_BANDSETTING_DIV_BY_6 0xC0 + +//RegFrf (MHz) +#define RFLR_FRFMSB_434_MHZ 0x6C // Default +#define RFLR_FRFMID_434_MHZ 0x80 // Default +#define RFLR_FRFLSB_434_MHZ 0x00 // Default +#define RFLR_FRFMSB_863_MHZ 0xD7 +#define RFLR_FRFMID_863_MHZ 0xC0 +#define RFLR_FRFLSB_863_MHZ 0x00 +#define RFLR_FRFMSB_864_MHZ 0xD8 +#define RFLR_FRFMID_864_MHZ 0x00 +#define RFLR_FRFLSB_864_MHZ 0x00 +#define RFLR_FRFMSB_865_MHZ 0xD8 +#define RFLR_FRFMID_865_MHZ 0x40 +#define RFLR_FRFLSB_865_MHZ 0x00 +#define RFLR_FRFMSB_866_MHZ 0xD8 +#define RFLR_FRFMID_866_MHZ 0x80 +#define RFLR_FRFLSB_866_MHZ 0x00 +#define RFLR_FRFMSB_867_MHZ 0xD8 +#define RFLR_FRFMID_867_MHZ 0xC0 +#define RFLR_FRFLSB_867_MHZ 0x00 +#define RFLR_FRFMSB_868_MHZ 0xD9 +#define RFLR_FRFMID_868_MHZ 0x00 +#define RFLR_FRFLSB_868_MHZ 0x00 +#define RFLR_FRFMSB_869_MHZ 0xD9 +#define RFLR_FRFMID_869_MHZ 0x40 +#define RFLR_FRFLSB_869_MHZ 0x00 +#define RFLR_FRFMSB_870_MHZ 0xD9 +#define RFLR_FRFMID_870_MHZ 0x80 +#define RFLR_FRFLSB_870_MHZ 0x00 +#define RFLR_FRFMSB_902_MHZ 0xE1 +#define RFLR_FRFMID_902_MHZ 0x80 +#define RFLR_FRFLSB_902_MHZ 0x00 +#define RFLR_FRFMSB_903_MHZ 0xE1 +#define RFLR_FRFMID_903_MHZ 0xC0 +#define RFLR_FRFLSB_903_MHZ 0x00 +#define RFLR_FRFMSB_904_MHZ 0xE2 +#define RFLR_FRFMID_904_MHZ 0x00 +#define RFLR_FRFLSB_904_MHZ 0x00 +#define RFLR_FRFMSB_905_MHZ 0xE2 +#define RFLR_FRFMID_905_MHZ 0x40 +#define RFLR_FRFLSB_905_MHZ 0x00 +#define RFLR_FRFMSB_906_MHZ 0xE2 +#define RFLR_FRFMID_906_MHZ 0x80 +#define RFLR_FRFLSB_906_MHZ 0x00 +#define RFLR_FRFMSB_907_MHZ 0xE2 +#define RFLR_FRFMID_907_MHZ 0xC0 +#define RFLR_FRFLSB_907_MHZ 0x00 +#define RFLR_FRFMSB_908_MHZ 0xE3 +#define RFLR_FRFMID_908_MHZ 0x00 +#define RFLR_FRFLSB_908_MHZ 0x00 +#define RFLR_FRFMSB_909_MHZ 0xE3 +#define RFLR_FRFMID_909_MHZ 0x40 +#define RFLR_FRFLSB_909_MHZ 0x00 +#define RFLR_FRFMSB_910_MHZ 0xE3 +#define RFLR_FRFMID_910_MHZ 0x80 +#define RFLR_FRFLSB_910_MHZ 0x00 +#define RFLR_FRFMSB_911_MHZ 0xE3 +#define RFLR_FRFMID_911_MHZ 0xC0 +#define RFLR_FRFLSB_911_MHZ 0x00 +#define RFLR_FRFMSB_912_MHZ 0xE4 +#define RFLR_FRFMID_912_MHZ 0x00 +#define RFLR_FRFLSB_912_MHZ 0x00 +#define RFLR_FRFMSB_913_MHZ 0xE4 +#define RFLR_FRFMID_913_MHZ 0x40 +#define RFLR_FRFLSB_913_MHZ 0x00 +#define RFLR_FRFMSB_914_MHZ 0xE4 +#define RFLR_FRFMID_914_MHZ 0x80 +#define RFLR_FRFLSB_914_MHZ 0x00 +#define RFLR_FRFMSB_915_MHZ 0xE4 // Default +#define RFLR_FRFMID_915_MHZ 0xC0 // Default +#define RFLR_FRFLSB_915_MHZ 0x00 // Default +#define RFLR_FRFMSB_916_MHZ 0xE5 +#define RFLR_FRFMID_916_MHZ 0x00 +#define RFLR_FRFLSB_916_MHZ 0x00 +#define RFLR_FRFMSB_917_MHZ 0xE5 +#define RFLR_FRFMID_917_MHZ 0x40 +#define RFLR_FRFLSB_917_MHZ 0x00 +#define RFLR_FRFMSB_918_MHZ 0xE5 +#define RFLR_FRFMID_918_MHZ 0x80 +#define RFLR_FRFLSB_918_MHZ 0x00 +#define RFLR_FRFMSB_919_MHZ 0xE5 +#define RFLR_FRFMID_919_MHZ 0xC0 +#define RFLR_FRFLSB_919_MHZ 0x00 +#define RFLR_FRFMSB_920_MHZ 0xE6 +#define RFLR_FRFMID_920_MHZ 0x00 +#define RFLR_FRFLSB_920_MHZ 0x00 +#define RFLR_FRFMSB_921_MHZ 0xE6 +#define RFLR_FRFMID_921_MHZ 0x40 +#define RFLR_FRFLSB_921_MHZ 0x00 +#define RFLR_FRFMSB_922_MHZ 0xE6 +#define RFLR_FRFMID_922_MHZ 0x80 +#define RFLR_FRFLSB_922_MHZ 0x00 +#define RFLR_FRFMSB_923_MHZ 0xE6 +#define RFLR_FRFMID_923_MHZ 0xC0 +#define RFLR_FRFLSB_923_MHZ 0x00 +#define RFLR_FRFMSB_924_MHZ 0xE7 +#define RFLR_FRFMID_924_MHZ 0x00 +#define RFLR_FRFLSB_924_MHZ 0x00 +#define RFLR_FRFMSB_925_MHZ 0xE7 +#define RFLR_FRFMID_925_MHZ 0x40 +#define RFLR_FRFLSB_925_MHZ 0x00 +#define RFLR_FRFMSB_926_MHZ 0xE7 +#define RFLR_FRFMID_926_MHZ 0x80 +#define RFLR_FRFLSB_926_MHZ 0x00 +#define RFLR_FRFMSB_927_MHZ 0xE7 +#define RFLR_FRFMID_927_MHZ 0xC0 +#define RFLR_FRFLSB_927_MHZ 0x00 +#define RFLR_FRFMSB_928_MHZ 0xE8 +#define RFLR_FRFMID_928_MHZ 0x00 +#define RFLR_FRFLSB_928_MHZ 0x00 + +//RegPaConfig +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default +#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +//RegPaRamp +#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF +#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 +#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +//RegOcp +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +//RegLna +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 +#define RFLR_LNA_BOOST_LF_MASK 0xE7 +#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default +#define RFLR_LNA_BOOST_LF_GAIN 0x08 +#define RFLR_LNA_BOOST_LF_IP3 0x10 +#define RFLR_LNA_BOOST_LF_BOOST 0x18 +#define RFLR_LNA_RXBANDFORCE_MASK 0xFB +#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04 +#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default +#define RFLR_LNA_BOOST_HF_MASK 0xFC +#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default +#define RFLR_LNA_BOOST_HF_ON 0x03 + +//RegFifoAddrPtr +#define RFLR_FIFOADDRPTR 0x00 // Default + +//RegFifoTxBaseAddr +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +//RegFifoTxBaseAddr +#define RFLR_FIFORXBASEADDR 0x00 // Default + +//RegFifoRxCurrentAddr (Read Only) + +//RegIrqFlagsMask +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +//RegIrqFlags +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + + //RegModemStat (Read Only) +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +//RegModemConfig1 +#define RFLR_MODEMCONFIG1_BW_MASK 0x0F +#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 +#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 +#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 +#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 +#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 +#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x00 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x01 // Default + + //RegModemConfig2 +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 + +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 + +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + + +//RegHopChannel (Read Only) +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40 +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + + +//RegSymbTimeoutLsb +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +//RegPreambleLengthMsb +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +//RegPreambleLengthLsb +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +//RegPayloadLength +#define RFLR_PAYLOADLENGTH 0x0E // Default + +//RegPayloadMaxLength +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +//RegHopPeriod +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + + +//RegDioMapping1 +//DIO0 +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 +//DIO1 +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 +//DIO2 +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C +//DIO3 +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +//RegDioMapping2 +//DIO4 +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 +//DIO5 +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 +//MAP +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +// RegPllHop +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +//RegTcxo +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +//RegPaDac +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +//RegPll +#define RFLR_PLL_BANDWIDTH_MASK 0x3F +#define RFLR_PLL_BANDWIDTH_75 0x00 +#define RFLR_PLL_BANDWIDTH_150 0x40 +#define RFLR_PLL_BANDWIDTH_225 0x80 +#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default + +//RegPllLowPn +#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 +#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 +#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 +#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +//RegModemConfig3 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 + +//REGISTER +typedef struct _Sx1276RegType{ + uint8_t RegFifo; // 0x00 + // Common settings + uint8_t RegOpMode; // 0x01 + uint8_t RegRes02; // 0x02 + uint8_t RegRes03; // 0x03 + uint8_t RegBandSetting; // 0x04 + uint8_t RegRes05; // 0x05 + uint8_t RegFrfMsb; // 0x06 + uint8_t RegFrfMid; // 0x07 + uint8_t RegFrfLsb; // 0x08 + // Tx settings + uint8_t RegPaConfig; // 0x09 + uint8_t RegPaRamp; // 0x0A + uint8_t RegOcp; // 0x0B + // Rx settings + uint8_t RegLna; // 0x0C + // LoRa registers + uint8_t RegFifoAddrPtr; // 0x0D + uint8_t RegFifoTxBaseAddr; // 0x0E + uint8_t RegFifoRxBaseAddr; // 0x0F + uint8_t RegFifoRxCurrentAddr; // 0x10 + uint8_t RegIrqFlagsMask; // 0x11 + uint8_t RegIrqFlags; // 0x12 + uint8_t RegNbRxBytes; // 0x13 + uint8_t RegRxHeaderCntValueMsb; // 0x14 + uint8_t RegRxHeaderCntValueLsb; // 0x15 + uint8_t RegRxPacketCntValueMsb; // 0x16 + uint8_t RegRxPacketCntValueLsb; // 0x17 + uint8_t RegModemStat; // 0x18 + uint8_t RegPktSnrValue; // 0x19 + uint8_t RegPktRssiValue; // 0x1A + uint8_t RegRssiValue; // 0x1B + uint8_t RegHopChannel; // 0x1C + uint8_t RegModemConfig1; // 0x1D + uint8_t RegModemConfig2; // 0x1E + uint8_t RegSymbTimeoutLsb; // 0x1F + uint8_t RegPreambleMsb; // 0x20 + uint8_t RegPreambleLsb; // 0x21 + uint8_t RegPayloadLength; // 0x22 + uint8_t RegMaxPayloadLength; // 0x23 + uint8_t RegHopPeriod; // 0x24 + uint8_t RegFifoRxByteAddr; // 0x25 + uint8_t RegModemConfig3; // 0x26 + uint8_t RegTestReserved27[0x30 - 0x27]; // 0x27-0x30 + uint8_t RegTestReserved31; // 0x31 + uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x40 + // I/O settings + uint8_t RegDioMapping1; // 0x40 + uint8_t RegDioMapping2; // 0x41 + // Version + uint8_t RegVersion; // 0x42 + // Additional settings + uint8_t RegAgcRef; // 0x43 + uint8_t RegAgcThresh1; // 0x44 + uint8_t RegAgcThresh2; // 0x45 + uint8_t RegAgcThresh3; // 0x46 + // Test + uint8_t RegTestReserved47[0x4B - 0x47]; // 0x47-0x4A + // Additional settings + uint8_t RegPllHop; // 0x4B + uint8_t RegTestReserved4C; // 0x4C + uint8_t RegPaDac; // 0x4D + // Test + //uint8_t RegTestReserved4E[0x58-0x4E]; // 0x4E-0x57 + // Additional settings + //uint8_t RegTcxo; // 0x58 + // Test + //uint8_t RegTestReserved59; // 0x59 + // Test + //uint8_t RegTestReserved5B; // 0x5B + // Additional settings + //uint8_t RegPll; // 0x5C + // Test + //uint8_t RegTestReserved5D; // 0x5D + // Additional settings + //uint8_t RegPllLowPn; // 0x5E + // Test + //uint8_t RegTestReserved5F[0x6C - 0x5F]; // 0x5F-0x6B + // Additional settings + //uint8_t RegFormerTemp; // 0x6C + // Test + //uint8_t RegTestReserved6D[0x71 - 0x6D]; // 0x6D-0x70 +}Sx1276RegType; + +#define SIZE_OF_REGISTERS (sizeof(Sx1276RegType)) + +//RF state machine +typedef enum{ + RFLR_STATE_IDLE, + RFLR_STATE_RX_RUNNING, + RFLR_STATE_TX_RUNNING, +}LRStateType; + +typedef enum{ + RADIO_RESET_OFF, + RADIO_RESET_ON, +}tRadioResetState; + +typedef enum{ + RF_IDLE, + RF_BUSY, + RF_RX_DONE, + RF_RX_TIMEOUT, + RF_TX_DONE, + RF_TX_TIMEOUT, + RF_LEN_ERROR, + RF_CHANNEL_EMPTY, + RF_CHANNEL_ACTIVITY_DETECTED, +}Sx1276RetType; + +typedef enum{ + SX1276_BW_7K8= (0), + SX1276_BW_10K4= (1<<4), + SX1276_BW_15K6= (2<<4), + SX1276_BW_20K8= (3<<4), + SX1276_BW_31K2= (4<<4), + SX1276_BW_41K6= (5<<4), + SX1276_BW_62K5= (6<<4), + SX1276_BW_125K= (7<<4), + SX1276_BW_250K= (8<<4), + SX1276_BW_500K= (9<<4) +}Sx1276BwType; + +typedef enum{ + SX1276_SF_64= (6<<4), + SX1276_SF_128= (7<<4), + SX1276_SF_256= (8<<4), + SX1276_SF_512= (9<<4), + SX1276_SF_1024= (10<<4), + SX1276_SF_2048= (11<<4), + SX1276_SF_4096= (12<<4) +}Sx1276SpreadFactorType; + +typedef enum{ + SX1276_EC_4_5= (1<<1), + SX1276_EC_4_6= (2<<1), + SX1276_EC_4_7= (3<<1), + SX1276_EC_4_8= (4<<1) +}Sx1276ErrorCodingType; + +typedef enum{ + SX1276_CRC_OFF= (0), + SX1276_CRC_ON= (1<<2) +}Sx1276CrcOnType; + +typedef enum{ + SX1276_IH_OFF= (0), + SX1276_IH_ON= (1) +}Sx1276ImplicitHeaderOnType; + +// 杀 +typedef struct _AutoSfType{ + Sx1276SpreadFactorType Sf; + uint8_t ucRssiMin, ucRssiMax; + uint16_t wTimeout; +}AutoSfType, *PAutoSf; + +//Parameter +typedef enum{ + LORAPT_STATUS, + LORAPT_CHANNEL, + LORAPT_FREQ, + LORAPT_BW, + LORAPT_SF, + LORAPT_EC, + LORAPT_RSSI, + LORAPT_POWER, + LORAPT_SET_RX, + LORAPT_SET_SLEEP, + LORAPT_MAX +}Sx1276LoraParaType; + +#define SX1276_CHANNEL_MAX 17 + +#define LORA_RESET_SET() SET_LORA_RST() +#define LORA_RESET_CLR() CLR_LORA_RST() +#define LORA_SPI_NSS_SET() Spi_SetCS(M0P_SPI0, TRUE) //鍙栨秷鐗囬 +#define LORA_SPI_NSS_CLR() Spi_SetCS(M0P_SPI0, FALSE) //浣胯兘鍣ㄤ欢 +#define LORA_SPI_READ_WRITE(x) Spi0SendReceive(x) +#define LORA_GETDIO0() GET_LORA_DIO0() +#define LORA_GETDIO1() GET_LORA_DIO1() + +#define USE_RF_SW 0 +#define USE_LORA_LED 0 +#if USE_RF_SW == 1 +#define LORA_ANTTXEN() { \ + SET_LORA_TXEN();\ + CLR_LORA_RXEN();\ + } + +#define LORA_ANTRXEN() { \ + SET_LORA_RXEN();\ + CLR_LORA_TXEN();\ + } + +#define LORA_ANTCLOSE() { \ + CLR_LORA_RXEN();\ + CLR_LORA_TXEN();\ + } +#else +#define LORA_ANTTXEN() +#define LORA_ANTRXEN() +#define LORA_ANTCLOSE() +#endif + +#if USE_LORA_LED == 1 +#define LORA_TXLED_ON() SET_LED_PIN() +#define LORA_TXLED_OFF() CLR_LED_PIN() +#else +#define LORA_TXLED_ON() SET_LORA_TX_LED() +#define LORA_TXLED_OFF() CLR_LORA_TX_LED() +#endif + +#define LORA_BUFF_SIZE 255 + +typedef enum { + RF_ANT_TRANSMITTER, + RF_ANT_RECEIVER, + RF_ANT_CLOSE, +}Sx1276AntStatus_m; + +typedef enum { + SX1276_SLEEP, + SX1276_IDLE, + SX1276_RX, + SX1276_TX, + SX1276_BUSY, + SX1276_ERROR, + SX1276_MAX +}Sx1276StateType_t; + +typedef struct { + uint8_t ucChannel; + uint32_t dwFreqHz; + int8_t ucPower; + Sx1276BwType SignalBw; + Sx1276SpreadFactorType SpreadFactor; + Sx1276ErrorCodingType ErrorCoding; + uint8_t RegPreamble; + uint8_t ucOpModePrev; + Sx1276AntStatus_m bAntSwPrev; + Sx1276RegType RegBuff; + Sx1276StateType_t State; + uint8_t ucRxPacketSize; + uint8_t ucTxPacketSize; + uint8_t RxTxBuff[LORA_BUFF_SIZE]; + void (*RxCallBack)(uint8_t *rBuff, uint8_t rlen); +}Sx1276Type_t, *pSx1276Type; + +//ISM Freq In China +//Up Link: +//CH0-5: 470.3-471.3MHz +//CH39-44:478.1-479.1MHz +//CH78-95:485.9-489.3MHz +//Down Link: +//CH0-47:500.3-509.7MHz + +#define USE_915MHZ 0//=1使 915 =0使 433 + +#if (USE_915MHZ == 1) + // 频 剩 默 为449000000Hz + #define FREQ_CENT 915000000ul + //860MHz-1GHz使 PA 牛 默 喜 使 + //SX127x 澹琀OPERF模 要 + #define USE_LORA_860_PA +#endif + +/* +涓績棰戠巼閰嶇疆锛433100000ul + 200000*N +*/ +#define CH0 (433100000ul + 0) //娴嬭瘯棰戠巼 +#define CH1 (433100000ul + 200000) +#define CH2 (433100000ul + 400000) +#define CH3 (433100000ul + 600000) +#define CH4 (433100000ul + 800000) +#define CH5 (433100000ul + 1000000) +#define CH6 (433100000ul + 1200000) +#define CH7 (433100000ul + 1400000) +#define CH8 (433100000ul + 1600000) +#define CH9 (433100000ul + 1800000) +#define CH10 (433100000ul + 2000000) + +#if (USE_LORA_CH == 0) +#define FREQ_CENT CH0 +#elif (USE_LORA_CH == 1) +#define FREQ_CENT CH1 +#elif (USE_LORA_CH == 2) +#define FREQ_CENT CH2 +#elif (USE_LORA_CH == 3) +#define FREQ_CENT CH3 +#elif (USE_LORA_CH == 4) +#define FREQ_CENT CH4 +#elif (USE_LORA_CH == 5) +#define FREQ_CENT CH5 +#elif (USE_LORA_CH == 6) +#define FREQ_CENT CH6 +#elif (USE_LORA_CH == 7) +#define FREQ_CENT CH7 +#elif (USE_LORA_CH == 8) +#define FREQ_CENT CH8 +#elif (USE_LORA_CH == 9) +#define FREQ_CENT CH9 +#elif (USE_LORA_CH == 10) +#define FREQ_CENT CH10 +#endif + +#if !defined FREQ_CENT +#define FREQ_CENT (433100000ul + 0)//200000 +#endif +#if !defined FREQ_DEV +#define FREQ_DEV 1000000ul +#endif + +////////////////////////////////////////////////////////////////////// +void Sx1276LoRaLoopHandler(void); +void Sx1276LoRaInit(void (*RxCallBack)(uint8_t *rBuff, uint8_t rlen)); +void Sx1276LoRaSendBuffer(uint8_t* pucBuff, uint8_t ucLen); +uint8_t SX1276LoRaReadChannel(void); +boolean_t SX1276LoRaWriteChannel(uint8_t Channel); +uint32_t SX1276LoRaReadFreq(void); +void SX1276LoRaWriteFreq(uint32_t Freq); +void SX1276LoRaWriteBw(Sx1276BwType SignalBw); +uint32_t SX1276LoRaReadBw(void); +uint8_t SX1276LoRaReadSf(void); +void SX1276LoRaWriteSf(Sx1276SpreadFactorType SpreadFactor); +void SX1276LoRaWriteEc(Sx1276ErrorCodingType ErrorCoding); +uint8_t SX1276LoRaReadEc(void); +uint32_t SX1276LoRaParaReadRssi(void); +uint8_t SX1276LoRaReadRssiPkt(void); +void SX1276LoRaWritePwr(int8_t Pwr); +void SX1276LoRaWriteRx(void); +void SX1276LoRaWriteSleep(boolean_t Sleep); +Sx1276StateType_t SX1276LoRaReadStatus(void); +void SX1276LoCalcRssiSnr(int8_t *pswRssi, int8_t *psbSnr); +void Sx1276LoRaSleep(void); +void Sx1276LoRaWakeup(void); +#endif + diff --git a/Module/MahonyAHRS/MahonyAHRS.c b/Module/MahonyAHRS/MahonyAHRS.c new file mode 100644 index 0000000..5ac23de --- /dev/null +++ b/Module/MahonyAHRS/MahonyAHRS.c @@ -0,0 +1,247 @@ +//===================================================================================================== +// MahonyAHRS.c +//===================================================================================================== +// +// Madgwick's implementation of Mayhony's AHRS algorithm. +// See: http://www.x-io.co.uk/node/8#open_source_ahrs_and_imu_algorithms +// +// Date Author Notes +// 29/09/2011 SOH Madgwick Initial release +// 02/10/2011 SOH Madgwick Optimised for reduced CPU load +// +//===================================================================================================== + +//--------------------------------------------------------------------------------------------------- +// Header files + +#include "MahonyAHRS.h" +#include + +//--------------------------------------------------------------------------------------------------- +// Definitions + +#define sampleFreq 10.0f // sample frequency in Hz +#define twoKpDef (2.0f * 1.0f) // 2 * proportional gain +#define twoKiDef (2.0f * 0.0f) // 2 * integral gain + +//--------------------------------------------------------------------------------------------------- +// Variable definitions + +volatile float twoKp = twoKpDef; // 2 * proportional gain (Kp) +volatile float twoKi = twoKiDef; // 2 * integral gain (Ki) +volatile float q0 = 1.0f, q1 = 0.0f, q2 = 0.0f, q3 = 0.0f; // quaternion of sensor frame relative to auxiliary frame +volatile float integralFBx = 0.0f, integralFBy = 0.0f, integralFBz = 0.0f; // integral error terms scaled by Ki + +//--------------------------------------------------------------------------------------------------- +// Function declarations + + + +//==================================================================================================== +// Functions + +//--------------------------------------------------------------------------------------------------- +// AHRS algorithm update + +void MahonyAHRSupdate(float gx, float gy, float gz, float ax, float ay, float az, float mx, float my, float mz) { + float recipNorm; + float q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3, q2q2, q2q3, q3q3; + float hx, hy, bx, bz; + float halfvx, halfvy, halfvz, halfwx, halfwy, halfwz; + float halfex, halfey, halfez; + float qa, qb, qc; + + // Use IMU algorithm if magnetometer measurement invalid (avoids NaN in magnetometer normalisation) + // 鍦ㄧ鍔涜鏁版嵁鏃犳晥鏃朵娇鐢ㄥ叚杞磋瀺鍚堢畻娉 + if((mx == 0.0f) && (my == 0.0f) && (mz == 0.0f)) { + MahonyAHRSupdateIMU(gx, gy, gz, ax, ay, az); + return; + } + + // Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation) + // 鍙湪鍔犻熷害璁℃暟鎹湁鏁堟椂鎵嶈繘琛岃繍绠 + if(!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) { + + // Normalise accelerometer measurement + // 灏嗗姞閫熷害璁″緱鍒扮殑瀹為檯閲嶅姏鍔犻熷害鍚戦噺v鍗曚綅鍖 + recipNorm = invSqrt(ax * ax + ay * ay + az * az); + ax *= recipNorm; + ay *= recipNorm; + az *= recipNorm; + + // Normalise magnetometer measurement + // 灏嗙鍔涜寰楀埌鐨勫疄闄呯鍦哄悜閲弇鍗曚綅鍖 + recipNorm = invSqrt(mx * mx + my * my + mz * mz); + mx *= recipNorm; + my *= recipNorm; + mz *= recipNorm; + + // Auxiliary variables to avoid repeated arithmetic + // 杈呭姪鍙橀噺锛屼互閬垮厤閲嶅杩愮畻 + q0q0 = q0 * q0; + q0q1 = q0 * q1; + q0q2 = q0 * q2; + q0q3 = q0 * q3; + q1q1 = q1 * q1; + q1q2 = q1 * q2; + q1q3 = q1 * q3; + q2q2 = q2 * q2; + q2q3 = q2 * q3; + q3q3 = q3 * q3; + + // Reference direction of Earth's magnetic field + // 閫氳繃纾佸姏璁℃祴閲忓间笌鍧愭爣杞崲鐭╅樀寰楀埌澶у湴鍧愭爣绯讳笅鐨勭悊璁哄湴纾佸悜閲 + hx = 2.0f * (mx * (0.5f - q2q2 - q3q3) + my * (q1q2 - q0q3) + mz * (q1q3 + q0q2)); + hy = 2.0f * (mx * (q1q2 + q0q3) + my * (0.5f - q1q1 - q3q3) + mz * (q2q3 - q0q1)); + bx = sqrt(hx * hx + hy * hy); + bz = 2.0f * (mx * (q1q3 - q0q2) + my * (q2q3 + q0q1) + mz * (0.5f - q1q1 - q2q2)); + + // Estimated direction of gravity and magnetic field + // 灏嗙悊璁洪噸鍔涘姞閫熷害鍚戦噺涓庣悊璁哄湴纾佸悜閲忓彉鎹㈣嚦鏈轰綋鍧愭爣绯 + halfvx = q1q3 - q0q2; + halfvy = q0q1 + q2q3; + halfvz = q0q0 - 0.5f + q3q3; + halfwx = bx * (0.5f - q2q2 - q3q3) + bz * (q1q3 - q0q2); + halfwy = bx * (q1q2 - q0q3) + bz * (q0q1 + q2q3); + halfwz = bx * (q0q2 + q1q3) + bz * (0.5f - q1q1 - q2q2); + + // Error is sum of cross product between estimated direction and measured direction of field vectors + // 閫氳繃鍚戦噺澶栫Н寰楀埌閲嶅姏鍔犻熷害鍚戦噺鍜屽湴纾佸悜閲忕殑瀹為檯鍊间笌娴嬮噺鍊间箣闂磋宸 + halfex = (ay * halfvz - az * halfvy) + (my * halfwz - mz * halfwy); + halfey = (az * halfvx - ax * halfvz) + (mz * halfwx - mx * halfwz); + halfez = (ax * halfvy - ay * halfvx) + (mx * halfwy - my * halfwx); + + // Compute and apply integral feedback if enabled + // 鍦≒I琛ュ伩鍣ㄤ腑绉垎椤逛娇鑳芥儏鍐典笅璁＄畻骞跺簲鐢ㄧН鍒嗛」 + if(twoKi > 0.0f) { + integralFBx += twoKi * halfex * (1.0f / sampleFreq); // integral error scaled by Ki + integralFBy += twoKi * halfey * (1.0f / sampleFreq); + integralFBz += twoKi * halfez * (1.0f / sampleFreq); + gx += integralFBx; // apply integral feedback // 搴旂敤璇樊琛ュ伩涓殑绉垎椤 + gy += integralFBy; + gz += integralFBz; + } + else { + integralFBx = 0.0f; // prevent integral windup // 閬垮厤涓鸿礋鍊肩殑Ki鏃剁Н鍒嗗紓甯搁ケ鍜 + integralFBy = 0.0f; + integralFBz = 0.0f; + } + + // Apply proportional feedback + // 搴旂敤璇樊琛ュ伩涓殑姣斾緥椤 + gx += twoKp * halfex; + gy += twoKp * halfey; + gz += twoKp * halfez; + } + + // Integrate rate of change of quaternion + // 寰垎鏂圭▼杩唬姹傝В + gx *= (0.5f * (1.0f / sampleFreq)); // pre-multiply common factors + gy *= (0.5f * (1.0f / sampleFreq)); + gz *= (0.5f * (1.0f / sampleFreq)); + qa = q0; + qb = q1; + qc = q2; + q0 += (-qb * gx - qc * gy - q3 * gz); + q1 += (qa * gx + qc * gz - q3 * gy); + q2 += (qa * gy - qb * gz + q3 * gx); + q3 += (qa * gz + qb * gy - qc * gx); + + // Normalise quaternion + // 鍗曚綅鍖栧洓鍏冩暟 淇濊瘉鍥涘厓鏁板湪杩唬杩囩▼涓繚鎸佸崟浣嶆ц川 + recipNorm = invSqrt(q0 * q0 + q1 * q1 + q2 * q2 + q3 * q3); + q0 *= recipNorm; + q1 *= recipNorm; + q2 *= recipNorm; + q3 *= recipNorm; + //Mahony瀹樻柟绋嬪簭鍒版缁撴潫锛屼娇鐢ㄦ椂鍙渶鍦ㄥ嚱鏁板杩涜鍥涘厓鏁板弽瑙ｆ鎷夎鍗冲彲瀹屾垚鍏ㄩ儴濮挎佽В绠楄繃绋 +} + +//--------------------------------------------------------------------------------------------------- +// IMU algorithm update + +void MahonyAHRSupdateIMU(float gx, float gy, float gz, float ax, float ay, float az) { + float recipNorm; + float halfvx, halfvy, halfvz;//1/2 閲嶅姏鍒嗛噺 + float halfex, halfey, halfez;//1/2 閲嶅姏璇樊 + float qa, qb, qc; + + + // Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation) + // 鍦ㄧ鍔涜鏁版嵁鏃犳晥鏃朵娇鐢ㄥ叚杞磋瀺鍚堢畻娉 + if(!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) { + + // Normalise accelerometer measurement + recipNorm = invSqrt(ax * ax + ay * ay + az * az); + ax *= recipNorm; + ay *= recipNorm; + az *= recipNorm; + + // Estimated direction of gravity and vector perpendicular to magnetic flux + halfvx = q1 * q3 - q0 * q2; + halfvy = q0 * q1 + q2 * q3; + halfvz = q0 * q0 - 0.5f + q3 * q3; + + // Error is sum of cross product between estimated and measured direction of gravity + halfex = (ay * halfvz - az * halfvy); + halfey = (az * halfvx - ax * halfvz); + halfez = (ax * halfvy - ay * halfvx); + + // Compute and apply integral feedback if enabled + if(twoKi > 0.0f) { + integralFBx += twoKi * halfex * (1.0f / sampleFreq); // integral error scaled by Ki + integralFBy += twoKi * halfey * (1.0f / sampleFreq); + integralFBz += twoKi * halfez * (1.0f / sampleFreq); + gx += integralFBx; // apply integral feedback + gy += integralFBy; + gz += integralFBz; + } + else { + integralFBx = 0.0f; // prevent integral windup + integralFBy = 0.0f; + integralFBz = 0.0f; + } + + // Apply proportional feedback + gx += twoKp * halfex; + gy += twoKp * halfey; + gz += twoKp * halfez; + } + + // Integrate rate of change of quaternion + gx *= (0.5f * (1.0f / sampleFreq)); // pre-multiply common factors + gy *= (0.5f * (1.0f / sampleFreq)); + gz *= (0.5f * (1.0f / sampleFreq)); + qa = q0; + qb = q1; + qc = q2; + q0 += (-qb * gx - qc * gy - q3 * gz); + q1 += (qa * gx + qc * gz - q3 * gy); + q2 += (qa * gy - qb * gz + q3 * gx); + q3 += (qa * gz + qb * gy - qc * gx); + + // Normalise quaternion + recipNorm = invSqrt(q0 * q0 + q1 * q1 + q2 * q2 + q3 * q3); + q0 *= recipNorm; + q1 *= recipNorm; + q2 *= recipNorm; + q3 *= recipNorm; +} + +//--------------------------------------------------------------------------------------------------- +// Fast inverse square-root +// See: http://en.wikipedia.org/wiki/Fast_inverse_square_root + +float invSqrt(float x) { + float halfx = 0.5f * x; + float y = x; + long i = *(long*)&y; + i = 0x5f3759df - (i>>1); + y = *(float*)&i; + y = y * (1.5f - (halfx * y * y)); + return y; +} + +//==================================================================================================== +// END OF CODE +//==================================================================================================== diff --git a/Module/MahonyAHRS/MahonyAHRS.h b/Module/MahonyAHRS/MahonyAHRS.h new file mode 100644 index 0000000..a61e75c --- /dev/null +++ b/Module/MahonyAHRS/MahonyAHRS.h @@ -0,0 +1,32 @@ +//===================================================================================================== +// MahonyAHRS.h +//===================================================================================================== +// +// Madgwick's implementation of Mayhony's AHRS algorithm. +// See: http://www.x-io.co.uk/node/8#open_source_ahrs_and_imu_algorithms +// +// Date Author Notes +// 29/09/2011 SOH Madgwick Initial release +// 02/10/2011 SOH Madgwick Optimised for reduced CPU load +// +//===================================================================================================== +#ifndef MahonyAHRS_h +#define MahonyAHRS_h + +//---------------------------------------------------------------------------------------------------- +// Variable declaration + +extern volatile float twoKp; // 2 * proportional gain (Kp) +extern volatile float twoKi; // 2 * integral gain (Ki) +extern volatile float q0, q1, q2, q3; // quaternion of sensor frame relative to auxiliary frame + +//--------------------------------------------------------------------------------------------------- +// Function declarations +float invSqrt(float x); +void MahonyAHRSupdate(float gx, float gy, float gz, float ax, float ay, float az, float mx, float my, float mz); +void MahonyAHRSupdateIMU(float gx, float gy, float gz, float ax, float ay, float az); + +#endif +//===================================================================================================== +// End of file +//===================================================================================================== diff --git a/Module/lsm6dsl/lsm6dsl_app.c b/Module/lsm6dsl/lsm6dsl_app.c new file mode 100644 index 0000000..0317d9d --- /dev/null +++ b/Module/lsm6dsl/lsm6dsl_app.c @@ -0,0 +1,269 @@ + +/* Includes ------------------------------------------------------------------*/ +#include "lsm6dsl_app.h" +#include "lsm6dsl_reg.h" +#include +#include +#include "bsp.h" +#include "UartDebug.h" +#include "main.h" +#include "i2c.h" +#include "Algorithm.h" + +dev_ctx_t dev_ctx; +static bool InitFlag; + +#define ACC_CVTTIME (20 * 1000) +#define ACC_COLL_CNT_MAX 6 +#define ACC_FIFO_WATERMASK (ACC_COLL_CNT_MAX * 6) //采集一秒数据 +#define TX_BUF_DIM 1000 +#define BOOT_TIME 15 //ms + +typedef enum { + Acc_Idle, + Acc_Start, + Acc_Get_Data, + Acc_Wait_GetData, + Acc_Go_Bypass, +}AccStatusType_m; + +static AccStatusType_m acc_status; +static uint32_t acc_cvttime; +static bool Lsm6dslWaterMarkFullIntFlag; +static bool Lsm6dslWakeupIntFlag; + +static int16_t data_raw_acceleration[3]; +static int16_t data_raw_angular_rate[3]; +static int16_t data_raw_temperature; +static float acceleration_mg[3][ACC_COLL_CNT_MAX]; +static float angular_rate_mdps[3][ACC_COLL_CNT_MAX]; +static float temperature_degC; +static uint8_t whoamI, rst; + + +static void platform_delay(uint32_t ms) +{ + delay_ms(ms); +} + + +static void platform_write(uint8_t reg, uint8_t *bufp, uint32_t len) +{ + uint16_t Selve_Add = LSM6DSL_I2C_ADD_L >> 1; + I2C_MasterWriteData(M0P_I2C0, Selve_Add, reg, bufp, len); +} + + +static void platform_read(uint8_t reg, uint8_t *bufp, uint32_t len) +{ + uint16_t Selve_Add = LSM6DSL_I2C_ADD_L >> 1; + I2C_MasterReadData(M0P_I2C0, Selve_Add, reg, bufp, len); +} + +static void Lsm6dsl_Init(void) +{ + /* Initialize mems driver interface */ + dev_ctx.write_reg = platform_write; + dev_ctx.read_reg = platform_read; + dev_ctx.mdelay = platform_delay; + /* Wait sensor boot time */ + platform_delay(BOOT_TIME); + /* Check device ID */ + whoamI = 0; + lsm6dsl_device_id_get(&dev_ctx, &whoamI); + acc_cvttime = 100; + while(whoamI != LSM6DSL_ID){ + if(acc_cvttime <= 0){ + DBG_LOG("LSM6DS INIT Err...\r\n"); /*manage here device not found */ + InitFlag = false; + return; + } + } + + /* Restore default configuration */ + lsm6dsl_reset_set(&dev_ctx, PROPERTY_ENABLE); + + do { + lsm6dsl_reset_get(&dev_ctx, &rst); + } while (rst); + + lsm6dsl_xl_power_mode_set(&dev_ctx, LSM6DSL_XL_NORMAL); + /* Enable Block Data Update */ + lsm6dsl_block_data_update_set(&dev_ctx, PROPERTY_ENABLE); + /* Set Output Data Rate */ + lsm6dsl_xl_data_rate_set(&dev_ctx, LSM6DSL_XL_ODR_12Hz5); + lsm6dsl_gy_data_rate_set(&dev_ctx, LSM6DSL_GY_ODR_12Hz5); + //lsm6dsl_gy_data_rate_set(&left_dev_ctx, LSM6DSL_GY_ODR_OFF); //关闭地磁 + /* Set full scale */ + lsm6dsl_xl_full_scale_set(&dev_ctx, LSM6DSL_2g); + lsm6dsl_gy_full_scale_set(&dev_ctx, LSM6DSL_2000dps); + /* Configure filtering chain(No aux interface) */ + /* Accelerometer - analog filter */ + lsm6dsl_xl_filter_analog_set(&dev_ctx, LSM6DSL_XL_ANA_BW_400Hz); + /* Accelerometer - LPF1 path ( LPF2 not used )*/ + /*lsm6dsl_xl_lp1_bandwidth_set(&left_dev_ctx, LSM6DSL_XL_LP1_ODR_DIV_4);*/ + /* Accelerometer - LPF1 + LPF2 path */ + lsm6dsl_xl_lp2_bandwidth_set(&dev_ctx, LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_9); + /* Accelerometer - High Pass / Slope path */ + /*lsm6dsl_xl_reference_mode_set(&left_dev_ctx, PROPERTY_DISABLE);*/ + /*lsm6dsl_xl_hp_bandwidth_set(&left_dev_ctx, LSM6DSL_XL_HP_ODR_DIV_100);*/ + /* Gyroscope - filtering chain */ + lsm6dsl_gy_band_pass_set(&dev_ctx, LSM6DSL_HP_260mHz_LP1_STRONG); + + //fifo模式设置 + lsm6dsl_fifo_xl_batch_set(&dev_ctx, LSM6DSL_FIFO_XL_NO_DEC);//fifo加速度写入频率设置 + lsm6dsl_fifo_gy_batch_set(&dev_ctx, LSM6DSL_FIFO_GY_NO_DEC);//fifo陀螺仪写入频率设置 + lsm6dsl_fifo_data_rate_set(&dev_ctx, LSM6DSL_FIFO_12Hz5);//FIFO ODR选择 + + //中断1设置，watermark full中断 + lsm6dsl_int1_route_t int1val ={0, 0, 0}; + int1val.int1_full_flag = 1; //开阀值中断，fifo存储到缓存深度时触发 + lsm6dsl_pin_int1_route_set(&dev_ctx, int1val); + lsm6dsl_fifo_watermark_set(&dev_ctx, ACC_FIFO_WATERMASK);//FIFO水印电平设置，阈值设置，缓存深度 + lsm6dsl_fifo_stop_on_wtm_set(&dev_ctx, 1);//fifo缓存深度存满时，不再存储 + //lsm6dsl_fifo_xl_gy_8bit_format_set(&left_dev_ctx, 1);//在FIFO中为XL和陀螺启用MSByte记忆，缓存宽度 + lsm6dsl_block_data_update_set(&dev_ctx, 1); //fifo模式ctrl3_c bdu必须为1,直到读取MSB和LSB后才更新输出寄存器 + lsm6dsl_auto_increment_set(&dev_ctx, 1); //fifo模式ctrl3_c if_inc必须为1,通过串行接口(I2C或SPI)进行多字节访问时自动增加寄存器地址。 + lsm6dsl_ctrl3_c_t ctrl3_c; + platform_read(LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + //lsm6dsl_fifo_mode_set(&dev_ctx, LSM6DSL_FIFO_MODE); + + //中断2设置，唤醒中断 +// uint8_t temp = 0x90; //唤醒中断 +// platform_write(LSM6DSL_TAP_CFG, &temp, 1); +// temp = 0; +// platform_write(LSM6DSL_WAKE_UP_DUR, &temp, 1); +// lsm6dsl_wkup_threshold_set(&left_dev_ctx, 0x20); +// lsm6dsl_int2_route_t int2val ={0, 0, 0}; +// int2val.int2_wu = 1; +// lsm6dsl_pin_int2_route_set(&left_dev_ctx, int2val); + + if(InitFlag == false){ + DBG_LOG("LSM6DS INIT OK...\r\n"); + InitFlag = true; + } +} + +extern void Lsm6dDataProcessCallBack(float *Acc, float *Gy); +static void Acc_IntHandler(void) +{ + uint16_t DiffFifo; + AccGyData_t AccGy; + AccData_t Acc; + float VectorG; + float AverageAcc[XYZ], AverageGy[XYZ]; + + lsm6dsl_fifo_data_level_get(&dev_ctx, &DiffFifo); + if(DiffFifo == 0) { + return; + } + + if(DiffFifo > ACC_FIFO_WATERMASK) + DiffFifo = ACC_FIFO_WATERMASK; + for(int i = 0; i < DiffFifo / 6; i++) { + lsm6dsl_fifo_raw_data_get(&dev_ctx, (uint8_t *)&AccGy, sizeof(AccGy)); + angular_rate_mdps[X][i] = lsm6dsl_from_fs2000dps_to_mdps(AccGy.GyX); + angular_rate_mdps[Y][i] = lsm6dsl_from_fs2000dps_to_mdps(AccGy.GyY); + angular_rate_mdps[Z][i] = lsm6dsl_from_fs2000dps_to_mdps(AccGy.GyZ); + acceleration_mg[X][i] = lsm6dsl_from_fs2g_to_mg(AccGy.AccX); + acceleration_mg[Y][i] = lsm6dsl_from_fs2g_to_mg(AccGy.AccY); + acceleration_mg[Z][i] = lsm6dsl_from_fs2g_to_mg(AccGy.AccZ); + } + AverageGy[X] = IntFilter_Float(angular_rate_mdps[0], DiffFifo / 6, 2); + AverageGy[Y] = IntFilter_Float(angular_rate_mdps[1], DiffFifo / 6, 2); + AverageGy[Z] = IntFilter_Float(angular_rate_mdps[2], DiffFifo / 6, 2); + AverageAcc[X] = IntFilter_Float(acceleration_mg[0], DiffFifo / 6, 2); + AverageAcc[Y] = IntFilter_Float(acceleration_mg[1], DiffFifo / 6, 2); + AverageAcc[Z] = IntFilter_Float(acceleration_mg[2], DiffFifo / 6, 2); + Lsm6dDataProcessCallBack(AverageAcc, AverageGy); + + acc_status = Acc_Go_Bypass; +} + +static void ReadWakeUpIntStatus(void) +{ + lsm6dsl_wake_up_src_t wake_up_src; + if(Lsm6dslWakeupIntFlag) { + Lsm6dslWakeupIntFlag = false; + platform_read(LSM6DSL_WAKE_UP_SRC, (uint8_t *)&wake_up_src, sizeof(lsm6dsl_wake_up_src_t)); + } +} + +void Lsm6dslLoopHandler(void) +{ + ReadWakeUpIntStatus(); + switch(acc_status) + { + case Acc_Idle: + break; + + case Acc_Start: + if(acc_cvttime > 0) + break; + lsm6dsl_fifo_mode_set(&dev_ctx, LSM6DSL_FIFO_MODE); + acc_status = Acc_Get_Data; + acc_cvttime = ACC_CVTTIME; + break; + + case Acc_Get_Data: + acc_cvttime = 1000; + acc_status = Acc_Wait_GetData; + break; + + case Acc_Wait_GetData: + if(acc_cvttime <= 0){ + acc_status = Acc_Go_Bypass; + } + else if(Lsm6dslWaterMarkFullIntFlag) { + Lsm6dslWaterMarkFullIntFlag = false; + uint8_t wtm_flag; + lsm6dsl_fifo_wtm_flag_get(&dev_ctx, &wtm_flag); + Acc_IntHandler(); + acc_status = Acc_Go_Bypass; + } + break; + + case Acc_Go_Bypass: + lsm6dsl_fifo_mode_set(&dev_ctx, LSM6DSL_BYPASS_MODE); + Lsm6dsStop(); + acc_status = Acc_Idle; + acc_cvttime = 1; + break; + } +} + +void Lsm6dsl1mSRoutine(void) +{ + if(acc_cvttime > 0) + acc_cvttime--; +} + +void Lsm6dslInit(void) +{ + Lsm6dsl_Init(); +} + +void Lsm6dsStart(void) +{ + Lsm6dsl_Init(); + acc_status = Acc_Start; +} + +void Lsm6dsStop(void) +{ + lsm6dsl_xl_data_rate_set(&dev_ctx, LSM6DSL_XL_ODR_OFF); + lsm6dsl_gy_data_rate_set(&dev_ctx, LSM6DSL_GY_ODR_OFF); + lsm6dsl_fifo_data_rate_set(&dev_ctx, LSM6DSL_FIFO_DISABLE); + acc_status = Acc_Idle; +} + +void Lsm6dsInt1CallBack(void) +{ + Lsm6dslWaterMarkFullIntFlag = true; +} + +void Lsm6dsInt2CallBack(void) +{ + Lsm6dslWakeupIntFlag = true; + //Tilt.Acc_IRQ_Status = true; +} diff --git a/Module/lsm6dsl/lsm6dsl_app.h b/Module/lsm6dsl/lsm6dsl_app.h new file mode 100644 index 0000000..2143093 --- /dev/null +++ b/Module/lsm6dsl/lsm6dsl_app.h @@ -0,0 +1,36 @@ +#ifndef __LSM6DSL_APP_H__ +#define __LSM6DSL_APP_H__ + +#include "bsp.h" + +#define X 0 +#define Y 1 +#define Z 2 +#define XYZ 3 + +typedef struct { + uint16_t GyX; + uint16_t GyY; + uint16_t GyZ; + uint16_t AccX; + uint16_t AccY; + uint16_t AccZ; +}AccGyData_t; + +typedef struct { + uint16_t AccX; + uint16_t AccY; + uint16_t AccZ; +}AccData_t; + +void Lsm6dslInit(void); +void Lsm6dslLoopHandler(void); +void Lsm6dsl1mSRoutine(void); +void Lsm6dsStart(void); +void Lsm6dsStop(void); +void Lsm6dsInt1CallBack(void); +void Lsm6dsInt2CallBack(void); +#endif + + + diff --git a/Module/lsm6dsl/lsm6dsl_reg.c b/Module/lsm6dsl/lsm6dsl_reg.c new file mode 100644 index 0000000..de0745a --- /dev/null +++ b/Module/lsm6dsl/lsm6dsl_reg.c @@ -0,0 +1,7948 @@ +/** + ****************************************************************************** + * @file lsm6dsl_reg.c + * @author Sensors Software Solution Team + * @brief LSM6DSL driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lsm6dsl_reg.h" + +/** + * @defgroup LSM6DSL + * @brief This file provides a set of functions needed to drive the + * lsm6dsl enanced inertial module. + * @{ + * + */ + +/** + * @defgroup LSM6DSL_interfaces_functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsl_read_reg(dev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + //int32_t ret; + + ctx->read_reg(reg, data, len); + + return 0; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsl_write_reg(dev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + //int32_t ret; + + ctx->write_reg(reg, data, len); + + return 0; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t lsm6dsl_from_fs2g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.061f); +} + +float_t lsm6dsl_from_fs4g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.122f); +} + +float_t lsm6dsl_from_fs8g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.244f); +} + +float_t lsm6dsl_from_fs16g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.488f); +} + +float_t lsm6dsl_from_fs125dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 4.375f); +} + +float_t lsm6dsl_from_fs250dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 8.750f); +} + +float_t lsm6dsl_from_fs500dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 17.50f); +} + +float_t lsm6dsl_from_fs1000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 35.0f); +} + +float_t lsm6dsl_from_fs2000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 70.0f); +} + +float_t lsm6dsl_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +/** + * @} + * + */ + + +/** + * @defgroup LSM6DSL_data_generation + * @brief This section groups all the functions concerning data + * generation + * @{ + * + */ + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fs_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_full_scale_set(dev_ctx_t *ctx, + lsm6dsl_fs_xl_t val) +{ + lsm6dsl_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + if (ret == 0) + { + ctrl1_xl.fs_xl = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of fs_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_full_scale_get(dev_ctx_t *ctx, + lsm6dsl_fs_xl_t *val) +{ + lsm6dsl_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + switch (ctrl1_xl.fs_xl) + { + case LSM6DSL_2g: + *val = LSM6DSL_2g; + break; + + case LSM6DSL_16g: + *val = LSM6DSL_16g; + break; + + case LSM6DSL_4g: + *val = LSM6DSL_4g; + break; + + case LSM6DSL_8g: + *val = LSM6DSL_8g; + break; + + default: + *val = LSM6DSL_XL_FS_ND; + break; + } + + return ret; +} + +/** + * @brief Accelerometer data rate selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of odr_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_data_rate_set(dev_ctx_t *ctx, + lsm6dsl_odr_xl_t val) +{ + lsm6dsl_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + if (ret == 0) + { + ctrl1_xl.odr_xl = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + } + + return ret; +} + +/** + * @brief Accelerometer data rate selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of odr_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_data_rate_get(dev_ctx_t *ctx, + lsm6dsl_odr_xl_t *val) +{ + lsm6dsl_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + switch (ctrl1_xl.odr_xl) + { + case LSM6DSL_XL_ODR_OFF: + *val = LSM6DSL_XL_ODR_OFF; + break; + + case LSM6DSL_XL_ODR_12Hz5: + *val = LSM6DSL_XL_ODR_12Hz5; + break; + + case LSM6DSL_XL_ODR_26Hz: + *val = LSM6DSL_XL_ODR_26Hz; + break; + + case LSM6DSL_XL_ODR_52Hz: + *val = LSM6DSL_XL_ODR_52Hz; + break; + + case LSM6DSL_XL_ODR_104Hz: + *val = LSM6DSL_XL_ODR_104Hz; + break; + + case LSM6DSL_XL_ODR_208Hz: + *val = LSM6DSL_XL_ODR_208Hz; + break; + + case LSM6DSL_XL_ODR_416Hz: + *val = LSM6DSL_XL_ODR_416Hz; + break; + + case LSM6DSL_XL_ODR_833Hz: + *val = LSM6DSL_XL_ODR_833Hz; + break; + + case LSM6DSL_XL_ODR_1k66Hz: + *val = LSM6DSL_XL_ODR_1k66Hz; + break; + + case LSM6DSL_XL_ODR_3k33Hz: + *val = LSM6DSL_XL_ODR_3k33Hz; + break; + + case LSM6DSL_XL_ODR_6k66Hz: + *val = LSM6DSL_XL_ODR_6k66Hz; + break; + + case LSM6DSL_XL_ODR_1Hz6: + *val = LSM6DSL_XL_ODR_1Hz6; + break; + + default: + *val = LSM6DSL_XL_ODR_ND; + break; + } + + return ret; +} + +/** + * @brief Gyroscope chain full-scale selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fs_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_full_scale_set(dev_ctx_t *ctx, + lsm6dsl_fs_g_t val) +{ + lsm6dsl_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + + if (ret == 0) + { + ctrl2_g.fs_g = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + + return ret; +} + +/** + * @brief Gyroscope chain full-scale selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of fs_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_full_scale_get(dev_ctx_t *ctx, + lsm6dsl_fs_g_t *val) +{ + lsm6dsl_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + + switch (ctrl2_g.fs_g) + { + case LSM6DSL_250dps: + *val = LSM6DSL_250dps; + break; + + case LSM6DSL_125dps: + *val = LSM6DSL_125dps; + break; + + case LSM6DSL_500dps: + *val = LSM6DSL_500dps; + break; + + case LSM6DSL_1000dps: + *val = LSM6DSL_1000dps; + break; + + case LSM6DSL_2000dps: + *val = LSM6DSL_2000dps; + break; + + default: + *val = LSM6DSL_GY_FS_ND; + break; + } + + return ret; +} + +/** + * @brief Gyroscope data rate selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of odr_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_data_rate_set(dev_ctx_t *ctx, + lsm6dsl_odr_g_t val) +{ + lsm6dsl_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + + if (ret == 0) + { + ctrl2_g.odr_g = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + + return ret; +} + +/** + * @brief Gyroscope data rate selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of odr_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_data_rate_get(dev_ctx_t *ctx, + lsm6dsl_odr_g_t *val) +{ + lsm6dsl_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + + switch (ctrl2_g.odr_g) + { + case LSM6DSL_GY_ODR_OFF: + *val = LSM6DSL_GY_ODR_OFF; + break; + + case LSM6DSL_GY_ODR_12Hz5: + *val = LSM6DSL_GY_ODR_12Hz5; + break; + + case LSM6DSL_GY_ODR_26Hz: + *val = LSM6DSL_GY_ODR_26Hz; + break; + + case LSM6DSL_GY_ODR_52Hz: + *val = LSM6DSL_GY_ODR_52Hz; + break; + + case LSM6DSL_GY_ODR_104Hz: + *val = LSM6DSL_GY_ODR_104Hz; + break; + + case LSM6DSL_GY_ODR_208Hz: + *val = LSM6DSL_GY_ODR_208Hz; + break; + + case LSM6DSL_GY_ODR_416Hz: + *val = LSM6DSL_GY_ODR_416Hz; + break; + + case LSM6DSL_GY_ODR_833Hz: + *val = LSM6DSL_GY_ODR_833Hz; + break; + + case LSM6DSL_GY_ODR_1k66Hz: + *val = LSM6DSL_GY_ODR_1k66Hz; + break; + + case LSM6DSL_GY_ODR_3k33Hz: + *val = LSM6DSL_GY_ODR_3k33Hz; + break; + + case LSM6DSL_GY_ODR_6k66Hz: + *val = LSM6DSL_GY_ODR_6k66Hz; + break; + + default: + *val = LSM6DSL_GY_ODR_ND; + break; + } + + return ret; +} + +/** + * @brief Block data update.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of bdu in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_block_data_update_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.bdu = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Block data update.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of bdu in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_block_data_update_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.bdu; + + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers + * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of usr_off_w in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_offset_weight_set(dev_ctx_t *ctx, + lsm6dsl_usr_off_w_t val) +{ + lsm6dsl_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + if (ret == 0) + { + ctrl6_c.usr_off_w = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers + * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of usr_off_w in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_offset_weight_get(dev_ctx_t *ctx, + lsm6dsl_usr_off_w_t *val) +{ + lsm6dsl_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.usr_off_w) + { + case LSM6DSL_LSb_1mg: + *val = LSM6DSL_LSb_1mg; + break; + + case LSM6DSL_LSb_16mg: + *val = LSM6DSL_LSb_16mg; + break; + + default: + *val = LSM6DSL_WEIGHT_ND; + break; + } + + return ret; +} + +/** + * @brief High-performance operating mode for accelerometer[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of xl_hm_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_power_mode_set(dev_ctx_t *ctx, + lsm6dsl_xl_hm_mode_t val) +{ + lsm6dsl_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + if (ret == 0) + { + ctrl6_c.xl_hm_mode = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + + return ret; +} + +/** + * @brief High-performance operating mode for accelerometer.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of xl_hm_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_power_mode_get(dev_ctx_t *ctx, + lsm6dsl_xl_hm_mode_t *val) +{ + lsm6dsl_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.xl_hm_mode) + { + case LSM6DSL_XL_HIGH_PERFORMANCE: + *val = LSM6DSL_XL_HIGH_PERFORMANCE; + break; + + case LSM6DSL_XL_NORMAL: + *val = LSM6DSL_XL_NORMAL; + break; + + default: + *val = LSM6DSL_XL_PW_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief Source register rounding function on WAKE_UP_SRC (1Bh), + * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and + * FUNC_SRC1 (53h) registers in the primary interface.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of rounding_status in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_rounding_on_status_set(dev_ctx_t *ctx, + lsm6dsl_rounding_status_t val) +{ + lsm6dsl_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + if (ret == 0) + { + ctrl7_g.rounding_status = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + + return ret; +} + +/** + * @brief Source register rounding function on WAKE_UP_SRC (1Bh), + * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and + * FUNC_SRC1 (53h) registers in the primary interface.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of rounding_status in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_rounding_on_status_get(dev_ctx_t *ctx, + lsm6dsl_rounding_status_t *val) +{ + lsm6dsl_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + switch (ctrl7_g.rounding_status) + { + case LSM6DSL_STAT_RND_DISABLE: + *val = LSM6DSL_STAT_RND_DISABLE; + break; + + case LSM6DSL_STAT_RND_ENABLE: + *val = LSM6DSL_STAT_RND_ENABLE; + break; + + default: + *val = LSM6DSL_STAT_RND_ND; + break; + } + + return ret; +} + +/** + * @brief High-performance operating mode disable for gyroscope.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of g_hm_mode in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_power_mode_set(dev_ctx_t *ctx, + lsm6dsl_g_hm_mode_t val) +{ + lsm6dsl_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + if (ret == 0) + { + ctrl7_g.g_hm_mode = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + + return ret; +} + +/** + * @brief High-performance operating mode disable for gyroscope.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of g_hm_mode in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_power_mode_get(dev_ctx_t *ctx, + lsm6dsl_g_hm_mode_t *val) +{ + lsm6dsl_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + switch (ctrl7_g.g_hm_mode) + { + case LSM6DSL_GY_HIGH_PERFORMANCE: + *val = LSM6DSL_GY_HIGH_PERFORMANCE; + break; + + case LSM6DSL_GY_NORMAL: + *val = LSM6DSL_GY_NORMAL; + break; + + default: + *val = LSM6DSL_GY_PW_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief Read all the interrupt/status flag of the device.[get] + * + * @param ctx Read / write interface definitions + * @param val WAKE_UP_SRC, TAP_SRC, D6D_SRC, STATUS_REG, + * FUNC_SRC1, FUNC_SRC2, WRIST_TILT_IA, A_WRIST_TILT_Mask + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_all_sources_get(dev_ctx_t *ctx, + lsm6dsl_all_sources_t *val) +{ + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_SRC, + (uint8_t *) & (val->wake_up_src), 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_SRC, + (uint8_t *) & (val->tap_src), 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_D6D_SRC, + (uint8_t *) & (val->d6d_src), 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, + (uint8_t *) & (val->status_reg), 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_SRC1, + (uint8_t *) & (val->func_src1), 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_SRC2, + (uint8_t *) & (val->func_src2), 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WRIST_TILT_IA, + (uint8_t *) & (val->wrist_tilt_ia), 1); + } + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK, + (uint8_t *) & (val->a_wrist_tilt_mask), 1); + } + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + + return ret; +} +/** + * @brief The STATUS_REG register is read by the primary interface[get] + * + * @param ctx Read / write interface definitions + * @param val Registers STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_status_reg_get(dev_ctx_t *ctx, + lsm6dsl_status_reg_t *val) +{ + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, (uint8_t *) val, 1); + + return ret; +} + +/** + * @brief Accelerometer new data available.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of xlda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_flag_data_ready_get(dev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsl_status_reg_t status_reg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.xlda; + + return ret; +} + +/** + * @brief Gyroscope new data available.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of gda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_flag_data_ready_get(dev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsl_status_reg_t status_reg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.gda; + + return ret; +} + +/** + * @brief Temperature new data available.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_temp_flag_data_ready_get(dev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsl_status_reg_t status_reg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.tda; + + return ret; +} + +/** + * @brief Accelerometer axis user offset correction expressed in two鈥檚 + * complement, weight depends on USR_OFF_W in CTRL6_C. + * The value must be in the range [-127 127].[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_usr_offset_set(dev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_write_reg(ctx, LSM6DSL_X_OFS_USR, buff, 3); + + return ret; +} + +/** + * @brief Accelerometer axis user offset correction xpressed in two鈥檚 + * complement, weight depends on USR_OFF_W in CTRL6_C. + * The value must be in the range [-127 127].[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_usr_offset_get(dev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_X_OFS_USR, buff, 3); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h), + * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of timer_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_timestamp_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + ctrl10_c.timer_en = val; + + if (val != 0x00U) + { + ctrl10_c.func_en = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + } + } + + return ret; +} + +/** + * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h), + * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of timer_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_timestamp_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + *val = ctrl10_c.timer_en; + + return ret; +} + +/** + * @brief Timestamp register resolution setting. + * Configuration of this bit affects + * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h), + * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h), + * STEP_TIMESTAMP_H(4Ah) and + * STEP_COUNT_DELTA(15h) registers.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of timer_hr in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_timestamp_res_set(dev_ctx_t *ctx, + lsm6dsl_timer_hr_t val) +{ + lsm6dsl_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + wake_up_dur.timer_hr = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + + return ret; +} + +/** + * @brief Timestamp register resolution setting. + * Configuration of this bit affects + * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h), + * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h), + * STEP_TIMESTAMP_H(4Ah) and + * STEP_COUNT_DELTA(15h) registers.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of timer_hr in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_timestamp_res_get(dev_ctx_t *ctx, + lsm6dsl_timer_hr_t *val) +{ + lsm6dsl_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + switch (wake_up_dur.timer_hr) + { + case LSM6DSL_LSB_6ms4: + *val = LSM6DSL_LSB_6ms4; + break; + + case LSM6DSL_LSB_25us: + *val = LSM6DSL_LSB_25us; + break; + + default: + *val = LSM6DSL_TS_RES_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_Dataoutput + * @brief This section groups all the data output functions. + * @{ + * + */ + +/** + * @brief Circular burst-mode (rounding) read from output registers + * through the primary interface.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of rounding in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_rounding_mode_set(dev_ctx_t *ctx, + lsm6dsl_rounding_t val) +{ + lsm6dsl_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + if (ret == 0) + { + ctrl5_c.rounding = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + + return ret; +} + +/** + * @brief Circular burst-mode (rounding) read from output registers + * through the primary interface.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of rounding in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_rounding_mode_get(dev_ctx_t *ctx, + lsm6dsl_rounding_t *val) +{ + lsm6dsl_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch (ctrl5_c.rounding) + { + case LSM6DSL_ROUND_DISABLE: + *val = LSM6DSL_ROUND_DISABLE; + break; + + case LSM6DSL_ROUND_XL: + *val = LSM6DSL_ROUND_XL; + break; + + case LSM6DSL_ROUND_GY: + *val = LSM6DSL_ROUND_GY; + break; + + case LSM6DSL_ROUND_GY_XL: + *val = LSM6DSL_ROUND_GY_XL; + break; + + case LSM6DSL_ROUND_SH1_TO_SH6: + *val = LSM6DSL_ROUND_SH1_TO_SH6; + break; + + case LSM6DSL_ROUND_XL_SH1_TO_SH6: + *val = LSM6DSL_ROUND_XL_SH1_TO_SH6; + break; + + case LSM6DSL_ROUND_GY_XL_SH1_TO_SH12: + *val = LSM6DSL_ROUND_GY_XL_SH1_TO_SH12; + break; + + case LSM6DSL_ROUND_GY_XL_SH1_TO_SH6: + *val = LSM6DSL_ROUND_GY_XL_SH1_TO_SH6; + break; + + default: + *val = LSM6DSL_ROUND_OUT_ND; + break; + } + + return ret; +} + +/** + * @brief Temperature data output register (r). L and H registers together + * express a 16-bit word in two鈥檚 complement.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_temperature_raw_get(dev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUT_TEMP_L, buff, 2); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor. The value is expressed as a 16-bit word in + * two鈥檚 complement.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_angular_rate_raw_get(dev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUTX_L_G, buff, 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration output register. The value is expressed + * as a 16-bit word in two鈥檚 complement.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_acceleration_raw_get(dev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUTX_L_XL, buff, 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief External magnetometer raw data.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_mag_calibrated_raw_get(dev_ctx_t *ctx, + int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUT_MAG_RAW_X_L, buff, 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Read data in FIFO.[get] + * + * @param ctx Read / write interface definitions + * @param buffer Data buffer to store FIFO data. + * @param len Number of data to read from FIFO. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_raw_data_get(dev_ctx_t *ctx, uint8_t *buffer, + uint8_t len) +{ + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_DATA_OUT_L, buffer, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_common + * @brief This section groups common useful functions. + * @{ + * + */ + +/** + * @brief Enable access to the embedded functions/sensor hub + * configuration registers[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of func_cfg_en in reg FUNC_CFG_ACCESS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_mem_bank_set(dev_ctx_t *ctx, + lsm6dsl_func_cfg_en_t val) +{ + lsm6dsl_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.func_cfg_en = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enable access to the embedded functions/sensor hub configuration + * registers[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of func_cfg_en in reg FUNC_CFG_ACCESS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_mem_bank_get(dev_ctx_t *ctx, + lsm6dsl_func_cfg_en_t *val) +{ + lsm6dsl_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + + switch (func_cfg_access.func_cfg_en) + { + case LSM6DSL_USER_BANK: + *val = LSM6DSL_USER_BANK; + break; + + case LSM6DSL_BANK_B: + *val = LSM6DSL_BANK_B; + break; + + default: + *val = LSM6DSL_BANK_ND; + break; + } + + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of drdy_pulsed in reg DRDY_PULSE_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_data_ready_mode_set(dev_ctx_t *ctx, + lsm6dsl_drdy_pulsed_g_t val) +{ + lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G, + (uint8_t *)&drdy_pulse_cfg_g, 1); + + if (ret == 0) + { + drdy_pulse_cfg_g.drdy_pulsed = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G, + (uint8_t *)&drdy_pulse_cfg_g, 1); + } + + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of drdy_pulsed in reg DRDY_PULSE_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_data_ready_mode_get(dev_ctx_t *ctx, + lsm6dsl_drdy_pulsed_g_t *val) +{ + lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G, + (uint8_t *)&drdy_pulse_cfg_g, 1); + + switch (drdy_pulse_cfg_g.drdy_pulsed) + { + case LSM6DSL_DRDY_LATCHED: + *val = LSM6DSL_DRDY_LATCHED; + break; + + case LSM6DSL_DRDY_PULSED: + *val = LSM6DSL_DRDY_PULSED; + break; + + default: + *val = LSM6DSL_DRDY_ND; + break; + } + + return ret; +} + +/** + * @brief DeviceWhoamI.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_device_id_get(dev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WHO_AM_I, buff, 1); + + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sw_reset in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_reset_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.sw_reset = val; + ret = lsm6dsl_write_reg(ctx, 0x12, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sw_reset in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_reset_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.sw_reset; + + return ret; +} + +/** + * @brief Big/Little Endian Data selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ble in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_data_format_set(dev_ctx_t *ctx, lsm6dsl_ble_t val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.ble = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Big/Little Endian Data selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of ble in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_data_format_get(dev_ctx_t *ctx, lsm6dsl_ble_t *val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.ble) + { + case LSM6DSL_LSB_AT_LOW_ADD: + *val = LSM6DSL_LSB_AT_LOW_ADD; + break; + + case LSM6DSL_MSB_AT_LOW_ADD: + *val = LSM6DSL_MSB_AT_LOW_ADD; + break; + + default: + *val = LSM6DSL_DATA_FMT_ND; + break; + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of if_inc in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_auto_increment_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.if_inc = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of if_inc in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_auto_increment_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.if_inc; + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of boot in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_boot_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.boot = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of boot in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_boot_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.boot; + + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of st_xl in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_self_test_set(dev_ctx_t *ctx, + lsm6dsl_st_xl_t val) +{ + lsm6dsl_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + if (ret == 0) + { + ctrl5_c.st_xl = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of st_xl in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_self_test_get(dev_ctx_t *ctx, + lsm6dsl_st_xl_t *val) +{ + lsm6dsl_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch (ctrl5_c.st_xl) + { + case LSM6DSL_XL_ST_DISABLE: + *val = LSM6DSL_XL_ST_DISABLE; + break; + + case LSM6DSL_XL_ST_POSITIVE: + *val = LSM6DSL_XL_ST_POSITIVE; + break; + + case LSM6DSL_XL_ST_NEGATIVE: + *val = LSM6DSL_XL_ST_NEGATIVE; + break; + + default: + *val = LSM6DSL_XL_ST_ND; + break; + } + + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of st_g in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_self_test_set(dev_ctx_t *ctx, + lsm6dsl_st_g_t val) +{ + lsm6dsl_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + if (ret == 0) + { + ctrl5_c.st_g = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of st_g in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_self_test_get(dev_ctx_t *ctx, + lsm6dsl_st_g_t *val) +{ + lsm6dsl_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch (ctrl5_c.st_g) + { + case LSM6DSL_GY_ST_DISABLE: + *val = LSM6DSL_GY_ST_DISABLE; + break; + + case LSM6DSL_GY_ST_POSITIVE: + *val = LSM6DSL_GY_ST_POSITIVE; + break; + + case LSM6DSL_GY_ST_NEGATIVE: + *val = LSM6DSL_GY_ST_NEGATIVE; + break; + + default: + *val = LSM6DSL_GY_ST_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_filters + * @brief This section group all the functions concerning the filters + * configuration that impact both accelerometer and gyro. + * @{ + * + */ + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of drdy_mask in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_filter_settling_mask_set(dev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ctrl4_c.drdy_mask = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + + return ret; +} + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of drdy_mask in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_filter_settling_mask_get(dev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.drdy_mask; + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of slope_fds in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_hp_path_internal_set(dev_ctx_t *ctx, + lsm6dsl_slope_fds_t val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret == 0) + { + tap_cfg.slope_fds = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + } + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of slope_fds in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_hp_path_internal_get(dev_ctx_t *ctx, + lsm6dsl_slope_fds_t *val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + switch (tap_cfg.slope_fds) + { + case LSM6DSL_USE_SLOPE: + *val = LSM6DSL_USE_SLOPE; + break; + + case LSM6DSL_USE_HPF: + *val = LSM6DSL_USE_HPF; + break; + + default: + *val = LSM6DSL_HP_PATH_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_accelerometer_filters + * @brief This section group all the functions concerning the filters + * configuration that impact accelerometer in every mode. + * @{ + * + */ + +/** + * @brief Accelerometer analog chain bandwidth selection (only for + * accelerometer ODR 鈮 1.67 kHz).[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of bw0_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_filter_analog_set(dev_ctx_t *ctx, + lsm6dsl_bw0_xl_t val) +{ + lsm6dsl_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + if (ret == 0) + { + ctrl1_xl.bw0_xl = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + } + + return ret; +} + +/** + * @brief Accelerometer analog chain bandwidth selection (only for + * accelerometer ODR 鈮 1.67 kHz).[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of bw0_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_filter_analog_get(dev_ctx_t *ctx, + lsm6dsl_bw0_xl_t *val) +{ + lsm6dsl_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + switch (ctrl1_xl.bw0_xl) + { + case LSM6DSL_XL_ANA_BW_1k5Hz: + *val = LSM6DSL_XL_ANA_BW_1k5Hz; + break; + + case LSM6DSL_XL_ANA_BW_400Hz: + *val = LSM6DSL_XL_ANA_BW_400Hz; + break; + + default: + *val = LSM6DSL_XL_ANA_BW_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_accelerometer_filters + * @brief This section group all the functions concerning the filters + * configuration that impact accelerometer. + * @{ + * + */ + +/** + * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2 is + * not used.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of lpf1_bw_sel in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_lp1_bandwidth_set(dev_ctx_t *ctx, + lsm6dsl_lpf1_bw_sel_t val) +{ + lsm6dsl_ctrl1_xl_t ctrl1_xl; + lsm6dsl_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + if (ret == 0) + { + ctrl1_xl.lpf1_bw_sel = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ret == 0) + { + ctrl8_xl.lpf2_xl_en = 0; + ctrl8_xl.hp_slope_xl_en = 0; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + } + } + } + + return ret; +} + +/** + * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2 + * is not used.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of lpf1_bw_sel in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_lp1_bandwidth_get(dev_ctx_t *ctx, + lsm6dsl_lpf1_bw_sel_t *val) +{ + lsm6dsl_ctrl1_xl_t ctrl1_xl; + lsm6dsl_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ret == 0) + { + if ((ctrl8_xl.lpf2_xl_en != 0x00U) || + (ctrl8_xl.hp_slope_xl_en != 0x00U)) + { + *val = LSM6DSL_XL_LP1_NA; + } + + else + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + switch (ctrl1_xl.lpf1_bw_sel) + { + case LSM6DSL_XL_LP1_ODR_DIV_2: + *val = LSM6DSL_XL_LP1_ODR_DIV_2; + break; + + case LSM6DSL_XL_LP1_ODR_DIV_4: + *val = LSM6DSL_XL_LP1_ODR_DIV_4; + break; + + default: + *val = LSM6DSL_XL_LP1_NA; + break; + } + } + } + + return ret; +} + +/** + * @brief LPF2 on outputs[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of input_composite in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_lp2_bandwidth_set(dev_ctx_t *ctx, + lsm6dsl_input_composite_t val) +{ + lsm6dsl_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ret == 0) + { + ctrl8_xl.input_composite = ((uint8_t) val & 0x10U) >> 4; + ctrl8_xl.hpcf_xl = (uint8_t) val & 0x03U; + ctrl8_xl.lpf2_xl_en = 1; + ctrl8_xl.hp_slope_xl_en = 0; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + } + + return ret; +} + +/** + * @brief LPF2 on outputs[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of input_composite in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_lp2_bandwidth_get(dev_ctx_t *ctx, + lsm6dsl_input_composite_t *val) +{ + lsm6dsl_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ret == 0) + { + if ((ctrl8_xl.lpf2_xl_en == 0x00U) || + (ctrl8_xl.hp_slope_xl_en != 0x00U)) + { + *val = LSM6DSL_XL_LP_NA; + } + + else + { + switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl) + { + case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_50: + *val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_50; + break; + + case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_100: + *val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_100; + break; + + case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_9: + *val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_9; + break; + + case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_400: + *val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_400; + break; + + case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_50: + *val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_50; + break; + + case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_100: + *val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_100; + break; + + case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_9: + *val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_9; + break; + + case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_400: + *val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_400; + break; + + default: + *val = LSM6DSL_XL_LP_NA; + break; + } + } + } + + return ret; +} + +/** + * @brief Enable HP filter reference mode.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of hp_ref_mode in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_reference_mode_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ret == 0) + { + ctrl8_xl.hp_ref_mode = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + } + + return ret; +} + +/** + * @brief Enable HP filter reference mode.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of hp_ref_mode in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_reference_mode_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + *val = ctrl8_xl.hp_ref_mode; + + return ret; +} + +/** + * @brief High pass/Slope on outputs.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of hpcf_xl in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_hp_bandwidth_set(dev_ctx_t *ctx, + lsm6dsl_hpcf_xl_t val) +{ + lsm6dsl_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ret == 0) + { + ctrl8_xl.input_composite = 0; + ctrl8_xl.hpcf_xl = (uint8_t)val & 0x03U; + ctrl8_xl.hp_slope_xl_en = 1; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + } + + return ret; +} + +/** + * @brief High pass/Slope on outputs.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of hpcf_xl in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_xl_hp_bandwidth_get(dev_ctx_t *ctx, + lsm6dsl_hpcf_xl_t *val) +{ + lsm6dsl_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ctrl8_xl.hp_slope_xl_en == 0x00U) + { + *val = LSM6DSL_XL_HP_NA; + } + + switch (ctrl8_xl.hpcf_xl) + { + case LSM6DSL_XL_HP_ODR_DIV_4: + *val = LSM6DSL_XL_HP_ODR_DIV_4; + break; + + case LSM6DSL_XL_HP_ODR_DIV_100: + *val = LSM6DSL_XL_HP_ODR_DIV_100; + break; + + case LSM6DSL_XL_HP_ODR_DIV_9: + *val = LSM6DSL_XL_HP_ODR_DIV_9; + break; + + case LSM6DSL_XL_HP_ODR_DIV_400: + *val = LSM6DSL_XL_HP_ODR_DIV_400; + break; + + default: + *val = LSM6DSL_XL_HP_NA; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_gyroscope_filters + * @brief This section group all the functions concerning the filters + * configuration that impact gyroscope. + * @{ + * + */ + +/** + * @brief Gyroscope low pass path bandwidth.[set] + * + * @param ctx Read / write interface definitions + * @param val gyroscope filtering chain configuration. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_band_pass_set(dev_ctx_t *ctx, + lsm6dsl_lpf1_sel_g_t val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + lsm6dsl_ctrl6_c_t ctrl6_c; + lsm6dsl_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + if (ret == 0) + { + ctrl7_g.hpm_g = ((uint8_t)val & 0x30U) >> 4; + ctrl7_g.hp_en_g = ((uint8_t)val & 0x80U) >> 7; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + if (ret == 0) + { + ctrl6_c.ftype = (uint8_t)val & 0x03U; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, + (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ctrl4_c.lpf1_sel_g = ((uint8_t)val & 0x08U) >> 3; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, + (uint8_t *)&ctrl4_c, 1); + } + } + } + } + } + + return ret; +} + +/** + * @brief Gyroscope low pass path bandwidth.[get] + * + * @param ctx Read / write interface definitions + * @param val gyroscope filtering chain + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_band_pass_get(dev_ctx_t *ctx, + lsm6dsl_lpf1_sel_g_t *val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + lsm6dsl_ctrl6_c_t ctrl6_c; + lsm6dsl_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) + + (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype) + { + case LSM6DSL_HP_16mHz_LP2: + *val = LSM6DSL_HP_16mHz_LP2; + break; + + case LSM6DSL_HP_65mHz_LP2: + *val = LSM6DSL_HP_65mHz_LP2; + break; + + case LSM6DSL_HP_260mHz_LP2: + *val = LSM6DSL_HP_260mHz_LP2; + break; + + case LSM6DSL_HP_1Hz04_LP2: + *val = LSM6DSL_HP_1Hz04_LP2; + break; + + case LSM6DSL_HP_DISABLE_LP1_LIGHT: + *val = LSM6DSL_HP_DISABLE_LP1_LIGHT; + break; + + case LSM6DSL_HP_DISABLE_LP1_NORMAL: + *val = LSM6DSL_HP_DISABLE_LP1_NORMAL; + break; + + case LSM6DSL_HP_DISABLE_LP_STRONG: + *val = LSM6DSL_HP_DISABLE_LP_STRONG; + break; + + case LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE: + *val = LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE; + break; + + case LSM6DSL_HP_16mHz_LP1_LIGHT: + *val = LSM6DSL_HP_16mHz_LP1_LIGHT; + break; + + case LSM6DSL_HP_65mHz_LP1_NORMAL: + *val = LSM6DSL_HP_65mHz_LP1_NORMAL; + break; + + case LSM6DSL_HP_260mHz_LP1_STRONG: + *val = LSM6DSL_HP_260mHz_LP1_STRONG; + break; + + case LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE: + *val = LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE; + break; + + default: + *val = LSM6DSL_HP_GY_BAND_NA; + break; + } + } + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_serial_interface + * @brief This section groups all the functions concerning serial + * interface management + * @{ + * + */ + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sim in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_spi_mode_set(dev_ctx_t *ctx, lsm6dsl_sim_t val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.sim = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of sim in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_spi_mode_get(dev_ctx_t *ctx, lsm6dsl_sim_t *val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.sim) + { + case LSM6DSL_SPI_4_WIRE: + *val = LSM6DSL_SPI_4_WIRE; + break; + + case LSM6DSL_SPI_3_WIRE: + *val = LSM6DSL_SPI_3_WIRE; + break; + + default: + *val = LSM6DSL_SPI_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of i2c_disable in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_i2c_interface_set(dev_ctx_t *ctx, + lsm6dsl_i2c_disable_t val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ctrl4_c.i2c_disable = (uint8_t)val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of i2c_disable in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_i2c_interface_get(dev_ctx_t *ctx, + lsm6dsl_i2c_disable_t *val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + switch (ctrl4_c.i2c_disable) + { + case LSM6DSL_I2C_ENABLE: + *val = LSM6DSL_I2C_ENABLE; + break; + + case LSM6DSL_I2C_DISABLE: + *val = LSM6DSL_I2C_DISABLE; + break; + + default: + *val = LSM6DSL_I2C_MODE_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_interrupt_pins + * @brief This section groups all the functions that manage + * interrupt pins + * @{ + * + */ + +/** + * @brief Select the signal that need to route on int1 pad[set] + * + * @param ctx Read / write interface definitions + * @param val configure INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1), + * MASTER_CONFIG(drdy_on_int1) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pin_int1_route_set(dev_ctx_t *ctx, + lsm6dsl_int1_route_t val) +{ + lsm6dsl_master_config_t master_config; + lsm6dsl_int1_ctrl_t int1_ctrl; + lsm6dsl_md1_cfg_t md1_cfg; + lsm6dsl_md2_cfg_t md2_cfg; + lsm6dsl_ctrl4_c_t ctrl4_c; + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + if (ret == 0) + { + int1_ctrl.int1_drdy_xl = val.int1_drdy_xl; + int1_ctrl.int1_drdy_g = val.int1_drdy_g; + int1_ctrl.int1_boot = val.int1_boot; + int1_ctrl.int1_fth = val.int1_fth; + int1_ctrl.int1_fifo_ovr = val.int1_fifo_ovr; + int1_ctrl.int1_full_flag = val.int1_full_flag; + int1_ctrl.int1_sign_mot = val.int1_sign_mot; + int1_ctrl.int1_step_detector = val.int1_step_detector; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + md1_cfg.int1_timer = val.int1_timer; + md1_cfg.int1_tilt = val.int1_tilt; + md1_cfg.int1_6d = val.int1_6d; + md1_cfg.int1_double_tap = val.int1_double_tap; + md1_cfg.int1_ff = val.int1_ff; + md1_cfg.int1_wu = val.int1_wu; + md1_cfg.int1_single_tap = val.int1_single_tap; + md1_cfg.int1_inact_state = val.int1_inact_state; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + + if (ret == 0) + { + ctrl4_c.den_drdy_int1 = val.den_drdy_int1; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.drdy_on_int1 = val.den_drdy_int1; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if ((val.int1_6d != 0x00U) || + (val.int1_ff != 0x00U) || + (val.int1_wu != 0x00U) || + (val.int1_single_tap != 0x00U) || + (val.int1_double_tap != 0x00U) || + (val.int1_inact_state != 0x00U) || + (md2_cfg.int2_6d != 0x00U) || + (md2_cfg.int2_ff != 0x00U) || + (md2_cfg.int2_wu != 0x00U) || + (md2_cfg.int2_single_tap != 0x00U) || + (md2_cfg.int2_double_tap != 0x00U) || + (md2_cfg.int2_inact_state != 0x00U)) + { + tap_cfg.interrupts_enable = PROPERTY_ENABLE; + } + + else + { + tap_cfg.interrupts_enable = PROPERTY_DISABLE; + } + } + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + } + + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad[get] + * + * @param ctx Read / write interface definitions + * @param val read INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1), + * MASTER_CONFIG(drdy_on_int1) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pin_int1_route_get(dev_ctx_t *ctx, + lsm6dsl_int1_route_t *val) +{ + lsm6dsl_master_config_t master_config; + lsm6dsl_int1_ctrl_t int1_ctrl; + lsm6dsl_md1_cfg_t md1_cfg; + lsm6dsl_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + if (ret == 0) + { + val->int1_drdy_xl = int1_ctrl.int1_drdy_xl; + val->int1_drdy_g = int1_ctrl.int1_drdy_g; + val->int1_boot = int1_ctrl.int1_boot; + val->int1_fth = int1_ctrl.int1_fth; + val->int1_fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->int1_full_flag = int1_ctrl.int1_full_flag; + val->int1_sign_mot = int1_ctrl.int1_sign_mot; + val->int1_step_detector = int1_ctrl.int1_step_detector ; + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + if (ret == 0) + { + val->int1_timer = md1_cfg.int1_timer; + val->int1_tilt = md1_cfg.int1_tilt; + val->int1_6d = md1_cfg.int1_6d; + val->int1_double_tap = md1_cfg.int1_double_tap; + val->int1_ff = md1_cfg.int1_ff; + val->int1_wu = md1_cfg.int1_wu; + val->int1_single_tap = md1_cfg.int1_single_tap; + val->int1_inact_state = md1_cfg.int1_inact_state; + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + val->den_drdy_int1 = ctrl4_c.den_drdy_int1; + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + val->den_drdy_int1 = master_config.drdy_on_int1; + } + } + } + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad[set] + * + * @param ctx Read / write interface definitions + * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pin_int2_route_set(dev_ctx_t *ctx, + lsm6dsl_int2_route_t val) +{ + lsm6dsl_int2_ctrl_t int2_ctrl; + lsm6dsl_md1_cfg_t md1_cfg; + lsm6dsl_md2_cfg_t md2_cfg; + lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + if (ret == 0) + { + int2_ctrl.int2_drdy_xl = val.int2_drdy_xl; + int2_ctrl.int2_drdy_g = val.int2_drdy_g; + int2_ctrl.int2_drdy_temp = val.int2_drdy_temp; + int2_ctrl.int2_fth = val.int2_fth; + int2_ctrl.int2_fifo_ovr = val.int2_fifo_ovr; + int2_ctrl.int2_full_flag = val.int2_full_flag; + int2_ctrl.int2_step_count_ov = val.int2_step_count_ov; + int2_ctrl.int2_step_delta = val.int2_step_delta; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + md2_cfg.int2_iron = val.int2_iron; + md2_cfg.int2_tilt = val.int2_tilt; + md2_cfg.int2_6d = val.int2_6d; + md2_cfg.int2_double_tap = val.int2_double_tap; + md2_cfg.int2_ff = val.int2_ff; + md2_cfg.int2_wu = val.int2_wu; + md2_cfg.int2_single_tap = val.int2_single_tap; + md2_cfg.int2_inact_state = val.int2_inact_state; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G, + (uint8_t *)&drdy_pulse_cfg_g, 1); + } + + if (ret == 0) + { + drdy_pulse_cfg_g.int2_wrist_tilt = val.int2_wrist_tilt; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G, + (uint8_t *)&drdy_pulse_cfg_g, 1); + } + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if ((md1_cfg.int1_6d != 0x00U) || + (md1_cfg.int1_ff != 0x00U) || + (md1_cfg.int1_wu != 0x00U) || + (md1_cfg.int1_single_tap != 0x00U) || + (md1_cfg.int1_double_tap != 0x00U) || + (md1_cfg.int1_inact_state != 0x00U) || + (val.int2_6d != 0x00U) || + (val.int2_ff != 0x00U) || + (val.int2_wu != 0x00U) || + (val.int2_single_tap != 0x00U) || + (val.int2_double_tap != 0x00U) || + (val.int2_inact_state != 0x00U)) + { + tap_cfg.interrupts_enable = PROPERTY_ENABLE; + } + + else + { + tap_cfg.interrupts_enable = PROPERTY_DISABLE; + } + } + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + } + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad[get] + * + * @param ctx Read / write interface definitions + * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pin_int2_route_get(dev_ctx_t *ctx, + lsm6dsl_int2_route_t *val) +{ + lsm6dsl_int2_ctrl_t int2_ctrl; + lsm6dsl_md2_cfg_t md2_cfg; + lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + if (ret == 0) + { + val->int2_drdy_xl = int2_ctrl.int2_drdy_xl; + val->int2_drdy_g = int2_ctrl.int2_drdy_g; + val->int2_drdy_temp = int2_ctrl.int2_drdy_temp; + val->int2_fth = int2_ctrl.int2_fth; + val->int2_fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->int2_full_flag = int2_ctrl.int2_full_flag; + val->int2_step_count_ov = int2_ctrl.int2_step_count_ov; + val->int2_step_delta = int2_ctrl.int2_step_delta; + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + if (ret == 0) + { + val->int2_iron = md2_cfg.int2_iron; + val->int2_tilt = md2_cfg.int2_tilt; + val->int2_6d = md2_cfg.int2_6d; + val->int2_double_tap = md2_cfg.int2_double_tap; + val->int2_ff = md2_cfg.int2_ff; + val->int2_wu = md2_cfg.int2_wu; + val->int2_single_tap = md2_cfg.int2_single_tap; + val->int2_inact_state = md2_cfg.int2_inact_state; + ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G, + (uint8_t *)&drdy_pulse_cfg_g, 1); + val->int2_wrist_tilt = drdy_pulse_cfg_g.int2_wrist_tilt; + } + } + + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pp_od in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pin_mode_set(dev_ctx_t *ctx, lsm6dsl_pp_od_t val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.pp_od = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of pp_od in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pin_mode_get(dev_ctx_t *ctx, lsm6dsl_pp_od_t *val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.pp_od) + { + case LSM6DSL_PUSH_PULL: + *val = LSM6DSL_PUSH_PULL; + break; + + case LSM6DSL_OPEN_DRAIN: + *val = LSM6DSL_OPEN_DRAIN; + break; + + default: + *val = LSM6DSL_PIN_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief Interrupt active-high/low.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of h_lactive in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pin_polarity_set(dev_ctx_t *ctx, + lsm6dsl_h_lactive_t val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.h_lactive = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Interrupt active-high/low.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of h_lactive in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pin_polarity_get(dev_ctx_t *ctx, + lsm6dsl_h_lactive_t *val) +{ + lsm6dsl_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.h_lactive) + { + case LSM6DSL_ACTIVE_HIGH: + *val = LSM6DSL_ACTIVE_HIGH; + break; + + case LSM6DSL_ACTIVE_LOW: + *val = LSM6DSL_ACTIVE_LOW; + break; + + default: + *val = LSM6DSL_POLARITY_ND; + break; + } + + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of int2_on_int1 in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_all_on_int1_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ctrl4_c.int2_on_int1 = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of int2_on_int1 in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_all_on_int1_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.int2_on_int1; + + return ret; +} + +/** + * @brief Latched/pulsed interrupt.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of lir in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_int_notification_set(dev_ctx_t *ctx, + lsm6dsl_lir_t val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret == 0) + { + tap_cfg.lir = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + } + + return ret; +} + +/** + * @brief Latched/pulsed interrupt.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of lir in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_int_notification_get(dev_ctx_t *ctx, + lsm6dsl_lir_t *val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + switch (tap_cfg.lir) + { + case LSM6DSL_INT_PULSED: + *val = LSM6DSL_INT_PULSED; + break; + + case LSM6DSL_INT_LATCHED: + *val = LSM6DSL_INT_LATCHED; + break; + + default: + *val = LSM6DSL_INT_MODE; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_Wake_Up_event + * @brief This section groups all the functions that manage the + * Wake Up event generation. + * @{ + * + */ + +/** + * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of wk_ths in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_wkup_threshold_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + + if (ret == 0) + { + wake_up_ths.wk_ths = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of wk_ths in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_wkup_threshold_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + *val = wake_up_ths.wk_ths; + + return ret; +} + +/** + * @brief Wake up duration event.1LSb = 1 / ODR[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of wake_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_wkup_dur_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + wake_up_dur.wake_dur = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + + return ret; +} + +/** + * @brief Wake up duration event.1LSb = 1 / ODR[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of wake_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_wkup_dur_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + *val = wake_up_dur.wake_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_Activity/Inactivity_detection + * @brief This section groups all the functions concerning + * activity/inactivity detection. + * @{ + * + */ + +/** + * @brief Enables gyroscope Sleep mode.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sleep in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_sleep_mode_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ctrl4_c.sleep = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + + return ret; +} + +/** + * @brief Enables gyroscope Sleep mode.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sleep in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_gy_sleep_mode_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.sleep; + + return ret; +} + +/** + * @brief Enable inactivity function.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of inact_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_act_mode_set(dev_ctx_t *ctx, + lsm6dsl_inact_en_t val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret == 0) + { + tap_cfg.inact_en = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + } + + return ret; +} + +/** + * @brief Enable inactivity function.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of inact_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_act_mode_get(dev_ctx_t *ctx, + lsm6dsl_inact_en_t *val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + switch (tap_cfg.inact_en) + { + case LSM6DSL_PROPERTY_DISABLE: + *val = LSM6DSL_PROPERTY_DISABLE; + break; + + case LSM6DSL_XL_12Hz5_GY_NOT_AFFECTED: + *val = LSM6DSL_XL_12Hz5_GY_NOT_AFFECTED; + break; + + case LSM6DSL_XL_12Hz5_GY_SLEEP: + *val = LSM6DSL_XL_12Hz5_GY_SLEEP; + break; + + case LSM6DSL_XL_12Hz5_GY_PD: + *val = LSM6DSL_XL_12Hz5_GY_PD; + break; + + default: + *val = LSM6DSL_ACT_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief Duration to go in sleep mode.1 LSb = 512 / ODR[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sleep_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_act_sleep_dur_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + wake_up_dur.sleep_dur = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + + return ret; +} + +/** + * @brief Duration to go in sleep mode. 1 LSb = 512 / ODR[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sleep_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_act_sleep_dur_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + *val = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_tap_generator + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Read the tap / double tap source register.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure of registers from TAP_SRC + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_src_get(dev_ctx_t *ctx, lsm6dsl_tap_src_t *val) +{ + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_SRC, (uint8_t *) val, 1); + + return ret; +} + +/** + * @brief Enable Z direction in tap recognition.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_z_en in reg TAP_CFG + * + */ +int32_t lsm6dsl_tap_detection_on_z_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret == 0) + { + tap_cfg.tap_z_en = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + } + + return ret; +} + +/** + * @brief Enable Z direction in tap recognition.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_z_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_detection_on_z_get(dev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + *val = tap_cfg.tap_z_en; + + return ret; +} + +/** + * @brief Enable Y direction in tap recognition.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_y_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_detection_on_y_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret == 0) + { + tap_cfg.tap_y_en = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + } + + return ret; +} + +/** + * @brief Enable Y direction in tap recognition.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_y_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_detection_on_y_get(dev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + *val = tap_cfg.tap_y_en; + + return ret; +} + +/** + * @brief Enable X direction in tap recognition.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_x_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_detection_on_x_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret == 0) + { + tap_cfg.tap_x_en = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + } + + return ret; +} + +/** + * @brief Enable X direction in tap recognition.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_x_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_detection_on_x_get(dev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsl_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + *val = tap_cfg.tap_x_en; + + return ret; +} + +/** + * @brief Threshold for tap recognition.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_threshold_x_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, + (uint8_t *)&tap_ths_6d, 1); + + if (ret == 0) + { + tap_ths_6d.tap_ths = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_THS_6D, + (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief Threshold for tap recognition.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_threshold_x_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, + (uint8_t *)&tap_ths_6d, 1); + *val = tap_ths_6d.tap_ths; + + return ret; +} + +/** + * @brief Maximum duration is the maximum time of an overthreshold signal + * detection to be recognized as a tap event. + * The default value of these bits is 00b which corresponds to + * 4*ODR_XL time. + * If the SHOCK[1:0] bits are set to a different + * value, 1LSB corresponds to 8*ODR_XL time.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of shock in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_shock_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret == 0) + { + int_dur2.shock = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + } + + return ret; +} + +/** + * @brief Maximum duration is the maximum time of an overthreshold signal + * detection to be recognized as a tap event. + * The default value of these bits is 00b which corresponds to + * 4*ODR_XL time. + * If the SHOCK[1:0] bits are set to a different value, 1LSB + * corresponds to 8*ODR_XL time.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of shock in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_shock_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + *val = int_dur2.shock; + + return ret; +} + +/** + * @brief Quiet time is the time after the first detected tap in which there + * must not be any overthreshold event. + * The default value of these bits is 00b which corresponds to + * 2*ODR_XL time. + * If the QUIET[1:0] bits are set to a different value, 1LSB + * corresponds to 4*ODR_XL time.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of quiet in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_quiet_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret == 0) + { + int_dur2.quiet = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + } + + return ret; +} + +/** + * @brief Quiet time is the time after the first detected tap in which there + * must not be any overthreshold event. + * The default value of these bits is 00b which corresponds to + * 2*ODR_XL time. + * If the QUIET[1:0] bits are set to a different value, 1LSB + * corresponds to 4*ODR_XL time.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of quiet in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_quiet_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + *val = int_dur2.quiet; + + return ret; +} + +/** + * @brief When double tap recognition is enabled, this register expresses the + * maximum time between two consecutive detected taps to determine a + * double tap event. + * The default value of these bits is 0000b which corresponds to + * 16*ODR_XL time. + * If the DUR[3:0] bits are set to a different value,1LSB corresponds + * to 32*ODR_XL time.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dur in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_dur_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret == 0) + { + int_dur2.dur = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + } + + return ret; +} + +/** + * @brief When double tap recognition is enabled, this register expresses the + * maximum time between two consecutive detected taps to determine a + * double tap event. + * The default value of these bits is 0000b which corresponds to + * 16*ODR_XL time. + * If the DUR[3:0] bits are set to a different value,1LSB corresponds + * to 32*ODR_XL time.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dur in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_dur_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + *val = int_dur2.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable/disable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of + * single_double_tap in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_mode_set(dev_ctx_t *ctx, + lsm6dsl_single_double_tap_t val) +{ + lsm6dsl_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + + if (ret == 0) + { + wake_up_ths.single_double_tap = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Single/double-tap event enable/disable.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of single_double_tap + * in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tap_mode_get(dev_ctx_t *ctx, + lsm6dsl_single_double_tap_t *val) +{ + lsm6dsl_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + + switch (wake_up_ths.single_double_tap) + { + case LSM6DSL_ONLY_SINGLE: + *val = LSM6DSL_ONLY_SINGLE; + break; + + case LSM6DSL_BOTH_SINGLE_DOUBLE: + *val = LSM6DSL_BOTH_SINGLE_DOUBLE; + break; + + default: + *val = LSM6DSL_TAP_MODE_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_ Six_position_detection(6D/4D) + * @brief This section groups all the functions concerning six + * position detection (6D). + * @{ + * + */ + +/** + * @brief LPF2 feed 6D function selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of low_pass_on_6d in + * reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_6d_feed_data_set(dev_ctx_t *ctx, + lsm6dsl_low_pass_on_6d_t val) +{ + lsm6dsl_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ret == 0) + { + ctrl8_xl.low_pass_on_6d = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + } + + return ret; +} + +/** + * @brief LPF2 feed 6D function selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of low_pass_on_6d in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_6d_feed_data_get(dev_ctx_t *ctx, + lsm6dsl_low_pass_on_6d_t *val) +{ + lsm6dsl_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + switch (ctrl8_xl.low_pass_on_6d) + { + case LSM6DSL_ODR_DIV_2_FEED: + *val = LSM6DSL_ODR_DIV_2_FEED; + break; + + case LSM6DSL_LPF2_FEED: + *val = LSM6DSL_LPF2_FEED; + break; + + default: + *val = LSM6DSL_6D_FEED_ND; + break; + } + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sixd_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_6d_threshold_set(dev_ctx_t *ctx, + lsm6dsl_sixd_ths_t val) +{ + lsm6dsl_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, + (uint8_t *)&tap_ths_6d, 1); + + if (ret == 0) + { + tap_ths_6d.sixd_ths = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_THS_6D, + (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of sixd_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_6d_threshold_get(dev_ctx_t *ctx, + lsm6dsl_sixd_ths_t *val) +{ + lsm6dsl_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, + (uint8_t *)&tap_ths_6d, 1); + + switch (tap_ths_6d.sixd_ths) + { + case LSM6DSL_DEG_80: + *val = LSM6DSL_DEG_80; + break; + + case LSM6DSL_DEG_70: + *val = LSM6DSL_DEG_70; + break; + + case LSM6DSL_DEG_60: + *val = LSM6DSL_DEG_60; + break; + + case LSM6DSL_DEG_50: + *val = LSM6DSL_DEG_50; + break; + + default: + *val = LSM6DSL_6D_TH_ND; + break; + } + + return ret; +} + +/** + * @brief 4D orientation detection enable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of d4d_en in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_4d_mode_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, + (uint8_t *)&tap_ths_6d, 1); + + if (ret == 0) + { + tap_ths_6d.d4d_en = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_THS_6D, + (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief 4D orientation detection enable.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of d4d_en in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_4d_mode_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, + (uint8_t *)&tap_ths_6d, 1); + *val = tap_ths_6d.d4d_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_free_fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Free-fall duration event. 1LSb = 1 / ODR[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ff_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_ff_dur_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_wake_up_dur_t wake_up_dur; + lsm6dsl_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1); + + if (ret == 0) + { + free_fall.ff_dur = (val & 0x1FU); + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + wake_up_dur.ff_dur = (val & 0x20U) >> 5; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + } + } + + return ret; +} + +/** + * @brief Free-fall duration event. 1LSb = 1 / ODR[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ff_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_ff_dur_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_wake_up_dur_t wake_up_dur; + lsm6dsl_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ff_ths in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_ff_threshold_set(dev_ctx_t *ctx, + lsm6dsl_ff_ths_t val) +{ + lsm6dsl_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1); + + if (ret == 0) + { + free_fall.ff_ths = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of ff_ths in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_ff_threshold_get(dev_ctx_t *ctx, + lsm6dsl_ff_ths_t *val) +{ + lsm6dsl_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1); + + switch (free_fall.ff_ths) + { + case LSM6DSL_FF_TSH_156mg: + *val = LSM6DSL_FF_TSH_156mg; + break; + + case LSM6DSL_FF_TSH_219mg: + *val = LSM6DSL_FF_TSH_219mg; + break; + + case LSM6DSL_FF_TSH_250mg: + *val = LSM6DSL_FF_TSH_250mg; + break; + + case LSM6DSL_FF_TSH_312mg: + *val = LSM6DSL_FF_TSH_312mg; + break; + + case LSM6DSL_FF_TSH_344mg: + *val = LSM6DSL_FF_TSH_344mg; + break; + + case LSM6DSL_FF_TSH_406mg: + *val = LSM6DSL_FF_TSH_406mg; + break; + + case LSM6DSL_FF_TSH_469mg: + *val = LSM6DSL_FF_TSH_469mg; + break; + + case LSM6DSL_FF_TSH_500mg: + *val = LSM6DSL_FF_TSH_500mg; + break; + + default: + *val = LSM6DSL_FF_TSH_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_fifo + * @brief This section group all the functions concerning the + * fifo usage + * @{ + * + */ + +/** + * @brief FIFO watermark level selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fth in reg FIFO_CTRL1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_watermark_set(dev_ctx_t *ctx, uint16_t val) +{ + lsm6dsl_fifo_ctrl1_t fifo_ctrl1; + lsm6dsl_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + + if (ret == 0) + { + fifo_ctrl1.fth = (uint8_t)(0x00FFU & val); + fifo_ctrl2.fth = (uint8_t)((0x0700U & val) >> 8); + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + } + + return ret; +} + +/** + * @brief FIFO watermark level selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fth in reg FIFO_CTRL1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_watermark_get(dev_ctx_t *ctx, uint16_t *val) +{ + lsm6dsl_fifo_ctrl1_t fifo_ctrl1; + lsm6dsl_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + + *val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth; + + return ret; +} + +/** + * @brief FIFO data level.[get] + * + * @param ctx Read / write interface definitions + * @param val get the values of diff_fifo in reg FIFO_STATUS1 and + * FIFO_STATUS2(diff_fifo), it is recommended to set the + * BDU bit. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_data_level_get(dev_ctx_t *ctx, uint16_t *val) +{ + lsm6dsl_fifo_status1_t fifo_status1; + lsm6dsl_fifo_status2_t fifo_status2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS1, + (uint8_t *)&fifo_status1, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + *val = ((uint16_t) fifo_status2.diff_fifo << 8) + + (uint16_t) fifo_status1.diff_fifo; + } + + return ret; +} + +/** + * @brief FIFO watermark.[get] + * + * @param ctx Read / write interface definitions + * @param val get the values of watermark in reg FIFO_STATUS2 and + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_wtm_flag_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_fifo_status2_t fifo_status2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + *val = fifo_status2.waterm; + + return ret; +} + +/** + * @brief FIFO pattern.[get] + * + * @param ctx Read / write interface definitions + * @param val get the values of fifo_pattern in reg FIFO_STATUS3 and + * FIFO_STATUS4, it is recommended to set the BDU bit + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_pattern_get(dev_ctx_t *ctx, uint16_t *val) +{ + lsm6dsl_fifo_status3_t fifo_status3; + lsm6dsl_fifo_status4_t fifo_status4; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS3, + (uint8_t *)&fifo_status3, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS4, + (uint8_t *)&fifo_status4, 1); + *val = ((uint16_t)fifo_status4.fifo_pattern << 8) + + fifo_status3.fifo_pattern; + } + + return ret; +} + +/** + * @brief Batching of temperature data[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_temp_batch_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + + if (ret == 0) + { + fifo_ctrl2.fifo_temp_en = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Batching of temperature data[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_temp_batch_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.fifo_temp_en; + + return ret; +} + +/** + * @brief Trigger signal for FIFO write operation.[set] + * + * @param ctx Read / write interface definitions + * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy) + * and MASTER_CONFIG(data_valid_sel_fifo) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_write_trigger_set(dev_ctx_t *ctx, + lsm6dsl_trigger_fifo_t val) +{ + lsm6dsl_fifo_ctrl2_t fifo_ctrl2; + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + + if (ret == 0) + { + fifo_ctrl2.timer_pedo_fifo_drdy = (uint8_t)val & 0x01U; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + + if (ret == 0) + { + master_config.data_valid_sel_fifo = (((uint8_t)val & 0x02U) >> 1); + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + } + } + + return ret; +} + +/** + * @brief Trigger signal for FIFO write operation.[get] + * + * @param ctx Read / write interface definitions + * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy) + * and MASTER_CONFIG(data_valid_sel_fifo) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_write_trigger_get(dev_ctx_t *ctx, + lsm6dsl_trigger_fifo_t *val) +{ + lsm6dsl_fifo_ctrl2_t fifo_ctrl2; + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + + switch ((fifo_ctrl2.timer_pedo_fifo_drdy << 1) + + fifo_ctrl2. timer_pedo_fifo_drdy) + { + case LSM6DSL_TRG_XL_GY_DRDY: + *val = LSM6DSL_TRG_XL_GY_DRDY; + break; + + case LSM6DSL_TRG_STEP_DETECT: + *val = LSM6DSL_TRG_STEP_DETECT; + break; + + case LSM6DSL_TRG_SH_DRDY: + *val = LSM6DSL_TRG_SH_DRDY; + break; + + default: + *val = LSM6DSL_TRG_SH_ND; + break; + } + } + + return ret; +} + +/** + * @brief Enable pedometer step counter and timestamp as 4th + * FIFO data set.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_set(dev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsl_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + + if (ret == 0) + { + fifo_ctrl2.timer_pedo_fifo_en = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enable pedometer step counter and timestamp as 4th + * FIFO data set.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(dev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsl_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.timer_pedo_fifo_en; + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) for + * accelerometer data.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dec_fifo_xl in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_xl_batch_set(dev_ctx_t *ctx, + lsm6dsl_dec_fifo_xl_t val) +{ + lsm6dsl_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + + if (ret == 0) + { + fifo_ctrl3.dec_fifo_xl = (uint8_t)val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) for + * accelerometer data.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of dec_fifo_xl in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_xl_batch_get(dev_ctx_t *ctx, + lsm6dsl_dec_fifo_xl_t *val) +{ + lsm6dsl_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + + switch (fifo_ctrl3.dec_fifo_xl) + { + case LSM6DSL_FIFO_XL_DISABLE: + *val = LSM6DSL_FIFO_XL_DISABLE; + break; + + case LSM6DSL_FIFO_XL_NO_DEC: + *val = LSM6DSL_FIFO_XL_NO_DEC; + break; + + case LSM6DSL_FIFO_XL_DEC_2: + *val = LSM6DSL_FIFO_XL_DEC_2; + break; + + case LSM6DSL_FIFO_XL_DEC_3: + *val = LSM6DSL_FIFO_XL_DEC_3; + break; + + case LSM6DSL_FIFO_XL_DEC_4: + *val = LSM6DSL_FIFO_XL_DEC_4; + break; + + case LSM6DSL_FIFO_XL_DEC_8: + *val = LSM6DSL_FIFO_XL_DEC_8; + break; + + case LSM6DSL_FIFO_XL_DEC_16: + *val = LSM6DSL_FIFO_XL_DEC_16; + break; + + case LSM6DSL_FIFO_XL_DEC_32: + *val = LSM6DSL_FIFO_XL_DEC_32; + break; + + default: + *val = LSM6DSL_FIFO_XL_DEC_ND; + break; + } + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dec_fifo_gyro in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_gy_batch_set(dev_ctx_t *ctx, + lsm6dsl_dec_fifo_gyro_t val) +{ + lsm6dsl_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + + if (ret == 0) + { + fifo_ctrl3.dec_fifo_gyro = (uint8_t)val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of dec_fifo_gyro in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_gy_batch_get(dev_ctx_t *ctx, + lsm6dsl_dec_fifo_gyro_t *val) +{ + lsm6dsl_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + + switch (fifo_ctrl3.dec_fifo_gyro) + { + case LSM6DSL_FIFO_GY_DISABLE: + *val = LSM6DSL_FIFO_GY_DISABLE; + break; + + case LSM6DSL_FIFO_GY_NO_DEC: + *val = LSM6DSL_FIFO_GY_NO_DEC; + break; + + case LSM6DSL_FIFO_GY_DEC_2: + *val = LSM6DSL_FIFO_GY_DEC_2; + break; + + case LSM6DSL_FIFO_GY_DEC_3: + *val = LSM6DSL_FIFO_GY_DEC_3; + break; + + case LSM6DSL_FIFO_GY_DEC_4: + *val = LSM6DSL_FIFO_GY_DEC_4; + break; + + case LSM6DSL_FIFO_GY_DEC_8: + *val = LSM6DSL_FIFO_GY_DEC_8; + break; + + case LSM6DSL_FIFO_GY_DEC_16: + *val = LSM6DSL_FIFO_GY_DEC_16; + break; + + case LSM6DSL_FIFO_GY_DEC_32: + *val = LSM6DSL_FIFO_GY_DEC_32; + break; + + default: + *val = LSM6DSL_FIFO_GY_DEC_ND; + break; + } + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for third data set.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dec_ds3_fifo in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_dataset_3_batch_set(dev_ctx_t *ctx, + lsm6dsl_dec_ds3_fifo_t val) +{ + lsm6dsl_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + if (ret == 0) + { + fifo_ctrl4.dec_ds3_fifo = (uint8_t)val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for third data set.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of dec_ds3_fifo in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_dataset_3_batch_get(dev_ctx_t *ctx, + lsm6dsl_dec_ds3_fifo_t *val) +{ + lsm6dsl_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.dec_ds3_fifo) + { + case LSM6DSL_FIFO_DS3_DISABLE: + *val = LSM6DSL_FIFO_DS3_DISABLE; + break; + + case LSM6DSL_FIFO_DS3_NO_DEC: + *val = LSM6DSL_FIFO_DS3_NO_DEC; + break; + + case LSM6DSL_FIFO_DS3_DEC_2: + *val = LSM6DSL_FIFO_DS3_DEC_2; + break; + + case LSM6DSL_FIFO_DS3_DEC_3: + *val = LSM6DSL_FIFO_DS3_DEC_3; + break; + + case LSM6DSL_FIFO_DS3_DEC_4: + *val = LSM6DSL_FIFO_DS3_DEC_4; + break; + + case LSM6DSL_FIFO_DS3_DEC_8: + *val = LSM6DSL_FIFO_DS3_DEC_8; + break; + + case LSM6DSL_FIFO_DS3_DEC_16: + *val = LSM6DSL_FIFO_DS3_DEC_16; + break; + + case LSM6DSL_FIFO_DS3_DEC_32: + *val = LSM6DSL_FIFO_DS3_DEC_32; + break; + + default: + *val = LSM6DSL_FIFO_DS3_DEC_ND; + break; + } + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for fourth data set.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dec_ds4_fifo in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_dataset_4_batch_set(dev_ctx_t *ctx, + lsm6dsl_dec_ds4_fifo_t val) +{ + lsm6dsl_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + if (ret == 0) + { + fifo_ctrl4.dec_ds4_fifo = (uint8_t)val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) for + * fourth data set.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of dec_ds4_fifo in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_dataset_4_batch_get(dev_ctx_t *ctx, + lsm6dsl_dec_ds4_fifo_t *val) +{ + lsm6dsl_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.dec_ds4_fifo) + { + case LSM6DSL_FIFO_DS4_DISABLE: + *val = LSM6DSL_FIFO_DS4_DISABLE; + break; + + case LSM6DSL_FIFO_DS4_NO_DEC: + *val = LSM6DSL_FIFO_DS4_NO_DEC; + break; + + case LSM6DSL_FIFO_DS4_DEC_2: + *val = LSM6DSL_FIFO_DS4_DEC_2; + break; + + case LSM6DSL_FIFO_DS4_DEC_3: + *val = LSM6DSL_FIFO_DS4_DEC_3; + break; + + case LSM6DSL_FIFO_DS4_DEC_4: + *val = LSM6DSL_FIFO_DS4_DEC_4; + break; + + case LSM6DSL_FIFO_DS4_DEC_8: + *val = LSM6DSL_FIFO_DS4_DEC_8; + break; + + case LSM6DSL_FIFO_DS4_DEC_16: + *val = LSM6DSL_FIFO_DS4_DEC_16; + break; + + case LSM6DSL_FIFO_DS4_DEC_32: + *val = LSM6DSL_FIFO_DS4_DEC_32; + break; + + default: + *val = LSM6DSL_FIFO_DS4_DEC_ND; + break; + } + + return ret; +} + +/** + * @brief 8-bit data storage in FIFO.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of only_high_data in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(dev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsl_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + if (ret == 0) + { + fifo_ctrl4.only_high_data = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief 8-bit data storage in FIFO.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of only_high_data in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(dev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsl_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + *val = fifo_ctrl4.only_high_data; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold + * level.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of stop_on_fth in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_stop_on_wtm_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + if (ret == 0) + { + fifo_ctrl4.stop_on_fth = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold + * level.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of stop_on_fth in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_stop_on_wtm_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + *val = fifo_ctrl4.stop_on_fth; + + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fifo_mode in reg FIFO_CTRL5 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_mode_set(dev_ctx_t *ctx, + lsm6dsl_fifo_mode_t val) +{ + lsm6dsl_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5, + (uint8_t *)&fifo_ctrl5, 1); + + if (ret == 0) + { + fifo_ctrl5.fifo_mode = (uint8_t)val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL5, + (uint8_t *)&fifo_ctrl5, 1); + } + + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of fifo_mode in reg FIFO_CTRL5 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_mode_get(dev_ctx_t *ctx, + lsm6dsl_fifo_mode_t *val) +{ + lsm6dsl_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5, + (uint8_t *)&fifo_ctrl5, 1); + + switch (fifo_ctrl5.fifo_mode) + { + case LSM6DSL_BYPASS_MODE: + *val = LSM6DSL_BYPASS_MODE; + break; + + case LSM6DSL_FIFO_MODE: + *val = LSM6DSL_FIFO_MODE; + break; + + case LSM6DSL_STREAM_TO_FIFO_MODE: + *val = LSM6DSL_STREAM_TO_FIFO_MODE; + break; + + case LSM6DSL_BYPASS_TO_STREAM_MODE: + *val = LSM6DSL_BYPASS_TO_STREAM_MODE; + break; + + case LSM6DSL_STREAM_MODE: + *val = LSM6DSL_STREAM_MODE; + break; + + default: + *val = LSM6DSL_FIFO_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief FIFO ODR selection, setting FIFO_MODE also.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of odr_fifo in reg FIFO_CTRL5 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_data_rate_set(dev_ctx_t *ctx, + lsm6dsl_odr_fifo_t val) +{ + lsm6dsl_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5, + (uint8_t *)&fifo_ctrl5, 1); + + if (ret == 0) + { + fifo_ctrl5.odr_fifo = (uint8_t)val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL5, + (uint8_t *)&fifo_ctrl5, 1); + } + + return ret; +} + +/** + * @brief FIFO ODR selection, setting FIFO_MODE also.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of odr_fifo in reg FIFO_CTRL5 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_fifo_data_rate_get(dev_ctx_t *ctx, + lsm6dsl_odr_fifo_t *val) +{ + lsm6dsl_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5, + (uint8_t *)&fifo_ctrl5, 1); + + switch (fifo_ctrl5.odr_fifo) + { + case LSM6DSL_FIFO_DISABLE: + *val = LSM6DSL_FIFO_DISABLE; + break; + + case LSM6DSL_FIFO_12Hz5: + *val = LSM6DSL_FIFO_12Hz5; + break; + + case LSM6DSL_FIFO_26Hz: + *val = LSM6DSL_FIFO_26Hz; + break; + + case LSM6DSL_FIFO_52Hz: + *val = LSM6DSL_FIFO_52Hz; + break; + + case LSM6DSL_FIFO_104Hz: + *val = LSM6DSL_FIFO_104Hz; + break; + + case LSM6DSL_FIFO_208Hz: + *val = LSM6DSL_FIFO_208Hz; + break; + + case LSM6DSL_FIFO_416Hz: + *val = LSM6DSL_FIFO_416Hz; + break; + + case LSM6DSL_FIFO_833Hz: + *val = LSM6DSL_FIFO_833Hz; + break; + + case LSM6DSL_FIFO_1k66Hz: + *val = LSM6DSL_FIFO_1k66Hz; + break; + + case LSM6DSL_FIFO_3k33Hz: + *val = LSM6DSL_FIFO_3k33Hz; + break; + + case LSM6DSL_FIFO_6k66Hz: + *val = LSM6DSL_FIFO_6k66Hz; + break; + + default: + *val = LSM6DSL_FIFO_RATE_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_DEN_functionality + * @brief This section groups all the functions concerning DEN + * functionality. + * @{ + * + */ + +/** + * @brief DEN active level configuration.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_lh in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_polarity_set(dev_ctx_t *ctx, + lsm6dsl_den_lh_t val) +{ + lsm6dsl_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + if (ret == 0) + { + ctrl5_c.den_lh = (uint8_t)val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + + return ret; +} + +/** + * @brief DEN active level configuration.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of den_lh in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_polarity_get(dev_ctx_t *ctx, + lsm6dsl_den_lh_t *val) +{ + lsm6dsl_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch (ctrl5_c.den_lh) + { + case LSM6DSL_DEN_ACT_LOW: + *val = LSM6DSL_DEN_ACT_LOW; + break; + + case LSM6DSL_DEN_ACT_HIGH: + *val = LSM6DSL_DEN_ACT_HIGH; + break; + + default: + *val = LSM6DSL_DEN_POL_ND; + break; + } + + return ret; +} + +/** + * @brief DEN functionality marking mode[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_mode_set(dev_ctx_t *ctx, + lsm6dsl_den_mode_t val) +{ + lsm6dsl_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + if (ret == 0) + { + ctrl6_c.den_mode = (uint8_t)val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + + return ret; +} + +/** + * @brief DEN functionality marking mode[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_mode_get(dev_ctx_t *ctx, + lsm6dsl_den_mode_t *val) +{ + lsm6dsl_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.den_mode) + { + case LSM6DSL_DEN_DISABLE: + *val = LSM6DSL_DEN_DISABLE; + break; + + case LSM6DSL_LEVEL_LETCHED: + *val = LSM6DSL_LEVEL_LETCHED; + break; + + case LSM6DSL_LEVEL_TRIGGER: + *val = LSM6DSL_LEVEL_TRIGGER; + break; + + case LSM6DSL_EDGE_TRIGGER: + *val = LSM6DSL_EDGE_TRIGGER; + break; + + default: + *val = LSM6DSL_DEN_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief Extend DEN functionality to accelerometer sensor.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_xl_g in reg CTRL9_XL + * and den_xl_en in CTRL4_C. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_enable_set(dev_ctx_t *ctx, + lsm6dsl_den_xl_en_t val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + lsm6dsl_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret == 0) + { + ctrl9_xl.den_xl_g = (uint8_t)val & 0x01U; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ctrl4_c.den_xl_en = (uint8_t)val & 0x02U; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + } + } + + return ret; +} + +/** + * @brief Extend DEN functionality to accelerometer sensor. [get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of den_xl_g in reg CTRL9_XL + * and den_xl_en in CTRL4_C. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_enable_get(dev_ctx_t *ctx, + lsm6dsl_den_xl_en_t *val) +{ + lsm6dsl_ctrl4_c_t ctrl4_c; + lsm6dsl_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g) + { + case LSM6DSL_STAMP_IN_GY_DATA: + *val = LSM6DSL_STAMP_IN_GY_DATA; + break; + + case LSM6DSL_STAMP_IN_XL_DATA: + *val = LSM6DSL_STAMP_IN_XL_DATA; + break; + + case LSM6DSL_STAMP_IN_GY_XL_DATA: + *val = LSM6DSL_STAMP_IN_GY_XL_DATA; + break; + + default: + *val = LSM6DSL_DEN_STAMP_ND; + break; + } + } + + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_z in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_mark_axis_z_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret == 0) + { + ctrl9_xl.den_z = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + } + + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_z in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_mark_axis_z_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_z; + + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_y in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_mark_axis_y_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret == 0) + { + ctrl9_xl.den_y = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + } + + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_y in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_mark_axis_y_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_y; + + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_x in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_mark_axis_x_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret == 0) + { + ctrl9_xl.den_x = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + } + + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_x in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_den_mark_axis_x_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_x; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_Pedometer + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Reset pedometer step counter.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pedo_rst_step in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_step_reset_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + ctrl10_c.pedo_rst_step = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + } + + return ret; +} + +/** + * @brief Reset pedometer step counter.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pedo_rst_step in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_step_reset_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + *val = ctrl10_c.pedo_rst_step; + + return ret; +} + +/** + * @brief Enable pedometer algorithm.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pedo_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_sens_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + ctrl10_c.pedo_en = val; + + if (val != 0x00U) + { + ctrl10_c.func_en = val; + } + + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + } + + return ret; +} + +/** + * @brief pedo_sens: Enable pedometer algorithm.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pedo_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_sens_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + *val = ctrl10_c.pedo_en; + + return ret; +} + +/** + * @brief Minimum threshold to detect a peak. Default is 10h.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ths_min in reg + * CONFIG_PEDO_THS_MIN + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_threshold_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN, + (uint8_t *)&config_pedo_ths_min, 1); + + if (ret == 0) + { + config_pedo_ths_min.ths_min = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN, + (uint8_t *)&config_pedo_ths_min, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + + return ret; +} + +/** + * @brief Minimum threshold to detect a peak. Default is 10h.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ths_min in reg CONFIG_PEDO_THS_MIN + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_threshold_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN, + (uint8_t *)&config_pedo_ths_min, 1); + + if (ret == 0) + { + *val = config_pedo_ths_min.ths_min; + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief pedo_full_scale: Pedometer data range.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pedo_fs in + * reg CONFIG_PEDO_THS_MIN + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_full_scale_set(dev_ctx_t *ctx, + lsm6dsl_pedo_fs_t val) +{ + lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN, + (uint8_t *)&config_pedo_ths_min, 1); + + if (ret == 0) + { + config_pedo_ths_min.pedo_fs = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN, + (uint8_t *)&config_pedo_ths_min, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + + return ret; +} + +/** + * @brief Pedometer data range.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of pedo_fs in + * reg CONFIG_PEDO_THS_MIN + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_full_scale_get(dev_ctx_t *ctx, + lsm6dsl_pedo_fs_t *val) +{ + lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN, + (uint8_t *)&config_pedo_ths_min, 1); + + if (ret == 0) + { + switch (config_pedo_ths_min.pedo_fs) + { + case LSM6DSL_PEDO_AT_2g: + *val = LSM6DSL_PEDO_AT_2g; + break; + + case LSM6DSL_PEDO_AT_4g: + *val = LSM6DSL_PEDO_AT_4g; + break; + + default: + *val = LSM6DSL_PEDO_FS_ND; + break; + } + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Pedometer debounce configuration register (r/w).[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of deb_step in reg PEDO_DEB_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_debounce_steps_set(dev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsl_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG, + (uint8_t *)&pedo_deb_reg, 1); + + if (ret == 0) + { + pedo_deb_reg.deb_step = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_PEDO_DEB_REG, + (uint8_t *)&pedo_deb_reg, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + + return ret; +} + +/** + * @brief Pedometer debounce configuration register (r/w).[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of deb_step in reg PEDO_DEB_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_debounce_steps_get(dev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsl_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG, + (uint8_t *)&pedo_deb_reg, 1); + + if (ret == 0) + { + *val = pedo_deb_reg.deb_step; + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Debounce time. If the time between two consecutive steps is + * greater than DEB_TIME*80ms, the debouncer is reactivated. + * Default value: 01101[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of deb_time in reg PEDO_DEB_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_timeout_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG, + (uint8_t *)&pedo_deb_reg, 1); + + if (ret == 0) + { + pedo_deb_reg.deb_time = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_PEDO_DEB_REG, + (uint8_t *)&pedo_deb_reg, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + + return ret; +} + +/** + * @brief Debounce time. If the time between two consecutive steps is + * greater than DEB_TIME*80ms, the debouncer is reactivated. + * Default value: 01101[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of deb_time in reg PEDO_DEB_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_timeout_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG, + (uint8_t *)&pedo_deb_reg, 1); + + if (ret == 0) + { + *val = pedo_deb_reg.deb_time; + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Time period register for step detection on delta time (r/w).[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_steps_period_set(dev_ctx_t *ctx, + uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_STEP_COUNT_DELTA, buff, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Time period register for step detection on delta time (r/w).[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_pedo_steps_period_get(dev_ctx_t *ctx, + uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_STEP_COUNT_DELTA, buff, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_significant_motion + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + +/** + * @brief Enable significant motion detection function.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sign_motion_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_motion_sens_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + ctrl10_c.sign_motion_en = val; + + if (val != 0x00U) + { + ctrl10_c.func_en = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + } + } + + return ret; +} + +/** + * @brief Enable significant motion detection function.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sign_motion_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_motion_sens_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + *val = ctrl10_c.sign_motion_en; + + return ret; +} + +/** + * @brief Significant motion threshold.[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that store significant motion threshold. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_motion_threshold_set(dev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SM_THS, buff, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Significant motion threshold.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that store significant motion threshold. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_motion_threshold_get(dev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SM_THS, buff, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_tilt_detection + * @brief This section groups all the functions that manage the tilt + * event detection. + * @{ + * + */ + +/** + * @brief Enable tilt calculation.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tilt_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tilt_sens_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + ctrl10_c.tilt_en = val; + + if (val != 0x00U) + { + ctrl10_c.func_en = val; + } + + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + } + + return ret; +} + +/** + * @brief Enable tilt calculation.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tilt_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tilt_sens_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + *val = ctrl10_c.tilt_en; + + return ret; +} + +/** + * @brief Enable tilt calculation.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tilt_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_wrist_tilt_sens_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + ctrl10_c.wrist_tilt_en = val; + + if (val != 0x00U) + { + ctrl10_c.func_en = val; + } + + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + } + + return ret; +} + +/** + * @brief Enable tilt calculation.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tilt_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_wrist_tilt_sens_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + *val = ctrl10_c.wrist_tilt_en; + + return ret; +} + +/** + * @brief Absolute Wrist Tilt latency register (r/w). + * Absolute wrist tilt latency parameters. + * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tilt_latency_set(dev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_A_WRIST_TILT_LAT, buff, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Absolute Wrist Tilt latency register (r/w). + * Absolute wrist tilt latency parameters. + * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tilt_latency_get(dev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_LAT, buff, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Absolute Wrist Tilt threshold register(r/w). + * Absolute wrist tilt threshold parameters. + * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tilt_threshold_set(dev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_A_WRIST_TILT_THS, buff, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Absolute Wrist Tilt threshold register(r/w). + * Absolute wrist tilt threshold parameters. + * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tilt_threshold_get(dev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_THS, buff, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Absolute Wrist Tilt mask register (r/w).[set] + * + * @param ctx Read / write interface definitions + * @param val Registers A_WRIST_TILT_MASK + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tilt_src_set(dev_ctx_t *ctx, + lsm6dsl_a_wrist_tilt_mask_t *val) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK, + (uint8_t *) val, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Absolute Wrist Tilt mask register (r/w).[get] + * + * @param ctx Read / write interface definitions + * @param val Registers A_WRIST_TILT_MASK + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_tilt_src_get(dev_ctx_t *ctx, + lsm6dsl_a_wrist_tilt_mask_t *val) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK, + (uint8_t *) val, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_ magnetometer_sensor + * @brief This section groups all the functions that manage additional + * magnetometer sensor. + * @{ + * + */ + +/** + * @brief Enable soft-iron correction algorithm for magnetometer.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of soft_en in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_mag_soft_iron_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret == 0) + { + ctrl9_xl.soft_en = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + } + + return ret; +} + +/** + * @brief Enable soft-iron correction algorithm for magnetometer.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of soft_en in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_mag_soft_iron_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.soft_en; + + return ret; +} + +/** + * @brief Enable hard-iron correction algorithm for magnetometer.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of iron_en in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_mag_hard_iron_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_master_config_t master_config; + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + + if (ret == 0) + { + master_config.iron_en = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + if (val != 0x00U) + { + ctrl10_c.func_en = val; + } + + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, + (uint8_t *)&ctrl10_c, 1); + } + } + } + + return ret; +} + +/** + * @brief Enable hard-iron correction algorithm for magnetometer.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of iron_en in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_mag_hard_iron_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + *val = master_config.iron_en; + + return ret; +} + +/** + * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format. + * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_mag_soft_iron_mat_set(dev_ctx_t *ctx, + uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MAG_SI_XX, buff, 9); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format. + * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_mag_soft_iron_mat_get(dev_ctx_t *ctx, + uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MAG_SI_XX, buff, 9); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Offset for hard-iron compensation register (r/w). The value is + * expressed as a 16-bit word in two鈥檚 complement.[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_mag_offset_set(dev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + buff[1] = (uint8_t)((uint16_t)val[0] / 256U); + buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U)); + buff[3] = (uint8_t)((uint16_t)val[1] / 256U); + buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U)); + buff[5] = (uint8_t)((uint16_t)val[2] / 256U); + buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U)); + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MAG_OFFX_L, buff, 6); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Offset for hard-iron compensation register(r/w). + * The value is expressed as a 16-bit word in two鈥檚 complement.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_mag_offset_get(dev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MAG_OFFX_L, buff, 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSL_Sensor_hub + * @brief This section groups all the functions that manage the sensor + * hub functionality. + * @{ + * + */ + +/** + * @brief Enable function.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values func_en + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_func_en_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + ctrl10_c.func_en = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + } + + return ret; +} + +/** + * @brief Sensor synchronization time frame with the step of 500 ms and + * full range of 5s. Unsigned 8-bit.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_sync_sens_frame_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_sensor_sync_time_frame_t sensor_sync_time_frame; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_TIME_FRAME, + (uint8_t *)&sensor_sync_time_frame, 1); + + if (ret == 0) + { + sensor_sync_time_frame.tph = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SENSOR_SYNC_TIME_FRAME, + (uint8_t *)&sensor_sync_time_frame, 1); + } + + return ret; +} + +/** + * @brief Sensor synchronization time frame with the step of 500 ms and + * full range of 5s. Unsigned 8-bit.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_sync_sens_frame_get(dev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsl_sensor_sync_time_frame_t sensor_sync_time_frame; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_TIME_FRAME, + (uint8_t *)&sensor_sync_time_frame, 1); + *val = sensor_sync_time_frame.tph; + + return ret; +} + +/** + * @brief Resolution ratio of error code for sensor synchronization.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of rr in reg SENSOR_SYNC_RES_RATIO + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_sync_sens_ratio_set(dev_ctx_t *ctx, + lsm6dsl_rr_t val) +{ + lsm6dsl_sensor_sync_res_ratio_t sensor_sync_res_ratio; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_RES_RATIO, + (uint8_t *)&sensor_sync_res_ratio, 1); + + if (ret == 0) + { + sensor_sync_res_ratio.rr = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SENSOR_SYNC_RES_RATIO, + (uint8_t *)&sensor_sync_res_ratio, 1); + } + + return ret; +} + +/** + * @brief Resolution ratio of error code for sensor synchronization.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of rr in reg SENSOR_SYNC_RES_RATIO + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_sync_sens_ratio_get(dev_ctx_t *ctx, + lsm6dsl_rr_t *val) +{ + lsm6dsl_sensor_sync_res_ratio_t sensor_sync_res_ratio; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_RES_RATIO, + (uint8_t *)&sensor_sync_res_ratio, 1); + + switch (sensor_sync_res_ratio.rr) + { + case LSM6DSL_RES_RATIO_2_11: + *val = LSM6DSL_RES_RATIO_2_11; + break; + + case LSM6DSL_RES_RATIO_2_12: + *val = LSM6DSL_RES_RATIO_2_12; + break; + + case LSM6DSL_RES_RATIO_2_13: + *val = LSM6DSL_RES_RATIO_2_13; + break; + + case LSM6DSL_RES_RATIO_2_14: + *val = LSM6DSL_RES_RATIO_2_14; + break; + + default: + *val = LSM6DSL_RES_RATIO_ND; + break; + } + + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of master_on in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_master_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + + if (ret == 0) + { + master_config.master_on = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of master_on in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_master_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + *val = master_config.master_on; + + return ret; +} + +/** + * @brief I2C interface pass-through.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pass_through_mode in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_pass_through_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + + if (ret == 0) + { + master_config.pass_through_mode = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + return ret; +} + +/** + * @brief I2C interface pass-through.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pass_through_mode in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_pass_through_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + *val = master_config.pass_through_mode; + + return ret; +} + +/** + * @brief Master I2C pull-up enable/disable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pull_up_en in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_pin_mode_set(dev_ctx_t *ctx, + lsm6dsl_pull_up_en_t val) +{ + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + + if (ret == 0) + { + master_config.pull_up_en = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + return ret; +} + +/** + * @brief Master I2C pull-up enable/disable.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of pull_up_en in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_pin_mode_get(dev_ctx_t *ctx, + lsm6dsl_pull_up_en_t *val) +{ + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + + switch (master_config.pull_up_en) + { + case LSM6DSL_EXT_PULL_UP: + *val = LSM6DSL_EXT_PULL_UP; + break; + + case LSM6DSL_INTERNAL_PULL_UP: + *val = LSM6DSL_INTERNAL_PULL_UP; + break; + + default: + *val = LSM6DSL_SH_PIN_MODE; + break; + } + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of start_config in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_syncro_mode_set(dev_ctx_t *ctx, + lsm6dsl_start_config_t val) +{ + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + + if (ret == 0) + { + master_config.start_config = (uint8_t)val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of start_config in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_syncro_mode_get(dev_ctx_t *ctx, + lsm6dsl_start_config_t *val) +{ + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + + switch (master_config.start_config) + { + case LSM6DSL_XL_GY_DRDY: + *val = LSM6DSL_XL_GY_DRDY; + break; + + case LSM6DSL_EXT_ON_INT2_PIN: + *val = LSM6DSL_EXT_ON_INT2_PIN; + break; + + default: + *val = LSM6DSL_SH_SYNCRO_ND; + break; + } + + return ret; +} + +/** + * @brief Manage the Master DRDY signal on INT1 pad.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_drdy_on_int1_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + + if (ret == 0) + { + master_config.drdy_on_int1 = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + return ret; +} + +/** + * @brief Manage the Master DRDY signal on INT1 pad.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_drdy_on_int1_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_master_config_t master_config; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + *val = master_config.drdy_on_int1; + + return ret; +} + +/** + * @brief Sensor hub output registers.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure of registers from SENSORHUB1_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_read_data_raw_get(dev_ctx_t *ctx, + lsm6dsl_emb_sh_read_t *val) +{ + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSORHUB1_REG, + (uint8_t *) & (val->sh_byte_1), 12); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSORHUB13_REG, + (uint8_t *) & (val->sh_byte_13), 6); + } + + return ret; +} + +/** + * @brief Master command code used for stamping for sensor sync.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of master_cmd_code in + * reg MASTER_CMD_CODE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_cmd_sens_sync_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_master_cmd_code_t master_cmd_code; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CMD_CODE, + (uint8_t *)&master_cmd_code, 1); + + if (ret == 0) + { + master_cmd_code.master_cmd_code = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CMD_CODE, + (uint8_t *)&master_cmd_code, 1); + } + + return ret; +} + +/** + * @brief Master command code used for stamping for sensor sync.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of master_cmd_code in + * reg MASTER_CMD_CODE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_cmd_sens_sync_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_master_cmd_code_t master_cmd_code; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CMD_CODE, + (uint8_t *)&master_cmd_code, 1); + *val = master_cmd_code.master_cmd_code; + + return ret; +} + +/** + * @brief Error code used for sensor synchronization.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of error_code in + * reg SENS_SYNC_SPI_ERROR_CODE. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_spi_sync_error_set(dev_ctx_t *ctx, uint8_t val) +{ + lsm6dsl_sens_sync_spi_error_code_t sens_sync_spi_error_code; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENS_SYNC_SPI_ERROR_CODE, + (uint8_t *)&sens_sync_spi_error_code, 1); + + if (ret == 0) + { + sens_sync_spi_error_code.error_code = val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SENS_SYNC_SPI_ERROR_CODE, + (uint8_t *)&sens_sync_spi_error_code, 1); + } + + return ret; +} + +/** + * @brief Error code used for sensor synchronization.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of error_code in + * reg SENS_SYNC_SPI_ERROR_CODE. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_spi_sync_error_get(dev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsl_sens_sync_spi_error_code_t sens_sync_spi_error_code; + int32_t ret; + + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENS_SYNC_SPI_ERROR_CODE, + (uint8_t *)&sens_sync_spi_error_code, 1); + *val = sens_sync_spi_error_code.error_code; + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of aux_sens_on in reg SLAVE0_CONFIG. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_num_of_dev_connected_set(dev_ctx_t *ctx, + lsm6dsl_aux_sens_on_t val) +{ + lsm6dsl_slave0_config_t slave0_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG, + (uint8_t *)&slave0_config, 1); + + if (ret == 0) + { + slave0_config.aux_sens_on = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG, + (uint8_t *)&slave0_config, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of aux_sens_on in reg SLAVE0_CONFIG. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_num_of_dev_connected_get(dev_ctx_t *ctx, + lsm6dsl_aux_sens_on_t *val) +{ + lsm6dsl_slave0_config_t slave0_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG, + (uint8_t *)&slave0_config, 1); + + if (ret == 0) + { + switch (slave0_config.aux_sens_on) + { + case LSM6DSL_SLV_0: + *val = LSM6DSL_SLV_0; + break; + + case LSM6DSL_SLV_0_1: + *val = LSM6DSL_SLV_0_1; + break; + + case LSM6DSL_SLV_0_1_2: + *val = LSM6DSL_SLV_0_1_2; + break; + + case LSM6DSL_SLV_0_1_2_3: + *val = LSM6DSL_SLV_0_1_2_3; + break; + + default: + *val = LSM6DSL_SLV_EN_ND; + break; + } + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write.[set] + * + * @param ctx Read / write interface definitions + * @param val Structure that contain: + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_data; 8 bit data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_cfg_write(dev_ctx_t *ctx, + lsm6dsl_sh_cfg_write_t *val) +{ + lsm6dsl_slv0_add_t slv0_add; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + slv0_add.slave0_add = val->slv0_add; + slv0_add.rw_0 = 0; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_ADD, (uint8_t *)&slv0_add, 1); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_SUBADD, + &(val->slv0_subadd), 1); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_DATAWRITE_SRC_MODE_SUB_SLV0, + &(val->slv0_data), 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a read.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure that contain: + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slv0_cfg_read(dev_ctx_t *ctx, + lsm6dsl_sh_cfg_read_t *val) +{ + lsm6dsl_slave0_config_t slave0_config; + lsm6dsl_slv0_add_t slv0_add; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + slv0_add.slave0_add = val->slv_add; + slv0_add.rw_0 = 1; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_ADD, (uint8_t *)&slv0_add, 1); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_SUBADD, + &(val->slv_subadd), 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG, + (uint8_t *)&slave0_config, 1); + slave0_config.slave0_numop = val->slv_len; + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG, + (uint8_t *)&slave0_config, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + } + } + + return ret; +} + +/** + * @brief Configure slave 1 for perform a read.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure that contain: + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slv1_cfg_read(dev_ctx_t *ctx, + lsm6dsl_sh_cfg_read_t *val) +{ + lsm6dsl_slave1_config_t slave1_config; + lsm6dsl_slv1_add_t slv1_add; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + slv1_add.slave1_add = val->slv_add; + slv1_add.r_1 = 1; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV1_ADD, (uint8_t *)&slv1_add, 1); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV1_SUBADD, + &(val->slv_subadd), 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG, + (uint8_t *)&slave1_config, 1); + slave1_config.slave1_numop = val->slv_len; + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG, + (uint8_t *)&slave1_config, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + } + } + + return ret; +} + +/** + * @brief Configure slave 2 for perform a read.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure that contain: + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slv2_cfg_read(dev_ctx_t *ctx, + lsm6dsl_sh_cfg_read_t *val) +{ + lsm6dsl_slv2_add_t slv2_add; + lsm6dsl_slave2_config_t slave2_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + slv2_add.slave2_add = val->slv_add; + slv2_add.r_2 = 1; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV2_ADD, (uint8_t *)&slv2_add, 1); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV2_SUBADD, + &(val->slv_subadd), 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE2_CONFIG, + (uint8_t *)&slave2_config, 1); + + if (ret == 0) + { + slave2_config.slave2_numop = val->slv_len; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE2_CONFIG, + (uint8_t *)&slave2_config, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + } + } + + return ret; +} + +/** + * @brief Configure slave 3 for perform a read.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure that contain: + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slv3_cfg_read(dev_ctx_t *ctx, + lsm6dsl_sh_cfg_read_t *val) +{ + lsm6dsl_slave3_config_t slave3_config; + lsm6dsl_slv3_add_t slv3_add; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + slv3_add.slave3_add = val->slv_add; + slv3_add.r_3 = 1; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV3_ADD, (uint8_t *)&slv3_add, 1); + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV3_SUBADD, + (uint8_t *) & (val->slv_subadd), 1); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE3_CONFIG, + (uint8_t *)&slave3_config, 1); + + if (ret == 0) + { + slave3_config.slave3_numop = val->slv_len; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE3_CONFIG, + (uint8_t *)&slave3_config, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + } + } + + return ret; +} + +/** + * @brief Decimation of read operation on Slave 0 starting from the + * sensor hub trigger.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of slave0_rate in reg SLAVE0_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slave_0_dec_set(dev_ctx_t *ctx, + lsm6dsl_slave0_rate_t val) +{ + lsm6dsl_slave0_config_t slave0_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG, + (uint8_t *)&slave0_config, 1); + + if (ret == 0) + { + slave0_config.slave0_rate = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG, + (uint8_t *)&slave0_config, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + + return ret; +} + +/** + * @brief Decimation of read operation on Slave 0 starting from the + * sensor hub trigger.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of slave0_rate in reg SLAVE0_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slave_0_dec_get(dev_ctx_t *ctx, + lsm6dsl_slave0_rate_t *val) +{ + lsm6dsl_slave0_config_t slave0_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG, + (uint8_t *)&slave0_config, 1); + + if (ret == 0) + { + switch (slave0_config.slave0_rate) + { + case LSM6DSL_SL0_NO_DEC: + *val = LSM6DSL_SL0_NO_DEC; + break; + + case LSM6DSL_SL0_DEC_2: + *val = LSM6DSL_SL0_DEC_2; + break; + + case LSM6DSL_SL0_DEC_4: + *val = LSM6DSL_SL0_DEC_4; + break; + + case LSM6DSL_SL0_DEC_8: + *val = LSM6DSL_SL0_DEC_8; + break; + + default: + *val = LSM6DSL_SL0_DEC_ND; + break; + } + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor + * hub cycle. + * This is effective if the Aux_sens_on[1:0] field in + * SLAVE0_CONFIG(04h) is set to a value other than 00.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of write_once in reg SLAVE1_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_write_mode_set(dev_ctx_t *ctx, + lsm6dsl_write_once_t val) +{ + lsm6dsl_slave1_config_t slave1_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG, + (uint8_t *)&slave1_config, 1); + slave1_config.write_once = (uint8_t) val; + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG, + (uint8_t *)&slave1_config, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor + * hub cycle. + * This is effective if the Aux_sens_on[1:0] field in + * SLAVE0_CONFIG(04h) is set to a value other than 00.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of write_once in reg SLAVE1_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_write_mode_get(dev_ctx_t *ctx, + lsm6dsl_write_once_t *val) +{ + lsm6dsl_slave1_config_t slave1_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG, + (uint8_t *)&slave1_config, 1); + + if (ret == 0) + { + switch (slave1_config.write_once) + { + case LSM6DSL_EACH_SH_CYCLE: + *val = LSM6DSL_EACH_SH_CYCLE; + break; + + case LSM6DSL_ONLY_FIRST_CYCLE: + *val = LSM6DSL_ONLY_FIRST_CYCLE; + break; + + default: + *val = LSM6DSL_SH_WR_MODE_ND; + break; + } + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Decimation of read operation on Slave 1 starting from the + * sensor hub trigger.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of slave1_rate in reg SLAVE1_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slave_1_dec_set(dev_ctx_t *ctx, + lsm6dsl_slave1_rate_t val) +{ + lsm6dsl_slave1_config_t slave1_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG, + (uint8_t *)&slave1_config, 1); + + if (ret == 0) + { + slave1_config.slave1_rate = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG, + (uint8_t *)&slave1_config, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + + return ret; +} + +/** + * @brief Decimation of read operation on Slave 1 starting from the + * sensor hub trigger.[get] + * + * @param ctx Read / write interface definitions reg SLAVE1_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slave_1_dec_get(dev_ctx_t *ctx, + lsm6dsl_slave1_rate_t *val) +{ + lsm6dsl_slave1_config_t slave1_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG, + (uint8_t *)&slave1_config, 1); + + if (ret == 0) + { + switch (slave1_config.slave1_rate) + { + case LSM6DSL_SL1_NO_DEC: + *val = LSM6DSL_SL1_NO_DEC; + break; + + case LSM6DSL_SL1_DEC_2: + *val = LSM6DSL_SL1_DEC_2; + break; + + case LSM6DSL_SL1_DEC_4: + *val = LSM6DSL_SL1_DEC_4; + break; + + case LSM6DSL_SL1_DEC_8: + *val = LSM6DSL_SL1_DEC_8; + break; + + default: + *val = LSM6DSL_SL1_DEC_ND; + break; + } + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Decimation of read operation on Slave 2 starting from the + * sensor hub trigger.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of slave2_rate in reg SLAVE2_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slave_2_dec_set(dev_ctx_t *ctx, + lsm6dsl_slave2_rate_t val) +{ + lsm6dsl_slave2_config_t slave2_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE2_CONFIG, + (uint8_t *)&slave2_config, 1); + + if (ret == 0) + { + slave2_config.slave2_rate = (uint8_t) val; + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE2_CONFIG, + (uint8_t *)&slave2_config, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + + return ret; +} + +/** + * @brief Decimation of read operation on Slave 2 starting from the + * sensor hub trigger.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of slave2_rate in reg SLAVE2_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slave_2_dec_get(dev_ctx_t *ctx, + lsm6dsl_slave2_rate_t *val) +{ + lsm6dsl_slave2_config_t slave2_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE2_CONFIG, + (uint8_t *)&slave2_config, 1); + + if (ret == 0) + { + switch (slave2_config.slave2_rate) + { + case LSM6DSL_SL2_NO_DEC: + *val = LSM6DSL_SL2_NO_DEC; + break; + + case LSM6DSL_SL2_DEC_2: + *val = LSM6DSL_SL2_DEC_2; + break; + + case LSM6DSL_SL2_DEC_4: + *val = LSM6DSL_SL2_DEC_4; + break; + + case LSM6DSL_SL2_DEC_8: + *val = LSM6DSL_SL2_DEC_8; + break; + + default: + *val = LSM6DSL_SL2_DEC_ND; + break; + } + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Decimation of read operation on Slave 3 starting from the + * sensor hub trigger.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of slave3_rate in reg SLAVE3_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slave_3_dec_set(dev_ctx_t *ctx, + lsm6dsl_slave3_rate_t val) +{ + lsm6dsl_slave3_config_t slave3_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE3_CONFIG, + (uint8_t *)&slave3_config, 1); + slave3_config.slave3_rate = (uint8_t)val; + + if (ret == 0) + { + ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE3_CONFIG, + (uint8_t *)&slave3_config, 1); + + if (ret == 0) + { + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + } + + return ret; +} + +/** + * @brief Decimation of read operation on Slave 3 starting from the + * sensor hub trigger.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of slave3_rate in reg SLAVE3_CONFIG. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsl_sh_slave_3_dec_get(dev_ctx_t *ctx, + lsm6dsl_slave3_rate_t *val) +{ + lsm6dsl_slave3_config_t slave3_config; + int32_t ret; + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A); + + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE3_CONFIG, + (uint8_t *)&slave3_config, 1); + + if (ret == 0) + { + switch (slave3_config.slave3_rate) + { + case LSM6DSL_SL3_NO_DEC: + *val = LSM6DSL_SL3_NO_DEC; + break; + + case LSM6DSL_SL3_DEC_2: + *val = LSM6DSL_SL3_DEC_2; + break; + + case LSM6DSL_SL3_DEC_4: + *val = LSM6DSL_SL3_DEC_4; + break; + + case LSM6DSL_SL3_DEC_8: + *val = LSM6DSL_SL3_DEC_8; + break; + + default: + *val = LSM6DSL_SL3_DEC_ND; + break; + } + + ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + } + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Module/lsm6dsl/lsm6dsl_reg.h b/Module/lsm6dsl/lsm6dsl_reg.h new file mode 100644 index 0000000..39f1e98 --- /dev/null +++ b/Module/lsm6dsl/lsm6dsl_reg.h @@ -0,0 +1,2722 @@ +#ifndef LSM6DSL_REGS_H +#define LSM6DSL_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup LSM6DSL + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef void (*dev_write_ptr)(uint8_t, uint8_t *, uint32_t); +typedef void (*dev_read_ptr)(uint8_t, uint8_t *, uint32_t); +typedef void (*dev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + dev_write_ptr write_reg; + dev_read_ptr read_reg; + /** Component optional fields **/ + dev_mdelay_ptr mdelay; +} dev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LSM6DSL_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define LSM6DSL_I2C_ADD_L 0xD5U +#define LSM6DSL_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define LSM6DSL_ID 0x6AU + +/** + * @} + * + */ + +#define LSM6DSL_FUNC_CFG_ACCESS 0x01U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; +uint8_t func_cfg_en : + 3; /* func_cfg_en + func_cfg_en_b */ +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN +uint8_t func_cfg_en : + 3; /* func_cfg_en + func_cfg_en_b */ + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_func_cfg_access_t; + +#define LSM6DSL_SENSOR_SYNC_TIME_FRAME 0x04U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tph : 4; + uint8_t not_used_01 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 4; + uint8_t tph : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensor_sync_time_frame_t; + +#define LSM6DSL_SENSOR_SYNC_RES_RATIO 0x05U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t rr : 2; + uint8_t not_used_01 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 6; + uint8_t rr : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensor_sync_res_ratio_t; + +#define LSM6DSL_FIFO_CTRL1 0x06U +typedef struct +{ + uint8_t fth : 8; /* + FIFO_CTRL2(fth) */ +} lsm6dsl_fifo_ctrl1_t; + +#define LSM6DSL_FIFO_CTRL2 0x07U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ + uint8_t fifo_temp_en : 1; + uint8_t not_used_01 : 2; + uint8_t timer_pedo_fifo_drdy : 1; + uint8_t timer_pedo_fifo_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timer_pedo_fifo_en : 1; + uint8_t timer_pedo_fifo_drdy : 1; + uint8_t not_used_01 : 2; + uint8_t fifo_temp_en : 1; + uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_fifo_ctrl2_t; + +#define LSM6DSL_FIFO_CTRL3 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dec_fifo_xl : 3; + uint8_t dec_fifo_gyro : 3; + uint8_t not_used_01 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 2; + uint8_t dec_fifo_gyro : 3; + uint8_t dec_fifo_xl : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_fifo_ctrl3_t; + +#define LSM6DSL_FIFO_CTRL4 0x09U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dec_ds3_fifo : 3; + uint8_t dec_ds4_fifo : 3; + uint8_t only_high_data : 1; + uint8_t stop_on_fth : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_fth : 1; + uint8_t only_high_data : 1; + uint8_t dec_ds4_fifo : 3; + uint8_t dec_ds3_fifo : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_fifo_ctrl4_t; + +#define LSM6DSL_FIFO_CTRL5 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t odr_fifo : 4; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t odr_fifo : 4; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_fifo_ctrl5_t; + +#define LSM6DSL_DRDY_PULSE_CFG_G 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_wrist_tilt : 1; + uint8_t not_used_01 : 6; + uint8_t drdy_pulsed : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t drdy_pulsed : 1; + uint8_t not_used_01 : 6; + uint8_t int2_wrist_tilt : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_drdy_pulse_cfg_g_t; + +#define LSM6DSL_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t int1_fth : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_full_flag : 1; + uint8_t int1_sign_mot : 1; + uint8_t int1_step_detector : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_step_detector : 1; + uint8_t int1_sign_mot : 1; + uint8_t int1_full_flag : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fth : 1; + uint8_t int1_boot : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_int1_ctrl_t; + +#define LSM6DSL_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_fth : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_full_flag : 1; + uint8_t int2_step_count_ov : 1; + uint8_t int2_step_delta : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_step_delta : 1; + uint8_t int2_step_count_ov : 1; + uint8_t int2_full_flag : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fth : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_int2_ctrl_t; + +#define LSM6DSL_WHO_AM_I 0x0FU +#define LSM6DSL_CTRL1_XL 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bw0_xl : 1; + uint8_t lpf1_bw_sel : 1; + uint8_t fs_xl : 2; + uint8_t odr_xl : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_xl : 4; + uint8_t fs_xl : 2; + uint8_t lpf1_bw_sel : 1; + uint8_t bw0_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_ctrl1_xl_t; + +#define LSM6DSL_CTRL2_G 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t fs_g : 3; /* fs_g + fs_125 */ + uint8_t odr_g : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_g : 4; + uint8_t fs_g : 3; /* fs_g + fs_125 */ + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_ctrl2_g_t; + +#define LSM6DSL_CTRL3_C 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t ble : 1; + uint8_t if_inc : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t if_inc : 1; + uint8_t ble : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_ctrl3_c_t; + +#define LSM6DSL_CTRL4_C 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t lpf1_sel_g : 1; + uint8_t i2c_disable : 1; + uint8_t drdy_mask : 1; + uint8_t den_drdy_int1 : 1; + uint8_t int2_on_int1 : 1; + uint8_t sleep : 1; + uint8_t den_xl_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_xl_en : 1; + uint8_t sleep : 1; + uint8_t int2_on_int1 : 1; + uint8_t den_drdy_int1 : 1; + uint8_t drdy_mask : 1; + uint8_t i2c_disable : 1; + uint8_t lpf1_sel_g : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_ctrl4_c_t; + +#define LSM6DSL_CTRL5_C 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t den_lh : 1; + uint8_t rounding : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t rounding : 3; + uint8_t den_lh : 1; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_ctrl5_c_t; + +#define LSM6DSL_CTRL6_C 0x15U + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ftype : 2; + uint8_t not_used_01 : 1; + uint8_t usr_off_w : 1; + uint8_t xl_hm_mode : 1; +uint8_t den_mode : + 3; /* trig_en + lvl_en + lvl2_en */ +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN +uint8_t den_mode : + 3; /* trig_en + lvl_en + lvl2_en */ + uint8_t xl_hm_mode : 1; + uint8_t usr_off_w : 1; + uint8_t not_used_01 : 1; + uint8_t ftype : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_ctrl6_c_t; + +#define LSM6DSL_CTRL7_G 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 2; + uint8_t rounding_status : 1; + uint8_t not_used_02 : 1; + uint8_t hpm_g : 2; + uint8_t hp_en_g : 1; + uint8_t g_hm_mode : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t g_hm_mode : 1; + uint8_t hp_en_g : 1; + uint8_t hpm_g : 2; + uint8_t not_used_02 : 1; + uint8_t rounding_status : 1; + uint8_t not_used_01 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_ctrl7_g_t; + +#define LSM6DSL_CTRL8_XL 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t low_pass_on_6d : 1; + uint8_t not_used_01 : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t input_composite : 1; + uint8_t hp_ref_mode : 1; + uint8_t hpcf_xl : 2; + uint8_t lpf2_xl_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t lpf2_xl_en : 1; + uint8_t hpcf_xl : 2; + uint8_t hp_ref_mode : 1; + uint8_t input_composite : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t not_used_01 : 1; + uint8_t low_pass_on_6d : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_ctrl8_xl_t; + +#define LSM6DSL_CTRL9_XL 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 2; + uint8_t soft_en : 1; + uint8_t not_used_02 : 1; + uint8_t den_xl_g : 1; + uint8_t den_z : 1; + uint8_t den_y : 1; + uint8_t den_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_x : 1; + uint8_t den_y : 1; + uint8_t den_z : 1; + uint8_t den_xl_g : 1; + uint8_t not_used_02 : 1; + uint8_t soft_en : 1; + uint8_t not_used_01 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_ctrl9_xl_t; + +#define LSM6DSL_CTRL10_C 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sign_motion_en : 1; + uint8_t pedo_rst_step : 1; + uint8_t func_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t timer_en : 1; + uint8_t not_used_01 : 1; + uint8_t wrist_tilt_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wrist_tilt_en : 1; + uint8_t not_used_01 : 1; + uint8_t timer_en : 1; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t func_en : 1; + uint8_t pedo_rst_step : 1; + uint8_t sign_motion_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_ctrl10_c_t; + +#define LSM6DSL_MASTER_CONFIG 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t master_on : 1; + uint8_t iron_en : 1; + uint8_t pass_through_mode : 1; + uint8_t pull_up_en : 1; + uint8_t start_config : 1; + uint8_t not_used_01 : 1; + uint8_t data_valid_sel_fifo : 1; + uint8_t drdy_on_int1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t drdy_on_int1 : 1; + uint8_t data_valid_sel_fifo : 1; + uint8_t not_used_01 : 1; + uint8_t start_config : 1; + uint8_t pull_up_en : 1; + uint8_t pass_through_mode : 1; + uint8_t iron_en : 1; + uint8_t master_on : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_master_config_t; + +#define LSM6DSL_WAKE_UP_SRC 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state_ia : 1; + uint8_t ff_ia : 1; + uint8_t not_used_01 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 2; + uint8_t ff_ia : 1; + uint8_t sleep_state_ia : 1; + uint8_t wu_ia : 1; + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_wake_up_src_t; + +#define LSM6DSL_TAP_SRC 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; + uint8_t tap_sign : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t tap_ia : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_sign : 1; + uint8_t x_tap : 1; + uint8_t y_tap : 1; + uint8_t z_tap : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_tap_src_t; + +#define LSM6DSL_D6D_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t den_drdy : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_drdy : 1; + uint8_t d6d_ia : 1; + uint8_t zh : 1; + uint8_t zl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t xh : 1; + uint8_t xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_d6d_src_t; + +#define LSM6DSL_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t not_used_01 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 5; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_status_reg_t; + +#define LSM6DSL_OUT_TEMP_L 0x20U +#define LSM6DSL_OUT_TEMP_H 0x21U +#define LSM6DSL_OUTX_L_G 0x22U +#define LSM6DSL_OUTX_H_G 0x23U +#define LSM6DSL_OUTY_L_G 0x24U +#define LSM6DSL_OUTY_H_G 0x25U +#define LSM6DSL_OUTZ_L_G 0x26U +#define LSM6DSL_OUTZ_H_G 0x27U +#define LSM6DSL_OUTX_L_XL 0x28U +#define LSM6DSL_OUTX_H_XL 0x29U +#define LSM6DSL_OUTY_L_XL 0x2AU +#define LSM6DSL_OUTY_H_XL 0x2BU +#define LSM6DSL_OUTZ_L_XL 0x2CU +#define LSM6DSL_OUTZ_H_XL 0x2DU +#define LSM6DSL_SENSORHUB1_REG 0x2EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub1_reg_t; + +#define LSM6DSL_SENSORHUB2_REG 0x2FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub2_reg_t; + +#define LSM6DSL_SENSORHUB3_REG 0x30U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub3_reg_t; + +#define LSM6DSL_SENSORHUB4_REG 0x31U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub4_reg_t; + +#define LSM6DSL_SENSORHUB5_REG 0x32U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub5_reg_t; + +#define LSM6DSL_SENSORHUB6_REG 0x33U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub6_reg_t; + +#define LSM6DSL_SENSORHUB7_REG 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub7_reg_t; + +#define LSM6DSL_SENSORHUB8_REG 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub8_reg_t; + +#define LSM6DSL_SENSORHUB9_REG 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub9_reg_t; + +#define LSM6DSL_SENSORHUB10_REG 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub10_reg_t; + +#define LSM6DSL_SENSORHUB11_REG 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub11_reg_t; + +#define LSM6DSL_SENSORHUB12_REG 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub12_reg_t; + +#define LSM6DSL_FIFO_STATUS1 0x3AU +typedef struct +{ + uint8_t diff_fifo : 8; /* + FIFO_STATUS2(diff_fifo) */ +} lsm6dsl_fifo_status1_t; + +#define LSM6DSL_FIFO_STATUS2 0x3BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ + uint8_t not_used_01 : 1; + uint8_t fifo_empty : 1; + uint8_t fifo_full_smart : 1; + uint8_t over_run : 1; + uint8_t waterm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t waterm : 1; + uint8_t over_run : 1; + uint8_t fifo_full_smart : 1; + uint8_t fifo_empty : 1; + uint8_t not_used_01 : 1; + uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_fifo_status2_t; + +#define LSM6DSL_FIFO_STATUS3 0x3CU +typedef struct +{ +uint8_t fifo_pattern : + 8; /* + FIFO_STATUS4(fifo_pattern) */ +} lsm6dsl_fifo_status3_t; + +#define LSM6DSL_FIFO_STATUS4 0x3DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN +uint8_t fifo_pattern : + 2; /* + FIFO_STATUS3(fifo_pattern) */ + uint8_t not_used_01 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 6; +uint8_t fifo_pattern : + 2; /* + FIFO_STATUS3(fifo_pattern) */ +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_fifo_status4_t; + +#define LSM6DSL_FIFO_DATA_OUT_L 0x3EU +#define LSM6DSL_FIFO_DATA_OUT_H 0x3FU +#define LSM6DSL_TIMESTAMP0_REG 0x40U +#define LSM6DSL_TIMESTAMP1_REG 0x41U +#define LSM6DSL_TIMESTAMP2_REG 0x42U +#define LSM6DSL_STEP_TIMESTAMP_L 0x49U +#define LSM6DSL_STEP_TIMESTAMP_H 0x4AU +#define LSM6DSL_STEP_COUNTER_L 0x4BU +#define LSM6DSL_STEP_COUNTER_H 0x4CU + +#define LSM6DSL_SENSORHUB13_REG 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub13_reg_t; + +#define LSM6DSL_SENSORHUB14_REG 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub14_reg_t; + +#define LSM6DSL_SENSORHUB15_REG 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub15_reg_t; + +#define LSM6DSL_SENSORHUB16_REG 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub16_reg_t; + +#define LSM6DSL_SENSORHUB17_REG 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub17_reg_t; + +#define LSM6DSL_SENSORHUB18_REG 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_sensorhub18_reg_t; + +#define LSM6DSL_FUNC_SRC1 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub_end_op : 1; + uint8_t si_end_op : 1; + uint8_t hi_fail : 1; + uint8_t step_overflow : 1; + uint8_t step_detected : 1; + uint8_t tilt_ia : 1; + uint8_t sign_motion_ia : 1; + uint8_t step_count_delta_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step_count_delta_ia : 1; + uint8_t sign_motion_ia : 1; + uint8_t tilt_ia : 1; + uint8_t step_detected : 1; + uint8_t step_overflow : 1; + uint8_t hi_fail : 1; + uint8_t si_end_op : 1; + uint8_t sensorhub_end_op : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_func_src1_t; + +#define LSM6DSL_FUNC_SRC2 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wrist_tilt_ia : 1; + uint8_t not_used_01 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used_01 : 2; + uint8_t wrist_tilt_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_func_src2_t; + +#define LSM6DSL_WRIST_TILT_IA 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 2; + uint8_t wrist_tilt_ia_zneg : 1; + uint8_t wrist_tilt_ia_zpos : 1; + uint8_t wrist_tilt_ia_yneg : 1; + uint8_t wrist_tilt_ia_ypos : 1; + uint8_t wrist_tilt_ia_xneg : 1; + uint8_t wrist_tilt_ia_xpos : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wrist_tilt_ia_xpos : 1; + uint8_t wrist_tilt_ia_xneg : 1; + uint8_t wrist_tilt_ia_ypos : 1; + uint8_t wrist_tilt_ia_yneg : 1; + uint8_t wrist_tilt_ia_zpos : 1; + uint8_t wrist_tilt_ia_zneg : 1; + uint8_t not_used_01 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_wrist_tilt_ia_t; + +#define LSM6DSL_TAP_CFG 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t slope_fds : 1; + uint8_t inact_en : 2; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t inact_en : 2; + uint8_t slope_fds : 1; + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_tap_cfg_t; + +#define LSM6DSL_TAP_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths : 5; + uint8_t sixd_ths : 2; + uint8_t d4d_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t d4d_en : 1; + uint8_t sixd_ths : 2; + uint8_t tap_ths : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_tap_ths_6d_t; + +#define LSM6DSL_INT_DUR2 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dur : 4; + uint8_t quiet : 2; + uint8_t shock : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_int_dur2_t; + +#define LSM6DSL_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t not_used_01 : 1; + uint8_t single_double_tap : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t single_double_tap : 1; + uint8_t not_used_01 : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_wake_up_ths_t; + +#define LSM6DSL_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t timer_hr : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t timer_hr : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_wake_up_dur_t; + +#define LSM6DSL_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_free_fall_t; + +#define LSM6DSL_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_timer : 1; + uint8_t int1_tilt : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_inact_state : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_inact_state : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_6d : 1; + uint8_t int1_tilt : 1; + uint8_t int1_timer : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_md1_cfg_t; + +#define LSM6DSL_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_iron : 1; + uint8_t int2_tilt : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_inact_state : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_inact_state : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_6d : 1; + uint8_t int2_tilt : 1; + uint8_t int2_iron : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_md2_cfg_t; + +#define LSM6DSL_MASTER_CMD_CODE 0x60U +typedef struct +{ + uint8_t master_cmd_code : 8; +} lsm6dsl_master_cmd_code_t; + +#define LSM6DSL_SENS_SYNC_SPI_ERROR_CODE 0x61U +typedef struct +{ + uint8_t error_code : 8; +} lsm6dsl_sens_sync_spi_error_code_t; + +#define LSM6DSL_OUT_MAG_RAW_X_L 0x66U +#define LSM6DSL_OUT_MAG_RAW_X_H 0x67U +#define LSM6DSL_OUT_MAG_RAW_Y_L 0x68U +#define LSM6DSL_OUT_MAG_RAW_Y_H 0x69U +#define LSM6DSL_OUT_MAG_RAW_Z_L 0x6AU +#define LSM6DSL_OUT_MAG_RAW_Z_H 0x6BU +#define LSM6DSL_X_OFS_USR 0x73U +#define LSM6DSL_Y_OFS_USR 0x74U +#define LSM6DSL_Z_OFS_USR 0x75U +#define LSM6DSL_SLV0_ADD 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t rw_0 : 1; + uint8_t slave0_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_add : 7; + uint8_t rw_0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_slv0_add_t; + +#define LSM6DSL_SLV0_SUBADD 0x03U +typedef struct +{ + uint8_t slave0_reg : 8; +} lsm6dsl_slv0_subadd_t; + +#define LSM6DSL_SLAVE0_CONFIG 0x04U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_numop : 3; + uint8_t src_mode : 1; + uint8_t aux_sens_on : 2; + uint8_t slave0_rate : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_rate : 2; + uint8_t aux_sens_on : 2; + uint8_t src_mode : 1; + uint8_t slave0_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_slave0_config_t; + +#define LSM6DSL_SLV1_ADD 0x05U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_1 : 1; + uint8_t slave1_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_add : 7; + uint8_t r_1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_slv1_add_t; + +#define LSM6DSL_SLV1_SUBADD 0x06U +typedef struct +{ + uint8_t slave1_reg : 8; +} lsm6dsl_slv1_subadd_t; + +#define LSM6DSL_SLAVE1_CONFIG 0x07U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_numop : 3; + uint8_t not_used_01 : 2; + uint8_t write_once : 1; + uint8_t slave1_rate : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_rate : 2; + uint8_t write_once : 1; + uint8_t not_used_01 : 2; + uint8_t slave1_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_slave1_config_t; + +#define LSM6DSL_SLV2_ADD 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_2 : 1; + uint8_t slave2_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_add : 7; + uint8_t r_2 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_slv2_add_t; + +#define LSM6DSL_SLV2_SUBADD 0x09U +typedef struct +{ + uint8_t slave2_reg : 8; +} lsm6dsl_slv2_subadd_t; + +#define LSM6DSL_SLAVE2_CONFIG 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_numop : 3; + uint8_t not_used_01 : 3; + uint8_t slave2_rate : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_rate : 2; + uint8_t not_used_01 : 3; + uint8_t slave2_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_slave2_config_t; + +#define LSM6DSL_SLV3_ADD 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_3 : 1; + uint8_t slave3_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_add : 7; + uint8_t r_3 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_slv3_add_t; + +#define LSM6DSL_SLV3_SUBADD 0x0CU +typedef struct +{ + uint8_t slave3_reg : 8; +} lsm6dsl_slv3_subadd_t; + +#define LSM6DSL_SLAVE3_CONFIG 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_numop : 3; + uint8_t not_used_01 : 3; + uint8_t slave3_rate : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_rate : 2; + uint8_t not_used_01 : 3; + uint8_t slave3_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_slave3_config_t; + +#define LSM6DSL_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU +typedef struct +{ + uint8_t slave_dataw : 8; +} lsm6dsl_datawrite_src_mode_sub_slv0_t; + +#define LSM6DSL_CONFIG_PEDO_THS_MIN 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ths_min : 5; + uint8_t not_used_01 : 2; + uint8_t pedo_fs : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pedo_fs : 1; + uint8_t not_used_01 : 2; + uint8_t ths_min : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_config_pedo_ths_min_t; + +#define LSM6DSL_SM_THS 0x13U +#define LSM6DSL_PEDO_DEB_REG 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deb_step : 3; + uint8_t deb_time : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t deb_time : 5; + uint8_t deb_step : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_pedo_deb_reg_t; + +#define LSM6DSL_STEP_COUNT_DELTA 0x15U +#define LSM6DSL_MAG_SI_XX 0x24U +#define LSM6DSL_MAG_SI_XY 0x25U +#define LSM6DSL_MAG_SI_XZ 0x26U +#define LSM6DSL_MAG_SI_YX 0x27U +#define LSM6DSL_MAG_SI_YY 0x28U +#define LSM6DSL_MAG_SI_YZ 0x29U +#define LSM6DSL_MAG_SI_ZX 0x2AU +#define LSM6DSL_MAG_SI_ZY 0x2BU +#define LSM6DSL_MAG_SI_ZZ 0x2CU +#define LSM6DSL_MAG_OFFX_L 0x2DU +#define LSM6DSL_MAG_OFFX_H 0x2EU +#define LSM6DSL_MAG_OFFY_L 0x2FU +#define LSM6DSL_MAG_OFFY_H 0x30U +#define LSM6DSL_MAG_OFFZ_L 0x31U +#define LSM6DSL_MAG_OFFZ_H 0x32U +#define LSM6DSL_A_WRIST_TILT_LAT 0x50U +#define LSM6DSL_A_WRIST_TILT_THS 0x54U +#define LSM6DSL_A_WRIST_TILT_MASK 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 2; + uint8_t wrist_tilt_mask_zneg : 1; + uint8_t wrist_tilt_mask_zpos : 1; + uint8_t wrist_tilt_mask_yneg : 1; + uint8_t wrist_tilt_mask_ypos : 1; + uint8_t wrist_tilt_mask_xneg : 1; + uint8_t wrist_tilt_mask_xpos : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wrist_tilt_mask_xpos : 1; + uint8_t wrist_tilt_mask_xneg : 1; + uint8_t wrist_tilt_mask_ypos : 1; + uint8_t wrist_tilt_mask_yneg : 1; + uint8_t wrist_tilt_mask_zpos : 1; + uint8_t wrist_tilt_mask_zneg : 1; + uint8_t not_used_01 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsl_a_wrist_tilt_mask_t; + +/** + * @defgroup LSM6DSL_Register_Union + * @brief This union group all the registers having a bit-field + * description. + * This union is useful but it's not needed by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + lsm6dsl_func_cfg_access_t func_cfg_access; + lsm6dsl_sensor_sync_time_frame_t sensor_sync_time_frame; + lsm6dsl_sensor_sync_res_ratio_t sensor_sync_res_ratio; + lsm6dsl_fifo_ctrl1_t fifo_ctrl1; + lsm6dsl_fifo_ctrl2_t fifo_ctrl2; + lsm6dsl_fifo_ctrl3_t fifo_ctrl3; + lsm6dsl_fifo_ctrl4_t fifo_ctrl4; + lsm6dsl_fifo_ctrl5_t fifo_ctrl5; + lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; + lsm6dsl_int1_ctrl_t int1_ctrl; + lsm6dsl_int2_ctrl_t int2_ctrl; + lsm6dsl_ctrl1_xl_t ctrl1_xl; + lsm6dsl_ctrl2_g_t ctrl2_g; + lsm6dsl_ctrl3_c_t ctrl3_c; + lsm6dsl_ctrl4_c_t ctrl4_c; + lsm6dsl_ctrl5_c_t ctrl5_c; + lsm6dsl_ctrl6_c_t ctrl6_c; + lsm6dsl_ctrl7_g_t ctrl7_g; + lsm6dsl_ctrl8_xl_t ctrl8_xl; + lsm6dsl_ctrl9_xl_t ctrl9_xl; + lsm6dsl_ctrl10_c_t ctrl10_c; + lsm6dsl_master_config_t master_config; + lsm6dsl_wake_up_src_t wake_up_src; + lsm6dsl_tap_src_t tap_src; + lsm6dsl_d6d_src_t d6d_src; + lsm6dsl_status_reg_t status_reg; + lsm6dsl_sensorhub1_reg_t sensorhub1_reg; + lsm6dsl_sensorhub2_reg_t sensorhub2_reg; + lsm6dsl_sensorhub3_reg_t sensorhub3_reg; + lsm6dsl_sensorhub4_reg_t sensorhub4_reg; + lsm6dsl_sensorhub5_reg_t sensorhub5_reg; + lsm6dsl_sensorhub6_reg_t sensorhub6_reg; + lsm6dsl_sensorhub7_reg_t sensorhub7_reg; + lsm6dsl_sensorhub8_reg_t sensorhub8_reg; + lsm6dsl_sensorhub9_reg_t sensorhub9_reg; + lsm6dsl_sensorhub10_reg_t sensorhub10_reg; + lsm6dsl_sensorhub11_reg_t sensorhub11_reg; + lsm6dsl_sensorhub12_reg_t sensorhub12_reg; + lsm6dsl_fifo_status1_t fifo_status1; + lsm6dsl_fifo_status2_t fifo_status2; + lsm6dsl_fifo_status3_t fifo_status3; + lsm6dsl_fifo_status4_t fifo_status4; + lsm6dsl_sensorhub13_reg_t sensorhub13_reg; + lsm6dsl_sensorhub14_reg_t sensorhub14_reg; + lsm6dsl_sensorhub15_reg_t sensorhub15_reg; + lsm6dsl_sensorhub16_reg_t sensorhub16_reg; + lsm6dsl_sensorhub17_reg_t sensorhub17_reg; + lsm6dsl_sensorhub18_reg_t sensorhub18_reg; + lsm6dsl_func_src1_t func_src1; + lsm6dsl_func_src2_t func_src2; + lsm6dsl_wrist_tilt_ia_t wrist_tilt_ia; + lsm6dsl_tap_cfg_t tap_cfg; + lsm6dsl_tap_ths_6d_t tap_ths_6d; + lsm6dsl_int_dur2_t int_dur2; + lsm6dsl_wake_up_ths_t wake_up_ths; + lsm6dsl_wake_up_dur_t wake_up_dur; + lsm6dsl_free_fall_t free_fall; + lsm6dsl_md1_cfg_t md1_cfg; + lsm6dsl_md2_cfg_t md2_cfg; + lsm6dsl_master_cmd_code_t master_cmd_code; + lsm6dsl_sens_sync_spi_error_code_t sens_sync_spi_error_code; + lsm6dsl_slv0_add_t slv0_add; + lsm6dsl_slv0_subadd_t slv0_subadd; + lsm6dsl_slave0_config_t slave0_config; + lsm6dsl_slv1_add_t slv1_add; + lsm6dsl_slv1_subadd_t slv1_subadd; + lsm6dsl_slave1_config_t slave1_config; + lsm6dsl_slv2_add_t slv2_add; + lsm6dsl_slv2_subadd_t slv2_subadd; + lsm6dsl_slave2_config_t slave2_config; + lsm6dsl_slv3_add_t slv3_add; + lsm6dsl_slv3_subadd_t slv3_subadd; + lsm6dsl_slave3_config_t slave3_config; + lsm6dsl_datawrite_src_mode_sub_slv0_t + datawrite_src_mode_sub_slv0; + lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min; + lsm6dsl_pedo_deb_reg_t pedo_deb_reg; + lsm6dsl_a_wrist_tilt_mask_t a_wrist_tilt_mask; + bitwise_t bitwise; + uint8_t byte; +} lsm6dsl_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t lsm6dsl_read_reg(dev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t lsm6dsl_write_reg(dev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t lsm6dsl_from_fs2g_to_mg(int16_t lsb); +float_t lsm6dsl_from_fs4g_to_mg(int16_t lsb); +float_t lsm6dsl_from_fs8g_to_mg(int16_t lsb); +float_t lsm6dsl_from_fs16g_to_mg(int16_t lsb); + +float_t lsm6dsl_from_fs125dps_to_mdps(int16_t lsb); +float_t lsm6dsl_from_fs250dps_to_mdps(int16_t lsb); +float_t lsm6dsl_from_fs500dps_to_mdps(int16_t lsb); +float_t lsm6dsl_from_fs1000dps_to_mdps(int16_t lsb); +float_t lsm6dsl_from_fs2000dps_to_mdps(int16_t lsb); + +float_t lsm6dsl_from_lsb_to_celsius(int16_t lsb); + +typedef enum +{ + LSM6DSL_2g = 0, + LSM6DSL_16g = 1, + LSM6DSL_4g = 2, + LSM6DSL_8g = 3, + LSM6DSL_XL_FS_ND = 4, /* ERROR CODE */ +} lsm6dsl_fs_xl_t; +int32_t lsm6dsl_xl_full_scale_set(dev_ctx_t *ctx, + lsm6dsl_fs_xl_t val); +int32_t lsm6dsl_xl_full_scale_get(dev_ctx_t *ctx, + lsm6dsl_fs_xl_t *val); + +typedef enum +{ + LSM6DSL_XL_ODR_OFF = 0, + LSM6DSL_XL_ODR_12Hz5 = 1, + LSM6DSL_XL_ODR_26Hz = 2, + LSM6DSL_XL_ODR_52Hz = 3, + LSM6DSL_XL_ODR_104Hz = 4, + LSM6DSL_XL_ODR_208Hz = 5, + LSM6DSL_XL_ODR_416Hz = 6, + LSM6DSL_XL_ODR_833Hz = 7, + LSM6DSL_XL_ODR_1k66Hz = 8, + LSM6DSL_XL_ODR_3k33Hz = 9, + LSM6DSL_XL_ODR_6k66Hz = 10, + LSM6DSL_XL_ODR_1Hz6 = 11, + LSM6DSL_XL_ODR_ND = 12, /* ERROR CODE */ +} lsm6dsl_odr_xl_t; +int32_t lsm6dsl_xl_data_rate_set(dev_ctx_t *ctx, + lsm6dsl_odr_xl_t val); +int32_t lsm6dsl_xl_data_rate_get(dev_ctx_t *ctx, + lsm6dsl_odr_xl_t *val); + +typedef enum +{ + LSM6DSL_250dps = 0, + LSM6DSL_125dps = 1, + LSM6DSL_500dps = 2, + LSM6DSL_1000dps = 4, + LSM6DSL_2000dps = 6, + LSM6DSL_GY_FS_ND = 7, /* ERROR CODE */ +} lsm6dsl_fs_g_t; +int32_t lsm6dsl_gy_full_scale_set(dev_ctx_t *ctx, + lsm6dsl_fs_g_t val); +int32_t lsm6dsl_gy_full_scale_get(dev_ctx_t *ctx, + lsm6dsl_fs_g_t *val); + +typedef enum +{ + LSM6DSL_GY_ODR_OFF = 0, + LSM6DSL_GY_ODR_12Hz5 = 1, + LSM6DSL_GY_ODR_26Hz = 2, + LSM6DSL_GY_ODR_52Hz = 3, + LSM6DSL_GY_ODR_104Hz = 4, + LSM6DSL_GY_ODR_208Hz = 5, + LSM6DSL_GY_ODR_416Hz = 6, + LSM6DSL_GY_ODR_833Hz = 7, + LSM6DSL_GY_ODR_1k66Hz = 8, + LSM6DSL_GY_ODR_3k33Hz = 9, + LSM6DSL_GY_ODR_6k66Hz = 10, + LSM6DSL_GY_ODR_ND = 11, /* ERROR CODE */ +} lsm6dsl_odr_g_t; +int32_t lsm6dsl_gy_data_rate_set(dev_ctx_t *ctx, + lsm6dsl_odr_g_t val); +int32_t lsm6dsl_gy_data_rate_get(dev_ctx_t *ctx, + lsm6dsl_odr_g_t *val); + +int32_t lsm6dsl_block_data_update_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_block_data_update_get(dev_ctx_t *ctx, + uint8_t *val); + +typedef enum +{ + LSM6DSL_LSb_1mg = 0, + LSM6DSL_LSb_16mg = 1, + LSM6DSL_WEIGHT_ND = 2, +} lsm6dsl_usr_off_w_t; +int32_t lsm6dsl_xl_offset_weight_set(dev_ctx_t *ctx, + lsm6dsl_usr_off_w_t val); +int32_t lsm6dsl_xl_offset_weight_get(dev_ctx_t *ctx, + lsm6dsl_usr_off_w_t *val); + +typedef enum +{ + LSM6DSL_XL_HIGH_PERFORMANCE = 0, + LSM6DSL_XL_NORMAL = 1, + LSM6DSL_XL_PW_MODE_ND = 2, /* ERROR CODE */ +} lsm6dsl_xl_hm_mode_t; +int32_t lsm6dsl_xl_power_mode_set(dev_ctx_t *ctx, + lsm6dsl_xl_hm_mode_t val); +int32_t lsm6dsl_xl_power_mode_get(dev_ctx_t *ctx, + lsm6dsl_xl_hm_mode_t *val); + +typedef enum +{ + LSM6DSL_STAT_RND_DISABLE = 0, + LSM6DSL_STAT_RND_ENABLE = 1, + LSM6DSL_STAT_RND_ND = 2, /* ERROR CODE */ +} lsm6dsl_rounding_status_t; +int32_t lsm6dsl_rounding_on_status_set(dev_ctx_t *ctx, + lsm6dsl_rounding_status_t val); +int32_t lsm6dsl_rounding_on_status_get(dev_ctx_t *ctx, + lsm6dsl_rounding_status_t *val); + +typedef enum +{ + LSM6DSL_GY_HIGH_PERFORMANCE = 0, + LSM6DSL_GY_NORMAL = 1, + LSM6DSL_GY_PW_MODE_ND = 2, /* ERROR CODE */ +} lsm6dsl_g_hm_mode_t; +int32_t lsm6dsl_gy_power_mode_set(dev_ctx_t *ctx, + lsm6dsl_g_hm_mode_t val); +int32_t lsm6dsl_gy_power_mode_get(dev_ctx_t *ctx, + lsm6dsl_g_hm_mode_t *val); + +typedef struct +{ + lsm6dsl_wake_up_src_t wake_up_src; + lsm6dsl_tap_src_t tap_src; + lsm6dsl_d6d_src_t d6d_src; + lsm6dsl_status_reg_t status_reg; + lsm6dsl_func_src1_t func_src1; + lsm6dsl_func_src2_t func_src2; + lsm6dsl_wrist_tilt_ia_t wrist_tilt_ia; + lsm6dsl_a_wrist_tilt_mask_t a_wrist_tilt_mask; +} lsm6dsl_all_sources_t; +int32_t lsm6dsl_all_sources_get(dev_ctx_t *ctx, + lsm6dsl_all_sources_t *val); + +int32_t lsm6dsl_status_reg_get(dev_ctx_t *ctx, + lsm6dsl_status_reg_t *val); + +int32_t lsm6dsl_xl_flag_data_ready_get(dev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsl_gy_flag_data_ready_get(dev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsl_temp_flag_data_ready_get(dev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsl_xl_usr_offset_set(dev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_xl_usr_offset_get(dev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_timestamp_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_timestamp_get(dev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSL_LSB_6ms4 = 0, + LSM6DSL_LSB_25us = 1, + LSM6DSL_TS_RES_ND = 2, /* ERROR CODE */ +} lsm6dsl_timer_hr_t; +int32_t lsm6dsl_timestamp_res_set(dev_ctx_t *ctx, + lsm6dsl_timer_hr_t val); +int32_t lsm6dsl_timestamp_res_get(dev_ctx_t *ctx, + lsm6dsl_timer_hr_t *val); + +typedef enum +{ + LSM6DSL_ROUND_DISABLE = 0, + LSM6DSL_ROUND_XL = 1, + LSM6DSL_ROUND_GY = 2, + LSM6DSL_ROUND_GY_XL = 3, + LSM6DSL_ROUND_SH1_TO_SH6 = 4, + LSM6DSL_ROUND_XL_SH1_TO_SH6 = 5, + LSM6DSL_ROUND_GY_XL_SH1_TO_SH12 = 6, + LSM6DSL_ROUND_GY_XL_SH1_TO_SH6 = 7, + LSM6DSL_ROUND_OUT_ND = 8, /* ERROR CODE */ +} lsm6dsl_rounding_t; +int32_t lsm6dsl_rounding_mode_set(dev_ctx_t *ctx, + lsm6dsl_rounding_t val); +int32_t lsm6dsl_rounding_mode_get(dev_ctx_t *ctx, + lsm6dsl_rounding_t *val); + +int32_t lsm6dsl_temperature_raw_get(dev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsl_angular_rate_raw_get(dev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsl_acceleration_raw_get(dev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsl_mag_calibrated_raw_get(dev_ctx_t *ctx, + int16_t *val); + +int32_t lsm6dsl_fifo_raw_data_get(dev_ctx_t *ctx, uint8_t *buffer, + uint8_t len); + +typedef enum +{ + LSM6DSL_USER_BANK = 0, + LSM6DSL_BANK_A = 4, + LSM6DSL_BANK_B = 5, + LSM6DSL_BANK_ND = 6, /* ERROR CODE */ +} lsm6dsl_func_cfg_en_t; +int32_t lsm6dsl_mem_bank_set(dev_ctx_t *ctx, + lsm6dsl_func_cfg_en_t val); +int32_t lsm6dsl_mem_bank_get(dev_ctx_t *ctx, + lsm6dsl_func_cfg_en_t *val); + +typedef enum +{ + LSM6DSL_DRDY_LATCHED = 0, + LSM6DSL_DRDY_PULSED = 1, + LSM6DSL_DRDY_ND = 2, /* ERROR CODE */ +} lsm6dsl_drdy_pulsed_g_t; +int32_t lsm6dsl_data_ready_mode_set(dev_ctx_t *ctx, + lsm6dsl_drdy_pulsed_g_t val); +int32_t lsm6dsl_data_ready_mode_get(dev_ctx_t *ctx, + lsm6dsl_drdy_pulsed_g_t *val); + +int32_t lsm6dsl_device_id_get(dev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_reset_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_reset_get(dev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSL_LSB_AT_LOW_ADD = 0, + LSM6DSL_MSB_AT_LOW_ADD = 1, + LSM6DSL_DATA_FMT_ND = 2, /* ERROR CODE */ +} lsm6dsl_ble_t; +int32_t lsm6dsl_data_format_set(dev_ctx_t *ctx, lsm6dsl_ble_t val); +int32_t lsm6dsl_data_format_get(dev_ctx_t *ctx, + lsm6dsl_ble_t *val); + +int32_t lsm6dsl_auto_increment_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_auto_increment_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_boot_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_boot_get(dev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSL_XL_ST_DISABLE = 0, + LSM6DSL_XL_ST_POSITIVE = 1, + LSM6DSL_XL_ST_NEGATIVE = 2, + LSM6DSL_XL_ST_ND = 3, /* ERROR CODE */ +} lsm6dsl_st_xl_t; +int32_t lsm6dsl_xl_self_test_set(dev_ctx_t *ctx, + lsm6dsl_st_xl_t val); +int32_t lsm6dsl_xl_self_test_get(dev_ctx_t *ctx, + lsm6dsl_st_xl_t *val); + +typedef enum +{ + LSM6DSL_GY_ST_DISABLE = 0, + LSM6DSL_GY_ST_POSITIVE = 1, + LSM6DSL_GY_ST_NEGATIVE = 3, + LSM6DSL_GY_ST_ND = 4, /* ERROR CODE */ +} lsm6dsl_st_g_t; +int32_t lsm6dsl_gy_self_test_set(dev_ctx_t *ctx, + lsm6dsl_st_g_t val); +int32_t lsm6dsl_gy_self_test_get(dev_ctx_t *ctx, + lsm6dsl_st_g_t *val); + +int32_t lsm6dsl_filter_settling_mask_set(dev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsl_filter_settling_mask_get(dev_ctx_t *ctx, + uint8_t *val); + +typedef enum +{ + LSM6DSL_USE_SLOPE = 0, + LSM6DSL_USE_HPF = 1, + LSM6DSL_HP_PATH_ND = 2, /* ERROR CODE */ +} lsm6dsl_slope_fds_t; +int32_t lsm6dsl_xl_hp_path_internal_set(dev_ctx_t *ctx, + lsm6dsl_slope_fds_t val); +int32_t lsm6dsl_xl_hp_path_internal_get(dev_ctx_t *ctx, + lsm6dsl_slope_fds_t *val); + +typedef enum +{ + LSM6DSL_XL_ANA_BW_1k5Hz = 0, + LSM6DSL_XL_ANA_BW_400Hz = 1, + LSM6DSL_XL_ANA_BW_ND = 2, /* ERROR CODE */ +} lsm6dsl_bw0_xl_t; +int32_t lsm6dsl_xl_filter_analog_set(dev_ctx_t *ctx, + lsm6dsl_bw0_xl_t val); +int32_t lsm6dsl_xl_filter_analog_get(dev_ctx_t *ctx, + lsm6dsl_bw0_xl_t *val); + +typedef enum +{ + LSM6DSL_XL_LP1_ODR_DIV_2 = 0, + LSM6DSL_XL_LP1_ODR_DIV_4 = 1, + LSM6DSL_XL_LP1_NA = 2, /* ERROR CODE */ +} lsm6dsl_lpf1_bw_sel_t; +int32_t lsm6dsl_xl_lp1_bandwidth_set(dev_ctx_t *ctx, + lsm6dsl_lpf1_bw_sel_t val); +int32_t lsm6dsl_xl_lp1_bandwidth_get(dev_ctx_t *ctx, + lsm6dsl_lpf1_bw_sel_t *val); + +typedef enum +{ + LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_50 = 0x00, + LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_100 = 0x01, + LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_9 = 0x02, + LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_400 = 0x03, + LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_50 = 0x10, + LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_100 = 0x11, + LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_9 = 0x12, + LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_400 = 0x13, + LSM6DSL_XL_LP_NA = 0x20, /* ERROR CODE */ +} lsm6dsl_input_composite_t; +int32_t lsm6dsl_xl_lp2_bandwidth_set(dev_ctx_t *ctx, + lsm6dsl_input_composite_t val); +int32_t lsm6dsl_xl_lp2_bandwidth_get(dev_ctx_t *ctx, + lsm6dsl_input_composite_t *val); + +int32_t lsm6dsl_xl_reference_mode_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_xl_reference_mode_get(dev_ctx_t *ctx, + uint8_t *val); + +typedef enum +{ + LSM6DSL_XL_HP_ODR_DIV_4 = 0x00, /* Slope filter */ + LSM6DSL_XL_HP_ODR_DIV_100 = 0x01, + LSM6DSL_XL_HP_ODR_DIV_9 = 0x02, + LSM6DSL_XL_HP_ODR_DIV_400 = 0x03, + LSM6DSL_XL_HP_NA = 0x10, /* ERROR CODE */ +} lsm6dsl_hpcf_xl_t; +int32_t lsm6dsl_xl_hp_bandwidth_set(dev_ctx_t *ctx, + lsm6dsl_hpcf_xl_t val); +int32_t lsm6dsl_xl_hp_bandwidth_get(dev_ctx_t *ctx, + lsm6dsl_hpcf_xl_t *val); + +typedef enum +{ + LSM6DSL_LP2_ONLY = 0x00, + + LSM6DSL_HP_16mHz_LP2 = 0x80, + LSM6DSL_HP_65mHz_LP2 = 0x90, + LSM6DSL_HP_260mHz_LP2 = 0xA0, + LSM6DSL_HP_1Hz04_LP2 = 0xB0, + + LSM6DSL_HP_DISABLE_LP1_LIGHT = 0x0A, + LSM6DSL_HP_DISABLE_LP1_NORMAL = 0x09, + LSM6DSL_HP_DISABLE_LP_STRONG = 0x08, + LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE = 0x0B, + + LSM6DSL_HP_16mHz_LP1_LIGHT = 0x8A, + LSM6DSL_HP_65mHz_LP1_NORMAL = 0x99, + LSM6DSL_HP_260mHz_LP1_STRONG = 0xA8, + LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE = 0xBB, + + LSM6DSL_HP_GY_BAND_NA = 0xFF, /* ERROR CODE */ +} lsm6dsl_lpf1_sel_g_t; +int32_t lsm6dsl_gy_band_pass_set(dev_ctx_t *ctx, + lsm6dsl_lpf1_sel_g_t val); +int32_t lsm6dsl_gy_band_pass_get(dev_ctx_t *ctx, + lsm6dsl_lpf1_sel_g_t *val); + +typedef enum +{ + LSM6DSL_SPI_4_WIRE = 0, + LSM6DSL_SPI_3_WIRE = 1, + LSM6DSL_SPI_MODE_ND = 2, /* ERROR CODE */ +} lsm6dsl_sim_t; +int32_t lsm6dsl_spi_mode_set(dev_ctx_t *ctx, lsm6dsl_sim_t val); +int32_t lsm6dsl_spi_mode_get(dev_ctx_t *ctx, lsm6dsl_sim_t *val); + +typedef enum +{ + LSM6DSL_I2C_ENABLE = 0, + LSM6DSL_I2C_DISABLE = 1, + LSM6DSL_I2C_MODE_ND = 2, /* ERROR CODE */ +} lsm6dsl_i2c_disable_t; +int32_t lsm6dsl_i2c_interface_set(dev_ctx_t *ctx, + lsm6dsl_i2c_disable_t val); +int32_t lsm6dsl_i2c_interface_get(dev_ctx_t *ctx, + lsm6dsl_i2c_disable_t *val); + +typedef struct +{ + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t int1_fth : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_full_flag : 1; + uint8_t int1_sign_mot : 1; + uint8_t int1_step_detector : 1; + uint8_t int1_timer : 1; + uint8_t int1_tilt : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_inact_state : 1; + uint8_t den_drdy_int1 : 1; + uint8_t drdy_on_int1 : 1; +} lsm6dsl_int1_route_t; +int32_t lsm6dsl_pin_int1_route_set(dev_ctx_t *ctx, + lsm6dsl_int1_route_t val); +int32_t lsm6dsl_pin_int1_route_get(dev_ctx_t *ctx, + lsm6dsl_int1_route_t *val); + +typedef struct +{ + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_fth : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_full_flag : 1; + uint8_t int2_step_count_ov : 1; + uint8_t int2_step_delta : 1; + uint8_t int2_iron : 1; + uint8_t int2_tilt : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_inact_state : 1; + uint8_t int2_wrist_tilt : 1; +} lsm6dsl_int2_route_t; +int32_t lsm6dsl_pin_int2_route_set(dev_ctx_t *ctx, + lsm6dsl_int2_route_t val); +int32_t lsm6dsl_pin_int2_route_get(dev_ctx_t *ctx, + lsm6dsl_int2_route_t *val); + +typedef enum +{ + LSM6DSL_PUSH_PULL = 0, + LSM6DSL_OPEN_DRAIN = 1, + LSM6DSL_PIN_MODE_ND = 2, /* ERROR CODE */ +} lsm6dsl_pp_od_t; +int32_t lsm6dsl_pin_mode_set(dev_ctx_t *ctx, lsm6dsl_pp_od_t val); +int32_t lsm6dsl_pin_mode_get(dev_ctx_t *ctx, lsm6dsl_pp_od_t *val); + +typedef enum +{ + LSM6DSL_ACTIVE_HIGH = 0, + LSM6DSL_ACTIVE_LOW = 1, + LSM6DSL_POLARITY_ND = 2, /* ERROR CODE */ +} lsm6dsl_h_lactive_t; +int32_t lsm6dsl_pin_polarity_set(dev_ctx_t *ctx, + lsm6dsl_h_lactive_t val); +int32_t lsm6dsl_pin_polarity_get(dev_ctx_t *ctx, + lsm6dsl_h_lactive_t *val); + +int32_t lsm6dsl_all_on_int1_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_all_on_int1_get(dev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSL_INT_PULSED = 0, + LSM6DSL_INT_LATCHED = 1, + LSM6DSL_INT_MODE = 2, /* ERROR CODE */ +} lsm6dsl_lir_t; +int32_t lsm6dsl_int_notification_set(dev_ctx_t *ctx, + lsm6dsl_lir_t val); +int32_t lsm6dsl_int_notification_get(dev_ctx_t *ctx, + lsm6dsl_lir_t *val); + +int32_t lsm6dsl_wkup_threshold_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_wkup_threshold_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_wkup_dur_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_wkup_dur_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_gy_sleep_mode_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_gy_sleep_mode_get(dev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSL_PROPERTY_DISABLE = 0, + LSM6DSL_XL_12Hz5_GY_NOT_AFFECTED = 1, + LSM6DSL_XL_12Hz5_GY_SLEEP = 2, + LSM6DSL_XL_12Hz5_GY_PD = 3, + LSM6DSL_ACT_MODE_ND = 4, /* ERROR CODE */ +} lsm6dsl_inact_en_t; +int32_t lsm6dsl_act_mode_set(dev_ctx_t *ctx, + lsm6dsl_inact_en_t val); +int32_t lsm6dsl_act_mode_get(dev_ctx_t *ctx, + lsm6dsl_inact_en_t *val); + +int32_t lsm6dsl_act_sleep_dur_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_act_sleep_dur_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_tap_src_get(dev_ctx_t *ctx, + lsm6dsl_tap_src_t *val); + +int32_t lsm6dsl_tap_detection_on_z_set(dev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsl_tap_detection_on_z_get(dev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsl_tap_detection_on_y_set(dev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsl_tap_detection_on_y_get(dev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsl_tap_detection_on_x_set(dev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsl_tap_detection_on_x_get(dev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsl_tap_threshold_x_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_tap_threshold_x_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_tap_shock_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_tap_shock_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_tap_quiet_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_tap_quiet_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_tap_dur_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_tap_dur_get(dev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSL_ONLY_SINGLE = 0, + LSM6DSL_BOTH_SINGLE_DOUBLE = 1, + LSM6DSL_TAP_MODE_ND = 2, /* ERROR CODE */ +} lsm6dsl_single_double_tap_t; +int32_t lsm6dsl_tap_mode_set(dev_ctx_t *ctx, + lsm6dsl_single_double_tap_t val); +int32_t lsm6dsl_tap_mode_get(dev_ctx_t *ctx, + lsm6dsl_single_double_tap_t *val); + +typedef enum +{ + LSM6DSL_ODR_DIV_2_FEED = 0, + LSM6DSL_LPF2_FEED = 1, + LSM6DSL_6D_FEED_ND = 2, /* ERROR CODE */ +} lsm6dsl_low_pass_on_6d_t; +int32_t lsm6dsl_6d_feed_data_set(dev_ctx_t *ctx, + lsm6dsl_low_pass_on_6d_t val); +int32_t lsm6dsl_6d_feed_data_get(dev_ctx_t *ctx, + lsm6dsl_low_pass_on_6d_t *val); + +typedef enum +{ + LSM6DSL_DEG_80 = 0, + LSM6DSL_DEG_70 = 1, + LSM6DSL_DEG_60 = 2, + LSM6DSL_DEG_50 = 3, + LSM6DSL_6D_TH_ND = 4, /* ERROR CODE */ +} lsm6dsl_sixd_ths_t; +int32_t lsm6dsl_6d_threshold_set(dev_ctx_t *ctx, + lsm6dsl_sixd_ths_t val); +int32_t lsm6dsl_6d_threshold_get(dev_ctx_t *ctx, + lsm6dsl_sixd_ths_t *val); + +int32_t lsm6dsl_4d_mode_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_4d_mode_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_ff_dur_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_ff_dur_get(dev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSL_FF_TSH_156mg = 0, + LSM6DSL_FF_TSH_219mg = 1, + LSM6DSL_FF_TSH_250mg = 2, + LSM6DSL_FF_TSH_312mg = 3, + LSM6DSL_FF_TSH_344mg = 4, + LSM6DSL_FF_TSH_406mg = 5, + LSM6DSL_FF_TSH_469mg = 6, + LSM6DSL_FF_TSH_500mg = 7, + LSM6DSL_FF_TSH_ND = 8, /* ERROR CODE */ +} lsm6dsl_ff_ths_t; +int32_t lsm6dsl_ff_threshold_set(dev_ctx_t *ctx, + lsm6dsl_ff_ths_t val); +int32_t lsm6dsl_ff_threshold_get(dev_ctx_t *ctx, + lsm6dsl_ff_ths_t *val); + +int32_t lsm6dsl_fifo_watermark_set(dev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsl_fifo_watermark_get(dev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsl_fifo_data_level_get(dev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsl_fifo_wtm_flag_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_fifo_pattern_get(dev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsl_fifo_temp_batch_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_fifo_temp_batch_get(dev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSL_TRG_XL_GY_DRDY = 0, + LSM6DSL_TRG_STEP_DETECT = 1, + LSM6DSL_TRG_SH_DRDY = 2, + LSM6DSL_TRG_SH_ND = 3, /* ERROR CODE */ +} lsm6dsl_trigger_fifo_t; +int32_t lsm6dsl_fifo_write_trigger_set(dev_ctx_t *ctx, + lsm6dsl_trigger_fifo_t val); +int32_t lsm6dsl_fifo_write_trigger_get(dev_ctx_t *ctx, + lsm6dsl_trigger_fifo_t *val); + +int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_set(dev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(dev_ctx_t *ctx, + uint8_t *val); + +typedef enum +{ + LSM6DSL_FIFO_XL_DISABLE = 0, + LSM6DSL_FIFO_XL_NO_DEC = 1, + LSM6DSL_FIFO_XL_DEC_2 = 2, + LSM6DSL_FIFO_XL_DEC_3 = 3, + LSM6DSL_FIFO_XL_DEC_4 = 4, + LSM6DSL_FIFO_XL_DEC_8 = 5, + LSM6DSL_FIFO_XL_DEC_16 = 6, + LSM6DSL_FIFO_XL_DEC_32 = 7, + LSM6DSL_FIFO_XL_DEC_ND = 8, /* ERROR CODE */ +} lsm6dsl_dec_fifo_xl_t; +int32_t lsm6dsl_fifo_xl_batch_set(dev_ctx_t *ctx, + lsm6dsl_dec_fifo_xl_t val); +int32_t lsm6dsl_fifo_xl_batch_get(dev_ctx_t *ctx, + lsm6dsl_dec_fifo_xl_t *val); + +typedef enum +{ + LSM6DSL_FIFO_GY_DISABLE = 0, + LSM6DSL_FIFO_GY_NO_DEC = 1, + LSM6DSL_FIFO_GY_DEC_2 = 2, + LSM6DSL_FIFO_GY_DEC_3 = 3, + LSM6DSL_FIFO_GY_DEC_4 = 4, + LSM6DSL_FIFO_GY_DEC_8 = 5, + LSM6DSL_FIFO_GY_DEC_16 = 6, + LSM6DSL_FIFO_GY_DEC_32 = 7, + LSM6DSL_FIFO_GY_DEC_ND = 8, /* ERROR CODE */ +} lsm6dsl_dec_fifo_gyro_t; +int32_t lsm6dsl_fifo_gy_batch_set(dev_ctx_t *ctx, + lsm6dsl_dec_fifo_gyro_t val); +int32_t lsm6dsl_fifo_gy_batch_get(dev_ctx_t *ctx, + lsm6dsl_dec_fifo_gyro_t *val); + +typedef enum +{ + LSM6DSL_FIFO_DS3_DISABLE = 0, + LSM6DSL_FIFO_DS3_NO_DEC = 1, + LSM6DSL_FIFO_DS3_DEC_2 = 2, + LSM6DSL_FIFO_DS3_DEC_3 = 3, + LSM6DSL_FIFO_DS3_DEC_4 = 4, + LSM6DSL_FIFO_DS3_DEC_8 = 5, + LSM6DSL_FIFO_DS3_DEC_16 = 6, + LSM6DSL_FIFO_DS3_DEC_32 = 7, + LSM6DSL_FIFO_DS3_DEC_ND = 8, /* ERROR CODE */ +} lsm6dsl_dec_ds3_fifo_t; +int32_t lsm6dsl_fifo_dataset_3_batch_set(dev_ctx_t *ctx, + lsm6dsl_dec_ds3_fifo_t val); +int32_t lsm6dsl_fifo_dataset_3_batch_get(dev_ctx_t *ctx, + lsm6dsl_dec_ds3_fifo_t *val); + +typedef enum +{ + LSM6DSL_FIFO_DS4_DISABLE = 0, + LSM6DSL_FIFO_DS4_NO_DEC = 1, + LSM6DSL_FIFO_DS4_DEC_2 = 2, + LSM6DSL_FIFO_DS4_DEC_3 = 3, + LSM6DSL_FIFO_DS4_DEC_4 = 4, + LSM6DSL_FIFO_DS4_DEC_8 = 5, + LSM6DSL_FIFO_DS4_DEC_16 = 6, + LSM6DSL_FIFO_DS4_DEC_32 = 7, + LSM6DSL_FIFO_DS4_DEC_ND = 8, /* ERROR CODE */ +} lsm6dsl_dec_ds4_fifo_t; +int32_t lsm6dsl_fifo_dataset_4_batch_set(dev_ctx_t *ctx, + lsm6dsl_dec_ds4_fifo_t val); +int32_t lsm6dsl_fifo_dataset_4_batch_get(dev_ctx_t *ctx, + lsm6dsl_dec_ds4_fifo_t *val); + +int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(dev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(dev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsl_fifo_stop_on_wtm_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_fifo_stop_on_wtm_get(dev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSL_BYPASS_MODE = 0, + LSM6DSL_FIFO_MODE = 1, + LSM6DSL_STREAM_TO_FIFO_MODE = 3, + LSM6DSL_BYPASS_TO_STREAM_MODE = 4, + LSM6DSL_STREAM_MODE = 6, + LSM6DSL_FIFO_MODE_ND = 8, /* ERROR CODE */ +} lsm6dsl_fifo_mode_t; +int32_t lsm6dsl_fifo_mode_set(dev_ctx_t *ctx, + lsm6dsl_fifo_mode_t val); +int32_t lsm6dsl_fifo_mode_get(dev_ctx_t *ctx, + lsm6dsl_fifo_mode_t *val); + +typedef enum +{ + LSM6DSL_FIFO_DISABLE = 0, + LSM6DSL_FIFO_12Hz5 = 1, + LSM6DSL_FIFO_26Hz = 2, + LSM6DSL_FIFO_52Hz = 3, + LSM6DSL_FIFO_104Hz = 4, + LSM6DSL_FIFO_208Hz = 5, + LSM6DSL_FIFO_416Hz = 6, + LSM6DSL_FIFO_833Hz = 7, + LSM6DSL_FIFO_1k66Hz = 8, + LSM6DSL_FIFO_3k33Hz = 9, + LSM6DSL_FIFO_6k66Hz = 10, + LSM6DSL_FIFO_RATE_ND = 11, /* ERROR CODE */ +} lsm6dsl_odr_fifo_t; +int32_t lsm6dsl_fifo_data_rate_set(dev_ctx_t *ctx, + lsm6dsl_odr_fifo_t val); +int32_t lsm6dsl_fifo_data_rate_get(dev_ctx_t *ctx, + lsm6dsl_odr_fifo_t *val); + +typedef enum +{ + LSM6DSL_DEN_ACT_LOW = 0, + LSM6DSL_DEN_ACT_HIGH = 1, + LSM6DSL_DEN_POL_ND = 2, /* ERROR CODE */ +} lsm6dsl_den_lh_t; +int32_t lsm6dsl_den_polarity_set(dev_ctx_t *ctx, + lsm6dsl_den_lh_t val); +int32_t lsm6dsl_den_polarity_get(dev_ctx_t *ctx, + lsm6dsl_den_lh_t *val); + +typedef enum +{ + LSM6DSL_DEN_DISABLE = 0, + LSM6DSL_LEVEL_FIFO = 6, + LSM6DSL_LEVEL_LETCHED = 3, + LSM6DSL_LEVEL_TRIGGER = 2, + LSM6DSL_EDGE_TRIGGER = 4, + LSM6DSL_DEN_MODE_ND = 5, /* ERROR CODE */ +} lsm6dsl_den_mode_t; +int32_t lsm6dsl_den_mode_set(dev_ctx_t *ctx, + lsm6dsl_den_mode_t val); +int32_t lsm6dsl_den_mode_get(dev_ctx_t *ctx, + lsm6dsl_den_mode_t *val); + +typedef enum +{ + LSM6DSL_STAMP_IN_GY_DATA = 0, + LSM6DSL_STAMP_IN_XL_DATA = 1, + LSM6DSL_STAMP_IN_GY_XL_DATA = 2, + LSM6DSL_DEN_STAMP_ND = 3, /* ERROR CODE */ +} lsm6dsl_den_xl_en_t; +int32_t lsm6dsl_den_enable_set(dev_ctx_t *ctx, + lsm6dsl_den_xl_en_t val); +int32_t lsm6dsl_den_enable_get(dev_ctx_t *ctx, + lsm6dsl_den_xl_en_t *val); + +int32_t lsm6dsl_den_mark_axis_z_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_den_mark_axis_z_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_den_mark_axis_y_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_den_mark_axis_y_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_den_mark_axis_x_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_den_mark_axis_x_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_pedo_step_reset_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_pedo_step_reset_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_pedo_sens_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_pedo_sens_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_pedo_threshold_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_pedo_threshold_get(dev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSL_PEDO_AT_2g = 0, + LSM6DSL_PEDO_AT_4g = 1, + LSM6DSL_PEDO_FS_ND = 2, /* ERROR CODE */ +} lsm6dsl_pedo_fs_t; +int32_t lsm6dsl_pedo_full_scale_set(dev_ctx_t *ctx, + lsm6dsl_pedo_fs_t val); +int32_t lsm6dsl_pedo_full_scale_get(dev_ctx_t *ctx, + lsm6dsl_pedo_fs_t *val); + +int32_t lsm6dsl_pedo_debounce_steps_set(dev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsl_pedo_debounce_steps_get(dev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsl_pedo_timeout_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_pedo_timeout_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_pedo_steps_period_set(dev_ctx_t *ctx, + uint8_t *buff); +int32_t lsm6dsl_pedo_steps_period_get(dev_ctx_t *ctx, + uint8_t *buff); + +int32_t lsm6dsl_motion_sens_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_motion_sens_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_motion_threshold_set(dev_ctx_t *ctx, + uint8_t *buff); +int32_t lsm6dsl_motion_threshold_get(dev_ctx_t *ctx, + uint8_t *buff); + +int32_t lsm6dsl_tilt_sens_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_tilt_sens_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_wrist_tilt_sens_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_wrist_tilt_sens_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_tilt_latency_set(dev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_tilt_latency_get(dev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsl_tilt_threshold_set(dev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_tilt_threshold_get(dev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsl_tilt_src_set(dev_ctx_t *ctx, + lsm6dsl_a_wrist_tilt_mask_t *val); +int32_t lsm6dsl_tilt_src_get(dev_ctx_t *ctx, + lsm6dsl_a_wrist_tilt_mask_t *val); + +int32_t lsm6dsl_mag_soft_iron_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_mag_soft_iron_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_mag_hard_iron_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_mag_hard_iron_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_mag_soft_iron_mat_set(dev_ctx_t *ctx, + uint8_t *buff); +int32_t lsm6dsl_mag_soft_iron_mat_get(dev_ctx_t *ctx, + uint8_t *buff); + +int32_t lsm6dsl_mag_offset_set(dev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsl_mag_offset_get(dev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsl_func_en_set(dev_ctx_t *ctx, uint8_t val); + +int32_t lsm6dsl_sh_sync_sens_frame_set(dev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsl_sh_sync_sens_frame_get(dev_ctx_t *ctx, + uint8_t *val); + +typedef enum +{ + LSM6DSL_RES_RATIO_2_11 = 0, + LSM6DSL_RES_RATIO_2_12 = 1, + LSM6DSL_RES_RATIO_2_13 = 2, + LSM6DSL_RES_RATIO_2_14 = 3, + LSM6DSL_RES_RATIO_ND = 4, /* ERROR CODE */ +} lsm6dsl_rr_t; +int32_t lsm6dsl_sh_sync_sens_ratio_set(dev_ctx_t *ctx, + lsm6dsl_rr_t val); +int32_t lsm6dsl_sh_sync_sens_ratio_get(dev_ctx_t *ctx, + lsm6dsl_rr_t *val); + +int32_t lsm6dsl_sh_master_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_sh_master_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_sh_pass_through_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_sh_pass_through_get(dev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSL_EXT_PULL_UP = 0, + LSM6DSL_INTERNAL_PULL_UP = 1, + LSM6DSL_SH_PIN_MODE = 2, /* ERROR CODE */ +} lsm6dsl_pull_up_en_t; +int32_t lsm6dsl_sh_pin_mode_set(dev_ctx_t *ctx, + lsm6dsl_pull_up_en_t val); +int32_t lsm6dsl_sh_pin_mode_get(dev_ctx_t *ctx, + lsm6dsl_pull_up_en_t *val); + +typedef enum +{ + LSM6DSL_XL_GY_DRDY = 0, + LSM6DSL_EXT_ON_INT2_PIN = 1, + LSM6DSL_SH_SYNCRO_ND = 2, /* ERROR CODE */ +} lsm6dsl_start_config_t; +int32_t lsm6dsl_sh_syncro_mode_set(dev_ctx_t *ctx, + lsm6dsl_start_config_t val); +int32_t lsm6dsl_sh_syncro_mode_get(dev_ctx_t *ctx, + lsm6dsl_start_config_t *val); + +int32_t lsm6dsl_sh_drdy_on_int1_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_sh_drdy_on_int1_get(dev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + lsm6dsl_sensorhub1_reg_t sh_byte_1; + lsm6dsl_sensorhub2_reg_t sh_byte_2; + lsm6dsl_sensorhub3_reg_t sh_byte_3; + lsm6dsl_sensorhub4_reg_t sh_byte_4; + lsm6dsl_sensorhub5_reg_t sh_byte_5; + lsm6dsl_sensorhub6_reg_t sh_byte_6; + lsm6dsl_sensorhub7_reg_t sh_byte_7; + lsm6dsl_sensorhub8_reg_t sh_byte_8; + lsm6dsl_sensorhub9_reg_t sh_byte_9; + lsm6dsl_sensorhub10_reg_t sh_byte_10; + lsm6dsl_sensorhub11_reg_t sh_byte_11; + lsm6dsl_sensorhub12_reg_t sh_byte_12; + lsm6dsl_sensorhub13_reg_t sh_byte_13; + lsm6dsl_sensorhub14_reg_t sh_byte_14; + lsm6dsl_sensorhub15_reg_t sh_byte_15; + lsm6dsl_sensorhub16_reg_t sh_byte_16; + lsm6dsl_sensorhub17_reg_t sh_byte_17; + lsm6dsl_sensorhub18_reg_t sh_byte_18; +} lsm6dsl_emb_sh_read_t; +int32_t lsm6dsl_sh_read_data_raw_get(dev_ctx_t *ctx, + lsm6dsl_emb_sh_read_t *val); + +int32_t lsm6dsl_sh_cmd_sens_sync_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_sh_cmd_sens_sync_get(dev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsl_sh_spi_sync_error_set(dev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_sh_spi_sync_error_get(dev_ctx_t *ctx, + uint8_t *val); + +typedef enum +{ + LSM6DSL_SLV_0 = 0, + LSM6DSL_SLV_0_1 = 1, + LSM6DSL_SLV_0_1_2 = 2, + LSM6DSL_SLV_0_1_2_3 = 3, + LSM6DSL_SLV_EN_ND = 4, /* ERROR CODE */ +} lsm6dsl_aux_sens_on_t; +int32_t lsm6dsl_sh_num_of_dev_connected_set(dev_ctx_t *ctx, + lsm6dsl_aux_sens_on_t val); +int32_t lsm6dsl_sh_num_of_dev_connected_get(dev_ctx_t *ctx, + lsm6dsl_aux_sens_on_t *val); + +typedef struct +{ + uint8_t slv0_add; + uint8_t slv0_subadd; + uint8_t slv0_data; +} lsm6dsl_sh_cfg_write_t; +int32_t lsm6dsl_sh_cfg_write(dev_ctx_t *ctx, + lsm6dsl_sh_cfg_write_t *val); + +typedef struct +{ + uint8_t slv_add; + uint8_t slv_subadd; + uint8_t slv_len; +} lsm6dsl_sh_cfg_read_t; +int32_t lsm6dsl_sh_slv0_cfg_read(dev_ctx_t *ctx, + lsm6dsl_sh_cfg_read_t *val); +int32_t lsm6dsl_sh_slv1_cfg_read(dev_ctx_t *ctx, + lsm6dsl_sh_cfg_read_t *val); +int32_t lsm6dsl_sh_slv2_cfg_read(dev_ctx_t *ctx, + lsm6dsl_sh_cfg_read_t *val); +int32_t lsm6dsl_sh_slv3_cfg_read(dev_ctx_t *ctx, + lsm6dsl_sh_cfg_read_t *val); + +typedef enum +{ + LSM6DSL_SL0_NO_DEC = 0, + LSM6DSL_SL0_DEC_2 = 1, + LSM6DSL_SL0_DEC_4 = 2, + LSM6DSL_SL0_DEC_8 = 3, + LSM6DSL_SL0_DEC_ND = 4, /* ERROR CODE */ +} lsm6dsl_slave0_rate_t; +int32_t lsm6dsl_sh_slave_0_dec_set(dev_ctx_t *ctx, + lsm6dsl_slave0_rate_t val); +int32_t lsm6dsl_sh_slave_0_dec_get(dev_ctx_t *ctx, + lsm6dsl_slave0_rate_t *val); + +typedef enum +{ + LSM6DSL_EACH_SH_CYCLE = 0, + LSM6DSL_ONLY_FIRST_CYCLE = 1, + LSM6DSL_SH_WR_MODE_ND = 2, /* ERROR CODE */ +} lsm6dsl_write_once_t; +int32_t lsm6dsl_sh_write_mode_set(dev_ctx_t *ctx, + lsm6dsl_write_once_t val); +int32_t lsm6dsl_sh_write_mode_get(dev_ctx_t *ctx, + lsm6dsl_write_once_t *val); + +typedef enum +{ + LSM6DSL_SL1_NO_DEC = 0, + LSM6DSL_SL1_DEC_2 = 1, + LSM6DSL_SL1_DEC_4 = 2, + LSM6DSL_SL1_DEC_8 = 3, + LSM6DSL_SL1_DEC_ND = 4, /* ERROR CODE */ +} lsm6dsl_slave1_rate_t; +int32_t lsm6dsl_sh_slave_1_dec_set(dev_ctx_t *ctx, + lsm6dsl_slave1_rate_t val); +int32_t lsm6dsl_sh_slave_1_dec_get(dev_ctx_t *ctx, + lsm6dsl_slave1_rate_t *val); + +typedef enum +{ + LSM6DSL_SL2_NO_DEC = 0, + LSM6DSL_SL2_DEC_2 = 1, + LSM6DSL_SL2_DEC_4 = 2, + LSM6DSL_SL2_DEC_8 = 3, + LSM6DSL_SL2_DEC_ND = 4, /* ERROR CODE */ +} lsm6dsl_slave2_rate_t; +int32_t lsm6dsl_sh_slave_2_dec_set(dev_ctx_t *ctx, + lsm6dsl_slave2_rate_t val); +int32_t lsm6dsl_sh_slave_2_dec_get(dev_ctx_t *ctx, + lsm6dsl_slave2_rate_t *val); + +typedef enum +{ + LSM6DSL_SL3_NO_DEC = 0, + LSM6DSL_SL3_DEC_2 = 1, + LSM6DSL_SL3_DEC_4 = 2, + LSM6DSL_SL3_DEC_8 = 3, + LSM6DSL_SL3_DEC_ND = 4, /* ERROR CODE */ +} lsm6dsl_slave3_rate_t; +int32_t lsm6dsl_sh_slave_3_dec_set(dev_ctx_t *ctx, + lsm6dsl_slave3_rate_t val); +int32_t lsm6dsl_sh_slave_3_dec_get(dev_ctx_t *ctx, + lsm6dsl_slave3_rate_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* LSM6DSL_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Module/mmc5983/mmc5983.c b/Module/mmc5983/mmc5983.c new file mode 100644 index 0000000..8b03eed --- /dev/null +++ b/Module/mmc5983/mmc5983.c @@ -0,0 +1,343 @@ +#include "main.h" +#include "mmc5983.h" +#include "UartDebug.h" +#include "i2c.h" +#include "Algorithm.h" + +static int32_t max_in[XYZ]; +static int32_t min_in[XYZ]; +static bool InitFlag; +static bool MMC5983IntFlag; +static MMC5983Var_t MMC5983Var; + +/***************************************************************************************** +* 函数名称: MMC5983_Write_Reg +* 功能描述: MMC5983写寄存器 +* 参 数: reg 寄存器地址 + val 寄存器数据 +* 返 回 值: 成功返回true，失败返回false +*****************************************************************************************/ +static bool MMC5983_Write_Reg(uint8_t reg, uint8_t val) +{ + return I2C_MasterWriteData(M0P_I2C0, MMC5983_ADDRESS, reg, &val, 1); +} + +/***************************************************************************************** +* 函数名称: MMC5983_Read_Reg +* 功能描述: MMC5983读寄存器 +* 参 数: reg 寄存器地址 +* 返 回 值: 返回寄存器值 +*****************************************************************************************/ +static uint8_t MMC5983_Read_Reg(uint8_t reg) +{ + uint8_t res; + if(I2C_MasterReadData(M0P_I2C0, MMC5983_ADDRESS, reg, &res, 1) == false) + res = 0; + return res; +} + +/***************************************************************************************** +* 函数名称: MMC5983_Read_Buffer +* 功能描述: MMC5983读数据 +* 参 数: reg 寄存器地址 + buffer 读取数据输出缓存入口 + len 读取长度 +* 返 回 值: 成功返回true，失败返回false +*****************************************************************************************/ +static bool MMC5983_Read_Buffer(uint8_t reg, void *buffer, uint8_t len) +{ + return I2C_MasterReadData(M0P_I2C0, MMC5983_ADDRESS, reg, buffer, len); +} + +/***************************************************************************************** +* 函数名称: MMC5983StartCov +* 功能描述: MMC5983开启连续转换 +* 参 数: 无 +* 返 回 值: 无 +*****************************************************************************************/ +static void MMC5983StartCov(void) +{ + MMC5983RegCtrl2 Ctrl2Reg; //开启/关闭连续转换 + Ctrl2Reg.Byte = 0x00; + Ctrl2Reg.Bit.Cm_freq = 0x04; + Ctrl2Reg.Bit.Cmm_en = 1; //连续设1，单次设0 + Ctrl2Reg.Bit.Prd_set = 3; + Ctrl2Reg.Bit.En_prd_set = 1; //连续设1，单次设0 + MMC5983_Write_Reg(MMC5983_CTRL_2, Ctrl2Reg.Byte); +} + +/***************************************************************************************** +* 函数名称: MMC5983_Init +* 功能描述: MMC5983初始化 +* 参 数: 无 +* 返 回 值: 无 +*****************************************************************************************/ +static void MMC5983_Init(void) +{ + uint8_t id; + + id = MMC5983_Read_Reg(MMC5983_ID); + //DBG_LOG("MMC5983 id=0x%x\r\n",id); + MMC5983Var.MMC5983Delay1mSCnt = 100; + while(id != 0x30){ + if(MMC5983Var.MMC5983Delay1mSCnt <= 0) { + DBG_LOG("LEFT MMC5983 INIT Err...\r\n"); + InitFlag = false; + return; + } + } + + MMC5983RegCtrl1 Ctrl1Reg; + Ctrl1Reg.Byte = 0x00; + Ctrl1Reg.Bit.SW_RST = 1; + MMC5983_Write_Reg(MMC5983_CTRL_1, Ctrl1Reg.Byte); + MMC5983Delay(15); + + MMC5983RegCtrl2 Ctrl2Reg; //开启/关闭连续转换 + Ctrl2Reg.Byte = 0x00; + Ctrl2Reg.Bit.Cm_freq = 0x04; + Ctrl2Reg.Bit.Cmm_en = 0; //连续设1，单次设0 + Ctrl2Reg.Bit.Prd_set = 3; + Ctrl2Reg.Bit.En_prd_set = 0; //连续设1，单次设0 + MMC5983_Write_Reg(MMC5983_CTRL_2, Ctrl2Reg.Byte); + + MMC5983RegCtrl3 Ctrl3Reg; + Ctrl3Reg.Byte = 0x00; + Ctrl3Reg.Bit.St_enm = 1; + Ctrl3Reg.Bit.St_enp = 1; + MMC5983_Write_Reg(MMC5983_CTRL_3, Ctrl3Reg.Byte); + + MMC5983RegCtrl0 Ctrl0Reg; + Ctrl0Reg.Byte = 0x00; + Ctrl0Reg.Bit.TM_M = 1; + Ctrl0Reg.Bit.Auto_SR_en = 1; + Ctrl0Reg.Bit.NT_meas_done_en = 1; + MMC5983_Write_Reg(MMC5983_CTRL_0, Ctrl0Reg.Byte); + + if(InitFlag == false){ + DBG_LOG("MMC5983 INIT OK...\r\n"); + InitFlag = true; + } +} + +/***************************************************************************************** +* 函数名称: MMC5983_Read +* 功能描述: MMC5983读取原始数据 +* 参 数: MagAdcX X轴数据 + MagAdcY Y轴数据 + MagAdcZ Z轴数据 +* 返 回 值: 成功返回true，失败返回false +*****************************************************************************************/ +static bool MMC5983_Read(int32_t *MagAdcX, int32_t *MagAdcY, int32_t *MagAdcZ) +{ + static uint8_t buff[7]; + + if (MMC5983_Read_Buffer(MMC5983_X_OUT_H, buff, 7) == false) + return false; + + *MagAdcX = (buff[0] << 10) | (buff[1] << 2) | ((buff[6] & 0xC0) >> 6); + *MagAdcY = (buff[2] << 10) | (buff[3] << 2) | ((buff[6] & 0x30) >> 4); + *MagAdcZ = (buff[4] << 10) | (buff[5] << 2) | ((buff[6] & 0x0C) >> 2);// Turn the 18 bits into unsigned 32-bit value + return true; +} + +/***************************************************************************************** +* 函数名称: MMC5983_Get_Mag +* 功能描述: 外部获取MMC5983磁场强度数据 +* 参 数: mag 读取数据输出缓存入口 +* 返 回 值: 无 +*****************************************************************************************/ +void MMC5983_Get_Mag(float *mag) +{ + if(mag == NULL) + return; + + float ADVal[XYZ]; + + ADVal[X] = MMC5983Var.Mag_Original[X] - 131072.0f; + ADVal[Y] = MMC5983Var.Mag_Original[Y] - 131072.0f; + ADVal[Z] = MMC5983Var.Mag_Original[Z] - 131072.0f; + + mag[0] = (float) (ADVal[X] * MMC5983_MAG_SCALE_18BIT); + mag[1] = (float) (ADVal[Y] * MMC5983_MAG_SCALE_18BIT); + mag[2] = (float) (ADVal[Z] * MMC5983_MAG_SCALE_18BIT); +} + +/***************************************************************************************** +* 函数名称: MMC5983LoopHandler +* 功能描述: MMC5983循环处理函数 +* 参 数: 无 +* 返 回 值: 无 +*****************************************************************************************/ +extern void MmcDataProcessCallBack(float *Mag); + +void MMC5983LoopHandler(void) +{ + static int32_t mag_array[XYZ][10]; + static uint8_t magcnt; + static uint8_t TimeOutMagcnt; + + switch(MMC5983Var.Status) { + case MMC5983_STATUS_IDLE:{ + break;} + + case MMC5983_STATUS_START:{ + for(int i = 0; i < 10; i++) { + mag_array[X][i] = 0; + mag_array[Y][i] = 0; + mag_array[Z][i] = 0; + } + magcnt = 0; + TimeOutMagcnt = 0; + memset(&MMC5983Var, NULL, sizeof(MMC5983Var)); + MMC5983Var.Status = MMC5983_STATUS_DELAY; + break;} + + case MMC5983_STATUS_DELAY:{ + MMC5983StartRead(); + MMC5983Var.MMC5983Delay1mSCnt = 50; + MMC5983Var.Status = MMC5983_STATUS_WAIT_DELAY; + break;} + + case MMC5983_STATUS_WAIT_DELAY:{ + if(MMC5983Var.MMC5983Delay1mSCnt <= 0){ + MMC5983Var.Status = MMC5983_STATUS_READ; + } + break;} + + case MMC5983_STATUS_READ:{ + MMC5983Var.MMC5983Delay1mSCnt = 50; + MMC5983Var.Status = MMC5983_STATUS_WAIT_READ; + break;} + + case MMC5983_STATUS_WAIT_READ:{ + if(MMC5983Var.MMC5983Delay1mSCnt <= 0){ + MMC5983Var.Status = MMC5983_STATUS_DELAY; + TimeOutMagcnt++; + } + if(MMC5983IntFlag == true){ + MMC5983IntFlag = false; + MMC5983_Read(&mag_array[X][magcnt], &mag_array[Y][magcnt], &mag_array[Z][magcnt]); + magcnt++; + MMC5983Var.Status = MMC5983_STATUS_DELAY; + } + if(TimeOutMagcnt >= 10){ + TimeOutMagcnt = 0; + if(magcnt > 0){ + MMC5983Var.Mag_Original[X] = AverageFilter_32t(mag_array[X], magcnt); + MMC5983Var.Mag_Original[Y] = AverageFilter_32t(mag_array[Y], magcnt); + MMC5983Var.Mag_Original[Z] = AverageFilter_32t(mag_array[Z], magcnt); + magcnt = 0; + MMC5983_Get_Mag(MMC5983Var.Mag); + MmcDataProcessCallBack(MMC5983Var.Mag); + MMC5983Var.Status = MMC5983_STATUS_STOP; + } + else{ + MMC5983Var.Status = MMC5983_STATUS_STOP; +// DBG_LOG("LEFT MMC5983 TimeOut...\r\n"); + } + } + if(magcnt >= 10){ + MMC5983Var.Mag_Original[X] = AverageFilter_32t(mag_array[X], magcnt); + MMC5983Var.Mag_Original[Y] = AverageFilter_32t(mag_array[Y], magcnt); + MMC5983Var.Mag_Original[Z] = AverageFilter_32t(mag_array[Z], magcnt); + magcnt = 0; + MMC5983_Get_Mag(MMC5983Var.Mag); + MmcDataProcessCallBack(MMC5983Var.Mag); + MMC5983Var.Status = MMC5983_STATUS_STOP; + } + break;} + + case MMC5983_STATUS_STOP:{ + MMC5983Stop(); + MMC5983Var.Status = MMC5983_STATUS_IDLE; + //MMC5983Var.Status = MMC5983_STATUS_START;//持续工作 + break;} + } +} + +/***************************************************************************************** +* 函数名称: LeftMMC59831mSRoutine +* 功能描述: MMC59831ms时基循环处理函数 +* 参 数: 无 +* 返 回 值: 无 +*****************************************************************************************/ +void MMC59831mSRoutine(void) +{ + if(MMC5983Var.MMC5983Delay1mSCnt > 0) + MMC5983Var.MMC5983Delay1mSCnt--; +} + +/***************************************************************************************** +* 函数名称: LeftMMC5983Init +* 功能描述: MMC5983初始化 +* 参 数: 无 +* 返 回 值: 无 +*****************************************************************************************/ +void MMC5983Init(void) +{ + if(!InitFlag){ + MMC5983_Init(); + return; + } + + MMC5983Var.Status = MMC5983_STATUS_START; +} + +/***************************************************************************************** +* 函数名称: LeftMMC5983Start +* 功能描述: MMC5983启动 +* 参 数: 无 +* 返 回 值: 无 +*****************************************************************************************/ +void MMC5983Start(void) +{ + if(!InitFlag){ + MMC5983_Init(); + return; + } + + MMC5983Var.Status = MMC5983_STATUS_START; +} + +/***************************************************************************************** +* 函数名称: LeftMMC5983StartRead +* 功能描述: MMC5983启动读取 +* 参 数: 无 +* 返 回 值: 无 +*****************************************************************************************/ +void MMC5983StartRead(void) +{ + MMC5983_Init();//读取时重新初始化 +} + +/***************************************************************************************** +* 函数名称: MMC5983Stop +* 功能描述: MMC5983停止 +* 参 数: 无 +* 返 回 值: 无 +*****************************************************************************************/ +void MMC5983Stop(void) +{ + MMC5983RegCtrl0 Ctrl0Reg; + Ctrl0Reg.Byte = 0x00; + MMC5983_Write_Reg(MMC5983_CTRL_0, Ctrl0Reg.Byte); + + MMC5983RegStatus StatusReg; + StatusReg.Byte = MMC5983_Read_Reg(MMC5983_STATUS); + if(StatusReg.Bit.Meas_M_Done == 1){ + MMC5983_Write_Reg(MMC5983_STATUS, StatusReg.Byte); + } +} + +/***************************************************************************************** +* 函数名称: LeftMMC5983IntCallBack +* 功能描述: MMC5983中断回调 +* 参 数: 无 +* 返 回 值: 无 +*****************************************************************************************/ +void MMC5983IntCallBack(void) +{ + MMC5983IntFlag = true; +} + diff --git a/Module/mmc5983/mmc5983.h b/Module/mmc5983/mmc5983.h new file mode 100644 index 0000000..9023e88 --- /dev/null +++ b/Module/mmc5983/mmc5983.h @@ -0,0 +1,140 @@ +/** + ***************************************************************************** + * @file ak8975.h + * @author WWJ + * @version v1.0 + * @date 2019/04/09 + * @environment stm32f407 + * @brief + ***************************************************************************** +**/ + +#ifndef _MMC5983_H +#define _MMC5983_H +#include "bsp.h" + +#define X 0 +#define Y 1 +#define Z 2 +#define XYZ 3 + +#define MAX(A, B) (A > B) ? A : B; +#define MIN(A, B) (A < B) ? A : B; + +#define MMC5983_X_OUT_H 0X00 //Device ID = 0x48 +#define MMC5983_X_OUT_L 0X01 +#define MMC5983_Y_OUT_H 0X02 +#define MMC5983_Y_OUT_L 0X03 +#define MMC5983_Z_OUT_H 0X04 +#define MMC5983_Z_OUT_L 0X05 +#define MMC5983_XYZ_OUT 0X06 +#define MMC5983_TMP_OUT 0X07 +#define MMC5983_STATUS 0X08 +#define MMC5983_CTRL_0 0X09 +#define MMC5983_CTRL_1 0X0A +#define MMC5983_CTRL_2 0X0B +#define MMC5983_CTRL_3 0X0C +#define MMC5983_ID 0X2F + +#define MMC5983_ADDRESS 0x30 +#define MMC5983_MAG_SCALE_16BIT 0.24414f +#define MMC5983_MAG_SCALE_18BIT 0.061035f + +#define MMC5983Delay(x) delay_ms(x) + +typedef union { + struct { + uint8_t Meas_M_Done: 1; + uint8_t Meas_T_Done: 1; + uint8_t Res0: 2; + uint8_t OTP_Read_Done: 1; + uint8_t Res1: 3; + }Bit; + uint8_t Byte; +}MMC5983RegStatus; + +typedef union { + struct { + uint8_t TM_M: 1; + uint8_t TM_T: 1; + uint8_t NT_meas_done_en: 1; + uint8_t Set: 1; + uint8_t Reset: 1; + uint8_t Auto_SR_en: 1; + uint8_t OTP_Read: 1; + uint8_t Res0: 1; + }Bit; + uint8_t Byte; +}MMC5983RegCtrl0; + +typedef union { + struct { + uint8_t BW: 2; + uint8_t X_Inhibit: 1; + uint8_t YZ_Inhibit: 2; + uint8_t Res0: 2; + uint8_t SW_RST: 1; + }Bit; + uint8_t Byte; +}MMC5983RegCtrl1; + +typedef union { + struct { + uint8_t Cm_freq: 3; + uint8_t Cmm_en: 1; + uint8_t Prd_set: 3; + uint8_t En_prd_set: 1; + }Bit; + uint8_t Byte; +}MMC5983RegCtrl2; + +typedef union { + struct { + uint8_t Res0: 1; + uint8_t St_enp: 1; + uint8_t St_enm: 1; + uint8_t Res1: 3; + uint8_t Spi_3w: 1; + uint8_t Res2: 1; + }Bit; + uint8_t Byte; +}MMC5983RegCtrl3; + +typedef enum{ + MMC5983_STATUS_IDLE, + MMC5983_STATUS_START, + MMC5983_STATUS_DELAY, + MMC5983_STATUS_WAIT_DELAY, + MMC5983_STATUS_READ, + MMC5983_STATUS_WAIT_READ, + MMC5983_STATUS_STOP, +}MMC5983Status_m; + + +typedef struct { + MMC5983Status_m Status; + uint16_t MMC5983Delay1mSCnt; + float Mag[3]; + int32_t Mag_Original[XYZ]; +}MMC5983Var_t; + +void MMC5983LoopHandler(void); +void MMC59831mSRoutine(void); +void MMC5983Init(void); +void MMC5983Start(void); +void MMC5983Stop(void); +void MMC5983IntCallBack(void); + +void MMC5983Calib(void); +void MMC5983GetADValue(int32_t *Mag); +void MMC5983_Get_Mag(float *mag); +MMC5983Status_m GetMMC5983Status(void); +void MMC5983StartRead(void); +bool GetMMC5983CalibStatus(void); +#endif + + + +/* end of ak8975.h */ + + diff --git a/ReadMe.txt b/ReadMe.txt new file mode 100644 index 0000000..8241ce8 --- /dev/null +++ b/ReadMe.txt @@ -0,0 +1,31 @@ +璁惧鍓嶈堪锛氬缓璁暱鏃堕棿渚涚數锛岄佹鏍锋満涓嶉渶瑕佽繘鍏ヤ綆鍔熻楋紝閬垮厤璁惧閲嶅鎬у樊鐨勯棶棰樸 +璇ョ増鏈负浣庡姛鑰楃増鏈紝閲囩敤12V渚涚數锛屼紤鐪犵數娴380uA锛屽伐浣滅數娴18mA + +纭欢鐗堟湰璁板綍锛欻V4.x绯诲垪 +==>>Crack_Left_HV4.0 and Crack_Right_HV4.0 + 1銆丠7233-1锛歀DO,杈撳嚭绋冲畾鐨3.3V锛屾渶澶ц緭鍏15V + 2銆丠C32L170JATA-LQ48锛氳澶囩殑MCU涓绘帶鑺墖 + 3銆丩SM6DSLTR锛氬叚杞村姞閫熷害鑺墖 + 4銆丮MC5983MA锛氫笁杞村湴纾佽姱鐗 + 5銆丮AX3471EUA+锛氫覆鍙ｈ浆485鑺墖 + 6銆丷a-02锛歀ORA閫氫俊鑺墖 + +纭欢鐗堟湰鍙樻洿璁板綍锛 +Crack_Left_HV4.0 ==> Crack_Left_HV4.1 Release 2024-06-21 +Crack_Right_HV4.0 ==> Crack_Right_HV4.1 Release 2024-06-21 + 1銆佽皟鏁翠簡涓诲壇鏉縁PC姣嶅骇浣嶇疆 + +==> Crack_Left_HV4.0 Release 2024-06-12 +==> Crack_Right_HV4.0 Release 2024-06-12 + 1銆佹澘妗嗘敼澶 + 2銆佽繛鎺ュ骇瀛愭崲鎴5P+4P鐨凢PC搴у瓙 + 3銆佷紶鎰熷櫒涓柇鑴氫慨鏀 + + +浠ｇ爜鐗堟湰鍙樻洿璁板綍锛 +CrackUnit_Active_SV1.0 ==>> CrackUnit_Active_SV1.1 Release 2024-08-08 + 1銆佷娇鐢ㄤ簡MMC5983涓柇寮曡剼锛屼慨澶嶄簡椹卞姩bug + 2銆佷慨澶嶄簡鍧囧兼护娉㈠嚱鏁癰ug + +==>>CrackUnit_Active_SV1.0 Release 2024-08-01 + 璇ョ増鏈负浣庡姛鑰楃増鏈 diff --git a/driver/inc/adc.h b/driver/inc/adc.h new file mode 100644 index 0000000..f1eccb9 --- /dev/null +++ b/driver/inc/adc.h @@ -0,0 +1,470 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file adc.h + ** + ** Header file for AD Converter functions + ** @link ADC Group Some description @endlink + ** + ** - 2017-06-28 Alex First Version + ** + ******************************************************************************/ + +#ifndef __ADC_H__ +#define __ADC_H__ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ddl.h" + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup AdcGroup AD Converter (ADC) + ** + ******************************************************************************/ + +//@{ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define ADC_SCAN_CH0_EN (0x1u) /*!< SCAN妯″紡浣跨敤ADC CH0 */ +#define ADC_SCAN_CH1_EN (0x1u<<1) /*!< SCAN妯″紡浣跨敤ADC CH1 */ +#define ADC_SCAN_CH2_EN (0x1u<<2) /*!< SCAN妯″紡浣跨敤ADC CH2 */ +#define ADC_SCAN_CH3_EN (0x1u<<3) /*!< SCAN妯″紡浣跨敤ADC CH3 */ +#define ADC_SCAN_CH4_EN (0x1u<<4) /*!< SCAN妯″紡浣跨敤ADC CH4 */ +#define ADC_SCAN_CH5_EN (0x1u<<5) /*!< SCAN妯″紡浣跨敤ADC CH5 */ +#define ADC_SCAN_CH6_EN (0x1u<<6) /*!< SCAN妯″紡浣跨敤ADC CH6 */ +#define ADC_SCAN_CH7_EN (0x1u<<7) /*!< SCAN妯″紡浣跨敤ADC CH7 */ + + +/****************************************************************************** + ** Global type definitions + *****************************************************************************/ + + /** + ****************************************************************************** + ** \brief ADC杞崲妯″紡 + *****************************************************************************/ +typedef enum en_adc_mode +{ + AdcSglMode = 0u, /*!< 鍗曡緭鍏ラ氶亾鍗曟杞崲妯″紡 */ + AdcScanMode = 1u, /*!< 澶氳緭鍏ラ氶亾椤哄簭/鎻掗槦鎵弿杞崲妯″紡*/ +}en_adc_mode_t; + +/** + ****************************************************************************** + ** \brief ADC鏃堕挓鍒嗛閫夋嫨 + *****************************************************************************/ +typedef enum en_adc_clk_sel +{ + AdcMskClkDiv1 = 0u<<2, /*!< PCLK */ + AdcMskClkDiv2 = 1u<<2, /*!< 1/2 PCLK */ + AdcMskClkDiv4 = 2u<<2, /*!< 1/4 PCLK */ + AdcMskClkDiv8 = 3u<<2, /*!< 1/8 PCLK */ +} en_adc_clk_div_t; + +/** + ****************************************************************************** + ** \brief ADC鍙傝冪數鍘 + *****************************************************************************/ +typedef enum en_adc_ref_vol_sel +{ + AdcMskRefVolSelInBgr1p5 = 0u<<9, /*!<鍐呴儴鍙傝冪數鍘1.5V(SPS<=200kHz)*/ + AdcMskRefVolSelInBgr2p5 = 1u<<9, /*!<鍐呴儴鍙傝冪數鍘2.5V(avdd>3V,SPS<=200kHz)*/ + AdcMskRefVolSelExtern1 = 2u<<9, /*!<澶栭儴杈撳叆(max avdd) PB01*/ + AdcMskRefVolSelAVDD = 3u<<9, /*!>4)*10) + ((x)&0x0F)) + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + ****************************************************************************** + ** Global Device Series List + ******************************************************************************/ +#define DDL_DEVICE_SERIES_HC32L17X (0u) + +/** + ****************************************************************************** + ** Global Device Package List + ******************************************************************************/ +// package definitions of HC device. +#define DDL_DEVICE_PACKAGE_HC_C (0x00u) +#define DDL_DEVICE_PACKAGE_HC_F (0x10u) +#define DDL_DEVICE_PACKAGE_HC_J (0x20u) +#define DDL_DEVICE_PACKAGE_HC_K (0x30u) + +/******************************************************************************/ +/* User Device Setting Include file */ +/******************************************************************************/ +#include "ddl_device.h" // MUST be included here! + +/******************************************************************************/ +/* Global type definitions ('typedef') */ +/******************************************************************************/ +/** + ****************************************************************************** + ** \brief Level + ** + ** Specifies levels. + ** + ******************************************************************************/ +typedef enum en_level +{ + DdlLow = 0u, ///< Low level '0' + DdlHigh = 1u ///< High level '1' +} en_level_t; + +/** + ****************************************************************************** + ** \brief Generic Flag Code + ** + ** Specifies flags. + ** + ******************************************************************************/ +typedef enum en_flag +{ + DdlClr = 0u, ///< Flag clr '0' + DdlSet = 1u ///< Flag set '1' +} en_stat_flag_t, en_irq_flag_t; +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + +/******************************************************************************* + * Global function prototypes + ******************************************************************************/ +extern void ddl_memclr(void* pu8Address, uint32_t u32Count); +uint32_t Log2(uint32_t u32Val); +/** + ******************************************************************************* + ** This hook is part of wait loops. + ******************************************************************************/ +void delay1ms(uint32_t u32Cnt); +void delay100us(uint32_t u32Cnt); +void delay10us(uint32_t u32Cnt); +void SetBit(uint32_t addr, uint32_t offset, boolean_t bFlag); +void ClrBit(uint32_t addr, uint32_t offset); +boolean_t GetBit(uint32_t addr, uint32_t offset); +#ifdef __cplusplus +} +#endif + +#endif /* __DDL_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/driver/inc/debug.h b/driver/inc/debug.h new file mode 100644 index 0000000..4f33fde --- /dev/null +++ b/driver/inc/debug.h @@ -0,0 +1,129 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file debug.h + ** + ** Headerfile for DEBUG functions + ** @link Debug Group Some description @endlink + ** + ** History: + ** - 2018-04-15 Lux First Version + ** + ******************************************************************************/ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ddl.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup DebugGroup (DEBUG) + ** + ******************************************************************************/ +//@{ + +/** + ******************************************************************************* + ** function prototypes. + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief 璋冭瘯妯″紡涓嬪悇妯″潡宸ヤ綔鐘舵佺被鍨嬪畾涔 + ** \note + ******************************************************************************/ +typedef enum en_debug_module_active +{ + DebugMskTim0 = 0x0001u, ///< TIM0 + DebugMskTim1 = 0x0002u, ///< TIM1 + DebugMskTim2 = 0x0004u, ///< TIM2 + DebugMskLpTim0 = 0x0008u, ///< LPTIM0 + DebugMskTim4 = 0x0010u, ///< TIM4 + DebugMskTim5 = 0x0020u, ///< TIM5 + DebugMskTim6 = 0x0040u, ///< TIM6 + DebugMskPca = 0x0080u, ///< PCA + DebugMskWdt = 0x0100u, ///< WDT + DebugMskRtc = 0x0200u, ///< RTC + DebugMskTim3 = 0x0800u, ///< TIM3 + DebugMskLpTim1 = 0x1000u, ///< LPTIM1 +}en_debug_module_active_t; + +/******************************************************************************* + * Global definitions + ******************************************************************************/ + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +///< 鍦⊿WD璋冭瘯妯″紡涓嬶紝浣胯兘妯″潡璁℃暟鍔熻兘 +en_result_t Debug_ActiveEnable(en_debug_module_active_t enModule); +///< 鍦⊿WD璋冭瘯妯″紡涓嬶紝鏆傚仠妯″潡璁℃暟鍔熻兘 +en_result_t Debug_ActiveDisable(en_debug_module_active_t enModule); + +//@} // Debug Group + +#ifdef __cplusplus +#endif + +#endif /* __DEBUG_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/driver/inc/dmac.h b/driver/inc/dmac.h new file mode 100644 index 0000000..bdd93b0 --- /dev/null +++ b/driver/inc/dmac.h @@ -0,0 +1,356 @@ +/***************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file dma.h +** +** A detailed description is available at +** @link DmacGroup Dmac description @endlink +** +** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac. +** +******************************************************************************/ +#ifndef __DMAC_H__ +#define __DMAC_H__ + +/******************************************************************************* +* Include files +******************************************************************************/ +#include "ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + ******************************************************************************* + ** \defgroup DmacGroup Direct Memory Access Control(DMAC) + ** + ******************************************************************************/ + //@{ + + /******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief DMA 閫氶亾 + ** + ******************************************************************************/ + typedef enum en_dma_channel + { + DmaCh0 = 0x00, ///< DMA 閫氶亾0 + DmaCh1 = 0x04, ///< DMA 閫氶亾1 + } en_dma_channel_t; + /** + ******************************************************************************* + ** \brief DMA 浼樺厛绾 + ** + ******************************************************************************/ + typedef enum en_dma_priority + { + DmaMskPriorityFix = 0x00000000, ///< DMA 鍚勯氶亾浼樺厛绾у浐瀹 (CH0>CH1) + DmaMskPriorityLoop = 0x10000000, ///< DMA 鍚勯氶亾浼樺厛绾ч噰鐢ㄨ疆璇㈡柟寮 + } en_dma_priority_t; + + /** + ******************************************************************************* + ** \brief DMA 浼犺緭鏁版嵁瀹藉害 + ** + ******************************************************************************/ + typedef enum en_dma_transfer_width + { + DmaMsk8Bit = 0x00000000, ///< 8 bit 瀛楄妭浼犺緭 + DmaMsk16Bit = 0x04000000, ///< 16 bit 鍗婂瓧浼犺緭 + DmaMsk32Bit = 0x08000000 ///< 32 bit 瀛椾紶杈 + } en_dma_transfer_width_t; + + /** + ******************************************************************************* + ** \brief DMA 浼犺緭妯″紡锛氬潡(Block)浼犺緭鎴栬呯獊鍙(Burst)浼犺緭 + ** + ******************************************************************************/ + typedef enum en_dma_transfer_mode + { + DmaMskBlock = 0x00000000, ///< 鍧(Block)浼犺緭 + DmaMskBurst = 0x10000000, ///< 绐佸彂(Burst)浼犺緭 + } en_dma_transfer_mode_t; + + /** + ******************************************************************************* + ** \brief DMA浼犺緭褰撳墠鐘舵 + ** + ******************************************************************************/ + typedef enum en_dma_stat + { + DmaDefault = 0U, ///< 鍒濆鍊 + DmaAddOverflow = 1U, ///< 浼犺緭閿欒寮曡捣涓锛堝湴鍧婧㈠嚭锛 + DmaHALT = 2U, ///< 浼犺緭鍋滄璇锋眰寮曡捣涓锛堝璁惧仠姝㈣姹傚紩璧风殑鍋滄鎴栬匛B/DE浣嶅紩璧风殑绂佹浼犺緭锛 + DmaAccSCRErr = 3U, ///< 浼犺緭閿欒寮曡捣涓锛堜紶杈撴簮鍦板潃璁块棶閿欒锛 + DmaAccDestErr = 4U, ///< 浼犺緭閿欒寮曡捣涓锛堜紶杈撶洰鐨勫湴鍧璁块棶閿欒锛 + DmaTransferComplete = 5U, ///< 鎴愬姛浼犺緭瀹屾垚 + DmaTransferPause = 7U, ///< 浼犺緭鏆傚仠 + } en_dma_stat_t; + + /** + ******************************************************************************* + ** \brief DMA婧愬湴鍧鎺у埗妯″紡锛氳嚜澧炴垨鍥哄畾 + ** + ******************************************************************************/ + typedef enum en_src_address_mode + { + DmaMskSrcAddrInc = 0x00000000, ///< 鍦板潃鑷 + DmaMskSrcAddrFix = 0x02000000, ///< 鍦板潃鍥哄畾 + } en_src_address_mode_t; + + /** + ******************************************************************************* + ** \brief DMA鐩殑鍦板潃鎺у埗妯″紡锛氳嚜澧炴垨鍥哄畾 + ** + ******************************************************************************/ + typedef enum en_dst_address_mode + { + DmaMskDstAddrInc = 0x00000000, ///< 鍦板潃鑷 + DmaMskDstAddrFix = 0x01000000, ///< 鍦板潃鍥哄畾 + } en_dst_address_mode_t; + + /** + ******************************************************************************* + ** \brief DMA CONFA:BC[3:0]鍜孋ONFA:TC[15:0]鐨勯噸杞藉姛鑳 + ** + ******************************************************************************/ + typedef enum en_bc_tc_reload_mode + { + DmaMskBcTcReloadDisable = 0x00000000, ///< 绂佹閲嶈浇 + DmaMskBcTcReloadEnable = 0x00800000, ///< 浣胯兘閲嶈浇 + } en_bc_tc_reload_mode_t; + + /** + ******************************************************************************* + ** \brief DMA婧愬湴鍧閲嶈浇鍔熻兘锛氫娇鑳芥垨绂佹 + ** + ******************************************************************************/ + typedef enum en_src_address_reload_mode + { + DmaMskSrcAddrReloadDisable = 0x00000000, ///< 绂佹DMA婧愬湴鍧閲嶈浇 + DmaMskSrcAddrReloadEnable = 0x00400000, ///< 浣胯兘DMA婧愬湴鍧閲嶈浇 + } en_src_address_reload_mode_t; + + /** + ******************************************************************************* + ** \brief DMA鐩殑鍦板潃閲嶈浇鍔熻兘锛氫娇鑳芥垨绂佹 + ** + ******************************************************************************/ + typedef enum en_dst_address_reload_mode + { + DmaMskDstAddrReloadDisable = 0x00000000, ///< 绂佹DMA鐩殑鍦板潃閲嶈浇 + DmaMskDstAddrReloadEnable = 0x00200000, ///< 浣胯兘DMA鐩殑鍦板潃閲嶈浇 + } en_dst_address_reload_mode_t; + + + + /** + ******************************************************************************* + ** \brief DMA 杩炵画浼犺緭璁剧疆 + ** + ******************************************************************************/ + typedef enum en_dma_msk + { + DmaMskOneTransfer = 0x00000000, ///< 浼犺緭涓娆★紝DMAC浼犺緭瀹屾垚鏃舵竻闄ONFA:ENS浣 + DmaMskContinuousTransfer = 0x00000001, ///< 杩炵画浼犺緭锛孌MAC浼犺緭瀹屾垚鏃朵笉娓呴櫎CONFA:ENS浣 + } en_dma_msk_t; + /** + ******************************************************************************* + ** \brief DMA 瑙﹀彂婧愰夋嫨 + ** + ******************************************************************************/ + typedef enum stc_dma_trig_sel + { + DmaSWTrig = 0U, ///< Select DMA software trig + DmaSPI0RXTrig = 64U, ///< Select DMA hardware trig 0 + DmaSPI0TXTrig = 65U, ///< Select DMA hardware trig 1 + DmaSPI1RXTrig = 66U, ///< Select DMA hardware trig 2 + DmaSPI1TXTrig = 67U, ///< Select DMA hardware trig 3 + DmaADCJQRTrig = 68U, ///< Select DMA hardware trig 4 + DmaADCSQRTrig = 69U, ///< Select DMA hardware trig 5 + DmaLCDTxTrig = 70U, ///< Select DMA hardware trig 6 + DmaUart0RxTrig = 72U, ///< Select DMA hardware trig 8 + DmaUart0TxTrig = 73U, ///< Select DMA hardware trig 9 + DmaUart1RxTrig = 74U, ///< Select DMA hardware trig 10 + DmaUart1TxTrig = 75U, ///< Select DMA hardware trig 11 + DmaLpUart0RxTrig = 76U, ///< Select DMA hardware trig 12 + DmaLpUart0TxTrig = 77U, ///< Select DMA hardware trig 13 + DmaLpUart1RxTrig = 78U, ///< Select DMA hardware trig 14 + DmaLpUart1TxTrig = 79U, ///< Select DMA hardware trig 15 + DmaDAC0Trig = 80U, ///< Select DMA hardware trig 16 + DmaDAC1Trig = 81U, ///< Select DMA hardware trig 17 + DmaTIM0ATrig = 82U, ///< Select DMA hardware trig 18 + DmaTIM0BTrig = 83U, ///< Select DMA hardware trig 19 + DmaTIM1ATrig = 84U, ///< Select DMA hardware trig 20 + DmaTIM1BTrig = 85U, ///< Select DMA hardware trig 21 + DmaTIM2ATrig = 86U, ///< Select DMA hardware trig 22 + DmaTIM2BTrig = 87U, ///< Select DMA hardware trig 23 + DmaTIM3ATrig = 88U, ///< Select DMA hardware trig 24 + DmaTIM3BTrig = 89U, ///< Select DMA hardware trig 25 + DmaTIM4ATrig = 90U, ///< Select DMA hardware trig 26 + DmaTIM4BTrig = 91U, ///< Select DMA hardware trig 27 + DmaTIM5ATrig = 92U, ///< Select DMA hardware trig 28 + DmaTIM5BTrig = 93U, ///< Select DMA hardware trig 29 + DmaTIM6ATrig = 94U, ///< Select DMA hardware trig 30 + DmaTIM6BTrig = 95U, ///< Select DMA hardware trig 31 + DmaUart2RxTrig = 96U, ///< Select DMA hardware trig 32 + DmaUart2TxTrig = 97U, ///< Select DMA hardware trig 33 + DmaUart3RxTrig = 98U, ///< Select DMA hardware trig 34 + DmaUart3TxTrig = 99U, ///< Select DMA hardware trig 35 + }en_dma_trig_sel_t; + + /** + ******************************************************************************* + ** \brief DMA閫氶亾鍒濆鍖栭厤缃粨鏋勪綋 + ** + ******************************************************************************/ + typedef struct stc_dma_cfg + { + en_dma_transfer_mode_t enMode; + + uint16_t u16BlockSize; ///< 鍧椾紶杈撲釜鏁 + uint16_t u16TransferCnt; ///< 浼犺緭鍧楁鏁 + en_dma_transfer_width_t enTransferWidth; ///< 浼犺緭鏁版嵁瀛楄妭瀹藉害 鍏蜂綋鍙傝冩灇涓惧畾涔:en_dma_transfer_width_t + + en_src_address_mode_t enSrcAddrMode; ///< DMA婧愬湴鍧鎺у埗妯″紡锛氳嚜澧炴垨鍥哄畾 + en_dst_address_mode_t enDstAddrMode; ///< DMA鐩殑鍦板潃鎺у埗妯″紡锛氳嚜澧炴垨鍥哄畾 + + en_src_address_reload_mode_t enSrcAddrReloadCtl; ///< 婧愬湴鍧閲嶈浇 鍏蜂綋鍙傝冩灇涓惧畾涔:en_src_address_reload_mode_t + en_dst_address_reload_mode_t enDestAddrReloadCtl;///< 鐩殑鍦板潃閲嶈浇 鍏蜂綋鍙傝冩灇涓惧畾涔:en_dst_address_reload_mode_t + en_bc_tc_reload_mode_t enSrcBcTcReloadCtl; ///< Bc/Tc鍊奸噸杞藉姛鑳 鍏蜂綋鍙傝冩灇涓惧畾涔:en_bc_tc_reload_mode_t + + uint32_t u32SrcAddress; ///< 婧愬湴鍧> + uint32_t u32DstAddress; ///< 鐩殑鍦板潃> + + en_dma_msk_t enTransferMode; ///DMA 杩炵画浼犺緭璁剧疆 鍏蜂綋鍙傝冩灇涓惧畾涔:en_dma_msk_t + en_dma_priority_t enPriority; ///DMA 浼樺厛绾ц瀹 鍏蜂綋鍙傝冩灇涓惧畾涔:en_dma_priority_t + en_dma_trig_sel_t enRequestNum; ///PCLK=HCLK=SystemClk=RCH4MHz +en_result_t Sysctrl_ClkDeInit(void); + +///< 绯荤粺鏃堕挓妯″潡鐨勫熀鏈姛鑳借缃 +///< 娉ㄦ剰锛氫娇鑳介渶瑕佷娇鐢ㄧ殑鏃堕挓婧愪箣鍓嶏紝蹇呴』浼樺厛璁剧疆鐩爣鍐呴儴鏃堕挓婧愮殑TRIM鍊兼垨澶栭儴鏃堕挓婧愮殑棰戠巼鑼冨洿 +en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag); + +///<澶栭儴鏅舵尟椹卞姩閰嶇疆锛氱郴缁熷垵濮嬪寲Sysctrl_ClkInit()涔嬪悗锛屽彲鏍规嵁闇瑕侀厤缃閮ㄦ櫠鎸殑椹卞姩鑳藉姏锛屾椂閽熷垵濮嬪寲Sysctrl_ClkInit()榛樿涓烘渶澶у; +en_result_t Sysctrl_XTHDriverCfg(en_sysctrl_xtal_driver_t enDriver); +en_result_t Sysctrl_XTLDriverCfg(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver); + +///<鏃堕挓绋冲畾鍛ㄦ湡璁剧疆:绯荤粺鍒濆鍖朣ysctrl_ClkInit()涔嬪悗锛屽彲鏍规嵁闇瑕侀厤缃椂閽熷紑鍚悗鐨勭ǔ瀹氫箣闂达紝榛樿涓烘渶澶у; +en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle); +en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle); +en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle); +en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle); + +///<绯荤粺鏃堕挓婧愬垏鎹㈠苟鏇存柊绯荤粺鏃堕挓锛氬鏋滈渶瑕佸湪绯荤粺鏃堕挓鍒濆鍖朣ysctrl_ClkInit()涔嬪悗鍒囨崲涓婚鏃堕挓婧愶紝鍒欎娇鐢ㄨ鍑芥暟锛 +///< 鏃堕挓鍒囨崲鍓嶅悗锛屽繀椤绘牴鎹洰鏍囬鐜囧艰缃瓼lash璇荤瓑寰呭懆鏈燂紝鍙厤缃彃鍏ュ懆鏈熶负0銆1銆2锛 +///< 娉ㄦ剰!!!锛氬綋HCLK澶т簬24MHz鏃讹紝FLASH绛夊緟鍛ㄦ湡鎻掑叆蹇呴』鑷冲皯涓1,鍚﹀垯绋嬪簭杩愯鍙兘浜х敓鏈煡閿欒 +en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource); + +///< 鏃堕挓婧愰鐜囪瀹氾細鏍规嵁绯荤粺鎯呭喌锛屽崟鐙缃笉鍚屾椂閽熸簮鐨勯鐜囧; +///< 鏃堕挓棰戠巼璁剧疆鍓嶏紝蹇呴』鏍规嵁鐩爣棰戠巼鍊艰缃瓼lash璇荤瓑寰呭懆鏈燂紝鍙厤缃彃鍏ュ懆鏈熶负0銆1銆2锛 +///< 鍏朵腑XTL鐨勬椂閽熺敱澶栭儴鏅舵尟鍐冲畾锛屾棤闇璁剧疆銆 +en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq); +en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq); +en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq); +en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_cfg_t *pstcPLLCfg); + +///< 鏃堕挓鍒嗛璁剧疆:鏍规嵁绯荤粺鎯呭喌锛屽崟鐙缃瓾CLK銆丳CLK鐨勫垎閰嶅; +en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv); +en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv); + +///< 鏃堕挓棰戠巼鑾峰彇锛氭牴鎹郴缁熼渶瑕侊紝鑾峰彇褰撳墠HCLK鍙奝CLK鐨勯鐜囧 +uint32_t Sysctrl_GetHClkFreq(void); +uint32_t Sysctrl_GetPClkFreq(void); + +///< 澶栬闂ㄦ帶寮鍏/鐘舵佽幏鍙栵細鐢ㄤ簬鎺у埗澶栬妯″潡鐨勪娇鑳斤紝浣跨敤璇ユā鍧楃殑鍔熻兘涔嬪墠锛屽繀椤讳娇鑳借妯″潡鐨勯棬鎺ф椂閽燂紱 +en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag); +boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral); + +///< 绯荤粺鍔熻兘閰嶇疆锛氱敤浜庤缃叾浠栫郴缁熺浉鍏崇壒娈婂姛鑳斤紱 +en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag); + +///< RTC楂橀熸椂閽熻ˉ鍋:鐢ㄤ簬璁剧疆RTC楂橀熸椂閽熶笅鐨勯鐜囪ˉ鍋 +en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj); + +//@} // Sysctrl Group + +#ifdef __cplusplus +#endif + +#endif /* __SYSCTRL_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/driver/inc/timer3.h b/driver/inc/timer3.h new file mode 100644 index 0000000..fbe59fc --- /dev/null +++ b/driver/inc/timer3.h @@ -0,0 +1,781 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file timer3.h + ** + ** 鍩烘湰瀹氭椂鍣ㄦ暟鎹粨鏋勫強API澹版槑 + ** @link Timer3 Group Some description @endlink + ** + ** History: + ** - 2019-04-18 Husj First Version + ** + *****************************************************************************/ + +#ifndef __TIMER3_H__ +#define __TIMER3_H__ + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "ddl.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup Tim3Group Timer3 (TIM3) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Timer3 閫氶亾瀹氫箟 + *****************************************************************************/ +typedef enum en_tim3_channel +{ + Tim3CH0 = 0u, ///< Timer3閫氶亾0 + Tim3CH1 = 1u, ///< Timer3閫氶亾1 + Tim3CH2 = 2u, ///< Timer3閫氶亾2 +}en_tim3_channel_t; + +/** + ****************************************************************************** + ** \brief 宸ヤ綔妯″紡閫夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (MODE)(妯″紡0/1/23) + *****************************************************************************/ +typedef enum en_tim3_work_mode +{ + Tim3WorkMode0 = 0u, ///< 瀹氭椂鍣ㄦā寮 + Tim3WorkMode1 = 1u, ///< PWC妯″紡 + Tim3WorkMode2 = 2u, ///< 閿娇娉㈡ā寮 + Tim3WorkMode3 = 3u, ///< 涓夎娉㈡ā寮 +}en_tim3_work_mode_t; + +/** + ****************************************************************************** + ** \brief 鏋佹ф帶鍒舵暟鎹被鍨嬮噸瀹氫箟 (GATE_P)(妯″紡0) + *****************************************************************************/ +typedef enum en_tim3_m0cr_gatep +{ + Tim3GatePositive = 0u, ///< 楂樼數骞虫湁鏁 + Tim3GateOpposite = 1u, ///< 浣庣數骞虫湁鏁 +}en_tim3_m0cr_gatep_t; + +/** + ****************************************************************************** + ** \brief TIM3 棰勯櫎棰戦夋嫨 (PRS)(妯″紡0/1/23) + *****************************************************************************/ +typedef enum en_tim3_cr_timclkdiv +{ + Tim3PCLKDiv1 = 0u, ///< Div 1 + Tim3PCLKDiv2 = 1u, ///< Div 2 + Tim3PCLKDiv4 = 2u, ///< Div 4 + Tim3PCLKDiv8 = 3u, ///< Div 8 + Tim3PCLKDiv16 = 4u, ///< Div 16 + Tim3PCLKDiv32 = 5u, ///< Div 32 + Tim3PCLKDiv64 = 6u, ///< Div 64 + Tim3PCLKDiv256 = 7u, ///< Div 256 +}en_tim3_cr_timclkdiv_t; + +/** + ****************************************************************************** + ** \brief 璁℃暟/瀹氭椂鍣ㄥ姛鑳介夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (CT)(妯″紡0/1/23) + *****************************************************************************/ +typedef enum en_tim3_cr_ct +{ + Tim3Timer = 0u, ///< 瀹氭椂鍣ㄥ姛鑳斤紝璁℃暟鏃堕挓涓哄唴閮≒CLK + Tim3Counter = 1u, ///< 璁℃暟鍣ㄥ姛鑳斤紝璁℃暟鏃堕挓涓哄閮‥TR +}en_tim3_cr_ct_t; + + +/** + ****************************************************************************** + ** \brief 瀹氭椂鍣ㄥ伐浣滄ā寮忔暟鎹被鍨嬮噸瀹氫箟 (MD)(妯″紡0) + *****************************************************************************/ +typedef enum en_tim3_m0cr_md +{ + Tim332bitFreeMode = 0u, ///< 32浣嶈鏁板櫒/瀹氭椂鍣 + Tim316bitArrMode = 1u, ///< 鑷姩閲嶈杞16浣嶈鏁板櫒/瀹氭椂鍣 +}en_tim3_m0cr_md_t; + +/** + ****************************************************************************** +** \brief TIM3涓柇绫诲瀷鏁版嵁绫诲瀷閲嶅畾涔(妯″紡0/1/23) + *****************************************************************************/ +typedef enum en_tim3_irq_type +{ + Tim3UevIrq = 0u, ///< 婧㈠嚭/浜嬩欢鏇存柊涓柇 + Tim3CA0Irq = 2u, ///< CH0A鎹曡幏/姣旇緝涓柇(浠呮ā寮1/23瀛樺湪) + Tim3CA1Irq = 3u, ///< CH1A鎹曡幏/姣旇緝涓柇(浠呮ā寮23瀛樺湪) + Tim3CA2Irq = 4u, ///< CH2A鎹曡幏/姣旇緝涓柇(浠呮ā寮23瀛樺湪) + Tim3CB0Irq = 5u, ///< CH0B鎹曡幏/姣旇緝涓柇(浠呮ā寮23瀛樺湪) + Tim3CB1Irq = 6u, ///< CH1B鎹曡幏/姣旇緝涓柇(浠呮ā寮23瀛樺湪) + Tim3CB2Irq = 7u, ///< CH2B鎹曡幏/姣旇緝涓柇(浠呮ā寮23瀛樺湪) + Tim3CA0E = 8u, ///< CH0A鎹曡幏鏁版嵁涓㈠け鏍囧織(浠呮ā寮23瀛樺湪)(涓嶆槸涓柇) + Tim3CA1E = 9u, ///< CH1A鎹曡幏鏁版嵁涓㈠け鏍囧織(浠呮ā寮23瀛樺湪)(涓嶆槸涓柇) + Tim3CA2E = 10u, ///< CH2A鎹曡幏鏁版嵁涓㈠け鏍囧織(浠呮ā寮23瀛樺湪)(涓嶆槸涓柇) + Tim3CB0E = 11u, ///< CH0B鎹曡幏鏁版嵁涓㈠け鏍囧織(浠呮ā寮23瀛樺湪)(涓嶆槸涓柇) + Tim3CB1E = 12u, ///< CH1B鎹曡幏鏁版嵁涓㈠け鏍囧織(浠呮ā寮23瀛樺湪)(涓嶆槸涓柇) + Tim3CB2E = 13u, ///< CH2B鎹曡幏鏁版嵁涓㈠け鏍囧織(浠呮ā寮23瀛樺湪)(涓嶆槸涓柇) + Tim3BkIrq = 14u, ///< 鍒硅溅涓柇(浠呮ā寮23瀛樺湪锛 + Tim3TrigIrq = 15u, ///< 瑙﹀彂涓柇(浠呮ā寮23瀛樺湪锛 +}en_tim3_irq_type_t; + +/** + ****************************************************************************** + ** \brief 娴嬮噺寮濮嬬粨鏉熸暟鎹被鍨嬮噸瀹氫箟 (Edg1stEdg2nd)(妯″紡1) + *****************************************************************************/ +typedef enum en_tim3_m1cr_Edge +{ + Tim3PwcRiseToRise = 0u, ///< 涓婂崌娌垮埌涓婂崌娌(鍛ㄦ湡) + Tim3PwcFallToRise = 1u, ///< 涓嬮檷娌垮埌涓婂崌娌(浣庣數骞) + Tim3PwcRiseToFall = 2u, ///< 涓婂崌娌垮埌涓嬮檷娌(楂樼數骞) + Tim3PwcFallToFall = 3u, ///< 涓嬮檷娌垮埌涓嬮檷娌(鍛ㄦ湡) +}en_tim3_m1cr_Edge_t; + +/** + ****************************************************************************** + ** \brief PWC娴嬮噺娴嬭瘯妯″紡閫夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (Oneshot)(妯″紡1) + *****************************************************************************/ +typedef enum en_tim3_m1cr_oneshot +{ + Tim3PwcCycleDetect = 0u, ///< PWC寰幆娴嬮噺 + Tim3PwcOneShotDetect = 1u, ///< PWC鍗曟娴嬮噺 +}en_tim3_m1cr_oneshot_t; + +/** + ****************************************************************************** + ** \brief PWC IA0閫夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (IA0S)(妯″紡1) + *****************************************************************************/ +typedef enum en_tim3_m1_mscr_ia0s +{ + Tim3IA0Input = 0u, ///< IAO杈撳叆 + Tim3XORInput = 1u, ///< IA0 ETR GATE XOR(TIM0/1/2)/IA0 IA1 IA2 XOR(TIM3) +}en_tim3_m1_mscr_ia0s_t; + +/** + ****************************************************************************** + ** \brief PWC IB0閫夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (IA0S)(妯″紡1) + *****************************************************************************/ +typedef enum en_tim3_m1_mscr_ib0s +{ + Tim3IB0Input = 0u, ///< IBO杈撳叆 + Tim3TsInput = 1u, ///< 鍐呴儴瑙﹀彂TS閫夋嫨淇″彿 +}en_tim3_m1_mscr_ib0s_t; + +/** + ****************************************************************************** + ** \brief 杈撳嚭鏋佹с佽緭鍏ョ浉浣 鏁版嵁绫诲瀷閲嶅畾涔 (CCPA0/CCPB0/ETP/BKP)(妯″紡1/23) + *****************************************************************************/ +typedef enum en_tim3_port_polarity +{ + Tim3PortPositive = 0u, ///< 姝ｅ父杈撳叆杈撳嚭 + Tim3PortOpposite = 1u, ///< 鍙嶅悜杈撳叆杈撳嚭 +}en_tim3_port_polarity_t; + +/** + ****************************************************************************** + ** \brief 婊ゆ尝閫夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (FLTET/FLTA0/FLAB0)(妯″紡1/23) + *****************************************************************************/ +typedef enum en_tim3_flt +{ + Tim3FltNone = 0u, ///< 鏃犳护娉 + Tim3FltPCLKCnt3 = 4u, ///< PCLK 3涓繛缁湁鏁 + Tim3FltPCLKDiv4Cnt3 = 5u, ///< PCLK/4 3涓繛缁湁鏁 + Tim3FltPCLKDiv16Cnt3 = 6u, ///< PCLK/16 3涓繛缁湁鏁 + Tim3FltPCLKDiv64Cnt3 = 7u, ///< PCLK/64 3涓繛缁湁鏁 +}en_tim3_flt_t; + +/** + ****************************************************************************** + ** \brief 閫氶亾姣旇緝鎺у埗 鏁版嵁绫诲瀷閲嶅畾涔 (OCMA/OCMB)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23_fltr_ocm +{ + Tim3ForceLow = 0u, ///< 寮哄埗涓0 + Tim3ForceHigh = 1u, ///< 寮哄埗涓1 + Tim3CMPForceLow = 2u, ///< 姣旇緝鍖归厤鏃跺己鍒朵负0 + Tim3CMPForceHigh = 3u, ///< 姣旇緝鍖归厤鏃跺己鍒朵负1 + Tim3CMPInverse = 4u, ///< 姣旇緝鍖归厤鏃剁炕杞數骞 + Tim3CMPOnePrdHigh = 5u, ///< 姣旇緝鍖归厤鏃惰緭鍑轰竴涓鏁板懆鏈熺殑楂樼數骞 + Tim3PWMMode1 = 6u, ///< 閫氶亾鎺у埗涓篜WM mode 1 + Tim3PWMMode2 = 7u, ///< 閫氶亾鎺у埗涓篜WM mode 2 +}en_tim3_m23_fltr_ocm_t; + +/** + ****************************************************************************** + ** \brief 涓讳粠妯″紡TS鏁版嵁绫诲瀷閲嶅畾涔 (TS)(妯″紡1/23) + *****************************************************************************/ +typedef enum en_tim3_mscr_ts +{ + Tim3Ts0ETR = 0u, ///< ETR澶栭儴杈撳叆婊ゆ尝鍚庣殑鐩镐綅閫夋嫨淇″彿 + Tim3Ts1TIM0TRGO = 1u, ///< Timer0鐨凾RGO杈撳嚭淇″彿 + Tim3Ts2TIM1TRGO = 2u, ///< Timer1鐨凾RGO杈撳嚭淇″彿 + Tim3Ts3TIM2TRGO = 3u, ///< Timer2鐨凾RGO杈撳嚭淇″彿 + Tim3Ts4TIM3TRGO = 4u, ///< Timer3鐨凾RGO杈撳嚭淇″彿 + //Tim3Ts5IA0ED = 5u, ///< 鏃犳晥 + Tim3Ts6IAFP = 6u, ///< CH0A 澶栭儴杈撹緭鍏ユ护娉㈠悗鐨勭浉浣嶉夋嫨淇″彿 + Tim3Ts7IBFP = 7u, ///< CH0B 澶栭儴杈撹緭鍏ユ护娉㈠悗鐨勭浉浣嶉夋嫨淇 +}en_tim3_mscr_ts_t; + +/** + ****************************************************************************** + ** \brief PWM杈撳嚭妯″紡閫夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (COMP)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_comp +{ + Tim3IndependentPWM = 0u, ///< 鐙珛PWM杈撳嚭 + Tim3ComplementaryPWM = 1u, ///< 浜掕ˉPWM杈撳嚭 +}en_tim3_m23cr_comp_t; + +/** + ****************************************************************************** + ** \brief 璁℃暟鏂瑰悜閫夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (DIR)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_dir +{ + Tim3CntUp = 0u, ///< 鍚戜笂璁℃暟 + Tim3CntDown = 1u, ///< 鍚戜笅璁℃暟 +}en_tim3_m23cr_dir_t; + +/** + ****************************************************************************** + ** \brief 璁℃暟鏂瑰悜閫夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (PWM2S)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_pwm2s +{ + Tim3DoublePointCmp = 0u, ///< 鍙岀偣姣旇緝浣胯兘锛屼娇鐢–CRA,CCRB姣旇緝鎺у埗OCREFA杈撳嚭 + Tim3SinglePointCmp = 1u, ///< 鍗曠偣姣旇緝浣胯兘锛屼娇鐢–CRA姣旇緝鎺у埗OCREFA杈撳嚭 +}en_tim3_m23cr_pwm2s_t; + +/** + ****************************************************************************** + ** \brief GATE鍦≒WM浜掕ˉ妯″紡涓嬫崟鑾锋垨姣旇緝鍔熻兘 閫夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (CSG)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_csg +{ + Tim3PWMCompGateCmpOut = 0u, ///< 鍦≒WM浜掕ˉ妯″紡涓嬶紝Gate浣滀负姣旇緝杈撳嚭 + Tim3PWMCompGateCapIn = 1u, ///< 鍦≒WM浜掕ˉ妯″紡涓嬶紝Gate浣滀负鎹曡幏杈撳叆 +}en_tim3_m23cr_csg_t; + + +/** + ****************************************************************************** + ** \brief 姣旇緝鎹曡幏瀵勫瓨鍣 鏁版嵁绫诲瀷閲嶅畾涔 (CCR0A,CCR0B)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23_ccrx +{ + Tim3CCR0A = 0u, ///< CCR0A姣旇緝鎹曡幏瀵勫瓨鍣 + Tim3CCR0B = 1u, ///< CCR0B姣旇緝鎹曡幏瀵勫瓨鍣 + Tim3CCR1A = 2u, ///< CCR1A姣旇緝鎹曡幏瀵勫瓨鍣 + Tim3CCR1B = 3u, ///< CCR1B姣旇緝鎹曡幏瀵勫瓨鍣 + Tim3CCR2A = 4u, ///< CCR2A姣旇緝鎹曡幏瀵勫瓨鍣 + Tim3CCR2B = 5u, ///< CCR2B姣旇緝鎹曡幏瀵勫瓨鍣 +}en_tim3_m23_ccrx_t; + +/** + ****************************************************************************** + ** \brief OCREF娓呴櫎婧 閫夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (OCCS)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23ce_occs +{ + Tim3OC_Ref_Clr = 0u, ///< 鏉ヨ嚜VC鐨凮C_Ref_Clr + Tim3ETRf = 1u, ///< 澶栭儴ETRf +}en_tim3_m23ce_occs_t; + +/** + ****************************************************************************** + ** \brief 姣旇緝鍖归厤涓柇妯″紡 閫夋嫨鏁版嵁绫诲瀷閲嶅畾涔 (CIS/CISB)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23_cisa_cisb +{ + Tim3CmpIntNone = 0u, ///< 鏃犳瘮杈冨尮閰嶄腑鏂 + Tim3CmpIntRise = 1u, ///< 姣旇緝鍖归厤涓婂崌娌夸腑鏂 + Tim3CmpIntFall = 2u, ///< 姣旇緝鍖归厤涓嬮檷娌夸腑鏂 + Tim3CmpIntRiseFall = 3u, ///< 姣旇緝鍖归厤涓婂崌娌夸笅闄嶆部涓柇 +}en_tim3_m23_cisa_cisb_t; + +/** + ****************************************************************************** + ** \brief TIM3绔彛鎺у埗 - 鍒硅溅鏃禖Hx杈撳嚭鐘舵佹帶鍒(BKSA/BKSB)(妯″紡23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crchx_bks +{ + Tim3CHxBksHiZ = 0u, ///< 鍒硅溅浣胯兘鏃讹紝CHx绔彛杈撳嚭楂橀樆鎬 + Tim3CHxBksNorm = 1u, ///< 鍒硅溅浣胯兘鏃讹紝CHx绔彛姝ｅ父杈撳嚭 + Tim3CHxBksLow = 2u, ///< 鍒硅溅浣胯兘鏃讹紝CHx绔彛杈撳嚭浣庣數骞 + Tim3CHxBksHigh = 3u, ///< 鍒硅溅浣胯兘鏃讹紝CHx绔彛杈撳嚭楂樼數骞 +}en_tim3_m23_crchx_bks_t; + +/** + ****************************************************************************** +** \brief TIM3绔彛鎺у埗 - CHx涓婂崌娌夸笅闄嶆部鎹曡幏(CRx/CFx)(妯″紡23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crch0_cfx_crx +{ + Tim3CHxCapNone = 0u, ///< CHx閫氶亾鎹曡幏绂佹 + Tim3CHxCapRise = 1u, ///< CHx閫氶亾涓婂崌娌挎崟鑾蜂娇鑳 + Tim3CHxCapFall = 2u, ///< CHx閫氶亾涓嬮檷娌挎崟鑾蜂娇鑳 + Tim3CHxCapFallRise = 3u, ///< CHx閫氶亾涓婂崌娌夸笅闄嶆部鎹曡幏閮戒娇鑳 +}en_tim3_m23_crch0_cfx_crx_t; + +/** + ****************************************************************************** +** \brief TIM3绔彛鎺у埗 - CHx姣旇緝鎹曡幏妯″紡(CSA/CSB)(妯″紡23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crch0_csa_csb +{ + Tim3CHxCmpMode = 0u, ///< CHx閫氶亾璁剧疆涓烘瘮杈冩ā寮 + Tim3CHxCapMode = 1u, ///< CHx閫氶亾璁剧疆涓烘崟鑾锋ā寮 +}en_tim3_m23_crch0_csa_csb_t; + +/** + ****************************************************************************** + ** \brief 姣旇緝妯″紡涓 DMA姣旇緝瑙﹀彂閫夋嫨 鏁版嵁绫诲瀷閲嶅畾涔 (CCDS)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_ccds +{ + Tim3CmpTrigDMA = 0u, ///< 姣旇緝鍖归厤瑙﹀彂DMA + Tim3UEVTrigDMA = 1u, ///< 浜嬩欢鏇存柊浠ｆ浛姣旇緝鍖归厤瑙﹀彂DMA +}en_tim3_m23_mscr_ccds_t; + +/** + ****************************************************************************** + ** \brief 涓讳粠妯″紡閫夋嫨 鏁版嵁绫诲瀷閲嶅畾涔 (MSM)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_msm +{ + Tim3SlaveMode = 0u, ///< 浠庢ā寮 + Tim3MasterMode = 1u, ///< 涓绘ā寮 +}en_tim3_m23_mscr_msm_t; + +/** + ****************************************************************************** + ** \brief 瑙﹀彂涓绘ā寮忚緭鍑烘簮 鏁版嵁绫诲瀷閲嶅畾涔 (MMS)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_mms +{ + Tim3MasterUG = 0u, ///< UG(杞欢鏇存柊)婧 + Tim3MasterCTEN = 1u, ///< CTEN婧 + Tim3MasterUEV = 2u, ///< UEV鏇存柊婧 + Tim3MasterCMPSO = 3u, ///< 姣旇緝鍖归厤閫夋嫨杈撳嚭婧 + Tim3MasterOCA0Ref = 4u, ///< OCA0_Ref婧 + Tim3MasterOCB0Ref = 5u, ///< OCB0_Ref婧 + //Tim3MasterOCB0Ref = 6u, + //Tim3MasterOCB0Ref = 7u, +}en_tim3_m23_mscr_mms_t; + +/** + ****************************************************************************** + ** \brief 瑙﹀彂浠庢ā寮忛夋嫨 鏁版嵁绫诲瀷閲嶅畾涔 (SMS)(妯″紡23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_sms +{ + Tim3SlaveIClk = 0u, ///< 浣跨敤鍐呴儴鏃堕挓 + Tim3SlaveResetTIM = 1u, ///< 澶嶄綅鍔熻兘 + Tim3SlaveTrigMode = 2u, ///< 瑙﹀彂妯″紡 + Tim3SlaveEClk = 3u, ///< 澶栭儴鏃堕挓妯″紡 + Tim3SlaveCodeCnt1 = 4u, ///< 姝ｄ氦缂栫爜璁℃暟妯″紡1 + Tim3SlaveCodeCnt2 = 5u, ///< 姝ｄ氦缂栫爜璁℃暟妯″紡2 + Tim3SlaveCodeCnt3 = 6u, ///< 姝ｄ氦缂栫爜璁℃暟妯″紡3 + Tim3SlaveGateCtrl = 7u, ///< 闂ㄦ帶鍔熻兘 +}en_tim3_m23_mscr_sms_t; + +/** + ****************************************************************************** + ** \brief 瀹氭椂鍣ㄨ繍琛屾帶鍒舵暟鎹被鍨嬮噸瀹氫箟 (CTEN) + *****************************************************************************/ +typedef enum en_tim3_start +{ + Tim3CTENDisable = 0u, ///< 鍋滄 + Tim3CTENEnable = 1u, ///< 杩愯 +}en_tim3_start_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode0 閰嶇疆缁撴瀯浣撳畾涔(妯″紡0) + *****************************************************************************/ +typedef struct stc_tim3_mode0_cfg +{ + en_tim3_work_mode_t enWorkMode; ///< 宸ヤ綔妯″紡璁剧疆 + en_tim3_m0cr_gatep_t enGateP; ///< 闂ㄦ帶鏋佹ф帶鍒 + boolean_t bEnGate; ///< 闂ㄦ帶浣胯兘 + en_tim3_cr_timclkdiv_t enPRS; ///< 棰勯櫎棰戦厤缃 + boolean_t bEnTog; ///< 缈昏浆杈撳嚭浣胯兘 + en_tim3_cr_ct_t enCT; ///< 瀹氭椂/璁℃暟鍔熻兘閫夋嫨 + en_tim3_m0cr_md_t enCntMode; ///< 璁℃暟妯″紡閰嶇疆 +}stc_tim3_mode0_cfg_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode1 閰嶇疆缁撴瀯浣撳畾涔(妯″紡1) + *****************************************************************************/ +typedef struct stc_tim3_mode1_cfg +{ + en_tim3_work_mode_t enWorkMode; ///< 宸ヤ綔妯″紡璁剧疆 + en_tim3_cr_timclkdiv_t enPRS; ///< 棰勯櫎棰戦厤缃 + en_tim3_cr_ct_t enCT; ///< 瀹氭椂/璁℃暟鍔熻兘閫夋嫨 + en_tim3_m1cr_oneshot_t enOneShot; ///< 鍗曟娴嬮噺/寰幆娴嬮噺閫夋嫨 +}stc_tim3_mode1_cfg_t; + +/** + ****************************************************************************** + ** \brief PWC杈撳叆閰嶇疆缁撴瀯浣撳畾涔(妯″紡1) + *****************************************************************************/ +typedef struct stc_tim3_pwc_input_cfg +{ + en_tim3_mscr_ts_t enTsSel; ///< 瑙﹀彂杈撳叆婧愰夋嫨 + en_tim3_m1_mscr_ia0s_t enIA0Sel; ///< CHA0杈撳叆閫夋嫨 + en_tim3_m1_mscr_ib0s_t enIB0Sel; ///< CHB0杈撳叆閫夋嫨 + en_tim3_port_polarity_t enETRPhase; ///< ETR鐩镐綅閫夋嫨 + en_tim3_flt_t enFltETR; ///< ETR婊ゆ尝璁剧疆 + en_tim3_flt_t enFltIA0; ///< CHA0婊ゆ尝璁剧疆 + en_tim3_flt_t enFltIB0; ///< CHB0婊ゆ尝璁剧疆 +}stc_tim3_pwc_input_cfg_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode23 閰嶇疆缁撴瀯浣撳畾涔(妯″紡23) + *****************************************************************************/ +typedef struct stc_tim3_mode23_cfg +{ + en_tim3_work_mode_t enWorkMode; ///< 宸ヤ綔妯″紡璁剧疆 + en_tim3_m23cr_dir_t enCntDir; ///< 璁℃暟鏂瑰悜 + en_tim3_cr_timclkdiv_t enPRS; ///< 鏃堕挓棰勯櫎棰戦厤缃 + en_tim3_cr_ct_t enCT; ///< 瀹氭椂/璁℃暟鍔熻兘閫夋嫨 + en_tim3_m23cr_comp_t enPWMTypeSel; ///< PWM妯″紡閫夋嫨锛堢嫭绔/浜掕ˉ锛 + en_tim3_m23cr_pwm2s_t enPWM2sSel; ///< OCREFA鍙岀偣姣旇緝鍔熻兘閫夋嫨 + boolean_t bOneShot; ///< 鍗曟瑙﹀彂妯″紡浣胯兘/绂佹 + boolean_t bURSSel; ///< 鏇存柊婧愰夋嫨 +}stc_tim3_mode23_cfg_t; + +/** + ****************************************************************************** + ** \brief GATE鍦≒WM浜掕ˉ妯″紡涓嬫崟鑾锋垨姣旇緝鍔熻兘 閰嶇疆缁撴瀯浣撳畾涔(妯″紡23) + *****************************************************************************/ +typedef struct stc_tim3_m23_gate_cfg +{ + en_tim3_m23cr_csg_t enGateFuncSel; ///< Gate姣旇緝銆佹崟鑾峰姛鑳介夋嫨 + boolean_t bGateRiseCap; ///< GATE浣滀负鎹曡幏鍔熻兘鏃讹紝涓婃部鎹曡幏鏈夋晥鎺у埗 + boolean_t bGateFallCap; ///< GATE浣滀负鎹曡幏鍔熻兘鏃讹紝涓嬫部鎹曡幏鏈夋晥鎺у埗 +}stc_tim3_m23_gate_cfg_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB閫氶亾姣旇緝鎺у埗 閰嶇疆缁撴瀯浣撳畾涔(妯″紡23) + *****************************************************************************/ +typedef struct stc_tim3_m23_compare_cfg +{ + en_tim3_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A姣旇緝/鎹曡幏鍔熻兘閫夋嫨 + en_tim3_m23_fltr_ocm_t enCHxACmpCtrl; ///< CH0A閫氶亾姣旇緝鎺у埗 + en_tim3_port_polarity_t enCHxAPolarity; ///< CH0A杈撳嚭鏋佹ф帶鍒 + boolean_t bCHxACmpBufEn; ///< 姣旇緝A缂撳瓨鍔熻兘 浣胯兘/绂佹 + en_tim3_m23_cisa_cisb_t enCHxACmpIntSel; ///< CHA姣旇緝鍖归厤涓柇閫夋嫨 + + en_tim3_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0B姣旇緝/鎹曡幏鍔熻兘閫夋嫨 + en_tim3_m23_fltr_ocm_t enCHxBCmpCtrl; ///< CH0B閫氶亾姣旇緝鎺у埗 + en_tim3_port_polarity_t enCHxBPolarity; ///< CH0B杈撳嚭鏋佹ф帶鍒 + boolean_t bCHxBCmpBufEn; ///< 姣旇緝B缂撳瓨鍔熻兘 浣胯兘/绂佹 + en_tim3_m23_cisa_cisb_t enCHxBCmpIntSel; ///< CHB0姣旇緝鍖归厤涓柇閫夋嫨 +}stc_tim3_m23_compare_cfg_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB閫氶亾鎹曡幏鎺у埗 閰嶇疆缁撴瀯浣撳畾涔(妯″紡23) + *****************************************************************************/ +typedef struct stc_tim3_m23_input_cfg +{ + en_tim3_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A姣旇緝/鎹曡幏鍔熻兘閫夋嫨 + en_tim3_m23_crch0_cfx_crx_t enCHxACapSel; ///< CH0A鎹曡幏杈规部閫夋嫨 + en_tim3_flt_t enCHxAInFlt; ///< CH0A閫氶亾鎹曡幏婊ゆ尝鎺у埗 + en_tim3_port_polarity_t enCHxAPolarity; ///< CH0A杈撳叆鐩镐綅 + + en_tim3_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0A姣旇緝/鎹曡幏鍔熻兘閫夋嫨 + en_tim3_m23_crch0_cfx_crx_t enCHxBCapSel; ///< CH0B鎹曡幏杈规部閫夋嫨 + en_tim3_flt_t enCHxBInFlt; ///< CH0B閫氶亾鎹曡幏婊ゆ尝鎺у埗 + en_tim3_port_polarity_t enCHxBPolarity; ///< CH0B杈撳叆鐩镐綅 + +}stc_tim3_m23_input_cfg_t; + +/** + ****************************************************************************** + ** \brief ETR杈撳叆鐩镐綅婊ゆ尝閰嶇疆缁撴瀯浣撳畾涔(妯″紡23) + *****************************************************************************/ +typedef struct stc_tim3_m23_etr_input_cfg +{ + en_tim3_port_polarity_t enETRPolarity; ///< ETR杈撳叆鏋佹ц缃 + en_tim3_flt_t enETRFlt; ///< ETR婊ゆ尝璁剧疆 +}stc_tim3_m23_etr_input_cfg_t; + +/** + ****************************************************************************** + ** \brief 鍒硅溅BK杈撳叆鐩镐綅婊ゆ尝閰嶇疆缁撴瀯浣撳畾涔(妯″紡23) + *****************************************************************************/ +typedef struct stc_tim3_m23_bk_input_cfg +{ + boolean_t bEnBrake; ///< 鍒硅溅浣胯兘 + boolean_t bEnVCBrake; ///< 浣胯兘VC鍒硅溅 + boolean_t bEnSafetyBk; ///< 浣胯兘safety鍒硅溅 + boolean_t bEnBKSync; ///< TIM0/TIM1/TIM2鍒硅溅鍚屾浣胯兘 + en_tim3_m23_crchx_bks_t enBkCH0AStat; ///< 鍒硅溅鏃禖HA绔彛鐘舵佽缃 + en_tim3_m23_crchx_bks_t enBkCH0BStat; ///< 鍒硅溅鏃禖HB绔彛鐘舵佽缃 + en_tim3_m23_crchx_bks_t enBkCH1AStat; ///< 鍒硅溅鏃禖HA绔彛鐘舵佽缃 + en_tim3_m23_crchx_bks_t enBkCH1BStat; ///< 鍒硅溅鏃禖HB绔彛鐘舵佽缃 + en_tim3_m23_crchx_bks_t enBkCH2AStat; ///< 鍒硅溅鏃禖HA绔彛鐘舵佽缃 + en_tim3_m23_crchx_bks_t enBkCH2BStat; ///< 鍒硅溅鏃禖HB绔彛鐘舵佽缃 + en_tim3_port_polarity_t enBrakePolarity; ///< 鍒硅溅BK杈撳叆鏋佹ц缃 + en_tim3_flt_t enBrakeFlt; ///< 鍒硅溅BK婊ゆ尝璁剧疆 +}stc_tim3_m23_bk_input_cfg_t; + +/** + ****************************************************************************** +** \brief 姝诲尯鍔熻兘閰嶇疆缁撴瀯浣撳畾涔(妯″紡23) + *****************************************************************************/ +typedef struct stc_tim3_m23_dt_cfg +{ + boolean_t bEnDeadTime; ///< 鍒硅溅鏃禖HA绔彛鐘舵佽缃 + uint8_t u8DeadTimeValue; ///< 鍒硅溅鏃禖HA绔彛鐘舵佽缃 +}stc_tim3_m23_dt_cfg_t; + +/** + ****************************************************************************** + ** \brief 瑙﹀彂ADC閰嶇疆缁撴瀯浣撳畾涔(妯″紡23) + *****************************************************************************/ +typedef struct stc_tim3_m23_adc_trig_cfg +{ + boolean_t bEnTrigADC; ///< 瑙﹀彂ADC鍏ㄥ眬鎺у埗 + boolean_t bEnUevTrigADC; ///< 浜嬩欢鏇存柊瑙﹀彂ADC + boolean_t bEnCH0ACmpTrigADC; ///< CH0A姣旇緝鍖归厤瑙﹀彂ADC + boolean_t bEnCH0BCmpTrigADC; ///< CH0B姣旇緝鍖归厤瑙﹀彂ADC + boolean_t bEnCH1ACmpTrigADC; ///< CH0A姣旇緝鍖归厤瑙﹀彂ADC + boolean_t bEnCH1BCmpTrigADC; ///< CH0B姣旇緝鍖归厤瑙﹀彂ADC + boolean_t bEnCH2ACmpTrigADC; ///< CH0A姣旇緝鍖归厤瑙﹀彂ADC + boolean_t bEnCH2BCmpTrigADC; ///< CH0B姣旇緝鍖归厤瑙﹀彂ADC +}stc_tim3_m23_adc_trig_cfg_t; + +/** + ****************************************************************************** + ** \brief DMA瑙﹀彂 閰嶇疆缁撴瀯浣撳畾涔(妯″紡23) + *****************************************************************************/ +typedef struct stc_tim3_m23_trig_dma_cfg +{ + boolean_t bUevTrigDMA; ///< 鏇存柊 瑙﹀彂DMA浣胯兘 + boolean_t bTITrigDMA; ///< Trig 瑙﹀彂DMA鍔熻兘 + boolean_t bCmpA0TrigDMA; ///< CH0A鎹曡幏姣旇緝瑙﹀彂DMA浣胯兘 + boolean_t bCmpB0TrigDMA; ///< CH0B鎹曡幏姣旇緝瑙﹀彂DMA浣胯兘 + boolean_t bCmpA1TrigDMA; ///< CH1A鎹曡幏姣旇緝瑙﹀彂DMA浣胯兘 + boolean_t bCmpB1TrigDMA; ///< CH1B鎹曡幏姣旇緝瑙﹀彂DMA浣胯兘 + boolean_t bCmpA2TrigDMA; ///< CH2A鎹曡幏姣旇緝瑙﹀彂DMA浣胯兘 + boolean_t bCmpB2TrigDMA; ///< CH2B鎹曡幏姣旇緝瑙﹀彂DMA浣胯兘 + en_tim3_m23_mscr_ccds_t enCmpUevTrigDMA; ///< 姣旇緝妯″紡涓婦MA姣旇緝瑙﹀彂閫夋嫨 +}stc_tim3_m23_trig_dma_cfg_t; + +/** + ****************************************************************************** + ** \brief 涓讳粠妯″紡 閰嶇疆缁撴瀯浣撳畾涔(妯″紡23) + *****************************************************************************/ +typedef struct stc_tim3_m23_master_slave_cfg +{ + en_tim3_m23_mscr_msm_t enMasterSlaveSel; ///< 涓讳粠妯″紡閫夋嫨 + en_tim3_m23_mscr_mms_t enMasterSrc; ///< 涓绘ā寮忚Е鍙戞簮閫夋嫨 + en_tim3_m23_mscr_sms_t enSlaveModeSel; ///< 浠庢ā寮忛夋嫨 + en_tim3_mscr_ts_t enTsSel; ///< 瑙﹀彂杈撳叆婧愰夋嫨 +}stc_tim3_m23_master_slave_cfg_t; + +/** + ****************************************************************************** + ** \brief OCREF娓呴櫎鍔熻兘 閰嶇疆缁撴瀯浣撳畾涔(妯″紡23) + *****************************************************************************/ +typedef struct stc_tim3_m23_OCREF_Clr_cfg +{ + en_tim3_m23ce_occs_t enOCRefClrSrcSel; ///< OCREF娓呴櫎婧愰夋嫨 + boolean_t bVCClrEn; ///< 鏄惁浣胯兘鏉ヨ嚜VC鐨凮CREF_Clr +}stc_tim3_m23_OCREF_Clr_cfg_t; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +//涓柇鐩稿叧鍑芥暟 + +//涓柇鏍囧織鑾峰彇 +boolean_t Tim3_GetIntFlag(en_tim3_irq_type_t enTim3Irq); +//涓柇鏍囧織娓呴櫎 +en_result_t Tim3_ClearIntFlag(en_tim3_irq_type_t enTim3Irq); +//鎵鏈変腑鏂爣蹇楁竻闄 +en_result_t Tim3_ClearAllIntFlag(void); +//妯″紡0涓柇浣胯兘 +en_result_t Tim3_Mode0_EnableIrq(void); +//妯″紡1涓柇浣胯兘 +en_result_t Tim3_Mode1_EnableIrq (en_tim3_irq_type_t enTim3Irq); +//妯″紡2涓柇浣胯兘 +en_result_t Tim3_Mode23_EnableIrq (en_tim3_irq_type_t enTim3Irq); +//妯″紡0涓柇绂佹 +en_result_t Tim3_Mode0_DisableIrq(void); +//妯″紡1涓柇绂佹 +en_result_t Tim3_Mode1_DisableIrq (en_tim3_irq_type_t enTim3Irq); +//妯″紡2涓柇绂佹 +en_result_t Tim3_Mode23_DisableIrq (en_tim3_irq_type_t enTim3Irq); + + +//妯″紡0鍒濆鍖栧強鐩稿叧鍔熻兘鎿嶄綔 + +//timer閰嶇疆鍙婂垵濮嬪寲 +en_result_t Tim3_Mode0_Init(stc_tim3_mode0_cfg_t* pstcCfg); +//timer 鍚姩/鍋滄 +en_result_t Tim3_M0_Run(void); +en_result_t Tim3_M0_Stop(void); +//閲嶈浇鍊艰缃 +en_result_t Tim3_M0_ARRSet(uint16_t u16Data); +//16浣嶈鏁板艰缃/鑾峰彇 +en_result_t Tim3_M0_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M0_Cnt16Get(void); +//32浣嶈鏁板艰缃/鑾峰彇 +en_result_t Tim3_M0_Cnt32Set(uint32_t u32Data); +uint32_t Tim3_M0_Cnt32Get(void); +//绔彛杈撳嚭浣胯兘/绂佹璁惧畾 +en_result_t Tim3_M0_Enable_Output(boolean_t bEnOutput); +//缈昏浆浣胯兘/绂佹锛堜綆鐢靛钩锛夎瀹 +en_result_t Tim3_M0_EnTOG(boolean_t bEnTOG); + +//妯″紡1鍒濆鍖栧強鐩稿叧鍔熻兘鎿嶄綔 + +//timer閰嶇疆鍙婂垵濮嬪寲 +en_result_t Tim3_Mode1_Init(stc_tim3_mode1_cfg_t* pstcCfg); +//PWC 杈撳叆閰嶇疆 +en_result_t Tim3_M1_Input_Cfg(stc_tim3_pwc_input_cfg_t* pstcCfg); +//PWC娴嬮噺杈规部璧峰缁撴潫閫夋嫨 +en_result_t Tim3_M1_PWC_Edge_Sel(en_tim3_m1cr_Edge_t enEdgeSel); +//timer 鍚姩/鍋滄 +en_result_t Tim3_M1_Run(void); +en_result_t Tim3_M1_Stop(void); +//16浣嶈鏁板艰缃/鑾峰彇 +en_result_t Tim3_M1_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M1_Cnt16Get(void); +//鑴夊啿瀹藉害娴嬮噺缁撴灉鏁板艰幏鍙 +uint16_t Tim3_M1_PWC_CapValueGet(void); + + +//妯″紡23鍒濆鍖栧強鐩稿叧鍔熻兘鎿嶄綔 + +//timer閰嶇疆鍙婂垵濮嬪寲 +en_result_t Tim3_Mode23_Init(stc_tim3_mode23_cfg_t* pstcCfg); +//timer 鍚姩/鍋滄 +en_result_t Tim3_M23_Run(void); +en_result_t Tim3_M23_Stop(void); +//PWM杈撳嚭浣胯兘 +en_result_t Tim3_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput); +//閲嶈浇鍊艰缃 +en_result_t Tim3_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn); +//16浣嶈鏁板艰缃/鑾峰彇 +en_result_t Tim3_M23_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M23_Cnt16Get(void); +//姣旇緝鎹曡幏瀵勫瓨鍣–CR0A/CCR0B璁剧疆/璇诲彇 +en_result_t Tim3_M23_CCR_Set(en_tim3_m23_ccrx_t enCCRSel, uint16_t u16Data); +uint16_t Tim3_M23_CCR_Get(en_tim3_m23_ccrx_t enCCRSel); +//PWM浜掕ˉ杈撳嚭妯″紡涓嬶紝GATE鍔熻兘閫夋嫨 +en_result_t Tim3_M23_GateFuncSel(stc_tim3_m23_gate_cfg_t* pstcCfg); +//涓讳粠妯″紡閰嶇疆 +en_result_t Tim3_M23_MasterSlave_Set(stc_tim3_m23_master_slave_cfg_t* pstcCfg); +//CH0A/CH0B姣旇緝閫氶亾鎺у埗 +en_result_t Tim3_M23_PortOutput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_compare_cfg_t* pstcCfg); +//CH0A/CH0B杈撳叆鎺у埗 +en_result_t Tim3_M23_PortInput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_input_cfg_t* pstcCfg); +//ERT杈撳叆鎺у埗 +en_result_t Tim3_M23_ETRInput_Cfg(stc_tim3_m23_etr_input_cfg_t* pstcCfg); +//鍒硅溅BK杈撳叆鎺у埗 +en_result_t Tim3_M23_BrakeInput_Cfg(stc_tim3_m23_bk_input_cfg_t* pstcBkCfg); +//瑙﹀彂ADC鎺у埗 +en_result_t Tim3_M23_TrigADC_Cfg(stc_tim3_m23_adc_trig_cfg_t* pstcCfg); +//姝诲尯鍔熻兘 +en_result_t Tim3_M23_DT_Cfg(stc_tim3_m23_dt_cfg_t* pstcCfg); +//閲嶅鍛ㄦ湡璁剧疆 +en_result_t Tim3_M23_SetValidPeriod(uint8_t u8ValidPeriod); +//OCREF娓呴櫎鍔熻兘 +en_result_t Tim3_M23_OCRefClr(stc_tim3_m23_OCREF_Clr_cfg_t* pstcCfg); +//浣胯兘DMA浼犺緭 +en_result_t Tim3_M23_EnDMA(stc_tim3_m23_trig_dma_cfg_t* pstcCfg); +//鎹曡幏姣旇緝A杞欢瑙﹀彂 +en_result_t Tim3_M23_EnSwTrigCapCmpA(en_tim3_channel_t enTim3Chx); +//鎹曡幏姣旇緝B杞欢瑙﹀彂 +en_result_t Tim3_M23_EnSwTrigCapCmpB(en_tim3_channel_t enTim3Chx); +//杞欢鏇存柊浣胯兘 +en_result_t Tim3_M23_EnSwUev(void); +//杞欢瑙﹀彂浣胯兘 +en_result_t Tim3_M23_EnSwTrig(void); +//杞欢鍒硅溅浣胯兘 +en_result_t Tim3_M23_EnSwBk(void); + + +//@} // Tim3Group + +#ifdef __cplusplus +#endif + + +#endif /* __BT_H__ */ +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + + diff --git a/driver/inc/trim.h b/driver/inc/trim.h new file mode 100644 index 0000000..5b8e7ef --- /dev/null +++ b/driver/inc/trim.h @@ -0,0 +1,184 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/*****************************************************************************/ +/** \file trim.h + ** + ** TRIM 鏁版嵁缁撴瀯鍙夾PI澹版槑 + ** + ** + ** History: + ** - 2018-04-21 Lux V1.0 + ** + *****************************************************************************/ + +#ifndef __TRIM_H__ +#define __TRIM_H__ + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "ddl.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup TrimGroup Clock Trimming (TRIM) + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + ** Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + + /** + ****************************************************************************** + ** \brief 鐩戞祴妯″紡浣胯兘鏋氫妇閲嶅畾涔 (MON_EN) + *****************************************************************************/ +typedef enum en_trim_monitor +{ + TrimMonDisable = 0u, ///< 绂佹 + TrimMonEnable = 0x40u, ///< 浣胯兘 +}en_trim_monitor_t; + + /** + ****************************************************************************** + ** \brief 寰呮牎鍑/鐩戞祴鏃堕挓閫夋嫨鏋氫妇閲嶅畾涔 (CALCLK_SEL) + *****************************************************************************/ +typedef enum en_trim_calclksel +{ + TrimCalMskRCH = 0x000u, ///< RCH + TrimCalMskXTH = 0x010u, ///< XTH + TrimCalMskRCL = 0x020u, ///< RCL + TrimCalMskXTL = 0x030u, ///< XTL + TrimCalMskPLL = 0x100u, ///< PLL +}en_trim_calclksel_t; + +/** + ****************************************************************************** + ** \brief 鍙傝冩椂閽熼夋嫨鏋氫妇閲嶅畾涔 (REFCLK_SEL) + *****************************************************************************/ +typedef enum en_trim_refclksel +{ + TrimRefMskRCH = 0x0u, ///< RCH + TrimRefMskXTH = 0x2u, ///< XTH + TrimRefMskRCL = 0x4u, ///< RCL + TrimRefMskXTL = 0x6u, ///< XTL + TrimRefMskIRC10K = 0x8u, ///< IRC10K + TrimRefMskExtClk = 0xau, ///< 澶栭儴杈撳叆鏃堕挓 +}en_trim_refclksel_t; + +/** + ****************************************************************************** + ** \brief 涓柇鏍囧織绫诲瀷鏋氫妇閲嶅畾涔 + *****************************************************************************/ +typedef enum en_trim_inttype +{ + TrimStop = 0x01u, ///< 鍙傝冭鏁板櫒鍋滄鏍囧織 + TrimCalCntOf = 0x02u, ///< 鏍″噯璁℃暟鍣ㄦ孩鍑烘爣蹇 + TrimXTLFault = 0x04u, ///< XTL 澶辨晥鏍囧織 + TrimXTHFault = 0x08u, ///< XTH 澶辨晥鏍囧織 + TrimPLLFault = 0x10u, ///< PLL 澶辨晥鏍囧織 +}en_trim_inttype_t; + +/** + ****************************************************************************** + ** \brief TRIM 閰嶇疆缁撴瀯浣撳畾涔 + *****************************************************************************/ +typedef struct stc_trim_cfg +{ + en_trim_monitor_t enMON; ///< 鐩戞祴妯″紡浣胯兘 + en_trim_calclksel_t enCALCLK; ///< 鏍″噯鏃堕挓閫夋嫨 + uint32_t u32CalCon; ///< 鏍″噯璁℃暟鍣ㄦ孩鍑哄奸厤缃 + en_trim_refclksel_t enREFCLK; ///< 鍙傝冩椂閽熼夋嫨 + uint32_t u32RefCon; ///< 鍙傝冭鏁板櫒鍒濆奸厤缃 +}stc_trim_cfg_t; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +///<<鍔熻兘閰嶇疆鍙婃搷浣滃嚱鏁 +///IFR&enAdcIrq) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + * \brief + * 鑾峰彇ADC涓柇鐘舵 + * + * \param [in] enAdcIrq ADC涓柇绫诲瀷 @ref en_adc_irq_type_t + * + * \retval Null + */ +void Adc_ClrIrqStatus(en_adc_irq_type_t enAdcIrq) +{ + M0P_ADC->ICR &= ~(uint32_t)enAdcIrq; +} + +/** + * \brief + * ADC涓柇浣胯兘 + * + * \param 鏃 + * + * \retval 鏃 + */ +void Adc_EnableIrq(void) +{ + M0P_ADC->CR0_f.IE = 1u; +} + +/** + * \brief + * ADC涓柇绂佹 + * + * \param 鏃 + * + * \retval 鏃 + */ +void Adc_DisableIrq(void) +{ + M0P_ADC->CR0_f.IE = 0u; +} + +/** + * \brief + * ADC鍒濆鍖 + * + * \param [in] pstcAdcCfg ADC閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + */ +en_result_t Adc_Init(stc_adc_cfg_t* pstcAdcCfg) +{ + if (NULL == pstcAdcCfg) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR0 = 0x1u; ///< ADC 浣胯兘 + delay10us(2); + + M0P_ADC->CR0 |= (uint32_t)pstcAdcCfg->enAdcClkDiv | + (uint32_t)pstcAdcCfg->enAdcRefVolSel | + (uint32_t)pstcAdcCfg->enAdcOpBuf | + (uint32_t)pstcAdcCfg->enAdcSampCycleSel | + (uint32_t)pstcAdcCfg->enInRef; + + M0P_ADC->CR1_f.MODE = pstcAdcCfg->enAdcMode; + M0P_ADC->CR1_f.ALIGN = pstcAdcCfg->enAdcAlign; + + return Ok; +} + + +/** + * \brief + * ADC鍗曟杞崲澶栭儴涓柇瑙﹀彂婧愰厤缃 + * + * \param [in] enAdcTrigSel 瑙﹀彂婧 + * + * \retval en_result_t Null + */ +void Adc_SglExtTrigCfg(en_adc_trig_sel_t enAdcTrigSel, boolean_t bValue) +{ + if(TRUE == bValue) + { + M0P_ADC->EXTTRIGGER0 |= (uint32_t)enAdcTrigSel; + } + else + { + M0P_ADC->EXTTRIGGER0 &= ~(uint32_t)enAdcTrigSel; + } + +} + +/** + * \brief + * ADC椤哄簭鎵弿杞崲澶栭儴涓柇瑙﹀彂婧愰厤缃 + * + * \param [in] enAdcTrigSel 瑙﹀彂婧 + * \param [in] TRUE or FALSE + * + * \retval en_result_t Null + */ +void Adc_SqrExtTrigCfg(en_adc_trig_sel_t enAdcTrigSel, boolean_t bValue) +{ + if(TRUE == bValue) + { + M0P_ADC->EXTTRIGGER0 |= (uint32_t)enAdcTrigSel; + } + else + { + M0P_ADC->EXTTRIGGER0 &= ~(uint32_t)enAdcTrigSel; + } + +} + +/** + * \brief + * ADC鎻掗槦鎵弿杞崲澶栭儴涓柇瑙﹀彂婧愰厤缃 + * + * \param [in] enAdcTrigSel 瑙﹀彂婧 + * \param [in] TRUE or FALSE + * + * \retval en_result_t Null + */ +void Adc_JqrExtTrigCfg(en_adc_trig_sel_t enAdcTrigSel, boolean_t bValue) +{ + if(TRUE == bValue) + { + M0P_ADC->EXTTRIGGER1 |= (uint32_t)enAdcTrigSel; + } + else + { + M0P_ADC->EXTTRIGGER1 &= ~(uint32_t)enAdcTrigSel; + } + +} + + +/** + * \brief + * ADC 鍗曟杞崲寮濮 + * + * \param 鏃 + * + * \retval 鏃 + */ + +void Adc_SGL_Start(void) +{ + M0P_ADC->SGLSTART = 1u; +} + +/** + * \brief + * ADC 鍗曟杞崲鍋滄 + * + * \param 鏃 + * + * \retval 鏃 + */ +void Adc_SGL_Stop(void) +{ + M0P_ADC->SGLSTART = 0u; +} + +/** + * \brief + * ADC 鍗曟杞崲涓鐩磋浆鎹㈠紑濮 + * + * \param 鏃 + * + * \retval 鏃 + */ + +void Adc_SGL_Always_Start(void) +{ + M0P_ADC->ALLSTART = 1u; +} + +/** + * \brief + * ADC 鍗曟杞崲涓鐩磋浆鎹㈠仠姝 + * + * \param 鏃 + * + * \retval 鏃 + */ + +void Adc_SGL_Always_Stop(void) +{ + M0P_ADC->ALLSTART = 0u; +} + +/** + * \brief + * ADC 椤哄簭鎵弿杞崲寮濮 + * + * \param 鏃 + * + * \retval 鏃 + */ + +void Adc_SQR_Start(void) +{ + M0P_ADC->SQRSTART = 1u; +} + +/** + * \brief + * ADC 椤哄簭鎵弿杞崲鍋滄 + * + * \param 鏃 + * + * \retval 鏃 + */ +void Adc_SQR_Stop(void) +{ + M0P_ADC->SQRSTART = 0u; +} +/** + * \brief + * ADC 鎻掗槦鎵弿杞崲寮濮 + * + * \param 鏃 + * + * \retval 鏃 + */ + +void Adc_JQR_Start(void) +{ + M0P_ADC->JQRSTART = 1u; +} + +/** + * \brief + * ADC 鎻掗槦鎵弿杞崲鍋滄 + * + * \param 鏃 + * + * \retval 鏃 + */ +void Adc_JQR_Stop(void) +{ + M0P_ADC->JQRSTART = 0u; +} + +/** + * \brief + * ADC浣胯兘 + * + * \param 鏃 + * + * \retval 鏃 + */ +void Adc_Enable(void) +{ + M0P_ADC->CR0_f.EN = 1u; +} + +/** + * \brief + * ADC闄よ兘 + * + * \param 鏃 + * + * \retval 鏃 + */ +void Adc_Disable(void) +{ + M0P_ADC->CR0_f.EN = 0u; +} + +/** + * \brief + * 閰嶇疆椤哄簭鎵弿杞崲妯″紡 + * + * \param [in] pstcAdcCfg ADC閰嶇疆鎸囬拡 + * \param [in] pstcAdcNormCfg 杩炵画杞崲妯″紡閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + */ +en_result_t Adc_SqrModeCfg(stc_adc_sqr_cfg_t* pstcAdcSqrCfg) +{ + if ((NULL == pstcAdcSqrCfg) || (pstcAdcSqrCfg->u8SqrCnt > 16)) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR1_f.RACCCLR = 0; //ADC杞崲缁撴灉绱姞瀵勫瓨鍣紙ADC_ResultAcc锛夋竻闆 + M0P_ADC->CR1_f.RACCEN = pstcAdcSqrCfg->enResultAcc; + M0P_ADC->CR1_f.DMASQR = pstcAdcSqrCfg->bSqrDmaTrig; + + M0P_ADC->SQR2_f.CNT = pstcAdcSqrCfg->u8SqrCnt - 1; + + return Ok; +} + +/** + * \brief + * 閰嶇疆鎻掗槦鎵弿杞崲妯″紡 + * + * \param [in] pstcAdcCfg ADC閰嶇疆鎸囬拡 + * \param [in] pstcAdcNormCfg 鎵弿杞崲妯″紡閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + */ +en_result_t Adc_JqrModeCfg(stc_adc_jqr_cfg_t* pstcAdcJqrCfg) +{ + if ((NULL == pstcAdcJqrCfg) || (pstcAdcJqrCfg->u8JqrCnt > 4)) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR1_f.DMASQR = pstcAdcJqrCfg->bJqrDmaTrig; + + M0P_ADC->JQR_f.CNT = pstcAdcJqrCfg->u8JqrCnt - 1; + + return Ok; +} + +/** + * \brief + * 閰嶇疆鍗曟杞崲閫氶亾 + * + * \param [in]enstcAdcSampCh 杞崲閫氶亾 + * + * \retval en_result_t Ok: 鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + */ +en_result_t Adc_CfgSglChannel( en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + M0P_ADC->CR0_f.SGLMUX = enstcAdcSampCh; + + return Ok; +} + +/** + * \brief + * 閰嶇疆椤哄簭鎵弿杞崲閫氶亾 + * + * \param [in]enstcAdcSqrChMux 椤哄簭鎵弿杞崲閫氶亾椤哄簭 + * \param [in]enstcAdcSampCh 杞崲閫氶亾 + * + * \retval en_result_t Ok: 鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + */ +en_result_t Adc_CfgSqrChannel(en_adc_sqr_chmux_t enstcAdcSqrChMux, en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + en_result_t enResult = Ok; + + switch(enstcAdcSqrChMux) + { + case AdcSQRCH0MUX: + M0P_ADC->SQR0_f.CH0MUX = enstcAdcSampCh; + break; + case AdcSQRCH1MUX: + M0P_ADC->SQR0_f.CH1MUX = enstcAdcSampCh; + break; + case AdcSQRCH2MUX: + M0P_ADC->SQR0_f.CH2MUX = enstcAdcSampCh; + break; + case AdcSQRCH3MUX: + M0P_ADC->SQR0_f.CH3MUX = enstcAdcSampCh; + break; + case AdcSQRCH4MUX: + M0P_ADC->SQR0_f.CH4MUX = enstcAdcSampCh; + break; + case AdcSQRCH5MUX: + M0P_ADC->SQR0_f.CH5MUX = enstcAdcSampCh; + break; + case AdcSQRCH6MUX: + M0P_ADC->SQR1_f.CH6MUX = enstcAdcSampCh; + break; + case AdcSQRCH7MUX: + M0P_ADC->SQR1_f.CH7MUX = enstcAdcSampCh; + break; + case AdcSQRCH8MUX: + M0P_ADC->SQR1_f.CH8MUX = enstcAdcSampCh; + break; + case AdcSQRCH9MUX: + M0P_ADC->SQR1_f.CH9MUX = enstcAdcSampCh; + break; + case AdcSQRCH10MUX: + M0P_ADC->SQR1_f.CH10MUX = enstcAdcSampCh; + break; + case AdcSQRCH11MUX: + M0P_ADC->SQR1_f.CH11MUX = enstcAdcSampCh; + break; + case AdcSQRCH12MUX: + M0P_ADC->SQR2_f.CH12MUX = enstcAdcSampCh; + break; + case AdcSQRCH13MUX: + M0P_ADC->SQR2_f.CH13MUX = enstcAdcSampCh; + break; + case AdcSQRCH14MUX: + M0P_ADC->SQR2_f.CH14MUX = enstcAdcSampCh; + break; + case AdcSQRCH15MUX: + M0P_ADC->SQR2_f.CH15MUX = enstcAdcSampCh; + break; + default: + enResult = ErrorInvalidParameter; + break; + + } + + return enResult; +} +/** + * \brief + * 閰嶇疆鎻掗槦鎵弿杞崲閫氶亾 + * + * \param [in]enstcAdcSqrChMux 鎻掗槦鎵弿杞崲閫氶亾椤哄簭 + * \param [in]enstcAdcSampCh 杞崲閫氶亾 + * + * \retval en_result_t Ok: 鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + */ +en_result_t Adc_CfgJqrChannel(en_adc_jqr_chmux_t enstcAdcJqrChMux, en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + en_result_t enResult = Ok; + + switch(enstcAdcJqrChMux) + { + case AdcJQRCH0MUX: + M0P_ADC->JQR_f.CH0MUX = enstcAdcSampCh; + break; + case AdcJQRCH1MUX: + M0P_ADC->JQR_f.CH1MUX = enstcAdcSampCh; + break; + case AdcJQRCH2MUX: + M0P_ADC->JQR_f.CH2MUX = enstcAdcSampCh; + break; + case AdcJQRCH3MUX: + M0P_ADC->JQR_f.CH3MUX = enstcAdcSampCh; + break; + default: + enResult = ErrorInvalidParameter; + break; + } + + return enResult; +} + +/** + * \brief + * 鑾峰彇閲囨牱鍊 + * + * + * \retval en_result_t 閲囨牱鍊 + */ +uint32_t Adc_GetSglResult(void) +{ + return M0P_ADC->RESULT; +} + +/** + * \brief + * 鑾峰彇閲囨牱鍊 + * + * \param [in] enstcAdcSqrChMux 椤哄簭鎵弿閫氶亾搴忓彿 @ref en_adc_sqr_chmux_t + * + * \retval en_result_t 閲囨牱鍊 + */ +uint32_t Adc_GetSqrResult(en_adc_sqr_chmux_t enstcAdcSqrChMux) +{ + volatile uint32_t *BaseSqrResultAddress = &(M0P_ADC->SQRRESULT0); + + return *(BaseSqrResultAddress + enstcAdcSqrChMux); + +} + +/** + * \brief + * 鑾峰彇鎻掗槦鎵弿閲囨牱鍊 + * + * \param [in] enstcAdcJqrChMux 鎻掗槦鎵弿閫氶亾搴忓彿@ref en_adc_jqr_chmux_t + * + * \retval en_result_t 閲囨牱鍊 + */ +uint32_t Adc_GetJqrResult(en_adc_jqr_chmux_t enstcAdcJqrChMux) +{ + volatile uint32_t *BaseJqrResultAddress = &(M0P_ADC->JQRRESULT0); + + return *(BaseJqrResultAddress + enstcAdcJqrChMux); + +} + +/** + * \brief + * 鑾峰彇绱姞閲囨牱鍊 + * + * + * \retval en_result_t 绱姞閲囨牱缁撴灉 + */ +uint32_t Adc_GetAccResult(void) +{ + return M0P_ADC->RESULTACC; + +} + +/** + * \brief + * 娓呴浂绱姞閲囨牱鍊 + * + * \param 鏃 + * + * \retval 鏃 + */ +void Adc_ClrAccResult(void) +{ + M0P_ADC->CR1_f.RACCCLR = 0u; +} + +/** + * \brief + * ADC姣旇緝浣胯兘(姣旇緝涓柇) + * + * \param [in] pstcAdcIrqCfg ADC姣旇緝閰嶇疆 @ref stc_adc_threshold_cfg_t + * + * \retval 鏃 + */ + +void Adc_ThresholdCfg(stc_adc_threshold_cfg_t* pstcAdcThrCfg) +{ + M0P_ADC->HT = pstcAdcThrCfg->u32AdcHighThd; + M0P_ADC->LT = pstcAdcThrCfg->u32AdcLowThd; + + M0P_ADC->CR1_f.THCH = pstcAdcThrCfg->enSampChSel; + + M0P_ADC->CR1_f.REGCMP = pstcAdcThrCfg->bAdcRegCmp; + M0P_ADC->CR1_f.HTCMP = pstcAdcThrCfg->bAdcHtCmp; + M0P_ADC->CR1_f.LTCMP = pstcAdcThrCfg->bAdcLtCmp; + +} + + +//@} // AdcGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/src/adt.c b/driver/src/adt.c new file mode 100644 index 0000000..5bcf38f --- /dev/null +++ b/driver/src/adt.c @@ -0,0 +1,1657 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file adt.c + ** + ** Low Voltage Detect driver API. + ** @link Lvd Group Some description @endlink + ** + ** - 2019-04-19 Husj First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "adt.h" + +/** + ****************************************************************************** + ** \addtogroup AdtGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_ADT_STATE(x) ( AdtCMAF == (x)||\ + AdtCMBF == (x)||\ + AdtCMCF == (x)||\ + AdtCMDF == (x)||\ + AdtOVFF == (x)||\ + AdtUDFF == (x)||\ + AdtDTEF == (x)||\ + AdtCMSAUF == (x)||\ + AdtCMSADF == (x)||\ + AdtCMSBUF == (x)||\ + AdtCMSBDF == (x)||\ + AdtCntDir == (x) ) +#define ADTIM_HW_STASTPCLR_EN 31 +#define ADTIM_HW_STASTPCLR_DIS 0x7FFFFFFF +#define ADTIM_SS_TIM4 1 +#define ADTIM_SS_TIM5 2 +#define ADTIM_SS_TIM6 4 +#define ADTIM_PORT_BKE_NUM 15 +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + + + +/***************************************************************** + * \brief + * 閰嶇疆涓柇 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtIrq 涓柇绫诲瀷 + * \param [in] bEn 涓柇浣胯兘/绂佹 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + ****************************************************************/ +en_result_t Adt_CfgIrq(M0P_ADTIM_TypeDef *ADTx, + en_adt_irq_type_t enAdtIrq, + boolean_t bEn) +{ + uint32_t u32Val; + + u32Val = ADTx->ICONR; + if (bEn) + { + u32Val |= 1u<ICONR = u32Val; + return Ok; +} + +/******************************************************************* + * \brief + * 鑾峰彇涓柇鏍囧織 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtIrq 涓柇绫诲瀷 + * + * + * \retval TRUE/FALSE + * + *****************************************************************/ +boolean_t Adt_GetIrqFlag(M0P_ADTIM_TypeDef *ADTx, + en_adt_irq_type_t enAdtIrq) +{ + uint32_t u32Val; + boolean_t bEn; + + ASSERT(IS_VALID_ADT_UNIT(enAdtUnit)); + + u32Val = ADTx->IFR; + bEn = (u32Val>>enAdtIrq) & 0x1; + + return bEn; +} + +/**************************************************************** + * \brief + * 娓呴櫎涓柇鏍囧織 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtIrq 涓柇绫诲瀷 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + ****************************************************************/ +en_result_t Adt_ClearIrqFlag(M0P_ADTIM_TypeDef *ADTx, + en_adt_irq_type_t enAdtIrq) +{ + ADTx->ICLR = ~(1u<ICLR = 0; + return Ok; +} + +/************************************************************** + * \brief + * 閰嶇疆纭欢閫掑姞浜嬩欢 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtHwCntUp 纭欢閫掑姞浜嬩欢 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * + ****************************************************************/ +en_result_t Adt_CfgHwCntUp(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_cnt_t enAdtHwCntUp) +{ + uint32_t u32Val; + + + if (AdtHwCntMax <= enAdtHwCntUp) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HCUPR; + ADTx->HCUPR = u32Val | (1u<HCUPR = 0; + return Ok; +} + + +/********************************************************** + * \brief + * 閰嶇疆纭欢閫掑噺浜嬩欢 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtHwCntDwn 纭欢閫掑噺浜嬩欢 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ***********************************************************/ +en_result_t Adt_CfgHwCntDwn(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_cnt_t enAdtHwCntDwn) +{ + uint32_t u32Val; + + + if(AdtHwCntMax <= enAdtHwCntDwn) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HCDOR; + ADTx->HCDOR = u32Val | (1u<HCDOR = 0; + return Ok; +} + +/****************************************************************** + * \brief + * 閰嶇疆纭欢鍚姩浜嬩欢 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtHwStart 纭欢鍚姩浜嬩欢 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + *******************************************************************/ +en_result_t Adt_CfgHwStart(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwStart) +{ + uint32_t u32Val; + + + if(AdtHwTrigEnd <= enAdtHwStart) + { + return ErrorInvalidParameter; + } + u32Val = ADTx->HSTAR; + ADTx->HSTAR = u32Val | (1u<HSTAR = 0; + return Ok; +} + +/********************************************************************* + * \brief + * 浣胯兘纭欢鍚姩 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * + *********************************************************************/ +en_result_t Adt_EnableHwStart(M0P_ADTIM_TypeDef *ADTx) +{ + uint32_t u32Val; + + u32Val = ADTx->HSTAR; + ADTx->HSTAR = u32Val | (1u<HSTAR; + ADTx->HSTAR = u32Val & ADTIM_HW_STASTPCLR_DIS; + return Ok; +} + +/**************************************************************** + * \brief + * 閰嶇疆纭欢鍋滄浜嬩欢 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtHwStop 纭欢鍋滄浜嬩欢 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ***************************************************************/ +en_result_t Adt_CfgHwStop(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwStop) +{ + uint32_t u32Val; + + if(AdtHwTrigEnd <= enAdtHwStop) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HSTPR; + ADTx->HSTPR = u32Val | (1u<HSTPR = 0; + return Ok; +} + +/************************************************************* + * \brief + * 浣胯兘纭欢鍋滄 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * + **********************************************************/ +en_result_t Adt_EnableHwStop(M0P_ADTIM_TypeDef *ADTx) +{ + uint32_t u32Val; + + u32Val = ADTx->HSTPR; + ADTx->HSTPR = u32Val | (1u<HSTPR; + ADTx->HSTPR = u32Val & ADTIM_HW_STASTPCLR_DIS; + return Ok; +} + +/************************************************************************** + * \brief + * 閰嶇疆纭欢娓呴浂浜嬩欢 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtHwClear 纭欢娓呴浂浜嬩欢 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + *************************************************************************/ +en_result_t Adt_CfgHwClear(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwClear) +{ + uint32_t u32Val; + + + if(AdtHwTrigEnd <= enAdtHwClear) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HCELR; + ADTx->HCELR = u32Val | (1u<HCELR = 0; + return Ok; +} + +/*************************************************************************** + * \brief + * 浣胯兘纭欢娓呴浂 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * + *************************************************************************/ +en_result_t Adt_EnableHwClear(M0P_ADTIM_TypeDef *ADTx) +{ + uint32_t u32Val; + + u32Val = ADTx->HCELR; + ADTx->HCELR = u32Val | (1u<HCELR; + ADTx->HCELR = u32Val & ADTIM_HW_STASTPCLR_DIS; + return Ok; +} + +/******************************************************************* + * \brief + * 閰嶇疆纭欢鎹曡幏A浜嬩欢 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtHwCaptureA 纭欢鎹曡幏A浜嬩欢閫夋嫨 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + *******************************************************************/ +en_result_t Adt_CfgHwCaptureA(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwCaptureA) +{ + uint32_t u32Val; + + + if(AdtHwTrigEnd <= enAdtHwCaptureA) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HCPAR; + ADTx->HCPAR = u32Val | (1u<PCONR_f.CAPCA = 1; + return Ok; +} + +/************************************************************************ + * \brief + * 娓呴櫎纭欢鎹曡幏A浜嬩欢 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * + ***********************************************************************/ +en_result_t Adt_ClearHwCaptureA(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->HCPAR = 0; + return Ok; +} + +/********************************************************************* + * \brief + * 閰嶇疆纭欢鎹曡幏B浜嬩欢 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtHwCaptureB 纭欢鎹曡幏B浜嬩欢閫夋嫨 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ********************************************************************/ +en_result_t Adt_CfgHwCaptureB(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwCaptureB) +{ + uint32_t u32Val; + + + if(AdtHwTrigEnd <= enAdtHwCaptureB) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HCPBR; + ADTx->HCPBR = u32Val | (1u<PCONR_f.CAPCB = 1; + return Ok; +} + +/******************************************************************** + * \brief + * 娓呴櫎纭欢鎹曡幏B浜嬩欢 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * + *******************************************************************/ +en_result_t Adt_ClearHwCaptureB(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->HCPBR = 0; + return Ok; +} + +/***************************************************************** + * \brief + * 杞欢鍚屾寮濮 + * + * \param [in] pstcAdtSwSyncStart 杞欢鍚屾寮濮嬫寚閽 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ***************************************************************/ +en_result_t Adt_SwSyncStart(stc_adt_sw_sync_t* pstcAdtSwSyncStart) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncStart) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncStart->bAdTim4) + { + u32Val |= ADTIM_SS_TIM4; + } + if (pstcAdtSwSyncStart->bAdTim5) + { + u32Val |= ADTIM_SS_TIM5; + } + if (pstcAdtSwSyncStart->bAdTim6) + { + u32Val |= ADTIM_SS_TIM6; + } + + M0P_ADTIM4->SSTAR = u32Val; + return Ok; +} + +/*************************************************************** + * \brief + * 杞欢鍚屾鍋滄 + * + * \param [in] pstcAdtSwSyncStop 杞欢鍚屾鍋滄鎸囬拡 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ***************************************************************/ +en_result_t Adt_SwSyncStop(stc_adt_sw_sync_t* pstcAdtSwSyncStop) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncStop) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncStop->bAdTim4) + { + u32Val |= ADTIM_SS_TIM4; + } + if (pstcAdtSwSyncStop->bAdTim5) + { + u32Val |= ADTIM_SS_TIM5; + } + if (pstcAdtSwSyncStop->bAdTim6) + { + u32Val |= ADTIM_SS_TIM6; + } + + M0P_ADTIM4->SSTPR = u32Val; + return Ok; +} + +/***************************************************************** + * \brief + * 杞欢鍚屾娓呴浂 + * + * \param [in] pstcAdtSwSyncClear 杞欢鍚屾娓呴浂鎸囬拡 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + *******************************************************************/ +en_result_t Adt_SwSyncClear(stc_adt_sw_sync_t* pstcAdtSwSyncClear) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncClear) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncClear->bAdTim4) + { + u32Val |= ADTIM_SS_TIM4; + } + if (pstcAdtSwSyncClear->bAdTim5) + { + u32Val |= ADTIM_SS_TIM5; + } + if (pstcAdtSwSyncClear->bAdTim6) + { + u32Val |= ADTIM_SS_TIM6; + } + + M0P_ADTIM4->SCLRR = u32Val; + return Ok; +} + +/******************************************************************* + * \brief + * 鑾峰彇杞欢鍚屾杩愯鐘舵 + * + * \param [in] pstcAdtSwSyncState ADV Timer杞欢鍚屾杩愯鐘舵佹寚閽 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + *******************************************************************/ +en_result_t Adt_GetSwSyncState(stc_adt_sw_sync_t* pstcAdtSwSyncState) +{ + if (NULL == pstcAdtSwSyncState) + { + return ErrorInvalidParameter; + } + + if (M0P_ADTIM4->SSTAR & ADTIM_SS_TIM4) + { + pstcAdtSwSyncState->bAdTim4 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim4 = FALSE; + } + if (M0P_ADTIM4->SSTAR & ADTIM_SS_TIM5) + { + pstcAdtSwSyncState->bAdTim5 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim5 = FALSE; + } + if (M0P_ADTIM4->SSTAR & ADTIM_SS_TIM6) + { + pstcAdtSwSyncState->bAdTim6 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim6 = FALSE; + } + return Ok; +} + +/************************************************************************ + * \brief + * AOS瑙﹀彂閰嶇疆 + * + * \param [in] pstcAdtAosTrigCfg 瑙﹀彂閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ************************************************************************/ +en_result_t Adt_AosTrigCfg(stc_adt_aos_trig_cfg_t* pstcAdtAosTrigCfg) +{ + if (NULL == pstcAdtAosTrigCfg) + { + return ErrorInvalidParameter; + } + + M0P_ADTIM4->ITRIG_f.IAOS0S = pstcAdtAosTrigCfg->enAos0TrigSrc; + M0P_ADTIM4->ITRIG_f.IAOS1S = pstcAdtAosTrigCfg->enAos1TrigSrc; + M0P_ADTIM4->ITRIG_f.IAOS2S = pstcAdtAosTrigCfg->enAos2TrigSrc; + M0P_ADTIM4->ITRIG_f.IAOS3S = pstcAdtAosTrigCfg->enAos3TrigSrc; + return Ok; +} + +/********************************************************************** + * \brief + * 涓柇瑙﹀彂閰嶇疆 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] pstcAdtIrqTrigCfg 瑙﹀彂閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ***********************************************************************/ +en_result_t Adt_IrqTrigCfg(M0P_ADTIM_TypeDef *ADTx, + stc_adt_irq_trig_cfg_t* pstcAdtIrqTrigCfg) +{ + if(NULL == pstcAdtIrqTrigCfg) + { + return ErrorInvalidParameter; + } + + ADTx->CR_f.CMAE = pstcAdtIrqTrigCfg->bAdtCntMatchATrigEn; + ADTx->CR_f.CMBE = pstcAdtIrqTrigCfg->bAdtCntMatchBTrigEn; + ADTx->CR_f.CMCE = pstcAdtIrqTrigCfg->bAdtCntMatchCTrigEn; + ADTx->CR_f.CMDE = pstcAdtIrqTrigCfg->bAdtCntMatchDTrigEn; + ADTx->CR_f.OVFE = pstcAdtIrqTrigCfg->bAdtOverFlowTrigEn; + ADTx->CR_f.UDFE = pstcAdtIrqTrigCfg->bAdtUnderFlowTrigEn; + ADTx->CR_f.DMA_G_CMA = pstcAdtIrqTrigCfg->bAdtCntMatchATrigDmaEn; + ADTx->CR_f.DMA_G_CMB = pstcAdtIrqTrigCfg->bAdtCntMatchBTrigDmaEn; + ADTx->CR_f.DMA_G_CMC = pstcAdtIrqTrigCfg->bAdtCntMatchCTrigDmaEn; + ADTx->CR_f.DMA_G_CMD = pstcAdtIrqTrigCfg->bAdtCntMatchDTrigDmaEn; + ADTx->CR_f.DMA_G_OVF = pstcAdtIrqTrigCfg->bAdtOverFlowTrigDmaEn; + ADTx->CR_f.DMA_G_UDF = pstcAdtIrqTrigCfg->bAdtUnderFlowTrigDmaEn; + ADTx->CR_f.DMA_S_CMA = pstcAdtIrqTrigCfg->bAdtSpecilMatchATrigDmaEn; + ADTx->CR_f.DMA_S_CMB = pstcAdtIrqTrigCfg->bAdtSpecilMatchBTrigDmaEn; + + return Ok; +} + +/************************************************************************* + * \brief + * 绔彛瑙﹀彂閰嶇疆 + * + * \param [in] enAdtTrigPort 瑙﹀彂绔彛 + * \param [in] pstcAdtPortTrigCfg 瑙﹀彂閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + *************************************************************************/ +en_result_t Adt_PortTrigCfg(en_adt_trig_port_t enAdtTrigPort, + stc_adt_port_trig_cfg_t* pstcAdtPortTrigCfg) +{ + if (NULL == pstcAdtPortTrigCfg) + { + return ErrorInvalidParameter; + } + + switch (enAdtTrigPort) + { + case AdtTrigA: + M0P_ADTIM4->TTRIG_f.TRIGAS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_ADTIM4->FCONR_f.NOFIENTA = pstcAdtPortTrigCfg->bFltEn; + M0P_ADTIM4->FCONR_f.NOFICKTA = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigB: + M0P_ADTIM4->TTRIG_f.TRIGBS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_ADTIM4->FCONR_f.NOFIENTB = pstcAdtPortTrigCfg->bFltEn; + M0P_ADTIM4->FCONR_f.NOFICKTB = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigC: + M0P_ADTIM4->TTRIG_f.TRIGCS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_ADTIM4->FCONR_f.NOFIENTC = pstcAdtPortTrigCfg->bFltEn; + M0P_ADTIM4->FCONR_f.NOFICKTC = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigD: + M0P_ADTIM4->TTRIG_f.TRIGDS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_ADTIM4->FCONR_f.NOFIENTD = pstcAdtPortTrigCfg->bFltEn; + M0P_ADTIM4->FCONR_f.NOFICKTD = pstcAdtPortTrigCfg->enFltClk; + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * CHxX绔彛閰嶇疆 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtCHxXPort CHxX绔彛 + * \param [in] pstcAdtCHxXCfg CHxX绔彛閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + *********************************************************************/ +en_result_t Adt_CHxXPortCfg(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + stc_adt_CHxX_port_cfg_t* pstcAdtCHxXCfg) +{ + if(NULL == pstcAdtCHxXCfg) + { + return ErrorInvalidParameter; + } + + switch (enAdtCHxXPort) + { + case AdtCHxA: + ADTx->PCONR_f.CAPCA = pstcAdtCHxXCfg->enCap; + ADTx->PCONR_f.STACA = pstcAdtCHxXCfg->enStaOut; + ADTx->PCONR_f.STPCA = pstcAdtCHxXCfg->enStpOut; + ADTx->PCONR_f.STASTPSA = pstcAdtCHxXCfg->enStaStp; + ADTx->PCONR_f.CMPCA = pstcAdtCHxXCfg->enCmpc; + ADTx->PCONR_f.PERCA = pstcAdtCHxXCfg->enPerc; + ADTx->PCONR_f.OUTENA = pstcAdtCHxXCfg->bOutEn; + ADTx->PCONR_f.DISSELA = pstcAdtCHxXCfg->enDisSel; + ADTx->PCONR_f.DISVALA = pstcAdtCHxXCfg->enDisVal; + ADTx->FCONR_f.NOFIENGA = pstcAdtCHxXCfg->bFltEn; + ADTx->FCONR_f.NOFICKGA = pstcAdtCHxXCfg->enFltClk; + break; + + case AdtCHxB: + ADTx->PCONR_f.CAPCB = pstcAdtCHxXCfg->enCap; + ADTx->PCONR_f.STACB = pstcAdtCHxXCfg->enStaOut; + ADTx->PCONR_f.STPCB = pstcAdtCHxXCfg->enStpOut; + ADTx->PCONR_f.STASTPSB = pstcAdtCHxXCfg->enStaStp; + ADTx->PCONR_f.CMPCB = pstcAdtCHxXCfg->enCmpc; + ADTx->PCONR_f.PERCB = pstcAdtCHxXCfg->enPerc; + ADTx->PCONR_f.OUTENB = pstcAdtCHxXCfg->bOutEn; + ADTx->PCONR_f.DISSELB = pstcAdtCHxXCfg->enDisSel; + ADTx->PCONR_f.DISVALB = pstcAdtCHxXCfg->enDisVal; + ADTx->FCONR_f.NOFIENGB = pstcAdtCHxXCfg->bFltEn; + ADTx->FCONR_f.NOFICKGB = pstcAdtCHxXCfg->enFltClk; + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/************************************************************************ + * \brief + * 浣胯兘绔彛鍒硅溅 + * + * \param [in] port 绔彛 + * \param [in] pstcAdtBrkPtCfg 绔彛鍒硅溅閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ************************************************************************/ +en_result_t Adt_EnableBrakePort(uint8_t port, stc_adt_break_port_cfg_t* pstcAdtBrkPtCfg) +{ + uint32_t u32Val; + + if (NULL == pstcAdtBrkPtCfg) + { + return ErrorInvalidParameter; + } + + u32Val = M0P_ADTIM4->PTBKP; + u32Val &= ~(1u<PTBKP = u32Val | (pstcAdtBrkPtCfg->enPol<PTBKS; + M0P_ADTIM4->PTBKS = u32Val | (1u<PTBKS = 0; +} + +/********************************************************************* + * \brief + * 鏃犳晥鏉′欢3閰嶇疆 + * + * \param [in] pstcAdtDisable3 鏃犳晥鏉′欢3閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ********************************************************************/ +en_result_t Adt_Disable3Cfg(stc_adt_disable_3_cfg_t* pstcAdtDisable3) +{ + uint8_t i; + + if (NULL == pstcAdtDisable3) + { + return ErrorInvalidParameter; + } + + Adt_ClearBrakePort(); + for (i = 0; i <= ADTIM_PORT_BKE_NUM; i++) + { + if (TRUE == pstcAdtDisable3->stcBrkPtCfg[i].bPortEn) + { + Adt_EnableBrakePort(i, &pstcAdtDisable3->stcBrkPtCfg[i]); + } + } + + M0P_ADTIM4->AOSSR_f.BFILTEN = pstcAdtDisable3->bFltEn; + M0P_ADTIM4->AOSSR_f.BFILTS = pstcAdtDisable3->enFltClk; + + return Ok; +} + +/********************************************************************* + * \brief 杞欢鍒硅溅 Enable/Disable(浠呴傜敤浜庢棤鏁堟潯浠3浣胯兘鐨勬儏鍐典笅) + * + * \param [in] bSwBrk 杞欢鍒硅溅浣胯兘/绂佹 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + ********************************************************************/ +en_result_t Adt_SwBrake(boolean_t bSwBrk) +{ + M0P_ADTIM4->AOSSR_f.SOFTBK = bSwBrk; + + return Ok; +} + +/******************************************************************* + * \brief + * 鑾峰彇绔彛鍒硅溅鏍囧織 + * + * \param none + * + * \retval TRUE or FALSE + ******************************************************************/ +boolean_t Adt_GetPortBrakeFlag(void) +{ + return M0P_ADTIM4->AOSSR_f.FBRAKE; +} + +/****************************************************************** + * \brief + * 娓呴櫎绔彛鍒硅溅鏍囧織 + * + * \param none + * + * \retval none + ******************************************************************/ +void Adt_ClearPortBrakeFlag(void) +{ + M0P_ADTIM4->AOSCL_f.FBRAKE = 0; +} + +/******************************************************************** + * \brief + * 鏃犳晥鏉′欢1閰嶇疆 + * + * \param [in] pstcAdtDisable1 鏃犳晥鏉′欢1閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ********************************************************************/ +en_result_t Adt_Disable1Cfg(stc_adt_disable_1_cfg_t* pstcAdtDisable1) +{ + + if (NULL == pstcAdtDisable1) + { + return ErrorInvalidParameter; + } + + M0P_ADTIM4->AOSSR_f.SMH2 = pstcAdtDisable1->bTim6OutSH; + M0P_ADTIM4->AOSSR_f.SMH1 = pstcAdtDisable1->bTim5OutSH; + M0P_ADTIM4->AOSSR_f.SMH0 = pstcAdtDisable1->bTim4OutSH; + M0P_ADTIM4->AOSSR_f.SML2 = pstcAdtDisable1->bTim6OutSL; + M0P_ADTIM4->AOSSR_f.SML1 = pstcAdtDisable1->bTim5OutSL; + M0P_ADTIM4->AOSSR_f.SML0 = pstcAdtDisable1->bTim4OutSL; + + return Ok; +} + +/******************************************************************** + * \brief + * 鑾峰彇鍚岄珮鍚屼綆鍒硅溅鏍囧織 + * + * \param none + * + * \retval TRUE or FALSE + ********************************************************************/ +boolean_t Adt_GetSameBrakeFlag(void) +{ + return M0P_ADTIM4->AOSSR_f.FSAME; +} + +/********************************************************************* + * \brief + * 娓呴櫎鍚岄珮鍚屼綆鍒硅溅鏍囧織 + * + * \param none + * + * \retval none + *********************************************************************/ +void Adt_ClearSameBrakeFlag(void) +{ + M0P_ADTIM4->AOSCL_f.FSAME = 0; +} + +/******************************************************************** + * \brief + * PWM灞曢閰嶇疆 + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] pstcAdtPwmDitherCfg PWM灞曢閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + *********************************************************************/ +en_result_t Adt_PwmDitherCfg(M0P_ADTIM_TypeDef *ADTx, stc_adt_pwm_dither_cfg_t* pstcAdtPwmDitherCfg) +{ + + + if (NULL == pstcAdtPwmDitherCfg) + { + return ErrorInvalidParameter; + } + + ADTx->CR_f.DITENS = pstcAdtPwmDitherCfg->enAdtPDType; + ADTx->CR_f.DITENB = pstcAdtPwmDitherCfg->bTimxBPDEn; + ADTx->CR_f.DITENA = pstcAdtPwmDitherCfg->bTimxAPDEn; + + return Ok; +} + +/********************************************************************** + * \brief + * ADT鍒濆鍖 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] pstcAdtBaseCntCfg 璁℃暟閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + **********************************************************************/ +en_result_t Adt_Init(M0P_ADTIM_TypeDef *ADTx, stc_adt_basecnt_cfg_t* pstcAdtBaseCntCfg) +{ + + + if(NULL == pstcAdtBaseCntCfg) + { + return ErrorInvalidParameter; + } + + if (AdtTriangleModeB < pstcAdtBaseCntCfg->enCntMode) + { + return ErrorInvalidParameter; + } + + ADTx->GCONR_f.MODE = pstcAdtBaseCntCfg->enCntMode; + ADTx->GCONR_f.DIR = pstcAdtBaseCntCfg->enCntDir; + ADTx->GCONR_f.CKDIV = pstcAdtBaseCntCfg->enCntClkDiv; + + return Ok; +} + +/************************************************************************ + * \brief + * ADT Deinit + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + ***********************************************************************/ +en_result_t Adt_DeInit(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->GCONR_f.START = 0; + ADTx->CNTER = 0; + ADTx->PCONR = 0; + ADTx->GCONR = 0x00000100; + ADTx->DCONR = 0; + ADTx->ICONR = 0; + ADTx->BCONR = 0; + ADTx->FCONR = 0; + ADTx->VPERR = 0; + ADTx->PERAR = 0xFFFF; + ADTx->PERBR = 0xFFFF; + ADTx->GCMAR = 0xFFFF; + ADTx->GCMBR = 0xFFFF; + ADTx->GCMCR = 0xFFFF; + ADTx->GCMDR = 0xFFFF; + ADTx->DTDAR = 0xFFFF; + ADTx->DTUAR = 0xFFFF; + ADTx->HSTAR = 0; + ADTx->HSTPR = 0; + ADTx->HCELR = 0; + ADTx->HCPAR = 0; + ADTx->HCPBR = 0; + ADTx->HCUPR = 0; + ADTx->HCDOR = 0; + ADTx->SSTAR = 0; + ADTx->SSTPR = 0; + ADTx->SCLRR = 0; + ADTx->IFR = 0; + ADTx->CR = 0x00000300; + ADTx->AOSSR = 0; + ADTx->AOSCL = 0; + ADTx->PTBKS = 0; + ADTx->PTBKP = 0; + ADTx->TTRIG = 0; + ADTx->ITRIG = 0; + + return Ok; +} + +/*********************************************************************** + * \brief + * 寮濮嬭鏁 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + ***********************************************************************/ +en_result_t Adt_StartCount(M0P_ADTIM_TypeDef *ADTx) +{ + + ADTx->GCONR_f.START = 1; + + return Ok; +} + +/*********************************************************************** + * \brief + * 鍋滄璁℃暟 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + **********************************************************************/ +en_result_t Adt_StopCount(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->GCONR_f.START = 0; + + return Ok; +} + +/******************************************************************** + * \brief + * 璁剧疆璁℃暟鍊 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] u16Value 璁℃暟鍊 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + *******************************************************************/ +en_result_t Adt_SetCount(M0P_ADTIM_TypeDef *ADTx, uint16_t u16Value) +{ + ADTx->CNTER_f.CNT = u16Value; + return Ok; +} + +/******************************************************************** + * \brief + * 鑾峰彇璁℃暟鍊 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * + * \retval uint16_t u16Value: 褰撳墠璁℃暟鍊 + * + *******************************************************************/ +uint16_t Adt_GetCount(M0P_ADTIM_TypeDef *ADTx) +{ + uint16_t u16Value; + + ASSERT(IS_VALID_ADT_UNIT(enAdtUnit)); + + u16Value = ADTx->CNTER_f.CNT; + + return u16Value; +} + +/************************************************************************** + * \brief + * 娓呴櫎璁℃暟鍊 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + **************************************************************************/ +en_result_t Adt_ClearCount(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->CNTER_f.CNT = 0; + return Ok; +} + +/************************************************************************* + * \brief + * 鑾峰彇鏈夋晥鍛ㄦ湡璁℃暟鍊 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * \retval uint8_t u8TempCnt: 鏈夋晥鍛ㄦ湡鍊 + * + *************************************************************************/ +uint8_t Adt_GetVperNum(M0P_ADTIM_TypeDef *ADTx) +{ + uint8_t u8TempCnt; + + + ASSERT(IS_VALID_ADT_UNIT(enAdtUnit)); + + u8TempCnt = ADTx->STFLR_f.VPERNUM; + + return u8TempCnt; +} + +/************************************************************************* + * \brief + * 鑾峰彇鐘舵佹爣蹇 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) +* \param [in] enstate 鐘舵佹爣蹇楃被鍨 + * + * \retval TURE/FALSE + * + *************************************************************************/ +boolean_t Adt_GetState(M0P_ADTIM_TypeDef *ADTx, en_adt_state_type_t enstate) +{ + + + ASSERT(IS_VALID_ADT_UNIT(enAdtUnit)); + ASSERT(IS_VALID_ADT_STATE(enstate)); + + return GetBit(((uint32_t)&ADTx->STFLR), enstate); +} + +/*********************************************************************** + * \brief + * 閰嶇疆璁℃暟鍛ㄦ湡 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] u16Period 璁℃暟鍛ㄦ湡鍊 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + ***********************************************************************/ +en_result_t Adt_SetPeriod(M0P_ADTIM_TypeDef *ADTx, uint16_t u16Period) +{ + ADTx->PERAR = u16Period; + + return Ok; +} + +/*********************************************************************** + * \brief + * 閰嶇疆璁℃暟鍛ㄦ湡缂撳啿 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] u16PeriodBuf 璁℃暟鍛ㄦ湡缂撳啿鍊 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + ***********************************************************************/ +en_result_t Adt_SetPeriodBuf(M0P_ADTIM_TypeDef *ADTx, uint16_t u16PeriodBuf) +{ + ADTx->PERBR = u16PeriodBuf; + ADTx->BCONR_f.BENP = 1u; + + return Ok; +} + +/********************************************************************** + * \brief + * 娓呴櫎璁℃暟鍛ㄦ湡缂撳啿 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + **********************************************************************/ +en_result_t Adt_ClearPeriodBuf(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->BCONR_f.BENP = 0; + ADTx->PERBR = 0; + + return Ok; +} + +/*********************************************************************** + * \brief + * 閰嶇疆鏈夋晥璁℃暟鍛ㄦ湡 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] pstcAdtValidPerCfg 鏈夋晥璁℃暟鍛ㄦ湡閰嶇疆鎸囬拡 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ***********************************************************************/ +en_result_t Adt_SetValidPeriod(M0P_ADTIM_TypeDef *ADTx, + stc_adt_validper_cfg_t* pstcAdtValidPerCfg) +{ + + + if(NULL == pstcAdtValidPerCfg) + { + return ErrorInvalidParameter; + } + + ADTx->VPERR_f.PCNTS = pstcAdtValidPerCfg->enValidCnt; + ADTx->VPERR_f.PCNTE = pstcAdtValidPerCfg->enValidCdt; + ADTx->VPERR_f.GEPERID = pstcAdtValidPerCfg->bPeriodD; + ADTx->VPERR_f.GEPERIC = pstcAdtValidPerCfg->bPeriodC; + ADTx->VPERR_f.GEPERIB = pstcAdtValidPerCfg->bPeriodB; + ADTx->VPERR_f.GEPERIA = pstcAdtValidPerCfg->bPeriodA; + + return Ok; +} + +/************************************************************************ + * \brief + * 閰嶇疆姣旇緝杈撳嚭璁℃暟鍩哄噯鍊 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtCompare 閫氱敤姣旇緝鍩哄噯瀵勫瓨鍣 + * \param [in] u16Compare 姣旇緝鍩哄噯鍊 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + *************************************************************************/ +en_result_t Adt_SetCompareValue(M0P_ADTIM_TypeDef *ADTx, + en_adt_compare_t enAdtCompare, + uint16_t u16Compare) +{ + if (AdtCompareA == enAdtCompare) + { + ADTx->GCMAR = u16Compare; + } + else if (AdtCompareB == enAdtCompare) + { + ADTx->GCMBR = u16Compare; + } + else if (AdtCompareC == enAdtCompare) + { + ADTx->GCMCR = u16Compare; + } + else if (AdtCompareD == enAdtCompare) + { + ADTx->GCMDR = u16Compare; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/************************************************************************ + * \brief + * 閰嶇疆涓撶敤姣旇緝璁℃暟鍩哄噯鍊 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtSpclCmp 涓撶敤姣旇緝鍩哄噯鍊煎瘎瀛樺櫒 + * \param [in] u16SpclCmp 姣旇緝鍩哄噯鍊 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + *************************************************************************/ +en_result_t Adt_SetSpecilCompareValue(M0P_ADTIM_TypeDef *ADTx, + en_adt_special_compare_t enAdtSpclCmp, + uint16_t u16SpclCmp) +{ + if (AdtSpclCompA == enAdtSpclCmp) + { + ADTx->SCMAR_f.SCMA = u16SpclCmp; + } + else if (AdtSpclCompB == enAdtSpclCmp) + { + ADTx->SCMBR_f.SCMB = u16SpclCmp; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/********************************************************************** + * \brief + * 閰嶇疆閫氱敤姣旇緝鍊/鎹曡幏鍊肩紦瀛樹紶閫 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtCHxXPort TIMxX閫氶亾 + * \param [in] bCompareBufEn 閫氱敤姣旇緝鍊肩紦瀛樹紶閫佷娇鑳 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + **********************************************************************/ +en_result_t Adt_EnableValueBuf(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + boolean_t bCompareBufEn) +{ + if (AdtCHxA == enAdtCHxXPort) + { + ADTx->BCONR_f.BENA = bCompareBufEn; + } + else if (AdtCHxB == enAdtCHxXPort) + { + ADTx->BCONR_f.BENB = bCompareBufEn; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * 娓呴櫎姣旇緝杈撳嚭璁℃暟鍊/鎹曡幏鍊肩紦瀛 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtCHxXPort TIMxX閫氶亾 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + **********************************************************************/ +en_result_t Adt_ClearValueBuf(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort) +{ + if (AdtCHxA == enAdtCHxXPort) + { + ADTx->GCMCR = 0; + } + else if (AdtCHxB == enAdtCHxXPort) + { + ADTx->GCMDR = 0; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * 鑾峰彇鎹曡幏鍊 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtCHxXPort TIMxX閫氶亾 + * \param [in] pu16Capture 鎹曡幏鍊兼寚閽 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ***********************************************************************/ +en_result_t Adt_GetCaptureValue(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + uint16_t* pu16Capture) +{ + if (AdtCHxA == enAdtCHxXPort) + { + *pu16Capture = ADTx->GCMAR_f.GCMA; + } + else if (AdtCHxB == enAdtCHxXPort) + { + *pu16Capture = ADTx->GCMBR_f.GCMB; + } + else + { + return ErrorInvalidParameter; + } + return Ok; +} + +/********************************************************************** + * \brief + * 鑾峰彇鎹曡幏缂撳瓨鍊 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] enAdtCHxXPort TIMxX閫氶亾 + * \param [in] pu16CaptureBuf 鎹曡幏缂撳瓨鍊兼寚閽 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + ***********************************************************************/ +en_result_t Adt_GetCaptureBuf(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + uint16_t* pu16CaptureBuf) +{ + if (AdtCHxA == enAdtCHxXPort) + { + *pu16CaptureBuf = ADTx->GCMCR_f.GCMC; + } + else if (AdtCHxB == enAdtCHxXPort) + { + *pu16CaptureBuf = ADTx->GCMDR_f.GCMD; + } + else + { + return ErrorInvalidParameter; + } + return Ok; +} + +/*********************************************************************** + * \brief + * 璁剧疆姝诲尯鏃堕棿涓婂熀鍑嗗 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] u16Value 姝诲尯鏃堕棿涓婂熀鍑嗗 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + ************************************************************************/ +en_result_t Adt_SetDTUA(M0P_ADTIM_TypeDef *ADTx, + uint16_t u16Value) +{ + ADTx->DTUAR = u16Value; + + return Ok; +} + +/*********************************************************************** + * \brief + * 璁剧疆姝诲尯鏃堕棿涓嬪熀鍑嗗 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] u16Value 姝诲尯鏃堕棿涓嬪熀鍑嗗 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + ***********************************************************************/ +en_result_t Adt_SetDTDA(M0P_ADTIM_TypeDef *ADTx, + uint16_t u16Value) +{ + ADTx->DTDAR = u16Value; + + return Ok; +} + +/****************************************************************** + * \brief + * 閰嶇疆姝诲尯鏃堕棿鍔熻兘 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] bDTEn 姝诲尯鍔熻兘浣胯兘 + * \param [in] bEqual DTDAR鐨勫煎拰DTUAR鐨勫艰嚜鍔ㄧ浉绛 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + *****************************************************************/ +en_result_t Adt_CfgDT(M0P_ADTIM_TypeDef *ADTx, + boolean_t bDTEn, + boolean_t bEqual) +{ + ADTx->DCONR_f.DTCEN = bDTEn; + ADTx->DCONR_f.SEPA = bEqual; + + return Ok; +} + +/************************************************************************* + * \brief + * Z鐩歌緭鍏ュ睆钄借缃 + * + * \param [in] ADTx ADV Timer閫氶亾閫夋嫨(M0P_ADTIM4銆丮0P_ADTIM5銆丮0P_ADTIM6) + * \param [in] pstcAdtZMaskCfg Z鐩歌緭鍏ュ睆钄藉姛鑳介厤缃寚閽 + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * + *************************************************************************/ +en_result_t Adt_CfgZMask(M0P_ADTIM_TypeDef *ADTx, stc_adt_zmask_cfg_t* pstcAdtZMaskCfg) +{ + if(NULL == pstcAdtZMaskCfg) + { + return ErrorInvalidParameter; + } + + ADTx->GCONR_f.ZMSK = pstcAdtZMaskCfg->enZMaskCycle; + ADTx->GCONR_f.ZMSKPOS = pstcAdtZMaskCfg->bFltPosCntMaksEn; + ADTx->GCONR_f.ZMSKREV = pstcAdtZMaskCfg->bFltRevCntMaksEn; + + return Ok; +} + +//@} // AdtGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/src/aes.c b/driver/src/aes.c new file mode 100644 index 0000000..63fb2e7 --- /dev/null +++ b/driver/src/aes.c @@ -0,0 +1,206 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file aes.c + ** + ** Common API of AES. + ** @link AesGroup Some description @endlink + ** + ** - 2019-04-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "aes.h" +/** + ******************************************************************************* + ** \addtogroup AesGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * \brief + * AES 鍔犲瘑 + * + * \param [in] pstcAesCfg AES 閰嶇疆缁撴瀯浣 @ref stc_aes_cfg_t + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + */ +en_result_t AES_Encrypt(stc_aes_cfg_t* pstcAesCfg) +{ + if (NULL == pstcAesCfg) + { + return ErrorInvalidParameter; + } + + M0P_AES->CR_f.KEYSIZE = pstcAesCfg->enKeyLen; + + //Key cfg + M0P_AES->KEY0 = pstcAesCfg->pu32Key[0]; + M0P_AES->KEY1 = pstcAesCfg->pu32Key[1]; + M0P_AES->KEY2 = pstcAesCfg->pu32Key[2]; + M0P_AES->KEY3 = pstcAesCfg->pu32Key[3]; + + if(AesKey192 == pstcAesCfg->enKeyLen) + { + M0P_AES->KEY4 = pstcAesCfg->pu32Key[4]; + M0P_AES->KEY5 = pstcAesCfg->pu32Key[5]; + } + + if(AesKey256 == pstcAesCfg->enKeyLen) + { + M0P_AES->KEY4 = pstcAesCfg->pu32Key[4]; + M0P_AES->KEY5 = pstcAesCfg->pu32Key[5]; + M0P_AES->KEY6 = pstcAesCfg->pu32Key[6]; + M0P_AES->KEY7 = pstcAesCfg->pu32Key[7]; + } + + //Data cfg + M0P_AES->DATA0 = pstcAesCfg->pu32Plaintext[0]; + M0P_AES->DATA1 = pstcAesCfg->pu32Plaintext[1]; + M0P_AES->DATA2 = pstcAesCfg->pu32Plaintext[2]; + M0P_AES->DATA3 = pstcAesCfg->pu32Plaintext[3]; + + M0P_AES->CR_f.MODE = 0;//Encry + M0P_AES->CR_f.START = 1; + while(M0P_AES->CR_f.START == 1) + { + ; + } + pstcAesCfg->pu32Cipher[0] = M0P_AES->DATA0; + pstcAesCfg->pu32Cipher[1] = M0P_AES->DATA1; + pstcAesCfg->pu32Cipher[2] = M0P_AES->DATA2; + pstcAesCfg->pu32Cipher[3] = M0P_AES->DATA3; + return Ok; +} + + +/** + * \brief + * AES 瑙ｅ瘑 + * + * \param [in] pstcAesCfg AES 閰嶇疆缁撴瀯浣 @ref stc_aes_cfg_t + * + * \retval en_result_t Ok: 閰嶇疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥鍙傛暟 + */ +en_result_t AES_Decrypt(stc_aes_cfg_t* pstcAesCfg) +{ + if (NULL == pstcAesCfg) + { + return ErrorInvalidParameter; + } + + M0P_AES->CR_f.KEYSIZE = pstcAesCfg->enKeyLen; + + //Key cfg + M0P_AES->KEY0 = pstcAesCfg->pu32Key[0]; + M0P_AES->KEY1 = pstcAesCfg->pu32Key[1]; + M0P_AES->KEY2 = pstcAesCfg->pu32Key[2]; + M0P_AES->KEY3 = pstcAesCfg->pu32Key[3]; + + if(AesKey192 == pstcAesCfg->enKeyLen) + { + M0P_AES->KEY4 = pstcAesCfg->pu32Key[4]; + M0P_AES->KEY5 = pstcAesCfg->pu32Key[5]; + } + + if(AesKey256 == pstcAesCfg->enKeyLen) + { + M0P_AES->KEY4 = pstcAesCfg->pu32Key[4]; + M0P_AES->KEY5 = pstcAesCfg->pu32Key[5]; + M0P_AES->KEY6 = pstcAesCfg->pu32Key[6]; + M0P_AES->KEY7 = pstcAesCfg->pu32Key[7]; + } + + //Data cfg + M0P_AES->DATA0 = pstcAesCfg->pu32Cipher[0]; + M0P_AES->DATA1 = pstcAesCfg->pu32Cipher[1]; + M0P_AES->DATA2 = pstcAesCfg->pu32Cipher[2]; + M0P_AES->DATA3 = pstcAesCfg->pu32Cipher[3]; + + M0P_AES->CR_f.MODE = 1;//UnEncry + M0P_AES->CR_f.START = 1; + while(M0P_AES->CR_f.START == 1) + { + ; + } + pstcAesCfg->pu32Plaintext[0] = M0P_AES->DATA0; + pstcAesCfg->pu32Plaintext[1] = M0P_AES->DATA1; + pstcAesCfg->pu32Plaintext[2] = M0P_AES->DATA2; + pstcAesCfg->pu32Plaintext[3] = M0P_AES->DATA3; + return Ok; +} + +//@} // AesGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/bgr.c b/driver/src/bgr.c new file mode 100644 index 0000000..c500c87 --- /dev/null +++ b/driver/src/bgr.c @@ -0,0 +1,143 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file bgr.c + ** + ** Common API of bgr. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "bgr.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief BGR 浣胯兘 + ** + ** + ** \retval Null + *****************************************************************************/ +void Bgr_BgrEnable(void) +{ + M0P_BGR->CR |= 0x1u; + + delay10us(2); +} + +/** + ***************************************************************************** + ** \brief BGR 绂佹 + ** + ** + ** \retval Null + *****************************************************************************/ +void Bgr_BgrDisable(void) +{ + M0P_BGR->CR &= 0x2u; +} + +/** + ***************************************************************************** + ** \brief BGR 娓╁害浼犳劅鍣ㄤ娇鑳(闇瑕佸厛寮鍚疊GR) + ** + ** + ** \retval Null + *****************************************************************************/ +void Bgr_TempSensorEnable(void) +{ + M0P_BGR->CR |= 0x2u; + + delay10us(2); +} + +/** + ***************************************************************************** + ** \brief BGR 娓╁害浼犳劅鍣ㄧ姝 + ** + ** + ** \retval Null + *****************************************************************************/ +void Bgr_TempSensorDisable(void) +{ + M0P_BGR->CR &= 0x1u; +} + + +//@} // BgrGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/bt.c b/driver/src/bt.c new file mode 100644 index 0000000..27ecd1d --- /dev/null +++ b/driver/src/bt.c @@ -0,0 +1,1381 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file bt.c + ** + ** Common API of base timer. + ** @link btGroup Some description @endlink + ** + ** - 2019-04-15 Husj First Version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "bt.h" +/** + ******************************************************************************* + ** \addtogroup BtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_TIM(x) (TIM0 == (x) ||\ + TIM1 == (x) ||\ + TIM2 == (x)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Base Timer 涓柇鏍囧織鑾峰彇(妯″紡0/1/23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] enBtIrq 涓柇绫诲瀷 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Bt_GetIntFlag(en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + boolean_t bRetVal = FALSE; + uint32_t u32Val; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u32Val = pstcM0PBt->IFR; + bRetVal = (u32Val>>enBtIrq) & 0x1; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Base Timer 涓柇鏍囧織娓呴櫎(妯″紡0/1/23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] enBtIrq 涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_ClearIntFlag(en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ICLR = ~(1u<ICLR = 0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 涓柇浣胯兘(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_EnableIrq(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.UIE = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 涓柇绂佹(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_DisableIrq(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.UIE = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 涓柇浣胯兘(妯″紡1) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] enBtIrq 涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_EnableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M1CR_f.UIE = TRUE; + break; + case BtCA0Irq: + pstcM0PBt->CR0_f.CIEA = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 涓柇绂佹(妯″紡1) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] enBtIrq 涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_DisableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M1CR_f.UIE = FALSE; + break; + case BtCA0Irq: + pstcM0PBt->CR0_f.CIEA = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 涓柇浣胯兘(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] enBtIrq 涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_EnableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M23CR_f.UIE = TRUE; + break; + case BtCA0Irq: + pstcM0PBt->CRCH0_f.CIEA = TRUE; + break; + case BtCB0Irq: + pstcM0PBt->CRCH0_f.CIEB = TRUE; + break; + case BtBkIrq: + pstcM0PBt->M23CR_f.BIE = TRUE; + break; + case BtTrigIrq: + pstcM0PBt->M23CR_f.TIE = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 涓柇绂佹(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] enBtIrq 涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_DisableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M23CR_f.UIE = FALSE; + break; + case BtCA0Irq: + pstcM0PBt->CRCH0_f.CIEA = FALSE; + break; + case BtCB0Irq: + pstcM0PBt->CRCH0_f.CIEB = FALSE; + break; + case BtBkIrq: + pstcM0PBt->M23CR_f.BIE = FALSE; + break; + case BtTrigIrq: + pstcM0PBt->M23CR_f.TIE = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鍒濆鍖栭厤缃(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_Init(en_bt_unit_t enUnit, stc_bt_mode0_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.MODE = pstcCfg->enWorkMode; + pstcM0PBt->M0CR_f.GATEP = pstcCfg->enGateP; + pstcM0PBt->M0CR_f.GATE = pstcCfg->bEnGate; + pstcM0PBt->M0CR_f.PRS = pstcCfg->enPRS; + pstcM0PBt->M0CR_f.TOGEN = pstcCfg->bEnTog; + pstcM0PBt->M0CR_f.CT = pstcCfg->enCT; + pstcM0PBt->M0CR_f.MD = pstcCfg->enCntMode; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鍚姩杩愯(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鍋滄杩愯(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 缈昏浆杈撳嚭浣胯兘/绂佹锛堜綆鐢靛钩锛夎瀹(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] bEnTOG 缈昏浆杈撳嚭璁惧畾 TRUE:浣胯兘, FALSE:绂佹 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_EnTOG_Output(en_bt_unit_t enUnit, boolean_t bEnTOG) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.TOGEN = bEnTOG; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 绔彛杈撳嚭浣胯兘/绂佹璁惧畾(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] bEnOutput 绔彛杈撳嚭璁惧畾 TRUE:浣胯兘, FALSE:绂佹 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Enable_Output(en_bt_unit_t enUnit, boolean_t bEnOutput) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.MOE = bEnOutput; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16浣嶈鏁板櫒鍒濆艰缃(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] u16Data 16浣嶅垵鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16浣嶈鏁板艰幏鍙(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval 16bits璁℃暟鍊 + *****************************************************************************/ +uint16_t Bt_M0_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u16CntData = pstcM0PBt->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 閲嶈浇鍊艰缃(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] u16Data 16bits閲嶈浇鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_ARRSet(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ARR_f.ARR = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 32浣嶈鏁板櫒鍒濆艰缃(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] u32Data 32浣嶅垵鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Cnt32Set(en_bt_unit_t enUnit, uint32_t u32Data) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CNT32_f.CNT32 = u32Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 32浣嶈鏁板艰幏鍙(妯″紡0) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval 32bits璁℃暟鍊 + *****************************************************************************/ +uint32_t Bt_M0_Cnt32Get(en_bt_unit_t enUnit) +{ + uint32_t u32CntData = 0; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u32CntData = pstcM0PBt->CNT32_f.CNT32; + + return u32CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鍒濆鍖栭厤缃(妯″紡1) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_Init(en_bt_unit_t enUnit, stc_bt_mode1_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M1CR_f.MODE = pstcCfg->enWorkMode; + pstcM0PBt->M1CR_f.PRS = pstcCfg->enPRS; + pstcM0PBt->M1CR_f.CT = pstcCfg->enCT; + pstcM0PBt->M1CR_f.ONESHOT = pstcCfg->enOneShot; + + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWC 杈撳叆閰嶇疆(妯″紡1) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Input_Cfg(en_bt_unit_t enUnit, stc_bt_pwc_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->MSCR_f.TS = pstcCfg->enTsSel; + pstcM0PBt->MSCR_f.IA0S = pstcCfg->enIA0Sel; + pstcM0PBt->MSCR_f.IB0S = pstcCfg->enIB0Sel; + pstcM0PBt->FLTR_f.ETP = pstcCfg->enETRPhase; + pstcM0PBt->FLTR_f.FLTET = pstcCfg->enFltETR; + pstcM0PBt->FLTR_f.FLTA0 = pstcCfg->enFltIA0; + pstcM0PBt->FLTR_f.FLTB0 = pstcCfg->enFltIB0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWC娴嬮噺杈规部璧峰缁撴潫閫夋嫨(妯″紡1) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] enEdgeSel pwc娴嬮噺璧峰缁堟鐢靛钩 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_PWC_Edge_Sel(en_bt_unit_t enUnit,en_bt_m1cr_Edge_t enEdgeSel) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enEdgeSel) + { + case 0: ///< 涓婂崌娌垮埌涓婂崌娌(鍛ㄦ湡) + pstcM0PBt->M1CR_f.EDG1ST = 0; //涓婂崌娌 + pstcM0PBt->M1CR_f.EDG2ND = 0; //涓婂崌娌 + break; + case 1: ///< 涓嬮檷娌垮埌涓婂崌娌(浣庣數骞) + pstcM0PBt->M1CR_f.EDG1ST = 1; //涓嬮檷娌 + pstcM0PBt->M1CR_f.EDG2ND = 0; //涓婂崌娌 + break; + case 2: ///< 涓婂崌娌垮埌涓嬮檷娌(楂樼數骞) + pstcM0PBt->M1CR_f.EDG1ST = 0; //涓婂崌娌 + pstcM0PBt->M1CR_f.EDG2ND = 1; //涓嬮檷娌 + break; + case 3: ///< 涓嬮檷娌垮埌涓嬮檷娌(鍛ㄦ湡) + pstcM0PBt->M1CR_f.EDG1ST = 1; //涓嬮檷娌 + pstcM0PBt->M1CR_f.EDG2ND = 1; //涓嬮檷娌 + break; + default: + ; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鍚姩杩愯(妯″紡1) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M1CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鍋滄杩愯(妯″紡1) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M1CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16浣嶈鏁板櫒鍒濆艰缃(妯″紡1) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] u16Data 16浣嶅垵鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16浣嶈鏁板艰幏鍙(妯″紡1) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval 16bits璁℃暟鍊 + *****************************************************************************/ +uint16_t Bt_M1_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u16CntData = pstcM0PBt->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鑴夊啿瀹藉害娴嬮噺缁撴灉鏁板艰幏鍙(妯″紡1) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval 16bits鑴夊啿瀹藉害娴嬮噺缁撴灉 + *****************************************************************************/ +uint16_t Bt_M1_PWC_CapValueGet(en_bt_unit_t enUnit) +{ + uint16_t u16CapData = 0; + + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u16CapData = pstcM0PBt->CCR0A_f.CCR0A; + + return u16CapData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鍒濆鍖栭厤缃(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_Init(en_bt_unit_t enUnit, stc_bt_mode23_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.MODE = pstcCfg->enWorkMode; + + pstcM0PBt->M23CR_f.PRS = pstcCfg->enPRS; + pstcM0PBt->M23CR_f.CT = pstcCfg->enCT; + pstcM0PBt->M23CR_f.COMP = pstcCfg->enPWMTypeSel; + pstcM0PBt->M23CR_f.PWM2S = pstcCfg->enPWM2sSel; + pstcM0PBt->M23CR_f.ONESHOT = pstcCfg->bOneShot; + pstcM0PBt->M23CR_f.URS = pstcCfg->bURSSel; + pstcM0PBt->M23CR_f.DIR = pstcCfg->enCntDir; + + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWM杈撳嚭浣胯兘/绂佹(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] bEnOutput PWM杈撳嚭浣胯兘/绂佹璁惧畾 + ** \param [in] bEnAutoOutput PWM鑷姩杈撳嚭浣胯兘/绂佹璁惧畾 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnPWM_Output(en_bt_unit_t enUnit, boolean_t bEnOutput, boolean_t bEnAutoOutput) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.MOE = bEnOutput; + pstcM0PBt->DTR_f.AOE = bEnAutoOutput; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief Base Timer 鍚姩杩愯(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鍋滄杩愯(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 閲嶈浇鍊艰缃(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] u16Data 16bits閲嶈浇鍊 + ** \param [in] bArrBufEn ARR閲嶈浇缂撳瓨浣胯兘TRUE/绂佹FALSE + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_ARRSet(en_bt_unit_t enUnit, uint16_t u16Data, boolean_t bArrBufEn) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ARR_f.ARR = u16Data; + pstcM0PBt->M23CR_f.BUFPEN = bArrBufEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16浣嶈鏁板櫒鍒濆艰缃(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] u16Data 16浣嶅垵鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16浣嶈鏁板艰幏鍙(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval 16bits璁℃暟鍊 + *****************************************************************************/ +uint16_t Bt_M23_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + u16CntData = pstcM0PBt->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 姣旇緝鎹曡幏瀵勫瓨鍣–CR0A/CCR0B璁剧疆(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] enCCRSel CCR0A/CCR0B璁惧畾 + ** \param [in] u16Data CCR0A/CCR0B 16浣嶅垵濮嬪 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_CCR_Set(en_bt_unit_t enUnit, en_bt_m23_ccrx_t enCCRSel, uint16_t u16Data) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + if(BtCCR0A == enCCRSel) + { + pstcM0PBt->CCR0A_f.CCR0A = u16Data; + } + else if(BtCCR0B == enCCRSel) + { + pstcM0PBt->CCR0B_f.CCR0B = u16Data; + } + else + { + enResult = Error; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 姣旇緝鎹曡幏瀵勫瓨鍣–CR0A/CCR0B璇诲彇(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] enCCRSel CCR0A/CCR0B璁惧畾 + ** + ** \retval 16bitsCCR0A鎹曡幏鍊 + *****************************************************************************/ +uint16_t Bt_M23_CCR_Get(en_bt_unit_t enUnit, en_bt_m23_ccrx_t enCCRSel) +{ + uint16_t u16Data = 0; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + if(BtCCR0A == enCCRSel) + { + u16Data = pstcM0PBt->CCR0A_f.CCR0A; + } + else if(BtCCR0B == enCCRSel) + { + u16Data = pstcM0PBt->CCR0B_f.CCR0B; + } + else + { + u16Data = 0; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWM浜掕ˉ杈撳嚭妯″紡涓嬶紝GATE鍔熻兘閫夋嫨(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_GateFuncSel(en_bt_unit_t enUnit,stc_bt_m23_gate_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CSG = pstcCfg->enGateFuncSel; + pstcM0PBt->M23CR_f.CRG = pstcCfg->bGateRiseCap; + pstcM0PBt->M23CR_f.CFG = pstcCfg->bGateFallCap; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 涓讳粠妯″紡閰嶇疆(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_MasterSlave_Set(en_bt_unit_t enUnit, stc_bt_m23_master_slave_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->MSCR_f.MSM = pstcCfg->enMasterSlaveSel; + pstcM0PBt->MSCR_f.MMS = pstcCfg->enMasterSrc; + pstcM0PBt->MSCR_f.SMS = pstcCfg->enSlaveModeSel; + pstcM0PBt->MSCR_f.TS = pstcCfg->enTsSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer CH0A/CH0B姣旇緝閫氶亾杈撳嚭鎺у埗(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_PortOutput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_compare_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CSA = 0; + pstcM0PBt->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCH0ACmpCtrl; + pstcM0PBt->FLTR_f.CCPA0 = pstcCfg->enCH0APolarity; + pstcM0PBt->CRCH0_f.BUFEA = pstcCfg->bCh0ACmpBufEn; + pstcM0PBt->M23CR_f.CIS = pstcCfg->enCh0ACmpIntSel; + + pstcM0PBt->CRCH0_f.CSB = 0; + pstcM0PBt->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCH0BCmpCtrl; + pstcM0PBt->FLTR_f.CCPB0 = pstcCfg->enCH0BPolarity; + pstcM0PBt->CRCH0_f.BUFEB = pstcCfg->bCH0BCmpBufEn; + pstcM0PBt->CRCH0_f.CISB = pstcCfg->enCH0BCmpIntSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer CH0A/CH0B杈撳叆鎺у埗(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_PortInput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CSA = 1; + pstcM0PBt->CRCH0_f.CFA_CRA_BKSA = pstcCfg->enCH0ACapSel; + pstcM0PBt->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCH0AInFlt; + pstcM0PBt->FLTR_f.CCPA0 = pstcCfg->enCH0APolarity; + + pstcM0PBt->CRCH0_f.CSB = 1; + pstcM0PBt->CRCH0_f.CFB_CRB_BKSB = pstcCfg->enCH0BCapSel; + pstcM0PBt->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCH0BInFlt; + pstcM0PBt->FLTR_f.CCPB0 = pstcCfg->enCH0BPolarity; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer ERT杈撳叆鎺у埗(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_ETRInput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_etr_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->FLTR_f.ETP = pstcCfg->enETRPolarity; + pstcM0PBt->FLTR_f.FLTET = pstcCfg->enETRFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鍒硅溅BK杈撳叆鎺у埗(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_BrakeInput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_bk_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.BKE = pstcCfg->bEnBrake; + pstcM0PBt->DTR_f.VCE = pstcCfg->bEnVCBrake; + pstcM0PBt->DTR_f.SAFEEN = pstcCfg->bEnSafetyBk; + pstcM0PBt->DTR_f.BKSEL = pstcCfg->bEnBKSync; + pstcM0PBt->CRCH0_f.CFA_CRA_BKSA = pstcCfg->enBkCH0AStat; + pstcM0PBt->CRCH0_f.CFB_CRB_BKSB = pstcCfg->enBkCH0BStat; + pstcM0PBt->FLTR_f.BKP = pstcCfg->enBrakePolarity; + pstcM0PBt->FLTR_f.FLTBK = pstcCfg->enBrakeFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 瑙﹀彂ADC鎺у埗(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_TrigADC_Cfg(en_bt_unit_t enUnit, stc_bt_m23_adc_trig_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ADTR_f.ADTE = pstcCfg->bEnTrigADC; + pstcM0PBt->ADTR_f.UEVE = pstcCfg->bEnUevTrigADC; + pstcM0PBt->ADTR_f.CMA0E = pstcCfg->bEnCH0ACmpTrigADC; + pstcM0PBt->ADTR_f.CMB0E = pstcCfg->bEnCH0BCmpTrigADC; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer 姝诲尯鍔熻兘(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_DT_Cfg(en_bt_unit_t enUnit, stc_bt_m23_dt_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.DTEN = pstcCfg->bEnDeadTime; + pstcM0PBt->DTR_f.DTR = pstcCfg->u8DeadTimeValue; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer 閲嶅鍛ㄦ湡璁剧疆(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] u8ValidPeriod 閲嶅鍛ㄦ湡鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_SetValidPeriod(en_bt_unit_t enUnit, uint8_t u8ValidPeriod) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->RCR_f.RCR = u8ValidPeriod; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer OCREF娓呴櫎鍔熻兘(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_OCRefClr(en_bt_unit_t enUnit, stc_bt_m23_OCREF_Clr_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.OCCS = pstcCfg->enOCRefClrSrcSel; + pstcM0PBt->M23CR_f.OCCE = pstcCfg->bVCClrEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 浣胯兘DMA浼犺緭(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnDMA(en_bt_unit_t enUnit, stc_bt_m23_trig_dma_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.UDE = pstcCfg->bUevTrigDMA; + pstcM0PBt->M23CR_f.TDE = pstcCfg->bTITrigDMA; + pstcM0PBt->CRCH0_f.CDEA = pstcCfg->bCmpATrigDMA; + pstcM0PBt->CRCH0_f.CDEB = pstcCfg->bCmpBTrigDMA; + pstcM0PBt->MSCR_f.CCDS = pstcCfg->enCmpUevTrigDMA; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鎹曡幏姣旇緝A杞欢瑙﹀彂(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrigCapCmpA(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CCGA = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 鎹曡幏姣旇緝B杞欢瑙﹀彂(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrigCapCmpB(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CCGB = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 杞欢鏇存柊浣胯兘(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwUev(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.UG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 杞欢瑙﹀彂浣胯兘(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrig(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.TG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 杞欢鍒硅溅浣胯兘(妯″紡23) + ** + ** + ** \param [in] enUnit Timer閫氶亾閫夋嫨锛圱IM0銆乀IM1銆乀IM2锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwBk(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.BG = TRUE; + + return enResult; +} + +//@} // BtGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/crc.c b/driver/src/crc.c new file mode 100644 index 0000000..aab257f --- /dev/null +++ b/driver/src/crc.c @@ -0,0 +1,438 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file crc.c + ** + ** Common API of crc. + ** @link crcGroup Some description @endlink + ** + ** - 2017-05-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "crc.h" +/** + ******************************************************************************* + ** \addtogroup CrcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief CRC16 缂栫爜(瀛楄妭濉厖鏂瑰紡) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庣敓鎴怌RC16缂栫爜. + ** + ** \param [in] pu8Data 寰呯紪鐮佹暟鎹寚閽堬紙瀛楄妭鏂瑰紡杈撳叆锛 + ** \param [in] u32Len 寰呯紪鐮佹暟鎹暱搴︼紙瀛楄妭鏁帮級 + ** + ** \retval CRC16 CRC16缂栫爜鍊. + *****************************************************************************/ +uint16_t CRC16_Get8(uint8_t* pu8Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT = 0xFFFF; + for(u32Index = 0;u32IndexDATA))) = pu8Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 缂栫爜(鍗婂瓧濉厖鏂瑰紡) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庣敓鎴怌RC16缂栫爜. + ** + ** \param [in] pu16Data 寰呯紪鐮佹暟鎹寚閽堬紙鍗婂瓧鏂瑰紡杈撳叆锛 + ** \param [in] u32Len 寰呯紪鐮佹暟鎹暱搴︼紙鍗婂瓧鏁帮級 + ** + ** \retval CRC16 CRC16缂栫爜鍊. + *****************************************************************************/ +uint16_t CRC16_Get16(uint16_t* pu16Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 缂栫爜(瀛楀～鍏呮柟寮) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庣敓鎴怌RC16缂栫爜. + ** + ** \param [in] pu32Data 寰呯紪鐮佹暟鎹寚閽堬紙瀛楁柟寮忚緭鍏ワ級 + ** \param [in] u32Len 寰呯紪鐮佹暟鎹暱搴︼紙瀛楁暟锛 + ** + ** \retval CRC16 CRC16缂栫爜鍊. + *****************************************************************************/ +uint16_t CRC16_Get32(uint32_t* pu32Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA_f.DATA = pu32Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 鏍￠獙(瀛楄妭濉厖鏂瑰紡) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庡鏁版嵁鍙奀RC16鍊艰繘琛屾牎楠. + ** + ** \param [in] pu8Data 寰呮牎楠屾暟鎹寚閽堬紙瀛楄妭鏂瑰紡杈撳叆锛 + ** \param [in] u32Len 寰呮牎楠屾暟鎹暱搴︼紙瀛楄妭鏁帮級 + ** \param [in] u16CRC 寰呮牎楠孋RC16鍊 + ** + ** \retval Ok CRC鏍￠獙姝ｇ‘ + ** \retval Error CRC鏍￠獙閿欒 + *****************************************************************************/ +en_result_t CRC16_Check8(uint8_t* pu8Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu8Data[u32Index]; + } + + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((((uint32_t)u16CRC)>>0)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)(((uint32_t)u16CRC>>8)&0xFF); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 鏍￠獙(鍗婂瓧濉厖鏂瑰紡) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庡鏁版嵁鍙奀RC16鍊艰繘琛屾牎楠. + ** + ** \param [in] pu16Data 寰呮牎楠屾暟鎹寚閽堬紙鍗婂瓧鏂瑰紡杈撳叆锛 + ** \param [in] u32Len 寰呮牎楠屾暟鎹暱搴︼紙鍗婂瓧鏁帮級 + ** \param [in] u16CRC 寰呮牎楠孋RC16鍊 + ** + ** \retval Ok CRC鏍￠獙姝ｇ‘ + ** \retval Error CRC鏍￠獙閿欒 + *****************************************************************************/ +en_result_t CRC16_Check16(uint16_t* pu16Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = u16CRC; + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 鏍￠獙(瀛楀～鍏呮柟寮) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庡鏁版嵁鍙奀RC16鍊艰繘琛屾牎楠. + ** + ** \param [in] pu32Data 寰呮牎楠屾暟鎹寚閽堬紙瀛楁柟寮忚緭鍏ワ級 + ** \param [in] u32Len 寰呮牎楠屾暟鎹暱搴︼紙瀛楁暟锛 + ** \param [in] u16CRC 寰呮牎楠孋RC16鍊 + ** + ** \retval Ok CRC鏍￠獙姝ｇ‘ + ** \retval Error CRC鏍￠獙閿欒 + *****************************************************************************/ +en_result_t CRC16_Check32(uint32_t* pu32Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu32Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = ((uint16_t)u16CRC); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 缂栫爜(瀛楄妭濉厖鏂瑰紡) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庣敓鎴怌RC16缂栫爜. + ** + ** \param [in] pu8Data 寰呯紪鐮佹暟鎹寚閽堬紙瀛楄妭鏂瑰紡杈撳叆锛 + ** \param [in] u32Len 寰呯紪鐮佹暟鎹暱搴︼紙瀛楄妭鏁帮級 + ** + ** \retval CRC16 CRC16缂栫爜鍊. + *****************************************************************************/ +uint32_t CRC32_Get8(uint8_t* pu8Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT = 0xFFFFFFFFu; + for(u32Index = 0;u32IndexDATA))) = pu8Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 缂栫爜(鍗婂瓧濉厖鏂瑰紡) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庣敓鎴怌RC16缂栫爜. + ** + ** \param [in] pu16Data 寰呯紪鐮佹暟鎹寚閽堬紙鍗婂瓧鏂瑰紡杈撳叆锛 + ** \param [in] u32Len 寰呯紪鐮佹暟鎹暱搴︼紙鍗婂瓧鏁帮級 + ** + ** \retval CRC16 CRC16缂栫爜鍊. + *****************************************************************************/ +uint32_t CRC32_Get16(uint16_t* pu16Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 缂栫爜(瀛楀～鍏呮柟寮) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庣敓鎴怌RC16缂栫爜. + ** + ** \param [in] pu32Data 寰呯紪鐮佹暟鎹寚閽堬紙瀛楁柟寮忚緭鍏ワ級 + ** \param [in] u32Len 寰呯紪鐮佹暟鎹暱搴︼紙瀛楁暟锛 + ** + ** \retval CRC16 CRC16缂栫爜鍊. + *****************************************************************************/ +uint32_t CRC32_Get32(uint32_t* pu32Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA_f.DATA = pu32Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 鏍￠獙(瀛楄妭濉厖鏂瑰紡) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庡鏁版嵁鍙奀RC16鍊艰繘琛屾牎楠. + ** + ** \param [in] pu8Data 寰呮牎楠屾暟鎹寚閽堬紙瀛楄妭鏂瑰紡杈撳叆锛 + ** \param [in] u32Len 寰呮牎楠屾暟鎹暱搴︼紙瀛楄妭鏁帮級 + ** \param [in] u16CRC 寰呮牎楠孋RC16鍊 + ** + ** \retval Ok CRC鏍￠獙姝ｇ‘ + ** \retval Error CRC鏍￠獙閿欒 + *****************************************************************************/ +en_result_t CRC32_Check8(uint8_t* pu8Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu8Data[u32Index]; + } + + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>0)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>8)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>16)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>24)&0xFF); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 鏍￠獙(鍗婂瓧濉厖鏂瑰紡) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庡鏁版嵁鍙奀RC16鍊艰繘琛屾牎楠. + ** + ** \param [in] pu16Data 寰呮牎楠屾暟鎹寚閽堬紙鍗婂瓧鏂瑰紡杈撳叆锛 + ** \param [in] u32Len 寰呮牎楠屾暟鎹暱搴︼紙鍗婂瓧鏁帮級 + ** \param [in] u16CRC 寰呮牎楠孋RC16鍊 + ** + ** \retval Ok CRC鏍￠獙姝ｇ‘ + ** \retval Error CRC鏍￠獙閿欒 + *****************************************************************************/ +en_result_t CRC32_Check16(uint16_t* pu16Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = (uint16_t)((u32CRC>>0)&0xFFFF); + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = (uint16_t)((u32CRC>>16)&0xFFFF); + + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 鏍￠獙(瀛楀～鍏呮柟寮) + ** + ** 璇ュ嚱鏁颁富瑕佺敤浜庡鏁版嵁鍙奀RC16鍊艰繘琛屾牎楠. + ** + ** \param [in] pu32Data 寰呮牎楠屾暟鎹寚閽堬紙瀛楁柟寮忚緭鍏ワ級 + ** \param [in] u32Len 寰呮牎楠屾暟鎹暱搴︼紙瀛楁暟锛 + ** \param [in] u16CRC 寰呮牎楠孋RC16鍊 + ** + ** \retval Ok CRC鏍￠獙姝ｇ‘ + ** \retval Error CRC鏍￠獙閿欒 + *****************************************************************************/ +en_result_t CRC32_Check32(uint32_t* pu32Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu32Data[u32Index]; + } + + *((volatile uint32_t*)(&(M0P_CRC->DATA))) = u32CRC; + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} +//@} // CrcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/dac.c b/driver/src/dac.c new file mode 100644 index 0000000..9fb01fa --- /dev/null +++ b/driver/src/dac.c @@ -0,0 +1,253 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file dac.c + ** + ** dac driver API. + ** + ** - 2019-04-10 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "dac.h" + +/** + ****************************************************************************** + ** \addtogroup AdcGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** +****************************************************************************** + ** \brief 浣胯兘鐩稿叧閫氶亾鐨凞MA DMA_CR0涓殑DMAEN0 + ** + ** @param NewState : TRUE 鎴栬 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Dac_DmaCmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_DAC->CR0)), 12, NewState); +} + +/** +****************************************************************************** + ** \brief 閰嶇疆DAC鐨凞MA涓嬫孩涓柇锛 DMA_CR0涓殑DMAUDRIE0 + ** + ** @param NewState : TRUE 鎴栬 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Dac_DmaITCfg(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_DAC->CR0)), 13, NewState); +} + +/** +****************************************************************************** + ** \brief 鑾峰彇DAC鐨凞MA涓嬫孩涓柇鏍囧織浣嶇姸鎬侊紝 DMA_SR涓殑DMAUDR0 + ** + ** @param 鏃 + ** \retval TRUE 鎴 FALSE + ** +******************************************************************************/ +boolean_t Dac_GetITStatus(void) +{ + return GetBit((uint32_t)(&(M0P_DAC->SR)), 13); +} + +/** +****************************************************************************** + ** \brief 閰嶇疆DAC鐨勪娇鑳戒笌绂佹锛 DMA_CR0涓殑EN0 + ** + ** @param NewState : TRUE 鎴栬 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Dac_Cmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_DAC->CR0)), 0, NewState); +} + +/** +****************************************************************************** + ** \brief 杞欢瑙﹀彂瀵勫瓨鍣紝瑙﹀彂DAC杞崲 DMA_SWTRIGR涓殑SWTRIG0 + ** + ** @param 鏃 + ** \retval 鏃 + ** +******************************************************************************/ +void Dac_SoftwareTriggerCmd(void) +{ + SetBit((uint32_t)(&(M0P_DAC->SWTRIGR)), 0, 1); +} + +/** +****************************************************************************** +** \brief 鍒濆鍖朌AC0 + ** + ** @param DAC_InitStruct : 鐢ㄤ簬鍒濆鍖朌AC0鐨勭粨鏋勪綋 + ** \retval 鏃 + ** +******************************************************************************/ +void Dac_Init(stc_dac_cfg_t* DAC_InitStruct) +{ + M0P_DAC->CR0_f.BOFF0 = DAC_InitStruct->boff_t; + M0P_DAC->CR0_f.TEN0 = DAC_InitStruct->ten_t; + M0P_DAC->CR0_f.TSEL0 = DAC_InitStruct->tsel_t; + M0P_DAC->CR0_f.WAVE0 = DAC_InitStruct->wave_t; + M0P_DAC->CR0_f.MAMP0 = DAC_InitStruct->mamp_t; + M0P_DAC->CR0_f.SREF0 = DAC_InitStruct->sref_t; + + if(DAC_InitStruct->align == DacLeftAlign) + { + M0P_DAC->DHR12L0_f.DHR0 = DAC_InitStruct->dhr12; + } + else if(DAC_InitStruct->align == DacRightAlign) + { + M0P_DAC->DHR12R0_f.DHR0 = DAC_InitStruct->dhr12; + } + else + { + M0P_DAC->DHR8R0_f.DHR0 = DAC_InitStruct->dhr8; + } +} + +/** +****************************************************************************** +** \brief 鍚慏AC0鐨勬暟鎹繚鎸佸瘎瀛樺櫒鍐欐暟鎹 + ** + ** @param DAC_Channel: Dac_0 + ** @param DAC_Align : Right_Align 涓嶭eft_Align + ** @param DAC_Bit : Bit8 涓嶣it12 + ** @param Data : 鎵瑕佸彂閫佺殑鏁版嵁 + ** \retval 鏃 + ** +******************************************************************************/ +void Dac_SetChannelData(en_align_t DAC_Align, en_bitno_t DAC_Bit, uint16_t Data) +{ + if(DAC_Align == DacRightAlign) + { + if(DAC_Bit == DacBit8) + { + M0P_DAC->DHR8R0_f.DHR0 = (uint8_t)Data; + } + else if(DAC_Bit == DacBit12) + { + M0P_DAC->DHR12R0_f.DHR0 = Data; + } + else + { + return; + } + } + else if(DAC_Align == DacLeftAlign) + { + if(DAC_Bit == DacBit8) + { + return; + } + else if(DAC_Bit == DacBit12) + { + M0P_DAC->DHR12L0_f.DHR0 = Data; + } + else + { + return; + } + } + else + { + return; + } +} + + + +/** +****************************************************************************** + ** \brief 鑾峰彇DAC鏁版嵁杈撳嚭瀵勫瓨鍣―AC_DOR0 + ** + ** @param 鏃 + ** \retval DAC_DOR0鐨勫 + ** +******************************************************************************/ +uint16_t Dac_GetDataOutputValue(void) +{ + uint16_t tmp; + + tmp = M0P_DAC->DOR0_f.DOR0; + return tmp&0x0fff; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/driver/src/ddl.c b/driver/src/ddl.c new file mode 100644 index 0000000..f2457e4 --- /dev/null +++ b/driver/src/ddl.c @@ -0,0 +1,250 @@ +/******************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file ddl.c + ** + ** Common API of DDL. + ** @link ddlGroup Some description @endlink + ** + ** - 2019-03-03 + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ddl.h" + +/** + ****************************************************************************** + ** \addtogroup DDL Common Functions + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +#ifndef __DEBUG +#define __DEBUG +//#define __CC_ARM +#endif + +uint32_t Log2(uint32_t u32Val) +{ + uint32_t u32V1 = 0; + + if(0u == u32Val) + { + return 0; + } + + while(u32Val > 1u) + { + u32V1++; + u32Val /=2; + } + + return u32V1; +} + + +/** + ******************************************************************************* + ** \brief Memory clear function for DDL_ZERO_STRUCT() + ******************************************************************************/ +void ddl_memclr(void *pu8Address, uint32_t u32Count) +{ + uint8_t *pu8Addr = (uint8_t *)pu8Address; + + if(NULL == pu8Addr) + { + return; + } + + while (u32Count--) + { + *pu8Addr++ = 0; + } +} + +/** + * \brief delay1ms + * delay approximately 1ms. + * \param [in] u32Cnt + * \retval void + */ +void delay1ms(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + u32end = 0x1000000 - SystemCoreClock/1000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + +/** + * \brief delay100us + * delay approximately 100us. + * \param [in] u32Cnt + * \retval void + */ +void delay100us(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + + u32end = 0x1000000 - SystemCoreClock/10000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + +/** + * \brief delay10us + * delay approximately 10us. + * \param [in] u32Cnt + * \retval void + */ +void delay10us(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + + u32end = 0x1000000 - SystemCoreClock/100000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + +/** + * \brief set register bit + * + * \param [in] addr + * \param [in] offset + * \retval void + */ +void SetBit(uint32_t addr, uint32_t offset, boolean_t bFlag) +{ + if(TRUE == bFlag) + { + *((volatile uint32_t *)(addr)) |= ((1UL)<<(offset)); + } + else + { + *((volatile uint32_t *)(addr)) &= (~(1UL<<(offset))); + } + + +} + + +/** + * \brief get register bit + * + * \param [in] addr + * \param [in] offset + * \retval void + */ +boolean_t GetBit(uint32_t addr, uint32_t offset) +{ + return ((((*((volatile uint32_t *)(addr))) >> (offset)) & 1u) > 0) ? TRUE : FALSE; +} +//@} // DDL Functions + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/src/debug.c b/driver/src/debug.c new file mode 100644 index 0000000..c7fb0fc --- /dev/null +++ b/driver/src/debug.c @@ -0,0 +1,119 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file debug.c + ** + ** Common API of debug. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "debug.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief 璋冭瘯妯″紡涓嬫ā鍧楀姛鑳借鏁颁娇鑳 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Debug_ActiveEnable(en_debug_module_active_t enModule) +{ + M0P_DEBUG_ACTIVE->DEBUG_ACTIVE &= ~(uint32_t)enModule; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief 璋冭瘯妯″紡涓嬫ā鍧楀姛鑳借鏁版殏鍋 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Debug_ActiveDisable(en_debug_module_active_t enModule) +{ + M0P_DEBUG_ACTIVE->DEBUG_ACTIVE |= (uint32_t)enModule; + + return Ok; +} + + +//@} // BgrGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/dmac.c b/driver/src/dmac.c new file mode 100644 index 0000000..7bb6234 --- /dev/null +++ b/driver/src/dmac.c @@ -0,0 +1,624 @@ +/****************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file dmac.c +** +** A detailed description is available at +** @link DmacGroup Dmac description @endlink +** +** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac. +** +******************************************************************************/ + +/******************************************************************************* +* Include files +******************************************************************************/ +#include "dmac.h" + +/** +******************************************************************************* +** \addtogroup DmacGroup +******************************************************************************/ +//@{ + +/******************************************************************************* +* Local type definitions ('typedef') +******************************************************************************/ + +/******************************************************************************* +* Local pre-processor symbols/macros ('#define') +******************************************************************************/ + +/******************************************************************************/ +/* DMA */ +/******************************************************************************/ + +/************** Bits definition for DMA_CONFBx(x=0~1) register *************/ +#define DMA_TRANSFER_WIDTH_Pos (26U) /*!< DMAC_CONFBx: ERR_IE Position */ +#define DMA_TRANSFER_WIDTH_Msk (0x03U << DMA_TRANSFER_WIDTH_Pos) /*!< DMAC_CONFBx: ERR_IE Mask 0x0C000000 */ + +/************** Bits definition for DMA_CONFBx(x=0~1) register *************/ +#define DMA_ERR_IE_Pos (20U) /*!< DMAC_CONFBx: ERR_IE Position */ +#define DMA_ERR_IE_Msk (0x01U << DMA_ERR_IE_Pos) /*!< DMAC_CONFBx: ERR_IE Mask 0x00000010 */ + +/************** Bits definition for DMA_CONFBx(x=0~1) register *************/ +#define DMA_FIS_IE_Pos (19U) /*!< DMAC_CONFBx: FIS_IE Position */ +#define DMA_FIS_IE_Msk (0x01U << DMA_FIS_IE_Pos) /*!< DMAC_CONFBx: FIS_IE Mask 0x00000010 */ + +/************** Bits definition for DMA_CONFBx(x=0~1) register *************/ +#define DMA_STAT_Pos (16U) /*!< DMAC_CONFBx: STAT Position */ +#define DMA_STAT_Msk (0x07U << DMA_STAT_Pos) /*!< DMAC_CONFBx: STAT Mask 0x00070000 */ + +/************** Bits definition for DMA_CONFBx(x=0~1) register *************/ +#define DMA_TRANSFER_RELOAD_Pos (0U) /*!< DMAC_CONFBx: MSK Position */ +#define DMA_TRANSFER_RELOAD_Msk (0x01U << DMA_TRANSFER_RELOAD_Pos) /*!< DMAC_CONFBx: MSK Mask 0x00000010 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_CH_ENABLE_Pos (31U) /*!< DMAC_CONFAx: ENS Position */ +#define DMA_CH_ENABLE_Msk (0x01U << DMA_CH_ENABLE_Pos) /*!< DMAC_CONFAx: ENS Mask 0x80000000 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_CH_PAUSE_Pos (30U) /*!< DMAC_CONFAx: PAS Position */ +#define DMA_CH_PAUSE_Msk (0x01U << DMA_CH_PAUSE_Pos) /*!< DMAC_CONFAx: PAS Mask 0x40000000 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_SOFTWARE_START_Pos (29U) /*!< DMAC_CONFAx: ENS Position */ +#define DMA_SOFTWARE_START_Msk (0x01U << DMA_SOFTWARE_START_Pos) /*!< DMAC_CONFAx: ENS Mask 0x20000000 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_TRI_SEL_Pos (22U) /*!< DMAC_CONFAx: TRISEL Position */ +#define DMA_TRI_SEL_Msk (0x7FU << DMA_TRI_SEL_Pos) /*!< DMAC_CONFAx: TRISEL Mask 0x1FC00000 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_BC_SEL_Pos (16U) /*!< DMAC_CONFAx: TRISEL Position */ +#define DMA_BC_SEL_Msk (0x0FU << DMA_BC_SEL_Pos) /*!< DMAC_CONFAx: TRISEL Mask 0x000F0000 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_TC_SEL_Pos (0U) /*!< DMAC_CONFAx: TRISEL Position */ +#define DMA_TC_SEL_Msk (0xFFFFU << DMA_TC_SEL_Pos) /*!< DMAC_CONFAx: TRISEL Mask 0x0000FFFF */ + +/************** Bits definition for DMA_CONF register *************/ +#define DMA_ENABLE_Pos (31U) /*!< DMAC_CONF: TRISEL Position */ +#define DMA_ENABLE_Msk (0x01U << DMA_ENABLE_Pos) /*!< DMAC_CONF: TRISEL Mask 0x80000000 */ + +/************** Bits definition for DMA_CONF register *************/ +#define DMA_PRIORITY_Pos (28U) /*!< DMAC_CONF: TRISEL Position */ +#define DMA_PRIORITY_Msk (0x01U << DMA_PRIORITY_Pos) /*!< DMAC_CONF: TRISEL Mask 0x10000000 */ + + +/*! Dmac閫氶亾鍙傛暟鏈夋晥鎬ф鏌. */ +#define IS_VALID_CH(x) \ +( (DmaCh0 == (x)) || \ + (DmaCh1 == (x))) + +/*! DMA 浼犺緭鏁版嵁瀹藉害锛屽弬鏁版湁鏁堟ф鏌. */ +#define IS_VALID_TRN_WIDTH(x) \ +( (DmaMsk8Bit == (x)) || \ + (DmaMsk16Bit == (x)) || \ + (DmaMsk32Bit == (x))) + +/*! DMA婧愬湴鍧鎺у埗妯″紡锛屽弬鏁版湁鏁堟ф鏌. */ +#define IS_VALID_SRC_ADDR_MODE(x) \ +( (DmaMskSrcAddrFix == (x)) || \ + (DmaMskSrcAddrInc == (x))) + +/*! DMA鐩殑鍦板潃鎺у埗妯″紡锛屽弬鏁版湁鏁堟ф鏌. */ +#define IS_VALID_DST_ADDR_MODE(x) \ +( (DmaMskDstAddrFix == (x)) || \ + (DmaMskDstAddrInc == (x))) + +/*! DMA 浼樺厛绾, 鍙傛暟鏈夋晥鎬ф鏌. */ +#define IS_VALID_PRIO_MODE(x) \ +( (DmaMskPriorityFix == (x)) || \ + (DmaMskPriorityLoop == (x))) + +/*! DMA 浼犺緭妯″紡锛屽弬鏁版湁鏁堟ф鏌. */ +#define IS_VALID_TRANSFER_MODE(x) \ +( (DmaMskOneTransfer == (x)) || \ + (DmaMskContinuousTransfer == (x))) + +/*! 鍧椾紶杈撳ぇ灏忥紝鍙傛暟鏈夋晥鎬ф鏌. */ +#define IS_VALID_BLKSIZE(x) ((!((x) & ~(DMA_BC_SEL_Msk >> DMA_BC_SEL_Pos)))&&((x)>0)) + +/*! 鍧椾紶杈撴鏁帮紝鍙傛暟鏈夋晥鎬ф鏌. */ +#define IS_VALID_TRNCNT(x) (!((x) & ~(DMA_TC_SEL_Msk >> DMA_TC_SEL_Pos))) + +/******************************************************************************* +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + +/******************************************************************************* +* Local function prototypes ('static') +******************************************************************************/ + +/******************************************************************************* +* Local variable definitions ('static') +******************************************************************************/ + +/******************************************************************************* +* Function implementation - global ('extern') and local ('static') +******************************************************************************/ + +/** +******************************************************************************* +** \brief 鍒濆鍖朌MAC閫氶亾 +** +** \param [in] enCh 鎸囧畾閫氶亾. +** \param [in] pstcCfg DMAC閫氶亾鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡. +** +** \retval Ok 鍒濆鍖栨垚鍔. +** \retval ErrorInvalidParameter pstcCfg鏄┖鎸囬拡. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_cfg_t* pstcCfg) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(NULL != pstcCfg); + ASSERT(IS_VALID_BLKSIZE(pstcCfg->u16BlockSize)); + ASSERT(IS_VALID_TRNCNT(pstcCfg->u16TransferCnt)); + ASSERT(IS_VALID_TRN_WIDTH(pstcCfg->enTransferWidth)); + ASSERT(IS_VALID_SRC_ADDR_MODE(pstcCfg->enSrcAddrMode)); + ASSERT(IS_VALID_DST_ADDR_MODE(pstcCfg->enDstAddrMode)); + ASSERT(IS_VALID_PRIO_MODE(pstcCfg->enPriority)); + ASSERT(IS_VALID_TRANSFER_MODE(pstcCfg->enTransferMode)); + + /* 妫鏌ラ氶亾鍊兼湁鏁堟у拰pstcCfg鏄惁绌烘寚閽 */ + if (NULL == pstcCfg) + { + return ErrorInvalidParameter; + } + + *(&M0P_DMAC->CONFB0+enCh) = 0; + *(&M0P_DMAC->CONFB0+enCh) = (uint32_t)pstcCfg->enMode | + (uint32_t)pstcCfg->enTransferWidth | + (uint32_t)pstcCfg->enSrcAddrMode | + (uint32_t)pstcCfg->enDstAddrMode | + (uint32_t)pstcCfg->enSrcAddrReloadCtl | + (uint32_t)pstcCfg->enDestAddrReloadCtl| + (uint32_t)pstcCfg->enSrcBcTcReloadCtl | + (uint32_t)pstcCfg->enTransferMode; + + /*棣栧厛鎶奣RI_SEL[6:0] BC[3:0] TC[15:0]杩欎簺浣嶆竻闆讹紝鐒跺悗鍐嶈祴鍊*/ + *(&M0P_DMAC->CONFA0+enCh) &= ((uint32_t)~(DMA_TRI_SEL_Msk | DMA_BC_SEL_Msk | DMA_TC_SEL_Msk)); + *(&M0P_DMAC->CONFA0+enCh) |= (uint32_t)(pstcCfg->u16TransferCnt - 1) | + ((uint32_t)(pstcCfg->u16BlockSize - 1)<<16)| + (uint32_t)(pstcCfg->enRequestNum<<22); + + M0P_DMAC->CONF |= (uint32_t)(pstcCfg->enPriority); + + *(&M0P_DMAC->SRCADR0+enCh) = (uint32_t)(pstcCfg->u32SrcAddress); + *(&M0P_DMAC->DSTADR0+enCh) = (uint32_t)(pstcCfg->u32DstAddress); + + return Ok; +} +/** +******************************************************************************* +** \brief DMA妯″潡浣胯兘鍑芥暟锛屼娇鑳芥墍鏈夐氶亾鐨勬搷浣滐紝姣忎釜閫氶亾鎸夌収鍚勮嚜璁剧疆宸ヤ綔. +** +** \param None +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Enable(void) +{ + M0P_DMAC->CONF |= DMA_ENABLE_Msk; +} + +/** +******************************************************************************* +** \brief DMA妯″潡鍔熻兘绂佹鍑芥暟锛屾墍鏈夐氶亾绂佹宸ヤ綔. +** +** \param None +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Disable(void) +{ + M0P_DMAC->CONF &= (~DMA_ENABLE_Msk); +} +/** +******************************************************************************* +** \brief 瑙﹀彂鎸囧畾DMA閫氶亾杞欢浼犺緭鍔熻兘. +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SwStart(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) |= DMA_SOFTWARE_START_Msk; +} + +/** +******************************************************************************* +** \brief 鍋滄鎸囧畾DMA閫氶亾杞欢浼犺緭鍔熻兘. +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SwStop(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) &= (~DMA_SOFTWARE_START_Msk); +} +/** +******************************************************************************* +** \brief 浣胯兘鎸囧畾dma閫氶亾鐨勶紙浼犺緭瀹屾垚锛変腑鏂. +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_EnableChannelIrq(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) |= DMA_FIS_IE_Msk; +} + +/** +******************************************************************************* +** \brief 绂佺敤鎸囧畾dma閫氶亾鐨勶紙浼犺緭瀹屾垚锛変腑鏂. +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_DisableChannelIrq(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_FIS_IE_Msk); +} +/** +******************************************************************************* +** \brief 浣胯兘鎸囧畾dma閫氶亾鐨勶紙浼犺緭閿欒锛変腑鏂.. +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_EnableChannelErrIrq(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) |= DMA_ERR_IE_Msk; +} + +/** +******************************************************************************* +** \brief 绂佺敤鎸囧畾dma閫氶亾鐨勶紙浼犺緭閿欒锛変腑鏂.. +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_DisableChannelErrIrq(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_ERR_IE_Msk); +} + +/** +******************************************************************************* +** \brief 浣胯兘鎸囧畾dma閫氶亾 +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_EnableChannel(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) |= DMA_CH_ENABLE_Msk; +} + +/** +******************************************************************************* +** \brief 绂佺敤鎸囧畾dma閫氶亾 +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_DisableChannel(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) &= (~DMA_CH_ENABLE_Msk); +} + +/** +******************************************************************************* +** \brief 璁惧畾鎸囧畾閫氶亾鐨勫潡(Block)灏哄 +** +** \param [杈撳叆] enCh 鎸囧畾閫氶亾 +** \param [杈撳叆] u16BlkSize 鍧(Block)灏哄. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SetBlockSize(en_dma_channel_t enCh, uint16_t u16BlkSize) +{ + volatile uint32_t *pReg = (&M0P_DMAC->CONFA0+enCh); + + *pReg = ((*pReg) & ((uint32_t)~DMA_BC_SEL_Msk)) | ((((uint32_t)u16BlkSize-1)&0x0f)<CONFA0+enCh); + + *pReg = ((*pReg)&((uint32_t)~DMA_TC_SEL_Msk))|(((uint32_t)(u16TrnCnt-1)<CONFB0+enCh) |= DMA_TRANSFER_RELOAD_Msk; +} + +/** +******************************************************************************* +** \brief 绂佹鎸囧畾閫氶亾杩炵画浼犺緭锛屽嵆DMAC鍦ㄤ紶杈撳畬鎴愭椂娓呴櫎. +** +** \param [杈撳叆] enCh 鎸囧畾閫氶亾. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_DisableContinusTranfer(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_TRANSFER_RELOAD_Msk); +} +/** +******************************************************************************* +** \brief 鏆傚仠鎵鏈塪ma閫氶亾. +** +** \param None +** +** \retval None. +** +** \note None +** +******************************************************************************/ +void Dma_HaltTranfer(void) +{ + M0P_DMAC->CONF_f.HALT = 0x1; +} +/** +******************************************************************************* +** \brief 鎭㈠锛堜箣鍓嶆殏鍋滅殑锛夋墍鏈塪ma閫氶亾. +** +** \param None +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_RecoverTranfer(void) +{ + M0P_DMAC->CONF_f.HALT = 0x0; +} +/** +******************************************************************************* +** \brief 鏆傚仠鎸囧畾dma閫氶亾. +** +** \param [杈撳叆] enCh 鎸囧畾閫氶亾. +** +** \retval void +** +** \note None +** +******************************************************************************/ +void Dma_PauseChannelTranfer(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) |= DMA_CH_PAUSE_Msk; +} +/** +******************************************************************************* +** \brief 鎭㈠锛堜箣鍓嶆殏瀹氱殑锛夋寚瀹歞ma閫氶亾. +** +** \param [杈撳叆] enCh 鎸囧畾閫氶亾. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_RecoverChannelTranfer(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) &= (~DMA_CH_PAUSE_Msk); +} +/** +******************************************************************************* +** \brief 璁惧畾鎸囧畾閫氶亾浼犺緭鏁版嵁瀹藉害. +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** \param [杈撳叆] enWidth 鎸囧畾鏁版嵁瀹藉害. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SetTransferWidth(en_dma_channel_t enCh, en_dma_transfer_width_t enWidth) +{ + volatile uint32_t *pReg = (&M0P_DMAC->CONFA0+enCh); + + *pReg = ((*pReg)&((uint32_t)~DMA_TRANSFER_WIDTH_Msk))|((uint32_t)enWidth); +} +/** +******************************************************************************* +** \brief 璁惧畾dma閫氶亾浼樺厛绾. +** +** \param [杈撳叆] enPrio 閫氶亾浼樺厛绾ц瀹氬弬鏁. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SetChPriority(en_dma_priority_t enPrio) +{ + M0P_DMAC->CONF = ((M0P_DMAC->CONF)&((uint32_t)~DMA_PRIORITY_Msk))|((uint32_t)enPrio); +} +/** +******************************************************************************* +** \brief 鑾峰彇鎸囧畾DMA閫氶亾鐨勭姸鎬. +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** +** \retval en_dma_stat_t DMA浼犺緭褰撳墠鐘舵 +** +** \note None +** +******************************************************************************/ +en_dma_stat_t Dma_GetStat(en_dma_channel_t enCh) +{ + return (en_dma_stat_t)((*(&M0P_DMAC->CONFB0+enCh)&(DMA_STAT_Msk))>>DMA_STAT_Pos); +} +/** +******************************************************************************* +** \brief 娓呴櫎鎸囧畾DMA閫氶亾鐨勭姸鎬佸. +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_ClrStat(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_STAT_Msk); +} + + +/** +******************************************************************************* +** \brief 璁惧畾鎸囧畾閫氶亾婧愬湴鍧 +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** \param [杈撳叆] u32Address 浼犺緭婧愬湴鍧. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SetSourceAddress(en_dma_channel_t enCh, uint32_t u32Address) +{ + *(&M0P_DMAC->SRCADR0+enCh) = u32Address; +} + +/** +******************************************************************************* +** \brief 璁惧畾鎸囧畾閫氶亾鐩爣鍦板潃. +** +** \param [杈撳叆] enCh 鎸囧畾dma閫氶亾. +** \param [杈撳叆] u32Address 浼犺緭鐩爣鍦板潃. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SetDestinationAddress(en_dma_channel_t enCh, uint32_t u32Address) +{ + *(&M0P_DMAC->DSTADR0+enCh) = u32Address; +} + +//@} // DmacGroup + +/******************************************************************************* +* EOF (not truncated) +******************************************************************************/ diff --git a/driver/src/flash.c b/driver/src/flash.c new file mode 100644 index 0000000..22d436a --- /dev/null +++ b/driver/src/flash.c @@ -0,0 +1,696 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file flash.c + ** + ** Common API of flash. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "flash.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define FLASH_END_ADDR (0x0001FFFFu) +#define FLASH_BYPASS() M0P_FLASH->BYPASS = 0x5A5A;\ + M0P_FLASH->BYPASS = 0xA5A5; +#define FLASH_IE_TRUE (0x03) +#define FLASH_IE_FALSE (0x00) + +#define FLASH_TIMEOUT_INIT (0xFFFFFFu) +#define FLASH_TIMEOUT_PGM (0xFFFFFFu) +#define FLASH_TIMEOUT_ERASE (0xFFFFFFu) + +#define FLASH_LOCK_ALL (0u) +#define FLASH_UNLOCK_ALL (0xFFFFFFFFu) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief FLASH OP + ** + ** Flash 鎿嶄綔鎺у埗鏁版嵁绫诲瀷閲嶅畾涔 + ******************************************************************************/ +typedef enum en_flash_op +{ + Read = 0u, ///<璇婚厤缃 + Program = 1u, ///<缂栫▼閰嶇疆鍊 + SectorErase = 2u, ///<鎵囧尯鎿﹂櫎閰嶇疆鍊 + ChipErase = 3u, ///<鍏ㄧ墖鎿﹂櫎閰嶇疆鍊 +} en_flash_op_t; + +/** + ****************************************************************************** + ** \brief FLASH 缂栫▼鏃堕棿鍙傛暟閰嶇疆 + ** + ** FLASH缂栫▼鏃堕棿鍙傛暟閰嶇疆鏁扮粍瀹氫箟 (4MHz) + ******************************************************************************/ +const uint32_t pu32PcgTimer4M[] = { + 0x20u, //Tnvs + 0x17u, //Tpgs + 0x1Bu, //Tprog + 0x4650u, //Tserase + 0x222E0u, //Tmerase + 0x18u, //Tprcv + 0xF0u, //Tsrcv + 0x3E8u //Tmrcv + }; +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Flash涓柇鏍囧織鑾峰彇 + ** + ** + ** \param [in] enFlashIntType Flash涓柇绫诲瀷 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Flash_GetIntFlag(en_flash_int_type_t enFlashIntType) +{ + boolean_t bRetVal = FALSE; + + if(M0P_FLASH->IFR & enFlashIntType) + { + bRetVal = TRUE; + } + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Flash涓柇鏍囧織娓呴櫎 + ** + ** + ** \param [in] enFlashIntType Flash涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_ClearIntFlag(en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + M0P_FLASH->ICLR &= ~(uint32_t)enFlashIntType; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Flash涓柇浣胯兘 + ** + ** + ** \param [in] enFlashIntType Flash涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_EnableIrq (en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE |= enFlashIntType; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Flash涓柇绂佹 + ** + ** + ** \param [in] enFlashIntType Flash涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_DisableIrq(en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE &= ~(uint32_t)enFlashIntType; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief FLASH 鍒濆鍖栧嚱鏁扳斺斾腑鏂湇鍔＄▼搴忋佺紪绋嬫椂闂撮厤缃強浣庡姛鑰楁ā寮 + ** + ** 璇ュ嚱鏁扮敤浜庨厤缃腑鏂湇鍔″嚱鏁般佷綆鍔熻楁ā寮忋佹牴鎹郴缁熸椂閽熼厤缃瓼LASH缂栫▼鏃堕棿鐩稿叧瀵勫瓨鍣. + ** + ** \param [in] u8FreqCfg FLASH缂栫▼鏃堕挓棰戠巼閰嶇疆(鏍规嵁HCLK鐨勯鐜囬夋嫨閰嶇疆鍊)锛 + ** 1 - 4MHz; + ** 2 - 8MHz; + ** 4 - 16MHz; + ** 6 - 24MHz; + ** 8 - 32MHz; + ** 12 - 48MHz; + ** other - 鏃犳晥鍊 + ** \param [in] bDpstbEn TRUE - 褰撶郴缁熻繘鍏eepSleep妯″紡锛孎LASH杩涘叆浣庡姛鑰楁ā寮; + ** FALSE - 褰撶郴缁熻繘鍏eepSleep妯″紡锛孎LASH涓嶈繘鍏ヤ綆鍔熻楁ā寮; + ** + ** \retval Ok 鎿嶄綔鎴愬姛. + ** \retval ErrorInvalidParameter 鍙傛暟鏃犳晥. + ** \retval ErrorUninitialized 鍒濆鍖栧け璐ャ + *****************************************************************************/ +en_result_t Flash_Init(uint8_t u8FreqCfg, boolean_t bDpstbEn) +{ + uint32_t u32Index = 0; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_INIT; + en_result_t enResult = Ok; + uint32_t u32PrgTimer[8] = {0}; + volatile uint32_t *pu32PrgTimerReg = (volatile uint32_t*)M0P_FLASH; + + if ((1 != u8FreqCfg) && (2 != u8FreqCfg) && + (4 != u8FreqCfg) && (6 != u8FreqCfg) && + (8 != u8FreqCfg) && (12 != u8FreqCfg)) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + M0P_FLASH->CR_f.DPSTB_EN = bDpstbEn; + + //flash鏃堕棿鍙傛暟閰嶇疆鍊艰绠 + for(u32Index=0; u32Index<8; u32Index++) + { + u32PrgTimer[u32Index] = u8FreqCfg * pu32PcgTimer4M[u32Index]; + } + + //flash鏃堕棿鍙傛暟瀵勫瓨鍣ㄩ厤缃 + for(u32Index=0; u32Index<8; u32Index++) + { + u32TimeOut = FLASH_TIMEOUT_INIT; + while(pu32PrgTimerReg[u32Index] != u32PrgTimer[u32Index]) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + pu32PrgTimerReg[u32Index] = u32PrgTimer[u32Index]; + } + else + { + return ErrorUninitialized; + } + } + } + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 瀛楄妭鍐 + ** + ** 鐢ㄤ簬鍚慒LASH鍐欏叆1瀛楄妭鏁版嵁. + ** + ** \param [in] u32Addr Flash鍦板潃 + ** \param [in] u8Data 1瀛楄妭鏁版嵁 + ** + ** \retval Ok 鍐欏叆鎴愬姛. + ** \retval ErrorInvalidParameter FLASH鍦板潃鏃犳晥 + ** \retval ErrorTimeout 鎿嶄綔瓒呮椂 + *****************************************************************************/ +en_result_t Flash_WriteByte(uint32_t u32Addr, uint8_t u8Data) +{ + en_result_t enResult = Ok; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_PGM; + + if (FLASH_END_ADDR < u32Addr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //set OP + u32TimeOut = FLASH_TIMEOUT_PGM; + while(Program != M0P_FLASH->CR_f.OP) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + } + else + { + return ErrorTimeout; + } + } + + //Flash 瑙ｉ攣 + Flash_UnlockAll(); + + //write data + *((volatile uint8_t*)u32Addr) = u8Data; + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 鍔犻攣 + Flash_LockAll(); + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 鍗婂瓧鍐 + ** + ** 鐢ㄤ簬鍚慒LASH鍐欏叆鍗婂瓧锛2瀛楄妭锛夋暟鎹. + ** + ** \param [in] u32Addr Flash鍦板潃 + ** \param [in] u16Data 鍗婂瓧锛2瀛楄妭锛夋暟鎹 + ** + ** \retval Ok 鍐欏叆鎴愬姛. + ** \retval ErrorInvalidParameter FLASH鍦板潃鏃犳晥 + ** \retval ErrorTimeout 鎿嶄綔瓒呮椂 + *****************************************************************************/ +en_result_t Flash_WriteHalfWord(uint32_t u32Addr, uint16_t u16Data) +{ + en_result_t enResult = Ok; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_PGM; + + if (FLASH_END_ADDR < u32Addr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //set OP + u32TimeOut = FLASH_TIMEOUT_PGM; + while(Program != M0P_FLASH->CR_f.OP) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + } + else + { + return ErrorTimeout; + } + } + + //Flash 瑙ｉ攣 + Flash_UnlockAll(); + + //write data + *((volatile uint16_t*)u32Addr) = u16Data; + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 鍔犻攣 + Flash_LockAll(); + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 瀛楀啓 + ** + ** 鐢ㄤ簬鍚慒LASH鍐欏叆1涓瓧鐨勬暟鎹. + ** + ** \param [in] u32Addr Flash鍦板潃 + ** \param [in] u32Data 1涓瓧鏁版嵁 + ** + ** \retval Ok 鍐欏叆鎴愬姛. + ** \retval ErrorInvalidParameter FLASH鍦板潃鏃犳晥 + ** \retval ErrorTimeout 鎿嶄綔瓒呮椂 + *****************************************************************************/ +en_result_t Flash_WriteWord(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enResult = Ok; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_PGM; + + if (FLASH_END_ADDR < u32Addr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 瑙ｉ攣 + Flash_UnlockAll(); + + //set OP + u32TimeOut = FLASH_TIMEOUT_PGM; + while(Program != M0P_FLASH->CR_f.OP) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + } + else + { + return ErrorTimeout; + } + } + + //write data + *((volatile uint32_t*)u32Addr) = u32Data; + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 鍔犻攣 + Flash_LockAll(); + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 鎵囧尯鎿﹂櫎 + ** + ** FLASH 鎵囧尯鎿﹂櫎. + ** + ** \param [in] u32SectorAddr 鎵鎿﹂櫎鎵囧尯鍐呯殑鍦板潃 + ** + ** \retval Ok 鎿﹂櫎鎴愬姛. + ** \retval ErrorInvalidParameter FLASH鍦板潃鏃犳晥 + ** \retval ErrorTimeout 鎿嶄綔瓒呮椂 + *****************************************************************************/ +en_result_t Flash_SectorErase(uint32_t u32SectorAddr) +{ + en_result_t enResult = Ok; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_ERASE; + + if (FLASH_END_ADDR < u32SectorAddr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //busy? + u32TimeOut = FLASH_TIMEOUT_ERASE; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 瑙ｉ攣 + Flash_UnlockAll(); + + //set OP + u32TimeOut = FLASH_TIMEOUT_ERASE; + while(SectorErase != M0P_FLASH->CR_f.OP) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = SectorErase; + } + else + { + return ErrorTimeout; + } + } + + //write data + *((volatile uint8_t*)u32SectorAddr) = 0; + + //busy? + u32TimeOut = FLASH_TIMEOUT_ERASE; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 鍔犻攣 + Flash_LockAll(); + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 鍏ㄧ墖鎿﹂櫎(璇ュ嚱鏁颁粎闄怰AM涓繍琛岋紒锛侊紒) + ** + ** FLASH 鍏ㄧ墖鎿﹂櫎. + ** + ** + ** \retval Ok 鎿﹂櫎鎴愬姛. + ** \retval ErrorTimeout 鎿嶄綔瓒呮椂 + ** + *****************************************************************************/ +en_result_t Flash_ChipErase(void) +{ + en_result_t enResult = Ok; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_ERASE; + + //busy? + u32TimeOut = FLASH_TIMEOUT_ERASE; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //set OP + u32TimeOut = FLASH_TIMEOUT_ERASE; + while(ChipErase != M0P_FLASH->CR_f.OP) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = ChipErase; + } + else + { + return ErrorTimeout; + } + } + + //Flash 瑙ｉ攣 + Flash_UnlockAll(); + + //write data + *((volatile uint8_t*)0) = 0; + + //busy? + u32TimeOut = FLASH_TIMEOUT_ERASE; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 鍔犻攣 + Flash_LockAll(); + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 缂栫▼淇濇姢鍔犻攣 + ** + ** + ** \retval Null + *****************************************************************************/ +void Flash_LockAll(void) +{ + FLASH_BYPASS(); + M0P_FLASH->SLOCK0 = FLASH_LOCK_ALL; + FLASH_BYPASS(); + M0P_FLASH->SLOCK1 = FLASH_LOCK_ALL; + +} + +/** + ***************************************************************************** + ** \brief FLASH 缂栫▼淇濇姢瑙ｉ攣 + ** + ** + ** \retval Null + *****************************************************************************/ +void Flash_UnlockAll(void) +{ + + FLASH_BYPASS(); + M0P_FLASH->SLOCK0 = FLASH_UNLOCK_ALL; + FLASH_BYPASS(); + M0P_FLASH->SLOCK1 = FLASH_UNLOCK_ALL; + +} + +/** + ***************************************************************************** + ** \brief FLASH 璇荤瓑寰呭懆鏈熻缃 + ** + ** \param [in] enWaitCycle 鎻掑叆FLASH璇荤瓑寰呭懆鏈熸暟鏋氫妇绫诲瀷 + ** + ** \retval Ok 瑙ｉ攣鎴愬姛 + ** \retval ErrorInvalidParameter 鍙傛暟閿欒 + *****************************************************************************/ +en_result_t Flash_WaitCycle(en_flash_waitcycle_t enWaitCycle) +{ + en_result_t enResult = Ok; + + FLASH_BYPASS(); + M0P_FLASH->CR_f.WAIT = enWaitCycle; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief FLASH LOCK 璁剧疆 + ** + ** \param [in] enLock @ref en_flash_lock_t + ** \param [in] u32LockValue 32bits锛屽搴攂it=0锛氬姞閿侊紝瀵瑰簲Sector涓嶅厑璁告摝鍐欙紱瀵瑰簲bit=1锛氳В閿併 + ** \note 鍔犺В閿佽寖鍥碨ector锛歔enLock*128 + i*4, enLock*128 + i*4+3] + ** (i琛ㄧずu32LockValue鐨刡it浣嶇疆锛0~31) + ** 渚嬪锛歟nLock = FlashLock1, u32LockValue = 0x00000002, + ** 鍒欏姞瑙ｉ攣鑼冨洿涓猴細[Sector128,Sector131] + ** \retval Ok 瑙ｉ攣鎴愬姛 + ** \retval ErrorInvalidParameter 鍙傛暟閿欒 + *****************************************************************************/ +en_result_t Flash_LockSet(en_flash_lock_t enLock, uint32_t u32LockValue) +{ + FLASH_BYPASS(); + *((&M0P_FLASH->SLOCK0) + enLock) = u32LockValue; + + return Ok; +} +//@} // FlashGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/gpio.c b/driver/src/gpio.c new file mode 100644 index 0000000..e639cc4 --- /dev/null +++ b/driver/src/gpio.c @@ -0,0 +1,582 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file Gpio.c + ** + ** GPIO driver API. + ** @link Driver Group Some description @endlink + ** + ** - 2018-04-22 1.0 Lux First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "gpio.h" + +/** + ******************************************************************************* + ** \addtogroup GpioGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_PIN(port,pin) ( ) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief GPIO 鍒濆鍖 + ** + ** \param [in] enPort IO Port鍙 + ** \param [in] enPin IO Pin鑴 + ** \param [in] pstcGpioCfg IO 閰嶇疆缁撴瀯浣撴寚閽 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ** 鍏朵粬鍊 璁剧疆澶辫触 + ******************************************************************************/ +en_result_t Gpio_Init(en_gpio_port_t enPort, en_gpio_pin_t enPin, stc_gpio_cfg_t *pstcGpioCfg) +{ + //閰嶇疆涓洪粯璁ゅ,GPIO鍔熻兘 + SetBit((uint32_t)&M0P_GPIO->PAADS + enPort, enPin, FALSE); + *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + enPort) + (((uint32_t)enPin)<<2))) = GpioAf0; + + //榛樿杈撳嚭鍊奸厤缃 + SetBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin, pstcGpioCfg->bOutputVal); + //鏂瑰悜閰嶇疆 + SetBit(((uint32_t)&M0P_GPIO->PADIR + enPort), enPin, (boolean_t)(pstcGpioCfg->enDir)); + //椹卞姩鑳藉姏閰嶇疆 + SetBit(((uint32_t)&M0P_GPIO->PADR + enPort), enPin, (boolean_t)(pstcGpioCfg->enDrv)); + //涓婃媺/涓嬫媺閰嶇疆 + SetBit(((uint32_t)&M0P_GPIO->PAPU + enPort), enPin, (boolean_t)(pstcGpioCfg->enPu)); + SetBit(((uint32_t)&M0P_GPIO->PAPD + enPort), enPin, (boolean_t)(pstcGpioCfg->enPd)); + //寮婕忚緭鍑哄姛鑳 + SetBit(((uint32_t)&M0P_GPIO->PAOD + enPort), enPin, (boolean_t)(pstcGpioCfg->enOD)); + + M0P_GPIO->CTRL2_f.AHB_SEL = pstcGpioCfg->enCtrlMode; + + return Ok; +} + + + +/** + ******************************************************************************* + ** \brief GPIO IO杈撳叆鍊艰幏鍙 + ** + ** \param [in] enPort IO Port鍙 + ** \param [in] enPin IO Pin鑴 + ** + ** \retval boolean_t IO鐢靛钩楂樹綆 + ******************************************************************************/ +boolean_t Gpio_GetInputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return GetBit(((uint32_t)&M0P_GPIO->PAIN + enPort), enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port杈撳叆鏁版嵁鑾峰彇 + ** + ** \param [in] enPort IO Port + ** + ** \retval boolean_t IO Port鏁版嵁 + ******************************************************************************/ +uint16_t Gpio_GetInputData(en_gpio_port_t enPort) +{ + return (uint16_t)(*((uint32_t *)((uint32_t)&M0P_GPIO->PAIN + enPort))); +} + +/** + ******************************************************************************* + ** \brief GPIO IO杈撳嚭鍊煎啓鍏 + ** + ** \param [in] enPort IO Port鍙 + ** \param [in] enPin IO Pin鑴 + ** \param [out] bVal 杈撳嚭鍊 + ** + ** \retval en_result_t Ok 璁剧疆鎴愬姛 + ** 鍏朵粬鍊 璁剧疆澶辫触 + ******************************************************************************/ +en_result_t Gpio_WriteOutputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin, boolean_t bVal) +{ + SetBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin, bVal); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO杈撳嚭鍊艰幏鍙 + ** + ** \param [in] enPort IO Port鍙 + ** \param [in] enPin IO Pin鑴 + ** + ** \retval boolean_t IO鐢靛钩楂樹綆 + ******************************************************************************/ +boolean_t Gpio_ReadOutputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return GetBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port璁剧疆锛屽彲鍚屾椂璁剧疆涓缁凱ort涓殑澶氫釜PIN + ** + ** \param [in] enPort IO Port + ** \param [in] u16ValMsk 璇ort鐨16涓狿IN鎺╃爜鍊,灏嗛渶瑕佽缃殑PIN瀵瑰簲鐨刡it鍐1鏈夋晥 + ** + ** \retval boolean_t IO Port鏁版嵁 + ******************************************************************************/ +en_result_t Gpio_SetPort(en_gpio_port_t enPort, uint16_t u16ValMsk) +{ + *((uint16_t*)(((uint32_t)&(M0P_GPIO->PABSET)) + enPort)) = u16ValMsk; + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO璁剧疆 + ** + ** \param [in] enPort IO Port鍙 + ** \param [in] enPin IO Pin鑴 + ** + ** \retval en_result_t Ok 璁剧疆鎴愬姛 + ** 鍏朵粬鍊 璁剧疆澶辫触 + ******************************************************************************/ +en_result_t Gpio_SetIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + SetBit(((uint32_t)&M0P_GPIO->PABSET + enPort), enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port娓呴浂锛屽彲鍚屾椂娓呴浂涓缁凱ort涓殑澶氫釜PIN + ** + ** \param [in] enPort IO Port + ** \param [in] u16ValMsk 璇ort鐨16涓狿IN鎺╃爜鍊,灏嗛渶瑕佹竻闆剁殑PIN瀵瑰簲鐨刡it鍐1鏈夋晥 + ** + ** \retval boolean_t IO Port鏁版嵁 + ******************************************************************************/ +en_result_t Gpio_ClrPort(en_gpio_port_t enPort, uint16_t u16ValMsk) +{ + *((uint16_t*)(((uint32_t)&(M0P_GPIO->PABCLR)) + enPort)) = u16ValMsk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO娓呴浂 + ** + ** \param [in] enPort IO Port鍙 + ** \param [in] enPin IO Pin鑴 + ** + ** \retval en_result_t Ok 璁剧疆鎴愬姛 + ** 鍏朵粬鍊 璁剧疆澶辫触 + ******************************************************************************/ +en_result_t Gpio_ClrIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + SetBit(((uint32_t)&M0P_GPIO->PABCLR + enPort), enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port缃綅/娓呴浂锛屽彲鍚屾椂缃綅/娓呴浂涓缁凱ort涓殑澶氫釜PIN + ** + ** \param [in] enPort IO Port + ** \param [in] u32ValMsk 楂16bits琛ㄧず璇ort鐨16涓狿IN缃綅鎺╃爜鍊, + ** 浣16bits琛ㄧず璇ort鐨16涓狿IN娓呴浂鎺╃爜鍊, + ** 灏嗛渶瑕佽缃殑PIN瀵瑰簲鐨刡it鍐1,鍚屼竴涓狿IN鐨勬帺鐮佸悓鏃朵负1,鍒欒PIN娓呴浂銆 + ** + ** \retval en_result_t Ok 璁剧疆鎴愬姛 + ** 鍏朵粬鍊 璁剧疆澶辫触 + ******************************************************************************/ +en_result_t Gpio_SetClrPort(en_gpio_port_t enPort, uint32_t u32ValMsk) +{ + *((uint32_t*)(((uint32_t)&(M0P_GPIO->PABSETCLR)) + enPort)) = u32ValMsk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO閰嶇疆涓烘ā鎷熷姛鑳芥ā寮 + ** + ** \param [in] enPort IO Port鍙 + ** \param [in] enPin IO Pin鑴 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ** 鍏朵粬鍊 璁剧疆澶辫触 + ******************************************************************************/ +en_result_t Gpio_SetAnalogMode(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + SetBit((uint32_t)&M0P_GPIO->PAADS + enPort, enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* +** \brief GPIO IO澶嶇敤鍔熻兘璁剧疆 + ** + ** \param [in] enPort IO Port鍙 + ** \param [in] enPin IO Pin鑴 + ** \param [in] enAf 澶嶇敤鍔熻兘鏋氫妇绫诲瀷閫夋嫨 + ** \retval Ok 璁剧疆鎴愬姛 + ** 鍏朵粬鍊 璁剧疆澶辫触 + ******************************************************************************/ +en_result_t Gpio_SetAfMode(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_af_t enAf) +{ + *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + enPort) + (((uint32_t)enPin)<<2))) = enAf; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO澶嶇敤鍔熻兘璁剧疆 + ** + ** \param [in] PinMux 澶嶇敤鍔熻兘瀹忓畾涔 + ** \retval Null + ** + ******************************************************************************/ +void Gpio_SetAfMode_Lite(GpioPinMux PinMux) +{ + *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + ((PinMux>>16u)&0xFFFFu)) + (((uint32_t)((PinMux>>8u)&0xFFu))<<2))) = (uint32_t)(PinMux&0x7u); +} + +/** + ******************************************************************************* + ** \brief GPIO IO涓柇浣胯兘 + ** + ** \param [in] enPort IO Port鍙 + ** \param [in] enPin IO Pin鑴 + ** \param [in] enType 涓柇浣胯兘绫诲瀷 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ******************************************************************************/ +en_result_t Gpio_EnableIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_irqtype_t enType) +{ + uint32_t u32PieAddr; + + u32PieAddr = ((uint32_t)((&M0P_GPIO->PAHIE) + enType)) + enPort; + + SetBit(u32PieAddr, enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO涓柇鍏抽棴 + ** + ** \param [in] enPort IO Port鍙 + ** \param [in] enPin IO Pin鑴 + ** \param [in] enType 涓柇浣胯兘绫诲瀷 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ******************************************************************************/ +en_result_t Gpio_DisableIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_irqtype_t enType) +{ + uint32_t u32PieAddr; + + u32PieAddr = ((uint32_t)((&M0P_GPIO->PAHIE) + enType)) + enPort; + + SetBit(u32PieAddr, enPin, FALSE); + + return Ok; +} + + +/** + ******************************************************************************* + ** \brief GPIO 鑾峰緱IO涓柇鐘舵 + ** + ** \param [in] u8Port IO Port鍙 + ** \param [in] u8Pin IO Pin鑴 + ** + ** \retval IO涓柇鐘舵佸紑鍏 + ******************************************************************************/ +boolean_t Gpio_GetIrqStatus(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return GetBit((uint32_t)&M0P_GPIO->PA_STAT + enPort, enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO 娓呴櫎IO涓柇鐘舵 + ** + ** \param [in] u8Port IO Port鍙 + ** \param [in] u8Pin IO Pin鑴 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ******************************************************************************/ +en_result_t Gpio_ClearIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + SetBit((uint32_t)&M0P_GPIO->PA_ICLR + enPort, enPin, FALSE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 绔彛杈呭姪鍔熻兘閰嶇疆鈥斺斾腑鏂ā寮忛厤缃 + ** + ** \param [in] enIrqMode 绔彛涓柇妯″紡锛堟繁搴︿紤鐪犳槸鍚﹀搷搴斾腑鏂級 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ******************************************************************************/ +en_result_t Gpio_SfIrqModeCfg(en_gpio_sf_irqmode_t enIrqMode) +{ + M0P_GPIO->CTRL0_f.IESEL = enIrqMode; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 绔彛杈呭姪鍔熻兘閰嶇疆鈥斺擨R杈撳嚭鏋佹ч厤缃 + ** + ** \param [in] enIrPolMode IR杈撳嚭鏋佹ч厤缃灇涓 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ******************************************************************************/ +en_result_t Gpio_SfIrPolCfg(en_gpio_sf_irpol_t enIrPolMode) +{ + M0P_GPIO->CTRL1_f.IR_POL = enIrPolMode; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 绔彛杈呭姪鍔熻兘閰嶇疆鈥斺擧CLK杈撳嚭閰嶇疆 + ** + ** \param [in] enGate HCLK杈撳嚭浣胯兘 + ** \param [in] enDiv 杈撳嚭鍒嗛鏋氫妇鍊 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ******************************************************************************/ +en_result_t Gpio_SfHClkOutputCfg(en_gpio_sf_hclkout_g_t enGate, en_gpio_sf_hclkout_div_t enDiv) +{ + M0P_GPIO->CTRL1_f.HCLK_EN = enGate; + M0P_GPIO->CTRL1_f.HCLK_SEL = enDiv; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 绔彛杈呭姪鍔熻兘閰嶇疆鈥斺擯CLK杈撳嚭閰嶇疆 + ** + ** \param [in] enGate PCLK杈撳嚭浣胯兘 + ** \param [in] enDiv 杈撳嚭鍒嗛鏋氫妇鍊 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ******************************************************************************/ +en_result_t Gpio_SfPClkOutputCfg(en_gpio_sf_pclkout_g_t enGate, en_gpio_sf_pclkout_div_t enDiv) +{ + M0P_GPIO->CTRL1_f.PCLK_EN = enGate; + M0P_GPIO->CTRL1_f.PCLK_SEL = enDiv; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 绔彛杈呭姪鍔熻兘閰嶇疆鈥斺斿閮ㄦ椂閽熻緭鍏ユ潵婧愰厤缃 + ** + ** \param [in] enExtClk 澶栭儴鏃堕挓淇″彿鏉ユ簮閫夋嫨鏋氫妇 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ******************************************************************************/ +en_result_t Gpio_SfExtClkCfg(en_gpio_sf_ssn_extclk_t enExtClk) +{ + M0P_GPIO->CTRL1_f.EXT_CLK_SEL = enExtClk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 绔彛杈呭姪鍔熻兘閰嶇疆鈥斺擲SN 閫氶亾淇″彿鏉ユ簮閰嶇疆 + ** + ** \param [in] enSpi SSN SPI閫氶亾閫夋嫨鏋氫妇 + ** \param [in] enSsn SSN 淇″彿鏉ユ簮閫夋嫨鏋氫妇 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ******************************************************************************/ +en_result_t Gpio_SfSsnCfg(en_gpio_sf_ssnspi_t enSpi, en_gpio_sf_ssn_extclk_t enSsn) +{ + //SPI0 + if(enSpi == GpioSpi0) + { + M0P_GPIO->CTRL1_f.SSN0_SEL = enSsn; + } + //SPI1 + if(enSpi == GpioSpi1) + { + M0P_GPIO->CTRL2_f.SSN1_SEL = enSsn; + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 绔彛杈呭姪鍔熻兘閰嶇疆鈥斺擳imer 闂ㄦ帶杈撳叆閰嶇疆 + ** + ** \param [in] enTimG Timer绫诲瀷閫夋嫨鏋氫妇 + ** \param [in] enSf Timer浜掕仈鍔熻兘閫夋嫨鏋氫妇 + ** + ** \retval Ok 璁剧疆鎴愬姛 + ******************************************************************************/ +en_result_t Gpio_SfTimGCfg(en_gpio_sf_tim_g_t enTimG, en_gpio_sf_t enSf) +{ + if(enTimG&0x20u) + { + enTimG &= ~0x20u; + M0P_GPIO->PCAS &= (uint32_t)(~(0x07U<PCAS |= (uint32_t)(enSf<TIMGS &= (uint32_t)(~(0x07U<TIMGS |= (uint32_t)(enSf<PCAS &= (uint32_t)(~(0x07U<PCAS |= (uint32_t)(enSf<TIMES &= (uint32_t)(~(0x07U<TIMES |= (uint32_t)(enSf<TIMCPS &= (uint32_t)(~(0x07u<TIMCPS |= (uint32_t)(enSf<PCAS &= (uint32_t)(~(0x07u<PCAS |= (uint32_t)(enSf<TM = u8Tm; + + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief I2C鍔熻兘璁剧疆鐩稿叧鍑芥暟 + ** + ** \param [in] enFunc鍔熻兘鍙傛暟 + ** + ** \retval enRet 鎴愬姛鎴栧け璐 + ** + ******************************************************************************/ +en_result_t I2C_SetFunc(M0P_I2C_TypeDef* I2Cx, en_i2c_func_t enFunc) +{ + en_result_t enRet = Error; + + SetBit((uint32_t)&I2Cx->CR, enFunc, TRUE); + + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief I2C鍔熻兘娓呴櫎鐩稿叧鍑芥暟 + ** + ** \param [in] enFunc鍔熻兘鍙傛暟 + ** + ** \retval enRet 鎴愬姛鎴栧け璐 + ** + ******************************************************************************/ + en_result_t I2C_ClearFunc(M0P_I2C_TypeDef* I2Cx, en_i2c_func_t enFunc) + { + en_result_t enRet = Error; + + SetBit((uint32_t)&I2Cx->CR, enFunc, FALSE); + + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief I2C鑾峰彇涓柇鏍囪鍑芥暟 + ** + ** \param 鏃 + ** + ** \retval bIrq涓柇鏍囪 + ** + ******************************************************************************/ +boolean_t I2C_GetIrq(M0P_I2C_TypeDef* I2Cx) +{ + if(I2Cx->CR&0x8) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + ****************************************************************************** + ** \brief I2C娓呴櫎涓柇鏍囪鍑芥暟 + ** + ** \param 鏃 + ** + ** \retval bIrq涓柇鏍囪 + ** + ******************************************************************************/ +en_result_t I2C_ClearIrq(M0P_I2C_TypeDef* I2Cx) +{ + en_result_t enRet = Error; + + I2Cx->CR &= ~0x8u; + + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief I2C鑾峰彇鐩稿叧鐘舵 + ** + ** \param 鏃 + ** + ** \retval I2C鐘舵 + ** + ******************************************************************************/ +uint8_t I2C_GetState(M0P_I2C_TypeDef* I2Cx) +{ + uint8_t u8State = 0; + + u8State = I2Cx->STAT; + + return u8State; +} + +/** + ****************************************************************************** + ** \brief 瀛楄妭鏁版嵁鍐欏嚱鏁 + ** + ** \param u8Data鍐欐暟鎹 + ** + ** \retval 鍐欐暟鎹槸鍚︽垚鍔 + ** + ******************************************************************************/ +en_result_t I2C_WriteByte(M0P_I2C_TypeDef* I2Cx, uint8_t u8Data) +{ + en_result_t enRet = Error; + + I2Cx->DATA = u8Data; + + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief 瀛楄妭鏁版嵁璇诲嚱鏁 + ** + ** \param 鏃 + ** + ** \retval 璇诲彇鏁版嵁 + ** + ******************************************************************************/ +uint8_t I2C_ReadByte(M0P_I2C_TypeDef* I2Cx) +{ + uint8_t u8Data = 0; + + u8Data = I2Cx->DATA; + + return u8Data; +} + +/** + ****************************************************************************** + ** \brief I2C妯″潡鍒濆鍖 + ** + ** \param pstcI2CCfg鍒濆鍖栭厤缃粨鏋勪綋 + ** + ** \retval 鍒濆鍖栨槸鍚︽垚鍔 + ** + ******************************************************************************/ +en_result_t I2C_Init(M0P_I2C_TypeDef* I2Cx, stc_i2c_cfg_t *pstcI2CCfg) +{ + en_result_t enRet = Error; + uint8_t u8Tm; + + if(M0P_I2C0 == I2Cx) + { + M0P_RESET->PERI_RESET0 &= ~(uint32_t)0x10u; + M0P_RESET->PERI_RESET0 |= (uint32_t)0x10u; + } + else + { + M0P_RESET->PERI_RESET0 &= ~(uint32_t)0x20u; + M0P_RESET->PERI_RESET0 |= (uint32_t)0x20u; + } + + I2Cx->CR = 0; + I2Cx->CR = pstcI2CCfg->enMode; + + if((pstcI2CCfg->u32Baud<<4) > pstcI2CCfg->u32Pclk) + { + return Error; + } + + if(I2cMasterMode == pstcI2CCfg->enMode) + { + I2Cx->TMRUN = TRUE; + ///< Fsck = Fpclk/8*(Tm+1) + u8Tm = ((pstcI2CCfg->u32Pclk / pstcI2CCfg->u32Baud) >> 3) - 1; + if(9 > u8Tm) + { + I2C_SetFunc(I2Cx,I2cHlm_En); + } + enRet = I2C_SetBaud(I2Cx, u8Tm); + } + else + { + I2Cx->TMRUN = FALSE; + pstcI2CCfg->u8SlaveAddr = (uint8_t)(((uint32_t)pstcI2CCfg->u8SlaveAddr<<1)|(pstcI2CCfg->bGc)); + I2Cx->ADDR = pstcI2CCfg->u8SlaveAddr; + } + + return enRet; +} +/** + ****************************************************************************** + ** \brief I2C妯″潡鎺ユ敹鎸囧畾闀垮害鍑芥暟 + ** + ** \param u8SlaveAddr浠庢満璁惧鍦板潃锛寀8Addr浠庢満鍐呭瓨鍦板潃锛宲u8Data璇绘暟鎹瓨鏀剧紦瀛橈紝u32Len璇绘暟鎹暱搴 + ** + ** \retval 璇绘暟鎹槸鍚︽垚鍔 + ** + ******************************************************************************/ + boolean_t I2C_MasterReadData(M0P_I2C_TypeDef* I2CX,uint8_t u8SlaveAddr,uint8_t u8Addr,uint8_t *pu8Data,uint32_t u32Len) +{ + boolean_t enRet = FALSE; + uint8_t u8i=0,u8State; + + I2C_SetFunc(I2CX,I2cStart_En);//寮濮 + + while(1) + { + while(0 == I2C_GetIrq(I2CX))//鑾峰彇涓柇鏍囪鍑芥暟 + {;} + u8State = I2C_GetState(I2CX);//鑾峰彇i2c鐩稿叧鐘舵 + switch(u8State) + { + case 0x08: ///< 涓昏澶囧悜鎬荤嚎宸插彂鍑轰簡涓涓捣濮嬫潯浠 + I2C_ClearFunc(I2CX,I2cStart_En); + I2C_WriteByte(I2CX,(u8SlaveAddr << 1)); + break; + case 0x18: ///< 涓昏澶囧悜鎬荤嚎宸插彂鍑轰簡涓涓粠璁惧鍦板潃锛堝啓鏂瑰悜锛夊苟涓旀帴鏀跺埌浠庤澶囩殑搴旂瓟 + I2C_WriteByte(I2CX,u8Addr); ///< 鍙戦佷粠鏈哄唴瀛樺湴鍧 + break; + case 0x28: ///< 宸插彂閫佹暟鎹紝鎺ユ敹鍒癆CK, 姝ゅ鏄凡鍙戦佷粠鏈哄唴瀛樺湴鍧u8Addr骞舵帴鏀跺埌ACK + I2C_SetFunc(I2CX,I2cStart_En); ///< 鍙戦侀噸澶嶈捣濮嬫潯浠 + break; + case 0x10: ///< 涓昏澶囧悜鎬荤嚎宸插彂鍑轰簡涓涓噸澶嶇殑璧峰鏉′欢 + I2C_ClearFunc(I2CX,I2cStart_En); + I2C_WriteByte(I2CX,(u8SlaveAddr << 1) | 0x01);///< 鍙戦丼LA+R锛屽紑濮嬩粠浠庢満璇诲彇鏁版嵁 + break; + case 0x40: ///< 宸插彂閫丼LA+R锛屽苟鎺ユ敹鍒癆CK + if(u32Len>1) + { + I2C_SetFunc(I2CX,I2cAck_En); ///< 浣胯兘涓绘満搴旂瓟鍔熻兘 + } + break; + case 0x50: ///< 宸叉帴鏀舵暟鎹瓧鑺傦紝骞跺凡杩斿洖ACK淇″彿 + pu8Data[u8i++] = I2C_ReadByte(I2CX); + if(u8i==u32Len-1) + { + I2C_ClearFunc(I2CX,I2cAck_En); ///< 宸叉帴鏀跺埌鍊掓暟绗簩涓瓧鑺傦紝鍏抽棴ACK搴旂瓟鍔熻兘 + } + break; + case 0x58: ///< 宸叉帴鏀跺埌鏈鍚庝竴涓暟鎹紝NACK宸茶繑鍥 + pu8Data[u8i++] = I2C_ReadByte(I2CX); + I2C_SetFunc(I2CX,I2cStop_En); ///< 鍙戦佸仠姝㈡潯浠 + break; + case 0x38: ///< 鍦ㄥ彂閫佸湴鍧鎴栨暟鎹椂锛屼徊瑁佷涪澶 + I2C_SetFunc(I2CX,I2cStart_En); ///< 褰撴荤嚎绌洪棽鏃跺彂璧疯捣濮嬫潯浠 + break; + case 0x48: ///< 鍙戦丼LA+R鍚庯紝鏀跺埌涓涓狽ACK + I2C_SetFunc(I2CX,I2cStop_En); ///< 鍙戦佸仠姝㈡潯浠 + I2C_SetFunc(I2CX,I2cStart_En); ///< 鍙戦佽捣濮嬫潯浠 + break; + default: + I2C_SetFunc(I2CX,I2cStart_En); ///< 鍏朵粬閿欒鐘舵侊紝閲嶆柊鍙戦佽捣濮嬫潯浠 + break; + } + I2C_ClearIrq(I2CX); ///< 娓呴櫎涓柇鐘舵佹爣蹇椾綅 + if(u8i==u32Len) ///< 鏁版嵁鍏ㄩ儴璇诲彇瀹屾垚锛岃烦鍑簑hile寰幆 + { + break; + } + } + enRet = TRUE; + return enRet; +} +/** + ****************************************************************************** + ** \brief I2C妯″潡涓绘満鍙戦佹寚瀹氶暱搴﹀嚱鏁 + ** + ** \param u8SlaveAddr浠庢満璁惧鍦板潃锛寀8Addr浠庢満鍐呭瓨鍦板潃锛宲u8Data鍐欐暟鎹紝u32Len鍐欐暟鎹暱搴 + ** + ** \retval 鍐欐暟鎹槸鍚︽垚鍔 + ** + ******************************************************************************/ +boolean_t I2C_MasterWriteData(M0P_I2C_TypeDef* I2CX,uint8_t u8SlaveAddr,uint8_t u8Addr,uint8_t *pu8Data,uint32_t u32Len) +{ + boolean_t enRet = FALSE; + uint8_t u8i=0,u8State, u8Flag=FALSE; + I2C_SetFunc(I2CX,I2cStart_En); + while(1) + { + while(0 == I2C_GetIrq(I2CX)) + {;} + u8State = I2C_GetState(I2CX); + switch(u8State) + { + case 0x08: ///< 宸插彂閫佽捣濮嬫潯浠 + I2C_ClearFunc(I2CX,I2cStart_En); + I2C_WriteByte(I2CX,(u8SlaveAddr << 1)); ///< 浠庤澶囧湴鍧鍙戦 + break; + case 0x18: ///< 宸插彂閫丼LA+W锛屽苟鎺ユ敹鍒癆CK + I2C_WriteByte(I2CX,u8Addr); ///< 浠庤澶囧唴瀛樺湴鍧鍙戦 + break; + case 0x28: ///< 涓婁竴娆″彂閫佹暟鎹悗鎺ユ敹鍒癆CK + if (u8i < u32Len) + { + I2C_WriteByte(I2CX,pu8Data[u8i++]); ///< 缁х画鍙戦佹暟鎹 + }else + { + I2C_SetFunc(I2CX,I2cStop_En); ///< 鍑哄仠姝㈡潯浠 + u8Flag = TRUE; + } + break; + case 0x38: ///< 涓婁竴娆″湪SLA+璇绘垨鍐欐椂涓㈠け浠茶 + I2C_SetFunc(I2CX,I2cStart_En); ///< 褰揑2C鎬荤嚎绌洪棽鏃跺彂閫佽捣濮嬫潯浠 + break; + case 0x30: ///< 宸插彂閫両2Cx_DATA涓殑鏁版嵁锛屾敹鍒癗ACK锛屽皢浼犺緭涓涓猄TOP鏉′欢 + I2C_SetFunc(I2CX,I2cStop_En); ///< 鍙戦佸仠姝㈡潯浠 + break; + default: + break; + } + + I2C_ClearIrq(I2CX); ///< 娓呴櫎涓柇鐘舵佹爣蹇椾綅 + + if(u8Flag == TRUE) ///< 鏁版嵁鍙戦佸畬鎴 + { + break; + } + } + enRet = TRUE; + return enRet; +} +//@} // I2cGroup diff --git a/driver/src/lcd.c b/driver/src/lcd.c new file mode 100644 index 0000000..dfbab6e --- /dev/null +++ b/driver/src/lcd.c @@ -0,0 +1,289 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lcd.c + ** + ** lcd driver API. + ** + ** - 2019-04-02 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "lcd.h" + + +/** + ****************************************************************************** + ** \addtogroup AdcGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** +****************************************************************************** + ** \brief 鑾峰彇LCD涓柇鏍囧織浣岻NTF + ** + ** @param 鏃 + ** \retval 鏃 + ** +******************************************************************************/ +boolean_t Lcd_GetItStatus(void) +{ + return (((M0P_LCD->CR1)>>11)&0x01)? TRUE : FALSE; +} + +/** +****************************************************************************** + ** \brief 娓呴櫎涓柇鏍囧織浣岻NTF + ** + ** @param 鏃 + ** \retval 鏃 + ** +******************************************************************************/ +void Lcd_ClearItPendingBit(void) +{ + SetBit((uint32_t)(&(M0P_LCD->INTCLR)), 10, 0); +} + +/** +****************************************************************************** + ** \brief 鏍规嵁LCD鏄剧ず妯″紡鑾峰彇绔彛閰嶇疆 + ** + ** \param pstcSegComPara锛氭樉绀烘柟寮忥紝 stcSegCom鑾峰彇绔彛鍙傛暟 + ** + ** \retval enRet 鎴愬姛鎴栧け璐 + ** +******************************************************************************/ +en_result_t Lcd_GetSegCom(stc_lcd_segcompara_t *pstcSegComPara,stc_lcd_segcom_t *pstcSegCom) +{ + en_result_t enRet = Error; + pstcSegCom->stc_seg32_51_com0_8_t.seg32_51_com0_8 = 0xffffffffu; + pstcSegCom->u32Seg0_31 = 0xffffffffu; + if(pstcSegComPara->u8MaxSeg>51) + { + return ErrorInvalidParameter; + } + switch(pstcSegComPara->LcdBiasSrc) + { + case LcdInResHighPower: + case LcdInResLowPower: + case LcdInResMidPower: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Mux = 1; + break; + case LcdExtCap: + case LcdExtRes: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Mux = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg32_35 = 0; + break; + default: + return ErrorInvalidParameter; + } + switch(pstcSegComPara->LcdDuty) + { + case LcdStatic: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~1u)&0x0fu; + break; + case LcdDuty2: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~3u)&0x0fu; + break; + case LcdDuty3: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~7u)&0x0fu; + break; + case LcdDuty4: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~15u)&0x0fu; + break; + case LcdDuty6: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg39Com4 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg38Com5 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg37Com6 = 1; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg36Com7 = 1; + break; + case LcdDuty8: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg39Com4 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg38Com5 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg37Com6 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg36Com7 = 0; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; +} + +/** +****************************************************************************** + ** \brief LCD COMSEG绔彛閰嶇疆锛屼娇鐢ㄨ鍑芥暟涔嬪墠闇瑕佸厛浣胯兘鐩稿簲鐨凷eg + ** + ** \param [in] pstcSegCom绔彛閰嶇疆缁撴瀯浣 + ** + ** \retval enRet 鎴愬姛鎴栧け璐 + ** +******************************************************************************/ +void Lcd_SetSegCom(stc_lcd_segcom_t *pstcSegCom) +{ + M0P_LCD->POEN0 = pstcSegCom->u32Seg0_31; + M0P_LCD->POEN1 = pstcSegCom->stc_seg32_51_com0_8_t.seg32_51_com0_8; +} + +/** +****************************************************************************** + ** \brief LCD妯″潡鍒濆鍖栧嚱鏁 + ** + ** \param stcLcdCfg閰嶇疆鍒濆鍖栫粨鏋勪綋 + ** + ** \retval 鏃 + ** +******************************************************************************/ +void Lcd_Init(stc_lcd_cfg_t *pstcLcdCfg) +{ + M0P_LCD->CR0_f.BSEL = pstcLcdCfg->LcdBiasSrc; + M0P_LCD->CR0_f.DUTY = pstcLcdCfg->LcdDuty; + M0P_LCD->CR0_f.BIAS = pstcLcdCfg->LcdBias; + M0P_LCD->CR0_f.CPCLK = pstcLcdCfg->LcdCpClk; + M0P_LCD->CR0_f.LCDCLK = pstcLcdCfg->LcdScanClk; + M0P_LCD->CR1_f.MODE = pstcLcdCfg->LcdMode; + M0P_LCD->CR1_f.CLKSRC = pstcLcdCfg->LcdClkSrc; + M0P_LCD->CR0_f.EN = pstcLcdCfg->LcdEn; +} + +/** +****************************************************************************** + ** \brief 娑叉櫠鍏ㄦ樉 + ** + ** \param 鏃 + ** + ** \retval 鏃 + ** +******************************************************************************/ +void Lcd_FullDisp(void) +{ + uint8_t tmp; + volatile uint32_t *ram = NULL; + ram = &M0P_LCD->RAM0; + for(tmp=0;tmp<16;tmp++) + { + *ram = 0xffffffffu; + ram++; + } +} + +/** +****************************************************************************** + ** \brief 娓呭睆 + ** + ** \param 鏃 + ** + ** \retval 鏃 + ** +******************************************************************************/ +void Lcd_ClearDisp(void) +{ + uint8_t tmp; + volatile uint32_t *ram = NULL; + ram = &M0P_LCD->RAM0; + for(tmp=0;tmp<16;tmp++) + { + *ram = 0; + ram++; + } +} + +/** + ****************************************************************************** + ** \brief LCD RAM 0-f瀵勫瓨鍣ㄨ缃嚱鏁 + ** + ** \param u8Row RAM鍦板潃绱㈠紩锛岃寖鍥达細0-15锛寀8Data鍐欏叆瀵勫瓨鍣ㄦ暟鍊 + ** + ** \retval enRet 鎴愬姛鎴栧け璐 + ** + ******************************************************************************/ +en_result_t Lcd_WriteRam(uint8_t u8Row,uint32_t u32Data) +{ + en_result_t enRet = Error; + volatile uint32_t *ram = NULL; + ram = (volatile uint32_t*)&M0P_LCD->RAM0; + + if (u8Row > 15) + { + enRet = ErrorInvalidParameter; + return enRet; + } + + ram += u8Row; + *ram = u32Data; + enRet = Ok; + return enRet; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/src/lpm.c b/driver/src/lpm.c new file mode 100644 index 0000000..93bcf7a --- /dev/null +++ b/driver/src/lpm.c @@ -0,0 +1,122 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file lpm.c + ** + ** Common API of lpm. + ** @link LpmGroup Some description @endlink + ** + ** - 2017-06-06 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "lpm.h" +/** + ******************************************************************************* + ** \addtogroup LpmGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief 杩涘叆娣卞害鐫＄湢妯″紡 + ** + ** \input bOnExit - TRUE:褰撻鍑哄紓甯稿鐞嗗悗锛岃嚜鍔ㄥ啀娆¤繘鍏ヤ紤鐪狅紱 + ** FALSE锛氬敜閱掑悗涓嶅啀鑷姩杩涘叆浼戠湢 + ** + ** \retval NULL + *****************************************************************************/ +void Lpm_GotoDeepSleep(boolean_t bOnExit) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SCB->SCR |= 1u<SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + SCB->SCR |= 1u<CR)), 10, NewStatus); +} + +/** +****************************************************************************** + ** \brief 瀹氭椂鍣↙PTIMx鐨勫惎鍔/鍋滄鎺у埗 + ** @param Lptimx : LPTIM0 鎴朙PTIM1 + ** @param NewStatus : TRUE 鎴 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Lptim_Cmd(M0P_LPTIMER_TypeDef* Lptimx, boolean_t NewStatus) +{ + SetBit((uint32_t)(&(Lptimx->CR)), 0, NewStatus); +} + +/** +****************************************************************************** + ** \brief 瀹氭椂鍣↙PTIMx鐨勪腑鏂爣蹇椾綅鑾峰彇 + ** @param Lptimx : LPTIM0 鎴朙PTIM1 + ** \retval TRUE 鎴 FALSE + ** +******************************************************************************/ +boolean_t Lptim_GetItStatus(M0P_LPTIMER_TypeDef* Lptimx) +{ + return GetBit((uint32_t)(&(Lptimx->IFR)), 0); +} + +/** +****************************************************************************** + ** \brief 瀹氭椂鍣↙PTIMx鐨勪腑鏂爣蹇椾綅娓呴櫎 + ** @param Lptimx : LPTIM0 鎴朙PTIM1 + ** \retval 鏃 + ** +******************************************************************************/ +void Lptim_ClrItStatus(M0P_LPTIMER_TypeDef* Lptimx) +{ + SetBit((uint32_t)(&(Lptimx->ICLR)), 0, 0); +} + +/** +****************************************************************************** + ** \brief 瀹氭椂鍣↙PTIMx鐨勫垵濮嬪寲閰嶇疆 + ** @param Lptimx : LPTIM0 鎴朙PTIM1 + ** @param InitStruct : 鍒濆鍖朙PTIMx鐨勭粨鏋勪綋 + ** \retval en_result_t绫诲瀷鏁版嵁 + ** +******************************************************************************/ +en_result_t Lptim_Init(M0P_LPTIMER_TypeDef* Lptimx, stc_lptim_cfg_t* InitStruct) +{ + uint16_t u16TimeOut; + u16TimeOut = 1000; + Lptimx->CR_f.PRS = InitStruct->enPrs; + Lptimx->CR_f.TCK_SEL = InitStruct->enTcksel; + Lptimx->CR_f.GATE_P = InitStruct->enGatep; + Lptimx->CR_f.GATE = InitStruct->enGate; + Lptimx->CR_f.TOG_EN = InitStruct->enTogen; + Lptimx->CR_f.CT = InitStruct->enCt; + Lptimx->CR_f.MD = InitStruct->enMd; + while(u16TimeOut--) + { + if(Lptimx->CR_f.WT_FLAG) + { + break; + } + } + if(u16TimeOut == 0) + { + return ErrorTimeout; + } + Lptimx->ARR_f.ARR = InitStruct->u16Arr; + return Ok; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/lpuart.c b/driver/src/lpuart.c new file mode 100644 index 0000000..5e8828f --- /dev/null +++ b/driver/src/lpuart.c @@ -0,0 +1,409 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lpuart.c + ** + ** LPUART function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "lpuart.h" +/** + ****************************************************************************** + ** \addtogroup LPUartGroup + ******************************************************************************/ +//@{ +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief LPUART閫氫俊涓柇浣胯兘鍑芥暟璁剧疆 + ** + ** \param [in] LPUARTx閫氶亾鍙凤紝enIrqSel鍙戦乷r鎺ユ敹涓柇浣胯兘 + ** + ** \retval OK閰嶇疆鎴愬姛 + **\retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t LPUart_EnableIrq(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_irq_sel_t enIrqSel) +{ + + SetBit((uint32_t)(&(LPUARTx->SCON)), enIrqSel, TRUE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART閫氫俊涓柇绂佹鍑芥暟璁剧疆 + ** + ** \param [in] LPUARTx閫氶亾鍙凤紝enIrqSel鍙戦乷r鎺ユ敹涓柇绂佹 + ** + ** \retval OK閰嶇疆鎴愬姛 + **\retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t LPUart_DisableIrq(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_irq_sel_t enIrqSel) +{ + + SetBit((uint32_t)(&(LPUARTx->SCON)), enIrqSel, FALSE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief lpuart閫氫俊鏃堕挓婧愰夋嫨 + ** + ** \param [in] LPUARTx閫氶亾鍙凤紝enClk 鏃堕挓婧愰夐」 + ** + ** \retval Ok 璁剧疆鎴愬姛 + **\retval ErrorInvalidParameter璁剧疆澶辫触 + ******************************************************************************/ +en_result_t LPUart_SelSclk(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_sclksel_t enSclk) +{ + ASSERT(IS_VALID_CLK(enSclk)); + + LPUARTx->SCON_f.SCLKSEL = enSclk; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾澶氫富鏈烘ā寮忛厤缃 + ** + ** \param [in] LPUARTx閫氶亾鍙凤紝stcMultiCfg澶氫富鏈烘ā寮忕粨鏋 + ** + ** \retval OK閰嶇疆鎴愬姛 + **\retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t LPUart_SetMultiMode(M0P_LPUART_TypeDef* LPUARTx, stc_lpuart_multimode_t* pstcMultiCfg) +{ + + if(NULL != pstcMultiCfg) + { + LPUARTx->SCON_f.ADRDET = TRUE; + LPUARTx->SADDR = pstcMultiCfg->u8SlaveAddr; + LPUARTx->SADEN = pstcMultiCfg->u8SaddEn; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART鍗曠嚎鍗婂弻宸ユā寮忎娇鑳 + ** + ** \param [in] LPUARTx 閫氶亾鍙 + ** + ** \retval Null + ******************************************************************************/ +void LPUart_HdModeEnable(M0P_LPUART_TypeDef* LPUARTx) +{ + LPUARTx->SCON_f.HDSEL = TRUE; +} + + +/** + ****************************************************************************** + ** \brief LPUART鍗曠嚎鍗婂弻宸ユā寮忓叧闂 + ** + ** \param [in] LPUARTx 閫氶亾鍙 + ** + ** \retval Null + ******************************************************************************/ +void LPUart_HdModeDisable(M0P_LPUART_TypeDef* LPUARTx) +{ + LPUARTx->SCON_f.HDSEL = FALSE; +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾澶氭満妯″紡鍙戦佹暟鎹/鍦板潃甯ч厤缃甌B8 + ** + ** \param [in] LPUARTx 閫氶亾鍙 + ** \param [in] TRUE-TB8涓哄湴鍧甯ф爣蹇楋紱FALSE-TB8涓烘暟鎹抚鏍囧織锛 + ** + ** \retval Null + ******************************************************************************/ +void LPUart_SetTb8(M0P_LPUART_TypeDef* LPUARTx, boolean_t bTB8Value) +{ + LPUARTx->SCON_f.B8CONT = bTB8Value; + +} + +/** + ****************************************************************************** + ** \brief 鑾峰彇RB8鏁板 + ** + ** \param [in] LPUARTx 閫氶亾鍙 + ** + ** \retval RB8 + **\retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +boolean_t LPUart_GetRb8(M0P_LPUART_TypeDef* LPUARTx) +{ + return (LPUARTx->SBUF_f.DATA8); +} +/** + ****************************************************************************** + ** \brief LPUART閫氶亾澶氫富鏈烘ā寮忎粠鏈哄湴鍧閰嶇疆鍑芥暟 + ** + ** \param [in] LPUARTx 閫氶亾鍙凤紝addr鍦板潃 + ** + ** \retval OK閰嶇疆鎴愬姛 + **\retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t LPUart_SetSaddr(M0P_LPUART_TypeDef* LPUARTx,uint8_t u8Addr) +{ + LPUARTx->SADDR = u8Addr; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾鍙戦佹垨鎺ユ敹绛夊姛鑳戒娇鑳借缃 + ** + ** \param [in] u8Idx閫氶亾鍙凤紝enFunc鍔熻兘 + ** + ** \retval OK閰嶇疆鎴愬姛 + **\retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t LPUart_EnableFunc(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_func_t enFunc) +{ + SetBit((uint32_t)(&(LPUARTx->SCON)), enFunc, TRUE); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾鍙戦佹垨鎺ユ敹绛夊姛鑳界姝㈣缃 + ** + ** \param [in] u8Idx閫氶亾鍙凤紝enFunc鍔熻兘 + ** + ** \retval OK閰嶇疆鎴愬姛 + **\retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t LPUart_DisableFunc(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_func_t enFunc) +{ + SetBit((uint32_t)(&(LPUARTx->SCON)), enFunc, FALSE); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾閫氫俊鐘舵佽幏鍙 + ** + ** \param [in] u8Idx閫氶亾鍙 + ** + ** \retval 鐘舵佸 + ******************************************************************************/ +uint8_t LPUart_GetIsr(M0P_LPUART_TypeDef* LPUARTx) +{ + return (LPUARTx->ISR); +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾閫氫俊鐘舵佽幏鍙 + ** + ** \param [in] u8Idx閫氶亾鍙凤紝enStatus鑾峰彇鍝釜鐘舵 + ** + ** \retval 鐘舵佸 + **\retval ErrorInvalidParameter鑾峰彇澶辫触 + ******************************************************************************/ +boolean_t LPUart_GetStatus(M0P_LPUART_TypeDef* LPUARTx,en_lpuart_status_t enStatus) +{ + boolean_t bStatus = FALSE; + + ASSERT(IS_VALID_STATUS(enStatus)); + + bStatus = GetBit((uint32_t)(&(LPUARTx->ISR)), enStatus); + + return bStatus; +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾閫氫俊鐘舵佸叏閮ㄦ竻闄 + ** + ** \param [in] u8Idx閫氶亾鍙 + ** + ** \retval OK + ******************************************************************************/ +en_result_t LPUart_ClrIsr(M0P_LPUART_TypeDef* LPUARTx) +{ + LPUARTx->ICR = 0u; + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾閫氫俊鐘舵佹竻闄 + ** + ** \param [in] u8Idx閫氶亾鍙凤紝enStatus娓呴櫎鍝釜鐘舵 + ** + ** \retval 鐘舵佸 + **\retval ErrorInvalidParameter娓呴櫎澶辫触 + ******************************************************************************/ +en_result_t LPUart_ClrStatus(M0P_LPUART_TypeDef* LPUARTx,en_lpuart_status_t enStatus) +{ + ASSERT(IS_VALID_STATUS(enStatus)); + + SetBit((uint32_t)(&(LPUARTx->ICR)), enStatus, FALSE); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾鍙戦佹暟鎹嚱鏁,鏌ヨ鏂瑰紡璋冪敤姝ゅ嚱鏁帮紝涓柇鏂瑰紡鍙戦佷笉閫傜敤 + ** + ** \param [in] u8Idx閫氶亾鍙凤紝Data鍙戦佹暟鎹 + ** + ** \retval Ok鍙戦佹垚鍔 + **\retval ErrorInvalidParameter鍙戦佸け璐 + ******************************************************************************/ +en_result_t LPUart_SendData(M0P_LPUART_TypeDef* LPUARTx, uint8_t u8Data) +{ + while(FALSE == LPUart_GetStatus(LPUARTx,LPUartTxe)) + {} + LPUARTx->SBUF_f.DATA = u8Data; + while(FALSE == LPUart_GetStatus(LPUARTx,LPUartTC)) + {} + LPUart_ClrStatus(LPUARTx,LPUartTC); + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾鍙戦佹暟鎹嚱鏁,涓柇鏂瑰紡璋冪敤姝ゅ嚱鏁 + ** + ** \param [in] u8Idx閫氶亾鍙凤紝Data鍙戦佹暟鎹 + ** + ** \retval Ok鍙戦佹垚鍔 + **\retval ErrorInvalidParameter鍙戦佸け璐 + ******************************************************************************/ +en_result_t LPUart_SendDataIt(M0P_LPUART_TypeDef* LPUARTx, uint8_t u8Data) +{ + LPUARTx->SBUF_f.DATA = u8Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾鎺ユ敹鏁版嵁鍑芥暟 + ** + ** \param [in] u8Idx閫氶亾鍙 + ** + ** \retval 鎺ユ敹鏁版嵁 + **\retval ErrorInvalidParameter鎺ユ敹澶辫触 + ******************************************************************************/ +uint8_t LPUart_ReceiveData(M0P_LPUART_TypeDef* LPUARTx) +{ + return (LPUARTx->SBUF_f.DATA); +} + +/** + ****************************************************************************** + ** \brief LPUART閫氶亾鍒濆鍖栧嚱鏁 + ** + ** \param [in] u8Idx閫氶亾鍙凤紝pstcCfg鍒濆鍖栫粨鏋勪綋 @ref stc_lpuart_cfg_t + ** + ** \retval OK閰嶇疆鎴愬姛 + **\retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t LPUart_Init(M0P_LPUART_TypeDef* LPUARTx,stc_lpuart_cfg_t* pstcCfg) +{ + en_result_t enRet = Error; + const uint32_t u32Over[3] = {0x4, 0x3, 0x2}; + uint16_t u16OverShift; + float32_t f32Scnt=0; + + if(NULL == pstcCfg) + { + return ErrorInvalidParameter; + } + + LPUARTx->SCON = 0; + + LPUARTx->SCON = (uint32_t)pstcCfg->enStopBit | + (uint32_t)pstcCfg->enMmdorCk | + (uint32_t)pstcCfg->stcBaud.enSclkDiv | + (uint32_t)pstcCfg->stcBaud.enSclkSel | + (uint32_t)pstcCfg->enRunMode; + + if((LPUartMskMode1 == pstcCfg->enRunMode) || (LPUartMskMode3 == pstcCfg->enRunMode)) + { + u16OverShift = u32Over[pstcCfg->stcBaud.enSclkDiv/LPUartMsk8Or16Div]; + f32Scnt = (float32_t)(pstcCfg->stcBaud.u32Sclk)/(float32_t)(pstcCfg->stcBaud.u32Baud<SCNT = (uint16_t)(float32_t)(f32Scnt + 0.5f); + LPUart_EnableFunc(LPUARTx,LPUartRenFunc); ///<浣胯兘鏀跺彂 + } + + + + enRet = Ok; + return enRet; +} +//@} // LPUartGroup diff --git a/driver/src/lvd.c b/driver/src/lvd.c new file mode 100644 index 0000000..c41a48a --- /dev/null +++ b/driver/src/lvd.c @@ -0,0 +1,216 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lvd.c + ** + ** Low Voltage Detect driver API. + ** @link Lvd Group Some description @endlink + ** + ** - 2017-06-28 Alex First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "lvd.h" + +/** + ****************************************************************************** + ** \addtogroup LvdGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define IS_VALID_INPUT(x) ( (x) <= LvdInputPB07 ) + +#define IS_VALID_THRESHOLD(x) ( (x) <= LvdTH3p3V ) + +#define IS_VALID_FILTER(x) ( (x) <= LvdFilter29ms ) + +#define IS_VALID_IRQTYPE(x) ( (x) <= LvdIrqFall ) + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +// static void LvdEnableNvic(void); +// static void LvdDisableNvic(void); +// static en_result_t LvdEnable(en_lvd_type_t enType, boolean_t bFlag); + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ +/** + * \brief + * 浣胯兘LVD涓柇 + * + * \param [in] enType LVD涓柇绫诲瀷 + * + * \retval en_result_t Ok: 璁剧疆鎴愬姛 + * \retval en_result_t ErrorInvalidParameter: 鏃犳晥绫诲瀷 + */ +void Lvd_EnableIrq(void) +{ + M0P_LVD->CR_f.IE = TRUE; +} + +/** + * \brief + * 闄よ兘LVD涓柇 + * + * \param 鏃 + * + * \retval 鏃 + */ +void Lvd_DisableIrq(void) +{ + M0P_LVD->CR_f.IE = FALSE; +} + +/** + * \brief + * LVD鍒濆鍖 + * + * \param [in] pstcCfg LVD閰嶇疆鎸囬拡 + * + * \retval 鏃 + */ +void Lvd_Init(stc_lvd_cfg_t *pstcCfg) +{ + M0P_LVD->CR = 0; + + M0P_LVD->CR = (uint32_t)pstcCfg->enAct | + (uint32_t)pstcCfg->enFilter | + (uint32_t)pstcCfg->enFilterTime | + (uint32_t)pstcCfg->enInputSrc | + (uint32_t)pstcCfg->enIrqType | + (uint32_t)pstcCfg->enThreshold; +} + +/** + * \brief + * 浣胯兘LVD + * + * \param 鏃 + * + * \retval 鏃 + * + */ +void Lvd_Enable(void) +{ + M0P_LVD->CR_f.LVDEN = 1u; +} + +/** + * \brief + * 闄よ兘LVD + * + * \param 鏃 + * + * \retval 鏃 + */ +void Lvd_Disable(void) +{ + M0P_LVD->CR_f.LVDEN = 0u; +} + +/** + * \brief + * 鑾峰彇LVD涓柇鏍囧織 + * + * \param 鏃 + * + * \retval boolean_t 涓柇鏍囧織 + */ +boolean_t Lvd_GetIrqStat(void) +{ + return M0P_LVD->IFR_f.INTF; + +} + +/** + * \brief + * 娓呴櫎LVD涓柇鏍囧織 + * + * \param 鏃 + * + * \retval 鏃 + */ +void Lvd_ClearIrq(void) +{ + M0P_LVD->IFR_f.INTF = 0u; +} + +/** + * \brief + * 鑾峰彇Filter缁撴灉 + * + * \param 鏃 + * + * \retval boolean_t Fliter缁撴灉 + */ +boolean_t Lvd_GetFilterResult(void) +{ + return (boolean_t)M0P_LVD->IFR_f.FILTER; +} +//@} // LvdGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/src/opa.c b/driver/src/opa.c new file mode 100644 index 0000000..142db0a --- /dev/null +++ b/driver/src/opa.c @@ -0,0 +1,153 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file opa.c + ** + ** opa driver API. + ** @link opa Group Some description @endlink + ** + ** - 2019-04-11 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "opa.h" + +/** + ****************************************************************************** + ** \addtogroup OPAGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** +****************************************************************************** + ** \brief OPA 閫氶亾浣胯兘 + ** + ** \param NewStatus : TRUE FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Opa_Cmd(boolean_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_OPA->CR0)), 0, NewStatus); +} + +void Opa_CmdBuf(boolean_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_OPA->CR0)), 2, NewStatus); +} + +/** +****************************************************************************** + ** \brief OPA闆剁偣鏍″噯閰嶇疆 + ** + ** \param InitZero : + ** \retval 鏃 + ** +******************************************************************************/ +void Opa_SetZero(stc_opa_zcfg_t* InitZero) +{ + M0P_OPA->CR0_f.AZEN = InitZero->bAzen; + M0P_OPA->CR1_f.CLK_SW_SET = InitZero->bClk_sw_set; + M0P_OPA->CR1_f.AZ_PULSE = InitZero->bAz_pulse; + M0P_OPA->CR1_f.TRIGGER = InitZero->bTrigger; + M0P_OPA->CR1_f.ADCTR_EN = InitZero->bAdctr_en; +} + +/** +****************************************************************************** + ** \brief 浣胯兘杈撳嚭OUTX + ** + ** \param onex : en_opa_oenx_t瀹氫箟鐨勫厓绱 + ** \retval 鏃 + ** +******************************************************************************/ +void Opa_CmdOnex(en_opa_oenx_t onex, boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_OPA->CR0)), onex, NewState); //浣胯兘OP3杈撳嚭X浣胯兘 +} + +/** +****************************************************************************** + ** \brief 閰嶇疆鏍￠浂鐩稿叧鐨勪綅 + ** + ** \param CtrlBit : en_opa_set0ctrl_t瀹氫箟鐨勫厓绱 + ** \param NewState: TRUE 鎴 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Opa_ZeroBitCtrl(en_opa_set0ctrl_t CtrlBit, boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_OPA->CR1)), CtrlBit, NewState); +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/src/pca.c b/driver/src/pca.c new file mode 100644 index 0000000..39de82d --- /dev/null +++ b/driver/src/pca.c @@ -0,0 +1,555 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file pca.c + ** + ** pca driver API. + ** @link pcnt Group Some description @endlink + ** + ** - 2019-04-09 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "pca.h" + +/** + ****************************************************************************** + ** \addtogroup PCNTGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/** +****************************************************************************** + ** \brief 鑾峰彇涓柇婧愮殑鏍囧織浣 + ** @param IT_Src : 涓柇婧愭爣蹇椾綅 + ** \retval FALSE 鎴朤RUE + ** +******************************************************************************/ +boolean_t Pca_GetItStatus(en_pca_ccficlr_t It_Src) +{ + return (((M0P_PCA->CCON)>>It_Src) & 1) > 0? TRUE : FALSE; +} + +/** +****************************************************************************** + ** \brief 娓呴櫎涓柇婧愮殑鏍囧織浣 + ** @param IT_Src : 涓柇婧愭爣蹇椾綅 + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_ClrItStatus(en_pca_ccficlr_t It_Src) +{ + M0P_PCA->ICLR &= ~(uint32_t)(1<CCON)), 6, NewStatus); +} + +/** +****************************************************************************** + ** \brief PCA 绌洪棽妯″紡IDLE涓嬶紝PCA鏄惁鍋滄宸ヤ綔璁剧疆 + ** @param NewStatus : TRUE 鎴 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_SetCidl(boolean_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_PCA->CMOD)), 7, NewStatus); +} + +/** +****************************************************************************** + ** \brief PCA 妯″潡4鐨勭湅闂ㄧ嫍浣胯兘鎺у埗 + ** @param NewStatus : TRUE 鎴 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_Set4Wdte(boolean_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_PCA->CMOD)), 6, NewStatus); +} + +/** +****************************************************************************** + ** \brief PCA 璁℃暟鍣ㄤ腑鏂帶鍒禤CA_CMOD涓瑿FIE锛屽搴旂殑鎺у埗涓柇浣峆CA_CCON涓殑CF涓嶱CA_ICLR涓殑CF + ** @param NewStatus : TRUE 鎴 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_ConfPcaIt(boolean_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_PCA->CMOD)), 0, NewStatus); +} + +/** +****************************************************************************** + ** \brief PCA 姣旇緝鎹曡幏涓柇浣胯兘鎺у埗 PCA_CCAPMx鐨凜CIE + ** @param Modulex : pca_module0~4 + ** @param NewStatus : TRUE 鎴 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_ConfModulexIt(en_pca_module_t Modulex, boolean_t NewStatus) +{ + switch(Modulex) + { + case PcaModule0: + SetBit((uint32_t)(&(M0P_PCA->CCAPM0)), 0, NewStatus); + break; + case PcaModule1: + SetBit((uint32_t)(&(M0P_PCA->CCAPM1)), 0, NewStatus); + break; + case PcaModule2: + SetBit((uint32_t)(&(M0P_PCA->CCAPM2)), 0, NewStatus); + break; + case PcaModule3: + SetBit((uint32_t)(&(M0P_PCA->CCAPM3)), 0, NewStatus); + break; + case PcaModule4: + SetBit((uint32_t)(&(M0P_PCA->CCAPM4)), 0, NewStatus); + break; + default: + break; + } +} + +/** +****************************************************************************** + ** \brief PCA 妯″潡0鐨勫垵濮嬪寲 + ** @param InitStruct : PCA鍒濆鍖栭厤缃殑缁撴瀯浣 + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_M0Init(stc_pcacfg_t* InitStruct) +{ + M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc; + M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl; + M0P_PCA->CCAPM0_f.ECOM = InitStruct->pca_ecom; + M0P_PCA->CCAPM0_f.CAPP = InitStruct->pca_capp; + M0P_PCA->CCAPM0_f.CAPN = InitStruct->pca_capn; + M0P_PCA->CCAPM0_f.MAT = InitStruct->pca_mat; + M0P_PCA->CCAPM0_f.TOG = InitStruct->pca_tog; + M0P_PCA->CCAPM0_f.PWM = InitStruct->pca_pwm; + M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm; + if(InitStruct->pca_pwm == PcaPwm8bitEnable) + { + M0P_PCA->CCAP0L_f.CCAP0 = InitStruct->pca_ccapl; + M0P_PCA->CCAP0H_f.CCAP0 = InitStruct->pca_ccaph; + } + else + { + M0P_PCA->CCAP0_f.CCAP0 = InitStruct->pca_ccap; + } + M0P_PCA->CARR_f.CARR = InitStruct->pca_carr; +} + +/** +****************************************************************************** + ** \brief PCA 妯″潡1鐨勫垵濮嬪寲 + ** @param InitStruct : PCA鍒濆鍖栭厤缃殑缁撴瀯浣 + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_M1Init(stc_pcacfg_t* InitStruct) +{ + M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc; + M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl; + M0P_PCA->CCAPM1_f.ECOM = InitStruct->pca_ecom; + M0P_PCA->CCAPM1_f.CAPP = InitStruct->pca_capp; + M0P_PCA->CCAPM1_f.CAPN = InitStruct->pca_capn; + M0P_PCA->CCAPM1_f.MAT = InitStruct->pca_mat; + M0P_PCA->CCAPM1_f.TOG = InitStruct->pca_tog; + M0P_PCA->CCAPM1_f.PWM = InitStruct->pca_pwm; + M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm; + if(InitStruct->pca_pwm == PcaPwm8bitEnable) + { + M0P_PCA->CCAP1L_f.CCAP1 = InitStruct->pca_ccapl; + M0P_PCA->CCAP1H_f.CCAP1 = InitStruct->pca_ccaph; + } + else + { + M0P_PCA->CCAP1_f.CCAP1 = InitStruct->pca_ccap; + } + M0P_PCA->CARR_f.CARR = InitStruct->pca_carr; +} + +/** +****************************************************************************** + ** \brief PCA 妯″潡2鐨勫垵濮嬪寲 + ** @param InitStruct : PCA鍒濆鍖栭厤缃殑缁撴瀯浣 + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_M2Init(stc_pcacfg_t* InitStruct) +{ + M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc; + M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl; + M0P_PCA->CCAPM2_f.ECOM = InitStruct->pca_ecom; + M0P_PCA->CCAPM2_f.CAPP = InitStruct->pca_capp; + M0P_PCA->CCAPM2_f.CAPN = InitStruct->pca_capn; + M0P_PCA->CCAPM2_f.MAT = InitStruct->pca_mat; + M0P_PCA->CCAPM2_f.TOG = InitStruct->pca_tog; + M0P_PCA->CCAPM2_f.PWM = InitStruct->pca_pwm; + M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm; + if(InitStruct->pca_pwm == PcaPwm8bitEnable) + { + M0P_PCA->CCAP2L_f.CCAP2 = InitStruct->pca_ccapl; + M0P_PCA->CCAP2H_f.CCAP2 = InitStruct->pca_ccaph; + } + else + { + M0P_PCA->CCAP2_f.CCAP2 = InitStruct->pca_ccap; + } + M0P_PCA->CARR_f.CARR = InitStruct->pca_carr; +} + +/** +****************************************************************************** + ** \brief PCA 妯″潡3鐨勫垵濮嬪寲 + ** @param InitStruct : PCA鍒濆鍖栭厤缃殑缁撴瀯浣 + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_M3Init(stc_pcacfg_t* InitStruct) +{ + M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc; + M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl; + M0P_PCA->CCAPM3_f.ECOM = InitStruct->pca_ecom; + M0P_PCA->CCAPM3_f.CAPP = InitStruct->pca_capp; + M0P_PCA->CCAPM3_f.CAPN = InitStruct->pca_capn; + M0P_PCA->CCAPM3_f.MAT = InitStruct->pca_mat; + M0P_PCA->CCAPM3_f.TOG = InitStruct->pca_tog; + M0P_PCA->CCAPM3_f.PWM = InitStruct->pca_pwm; + M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm; + if(InitStruct->pca_pwm == PcaPwm8bitEnable) + { + M0P_PCA->CCAP3L_f.CCAP3 = InitStruct->pca_ccapl; + M0P_PCA->CCAP3H_f.CCAP3 = InitStruct->pca_ccaph; + } + else + { + M0P_PCA->CCAP3_f.CCAP3 = InitStruct->pca_ccap; + } + M0P_PCA->CARR_f.CARR = InitStruct->pca_carr; +} + +/** +****************************************************************************** + ** \brief PCA 妯″潡4鐨勫垵濮嬪寲 + ** @param InitStruct : PCA鍒濆鍖栭厤缃殑缁撴瀯浣 + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_M4Init(stc_pcacfg_t* InitStruct) +{ + M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc; + M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl; + M0P_PCA->CCAPM4_f.ECOM = InitStruct->pca_ecom; + M0P_PCA->CCAPM4_f.CAPP = InitStruct->pca_capp; + M0P_PCA->CCAPM4_f.CAPN = InitStruct->pca_capn; + M0P_PCA->CCAPM4_f.MAT = InitStruct->pca_mat; + M0P_PCA->CCAPM4_f.TOG = InitStruct->pca_tog; + M0P_PCA->CCAPM4_f.PWM = InitStruct->pca_pwm; + M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm; + if(InitStruct->pca_pwm == PcaPwm8bitEnable) + { + M0P_PCA->CCAP4L_f.CCAP4 = InitStruct->pca_ccapl; + M0P_PCA->CCAP4H_f.CCAP4 = InitStruct->pca_ccaph; + } + else + { + M0P_PCA->CCAP4_f.CCAP4 = InitStruct->pca_ccap; + } + M0P_PCA->CARR_f.CARR = InitStruct->pca_carr; +} + +/** +****************************************************************************** + ** \brief PCA 璇诲彇CNT瀵勫瓨鍣ㄧ殑鏁板 + ** @param 鏃 + ** \retval CNT鐨勪綆鍗婂瓧鍊 + ** +******************************************************************************/ +uint16_t Pca_GetCnt(void) +{ + return (uint16_t)(M0P_PCA->CNT); +} + +/** +****************************************************************************** + ** \brief PCA 鍚慍NT瀵勫瓨鍣ㄥ啓鍏ユ暟鍊 + ** @param cnt : 鎵瑕佸啓鍏ョ殑鏁板 + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_SetCnt(uint16_t cnt) +{ + if(GetBit((uint32_t)(&(M0P_PCA->CCON)), 6)==TRUE) + { + Pca_StartPca(FALSE); + M0P_PCA->CNT_f.CNT = cnt; + Pca_StartPca(TRUE); + } + else + { + M0P_PCA->CNT_f.CNT = cnt; + } + +} + +/** +****************************************************************************** + ** \brief PCA 杩斿洖鎸囧畾閫氶亾姣旇緝楂橀熻緭鍑烘爣蹇楀瘎瀛樺櫒鐨勫 + ** @param Modulex : 閫氶亾鍙穢=0銆1銆2銆3銆4 + ** \retval TRUE 鎴 FALSE + ** +******************************************************************************/ +boolean_t Pca_GetOut(en_pca_module_t Modulex) +{ + return GetBit((uint32_t)(&(M0P_PCA->CCAPO)), Modulex); +} + +/** +****************************************************************************** + ** \brief PCA 璁剧疆姣旇緝鎹曡幏16浣嶅瘎瀛樺櫒CCAPx鏁板 + ** @param Modulex : 閫氶亾鍙穢=0銆1銆2銆3銆4 + ** @param Value: 鎵瑕佽缃殑鍊 + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_SetCcap(en_pca_module_t Modulex, uint16_t Value) +{ + switch(Modulex) + { + case 0: + M0P_PCA->CCAP0_f.CCAP0 = Value; + break; + case 1: + M0P_PCA->CCAP1_f.CCAP1 = Value; + break; + case 2: + M0P_PCA->CCAP2_f.CCAP2 = Value; + break; + case 3: + M0P_PCA->CCAP3_f.CCAP3 = Value; + break; + case 4: + M0P_PCA->CCAP4_f.CCAP4 = Value; + break; + default: + break; + } +} + +/** +****************************************************************************** + ** \brief PCA 璇诲彇姣旇緝鎹曡幏16浣嶅瘎瀛樺櫒CCAPx鏁板 + ** @param Modulex : 閫氶亾鍙穢=0銆1銆2銆3銆4 + ** \retval CCAPx鐨勫硷紝x=0銆1銆2銆3銆4 + ** +******************************************************************************/ +uint16_t Pca_GetCcap(en_pca_module_t Modulex) +{ + uint16_t tmp; + switch(Modulex) + { + case 0: + tmp = M0P_PCA->CCAP0_f.CCAP0; + break; + case 1: + tmp = M0P_PCA->CCAP1_f.CCAP1; + break; + case 2: + tmp = M0P_PCA->CCAP2_f.CCAP2; + break; + case 3: + tmp = M0P_PCA->CCAP3_f.CCAP3; + break; + case 4: + tmp = M0P_PCA->CCAP4_f.CCAP4; + break; + default: + break; + } + return tmp; +} + +/** +****************************************************************************** + ** \brief PCA 璁剧疆鑷姩閲嶈杞藉瘎瀛樺櫒鏁板 + ** @param 鏃 + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_SetCarr(uint16_t Value) +{ + M0P_PCA->CARR_f.CARR = Value; +} + +/** +****************************************************************************** + ** \brief PCA 鑾峰彇鑷姩閲嶈杞藉瘎瀛樺櫒鏁板 + ** @param 鏃 + ** \retval 鏃 + ** +******************************************************************************/ +uint16_t Pca_GetCarr(void) +{ + return M0P_PCA->CARR_f.CARR; +} + +/** +****************************************************************************** + ** \brief PCA 璁剧疆姣旇緝鎹曡幏瀵勫瓨鍣ㄧ殑楂8浣嶅拰浣8浣 + ** @param Modulex : 閫氶亾鍙穢=0銆1銆2銆3銆4 + ** @param ValueH : 瑕佸啓鍏ラ珮8浣嶇殑鏁板 + ** @param ValueL : 瑕佸啓鍏ヤ綆8浣嶇殑鏁板 + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_SetCcapHL(en_pca_module_t Modulex, uint8_t ValueH, uint8_t ValueL) +{ + switch(Modulex) + { + case 0: + M0P_PCA->CCAP0H_f.CCAP0 = ValueH; + M0P_PCA->CCAP0L_f.CCAP0 = ValueL; + break; + case 1: + M0P_PCA->CCAP1H_f.CCAP1 = ValueH; + M0P_PCA->CCAP1L_f.CCAP1 = ValueL; + break; + case 2: + M0P_PCA->CCAP2H_f.CCAP2 = ValueH; + M0P_PCA->CCAP2L_f.CCAP2 = ValueL; + break; + case 3: + M0P_PCA->CCAP3H_f.CCAP3 = ValueH; + M0P_PCA->CCAP3L_f.CCAP3 = ValueL; + break; + case 4: + M0P_PCA->CCAP4H_f.CCAP4 = ValueH; + M0P_PCA->CCAP4L_f.CCAP4 = ValueL; + break; + default: + break; + } +} + +/** +****************************************************************************** + ** \brief PCA 璇诲彇姣旇緝鎹曡幏瀵勫瓨鍣ㄧ殑楂8浣嶅拰浣8浣 + ** @param Modulex : 閫氶亾鍙穢=0銆1銆2銆3銆4 + ** @param ValueH : CCAPx楂8浣嶇殑鏁板 + ** @param ValueL : CCAPx浣8浣嶇殑鏁板 + ** \retval 鏃 + ** +******************************************************************************/ +void Pca_GetCcapHL(en_pca_module_t Modulex, uint8_t *ValueH, uint8_t *ValueL) +{ + switch(Modulex) + { + case 0: + *ValueH = M0P_PCA->CCAP0H_f.CCAP0; + *ValueL = M0P_PCA->CCAP0L_f.CCAP0; + break; + case 1: + *ValueH = M0P_PCA->CCAP1H_f.CCAP1; + *ValueL = M0P_PCA->CCAP1L_f.CCAP1; + break; + case 2: + *ValueH = M0P_PCA->CCAP2H_f.CCAP2; + *ValueL = M0P_PCA->CCAP2L_f.CCAP2; + break; + case 3: + *ValueH = M0P_PCA->CCAP3H_f.CCAP3; + *ValueL = M0P_PCA->CCAP3L_f.CCAP3; + break; + case 4: + *ValueH = M0P_PCA->CCAP4H_f.CCAP4; + *ValueL = M0P_PCA->CCAP4L_f.CCAP4; + break; + default: + break; + } +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + + + + + diff --git a/driver/src/pcnt.c b/driver/src/pcnt.c new file mode 100644 index 0000000..cdcf160 --- /dev/null +++ b/driver/src/pcnt.c @@ -0,0 +1,316 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file pcnt.c + ** + ** pcnt driver API. + ** @link pcnt Group Some description @endlink + ** + ** - 2019-04-08 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "pcnt.h" + +/** + ****************************************************************************** + ** \addtogroup PCNTGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + + +/** +****************************************************************************** + ** \brief PCNT鐨勫惎鍔ㄥ拰鍋滄鎺у埗 + ** @param NewState : Run_Enable 鎴栬 Run_Disable + ** @param NewState : FALSE鎴栬匱RUE + ** \retval 鏃 + ** +******************************************************************************/ +boolean_t Pcnt_Cmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_PCNT->RUN)), 0, NewState); + return GetBit((uint32_t)(&(M0P_PCNT->RUN)), 0); +} + + +/** +****************************************************************************** + ** \brief 灏咮UF涓殑鍊煎悓姝ュ埌CNT + ** @param value : 瑕佸悓姝ュ埌TOP鐨勬暟鍊 + ** \retval ok 鎴 ErrorTimeout + ** +******************************************************************************/ +en_result_t Pcnt_SetB2T(uint16_t value) +{ + uint16_t u16TimeOut; + + u16TimeOut = 1000; + M0P_PCNT->BUF = value; + M0P_PCNT->CMD_f.B2T = 1; + + while(u16TimeOut--) + { + if(M0P_PCNT->SR2_f.B2T == FALSE) + { + break; + } + } + if(u16TimeOut == 0) + { + return ErrorTimeout; + } + return Ok; +} + +/** +****************************************************************************** + ** \brief 灏咮UF涓殑鍊煎悓姝ュ埌CNT + ** @param value : 瑕佸悓姝ュ埌CNT鐨勬暟鍊 + ** \retval ok 鎴 ErrorTimeout + ** +******************************************************************************/ +en_result_t Pcnt_SetB2C(uint16_t value) +{ + uint16_t u16TimeOut; + u16TimeOut = 1000; + M0P_PCNT->BUF = value; + M0P_PCNT->CMD_f.B2C = 1; + + while(u16TimeOut--) + { + if(M0P_PCNT->SR2_f.B2C == FALSE) + { + break; + } + } + if(u16TimeOut == 0) + { + return ErrorTimeout; + } + return Ok; +} + +/** +****************************************************************************** + ** \brief 灏員OP涓殑鍊煎悓姝ュ埌CNT + ** @param value : 瑕佸悓姝ュ埌CNT鐨勬暟鍊 + ** \retval ok 鎴 ErrorTimeout + ** +******************************************************************************/ +en_result_t Pcnt_SetT2C(void) +{ + uint16_t u16TimeOut; + u16TimeOut = 1000; + M0P_PCNT->CMD_f.T2C = 1; + while(u16TimeOut--) + { + if(M0P_PCNT->SR2_f.T2C == FALSE) + { + break; + } + } + if(u16TimeOut == 0) + { + return ErrorTimeout; + } + return Ok; +} + + +/** +****************************************************************************** + ** \brief 璧嬪糂UF + ** @param value : 瑕佽祴鍊肩粰BUF鐨勬暟鍊 + ** \retval 鏃 + ** +******************************************************************************/ +void Pcnt_SetBuf(uint16_t value) +{ + M0P_PCNT->TOP_f.TOP = value; +} + +/** +****************************************************************************** + ** \brief 鍒濆鍖 + ** @param start : 瑕佸悓姝ュ埌TOP鐨勬暟鍊 + ** @param end : 瑕佸悓姝ュ埌CNT鐨勬暟鍊 + ** \retval ok 鎴 ErrorTimeout + ** +******************************************************************************/ +void Pcnt_Init(stc_pcnt_initstruct_t* InitStruct) +{ + M0P_PCNT->CTRL_f.S1P = InitStruct->Pcnt_S1Sel; + M0P_PCNT->CTRL_f.S0P = InitStruct->Pcnt_S0Sel; + M0P_PCNT->CTRL_f.CLKSEL = InitStruct->Pcnt_Clk; + M0P_PCNT->CTRL_f.MODE = InitStruct->Pcnt_Mode; + if(InitStruct->Pcnt_Mode == PcntDoubleMode)//濡傛灉鏄弻閫氶亾姝ｄ氦鑴夊啿璁℃暟妯″紡 + { + M0P_PCNT->SR1_f.DIR = InitStruct->Pcnt_Dir; + } + else + { + M0P_PCNT->CTRL_f.DIR = InitStruct->Pcnt_Dir; + } + M0P_PCNT->FLT_f.EN = InitStruct->Pcnt_FltEn; + M0P_PCNT->FLT_f.DEBTOP = InitStruct->Pcnt_DebTop; + M0P_PCNT->FLT_f.CLKDIV = InitStruct->Pcnt_ClkDiv; + M0P_PCNT->TOCR_f.EN = InitStruct->Pcnt_TocrEn; + M0P_PCNT->TOCR_f.TH = InitStruct->Pcnt_TocrTh; + + M0P_PCNT->DBG_f.DBG = InitStruct->Pcnt_Dbg; +} + +/** +****************************************************************************** + ** \brief 閰嶇疆涓柇婧愮殑浣胯兘 + ** @param IT_Src : 涓柇婧愬啀PCNT_IEN鍐呴儴鐨勪綅浣嶇疆 + ** @param NewState : FALSE 鎴朤RUE + ** \retval 鏃 + ** +******************************************************************************/ +void Pcnt_ItCfg(en_pcnt_itfce_t IT_Src, boolean_t NewState) +{ + if(NewState == TRUE) + { + M0P_PCNT->IEN |= (uint32_t)(1<IEN &= ~(uint32_t)(1<IFR >> IT_Src) & 1u) > 0 ? TRUE : FALSE; +} + +/** +****************************************************************************** + ** \brief 娓呴櫎涓柇婧愮殑鏍囧織浣 + ** @param IT_Src : 涓柇婧愭爣蹇椾綅 + ** \retval 鏃 + ** +******************************************************************************/ +void Pcnt_ClrItStatus(en_pcnt_itfce_t IT_Src) +{ + M0P_PCNT->ICR &= ~(uint32_t)(1<<(uint32_t)IT_Src); +} + + +/** +****************************************************************************** + ** \brief 鑾峰彇PCNT_CNT瀵勫瓨鍣ㄧ殑鏁板 + ** @param 鏃 + ** \retval PCNT_CNT鏁板 + ** +******************************************************************************/ +uint16_t Pcnt_GetCnt(void) +{ + return (uint16_t)(M0P_PCNT->CNT); +} + +/** +****************************************************************************** + ** \brief 鑾峰彇PCNT_TOP瀵勫瓨鍣ㄧ殑鏁板 + ** @param 鏃 + ** \retval PCNT_TOP鏁板 + ** +******************************************************************************/ +uint16_t Pcnt_GetTop(void) +{ + return (uint16_t)(M0P_PCNT->TOP); +} + +/** +****************************************************************************** + ** \brief 鑾峰彇PCNT_BUF瀵勫瓨鍣ㄧ殑鏁板 + ** @param 鏃 + ** \retval PCNT_BUF鏁板 + ** +******************************************************************************/ +uint16_t Pcnt_GetBuf(void) +{ + return (uint16_t)(M0P_PCNT->BUF); +} + +//@} // Group +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/src/ram.c b/driver/src/ram.c new file mode 100644 index 0000000..44081b6 --- /dev/null +++ b/driver/src/ram.c @@ -0,0 +1,156 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file ram.c + ** + ** Common API of ram. + ** @link RamGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ram.h" +/** + ******************************************************************************* + ** \addtogroup ramGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Ram濂囧伓鏍￠獙鍑洪敊鍦板潃鑾峰彇 + ** + ** + ** \retval ERROR ADDRESS + *****************************************************************************/ +uint32_t Ram_ErrAddrGet(void) +{ + return M0P_RAM->ERRADDR; +} + +/** + ***************************************************************************** + ** \brief Ram涓柇鏍囧織鑾峰彇 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Ram_GetIntFlag(void) +{ + if(M0P_RAM->IFR & 0x1) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + ***************************************************************************** + ** \brief Ram涓柇鏍囧織娓呴櫎 + ** + ** + ** \retval Null + *****************************************************************************/ +void Ram_ClearIntFlag(void) +{ + M0P_RAM->ICLR = 0u; +} + +/** + ***************************************************************************** + ** \brief Ram涓柇浣胯兘 + ** + ** \retval Null + *****************************************************************************/ +void Ram_EnableIrq (void) +{ + M0P_RAM->CR |= 0x2u; +} + +/** + ***************************************************************************** + ** \brief ram涓柇绂佹 + ** + ** \retval Null + *****************************************************************************/ +void Ram_DisableIrq(void) +{ + M0P_RAM->CR &= 0x1; +} + + +//@} // RamGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/reset.c b/driver/src/reset.c new file mode 100644 index 0000000..41d0321 --- /dev/null +++ b/driver/src/reset.c @@ -0,0 +1,184 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file reset.c + ** + ** Common API of reset. + ** @link resetGroup Some description @endlink + ** + ** - 2017-05-04 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "reset.h" + +/** + ******************************************************************************* + ** \addtogroup ResetGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief 鑾峰彇澶嶄綅婧愮被鍨. + ** + ** \param [out] enRstFlg @ref en_reset_flag_t + ** + ** \retval TRUE or FALSE + ******************************************************************************/ +boolean_t Reset_GetFlag(en_reset_flag_t enRstFlg) +{ + if(M0P_RESET->RESET_FLAG&enRstFlg) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + ******************************************************************************* + ** \brief 娓呴櫎澶嶄綅婧愮被鍨. + ** + ** \param [in] pstcFlag @ref en_reset_flag_t + ** + ** \retval Null + ******************************************************************************/ +void Reset_ClearFlag(en_reset_flag_t enRstFlg) +{ + M0P_RESET->RESET_FLAG &= ~(uint32_t)enRstFlg; +} + +/** + ******************************************************************************* + ** \brief 娓呴櫎鎵鏈夊浣嶆簮绫诲瀷. + ** + ** \param Null + ** + ** \retval Null + ******************************************************************************/ +void Reset_ClearFlagAll(void) +{ + M0P_RESET->RESET_FLAG = 0; +} + +/** + ******************************************************************************* + ** \brief 鎵鏈夋ā鍧楄繘琛屼竴娆″浣. + ** + ** + ** \retval Null + ******************************************************************************/ +void Reset_RstPeripheralAll(void) +{ + M0P_RESET->PERI_RESET0 = 0u; + M0P_RESET->PERI_RESET0 = 0xFFFFFFFFu; + M0P_RESET->PERI_RESET1 = 0u; + M0P_RESET->PERI_RESET1 = 0xFFFFFFFFu; +} + +/** + ******************************************************************************* + ** \brief 瀵瑰璁炬簮0妯″潡杩涜涓娆″浣. + ** + ** \param [in] enPeri @ref en_reset_peripheral0_t + ** + ** \retval Null + ******************************************************************************/ +void Reset_RstPeripheral0(en_reset_peripheral0_t enPeri) +{ + M0P_RESET->PERI_RESET0 &= ~(uint32_t)enPeri; + M0P_RESET->PERI_RESET0 |= (uint32_t)enPeri; +} + +/** + ******************************************************************************* + ** \brief 瀵瑰璁炬簮1妯″潡杩涜涓娆″浣. + ** + ** \param [in] enPeri @ref en_reset_peripheral1_t + ** + ** \retval Null + ******************************************************************************/ +void Reset_RstPeripheral1(en_reset_peripheral1_t enPeri) +{ + M0P_RESET->PERI_RESET1 &= ~(uint32_t)enPeri; + M0P_RESET->PERI_RESET1 |= (uint32_t)enPeri; +} + +//@} // ResetGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/driver/src/rtc.c b/driver/src/rtc.c new file mode 100644 index 0000000..6d25249 --- /dev/null +++ b/driver/src/rtc.c @@ -0,0 +1,520 @@ +/************************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file rtc.c + ** + ** RTC function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2019-04-10 First version + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "rtc.h" +/** + ****************************************************************************** + ** \addtogroup RtcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('const') */ +/******************************************************************************/ +const uint8_t Leap_Month_Base[] = {3,6,0,3,5,1,3,6,2,4,0,2}; +const uint8_t NonLeap_Month_Base[] = {4,0,0,3,5,1,3,6,2,4,0,2}; +const uint8_t Cnst_Month_Tbl[12]={0x31,0x28,0x31,0x30,0x31,0x30,0x31,0x31,0x30,0x31,0x30,0x31}; +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable prototypes ('static') */ +/******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** +****************************************************************************** + ** \brief RTC璁℃暟鍣ㄧ殑浣胯兘鎴栧仠姝 + ** + ** @param NewState : TRUE 鎴 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Rtc_Cmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_RTC->CR0)), 7, NewState); +} + +/** +****************************************************************************** + ** \brief RTC璁℃暟鍣ㄥ惎鍔ㄧ瓑寰呭嚱鏁帮紝濡傚惎鍔≧TC璁℃暟鍣ㄥ悗绔嬪嵆杩涘叆浣庡姛鑰楁ā寮忥紝 + ** 杩涘叆浣庡姛鑰楁ā寮忎箣鍓嶉渶鎵ц姝ゅ嚱鏁帮紝浠ョ‘淇漅TC宸插惎鍔ㄥ畬鎴 + ** + ** @param NewState : TRUE 鎴 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Rtc_StartWait(void) +{ + M0P_RTC->CR1_f.WAIT = 1; + while (M0P_RTC->CR1_f.WAITF != 1) //绛夊緟鐩村埌WAITF=1 + { + ; + } + M0P_RTC->CR1_f.WAIT = 0; + while (M0P_RTC->CR1_f.WAITF != 0) //绛夊緟鐩村埌WAITF=0 + { + ; + } +} + +/** +****************************************************************************** + ** \brief RTC鐨1Hz杈撳嚭鐨勪娇鑳芥垨鍋滄 + ** @param pricision : RtcHz1selGeneralPricision 鎴 RtcHz1selHighPricision + ** @param NewState : Hz1o_Disable 鎴 HZ1o_Enable + ** \retval 鏃 + ** +******************************************************************************/ +void Rtc_Hz1Cmd(en_rtc_hz1sel_t pricision, boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_RTC->CR0)), 6, pricision); //璁剧疆鏅氱簿搴︽垨鑰呴珮绮惧害1Hz杈撳嚭 + SetBit((uint32_t)(&(M0P_RTC->CR0)), 5, NewState); //璁剧疆1Hz杈撳嚭浣胯兘鎴栫姝 +} + +/** +****************************************************************************** + ** \brief 璁剧疆鍛ㄦ湡涓柇鐨勭被鍨(PRDSEL)鍙婂叾鎵閫夌被鍨嬬殑鏃堕棿(PRDS鎴朠RDX) + ** + ** @param pstCyc: 鏍规嵁缁撴瀯浣撶殑瀹氫箟璁剧疆PRDSEL銆丳RDS涓嶱RDX + ** \retval Ok銆丒rror 鎴 ErrorInvalidParameter + ** +******************************************************************************/ +en_result_t Rtc_SetCyc(stc_rtc_cyccfg_t* pstCyc) +{ + en_result_t enRet = Error; + M0P_RTC->CR0_f.PRDSEL = pstCyc->rtcPrdsel; + if(pstCyc->rtcPrdsel == RtcPrds) + { + M0P_RTC->CR0_f.PRDS = pstCyc->rtcPrds; + } + else if(pstCyc->rtcPrdsel == RtcPrdx) + { + if(pstCyc->rtcPrdx>=64) + { + enRet = ErrorInvalidParameter; + return enRet; + } + M0P_RTC->CR0_f.PRDX = pstCyc->rtcPrdx; + } + else + { + ; + } + enRet = Ok; + return enRet; +} + +/** +****************************************************************************** + ** \brief RTC闂归挓涓柇鐨勪娇鑳芥垨鍋滄 + ** + ** @param NewState : TRUE 鎴 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Rtc_AlmIeCmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_RTC->CR1)), 3, 0); //娓呴櫎鍛ㄦ湡涓柇鏍囧織浣 + SetBit((uint32_t)(&(M0P_RTC->CR1)), 4, 0); //娓呴櫎鍛ㄦ湡涓柇鏍囧織浣 + SetBit((uint32_t)(&(M0P_RTC->CR1)), 6, NewState); +} + +/** +****************************************************************************** + ** \brief RTC闂归挓鐨勪娇鑳芥垨鍋滄 + ** + ** @param NewState : Almen_Disable 鎴 Almen_Enable + ** \retval 鏃 + ** +******************************************************************************/ +void Rtc_AlmEnCmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_RTC->CR1)), 7, NewState); +} + +/** +****************************************************************************** + ** \brief 鑾峰彇RTC闂归挓涓柇鐘舵佷綅 + ** + ** @param 鏃 + ** \retval TRUE 鎴 FALSE + ** +******************************************************************************/ +boolean_t Rtc_GetAlmfItStatus(void) +{ + return GetBit((uint32_t)(&(M0P_RTC->CR1)), 4); +} + +/** +****************************************************************************** + ** \brief 娓呴櫎RTC闂归挓涓柇鐘舵佷綅 + ** + ** @param 鏃 + ** \retval 鏃 + ** +******************************************************************************/ +void Rtc_ClearAlmfItStatus(void) +{ + SetBit((uint32_t)(&(M0P_RTC->CR1)), 4, 0); +} + +/** +****************************************************************************** + ** \brief 娓呴櫎RTC鍛ㄦ湡涓柇鐘舵佷綅 + ** + ** @param 鏃 + ** \retval 鏃 + ** +******************************************************************************/ +void Rtc_ClearPrdfItStatus(void) +{ + SetBit((uint32_t)(&(M0P_RTC->CR1)), 3, 0); +} + +/** +****************************************************************************** + ** \brief 鑾峰彇RTC鍛ㄦ湡涓柇鐘舵佷綅 + ** + ** @param 鏃 + ** \retval TRUE 鎴 FALSE + ** +******************************************************************************/ +boolean_t Rtc_GetPridItStatus(void) +{ + return GetBit((uint32_t)(&(M0P_RTC->CR1)), 3); +} + +/** +****************************************************************************** + ** \brief 閰嶇疆RTC鐨勮宸ˉ鍋垮瘎瀛樺櫒 + ** + ** @param CompValue:鏁板肩殑鑼冨洿涓猴細32-256 + ** @param NewStatus: RtcCompenDisable 鎴 RtcAmCompenEnable + ** \retval Ok ErrorInvalidParameter + ** +******************************************************************************/ +en_result_t Rtc_CompCfg(uint16_t CompVlue, en_rtc_compen_t NewStatus) +{ + en_result_t enRet = Error; + if(CompVlue<=256) + { + M0P_RTC->COMPEN_f.EN = NewStatus; + M0P_RTC->COMPEN_f.CR = CompVlue; + } + else + { + enRet = ErrorInvalidParameter; + } + return enRet; +} + +/** + ****************************************************************************** + ** \brief RTC鏍规嵁鏃ユ湡璁＄畻鍛ㄦ暟 + ** + ** \param pu8buf鏃堕棿鏁版嵁 + ** \param u8limit_min鏈灏忓 + ** \param u8limit_max鏈澶у + ** + ** \retval Error 閿欒锛孫k鏍￠獙姝ｇ‘ + ** + ******************************************************************************/ +en_result_t Check_BCD_Format(uint8_t u8data,uint8_t u8limit_min, uint8_t u8limit_max) +{ + + if (((u8data & 0x0F) > 0x09) || ((u8data & 0xF0) > 0x90) + ||(u8data > u8limit_max) || (u8data < u8limit_min)) + { + return Error; + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief RTC 骞炽侀棸骞存娴 + ** +** \param u8year:骞村崄杩涘埗浣庝袱浣:0-99 + ** + ** \retval 1:闂板勾 0锛氬钩骞 + ** + ******************************************************************************/ +uint8_t Rtc_CheckLeapYear(uint8_t u8year) +{ + uint16_t tmp; + tmp=2000+u8year; + if((((tmp % 4)==0) && ((tmp % 100) !=0))|| ((tmp % 400) ==0)) + { + return 1; + } + else + { + return 0; + } +} + +/** + ****************************************************************************** + ** \brief RTC鏍规嵁骞磋幏鍙栦簩鏈堢殑澶╂暟 + ** + ** \param [in] u8month鏈堜唤锛寀8year骞翠唤 + ** +** \retval u8day澶╂暟:28鎴29 + ** + ******************************************************************************/ +uint8_t Get_Month2_Day( uint8_t u8year) +{ + uint8_t u8day = 0; + + u8day = 28; + if(Rtc_CheckLeapYear(u8year) == 1) + { + u8day++; + } + return u8day; +} + +/** + ****************************************************************************** + ** \brief RTC鑾峰彇鏃堕棿鍑芥暟 + ** + ** \param time: 鐢ㄤ簬瀛樻斁璇诲彇鑷椂闂村瘎瀛樺櫒鐨勬椂闂存暟鎹紝鏍煎紡涓築CD鐮佹牸寮 + ** + ** \retval Ok 鑾峰彇姝ｅ父 + ** \retval ErrorTimeout 鏃堕棿婧㈠嚭閿欒 + ******************************************************************************/ +en_result_t Rtc_ReadDateTime(stc_rtc_time_t* time) +{ + uint32_t u32TimeOut; + ASSERT(NULL != pstcTimeDate); + u32TimeOut = 1000; + if(1 == M0P_RTC->CR0_f.START) + { + M0P_RTC->CR1_f.WAIT = 1; + while(u32TimeOut--) + { + if(M0P_RTC->CR1_f.WAITF) + { + break; + } + } + if(u32TimeOut==0) + { + return ErrorTimeout; + } + } + time->u8Second = M0P_RTC->SEC; + time->u8Minute = M0P_RTC->MIN; + if(1 == M0P_RTC->CR0_f.AMPM) + { + time->u8Hour = M0P_RTC->HOUR; + } + else + { + time->u8Hour = M0P_RTC->HOUR&0x1f; + } + time->u8Day = M0P_RTC->DAY; + time->u8DayOfWeek = M0P_RTC->WEEK; + time->u8Month = M0P_RTC->MON; + time->u8Year = M0P_RTC->YEAR; + + M0P_RTC->CR1_f.WAIT = 0; + if(1 == M0P_RTC->CR0_f.START) + { + while(M0P_RTC->CR1_f.WAITF) + {} + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief 鍚慠TC鏃堕棿瀵勫瓨鍣ㄥ啓鍏ユ椂闂 + ** + ** \param time锛 瀛樻斁鏃堕棿鐨勭粨鏋勪綋锛屽悇涓椂闂村潎涓築CD鐮佹牸寮 + ** + ** \retval ErrorTimeout 鎴 Ok + ** + ******************************************************************************/ +en_result_t Rtc_SetTime(stc_rtc_time_t* time) +{ + en_result_t enRet = Ok; + uint16_t u16TimeOut; + u16TimeOut = 1000; + if(M0P_RTC->CR0_f.START == 1) + { + M0P_RTC->CR1_f.WAIT = 1; + while(--u16TimeOut) + { + if(M0P_RTC->CR1_f.WAITF) + { + break; + } + } + if(u16TimeOut==0) + { + return ErrorTimeout; + } + } + M0P_RTC->SEC = time->u8Second; + M0P_RTC->MIN = time->u8Minute; + M0P_RTC->HOUR = time->u8Hour; + M0P_RTC->DAY = time->u8Day; + M0P_RTC->MON = time->u8Month; + M0P_RTC->YEAR = time->u8Year; + M0P_RTC->WEEK = time->u8DayOfWeek; + + M0P_RTC->CR1_f.WAIT = 0; + if(M0P_RTC->CR0_f.START == 1) + { + while(M0P_RTC->CR1_f.WAITF) + {} + } + enRet = Ok; + return enRet; +} + +/** + ****************************************************************************** + ** \brief RTC闂归挓涓柇鏃堕棿鑾峰彇 + ** + ** \param pstcAlarmTime锛氬瓨鏀鹃椆閽熸椂闂村瘎瀛樺櫒鏁版嵁锛氱 鍒 鏃 鍛 + ** + ** \retval 鏃 + ** + ******************************************************************************/ +void Rtc_GetAlarmTime(stc_rtc_alarmtime_t* pstcAlarmTime) +{ + pstcAlarmTime->RtcAlarmSec = M0P_RTC->ALMSEC; + pstcAlarmTime->RtcAlarmMinute = M0P_RTC->ALMMIN; + pstcAlarmTime->RtcAlarmHour = M0P_RTC->ALMHOUR; + pstcAlarmTime->RtcAlarmWeek = M0P_RTC->ALMWEEK; +} + +/** + ****************************************************************************** + ** \brief RTC闂归挓璁剧疆 + ** + ** \param [in] pstcAlarmTime闂归挓鏃堕棿锛氱 鍒 鏃 鍛 + ** + ** \retval Ok 璁剧疆姝ｅ父 + ** + ******************************************************************************/ +en_result_t Rtc_SetAlarmTime(stc_rtc_alarmtime_t* pstcAlarmTime) +{ + en_result_t enRet = Ok; +// ASSERT(NULL != pstcAlarmTime); + Rtc_AlmEnCmd(FALSE); //闂归挓绂佹浠ュ悗鍐嶈缃椆閽熸椂闂 + enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmSec,0x00,0x59); + if(M0P_RTC->CR0_f.AMPM == RtcAm) + { + enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmHour,0x00,0x12); + } + else + { + enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmHour,0x00,0x24); + } + if(enRet != Ok) + { + return enRet; + } + enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmMinute,0x00,0x59); + if(enRet != Ok) + { + return enRet; + } + + if(enRet != Ok) + { + return enRet; + } + M0P_RTC->ALMSEC = pstcAlarmTime->RtcAlarmSec & 0x7f; + M0P_RTC->ALMMIN = pstcAlarmTime->RtcAlarmMinute & 0x7f; + M0P_RTC->ALMHOUR = pstcAlarmTime->RtcAlarmHour & 0x3f; + M0P_RTC->ALMWEEK = pstcAlarmTime->RtcAlarmWeek; + Rtc_AlmEnCmd(TRUE); //闂归挓璁稿彲 + enRet = Ok; + return enRet; +} + +/** +****************************************************************************** + ** \brief 鍒濆鍖朢TC + ** + ** @param Rtc_InitStruct 瀛樻斁stc_rtc_initstruct_t绫诲瀷鐨勭粨鏋勪綋 + ** \retval 鏃 + ** +******************************************************************************/ +void Rtc_Init(stc_rtc_initstruct_t* Rtc_InitStruct) +{ + Rtc_Cmd(FALSE); + M0P_RTC->CR0_f.AMPM = Rtc_InitStruct->rtcAmpm; //瀹炴椂鏃堕挓灏忔椂鐨勬椂鍒 + Rtc_SetCyc(&Rtc_InitStruct->rtcPrdsel); //璁剧疆鍛ㄦ湡涓柇鐨勭被鍨(PRDSEL)鍙婂叾鎵閫夌被鍨嬬殑鏃堕棿(PRDS鎴朠RDX) + M0P_RTC->CR1_f.CKSEL = Rtc_InitStruct->rtcClksrc; //瀹炴椂鏃堕挓RTC鐨勬椂閽熸簮 + Rtc_CompCfg(Rtc_InitStruct->rtcCompValue, Rtc_InitStruct->rtcCompen); //閰嶇疆鏃堕挓璇樊琛ュ伩瀵勫瓨鍣 + Rtc_SetTime(&Rtc_InitStruct->rtcTime); //璁剧疆鍒濆鏃堕挓 +} + + + diff --git a/driver/src/spi.c b/driver/src/spi.c new file mode 100644 index 0000000..a833ccd --- /dev/null +++ b/driver/src/spi.c @@ -0,0 +1,363 @@ +/****************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with eaenCh copy of this software, whether used in part or whole, +* at all times. +*/ +/*****************************************************************************/ +/** \file spi.c + ** + ** SPI driver API. + ** @link Driver Group Some description @endlink + ** + ** - 2018-05-17 1.0 Devi First version for Device Driver Library of + ** Module. + ** + *****************************************************************************/ + +/****************************************************************************** + * Include files + *****************************************************************************/ +#include "spi.h" + +/** + ****************************************************************************** + ** \addtogroup SpiGroup + *****************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + *****************************************************************************/ + +#define IS_VALID_STAT(x) ( SpiIf == (x)||\ + SpiSserr == (x)||\ + SpiBusy == (x)||\ + SpiMdf == (x)||\ + SpiTxe == (x)||\ + SpiRxne == (x)) + + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable prototypes ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief SPI 璇锋眰鐘舵佽幏鍙 + ** + ** \param [in]SPIx 閫氶亾锛 enStatus 鑾峰彇璇锋眰 + ** + ** \retval 璇锋眰鐘舵 + ** + ******************************************************************************/ +boolean_t Spi_GetStatus(M0P_SPI_TypeDef* SPIx, en_spi_status_t enStatus) +{ + ASSERT(IS_VALID_STAT(enStatus)); + + if(SPIx->STAT&enStatus) + { + return TRUE; + } + else + { + return FALSE; + } + +} +/** + ****************************************************************************** + ** \brief SPI涓柇娓呴櫎 + ** + ** \param [in]SPIx 閫氶亾閫夋嫨 + ** + ** \retval 璇锋眰鐘舵 + ** + ******************************************************************************/ +en_result_t Spi_ClearStatus(M0P_SPI_TypeDef* SPIx) +{ + SPIx->ICLR = 0; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 涓柇浣胯兘鍑芥暟 + ** + ** \param [in] SPIx 閫氶亾 + ** + ** \retval Ok鎴愬姛 + ** + ******************************************************************************/ +en_result_t Spi_IrqEnable(M0P_SPI_TypeDef* SPIx) +{ + SPIx->CR2 |= 0x4u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 涓柇绂佹鍑芥暟 + ** + ** \param [in] enCh閫氶亾 + ** + ** \retval Ok鎴愬姛 + ** + ******************************************************************************/ +en_result_t Spi_IrqDisable(M0P_SPI_TypeDef* SPIx) +{ + SPIx->CR2 &= ~0x4u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 鍔熻兘浣胯兘鍑芥暟 + ** + ** \param [in] SPIx 閫氶亾锛宔nFunc鍔熻兘 + ** + ** \retval Ok鍒濆鍖栨垚鍔 + ** + ******************************************************************************/ +en_result_t Spi_FuncEnable(M0P_SPI_TypeDef* SPIx, en_spi_func_t enFunc) +{ + SPIx->CR2 |= enFunc; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 鍔熻兘绂佹鍑芥暟 + ** + ** \param [in] SPIx 閫氶亾锛宔nFunc鍔熻兘 + ** + ** \retval Ok鍒濆鍖栨垚鍔 + ** + ******************************************************************************/ +en_result_t Spi_FuncDisable(M0P_SPI_TypeDef* SPIx, en_spi_func_t enFunc) +{ + SPIx->CR2 &= ~(uint32_t)enFunc; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 鎬讳綋鍒濆鍖栧嚱鏁 + ** + ** \param [in] SPIx 閫氶亾 + ** \param [in] pstcSpiCfg 鍒濆鍖栫粨鏋勪綋 + ** + ** \retval Ok鍒濆鍖栨垚鍔 + ** \retval ErrorInvalidParameter 鍒濆鍖栭敊璇 + ******************************************************************************/ +en_result_t Spi_Init(M0P_SPI_TypeDef* SPIx, stc_spi_cfg_t *pstcSpiCfg) +{ + ASSERT(NULL != pstcSpiCfg); + + SPIx->CR = 0; + + SPIx->SSN = TRUE; + + SPIx->CR = (uint32_t)pstcSpiCfg->enSpiMode | + (uint32_t)pstcSpiCfg->enPclkDiv | + (uint32_t)pstcSpiCfg->enCPOL | + (uint32_t)pstcSpiCfg->enCPHA | + (uint32_t)0x40; + + SPIx->STAT = 0x00; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 閰嶇疆涓诲彂閫佺殑鐢靛钩 + ** + ** \param [in] SPIx 閫氶亾閫夋嫨锛宐Flag楂樹綆鐢靛钩 + ** + ** \retval 鏃 + ** + ******************************************************************************/ +void Spi_SetCS(M0P_SPI_TypeDef* SPIx, boolean_t bFlag) +{ + SPIx->SSN = bFlag; +} +/** + ****************************************************************************** + ** \brief SPI 鍙戦佷竴瀛楄妭鍑芥暟 + ** + ** \param [in] SPIx 閫氶亾閫夋嫨锛寀8Data鍙戦佸瓧鑺 + ** + ** \retval Ok鍙戦佹垚鍔 + ** + ******************************************************************************/ +en_result_t Spi_SendData(M0P_SPI_TypeDef* SPIx, uint8_t u8Data) +{ + SPIx->DATA = u8Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 璇/鍐欎竴瀛楄妭鍑芥暟 + ** + ** \param [in] SPIx 閫氶亾閫夋嫨 + ** \param [in] u8Data 鍙戦佷竴瀛楄妭鏁版嵁 + ** + ** \retval 鎺ユ敹涓瀛楄妭鏁版嵁 + ** + ******************************************************************************/ +uint8_t Spi_RWByte(M0P_SPI_TypeDef* SPIx, uint8_t u8Data) +{ + uint16_t Dly = 0xffff; + + while(FALSE == SPIx->STAT_f.TXE) { + Dly--; + if(Dly == 0) + break; + } + Dly = 0xffff; + SPIx->DATA = u8Data; + while(FALSE == SPIx->STAT_f.RXNE) { + Dly--; + if(Dly == 0) + break; + } + return SPIx->DATA; +} + +/** + ****************************************************************************** +** \brief SPI 浠庢満棰勫噯澶囩涓瀛楄妭鏁版嵁 + ** + ** \param [in] SPIx 閫氶亾閫夋嫨 + ** \param [in] u8Data 棰勫噯澶囩涓瀛楄妭鏁版嵁 + ** + ** \retval None + ** + ******************************************************************************/ +void Spi_Slave_DummyWriteData(M0P_SPI_TypeDef* SPIx, uint8_t u8Data) +{ + while(FALSE == SPIx->STAT_f.TXE){;} + SPIx->DATA = u8Data; +} + +/** + ****************************************************************************** + ** \brief SPI 杩炵画鍙戦佸瀛楄妭鍑芥暟 + ** + ** \param [in] SPIx 閫氶亾閫夋嫨 + ** \param [in] pu8Buf 鍙戦佹暟鎹寚閽 + ** + ** \retval Ok鍙戦佹垚鍔 + ** + ******************************************************************************/ +en_result_t Spi_SendBuf(M0P_SPI_TypeDef* SPIx, uint8_t* pu8Buf, uint32_t u32Len) +{ + uint32_t u32Index=0; + + for(u32Index=0; u32IndexSTAT_f.TXE){;} + SPIx->DATA = pu8Buf[u32Index]; + while(FALSE == SPIx->STAT_f.RXNE){;} + pu8Buf[u32Index] = SPIx->DATA; + } + + while(FALSE == SPIx->STAT_f.TXE){;} + while(TRUE == SPIx->STAT_f.BUSY){;} + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 鎺ユ敹涓瀛楄妭鍑芥暟 + ** + ** \param [in] SPIx鎺ユ敹閫氶亾 + ** + ** \retval 鎺ユ敹涓瀛楄妭鏁版嵁 + ** + ******************************************************************************/ +uint8_t Spi_ReceiveData(M0P_SPI_TypeDef* SPIx) +{ + return SPIx->DATA; +} + +/** + ****************************************************************************** + ** \brief SPI 杩炵画鎺ユ敹澶氬瓧鑺傚嚱鏁 + ** + ** \param [in] SPIx 閫氶亾閫夋嫨 + ** \param [in] pu8Buf 鍙戦佹暟鎹寚閽 + ** + ** \retval Ok鍙戦佹垚鍔 + ** + ******************************************************************************/ +en_result_t Spi_ReceiveBuf(M0P_SPI_TypeDef* SPIx, uint8_t* pu8Buf, uint32_t u32Len) +{ + uint32_t u32Index=0; + + for(u32Index=0; u32IndexSTAT_f.TXE){;} + SPIx->DATA = 0x00; + while(FALSE == SPIx->STAT_f.RXNE){;} + pu8Buf[u32Index] = SPIx->DATA; + } + + while(TRUE == SPIx->STAT_f.BUSY){;} + + return Ok; +} + +//@} // SpiGroup +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + diff --git a/driver/src/sysctrl.c b/driver/src/sysctrl.c new file mode 100644 index 0000000..83f00be --- /dev/null +++ b/driver/src/sysctrl.c @@ -0,0 +1,746 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file sysctrl.c + ** + ** Common API of sysctrl. + ** @link SysctrlGroup Some description @endlink + ** + ** - 2018-04-22 Lux + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "sysctrl.h" + +/** + ******************************************************************************* + ** \addtogroup SysctrlGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CLK_TIMEOUT (1000000u) + +#define IS_VALID_SRC(x) ( ClkRCH == (x)||\ + ClkXTH == (x)||\ + ClkRCL == (x)||\ + ClkXTL == (x) ) + + +#define IS_VALID_FUNC(x) ( ClkFuncWkupRCH == (x)||\ + ClkFuncXTHEn == (x)||\ + ClkFuncXTLEn == (x)||\ + ClkFuncXTLAWSON == (x)||\ + ClkFuncFaultEn == (x)||\ + ClkFuncRtcLPWEn == (x)||\ + ClkFuncLockUpEn == (x)||\ + ClkFuncRstPinIOEn == (x)||\ + ClkFuncSwdPinIOEn == (x) ) + +#define RC_TRIM_BASE_ADDR ((volatile uint16_t*) (0x00100C00ul)) +#define RCH_CR_TRIM_24M_VAL (*((volatile uint16_t*) (0x00100C00ul))) +#define RCH_CR_TRIM_22_12M_VAL (*((volatile uint16_t*) (0x00100C02ul))) +#define RCH_CR_TRIM_16M_VAL (*((volatile uint16_t*) (0x00100C04ul))) +#define RCH_CR_TRIM_8M_VAL (*((volatile uint16_t*) (0x00100C06ul))) +#define RCH_CR_TRIM_4M_VAL (*((volatile uint16_t*) (0x00100C08ul))) + +#define RCL_CR_TRIM_38400_VAL (*((volatile uint16_t*) (0x00100C20ul))) +#define RCL_CR_TRIM_32768_VAL (*((volatile uint16_t*) (0x00100C22ul))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +extern uint32_t SystemCoreClock; +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief SYSCTRL0\SYSCTRL1瀵勫瓨鍣ㄦ搷浣滆В閿 + ** + ** \retval None + ******************************************************************************/ +static void _SysctrlUnlock(void) +{ + M0P_SYSCTRL->SYSCTRL2 = 0x5A5A; + M0P_SYSCTRL->SYSCTRL2 = 0xA5A5; +} + +/** + ******************************************************************************* + ** \brief 绯荤粺鏃堕挓婧愪娇鑳 + ** \param [in] enSource 鐩爣鏃堕挓婧 + ** \param [in] bFlag 浣胯兘1-寮/0-鍏 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag) +{ + en_result_t enRet = Ok; + uint32_t u32Temp; + + _SysctrlUnlock(); + bFlag = !!bFlag; + + u32Temp = M0P_SYSCTRL->PERI_CLKEN0; + switch (enSource) + { + case SysctrlClkRCH: + M0P_SYSCTRL->SYSCTRL0_f.RCH_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->RCH_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkXTH: + M0P_SYSCTRL->PERI_CLKEN0_f.GPIO = TRUE; + M0P_GPIO->PFADS |= 3u; + M0P_SYSCTRL->SYSCTRL0_f.XTH_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->XTH_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkRCL: + + M0P_SYSCTRL->SYSCTRL0_f.RCL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->RCL_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkXTL: + M0P_SYSCTRL->PERI_CLKEN0_f.GPIO = TRUE; + M0P_GPIO->PCADS |= 0xC000; + M0P_SYSCTRL->SYSCTRL0_f.XTL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->XTL_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkPLL: + M0P_SYSCTRL->PERI_CLKEN0_f.ADC = TRUE; + M0P_BGR->CR_f.BGR_EN = TRUE; + delay10us(20); + M0P_SYSCTRL->SYSCTRL0_f.PLL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->PLL_CR_f.STABLE)) + { + ; + } + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + M0P_SYSCTRL->PERI_CLKEN0 = u32Temp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 澶栭儴楂橀熸櫠鎸┍鍔ㄩ厤缃 + ** \param [in] enFreq 澶栭儴楂橀熸櫠鎸鐜囪寖鍥撮夋嫨 + ** \param [in] enDriver 澶栭儴楂橀熸櫠鎸┍鍔ㄨ兘鍔涢夋嫨 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_XTHDriverCfg(en_sysctrl_xtal_driver_t enDriver) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTH_CR_f.DRIVER = enDriver; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 澶栭儴浣庨熸櫠鎸┍鍔ㄩ厤缃 + ** \param [in] enFreq 澶栭儴浣庨熸櫠鎸鐜囪寖鍥撮夋嫨 + ** \param [in] enDriver 澶栭儴浣庨熸櫠鎸┍鍔ㄨ兘鍔涢夋嫨 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_XTLDriverCfg(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTL_CR_f.AMP_SEL = enAmp; + M0P_SYSCTRL->XTL_CR_f.DRIVER = enDriver; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 澶栭儴楂橀熸椂閽熺ǔ瀹氬懆鏈熼厤缃 + ** \param [in] enCycle 澶栭儴楂橀熸椂閽熺ǔ瀹氬懆鏈熻缃 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->XTH_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 鍐呴儴浣庨熸椂閽熺ǔ瀹氬懆鏈熼厤缃 + ** \param [in] enCycle 鍐呴儴浣庨熸椂閽熺ǔ瀹氬懆鏈熻缃 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->RCL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 澶栭儴浣庨熸椂閽熺ǔ瀹氬懆鏈熼厤缃 + ** \param [in] enCycle 澶栭儴浣庨熸椂閽熺ǔ瀹氬懆鏈熻缃 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->XTL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief PLL绋冲畾鍛ㄦ湡閰嶇疆 + ** \param [in] enCycle PLL绋冲畾鍛ㄦ湡璁剧疆 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->PLL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 鏃堕挓婧愬垏鎹紝璇ュ嚱鏁版墽琛屽悗浼氬紑鍚柊鏃堕挓婧 + ** \note 閫夋嫨鏃堕挓婧愪箣鍓嶏紝闇鏍规嵁闇瑕侀厤缃洰鏍囨椂閽熸簮鐨勯鐜/椹卞姩鍙傛暟/浣胯兘鏃堕挓婧愮瓑 + ** \param [in] enSource 鏂版椂閽熸簮 + ** + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource) +{ + en_result_t enRet = Ok; + + en_sysctrl_clk_source_t ClkNew = enSource; + + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.CLKSW = ClkNew; + + //鏇存柊Core鏃堕挓锛圚CLK锛 + SystemCoreClockUpdate(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 鑾峰緱绯荤粺鏃堕挓锛圚CLK锛夐鐜囧 + ** \retval uint32_t HCLK棰戠巼鍊 + ** + ******************************************************************************/ +uint32_t Sysctrl_GetHClkFreq(void) +{ + uint32_t u32Val = 0; + const uint32_t u32hcr_tbl[] = { 4000000, 8000000, 16000000, 22120000, 24000000}; + const uint16_t u32lcr_tbl[] = { 32768, 38400}; + en_sysctrl_clk_source_t enSrc; + uint16_t u16Trim[5] = {0}; + u16Trim[4] = RCH_CR_TRIM_24M_VAL; + u16Trim[3] = RCH_CR_TRIM_22_12M_VAL; + u16Trim[2] = RCH_CR_TRIM_16M_VAL; + u16Trim[1] = RCH_CR_TRIM_8M_VAL; + u16Trim[0] = RCL_CR_TRIM_38400_VAL; + + //鑾峰彇褰撳墠绯荤粺鏃堕挓 + enSrc = (en_sysctrl_clk_source_t)(M0P_SYSCTRL->SYSCTRL0_f.CLKSW); + + switch (enSrc) + { + case SysctrlClkRCH: + { + + if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[4])) + { + u32Val = u32hcr_tbl[4]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[3])) + { + u32Val = u32hcr_tbl[3]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[2])) + { + u32Val = u32hcr_tbl[2]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[1])) + { + u32Val = u32hcr_tbl[1]; + } + else + { + u32Val = u32hcr_tbl[0]; + } + } + break; + case SysctrlClkXTH: + u32Val = SYSTEM_XTH; + break; + case SysctrlClkRCL: + { + if(u16Trim[0] == (M0P_SYSCTRL->RCL_CR_f.TRIM)) + { + u32Val = u32lcr_tbl[1]; + } + else + { + u32Val = u32lcr_tbl[0]; + } + } + break; + case SysctrlClkXTL: + u32Val = SYSTEM_XTL; + break; + case SysctrlClkPLL: + { + if (SysctrlPllRch == M0P_SYSCTRL->PLL_CR_f.REFSEL) + { + if(u16Trim[4] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[4]; + } + else if(u16Trim[3] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[3]; + } + else if(u16Trim[2] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[2]; + } + else if(u16Trim[1] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[1]; + } + else + { + u32Val = u32hcr_tbl[0]; + } + } + else + { + u32Val = SYSTEM_XTH; + } + + u32Val = (u32Val * M0P_SYSCTRL->PLL_CR_f.DIVN); + } + break; + default: + u32Val = 0u; + break; + } + + u32Val = (u32Val >> M0P_SYSCTRL->SYSCTRL0_f.HCLK_PRS); + + return u32Val; +} + +/** + ******************************************************************************* + ** \brief 鑾峰緱澶栬鏃堕挓锛圥CLK锛夐鐜囧 + ** \retval uint32_t PCLK棰戠巼鍊(Hz) + ** + ******************************************************************************/ +uint32_t Sysctrl_GetPClkFreq(void) +{ + uint32_t u32Val = 0; + + u32Val = Sysctrl_GetHClkFreq(); + u32Val = (u32Val >> (M0P_SYSCTRL->SYSCTRL0_f.PCLK_PRS)); + + return u32Val; +} + + +/** + ******************************************************************************* + ** \brief 鏃堕挓鍒濆鍖栧嚱鏁 + ** \param [in] pstcCfg 鍒濆鍖栭厤缃弬鏁 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_ClkInit(stc_sysctrl_clk_cfg_t *pstcCfg) +{ + en_result_t enRet = Ok; + + //绯荤粺鏃堕挓鍙傛暟閰嶇疆 + switch(pstcCfg->enClkSrc) + { + case SysctrlClkRCH: + + break; + case SysctrlClkXTH: + Sysctrl_XTHDriverCfg(SysctrlXtalDriver3); + Sysctrl_SetXTHStableTime(SysctrlXthStableCycle16384); + break; + case SysctrlClkRCL: + Sysctrl_SetRCLStableTime(SysctrlRclStableCycle256); + break; + case SysctrlClkXTL: + Sysctrl_XTLDriverCfg(SysctrlXtlAmp3, SysctrlXtalDriver3); + Sysctrl_SetXTLStableTime(SysctrlXtlStableCycle16384); + break; + case SysctrlClkPLL: + Sysctrl_SetPLLStableTime(SysctrlPllStableCycle16384); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + //鏃堕挓婧愪娇鑳 + Sysctrl_ClkSourceEnable(pstcCfg->enClkSrc, TRUE); + + //鏃堕挓婧愬垏鎹 + Sysctrl_SysClkSwitch(pstcCfg->enClkSrc); + + //鏃堕挓鍒嗛璁剧疆 + Sysctrl_SetHCLKDiv(pstcCfg->enHClkDiv); + Sysctrl_SetPCLKDiv(pstcCfg->enPClkDiv); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 鏃堕挓鍘诲垵濮嬪寲鍑芥暟 + ** \param [in] + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_ClkDeInit(void) +{ + en_result_t enRet = Ok; + + //閰嶇疆RCH涓哄唴閮4Hz + Sysctrl_SetRCHTrim(SysctrlRchFreq4MHz); + + //鏃堕挓婧愪娇鑳 + Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE); + + //鏃堕挓婧愬垏鎹 + Sysctrl_SysClkSwitch(SysctrlClkRCH); + + //鍏跺畠鏃堕挓婧愪娇鑳藉叧闂 + Sysctrl_ClkSourceEnable(SysctrlClkXTH, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkRCL, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkXTL, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkPLL, FALSE); + + //鏃堕挓鍒嗛璁剧疆 + Sysctrl_SetHCLKDiv(SysctrlHclkDiv1); + Sysctrl_SetPCLKDiv(SysctrlPclkDiv1); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 鍐呴儴楂橀熸椂閽熼鐜嘥RIM鍊煎姞杞 + ** \param [in] enRCHFreq 璁惧畾鐨凴CH鐩爣棰戠巼鍊 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触鎴栨椂閽熸湭绋冲畾 + ******************************************************************************/ +en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq) +{ + //鍔犺浇RCH Trim鍊 + M0P_SYSCTRL->RCH_CR_f.TRIM = *(RC_TRIM_BASE_ADDR + enRCHFreq); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 澶栭儴楂橀熸椂閽熼鐜囪寖鍥磋瀹 + ** \param [in] enXTHFreq 璁惧畾鐨勯鐜囧 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触鎴栨椂閽熸湭绋冲畾 + ******************************************************************************/ +en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTH_CR_f.XTH_FSEL = enXTHFreq; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief PLL鏃堕挓閰嶇疆 + ** \param [in] pstcPLLCfg PLL閰嶇疆缁撴瀯浣撴寚閽 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触鎴栧弬鏁板间笉鍖归厤 + ******************************************************************************/ +en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_cfg_t *pstcPLLCfg) +{ + en_result_t enRet = Ok; + + uint16_t u16Trim[5] = {0}; + u16Trim[4] = RCH_CR_TRIM_24M_VAL; + u16Trim[3] = RCH_CR_TRIM_22_12M_VAL; + u16Trim[2] = RCH_CR_TRIM_16M_VAL; + u16Trim[1] = RCH_CR_TRIM_8M_VAL; + + ////PLL鏈楂樻椂閽熶笉鑳借秴杩48MHz + //RCH浣滀负PLL杈撳叆 + if (SysctrlPllRch == pstcPLLCfg->enPllClkSrc) + { + if( ((u16Trim[4] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 2)) || + ((u16Trim[3] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 2)) || + ((u16Trim[2] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 3)) || + ((u16Trim[1] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 6))) + { + return ErrorInvalidMode; + } + } + else //XTH浣滀负PLL杈撳叆 + { + if ((SYSTEM_XTH * pstcPLLCfg->enPllMul) > 48*1000*1000) + { + return ErrorInvalidMode; + } + } + + M0P_SYSCTRL->PLL_CR_f.FRSEL = pstcPLLCfg->enInFreq; + M0P_SYSCTRL->PLL_CR_f.FOSC = pstcPLLCfg->enOutFreq; + M0P_SYSCTRL->PLL_CR_f.DIVN = pstcPLLCfg->enPllMul; + M0P_SYSCTRL->PLL_CR_f.REFSEL = pstcPLLCfg->enPllClkSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 鍐呴儴浣庨熸椂閽熼鐜嘥RIM鍊煎姞杞 + ** \param [in] enRCLFreq 璁惧畾鐨凴CL鐩爣棰戠巼鍊 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq) +{ + M0P_SYSCTRL->RCL_CR_f.TRIM = *(RC_TRIM_BASE_ADDR + enRCLFreq); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 绯荤粺鏃堕挓锛圚CLK锛夊垎棰戣瀹 + ** \param [in] enHCLKDiv 鍒嗛璁惧畾鍊 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv) +{ + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.HCLK_PRS = enHCLKDiv; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 澶栬鏃堕挓锛圥CLK锛夊垎棰戣瀹 + ** \param [in] enPCLKDiv 鍒嗛璁惧畾鍊 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv) +{ + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.PCLK_PRS = enPCLKDiv; + + return Ok; +} + +///<< for Sysctrl_SetPeripheralGate() & Sysctrl_GetPeripheralGate() +static volatile boolean_t bDacPeriBac = FALSE; + +/** + ******************************************************************************* + ** \brief 璁剧疆澶栬鏃堕挓闂ㄦ帶寮鍏 + ** \param [in] enPeripheral 鐩爣澶栬 + ** \param [in] bFlag 浣胯兘寮鍏 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag) +{ + if(enPeripheral&0x20u) + { + enPeripheral &= ~0x20u; + SetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN1)), enPeripheral, bFlag); + + if((SysctrlPeripheralDac & ~0x20u) == enPeripheral) + { + bDacPeriBac = bFlag; + } + else + { + SetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN1)), (SysctrlPeripheralDac & ~0x20u), bDacPeriBac); + } + } + else + { + SetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN0)), enPeripheral, bFlag); + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 鑾峰緱澶栬鏃堕挓闂ㄦ帶寮鍏崇姸鎬 + ** \param [in] enPeripheral 鐩爣澶栬 + ** \retval TRUE 寮 + ** FALSE 鍏 + ******************************************************************************/ +boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral) +{ + if(enPeripheral&0x20u) + { + if(SysctrlPeripheralDac == enPeripheral) + { + return bDacPeriBac; + } + else + { + enPeripheral &= ~0x20u; + return GetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN1)), enPeripheral); + } + + } + else + { + return GetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN0)), enPeripheral); + } + +} + +/** + ******************************************************************************* + ** \brief 绯荤粺鍔熻兘璁惧畾 + ** \param [in] enFunc 绯荤粺鍔熻兘鏋氫妇绫诲瀷 + ** \param [in] bFlag 1-寮/0-鍏 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag) +{ + _SysctrlUnlock(); + SetBit((uint32_t)(&(M0P_SYSCTRL->SYSCTRL1)), enFunc, bFlag); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 璁惧畾RTC鏍″噯鏃堕挓棰戠巼 + ** \param [in] enRtcAdj 鏍″噯棰戠巼鍊 + ** \retval Ok 璁惧畾鎴愬姛 + ** 鍏朵粬 璁惧畾澶辫触 + ******************************************************************************/ +en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj) +{ + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL1_f.RTC_FREQ_ADJUST = enRtcAdj; + + return Ok; +} + +//@} // SysctrlGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/timer3.c b/driver/src/timer3.c new file mode 100644 index 0000000..c45059a --- /dev/null +++ b/driver/src/timer3.c @@ -0,0 +1,1368 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file timer3.c + ** + ** Common API of base timer. + ** @link Tiemr3 Group Some description @endlink + ** + ** - 2019-04-18 Husj First Version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "timer3.h" +/** + ******************************************************************************* + ** \addtogroup Tim3Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Timer3 涓柇鏍囧織鑾峰彇(妯″紡0/1/23) + ** + ** + ** \param [in] enTim3Irq 涓柇绫诲瀷 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Tim3_GetIntFlag(en_tim3_irq_type_t enTim3Irq) +{ + boolean_t bRetVal = FALSE; + uint32_t u32Val; + + u32Val = M0P_TIM3_MODE23->IFR; + bRetVal = (u32Val>>enTim3Irq) & 0x1; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Timer3 涓柇鏍囧織娓呴櫎(妯″紡0/1/23) + ** + ** + ** \param [in] enTim3Irq 涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_ClearIntFlag(en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ICLR = ~(1u<ICLR = 0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 涓柇浣胯兘(妯″紡0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_EnableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.UIE = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 涓柇绂佹(妯″紡0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_DisableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.UIE = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 涓柇浣胯兘(妯″紡1) + ** + ** + ** \param [in] enTim3Irq 涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_EnableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE1->M1CR_f.UIE = TRUE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE1->CR0_f.CIEA = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 涓柇绂佹(妯″紡1) + ** + ** + ** \param [in] enTim3Irq 涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_DisableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE1->M1CR_f.UIE = FALSE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE1->CR0_f.CIEA = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 涓柇浣胯兘(妯″紡23) + ** + ** + ** \param [in] enTim3Irq 涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_EnableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE23->M23CR_f.UIE = TRUE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEA = TRUE; + break; + case Tim3CB0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEB = TRUE; + break; + case Tim3CA1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEA = TRUE; + break; + case Tim3CB1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEB = TRUE; + break; + case Tim3CA2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEA = TRUE; + break; + case Tim3CB2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEB = TRUE; + break; + case Tim3BkIrq: + M0P_TIM3_MODE23->M23CR_f.BIE = TRUE; + break; + case Tim3TrigIrq: + M0P_TIM3_MODE23->M23CR_f.TIE = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 涓柇绂佹(妯″紡23) + ** + ** + ** \param [in] enTim3Irq 涓柇绫诲瀷 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_DisableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE23->M23CR_f.UIE = FALSE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEA = FALSE; + break; + case Tim3CB0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEB = FALSE; + break; + case Tim3CA1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEA = FALSE; + break; + case Tim3CB1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEB = FALSE; + break; + case Tim3CA2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEA = FALSE; + break; + case Tim3CB2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEB = FALSE; + break; + case Tim3BkIrq: + M0P_TIM3_MODE23->M23CR_f.BIE = FALSE; + break; + case Tim3TrigIrq: + M0P_TIM3_MODE23->M23CR_f.TIE = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 鍒濆鍖栭厤缃(妯″紡0) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_Init(stc_tim3_mode0_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.MODE = pstcCfg->enWorkMode; + M0P_TIM3_MODE0->M0CR_f.GATEP = pstcCfg->enGateP; + M0P_TIM3_MODE0->M0CR_f.GATE = pstcCfg->bEnGate; + M0P_TIM3_MODE0->M0CR_f.PRS = pstcCfg->enPRS; + M0P_TIM3_MODE0->M0CR_f.TOGEN = pstcCfg->bEnTog; + M0P_TIM3_MODE0->M0CR_f.CT = pstcCfg->enCT; + M0P_TIM3_MODE0->M0CR_f.MD = pstcCfg->enCntMode; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 鍚姩杩愯(妯″紡0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 鍋滄杩愯(妯″紡0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 绔彛杈撳嚭浣胯兘/绂佹璁惧畾(妯″紡0) + ** + ** + ** \param [in] bEnOutput 缈昏浆杈撳嚭璁惧畾 TRUE:浣胯兘, FALSE:绂佹 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Enable_Output(boolean_t bEnOutput) +{ + en_result_t enResult = Ok; + + + M0P_TIM3_MODE0->DTR_f.MOE = bEnOutput; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 缈昏浆浣胯兘/绂佹锛堜綆鐢靛钩锛夎瀹(妯″紡0) + ** + ** + ** \param [in] bEnTOG 缈昏浆杈撳嚭璁惧畾 TRUE:浣胯兘, FALSE:绂佹 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_EnTOG(boolean_t bEnTOG) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.TOGEN = bEnTOG; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16浣嶈鏁板櫒鍒濆艰缃(妯″紡0) + ** + ** + ** \param [in] u16Data CNT 16浣嶅垵鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16浣嶈鏁板艰幏鍙(妯″紡0) + ** + ** + ** \param [in] none + ** + ** \retval 16bits璁℃暟鍊 + *****************************************************************************/ +uint16_t Tim3_M0_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE0->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Timer3 閲嶈浇鍊艰缃(妯″紡0) + ** + ** + ** \param [in] u16Data 16bits閲嶈浇鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_ARRSet(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->ARR_f.ARR = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 32浣嶈鏁板櫒鍒濆艰缃(妯″紡0) + ** + ** + ** \param [in] u32Data 32浣嶅垵鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Cnt32Set(uint32_t u32Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->CNT32_f.CNT32 = u32Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 32浣嶈鏁板艰幏鍙(妯″紡0) + ** + ** + ** \param [in] none + ** + ** \retval 32bits璁℃暟鍊 + *****************************************************************************/ +uint32_t Tim3_M0_Cnt32Get(void) +{ + uint32_t u32CntData = 0; + + u32CntData = M0P_TIM3_MODE0->CNT32_f.CNT32; + + return u32CntData; +} + +/** + ***************************************************************************** + ** \brief Timer3 鍒濆鍖栭厤缃(妯″紡1) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_Init(stc_tim3_mode1_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.MODE = pstcCfg->enWorkMode; + M0P_TIM3_MODE1->M1CR_f.PRS = pstcCfg->enPRS; + M0P_TIM3_MODE1->M1CR_f.CT = pstcCfg->enCT; + M0P_TIM3_MODE1->M1CR_f.ONESHOT = pstcCfg->enOneShot; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 PWC 杈撳叆閰嶇疆(妯″紡1) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Input_Cfg(stc_tim3_pwc_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->MSCR_f.TS = pstcCfg->enTsSel; + M0P_TIM3_MODE1->MSCR_f.IA0S = pstcCfg->enIA0Sel; + M0P_TIM3_MODE1->MSCR_f.IB0S = pstcCfg->enIB0Sel; + M0P_TIM3_MODE1->FLTR_f.ETP = pstcCfg->enETRPhase; + M0P_TIM3_MODE1->FLTR_f.FLTET = pstcCfg->enFltETR; + M0P_TIM3_MODE1->FLTR_f.FLTA0 = pstcCfg->enFltIA0; + M0P_TIM3_MODE1->FLTR_f.FLTB0 = pstcCfg->enFltIB0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 PWC娴嬮噺杈规部璧峰缁撴潫閫夋嫨(妯″紡1) + ** + ** + ** \param [in] enEdgeSel pwc娴嬮噺璧峰缁堟鐢靛钩 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_PWC_Edge_Sel(en_tim3_m1cr_Edge_t enEdgeSel) +{ + en_result_t enResult = Ok; + + switch (enEdgeSel) + { + case 0: ///< 涓婂崌娌垮埌涓婂崌娌(鍛ㄦ湡) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 0; //涓婂崌娌 + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 0; //涓婂崌娌 + break; + case 1: ///< 涓嬮檷娌垮埌涓婂崌娌(浣庣數骞) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 1; //涓嬮檷娌 + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 0; //涓婂崌娌 + break; + case 2: ///< 涓婂崌娌垮埌涓嬮檷娌(楂樼數骞) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 0; //涓婂崌娌 + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 1; //涓嬮檷娌 + break; + case 3: ///< 涓嬮檷娌垮埌涓嬮檷娌(鍛ㄦ湡) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 1; //涓嬮檷娌 + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 1; //涓嬮檷娌 + break; + default: + ; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 鍚姩杩愯(妯″紡1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 鍋滄杩愯(妯″紡1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16浣嶈鏁板櫒鍒濆艰缃(妯″紡1) + ** + ** + ** \param [in] u16Data 16浣嶅垵鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16浣嶈鏁板艰幏鍙(妯″紡1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits璁℃暟鍊 + *****************************************************************************/ +uint16_t Tim3_M1_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE1->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Timer3 鑴夊啿瀹藉害娴嬮噺缁撴灉鏁板艰幏鍙(妯″紡1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits鑴夊啿瀹藉害娴嬮噺缁撴灉 + *****************************************************************************/ +uint16_t Tim3_M1_PWC_CapValueGet(void) +{ + uint16_t u16CapData = 0; + + u16CapData = M0P_TIM3_MODE1->CCR0A_f.CCR0A; + + return u16CapData; +} + +/** + ***************************************************************************** + ** \brief Timer3 鍒濆鍖栭厤缃(妯″紡23) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_Init(stc_tim3_mode23_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.MODE = pstcCfg->enWorkMode; + + M0P_TIM3_MODE23->M23CR_f.PRS = pstcCfg->enPRS; + M0P_TIM3_MODE23->M23CR_f.CT = pstcCfg->enCT; + M0P_TIM3_MODE23->M23CR_f.COMP = pstcCfg->enPWMTypeSel; + M0P_TIM3_MODE23->M23CR_f.PWM2S = pstcCfg->enPWM2sSel; + M0P_TIM3_MODE23->M23CR_f.ONESHOT = pstcCfg->bOneShot; + M0P_TIM3_MODE23->M23CR_f.URS = pstcCfg->bURSSel; + M0P_TIM3_MODE23->M23CR_f.DIR = pstcCfg->enCntDir; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 PWM杈撳嚭浣胯兘(妯″紡23) + ** + ** + ** \param [in] bEnOutput PWM杈撳嚭浣胯兘/绂佹璁惧畾 + ** \param [in] bEnAutoOutput PWM鑷姩杈撳嚭浣胯兘/绂佹璁惧畾 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.MOE = bEnOutput; + M0P_TIM3_MODE23->DTR_f.AOE = bEnAutoOutput; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief Timer3 鍚姩杩愯(妯″紡23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 鍋滄杩愯(妯″紡23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 閲嶈浇鍊艰缃(妯″紡23) + ** + ** + ** \param [in] u16Data 16bits閲嶈浇鍊 + ** \param [in] bArrBufEn ARR閲嶈浇缂撳瓨浣胯兘TRUE/绂佹FALSE + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ARR_f.ARR = u16Data; + M0P_TIM3_MODE23->M23CR_f.BUFPEN = bArrBufEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16浣嶈鏁板櫒鍒濆艰缃(妯″紡23) + ** + ** + ** \param [in] u16Data 16浣嶅垵鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16浣嶈鏁板艰幏鍙(妯″紡23) + ** + ** + ** \param [in] none + ** + ** \retval 16bits璁℃暟鍊 + *****************************************************************************/ +uint16_t Tim3_M23_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE23->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Timer3 姣旇緝鎹曡幏瀵勫瓨鍣–CRxA/CCRxB璁剧疆(妯″紡23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB璁惧畾 + ** \param [in] u16Data CCRxA/CCRxB 16浣嶅垵濮嬪 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_CCR_Set(en_tim3_m23_ccrx_t enCCRSel, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + if(Tim3CCR0A == enCCRSel) + { + M0P_TIM3_MODE23->CCR0A_f.CCR0A = u16Data; + } + else if(Tim3CCR0B == enCCRSel) + { + M0P_TIM3_MODE23->CCR0B_f.CCR0B = u16Data; + } + else if(Tim3CCR1A == enCCRSel) + { + M0P_TIM3_MODE23->CCR1A_f.CCR1A = u16Data; + } + else if(Tim3CCR1B == enCCRSel) + { + M0P_TIM3_MODE23->CCR1B_f.CCR1B = u16Data; + } + else if(Tim3CCR2A == enCCRSel) + { + M0P_TIM3_MODE23->CCR2A_f.CCR2A = u16Data; + } + else if(Tim3CCR2B == enCCRSel) + { + M0P_TIM3_MODE23->CCR2B_f.CCR2B = u16Data; + } + else + { + enResult = Error; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 姣旇緝鎹曡幏瀵勫瓨鍣–CRxA/CCRxB璇诲彇(妯″紡23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB璁惧畾 + ** + ** \retval 16bitsCCRxA/CCRxB鎹曡幏鍊 + *****************************************************************************/ +uint16_t Tim3_M23_CCR_Get(en_tim3_m23_ccrx_t enCCRSel) +{ + uint16_t u16Data = 0; + + if(Tim3CCR0A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR0A_f.CCR0A; + } + else if(Tim3CCR0B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR0B_f.CCR0B; + } + else if(Tim3CCR1A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR1A_f.CCR1A; + } + else if(Tim3CCR1B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR1B_f.CCR1B; + } + else if(Tim3CCR2A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR2A_f.CCR2A; + } + else if(Tim3CCR2B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR2B_f.CCR2B; + } + else + { + u16Data = 0; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief Timer3 PWM浜掕ˉ杈撳嚭妯″紡涓嬶紝GATE鍔熻兘閫夋嫨(妯″紡23) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_GateFuncSel(stc_tim3_m23_gate_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CSG = pstcCfg->enGateFuncSel; + M0P_TIM3_MODE23->M23CR_f.CRG = pstcCfg->bGateRiseCap; + M0P_TIM3_MODE23->M23CR_f.CFG = pstcCfg->bGateFallCap; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 涓讳粠妯″紡閰嶇疆(妯″紡23) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_MasterSlave_Set(stc_tim3_m23_master_slave_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->MSCR_f.MSM = pstcCfg->enMasterSlaveSel; + M0P_TIM3_MODE23->MSCR_f.MMS = pstcCfg->enMasterSrc; + M0P_TIM3_MODE23->MSCR_f.SMS = pstcCfg->enSlaveModeSel; + M0P_TIM3_MODE23->MSCR_f.TS = pstcCfg->enTsSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 CHxA/CHxB姣旇緝閫氶亾鎺у埗(妯″紡23) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** \param [in] enTim3Chx Timer3閫氶亾(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_PortOutput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_compare_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + switch (enTim3Chx) + { + case Tim3CH0: + M0P_TIM3_MODE23->CRCH0_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA0 = pstcCfg->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH0_f.BUFEA = pstcCfg->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcCfg->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH0_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB0 = pstcCfg->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH0_f.BUFEB = pstcCfg->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH0_f.CISB = pstcCfg->enCHxBCmpIntSel; + break; + case Tim3CH1: + M0P_TIM3_MODE23->CRCH1_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA1_FLTA1 = pstcCfg->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA1 = pstcCfg->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH1_f.BUFEA = pstcCfg->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcCfg->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH1_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB1_FLTB1 = pstcCfg->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB1 = pstcCfg->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH1_f.BUFEB = pstcCfg->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH1_f.CISB = pstcCfg->enCHxBCmpIntSel; + break; + case Tim3CH2: + M0P_TIM3_MODE23->CRCH2_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA2_FLTA2 = pstcCfg->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA2 = pstcCfg->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH2_f.BUFEA = pstcCfg->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcCfg->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH2_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB2_FLTB2 = pstcCfg->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB2 = pstcCfg->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH2_f.BUFEB = pstcCfg->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH2_f.CISB = pstcCfg->enCHxBCmpIntSel; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 CHxA/CHxB杈撳叆鎺у埗(妯″紡23) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** \param [in] enTim3Chx Timer3閫氶亾(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_PortInput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + switch (enTim3Chx) + { + case Tim3CH0: + M0P_TIM3_MODE23->CRCH0_f.CSA = 1; + M0P_TIM3_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcCfg->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA0 = pstcCfg->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH0_f.CSB = 1; + M0P_TIM3_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcCfg->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB0 = pstcCfg->enCHxBPolarity; + break; + case Tim3CH1: + M0P_TIM3_MODE23->CRCH1_f.CSA = 1; + M0P_TIM3_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcCfg->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA1_FLTA1 = pstcCfg->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA1 = pstcCfg->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH1_f.CSB = 1; + M0P_TIM3_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcCfg->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB1_FLTB1 = pstcCfg->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB1 = pstcCfg->enCHxBPolarity; + break; + case Tim3CH2: + M0P_TIM3_MODE23->CRCH2_f.CSA = 1; + M0P_TIM3_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcCfg->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA2_FLTA2 = pstcCfg->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA2 = pstcCfg->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH2_f.CSB = 1; + M0P_TIM3_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcCfg->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB2_FLTB2 = pstcCfg->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB2 = pstcCfg->enCHxBPolarity; + break; + default: + enResult = Error; + break; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 ERT杈撳叆鎺у埗(妯″紡23) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_ETRInput_Cfg(stc_tim3_m23_etr_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->FLTR_f.ETP = pstcCfg->enETRPolarity; + M0P_TIM3_MODE23->FLTR_f.FLTET = pstcCfg->enETRFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 鍒硅溅BK杈撳叆鎺у埗(妯″紡23) + ** + ** + ** \param [in] pstcBkCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_BrakeInput_Cfg(stc_tim3_m23_bk_input_cfg_t* pstcBkCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.BKE = pstcBkCfg->bEnBrake; + M0P_TIM3_MODE23->DTR_f.VCE = pstcBkCfg->bEnVCBrake; + M0P_TIM3_MODE23->DTR_f.SAFEEN = pstcBkCfg->bEnSafetyBk; + M0P_TIM3_MODE23->DTR_f.BKSEL = pstcBkCfg->bEnBKSync; + M0P_TIM3_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcBkCfg->enBkCH0AStat; + M0P_TIM3_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcBkCfg->enBkCH0BStat; + M0P_TIM3_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcBkCfg->enBkCH1AStat; + M0P_TIM3_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcBkCfg->enBkCH1BStat; + M0P_TIM3_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcBkCfg->enBkCH2AStat; + M0P_TIM3_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcBkCfg->enBkCH2BStat; + M0P_TIM3_MODE23->FLTR_f.BKP = pstcBkCfg->enBrakePolarity; + M0P_TIM3_MODE23->FLTR_f.FLTBK = pstcBkCfg->enBrakeFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 瑙﹀彂ADC鎺у埗(妯″紡23) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_TrigADC_Cfg(stc_tim3_m23_adc_trig_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ADTR_f.ADTE = pstcCfg->bEnTrigADC; + M0P_TIM3_MODE23->ADTR_f.UEVE = pstcCfg->bEnUevTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA0E = pstcCfg->bEnCH0ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB0E = pstcCfg->bEnCH0BCmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA1E = pstcCfg->bEnCH1ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB1E = pstcCfg->bEnCH1BCmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA2E = pstcCfg->bEnCH2ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB2E = pstcCfg->bEnCH2BCmpTrigADC; + return enResult; +} + +/** + ***************************************************************************** +** \brief Timer3 姝诲尯鍔熻兘(妯″紡23) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_DT_Cfg(stc_tim3_m23_dt_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.DTEN = pstcCfg->bEnDeadTime; + M0P_TIM3_MODE23->DTR_f.DTR = pstcCfg->u8DeadTimeValue; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Timer3 閲嶅鍛ㄦ湡璁剧疆(妯″紡23) + ** + ** + ** \param [in] u8ValidPeriod 閲嶅鍛ㄦ湡鍊 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_SetValidPeriod(uint8_t u8ValidPeriod) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->RCR_f.RCR = u8ValidPeriod; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 OCREF娓呴櫎鍔熻兘(妯″紡23) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_OCRefClr(stc_tim3_m23_OCREF_Clr_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.OCCS = pstcCfg->enOCRefClrSrcSel; + M0P_TIM3_MODE23->M23CR_f.OCCE = pstcCfg->bVCClrEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 浣胯兘DMA浼犺緭(妯″紡23) + ** + ** + ** \param [in] pstcCfg 鍒濆鍖栭厤缃粨鏋勪綋鎸囬拡 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnDMA(stc_tim3_m23_trig_dma_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.UDE = pstcCfg->bUevTrigDMA; + M0P_TIM3_MODE23->M23CR_f.TDE = pstcCfg->bTITrigDMA; + M0P_TIM3_MODE23->CRCH0_f.CDEA = pstcCfg->bCmpA0TrigDMA; + M0P_TIM3_MODE23->CRCH0_f.CDEB = pstcCfg->bCmpB0TrigDMA; + M0P_TIM3_MODE23->CRCH1_f.CDEA = pstcCfg->bCmpA1TrigDMA; + M0P_TIM3_MODE23->CRCH1_f.CDEB = pstcCfg->bCmpB1TrigDMA; + M0P_TIM3_MODE23->CRCH2_f.CDEA = pstcCfg->bCmpA2TrigDMA; + M0P_TIM3_MODE23->CRCH2_f.CDEB = pstcCfg->bCmpB2TrigDMA; + M0P_TIM3_MODE23->MSCR_f.CCDS = pstcCfg->enCmpUevTrigDMA; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 鎹曡幏姣旇緝A杞欢瑙﹀彂(妯″紡23) + ** + ** + ** \param [in] enTim3Chx Timer3閫氶亾(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrigCapCmpA(en_tim3_channel_t enTim3Chx) +{ + en_result_t enResult = Ok; + if(Tim3CH0 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH0_f.CCGA = TRUE; + } + else if(Tim3CH1 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH1_f.CCGA = TRUE; + } + else if(Tim3CH2 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH2_f.CCGA = TRUE; + } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 鎹曡幏姣旇緝B杞欢瑙﹀彂(妯″紡23) + ** + ** + ** \param [in] enTim3Chx Timer3閫氶亾(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrigCapCmpB(en_tim3_channel_t enTim3Chx) +{ + en_result_t enResult = Ok; + if(Tim3CH0 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH0_f.CCGB = TRUE; + } + else if(Tim3CH1 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH1_f.CCGB = TRUE; + } + else if(Tim3CH2 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH2_f.CCGB = TRUE; + } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 杞欢鏇存柊浣胯兘(妯″紡23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwUev(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.UG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 杞欢瑙﹀彂浣胯兘(妯″紡23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrig(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.TG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 杞欢鍒硅溅浣胯兘(妯″紡23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwBk(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.BG = TRUE; + + return enResult; +} + +//@} // Tim3Group + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/trim.c b/driver/src/trim.c new file mode 100644 index 0000000..91d1b97 --- /dev/null +++ b/driver/src/trim.c @@ -0,0 +1,248 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file trim.c + ** + ** Common API of trim. + ** @link trimGroup Some description @endlink + ** + ** - 2017-05-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "trim.h" +/** + ******************************************************************************* + ** \addtogroup TrimGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#define IS_VALID_TRIMINT(x) (TrimStop == (x) ||\ + TrimCalCntOf == (x) ||\ + TrimXTLFault == (x) ||\ + TrimXTHFault == (x) ||\ + TrimPLLFault == (x)) + + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ***************************************************************************** + ** \brief Trim涓柇鏍囧織鑾峰彇 + ** + ** + ** \param [in] enIntType 涓柇绫诲瀷锛圧efStop銆丆alCntOf銆乆TAL32KFault銆乆TAL32MFault锛 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Trim_GetIntFlag(en_trim_inttype_t enIntType) +{ + ASSERT(IS_VALID_TRIMINT(enIntType)); + + if(M0P_CLK_TRIM->IFR&enIntType) + { + return TRUE; + } + else + { + return FALSE; + } + +} + +/** + ***************************************************************************** + ** \brief Trim涓柇鏍囧織娓呴櫎 + ** + ** + ** \param [in] enIntType 涓柇绫诲瀷锛圧efStop銆丆alCntOf銆乆TAL32KFault銆乆TAL32MFault锛 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_ClearIntFlag(en_trim_inttype_t enIntType) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_TRIMINT(enIntType)); + + M0P_CLK_TRIM->ICLR &= ~(uint32_t)enIntType; + + return enResult; +} + + + +/** + ***************************************************************************** + ** \brief Trim涓柇浣胯兘 + ** + ** + ** + ** \retval Null + *****************************************************************************/ +void Trim_EnableIrq (void) +{ + M0P_CLK_TRIM->CR_f.IE = TRUE; +} + +/** + ***************************************************************************** + ** \brief Trim涓柇绂佹 + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +void Trim_DisableIrq(void) +{ + M0P_CLK_TRIM->CR_f.IE = FALSE; +} + +/** + ***************************************************************************** + ** \brief Trim鍒濆鍖栭厤缃 + ** + ** + ** \param [in] pstcCfg Trim閰嶇疆缁撴瀯浣撴寚閽 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_Init(stc_trim_cfg_t* pstcCfg) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR = 0; + + M0P_CLK_TRIM->CR = (uint32_t)pstcCfg->enCALCLK | + (uint32_t)pstcCfg->enREFCLK | + (uint32_t)pstcCfg->enMON; + + M0P_CLK_TRIM->REFCON = pstcCfg->u32RefCon; + M0P_CLK_TRIM->CALCON = pstcCfg->u32CalCon; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trim鏍″噯/鐩戞祴鍚姩杩愯 + ** + ** + ** + ** \retval Null + *****************************************************************************/ +void Trim_Run(void) +{ + M0P_CLK_TRIM->CR_f.TRIM_START = TRUE; +} + +/** + ***************************************************************************** + ** \brief Trim鏍″噯/鐩戞祴鍋滄 + ** + ** + ** + ** + ** \retval Null + *****************************************************************************/ +void Trim_Stop(void) +{ + M0P_CLK_TRIM->CR_f.TRIM_START = FALSE; +} + +/** + ***************************************************************************** + ** \brief Trim鍙傝冭鏁板櫒璁℃暟鍊艰幏鍙 + ** + ** + ** \retval u32Data 鍙傝冭鏁板櫒璁℃暟鍊 + *****************************************************************************/ +uint32_t Trim_RefCntGet(void) +{ + return (uint32_t)M0P_CLK_TRIM->REFCNT; +} + +/** + ***************************************************************************** + ** \brief Trim鏍″噯璁℃暟鍣ㄨ鏁板艰幏鍙 + ** + ** + ** + ** + ** \retval u32Data 鏍″噯璁℃暟鍣ㄨ鏁板 + *****************************************************************************/ +uint32_t Trim_CalCntGet(void) +{ + return (uint32_t)M0P_CLK_TRIM->CALCNT; +} + +//@} // TrimGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/trng.c b/driver/src/trng.c new file mode 100644 index 0000000..3cc7842 --- /dev/null +++ b/driver/src/trng.c @@ -0,0 +1,191 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file rng.c + ** + ** Common API of rng. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "trng.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief 闅忔満鏁板垵濮嬪寲(涓婄數绗竴娆＄敓鎴愰殢鏈烘暟锛 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Trng_Init(void) +{ + //==>>鐢熸垚64bits闅忔満鏁帮紙涓婄數绗竴娆★級 + M0P_TRNG->CR_f.RNGCIR_EN = 1; + //妯″紡閰嶇疆0 + M0P_TRNG->MODE_f.LOAD = 1; + M0P_TRNG->MODE_f.FDBK = 1; + M0P_TRNG->MODE_f.CNT = 6; + //鐢熸垚闅忔満鏁0 + M0P_TRNG->CR_f.RNG_RUN = 1; + while(M0P_TRNG->CR_f.RNG_RUN) + { + ; + } + + //妯″紡閰嶇疆1 + M0P_TRNG->MODE_f.LOAD = 0; + M0P_TRNG->MODE_f.FDBK = 0; + M0P_TRNG->MODE_f.CNT = 4; + //鐢熸垚闅忔満鏁1 + M0P_TRNG->CR_f.RNG_RUN = 1; + while(M0P_TRNG->CR_f.RNG_RUN) + { + ; + } + + //鍏抽棴闅忔満婧愮數璺紝鑺傜渷鍔熻 + M0P_TRNG->CR_f.RNGCIR_EN = 0; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief 鐢熸垚闅忔満鏁帮紙闈炰笂鐢电涓娆＄敓鎴愰殢鏈烘暟锛 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Trng_Generate(void) +{ + //==>>鐢熸垚64bits闅忔満鏁帮紙闈炰笂鐢电涓娆＄敓鎴愶級 + M0P_TRNG->CR_f.RNGCIR_EN = 1; + + //妯″紡閰嶇疆0 + M0P_TRNG->MODE_f.LOAD = 0; + M0P_TRNG->MODE_f.FDBK = 1; + M0P_TRNG->MODE_f.CNT = 6; + //鐢熸垚闅忔満鏁0 + M0P_TRNG->CR_f.RNG_RUN = 1; + while(M0P_TRNG->CR_f.RNG_RUN) + { + ; + } + + //妯″紡閰嶇疆1 + M0P_TRNG->MODE_f.FDBK = 0; + M0P_TRNG->MODE_f.CNT = 4; + M0P_TRNG->MODE_f.CNT = 4; + //鐢熸垚闅忔満鏁1 + M0P_TRNG->CR_f.RNG_RUN = 1; + while(M0P_TRNG->CR_f.RNG_RUN) + { + ; + } + + //鍏抽棴闅忔満婧愮數璺紝鑺傜渷鍔熻 + M0P_TRNG->CR_f.RNGCIR_EN = 0; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief 闅忔満鏁拌幏鍙 + ** + ** \retval data0 + *****************************************************************************/ +uint32_t Trng_GetData0(void) +{ + return M0P_TRNG->DATA0; +} + +/** + ***************************************************************************** + ** \brief 闅忔満鏁拌幏鍙 + ** + ** \retval data1 + *****************************************************************************/ +uint32_t Trng_GetData1(void) +{ + return M0P_TRNG->DATA1; +} + +//@} // TrngGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/driver/src/uart.c b/driver/src/uart.c new file mode 100644 index 0000000..2dee506 --- /dev/null +++ b/driver/src/uart.c @@ -0,0 +1,405 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file uart.c + ** + ** UART function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "uart.h" +/** + ****************************************************************************** + ** \addtogroup UartGroup + ******************************************************************************/ +//@{ +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief UART閫氫俊涓柇浣胯兘鍑芥暟璁剧疆 + ** + ** \param [in] UARTx閫氶亾鍙凤紝enIrqSel鍙戦乷r鎺ユ敹涓柇浣胯兘 + ** + ** \retval OK閰嶇疆鎴愬姛 + ** \retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t Uart_EnableIrq(M0P_UART_TypeDef* UARTx, en_uart_irq_sel_t enIrqSel) +{ + SetBit((uint32_t)(&(UARTx->SCON)), enIrqSel, TRUE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief UART閫氫俊涓柇绂佹鍑芥暟璁剧疆 + ** + ** \param [in] UARTx閫氶亾鍙凤紝enIrqSel鍙戦乷r鎺ユ敹涓柇绂佹 + ** + ** \retval OK閰嶇疆鎴愬姛 + ** \retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t Uart_DisableIrq(M0P_UART_TypeDef* UARTx, en_uart_irq_sel_t enIrqSel) +{ + SetBit((uint32_t)(&(UARTx->SCON)), enIrqSel, FALSE); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART閫氶亾澶氫富鏈烘ā寮忛厤缃 + ** + ** \param [in] UARTx閫氶亾鍙凤紝stcMultiCfg澶氫富鏈烘ā寮忕粨鏋 + ** + ** \retval OK閰嶇疆鎴愬姛 + ** \retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t Uart_SetMultiMode(M0P_UART_TypeDef* UARTx, stc_uart_multimode_t* pstcMultiCfg) +{ + if(NULL != pstcMultiCfg) + { + UARTx->SCON_f.ADRDET = TRUE; + UARTx->SADDR = pstcMultiCfg->u8SlaveAddr; + UARTx->SADEN = pstcMultiCfg->u8SaddEn; + + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART鍗曠嚎鍗婂弻宸ユā寮忎娇鑳 + ** + ** \param [in] UARTx 閫氶亾鍙 + ** + ** \retval Null + ******************************************************************************/ +void Uart_HdModeEnable(M0P_UART_TypeDef* UARTx) +{ + UARTx->SCON_f.HDSEL = TRUE; +} + +/** + ****************************************************************************** + ** \brief UART鍗曠嚎鍗婂弻宸ユā寮忓叧闂 + ** + ** \param [in] UARTx 閫氶亾鍙 + ** + ** \retval Null + ******************************************************************************/ +void Uart_HdModeDisable(M0P_UART_TypeDef* UARTx) +{ + UARTx->SCON_f.HDSEL = FALSE; +} + +/** + ****************************************************************************** + ** \brief UART閫氶亾澶氭満妯″紡鍙戦佹暟鎹/鍦板潃甯ч厤缃甌B8 + ** + ** \param [in] UARTx 閫氶亾鍙 + ** \param [in] TRUE-TB8涓哄湴鍧甯ф爣蹇楋紱FALSE-TB8涓烘暟鎹抚鏍囧織锛 + ** + ** \retval Null + ******************************************************************************/ +void Uart_SetTb8(M0P_UART_TypeDef* UARTx, boolean_t bTB8Value) +{ + UARTx->SCON_f.B8CONT = bTB8Value; + +} + +/** + ****************************************************************************** + ** \brief 鑾峰彇RB8鏁板 + ** + ** \param [in] UARTx閫氶亾鍙 + ** + ** \retval RB8 + ******************************************************************************/ +boolean_t Uart_GetRb8(M0P_UART_TypeDef* UARTx) +{ + return (UARTx->SBUF_f.DATA8); +} + +/** + ****************************************************************************** + ** \brief UART閫氶亾澶氫富鏈烘ā寮忎粠鏈哄湴鍧閰嶇疆鍑芥暟 + ** + ** \param [in] UARTx閫氶亾鍙凤紝addr鍦板潃 + ** + ** \retval OK閰嶇疆鎴愬姛 + ** \retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t Uart_SetSaddr(M0P_UART_TypeDef* UARTx,uint8_t u8Addr) +{ + UARTx->SADDR = u8Addr; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART閫氶亾鍙戦佹垨鎺ユ敹绛夊姛鑳戒娇鑳借缃 + ** + ** \param [in] UARTx閫氶亾鍙凤紝enFunc鍔熻兘 + ** + ** \retval OK閰嶇疆鎴愬姛 + ** \retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t Uart_EnableFunc(M0P_UART_TypeDef* UARTx, en_uart_func_t enFunc) +{ + SetBit((uint32_t)(&(UARTx->SCON)), enFunc, TRUE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief UART閫氶亾鍙戦佹垨鎺ユ敹绛夊姛鑳界姝㈣缃 + ** + ** \param [in] UARTx閫氶亾鍙凤紝enFunc鍔熻兘 + ** + ** \retval OK閰嶇疆鎴愬姛 + ** \retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t Uart_DisableFunc(M0P_UART_TypeDef* UARTx, en_uart_func_t enFunc) +{ + SetBit((uint32_t)(&(UARTx->SCON)), enFunc, FALSE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief UART閫氶亾閫氫俊鐘舵佽幏鍙 + ** + ** \param [in] UARTx閫氶亾鍙 + ** + ** \retval 鐘舵佸 + ******************************************************************************/ +uint8_t Uart_GetIsr(M0P_UART_TypeDef* UARTx) +{ + return (UARTx->ISR); +} + +/** + ****************************************************************************** + ** \brief UART閫氶亾閫氫俊鐘舵佽幏鍙 + ** + ** \param [in] UARTx閫氶亾鍙凤紝enStatus鑾峰彇鍝釜鐘舵 + ** + ** \retval 鐘舵佸 + ******************************************************************************/ +boolean_t Uart_GetStatus(M0P_UART_TypeDef* UARTx, en_uart_status_t enStatus) +{ + boolean_t bStatus = FALSE; + + + ASSERT(IS_VALID_STATUS(enStatus)); + + bStatus = GetBit((uint32_t)(&(UARTx->ISR)), enStatus); + + return bStatus; +} +/** + ****************************************************************************** + ** \brief UART閫氶亾閫氫俊鐘舵佹竻闄 + ** + ** \param [in] UARTx閫氶亾鍙 + ** + ** \retval OK + ** \retval ErrorInvalidParameter娓呴櫎澶辫触 + ******************************************************************************/ +en_result_t Uart_ClrIsr(M0P_UART_TypeDef* UARTx) +{ + UARTx->ICR = 0u; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART閫氶亾閫氫俊鐘舵佹竻闄 + ** + ** \param [in] UARTx閫氶亾鍙凤紝enStatus娓呴櫎鍝釜鐘舵 + ** + ** \retval OK + ** \retval ErrorInvalidParameter娓呴櫎澶辫触 + ******************************************************************************/ +en_result_t Uart_ClrStatus(M0P_UART_TypeDef* UARTx,en_uart_status_t enStatus) +{ + ASSERT(IS_VALID_STATUS(enStatus)); + + SetBit((uint32_t)(&(UARTx->ICR)), enStatus, FALSE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief UART閫氶亾鍙戦佹暟鎹嚱鏁,鏌ヨ鏂瑰紡璋冪敤姝ゅ嚱鏁帮紝涓柇鏂瑰紡鍙戦佷笉閫傜敤 + ** + ** \param [in] UARTx閫氶亾鍙凤紝Data鍙戦佹暟鎹 + ** + ** \retval Ok鍙戦佹垚鍔 + ** \retval ErrorInvalidParameter鍙戦佸け璐 + ******************************************************************************/ +en_result_t Uart_SendDataPoll(M0P_UART_TypeDef* UARTx, uint8_t u8Data) +{ + while(FALSE == Uart_GetStatus(UARTx,UartTxe)) + {} + UARTx->SBUF_f.DATA = u8Data; + while(FALSE == Uart_GetStatus(UARTx,UartTC)) + {} + Uart_ClrStatus(UARTx,UartTC); + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART閫氶亾鍙戦佹暟鎹嚱鏁,涓柇鏂瑰紡璋冪敤姝ゅ嚱鏁 + ** + ** \param [in] UARTx閫氶亾鍙凤紝Data鍙戦佹暟鎹 + ** + ** \retval Ok鍙戦佹垚鍔 + ** \retval ErrorInvalidParameter鍙戦佸け璐 + ******************************************************************************/ +en_result_t Uart_SendDataIt(M0P_UART_TypeDef* UARTx, uint8_t u8Data) +{ + UARTx->SBUF_f.DATA = u8Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART閫氶亾鎺ユ敹鏁版嵁鍑芥暟 + ** + ** \param [in] UARTx閫氶亾鍙 + ** + ** \retval 鎺ユ敹鏁版嵁 + ******************************************************************************/ +uint8_t Uart_ReceiveData(M0P_UART_TypeDef* UARTx) +{ + return (UARTx->SBUF_f.DATA); +} + +/** + ****************************************************************************** + ** \brief UART閫氶亾鍒濆鍖栧嚱鏁 + ** + ** \param [in] UARTx閫氶亾鍙凤紝pstcCfg鍒濆鍖栫粨鏋勪綋 @ref stc_uart_cfg_t + ** + ** \retval OK閰嶇疆鎴愬姛 + ** \retval ErrorInvalidParameter閰嶇疆澶辫触 + ******************************************************************************/ +en_result_t Uart_Init(M0P_UART_TypeDef* UARTx, stc_uart_cfg_t* pstcCfg) +{ + en_result_t enRet = Error; + uint32_t u32Over[2] = {0x4, 0x3}; + uint16_t u16OverShift; + float32_t f32Scnt=0; + + if(NULL == pstcCfg) + { + return ErrorInvalidParameter; + } + + UARTx->SCON = 0; + + UARTx->SCON = (uint32_t)pstcCfg->enStopBit | + (uint32_t)pstcCfg->enMmdorCk | + (uint32_t)pstcCfg->stcBaud.enClkDiv | + (uint32_t)pstcCfg->enRunMode; + + if((UartMskMode1 == pstcCfg->enRunMode) || (UartMskMode3 == pstcCfg->enRunMode)) + { + u16OverShift = u32Over[pstcCfg->stcBaud.enClkDiv/UartMsk8Or16Div]; + f32Scnt = (float32_t)(pstcCfg->stcBaud.u32Pclk)/(float32_t)(pstcCfg->stcBaud.u32Baud<SCNT = (uint16_t)(float32_t)(f32Scnt + 0.5f); + Uart_EnableFunc(UARTx,UartRenFunc); ///<浣胯兘鏀跺彂 + } + + + + enRet = Ok; + return enRet; +} + +/** + ****************************************************************************** + ** \brief UART鍙戦佸瓧绗︿覆 + ** + ** \param [in] UARTx閫氶亾鍙凤紝SendDataString瑕佸彂閫佺殑瀛楃涓 + ** + ** \retval + ** \retval + ******************************************************************************/ +void USART_SendString(M0P_UART_TypeDef* USARTx,uint16_t Len, uint8_t *SendDataString) +{ + int i = 0; + while(i < Len) //瀛楃涓茬粨鏉熺 + { + Uart_SendDataPoll(USARTx,SendDataString[i]); //姣忔鍙戦佸瓧绗︿覆鐨勪竴涓瓧绗 + //Uart_ClrStatus(USARTx, UartTC); //鍙戦佸瓧绗﹀悗娓呯┖鏍囧織浣 + i++; + } +} + + +//@} // UartGroup diff --git a/driver/src/vc.c b/driver/src/vc.c new file mode 100644 index 0000000..8e09495 --- /dev/null +++ b/driver/src/vc.c @@ -0,0 +1,298 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file vc.c + ** + ** voltage comparator driver API. + ** @link VC Group Some description @endlink + ** + ** - 2019-04-10 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "vc.h" + +/** + ****************************************************************************** + ** \addtogroup VcGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** +****************************************************************************** + ** \brief 閰嶇疆VC涓柇瑙﹀彂鏂瑰紡 + ** + ** @param Channelx : VcChannelx x=0銆1銆2 + ** @param enSel : VcIrqRise銆乂cIrqFall銆乂cIrqHigh + ** \retval 鏃 + ** +******************************************************************************/ +void Vc_CfgItType(en_vc_channel_t Channelx, en_vc_irq_sel_t ItType) +{ + stc_vc_vc0_cr_field_t *stcVcnCr; + switch(Channelx) + { + case VcChannel0: + stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC0_CR_f; + break; + case VcChannel1: + stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC1_CR_f; + break; + case VcChannel2: + stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC2_CR_f; + break; + default: + break; + } + switch (ItType) + { + case VcIrqNone: + stcVcnCr->RISING = 0u; + stcVcnCr->FALLING = 0u; + stcVcnCr->LEVEL = 0u; + break; + case VcIrqRise: + stcVcnCr->RISING = 1u; + break; + case VcIrqFall: + stcVcnCr->FALLING = 1u; + break; + case VcIrqHigh: + stcVcnCr->LEVEL = 1u; + break; + default: + break; + } +} + +/** +****************************************************************************** + ** \brief VC 涓柇浣胯兘涓庣姝 + ** + ** @param Channelx : VcChannelx x=0銆1銆2 + ** @param NewStatus : TRUE 鎴 FALSE + ** \retval 鏃 + ** +******************************************************************************/ +void Vc_ItCfg(en_vc_channel_t Channelx, boolean_t NewStatus) +{ + switch(Channelx) + { + case VcChannel0: + SetBit((uint32_t)(&(M0P_VC->VC0_CR)), 15, NewStatus); + break; + case VcChannel1: + SetBit((uint32_t)(&(M0P_VC->VC1_CR)), 15, NewStatus); + break; + case VcChannel2: + SetBit((uint32_t)(&(M0P_VC->VC2_CR)), 15, NewStatus); + break; + default: + break; + } +} + +/** +****************************************************************************** + ** \brief VC 姣旇緝缁撴灉鑾峰彇锛屽寘鍚腑鏂爣蹇椾綅鍜屾护娉㈢粨鏋 + ** + ** @param Result : 鎵瑕佽鍙栫殑缁撴灉 + ** \retval TRUE 鎴 FALSE + ** +******************************************************************************/ +boolean_t Vc_GetItStatus(en_vc_ifr_t Result) +{ + boolean_t bFlag; + bFlag = GetBit((uint32_t)(&(M0P_VC->IFR)), Result); + return bFlag; +} + +/** +****************************************************************************** + ** \brief VC 娓呴櫎涓柇鏍囧織浣 + ** + ** @param NewStatus : Vc0_Intf銆乂c1_Intf銆乂c2_Intf + ** \retval 鏃 + ** +******************************************************************************/ +void Vc_ClearItStatus(en_vc_ifr_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_VC->IFR)), NewStatus, 0); +} + +/** +****************************************************************************** + ** \brief VC 閰嶇疆DAC鐩稿叧鐨勫唴瀹 VC_CR涓 VC_REF2P5_SEL VC_DIV_EN VC_DIV + ** + ** @param pstcDacCfg : + ** \retval Ok 鎴 ErrorInvalidParameter + ** +******************************************************************************/ +en_result_t Vc_DacInit(stc_vc_dac_cfg_t *pstcDacCfg) +{ + if (NULL == pstcDacCfg) + { + return ErrorInvalidParameter; + } + + M0P_VC->CR_f.DIV_EN = pstcDacCfg->bDivEn; + M0P_VC->CR_f.REF2P5_SEL = pstcDacCfg->enDivVref; + + if (pstcDacCfg->u8DivVal < 0x40) + { + M0P_VC->CR_f.DIV = pstcDacCfg->u8DivVal; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** +****************************************************************************** + ** \brief VC閫氶亾鍒濆鍖 + ** + ** @param pstcDacCfg : + ** \retval 鏃 + ** +******************************************************************************/ +void Vc_Init(stc_vc_channel_cfg_t *pstcChannelCfg) +{ + if (VcChannel0 == pstcChannelCfg->enVcChannel) + { + M0P_VC->CR_f.VC0_HYS_SEL = pstcChannelCfg->enVcCmpDly; + M0P_VC->CR_f.VC0_BIAS_SEL = pstcChannelCfg->enVcBiasCurrent; + M0P_VC->VC0_CR_f.DEBOUNCE_TIME = pstcChannelCfg->enVcFilterTime; + M0P_VC->VC0_CR_f.P_SEL = pstcChannelCfg->enVcInPin_P; + M0P_VC->VC0_CR_f.N_SEL = pstcChannelCfg->enVcInPin_N; + M0P_VC->VC0_CR_f.FLTEN = pstcChannelCfg->bFlten; + M0P_VC->VC0_OUT_CFG = 1<enVcOutCfg; + } + else if (VcChannel1 == pstcChannelCfg->enVcChannel) + { + M0P_VC->CR_f.VC1_HYS_SEL = pstcChannelCfg->enVcCmpDly; + M0P_VC->CR_f.VC1_BIAS_SEL = pstcChannelCfg->enVcBiasCurrent; + M0P_VC->VC1_CR_f.DEBOUNCE_TIME = pstcChannelCfg->enVcFilterTime; + M0P_VC->VC1_CR_f.P_SEL = pstcChannelCfg->enVcInPin_P; + M0P_VC->VC1_CR_f.N_SEL = pstcChannelCfg->enVcInPin_N; + M0P_VC->VC1_CR_f.FLTEN = pstcChannelCfg->bFlten; + M0P_VC->VC1_OUT_CFG = 1<enVcOutCfg; + } + else if(VcChannel2 == pstcChannelCfg->enVcChannel) + { + M0P_VC->CR_f.VC2_HYS_SEL = pstcChannelCfg->enVcCmpDly; + M0P_VC->CR_f.VC2_BIAS_SEL = pstcChannelCfg->enVcBiasCurrent; + M0P_VC->VC2_CR_f.DEBOUNCE_TIME = pstcChannelCfg->enVcFilterTime; + M0P_VC->VC2_CR_f.P_SEL = pstcChannelCfg->enVcInPin_P; + M0P_VC->VC2_CR_f.N_SEL = pstcChannelCfg->enVcInPin_N; + M0P_VC->VC2_CR_f.FLTEN = pstcChannelCfg->bFlten; + M0P_VC->VC2_OUT_CFG = 1<enVcOutCfg; + } + else + { + ; + } +} + +/** +****************************************************************************** + ** \brief VC 閫氶亾浣胯兘 + ** + ** \param enChannel : 閫氶亾鍙稸cChannel0 VcChannel1 VcChannel2 + ** \param NewStatus : TRUE FALSE + ** \retval NewStatus : TRUE FALSE + ** +******************************************************************************/ +void Vc_Cmd(en_vc_channel_t enChannel, boolean_t NewStatus) +{ + switch(enChannel) + { + case VcChannel0: + SetBit((uint32_t)(&(M0P_VC->VC0_CR)), 16, NewStatus); + break; + case VcChannel1: + SetBit((uint32_t)(&(M0P_VC->VC1_CR)), 16, NewStatus); + break; + case VcChannel2: + SetBit((uint32_t)(&(M0P_VC->VC2_CR)), 16, NewStatus); + break; + default: + break; + } +} + +//@} // VcGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/driver/src/wdt.c b/driver/src/wdt.c new file mode 100644 index 0000000..4d07496 --- /dev/null +++ b/driver/src/wdt.c @@ -0,0 +1,203 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file wdt.c + ** + ** WDT function driver API. + ** @link WdtGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "wdt.h" + +/** + ****************************************************************************** + ** \defgroup WdtGroup + ** + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief WDT婧㈠嚭鏃堕棿璁剧疆鍑芥暟 + ** + ** \param [in] u8LoadValue 婧㈠嚭鏃堕棿 + ** + ** \retval 鏃 + ** + ******************************************************************************/ +void Wdt_WriteWdtLoad(uint8_t u8LoadValue) +{ + M0P_WDT->CON_f.WOV = u8LoadValue; +} +/** + ****************************************************************************** + ** \brief WDT鍒濆鍖栧嚱鏁 + ** + ** \param [in] enFunc @ref en_wdt_func_t + ** \param [in] enTime @ref en_wdt_time_t + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Wdt_Init(en_wdt_func_t enFunc, en_wdt_time_t enTime) +{ + en_result_t enRet = Error; + + Wdt_WriteWdtLoad(enTime); + M0P_WDT->CON_f.WINT_EN = enFunc; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief WDT澶嶄綅鍙婂惎鍔ㄥ嚱鏁 + ** + ** \param [in] 鏃 + ** + ** \retval 鏃 + ** + ******************************************************************************/ +void Wdt_Start(void) +{ + M0P_WDT->RST = 0x1E; + M0P_WDT->RST = 0xE1; +} + +/** + ****************************************************************************** + ** \brief WDT鍠傜嫍 + ** + ** \param [in] 鏃 + ** + ** \retval Ok + ** + ******************************************************************************/ +void Wdt_Feed(void) +{ + M0P_WDT->RST = 0x1E; + M0P_WDT->RST = 0xE1; +} + +/** + ****************************************************************************** + ** \brief WDT涓柇鏍囧織娓呴櫎 + ** + ** \param [in] 鏃 + ** + ** \retval Ok + ** + ******************************************************************************/ +void Wdt_IrqClr(void) +{ + M0P_WDT->RST = 0x1E; + M0P_WDT->RST = 0xE1; +} + +/** + ****************************************************************************** + ** \brief WDT璇诲彇褰撳墠璁℃暟鍊煎嚱鏁 + ** + ** \param [in] 鏃 + ** + ** \retval 璁℃暟鍊 + ** + ******************************************************************************/ +uint8_t Wdt_ReadWdtValue(void) +{ + uint8_t u8Count; + + u8Count = M0P_WDT->CON_f.WCNTL; + + return u8Count; +} +/** + ****************************************************************************** + ** \brief WDT璇诲彇褰撳墠杩愯鐘舵 + ** + ** \param [in] 鏃 + ** + ** \retval 鐘舵佸 + ** + ******************************************************************************/ +boolean_t Wdt_ReadwdtStatus(void) +{ + if(M0P_WDT->CON&0x10u) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + ******************************************************************************* + ** \brief WDT 涓柇鐘舵佹爣璁拌幏鍙 + ** + ** + ** \retval 涓柇鐘舵 + ******************************************************************************/ +boolean_t Wdt_GetIrqStatus(void) +{ + if(M0P_WDT->CON&0x80u) + { + return TRUE; + } + else + { + return FALSE; + } +} + + +//@} // WdtGroup diff --git a/keilkill.bat b/keilkill.bat new file mode 100644 index 0000000..f7819f4 --- /dev/null +++ b/keilkill.bat @@ -0,0 +1,30 @@ +del *.bak /s +del *.ddk /s +del *.edk /s +del *.lst /s +del *.lnp /s +del *.mpf /s +del *.mpj /s +del *.obj /s +del *.omf /s +::del *.opt /s ::不允许删除JLINK的设置 +del *.plg /s +del *.rpt /s +del *.tmp /s +del *.__i /s +del *.crf /s +del *.o /s +del *.d /s +del *.axf /s +del *.tra /s +del *.dep /s +del JLinkLog.txt /s + +del *.iex /s +del *.htm /s +del *.sct /s +del *.map /s + +del *.dbgconf /s +del *.Administrator /s +exit diff --git a/mcu/EWARM/HC32L17X.svd b/mcu/EWARM/HC32L17X.svd new file mode 100644 index 0000000..85deab5 --- /dev/null +++ b/mcu/EWARM/HC32L17X.svd @@ -0,0 +1,37132 @@ + + + HDSC Co.Ltd + HDSC + HDSC_HC32L17X + ARMCM0P + 1.2 + + CM0 + r0p0 + little + false + false + 3 + false + + 8 + 32 + 32 + read-write + 0x0 + 0x0 + + + ADC + desc ADC + 0x40002400 + + 0x0 + 0xD0 + + + + CR0 + desc CR0 + 0x4 + 32 + read-write + 0x67F0 + 0xBFFF + + + EN + desc EN + 0 + 0 + read-write + + + CLKDIV + desc CLKDIV + 3 + 2 + read-write + + + SGLMUX + desc SGLMUX + 8 + 4 + read-write + + + REF + desc REF + 10 + 9 + read-write + + + BUF + desc BUF + 11 + 11 + read-write + + + SAM + desc SAM + 13 + 12 + read-write + + + INREFEN + desc INREFEN + 14 + 14 + read-write + + + IE + desc IE + 15 + 15 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + CR1 + desc CR1 + 0x8 + 32 + read-write + 0x8000 + 0xFFFC + + + ALIGN + desc ALIGN + 2 + 2 + read-write + + + THCH + desc THCH + 7 + 3 + read-write + + + DMASQR + desc DMASQR + 8 + 8 + read-write + + + DMAJQR + desc DMAJQR + 9 + 9 + read-write + + + MODE + desc MODE + 10 + 10 + read-write + + + RACCEN + desc RACCEN + 11 + 11 + read-write + + + LTCMP + desc LTCMP + 12 + 12 + read-write + + + HTCMP + desc HTCMP + 13 + 13 + read-write + + + REGCMP + desc REGCMP + 14 + 14 + read-write + + + RACCCLR + desc RACCCLR + 15 + 15 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQR0 + desc SQR0 + 0x40 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + CH0MUX + desc CH0MUX + 4 + 0 + read-write + + + CH1MUX + desc CH1MUX + 9 + 5 + read-write + + + CH2MUX + desc CH2MUX + 14 + 10 + read-write + + + CH3MUX + desc CH3MUX + 19 + 15 + read-write + + + CH4MUX + desc CH4MUX + 24 + 20 + read-write + + + CH5MUX + desc CH5MUX + 29 + 25 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQR1 + desc SQR1 + 0x44 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + CH6MUX + desc CH6MUX + 4 + 0 + read-write + + + CH7MUX + desc CH7MUX + 9 + 5 + read-write + + + CH8MUX + desc CH8MUX + 14 + 10 + read-write + + + CH9MUX + desc CH9MUX + 19 + 15 + read-write + + + CH10MUX + desc CH10MUX + 24 + 20 + read-write + + + CH11MUX + desc CH11MUX + 29 + 25 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQR2 + desc SQR2 + 0x48 + 32 + read-write + 0x0 + 0xFFFFFFF + + + CH12MUX + desc CH12MUX + 4 + 0 + read-write + + + CH13MUX + desc CH13MUX + 9 + 5 + read-write + + + CH14MUX + desc CH14MUX + 14 + 10 + read-write + + + CH15MUX + desc CH15MUX + 19 + 15 + read-write + + + CNT + desc CNT + 23 + 20 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + JQR + desc JQR + 0x4C + 32 + read-write + 0x0 + 0x3FFFFFF + + + CH0MUX + desc CH0MUX + 4 + 0 + read-write + + + CH1MUX + desc CH1MUX + 9 + 5 + read-write + + + CH2MUX + desc CH2MUX + 14 + 10 + read-write + + + CH3MUX + desc CH3MUX + 19 + 15 + read-write + + + CNT + desc CNT + 21 + 20 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT0 + desc SQRRESULT0 + 0x50 + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT1 + desc SQRRESULT1 + 0x54 + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT2 + desc SQRRESULT2 + 0x58 + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT3 + desc SQRRESULT3 + 0x5C + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT4 + desc SQRRESULT4 + 0x60 + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT5 + desc SQRRESULT5 + 0x64 + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT6 + desc SQRRESULT6 + 0x68 + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT7 + desc SQRRESULT7 + 0x6C + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT8 + desc SQRRESULT8 + 0x70 + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT9 + desc SQRRESULT9 + 0x74 + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT10 + desc SQRRESULT10 + 0x78 + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SQRRESULT11 + desc SQRRESULT11 + 0x7C + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + 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+ desc CMA1E + 2 + 2 + read-write + + + CMA2E + desc CMA2E + 3 + 3 + read-write + + + CMB0E + desc CMB0E + 4 + 4 + read-write + + + CMB1E + desc CMB1E + 5 + 5 + read-write + + + CMB2E + desc CMB2E + 6 + 6 + read-write + + + ADTE + desc ADTE + 7 + 7 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + CRCH0 + desc CRCH0 + 0x24 + 32 + read-write + 0x3000 + 0xFFFF + + + CFA_CRA_BKSA + desc CFA_CRA_BKSA + 1 + 0 + read-write + + + CFB_CRB_BKSB + desc CFB_CRB_BKSB + 3 + 2 + read-write + + + CSA + desc CSA + 4 + 4 + read-write + + + CSB + desc CSB + 5 + 5 + read-write + + + BUFEA + desc BUFEA + 6 + 6 + read-write + + + BUFEB + desc BUFEB + 7 + 7 + read-write + + + CIEA + desc CIEA + 8 + 8 + read-write + + + CIEB + desc CIEB + 9 + 9 + read-write + + + CDEA + desc CDEA + 10 + 10 + read-write + + + CDEB + desc CDEB + 11 + 11 + read-write + + + CISB + desc CISB + 13 + 12 + read-write + + + CCGA + desc CCGA + 14 + 14 + read-write + + + CCGB + desc CCGB + 15 + 15 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + CRCH1 + desc CRCH1 + 0x28 + 32 + read-write + 0x3000 + 0xFFFF + + + CFA_CRA_BKSA + desc CFA_CRA_BKSA + 1 + 0 + read-write + + + CFB_CRB_BKSB + desc CFB_CRB_BKSB + 3 + 2 + read-write + + + CSA + desc CSA + 4 + 4 + read-write + + + CSB + desc CSB + 5 + 5 + read-write + + + BUFEA + desc BUFEA + 6 + 6 + read-write + + + BUFEB + desc BUFEB + 7 + 7 + read-write + + + CIEA + desc CIEA + 8 + 8 + read-write + + + CIEB + desc CIEB + 9 + 9 + read-write + + + CDEA + desc CDEA + 10 + 10 + read-write + + + CDEB + desc CDEB + 11 + 11 + read-write + + + CISB + desc CISB + 13 + 12 + read-write + + + CCGA + desc CCGA + 14 + 14 + read-write + + + CCGB + desc CCGB + 15 + 15 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + CRCH2 + desc CRCH2 + 0x2C + 32 + read-write + 0x3000 + 0xFFFF + + + CFA_CRA_BKSA + desc CFA_CRA_BKSA + 1 + 0 + read-write + + + CFB_CRB_BKSB + desc CFB_CRB_BKSB + 3 + 2 + read-write + + + CSA + desc CSA + 4 + 4 + read-write + + + CSB + desc CSB + 5 + 5 + read-write + + + BUFEA + desc BUFEA + 6 + 6 + read-write + + + BUFEB + desc BUFEB + 7 + 7 + read-write + + + CIEA + desc CIEA + 8 + 8 + read-write + + + CIEB + desc CIEB + 9 + 9 + read-write + + + CDEA + desc CDEA + 10 + 10 + read-write + + + CDEB + desc CDEB + 11 + 11 + read-write + + + CISB + desc CISB + 13 + 12 + read-write + + + CCGA + desc CCGA + 14 + 14 + read-write + + + CCGB + desc CCGB + 15 + 15 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + DTR + desc DTR + 0x30 + 32 + read-write + 0x0 + 0xFFFF + + + DTR + desc DTR + 7 + 0 + read-write + + + BKSEL + desc BKSEL + 8 + 8 + read-write + + + DTEN + desc DTEN + 9 + 9 + read-write + + + BKE + desc BKE + 10 + 10 + read-write + + + AOE + desc AOE + 11 + 11 + read-write + + + MOE + desc MOE + 12 + 12 + read-write + + + SAFEEN + desc SAFEEN + 13 + 13 + read-write + + + VCE + desc VCE + 14 + 14 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + RCR + desc RCR + 0x34 + 32 + read-write + 0x0 + 0xFF + + + RCR + desc RCR + 7 + 0 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + ARRDM + desc ARRDM + 0x38 + 32 + read-write + 0x0 + 0xFFFF + + + ARRDM + desc ARRDM + 15 + 0 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + CCR0A + desc CCR0A + 0x3C + 32 + read-write + 0x0 + 0xFFFF + + + CCR0A + desc CCR0A + 15 + 0 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + CCR0B + desc CCR0B + 0x40 + 32 + read-write + 0x0 + 0xFFFF + + + CCR0B + desc CCR0B + 15 + 0 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + CCR1A + desc CCR1A + 0x44 + 32 + read-write + 0x0 + 0xFFFF + + + CCR1A + desc CCR1A + 15 + 0 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + CCR1B + desc CCR1B + 0x48 + 32 + read-write + 0x0 + 0xFFFF + + + CCR1B + desc CCR1B + 15 + 0 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + CCR2A + desc CCR2A + 0x4C + 32 + read-write + 0x0 + 0xFFFF + + + CCR2A + desc CCR2A + 15 + 0 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + CCR2B + desc CCR2B + 0x50 + 32 + read-write + 0x0 + 0xFFFF + + + CCR2B + desc CCR2B + 15 + 0 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + + + TRNG + desc TRNG + 0x40004C00 + + 0x0 + 0x14 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + RNGCIR_EN + desc RNGCIR_EN + 0 + 0 + read-write + + + RNG_RUN + desc RNG_RUN + 1 + 1 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + MODE + desc MODE + 0x4 + 32 + read-write + 0x10 + 0x1F + + + LOAD + desc LOAD + 0 + 0 + read-write + + + FDBK + desc FDBK + 1 + 1 + read-write + + + CNT + desc CNT + 4 + 2 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + DATA0 + desc DATA0 + 0xC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA0 + desc DATA0 + 31 + 0 + read-only + + + + + DATA1 + desc DATA1 + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA1 + desc DATA1 + 31 + 0 + read-only + + + + + + + UART0 + desc UART + 0x40000000 + + 0x0 + 0x1C + + + + SBUF + desc SBUF + 0x0 + 32 + read-write + 0x0 + 0x1FF + + + DATA + desc DATA + 7 + 0 + read-write + + + DATA8 + desc DATA8 + 8 + 8 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SCON + desc SCON + 0x4 + 32 + read-write + 0x0 + 0x7FE3FF + + + RCIE + desc RCIE + 0 + 0 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + B8CONT + desc B8CONT + 3 + 2 + read-write + + + REN + desc REN + 4 + 4 + read-write + + + ADRDET + desc ADRDET + 5 + 5 + read-write + + + SM + desc SM + 7 + 6 + read-write + + + TXEIE + desc TXEIE + 8 + 8 + read-write + + + OVER + desc OVER + 9 + 9 + read-write + + + PEIE + desc PEIE + 13 + 13 + read-write + + + STOPBIT + desc STOPBIT + 15 + 14 + read-write + + + DMARXEN + desc DMARXEN + 16 + 16 + read-write + + + DMATXEN + desc DMATXEN + 17 + 17 + read-write + + + RTSEN + desc RTSEN + 18 + 18 + read-write + + + CTSEN + desc CTSEN + 19 + 19 + read-write + + + CTSIE + desc CTSIE + 20 + 20 + read-write + + + FEIE + desc FEIE + 21 + 21 + read-write + + + HDSEL + desc HDSEL + 22 + 22 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SADDR + desc SADDR + 0x8 + 32 + read-write + 0x0 + 0xFF + + + SADDR + desc SADDR + 7 + 0 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SADEN + desc SADEN + 0xC + 32 + read-write + 0x0 + 0xFF + + + SADEN + desc SADEN + 7 + 0 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + ISR + desc ISR + 0x10 + 32 + read-only + 0x8 + 0x7F + + + RC + desc RC + 0 + 0 + read-only + + + TC + desc TC + 1 + 1 + read-only + + + FE + desc FE + 2 + 2 + read-only + + + TXE + desc TXE + 3 + 3 + read-only + + + PE + desc PE + 4 + 4 + read-only + + + CTSIF + desc CTSIF + 5 + 5 + read-only + + + CTS + desc CTS + 6 + 6 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + ICR + desc ICR + 0x14 + 32 + write-only + 0x0 + 0x37 + + + RCCF + desc RCCF + 0 + 0 + write-only + + + TCCF + desc TCCF + 1 + 1 + write-only + + + FECF + desc FECF + 2 + 2 + write-only + + + PECF + desc PECF + 4 + 4 + write-only + + + CTSIFCF + desc CTSIFCF + 5 + 5 + write-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + SCNT + desc SCNT + 0x18 + 32 + read-write + 0x0 + 0xFFFF + + + SCNT + desc SCNT + 15 + 0 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + + + UART1 + desc UART + 0x40000100 + + 0x0 + 0x1C + + + + UART2 + desc UART + 0x40006000 + + 0x0 + 0x1C + + + + UART3 + desc UART + 0x40006400 + + 0x0 + 0x1C + + + + VC + desc VC + 0x40002400 + ADC + + 0x0 + 0x158 + + + + CR + desc CR + 0x10 + 32 + read-write + 0x20 + 0xFFFFF + + + DIV + desc DIV + 5 + 0 + read-write + + + DIV_EN + desc DIV_EN + 6 + 6 + read-write + + + REF2P5_SEL + desc REF2P5_SEL + 7 + 7 + read-write + + + VC0_BIAS_SEL + desc VC0_BIAS_SEL + 9 + 8 + read-write + + + VC0_HYS_SEL + desc VC0_HYS_SEL + 11 + 10 + read-write + + + VC1_BIAS_SEL + desc VC1_BIAS_SEL + 13 + 12 + read-write + + + VC1_HYS_SEL + desc VC1_HYS_SEL + 15 + 14 + read-write + + + VC2_BIAS_SEL + desc VC2_BIAS_SEL + 17 + 16 + read-write + + + VC2_HYS_SEL + desc VC2_HYS_SEL + 19 + 18 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + VC0_CR + desc VC0_CR + 0x14 + 32 + read-write + 0x0 + 0x1FFFF + + + P_SEL + desc P_SEL + 3 + 0 + read-write + + + N_SEL + desc N_SEL + 7 + 4 + read-write + + + FLTEN + desc FLTEN + 8 + 8 + read-write + + + DEBOUNCE_TIME + desc DEBOUNCE_TIME + 11 + 9 + read-write + + + FALLING + desc FALLING + 12 + 12 + read-write + + + RISING + desc RISING + 13 + 13 + read-write + + + LEVEL + desc LEVEL + 14 + 14 + read-write + + + IE + desc IE + 15 + 15 + read-write + + + EN + desc EN + 16 + 16 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + VC1_CR + desc VC1_CR + 0x18 + 32 + read-write + 0x0 + 0x1FFFF + + + P_SEL + desc P_SEL + 3 + 0 + read-write + + + N_SEL + desc N_SEL + 7 + 4 + read-write + + + FLTEN + desc FLTEN + 8 + 8 + read-write + + + DEBOUNCE_TIME + desc DEBOUNCE_TIME + 11 + 9 + read-write + + + FALLING + desc FALLING + 12 + 12 + read-write + + + RISING + desc RISING + 13 + 13 + read-write + + + LEVEL + desc LEVEL + 14 + 14 + read-write + + + IE + desc IE + 15 + 15 + read-write + + + EN + desc EN + 16 + 16 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + VC0_OUT_CFG + desc VC0_OUT_CFG + 0x1C + 32 + read-write + 0x0 + 0xFE3F + + + INV_TIMER + desc INV_TIMER + 0 + 0 + read-write + + + TIM0RCLR + desc TIM0RCLR + 1 + 1 + read-write + + + TIM1RCLR + desc TIM1RCLR + 2 + 2 + read-write + + + TIM2RCLR + desc TIM2RCLR + 3 + 3 + read-write + + + TIM3RCLR + desc TIM3RCLR + 4 + 4 + read-write + + + TIMBK + desc TIMBK + 5 + 5 + read-write + + + INV_TIM4 + desc INV_TIM4 + 9 + 9 + read-write + + + TIM4 + desc TIM4 + 10 + 10 + read-write + + + INV_TIM5 + desc INV_TIM5 + 11 + 11 + read-write + + + TIM5 + desc TIM5 + 12 + 12 + read-write + + + INV_TIM6 + desc INV_TIM6 + 13 + 13 + read-write + + + TIM6 + desc TIM6 + 14 + 14 + read-write + + + BRAKE + desc BRAKE + 15 + 15 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + VC1_OUT_CFG + desc VC1_OUT_CFG + 0x20 + 32 + read-write + 0x0 + 0xFEFF + + + INV_TIMER + desc INV_TIMER + 0 + 0 + read-write + + + TIM0RCLR + desc TIM0RCLR + 1 + 1 + read-write + + + TIM1RCLR + desc TIM1RCLR + 2 + 2 + read-write + + + TIM2RCLR + desc TIM2RCLR + 3 + 3 + read-write + + + TIM3RCLR + desc TIM3RCLR + 4 + 4 + read-write + + + TIMBK + desc TIMBK + 5 + 5 + read-write + + + INV_TIM4 + desc INV_TIM4 + 9 + 9 + read-write + + + TIM4 + desc TIM4 + 10 + 10 + read-write + + + INV_TIM5 + desc INV_TIM5 + 11 + 11 + read-write + + + TIM5 + desc TIM5 + 12 + 12 + read-write + + + INV_TIM6 + desc INV_TIM6 + 13 + 13 + read-write + + + TIM6 + desc TIM6 + 14 + 14 + read-write + + + BRAKE + desc BRAKE + 15 + 15 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + IFR + desc IFR + 0x24 + 32 + read-write + 0x0 + 0x3F + + + VC0_INTF + desc VC0_INTF + 0 + 0 + read-write + + + VC1_INTF + desc VC1_INTF + 1 + 1 + read-write + + + VC0_FILTER + desc VC0_FILTER + 2 + 2 + read-only + + + VC1_FILTER + desc VC1_FILTER + 3 + 3 + read-only + + + VC2_INTF + desc VC2_INTF + 4 + 4 + read-write + + + VC2_FILTER + desc VC2_FILTER + 5 + 5 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + VC2_CR + desc VC2_CR + 0x150 + 32 + read-write + 0x0 + 0x1FFFF + + + P_SEL + desc P_SEL + 3 + 0 + read-write + + + N_SEL + desc N_SEL + 7 + 4 + read-write + + + FLTEN + desc FLTEN + 8 + 8 + read-write + + + DEBOUNCE_TIME + desc DEBOUNCE_TIME + 11 + 9 + read-write + + + FALLING + desc FALLING + 12 + 12 + read-write + + + RISING + desc RISING + 13 + 13 + read-write + + + LEVEL + desc LEVEL + 14 + 14 + read-write + + + IE + desc IE + 15 + 15 + read-write + + + EN + desc EN + 16 + 16 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + VC2_OUT_CFG + desc VC2_OUT_CFG + 0x154 + 32 + read-write + 0x0 + 0xFEFF + + + INV_TIMER + desc INV_TIMER + 0 + 0 + read-write + + + TIM0RCLR + desc TIM0RCLR + 1 + 1 + read-write + + + TIM1RCLR + desc TIM1RCLR + 2 + 2 + read-write + + + TIM2RCLR + desc TIM2RCLR + 3 + 3 + read-write + + + TIM3RCLR + desc TIM3RCLR + 4 + 4 + read-write + + + TIMBK + desc TIMBK + 5 + 5 + read-write + + + INV_TIM4 + desc INV_TIM4 + 9 + 9 + read-write + + + TIM4 + desc TIM4 + 10 + 10 + read-write + + + INV_TIM5 + desc INV_TIM5 + 11 + 11 + read-write + + + TIM5 + desc TIM5 + 12 + 12 + read-write + + + INV_TIM6 + desc INV_TIM6 + 13 + 13 + read-write + + + TIM6 + desc TIM6 + 14 + 14 + read-write + + + BRAKE + desc BRAKE + 15 + 15 + read-write + + + RSV + desc RSV + 31 + 31 + read-write + + + + + + + WDT + desc WDT + 0x40000F00 + LPTIMER0 + + 0x0 + 0x88 + + + + RST + desc RST + 0x80 + 32 + write-only + 0x0 + 0xFF + + + RST + desc RST + 7 + 0 + write-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + CON + desc CON + 0x84 + 32 + read-write + 0xF + 0xFFBF + + + WOV + desc WOV + 3 + 0 + read-write + + + R + desc R + 4 + 4 + read-only + + + WINT_EN + desc WINT_EN + 5 + 5 + read-write + + + INT + desc INT + 7 + 7 + read-only + + + WCNTL + desc WCNTL + 15 + 8 + read-only + + + RSV + desc RSV + 31 + 31 + read-write + + + + + + + diff --git a/mcu/EWARM/config/flashloader/FlashHC32L17X.flash b/mcu/EWARM/config/flashloader/FlashHC32L17X.flash new file mode 100644 index 0000000..74ef3c3 --- /dev/null +++ b/mcu/EWARM/config/flashloader/FlashHC32L17X.flash @@ -0,0 +1,10 @@ + + + + $PROJ_DIR$\config\flashloader\FlashHC32L17X.out + 1 + 256 0x200 + 0x00000000 + $PROJ_DIR$\config\flashloader\FlashHC32L17X.mac + 0 + diff --git a/mcu/EWARM/config/flashloader/FlashHC32L17X.mac b/mcu/EWARM/config/flashloader/FlashHC32L17X.mac new file mode 100644 index 0000000..b321dac --- /dev/null +++ b/mcu/EWARM/config/flashloader/FlashHC32L17X.mac @@ -0,0 +1,23 @@ +setup() +{ + __message "----- setup hardware for Flashloader -----\n"; + /*Wait*/ + __delay(5); + __emulatorSpeed(0); + + /*Vectors at RAM*/ + __writeMemory32(0x20000000, 0xE000ED08, "Memory"); +} + +execUserPreload() +{ + __message "----- execUserPreload -----\n"; + setup(); +} + +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __message "----- execUserFlashInit -----\n"; + setup(); +} + diff --git a/mcu/EWARM/config/flashloader/HC32L17X.board b/mcu/EWARM/config/flashloader/HC32L17X.board new file mode 100644 index 0000000..792e0b8 --- /dev/null +++ b/mcu/EWARM/config/flashloader/HC32L17X.board @@ -0,0 +1,8 @@ + + + + + $PROJ_DIR$\config\flashloader\FlashHC32L17X.flash + CODE 0x00000000 0x0001FFFF + + diff --git a/mcu/EWARM/config/hc32l17x_ram.icf b/mcu/EWARM/config/hc32l17x_ram.icf new file mode 100644 index 0000000..82d0b02 --- /dev/null +++ b/mcu/EWARM/config/hc32l17x_ram.icf @@ -0,0 +1,29 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x20001FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/mcu/EWARM/config/reset.mac b/mcu/EWARM/config/reset.mac new file mode 100644 index 0000000..8604cd0 --- /dev/null +++ b/mcu/EWARM/config/reset.mac @@ -0,0 +1,8 @@ +execUserReset() +{ + __message("Executing __hwReset"); + __hwReset(0); + __message("__hwReset done"); + + __hwResetWithStrategy(0, 2); +} diff --git a/mcu/MDK/HC32L17X.sfr b/mcu/MDK/HC32L17X.sfr new file mode 100644 index 0000000..ec51925 Binary files /dev/null and b/mcu/MDK/HC32L17X.sfr differ diff --git a/mcu/MDK/config/FlashHC32L17X_128K.FLM b/mcu/MDK/config/FlashHC32L17X_128K.FLM new file mode 100644 index 0000000..6ced45f Binary files /dev/null and b/mcu/MDK/config/FlashHC32L17X_128K.FLM differ diff --git a/mcu/common/base_types.h b/mcu/common/base_types.h new file mode 100644 index 0000000..ab32088 --- /dev/null +++ b/mcu/common/base_types.h @@ -0,0 +1,147 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file base_types.h + ** + ** base type common define. + ** @link SampleGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __BASE_TYPES_H__ +#define __BASE_TYPES_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include +#include + + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE + /** Value is true (boolean_t type) */ + #define TRUE ((boolean_t) 1u) +#endif + +#ifndef FALSE + /** Value is false (boolean_t type) */ + #define FALSE ((boolean_t) 0u) +#endif + +/** Returns the minimum value out of two values */ +#define MINIMUM( X, Y ) ((X) < (Y) ? (X) : (Y)) + +/** Returns the maximum value out of two values */ +#define MAXIMUM( X, Y ) ((X) > (Y) ? (X) : (Y)) + +/** Returns the dimension of an array */ +#define ARRAY_SZ( X ) (sizeof(X) / sizeof((X)[0])) + +#ifdef __DEBUG_ASSERT + #define ASSERT(x) do{ assert((x)> 0u) ; }while(0); +#else + #define ASSERT(x) {} +#endif +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCII character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t u8Param); + +/** generic error codes */ +typedef enum en_result +{ + Ok = 0u, ///< No error + Error = 1u, ///< Non-specific error code + ErrorAddressAlignment = 2u, ///< Address alignment does not match + ErrorAccessRights = 3u, ///< Wrong mode (e.g. user/system) mode is set + ErrorInvalidParameter = 4u, ///< Provided parameter is not valid + ErrorOperationInProgress = 5u, ///< A conflicting or requested operation is still in progress + ErrorInvalidMode = 6u, ///< Operation not allowed in current mode + ErrorUninitialized = 7u, ///< Module (or part of it) was not initialized properly + ErrorBufferFull = 8u, ///< Circular buffer can not be written because the buffer is full + ErrorTimeout = 9u, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) + ErrorNotReady = 10u, ///< A requested final state is not reached + OperationInProgress = 11u ///< Indicator for operation in progress +} en_result_t; + + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + + + diff --git a/mcu/common/board_stkhc32l17x.h b/mcu/common/board_stkhc32l17x.h new file mode 100644 index 0000000..1ed42e7 --- /dev/null +++ b/mcu/common/board_stkhc32l17x.h @@ -0,0 +1,130 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file stkhc32l17x.h + ** + ** stk board common define. + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-09 1.0 Lux First version. + ** + ******************************************************************************/ +#ifndef __BOARD_STKHC32L17X_H__ +#define __BOARD_STKHC32L17X_H__ + +///< STK GPIO DEFINE +///< USER KEY +#define STK_USER_PORT GpioPortA +#define STK_USER_PIN GpioPin7 + +///< LED +#define STK_LED_PORT GpioPortD +#define STK_LED_PIN GpioPin14 + +///< XTH +#define SYSTEM_XTH (8*1000*1000u) ///< 32MHz + +#define STK_XTHI_PORT GpioPortF +#define STK_XTHI_PIN GpioPin0 +#define STK_XTHO_PORT GpioPortF +#define STK_XTHO_PIN GpioPin1 + +///< XTL +#define SYSTEM_XTL (32768u) ///< 32768Hz +#define STK_XTLI_PORT GpioPortC +#define STK_XTLI_PIN GpioPin14 +#define STK_XTLO_PORT GpioPortC +#define STK_XTLO_PIN GpioPin15 + +///< LCD +#define STK_LCD_COM0_PORT GpioPortA +#define STK_LCD_COM0_PIN GpioPin9 +#define STK_LCD_COM1_PORT GpioPortA +#define STK_LCD_COM1_PIN GpioPin10 +#define STK_LCD_COM2_PORT GpioPortA +#define STK_LCD_COM2_PIN GpioPin11 +#define STK_LCD_COM3_PORT GpioPortA +#define STK_LCD_COM3_PIN GpioPin12 +#define STK_LCD_SEG0_PORT GpioPortA +#define STK_LCD_SEG0_PIN GpioPin8 +#define STK_LCD_SEG1_PORT GpioPortC +#define STK_LCD_SEG1_PIN GpioPin9 +#define STK_LCD_SEG2_PORT GpioPortC +#define STK_LCD_SEG2_PIN GpioPin8 +#define STK_LCD_SEG3_PORT GpioPortC +#define STK_LCD_SEG3_PIN GpioPin7 +#define STK_LCD_SEG4_PORT GpioPortC +#define STK_LCD_SEG4_PIN GpioPin6 +#define STK_LCD_SEG5_PORT GpioPortB +#define STK_LCD_SEG5_PIN GpioPin15 +#define STK_LCD_SEG6_PORT GpioPortB +#define STK_LCD_SEG6_PIN GpioPin14 +#define STK_LCD_SEG7_PORT GpioPortB +#define STK_LCD_SEG7_PIN GpioPin13 + +///< I2C EEPROM +#define EVB_I2C0_EEPROM_SCL_PORT GpioPortB +#define EVB_I2C0_EEPROM_SCL_PIN GpioPin6 +#define EVB_I2C0_EEPROM_SDA_PORT GpioPortB +#define EVB_I2C0_EEPROM_SDA_PIN GpioPin7 + +///< SPI0 +#define STK_SPI0_CS_PORT GpioPortE +#define STK_SPI0_CS_PIN GpioPin12 +#define STK_SPI0_SCK_PORT GpioPortE +#define STK_SPI0_SCK_PIN GpioPin13 +#define STK_SPI0_MISO_PORT GpioPortE +#define STK_SPI0_MISO_PIN GpioPin14 +#define STK_SPI0_MOSI_PORT GpioPortE +#define STK_SPI0_MOSI_PIN GpioPin15 + +///< SPI1 +#define STK_SPI1_CS_PORT GpioPortB +#define STK_SPI1_CS_PIN GpioPin12 +#define STK_SPI1_SCK_PORT GpioPortB +#define STK_SPI1_SCK_PIN GpioPin13 +#define STK_SPI1_MISO_PORT GpioPortB +#define STK_SPI1_MISO_PIN GpioPin14 +#define STK_SPI1_MOSI_PORT GpioPortB +#define STK_SPI1_MOSI_PIN GpioPin15 + +#endif diff --git a/mcu/common/hc32l17x.h b/mcu/common/hc32l17x.h new file mode 100644 index 0000000..d871b73 --- /dev/null +++ b/mcu/common/hc32l17x.h @@ -0,0 +1,10833 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \\file HC32L17X.h +** +** Auto generate. +** Headerfile for HC32L17X series MCU +** +** History: +** +** - 2019-07-01 0.1 Lux First version. +** +******************************************************************************/ + +#ifndef __HC32L17X_H__ +#define __HC32L17X_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** +* Configuration of the Cortex-M0P Processor and Core Peripherals +******************************************************************************/ +#define __MPU_PRESENT 0 /* No MPU */ +#define __NVIC_PRIO_BITS 2 /* M0P uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +/****************************************************************************** +* Interrupt Number Definition +******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + + PORTA_IRQn = 0 , + PORTB_IRQn = 1 , + PORTC_E_IRQn = 2 , + PORTD_F_IRQn = 3 , + DMAC_IRQn = 4 , + TIM3_IRQn = 5 , + UART0_2_IRQn = 6 , + UART1_3_IRQn = 7 , + LPUART0_IRQn = 8 , + LPUART1_IRQn = 9 , + SPI0_IRQn = 10, + SPI1_IRQn = 11, + I2C0_IRQn = 12, + I2C1_IRQn = 13, + TIM0_IRQn = 14, + TIM1_IRQn = 15, + TIM2_IRQn = 16, + LPTIM_0_1_IRQn = 17, + ADTIM4_IRQn = 18, + ADTIM5_IRQn = 19, + ADTIM6_IRQn = 20, + PCA_IRQn = 21, + WDT_IRQn = 22, + RTC_IRQn = 23, + ADC_DAC_IRQn = 24, + PCNT_IRQn = 25, + VC0_IRQn = 26, + VC1_2_IRQn = 27, + LVD_IRQn = 28, + LCD_IRQn = 29, + FLASH_RAM_IRQn = 30, + CLKTRIM_IRQn = 31, + + +} IRQn_Type; + + +#include +#include + +#define SUCCESS (0) +#define ERROR (-1) + +#ifndef NULL +#define NULL (0) +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +typedef struct +{ + __IO uint32_t EN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CLKDIV : 2; + __IO uint32_t SGLMUX : 5; + __IO uint32_t REF : 2; + __IO uint32_t BUF : 1; + __IO uint32_t SAM : 2; + __IO uint32_t INREFEN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adc_cr0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t ALIGN : 1; + __IO uint32_t THCH : 5; + __IO uint32_t DMASQR : 1; + __IO uint32_t DMAJQR : 1; + __IO uint32_t MODE : 1; + __IO uint32_t RACCEN : 1; + __IO uint32_t LTCMP : 1; + __IO uint32_t HTCMP : 1; + __IO uint32_t REGCMP : 1; + __IO uint32_t RACCCLR : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adc_cr1_field_t; + +typedef struct +{ + __IO uint32_t CH0MUX : 5; + __IO uint32_t CH1MUX : 5; + __IO uint32_t CH2MUX : 5; + __IO uint32_t CH3MUX : 5; + __IO uint32_t CH4MUX : 5; + __IO uint32_t CH5MUX : 5; + uint32_t RESERVED30 : 1; + __IO uint32_t RSV : 1; +} stc_adc_sqr0_field_t; + +typedef struct +{ + __IO uint32_t CH6MUX : 5; + __IO uint32_t CH7MUX : 5; + __IO uint32_t CH8MUX : 5; + __IO uint32_t CH9MUX : 5; + __IO uint32_t CH10MUX : 5; + __IO uint32_t CH11MUX : 5; + uint32_t RESERVED30 : 1; + __IO uint32_t RSV : 1; +} stc_adc_sqr1_field_t; + +typedef struct +{ + __IO uint32_t CH12MUX : 5; + __IO uint32_t CH13MUX : 5; + __IO uint32_t CH14MUX : 5; + __IO uint32_t CH15MUX : 5; + __IO uint32_t CNT : 4; + uint32_t RESERVED24 : 7; + __IO uint32_t RSV : 1; +} stc_adc_sqr2_field_t; + +typedef struct +{ + __IO uint32_t CH0MUX : 5; + __IO uint32_t CH1MUX : 5; + __IO uint32_t CH2MUX : 5; + __IO uint32_t CH3MUX : 5; + __IO uint32_t CNT : 2; + uint32_t RESERVED22 : 9; + __IO uint32_t RSV : 1; +} stc_adc_jqr_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult0_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult1_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult2_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult3_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult4_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult5_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult6_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult7_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult8_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult9_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult10_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult11_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult12_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqr_result13_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult14_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult15_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_jqrresult0_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_jqrresult1_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_jqrresult2_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_jqrresult3_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_result_field_t; + +typedef struct +{ + __IO uint32_t RESULTACC :20; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_adc_resultacc_field_t; + +typedef struct +{ + __IO uint32_t HT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_ht_field_t; + +typedef struct +{ + __IO uint32_t LT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_lt_field_t; + +typedef struct +{ + __IO uint32_t SGLIF : 1; + __IO uint32_t LTIF : 1; + __IO uint32_t HTIF : 1; + __IO uint32_t REGIF : 1; + __IO uint32_t SQRIF : 1; + __IO uint32_t JQRIF : 1; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_adc_ifr_field_t; + +typedef struct +{ + __IO uint32_t SGLIC : 1; + __IO uint32_t LTIC : 1; + __IO uint32_t HTIC : 1; + __IO uint32_t REGIC : 1; + __IO uint32_t SQRIC : 1; + __IO uint32_t JQRIC : 1; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_adc_icr_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t TIM3 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t VC0 : 1; + __IO uint32_t VC1 : 1; + __IO uint32_t RTC : 1; + __IO uint32_t PCA : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t DMA : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PA15 : 1; + __IO uint32_t PB15 : 1; + __IO uint32_t PC15 : 1; +} stc_adc_exttrigger0_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t TIM3 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t VC0 : 1; + __IO uint32_t VC1 : 1; + __IO uint32_t RTC : 1; + __IO uint32_t PCA : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t DMA : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PA15 : 1; + __IO uint32_t PB15 : 1; + __IO uint32_t PC15 : 1; +} stc_adc_exttrigger1_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_adc_sglstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_adc_sqrstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_adc_jqrstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_adc_allstart_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_perbr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_scmbr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_dtdar_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSK : 2; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_adtim_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDE : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t INTENSAML : 1; + __IO uint32_t INTENSAMH : 1; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_adtim_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPCA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + __IO uint32_t DISSELA : 2; + __IO uint32_t DISVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPCB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + __IO uint32_t DISSELB : 2; + __IO uint32_t DISVALB : 2; + uint32_t RESERVED29 : 2; + __IO uint32_t RSV : 1; +} stc_adtim_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t BENB : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t BENP : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_adtim_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SEPA : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_adtim_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 1; + __IO uint32_t NOFIENTC : 1; + __IO uint32_t NOFICKTC : 2; + uint32_t RESERVED27 : 1; + __IO uint32_t NOFIENTD : 1; + __IO uint32_t NOFICKTD : 2; + __IO uint32_t RSV : 1; +} stc_adtim_fconr_field_t; + +typedef struct +{ + __IO uint32_t GEPERIA : 1; + __IO uint32_t GEPERIB : 1; + __IO uint32_t GEPERIC : 1; + __IO uint32_t GEPERID : 1; + uint32_t RESERVED4 :12; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; + uint32_t RESERVED21 :10; + __IO uint32_t RSV : 1; +} stc_adtim_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __IO uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __IO uint32_t DIRF : 1; +} stc_adtim_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + __IO uint32_t HSTA2 : 1; + __IO uint32_t HSTA3 : 1; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + __IO uint32_t HSTA12 : 1; + __IO uint32_t HSTA13 : 1; + __IO uint32_t HSTA14 : 1; + __IO uint32_t HSTA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_adtim_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + __IO uint32_t HSTP2 : 1; + __IO uint32_t HSTP3 : 1; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + __IO uint32_t HSTP12 : 1; + __IO uint32_t HSTP13 : 1; + __IO uint32_t HSTP14 : 1; + __IO uint32_t HSTP15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STOPS : 1; +} stc_adtim_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCEL0 : 1; + __IO uint32_t HCEL1 : 1; + __IO uint32_t HCEL2 : 1; + __IO uint32_t HCEL3 : 1; + __IO uint32_t HCEL4 : 1; + __IO uint32_t HCEL5 : 1; + __IO uint32_t HCEL6 : 1; + __IO uint32_t HCEL7 : 1; + __IO uint32_t HCEL8 : 1; + __IO uint32_t HCEL9 : 1; + __IO uint32_t HCEL10 : 1; + __IO uint32_t HCEL11 : 1; + __IO uint32_t HCEL12 : 1; + __IO uint32_t HCEL13 : 1; + __IO uint32_t HCEL14 : 1; + __IO uint32_t HCEL15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t CLEARS : 1; +} stc_adtim_hcelr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + __IO uint32_t HCPA2 : 1; + __IO uint32_t HCPA3 : 1; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + __IO uint32_t HCPA12 : 1; + __IO uint32_t HCPA13 : 1; + __IO uint32_t HCPA14 : 1; + __IO uint32_t HCPA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + __IO uint32_t HCPB2 : 1; + __IO uint32_t HCPB3 : 1; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + __IO uint32_t HCPB12 : 1; + __IO uint32_t HCPB13 : 1; + __IO uint32_t HCPB14 : 1; + __IO uint32_t HCPB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + __IO uint32_t HCUP12 : 1; + __IO uint32_t HCUP13 : 1; + __IO uint32_t HCUP14 : 1; + __IO uint32_t HCUP15 : 1; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + __IO uint32_t HCUP18 : 1; + __IO uint32_t HCUP19 : 1; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_adtim_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + __IO uint32_t HCDO12 : 1; + __IO uint32_t HCDO13 : 1; + __IO uint32_t HCDO14 : 1; + __IO uint32_t HCDO15 : 1; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + __IO uint32_t HCDO18 : 1; + __IO uint32_t HCDO19 : 1; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_adtim_hcdor_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLF : 1; + __IO uint32_t SAMHF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_ifr_field_t; + +typedef struct +{ + __IO uint32_t CMAC : 1; + __IO uint32_t CMBC : 1; + __IO uint32_t CMCC : 1; + __IO uint32_t CMDC : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFC : 1; + __IO uint32_t UDFC : 1; + __IO uint32_t DTEC : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLC : 1; + __IO uint32_t SAMHC : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_iclr_field_t; + +typedef struct +{ + __IO uint32_t CMAE : 1; + __IO uint32_t CMBE : 1; + __IO uint32_t CMCE : 1; + __IO uint32_t CMDE : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFE : 1; + __IO uint32_t UDFE : 1; + __IO uint32_t DITENA : 1; + __IO uint32_t DITENB : 1; + __IO uint32_t DITENS : 1; + __IO uint32_t CMSAE : 1; + __IO uint32_t CMSBE : 1; + __IO uint32_t DMA_G_CMA : 1; + __IO uint32_t DMA_G_CMB : 1; + __IO uint32_t DMA_G_CMC : 1; + __IO uint32_t DMA_G_CMD : 1; + uint32_t RESERVED17 : 2; + __IO uint32_t DMA_G_OVF : 1; + __IO uint32_t DMA_G_UDF : 1; + __IO uint32_t DMA_S_CMA : 1; + __IO uint32_t DMA_S_CMB : 1; + uint32_t RESERVED23 : 8; + __IO uint32_t RSV : 1; +} stc_adtim_cr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; + __IO uint32_t BFILTS : 2; + __IO uint32_t BFILTEN : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t SOFTBK : 1; + __IO uint32_t SML0 : 1; + __IO uint32_t SML1 : 1; + __IO uint32_t SML2 : 1; + __IO uint32_t SMH0 : 1; + __IO uint32_t SMH1 : 1; + __IO uint32_t SMH2 : 1; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_adtim_aossr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_adtim_aoscl_field_t; + +typedef struct +{ + __IO uint32_t EN0 : 1; + __IO uint32_t EN1 : 1; + __IO uint32_t EN2 : 1; + __IO uint32_t EN3 : 1; + __IO uint32_t EN4 : 1; + __IO uint32_t EN5 : 1; + __IO uint32_t EN6 : 1; + __IO uint32_t EN7 : 1; + __IO uint32_t EN8 : 1; + __IO uint32_t EN9 : 1; + __IO uint32_t EN10 : 1; + __IO uint32_t EN11 : 1; + __IO uint32_t EN12 : 1; + __IO uint32_t EN13 : 1; + __IO uint32_t EN14 : 1; + __IO uint32_t EN15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_ptbks_field_t; + +typedef struct +{ + __IO uint32_t TRIGAS : 4; + __IO uint32_t TRIGBS : 4; + __IO uint32_t TRIGCS : 4; + __IO uint32_t TRIGDS : 4; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_ttrig_field_t; + +typedef struct +{ + __IO uint32_t IAOS0S : 4; + __IO uint32_t IAOS1S : 4; + __IO uint32_t IAOS2S : 4; + __IO uint32_t IAOS3S : 4; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_itrig_field_t; + +typedef struct +{ + __IO uint32_t POL0 : 1; + __IO uint32_t POL1 : 1; + __IO uint32_t POL2 : 1; + __IO uint32_t POL3 : 1; + __IO uint32_t POL4 : 1; + __IO uint32_t POL5 : 1; + __IO uint32_t POL6 : 1; + __IO uint32_t POL7 : 1; + __IO uint32_t POL8 : 1; + __IO uint32_t POL9 : 1; + __IO uint32_t POL10 : 1; + __IO uint32_t POL11 : 1; + __IO uint32_t POL12 : 1; + __IO uint32_t POL13 : 1; + __IO uint32_t POL14 : 1; + __IO uint32_t POL15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_ptbkp_field_t; + +typedef struct +{ + __IO uint32_t SSTA0 : 1; + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_adtim_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP0 : 1; + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_adtim_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLR0 : 1; + __IO uint32_t SCLR1 : 1; + __IO uint32_t SCLR2 : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_adtim_sclrr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t KEYSIZE : 2; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_aes_cr_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data0_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data1_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data2_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data3_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key0_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key1_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key2_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key3_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key4_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key5_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key6_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key7_field_t; + +typedef struct +{ + __IO uint32_t BGR_EN : 1; + __IO uint32_t TS_EN : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_bgr_cr_field_t; + +typedef struct +{ + __IO uint32_t TRIM_START : 1; + __IO uint32_t REFCLK_SEL : 3; + __IO uint32_t CALCLK_SEL : 2; + __IO uint32_t MON_EN : 1; + __IO uint32_t IE : 1; + __IO uint32_t CALCLK_SEL2 : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_clk_trim_cr_field_t; + +typedef struct +{ + __IO uint32_t RCNTVAL :32; +} stc_clk_trim_refcon_field_t; + +typedef struct +{ + __IO uint32_t REFCNT :32; +} stc_clk_trim_refcnt_field_t; + +typedef struct +{ + __IO uint32_t CALCNT :32; +} stc_clk_trim_calcnt_field_t; + +typedef struct +{ + __IO uint32_t STOP : 1; + __IO uint32_t CALCNT_OF : 1; + __IO uint32_t XTL_FAULT : 1; + __IO uint32_t XTH_FAULT : 1; + __IO uint32_t PLL_FAULT : 1; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_clk_trim_ifr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t XTL_FAULT_CLR : 1; + __IO uint32_t XTH_FAULT_CLR : 1; + __IO uint32_t PLL_FAULT_CLR : 1; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_clk_trim_iclr_field_t; + +typedef struct +{ + __IO uint32_t CCNTVAL :32; +} stc_clk_trim_calcon_field_t; + +typedef struct +{ + __IO uint32_t CR : 1; + __IO uint32_t FLAG : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_crc_cr_field_t; + +typedef struct +{ + __IO uint32_t RESULT :32; +} stc_crc_result_field_t; + +typedef struct +{ + __IO uint32_t DATA :32; +} stc_crc_data_field_t; + +typedef struct +{ + __IO uint32_t EN0 : 1; + __IO uint32_t BOFF0 : 1; + __IO uint32_t TEN0 : 1; + __IO uint32_t TSEL0 : 3; + __IO uint32_t WAVE0 : 2; + __IO uint32_t MAMP0 : 4; + __IO uint32_t DMAEN0 : 1; + __IO uint32_t DMAUDRIE0 : 1; + __IO uint32_t SREF0 : 2; +} stc_dac_cr0_field_t; + +typedef struct +{ + __IO uint32_t SWTRIG0 : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_dac_swtrigr_field_t; + +typedef struct +{ + __IO uint32_t DHR0 :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_dac_dhr12r0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 4; + __IO uint32_t DHR0 :12; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_dac_dhr12l0_field_t; + +typedef struct +{ + __IO uint32_t DHR0 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_dac_dhr8r0_field_t; + +typedef struct +{ + __IO uint32_t DOR0 :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_dac_dor0_field_t; + +typedef struct +{ + uint32_t RESERVED0 :13; + __IO uint32_t DMAUDR0 : 1; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_dac_sr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 4; + __IO uint32_t PTRIGSEL : 3; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_dac_etrs_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t LPTIM0 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t PCA : 1; + __IO uint32_t WDT : 1; + __IO uint32_t RTC : 1; + uint32_t RESERVED10 : 1; + __IO uint32_t TIM3 : 1; + __IO uint32_t LPTIM1 : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_debug_active_field_t; + +typedef struct +{ + uint32_t RESERVED0 :24; + __IO uint32_t HALT : 4; + __IO uint32_t PRIO : 1; + uint32_t RESERVED29 : 1; + __IO uint32_t ST : 1; + __IO uint32_t EN : 1; +} stc_dmac_conf_field_t; + +typedef struct +{ + __IO uint32_t TC :16; + __IO uint32_t BC : 4; + uint32_t RESERVED20 : 2; + __IO uint32_t TRI_SEL : 7; + __IO uint32_t ST : 1; + __IO uint32_t PAS : 1; + __IO uint32_t ENS : 1; +} stc_dmac_confa0_field_t; + +typedef struct +{ + __IO uint32_t MSK : 1; + uint32_t RESERVED1 :15; + __IO uint32_t STAT : 3; + __IO uint32_t FIS_IE : 1; + __IO uint32_t ERR_IE : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t WIDTH : 2; + __IO uint32_t MODE : 2; +} stc_dmac_confb0_field_t; + +typedef struct +{ + __IO uint32_t SRCADR :32; +} stc_dmac_srcadr0_field_t; + +typedef struct +{ + __IO uint32_t DSTADR :32; +} stc_dmac_dstadr0_field_t; + +typedef struct +{ + __IO uint32_t TC :16; + __IO uint32_t BC : 4; + uint32_t RESERVED20 : 2; + __IO uint32_t TRI_SEL : 7; + __IO uint32_t ST : 1; + __IO uint32_t PAS : 1; + __IO uint32_t ENS : 1; +} stc_dmac_confa1_field_t; + +typedef struct +{ + __IO uint32_t MSK : 1; + uint32_t RESERVED1 :15; + __IO uint32_t STAT : 3; + __IO uint32_t FIS_IE : 1; + __IO uint32_t ERR_IE : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t WIDTH : 2; + __IO uint32_t MODE : 2; +} stc_dmac_confb1_field_t; + +typedef struct +{ + __IO uint32_t SRCADR :32; +} stc_dmac_srcadr1_field_t; + +typedef struct +{ + __IO uint32_t DSTADR :32; +} stc_dmac_dstadr1_field_t; + +typedef struct +{ + __IO uint32_t TNVS : 9; + __IO uint32_t RSV :23; +} stc_flash_tnvs_field_t; + +typedef struct +{ + __IO uint32_t TPGS : 8; + __IO uint32_t RSV :24; +} stc_flash_tpgs_field_t; + +typedef struct +{ + __IO uint32_t TPROG : 9; + __IO uint32_t RSV :23; +} stc_flash_tprog_field_t; + +typedef struct +{ + __IO uint32_t TSERASE :18; + __IO uint32_t RSV :14; +} stc_flash_tserase_field_t; + +typedef struct +{ + __IO uint32_t TMERASE :21; + __IO uint32_t RSV :11; +} stc_flash_tmerase_field_t; + +typedef struct +{ + __IO uint32_t TPRCV :12; + __IO uint32_t RSV :20; +} stc_flash_tprcv_field_t; + +typedef struct +{ + __IO uint32_t TSRCV :12; + __IO uint32_t RSV :20; +} stc_flash_tsrcv_field_t; + +typedef struct +{ + __IO uint32_t TMRCV :14; + __IO uint32_t RSV :18; +} stc_flash_tmrcv_field_t; + +typedef struct +{ + __IO uint32_t OP : 2; + __IO uint32_t WAIT : 2; + __IO uint32_t BUSY : 1; + __IO uint32_t IE : 2; + uint32_t RESERVED7 : 2; + __IO uint32_t DPSTB_EN : 1; + __IO uint32_t RSV :22; +} stc_flash_cr_field_t; + +typedef struct +{ + __IO uint32_t IF0 : 1; + __IO uint32_t IF1 : 1; + __IO uint32_t RSV :30; +} stc_flash_ifr_field_t; + +typedef struct +{ + __IO uint32_t ICLR0 : 1; + __IO uint32_t ICLR1 : 1; + __IO uint32_t RSV :30; +} stc_flash_iclr_field_t; + +typedef struct +{ + __IO uint32_t BYSEQ :16; + __IO uint32_t RSV :16; +} stc_flash_bypass_field_t; + +typedef struct +{ + __IO uint32_t SLOCK :32; +} stc_flash_slock0_field_t; + +typedef struct +{ + __IO uint32_t SLOCK :32; +} stc_flash_slock1_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd15_sel_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_padir_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pain_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_paout_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_paads_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pabset_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pabclr_field_t; + +typedef struct +{ + __IO uint32_t PABCLR :16; + __IO uint32_t PABSET :16; +} stc_gpio_pabsetclr_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_padr_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_papu_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_papd_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_paod_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pahie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_palie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_parie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pafie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbdir_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbin_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbout_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbads_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbbset_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbbclr_field_t; + +typedef struct +{ + __IO uint32_t PBBCLR :16; + __IO uint32_t PBBSET :16; +} stc_gpio_pbbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbdr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbpu_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbpd_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbod_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbhie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pblie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbrie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbfie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcdir_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcin_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcout_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcads_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcbset_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcbclr_field_t; + +typedef struct +{ + __IO uint32_t PCBCLR :16; + __IO uint32_t PCBSET :16; +} stc_gpio_pcbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcdr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcpu_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcpd_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcod_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pchie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pclie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcrie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcfie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pddir_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdin_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdout_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdads_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdbset_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdbclr_field_t; + +typedef struct +{ + __IO uint32_t PDBCLR :16; + __IO uint32_t PDBSET :16; +} stc_gpio_pdbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pddr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdpu_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdpd_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdod_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdhie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdlie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdrie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdfie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pa_stat_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pa_iclr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pb_stat_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pb_iclr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pc_stat_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pc_iclr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pd_stat_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pd_iclr_field_t; + +typedef struct +{ + __IO uint32_t IESEL : 1; +} stc_gpio_ctrl0_field_t; + +typedef struct +{ + __IO uint32_t EXT_CLK_SEL : 4; + __IO uint32_t SSN0_SEL : 4; + __IO uint32_t PCLK_SEL : 2; + __IO uint32_t HCLK_SEL : 2; + __IO uint32_t PCLK_EN : 1; + __IO uint32_t HCLK_EN : 1; + __IO uint32_t IR_POL : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_gpio_ctrl1_field_t; + +typedef struct +{ + __IO uint32_t SSN1_SEL : 4; + __IO uint32_t TCLK_SEL : 2; + __IO uint32_t TCLK_DIV : 2; + uint32_t RESERVED8 : 7; + __IO uint32_t AHB_SEL : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_ctrl2_field_t; + +typedef struct +{ + __IO uint32_t TIM0_G : 3; + __IO uint32_t TIM1_G : 3; + __IO uint32_t TIM2_G : 3; + __IO uint32_t TIM3_G : 3; + __IO uint32_t LPTIM0_G : 3; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_gpio_timgs_field_t; + +typedef struct +{ + __IO uint32_t TIM0_E : 3; + __IO uint32_t TIM1_E : 3; + __IO uint32_t TIM2_E : 3; + __IO uint32_t TIM3_E : 3; + __IO uint32_t LPTIM0_E : 3; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_gpio_times_field_t; + +typedef struct +{ + __IO uint32_t TIM0_CA : 3; + __IO uint32_t TIM1_CA : 3; + __IO uint32_t TIM2_CA : 3; + __IO uint32_t TIM3_CA : 3; + __IO uint32_t TIM3_CB : 3; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_gpio_timcps_field_t; + +typedef struct +{ + __IO uint32_t PCA_CH0 : 3; + __IO uint32_t PCA_ECI : 3; + __IO uint32_t LPTIM1_G : 3; + __IO uint32_t LPTIM1_E : 3; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pcas_field_t; + +typedef struct +{ + __IO uint32_t PCNT_S0 : 2; + __IO uint32_t PCNT_S1 : 2; + uint32_t RESERVED4 :27; + __IO uint32_t RSV : 1; +} stc_gpio_pcnt_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf11_sel_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pedir_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pein_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_peout_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_peads_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pebset_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pebclr_field_t; + +typedef struct +{ + __IO uint32_t PEBCLR :16; + __IO uint32_t PEBSET :16; +} stc_gpio_pebsetclr_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pedr_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pepu_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pepd_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_peod_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pehie_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pelie_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_perie_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pefie_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfdir_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfin_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfout_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfads_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfbset_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfbclr_field_t; + +typedef struct +{ + __IO uint32_t PFBCLR :12; + uint32_t RESERVED12 : 4; + __IO uint32_t PFBSET :12; +} stc_gpio_pfbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfdr_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfpu_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfpd_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfod_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfhie_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pflie_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfrie_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pffie_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pe_stat_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pe_iclr_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pf_stat_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pf_iclr_field_t; + +typedef struct +{ + __IO uint32_t TME : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_i2c_tmrun_field_t; + +typedef struct +{ + __IO uint32_t TM : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_i2c_tm_field_t; + +typedef struct +{ + __IO uint32_t H1M : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t AA : 1; + __IO uint32_t SI : 1; + __IO uint32_t STO : 1; + __IO uint32_t STA : 1; + __IO uint32_t ENS : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_i2c_cr_field_t; + +typedef struct +{ + __IO uint32_t DAT : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_i2c_data_field_t; + +typedef struct +{ + __IO uint32_t GC : 1; + __IO uint32_t ADR : 7; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_i2c_addr_field_t; + +typedef struct +{ + __IO uint32_t STA : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_i2c_stat_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t LCDCLK : 2; + __IO uint32_t CPCLK : 2; + __IO uint32_t BIAS : 1; + __IO uint32_t DUTY : 3; + __IO uint32_t BSEL : 3; + __IO uint32_t CONTRAST : 4; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_lcd_cr0_field_t; + +typedef struct +{ + __IO uint32_t BLINKCNT : 6; + __IO uint32_t BLINKEN : 1; + __IO uint32_t CLKSRC : 1; + __IO uint32_t MODE : 1; + __IO uint32_t IE : 1; + __IO uint32_t DMAEN : 1; + __IO uint32_t INTF : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_lcd_cr1_field_t; + +typedef struct +{ + uint32_t RESERVED0 :10; + __IO uint32_t INTF : 1; + uint32_t RESERVED11 :20; + __IO uint32_t RSV : 1; +} stc_lcd_intclr_field_t; + +typedef struct +{ + __IO uint32_t S0 : 1; + __IO uint32_t S1 : 1; + __IO uint32_t S2 : 1; + __IO uint32_t S3 : 1; + __IO uint32_t S4 : 1; + __IO uint32_t S5 : 1; + __IO uint32_t S6 : 1; + __IO uint32_t S7 : 1; + __IO uint32_t S8 : 1; + __IO uint32_t S9 : 1; + __IO uint32_t S10 : 1; + __IO uint32_t S11 : 1; + __IO uint32_t S12 : 1; + __IO uint32_t S13 : 1; + __IO uint32_t S14 : 1; + __IO uint32_t S15 : 1; + __IO uint32_t S16 : 1; + __IO uint32_t S17 : 1; + __IO uint32_t S18 : 1; + __IO uint32_t S19 : 1; + __IO uint32_t S20 : 1; + __IO uint32_t S21 : 1; + __IO uint32_t S22 : 1; + __IO uint32_t S23 : 1; + __IO uint32_t S24 : 1; + __IO uint32_t S25 : 1; + __IO uint32_t S26 : 1; + __IO uint32_t S27 : 1; + __IO uint32_t S28 : 1; + __IO uint32_t S29 : 1; + __IO uint32_t S30 : 1; + __IO uint32_t S31 : 1; +} stc_lcd_poen0_field_t; + +typedef struct +{ + __IO uint32_t S32 : 1; + __IO uint32_t S33 : 1; + __IO uint32_t S34 : 1; + __IO uint32_t S35 : 1; + __IO uint32_t S36C7 : 1; + __IO uint32_t S37C6 : 1; + __IO uint32_t S38C5 : 1; + __IO uint32_t S39C4 : 1; + __IO uint32_t S40 : 1; + __IO uint32_t S41 : 1; + __IO uint32_t S42 : 1; + __IO uint32_t S43 : 1; + __IO uint32_t MUX : 1; + __IO uint32_t S44 : 1; + __IO uint32_t S45 : 1; + __IO uint32_t S46 : 1; + __IO uint32_t S47 : 1; + __IO uint32_t S48 : 1; + __IO uint32_t S49 : 1; + __IO uint32_t S50 : 1; + __IO uint32_t S51 : 1; + __IO uint32_t C0 : 1; + __IO uint32_t C1 : 1; + __IO uint32_t C2 : 1; + __IO uint32_t C3 : 1; +} stc_lcd_poen1_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram0_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram1_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram2_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram3_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram4_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram5_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram6_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram7_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ram8_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ram9_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_rama_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ramb_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ramc_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ramd_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_rame_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ramf_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_lptimer_cnt_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_lptimer_arr_field_t; + +typedef struct +{ + __IO uint32_t TR : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOG_EN : 1; + __IO uint32_t TCK_SEL : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t WT_FLAG : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATE_P : 1; + __IO uint32_t IE : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_lptimer_cr_field_t; + +typedef struct +{ + __IO uint32_t TF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_lptimer_ifr_field_t; + +typedef struct +{ + __IO uint32_t TFC : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_lptimer_iclr_field_t; + +typedef struct +{ + __IO uint32_t DATA : 8; + __IO uint32_t DATA8 : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_lpuart_sbuf_field_t; + +typedef struct +{ + __IO uint32_t RCIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t B8CONT : 2; + __IO uint32_t REN : 1; + __IO uint32_t ADRDET : 1; + __IO uint32_t SM : 2; + __IO uint32_t TXEIE : 1; + __IO uint32_t OVER : 2; + __IO uint32_t SCLKSEL : 2; + __IO uint32_t PEIE : 1; + __IO uint32_t STOPBIT : 2; + __IO uint32_t DMARXEN : 1; + __IO uint32_t DMATXEN : 1; + __IO uint32_t RTSEN : 1; + __IO uint32_t CTSEN : 1; + __IO uint32_t CTSIE : 1; + __IO uint32_t FEIE : 1; + __IO uint32_t HDSEL : 1; + uint32_t RESERVED23 : 8; + __IO uint32_t RSV : 1; +} stc_lpuart_scon_field_t; + +typedef struct +{ + __IO uint32_t SADDR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_lpuart_saddr_field_t; + +typedef struct +{ + __IO uint32_t SADEN : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_lpuart_saden_field_t; + +typedef struct +{ + __IO uint32_t RC : 1; + __IO uint32_t TC : 1; + __IO uint32_t FE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t PE : 1; + __IO uint32_t CTSIF : 1; + __IO uint32_t CTS : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_lpuart_isr_field_t; + +typedef struct +{ + __IO uint32_t RCCF : 1; + __IO uint32_t TCCF : 1; + __IO uint32_t FECF : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PECF : 1; + __IO uint32_t CTSIFCF : 1; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_lpuart_icr_field_t; + +typedef struct +{ + __IO uint32_t SCNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_lpuart_scnt_field_t; + +typedef struct +{ + __IO uint32_t LVDEN : 1; + __IO uint32_t ACT : 1; + __IO uint32_t SOURCE_SEL : 2; + __IO uint32_t VTDS : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FTEN : 1; + __IO uint32_t RTEN : 1; + __IO uint32_t HTEN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_lvd_cr_field_t; + +typedef struct +{ + __IO uint32_t INTF : 1; + __IO uint32_t FILTER : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_lvd_ifr_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t AZEN : 1; + __IO uint32_t BUFEN : 1; + __IO uint32_t OEN1 : 1; + __IO uint32_t OEN2 : 1; + __IO uint32_t OEN3 : 1; + __IO uint32_t OEN4 : 1; + __IO uint32_t BIASSEL : 3; + uint32_t RESERVED10 :21; + __IO uint32_t RSV : 1; +} stc_opa_cr0_field_t; + +typedef struct +{ + __IO uint32_t ADCTR_EN : 1; + __IO uint32_t TRIGGER : 1; + __IO uint32_t AZ_PULSE : 1; + __IO uint32_t CLK_SW_SET : 1; + __IO uint32_t CLK_SEL : 4; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_opa_cr1_field_t; + +typedef struct +{ + __IO uint32_t CCF0 : 1; + __IO uint32_t CCF1 : 1; + __IO uint32_t CCF2 : 1; + __IO uint32_t CCF3 : 1; + __IO uint32_t CCF4 : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t CR : 1; + __IO uint32_t CF : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccon_field_t; + +typedef struct +{ + __IO uint32_t CFIE : 1; + __IO uint32_t CPS : 3; + uint32_t RESERVED4 : 2; + __IO uint32_t WDTE : 1; + __IO uint32_t CIDL : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_cmod_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_cnt_field_t; + +typedef struct +{ + __IO uint32_t CCF0 : 1; + __IO uint32_t CCF1 : 1; + __IO uint32_t CCF2 : 1; + __IO uint32_t CCF3 : 1; + __IO uint32_t CCF4 : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t CF : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_iclr_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pca_ccapm0_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pca_ccapm1_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pca_ccapm2_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pca_ccapm3_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pca_ccapm4_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap0h_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap0l_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap1h_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap1l_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap2h_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap2l_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap3h_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap3l_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap4h_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap4l_field_t; + +typedef struct +{ + __IO uint32_t CCAPO0 : 1; + __IO uint32_t CCAPO1 : 1; + __IO uint32_t CCAPO2 : 1; + __IO uint32_t CCAPO3 : 1; + __IO uint32_t CCAPO4 : 1; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_pca_ccapo_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_ccap0_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_ccap1_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_ccap2_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_ccap3_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_ccap4_field_t; + +typedef struct +{ + __IO uint32_t CARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_carr_field_t; + +typedef struct +{ + __IO uint32_t EPWM : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_pca_epwm_field_t; + +typedef struct +{ + __IO uint32_t RUN : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_pcnt_run_field_t; + +typedef struct +{ + __IO uint32_t MODE : 2; + __IO uint32_t CLKSEL : 2; + __IO uint32_t DIR : 1; + __IO uint32_t S0P : 1; + __IO uint32_t S1P : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pcnt_ctrl_field_t; + +typedef struct +{ + __IO uint32_t CLKDIV :13; + __IO uint32_t DEBTOP : 3; + __IO uint32_t EN : 1; + uint32_t RESERVED17 :14; + __IO uint32_t RSV : 1; +} stc_pcnt_flt_field_t; + +typedef struct +{ + __IO uint32_t TH :12; + uint32_t RESERVED12 : 4; + __IO uint32_t EN : 1; + uint32_t RESERVED17 :14; + __IO uint32_t RSV : 1; +} stc_pcnt_tocr_field_t; + +typedef struct +{ + __IO uint32_t T2C : 1; + __IO uint32_t B2T : 1; + __IO uint32_t B2C : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_pcnt_cmd_field_t; + +typedef struct +{ + __IO uint32_t DIR : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_pcnt_sr1_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pcnt_cnt_field_t; + +typedef struct +{ + __IO uint32_t TOP :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pcnt_top_field_t; + +typedef struct +{ + __IO uint32_t BUF :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pcnt_buf_field_t; + +typedef struct +{ + __IO uint32_t UF : 1; + __IO uint32_t OV : 1; + __IO uint32_t TO : 1; + __IO uint32_t DIR : 1; + __IO uint32_t FE : 1; + __IO uint32_t BB : 1; + __IO uint32_t S0E : 1; + __IO uint32_t S1E : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pcnt_ifr_field_t; + +typedef struct +{ + __IO uint32_t UF : 1; + __IO uint32_t OV : 1; + __IO uint32_t TO : 1; + __IO uint32_t DIR : 1; + __IO uint32_t FE : 1; + __IO uint32_t BB : 1; + __IO uint32_t S0E : 1; + __IO uint32_t S1E : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pcnt_icr_field_t; + +typedef struct +{ + __IO uint32_t UF : 1; + __IO uint32_t OV : 1; + __IO uint32_t TO : 1; + __IO uint32_t DIR : 1; + __IO uint32_t FE : 1; + __IO uint32_t BB : 1; + __IO uint32_t S0E : 1; + __IO uint32_t S1E : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pcnt_ien_field_t; + +typedef struct +{ + __IO uint32_t T2C : 1; + __IO uint32_t B2T : 1; + __IO uint32_t B2C : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_pcnt_sr2_field_t; + +typedef struct +{ + __IO uint32_t DBG : 2; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_pcnt_dbg_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_ram_cr_field_t; + +typedef struct +{ + __IO uint32_t ERRADDR :14; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_ram_erraddr_field_t; + +typedef struct +{ + __IO uint32_t ERR : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_ram_ifr_field_t; + +typedef struct +{ + __IO uint32_t ERRCLR : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_ram_iclr_field_t; + +typedef struct +{ + __IO uint32_t POR5V : 1; + __IO uint32_t POR15V : 1; + __IO uint32_t LVD : 1; + __IO uint32_t WDT : 1; + __IO uint32_t PCA : 1; + __IO uint32_t LOCKUP : 1; + __IO uint32_t SYSREQ : 1; + __IO uint32_t RSTB : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_reset_flag_field_t; + +typedef struct +{ + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t I2C0 : 1; + __IO uint32_t I2C1 : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t BASETIM : 1; + __IO uint32_t LPTIM0 : 1; + __IO uint32_t ADVTIM : 1; + __IO uint32_t TIM3 : 1; + uint32_t RESERVED12 : 1; + __IO uint32_t OPA : 1; + __IO uint32_t PCA : 1; + uint32_t RESERVED15 : 1; + __IO uint32_t ADC : 1; + __IO uint32_t VC : 1; + __IO uint32_t RNG : 1; + __IO uint32_t PCNT : 1; + __IO uint32_t RTC : 1; + __IO uint32_t TRIM : 1; + __IO uint32_t LCD : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t TICK : 1; + __IO uint32_t SWD : 1; + __IO uint32_t CRC : 1; + __IO uint32_t AES : 1; + __IO uint32_t GPIO : 1; + __IO uint32_t DMA : 1; +} stc_reset_peri_reset0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 3; + __IO uint32_t DAC : 1; + __IO uint32_t LPTIM1 : 1; + uint32_t RESERVED5 : 3; + __IO uint32_t UART2 : 1; + __IO uint32_t UART3 : 1; + uint32_t RESERVED10 :21; + __IO uint32_t RSV : 1; +} stc_reset_peri_reset1_field_t; + +typedef struct +{ + __IO uint32_t PRDS : 3; + __IO uint32_t AMPM : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t HZ1OE : 1; + __IO uint32_t HZ1SEL : 1; + __IO uint32_t START : 1; + __IO uint32_t PRDX : 6; + __IO uint32_t PRDSEL : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_rtc_cr0_field_t; + +typedef struct +{ + __IO uint32_t WAIT : 1; + __IO uint32_t WAITF : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t PRDF : 1; + __IO uint32_t ALMF : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t ALMIE : 1; + __IO uint32_t ALMEN : 1; + __IO uint32_t CKSEL : 3; + uint32_t RESERVED11 :20; + __IO uint32_t RSV : 1; +} stc_rtc_cr1_field_t; + +typedef struct +{ + __IO uint32_t SECL : 4; + __IO uint32_t SECH : 3; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_rtc_sec_field_t; + +typedef struct +{ + __IO uint32_t MINL : 4; + __IO uint32_t MINH : 3; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_rtc_min_field_t; + +typedef struct +{ + __IO uint32_t HOURL : 4; + __IO uint32_t HOURH : 2; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_rtc_hour_field_t; + +typedef struct +{ + __IO uint32_t WEEK : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_rtc_week_field_t; + +typedef struct +{ + __IO uint32_t DAYL : 4; + __IO uint32_t DAYH : 2; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_rtc_day_field_t; + +typedef struct +{ + __IO uint32_t MON : 5; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_rtc_mon_field_t; + +typedef struct +{ + __IO uint32_t YEARL : 4; + __IO uint32_t YEARH : 4; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_rtc_year_field_t; + +typedef struct +{ + __IO uint32_t ALMMINL : 4; + __IO uint32_t ALMMINH : 3; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_rtc_almmin_field_t; + +typedef struct +{ + __IO uint32_t ALMHOURL : 4; + __IO uint32_t ALMHOURH : 2; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_rtc_almhour_field_t; + +typedef struct +{ + __IO uint32_t ALMWEEK : 7; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_rtc_almweek_field_t; + +typedef struct +{ + __IO uint32_t CR : 9; + uint32_t RESERVED9 : 6; + __IO uint32_t EN : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_rtc_compen_field_t; + +typedef struct +{ + __IO uint32_t ALMSECL : 4; + __IO uint32_t ALMSECH : 3; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_rtc_almsec_field_t; + +typedef struct +{ + __IO uint32_t SPR0 : 1; + __IO uint32_t SPR1 : 1; + __IO uint32_t CPHA : 1; + __IO uint32_t CPOL : 1; + __IO uint32_t MSTR : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t SPEN : 1; + __IO uint32_t SPR2 : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_spi_cr_field_t; + +typedef struct +{ + __IO uint32_t SSN : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_spi_ssn_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t RXNE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t BUSY : 1; + __IO uint32_t MDF : 1; + __IO uint32_t SSERR : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t SPIF : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_spi_stat_field_t; + +typedef struct +{ + __IO uint32_t DAT : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_spi_data_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t INT_EN : 1; + __IO uint32_t HDMA_RX : 1; + __IO uint32_t HDMA_TX : 1; + __IO uint32_t TXEIE : 1; + __IO uint32_t RXNEIE : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_spi_cr2_field_t; + +typedef struct +{ + __IO uint32_t INT_CLR : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_spi_iclr_field_t; + +typedef struct +{ + __IO uint32_t RCH_EN : 1; + __IO uint32_t XTH_EN : 1; + __IO uint32_t RCL_EN : 1; + __IO uint32_t XTL_EN : 1; + __IO uint32_t PLL_EN : 1; + __IO uint32_t CLKSW : 3; + __IO uint32_t HCLK_PRS : 3; + __IO uint32_t PCLK_PRS : 2; + uint32_t RESERVED13 : 2; + __IO uint32_t WAKEUP_BYRCH : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_sysctrl_sysctrl0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t EXTH_EN : 1; + __IO uint32_t EXTL_EN : 1; + __IO uint32_t XTL_ALWAYS_ON : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t RTC_LPW : 1; + __IO uint32_t LOCKUP_EN : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t SWD_USE_IO : 1; + __IO uint32_t RTC_FREQ_ADJUST : 3; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_sysctrl_sysctrl1_field_t; + +typedef struct +{ + __IO uint32_t SYSCTRL2 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_sysctrl_sysctrl2_field_t; + +typedef struct +{ + __IO uint32_t TRIM :11; + __IO uint32_t STABLE : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_sysctrl_rch_cr_field_t; + +typedef struct +{ + __IO uint32_t DRIVER : 2; + __IO uint32_t XTH_FSEL : 2; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_sysctrl_xth_cr_field_t; + +typedef struct +{ + __IO uint32_t TRIM :10; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_sysctrl_rcl_cr_field_t; + +typedef struct +{ + __IO uint32_t DRIVER : 2; + __IO uint32_t AMP_SEL : 2; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_sysctrl_xtl_cr_field_t; + +typedef struct +{ + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t I2C0 : 1; + __IO uint32_t I2C1 : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t BASETIM : 1; + __IO uint32_t LPTIM0 : 1; + __IO uint32_t ADVTIM : 1; + __IO uint32_t TIM3 : 1; + uint32_t RESERVED12 : 1; + __IO uint32_t OPA : 1; + __IO uint32_t PCA : 1; + __IO uint32_t WDT : 1; + __IO uint32_t ADC : 1; + __IO uint32_t VC : 1; + __IO uint32_t RNG : 1; + __IO uint32_t PCNT : 1; + __IO uint32_t RTC : 1; + __IO uint32_t TRIM : 1; + __IO uint32_t LCD : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t TICK : 1; + __IO uint32_t SWD : 1; + __IO uint32_t CRC : 1; + __IO uint32_t AES : 1; + __IO uint32_t GPIO : 1; + __IO uint32_t DMA : 1; + uint32_t RESERVED30 : 1; + __IO uint32_t FLASH : 1; +} stc_sysctrl_peri_clken0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 3; + __IO uint32_t DAC : 1; + __IO uint32_t LPTIM1 : 1; + uint32_t RESERVED5 : 3; + __IO uint32_t UART2 : 1; + __IO uint32_t UART3 : 1; + uint32_t RESERVED10 :21; + __IO uint32_t RSV : 1; +} stc_sysctrl_peri_clken1_field_t; + +typedef struct +{ + __IO uint32_t REFSEL : 2; + __IO uint32_t FOSC : 3; + __IO uint32_t DIVN : 4; + __IO uint32_t IBSEL : 2; + __IO uint32_t LFSEL : 2; + __IO uint32_t FRSEL : 2; + __IO uint32_t STARTUP : 3; + __IO uint32_t STABLE : 1; + uint32_t RESERVED19 :12; + __IO uint32_t RSV : 1; +} stc_sysctrl_pll_cr_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim0_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim0_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim0_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VCE : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim1_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim1_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim1_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VCE : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim2_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim2_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim2_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VCE : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim3_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim3_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + __IO uint32_t CA1F : 1; + __IO uint32_t CA2F : 1; + __IO uint32_t CB0F : 1; + __IO uint32_t CB1F : 1; + __IO uint32_t CB2F : 1; + __IO uint32_t CA0E : 1; + __IO uint32_t CA1E : 1; + __IO uint32_t CA2E : 1; + __IO uint32_t CB0E : 1; + __IO uint32_t CB1E : 1; + __IO uint32_t CB2E : 1; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + __IO uint32_t CA1F : 1; + __IO uint32_t CA2F : 1; + __IO uint32_t CB0F : 1; + __IO uint32_t CB1F : 1; + __IO uint32_t CB2F : 1; + __IO uint32_t CA0E : 1; + __IO uint32_t CA1E : 1; + __IO uint32_t CA2E : 1; + __IO uint32_t CB0E : 1; + __IO uint32_t CB1E : 1; + __IO uint32_t CB2E : 1; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + __IO uint32_t OCMA1_FLTA1 : 3; + __IO uint32_t CCPA1 : 1; + __IO uint32_t OCMB1_FLTB1 : 3; + __IO uint32_t CCPB1 : 1; + __IO uint32_t OCMA2_FLTA2 : 3; + __IO uint32_t CCPA2 : 1; + __IO uint32_t OCMB2_FLTB2 : 3; + __IO uint32_t CCPB2 : 1; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim3_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + __IO uint32_t CMA1E : 1; + __IO uint32_t CMA2E : 1; + __IO uint32_t CMB0E : 1; + __IO uint32_t CMB1E : 1; + __IO uint32_t CMB2E : 1; + __IO uint32_t ADTE : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_crch1_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_crch2_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VCE : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t CCR1A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr1a_field_t; + +typedef struct +{ + __IO uint32_t CCR1B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr1b_field_t; + +typedef struct +{ + __IO uint32_t CCR2A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr2a_field_t; + +typedef struct +{ + __IO uint32_t CCR2B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr2b_field_t; + +typedef struct +{ + __IO uint32_t RNGCIR_EN : 1; + __IO uint32_t RNG_RUN : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_trng_cr_field_t; + +typedef struct +{ + __IO uint32_t LOAD : 1; + __IO uint32_t FDBK : 1; + __IO uint32_t CNT : 3; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_trng_mode_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_trng_data0_field_t; + +typedef struct +{ + __IO uint32_t DATA1 :32; +} stc_trng_data1_field_t; + +typedef struct +{ + __IO uint32_t DATA : 8; + __IO uint32_t DATA8 : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_uart_sbuf_field_t; + +typedef struct +{ + __IO uint32_t RCIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t B8CONT : 2; + __IO uint32_t REN : 1; + __IO uint32_t ADRDET : 1; + __IO uint32_t SM : 2; + __IO uint32_t TXEIE : 1; + __IO uint32_t OVER : 1; + uint32_t RESERVED10 : 3; + __IO uint32_t PEIE : 1; + __IO uint32_t STOPBIT : 2; + __IO uint32_t DMARXEN : 1; + __IO uint32_t DMATXEN : 1; + __IO uint32_t RTSEN : 1; + __IO uint32_t CTSEN : 1; + __IO uint32_t CTSIE : 1; + __IO uint32_t FEIE : 1; + __IO uint32_t HDSEL : 1; + uint32_t RESERVED23 : 8; + __IO uint32_t RSV : 1; +} stc_uart_scon_field_t; + +typedef struct +{ + __IO uint32_t SADDR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_uart_saddr_field_t; + +typedef struct +{ + __IO uint32_t SADEN : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_uart_saden_field_t; + +typedef struct +{ + __IO uint32_t RC : 1; + __IO uint32_t TC : 1; + __IO uint32_t FE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t PE : 1; + __IO uint32_t CTSIF : 1; + __IO uint32_t CTS : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_uart_isr_field_t; + +typedef struct +{ + __IO uint32_t RCCF : 1; + __IO uint32_t TCCF : 1; + __IO uint32_t FECF : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PECF : 1; + __IO uint32_t CTSIFCF : 1; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_uart_icr_field_t; + +typedef struct +{ + __IO uint32_t SCNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_uart_scnt_field_t; + +typedef struct +{ + __IO uint32_t DIV : 6; + __IO uint32_t DIV_EN : 1; + __IO uint32_t REF2P5_SEL : 1; + __IO uint32_t VC0_BIAS_SEL : 2; + __IO uint32_t VC0_HYS_SEL : 2; + __IO uint32_t VC1_BIAS_SEL : 2; + __IO uint32_t VC1_HYS_SEL : 2; + __IO uint32_t VC2_BIAS_SEL : 2; + __IO uint32_t VC2_HYS_SEL : 2; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_vc_cr_field_t; + +typedef struct +{ + __IO uint32_t P_SEL : 4; + __IO uint32_t N_SEL : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FALLING : 1; + __IO uint32_t RISING : 1; + __IO uint32_t LEVEL : 1; + __IO uint32_t IE : 1; + __IO uint32_t EN : 1; + uint32_t RESERVED17 :14; + __IO uint32_t RSV : 1; +} stc_vc_vc0_cr_field_t; + +typedef struct +{ + __IO uint32_t P_SEL : 4; + __IO uint32_t N_SEL : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FALLING : 1; + __IO uint32_t RISING : 1; + __IO uint32_t LEVEL : 1; + __IO uint32_t IE : 1; + __IO uint32_t EN : 1; + uint32_t RESERVED17 :14; + __IO uint32_t RSV : 1; +} stc_vc_vc1_cr_field_t; + +typedef struct +{ + __IO uint32_t INV_TIMER : 1; + __IO uint32_t TIM0RCLR : 1; + __IO uint32_t TIM1RCLR : 1; + __IO uint32_t TIM2RCLR : 1; + __IO uint32_t TIM3RCLR : 1; + __IO uint32_t TIMBK : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t INV_TIM4 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t INV_TIM5 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t INV_TIM6 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t BRAKE : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_vc_vc0_out_cfg_field_t; + +typedef struct +{ + __IO uint32_t INV_TIMER : 1; + __IO uint32_t TIM0RCLR : 1; + __IO uint32_t TIM1RCLR : 1; + __IO uint32_t TIM2RCLR : 1; + __IO uint32_t TIM3RCLR : 1; + __IO uint32_t TIMBK : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t INV_TIM4 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t INV_TIM5 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t INV_TIM6 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t BRAKE : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_vc_vc1_out_cfg_field_t; + +typedef struct +{ + __IO uint32_t VC0_INTF : 1; + __IO uint32_t VC1_INTF : 1; + __IO uint32_t VC0_FILTER : 1; + __IO uint32_t VC1_FILTER : 1; + __IO uint32_t VC2_INTF : 1; + __IO uint32_t VC2_FILTER : 1; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_vc_ifr_field_t; + +typedef struct +{ + __IO uint32_t P_SEL : 4; + __IO uint32_t N_SEL : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FALLING : 1; + __IO uint32_t RISING : 1; + __IO uint32_t LEVEL : 1; + __IO uint32_t IE : 1; + __IO uint32_t EN : 1; + uint32_t RESERVED17 :14; + __IO uint32_t RSV : 1; +} stc_vc_vc2_cr_field_t; + +typedef struct +{ + __IO uint32_t INV_TIMER : 1; + __IO uint32_t TIM0RCLR : 1; + __IO uint32_t TIM1RCLR : 1; + __IO uint32_t TIM2RCLR : 1; + __IO uint32_t TIM3RCLR : 1; + __IO uint32_t TIMBK : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t INV_TIM4 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t INV_TIM5 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t INV_TIM6 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t BRAKE : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_vc_vc2_out_cfg_field_t; + +typedef struct +{ + __IO uint32_t RST : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_wdt_rst_field_t; + +typedef struct +{ + __IO uint32_t WOV : 4; + __IO uint32_t R : 1; + __IO uint32_t WINT_EN : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t INT : 1; + __IO uint32_t WCNTL : 8; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_wdt_con_field_t; + + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CR0; + stc_adc_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_adc_cr1_field_t CR1_f; + }; + uint8_t RESERVED2[52]; + union + { + __IO uint32_t SQR0; + stc_adc_sqr0_field_t SQR0_f; + }; + union + { + __IO uint32_t SQR1; + stc_adc_sqr1_field_t SQR1_f; + }; + union + { + __IO uint32_t SQR2; + stc_adc_sqr2_field_t SQR2_f; + }; + union + { + __IO uint32_t JQR; + stc_adc_jqr_field_t JQR_f; + }; + union + { + __IO uint32_t SQRRESULT0; + stc_adc_sqrresult0_field_t SQRRESULT0_f; + }; + union + { + __IO uint32_t SQRRESULT1; + stc_adc_sqrresult1_field_t SQRRESULT1_f; + }; + union + { + __IO uint32_t SQRRESULT2; + stc_adc_sqrresult2_field_t SQRRESULT2_f; + }; + union + { + __IO uint32_t SQRRESULT3; + stc_adc_sqrresult3_field_t SQRRESULT3_f; + }; + union + { + __IO uint32_t SQRRESULT4; + stc_adc_sqrresult4_field_t SQRRESULT4_f; + }; + union + { + __IO uint32_t SQRRESULT5; + stc_adc_sqrresult5_field_t SQRRESULT5_f; + }; + union + { + __IO uint32_t SQRRESULT6; + stc_adc_sqrresult6_field_t SQRRESULT6_f; + }; + union + { + __IO uint32_t SQRRESULT7; + stc_adc_sqrresult7_field_t SQRRESULT7_f; + }; + union + { + __IO uint32_t SQRRESULT8; + stc_adc_sqrresult8_field_t SQRRESULT8_f; + }; + union + { + __IO uint32_t SQRRESULT9; + stc_adc_sqrresult9_field_t SQRRESULT9_f; + }; + union + { + __IO uint32_t SQRRESULT10; + stc_adc_sqrresult10_field_t SQRRESULT10_f; + }; + union + { + __IO uint32_t SQRRESULT11; + stc_adc_sqrresult11_field_t SQRRESULT11_f; + }; + union + { + __IO uint32_t SQRRESULT12; + stc_adc_sqrresult12_field_t SQRRESULT12_f; + }; + union + { + __IO uint32_t SQR_RESULT13; + stc_adc_sqr_result13_field_t SQR_RESULT13_f; + }; + union + { + __IO uint32_t SQRRESULT14; + stc_adc_sqrresult14_field_t SQRRESULT14_f; + }; + union + { + __IO uint32_t SQRRESULT15; + stc_adc_sqrresult15_field_t SQRRESULT15_f; + }; + union + { + __IO uint32_t JQRRESULT0; + stc_adc_jqrresult0_field_t JQRRESULT0_f; + }; + union + { + __IO uint32_t JQRRESULT1; + stc_adc_jqrresult1_field_t JQRRESULT1_f; + }; + union + { + __IO uint32_t JQRRESULT2; + stc_adc_jqrresult2_field_t JQRRESULT2_f; + }; + union + { + __IO uint32_t JQRRESULT3; + stc_adc_jqrresult3_field_t JQRRESULT3_f; + }; + union + { + __IO uint32_t RESULT; + stc_adc_result_field_t RESULT_f; + }; + union + { + __IO uint32_t RESULTACC; + stc_adc_resultacc_field_t RESULTACC_f; + }; + union + { + __IO uint32_t HT; + stc_adc_ht_field_t HT_f; + }; + union + { + __IO uint32_t LT; + stc_adc_lt_field_t LT_f; + }; + union + { + __IO uint32_t IFR; + stc_adc_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICR; + stc_adc_icr_field_t ICR_f; + }; + union + { + __IO uint32_t EXTTRIGGER0; + stc_adc_exttrigger0_field_t EXTTRIGGER0_f; + }; + union + { + __IO uint32_t EXTTRIGGER1; + stc_adc_exttrigger1_field_t EXTTRIGGER1_f; + }; + union + { + __IO uint32_t SGLSTART; + stc_adc_sglstart_field_t SGLSTART_f; + }; + union + { + __IO uint32_t SQRSTART; + stc_adc_sqrstart_field_t SQRSTART_f; + }; + union + { + __IO uint32_t JQRSTART; + stc_adc_jqrstart_field_t JQRSTART_f; + }; + union + { + __IO uint32_t ALLSTART; + stc_adc_allstart_field_t ALLSTART_f; + }; +}M0P_ADC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_adtim_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_adtim_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_adtim_perbr_field_t PERBR_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t GCMAR; + stc_adtim_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_adtim_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_adtim_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_adtim_gcmdr_field_t GCMDR_f; + }; + uint8_t RESERVED7[8]; + union + { + __IO uint32_t SCMAR; + stc_adtim_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_adtim_scmbr_field_t SCMBR_f; + }; + uint8_t RESERVED9[16]; + union + { + __IO uint32_t DTUAR; + stc_adtim_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_adtim_dtdar_field_t DTDAR_f; + }; + uint8_t RESERVED11[8]; + union + { + __IO uint32_t GCONR; + stc_adtim_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_adtim_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_adtim_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_adtim_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_adtim_dconr_field_t DCONR_f; + }; + uint8_t RESERVED16[4]; + union + { + __IO uint32_t FCONR; + stc_adtim_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_adtim_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_adtim_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_adtim_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_adtim_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCELR; + stc_adtim_hcelr_field_t HCELR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_adtim_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_adtim_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_adtim_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_adtim_hcdor_field_t HCDOR_f; + }; + uint8_t RESERVED26[112]; + union + { + __IO uint32_t IFR; + stc_adtim_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_adtim_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CR; + stc_adtim_cr_field_t CR_f; + }; + uint8_t RESERVED29[4]; + union + { + __IO uint32_t AOSSR; + stc_adtim_aossr_field_t AOSSR_f; + }; + union + { + __IO uint32_t AOSCL; + stc_adtim_aoscl_field_t AOSCL_f; + }; + union + { + __IO uint32_t PTBKS; + stc_adtim_ptbks_field_t PTBKS_f; + }; + union + { + __IO uint32_t TTRIG; + stc_adtim_ttrig_field_t TTRIG_f; + }; + union + { + __IO uint32_t ITRIG; + stc_adtim_itrig_field_t ITRIG_f; + }; + union + { + __IO uint32_t PTBKP; + stc_adtim_ptbkp_field_t PTBKP_f; + }; + uint8_t RESERVED35[716]; + union + { + __IO uint32_t SSTAR; + stc_adtim_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_adtim_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_adtim_sclrr_field_t SCLRR_f; + }; +}M0P_ADTIM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_aes_cr_field_t CR_f; + }; + uint8_t RESERVED1[12]; + union + { + __IO uint32_t DATA0; + stc_aes_data0_field_t DATA0_f; + }; + union + { + __IO uint32_t DATA1; + stc_aes_data1_field_t DATA1_f; + }; + union + { + __IO uint32_t DATA2; + stc_aes_data2_field_t DATA2_f; + }; + union + { + __IO uint32_t DATA3; + stc_aes_data3_field_t DATA3_f; + }; + union + { + __IO uint32_t KEY0; + stc_aes_key0_field_t KEY0_f; + }; + union + { + __IO uint32_t KEY1; + stc_aes_key1_field_t KEY1_f; + }; + union + { + __IO uint32_t KEY2; + stc_aes_key2_field_t KEY2_f; + }; + union + { + __IO uint32_t KEY3; + stc_aes_key3_field_t KEY3_f; + }; + union + { + __IO uint32_t KEY4; + stc_aes_key4_field_t KEY4_f; + }; + union + { + __IO uint32_t KEY5; + stc_aes_key5_field_t KEY5_f; + }; + union + { + __IO uint32_t KEY6; + stc_aes_key6_field_t KEY6_f; + }; + union + { + __IO uint32_t KEY7; + stc_aes_key7_field_t KEY7_f; + }; +}M0P_AES_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_bgr_cr_field_t CR_f; + }; +}M0P_BGR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_clk_trim_cr_field_t CR_f; + }; + union + { + __IO uint32_t REFCON; + stc_clk_trim_refcon_field_t REFCON_f; + }; + union + { + __IO uint32_t REFCNT; + stc_clk_trim_refcnt_field_t REFCNT_f; + }; + union + { + __IO uint32_t CALCNT; + stc_clk_trim_calcnt_field_t CALCNT_f; + }; + union + { + __IO uint32_t IFR; + stc_clk_trim_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_clk_trim_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CALCON; + stc_clk_trim_calcon_field_t CALCON_f; + }; +}M0P_CLK_TRIM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_crc_cr_field_t CR_f; + }; + union + { + __IO uint32_t RESULT; + stc_crc_result_field_t RESULT_f; + }; + uint8_t RESERVED2[120]; + union + { + __IO uint32_t DATA; + stc_crc_data_field_t DATA_f; + }; +}M0P_CRC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_dac_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t SWTRIGR; + stc_dac_swtrigr_field_t SWTRIGR_f; + }; + union + { + __IO uint32_t DHR12R0; + stc_dac_dhr12r0_field_t DHR12R0_f; + }; + union + { + __IO uint32_t DHR12L0; + stc_dac_dhr12l0_field_t DHR12L0_f; + }; + union + { + __IO uint32_t DHR8R0; + stc_dac_dhr8r0_field_t DHR8R0_f; + }; + uint8_t RESERVED5[24]; + union + { + __IO uint32_t DOR0; + stc_dac_dor0_field_t DOR0_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t SR; + stc_dac_sr_field_t SR_f; + }; + union + { + __IO uint32_t ETRS; + stc_dac_etrs_field_t ETRS_f; + }; +}M0P_DAC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t DEBUG_ACTIVE; + stc_debug_active_field_t DEBUG_ACTIVE_f; + }; +}M0P_DEBUG_ACTIVE_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CONF; + stc_dmac_conf_field_t CONF_f; + }; + uint8_t RESERVED1[12]; + union + { + __IO uint32_t CONFA0; + stc_dmac_confa0_field_t CONFA0_f; + }; + union + { + __IO uint32_t CONFB0; + stc_dmac_confb0_field_t CONFB0_f; + }; + union + { + __IO uint32_t SRCADR0; + stc_dmac_srcadr0_field_t SRCADR0_f; + }; + union + { + __IO uint32_t DSTADR0; + stc_dmac_dstadr0_field_t DSTADR0_f; + }; + union + { + __IO uint32_t CONFA1; + stc_dmac_confa1_field_t CONFA1_f; + }; + union + { + __IO uint32_t CONFB1; + stc_dmac_confb1_field_t CONFB1_f; + }; + union + { + __IO uint32_t SRCADR1; + stc_dmac_srcadr1_field_t SRCADR1_f; + }; + union + { + __IO uint32_t DSTADR1; + stc_dmac_dstadr1_field_t DSTADR1_f; + }; +}M0P_DMAC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t TNVS; + stc_flash_tnvs_field_t TNVS_f; + }; + union + { + __IO uint32_t TPGS; + stc_flash_tpgs_field_t TPGS_f; + }; + union + { + __IO uint32_t TPROG; + stc_flash_tprog_field_t TPROG_f; + }; + union + { + __IO uint32_t TSERASE; + stc_flash_tserase_field_t TSERASE_f; + }; + union + { + __IO uint32_t TMERASE; + stc_flash_tmerase_field_t TMERASE_f; + }; + union + { + __IO uint32_t TPRCV; + stc_flash_tprcv_field_t TPRCV_f; + }; + union + { + __IO uint32_t TSRCV; + stc_flash_tsrcv_field_t TSRCV_f; + }; + union + { + __IO uint32_t TMRCV; + stc_flash_tmrcv_field_t TMRCV_f; + }; + union + { + __IO uint32_t CR; + stc_flash_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_flash_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_flash_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t BYPASS; + stc_flash_bypass_field_t BYPASS_f; + }; + union + { + __IO uint32_t SLOCK0; + stc_flash_slock0_field_t SLOCK0_f; + }; + union + { + __IO uint32_t SLOCK1; + stc_flash_slock1_field_t SLOCK1_f; + }; +}M0P_FLASH_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t PA00_SEL; + stc_gpio_pa00_sel_field_t PA00_SEL_f; + }; + union + { + __IO uint32_t PA01_SEL; + stc_gpio_pa01_sel_field_t PA01_SEL_f; + }; + union + { + __IO uint32_t PA02_SEL; + stc_gpio_pa02_sel_field_t PA02_SEL_f; + }; + union + { + __IO uint32_t PA03_SEL; + stc_gpio_pa03_sel_field_t PA03_SEL_f; + }; + union + { + __IO uint32_t PA04_SEL; + stc_gpio_pa04_sel_field_t PA04_SEL_f; + }; + union + { + __IO uint32_t PA05_SEL; + stc_gpio_pa05_sel_field_t PA05_SEL_f; + }; + union + { + __IO uint32_t PA06_SEL; + stc_gpio_pa06_sel_field_t PA06_SEL_f; + }; + union + { + __IO uint32_t PA07_SEL; + stc_gpio_pa07_sel_field_t PA07_SEL_f; + }; + union + { + __IO uint32_t PA08_SEL; + stc_gpio_pa08_sel_field_t PA08_SEL_f; + }; + union + { + __IO uint32_t PA09_SEL; + stc_gpio_pa09_sel_field_t PA09_SEL_f; + }; + union + { + __IO uint32_t PA10_SEL; + stc_gpio_pa10_sel_field_t PA10_SEL_f; + }; + union + { + __IO uint32_t PA11_SEL; + stc_gpio_pa11_sel_field_t PA11_SEL_f; + }; + union + { + __IO uint32_t PA12_SEL; + stc_gpio_pa12_sel_field_t PA12_SEL_f; + }; + union + { + __IO uint32_t PA13_SEL; + stc_gpio_pa13_sel_field_t PA13_SEL_f; + }; + union + { + __IO uint32_t PA14_SEL; + stc_gpio_pa14_sel_field_t PA14_SEL_f; + }; + union + { + __IO uint32_t PA15_SEL; + stc_gpio_pa15_sel_field_t PA15_SEL_f; + }; + union + { + __IO uint32_t PB00_SEL; + stc_gpio_pb00_sel_field_t PB00_SEL_f; + }; + union + { + __IO uint32_t PB01_SEL; + stc_gpio_pb01_sel_field_t PB01_SEL_f; + }; + union + { + __IO uint32_t PB02_SEL; + stc_gpio_pb02_sel_field_t PB02_SEL_f; + }; + union + { + __IO uint32_t PB03_SEL; + stc_gpio_pb03_sel_field_t PB03_SEL_f; + }; + union + { + __IO uint32_t PB04_SEL; + stc_gpio_pb04_sel_field_t PB04_SEL_f; + }; + union + { + __IO uint32_t PB05_SEL; + stc_gpio_pb05_sel_field_t PB05_SEL_f; + }; + union + { + __IO uint32_t PB06_SEL; + stc_gpio_pb06_sel_field_t PB06_SEL_f; + }; + union + { + __IO uint32_t PB07_SEL; + stc_gpio_pb07_sel_field_t PB07_SEL_f; + }; + union + { + __IO uint32_t PB08_SEL; + stc_gpio_pb08_sel_field_t PB08_SEL_f; + }; + union + { + __IO uint32_t PB09_SEL; + stc_gpio_pb09_sel_field_t PB09_SEL_f; + }; + union + { + __IO uint32_t PB10_SEL; + stc_gpio_pb10_sel_field_t PB10_SEL_f; + }; + union + { + __IO uint32_t PB11_SEL; + stc_gpio_pb11_sel_field_t PB11_SEL_f; + }; + union + { + __IO uint32_t PB12_SEL; + stc_gpio_pb12_sel_field_t PB12_SEL_f; + }; + union + { + __IO uint32_t PB13_SEL; + stc_gpio_pb13_sel_field_t PB13_SEL_f; + }; + union + { + __IO uint32_t PB14_SEL; + stc_gpio_pb14_sel_field_t PB14_SEL_f; + }; + union + { + __IO uint32_t PB15_SEL; + stc_gpio_pb15_sel_field_t PB15_SEL_f; + }; + union + { + __IO uint32_t PC00_SEL; + stc_gpio_pc00_sel_field_t PC00_SEL_f; + }; + union + { + __IO uint32_t PC01_SEL; + stc_gpio_pc01_sel_field_t PC01_SEL_f; + }; + union + { + __IO uint32_t PC02_SEL; + stc_gpio_pc02_sel_field_t PC02_SEL_f; + }; + union + { + __IO uint32_t PC03_SEL; + stc_gpio_pc03_sel_field_t PC03_SEL_f; + }; + union + { + __IO uint32_t PC04_SEL; + stc_gpio_pc04_sel_field_t PC04_SEL_f; + }; + union + { + __IO uint32_t PC05_SEL; + stc_gpio_pc05_sel_field_t PC05_SEL_f; + }; + union + { + __IO uint32_t PC06_SEL; + stc_gpio_pc06_sel_field_t PC06_SEL_f; + }; + union + { + __IO uint32_t PC07_SEL; + stc_gpio_pc07_sel_field_t PC07_SEL_f; + }; + union + { + __IO uint32_t PC08_SEL; + stc_gpio_pc08_sel_field_t PC08_SEL_f; + }; + union + { + __IO uint32_t PC09_SEL; + stc_gpio_pc09_sel_field_t PC09_SEL_f; + }; + union + { + __IO uint32_t PC10_SEL; + stc_gpio_pc10_sel_field_t PC10_SEL_f; + }; + union + { + __IO uint32_t PC11_SEL; + stc_gpio_pc11_sel_field_t PC11_SEL_f; + }; + union + { + __IO uint32_t PC12_SEL; + stc_gpio_pc12_sel_field_t PC12_SEL_f; + }; + union + { + __IO uint32_t PC13_SEL; + stc_gpio_pc13_sel_field_t PC13_SEL_f; + }; + union + { + __IO uint32_t PC14_SEL; + stc_gpio_pc14_sel_field_t PC14_SEL_f; + }; + union + { + __IO uint32_t PC15_SEL; + stc_gpio_pc15_sel_field_t PC15_SEL_f; + }; + union + { + __IO uint32_t PD00_SEL; + stc_gpio_pd00_sel_field_t PD00_SEL_f; + }; + union + { + __IO uint32_t PD01_SEL; + stc_gpio_pd01_sel_field_t PD01_SEL_f; + }; + union + { + __IO uint32_t PD02_SEL; + stc_gpio_pd02_sel_field_t PD02_SEL_f; + }; + union + { + __IO uint32_t PD03_SEL; + stc_gpio_pd03_sel_field_t PD03_SEL_f; + }; + union + { + __IO uint32_t PD04_SEL; + stc_gpio_pd04_sel_field_t PD04_SEL_f; + }; + union + { + __IO uint32_t PD05_SEL; + stc_gpio_pd05_sel_field_t PD05_SEL_f; + }; + union + { + __IO uint32_t PD06_SEL; + stc_gpio_pd06_sel_field_t PD06_SEL_f; + }; + union + { + __IO uint32_t PD07_SEL; + stc_gpio_pd07_sel_field_t PD07_SEL_f; + }; + union + { + __IO uint32_t PD08_SEL; + stc_gpio_pd08_sel_field_t PD08_SEL_f; + }; + union + { + __IO uint32_t PD09_SEL; + stc_gpio_pd09_sel_field_t PD09_SEL_f; + }; + union + { + __IO uint32_t PD10_SEL; + stc_gpio_pd10_sel_field_t PD10_SEL_f; + }; + union + { + __IO uint32_t PD11_SEL; + stc_gpio_pd11_sel_field_t PD11_SEL_f; + }; + union + { + __IO uint32_t PD12_SEL; + stc_gpio_pd12_sel_field_t PD12_SEL_f; + }; + union + { + __IO uint32_t PD13_SEL; + stc_gpio_pd13_sel_field_t PD13_SEL_f; + }; + union + { + __IO uint32_t PD14_SEL; + stc_gpio_pd14_sel_field_t PD14_SEL_f; + }; + union + { + __IO uint32_t PD15_SEL; + stc_gpio_pd15_sel_field_t PD15_SEL_f; + }; + union + { + __IO uint32_t PADIR; + stc_gpio_padir_field_t PADIR_f; + }; + union + { + __IO uint32_t PAIN; + stc_gpio_pain_field_t PAIN_f; + }; + union + { + __IO uint32_t PAOUT; + stc_gpio_paout_field_t PAOUT_f; + }; + union + { + __IO uint32_t PAADS; + stc_gpio_paads_field_t PAADS_f; + }; + union + { + __IO uint32_t PABSET; + stc_gpio_pabset_field_t PABSET_f; + }; + union + { + __IO uint32_t PABCLR; + stc_gpio_pabclr_field_t PABCLR_f; + }; + union + { + __IO uint32_t PABSETCLR; + stc_gpio_pabsetclr_field_t PABSETCLR_f; + }; + union + { + __IO uint32_t PADR; + stc_gpio_padr_field_t PADR_f; + }; + union + { + __IO uint32_t PAPU; + stc_gpio_papu_field_t PAPU_f; + }; + union + { + __IO uint32_t PAPD; + stc_gpio_papd_field_t PAPD_f; + }; + uint8_t RESERVED74[4]; + union + { + __IO uint32_t PAOD; + stc_gpio_paod_field_t PAOD_f; + }; + union + { + __IO uint32_t PAHIE; + stc_gpio_pahie_field_t PAHIE_f; + }; + union + { + __IO uint32_t PALIE; + stc_gpio_palie_field_t PALIE_f; + }; + union + { + __IO uint32_t PARIE; + stc_gpio_parie_field_t PARIE_f; + }; + union + { + __IO uint32_t PAFIE; + stc_gpio_pafie_field_t PAFIE_f; + }; + union + { + __IO uint32_t PBDIR; + stc_gpio_pbdir_field_t PBDIR_f; + }; + union + { + __IO uint32_t PBIN; + stc_gpio_pbin_field_t PBIN_f; + }; + union + { + __IO uint32_t PBOUT; + stc_gpio_pbout_field_t PBOUT_f; + }; + union + { + __IO uint32_t PBADS; + stc_gpio_pbads_field_t PBADS_f; + }; + union + { + __IO uint32_t PBBSET; + stc_gpio_pbbset_field_t PBBSET_f; + }; + union + { + __IO uint32_t PBBCLR; + stc_gpio_pbbclr_field_t PBBCLR_f; + }; + union + { + __IO uint32_t PBBSETCLR; + stc_gpio_pbbsetclr_field_t PBBSETCLR_f; + }; + union + { + __IO uint32_t PBDR; + stc_gpio_pbdr_field_t PBDR_f; + }; + union + { + __IO uint32_t PBPU; + stc_gpio_pbpu_field_t PBPU_f; + }; + union + { + __IO uint32_t PBPD; + stc_gpio_pbpd_field_t PBPD_f; + }; + uint8_t RESERVED89[4]; + union + { + __IO uint32_t PBOD; + stc_gpio_pbod_field_t PBOD_f; + }; + union + { + __IO uint32_t PBHIE; + stc_gpio_pbhie_field_t PBHIE_f; + }; + union + { + __IO uint32_t PBLIE; + stc_gpio_pblie_field_t PBLIE_f; + }; + union + { + __IO uint32_t PBRIE; + stc_gpio_pbrie_field_t PBRIE_f; + }; + union + { + __IO uint32_t PBFIE; + stc_gpio_pbfie_field_t PBFIE_f; + }; + union + { + __IO uint32_t PCDIR; + stc_gpio_pcdir_field_t PCDIR_f; + }; + union + { + __IO uint32_t PCIN; + stc_gpio_pcin_field_t PCIN_f; + }; + union + { + __IO uint32_t PCOUT; + stc_gpio_pcout_field_t PCOUT_f; + }; + union + { + __IO uint32_t PCADS; + stc_gpio_pcads_field_t PCADS_f; + }; + union + { + __IO uint32_t PCBSET; + stc_gpio_pcbset_field_t PCBSET_f; + }; + union + { + __IO uint32_t PCBCLR; + stc_gpio_pcbclr_field_t PCBCLR_f; + }; + union + { + __IO uint32_t PCBSETCLR; + stc_gpio_pcbsetclr_field_t PCBSETCLR_f; + }; + union + { + __IO uint32_t PCDR; + stc_gpio_pcdr_field_t PCDR_f; + }; + union + { + __IO uint32_t PCPU; + stc_gpio_pcpu_field_t PCPU_f; + }; + union + { + __IO uint32_t PCPD; + stc_gpio_pcpd_field_t PCPD_f; + }; + uint8_t RESERVED104[4]; + union + { + __IO uint32_t PCOD; + stc_gpio_pcod_field_t PCOD_f; + }; + union + { + __IO uint32_t PCHIE; + stc_gpio_pchie_field_t PCHIE_f; + }; + union + { + __IO uint32_t PCLIE; + stc_gpio_pclie_field_t PCLIE_f; + }; + union + { + __IO uint32_t PCRIE; + stc_gpio_pcrie_field_t PCRIE_f; + }; + union + { + __IO uint32_t PCFIE; + stc_gpio_pcfie_field_t PCFIE_f; + }; + union + { + __IO uint32_t PDDIR; + stc_gpio_pddir_field_t PDDIR_f; + }; + union + { + __IO uint32_t PDIN; + stc_gpio_pdin_field_t PDIN_f; + }; + union + { + __IO uint32_t PDOUT; + stc_gpio_pdout_field_t PDOUT_f; + }; + union + { + __IO uint32_t PDADS; + stc_gpio_pdads_field_t PDADS_f; + }; + union + { + __IO uint32_t PDBSET; + stc_gpio_pdbset_field_t PDBSET_f; + }; + union + { + __IO uint32_t PDBCLR; + stc_gpio_pdbclr_field_t PDBCLR_f; + }; + union + { + __IO uint32_t PDBSETCLR; + stc_gpio_pdbsetclr_field_t PDBSETCLR_f; + }; + union + { + __IO uint32_t PDDR; + stc_gpio_pddr_field_t PDDR_f; + }; + union + { + __IO uint32_t PDPU; + stc_gpio_pdpu_field_t PDPU_f; + }; + union + { + __IO uint32_t PDPD; + stc_gpio_pdpd_field_t PDPD_f; + }; + uint8_t RESERVED119[4]; + union + { + __IO uint32_t PDOD; + stc_gpio_pdod_field_t PDOD_f; + }; + union + { + __IO uint32_t PDHIE; + stc_gpio_pdhie_field_t PDHIE_f; + }; + union + { + __IO uint32_t PDLIE; + stc_gpio_pdlie_field_t PDLIE_f; + }; + union + { + __IO uint32_t PDRIE; + stc_gpio_pdrie_field_t PDRIE_f; + }; + union + { + __IO uint32_t PDFIE; + stc_gpio_pdfie_field_t PDFIE_f; + }; + union + { + __IO uint32_t PA_STAT; + stc_gpio_pa_stat_field_t PA_STAT_f; + }; + uint8_t RESERVED125[12]; + union + { + __IO uint32_t PA_ICLR; + stc_gpio_pa_iclr_field_t PA_ICLR_f; + }; + uint8_t RESERVED126[44]; + union + { + __IO uint32_t PB_STAT; + stc_gpio_pb_stat_field_t PB_STAT_f; + }; + uint8_t RESERVED127[12]; + union + { + __IO uint32_t PB_ICLR; + stc_gpio_pb_iclr_field_t PB_ICLR_f; + }; + uint8_t RESERVED128[44]; + union + { + __IO uint32_t PC_STAT; + stc_gpio_pc_stat_field_t PC_STAT_f; + }; + uint8_t RESERVED129[12]; + union + { + __IO uint32_t PC_ICLR; + stc_gpio_pc_iclr_field_t PC_ICLR_f; + }; + uint8_t RESERVED130[44]; + union + { + __IO uint32_t PD_STAT; + stc_gpio_pd_stat_field_t PD_STAT_f; + }; + uint8_t RESERVED131[12]; + union + { + __IO uint32_t PD_ICLR; + stc_gpio_pd_iclr_field_t PD_ICLR_f; + }; + uint8_t RESERVED132[44]; + union + { + __IO uint32_t CTRL0; + stc_gpio_ctrl0_field_t CTRL0_f; + }; + union + { + __IO uint32_t CTRL1; + stc_gpio_ctrl1_field_t CTRL1_f; + }; + union + { + __IO uint32_t CTRL2; + stc_gpio_ctrl2_field_t CTRL2_f; + }; + union + { + __IO uint32_t TIMGS; + stc_gpio_timgs_field_t TIMGS_f; + }; + union + { + __IO uint32_t TIMES; + stc_gpio_times_field_t TIMES_f; + }; + union + { + __IO uint32_t TIMCPS; + stc_gpio_timcps_field_t TIMCPS_f; + }; + union + { + __IO uint32_t PCAS; + stc_gpio_pcas_field_t PCAS_f; + }; + union + { + __IO uint32_t PCNT; + stc_gpio_pcnt_field_t PCNT_f; + }; + uint8_t RESERVED140[3296]; + union + { + __IO uint32_t PE00_SEL; + stc_gpio_pe00_sel_field_t PE00_SEL_f; + }; + union + { + __IO uint32_t PE01_SEL; + stc_gpio_pe01_sel_field_t PE01_SEL_f; + }; + union + { + __IO uint32_t PE02_SEL; + stc_gpio_pe02_sel_field_t PE02_SEL_f; + }; + union + { + __IO uint32_t PE03_SEL; + stc_gpio_pe03_sel_field_t PE03_SEL_f; + }; + union + { + __IO uint32_t PE04_SEL; + stc_gpio_pe04_sel_field_t PE04_SEL_f; + }; + union + { + __IO uint32_t PE05_SEL; + stc_gpio_pe05_sel_field_t PE05_SEL_f; + }; + union + { + __IO uint32_t PE06_SEL; + stc_gpio_pe06_sel_field_t PE06_SEL_f; + }; + union + { + __IO uint32_t PE07_SEL; + stc_gpio_pe07_sel_field_t PE07_SEL_f; + }; + union + { + __IO uint32_t PE08_SEL; + stc_gpio_pe08_sel_field_t PE08_SEL_f; + }; + union + { + __IO uint32_t PE09_SEL; + stc_gpio_pe09_sel_field_t PE09_SEL_f; + }; + union + { + __IO uint32_t PE10_SEL; + stc_gpio_pe10_sel_field_t PE10_SEL_f; + }; + union + { + __IO uint32_t PE11_SEL; + stc_gpio_pe11_sel_field_t PE11_SEL_f; + }; + union + { + __IO uint32_t PE12_SEL; + stc_gpio_pe12_sel_field_t PE12_SEL_f; + }; + union + { + __IO uint32_t PE13_SEL; + stc_gpio_pe13_sel_field_t PE13_SEL_f; + }; + union + { + __IO uint32_t PE14_SEL; + stc_gpio_pe14_sel_field_t PE14_SEL_f; + }; + union + { + __IO uint32_t PE15_SEL; + stc_gpio_pe15_sel_field_t PE15_SEL_f; + }; + union + { + __IO uint32_t PF00_SEL; + stc_gpio_pf00_sel_field_t PF00_SEL_f; + }; + union + { + __IO uint32_t PF01_SEL; + stc_gpio_pf01_sel_field_t PF01_SEL_f; + }; + union + { + __IO uint32_t PF02_SEL; + stc_gpio_pf02_sel_field_t PF02_SEL_f; + }; + union + { + __IO uint32_t PF03_SEL; + stc_gpio_pf03_sel_field_t PF03_SEL_f; + }; + union + { + __IO uint32_t PF04_SEL; + stc_gpio_pf04_sel_field_t PF04_SEL_f; + }; + union + { + __IO uint32_t PF05_SEL; + stc_gpio_pf05_sel_field_t PF05_SEL_f; + }; + union + { + __IO uint32_t PF06_SEL; + stc_gpio_pf06_sel_field_t PF06_SEL_f; + }; + union + { + __IO uint32_t PF07_SEL; + stc_gpio_pf07_sel_field_t PF07_SEL_f; + }; + union + { + __IO uint32_t PF08_SEL; + stc_gpio_pf08_sel_field_t PF08_SEL_f; + }; + union + { + __IO uint32_t PF09_SEL; + stc_gpio_pf09_sel_field_t PF09_SEL_f; + }; + union + { + __IO uint32_t PF10_SEL; + stc_gpio_pf10_sel_field_t PF10_SEL_f; + }; + union + { + __IO uint32_t PF11_SEL; + stc_gpio_pf11_sel_field_t PF11_SEL_f; + }; + uint8_t RESERVED168[144]; + union + { + __IO uint32_t PEDIR; + stc_gpio_pedir_field_t PEDIR_f; + }; + union + { + __IO uint32_t PEIN; + stc_gpio_pein_field_t PEIN_f; + }; + union + { + __IO uint32_t PEOUT; + stc_gpio_peout_field_t PEOUT_f; + }; + union + { + __IO uint32_t PEADS; + stc_gpio_peads_field_t PEADS_f; + }; + union + { + __IO uint32_t PEBSET; + stc_gpio_pebset_field_t PEBSET_f; + }; + union + { + __IO uint32_t PEBCLR; + stc_gpio_pebclr_field_t PEBCLR_f; + }; + union + { + __IO uint32_t PEBSETCLR; + stc_gpio_pebsetclr_field_t PEBSETCLR_f; + }; + union + { + __IO uint32_t PEDR; + stc_gpio_pedr_field_t PEDR_f; + }; + union + { + __IO uint32_t PEPU; + stc_gpio_pepu_field_t PEPU_f; + }; + union + { + __IO uint32_t PEPD; + stc_gpio_pepd_field_t PEPD_f; + }; + uint8_t RESERVED178[4]; + union + { + __IO uint32_t PEOD; + stc_gpio_peod_field_t PEOD_f; + }; + union + { + __IO uint32_t PEHIE; + stc_gpio_pehie_field_t PEHIE_f; + }; + union + { + __IO uint32_t PELIE; + stc_gpio_pelie_field_t PELIE_f; + }; + union + { + __IO uint32_t PERIE; + stc_gpio_perie_field_t PERIE_f; + }; + union + { + __IO uint32_t PEFIE; + stc_gpio_pefie_field_t PEFIE_f; + }; + union + { + __IO uint32_t PFDIR; + stc_gpio_pfdir_field_t PFDIR_f; + }; + union + { + __IO uint32_t PFIN; + stc_gpio_pfin_field_t PFIN_f; + }; + union + { + __IO uint32_t PFOUT; + stc_gpio_pfout_field_t PFOUT_f; + }; + union + { + __IO uint32_t PFADS; + stc_gpio_pfads_field_t PFADS_f; + }; + union + { + __IO uint32_t PFBSET; + stc_gpio_pfbset_field_t PFBSET_f; + }; + union + { + __IO uint32_t PFBCLR; + stc_gpio_pfbclr_field_t PFBCLR_f; + }; + union + { + __IO uint32_t PFBSETCLR; + stc_gpio_pfbsetclr_field_t PFBSETCLR_f; + }; + union + { + __IO uint32_t PFDR; + stc_gpio_pfdr_field_t PFDR_f; + }; + union + { + __IO uint32_t PFPU; + stc_gpio_pfpu_field_t PFPU_f; + }; + union + { + __IO uint32_t PFPD; + stc_gpio_pfpd_field_t PFPD_f; + }; + uint8_t RESERVED193[4]; + union + { + __IO uint32_t PFOD; + stc_gpio_pfod_field_t PFOD_f; + }; + union + { + __IO uint32_t PFHIE; + stc_gpio_pfhie_field_t PFHIE_f; + }; + union + { + __IO uint32_t PFLIE; + stc_gpio_pflie_field_t PFLIE_f; + }; + union + { + __IO uint32_t PFRIE; + stc_gpio_pfrie_field_t PFRIE_f; + }; + union + { + __IO uint32_t PFFIE; + stc_gpio_pffie_field_t PFFIE_f; + }; + uint8_t RESERVED198[128]; + union + { + __IO uint32_t PE_STAT; + stc_gpio_pe_stat_field_t PE_STAT_f; + }; + uint8_t RESERVED199[12]; + union + { + __IO uint32_t PE_ICLR; + stc_gpio_pe_iclr_field_t PE_ICLR_f; + }; + uint8_t RESERVED200[44]; + union + { + __IO uint32_t PF_STAT; + stc_gpio_pf_stat_field_t PF_STAT_f; + }; + uint8_t RESERVED201[12]; + union + { + __IO uint32_t PF_ICLR; + stc_gpio_pf_iclr_field_t PF_ICLR_f; + }; +}M0P_GPIO_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t TMRUN; + stc_i2c_tmrun_field_t TMRUN_f; + }; + union + { + __IO uint32_t TM; + stc_i2c_tm_field_t TM_f; + }; + union + { + __IO uint32_t CR; + stc_i2c_cr_field_t CR_f; + }; + union + { + __IO uint32_t DATA; + stc_i2c_data_field_t DATA_f; + }; + union + { + __IO uint32_t ADDR; + stc_i2c_addr_field_t ADDR_f; + }; + union + { + __IO uint32_t STAT; + stc_i2c_stat_field_t STAT_f; + }; +}M0P_I2C_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_lcd_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_lcd_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t INTCLR; + stc_lcd_intclr_field_t INTCLR_f; + }; + union + { + __IO uint32_t POEN0; + stc_lcd_poen0_field_t POEN0_f; + }; + union + { + __IO uint32_t POEN1; + stc_lcd_poen1_field_t POEN1_f; + }; + uint8_t RESERVED5[44]; + union + { + __IO uint32_t RAM0; + stc_lcd_ram0_field_t RAM0_f; + }; + union + { + __IO uint32_t RAM1; + stc_lcd_ram1_field_t RAM1_f; + }; + union + { + __IO uint32_t RAM2; + stc_lcd_ram2_field_t RAM2_f; + }; + union + { + __IO uint32_t RAM3; + stc_lcd_ram3_field_t RAM3_f; + }; + union + { + __IO uint32_t RAM4; + stc_lcd_ram4_field_t RAM4_f; + }; + union + { + __IO uint32_t RAM5; + stc_lcd_ram5_field_t RAM5_f; + }; + union + { + __IO uint32_t RAM6; + stc_lcd_ram6_field_t RAM6_f; + }; + union + { + __IO uint32_t RAM7; + stc_lcd_ram7_field_t RAM7_f; + }; + union + { + __IO uint32_t RAM8; + stc_lcd_ram8_field_t RAM8_f; + }; + union + { + __IO uint32_t RAM9; + stc_lcd_ram9_field_t RAM9_f; + }; + union + { + __IO uint32_t RAMA; + stc_lcd_rama_field_t RAMA_f; + }; + union + { + __IO uint32_t RAMB; + stc_lcd_ramb_field_t RAMB_f; + }; + union + { + __IO uint32_t RAMC; + stc_lcd_ramc_field_t RAMC_f; + }; + union + { + __IO uint32_t RAMD; + stc_lcd_ramd_field_t RAMD_f; + }; + union + { + __IO uint32_t RAME; + stc_lcd_rame_field_t RAME_f; + }; + union + { + __IO uint32_t RAMF; + stc_lcd_ramf_field_t RAMF_f; + }; +}M0P_LCD_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNT; + stc_lptimer_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t ARR; + stc_lptimer_arr_field_t ARR_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t CR; + stc_lptimer_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_lptimer_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_lptimer_iclr_field_t ICLR_f; + }; +}M0P_LPTIMER_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SBUF; + stc_lpuart_sbuf_field_t SBUF_f; + }; + union + { + __IO uint32_t SCON; + stc_lpuart_scon_field_t SCON_f; + }; + union + { + __IO uint32_t SADDR; + stc_lpuart_saddr_field_t SADDR_f; + }; + union + { + __IO uint32_t SADEN; + stc_lpuart_saden_field_t SADEN_f; + }; + union + { + __IO uint32_t ISR; + stc_lpuart_isr_field_t ISR_f; + }; + union + { + __IO uint32_t ICR; + stc_lpuart_icr_field_t ICR_f; + }; + union + { + __IO uint32_t SCNT; + stc_lpuart_scnt_field_t SCNT_f; + }; +}M0P_LPUART_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[40]; + union + { + __IO uint32_t CR; + stc_lvd_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_lvd_ifr_field_t IFR_f; + }; +}M0P_LVD_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[48]; + union + { + __IO uint32_t CR0; + stc_opa_cr0_field_t CR0_f; + }; + uint8_t RESERVED1[8]; + union + { + __IO uint32_t CR1; + stc_opa_cr1_field_t CR1_f; + }; +}M0P_OPA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CCON; + stc_pca_ccon_field_t CCON_f; + }; + union + { + __IO uint32_t CMOD; + stc_pca_cmod_field_t CMOD_f; + }; + union + { + __IO uint32_t CNT; + stc_pca_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t ICLR; + stc_pca_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CCAPM0; + stc_pca_ccapm0_field_t CCAPM0_f; + }; + union + { + __IO uint32_t CCAPM1; + stc_pca_ccapm1_field_t CCAPM1_f; + }; + union + { + __IO uint32_t CCAPM2; + stc_pca_ccapm2_field_t CCAPM2_f; + }; + union + { + __IO uint32_t CCAPM3; + stc_pca_ccapm3_field_t CCAPM3_f; + }; + union + { + __IO uint32_t CCAPM4; + stc_pca_ccapm4_field_t CCAPM4_f; + }; + union + { + __IO uint32_t CCAP0H; + stc_pca_ccap0h_field_t CCAP0H_f; + }; + union + { + __IO uint32_t CCAP0L; + stc_pca_ccap0l_field_t CCAP0L_f; + }; + union + { + __IO uint32_t CCAP1H; + stc_pca_ccap1h_field_t CCAP1H_f; + }; + union + { + __IO uint32_t CCAP1L; + stc_pca_ccap1l_field_t CCAP1L_f; + }; + union + { + __IO uint32_t CCAP2H; + stc_pca_ccap2h_field_t CCAP2H_f; + }; + union + { + __IO uint32_t CCAP2L; + stc_pca_ccap2l_field_t CCAP2L_f; + }; + union + { + __IO uint32_t CCAP3H; + stc_pca_ccap3h_field_t CCAP3H_f; + }; + union + { + __IO uint32_t CCAP3L; + stc_pca_ccap3l_field_t CCAP3L_f; + }; + union + { + __IO uint32_t CCAP4H; + stc_pca_ccap4h_field_t CCAP4H_f; + }; + union + { + __IO uint32_t CCAP4L; + stc_pca_ccap4l_field_t CCAP4L_f; + }; + union + { + __IO uint32_t CCAPO; + stc_pca_ccapo_field_t CCAPO_f; + }; + union + { + __IO uint32_t CCAP0; + stc_pca_ccap0_field_t CCAP0_f; + }; + union + { + __IO uint32_t CCAP1; + stc_pca_ccap1_field_t CCAP1_f; + }; + union + { + __IO uint32_t CCAP2; + stc_pca_ccap2_field_t CCAP2_f; + }; + union + { + __IO uint32_t CCAP3; + stc_pca_ccap3_field_t CCAP3_f; + }; + union + { + __IO uint32_t CCAP4; + stc_pca_ccap4_field_t CCAP4_f; + }; + union + { + __IO uint32_t CARR; + stc_pca_carr_field_t CARR_f; + }; + union + { + __IO uint32_t EPWM; + stc_pca_epwm_field_t EPWM_f; + }; +}M0P_PCA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t RUN; + stc_pcnt_run_field_t RUN_f; + }; + union + { + __IO uint32_t CTRL; + stc_pcnt_ctrl_field_t CTRL_f; + }; + union + { + __IO uint32_t FLT; + stc_pcnt_flt_field_t FLT_f; + }; + union + { + __IO uint32_t TOCR; + stc_pcnt_tocr_field_t TOCR_f; + }; + union + { + __IO uint32_t CMD; + stc_pcnt_cmd_field_t CMD_f; + }; + union + { + __IO uint32_t SR1; + stc_pcnt_sr1_field_t SR1_f; + }; + union + { + __IO uint32_t CNT; + stc_pcnt_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t TOP; + stc_pcnt_top_field_t TOP_f; + }; + union + { + __IO uint32_t BUF; + stc_pcnt_buf_field_t BUF_f; + }; + union + { + __IO uint32_t IFR; + stc_pcnt_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICR; + stc_pcnt_icr_field_t ICR_f; + }; + union + { + __IO uint32_t IEN; + stc_pcnt_ien_field_t IEN_f; + }; + union + { + __IO uint32_t SR2; + stc_pcnt_sr2_field_t SR2_f; + }; + union + { + __IO uint32_t DBG; + stc_pcnt_dbg_field_t DBG_f; + }; +}M0P_PCNT_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_ram_cr_field_t CR_f; + }; + union + { + __IO uint32_t ERRADDR; + stc_ram_erraddr_field_t ERRADDR_f; + }; + union + { + __IO uint32_t IFR; + stc_ram_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_ram_iclr_field_t ICLR_f; + }; +}M0P_RAM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t RESET_FLAG; + stc_reset_flag_field_t RESET_FLAG_f; + }; + uint8_t RESERVED1[8]; + union + { + __IO uint32_t PERI_RESET0; + stc_reset_peri_reset0_field_t PERI_RESET0_f; + }; + union + { + __IO uint32_t PERI_RESET1; + stc_reset_peri_reset1_field_t PERI_RESET1_f; + }; +}M0P_RESET_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_rtc_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_rtc_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t SEC; + stc_rtc_sec_field_t SEC_f; + }; + union + { + __IO uint32_t MIN; + stc_rtc_min_field_t MIN_f; + }; + union + { + __IO uint32_t HOUR; + stc_rtc_hour_field_t HOUR_f; + }; + union + { + __IO uint32_t WEEK; + stc_rtc_week_field_t WEEK_f; + }; + union + { + __IO uint32_t DAY; + stc_rtc_day_field_t DAY_f; + }; + union + { + __IO uint32_t MON; + stc_rtc_mon_field_t MON_f; + }; + union + { + __IO uint32_t YEAR; + stc_rtc_year_field_t YEAR_f; + }; + union + { + __IO uint32_t ALMMIN; + stc_rtc_almmin_field_t ALMMIN_f; + }; + union + { + __IO uint32_t ALMHOUR; + stc_rtc_almhour_field_t ALMHOUR_f; + }; + union + { + __IO uint32_t ALMWEEK; + stc_rtc_almweek_field_t ALMWEEK_f; + }; + union + { + __IO uint32_t COMPEN; + stc_rtc_compen_field_t COMPEN_f; + }; + union + { + __IO uint32_t ALMSEC; + stc_rtc_almsec_field_t ALMSEC_f; + }; +}M0P_RTC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_spi_cr_field_t CR_f; + }; + union + { + __IO uint32_t SSN; + stc_spi_ssn_field_t SSN_f; + }; + union + { + __IO uint32_t STAT; + stc_spi_stat_field_t STAT_f; + }; + union + { + __IO uint32_t DATA; + stc_spi_data_field_t DATA_f; + }; + union + { + __IO uint32_t CR2; + stc_spi_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t ICLR; + stc_spi_iclr_field_t ICLR_f; + }; +}M0P_SPI_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SYSCTRL0; + stc_sysctrl_sysctrl0_field_t SYSCTRL0_f; + }; + union + { + __IO uint32_t SYSCTRL1; + stc_sysctrl_sysctrl1_field_t SYSCTRL1_f; + }; + union + { + __IO uint32_t SYSCTRL2; + stc_sysctrl_sysctrl2_field_t SYSCTRL2_f; + }; + union + { + __IO uint32_t RCH_CR; + stc_sysctrl_rch_cr_field_t RCH_CR_f; + }; + union + { + __IO uint32_t XTH_CR; + stc_sysctrl_xth_cr_field_t XTH_CR_f; + }; + union + { + __IO uint32_t RCL_CR; + stc_sysctrl_rcl_cr_field_t RCL_CR_f; + }; + union + { + __IO uint32_t XTL_CR; + stc_sysctrl_xtl_cr_field_t XTL_CR_f; + }; + uint8_t RESERVED7[4]; + union + { + __IO uint32_t PERI_CLKEN0; + stc_sysctrl_peri_clken0_field_t PERI_CLKEN0_f; + }; + union + { + __IO uint32_t PERI_CLKEN1; + stc_sysctrl_peri_clken1_field_t PERI_CLKEN1_f; + }; + uint8_t RESERVED9[20]; + union + { + __IO uint32_t PLL_CR; + stc_sysctrl_pll_cr_field_t PLL_CR_f; + }; +}M0P_SYSCTRL_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim0_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim0_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim0_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim0_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim0_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM0_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim0_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim0_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim0_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim0_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim0_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim0_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM0_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim0_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim0_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim0_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim0_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim0_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim0_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim0_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim0_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim0_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim0_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim0_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim0_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM0_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim1_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim1_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim1_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim1_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim1_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM1_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim1_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim1_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim1_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim1_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim1_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim1_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM1_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim1_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim1_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim1_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim1_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim1_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim1_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim1_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim1_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim1_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim1_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim1_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim1_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM1_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim2_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim2_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim2_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim2_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim2_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM2_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim2_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim2_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim2_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim2_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim2_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim2_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM2_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim2_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim2_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim2_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim2_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim2_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim2_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim2_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim2_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim2_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim2_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim2_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim2_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM2_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim3_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim3_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim3_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim3_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim3_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM3_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim3_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim3_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim3_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim3_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim3_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim3_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM3_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim3_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim3_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim3_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim3_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim3_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim3_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim3_mode23_crch0_field_t CRCH0_f; + }; + union + { + __IO uint32_t CRCH1; + stc_tim3_mode23_crch1_field_t CRCH1_f; + }; + union + { + __IO uint32_t CRCH2; + stc_tim3_mode23_crch2_field_t CRCH2_f; + }; + union + { + __IO uint32_t DTR; + stc_tim3_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim3_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim3_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim3_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim3_mode23_ccr0b_field_t CCR0B_f; + }; + union + { + __IO uint32_t CCR1A; + stc_tim3_mode23_ccr1a_field_t CCR1A_f; + }; + union + { + __IO uint32_t CCR1B; + stc_tim3_mode23_ccr1b_field_t CCR1B_f; + }; + union + { + __IO uint32_t CCR2A; + stc_tim3_mode23_ccr2a_field_t CCR2A_f; + }; + union + { + __IO uint32_t CCR2B; + stc_tim3_mode23_ccr2b_field_t CCR2B_f; + }; +}M0P_TIM3_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_trng_cr_field_t CR_f; + }; + union + { + __IO uint32_t MODE; + stc_trng_mode_field_t MODE_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t DATA0; + stc_trng_data0_field_t DATA0_f; + }; + union + { + __IO uint32_t DATA1; + stc_trng_data1_field_t DATA1_f; + }; +}M0P_TRNG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SBUF; + stc_uart_sbuf_field_t SBUF_f; + }; + union + { + __IO uint32_t SCON; + stc_uart_scon_field_t SCON_f; + }; + union + { + __IO uint32_t SADDR; + stc_uart_saddr_field_t SADDR_f; + }; + union + { + __IO uint32_t SADEN; + stc_uart_saden_field_t SADEN_f; + }; + union + { + __IO uint32_t ISR; + stc_uart_isr_field_t ISR_f; + }; + union + { + __IO uint32_t ICR; + stc_uart_icr_field_t ICR_f; + }; + union + { + __IO uint32_t SCNT; + stc_uart_scnt_field_t SCNT_f; + }; +}M0P_UART_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[16]; + union + { + __IO uint32_t CR; + stc_vc_cr_field_t CR_f; + }; + union + { + __IO uint32_t VC0_CR; + stc_vc_vc0_cr_field_t VC0_CR_f; + }; + union + { + __IO uint32_t VC1_CR; + stc_vc_vc1_cr_field_t VC1_CR_f; + }; + union + { + __IO uint32_t VC0_OUT_CFG; + stc_vc_vc0_out_cfg_field_t VC0_OUT_CFG_f; + }; + union + { + __IO uint32_t VC1_OUT_CFG; + stc_vc_vc1_out_cfg_field_t VC1_OUT_CFG_f; + }; + union + { + __IO uint32_t IFR; + stc_vc_ifr_field_t IFR_f; + }; + uint8_t RESERVED6[296]; + union + { + __IO uint32_t VC2_CR; + stc_vc_vc2_cr_field_t VC2_CR_f; + }; + union + { + __IO uint32_t VC2_OUT_CFG; + stc_vc_vc2_out_cfg_field_t VC2_OUT_CFG_f; + }; +}M0P_VC_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[128]; + union + { + __IO uint32_t RST; + stc_wdt_rst_field_t RST_f; + }; + union + { + __IO uint32_t CON; + stc_wdt_con_field_t CON_f; + }; +}M0P_WDT_TypeDef; + + + +#define M0P_PERIPH_BASE (0x40000000UL) +#define M0P_ADC_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_ADTIM4_BASE (M0P_PERIPH_BASE + 0x00003000UL) +#define M0P_ADTIM5_BASE (M0P_PERIPH_BASE + 0x00003400UL) +#define M0P_ADTIM6_BASE (M0P_PERIPH_BASE + 0x00003800UL) +#define M0P_AES_BASE (M0P_PERIPH_BASE + 0x00021400UL) +#define M0P_BGR_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_CLK_TRIM_BASE (M0P_PERIPH_BASE + 0x00001800UL) +#define M0P_CRC_BASE (M0P_PERIPH_BASE + 0x00020900UL) +#define M0P_DAC_BASE (M0P_PERIPH_BASE + 0x00002500UL) +#define M0P_DEBUG_ACTIVE_BASE (M0P_PERIPH_BASE + 0x00002038UL) +#define M0P_DMAC_BASE (M0P_PERIPH_BASE + 0x00021000UL) +#define M0P_FLASH_BASE (M0P_PERIPH_BASE + 0x00020000UL) +#define M0P_GPIO_BASE (M0P_PERIPH_BASE + 0x00020C00UL) +#define M0P_I2C0_BASE (M0P_PERIPH_BASE + 0x00000400UL) +#define M0P_I2C1_BASE (M0P_PERIPH_BASE + 0x00004400UL) +#define M0P_LCD_BASE (M0P_PERIPH_BASE + 0x00005C00UL) +#define M0P_LPTIMER0_BASE (M0P_PERIPH_BASE + 0x00000F00UL) +#define M0P_LPTIMER1_BASE (M0P_PERIPH_BASE + 0x00000F40UL) +#define M0P_LPUART0_BASE (M0P_PERIPH_BASE + 0x00000200UL) +#define M0P_LPUART1_BASE (M0P_PERIPH_BASE + 0x00004000UL) +#define M0P_LVD_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_OPA_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_PCA_BASE (M0P_PERIPH_BASE + 0x00001000UL) +#define M0P_PCNT_BASE (M0P_PERIPH_BASE + 0x00005400UL) +#define M0P_RAM_BASE (M0P_PERIPH_BASE + 0x00020400UL) +#define M0P_RESET_BASE (M0P_PERIPH_BASE + 0x0000201CUL) +#define M0P_RTC_BASE (M0P_PERIPH_BASE + 0x00001400UL) +#define M0P_SPI0_BASE (M0P_PERIPH_BASE + 0x00000800UL) +#define M0P_SPI1_BASE (M0P_PERIPH_BASE + 0x00004800UL) +#define M0P_SYSCTRL_BASE (M0P_PERIPH_BASE + 0x00002000UL) +#define M0P_TIM0_MODE0_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM0_MODE1_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM0_MODE23_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM1_MODE0_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM1_MODE1_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM1_MODE23_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM2_MODE0_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM2_MODE1_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM2_MODE23_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM3_MODE0_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TIM3_MODE1_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TIM3_MODE23_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TRNG_BASE (M0P_PERIPH_BASE + 0x00004C00UL) +#define M0P_UART0_BASE (M0P_PERIPH_BASE + 0x00000000UL) +#define M0P_UART1_BASE (M0P_PERIPH_BASE + 0x00000100UL) +#define M0P_UART2_BASE (M0P_PERIPH_BASE + 0x00006000UL) +#define M0P_UART3_BASE (M0P_PERIPH_BASE + 0x00006400UL) +#define M0P_VC_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_WDT_BASE (M0P_PERIPH_BASE + 0x00000F00UL) + + +#define M0P_ADC ((M0P_ADC_TypeDef *)0x40002400UL) +#define M0P_ADTIM4 ((M0P_ADTIM_TypeDef *)0x40003000UL) +#define M0P_ADTIM5 ((M0P_ADTIM_TypeDef *)0x40003400UL) +#define M0P_ADTIM6 ((M0P_ADTIM_TypeDef *)0x40003800UL) +#define M0P_AES ((M0P_AES_TypeDef *)0x40021400UL) +#define M0P_BGR ((M0P_BGR_TypeDef *)0x40002400UL) +#define M0P_CLK_TRIM ((M0P_CLK_TRIM_TypeDef *)0x40001800UL) +#define M0P_CRC ((M0P_CRC_TypeDef *)0x40020900UL) +#define M0P_DAC ((M0P_DAC_TypeDef *)0x40002500UL) +#define M0P_DEBUG_ACTIVE ((M0P_DEBUG_ACTIVE_TypeDef *)0x40002038UL) +#define M0P_DMAC ((M0P_DMAC_TypeDef *)0x40021000UL) +#define M0P_FLASH ((M0P_FLASH_TypeDef *)0x40020000UL) +#define M0P_GPIO ((M0P_GPIO_TypeDef *)0x40020C00UL) +#define M0P_I2C0 ((M0P_I2C_TypeDef *)0x40000400UL) +#define M0P_I2C1 ((M0P_I2C_TypeDef *)0x40004400UL) +#define M0P_LCD ((M0P_LCD_TypeDef *)0x40005C00UL) +#define M0P_LPTIMER0 ((M0P_LPTIMER_TypeDef *)0x40000F00UL) +#define M0P_LPTIMER1 ((M0P_LPTIMER_TypeDef *)0x40000F40UL) +#define M0P_LPUART0 ((M0P_LPUART_TypeDef *)0x40000200UL) +#define M0P_LPUART1 ((M0P_LPUART_TypeDef *)0x40004000UL) +#define M0P_LVD ((M0P_LVD_TypeDef *)0x40002400UL) +#define M0P_OPA ((M0P_OPA_TypeDef *)0x40002400UL) +#define M0P_PCA ((M0P_PCA_TypeDef *)0x40001000UL) +#define M0P_PCNT ((M0P_PCNT_TypeDef *)0x40005400UL) +#define M0P_RAM ((M0P_RAM_TypeDef *)0x40020400UL) +#define M0P_RESET ((M0P_RESET_TypeDef *)0x4000201CUL) +#define M0P_RTC ((M0P_RTC_TypeDef *)0x40001400UL) +#define M0P_SPI0 ((M0P_SPI_TypeDef *)0x40000800UL) +#define M0P_SPI1 ((M0P_SPI_TypeDef *)0x40004800UL) +#define M0P_SYSCTRL ((M0P_SYSCTRL_TypeDef *)0x40002000UL) +#define M0P_TIM0_MODE0 ((M0P_TIM0_MODE0_TypeDef *)0x40000C00UL) +#define M0P_TIM0_MODE1 ((M0P_TIM0_MODE1_TypeDef *)0x40000C00UL) +#define M0P_TIM0_MODE23 ((M0P_TIM0_MODE23_TypeDef *)0x40000C00UL) +#define M0P_TIM1_MODE0 ((M0P_TIM1_MODE0_TypeDef *)0x40000D00UL) +#define M0P_TIM1_MODE1 ((M0P_TIM1_MODE1_TypeDef *)0x40000D00UL) +#define M0P_TIM1_MODE23 ((M0P_TIM1_MODE23_TypeDef *)0x40000D00UL) +#define M0P_TIM2_MODE0 ((M0P_TIM2_MODE0_TypeDef *)0x40000E00UL) +#define M0P_TIM2_MODE1 ((M0P_TIM2_MODE1_TypeDef *)0x40000E00UL) +#define M0P_TIM2_MODE23 ((M0P_TIM2_MODE23_TypeDef *)0x40000E00UL) +#define M0P_TIM3_MODE0 ((M0P_TIM3_MODE0_TypeDef *)0x40005800UL) +#define M0P_TIM3_MODE1 ((M0P_TIM3_MODE1_TypeDef *)0x40005800UL) +#define M0P_TIM3_MODE23 ((M0P_TIM3_MODE23_TypeDef *)0x40005800UL) +#define M0P_TRNG ((M0P_TRNG_TypeDef *)0x40004C00UL) +#define M0P_UART0 ((M0P_UART_TypeDef *)0x40000000UL) +#define M0P_UART1 ((M0P_UART_TypeDef *)0x40000100UL) +#define M0P_UART2 ((M0P_UART_TypeDef *)0x40006000UL) +#define M0P_UART3 ((M0P_UART_TypeDef *)0x40006400UL) +#define M0P_VC ((M0P_VC_TypeDef *)0x40002400UL) +#define M0P_WDT ((M0P_WDT_TypeDef *)0x40000F00UL) + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32L17X_H__ */ + diff --git a/mcu/common/interrupts_hc32l17x.c b/mcu/common/interrupts_hc32l17x.c new file mode 100644 index 0000000..a37b82b --- /dev/null +++ b/mcu/common/interrupts_hc32l17x.c @@ -0,0 +1,610 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file interrupts_hc32l136.c + ** + ** Interrupt management + ** @link Driver Group Some description @endlink + ** + ** - 2018-04-15 1.0 Lux First version. + ** + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l17x.h" + +/******************************************************************************* + * IRQ WEAK DEFINE + ******************************************************************************/ +__WEAK void SysTick_IRQHandler(void); + + +__WEAK void PortA_IRQHandler(void); +__WEAK void PortB_IRQHandler(void); +__WEAK void PortC_IRQHandler(void); +__WEAK void PortD_IRQHandler(void); +__WEAK void PortE_IRQHandler(void); +__WEAK void PortF_IRQHandler(void); +__WEAK void Dmac_IRQHandler(void); +__WEAK void Tim3_IRQHandler(void); +__WEAK void Uart0_IRQHandler(void); +__WEAK void Uart1_IRQHandler(void); +__WEAK void Uart2_IRQHandler(void); +__WEAK void Uart3_IRQHandler(void); +__WEAK void LpUart0_IRQHandler(void); +__WEAK void LpUart1_IRQHandler(void); +__WEAK void Spi0_IRQHandler(void); +__WEAK void Spi1_IRQHandler(void); +__WEAK void I2c0_IRQHandler(void); +__WEAK void I2c1_IRQHandler(void); +__WEAK void Tim0_IRQHandler(void); +__WEAK void Tim1_IRQHandler(void); +__WEAK void Tim2_IRQHandler(void); +__WEAK void LpTim0_IRQHandler(void); +__WEAK void LpTim1_IRQHandler(void); +__WEAK void Tim4_IRQHandler(void); +__WEAK void Tim5_IRQHandler(void); +__WEAK void Tim6_IRQHandler(void); +__WEAK void Pca_IRQHandler(void); +__WEAK void Wdt_IRQHandler(void); +__WEAK void Rtc_IRQHandler(void); +__WEAK void Adc_IRQHandler(void); +__WEAK void Dac_IRQHandler(void); +__WEAK void Pcnt_IRQHandler(void); +__WEAK void Vc0_IRQHandler(void); +__WEAK void Vc1_IRQHandler(void); +__WEAK void Vc2_IRQHandler(void); +__WEAK void Lvd_IRQHandler(void); +__WEAK void Lcd_IRQHandler(void); +__WEAK void Flash_IRQHandler(void); +__WEAK void Ram_IRQHandler(void); +__WEAK void ClkTrim_IRQHandler(void); + +/** + ******************************************************************************* + ** \brief NVIC 涓柇浣胯兘 + ** + ** \param [in] enIrq 涓柇鍙锋灇涓剧被鍨 + ** \param [in] enLevel 涓柇浼樺厛绾ф灇涓剧被鍨 + ** \param [in] bEn 涓柇寮鍏 + ** \retval Ok 璁剧疆鎴愬姛 + ** 鍏朵粬鍊 璁剧疆澶辫触 + ******************************************************************************/ +void EnableNvic(IRQn_Type enIrq, en_irq_level_t enLevel, boolean_t bEn) +{ + NVIC_ClearPendingIRQ(enIrq); + NVIC_SetPriority(enIrq, enLevel); + if (TRUE == bEn) + { + NVIC_EnableIRQ(enIrq); + } + else + { + NVIC_DisableIRQ(enIrq); + } +} + +/** + ******************************************************************************* + ** \brief NVIC hardware fault 涓柇瀹炵幇 + ** + ** + ** \retval + ******************************************************************************/ +void HardFault_Handler(void) +{ + volatile int a = 0; + + while( 0 == a) + { + ; + } + +} + + +/** + ******************************************************************************* + ** \brief NVIC SysTick 涓柇瀹炵幇 + ** + ** \retval + ******************************************************************************/ +void SysTick_Handler(void) +{ + SysTick_IRQHandler(); +} + +/** + ******************************************************************************* + ** \brief GPIO PortA 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void PORTA_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTA) + PortA_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief GPIO PortB 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void PORTB_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTB) + PortB_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief GPIO PortC/E 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void PORTC_E_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTC) + PortC_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTE) + PortE_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief GPIO PortD/F 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void PORTD_F_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTD) + PortD_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTF) + PortF_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief DMAC 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void DMAC_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_DMAC) + Dmac_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM3 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void TIM3_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM3) + Tim3_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief UART0/2 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void UART0_2_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_UART0) + Uart0_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_UART2) + Uart2_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief UART1/3 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void UART1_3_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_UART1) + Uart1_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_UART3) + Uart3_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief LPUART0 浣庡姛鑰椾覆鍙0 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void LPUART0_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_LPUART0) + LpUart0_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief LPUART1 浣庡姛鑰椾覆鍙1 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void LPUART1_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_LPUART1) + LpUart1_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief SPI0 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void SPI0_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_SPI0) + Spi0_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief SPI1 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void SPI1_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_SPI1) + Spi1_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief I2C0 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void I2C0_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_I2C0) + I2c0_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief I2C1 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void I2C1_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_I2C1) + I2c1_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM0 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void TIM0_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM0) + Tim0_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM1 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void TIM1_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM1) + Tim1_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM2 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void TIM2_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM2) + Tim2_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief LPTIM0/1 浣庡姛鑰楁椂閽 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void LPTIM0_1_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_LPTIM0) + LpTim0_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_LPTIM1) + LpTim1_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM4 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void TIM4_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM4) + Tim4_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM5 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void TIM5_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM5) + Tim5_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM6 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void TIM6_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM6) + Tim6_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief PCA 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void PCA_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PCA) + Pca_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief WDT 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void WDT_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_WDT) + Wdt_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief RTC 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void RTC_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_RTC) + Rtc_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief ADC/DAC 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void ADC_DAC_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_ADC) + Adc_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_DAC) + Dac_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief PCNT 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void PCNT_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PCNT) + Pcnt_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief VC0 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void VC0_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_VC0) + Vc0_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief VC1/2 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void VC1_2_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_VC1) + Vc1_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_VC2) + Vc2_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief LVD 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void LVD_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_LVD) + Lvd_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief LCD 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void LCD_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_LCD) + Lcd_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief FLASH/RAM 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void FLASH_RAM_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_FLASH) + Flash_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_RAM) + Ram_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief CLKTRIM 涓柇澶勭悊鍑芥暟 + ** + ** \retval + ******************************************************************************/ +void CLKTRIM_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_CLKTRIM) + ClkTrim_IRQHandler(); +#endif +} + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/mcu/common/interrupts_hc32l17x.h b/mcu/common/interrupts_hc32l17x.h new file mode 100644 index 0000000..568efbb --- /dev/null +++ b/mcu/common/interrupts_hc32l17x.h @@ -0,0 +1,150 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file interrupts_hc32l17x.h + ** + ** Interrupt common define. + ** @link IRQGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ +#ifndef __INTERRUPTS_HC32L17X_H__ +#define __INTERRUPTS_HC32L17X_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define DDL_IRQ_LEVEL_DEFAULT 3u + +//<<姝ら夐」浼氭墦寮interrupt_hc32xxx.c涓殑涓柇鍥炶皟鍑芥暟锛岀敤鎴峰鏋滈渶瑕佸疄鐜颁腑鏂湇鍔″嚱鏁帮紝 +//<<鍙湪婧愮爜鏂囦欢涓畾涔夎鏂囦欢涓敤"__WEAK"澹版槑鐨勫悓鍚嶄腑鏂湇鍔″嚱鏁板嵆鍙 +#define INT_CALLBACK_ON 1u //<<(榛樿鍊) +//<<姝ら夐」浼氬叧闂璱nterrupt_hc32xxx.c涓殑涓柇鍥炶皟鍑芥暟锛屾鏃剁敤鎴峰彲鍦ㄨ鏂囦欢涓嚜琛屽畾涔変腑鏂湇鍔″嚱鏁扮殑瀹炵幇銆 +#define INT_CALLBACK_OFF 0u +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#define INT_CALLBACK_PORTA INT_CALLBACK_ON +#define INT_CALLBACK_PORTB INT_CALLBACK_ON +#define INT_CALLBACK_PORTC INT_CALLBACK_ON +#define INT_CALLBACK_PORTD INT_CALLBACK_OFF +#define INT_CALLBACK_PORTE INT_CALLBACK_OFF +#define INT_CALLBACK_PORTF INT_CALLBACK_ON +#define INT_CALLBACK_DMAC INT_CALLBACK_ON +#define INT_CALLBACK_TIM3 INT_CALLBACK_ON +#define INT_CALLBACK_UART0 INT_CALLBACK_ON +#define INT_CALLBACK_UART1 INT_CALLBACK_ON +#define INT_CALLBACK_UART2 INT_CALLBACK_ON +#define INT_CALLBACK_UART3 INT_CALLBACK_ON +#define INT_CALLBACK_LPUART0 INT_CALLBACK_ON +#define INT_CALLBACK_LPUART1 INT_CALLBACK_ON +#define INT_CALLBACK_SPI0 INT_CALLBACK_ON +#define INT_CALLBACK_SPI1 INT_CALLBACK_ON +#define INT_CALLBACK_I2C0 INT_CALLBACK_ON +#define INT_CALLBACK_I2C1 INT_CALLBACK_ON +#define INT_CALLBACK_TIM0 INT_CALLBACK_ON +#define INT_CALLBACK_TIM1 INT_CALLBACK_ON +#define INT_CALLBACK_TIM2 INT_CALLBACK_ON +#define INT_CALLBACK_LPTIM0 INT_CALLBACK_ON +#define INT_CALLBACK_LPTIM1 INT_CALLBACK_ON +#define INT_CALLBACK_TIM4 INT_CALLBACK_ON +#define INT_CALLBACK_TIM5 INT_CALLBACK_ON +#define INT_CALLBACK_TIM6 INT_CALLBACK_ON +#define INT_CALLBACK_PCA INT_CALLBACK_ON +#define INT_CALLBACK_WDT INT_CALLBACK_ON +#define INT_CALLBACK_RTC INT_CALLBACK_ON +#define INT_CALLBACK_ADC INT_CALLBACK_ON +#define INT_CALLBACK_DAC INT_CALLBACK_ON +#define INT_CALLBACK_PCNT INT_CALLBACK_ON +#define INT_CALLBACK_VC0 INT_CALLBACK_ON +#define INT_CALLBACK_VC1 INT_CALLBACK_ON +#define INT_CALLBACK_VC2 INT_CALLBACK_ON +#define INT_CALLBACK_LVD INT_CALLBACK_ON +#define INT_CALLBACK_LCD INT_CALLBACK_ON +#define INT_CALLBACK_FLASH INT_CALLBACK_ON +#define INT_CALLBACK_RAM INT_CALLBACK_ON +#define INT_CALLBACK_CLKTRIM INT_CALLBACK_ON + + +/** + ******************************************************************************* + ** \brief 涓柇浼樺厛绾ф暟鎹被鍨嬪畾涔 + ** \note + ******************************************************************************/ +typedef enum en_irq_level +{ + IrqLevel0 = 0u, ///< 浼樺厛绾0 + IrqLevel1 = 1u, ///< 浼樺厛绾1 + IrqLevel2 = 2u, ///< 浼樺厛绾2 + IrqLevel3 = 3u, ///< 浼樺厛绾3 +} en_irq_level_t; + + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +///< 绯荤粺涓柇浣胯兘寮鍏 +extern void EnableNvic(IRQn_Type enIrq, en_irq_level_t enLevel, boolean_t bEn); + + +#ifdef __cplusplus +} +#endif + + +#endif /* __INTERRUPTS_HC32L17X_H__ */ + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/common/system_hc32l17x.c b/mcu/common/system_hc32l17x.c new file mode 100644 index 0000000..c0cb41d --- /dev/null +++ b/mcu/common/system_hc32l17x.c @@ -0,0 +1,212 @@ +/******************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l136.c + ** + ** System clock initialization. + ** @link SampleGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "base_types.h" +#include "hc32l17x.h" +#include "system_hc32l17x.h" +#include "sysctrl.h" + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t SystemCoreClock = 4000000; + + +//add clock source. +void SystemCoreClockUpdate (void) // Update SystemCoreClock variable +{ + SystemCoreClock = Sysctrl_GetHClkFreq(); +} + +/** + ****************************************************************************** + ** \brief 瀵筂CU鏈紩鍑篒O绔彛杩涜榛樿閰嶇疆. + ** + ** \param none + ** \return none + ******************************************************************************/ +static void _InitHidePin(void) +{ + uint32_t tmpReg = M0P_SYSCTRL->PERI_CLKEN0; + + M0P_SYSCTRL->PERI_CLKEN0_f.GPIO = 1; + +#if defined(HC32L17xPxxx) //100PIN MCU + M0P_GPIO->PFADS &= 0xFF4F; ///< PF04/PF05/PF07閰嶇疆涓烘暟瀛楃鍙 + + M0P_GPIO->PFDIR |= 0x00B0; ///< PF04/PF05/PF07閰嶇疆涓虹鍙ｈ緭鍏 + + M0P_GPIO->PFPU |= 0x00B0; ///< PF04/PF05/PF07閰嶇疆涓轰笂鎷 + +#elif defined(HC32L17xMxxx) //80PIN MCU + M0P_GPIO->PDADS &= 0x0F1F; ///< PD05~07/PD12~15閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PEADS &= 0x783C; ///< PE00/PE01/PE06~10/PE15閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PFADS &= 0xF9F3; ///< PF02/PF03/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + + M0P_GPIO->PDDIR |= 0xF0E0; ///< PD05~07/PD12~15閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PEDIR |= 0x87C3; ///< PE00/PE01/PE06~10/PE15閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PFDIR |= 0x060C; ///< PF02/PF03/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + + + M0P_GPIO->PDPU |= 0xF0E0; ///< PD05~07/PD12~15閰嶇疆涓轰笂鎷 + M0P_GPIO->PEPU |= 0x87C3; ///< PE00/PE01/PE06~10/PE15閰嶇疆涓轰笂鎷 + M0P_GPIO->PFPU |= 0x060C; ///< PF02/PF03/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + +#elif defined(HC32L17xKxxx) //64PIN MCU + M0P_GPIO->PDADS &= 0x0004; ///< PD00/PD01/PD03~15閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PEADS &= 0x0000; ///< PE00~15閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PFADS &= 0xF9F3; ///< PF02/PF03/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + + M0P_GPIO->PDDIR |= 0xFFFB; ///< PD00/PD01/PD03~15閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PEDIR |= 0xFFFF; ///< PE00~15閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PFDIR |= 0x060C; ///< PF02/PF03/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + + M0P_GPIO->PDPU |= 0xFFFB; ///< PD00/PD01/PD03~15閰嶇疆涓轰笂鎷 + M0P_GPIO->PEPU |= 0xFFFF; ///< PE00~15閰嶇疆涓轰笂鎷 + M0P_GPIO->PFPU |= 0x060C; ///< PF02/PF03/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + +#elif defined(HC32L17xJxxx) //48PIN MCU + M0P_GPIO->PCADS &= 0xE000; ///< PC00~12閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PDADS &= 0x0000; ///< PD00~15閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PEADS &= 0x0000; ///< PE00~15閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PFADS &= 0xF9C3; ///< PF02~05/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + + M0P_GPIO->PCDIR |= 0x1FFF; ///< PC00~12閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PDDIR |= 0xFFFF; ///< PD00~15閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PEDIR |= 0xFFFF; ///< PE00~15閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PFDIR |= 0x063C; ///< PF02~05/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + + + M0P_GPIO->PCPU |= 0x1FFF; ///< PC00~12閰嶇疆涓轰笂鎷 + M0P_GPIO->PDPU |= 0xFFFF; ///< PD00~15閰嶇疆涓轰笂鎷 + M0P_GPIO->PEPU |= 0xFFFF; ///< PE00~15閰嶇疆涓轰笂鎷 + M0P_GPIO->PFPU |= 0x063C; ///< PF02~05/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + +#elif defined(HC32L17xFxxx) //32PIN MCU + M0P_GPIO->PAADS &= 0xFFF4; ///< PA00/PA01/PA03閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PBADS &= 0x08FB; ///< PB02/PB08~10/PB12~15閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PCADS &= 0xC000; ///< PC00~13閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PDADS &= 0x0000; ///< PD00~15閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PEADS &= 0x0000; ///< PE00~15閰嶇疆涓烘暟瀛楃鍙 + M0P_GPIO->PFADS &= 0xF903; ///< PF02~07/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + + M0P_GPIO->PADIR |= 0x000B; ///< PA00/PA01/PA03閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PBDIR |= 0xF704; ///< PB02/PB08~10/PB12~15閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PCDIR |= 0x3FFF; ///< PC00~13閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PDDIR |= 0xFFFF; ///< PD00~15閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PEDIR |= 0xFFFF; ///< PE00~15閰嶇疆涓虹鍙ｈ緭鍏 + M0P_GPIO->PFDIR |= 0x06FC; ///< PF02~07/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + + M0P_GPIO->PAPU |= 0x000B; ///< PA00/PA01/PA03閰嶇疆涓轰笂鎷 + M0P_GPIO->PBPU |= 0xF704; ///< PB02/PB08~10/PB12~15閰嶇疆涓轰笂鎷 + M0P_GPIO->PCPU |= 0x3FFF; ///< PC00~13閰嶇疆涓轰笂鎷 + M0P_GPIO->PDPU |= 0xFFFF; ///< PD00~15閰嶇疆涓轰笂鎷 + M0P_GPIO->PEPU |= 0xFFFF; ///< PE00~15閰嶇疆涓轰笂鎷 + M0P_GPIO->PFPU |= 0x06FC; ///< PF02~07/PF09/PF10閰嶇疆涓烘暟瀛楃鍙 + +#endif + + M0P_SYSCTRL->PERI_CLKEN0 = tmpReg; +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit(void) +{ + M0P_SYSCTRL->RCL_CR_f.TRIM = (*((volatile uint16_t*) (0x00100C22ul))); + M0P_SYSCTRL->RCH_CR_f.TRIM = (*((volatile uint16_t*) (0x00100C08ul))); + SystemCoreClockUpdate(); + _InitHidePin(); +} + + +#if defined (__CC_ARM) +extern int32_t $Super$$main(void); +/* re-define main function */ +int $Sub$$main(void) +{ + SystemInit(); + $Super$$main(); + return 0; +} +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +extern int32_t $Super$$main(void); +/* re-define main function */ +int $Sub$$main(void) +{ + SystemInit(); + $Super$$main(); + return 0; +} +#elif defined(__ICCARM__) +extern int32_t main(void); +/* __low_level_init will auto called by IAR cstartup */ +extern void __iar_data_init3(void); +int __low_level_init(void) +{ + // call IAR table copy function. + __iar_data_init3(); + SystemInit(); + main(); + return 0; +} +#endif + diff --git a/mcu/common/system_hc32l17x.h b/mcu/common/system_hc32l17x.h new file mode 100644 index 0000000..6ff8efb --- /dev/null +++ b/mcu/common/system_hc32l17x.h @@ -0,0 +1,116 @@ +/******************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l17x.h + ** + ** A detailed description is available at + ** @link SampleGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __SYSTEM_HC32L17X_H__ +#define __SYSTEM_HC32L17X_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ +#define HWWD_DISABLE (1) + + + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + +//#define HC32L17xPxxx //100PIN +//#define HC32L17xMxxx //80PIN +//#define HC32L17xKxxx //64PIN +//#define HC32L17xJxxx //48PIN +#define HC32L17xFxxx //32PIN + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit (void); // Initialize the system +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32L17X _H__ */ + + + + + + + diff --git a/source/ddl_device.h b/source/ddl_device.h new file mode 100644 index 0000000..582bd95 --- /dev/null +++ b/source/ddl_device.h @@ -0,0 +1,76 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file ddl_device.h + ** + ** Device define + ** @link SampleGroup Some description @endlink + ** + ** - 2018-04-15 + ** + *****************************************************************************/ + +#ifndef __DDL_DEVICE_H__ +#define __DDL_DEVICE_H__ + +/** + ******************************************************************************* + ** \brief Global device series definition + ** + ** \note + ******************************************************************************/ +#define DDL_MCU_SERIES DDL_DEVICE_SERIES_HC32L17X + + +/** + ******************************************************************************* + ** \brief Global package definition + ** + ** \note This definition is used for device package settings + ******************************************************************************/ +#define DDL_MCU_PACKAGE DDL_DEVICE_PACKAGE_HC_K + +#endif /* __DDL_DEVICE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/source/inc/Algorithm.h b/source/inc/Algorithm.h new file mode 100644 index 0000000..dd97796 --- /dev/null +++ b/source/inc/Algorithm.h @@ -0,0 +1,55 @@ +#ifndef __ALGORITHM_H +#define __ALGORITHM_H + +#include +#include +#include +#include +#include +#include + +#define CRC16_BASE 0xA001 + + +// 峰值谷值检查结果结构体 +typedef struct { + bool peaks_positive; // 所有峰值是否大于0 + bool valleys_negative; // 所有谷值是否小于0 + int peak_count; // 检测到的峰值数量 + int valley_count; // 检测到的谷值数量 +} PeakValleyCheck; + +// 趋势分析结果结构体 +typedef struct { + double slope; // 线性斜率 + int sign_changes; // 符号变化次数 + char trend_type; // 趋势类型 + char steepness; // 陡峭度 +} TrendResult; + +PeakValleyCheck check_peaks_valleys(int data[], int length); +TrendResult analyze_trend(int data[], int length); +float calculateAverage(int *arr, int size); +double slope(int32_t *x_data, int32_t *y_data, int n) ; +long long power(int base, unsigned int exponent); +int IntFilter_16t(int16_t *Data, uint8_t Cnt, uint8_t FilterCnt); +int IntFilter_32t(int32_t *Data, uint8_t Cnt, uint8_t FilterCnt); +uint32_t IntFilter_u32t(uint32_t *Data, uint8_t Cnt, uint8_t FilterCnt); +float IntFilter_Float(float *Data, uint8_t Cnt, uint8_t FilterCnt); +uint32_t AverageFilter_u32t(uint32_t *Data, uint8_t Cnt); +int AverageFilter_32t(int32_t *Data, uint8_t Cnt); +void Fitting_Polynomial(double *AD, double *Actual, uint8_t Cnt); +float get_K(uint8_t count , int32_t *dataCol_X, int32_t *dataRow_Y); +int8_t TrendAnalyse(int32_t *Data, uint8_t Cnt, int32_t VPT); +void Waveform_Up(int32_t *Data, uint8_t dCnt, uint8_t pCnt, int32_t *vlue); +void Waveform_Down(int32_t *Data, uint8_t dCnt, uint8_t pCnt, int32_t *vlue); +bool count_most_greater(int32_t *arr, uint8_t size, int32_t target); +bool count_greater(int32_t *arr, uint8_t size, int32_t target); +bool count_smaller(int32_t *arr, uint8_t size, int32_t target); +uint16_t CRC_Modbus(uint16_t wBase, uint8_t *para, uint16_t length); +uint8_t CRC_Sum(uint8_t *_pbuff, uint16_t _cmdLen); +bool isAllZero(uint8_t *arr, int size); +#endif + + + diff --git a/source/inc/SGCP.h b/source/inc/SGCP.h new file mode 100644 index 0000000..448f0dc --- /dev/null +++ b/source/inc/SGCP.h @@ -0,0 +1,290 @@ +/* 传感器通用通讯协议V1.0*/ + +#ifndef __SGCP_H +#define __SGCP_H +#include "bsp.h" + +#define WORK_MODE 1 //工作模式选择，0、本机为查询模式，1、本机为上报模式(低功耗) +#define SGCP_SELECT 1 //协议选择，0、本机为单个主设备接多个子设备，1、本机为单个主设备不接子设备，2、本机为单个子设备 +#define LocalDataLen sizeof(SGCP.DevData.LaserTracing)//本机设备数据长度 +#define LocalType LASER_TRACING //本机设备类型 +#define CommWay LORA //本机通讯方式 +#define DeviceSign MASTER //本机设备标志 +#define AddNumber (0x000017 + DeviceSign)//本机地址编号，数字部分对应唯一地址编号 +//09 00 01 00 00 00 + +typedef struct {//网关与主设备固定帧 + uint8_t Header; + uint8_t GWAddr[6]; + uint8_t MDAddr[6]; + uint8_t Cmd; + uint16_t PayloadLen; +}__attribute__ ((packed))GatewayFrameHeader_t,*GatewayFrameHeader; + +typedef struct {//主设备与子设备固定帧 + uint8_t Header; + uint8_t Addr; + uint8_t Cmd; + uint8_t PayloadLen; +}__attribute__ ((packed))SubsetFrameHeader_t,*SubsetFrameHeader; + +typedef struct {//内部指令固定帧 + uint8_t Header; + uint8_t MAC[6]; + uint8_t Cmd; + uint8_t PayloadLen; +}__attribute__ ((packed))InsideFrameHeader_t,*InsideFrameHeader; + +typedef struct {//主设备固定包头 + uint8_t BatLevel; //电池电量 + int8_t RSSI; //信号强度 + int8_t Nsr; //信噪比 +}__attribute__ ((packed))MasterDev_T,*MasterDevDp; + +typedef struct {//0x0006 三维连续变形 + int16_t PitchAngle; //俯仰角 （范围±900）单位0.1° + int16_t RollAngle; //横滚角 （范围±900）单位0.1° + int16_t YawAngle; //偏航角 （范围0~3600）单位0.1° +}__attribute__ ((packed))ContDefor3D_T,*ContDefor3DDp; + +typedef struct {//0x0007 通讯单元 + MasterDev_T MasterDev; +}__attribute__ ((packed))CommUnit_T,*CommUnitDp; + +typedef struct {//0x0008 三维应力 + int16_t PitchAngle; //俯仰角（范围±900）单位0.1° + int16_t RollAngle; //横滚角（范围±900）单位0.1° + int16_t YawAngle; //偏航角（范围0~3600）单位0.1° + int32_t Strain1; //X轴应力值（范围±10MPa,单位Pa） + int32_t Strain2; //Y轴应力值（范围±10MPa,单位Pa） + int32_t Strain3; //Z轴应力值（范围±10MPa,单位Pa） +}__attribute__ ((packed))Force3D_T,*Force3DDp; + +typedef struct {//0x0009 激光示踪 + MasterDev_T MasterDev; + int16_t PitchAngle; //俯仰角 （范围±900）单位0.1° + int16_t RollAngle; //横滚角 （范围±900）单位0.1° + int16_t YawAngle; //偏航角 （范围0~3600）单位0.1° +}__attribute__ ((packed))LaserTracing_T,*LaserTracingDp; + +typedef struct {//0x000E 裂缝仪 + int16_t XwiseDist; //横向位移量（范围0~150mm） + int16_t LgthwysDist; //纵向位移距离（范围0~150mm） + int16_t RotationDist; //旋转位移距离（范围0~150mm） +}__attribute__ ((packed))Crack_T,*CrackDp; + +typedef struct { + ContDefor3D_T ContDefor3D; + CommUnit_T CommUnit; + Force3D_T Force3D; + Crack_T Crack; + LaserTracing_T LaserTracing; +}__attribute__ ((packed))DeviceData_T,*DeviceDp; //设备数据 + +/*接收子设备数据状态机*/ +typedef enum { + SUB_STATUS_IDLE, + SUB_STATUS_BROADCAST_CALI, + SUB_STATUS_READMASTER_DATA, + SUB_STATUS_READSUBSET_DATA, + SUB_STATUS_WAIT_READSUBSET, + SUB_STATUS_MASTER_QUERY, + SUB_STATUS_SUBSET_QUERY, + SUB_STATUS_WAIT_SUBSET_QUERY, + SUB_STATUS_BROADCAST_SET_COLTIME, + SUB_STATUS_BROADCAST_SYNC_TIME, +}SubStatus_m; + +/*接收网关数据状态机*/ +typedef enum { + GW_STATUS_IDLE, + GW_STATUS_WAIT_SUBIDLE, + GW_STATUS_LOGIN, + GW_STATUS_WAIT_LOGIN, + GW_STATUS_CALI, + GW_STATUS_READ_SENSOR, + GW_STATUS_SET_COL_TIME, + GW_STATUS_SYNC_TIME, + GW_STATUS_UPLOAD_SENSOR,//主动上报模式时会使用该状态 + GW_STATUS_WAIT_UPLOAD,//主动上报模式时会使用该状态 + GW_STATUS_LASER_STARES,//激光状态回应 +}GWStatus_m; +/*接收主设备数据状态机*/ +typedef enum { + MAS_STATUS_IDLE, + MAS_STATUS_CALI, + MAS_STATUS_READ_SENSOR, + MAS_STATUS_DEVICE_INQUIRE, + MAS_STATUS_SET_COL_TIME, + MAS_STATUS_SYNC_TIME, +}MasStatus_m; +/*内部指令数据状态机*/ +typedef enum { + IN_STATUS_IDLE, + IN_STATUS_UPDATE, + IN_STATUS_ALTER_485ADDR, +}InStatus_m; +/*网关到主设备命令集*/ +typedef enum { + GWTOMD_CMD_LOGIN = 0x00, //0x00，设备注册 + GWTOMD_CMD_CALI = 0x01, //0x01, 校准指令 + GWTOMD_CMD_READ_UPLOAD_SENSOR = 0x02, //0x02，读取数据指令or上传数据指令 + GWTOMD_CMD_SET_COL_TIME = 0x05, //0x05，设置采集时间间隔 + GWTOMD_CMD_SYNC_TIME = 0x06, //0x06，时间同步 + GWTOMD_CMD_SET_LASER = 0x08,//打开or关闭激光 +}GWTOMD_CMD_M; + +/*主设备到子设备命令集*/ +typedef enum { + MDTOSD_CMD_CALI = 0x01, //0x01, 校准指令 + MDTOSD_CMD_READ_DATA = 0x02, //0x02，读取数据指令 + MDTOSD_CMD_INQUIRE = 0x03, //0x03, 设备查询指令 + MDTOSD_CMD_SET_COL_TIME = 0x05, //0x05，设置采集时间间隔 + MDTOSD_CMD_SYNC_TIME = 0x06, //0x06，时间同步 +}MDTOSD_CMD_M; +/*内部指令命令集*/ +typedef enum { + INSIDE_CMD_UPDATE = 0x81, //0x81，升级程序下发请求，由主机发起，从机应答 + INSIDE_CMD_ALTER_485ADDR = 0x04, //0x04, 设置设备485地址 +}INSIDE_CMD_M; +/*设备类型*/ +typedef enum { + NUL, //0x0000 空设备 + FORCE_6D, //0x0001 六维应力 + OSMOTIC_PRESSURE, //0x0002 渗透压 + ELASTIC_WAVEGUIDE, //0x0003 弹性波导 + DIELECTRIC_MASS, //0x0004 介电质普 + _0x0005, //0x0005 保留 + CONT_DEFOR_3D, //0x0006 三维连续变形 + COMM_UNIT, //0x0007 通讯单元 + FORCE_3D, //0x0008 三维应力 + LASER_TRACING, //0x0009 激光示踪 + _0x000A, //0x000A 保留 + _0x000B, //0x000B 保留 + _0x000C, //0x000C 保留 + MULTI_PARAMETER_FUSION, //0x000D 多参数融合 + CRACK_DETECTION, //0x000E 裂缝仪 + _0x000F, //0x000F 保留 + ATTITUDE_MONITOR, //0x0010 姿态检测 + LASER_DISPLACE, //0x0011 激光位移 + REBAR_STRESS, //0x0012 钢筋应力 + ANCHOR_ROD_STRESS, //0x0013 锚杆轴力 + SURFACE_STRESS, //0x0014 表面应力 + PRESSURE, //0x0015 压力 + MICROWAVE_DISPLACE, //0x0016 微波测距 +}DEVICE_TYPE_M; +/*通讯方式*/ +typedef enum { + LORA = 0x01, //0x01 LORA通讯 + RS485 = 0x02, //0x02 RS485通讯 + RS232 = 0x03, //0x03 RS232通讯 + CAN = 0x04, //0x04 CAN通讯 + _4G = 0x05, //0x05 _4G通讯 + BLE = 0x06, //0x06 BLE通讯 + WIFI = 0x07, //0x07 WIFI通讯 + UART = 0x08, //0x08 UART通讯 +}COMM_WAY_M; +/*设备标志*/ +typedef enum { + MASTER = 0x000000, //0x000000 主设备 + SUBSET = 0x800000, //0x800000 子设备 +}DEVICE_SIGN_M; +typedef struct { + __IO GWTOMD_CMD_M rCmdGWToMD; //网关下发命令 + __IO GWTOMD_CMD_M sCmdMDToGW; //主设备返回命令 + __IO uint16_t rPayLen; + __IO bool HeaderFrame; + __IO uint8_t RxLen; + uint8_t RxBuff[256]; +}GWTOMD_Rx_T; + +typedef struct { + __IO MDTOSD_CMD_M rCmdSDToMD; //子设备返回命令 + __IO MDTOSD_CMD_M sCmdMDToSD; //主设备下发命令 + __IO uint8_t rPayLen; + __IO bool HeaderFrame; + __IO uint8_t RxLen; + uint8_t RxBuff[256]; +}MDTOSD_Rx_T; + +typedef struct { + uint32_t LpUart0Delay1mSCnt; + uint32_t LoraDelay1mSCnt; + uint32_t Uart1Delay1mSCnt; + uint32_t GW1mSDelayCnt; + uint32_t SD1mSDelayCnt; + uint32_t In1mSDelayCnt; + + GWTOMD_Rx_T GWRS485Rx; + uint8_t GatewayBuffLen; + uint8_t GatewayBuff[256]; + uint8_t GatewayRevTimeoutCnt; //网关串口接收超时计数 + + MDTOSD_Rx_T SDRS485Rx; + uint8_t SubsetBuffLen; + uint8_t SubsetBuff[256]; + uint8_t SubsetRevTimeoutCnt; //子设备串口接收超时计数 + + uint8_t InsidePayLen; + uint8_t InsideBuffLen; + uint8_t InsideBuff[256]; + uint8_t InsidePay[256]; + + SubStatus_m SubStatus; + SubStatus_m NextSubStatus; + GWStatus_m GWStatus; + GWStatus_m NextGWStatus; + MasStatus_m MasStatus; + InStatus_m InStatus; + + DeviceData_T DevData; + + bool SubsetCaliOk; //子设备校准标志位 + bool MasterCaliOk; //主设备标校标志位 + + uint8_t ReadDataAdd; //获取数据地址 + uint16_t DeviceDataLen; //在线设备采集到的数据长度总和 + uint8_t DeviceDataBuff[512]; //在线设备采集到的数据缓存（主设备的数据永远排在最前面） + uint8_t DeviceData[512]; //在线设备采集到的数据（主设备的数据永远排在最前面） + bool SubsetReadDataOk; //子设备读取数据成功标志位 + bool DeviceReadDataOk; //设备读取数据完成标志位 + + uint8_t DeviceN; //在线设备数量（最多32个子设备,1个主设备） + uint8_t Dev485Addr; //在线设备485地址（最多32个子设备,1个主设备） + uint8_t Dev485Addrs[16]; //在线设备485地址缓存，0位为0x00广播地址 + uint8_t DeviceMAC[16][6]; //在线设备的唯一MAC地址（主设备的MAC永远排在最前面） + bool SubsetMACOk; //在线子设备MAC获取成功标志位 + bool DeviceMACOk; //在线设备获取完成标志位 + + bool CollTimeSetOk; //采集时间设置成功标志位 + uint8_t CollTimeAdd; //设置采集时间地址 + + bool SyncTimeOk; //时间同步成功标志位 + uint8_t SyncTimeAdd; //时间同步设备地址 + + bool BroadCmd; //广播命令 + + bool LoginOk; //注册成功标志位 + bool LoginMess; + + bool UploadOk; //上传成功标志位 + bool UploadMess; + + bool Gateway_IRQ_Status; //网关接收中断 + bool Subset_IRQ_Status; //子设备接收中断 + bool TimingAcquisition; //采集传感器数据 + + /**激光示踪私有**/ + bool LaserOnOff; //打开与关闭激光标志位 +}SGCP_t; +extern SGCP_t SGCP; + +void SGCP1mSRoutine(void); + +void GwRevLoopHandler(void); +void MasRevLoopHandler(void); +void SubRevLoopHandler(void); +void InRevLoopHandler(void); +#endif + + diff --git a/source/inc/Update.h b/source/inc/Update.h new file mode 100644 index 0000000..2bf53aa --- /dev/null +++ b/source/inc/Update.h @@ -0,0 +1,61 @@ +#ifndef __UPDATE_H +#define __UPDATE_H + +#include +#include "bsp.h" +#include "UartDebug.h" + +#define APP_START_FLAG 0x55AA5A5A +#define APP_UPDATE_FLAG 0xA5A5AA55 + +#define FLASH_SECTOR_SIZE 0x200ul +#define FLASH_BASE ((uint32_t)0x00000000) +#define FLASH_SIZE (256u * FLASH_SECTOR_SIZE) + +#define SRAM_BASE ((uint32_t)0x20000000) +#define RAM_SIZE 0x2000ul + +#define BOOT_ADDRESS FLASH_BASE +#define BOOT_SIZE (20 * FLASH_SECTOR_SIZE) +#define DEV_MAC_ADDRESS (BOOT_ADDRESS + BOOT_SIZE) //0x00002800 +#define DEV_MAC_SIZE FLASH_SECTOR_SIZE +#define APP_ADDRESS (DEV_MAC_ADDRESS + DEV_MAC_SIZE) + +#define BOOT_PARA_ADDRESS (0x0001FC00)//(FLASH_BASE + BOOT_SIZE) +#define BOOT_PARA_SIZE (FLASH_SECTOR_SIZE) + +typedef struct { + uint32_t AppFlag; + uint32_t UpdateFlag; + uint32_t PackageCnt; + uint32_t AppSize; + uint32_t Crc32Check; +}BootPara_t, *BootPara; + +//主机下发升级请求载荷结构体 +typedef struct { + uint16_t PackageNum; + uint32_t AppSize; + uint32_t AppCrc32; +}__attribute__ ((packed))UpDataRequset_t, *UDReq; + +//帧头结构体 +typedef struct { + uint8_t Header; + uint8_t DevMac[6]; + uint8_t Cmd; + uint8_t PayloadLen; +}__attribute__((packed))UpdateFrameHeader_t,*pUpdateFrameHeader; + + +//输入接口函数定义,需根据接口重新定义 +#define U_DBG_LOG(...) DBG_LOG(__VA_ARGS__) +#define U_DELAY_MS(x) delay_ms(x) +#define U_SYSTEM_TESET() SystemReset() +#define SAVE_BOOT_PARA(addr) FlashWrite(BOOT_PARA_ADDRESS, addr, sizeof(BLPara) / 4) +#define READ_BOOT_PARA(addr) FlashRead(BOOT_PARA_ADDRESS, addr, sizeof(BLPara) / 4) + +//输出接口 +void Update(uint8_t *PayLoad); +void UpdateInit(void); +#endif \ No newline at end of file diff --git a/source/inc/bsp.h b/source/inc/bsp.h new file mode 100644 index 0000000..377ecdf --- /dev/null +++ b/source/inc/bsp.h @@ -0,0 +1,271 @@ +#ifndef _BSP_H +#define _BSP_H + +#include +#include +#include +#include "gpio.h" +#include "spi.h" + +/*模块启用与关闭*/ +#define USE_DEBUG 1 //调试串口选择，0、关闭，1、启用 +#define USE_VBAT_AD 1 //电池电压AD获取选择，0、关闭，1、启用 +#define USE_WDT 1 //看门狗选择，0、关闭，1启用 +#define USE_EXFALSE 0 //外部FALSE存储选择，0、关闭，1、启用 +#define USE_LED 1 //状态灯选择，0、关闭，1、启用 +#define USE_RTC 1 //RTC时钟开关，0、关闭，1、开启 + +#define USE_LPUART0 1 //LPUART0开关，0、关闭，1、启用 +#define USE_UART0 1 //UART0开关，0、关闭，1、启用 +#define USE_UART1 0 //UART0开关，0、关闭，1、启用 +#define USE_I2C0 1 //I2C0开关，0、关闭，1、启用 +#define USE_I2C1 1 //I2C1开关，0、关闭，1、启用 +#define USE_SPI0 1 //SPI1开关，0、关闭，1、启用 +#define USE_SPI1 0 //SPI1开关，0、关闭，1、启用 + +#define USE_BOOTLOADER 1 //BOOTLOADER开关，0、关闭，1、启用 +#define USE_LORA_CH 1 //0为测试通道 + +//<<---------------------------- MCU -------------------------------->> +//< UART0 +#define UART0_TX_PORT GpioPortA +#define UART0_TX_PIN GpioPin9 +#define UART0_TX_AF GpioAf1 + +#define UART0_RX_PORT GpioPortA +#define UART0_RX_PIN GpioPin10 +#define UART0_RX_AF GpioAf1 + +//< UART1 +#define UART1_TX_PORT GpioPortF +#define UART1_TX_PIN GpioPin0 +#define UART1_TX_AF GpioAf3 + +#define UART1_RX_PORT GpioPortF +#define UART1_RX_PIN GpioPin1 +#define UART1_RX_AF GpioAf3 + +//< 低功耗串口 +#define LPUart0_TxPortx GpioPortB //低功耗串口0通道 +#define LPUART0_TxPinx GpioPin10 //配置PB10为LPUART0_Tx +#define LPUART0_TX_AF GpioAf4 + +#define LPUart0_RxPortx GpioPortB //低功耗串口0通道 +#define LPUART0_RxPinx GpioPin11 //配置PB11为LPUART0_Rx +#define LPUART0_RX_AF GpioAf3 + +//< SPI0 +#define SPI0_NSS_PORTx GpioPortA //NSSIO口 +#define SPI0_NSS_PINx GpioPin15 //配置PA04为NSS +#define SET_SPI0_NSS() Gpio_SetIO(SPI0_NSS_PORTx, SPI0_NSS_PINx) //NSS拉高 +#define CLR_SPI0_NSS() Gpio_ClrIO(SPI0_NSS_PORTx, SPI0_NSS_PINx) //NSS拉低 +#define SPI0_NSS_AF GpioAf1 + +#define SPI0_SCK_PORTx GpioPortB //SCKIO口 +#define SPI0_SCK_PINx GpioPin3 //配置PA05为SCK +#define SET_SPI0_SCK() Gpio_SetIO(SPI0_SCK_PORTx, SPI0_SCK_PINx) //SCK拉高 +#define CLR_SPI0_SCK() Gpio_ClrIO(SPI0_SCK_PORTx, SPI0_SCK_PINx) //SCK拉低 +#define SPI0_SCK_AF GpioAf1 + +#define SPI0_MISO_PORTx GpioPortB //MISOIO口 +#define SPI0_MISO_PINx GpioPin4 //配置PA06为MISO +#define SET_SPI0_MISO() Gpio_SetIO(SPI0_MISO_PORTx, SPI0_MISO_PINx) //MISO拉高 +#define CLR_SPI0_MISO() Gpio_ClrIO(SPI0_MISO_PORTx, SPI0_MISO_PINx) //MISO拉低 +#define SPI0_MISO_AF GpioAf1 + +#define SPI0_MOSI_PORTx GpioPortB //MOSIIO口 +#define SPI0_MOSI_PINx GpioPin5 //配置PA07为MOSI +#define SET_SPI0_MOSI() Gpio_SetIO(SPI0_MOSI_PORTx, SPI0_MOSI_PINx) //MOSI拉高 +#define CLR_SPI0_MOSI() Gpio_ClrIO(SPI0_MOSI_PORTx, SPI0_MOSI_PINx) //MOSI拉低 +#define SPI0_MOSI_AF GpioAf1 + +//< SPI1 +#define SPI1_NSS_PORTx GpioPortB //NSSIO口 +#define SPI1_NSS_PINx GpioPin12 //配置PB12为NSS +#define SET_SPI1_NSS() Gpio_SetIO(SPI1_NSS_PORTx, SPI1_NSS_PINx) //NSS拉高 +#define CLR_SPI1_NSS() Gpio_ClrIO(SPI1_NSS_PORTx, SPI1_NSS_PINx) //NSS拉低 +#define SPI1_NSS_AF GpioAf1 + +#define SPI1_SCK_PORTx GpioPortB //SCKIO口 +#define SPI1_SCK_PINx GpioPin3 //配置PB13为SCK +#define SET_SPI1_SCK() Gpio_SetIO(SPI1_SCK_PORTx, SPI1_SCK_PINx) //SCK拉高 +#define CLR_SPI1_SCK() Gpio_ClrIO(SPI1_SCK_PORTx, SPI1_SCK_PINx) //SCK拉低 +#define SPI1_SCK_AF GpioAf1 + +#define SPI1_MISO_PORTx GpioPortB //MISOIO口 +#define SPI1_MISO_PINx GpioPin4 //配置PB14为MISO +#define SET_SPI1_MISO() Gpio_SetIO(SPI1_MISO_PORTx, SPI1_MISO_PINx) //MISO拉高 +#define CLR_SPI1_MISO() Gpio_ClrIO(SPI1_MISO_PORTx, SPI1_MISO_PINx) //MISO拉低 +#define SPI1_MISO_AF GpioAf1 + +#define SPI1_MOSI_PORTx GpioPortB //MOSIIO口 +#define SPI1_MOSI_PINx GpioPin5 //配置PB15为MOSI +#define SET_SPI1_MOSI() Gpio_SetIO(SPI1_MOSI_PORTx, SPI1_MOSI_PINx) //MOSI拉高 +#define CLR_SPI1_MOSI() Gpio_ClrIO(SPI1_MOSI_PORTx, SPI1_MOSI_PINx) //MOSI拉低 +#define SPI1_MOSI_AF GpioAf1 + +//< I2C0 +#define I2C0_SCL_PORTx GpioPortF //SCL的GPIO通道 +#define I2C0_SCL_PINx GpioPin1 //SCL的通道位 +#define I2C0_SCL_AF GpioAf1 +#define SET_I2C0_SCL() Gpio_SetIO(I2C0_SCL_PORTx, I2C0_SCL_PINx) +#define CLR_I2C0_SCL() Gpio_ClrIO(I2C0_SCL_PORTx, I2C0_SCL_PINx) + +#define I2C0_SDA_PORTx GpioPortF //SDA的GPIO通道 +#define I2C0_SDA_PINx GpioPin0 //SDA的通道位 +#define I2C0_SDA_AF GpioAf1 +#define SET_I2C0_SDA() Gpio_SetIO(I2C0_SDA_PORTx, I2C0_SDA_PINx) +#define CLR_I2C0_SDA() Gpio_ClrIO(I2C0_SDA_PORTx, I2C0_SDA_PINx) + +//< I2C1 +#define I2C1_SCL_PORTx GpioPortA //SCL的GPIO通道 +#define I2C1_SCL_PINx GpioPin11 //SCL的通道位 +#define I2C1_SCL_AF GpioAf3 +#define SET_I2C1_SCL() Gpio_SetIO(I2C1_SCL_PORTx, I2C1_SCL_PINx) +#define CLR_I2C1_SCL() Gpio_ClrIO(I2C1_SCL_PORTx, I2C1_SCL_PINx) + +#define I2C1_SDA_PORTx GpioPortA //SDA的GPIO通道 +#define I2C1_SDA_PINx GpioPin12 //SDA的通道位 +#define I2C1_SDA_AF GpioAf3 +#define SET_I2C1_SDA() Gpio_SetIO(I2C1_SDA_PORTx, I2C1_SDA_PINx) +#define CLR_I2C1_SDA() Gpio_ClrIO(I2C1_SDA_PORTx, I2C1_SDA_PINx) + +//<<---------------------------- 485 -------------------------------->> +//< LPUart0 +#define RS485_CTRL_PORTx GpioPortB //RS485_1通信控制 +#define RS485_CTRL_PINx GpioPin1 //配置PB02为RS485_1_CTRL +#define RS485_CTRL_TX() Gpio_SetIO(RS485_CTRL_PORTx, RS485_CTRL_PINx) //RS485_1_CTRL拉高发送 +#define RS485_CTRL_RX() Gpio_ClrIO(RS485_CTRL_PORTx, RS485_CTRL_PINx) //RS485_1_CTRL拉低接收 + +//<<---------------------------- LED -------------------------------->> +//< LED_State +#define LED_STATE_PORTx GpioPortF //状态指示灯IO通道 +#define LED_STATE_PINx GpioPin7 //状态指示灯脚位 +#define LED_ON() Gpio_SetIO(LED_STATE_PORTx, LED_STATE_PINx);//状态指示灯亮 +#define LED_OFF() Gpio_ClrIO(LED_STATE_PORTx, LED_STATE_PINx);//状态指示灯灭 + +//<<---------------------------- LORA --> SPI0 -------------------------------->> +//< LORA --> DIO0 +#define LORA_DIO0_PORTx GpioPortB //LORA_DIO0口 +#define LORA_DIO0_PINx GpioPin7 //配置PA01为DIO0 +#define GET_LORA_DIO0() Gpio_GetInputIO(LORA_DIO0_PORTx, LORA_DIO0_PINx) //获取LORA_DIO0电平状态 +//< LORA --> DIO1 +#define LORA_DIO1_PORTx GpioPortB //LORA_DIO0口 +#define LORA_DIO1_PINx GpioPin0 //配置PA01为DIO0 +#define GET_LORA_DIO1() Gpio_GetInputIO(LORA_DIO1_PORTx, LORA_DIO1_PINx) //获取LORA_DIO0电平状态 + +//< LORA --> RST +#define LORA_RST_PORTx GpioPortB //LORA_RST口 +#define LORA_RST_PINx GpioPin6 //配置PA00为RST +#define SET_LORA_RST() Gpio_SetIO(LORA_RST_PORTx, LORA_RST_PINx) //LORA复位脚拉高 +#define CLR_LORA_RST() Gpio_ClrIO(LORA_RST_PORTx, LORA_RST_PINx) //LORA复位脚拉低 + +//<<---------------------------- LSM6DSLTR --> I2C0 -------------------------------->> +//< ACC_INT1 +#define LSM6DSLTR_INT1_PORTx GpioPortC //LSM6DSLTR中断1IO通道 +#define LSM6DSLTR_INT1_PINx GpioPin15 //配置PB01为ACC_INT1 +#define GET_LSM6DSLTR_INT1() Gpio_GetInputIO(LSM6DSLTR_INT1_PORTx, LSM6DSLTR_INT1_PINx) //获取ACC_INT1电平状态 + +//< ACC_INT2 +#define LSM6DSLTR_INT2_PORTx GpioPortC //LSM6DSLTR中断1IO通道 +#define LSM6DSLTR_INT2_PINx GpioPin13 //配置PA08为ACC_INT2 +#define GET_LSM6DSLTR_INT2() Gpio_GetInputIO(LSM6DSLTR_INT2_PORTx, LSM6DSLTR_INT2_PINx) //获取ACC_INT2电平状态 + +//<<---------------------------- MMC5983MA --> I2C0 -------------------------------->> +//< MMC0_INT +#define MMC5983MA_INT_PORTx GpioPortC //MMC5983MA中断IO通道 +#define MMC5983MA_INT_PINx GpioPin14 //配置PB00为MMC_INT +#define GET_MMC5983MA_INT() Gpio_GetInputIO(MMC5983MA_INT_PORTx, MMC5983MA_INT_PINx) //获取ACC_INT2电平状态 + +//<<---------------------------- LASER -------------------------------->> +//< LASER1 +#define LASER1_ON_OFF_PORTx GpioPortB +#define LASER1_ON_OFF_PINx GpioPin14 +#define LASER1_ON() Gpio_SetIO(LASER1_ON_OFF_PORTx, LASER1_ON_OFF_PINx) //LORA复位脚拉高 +#define LASER1_OFF() Gpio_ClrIO(LASER1_ON_OFF_PORTx, LASER1_ON_OFF_PINx) //LORA复位脚拉低 +//< LASER2 +#define LASER2_ON_OFF_PORTx GpioPortB +#define LASER2_ON_OFF_PINx GpioPin13 +#define LASER2_ON() Gpio_SetIO(LASER2_ON_OFF_PORTx, LASER2_ON_OFF_PINx) //LORA复位脚拉高 +#define LASER2_OFF() Gpio_ClrIO(LASER2_ON_OFF_PORTx, LASER2_ON_OFF_PINx) //LORA复位脚拉低 +//< LASER3 +#define LASER3_ON_OFF_PORTx GpioPortB +#define LASER3_ON_OFF_PINx GpioPin12 +#define LASER3_ON() Gpio_SetIO(LASER3_ON_OFF_PORTx, LASER3_ON_OFF_PINx) //LORA复位脚拉高 +#define LASER3_OFF() Gpio_ClrIO(LASER3_ON_OFF_PORTx, LASER3_ON_OFF_PINx) //LORA复位脚拉低 + +//<<------------------------------ ADC ---------------------------------->> +#define AD_ON_OFF_PORTx GpioPortA +#define AD_ON_OFF_PINx GpioPin3 +#define AD_ON() Gpio_SetIO(AD_ON_OFF_PORTx, AD_ON_OFF_PINx) //LORA复位脚拉高 +#define AD_OFF() Gpio_ClrIO(AD_ON_OFF_PORTx, AD_ON_OFF_PINx) //LORA复位脚拉低 + +#define VBAT_PORTx GpioPortA +#define VBAT_PINx GpioPin4 +#define VBAT_ADC_PORTx AdcExInputCH4//采样通道 +#define VBAT_CAL 3.5 //电池电压校准 + +//< 电池电压 +extern float VBAT_8V4; +extern uint8_t VBAT_Percentage; + + +typedef struct { + uint16_t CollectTime; //数据采集时间间隔,设置范围30*N秒,1<=N<=240，(默认5分钟,N=10) + uint16_t ReportInterval; //上报时间间隔，设置范围,30*N秒,10<=N<=1440（默认20分钟,N=40） + uint8_t ERInterval; //紧急上报时间间隔,设置范围,30*N秒,2<=N<=10（默认2分钟,N=4） + uint8_t ERTime; //紧急上报时长,设置范围,30*N秒,20<=N<=240（默认20分钟,N=40） + uint32_t TimeStamp; //网关返回RTC时间戳 +}__attribute__((packed))LayoutPara_t,*LayoutPara;//上位机下发的配置参数 + +typedef struct { + int16_t PitchZero; //俯仰角零点 + int16_t RollZero; //横滚角零点 + int16_t YawZero; //偏航角零点 +}__attribute__ ((packed))CalibratePara_t, *CalibratePara; + +typedef struct { + LayoutPara_t Layout; + CalibratePara_t CaliPara; + uint32_t RS485Addr; //本机485地址 + uint32_t FactoryFlag;//出厂标志位 +}AppPara_T, *pAppPara; +#define APP_PARA_ADDRESS (0x0001FE00) +#define SAVE_APP_PARA(addr) FlashWrite(APP_PARA_ADDRESS, addr, sizeof(App.Para) / 4) +#define READ_APP_PARA(addr) FlashRead(APP_PARA_ADDRESS, addr, sizeof(App.Para) / 4) + +void BspInit(void); +void EnterDeepSleep(void); +void DBGUartSendByte(uint8_t sData); +void DBGUartSend(uint8_t *sData, int sLen); +void LPUart0SendArray(uint8_t *sData, uint8_t sLen); +void Uart1SendArray(uint8_t *sData, uint8_t sLen); + +uint32_t GetSysTick(void); +void delay_ms(uint32_t ms); +void Delay(uint32_t time); +void RTCInit(uint8_t sec); +void LPTimer0_ON(uint16_t _100ms); +void LPTimer0_OFF(void); +void WakeUpInit(void); +void FeedDog(void); +uint32_t TimeTs(void); +void TimeShow(uint32_t dwStamp); +void TimeSync(time_t ts); +void PrintfMess(void); +void SystemReset(void); +uint8_t Spi0SendReceive(uint8_t sData); +uint8_t Spi1SendReceive(uint8_t sData); +void FlashWrite(uint32_t Addr, uint32_t *wData, int wLen); +void FlashRead(uint32_t Addr, uint32_t *rData, int rLen); + +void ADCLoopHandler(void); +void LORA_RxCallBack(uint8_t *rBuff, uint8_t rlen); + +void GlobalIntEnable(void); +void GlobalIntDisable(void); +void LORAIntEnable(void); +void LORAIntDisable(void); +void ACCandMMCIntEnable(void); +void ACCandMMCIntDisable(void); +#endif diff --git a/source/inc/main.h b/source/inc/main.h new file mode 100644 index 0000000..f3c09e7 --- /dev/null +++ b/source/inc/main.h @@ -0,0 +1,107 @@ +#ifndef __MAIN_H +#define __MAIN_H +#include "bsp.h" +#include "UartDebug.h" +#include "Imu.h" + +#define X 0 +#define Y 1 +#define Z 2 +#define XYZ 3 + +#define SYSTEM_TIMING_LOGIN (86400 / 30) //系统定时注册时间(一天86400秒) +#define ERR_TIMING_LOGIN (1800 / 30) //注册错误重新注册时间(半个小时1800秒) + +#define TEST_TIME (60*60*1000) + +#define ERINTERVAL_VPT 10 //紧急上报阈值，单位0.1° +#define ERINTERVAL_VPT 10 //紧急上报阈值，单位0.1° + +typedef struct {//传感器原始数据 + float acce[XYZ]; + float gy[XYZ]; + float mag[XYZ]; +}__attribute__ ((packed))SensorData_T,*SensorDp;//传感器数据 + +typedef struct {//转换的数据 + int16_t Pitch; //俯仰角偏斜 （范围±900）单位0.1° + int16_t Roll; //横滚角偏斜 （范围±900）单位0.1° + int16_t Yaw; //偏航角偏斜 （范围0~3600）单位0.1° +// int16_t Temp; //温度值 +// int32_t AD; //AD值 +}__attribute__ ((packed))ConvertedData_T, *ConvertedDp; + +typedef struct {// 姿态角数据 + Rad_T Rad; + Deg_T Deg; +}__attribute__ ((packed))AHRSData_T,*AHRSDp; + +/*主程序状态机*/ +typedef enum { + APP_STATUS_IDLE, + APP_STATUS_SLEEP, + APP_STATUS_ON, + APP_STATUS_OFF, + APP_STATUS_ACTION, + APP_STATUS_WAIT_LOGIN, + APP_STATUS_WAIT_UPLOAD, +}AppStatus_m; + +/*数据读取状态机*/ +typedef enum { + READDATA_STATUS_IDLE, + READDATA_STATUS_UPDAING, + READDATA_STATUS_WAIT_UPDAING, + READDATA_STATUS_DATA_HANDLE, +}ReadDataStatus_m; + +typedef struct { + AppStatus_m Status;//状态 + ReadDataStatus_m RDStatus;//读取数据状态 + + uint32_t TD1mSDelayCnt; + uint8_t FeedDogDlyCnt; + uint32_t ReadData1mSDelayCnt; + uint32_t SysResetTimeCnt; + + SensorData_T Sensor; + AppPara_T Para; + AHRSData_T AHRSData; + ConvertedData_T ConvertedData; + + uint32_t RepeLoginCount; //24h重复注册计数 + uint8_t Login30MinCount; //注册30分定时计数 + uint8_t Login2Min30SCount; //注册100ms~2分+30s定时计数 + bool Login_RTC; //注册30分定时器启动标志位 + bool Login_LPTimer0; //注册100ms~2分+30s定时器启动标志位 + bool LoginFlag; //注册标志位 + + uint16_t Coll_N; //数据采集时间计数 + uint16_t Repor_N; //上报时间计数 + uint16_t ERInterval_N; //紧急上报时间间隔计数 + uint8_t ERTime_N; //紧急上报时间计数 + bool ERFlag; //紧急上报标志位 + + bool UploadFlag; //上传数据标志位 + uint8_t Upload45S10SCount; //上传数据超时计数 + bool Upload_LPTimer0; //上传100~10000ms+45秒定时器启动标志位 + + bool MagRead_EndFlag; + bool AccRead_EndFlag; + bool UpdateOk; //数据更新标志位 + + bool CaliFlag; //标校标志位 + + int16_t Nonce; //随机数 + + uint32_t TestTimeCnt; + uint8_t Tcnt; + bool LaserFlag; +}AppDetect_t; + +extern AppDetect_t App; +#endif + + + + diff --git a/source/src/Algorithm.c b/source/src/Algorithm.c new file mode 100644 index 0000000..c28bba9 --- /dev/null +++ b/source/src/Algorithm.c @@ -0,0 +1,783 @@ +#include "bsp.h" +#include "Algorithm.h" +#include "UartDebug.h" + +/***************************************************************************************** +* 函数名称: check_peaks_valleys_ratio +* 功能描述: 检查数据的峰值是否大于0，谷值是否小于0（忽略0值） +* 参 数: data, 数据 + length, 数据长度 +* 返 回 值: 结果返回峰值谷值检查结果结构体 +*****************************************************************************************/ +PeakValleyCheck check_peaks_valleys(int data[], int length) { + PeakValleyCheck result = {true, true, 0, 0}; + + // 如果数据长度小于3，无法形成有效的峰值/谷值 + if (length < 3) { + return result; + } + + int i = 0; + // 跳过开头的0值 + while (i < length && data[i] == 0) { + i++; + } + + // 遍历数据点 + while (i < length) { + // 1. 寻找下一个非零点作为起点 + int start = i; + while (i < length && data[i] == 0) { + i++; + } + if (i >= length) break; + + // 2. 寻找当前非零段的结束点 + int end = i; + while (end < length && data[end] != 0) { + end++; + } + end--; // 指向最后一个非零点 + + // 3. 在当前非零段中检测峰值和谷值 + for (int j = i; j <= end; j++) { + // 跳过边界点 + if (j == i || j == end) continue; + + // 检查是否为峰值（大于左右相邻的非零点） + if (data[j] > data[j-1] && data[j] > data[j+1]) { + result.peak_count++; + if (data[j] <= 0) { + result.peaks_positive = false; + } + } + + // 检查是否为谷值（小于左右相邻的非零点） + if (data[j] < data[j-1] && data[j] < data[j+1]) { + result.valley_count++; + if (data[j] >= 0) { + result.valleys_negative = false; + } + } + } + + // 移动到下一段 + i = end + 1; + } + + return result; +} +/***************************************************************************************** +* 函数名称: analyze_trend +* 功能描述: 趋势分析函数 +* 参 数: data, 数据 + length, 数据长度 +* 返 回 值: 结果返回趋势分析结构体 +*****************************************************************************************/ +TrendResult analyze_trend(int data[], int length) { + TrendResult result = {0}; + #if 1 + // 0. 检查有效数据长度 + if (length < 2) { + DBG_LOG("Data deficient\r\n"); + return result; + } + + // 1. 计算线性回归斜率 + double sum_x = 0, sum_y = 0, sum_xy = 0, sum_x2 = 0; + + for (int i = 0; i < length; i++) { + double x = i; // 时间序列 (0,1,2,...) + double y = data[i]; + sum_x += x; + sum_y += y; + sum_xy += x * y; + sum_x2 += x * x; + } + + double numerator = length * sum_xy - sum_x * sum_y; + double denominator = length * sum_x2 - sum_x * sum_x; + + // 处理分母为零的情况 + if (fabs(denominator) > 1e-10) { + result.slope = numerator / denominator; + } + #endif + #if 0 + // 2. 计算振荡特征（差分符号变化次数） + int sign_changes = 0; + int prev_sign = 0; // 0=未初始化, 1=正, -1=负 + + for (int i = 1; i < length; i++) { + int diff = data[i] - data[i-1]; + int curr_sign = (diff > 0) ? 1 : (diff < 0) ? -1 : 0; + + if (curr_sign != 0) { + if (prev_sign != 0 && curr_sign != prev_sign) { + sign_changes++; + } + prev_sign = curr_sign; + } + } + result.sign_changes = sign_changes; + #endif + #if 0 + // 3. 动态计算阈值（基于数据长度） + int oscillation_threshold = (int)(0.4 * (length - 1)); // 40%的变化率 + double slope_threshold = 0.05 * (length / 20.0); // 长度标准化 + #endif + #if 0 + // 4. 趋势判断 + if (sign_changes >= oscillation_threshold) { + //DBG_LOG("Oscillating trend\r\n");//振荡趋势 + result.trend_type = 0; + } else if (fabs(result.slope) < slope_threshold) { + //DBG_LOG("Smooth trend\r\n");//平稳趋势 + result.trend_type = 1; + } else if (result.slope > 0) { + //DBG_LOG("Up trend\r\n");//上升趋势 + result.trend_type = 2; + } else { + //DBG_LOG("Down trend\r\n");//下降趋势 + result.trend_type = 3; + } + #endif + #if 0 + // 5. 陡峭判断 + double abs_slope = fabs(result.slope); + if (abs_slope > 0.8) { + //DBG_LOG("Steeply");//陡峭 + result.sign_changes = 0; + } else if (abs_slope > 0.3) { + //DBG_LOG("Obvious");//明显 + result.sign_changes = 1; + } else if (abs_slope > 0.1) { + //DBG_LOG("Mild");//温和 + result.sign_changes = 2; + } else { + //DBG_LOG("gentle");//平缓 + result.sign_changes = 3; + } + #endif + return result; +} +/***************************************************************************************** +* 函数名称: calculateAverage +* 功能描述: 计算平均值 +* 参 数: arr, 数据 + size, 数据长度 +* 返 回 值: 结果返回 long long 防溢出 +*****************************************************************************************/ +float calculateAverage(int *arr, int size) +{ + int sum = 0; + for (int i = 0; i < size; i++) { + sum += arr[i]; // 累加数组中的每个元素 + } + return (float)sum / size; // 返回平均值 +} +/***************************************************************************************** +* 函数名称: slope +* 功能描述: 计算斜率 +* 参 数: x_data, x轴数据 + y_data, y轴数据 +* 返 回 值: 结果返回 long long 防溢出 +*****************************************************************************************/ +double slope(int32_t *x_data, int32_t *y_data, int n) +{ + double sum_x = 0, sum_y = 0, sum_xx = 0, sum_xy = 0; + for (int i = 0; i < n; i++) { + sum_x += x_data[i]; + sum_y += y_data[i]; + sum_xx += pow(x_data[i] - calculateAverage(x_data, n), 2); + sum_xy += (x_data[i] - calculateAverage(x_data, n)) * (y_data[i] - calculateAverage(y_data, n)); + } + + return sum_xy / sum_xx; +} +/***************************************************************************************** +* 函数名称: power +* 功能描述: 快速幂算法 +* 参 数: base, 滤波数据 + exponent, 滤波数据长度 +* 返 回 值: 结果返回 long long 防溢出 +*****************************************************************************************/ +long long power(int base, unsigned int exponent) { + long long result = 1; + while (exponent > 0) { + if (exponent % 2 == 1) { + result *= base; // 指数为奇数时累乘 + } + base *= base; // 底数平方 + exponent /= 2; // 指数折半 + } + return result; +} +/***************************************************************************************** +* 函数名称: IntFilter_16t +* 功能描述: 16位数据中值滤波函数 +* 参 数: Data, 滤波数据 + Cnt, 滤波数据长度 + FilterCnt, 滤除的数据长度，必须为2的倍数 +* 返 回 值: 滤波后的16位数据 +*****************************************************************************************/ +int IntFilter_16t(int16_t *Data, uint8_t Cnt, uint8_t FilterCnt) +{ + int32_t sum = 0; + int32_t temp; + + if(Cnt < 2) + return *Data; + + for(int j=0; j Data[i+1]) { + temp = Data[i]; + Data[i] = Data[i+1]; + Data[i+1] = temp; + } + } + } + + for(int count = FilterCnt / 2; count < Cnt - FilterCnt / 2; count++) + sum += Data[count]; + return (sum / (Cnt - FilterCnt)); +} + +/***************************************************************************************** +* 函数名称: IntFilter_32t +* 功能描述: 32位数据中值滤波函数 +* 参 数: Data, 滤波数据 + Cnt, 滤波数据长度 + FilterCnt, 滤除的数据长度，必须为2的倍数 +* 返 回 值: 滤波后的32位数据 +*****************************************************************************************/ +int IntFilter_32t(int32_t *Data, uint8_t Cnt, uint8_t FilterCnt) +{ + int32_t sum = 0; + int32_t temp; + + if(Cnt < 2) + return *Data; + + for(int j=0; j Data[i+1]) { + temp = Data[i]; + Data[i] = Data[i+1]; + Data[i+1] = temp; + } + } + } + + for(int count = FilterCnt / 2; count < Cnt - FilterCnt / 2; count++) + sum += Data[count]; + return (sum / (Cnt - FilterCnt)); +} +/***************************************************************************************** +* 函数名称: IntFilter_u32t +* 功能描述: 32位无符号位数据中值滤波函数 +* 参 数: Data, 滤波数据 + Cnt, 滤波数据长度 + FilterCnt, 滤除的数据长度，必须为2的倍数 +* 返 回 值: 滤波后的32位数据 +*****************************************************************************************/ +uint32_t IntFilter_u32t(uint32_t *Data, uint8_t Cnt, uint8_t FilterCnt) +{ + uint32_t sum = 0; + uint32_t temp; + + if(Cnt < 2) + return *Data; + + for(int j=0; j Data[i+1]) { + temp = Data[i]; + Data[i] = Data[i+1]; + Data[i+1] = temp; + } + } + } + + for(int count = FilterCnt / 2; count < Cnt - FilterCnt / 2; count++) + sum += Data[count]; + return (sum / (Cnt - FilterCnt)); +} +/***************************************************************************************** +* 函数名称: IntFilter_Float +* 功能描述: 32位浮点数数据中值滤波函数 +* 参 数: Data, 滤波数据 + Cnt, 滤波数据长度 + FilterCnt, 滤除的数据长度，必须为2的倍数 +* 返 回 值: 滤波后的32位数据 +*****************************************************************************************/ +float IntFilter_Float(float *Data, uint8_t Cnt, uint8_t FilterCnt) +{ + float sum = 0; + float temp; + + if(Cnt < 2) + return *Data; + + for(int j=0; j Data[i+1]) { + temp = Data[i]; + Data[i] = Data[i+1]; + Data[i+1] = temp; + } + } + } + + for(int count = FilterCnt / 2; count < Cnt - FilterCnt / 2; count++) + sum += Data[count]; + return (sum / (Cnt - FilterCnt)); +} +/***************************************************************************************** +* 函数名称: AverageFilter_u32t +* 功能描述: 32位数据均值滤波函数,去除了最大值和最小值 +* 参 数: Data, 滤波数据 + Cnt, 滤波数据长度 +* 返 回 值: 滤波后的32位数据 +*****************************************************************************************/ +uint32_t AverageFilter_u32t(uint32_t *Data, uint8_t Cnt) +{ + uint32_t sum = 0; + uint32_t temp; + uint32_t max = Data[0]; + uint32_t min = Data[0]; + + if(Cnt == 0) + return 0; + + if(Cnt == 1) + return Data[0]; + + if(Cnt == 2) + { + sum = Data[0] + Data[1]; + return sum / 2; + } + + for (uint8_t i = 0; i < Cnt; i++)//找出最大值 + { + if (Data[i] > max) + { + max = Data[i]; + } + } + + for (uint8_t i = 0; i < Cnt; i++)//找出最小值 + { + if (Data[i] < min) + { + min = Data[i]; + } + } + + for(int i = 0; i < Cnt; i++){//求和 + sum += Data[i]; + } + + return (sum - max - min) / (Cnt - 2); +} + +/***************************************************************************************** +* 函数名称: AverageFilter_32t +* 功能描述: 32位数据均值滤波函数,去除了最大值和最小值 +* 参 数: Data, 滤波数据 + Cnt, 滤波数据长度 +* 返 回 值: 滤波后的32位数据 +*****************************************************************************************/ +int AverageFilter_32t(int32_t *Data, uint8_t Cnt) +{ + int32_t sum = 0; + int32_t max = Data[0]; + int32_t min = Data[0]; + + if(Cnt == 0) + return 0; + + if(Cnt == 1) + return Data[0]; + + if(Cnt == 2) + { + sum = Data[0] + Data[1]; + return sum / 2; + } + + for (uint8_t i = 0; i < Cnt; i++)//找出最大值 + { + if (Data[i] > max) + { + max = Data[i]; + } + } + + for (uint8_t i = 0; i < Cnt; i++)//找出最小值 + { + if (Data[i] < min) + { + min = Data[i]; + } + } + + for(int i = 0; i < Cnt; i++){//求和 + sum += Data[i]; + } + + return (sum - max - min) / (Cnt - 2); +} +/***************************************************************************************** +* 函数名称: Fitting_Polynomial +* 功能描述: 根据数组AD[], Actual[]列出的一组数据，用最小二乘法求它的拟合曲线,默认3阶 + 近似解析表达式为y = a3*x^3 + a2*x^2 + a1*x + a0; +* 参 数: AD, AD芯片采样值 + Actual, 实际标校值 + Cnt, 拟合数据个数 +* 返 回 值: 无 +*****************************************************************************************/ +void Fitting_Polynomial(double *AD, double *Actual, uint8_t Cnt) +{ + static const uint8_t rank_ = 3;//拟合阶数3 + double atemp[2 * (rank_ + 1)], b[rank_ + 1], a[rank_ + 1][rank_ + 1]; + int i, j, k; + + for(i = 0; i < Cnt; i++){ + atemp[1] += AD[i]; + atemp[2] += pow(AD[i], 2); + atemp[3] += pow(AD[i], 3); + atemp[4] += pow(AD[i], 4); + atemp[5] += pow(AD[i], 5); + atemp[6] += pow(AD[i], 6); + b[0] += Actual[i]; + b[1] += AD[i] * Actual[i]; + b[2] += pow(AD[i], 2) * Actual[i]; + b[3] += pow(AD[i], 3) * Actual[i]; + } + + atemp[0] = Cnt; + + for(i = 0; i < rank_ + 1; i++){ //构建线性方程组系数矩阵，b[]不变 + k = i; + for(j = 0; j < rank_ + 1; j++) a[i][j] = atemp[k++]; + } + + //以下为高斯列主元消去法解线性方程组 + for(k = 0; k < rank_ + 1 - 1; k++){ //n - 1列 + int column = k; + double mainelement = a[k][k]; + + for(i = k; i < rank_ + 1; i++) //找主元素 + if(fabs(a[i][k]) > mainelement){ + mainelement = fabs(a[i][k]); + column = i; + } + for(j = k; j < rank_ + 1; j++){ //交换两行 + double atemp = a[k][j]; + a[k][j] = a[column][j]; + a[column][j] = atemp; + } + double btemp = b[k]; + b[k] = b[column]; + b[column] = btemp; + + for(i = k + 1; i < rank_ + 1; i++){ //消元过程 + double Mik = a[i][k] / a[k][k]; + for(j = k; j < rank_ + 1; j++) a[i][j] -= Mik * a[k][j]; + b[i] -= Mik * b[k]; + } + } + + b[rank_ + 1 - 1] /= a[rank_ + 1 - 1][rank_ + 1 - 1]; //回代过程 + for(i = rank_ + 1 - 2; i >= 0; i--){ + double sum = 0; + for(j = i + 1; j < rank_ + 1; j++) sum += a[i][j] * b[j]; + b[i] = (b[i] - sum) / a[i][i]; + }//高斯列主元消去法结束 + + DBG_LOG("P(x) = %.16fx^3%+.16fx^2%+.16fx%+.16f\r\n", b[3], b[2], b[1], b[0]); + +// App.Para.Cali.FitCoef[0] = b[0]; +// App.Para.Cali.FitCoef[1] = b[1]; +// App.Para.Cali.FitCoef[2] = b[2]; +// App.Para.Cali.FitCoef[3] = b[3]; + +} +/***************************************************************************************** +* 函数名称: get_K +* 功能描述: 斜率计算 +* 参 数: count，数据个数 数组行(列)的个数 数组的行列数目相等 + dataCol_X[count]，数据的列数据 + dataRow_Y[count]，数据的行数据 +* 返 回 值: k 斜率 +*****************************************************************************************/ +float get_K(uint8_t count , int32_t *dataCol_X, int32_t *dataRow_Y) +{ + float k = 0;//斜率 + float aveCol_X = 0;//列的平均值x + float aveRow_Y = 0;//行的平均值y + int32_t sum_XY = 0;//行列的总和xy + int32_t sumRow_Y = 0;//行的总和y + int32_t sumCol_X = 0;//列的总和x + int32_t sumCol_X2 = 0;//列的总和x^2 + + for(uint16_t i = 0 ; i < count ; i++) + { + sumCol_X += dataCol_X[i];//求列x的总和 + sumRow_Y += dataRow_Y[i];//求行y的总和 + sumCol_X2 += dataCol_X[i] * dataCol_X[i];//求x^2的总和 + sum_XY += (dataCol_X[i] * dataRow_Y[i]);//求xy的总和 + } + + aveCol_X = 1.0 * sumCol_X / count;//求平均值 + aveRow_Y = 1.0 * sumRow_Y / count; + + k = (sum_XY - aveCol_X * aveRow_Y * count) / //根据公式求斜率 + (sumCol_X2 - aveCol_X * aveCol_X * count); + + return k; +} +/***************************************************************************************** +* 函数名称: TrendAnalyse +* 功能描述: 判断数组中的值的总体趋势 +* 参 数: Data, + Cnt, + VPT, +* 返 回 值: true或false +*****************************************************************************************/ +int8_t TrendAnalyse(int32_t *Data, uint8_t Cnt, int32_t VPT) +{ + int8_t zero = 0,plus = 0, minus = 0, Trend = 0xEE; + + if(Cnt < 2) + return Trend; + + for(uint8_t i = 1; i < Cnt; i++) + { + if((Data[i] - Data[i - 1]) <= VPT && ((Data[i] - Data[i - 1]) >= (-VPT))) + { + zero++; + } + else if((Data[i] - Data[i - 1]) > VPT) + { + plus++; + } + else if((Data[i] - Data[i - 1]) < VPT) + { + minus++; + } + } + if(zero > (Cnt-(Cnt / 5))) + Trend = 0;//振荡趋势 + else if(plus > (Cnt-(Cnt/ 5))) + Trend = 1;//上升趋势 + else if(minus > (Cnt-(Cnt/ 5))) + Trend = -1;//下降趋势 + + return Trend;//总趋势 +} +/***************************************************************************************** +* 函数名称: Waveform_Up +* 功能描述: 找出一段波形的波峰值 + dCnt, 波形数据长度 + pCnt, 要查找波峰数 + vlue, 返回的波峰值 +* 返 回 值: true或false +*****************************************************************************************/ +void Waveform_Up(int32_t *Data, uint8_t dCnt, uint8_t pCnt, int32_t *vlue) +{ + uint8_t peak[pCnt]; + for(uint8_t i = 0, j = 0; i < dCnt; i++)//找出峰值地址 + { + if(Data[i] < Data[i + 1] && Data[i + 1] > Data[i + 2]) + { + peak[j++] = i; + } + if(j == pCnt) + break; + } + for(uint8_t i = 0; i < pCnt; i++) + { + vlue[i] = Data[peak[i]]; + } +} +/***************************************************************************************** +* 函数名称: Waveform_Down +* 功能描述: 找出一段波形的波谷值 + dCnt, 波形数据长度 + pCnt, 要查找波谷数 + vlue, 返回的波谷值 +* 返 回 值: true或false +*****************************************************************************************/ +void Waveform_Down(int32_t *Data, uint8_t dCnt, uint8_t pCnt, int32_t *vlue) +{ + uint8_t peak[pCnt]; + for(uint8_t i = 0, j = 0; i < dCnt; i++)//找出峰值地址 + { + if(Data[i] > Data[i + 1] && Data[i + 1] < Data[i + 2]) + { + peak[j++] = i; + } + if(j == pCnt) + break; + } + for(uint8_t i = 0; i < pCnt; i++) + { + vlue[i] = Data[peak[i]]; + } +} +/***************************************************************************************** +* 函数名称: count_most_greater +* 功能描述: 判断数组中的值是否大部分大于 target +* 参 数: arr, + size, + target, +* 返 回 值: true或false +*****************************************************************************************/ +bool count_most_greater(int32_t *arr, uint8_t size, int32_t target) +{ + uint8_t cnt = 0; + for (int i = 0; i < size; i++) { + if (arr[i] < target) + cnt++; + if(cnt > (size - (size / 5))) + return false; + } + return true; +} +/***************************************************************************************** +* 函数名称: count_greater +* 功能描述: 判断数组中的值是否全部大于 target +* 参 数: arr, + size, + target, +* 返 回 值: true或false +*****************************************************************************************/ +bool count_greater(int32_t *arr, uint8_t size, int32_t target) +{ + for (int i = 0; i < size; i++) { + if (arr[i] < target) + return false; + } + return true; +} +/***************************************************************************************** +* 函数名称: count_smaller +* 功能描述: 判断数组中的值是否全部小于 target +* 参 数: arr, + size, + target, +* 返 回 值: true或false +*****************************************************************************************/ +bool count_smaller(int32_t *arr, uint8_t size, int32_t target) +{ + for (int i = 0; i < size; i++) { + if (arr[i] > target) + return false; + } + return true; +} + +/***************************************************************************************** +* 函数名称: CRC_Modbus +* 功能描述: CRC16计算函数 +* 参 数: wBase, 多项式 + Para，校验数据入口 + Data, 校验数据长度入口 +* 返 回 值: crc16校验值 +*****************************************************************************************/ +uint16_t CRC_Modbus(uint16_t wBase, uint8_t *para, uint16_t length) +{ + uint16_t crc = 0xffff; + + uint16_t index,i; + + for(index = 0 ; index < length;index++) { + crc ^= para[index]; + for(i = 0; i < 8; i++) { + if(crc & 1) { + crc >>= 1; + crc ^= wBase; + } + else + crc >>= 1; + } + } + return crc; +} + +/***************************************************************************************** +* 函数名称: CRC_Sum +* 功能描述: 从第二个字节开始，求和取反 +* 参 数: _pbuff，校验数据入口 + _cmdLen，校验数据长度入口 +* 返 回 值: cmd_sum，校验值(一个字节) +*****************************************************************************************/ +uint8_t CRC_Sum(uint8_t *_pbuff, uint16_t _cmdLen) +{ + uint8_t cmd_sum=0; + uint16_t i; + + for(i=1;i<_cmdLen;i++)//从1开始，跳过第一个字节 + { + cmd_sum += _pbuff[i]; + } + cmd_sum = (~cmd_sum); + + return cmd_sum; +} +/***************************************************************************************** +* 函数名称: isAllZero +* 功能描述: 判断一个数组的值是否全部为0 +* 参 数: arr，数组 + size，长度 +* 返 回 值: true或false +*****************************************************************************************/ +bool isAllZero(uint8_t *arr, int size) +{ + for (int i = 0; i < size; i++) { + if (arr[i] != 0) { + return false; // 如果数组中有一个元素不为0，则返回false + } + } + return true; // 遍历完数组后，若所有元素都为0，则返回true +} + +/***************************************************************************************** +* 函数名称: HexToAscii +* 功能描述: 16进制转ASCII码 +* 参 数: HexData，16进制数组 + ASCData，ASCII码 + sLen，数据长度 +* 返 回 值: true或false +*****************************************************************************************/ +void HexToAscii(uint8_t *HexData, char *ASCData, uint8_t sLen) +{ + uint8_t temp; + + for(int i = 0; i < sLen; i++) { + temp = (HexData[i] >> 4) & 0x0f; + if(temp < 10) + temp += '0'; + else + temp = (temp - 10) + 'A'; + + ASCData[i * 2] = temp; + + temp = HexData[i] & 0x0f; + if(temp < 10) + temp += '0'; + else + temp = (temp - 10) + 'A'; + + ASCData[i * 2 + 1] = temp; + } + ASCData[sLen * 2] = '\r'; + ASCData[sLen * 2 + 1] = '\n'; + ASCData[sLen * 2 + 2] = 0; +} + + diff --git a/source/src/SGCP.c b/source/src/SGCP.c new file mode 100644 index 0000000..e0240f8 --- /dev/null +++ b/source/src/SGCP.c @@ -0,0 +1,2227 @@ +#include "SGCP.h" +#include "main.h" +#include "UartDebug.h" +#include "Update.h" +#include "sx127x.h" +#include "Algorithm.h" + +/*烧录时配置项 +IROM1起始地址 0x00 0x20000 +IROM1串口升级地址 0x2A00 0x1D600 +串口升级打开USE_BOOTLOADER和点s文件中的LDR R2, =new_vect_table ;升级时打开 +*/ + +//09 00 01 00 00 00 +uint8_t LocalMAC[6] = {LocalType & 0xFF, (LocalType >> 8) & 0xFF, CommWay, (AddNumber >> 16) & 0xFF, (AddNumber >> 8) & 0xFF, AddNumber & 0xFF}; //本机MAC地址 +uint8_t GatewayMAC[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; //网关MAC地址，注册时全为0 +uint8_t LocalDataPack[LocalDataLen]; //本机数据包 + + +SGCP_t SGCP; + +/** + ******************************************************************************* + ** \brief 设备数据信息获取 + ** + ** \param Devtype 设备类型 + ** + ** \param PayLoad 数据体 + ** + ** \retval Len 数据长度 + ******************************************************************************/ +static uint8_t DevGetDataMess(DEVICE_TYPE_M Devtype, uint8_t *PayLoad) +{ + uint8_t Len; + switch(Devtype) + { + case NUL: break; + case FORCE_6D: break; + case OSMOTIC_PRESSURE: break; + case ELASTIC_WAVEGUIDE: break; + case DIELECTRIC_MASS: break; + case _0x0005:break; + case CONT_DEFOR_3D:{ + if(PayLoad == NULL) + memset(&SGCP.DevData.ContDefor3D, 0x00, sizeof(SGCP.DevData.ContDefor3D)); + else + memcpy(&SGCP.DevData.ContDefor3D, &PayLoad[0], sizeof(SGCP.DevData.ContDefor3D)); + DBG_LOG("\tDevice Type:%04X, PitchSkew:%06d, RollSkew:%06d, YawSkew:%06d\r\n", + Devtype, + (SGCP.DevData.ContDefor3D.PitchAngle), + (SGCP.DevData.ContDefor3D.RollAngle), + (SGCP.DevData.ContDefor3D.YawAngle)); + Len = sizeof(SGCP.DevData.ContDefor3D); + break;} + case COMM_UNIT: { + DBG_LOG("\tDevice Type:%04X\r\n",Devtype); + Len = sizeof(SGCP.DevData.CommUnit); + break;} + case FORCE_3D:{ + if(PayLoad == NULL) + memset(&SGCP.DevData.Force3D, 0x00, sizeof(SGCP.DevData.Force3D)); + else + memcpy(&SGCP.DevData.Force3D, &PayLoad[0], sizeof(SGCP.DevData.Force3D)); + DBG_LOG("\tDevice Type:%04X, PitchSkew:%06d, RollSkew:%06d, YawSkew:%06d, Strain1:%09d, Strain2:%09d, Strain3:%09d\r\n", + Devtype, + (SGCP.DevData.Force3D.PitchAngle), + (SGCP.DevData.Force3D.RollAngle), + (SGCP.DevData.Force3D.YawAngle), + (SGCP.DevData.Force3D.Strain1), + (SGCP.DevData.Force3D.Strain2), + (SGCP.DevData.Force3D.Strain3)); + Len = sizeof(SGCP.DevData.Force3D); + break;} + case LASER_TRACING: { + if(PayLoad == NULL) + memset(&SGCP.DevData.LaserTracing, 0x00, sizeof(SGCP.DevData.LaserTracing)); + else + + memcpy(&SGCP.DevData.LaserTracing, &PayLoad[0], sizeof(SGCP.DevData.LaserTracing)); + DBG_LOG("\tBatLevel:%03d, RSSI:%02d, Nsr:%02d\r\n",SGCP.DevData.LaserTracing.MasterDev.BatLevel, SGCP.DevData.LaserTracing.MasterDev.RSSI,SGCP.DevData.LaserTracing.MasterDev.Nsr); + DBG_LOG("\tDevice Type:%04X, PitchSkew:%04d, RollSkew:%04d, YawSkew:%04d\r\n", + Devtype, + (SGCP.DevData.LaserTracing.PitchAngle), + (SGCP.DevData.LaserTracing.RollAngle), + (SGCP.DevData.LaserTracing.YawAngle)); + Len = sizeof(SGCP.DevData.LaserTracing); + break;} + case _0x000A: break; + case _0x000B: break; + case _0x000C: break; + case MULTI_PARAMETER_FUSION: break; + case CRACK_DETECTION: break; + case _0x000F: break; + case ATTITUDE_MONITOR: break; + case LASER_DISPLACE: break; + case REBAR_STRESS: break; + case ANCHOR_ROD_STRESS: break; + case SURFACE_STRESS: break; + case PRESSURE: break; + case MICROWAVE_DISPLACE: break; + } + + return Len; +} +/** + ******************************************************************************* + ** \brief 子设备校准指令 + ** + ** \param [in] Addr 子设备地址 + ** + ** \param [in] PayLoad 数据体 + ** + ** \retval 无 + ******************************************************************************/ +static void ToSDCali(uint8_t Addr) +{ + uint8_t Pack[50]; + uint16_t Crc16; + uint8_t len; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)Pack; + + SFHeader->Header = 0x7C; + SFHeader->Addr = Addr; + SFHeader->Cmd = MDTOSD_CMD_CALI; + SFHeader->PayloadLen = 0; + + len = sizeof(SubsetFrameHeader_t); + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, len); + Pack[len++] = Crc16 & 0x00ff; + Pack[len++] = (Crc16 >> 8) & 0x00ff; + + SGCP.SDRS485Rx.sCmdMDToSD = (MDTOSD_CMD_M)SFHeader->Cmd; + Uart1SendArray(Pack, len); +} +/** + ******************************************************************************* + ** \brief 子设备读取数据指令 + ** + ** \param [in] Addr 子设备地址 + ** + ** \param [in] PayLoad 数据体 + ** + ** \retval 无 + ******************************************************************************/ +static void ToSDReadData(uint8_t Addr) +{ + uint8_t Pack[50]; + uint16_t Crc16; + uint8_t len; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)Pack; + + SFHeader->Header = 0x7C; + SFHeader->Addr = Addr; + SFHeader->Cmd = MDTOSD_CMD_READ_DATA; + SFHeader->PayloadLen = 0; + + len = sizeof(SubsetFrameHeader_t); + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, len); + Pack[len++] = Crc16 & 0x00ff; + Pack[len++] = (Crc16 >> 8) & 0x00ff; + + SGCP.SDRS485Rx.sCmdMDToSD = (MDTOSD_CMD_M)SFHeader->Cmd; + Uart1SendArray(Pack, len); +} +/** + ******************************************************************************* + ** \brief 子设备查询指令 + ** + ** \param [in] Addr 子设备485地址 + ** + ** \param [in] PayLoad 数据体 + ** + ** \retval 无 + ******************************************************************************/ +static void ToSDInquire(uint8_t Addr) +{ + uint8_t Pack[50]; + uint16_t Crc16; + uint8_t len; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)Pack; + + SFHeader->Header = 0x7C; + SFHeader->Addr = Addr; + SFHeader->Cmd = MDTOSD_CMD_INQUIRE; + SFHeader->PayloadLen = 0; + + len = sizeof(SubsetFrameHeader_t); + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, len); + Pack[len++] = Crc16 & 0x00ff; + Pack[len++] = (Crc16 >> 8) & 0x00ff; + + SGCP.SDRS485Rx.sCmdMDToSD = (MDTOSD_CMD_M)SFHeader->Cmd; + Uart1SendArray(Pack, len); +} +/** + ******************************************************************************* + ** \brief 子设备设置采集时间间隔指令 + ** + ** \param [in] Addr 子设备地址 + ** + ** \param [in] CollTime 采集时间间隔 + ** + ** \retval 无 + ******************************************************************************/ +static void ToSDSetColTime(uint8_t Addr, uint16_t CollectInterval) +{ + uint8_t Pack[50]; + uint16_t Crc16; + uint8_t len; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)Pack; + + SFHeader->Header = 0x7C; + SFHeader->Addr = Addr; + SFHeader->Cmd = MDTOSD_CMD_SET_COL_TIME; + SFHeader->PayloadLen = sizeof(CollectInterval); + + len = sizeof(SubsetFrameHeader_t); + + Pack[len++] = CollectInterval & 0xFF; + Pack[len++] = (CollectInterval >> 8) & 0xFF; + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, len); + Pack[len++] = Crc16 & 0x00ff; + Pack[len++] = (Crc16 >> 8) & 0x00ff; + + SGCP.SDRS485Rx.sCmdMDToSD = (MDTOSD_CMD_M)SFHeader->Cmd; + Uart1SendArray(Pack, len); +} +/** + ******************************************************************************* + ** \brief 子设备时间同步指令 + ** + ** \param [in] Addr 子设备地址 + ** + ** \param [in] PayLoad 数据体 + ** + ** \retval 无 + ******************************************************************************/ +static void ToSDSyncTime(uint8_t Addr, uint32_t TimeStamp) +{ + uint8_t Pack[50]; + uint16_t Crc16; + uint8_t len; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)Pack; + + SFHeader->Header = 0x7C; + SFHeader->Addr = Addr; + SFHeader->Cmd = MDTOSD_CMD_SYNC_TIME; + SFHeader->PayloadLen = sizeof(TimeStamp); + + len = sizeof(SubsetFrameHeader_t); + + Pack[len++] = TimeStamp & 0xFF; + Pack[len++] = (TimeStamp >> 8) & 0xFF; + Pack[len++] = (TimeStamp >> 16) & 0xFF; + Pack[len++] = (TimeStamp >> 24) & 0xFF; + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, len); + Pack[len++] = Crc16 & 0x00ff; + Pack[len++] = (Crc16 >> 8) & 0x00ff; + + SGCP.SDRS485Rx.sCmdMDToSD = (MDTOSD_CMD_M)SFHeader->Cmd; + Uart1SendArray(Pack, len); +} + +/** + ******************************************************************************* + ** \brief 子设备校准回应 + ** + ** \param [in] Addr 子设备地址 + ** + ** \param [in] Ok_Err 成功失败标志位 + ** + ** \retval 无 + ******************************************************************************/ +static void ToMDCaliRes(uint8_t Addr, bool Ok_Err) +{ + uint8_t Pack[50]; + uint16_t Crc16; + uint8_t len; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)Pack; + + SFHeader->Header = 0x7C; + SFHeader->Addr = Addr; + SFHeader->Cmd = MDTOSD_CMD_CALI; + SFHeader->PayloadLen = sizeof(Ok_Err); + + len = sizeof(SubsetFrameHeader_t); + + Pack[len++] = Ok_Err; + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, len); + Pack[len++] = Crc16 & 0x00ff; + Pack[len++] = (Crc16 >> 8) & 0x00ff; + + SGCP.SDRS485Rx.sCmdMDToSD = (MDTOSD_CMD_M)SFHeader->Cmd; + LPUart0SendArray(Pack, len); +} +/** + ******************************************************************************* + ** \brief 子设备读取数据指令回应 + ** + ** \param [in] Addr 子设备地址 + ** + ** \param [in] PayLoad 数据体 + ** + ** \retval 无 + ******************************************************************************/ +static void ToMDReadDataRes(uint8_t Addr, uint8_t *PayLoad, uint8_t Len) +{ + uint8_t Pack[50]; + uint16_t Crc16; + uint8_t len; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)Pack; + + SFHeader->Header = 0x7C; + SFHeader->Addr = Addr; + SFHeader->Cmd = MDTOSD_CMD_READ_DATA; + SFHeader->PayloadLen = Len; + + len = sizeof(SubsetFrameHeader_t); + + for(uint8_t i = 0; i < SFHeader->PayloadLen; i++) + { + Pack[len++] = PayLoad[i]; + } + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, len); + Pack[len++] = Crc16 & 0x00ff; + Pack[len++] = (Crc16 >> 8) & 0x00ff; + + SGCP.SDRS485Rx.sCmdMDToSD = (MDTOSD_CMD_M)SFHeader->Cmd; + LPUart0SendArray(Pack, len); +} +/** + ******************************************************************************* + ** \brief 子设备查询指令回应 + ** + ** \param [in] Addr 子设备485地址 + ** + ** \param [in] PayLoad 数据体 + ** + ** \retval 无 + ******************************************************************************/ +static void ToMDInquireRes(uint8_t Addr) +{ + uint8_t Pack[50]; + uint16_t Crc16; + uint8_t len; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)Pack; + + SFHeader->Header = 0x7C; + SFHeader->Addr = Addr; + SFHeader->Cmd = MDTOSD_CMD_INQUIRE; + SFHeader->PayloadLen = 6; + + len = sizeof(SubsetFrameHeader_t); + + for(uint8_t i = 0; i < SFHeader->PayloadLen; i++) + { + Pack[len++] = LocalMAC[i]; + } + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, len); + Pack[len++] = Crc16 & 0x00ff; + Pack[len++] = (Crc16 >> 8) & 0x00ff; + + SGCP.SDRS485Rx.sCmdMDToSD = (MDTOSD_CMD_M)SFHeader->Cmd; + LPUart0SendArray(Pack, len); +} +/** + ******************************************************************************* + ** \brief 子设备设置采集时间间隔指令回应 + ** + ** \param [in] Addr 子设备地址 + ** + ** \param [in] Ok_Err 成功失败标志位 + ** + ** \retval 无 + ******************************************************************************/ +static void ToMDSetColTimeRes(uint8_t Addr, bool Ok_Err) +{ + uint8_t Pack[50]; + uint16_t Crc16; + uint8_t len; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)Pack; + + SFHeader->Header = 0x7C; + SFHeader->Addr = Addr; + SFHeader->Cmd = MDTOSD_CMD_SET_COL_TIME; + SFHeader->PayloadLen = sizeof(Ok_Err); + + len = sizeof(SubsetFrameHeader_t); + + Pack[len++] = Ok_Err; + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, len); + Pack[len++] = Crc16 & 0x00ff; + Pack[len++] = (Crc16 >> 8) & 0x00ff; + + SGCP.SDRS485Rx.sCmdMDToSD = (MDTOSD_CMD_M)SFHeader->Cmd; + LPUart0SendArray(Pack, len); +} +/** + ******************************************************************************* + ** \brief 子设备时间同步指令回应 + ** + ** \param [in] Addr 子设备地址 + ** + ** \param [in] Ok_Err 成功失败标志位 + ** + ** \retval 无 + ******************************************************************************/ +static void ToMDSyncTimeRes(uint8_t Addr, bool Ok_Err) +{ + uint8_t Pack[50]; + uint16_t Crc16; + uint8_t len; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)Pack; + + SFHeader->Header = 0x7C; + SFHeader->Addr = Addr; + SFHeader->Cmd = MDTOSD_CMD_SYNC_TIME; + SFHeader->PayloadLen = sizeof(Ok_Err); + + len = sizeof(SubsetFrameHeader_t); + + Pack[len++] = Ok_Err; + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, len); + Pack[len++] = Crc16 & 0x00ff; + Pack[len++] = (Crc16 >> 8) & 0x00ff; + + SGCP.SDRS485Rx.sCmdMDToSD = (MDTOSD_CMD_M)SFHeader->Cmd; + LPUart0SendArray(Pack, len); +} + + +/** + ******************************************************************************* + ** \brief 向网关申请注册 + ** + ** \param PayLoad 数据体 + ** + ** \retval 无 + ******************************************************************************/ +static void ToGWDevLogin(void) +{ + uint8_t Pack[512]; + uint16_t Crc16, Len; + + GatewayFrameHeader GFHeader = (GatewayFrameHeader)Pack; + + GFHeader->Header = 0x7B; + memset(&GFHeader->GWAddr[0], 0x00, sizeof(GFHeader->GWAddr)); + memcpy(&GFHeader->MDAddr[0], &LocalMAC[0], sizeof(GFHeader->MDAddr)); + GFHeader->Cmd = GWTOMD_CMD_LOGIN; + GFHeader->PayloadLen = (SGCP.DeviceN * 6 + 1); + + Len = sizeof(GatewayFrameHeader_t); + + Pack[Len++] = SGCP.DeviceN; + for(uint8_t i = 0; i < SGCP.DeviceN; i++) + { + for(uint8_t j = 0; j < 6; j++) + { + Pack[Len++] = SGCP.DeviceMAC[i][j]; + } + } + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, Len); + Pack[Len++] = Crc16 & 0x00ff; + Pack[Len++] = (Crc16 >> 8) & 0x00ff; + + SGCP.GWRS485Rx.sCmdMDToGW = (GWTOMD_CMD_M)GFHeader->Cmd; +#if(SGCP_SELECT == 1 || SGCP_SELECT == 2) + Sx1276LoRaSendBuffer(Pack, Len); +#endif +#if(SGCP_SELECT == 3) + LPUart0SendArray(Pack, Len); +#endif +} +/** + ******************************************************************************* + ** \brief 网关校准指令回应 + ** + ** \param Ok_Err 成功失败标志位 + ** + ** \retval 无 + ******************************************************************************/ +static void ToGWCaliRes(bool Ok_Err) +{ + uint8_t Pack[256]; + uint16_t Crc16; + uint8_t Len; + + GatewayFrameHeader GFHeader = (GatewayFrameHeader)Pack; + + GFHeader->Header = 0x7B; + memcpy(&GFHeader->GWAddr[0], &GatewayMAC[0], sizeof(GFHeader->GWAddr)); + memcpy(&GFHeader->MDAddr[0], &LocalMAC[0], sizeof(GFHeader->MDAddr)); + GFHeader->Cmd = GWTOMD_CMD_CALI; + GFHeader->PayloadLen = sizeof(Ok_Err); + + Len = sizeof(GatewayFrameHeader_t); + + Pack[Len++] = Ok_Err; + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, Len); + Pack[Len++] = Crc16 & 0x00ff; + Pack[Len++] = (Crc16 >> 8) & 0x00ff; + +SGCP.GWRS485Rx.sCmdMDToGW = (GWTOMD_CMD_M)GFHeader->Cmd; +#if(SGCP_SELECT == 1 || SGCP_SELECT == 2) + Sx1276LoRaSendBuffer(Pack, Len); +#endif +#if(SGCP_SELECT == 3) + LPUart0SendArray(Pack, Len); +#endif +} +/** + ******************************************************************************* + ** \brief 网关读取数据指令回应 + ** + ** \param PayLoad 数据体 + ** + ** \retval 无 + ******************************************************************************/ +static void ToGWReadDataRes(uint8_t *PayLoad) +{ + uint8_t Pack[512]; + uint16_t Crc16, Len; + + GatewayFrameHeader GFHeader = (GatewayFrameHeader)Pack; + + GFHeader->Header = 0x7B; + memcpy(&GFHeader->GWAddr[0], &GatewayMAC[0], sizeof(GFHeader->GWAddr)); + memcpy(&GFHeader->MDAddr[0], &LocalMAC[0], sizeof(GFHeader->MDAddr)); + GFHeader->Cmd = GWTOMD_CMD_READ_UPLOAD_SENSOR; + GFHeader->PayloadLen = SGCP.DeviceDataLen; + + Len = sizeof(GatewayFrameHeader_t); + + for(uint8_t i = 0; i < GFHeader->PayloadLen; i++) + { + Pack[Len++] = PayLoad[i]; + } + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, Len); + Pack[Len++] = Crc16 & 0x00ff; + Pack[Len++] = (Crc16 >> 8) & 0x00ff; + +SGCP.GWRS485Rx.sCmdMDToGW = (GWTOMD_CMD_M)GFHeader->Cmd; +#if(SGCP_SELECT == 1 || SGCP_SELECT == 2) + Sx1276LoRaSendBuffer(Pack, Len); +#endif +#if(SGCP_SELECT == 3) + LPUart0SendArray(Pack, Len); +#endif +} + +/** + ******************************************************************************* + ** \brief 网关设置采集时间间隔指令回应 + ** + ** \param Ok_Err 成功失败标志位 + ** + ** \retval 无 + ******************************************************************************/ +static void ToGWSetColTimeRes(bool Ok_Err) +{ + uint8_t Pack[256]; + uint16_t Crc16; + uint8_t Len; + + GatewayFrameHeader GFHeader = (GatewayFrameHeader)Pack; + + GFHeader->Header = 0x7B; + memcpy(&GFHeader->GWAddr[0], &GatewayMAC[0], sizeof(GFHeader->GWAddr)); + memcpy(&GFHeader->MDAddr[0], &LocalMAC[0], sizeof(GFHeader->MDAddr)); + GFHeader->Cmd = GWTOMD_CMD_SET_COL_TIME; + GFHeader->PayloadLen = sizeof(Ok_Err); + + Len = sizeof(GatewayFrameHeader_t); + + Pack[Len++] = Ok_Err; + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, Len); + Pack[Len++] = Crc16 & 0x00ff; + Pack[Len++] = (Crc16 >> 8) & 0x00ff; + +SGCP.GWRS485Rx.sCmdMDToGW = (GWTOMD_CMD_M)GFHeader->Cmd; +#if(SGCP_SELECT == 1 || SGCP_SELECT == 2) + Sx1276LoRaSendBuffer(Pack, Len); +#endif +#if(SGCP_SELECT == 3) + LPUart0SendArray(Pack, Len); +#endif +} + +/** + ******************************************************************************* + ** \brief 网关时间同步指令回应 + ** + ** \param Ok_Err 成功失败标志位 + ** + ** \retval 无 + ******************************************************************************/ +static void ToGWSyncTimeRes(bool Ok_Err) +{ + uint8_t Pack[256]; + uint16_t Crc16; + uint8_t Len; + + GatewayFrameHeader GFHeader = (GatewayFrameHeader)Pack; + + GFHeader->Header = 0x7B; + memcpy(&GFHeader->GWAddr[0], &GatewayMAC[0], sizeof(GFHeader->GWAddr)); + memcpy(&GFHeader->MDAddr[0], &LocalMAC[0], sizeof(GFHeader->MDAddr)); + GFHeader->Cmd = GWTOMD_CMD_SYNC_TIME; + GFHeader->PayloadLen = sizeof(Ok_Err); + + Len = sizeof(GatewayFrameHeader_t); + + Pack[Len++] = Ok_Err; + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, Len); + Pack[Len++] = Crc16 & 0x00ff; + Pack[Len++] = (Crc16 >> 8) & 0x00ff; + +SGCP.GWRS485Rx.sCmdMDToGW = (GWTOMD_CMD_M)GFHeader->Cmd; +#if(SGCP_SELECT == 1 || SGCP_SELECT == 2) + Sx1276LoRaSendBuffer(Pack, Len); +#endif +#if(SGCP_SELECT == 3) + LPUart0SendArray(Pack, Len); +#endif +} +/** + ******************************************************************************* + ** \brief 内部指令修改RS485地址回应 + ** + ** \param PayLoad 数据体 + ** + ** \retval 无 + ******************************************************************************/ +static void Alter485AddrRes(uint8_t *MAC, bool Ok_Err) +{ + uint8_t Pack[50]; + uint16_t Crc16; + uint8_t len; + + InsideFrameHeader IFHeader = (InsideFrameHeader)Pack; + + IFHeader->Header = 0x7D; + memcpy(&IFHeader->MAC[0], &MAC[0], sizeof(IFHeader->MAC)); + IFHeader->Cmd = INSIDE_CMD_ALTER_485ADDR; + IFHeader->PayloadLen = sizeof(Ok_Err); + + len = sizeof(InsideFrameHeader_t); + + Pack[len++] = Ok_Err; + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, len); + Pack[len++] = Crc16 & 0x00ff; + Pack[len++] = (Crc16 >> 8) & 0x00ff; + + LPUart0SendArray(Pack, len); +} +/** + ******************************************************************************* + ** \brief 主设备接收子设备数据处理 + ** + ** \param 无 + ** + ** \retval 无 + ******************************************************************************/ +static void SubsetRevHandler(void) +{ + uint16_t crc16, Check; + uint8_t *PayLoad; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)SGCP.SubsetBuff; + + crc16 = (SGCP.SubsetBuff[SGCP.SubsetBuffLen - 1] << 8) | SGCP.SubsetBuff[SGCP.SubsetBuffLen - 2]; + Check = CRC_Modbus(CRC16_BASE, SGCP.SubsetBuff, SGCP.SubsetBuffLen - 2); + + if(crc16 != Check){ + DBG_LOG("Subset CRC Err...\r\n"); + return; + } + + + SGCP.SDRS485Rx.rCmdSDToMD = (MDTOSD_CMD_M)SFHeader->Cmd; + PayLoad = &SGCP.SubsetBuff[sizeof(SubsetFrameHeader_t)]; + + switch(SGCP.SDRS485Rx.rCmdSDToMD) { + case MDTOSD_CMD_CALI:{ + SGCP.SubsetCaliOk = PayLoad[0]; + break;} + + case MDTOSD_CMD_READ_DATA:{ + memcpy(&SGCP.DeviceDataBuff[SGCP.DeviceDataLen], PayLoad, SGCP.SDRS485Rx.rPayLen); + SGCP.SubsetReadDataOk = true; + break;} + + case MDTOSD_CMD_INQUIRE:{ + memcpy(&SGCP.DeviceMAC[SGCP.DeviceN], PayLoad, sizeof(SGCP.DeviceMAC[SGCP.DeviceN]));//子设备MAC + SGCP.SubsetMACOk = true; + break;} + + case MDTOSD_CMD_SET_COL_TIME:{ + SGCP.CollTimeSetOk = PayLoad[0]; + break;} + + case MDTOSD_CMD_SYNC_TIME:{ + SGCP.SyncTimeOk = PayLoad[0]; + break;} + } +} +/** + ******************************************************************************* + ** \brief 子设备接收主设备数据处理 + ** + ** \param 无 + ** + ** \retval 无 + ******************************************************************************/ +static void MasRevHandler(void) +{ + uint16_t crc16, Check; + uint8_t *PayLoad; + + SubsetFrameHeader SFHeader = (SubsetFrameHeader)SGCP.SubsetBuff; + + crc16 = (SGCP.SubsetBuff[SGCP.SubsetBuffLen - 1] << 8) | SGCP.SubsetBuff[SGCP.SubsetBuffLen - 2]; + Check = CRC_Modbus(CRC16_BASE, SGCP.SubsetBuff, SGCP.SubsetBuffLen - 2); + + if(crc16 != Check){ + DBG_LOG("Master CRC Err...\r\n"); + return; + } + + if(SFHeader->Addr != App.Para.RS485Addr) + { + if(SFHeader->Addr != 0x00) + { + DBG_LOG("Master RS485Addr Err...\r\n"); + return; + } + else + { + SGCP.BroadCmd = true; + } + } + + SGCP.SDRS485Rx.rCmdSDToMD = (MDTOSD_CMD_M)SFHeader->Cmd; + PayLoad = &SGCP.SubsetBuff[sizeof(SubsetFrameHeader_t)]; + + switch(SGCP.SDRS485Rx.rCmdSDToMD) { + case MDTOSD_CMD_CALI:{ + if(SGCP.MasStatus == MAS_STATUS_IDLE) + { + SGCP.SubsetCaliOk = true; + SGCP.MasStatus = MAS_STATUS_CALI; + } + break;} + + case MDTOSD_CMD_READ_DATA:{ + if(SGCP.BroadCmd == true) + { + SGCP.BroadCmd = false; + return; + } + if(SGCP.MasStatus == MAS_STATUS_IDLE) + { + SGCP.MasStatus = MAS_STATUS_READ_SENSOR; + } + break;} + + case MDTOSD_CMD_INQUIRE:{ + if(SGCP.BroadCmd == true) + { + SGCP.BroadCmd = false; + return; + } + if(SGCP.MasStatus == MAS_STATUS_IDLE) + { + SGCP.MasStatus = MAS_STATUS_DEVICE_INQUIRE; + } + break;} + + case MDTOSD_CMD_SET_COL_TIME:{ + uint32_t temp; + temp = PayLoad[0]; + temp |= (PayLoad[1] << 8); + if(temp < 1 || temp > 7200) + { + DBG_LOG("CollectInterval Err\r\n"); + return; + } + else + { + App.Para.Layout.CollectTime = temp; + SAVE_APP_PARA((uint32_t *)&App.Para); + if(App.Para.Layout.CollectTime >= 30) + RTCInit(30);//定时采集时间重新初始化 + else + RTCInit(App.Para.Layout.CollectTime);//定时采集时间重新初始化 + if(SGCP.MasStatus == MAS_STATUS_IDLE) + { + SGCP.MasStatus = MAS_STATUS_SET_COL_TIME; + } + } + break;} + + case MDTOSD_CMD_SYNC_TIME:{ + uint32_t temp; + temp = PayLoad[0]; + temp |= (PayLoad[1] << 8); + temp |= (PayLoad[2] << 16); + temp |= (PayLoad[3] << 24); + if(temp < 1701173083 || temp > 4102372799) + { + DBG_LOG("TimeStamp Err\r\n"); + return; + } + else + { + App.Para.Layout.TimeStamp = temp; + SAVE_APP_PARA((uint32_t *)&App.Para); + TimeSync(App.Para.Layout.TimeStamp); //设置时间 + if(SGCP.MasStatus == MAS_STATUS_IDLE) + { + SGCP.MasStatus = MAS_STATUS_SYNC_TIME; + } + } + break;} + } +} +/** + ******************************************************************************* + ** \brief 主设备接收网关数据处理 + ** + ** \param 无 + ** + ** \retval 无 + ******************************************************************************/ +static void GWRevHandler(void) +{ + uint16_t crc16,Check; + uint8_t *PayLoad; + uint16_t PayLoadLen; + + GatewayFrameHeader GFHeader = (GatewayFrameHeader)SGCP.GatewayBuff; + + crc16 = (SGCP.GatewayBuff[SGCP.GatewayBuffLen - 1] << 8) | SGCP.GatewayBuff[SGCP.GatewayBuffLen - 2]; + Check = CRC_Modbus(CRC16_BASE, SGCP.GatewayBuff, SGCP.GatewayBuffLen - 2); + + if(crc16 != Check){ + DBG_LOG("Gateway CRC Err...\r\n"); + return; + } + + if(memcmp(GFHeader->MDAddr, LocalMAC, sizeof(GFHeader->MDAddr)) != false) + { + if(isAllZero(GFHeader->MDAddr, sizeof(GFHeader->MDAddr)) != true) + { + DBG_LOG("Gateway Master Device MAC Err...\r\n"); + return; + } + else + { + SGCP.BroadCmd = true; + } + } + + + SGCP.GWRS485Rx.rCmdGWToMD = (GWTOMD_CMD_M)GFHeader->Cmd; + PayLoad = &SGCP.GatewayBuff[sizeof(GatewayFrameHeader_t)]; + LayoutPara LPay = (LayoutPara)PayLoad; + PayLoadLen = GFHeader->PayloadLen; + + switch(SGCP.GWRS485Rx.rCmdGWToMD) { + case GWTOMD_CMD_LOGIN:{ + SGCP.LoginOk = PayLoad[0]; + if(SGCP.LoginOk == true) + { + memcpy(GatewayMAC, GFHeader->GWAddr, sizeof(GatewayMAC)); + } + break;} + + case GWTOMD_CMD_CALI:{ + if(SGCP.LoginOk == true) + { + SGCP.MasterCaliOk = true; + if(SGCP.GWStatus == GW_STATUS_WAIT_UPLOAD) + { + SGCP.UploadOk = true; + SGCP.NextGWStatus = GW_STATUS_CALI; + } + else + SGCP.GWStatus = GW_STATUS_CALI; + } + break;} + + case GWTOMD_CMD_READ_UPLOAD_SENSOR:{ + if(SGCP.LoginOk == true) + { + if(WORK_MODE == 0) + SGCP.GWStatus = GW_STATUS_READ_SENSOR; + else if(WORK_MODE == 1) + { + if(PayLoadLen == 4) + { + App.Para.Layout.TimeStamp = LPay->TimeStamp; + + int8_t TimeDiff;//时间差 + int RTCTimes = TimeTs(); + TimeDiff = App.Para.Layout.TimeStamp - RTCTimes; + if(TimeDiff > 1 || TimeDiff < -1) + { + TimeSync(App.Para.Layout.TimeStamp); //向通讯单元RTC时间寄存器写入时间网关下发的时间 + } + SGCP.UploadOk = true; + SGCP.NextGWStatus = GW_STATUS_IDLE; + } + else if(PayLoadLen == 10) + { + App.Para.Layout.CollectTime = LPay->CollectTime/30; + App.Para.Layout.ReportInterval = LPay->ReportInterval * 2; + App.Para.Layout.ERInterval = LPay->ERInterval * 2; + App.Para.Layout.ERTime = LPay->ERTime * 2; + App.Para.Layout.TimeStamp = LPay->TimeStamp; + + DBG_LOG("The parameters have been updated. CI:%ds, RI:%dmin, EI:%dmin, ET:%dmin\r\n", + LPay->CollectTime, + LPay->ReportInterval, + LPay->ERInterval, + LPay->ERTime); + + int8_t TimeDiff;//时间差 + int RTCTimes = TimeTs(); + TimeDiff = App.Para.Layout.TimeStamp - RTCTimes; + if(TimeDiff > 1 || TimeDiff < -1) + { + TimeSync(App.Para.Layout.TimeStamp); //向通讯单元RTC时间寄存器写入时间网关下发的时间 + } + SGCP.UploadOk = true; + SGCP.NextGWStatus = GW_STATUS_UPLOAD_SENSOR; + } + } + } + break;} + + case GWTOMD_CMD_SET_COL_TIME:{ + if(SGCP.LoginOk == true) + { + uint16_t temp; + temp = PayLoad[0]; + temp |= (PayLoad[1] << 8); + if(temp < 1 || temp > 7200) + { + DBG_LOG("CollectInterval Err\r\n"); + if(SGCP.GWStatus == GW_STATUS_WAIT_UPLOAD) + { + SGCP.UploadOk = true; + SGCP.NextGWStatus = GW_STATUS_IDLE; + } + return; + } + else + { + if(SGCP.GWStatus == GW_STATUS_WAIT_UPLOAD) + { + SGCP.UploadOk = true; + SGCP.NextGWStatus = GW_STATUS_SET_COL_TIME; + } + else + { + SGCP.GWStatus = GW_STATUS_SET_COL_TIME; + } + App.Para.Layout.CollectTime = temp; + SAVE_APP_PARA((uint32_t *)&App.Para); + } + } + break;} + + case GWTOMD_CMD_SYNC_TIME:{ + if(SGCP.LoginOk == true) + { + uint32_t temp; + temp = PayLoad[0]; + temp |= (PayLoad[1] << 8); + temp |= (PayLoad[2] << 16); + temp |= (PayLoad[3] << 24); + if(temp < 1701173083 || temp > 4102372799) + { + DBG_LOG("TimeStamp Err\r\n"); + if(SGCP.GWStatus == GW_STATUS_WAIT_UPLOAD) + { + SGCP.UploadOk = true; + SGCP.NextGWStatus = GW_STATUS_IDLE; + } + return; + } + else + { + if(SGCP.GWStatus == GW_STATUS_WAIT_UPLOAD) + { + SGCP.UploadOk = true; + SGCP.NextGWStatus = GW_STATUS_SYNC_TIME; + } + else + { + SGCP.GWStatus = GW_STATUS_SYNC_TIME; + } + App.Para.Layout.TimeStamp = temp; + SAVE_APP_PARA((uint32_t *)&App.Para); + TimeSync(App.Para.Layout.TimeStamp); //设置时间 + } + } + break;} + + case GWTOMD_CMD_SET_LASER:{ + if(SGCP.LoginOk == true) + { + int8_t temp = PayLoad[0]; + if(temp == 1) + { + LASER1_ON(); + SGCP.LaserOnOff = true; + if(SGCP.GWStatus == GW_STATUS_WAIT_UPLOAD) + { + SGCP.UploadOk = true; + SGCP.NextGWStatus = GW_STATUS_LASER_STARES; + } + else + SGCP.GWStatus = GW_STATUS_LASER_STARES; + } + else if(temp == 0) + { + LASER1_OFF(); + SGCP.LaserOnOff = false; + if(SGCP.GWStatus == GW_STATUS_WAIT_UPLOAD) + { + SGCP.UploadOk = true; + SGCP.NextGWStatus = GW_STATUS_LASER_STARES; + } + else + SGCP.GWStatus = GW_STATUS_LASER_STARES; + } + } + break;} + } + SGCP.Gateway_IRQ_Status = true; +} +/** + ******************************************************************************* + ** \brief 内部指令指令数据接收处理 + ** + ** \param 无 + ** + ** \retval 无 + ******************************************************************************/ +static void InRevHandler(void) +{ + uint16_t crc16,Check; + uint8_t *PayLoad; + + InsideFrameHeader IFHeader = (InsideFrameHeader)SGCP.InsideBuff; + + crc16 = (SGCP.InsideBuff[SGCP.InsideBuffLen - 1] << 8) | SGCP.InsideBuff[SGCP.InsideBuffLen - 2]; + Check = CRC_Modbus(CRC16_BASE, SGCP.InsideBuff, SGCP.InsideBuffLen - 2); + + if(crc16 != Check) + { + DBG_LOG("Inside CRC Err...\r\n"); + return; + } + + if(memcmp(IFHeader->MAC, LocalMAC, sizeof(IFHeader->MAC)) != false) + { + DBG_LOG("Inside MAC Err...\r\n"); + return; + } + + PayLoad = &SGCP.InsideBuff[sizeof(InsideFrameHeader_t)]; + + switch((INSIDE_CMD_M)IFHeader->Cmd) { + case INSIDE_CMD_UPDATE:{ + memcpy(SGCP.InsidePay, PayLoad, SGCP.InsidePayLen); + SGCP.InStatus = IN_STATUS_UPDATE; + break;} + + case INSIDE_CMD_ALTER_485ADDR:{ + uint8_t temp; + temp = PayLoad[0]; + if(temp > 16 || temp < 1) + { + DBG_LOG("RS485Addr Err\r\n"); + return; + } + else + { + App.Para.RS485Addr = temp; + SAVE_APP_PARA((uint32_t *)&App.Para); + if(SGCP.InStatus == IN_STATUS_IDLE) + { + SGCP.InStatus = IN_STATUS_ALTER_485ADDR; + } + } + break;} + } +} +#if (SGCP_SELECT == 0)//本机为单个主设备接多个子设备 +/** + ******************************************************************************* + ** \brief 接收子设备数据状态机 + ** + ** \param 无 + ** + ** \retval 无 + ******************************************************************************/ +void SubRevLoopHandler(void) +{ + switch(SGCP.SubStatus) + { + case SUB_STATUS_IDLE:{ + break;} + + case SUB_STATUS_BROADCAST_CALI:{ + ToSDCali(0x00); + SGCP.SubStatus = SUB_STATUS_IDLE; + break;} + + case SUB_STATUS_READMASTER_DATA:{ + DBG_LOG("<----------- Cache Updating ----------->\r\n"); + memset(SGCP.DeviceDataBuff, NULL, sizeof(SGCP.DeviceDataBuff)); + SGCP.DeviceReadDataOk = false; + SGCP.DeviceDataLen = 0; + SGCP.ReadDataAdd = 0; + #if (USE_VBAT_AD == 1) + SGCP.DevData.MasterDev.BatLevel = VBAT_Percentage; + #else + SGCP.DevData.MasterDev.BatLevel = 0x00; + #endif + #if (SGCP_SELECT == 1 || SGCP_SELECT == 2) + SX1276LoCalcRssiSnr(&SGCP.DevData.MasterDev.RSSI, &SGCP.DevData.MasterDev.Nsr); + #else + SGCP.DevData.MasterDev.RSSI = 0x00; + SGCP.DevData.MasterDev.Nsr = 0x00; + #endif + memcpy(&SGCP.DeviceDataBuff[0], &SGCP.DevData.MasterDev, sizeof(SGCP.DevData.MasterDev)); + + DBG_LOG("Master Device MAC:%02X %02X %02X %02X %02X %02X\r\n", + SGCP.DeviceMAC[SGCP.ReadDataAdd][0],SGCP.DeviceMAC[SGCP.ReadDataAdd][1],SGCP.DeviceMAC[SGCP.ReadDataAdd][2], + SGCP.DeviceMAC[SGCP.ReadDataAdd][3],SGCP.DeviceMAC[SGCP.ReadDataAdd][4],SGCP.DeviceMAC[SGCP.ReadDataAdd][5]); + DBG_LOG("\tBatLevel:%03d, RSSI:%05.2f, Nsr:%05.2f\r\n",SGCP.DevData.MasterDev.BatLevel, SGCP.DevData.MasterDev.RSSI,SGCP.DevData.MasterDev.Nsr); + SGCP.DeviceDataLen = SGCP.DeviceDataLen + sizeof(SGCP.DevData.MasterDev); + if(sizeof(LocalDataPack) != 0x00) + { + memcpy(&SGCP.DeviceDataBuff[SGCP.DeviceDataLen], LocalDataPack, sizeof(LocalDataPack)); + SGCP.DeviceDataLen = SGCP.DeviceDataLen + DevGetDataMess(LocalType, LocalDataPack);; + } + + SGCP.ReadDataAdd++; + SGCP.SubStatus = SUB_STATUS_READSUBSET_DATA; + break;} + + case SUB_STATUS_READSUBSET_DATA:{ + SGCP.SubsetReadDataOk = false; + SGCP.Subset_IRQ_Status = false; + ToSDReadData(SGCP.Dev485Addrs[SGCP.ReadDataAdd]); + SGCP.SD1mSDelayCnt = 100; + SGCP.SubStatus = SUB_STATUS_WAIT_READSUBSET; + break;} + + case SUB_STATUS_WAIT_READSUBSET:{ + if(SGCP.SD1mSDelayCnt <= 0) + { + DBG_LOG("\r\nSub485Addrs:%02X\r\n",SGCP.Dev485Addrs[SGCP.ReadDataAdd]); + DBG_LOG("Subset Device MAC:%02X %02X %02X %02X %02X %02X\r\n", + SGCP.DeviceMAC[SGCP.ReadDataAdd][0],SGCP.DeviceMAC[SGCP.ReadDataAdd][1],SGCP.DeviceMAC[SGCP.ReadDataAdd][2], + SGCP.DeviceMAC[SGCP.ReadDataAdd][3],SGCP.DeviceMAC[SGCP.ReadDataAdd][4],SGCP.DeviceMAC[SGCP.ReadDataAdd][5]); + DBG_LOG("\tDevice Read Data TimeOut!"); + + uint16_t Devtype; + Devtype = (SGCP.DeviceMAC[SGCP.ReadDataAdd][1] << 8) + SGCP.DeviceMAC[SGCP.ReadDataAdd][0]; + SGCP.DeviceDataLen += DevGetDataMess((DEVICE_TYPE_M)Devtype, NULL); + SGCP.ReadDataAdd++; + SGCP.SubStatus = SUB_STATUS_READSUBSET_DATA; + } + if(SGCP.Subset_IRQ_Status == true) + { + SGCP.Subset_IRQ_Status = false; + DBG_LOG("\r\nSub485Addrs:%02X\r\n",SGCP.Dev485Addrs[SGCP.ReadDataAdd]); + DBG_LOG("Subset Device MAC:%02X %02X %02X %02X %02X %02X\r\n", + SGCP.DeviceMAC[SGCP.ReadDataAdd][0],SGCP.DeviceMAC[SGCP.ReadDataAdd][1],SGCP.DeviceMAC[SGCP.ReadDataAdd][2], + SGCP.DeviceMAC[SGCP.ReadDataAdd][3],SGCP.DeviceMAC[SGCP.ReadDataAdd][4],SGCP.DeviceMAC[SGCP.ReadDataAdd][5]); + SubsetRevHandler(); + + uint16_t Devtype; + Devtype = (SGCP.DeviceMAC[SGCP.ReadDataAdd][1] << 8) + SGCP.DeviceMAC[SGCP.ReadDataAdd][0]; + + if(SGCP.SubsetReadDataOk == false) + { + SGCP.DeviceDataLen += DevGetDataMess((DEVICE_TYPE_M)Devtype, NULL); + DBG_LOG("\tDevice Read Data Err!\r\n"); + } + if(SGCP.SubsetReadDataOk == true) + { + SGCP.SubsetReadDataOk = false; + SGCP.DeviceDataLen += DevGetDataMess((DEVICE_TYPE_M)Devtype, &SGCP.DeviceDataBuff[SGCP.DeviceDataLen]); + DBG_LOG("\tDevice Read Data Ok!\r\n"); + } + SGCP.ReadDataAdd++; + SGCP.SubStatus = SUB_STATUS_READSUBSET_DATA; + } + if(SGCP.ReadDataAdd >= SGCP.DeviceN) + { + SGCP.DeviceReadDataOk = true; + memcpy(SGCP.DeviceData, SGCP.DeviceDataBuff, sizeof(SGCP.DeviceData)); + SGCP.SubStatus = SUB_STATUS_IDLE; + DBG_LOG("<----------- Cache Updat End ----------->\r\n"); + } + break;} + + case SUB_STATUS_MASTER_QUERY:{ + DBG_LOG("<----------- Device Scaning ----------->\r\n"); + SGCP.DeviceN = 0; + SGCP.Dev485Addr = 0; + SGCP.DeviceMACOk = false; + SGCP.Subset_IRQ_Status = false; + memset(&SGCP.Dev485Addrs, NULL, sizeof(SGCP.Dev485Addrs)); + memset(&SGCP.DeviceMAC, NULL, sizeof(SGCP.DeviceMAC)); + SGCP.Dev485Addrs[SGCP.DeviceN] = SGCP.Dev485Addr;//主设备485 + memcpy(SGCP.DeviceMAC[SGCP.DeviceN], LocalMAC, sizeof(LocalMAC));//主设备MAC + DBG_LOG("Master Device MAC:%02X %02X %02X %02X %02X %02X\r\n", + SGCP.DeviceMAC[SGCP.DeviceN][0],SGCP.DeviceMAC[SGCP.DeviceN][1],SGCP.DeviceMAC[SGCP.DeviceN][2], + SGCP.DeviceMAC[SGCP.DeviceN][3],SGCP.DeviceMAC[SGCP.DeviceN][4],SGCP.DeviceMAC[SGCP.DeviceN][5]); + SGCP.DeviceN++; + SGCP.Dev485Addr++; + SGCP.SubStatus = SUB_STATUS_SUBSET_QUERY; + break;} + + case SUB_STATUS_SUBSET_QUERY:{ + SGCP.Subset_IRQ_Status = false; + SGCP.SubsetMACOk = false; + ToSDInquire(SGCP.Dev485Addr); + SGCP.SD1mSDelayCnt = 100; + SGCP.SubStatus = SUB_STATUS_WAIT_SUBSET_QUERY; + break;} + + case SUB_STATUS_WAIT_SUBSET_QUERY:{ + if(SGCP.SD1mSDelayCnt <= 0) + { + DBG_LOG("Sub485Addrs:%02X No Device!\r\n",SGCP.Dev485Addr); + SGCP.Dev485Addr++; + SGCP.SubStatus = SUB_STATUS_SUBSET_QUERY; + } + if(SGCP.Subset_IRQ_Status == true) + { + SGCP.Subset_IRQ_Status = false; + SubsetRevHandler(); + + if(SGCP.SubsetMACOk == false) + { + DBG_LOG("Sub485Addrs:%02X Error In Data!",SGCP.Dev485Addr); + } + if(SGCP.SubsetMACOk == true) + { + SGCP.SubsetMACOk = false; + SGCP.Dev485Addrs[SGCP.DeviceN] = SGCP.Dev485Addr; + DBG_LOG("Sub485Addrs:%02X\r\n",SGCP.Dev485Addrs[SGCP.DeviceN]); + DBG_LOG("Subset MAC:%02X %02X %02X %02X %02X %02X\r\n", + SGCP.DeviceMAC[SGCP.DeviceN][0],SGCP.DeviceMAC[SGCP.DeviceN][1],SGCP.DeviceMAC[SGCP.DeviceN][2], + SGCP.DeviceMAC[SGCP.DeviceN][3],SGCP.DeviceMAC[SGCP.DeviceN][4],SGCP.DeviceMAC[SGCP.DeviceN][5]); + SGCP.DeviceN++; + } + SGCP.Dev485Addr++; + SGCP.SubStatus = SUB_STATUS_SUBSET_QUERY; + } + if(SGCP.Dev485Addr >= 16) + { + SGCP.SubStatus = SUB_STATUS_IDLE; + SGCP.DeviceMACOk = true; + DBG_LOG("Device Number:%02d\r\n",SGCP.DeviceN); + DBG_LOG("<----------- Device Scan End ----------->\r\n"); + } + break;} + + case SUB_STATUS_BROADCAST_SET_COLTIME:{ + ToSDSetColTime(0x00, App.Para.Layout.CollectTime); + SGCP.SubStatus = SUB_STATUS_IDLE; + break;} + + case SUB_STATUS_BROADCAST_SYNC_TIME:{ + ToSDSetColTime(0x00, App.Para.Layout.TimeStamp); + SGCP.SubStatus = SUB_STATUS_IDLE; + break;} + } +} + +/** + ******************************************************************************* + ** \brief 接收网关数据状态机 + ** + ** \param 无 + ** + ** \retval 无 + ******************************************************************************/ +void GwRevLoopHandler(void) +{ + switch(SGCP.GWStatus) + { + case GW_STATUS_IDLE:{ + break;} + + case GW_STATUS_WAIT_SUBIDLE:{ + if(SGCP.GW1mSDelayCnt <= 0) + { + DBG_LOG("Subset Be busy!\r\n"); + SGCP.NextSubStatus = SUB_STATUS_IDLE; + SGCP.GWStatus = GW_STATUS_IDLE; + } + if(SGCP.SubStatus == SUB_STATUS_IDLE) + { + SGCP.GW1mSDelayCnt = 0; + SGCP.SubStatus = SGCP.NextSubStatus; + SGCP.NextSubStatus = SUB_STATUS_IDLE; + SGCP.GWStatus = GW_STATUS_IDLE; + } + break;} + + case GW_STATUS_LOGIN:{ + SGCP.LoginOk = false; + SGCP.LoginMess = false; + SGCP.Gateway_IRQ_Status = false; + ToGWDevLogin(); + SGCP.GW1mSDelayCnt = 2000; + SGCP.GWStatus = GW_STATUS_WAIT_LOGIN; + break;} + + case GW_STATUS_WAIT_LOGIN:{ + if(SGCP.GW1mSDelayCnt <= 0) + { + SGCP.LoginMess = true; + DBG_LOG("Login Timeout!\r\n"); + SGCP.GWStatus = GW_STATUS_IDLE; + } + if(SGCP.Gateway_IRQ_Status == true) + { + SGCP.Gateway_IRQ_Status = false; + + if(SGCP.LoginOk == true) + { + DBG_LOG("Login Ok!\r\n"); + } + else if(SGCP.LoginOk == false) + { + DBG_LOG("Login Err!\r\n"); + } + SGCP.LoginMess = true; + SGCP.GWStatus = GW_STATUS_IDLE; + } + break;} + + case GW_STATUS_CALI:{ + PrintfMess(); + if(SGCP.BroadCmd == true) + { + SGCP.GWStatus = GW_STATUS_WAIT_SUBIDLE; + SGCP.NextSubStatus = SUB_STATUS_BROADCAST_CALI; + SGCP.GW1mSDelayCnt = 5000; + SGCP.BroadCmd = false; + DBG_LOG("Broad Cali Ok!\r\n"); + } + else + { + SGCP.GWStatus = GW_STATUS_IDLE; + ToGWCaliRes(SGCP.MasterCaliOk); + DBG_LOG("Alone Cali Ok!\r\n"); + } + SGCP.TimingAcquisition = true;//采集新的传感器数据 + break;} + + case GW_STATUS_READ_SENSOR:{ + PrintfMess(); + ToGWReadDataRes(SGCP.DeviceData); + DBG_LOG("Upload data Ok!\r\n"); + SGCP.TimingAcquisition = true;//采集新的传感器数据 + SGCP.GWStatus = GW_STATUS_WAIT_SUBIDLE; + SGCP.NextSubStatus = SUB_STATUS_READMASTER_DATA; + SGCP.GW1mSDelayCnt = 5000; + break;} + + case GW_STATUS_SET_COL_TIME:{ + PrintfMess(); + if(SGCP.BroadCmd == true) + { + SGCP.BroadCmd = false; + DBG_LOG("Broad CollectInterval Set as %04d\r\n",0x00, App.Para.Layout.CollectTime); + } + else + { + ToGWSetColTimeRes(NULL); + DBG_LOG("Alone CollectInterval Set as %04d\r\n",0x00, App.Para.Layout.CollectTime); + } + SGCP.GWStatus = GW_STATUS_WAIT_SUBIDLE; + SGCP.NextSubStatus = SUB_STATUS_BROADCAST_SET_COLTIME; + SGCP.GW1mSDelayCnt = 5000; + break;} + + case GW_STATUS_SYNC_TIME:{ + PrintfMess(); + if(SGCP.BroadCmd == true) + { + SGCP.BroadCmd = false; + DBG_LOG("Broad CollectInterval Set as %08d\r\n",App.Para.Layout.TimeStamp); + } + + else + { + ToGWSyncTimeRes(true); + DBG_LOG("Alone CollectInterval Set as %08d\r\n",App.Para.Layout.TimeStamp); + } + SGCP.GWStatus = GW_STATUS_WAIT_SUBIDLE; + SGCP.NextSubStatus = SUB_STATUS_BROADCAST_SYNC_TIME; + SGCP.GW1mSDelayCnt = 5000; + break;} + } +} + + + +/* 中断回调函数 */ +/***************************************************************************************** +* 函数名称: LORA_RxCallBack +* 功能描述: Lora数据接收函数 +* 参 数: *rBuff，接收到的字符串 + rlen，接收到的字符串长度 +* 返 回 值: 无 +*****************************************************************************************/ +void LORA_RxCallBack(uint8_t *rBuff, uint8_t rlen) +{ +// if (rlen > 0 && rBuff[0] == 0x7C && memcmp(&rBuff[7],&Comm_DevAddr[0],6) == 0) // 如果接收到了数据,并且设备地址相同则处理接收到的数据 +// { +// //< 处理接收到的数据 +// memcpy(App.UpperBuff, rBuff, rlen); +// App.UpperBuffLen = rlen; +// App.Upper_IRQ_Status = true;//上位机串口中断 +// } +} + +/***************************************************************************************** +* 函数名称: LPUartRx_CallBack +* 功能描述: 低功耗串口数据接收函数 +* 参 数: rData，接收到的字节 +* 返 回 值: 无 +*****************************************************************************************/ +void LPUartRx_CallBack(uint8_t rData) +{ + if(SGCP.LpUart0Delay1mSCnt == 0) { + SGCP.GWRS485Rx.HeaderFrame = false; + } + SGCP.LpUart0Delay1mSCnt = 5; + if(SGCP.GWRS485Rx.HeaderFrame == false) { + if(rData == 0x7B || rData == 0x7D) { + SGCP.GWRS485Rx.HeaderFrame = true; + SGCP.GWRS485Rx.RxLen = 0; + SGCP.GWRS485Rx.rPayLen = 0; + SGCP.InsideBuffLen = 0; + SGCP.InsidePayLen = 0; + SGCP.GWRS485Rx.RxBuff[SGCP.GWRS485Rx.RxLen++] = rData; + } + } + else { + if(SGCP.GWRS485Rx.RxBuff[0] == 0x7B) + { + if(SGCP.GWRS485Rx.RxLen == 14) { + SGCP.GWRS485Rx.rPayLen = rData; + } + if(SGCP.GWRS485Rx.RxLen == 15) { + SGCP.GWRS485Rx.rPayLen |= (rData << 8); + } + if(SGCP.GWRS485Rx.rPayLen > 10) { //大于最大负载长度，认为错误 + SGCP.GWRS485Rx.HeaderFrame = false; + return; + } + + SGCP.GWRS485Rx.RxBuff[SGCP.GWRS485Rx.RxLen++] = rData; + if(SGCP.GWRS485Rx.RxLen >= SGCP.GWRS485Rx.rPayLen + 18) { + SGCP.GWRS485Rx.HeaderFrame = false; + if(SGCP.GWRS485Rx.RxLen > 100) + return; + + memcpy(SGCP.GatewayBuff, SGCP.GWRS485Rx.RxBuff, SGCP.GWRS485Rx.RxLen); + SGCP.GatewayBuffLen = SGCP.GWRS485Rx.RxLen; + if(SGCP.GWRS485Rx.RxBuff[0] == 0x7B) GWRevHandler();//网关数据接收处理 + } + } + if(SGCP.GWRS485Rx.RxBuff[0] == 0x7D) + { + if(SGCP.GWRS485Rx.RxLen == 8) + { + SGCP.InsidePayLen = rData; + } + SGCP.GWRS485Rx.RxBuff[SGCP.GWRS485Rx.RxLen++] = rData; + if(SGCP.GWRS485Rx.RxLen >= SGCP.InsidePayLen + 11) + { + SGCP.GWRS485Rx.HeaderFrame = false; + + memcpy(SGCP.InsideBuff, SGCP.GWRS485Rx.RxBuff, SGCP.GWRS485Rx.RxLen); + SGCP.InsideBuffLen = SGCP.GWRS485Rx.RxLen; + if(SGCP.InsideBuff[0] == 0x7D) InRevHandler();//内部指令 + } + } + } +} + +/***************************************************************************************** +* 函数名称: Uart1Rx_CallBack +* 功能描述: 串口1数据接收函数 +* 参 数: rData，接收到的字节 +* 返 回 值: 无 +*****************************************************************************************/ +void Uart1Rx_CallBack(uint8_t rData) +{ + if(SGCP.Uart1Delay1mSCnt == 0) { + SGCP.SDRS485Rx.HeaderFrame = false; + } + SGCP.Uart1Delay1mSCnt = 5; + if(SGCP.SDRS485Rx.HeaderFrame == false) { + if(rData == 0x7C) { + SGCP.SDRS485Rx.HeaderFrame = true; + SGCP.SDRS485Rx.RxLen = 0; + SGCP.SDRS485Rx.rPayLen = 0; + SGCP.SDRS485Rx.RxBuff[SGCP.SDRS485Rx.RxLen++] = rData; + } + } + else { + if(SGCP.SDRS485Rx.RxLen == 3) { + if(rData > 36) { //大于最大负载长度，认为错误 + SGCP.SDRS485Rx.HeaderFrame = false; + return; + } + SGCP.SDRS485Rx.rPayLen = rData; + } + + SGCP.SDRS485Rx.RxBuff[SGCP.SDRS485Rx.RxLen++] = rData; + if(SGCP.SDRS485Rx.RxLen >= SGCP.SDRS485Rx.rPayLen + 6) { + SGCP.SDRS485Rx.HeaderFrame = false; + if(SGCP.SDRS485Rx.RxLen > 100) + return; + + memcpy(SGCP.SubsetBuff, SGCP.SDRS485Rx.RxBuff, SGCP.SDRS485Rx.RxLen); + SGCP.SubsetBuffLen = SGCP.SDRS485Rx.RxLen; + if(SGCP.SDRS485Rx.RxBuff[0] == 0x7C) SGCP.Subset_IRQ_Status = true;//子设备串口中断 + } + } +} +#endif + +#if (SGCP_SELECT == 1)//本机为单个主设备 +#if (LocalType == LASER_TRACING) +/** + ******************************************************************************* + ** \brief 网关激光状态回应 + ** + ** \param Ok_Err 成功失败标志位 + ** + ** \retval 无 + ******************************************************************************/ +static void ToGWLaserRes(bool Ok_Err) +{ + uint8_t Pack[256]; + uint16_t Crc16; + uint8_t Len; + + GatewayFrameHeader GFHeader = (GatewayFrameHeader)Pack; + + GFHeader->Header = 0x7B; + memcpy(&GFHeader->GWAddr[0], &GatewayMAC[0], sizeof(GFHeader->GWAddr)); + memcpy(&GFHeader->MDAddr[0], &LocalMAC[0], sizeof(GFHeader->MDAddr)); + GFHeader->Cmd = GWTOMD_CMD_SET_LASER; + GFHeader->PayloadLen = sizeof(Ok_Err); + + Len = sizeof(GatewayFrameHeader_t); + + Pack[Len++] = Ok_Err; + + Crc16 = CRC_Modbus(CRC16_BASE, Pack, Len); + Pack[Len++] = Crc16 & 0x00ff; + Pack[Len++] = (Crc16 >> 8) & 0x00ff; + +SGCP.GWRS485Rx.sCmdMDToGW = (GWTOMD_CMD_M)GFHeader->Cmd; +#if(SGCP_SELECT == 1 || SGCP_SELECT == 2) + Sx1276LoRaSendBuffer(Pack, Len); +#endif +#if(SGCP_SELECT == 3) + LPUart0SendArray(Pack, Len); +#endif +} +#endif +/** + ******************************************************************************* + ** \brief 接收网关数据状态机 + ** + ** \param 无 + ** + ** \retval 无 + ******************************************************************************/ +void GwRevLoopHandler(void) +{ + switch(SGCP.GWStatus) + { + case GW_STATUS_IDLE:{ + break;} + + case GW_STATUS_WAIT_SUBIDLE:{ + SGCP.GWStatus = GW_STATUS_IDLE; + break;} + + case GW_STATUS_LOGIN:{ + SGCP.DeviceN = 0; + SGCP.Dev485Addr = 0; + memset(&SGCP.Dev485Addrs, NULL, sizeof(SGCP.Dev485Addrs)); + memset(&SGCP.DeviceMAC, NULL, sizeof(SGCP.DeviceMAC)); + SGCP.Dev485Addrs[SGCP.DeviceN] = SGCP.Dev485Addr;//主设备485 + memcpy(SGCP.DeviceMAC[SGCP.DeviceN], LocalMAC, sizeof(LocalMAC));//主设备MAC + DBG_LOG("Master Device MAC:%02X %02X %02X %02X %02X %02X\r\n", + SGCP.DeviceMAC[SGCP.DeviceN][0],SGCP.DeviceMAC[SGCP.DeviceN][1],SGCP.DeviceMAC[SGCP.DeviceN][2], + SGCP.DeviceMAC[SGCP.DeviceN][3],SGCP.DeviceMAC[SGCP.DeviceN][4],SGCP.DeviceMAC[SGCP.DeviceN][5]); + SGCP.DeviceN++; + SGCP.LoginOk = false; + SGCP.LoginMess = false; + SGCP.Gateway_IRQ_Status = false; + ToGWDevLogin(); + SGCP.GW1mSDelayCnt = 2000; + SGCP.GWStatus = GW_STATUS_WAIT_LOGIN; + break;} + + case GW_STATUS_WAIT_LOGIN:{ + if(SGCP.GW1mSDelayCnt <= 0) + { + SGCP.LoginMess = true; + DBG_LOG("Login Timeout!\r\n"); + SGCP.GWStatus = GW_STATUS_IDLE; + break; + } + if(SGCP.Gateway_IRQ_Status == true) + { + SGCP.Gateway_IRQ_Status = false; + if(SGCP.LoginOk == true) + { + DBG_LOG("Login Ok!\r\n"); + /*注册后传感器需立即更新数据*/ + SGCP.TimingAcquisition = true;//采集新的传感器数据 + } + if(SGCP.LoginOk == false) + { + DBG_LOG("Login Err!\r\n"); + } + SGCP.LoginMess = true; + SGCP.GWStatus = GW_STATUS_IDLE; + } + break;} + + case GW_STATUS_CALI:{ + PrintfMess(); + if(SGCP.BroadCmd == true) + { + SGCP.BroadCmd = false; + DBG_LOG("Broad Cali Ok!\r\n"); + } + else + { + ToGWCaliRes(SGCP.MasterCaliOk); + DBG_LOG("Alone Cali Ok!\r\n"); + } + SGCP.TimingAcquisition = true;//采集新的传感器数据 + SGCP.GWStatus = GW_STATUS_IDLE; + break;} + + case GW_STATUS_READ_SENSOR:{ + PrintfMess(); + + SGCP.DeviceDataLen = 0; + memset(SGCP.DeviceData, NULL, sizeof(SGCP.DeviceData)); + #if (USE_VBAT_AD == 1) + SGCP.DevData.LaserTracing.MasterDev.BatLevel = VBAT_Percentage; + #else + SGCP.DevData.LaserTracing.MasterDev.BatLevel = 0x00; + #endif + #if (SGCP_SELECT == 1 || SGCP_SELECT == 2) + SX1276LoCalcRssiSnr(&SGCP.DevData.LaserTracing.MasterDev.RSSI, &SGCP.DevData.LaserTracing.MasterDev.Nsr);//获取信号强度 + #else + SGCP.DevData.LaserTracing.MasterDev.RSSI = 0x00; + SGCP.DevData.LaserTracing.MasterDev.Nsr = 0x00; + #endif + memcpy(&SGCP.DeviceData[0], &SGCP.DevData.LaserTracing.MasterDev, sizeof(SGCP.DevData.LaserTracing.MasterDev)); + + DBG_LOG("Master Device MAC:%02X %02X %02X %02X %02X %02X\r\n", + SGCP.DeviceMAC[SGCP.ReadDataAdd][0],SGCP.DeviceMAC[SGCP.ReadDataAdd][1],SGCP.DeviceMAC[SGCP.ReadDataAdd][2], + SGCP.DeviceMAC[SGCP.ReadDataAdd][3],SGCP.DeviceMAC[SGCP.ReadDataAdd][4],SGCP.DeviceMAC[SGCP.ReadDataAdd][5]); + DBG_LOG("\tBatLevel:%03d, RSSI:%05.2f, Nsr:%05.2f\r\n",SGCP.DevData.LaserTracing.MasterDev.BatLevel, SGCP.DevData.LaserTracing.MasterDev.RSSI,SGCP.DevData.LaserTracing.MasterDev.Nsr); + memcpy(&SGCP.DeviceData[SGCP.DeviceDataLen], &SGCP.DevData.LaserTracing.MasterDev, sizeof(SGCP.DevData.LaserTracing.MasterDev)); + SGCP.DeviceDataLen += sizeof(SGCP.DevData.LaserTracing.MasterDev); + + if(isAllZero(LocalDataPack, LocalDataLen) == false) + { + memcpy(&SGCP.DeviceData[SGCP.DeviceDataLen], LocalDataPack, sizeof(LocalDataPack)); + SGCP.DeviceDataLen = SGCP.DeviceDataLen + DevGetDataMess(LocalType, LocalDataPack);; + } + ToGWReadDataRes(SGCP.DeviceData); + DBG_LOG("Upload data Ok!\r\n"); + /*上传完数据后传感器需立即更新数据*/ + SGCP.TimingAcquisition = true;//采集新的传感器数据 + SGCP.GWStatus = GW_STATUS_IDLE; + break;} + + case GW_STATUS_SET_COL_TIME:{ + PrintfMess(); + if(SGCP.BroadCmd == true) + { + SGCP.BroadCmd = false; + DBG_LOG("Broad CollectInterval Set as %04d\r\n",0x00, App.Para.Layout.CollectTime); + } + else + { + ToGWSetColTimeRes(true); + DBG_LOG("Alone CollectInterval Set as %04d\r\n",0x00, App.Para.Layout.CollectTime); + } + /*GWRevHandler函数中已经缓存了接收到的采集时间间隔*/ + SGCP.GWStatus = GW_STATUS_IDLE; + break;} + + case GW_STATUS_SYNC_TIME:{ + PrintfMess(); + if(SGCP.BroadCmd == true) + { + SGCP.BroadCmd = false; + DBG_LOG("Broad time synchronization %08d\r\n",App.Para.Layout.TimeStamp); + } + else + { + ToGWSyncTimeRes(true); + DBG_LOG("Alone time synchronization %08d\r\n",App.Para.Layout.TimeStamp); + } + /*GWRevHandler函数中已经同步了接收到的时间戳*/ + SGCP.GWStatus = GW_STATUS_IDLE; + break;} + + case GW_STATUS_UPLOAD_SENSOR:{ + DBG_LOG("Uploading data...\r\n"); + SGCP.DeviceDataLen = 0; + memset(SGCP.DeviceData, NULL, sizeof(SGCP.DeviceData)); + + DBG_LOG("Master Device MAC:%02X %02X %02X %02X %02X %02X\r\n", + SGCP.DeviceMAC[SGCP.ReadDataAdd][0],SGCP.DeviceMAC[SGCP.ReadDataAdd][1],SGCP.DeviceMAC[SGCP.ReadDataAdd][2], + SGCP.DeviceMAC[SGCP.ReadDataAdd][3],SGCP.DeviceMAC[SGCP.ReadDataAdd][4],SGCP.DeviceMAC[SGCP.ReadDataAdd][5]); + + if(isAllZero(LocalDataPack, LocalDataLen) == false) + { + memcpy(&SGCP.DeviceData[SGCP.DeviceDataLen], LocalDataPack, sizeof(LocalDataPack)); + SGCP.DeviceDataLen = DevGetDataMess(LocalType, LocalDataPack); + } + SGCP.UploadOk = false; + SGCP.UploadMess = false; + SGCP.Gateway_IRQ_Status = false; + ToGWReadDataRes(SGCP.DeviceData); + SGCP.GW1mSDelayCnt = 2000; + SGCP.GWStatus = GW_STATUS_WAIT_UPLOAD; + break;} + + case GW_STATUS_WAIT_UPLOAD:{ + if(SGCP.GW1mSDelayCnt <= 0) + { + SGCP.UploadMess = true; + DBG_LOG("\r\nUpload timeout!\r\n"); + SGCP.GWStatus = SGCP.NextGWStatus; + break; + } + if(SGCP.Gateway_IRQ_Status == true) + { + SGCP.Gateway_IRQ_Status = false; + if(SGCP.UploadOk == true) + { + DBG_LOG("\r\nUpload data ok!\r\n"); + /*上传完数据后传感器需立即更新数据*/ + SGCP.TimingAcquisition = true;//采集新的传感器数据 + } + else if(SGCP.UploadOk == false) + { + DBG_LOG("\r\nUpload data err!\r\n"); + } + SGCP.UploadMess = true; + SGCP.GWStatus = SGCP.NextGWStatus; + } + break;} + + case GW_STATUS_LASER_STARES:{ + PrintfMess(); + if(SGCP.LaserOnOff == true) + { + ToGWLaserRes(SGCP.LaserOnOff); + DBG_LOG("The laser has been activated!\r\n"); + } + else if(SGCP.LaserOnOff == false) + { + ToGWLaserRes(SGCP.LaserOnOff); + DBG_LOG("The laser has been turned off!\r\n"); + } + SGCP.GWStatus = GW_STATUS_IDLE; + break;} + } +} + +/* 中断回调函数 */ +/***************************************************************************************** +* 函数名称: LORA_RxCallBack +* 功能描述: Lora数据接收函数 +* 参 数: *rBuff，接收到的字符串 + rlen，接收到的字符串长度 +* 返 回 值: 无 +*****************************************************************************************/ +void LORA_RxCallBack(uint8_t *rBuff, uint8_t rlen) +{ + if (rlen > 0 && rBuff[0] == 0x7B && memcmp(&rBuff[7],&LocalMAC[0],6) == 0) // 如果接收到了数据,并且设备地址相同则处理接收到的数据 + { + //< 处理接收到的数据 + memcpy(SGCP.GatewayBuff, rBuff, rlen); + SGCP.GatewayBuffLen = rlen; + GWRevHandler();//网关数据接收处理 + } +} + +/***************************************************************************************** +* 函数名称: LPUartRx_CallBack +* 功能描述: 低功耗串口数据接收函数 +* 参 数: rData，接收到的字节 +* 返 回 值: 无 +*****************************************************************************************/ +void LPUartRx_CallBack(uint8_t rData) +{ + if(SGCP.LpUart0Delay1mSCnt == 0) { + SGCP.GWRS485Rx.HeaderFrame = false; + } + SGCP.LpUart0Delay1mSCnt = 5; + if(SGCP.GWRS485Rx.HeaderFrame == false) { + if(rData == 0x7B || rData == 0x7D) { + SGCP.GWRS485Rx.HeaderFrame = true; + SGCP.GWRS485Rx.RxLen = 0; + SGCP.GWRS485Rx.rPayLen = 0; + SGCP.InsideBuffLen = 0; + SGCP.InsidePayLen = 0; + SGCP.GWRS485Rx.RxBuff[SGCP.GWRS485Rx.RxLen++] = rData; + } + } + else { + if(SGCP.GWRS485Rx.RxBuff[0] == 0x7B) + { + if(SGCP.GWRS485Rx.RxLen == 14) { + SGCP.GWRS485Rx.rPayLen = rData; + } + if(SGCP.GWRS485Rx.RxLen == 15) { + SGCP.GWRS485Rx.rPayLen |= (rData << 8); + } + if(SGCP.GWRS485Rx.rPayLen > 10) { //大于最大负载长度，认为错误 + SGCP.GWRS485Rx.HeaderFrame = false; + return; + } + + SGCP.GWRS485Rx.RxBuff[SGCP.GWRS485Rx.RxLen++] = rData; + if(SGCP.GWRS485Rx.RxLen >= SGCP.GWRS485Rx.rPayLen + 18) { + SGCP.GWRS485Rx.HeaderFrame = false; + if(SGCP.GWRS485Rx.RxLen > 100) + return; + + memcpy(SGCP.GatewayBuff, SGCP.GWRS485Rx.RxBuff, SGCP.GWRS485Rx.RxLen); + SGCP.GatewayBuffLen = SGCP.GWRS485Rx.RxLen; + if(SGCP.GWRS485Rx.RxBuff[0] == 0x7B) GWRevHandler();//网关数据接收处理 + } + } + if(SGCP.GWRS485Rx.RxBuff[0] == 0x7D) + { + if(SGCP.GWRS485Rx.RxLen == 8) + { + SGCP.InsidePayLen = rData; + } + SGCP.GWRS485Rx.RxBuff[SGCP.GWRS485Rx.RxLen++] = rData; + if(SGCP.GWRS485Rx.RxLen >= SGCP.InsidePayLen + 11) + { + SGCP.GWRS485Rx.HeaderFrame = false; + + memcpy(SGCP.InsideBuff, SGCP.GWRS485Rx.RxBuff, SGCP.GWRS485Rx.RxLen); + SGCP.InsideBuffLen = SGCP.GWRS485Rx.RxLen; + if(SGCP.GWRS485Rx.RxBuff[0] == 0x7D) InRevHandler();//内部指令 + } + } + } +} + +/***************************************************************************************** +* 函数名称: Uart1Rx_CallBack +* 功能描述: 串口1数据接收函数 +* 参 数: rData，接收到的字节 +* 返 回 值: 无 +*****************************************************************************************/ +void Uart1Rx_CallBack(uint8_t rData) +{ +// if(SGCP.Uart1Delay1mSCnt == 0) { +// SGCP.SDRS485Rx.HeaderFrame = false; +// } +// SGCP.Uart1Delay1mSCnt = 5; +// if(SGCP.SDRS485Rx.HeaderFrame == false) { +// if(rData == 0x7C) { +// SGCP.SDRS485Rx.HeaderFrame = true; +// SGCP.SDRS485Rx.RxLen = 0; +// SGCP.SDRS485Rx.rPayLen = 0; +// SGCP.SDRS485Rx.RxBuff[SGCP.SDRS485Rx.RxLen++] = rData; +// } +// } +// else { +// if(SGCP.SDRS485Rx.RxLen == 3) { +// if(rData > 36) { //大于最大负载长度，认为错误 +// SGCP.SDRS485Rx.HeaderFrame = false; +// return; +// } +// SGCP.SDRS485Rx.rPayLen = rData; +// } +// +// SGCP.SDRS485Rx.RxBuff[SGCP.SDRS485Rx.RxLen++] = rData; +// if(SGCP.SDRS485Rx.RxLen >= SGCP.SDRS485Rx.rPayLen + 6) { +// SGCP.SDRS485Rx.HeaderFrame = false; +// if(SGCP.SDRS485Rx.RxLen > 100) +// return; + +// memcpy(SGCP.SubsetBuff, SGCP.SDRS485Rx.RxBuff, SGCP.SDRS485Rx.RxLen); +// SGCP.SubsetBuffLen = SGCP.SDRS485Rx.RxLen; +// if(SGCP.SDRS485Rx.RxBuff[0] == 0x7C) SGCP.Subset_IRQ_Status = true;//子设备串口中断 +// } +// } +} +#endif + +#if (SGCP_SELECT == 2)//本机为单个子设备 +/** + ******************************************************************************* + ** \brief 接收主设备数据状态机 + ** + ** \param 无 + ** + ** \retval 无 + ******************************************************************************/ +void MasRevLoopHandler(void) +{ + switch(SGCP.MasStatus) + { + case MAS_STATUS_IDLE:{ + break;} + + case MAS_STATUS_CALI:{ + PrintfMess(); + if(SGCP.BroadCmd == true) + { + SGCP.BroadCmd = false; + DBG_LOG("Broad Cail!\r\n"); + } + else + { + ToMDCaliRes(App.Para.Layout.RS485Addr, SGCP.SubsetCaliOk); + DBG_LOG("Alone Cail!\r\n"); + } + SGCP.TimingAcquisition = true;//采集新的传感器数据 + SGCP.MasStatus = MAS_STATUS_IDLE; + break;} + + case MAS_STATUS_READ_SENSOR:{ + PrintfMess(); + + SGCP.DeviceDataLen = 0; + memset(SGCP.DeviceData, NULL, sizeof(SGCP.DeviceData)); + DBG_LOG("Sub485Addr:%02X\r\n",App.Para.Layout.RS485Addr); + + if(sizeof(LocalDataPack) != 0x00) + { + memcpy(&SGCP.DeviceData[SGCP.DeviceDataLen], LocalDataPack, sizeof(LocalDataPack)); + SGCP.DeviceDataLen = SGCP.DeviceDataLen + DevGetDataMess(LocalType, LocalDataPack);; + } + + ToMDReadDataRes(App.Para.Layout.RS485Addr, SGCP.DeviceData, SGCP.DeviceDataLen); + DBG_LOG("Upload Sensor Data Ok!\r\n"); + SGCP.TimingAcquisition = true;//采集新的传感器数据 + SGCP.MasStatus = MAS_STATUS_IDLE; + break;} + + case MAS_STATUS_DEVICE_INQUIRE:{ + PrintfMess(); + ToMDInquireRes(App.Para.Layout.RS485Addr); + DBG_LOG("Device Inquire!\r\n"); + SGCP.MasStatus = MAS_STATUS_IDLE; + break;} + + case MAS_STATUS_SET_COL_TIME:{ + PrintfMess(); + if(SGCP.BroadCmd == true) + { + SGCP.BroadCmd = false; + DBG_LOG("Broad Set Col Time!\r\n"); + } + else + { + + ToMDSetColTimeRes(App.Para.Layout.RS485Addr, true); + DBG_LOG("Alone Set Col Time!\r\n"); + } + SGCP.MasStatus = MAS_STATUS_IDLE; + break;} + + case MAS_STATUS_SYNC_TIME:{ + PrintfMess(); + if(SGCP.BroadCmd == true) + { + SGCP.BroadCmd = false; + DBG_LOG("Broad Sync Time!\r\n"); + } + else + { + ToMDSyncTimeRes(App.Para.Layout.RS485Addr, true); + DBG_LOG("Alone Sync Time!\r\n"); + } + SGCP.MasStatus = MAS_STATUS_IDLE; + break;} + } +} +/* 中断回调函数 */ +/***************************************************************************************** +* 函数名称: LORA_RxCallBack +* 功能描述: Lora数据接收函数 +* 参 数: *rBuff，接收到的字符串 + rlen，接收到的字符串长度 +* 返 回 值: 无 +*****************************************************************************************/ +void LORA_RxCallBack(uint8_t *rBuff, uint8_t rlen) +{ +// if (rlen > 0 && rBuff[0] == 0x7C && memcmp(&rBuff[7],&Comm_DevAddr[0],6) == 0) // 如果接收到了数据,并且设备地址相同则处理接收到的数据 +// { +// //< 处理接收到的数据 +// memcpy(App.UpperBuff, rBuff, rlen); +// App.UpperBuffLen = rlen; +// App.Upper_IRQ_Status = true;//上位机串口中断 +// } +} + +/***************************************************************************************** +* 函数名称: LPUartRx_CallBack +* 功能描述: 低功耗串口数据接收函数 +* 参 数: rData，接收到的字节 +* 返 回 值: 无 +*****************************************************************************************/ +void LPUartRx_CallBack(uint8_t rData) +{ + if(SGCP.LpUart0Delay1mSCnt == 0) { + SGCP.SDRS485Rx.HeaderFrame = false; + } + SGCP.LpUart0Delay1mSCnt = 5; + if(SGCP.SDRS485Rx.HeaderFrame == false) { + if(rData == 0x7C || rData == 0x7D) { + SGCP.SDRS485Rx.HeaderFrame = true; + SGCP.SDRS485Rx.RxLen = 0; + SGCP.SDRS485Rx.rPayLen = 0; + SGCP.InsideBuffLen = 0; + SGCP.InsidePayLen = 0; + SGCP.SDRS485Rx.RxBuff[SGCP.SDRS485Rx.RxLen++] = rData; + } + } + else { + if(SGCP.SDRS485Rx.RxBuff[0] == 0x7C) + { + if(SGCP.SDRS485Rx.RxLen == 3) { + if(rData > 36) { //大于最大负载长度，认为错误 + SGCP.SDRS485Rx.HeaderFrame = false; + return; + } + SGCP.SDRS485Rx.rPayLen = rData; + } + + SGCP.SDRS485Rx.RxBuff[SGCP.SDRS485Rx.RxLen++] = rData; + if(SGCP.SDRS485Rx.RxLen >= SGCP.SDRS485Rx.rPayLen + 6) { + SGCP.SDRS485Rx.HeaderFrame = false; + if(SGCP.SDRS485Rx.RxLen > 100) + return; + + memcpy(SGCP.SubsetBuff, SGCP.SDRS485Rx.RxBuff, SGCP.SDRS485Rx.RxLen); + SGCP.SubsetBuffLen = SGCP.SDRS485Rx.RxLen; + if(SGCP.SDRS485Rx.RxBuff[0] == 0x7C) MasRevHandler();//子设备串口中断 + } + } + if(SGCP.SDRS485Rx.RxBuff[0] == 0x7D) + { + if(SGCP.SDRS485Rx.RxLen == 8) + { + SGCP.InsidePayLen = rData; + } + SGCP.SDRS485Rx.RxBuff[SGCP.SDRS485Rx.RxLen++] = rData; + if(SGCP.SDRS485Rx.RxLen >= SGCP.InsidePayLen + 11) + { + SGCP.SDRS485Rx.HeaderFrame = false; + + memcpy(SGCP.InsideBuff, SGCP.SDRS485Rx.RxBuff, SGCP.SDRS485Rx.RxLen); + SGCP.InsideBuffLen = SGCP.SDRS485Rx.RxLen; + if(SGCP.SDRS485Rx.RxBuff[0] == 0x7D) InRevHandler();//内部指令 + } + } + } +} +/***************************************************************************************** +* 函数名称: Uart1Rx_CallBack +* 功能描述: 串口1数据接收函数 +* 参 数: rData，接收到的字节 +* 返 回 值: 无 +*****************************************************************************************/ +void Uart1Rx_CallBack(uint8_t rData) +{ +// if(SGCP.Uart1Delay1mSCnt == 0) { +// SGCP.SDRS485Rx.HeaderFrame = false; +// } +// SGCP.Uart1Delay1mSCnt = 5; +// if(SGCP.SDRS485Rx.HeaderFrame == false) { +// if(rData == 0x7C) { +// SGCP.SDRS485Rx.HeaderFrame = true; +// SGCP.SDRS485Rx.RxLen = 0; +// SGCP.SDRS485Rx.rPayLen = 0; +// SGCP.SDRS485Rx.RxBuff[SGCP.SDRS485Rx.RxLen++] = rData; +// } +// } +// else { +// if(SGCP.SDRS485Rx.RxLen == 3) { +// if(rData > 36) { //大于最大负载长度，认为错误 +// SGCP.SDRS485Rx.HeaderFrame = false; +// return; +// } +// SGCP.SDRS485Rx.rPayLen = rData; +// } +// +// SGCP.SDRS485Rx.RxBuff[SGCP.SDRS485Rx.RxLen++] = rData; +// if(SGCP.SDRS485Rx.RxLen >= SGCP.SDRS485Rx.rPayLen + 6) { +// SGCP.SDRS485Rx.HeaderFrame = false; +// if(SGCP.SDRS485Rx.RxLen > 100) +// return; + +// memcpy(SGCP.SubsetBuff, SGCP.SDRS485Rx.RxBuff, SGCP.SDRS485Rx.RxLen); +// SGCP.SubsetBuffLen = SGCP.SDRS485Rx.RxLen; +// if(SGCP.SDRS485Rx.RxBuff[0] == 0x7C) SGCP.Subset_IRQ_Status = true;//子设备串口中断 +// } +// } +} + +#endif + +/** + ******************************************************************************* + ** \brief 内部指令数据状态机 + ** + ** \param 无 + ** + ** \retval 无 + ******************************************************************************/ +void InRevLoopHandler(void) +{ + switch(SGCP.InStatus) + { + case IN_STATUS_IDLE:{ + break;} + + case IN_STATUS_ALTER_485ADDR:{ + PrintfMess(); + Alter485AddrRes(LocalMAC, true); + DBG_LOG("Alter RS485Addr:%X\r\n", App.Para.RS485Addr); + SGCP.InStatus = IN_STATUS_IDLE; + break;} + + case IN_STATUS_UPDATE:{ + Update(SGCP.InsidePay);//固件更新. + memset(SGCP.InsidePay, NULL, sizeof(SGCP.InsidePay)); + SGCP.InStatus = IN_STATUS_IDLE; + break;} + } +} +/***************************************************************************************** +* 函数名称: SGCP1mSRoutine +* 功能描述: SGCP时基循环处理函数 +* 参 数: 无 +* 返 回 值: 无 +*****************************************************************************************/ +void SGCP1mSRoutine(void) +{ + if(SGCP.LpUart0Delay1mSCnt > 0) + SGCP.LpUart0Delay1mSCnt--; + if(SGCP.LoraDelay1mSCnt > 0) + SGCP.LoraDelay1mSCnt--; + if(SGCP.Uart1Delay1mSCnt > 0) + SGCP.Uart1Delay1mSCnt--; + if(SGCP.SD1mSDelayCnt > 0) + SGCP.SD1mSDelayCnt--; + if(SGCP.GW1mSDelayCnt > 0) + SGCP.GW1mSDelayCnt--; + if(SGCP.In1mSDelayCnt > 0) + SGCP.In1mSDelayCnt--; +} + + diff --git a/source/src/Update.c b/source/src/Update.c new file mode 100644 index 0000000..ec791e3 --- /dev/null +++ b/source/src/Update.c @@ -0,0 +1,48 @@ +#include "Update.h" +#include "UartDebug.h" + +static BootPara_t BLPara; + +/***************************************************************************************** +* 函数名称: Update +* 功能描述: 固件升级,此函数在解析到升级指令是调用 +* 参 数: PayLoad 协议负载，需去除帧头等信息，只传负载数据 +* 返 回 值: 无 +*****************************************************************************************/ +void Update(uint8_t *PayLoad) +{ + UpDataRequset_t Req; + + memcpy(&Req, PayLoad, sizeof(UpDataRequset_t)); + BLPara.AppSize = Req.AppSize; + BLPara.Crc32Check = Req.AppCrc32; + BLPara.PackageCnt = Req.PackageNum; + BLPara.AppFlag = 0; + BLPara.UpdateFlag = APP_UPDATE_FLAG; + + U_DBG_LOG("Receive upgrade command:\r\n"); + U_DBG_LOG("PackageNum: %d\r\n", BLPara.PackageCnt); + U_DBG_LOG("AppSize: %d\r\n", BLPara.AppSize); + U_DBG_LOG("AppCrc32: 0x%08x\r\n", BLPara.Crc32Check); + U_DBG_LOG("System Reset!\r\n"); + + SAVE_BOOT_PARA((uint32_t *)&BLPara); + U_DELAY_MS(200); + U_SYSTEM_TESET(); +} + +/***************************************************************************************** +* 函数名称: UpdateInit +* 功能描述: 升级参数初始化，需要在程序启动，外设初试完后调用 +* 参 数: 无 +* 返 回 值: 无 +*****************************************************************************************/ +void UpdateInit(void) +{ + READ_BOOT_PARA((uint32_t *)&BLPara); + if(BLPara.AppFlag != APP_START_FLAG) { + BLPara.AppFlag = APP_START_FLAG; + SAVE_BOOT_PARA((uint32_t *)&BLPara); + } +} + diff --git a/source/src/bsp.c b/source/src/bsp.c new file mode 100644 index 0000000..a01992c --- /dev/null +++ b/source/src/bsp.c @@ -0,0 +1,937 @@ +#include +#include +#include "sysctrl.h" +#include "gpio.h" +#include "flash.h" +#include "bsp.h" +#include "lpuart.h" +#include "uart.h" +#include "lpm.h" +#include "lptim.h" +#include "spi.h" +#include "reset.h" +#include "wdt.h" +#include "rtc.h" +#include "i2c.h" +#include "bgr.h" +#include "adc.h" +#include "UartDebug.h" + +#include "lsm6dsl_app.h" +#include "mmc5983.h" +#include "sx127x.h" + +extern void LPUartRx_CallBack(uint8_t Rx); +extern void Uart1Rx_CallBack(uint8_t Rx); +extern void DebugUartIRQ(uint8_t Data); +extern void SysTick_CallBack(void); +extern void RtcIRQHander(void); +extern void LPTimer0IRQHander(void); +extern void LORA_RxCallBack(uint8_t *rBuff, uint8_t rlen); + +static __IO uint32_t SysTickCnt = 0; +static volatile uint32_t u32AdcRestult; + +static void SystemClkDivInit(void)//系统时钟分频设置 +{ + //时钟分频设置 + Sysctrl_SetHCLKDiv(SysctrlHclkDiv1); + Sysctrl_SetPCLKDiv(SysctrlPclkDiv1); +} +static void SystemClkInit(en_sysctrl_rch_freq_t enRchFreq)//时钟初始化 +{ + ///< RCH时钟不同频率的切换，需要先将时钟切换到RCL + Sysctrl_SetRCLTrim(SysctrlRclFreq38400); + Sysctrl_SetRCLStableTime(SysctrlRclStableCycle64); + Sysctrl_ClkSourceEnable(SysctrlClkRCL, TRUE); + + /*内部高速时钟初始化 24MHZ*/ + /*Sysctrl_SetRCHTrim(enRchFreq); + Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE); + //< HCLK不超过24M：此处设置FLASH读等待周期为0 cycle + Flash_WaitCycle(FlashWaitCycle0); + + Sysctrl_SysClkSwitch(SysctrlClkRCH);//系统时钟源选择 + */ + + /*内部高速时钟初始化 48MHZ*/ + stc_sysctrl_pll_cfg_t stcPLLCfg; + + ///< 加载目标频率的RCH的TRIM值 + Sysctrl_SetRCHTrim(SysctrlRchFreq4MHz); + ///< 使能RCH + Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE); + + stcPLLCfg.enInFreq = SysctrlPllInFreq4_6MHz; //RCH 4MHz + stcPLLCfg.enOutFreq = SysctrlPllOutFreq36_48MHz; //PLL 输出 + stcPLLCfg.enPllClkSrc = SysctrlPllRch; //输入时钟源选择RCH + stcPLLCfg.enPllMul = SysctrlPllMul12; //4MHz x 12 = 48MHz + Sysctrl_SetPLLFreq(&stcPLLCfg); + + ///< 当使用的时钟源HCLK大于24M：设置FLASH 读等待周期为1 cycle(默认值也为1 cycle) + Flash_WaitCycle(FlashWaitCycle1); + + ///< 使能PLL + Sysctrl_ClkSourceEnable(SysctrlClkPLL, TRUE); + ///< 时钟切换到PLL + Sysctrl_SysClkSwitch(SysctrlClkPLL); + + /*外部低速晶振初始化 32.768KHz*/ +/* Sysctrl_XTLDriverCfg(SysctrlXtlAmp3, SysctrlXtalDriver3); + Sysctrl_SetXTLStableTime(SysctrlXtlStableCycle16384); + Sysctrl_ClkSourceEnable(SysctrlClkXTL, TRUE); +*/ +} +static void SystemRCLInit(void) +{ + Sysctrl_SetRCLTrim(SysctrlRclFreq38400); ///< 配置RCL时钟为38400kHz + Sysctrl_SetRCLStableTime(SysctrlRclStableCycle256); + Sysctrl_ClkSourceEnable(SysctrlClkRCL, TRUE); ///< 使能RCL时钟 +} + +static void Uart0Init(void) +{ + stc_gpio_cfg_t stcGpioCfg; + stc_uart_cfg_t stcCfg; + DDL_ZERO_STRUCT(stcGpioCfg); + + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio,TRUE); + + /// 0x99 || RtcInitStruct.rtcTime.u8Month > 0x12) { + RtcInitStruct.rtcTime.u8Second = 0x30; + RtcInitStruct.rtcTime.u8Minute = 0x38; + RtcInitStruct.rtcTime.u8Hour = 0x08; + RtcInitStruct.rtcTime.u8Day = 0x02; + RtcInitStruct.rtcTime.u8DayOfWeek = 0x06; + RtcInitStruct.rtcTime.u8Month = 0x09; + RtcInitStruct.rtcTime.u8Year = 0x23; + } + RtcInitStruct.rtcCompen = RtcCompenEnable; + RtcInitStruct.rtcCompValue = 0; //补偿值 根据实际情况进行补偿 + Rtc_Init(&RtcInitStruct); + Rtc_AlmIeCmd(TRUE); //使能闹钟中断 + EnableNvic(RTC_IRQn, IrqLevel3, TRUE); //使能RTC中断向量 + Rtc_Cmd(TRUE); //使能RTC开始计数 + Rtc_StartWait(); //启动RTC计数，如果要立即切换到低功耗，需要执行此函数 +} +/****************************************************************************** +* 函数名称: LPTimer0Init +* 功能描述: 低功耗定时器0初始化 +* 参 数: sTime 定时中断秒时间 +* 返 回 值: 无 + ******************************************************************************/ +void LPTimer0Init(uint16_t _100ms) +{ + Lptim_Cmd(M0P_LPTIMER0, FALSE); + + stc_lptim_cfg_t stcLptCfg; + DDL_ZERO_STRUCT(stcLptCfg); + + ///< 使能LPTIM0 外设时钟 + Sysctrl_SetPeripheralGate(SysctrlPeripheralLpTim0, TRUE); + + stcLptCfg.enPrs = LptimPrsDiv256; + stcLptCfg.enGate = LptimGateLow; + stcLptCfg.enGatep = LptimGatePLow; + stcLptCfg.enTcksel = LptimRcl; + stcLptCfg.enTogen = LptimTogEnLow; + stcLptCfg.enCt = LptimTimerFun; //警示器功能 + stcLptCfg.enMd = LptimMode1; //工作模式为模式1：无自动重装载16位计数器/定时器 + stcLptCfg.u16Arr = 0x10000 - (_100ms * 13); //预装载寄存器值 + Lptim_Init(M0P_LPTIMER0, &stcLptCfg); + + Lptim_ClrItStatus(M0P_LPTIMER0); //清除中断标志位 + Lptim_ConfIt(M0P_LPTIMER0, TRUE); //允许LPTIMER中断 + EnableNvic(LPTIM_0_1_IRQn, IrqLevel3, TRUE); + + Lptim_Cmd(M0P_LPTIMER0, TRUE); +} +void LPTimer0_ON(uint16_t _100ms) +{ + LPTimer0Init(_100ms); +} +void LPTimer0_OFF(void) +{ + EnableNvic(LPTIM_0_1_IRQn, IrqLevel3, FALSE); + Lptim_Cmd(M0P_LPTIMER0, FALSE); +} +static void GPIOInit(void) +{ + stc_gpio_cfg_t GpioInitStruct; + + DDL_ZERO_STRUCT(GpioInitStruct); + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio,TRUE); + + //未使用或引出的脚设为输入上拉 + GpioInitStruct.enDir = GpioDirIn; + GpioInitStruct.enPu = GpioPuEnable; + + Gpio_Init(GpioPortA, GpioPin0, &GpioInitStruct); + Gpio_Init(GpioPortA, GpioPin1, &GpioInitStruct); + Gpio_Init(GpioPortA, GpioPin2, &GpioInitStruct); + Gpio_Init(GpioPortA, GpioPin5, &GpioInitStruct); + Gpio_Init(GpioPortA, GpioPin6, &GpioInitStruct); + Gpio_Init(GpioPortA, GpioPin7, &GpioInitStruct); + Gpio_Init(GpioPortA, GpioPin8, &GpioInitStruct); + + Gpio_Init(GpioPortB, GpioPin2, &GpioInitStruct); + Gpio_Init(GpioPortB, GpioPin8, &GpioInitStruct); + Gpio_Init(GpioPortB, GpioPin9, &GpioInitStruct); + Gpio_Init(GpioPortB, GpioPin15, &GpioInitStruct); + + Gpio_Init(GpioPortF, GpioPin6, &GpioInitStruct); + //end + + /********************************** GPIO输出 ****************************************/ + GpioInitStruct.enDir = GpioDirOut; ///< 端口方向配置->输出 + GpioInitStruct.enDrv = GpioDrvH; ///< 端口驱动能力配置->高驱动能力 + GpioInitStruct.enPu = GpioPuDisable; ///< 端口上下拉配置->无 + GpioInitStruct.enPd = GpioPdDisable; + GpioInitStruct.enOD = GpioOdDisable; ///< 端口开漏输出配置->开漏输出关闭 + GpioInitStruct.enCtrlMode = GpioAHB; ///< 端口输入/输出值寄存器总线控制模式配置->AHB + GpioInitStruct.bOutputVal = false; ///< 端口默认输出配置->低电平 + //< RS485控制引脚 + Gpio_Init(RS485_CTRL_PORTx,RS485_CTRL_PINx,&GpioInitStruct); + //< 激光控制引脚 + Gpio_Init(LASER1_ON_OFF_PORTx,LASER1_ON_OFF_PINx,&GpioInitStruct); + Gpio_Init(LASER2_ON_OFF_PORTx,LASER2_ON_OFF_PINx,&GpioInitStruct); + Gpio_Init(LASER3_ON_OFF_PORTx,LASER3_ON_OFF_PINx,&GpioInitStruct); + + GpioInitStruct.bOutputVal = true; ///< 端口默认输出配置->高电平 + //< LORA --> RST + Gpio_Init(LORA_RST_PORTx,LORA_RST_PINx,&GpioInitStruct); + //< LED_State + Gpio_Init(LED_STATE_PORTx,LED_STATE_PINx,&GpioInitStruct); + + /********************************** GPIO输入 ****************************************/ + GpioInitStruct.enDir = GpioDirIn; ///< 端口方向配置->输入 + GpioInitStruct.enPu = GpioPuDisable; ///< 端口上下拉配置->无 + GpioInitStruct.enPd = GpioPdDisable; + GpioInitStruct.enOD = GpioOdDisable; + + //< LORA --> DIO0 + Gpio_Init(LORA_DIO0_PORTx,LORA_DIO0_PINx,&GpioInitStruct); + //< LORA --> DIO0 + Gpio_Init(LORA_DIO1_PORTx,LORA_DIO1_PINx,&GpioInitStruct); + //< ACC_INT1 + Gpio_Init(LSM6DSLTR_INT1_PORTx,LSM6DSLTR_INT1_PINx,&GpioInitStruct); + //< ACC_INT2 + Gpio_Init(LSM6DSLTR_INT2_PORTx,LSM6DSLTR_INT2_PINx,&GpioInitStruct); + //< MMC_INT + Gpio_Init(MMC5983MA_INT_PORTx,MMC5983MA_INT_PINx,&GpioInitStruct); + GlobalIntEnable(); +} +void GlobalIntEnable(void)//全局中断使能 +{ + EnableNvic(PORTB_IRQn, IrqLevel3, TRUE); + EnableNvic(PORTC_E_IRQn, IrqLevel3, TRUE); +} +void GlobalIntDisable(void)//全局中断失能 +{ + EnableNvic(PORTB_IRQn, IrqLevel3, FALSE); + EnableNvic(PORTC_E_IRQn, IrqLevel3, FALSE); +} +void LORAIntEnable(void)//LORA中断使能 +{ + Gpio_EnableIrq(LORA_DIO0_PORTx, LORA_DIO0_PINx, GpioIrqRising);//LORA_DIO0 + Gpio_EnableIrq(LORA_DIO1_PORTx, LORA_DIO1_PINx, GpioIrqRising);//LORA_DIO1 +} +void LORAIntDisable(void)//LORA中断失能 +{ + Gpio_DisableIrq(LORA_DIO0_PORTx, LORA_DIO0_PINx, GpioIrqRising); + Gpio_DisableIrq(LORA_DIO1_PORTx, LORA_DIO1_PINx, GpioIrqRising); +} +void ACCandMMCIntEnable(void)//加速度和地磁中断使能 +{ + Gpio_EnableIrq(LSM6DSLTR_INT1_PORTx, LSM6DSLTR_INT1_PINx, GpioIrqRising);//ACC_Int1 + Gpio_EnableIrq(LSM6DSLTR_INT2_PORTx, LSM6DSLTR_INT2_PINx, GpioIrqRising);//ACC_Int2 + Gpio_EnableIrq(MMC5983MA_INT_PORTx, MMC5983MA_INT_PINx, GpioIrqRising);//MMC_Int +} +void ACCandMMCIntDisable(void)//加速度和地磁中断失能 +{ + Gpio_DisableIrq(LSM6DSLTR_INT1_PORTx, LSM6DSLTR_INT1_PINx, GpioIrqRising);//ACC_Int1 + Gpio_DisableIrq(LSM6DSLTR_INT2_PORTx, LSM6DSLTR_INT2_PINx, GpioIrqRising);//ACC_Int2 + Gpio_DisableIrq(MMC5983MA_INT_PORTx, MMC5983MA_INT_PINx, GpioIrqRising);//MMC_Int +} + +static void SPI0Init(void) +{ + stc_gpio_cfg_t GpioInitStruct; + stc_spi_cfg_t SpiInitStruct; + + DDL_ZERO_STRUCT(GpioInitStruct); + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio,TRUE); + + /************************** SPI0配置:主机-->LORA *******************************/ + GpioInitStruct.enDir = GpioDirOut; + + Gpio_Init(SPI0_NSS_PORTx,SPI0_NSS_PINx,&GpioInitStruct); + Gpio_SetAfMode(SPI0_NSS_PORTx,SPI0_NSS_PINx,SPI0_NSS_AF); //配置SPI0_NSS + + Gpio_Init(SPI0_SCK_PORTx,SPI0_SCK_PINx,&GpioInitStruct); + Gpio_SetAfMode(SPI0_SCK_PORTx,SPI0_SCK_PINx,SPI0_SCK_AF); //配置SPI0_SCK + + Gpio_Init(SPI0_MOSI_PORTx,SPI0_MOSI_PINx,&GpioInitStruct); + Gpio_SetAfMode(SPI0_MOSI_PORTx,SPI0_MOSI_PINx,SPI0_MOSI_AF); //配置SPI0_MOSI + + GpioInitStruct.enDir = GpioDirIn; ///< 端口方向配置->输入 + + Gpio_Init(SPI0_MISO_PORTx,SPI0_MISO_PINx,&GpioInitStruct); + Gpio_SetAfMode(SPI0_MISO_PORTx, SPI0_MISO_PINx,SPI0_MISO_AF); //配置SPI0_MISO + + Sysctrl_SetPeripheralGate(SysctrlPeripheralSpi0,TRUE); ///< 打开SPI0外设时钟 + Reset_RstPeripheral0(ResetMskSpi0); ///<复位模块 + + //SPI0模块配置：主机 + SpiInitStruct.enSpiMode = SpiMskMaster; //配置位主机模式 + SpiInitStruct.enPclkDiv = SpiClkMskDiv4; //波特率：PCLK/4 + SpiInitStruct.enCPHA = SpiMskCphasecond; //第二边沿采样 + SpiInitStruct.enCPOL = SpiMskcpolhigh; //极性为高 + Spi_Init(M0P_SPI0, &SpiInitStruct); +} + +static void SPI1Init(void) +{ + stc_gpio_cfg_t GpioInitStruct; + stc_spi_cfg_t SpiInitStruct; + + DDL_ZERO_STRUCT(GpioInitStruct); + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio,TRUE); + + /************************** SPI1配置:主机-->LORA *******************************/ + GpioInitStruct.enDir = GpioDirOut; + + Gpio_Init(SPI1_NSS_PORTx,SPI1_NSS_PINx,&GpioInitStruct); + Gpio_SetAfMode(SPI1_NSS_PORTx,SPI1_NSS_PINx,SPI1_NSS_AF); //配置SPI1_NSS + + Gpio_Init(SPI1_SCK_PORTx,SPI1_SCK_PINx,&GpioInitStruct); + Gpio_SetAfMode(SPI1_SCK_PORTx,SPI1_SCK_PINx,SPI1_SCK_AF); //配置SPI1_SCK + + Gpio_Init(SPI1_MOSI_PORTx,SPI1_MOSI_PINx,&GpioInitStruct); + Gpio_SetAfMode(SPI1_MOSI_PORTx,SPI1_MOSI_PINx,SPI1_MOSI_AF); //配置SPI1_MOSI + + GpioInitStruct.enDir = GpioDirIn; ///< 端口方向配置->输入 + + Gpio_Init(SPI1_MISO_PORTx,SPI1_MISO_PINx,&GpioInitStruct); + Gpio_SetAfMode(SPI1_MISO_PORTx, SPI1_MISO_PINx,SPI1_MISO_AF); //配置SPI1_MISO + + Sysctrl_SetPeripheralGate(SysctrlPeripheralSpi1,TRUE); ///< 打开SPI0外设时钟 + Reset_RstPeripheral0(ResetMskSpi1); ///<复位模块 + + //SPI1模块配置：主机 + SpiInitStruct.enSpiMode = SpiMskMaster; //配置位主机模式 + SpiInitStruct.enPclkDiv = SpiClkMskDiv2; //波特率：PCLK/2 + SpiInitStruct.enCPHA = SpiMskCphasecond; //第二边沿采样 + SpiInitStruct.enCPOL = SpiMskcpolhigh; //极性为高 + Spi_Init(M0P_SPI1, &SpiInitStruct); +} + +uint8_t Spi0SendReceive(uint8_t sData) +{ + return Spi_RWByte(M0P_SPI0, sData); +} + +uint8_t Spi1SendReceive(uint8_t sData) +{ + return Spi_RWByte(M0P_SPI1, sData); +} +static void I2C0Init(void) +{ + stc_gpio_cfg_t stcGpioCfg; + stc_i2c_cfg_t stcI2cCfg; + + DDL_ZERO_STRUCT(stcI2cCfg); + DDL_ZERO_STRUCT(stcGpioCfg); + + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio,TRUE); //开启GPIO时钟门控 + + stcGpioCfg.enDir = GpioDirOut; ///< 端口方向配置->输出 + stcGpioCfg.enOD = GpioOdEnable; ///< 开漏输出 + stcGpioCfg.enPu = GpioPuEnable; ///< 端口上拉配置->使能 + stcGpioCfg.enPd = GpioPdDisable; ///< 端口下拉配置->禁止 + stcGpioCfg.bOutputVal = TRUE; + + Gpio_Init(I2C0_SCL_PORTx, I2C0_SCL_PINx, &stcGpioCfg); ///< 端口初始化 + Gpio_SetAfMode(I2C0_SCL_PORTx, I2C0_SCL_PINx, I2C0_SCL_AF); + + Gpio_Init(I2C0_SDA_PORTx, I2C0_SDA_PINx, &stcGpioCfg); + Gpio_SetAfMode(I2C0_SDA_PORTx, I2C0_SDA_PINx, I2C0_SDA_AF); + + Sysctrl_SetPeripheralGate(SysctrlPeripheralI2c0,TRUE); ///< 开启I2C0时钟门控 + + stcI2cCfg.u32Pclk = Sysctrl_GetPClkFreq(); ///< 获取PCLK时钟 + stcI2cCfg.u32Baud = 400000; ///< 1MHz + stcI2cCfg.enMode = I2cMasterMode; ///< 主机模式 + stcI2cCfg.u8SlaveAddr = 0xD5; ///< 从地址，主模式无效 + stcI2cCfg.bGc = FALSE; ///< 广播地址应答使能关闭 + I2C_Init(M0P_I2C0, &stcI2cCfg); ///< 模块初始化 +} + +static void I2C1Init(void) +{ + stc_gpio_cfg_t stcGpioCfg; + stc_i2c_cfg_t stcI2cCfg; + + DDL_ZERO_STRUCT(stcI2cCfg); + DDL_ZERO_STRUCT(stcGpioCfg); + + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio,TRUE); //开启GPIO时钟门控 + + stcGpioCfg.enDir = GpioDirOut; ///< 端口方向配置->输出 + stcGpioCfg.enOD = GpioOdEnable; ///< 开漏输出 + stcGpioCfg.enPu = GpioPuEnable; ///< 端口上拉配置->使能 + stcGpioCfg.enPd = GpioPdDisable; ///< 端口下拉配置->禁止 + stcGpioCfg.bOutputVal = TRUE; + + Gpio_Init(I2C1_SCL_PORTx, I2C1_SCL_PINx, &stcGpioCfg); ///< 端口初始化 + Gpio_SetAfMode(I2C1_SCL_PORTx, I2C1_SCL_PINx, I2C1_SCL_AF); + + Gpio_Init(I2C1_SDA_PORTx, I2C1_SDA_PINx, &stcGpioCfg); + Gpio_SetAfMode(I2C1_SDA_PORTx, I2C1_SDA_PINx, I2C1_SDA_AF); + + Sysctrl_SetPeripheralGate(SysctrlPeripheralI2c1,TRUE); ///< 开启I2C1时钟门控 + + stcI2cCfg.u32Pclk = Sysctrl_GetPClkFreq(); ///< 获取PCLK时钟 + stcI2cCfg.u32Baud = 400000; ///< 1MHz + stcI2cCfg.enMode = I2cMasterMode; ///< 主机模式 + stcI2cCfg.u8SlaveAddr = 0xD5; ///< 从地址，主模式无效 + stcI2cCfg.bGc = FALSE; ///< 广播地址应答使能关闭 + I2C_Init(M0P_I2C1, &stcI2cCfg); ///< 模块初始化 +} + + +static void WdtInit(void) +{ +#if (USE_WDT == 1) + ///< 开启WDT外设时钟 + Sysctrl_SetPeripheralGate(SysctrlPeripheralWdt,TRUE); + ///< WDT 初始化 + Wdt_Init(WdtResetEn, WdtT52s4); + Wdt_Start(); +#endif +} + +void FlashWrite(uint32_t Addr, uint32_t *wData, int wLen) +{ + while(Ok != Flash_SectorErase(Addr)); + for(int i = 0; i < wLen; i++) { + Flash_WriteWord(Addr + i * 4, wData[i]); + } +} + +void FlashRead(uint32_t Addr, uint32_t *rData, int rLen) +{ + uint32_t u32Addr = Addr; + for(int i = 0; i < rLen; i++) { + rData[i] = *((volatile uint32_t*)(u32Addr + i * 4)); + } +} +void FeedDog(void) +{ +#if (USE_WDT == 1) + Wdt_Feed(); +#endif +} +static uint8_t BCDToDec(uint8_t bcd) +{ + return ((bcd >> 4)& 0x0f) * 10 + (bcd & 0x0f); +} + +static uint8_t DecToBCD(uint8_t Dec) +{ + return (Dec / 10) << 4 | (Dec % 10); +} + +void TimeGet(struct tm *cTime) +{ + stc_rtc_time_t RtcDateTime; + + Rtc_ReadDateTime(&RtcDateTime); + cTime->tm_year = BCDToDec(RtcDateTime.u8Year) + 100; + cTime->tm_mon = BCDToDec(RtcDateTime.u8Month) - 1; + cTime->tm_mday = BCDToDec(RtcDateTime.u8Day); + cTime->tm_hour = BCDToDec(RtcDateTime.u8Hour) + 8; + cTime->tm_min = BCDToDec(RtcDateTime.u8Minute); + cTime->tm_sec = BCDToDec(RtcDateTime.u8Second); + cTime->tm_isdst = 0; +} + +uint32_t TimeTs(void) +{ + struct tm cTime; + + TimeGet(&cTime); + time_t cTimet = mktime(&cTime); + return cTimet; +} + +void TimeShow(uint32_t dwStamp) +{ + struct tm *stime; + stime = localtime(&dwStamp); + DBG_LOG("%d/",stime->tm_year + 1900); + DBG_LOG("%d/",stime->tm_mon + 1); + DBG_LOG("%d ",stime->tm_mday); + DBG_LOG("%d:",stime->tm_hour); + DBG_LOG("%d:",stime->tm_min); + DBG_LOG("%d\r\n",stime->tm_sec); +} + +void TimeSync(time_t ts) +{ + struct tm *td; + stc_rtc_time_t RtcDateTime; + + td = localtime(&ts); + + RtcDateTime.u8Year = DecToBCD(td->tm_year - 100); + RtcDateTime.u8Month = DecToBCD(td->tm_mon + 1); + RtcDateTime.u8Day = DecToBCD(td->tm_mday); + RtcDateTime.u8DayOfWeek = DecToBCD(td->tm_wday); + RtcDateTime.u8Hour = DecToBCD(td->tm_hour); + RtcDateTime.u8Minute = DecToBCD(td->tm_min); + RtcDateTime.u8Second = DecToBCD(td->tm_sec); + + Rtc_SetTime(&RtcDateTime); +} + +void PrintfMess(void) +{ + DBG_LOG("\r\n"); + uint32_t CT = TimeTs(); + TimeShow(CT); +#if(USE_LED == 1) + LED_ON(); +#endif +#if(USE_VBAT_AD == 1) + DBG_LOG("VBAT_Percentage:%d\r\n",VBAT_Percentage); +#endif +} +void DBGUartSendByte(uint8_t sData) +{ + Uart_SendDataPoll(M0P_UART0, sData); +} + +void LPUart0SendArray(uint8_t *sData, uint8_t sLen) +{ + RS485_CTRL_TX(); + for(int i = 0; i < sLen; i++) { + LPUart_SendData(M0P_LPUART0, sData[i]); + } + RS485_CTRL_RX(); +} + +uint32_t GetSysTick(void) +{ + return SysTickCnt; +} +void delay_us(uint32_t uS)//24MHz一个nop延时0.5us，12MHz延时1us +{ + uS *= 2; + while(uS--) + { + __NOP(); + } +} +void delay_ms(uint32_t mS) +{ + volatile uint32_t cTick, mTick; + + cTick = GetSysTick(); + while(1){ + mTick = GetSysTick(); + if(mTick - cTick >= mS) + break; + } +} + +void SysTick_IRQHandler(void) +{ + SysTickCnt++; + SysTick_CallBack(); +} + +void PortA_IRQHandler(void) +{ + +} +void PortB_IRQHandler(void) +{ + //LORA DIO0 + if(TRUE == Gpio_GetIrqStatus(LORA_DIO0_PORTx, LORA_DIO0_PINx)) { + Gpio_ClearIrq(LORA_DIO0_PORTx, LORA_DIO0_PINx); + Sx1276LoRaLoopHandler(); //lora + } + //LORA DIO1 + if(TRUE == Gpio_GetIrqStatus(LORA_DIO1_PORTx, LORA_DIO1_PINx)) { + Gpio_ClearIrq(LORA_DIO1_PORTx, LORA_DIO1_PINx); + } +} + +void PortC_IRQHandler(void) +{ + //加速度INT1 + if(TRUE == Gpio_GetIrqStatus(LSM6DSLTR_INT1_PORTx, LSM6DSLTR_INT1_PINx)) { + Gpio_ClearIrq(LSM6DSLTR_INT1_PORTx, LSM6DSLTR_INT1_PINx); + Lsm6dsInt1CallBack(); + } + + //地磁INT + if(TRUE == Gpio_GetIrqStatus(MMC5983MA_INT_PORTx, MMC5983MA_INT_PINx)) { + Gpio_ClearIrq(MMC5983MA_INT_PORTx, MMC5983MA_INT_PINx); + MMC5983IntCallBack(); + } +} +///CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + //< LORA + Sx1276LoRaSleep();//Lora睡眠 + LORAIntDisable();//关闭LORA中断 + + ACCandMMCIntDisable();//关闭加速度和地磁中断 + +#if (USE_VBAT_AD == 1)//< AD + AD_OFF(); + Sysctrl_SetPeripheralGate(SysctrlPeripheralAdcBgr, TRUE); + Sysctrl_ClkSourceEnable(SysctrlClkPLL,FALSE); + Bgr_BgrDisable(); ///< 关闭BGR + Sysctrl_SetPeripheralGate(SysctrlPeripheralAdcBgr, FALSE); + Adc_SGL_Stop();//关闭单次采样 +#endif + +#if (USE_SPI0 == 1) + Sysctrl_SetPeripheralGate(SysctrlPeripheralSpi0,FALSE);//关闭SPI0外设时钟 +#endif +#if (USE_UART0 == 1) + EnableNvic(UART0_2_IRQn, IrqLevel3, false); + Sysctrl_SetPeripheralGate(SysctrlPeripheralUart0,FALSE); //关闭UART0时钟 +#endif + + DeepSleepGPIOCfg(); + Lpm_GotoDeepSleep(FALSE); +} + +void WakeUpInit(void) +{ + SystemClkDivInit(); + SystemClkInit(SysctrlRchFreq24MHz); + GPIOInit(); + +#if (USE_VBAT_AD == 1)//< AD + AD_ON(); + AdcInit(); +#endif +#if (USE_UART0 == 1) + Uart0Init(); +#endif +#if (USE_SPI0 == 1) + SPI0Init(); +#endif +#if (USE_WDT == 1)//< WDT + WdtInit(); +#endif + + LORAIntEnable();//开启LORA中断 + Sx1276LoRaWakeup();//LORA唤醒 + ACCandMMCIntEnable();//开启加速度和地磁中断 + + SysTick_Config(SystemCoreClock/1000); +} + +void SystemReset(void) +{ + NVIC_SystemReset(); +} + +void BspInit(void) +{ + SystemClkDivInit(); + SystemClkInit(SysctrlRchFreq24MHz); + GPIOInit(); + +#if (USE_VBAT_AD == 1)//< AD + AD_ON(); + AdcInit(); +#endif +#if (USE_UART0 == 1)//< DEBUG + Uart0Init(); +#endif +#if (USE_RTC == 1)//< RTC + RTCInit(30); +#endif +#if (USE_WDT == 1)//< WDT + WdtInit(); +#endif +#if (USE_SPI0 == 1) + SPI0Init(); +#endif +#if (USE_SPI1 == 1) + SPI1Init(); +#endif +#if (USE_LPUART0 == 1)//< LPUART0 + LpUart0Init(); +#endif +#if(USE_I2C0 == 1) + I2C0Init(); +#endif +#if(USE_I2C1 == 1) + I2C1Init(); +#endif + + SysTick_Config(SystemCoreClock/1000); + while(Ok != Flash_Init(6, TRUE)); +} \ No newline at end of file diff --git a/source/src/main.c b/source/src/main.c new file mode 100644 index 0000000..3475a40 --- /dev/null +++ b/source/src/main.c @@ -0,0 +1,571 @@ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include +#include "main.h" +#include "UartDebug.h" +#include "bsp.h" +#include "Algorithm.h" +#include "SGCP.h" +#include "Update.h" +#include "sx127x.h" +#include "lsm6dsl_app.h" +#include "mmc5983.h" + + +#define SOFTWARE_VERSION 11 //杞欢鐗堟湰 +#define HARDWARE_VERSION 11 //纭欢鐗堟湰 + +AppDetect_t App; + +extern uint8_t LocalMAC[6]; //鏈満MAC鍦板潃 +extern uint8_t GatewayMAC[6]; //缃戝叧MAC鍦板潃锛屾敞鍐屾椂鍏ㄤ负0 +extern uint8_t LocalDataPack[sizeof(SGCP.DevData.LaserTracing)]; //鏈満鏁版嵁鍖 //鏈満鏁版嵁鍖 + +void Lsm6dDataProcessCallBack(float *Acc, float *Gy) +{ + memcpy(App.Sensor.acce, Acc, 12); + memcpy(App.Sensor.gy, Gy, 12); + //DBG_LOG("acc_X:%07.1f, acc_Y:%07.1f, acc_Z:%07.1f\r\n", App.Sensor.acce[X], App.Sensor.acce[Y],App.Sensor.acce[Z]); + //DBG_LOG("gy_X:%07.1f, gy_Y:%07.1f, gy_Z:%07.1f\r\n", App.Sensor.gy[X], App.Sensor.gy[Y],App.Sensor.gy[Z]); + App.AccRead_EndFlag = true; +} + +void MmcDataProcessCallBack(float *Mag) +{ + memcpy(App.Sensor.mag, Mag, 12); + //DBG_LOG("mag_X:%07.1f, mag_Y:%07.1f, mag_Z:%07.1f\r\n", App.Sensor.mag[X], App.Sensor.mag[Y],App.Sensor.mag[Z]); + App.MagRead_EndFlag = true; +} + +static void AppInit(void) +{ + memset(&App, 0x00, sizeof(App)); + READ_APP_PARA((uint32_t *)&App.Para); + +#if(USE_BOOTLOADER == 1) + UpdateInit(); + + if(App.Para.FactoryFlag != 0x00) + { + App.Para.FactoryFlag = 0x00; + /*鏍″噯鍙傛暟鍒濆鍖*/ + App.Para.CaliPara.PitchZero = 0; + App.Para.CaliPara.RollZero = 0; + App.Para.CaliPara.YawZero = 0; + SAVE_APP_PARA((uint32_t *)&App.Para); + } +#endif + + if(App.Para.RS485Addr > 16 || App.Para.RS485Addr < 1){ + App.Para.RS485Addr = 1; + } + if(App.Para.Layout.CollectTime > 240 || App.Para.Layout.CollectTime < 1) { + App.Para.Layout.CollectTime = 10; + } + if(App.Para.Layout.ReportInterval > 1440 || App.Para.Layout.ReportInterval < 10) { + App.Para.Layout.ReportInterval = 40; + } + if(App.Para.Layout.ERInterval > 10 || App.Para.Layout.ERInterval < 2) { + App.Para.Layout.ERInterval = 4; + } + if(App.Para.Layout.ERTime > 240 || App.Para.Layout.ERTime < 20) { + App.Para.Layout.ERTime = 40; + } + + DBG_LOG("\r\n\r\n"); + DBG_LOG("****************************************************\r\n"); + DBG_LOG("** **\r\n"); + DBG_LOG("** LaserTracing **\r\n"); + DBG_LOG("** SoftWare V:%d.%d **\r\n", SOFTWARE_VERSION / 10, SOFTWARE_VERSION % 10); + DBG_LOG("** HardWare V:%d.%d **\r\n", HARDWARE_VERSION / 10, HARDWARE_VERSION % 10); + DBG_LOG("** Compile: %s %s **\r\n", __DATE__, __TIME__); + DBG_LOG("** **\r\n"); + DBG_LOG("****************************************************\r\n\r\n"); + DBG_LOG("RS485Addr: %02X\r\n",App.Para.RS485Addr); + DBG_LOG("LocalMAC: %02X %02X %02X %02X %02X %02X\r\n",LocalMAC[0], LocalMAC[1], LocalMAC[2], LocalMAC[3], LocalMAC[4], LocalMAC[5]); + DBG_LOG("CollectTime: %ds\r\n\r\n",(App.Para.Layout.CollectTime*30)); + + LORAIntEnable(); + Sx1276LoRaInit(LORA_RxCallBack); //< LORA鑺墖鍒濆鍖 + FeedDog(); + + Lsm6dslInit(); + MMC5983Init(); + MMC5983Stop(); + Lsm6dsStop(); + ACCandMMCIntEnable(); + + LPTimer0_OFF(); + + uint32_t seed = 0;//< 闅忔満鏁板垵濮嬪寲 + seed = seed + LocalMAC[2]; + seed = (seed << 8) + LocalMAC[3]; + seed = (seed << 8) + LocalMAC[4]; + seed = (seed << 8) + LocalMAC[5]; + srand(seed); + App.Nonce = rand(); + + SGCP.LoginOk = false; + SGCP.LoginMess = false; + SGCP.LaserOnOff = false; + SGCP.MasterCaliOk = true; + SGCP.DeviceReadDataOk = false; + SGCP.TimingAcquisition = false; + + App.Login2Min30SCount = 0; + App.Login30MinCount = 0; + App.RepeLoginCount = 0; + App.LoginFlag = false; + App.Login_RTC = false; + App.Login_LPTimer0 = true; + //LPTimer0_ON((App.Nonce % 1200) + 300);//瀹氭椂30s+闅忔満2鍒嗛挓锛屾渶灏忛棿闅100ms + LPTimer0_ON(50); + DBG_LOG("Login LPTimer0 Open\r\n"); + + App.Upload45S10SCount = 0; + App.UploadFlag = false; + App.Upload_LPTimer0 = false; + + App.Coll_N = 0; + App.Repor_N = 0; + App.ERInterval_N = 0; + App.ERTime_N = 0; + App.ERFlag = false; + + App.MagRead_EndFlag = false; + App.AccRead_EndFlag = false; + App.UpdateOk = false; + App.CaliFlag = false; + App.LaserFlag = false; + + App.Status = APP_STATUS_ON; + App.TD1mSDelayCnt = (App.Nonce % 2000) + 2000; +} + +static void ReadDataLoopHandler(void) +{ + switch (App.RDStatus) + { + case READDATA_STATUS_IDLE:{ + break;} + + case READDATA_STATUS_UPDAING:{ + DBG_LOG("<------------ Sensor Data Updaing ------------> \r\n"); + App.UpdateOk = false; + Lsm6dsStart(); + MMC5983Start(); + App.ReadData1mSDelayCnt = 2000; + App.RDStatus = READDATA_STATUS_WAIT_UPDAING; + break;} + + case READDATA_STATUS_WAIT_UPDAING:{ + if(App.ReadData1mSDelayCnt <= 0){ + if(App.AccRead_EndFlag == false) + DBG_LOG("Lsm6dsl Get Data TimeOut...\r\n"); + if(App.MagRead_EndFlag == false) + DBG_LOG("MMC5983 Get Data TimeOut...\r\n"); + App.RDStatus = READDATA_STATUS_DATA_HANDLE; + } + else if(App.MagRead_EndFlag == true + && App.AccRead_EndFlag == true){ + App.RDStatus = READDATA_STATUS_DATA_HANDLE; + } + break;} + + case READDATA_STATUS_DATA_HANDLE:{ + if(App.MagRead_EndFlag == false || App.AccRead_EndFlag == false){ + DBG_LOG("<------------ Sensor Data Upda End ------------> \r\n"); + App.RDStatus = READDATA_STATUS_IDLE; + App.UpdateOk = false; + break; + } + App.MagRead_EndFlag = false; + App.AccRead_EndFlag = false; + + IMU_Update(0, App.Sensor.acce, App.Sensor.mag, &App.AHRSData.Rad, &App.AHRSData.Deg); + App.ConvertedData.Pitch = (int16_t)(App.AHRSData.Deg.pitch * 10); + App.ConvertedData.Roll = (int16_t)(App.AHRSData.Deg.roll * 10); + App.ConvertedData.Yaw = (int16_t)(App.AHRSData.Deg.yaw * 10); + DBG_LOG("PitchAngle:%06.1f, RollAngle:%06.1f, YawAngle:%06.1f\r\n",App.AHRSData.Deg.pitch, App.AHRSData.Deg.roll, App.AHRSData.Deg.yaw); + + if(SGCP.MasterCaliOk == true) + { + SGCP.MasterCaliOk = false; + App.CaliFlag = true; + App.Para.CaliPara.PitchZero = App.ConvertedData.Pitch; + App.Para.CaliPara.RollZero = App.ConvertedData.Roll; + App.Para.CaliPara.YawZero = App.ConvertedData.Yaw; +// App.Para.CaliPara.PitchZero = 0; +// App.Para.CaliPara.RollZero = 0; +// App.Para.CaliPara.YawZero = 0; + SAVE_APP_PARA((uint32_t *)&App.Para); + } + if(App.CaliFlag == true && App.ERFlag == false) + { + int16_t PitchDiff,RollDiff; + PitchDiff = App.ConvertedData.Pitch - App.Para.CaliPara.PitchZero; + RollDiff = App.ConvertedData.Roll - App.Para.CaliPara.RollZero; + if((PitchDiff > ERINTERVAL_VPT) || (RollDiff > ERINTERVAL_VPT)) + { + //瑙﹀彂绱фヤ笂鎶 + App.ERFlag = true; + DBG_LOG("PitchDiff=%04d, PitchDiff=%04d\r\n", PitchDiff,RollDiff); + DBG_LOG("Start emergency reporting!\r\n"); + DBG_LOG("ERInterval: %dMin, ERTime: %dMin\r\n", App.Para.Layout.ERInterval/2, App.Para.Layout.ERTime/2); + } + } + + SGCP.DevData.LaserTracing.PitchAngle = App.ConvertedData.Pitch; + SGCP.DevData.LaserTracing.RollAngle = App.ConvertedData.Roll; + SGCP.DevData.LaserTracing.YawAngle = App.ConvertedData.Yaw; + +#if (USE_VBAT_AD == 1) + SGCP.DevData.LaserTracing.MasterDev.BatLevel = VBAT_Percentage; +#else + SGCP.DevData.LaserTracing.MasterDev.BatLevel = 0x00; +#endif +#if (SGCP_SELECT == 1 || SGCP_SELECT == 2) + SX1276LoCalcRssiSnr(&SGCP.DevData.LaserTracing.MasterDev.RSSI, &SGCP.DevData.LaserTracing.MasterDev.Nsr);//鑾峰彇淇″彿寮哄害 +#else + SGCP.DevData.LaserTracing.MasterDev.RSSI = 0x00; + SGCP.DevData.LaserTracing.MasterDev.Nsr = 0x00; +#endif + + memcpy(LocalDataPack, &SGCP.DevData.LaserTracing, sizeof(LocalDataPack)); + DBG_LOG("<------------ Sensor Data Upda End ------------> \r\n"); + //App.RDStatus = READDATA_STATUS_UPDAING;//鎸佺画宸ヤ綔 + App.RDStatus = READDATA_STATUS_IDLE; + App.UpdateOk = true; + break;} + } +} + +static void AppLoopHandler(void) +{ + switch(App.Status) { + case APP_STATUS_IDLE:{ + break;} + + case APP_STATUS_SLEEP:{ + DBG_LOG("Sleep...\r\n\n\n"); + FeedDog(); + EnterDeepSleep(); + FeedDog(); + + WakeUpInit(); + App.Status = APP_STATUS_ON; + break;} + + case APP_STATUS_ON:{ + if(App.TD1mSDelayCnt <= 0){ + App.TD1mSDelayCnt = 1000;//鍞ら啋鍚庡緟鏈烘椂闂 + App.Status = APP_STATUS_ACTION; + } + break;} + + case APP_STATUS_OFF:{ + LED_OFF(); + App.Status = APP_STATUS_SLEEP; + DBG_LOG("Power Off...\r\n"); + break;} + + case APP_STATUS_ACTION:{ + if(SGCP.InStatus != IN_STATUS_IDLE){ + break; + } + else if(SGCP.LoginOk == false && App.LoginFlag == true && SGCP.GWStatus == GW_STATUS_IDLE)//璁惧娉ㄥ唽 + { + PrintfMess(); + App.LoginFlag = false; + LPTimer0_OFF();//鍏抽棴浣庡姛鑰楀畾鏃跺櫒 + SGCP.GWStatus = GW_STATUS_LOGIN;//娉ㄥ唽 + App.Status = APP_STATUS_WAIT_LOGIN; + } + else if(SGCP.TimingAcquisition == true && App.RDStatus == READDATA_STATUS_IDLE)//璁惧鏁版嵁鑾峰彇 + { + PrintfMess(); + SGCP.TimingAcquisition = false; + App.RDStatus = READDATA_STATUS_UPDAING; + App.Status = APP_STATUS_ACTION; + App.TD1mSDelayCnt = 1000; + } + else if(SGCP.LoginOk == true && App.UploadFlag == true && SGCP.GWStatus == GW_STATUS_IDLE && App.UpdateOk == true) + { + PrintfMess(); + App.UploadFlag = false; + LPTimer0_OFF();//鍏抽棴浣庡姛鑰楀畾鏃跺櫒 + SGCP.GWStatus = GW_STATUS_UPLOAD_SENSOR;//涓婁紶 + App.Status = APP_STATUS_WAIT_UPLOAD; + } + else if(App.RDStatus == READDATA_STATUS_IDLE + && SGCP.GWStatus == GW_STATUS_IDLE + && SGCP.InStatus == IN_STATUS_IDLE + && SGCP.TimingAcquisition == false + && App.TD1mSDelayCnt == 0 + && App.ReadData1mSDelayCnt == 0 + && SGCP.LaserOnOff == false + && App.TestTimeCnt == 0) + { + //App.Status = APP_STATUS_ACTION;//鎸佺画宸ヤ綔 + App.Status = APP_STATUS_OFF; + } + else if(App.LaserFlag == true) + { + App.LaserFlag = false; + App.TestTimeCnt = 3000; + LASER1_ON(); + } + break;} + + case APP_STATUS_WAIT_LOGIN:{ + if(SGCP.LoginMess == true) + { + if(SGCP.LoginOk == false) + { + App.Login2Min30SCount++; + if(App.Login2Min30SCount >= 3) + { + PrintfMess(); + DBG_LOG("Number of registration failures:%d\r\n",App.Login2Min30SCount); + DBG_LOG("Login RTC Open\r\n"); + App.Login2Min30SCount = 0; + App.Login30MinCount = 0; + App.Login_RTC = true;//鍚姩30鍒嗘敞鍐屽畾鏃跺櫒 + } + else + { + PrintfMess(); + App.Login_LPTimer0 = true; + LPTimer0_ON((App.Nonce % 1200) + 300);//瀹氭椂30s+闅忔満2鍒嗛挓锛屾渶灏忛棿闅100ms + //LPTimer0_ON(100);//瀹氭椂10s + DBG_LOG("Number of registration failures:%d\r\n",App.Login2Min30SCount); + DBG_LOG("Login LPTimer0 Open\r\n"); + } + } + else if(SGCP.LoginOk == true) + { + App.Login2Min30SCount = 0; + App.Login30MinCount = 0; + App.Upload45S10SCount = 0; + App.UploadFlag = true; + App.RDStatus = READDATA_STATUS_UPDAING; + } + SGCP.LoginMess = false; + App.TD1mSDelayCnt = 1000; + App.Status = APP_STATUS_ACTION; + } + break;} + + case APP_STATUS_WAIT_UPLOAD:{ + if(SGCP.UploadMess == true) + { + if(SGCP.UploadOk == false) + { + App.Upload45S10SCount++; + if((App.Upload45S10SCount%3) == 0) + { + PrintfMess(); + DBG_LOG("Number of failed uploads:%d\r\n",App.Upload45S10SCount); + if(App.Upload45S10SCount >= 9) + { + DBG_LOG("Resend registration information.\r\n"); + SGCP.LoginOk = false; + App.LoginFlag = true; + } + } + else + { + PrintfMess(); + App.Upload_LPTimer0 = true; + LPTimer0_ON((App.Nonce % 100) + 45);//闅忔満寤舵椂100~10000ms+45绉掑悗閲嶆柊鍙戦 + //LPTimer0_ON(100);//瀹氭椂10s + DBG_LOG("Number of failed uploads:%d\r\n",App.Upload45S10SCount); + DBG_LOG("Upload LPTimer0 Open\r\n"); + } + } + else if(SGCP.UploadOk == true) + { + App.Upload45S10SCount = 0; + } + SGCP.UploadMess = false; + App.TD1mSDelayCnt = 1000; + App.Status = APP_STATUS_ACTION; + } + break;} + } +} + +static void App1mSRoutine(void) +{ + if(App.TD1mSDelayCnt > 0) + App.TD1mSDelayCnt--; + if(App.ReadData1mSDelayCnt > 0) + App.ReadData1mSDelayCnt--; + App.FeedDogDlyCnt++; + if(App.TestTimeCnt > 0) + { + App.TestTimeCnt--; + if(App.TestTimeCnt <= 0) + { + LASER1_OFF(); + } + } +} + +void FeedDogHandler(void) +{ + if(App.FeedDogDlyCnt >= 200) { + FeedDog(); + App.FeedDogDlyCnt = 0; + } +} + +void SystemResetHandler(void) +{ + //绯荤粺瀹氭椂閲嶅惎 + if(App.SysResetTimeCnt > SYSTEM_TIMING_LOGIN) { + delay_ms(5); + SystemReset(); + while(1); + } +} + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample + ** + ******************************************************************************/ +int32_t main(void) +{ + BspInit(); + delay_ms(3000);//涓婄數寤舵椂锛岀瓑寰呬粠璁惧鍚姩 + AppInit(); + + while (1) { +#if(USE_VBAT_AD == 1) + ADCLoopHandler(); +#endif +#if(USE_WDT == 1) + FeedDogHandler(); +#endif +#if(USE_DEBUG == 1) + DebugLoopHandler(); +#endif + Lsm6dslLoopHandler(); + MMC5983LoopHandler(); + ReadDataLoopHandler(); + GwRevLoopHandler(); + InRevLoopHandler(); + AppLoopHandler(); + } +} +/******************************************************************************* + * 涓柇鍥炶皟鍑芥暟 + ******************************************************************************/ +void SysTick_CallBack(void) +{ + App1mSRoutine(); + SGCP1mSRoutine(); + Debug1mSRoutine(); + Lsm6dsl1mSRoutine(); + MMC59831mSRoutine(); +} + +void RtcIRQHander(void) +{ + //SGCP.TimingAcquisition = true; //30S鏇存柊涓娆℃暟鎹 +#if USE_LORA_CH == 0 + App.Tcnt++;//涓鍒嗛挓寮鍚縺鍏3绉 + if(App.Tcnt >= 2) + { + App.Tcnt = 0; + App.LaserFlag = true; + } +#endif + if(SGCP.LoginOk == true) + { + App.RepeLoginCount++; + if(App.RepeLoginCount >= SYSTEM_TIMING_LOGIN){ + DBG_LOG("24h Repetition Login\r\n"); + App.RepeLoginCount = 0; + SGCP.LoginOk = false;//24h閲嶅娉ㄥ唽 + App.Login2Min30SCount = 0; + App.Login30MinCount = 0; + App.Login_RTC = false;//鍏抽棴30鍒嗘敞鍐屽畾鏃跺櫒 + + LPTimer0_ON((App.Nonce % 1200) + 300);//瀹氭椂30s+闅忔満2鍒嗛挓锛屾渶灏忛棿闅100ms + DBG_LOG("Login LPTimer0 Open\r\n"); + } + + App.Coll_N++; + if(App.Coll_N >= App.Para.Layout.CollectTime) + { + App.Coll_N = 0; + SGCP.TimingAcquisition = true; //瀹氭椂鏇存柊鏁版嵁 + } + + if(App.ERFlag == true) + { + App.ERInterval_N++; + App.ERTime_N++; + if(App.ERInterval_N >= App.Para.Layout.ERInterval) + { + App.ERInterval_N = 0; + App.UploadFlag = true; + } + if(App.ERTime_N >= App.Para.Layout.ERTime) + { + App.ERTime_N = 0; + App.ERFlag = false; + SGCP.MasterCaliOk = true;//绱фヤ笂鎶ユ椂闂寸粨鏉燂紝閲嶆柊鏍″噯鍙傛暟 + } + } + else{ + App.Repor_N++; + if(App.Repor_N >= App.Para.Layout.ReportInterval) + { + App.Repor_N = 0; + App.UploadFlag = true; + } + } + } + + if(App.Login_RTC == true) + { + App.Login30MinCount++; + if(App.Login30MinCount >= ERR_TIMING_LOGIN)//30鍒嗛挓閲嶇疆娉ㄥ唽閿欒淇℃伅 + { + PrintfMess(); + App.Login30MinCount = 0; + App.Login_RTC = false;//鍏抽棴30鍒嗘敞鍐屽畾鏃跺櫒 + DBG_LOG("Login RTC Close\r\n"); + + App.Login_LPTimer0 = true; + LPTimer0_ON((App.Nonce % 1200) + 300);//瀹氭椂30s+闅忔満2鍒嗛挓锛屾渶灏忛棿闅100ms + //LPTimer0_ON(100);//瀹氭椂10s + DBG_LOG("Login LPTimer0 Open\r\n"); + } + } +} +void LPTimer0IRQHander(void) +{ + if(App.Login_LPTimer0 == true) + { + App.Login_LPTimer0 = false; + App.LoginFlag = true; + } + if(App.Upload_LPTimer0 == true) + { + App.Upload_LPTimer0 = false; + App.UploadFlag = true; + } +} + + +