修复源代码中文注释乱码并统一为UTF-8编码,Lora频率改为470MHz频段

1. 修复 source/inc/bsp.h、source/inc/main.h、source/src/bsp.c 中文注释乱码,统一保存为UTF-8编码
2. Lora中心频率由433.1MHz改为470.1MHz~492.6MHz,步进500kHz,共46个信道(CH0~CH45)
3. 新增下载前配置检查注释块,LORA_FREQ默认信道改为CH0
4. 更新Keil调试配置(CMSIS_AGDI调试器及观察窗口设置)
This commit is contained in:
2026-09-02 12:55:16 +08:00
parent 2b23e8f0ed
commit 483114547f
4 changed files with 157 additions and 128 deletions
+4 -14
View File
@@ -103,7 +103,7 @@
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>6</nTsel>
<nTsel>12</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@@ -114,7 +114,7 @@
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
@@ -130,7 +130,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U4294967295 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8027 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L17X_128K.FLM -FS00 -FL020000 -FP0($$Device:HC32L170JATA$Flash\FlashHC32L17X_128K.FLM)</Name>
<Name>-U4294967295 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8027 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L17X_128K.FLM -FS00 -FL020000 -FP0($$Device:HC32L170JATA$Flash\FlashHC32L17X_128K.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@@ -190,16 +190,6 @@
<WinNumber>1</WinNumber>
<ItemText>BL.Status,0x0A</ItemText>
</Ww>
<Ww>
<count>7</count>
<WinNumber>1</WinNumber>
<ItemText>BL.Para</ItemText>
</Ww>
<Ww>
<count>8</count>
<WinNumber>1</WinNumber>
<ItemText>DevMac</ItemText>
</Ww>
</WatchWindow1>
<MemoryWindow1>
<Mm>
@@ -223,7 +213,7 @@
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>