diff --git a/MDK/.vscode/c_cpp_properties.json b/MDK/.vscode/c_cpp_properties.json
new file mode 100644
index 0000000..6d95022
--- /dev/null
+++ b/MDK/.vscode/c_cpp_properties.json
@@ -0,0 +1,428 @@
+{
+ "configurations": [
+ {
+ "name": "HC32L17X",
+ "includePath": [
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\mcu\\common",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\source",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\driver\\inc",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\source\\inc",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\Module\\LIS2HH12",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\Module\\Debug",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\Module\\GPS",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\Module\\spl06",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\Module\\CAT1",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\Module\\WH-BLE106",
+ "D:\\keil5\\ARM\\ARMCLANG\\include",
+ "D:\\keil5\\ARM\\ARMCLANG\\include\\arm_linux",
+ "D:\\keil5\\ARM\\ARMCLANG\\include\\arm_linux_compat",
+ "D:\\keil5\\ARM\\ARMCLANG\\include\\libcxx",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\MDK",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\source\\Src",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\source\\src",
+ "d:\\keilProject\\HC32L170\\projects\\Local\\HC32L170BootloaderGeneral\\driver\\src"
+ ],
+ "defines": [
+ "__alignof__(x)=",
+ "__asm(x)=",
+ "__asm__(x)=",
+ "__forceinline=",
+ "__restrict=",
+ "__volatile__=",
+ "__inline=",
+ "__inline__=",
+ "__declspec(x)=",
+ "__attribute__(x)=",
+ "__nonnull__(x)=",
+ "__unaligned=",
+ "__promise(x)=",
+ "__irq=",
+ "__swi=",
+ "__weak=",
+ "__register=",
+ "__pure=",
+ "__value_in_regs=",
+ "__breakpoint(x)=",
+ "__current_pc()=0U",
+ "__current_sp()=0U",
+ "__disable_fiq()=",
+ "__disable_irq()=",
+ "__enable_fiq()=",
+ "__enable_irq()=",
+ "__force_stores()=",
+ "__memory_changed()=",
+ "__schedule_barrier()=",
+ "__semihost(x,y)=0",
+ "__vfp_status(x,y)=0",
+ "__builtin_arm_nop()=",
+ "__builtin_arm_wfi()=",
+ "__builtin_arm_wfe()=",
+ "__builtin_arm_sev()=",
+ "__builtin_arm_sevl()=",
+ "__builtin_arm_yield()=",
+ "__builtin_arm_isb(x)=",
+ "__builtin_arm_dsb(x)=",
+ "__builtin_arm_dmb(x)=",
+ "__builtin_bswap32(x)=0U",
+ "__builtin_bswap16(x)=0U",
+ "__builtin_arm_rbit(x)=0U",
+ "__builtin_clz(x)=0U",
+ "__builtin_arm_ldrex(x)=0U",
+ "__builtin_arm_strex(x,y)=0U",
+ "__builtin_arm_clrex()=",
+ "__builtin_arm_ssat(x,y)=0U",
+ "__builtin_arm_usat(x,y)=0U",
+ "__builtin_arm_ldaex(x)=0U",
+ "__builtin_arm_stlex(x,y)=0U",
+ "_ILP32=1",
+ "_USE_STATIC_INLINE=1",
+ "__APCS_32__=1",
+ "__ARMCC_VERSION=6160001",
+ "__ARMCOMPILER_VERSION=6160001",
+ "__ARMEL__=1",
+ "__ARM_32BIT_STATE=1",
+ "__ARM_ACLE=200",
+ "__ARM_ARCH=4",
+ "__ARM_ARCH_4T__=1",
+ "__ARM_ARCH_ISA_ARM=1",
+ "__ARM_ARCH_ISA_THUMB=1",
+ "__ARM_EABI__=1",
+ "__ARM_FP16_ARGS=1",
+ "__ARM_FP16_FORMAT_IEEE=1",
+ "__ARM_NO_IMAGINARY_TYPE=1",
+ "__ARM_PCS=1",
+ "__ARM_PROMISE=__builtin_assume",
+ "__ARM_SIZEOF_MINIMAL_ENUM=4",
+ "__ARM_SIZEOF_WCHAR_T=4",
+ "__ARM_TARGET_COPROC=1",
+ "__ARM_TARGET_COPROC_V4=1",
+ "__ATOMIC_ACQUIRE=2",
+ "__ATOMIC_ACQ_REL=4",
+ "__ATOMIC_CONSUME=1",
+ "__ATOMIC_RELAXED=0",
+ "__ATOMIC_RELEASE=3",
+ "__ATOMIC_SEQ_CST=5",
+ "__BIGGEST_ALIGNMENT__=8",
+ "__BYTE_ORDER__=__ORDER_LITTLE_ENDIAN__",
+ "__CHAR16_TYPE__=unsigned short",
+ "__CHAR32_TYPE__=unsigned int",
+ "__CHAR_BIT__=8",
+ "__CHAR_UNSIGNED__=1",
+ "__CLANG_ATOMIC_BOOL_LOCK_FREE=1",
+ "__CLANG_ATOMIC_CHAR16_T_LOCK_FREE=1",
+ "__CLANG_ATOMIC_CHAR32_T_LOCK_FREE=1",
+ "__CLANG_ATOMIC_CHAR_LOCK_FREE=1",
+ "__CLANG_ATOMIC_INT_LOCK_FREE=1",
+ "__CLANG_ATOMIC_LLONG_LOCK_FREE=1",
+ "__CLANG_ATOMIC_LONG_LOCK_FREE=1",
+ "__CLANG_ATOMIC_POINTER_LOCK_FREE=1",
+ "__CLANG_ATOMIC_SHORT_LOCK_FREE=1",
+ "__CLANG_ATOMIC_WCHAR_T_LOCK_FREE=1",
+ "__CONSTANT_CFSTRINGS__=1",
+ "__DBL_DECIMAL_DIG__=17",
+ "__DBL_DENORM_MIN__=4.9406564584124654e-324",
+ "__DBL_DIG__=15",
+ "__DBL_EPSILON__=2.2204460492503131e-16",
+ "__DBL_HAS_DENORM__=1",
+ "__DBL_HAS_INFINITY__=1",
+ "__DBL_HAS_QUIET_NAN__=1",
+ "__DBL_MANT_DIG__=53",
+ "__DBL_MAX_10_EXP__=308",
+ "__DBL_MAX_EXP__=1024",
+ "__DBL_MAX__=1.7976931348623157e+308",
+ "__DBL_MIN_10_EXP__=(-307)",
+ "__DBL_MIN_EXP__=(-1021)",
+ "__DBL_MIN__=2.2250738585072014e-308",
+ "__DECIMAL_DIG__=__LDBL_DECIMAL_DIG__",
+ "__ELF__=1",
+ "__ESCAPE__=",
+ "__FINITE_MATH_ONLY__=1",
+ "__FLT16_DECIMAL_DIG__=5",
+ "__FLT16_DENORM_MIN__=5.9604644775390625e-8F16",
+ "__FLT16_DIG__=3",
+ "__FLT16_EPSILON__=9.765625e-4F16",
+ "__FLT16_HAS_DENORM__=1",
+ "__FLT16_HAS_INFINITY__=1",
+ "__FLT16_HAS_QUIET_NAN__=1",
+ "__FLT16_MANT_DIG__=11",
+ "__FLT16_MAX_10_EXP__=4",
+ "__FLT16_MAX_EXP__=16",
+ "__FLT16_MAX__=6.5504e+4F16",
+ "__FLT16_MIN_10_EXP__=(-4)",
+ "__FLT16_MIN_EXP__=(-13)",
+ "__FLT16_MIN__=6.103515625e-5F16",
+ "__FLT_DECIMAL_DIG__=9",
+ "__FLT_DENORM_MIN__=1.40129846e-45F",
+ "__FLT_DIG__=6",
+ "__FLT_EPSILON__=1.19209290e-7F",
+ "__FLT_EVAL_METHOD__=0",
+ "__FLT_HAS_DENORM__=1",
+ "__FLT_HAS_INFINITY__=1",
+ "__FLT_HAS_QUIET_NAN__=1",
+ "__FLT_MANT_DIG__=24",
+ "__FLT_MAX_10_EXP__=38",
+ "__FLT_MAX_EXP__=128",
+ "__FLT_MAX__=3.40282347e+38F",
+ "__FLT_MIN_10_EXP__=(-37)",
+ "__FLT_MIN_EXP__=(-125)",
+ "__FLT_MIN__=1.17549435e-38F",
+ "__FLT_RADIX__=2",
+ "__GCC_ATOMIC_BOOL_LOCK_FREE=1",
+ "__GCC_ATOMIC_CHAR16_T_LOCK_FREE=1",
+ "__GCC_ATOMIC_CHAR32_T_LOCK_FREE=1",
+ "__GCC_ATOMIC_CHAR_LOCK_FREE=1",
+ "__GCC_ATOMIC_INT_LOCK_FREE=1",
+ "__GCC_ATOMIC_LLONG_LOCK_FREE=1",
+ "__GCC_ATOMIC_LONG_LOCK_FREE=1",
+ "__GCC_ATOMIC_POINTER_LOCK_FREE=1",
+ "__GCC_ATOMIC_SHORT_LOCK_FREE=1",
+ "__GCC_ATOMIC_TEST_AND_SET_TRUEVAL=1",
+ "__GCC_ATOMIC_WCHAR_T_LOCK_FREE=1",
+ "__GNUC_MINOR__=2",
+ "__GNUC_PATCHLEVEL__=1",
+ "__GNUC_STDC_INLINE__=1",
+ "__GNUC__=4",
+ "__GXX_ABI_VERSION=1002",
+ "__ILP32__=1",
+ "__INT16_C_SUFFIX__=",
+ "__INT16_FMTd__=\"hd\"",
+ "__INT16_FMTi__=\"hi\"",
+ "__INT16_MAX__=32767",
+ "__INT16_TYPE__=short",
+ "__INT32_C_SUFFIX__=",
+ "__INT32_FMTd__=\"d\"",
+ "__INT32_FMTi__=\"i\"",
+ "__INT32_MAX__=2147483647",
+ "__INT32_TYPE__=int",
+ "__INT64_C_SUFFIX__=LL",
+ "__INT64_FMTd__=\"lld\"",
+ "__INT64_FMTi__=\"lli\"",
+ "__INT64_MAX__=9223372036854775807LL",
+ "__INT64_TYPE__=long long int",
+ "__INT8_C_SUFFIX__=",
+ "__INT8_FMTd__=\"hhd\"",
+ "__INT8_FMTi__=\"hhi\"",
+ "__INT8_MAX__=127",
+ "__INT8_TYPE__=signed char",
+ "__INTMAX_C_SUFFIX__=LL",
+ "__INTMAX_FMTd__=\"lld\"",
+ "__INTMAX_FMTi__=\"lli\"",
+ "__INTMAX_MAX__=9223372036854775807LL",
+ "__INTMAX_TYPE__=long long int",
+ "__INTMAX_WIDTH__=64",
+ "__INTPTR_FMTd__=\"d\"",
+ "__INTPTR_FMTi__=\"i\"",
+ "__INTPTR_MAX__=2147483647",
+ "__INTPTR_TYPE__=int",
+ "__INTPTR_WIDTH__=32",
+ "__INT_FAST16_FMTd__=\"hd\"",
+ "__INT_FAST16_FMTi__=\"hi\"",
+ "__INT_FAST16_MAX__=32767",
+ "__INT_FAST16_TYPE__=short",
+ "__INT_FAST32_FMTd__=\"d\"",
+ "__INT_FAST32_FMTi__=\"i\"",
+ "__INT_FAST32_MAX__=2147483647",
+ "__INT_FAST32_TYPE__=int",
+ "__INT_FAST64_FMTd__=\"lld\"",
+ "__INT_FAST64_FMTi__=\"lli\"",
+ "__INT_FAST64_MAX__=9223372036854775807LL",
+ "__INT_FAST64_TYPE__=long long int",
+ "__INT_FAST8_FMTd__=\"hhd\"",
+ "__INT_FAST8_FMTi__=\"hhi\"",
+ "__INT_FAST8_MAX__=127",
+ "__INT_FAST8_TYPE__=signed char",
+ "__INT_LEAST16_FMTd__=\"hd\"",
+ "__INT_LEAST16_FMTi__=\"hi\"",
+ "__INT_LEAST16_MAX__=32767",
+ "__INT_LEAST16_TYPE__=short",
+ "__INT_LEAST32_FMTd__=\"d\"",
+ "__INT_LEAST32_FMTi__=\"i\"",
+ "__INT_LEAST32_MAX__=2147483647",
+ "__INT_LEAST32_TYPE__=int",
+ "__INT_LEAST64_FMTd__=\"lld\"",
+ "__INT_LEAST64_FMTi__=\"lli\"",
+ "__INT_LEAST64_MAX__=9223372036854775807LL",
+ "__INT_LEAST64_TYPE__=long long int",
+ "__INT_LEAST8_FMTd__=\"hhd\"",
+ "__INT_LEAST8_FMTi__=\"hhi\"",
+ "__INT_LEAST8_MAX__=127",
+ "__INT_LEAST8_TYPE__=signed char",
+ "__INT_MAX__=2147483647",
+ "__I__=1.0if",
+ "__LDBL_DECIMAL_DIG__=17",
+ "__LDBL_DENORM_MIN__=4.9406564584124654e-324L",
+ "__LDBL_DIG__=15",
+ "__LDBL_EPSILON__=2.2204460492503131e-16L",
+ "__LDBL_HAS_DENORM__=1",
+ "__LDBL_HAS_INFINITY__=1",
+ "__LDBL_HAS_QUIET_NAN__=1",
+ "__LDBL_MANT_DIG__=53",
+ "__LDBL_MAX_10_EXP__=308",
+ "__LDBL_MAX_EXP__=1024",
+ "__LDBL_MAX__=1.7976931348623157e+308L",
+ "__LDBL_MIN_10_EXP__=(-307)",
+ "__LDBL_MIN_EXP__=(-1021)",
+ "__LDBL_MIN__=2.2250738585072014e-308L",
+ "__LITTLE_ENDIAN__=1",
+ "__LONG_LONG_MAX__=9223372036854775807LL",
+ "__LONG_MAX__=2147483647L",
+ "__NO_INLINE__=1",
+ "__OBJC_BOOL_IS_BOOL=0",
+ "__OPENCL_MEMORY_SCOPE_ALL_SVM_DEVICES=3",
+ "__OPENCL_MEMORY_SCOPE_DEVICE=2",
+ "__OPENCL_MEMORY_SCOPE_SUB_GROUP=4",
+ "__OPENCL_MEMORY_SCOPE_WORK_GROUP=1",
+ "__OPENCL_MEMORY_SCOPE_WORK_ITEM=0",
+ "__ORDER_BIG_ENDIAN__=4321",
+ "__ORDER_LITTLE_ENDIAN__=1234",
+ "__ORDER_PDP_ENDIAN__=3412",
+ "__POINTER_WIDTH__=32",
+ "__PRAGMA_REDEFINE_EXTNAME=1",
+ "__PTRDIFF_FMTd__=\"d\"",
+ "__PTRDIFF_FMTi__=\"i\"",
+ "__PTRDIFF_MAX__=2147483647",
+ "__PTRDIFF_TYPE__=int",
+ "__PTRDIFF_WIDTH__=32",
+ "__REGISTER_PREFIX__=",
+ "__SCHAR_MAX__=127",
+ "__SHRT_MAX__=32767",
+ "__SIG_ATOMIC_MAX__=2147483647",
+ "__SIG_ATOMIC_WIDTH__=32",
+ "__SIZEOF_DOUBLE__=8",
+ "__SIZEOF_FLOAT__=4",
+ "__SIZEOF_INT__=4",
+ "__SIZEOF_LONG_DOUBLE__=8",
+ "__SIZEOF_LONG_LONG__=8",
+ "__SIZEOF_LONG__=4",
+ "__SIZEOF_POINTER__=4",
+ "__SIZEOF_PTRDIFF_T__=4",
+ "__SIZEOF_SHORT__=2",
+ "__SIZEOF_SIZE_T__=4",
+ "__SIZEOF_WCHAR_T__=4",
+ "__SIZEOF_WINT_T__=4",
+ "__SIZE_FMTX__=\"X\"",
+ "__SIZE_FMTo__=\"o\"",
+ "__SIZE_FMTu__=\"u\"",
+ "__SIZE_FMTx__=\"x\"",
+ "__SIZE_MAX__=4294967295U",
+ "__SIZE_TYPE__=unsigned int",
+ "__SIZE_WIDTH__=32",
+ "__STDC_HOSTED__=1",
+ "__STDC_UTF_16__=1",
+ "__STDC_UTF_32__=1",
+ "__STDC_VERSION__=201710L",
+ "__STDC__=1",
+ "__UINT16_C_SUFFIX__=",
+ "__UINT16_FMTX__=\"hX\"",
+ "__UINT16_FMTo__=\"ho\"",
+ "__UINT16_FMTu__=\"hu\"",
+ "__UINT16_FMTx__=\"hx\"",
+ "__UINT16_MAX__=65535",
+ "__UINT16_TYPE__=unsigned short",
+ "__UINT32_C_SUFFIX__=U",
+ "__UINT32_FMTX__=\"X\"",
+ "__UINT32_FMTo__=\"o\"",
+ "__UINT32_FMTu__=\"u\"",
+ "__UINT32_FMTx__=\"x\"",
+ "__UINT32_MAX__=4294967295U",
+ "__UINT32_TYPE__=unsigned int",
+ "__UINT64_C_SUFFIX__=ULL",
+ "__UINT64_FMTX__=\"llX\"",
+ "__UINT64_FMTo__=\"llo\"",
+ "__UINT64_FMTu__=\"llu\"",
+ "__UINT64_FMTx__=\"llx\"",
+ "__UINT64_MAX__=18446744073709551615ULL",
+ "__UINT64_TYPE__=long long unsigned int",
+ "__UINT8_C_SUFFIX__=",
+ "__UINT8_FMTX__=\"hhX\"",
+ "__UINT8_FMTo__=\"hho\"",
+ "__UINT8_FMTu__=\"hhu\"",
+ "__UINT8_FMTx__=\"hhx\"",
+ "__UINT8_MAX__=255",
+ "__UINT8_TYPE__=unsigned char",
+ "__UINTMAX_C_SUFFIX__=ULL",
+ "__UINTMAX_FMTX__=\"llX\"",
+ "__UINTMAX_FMTo__=\"llo\"",
+ "__UINTMAX_FMTu__=\"llu\"",
+ "__UINTMAX_FMTx__=\"llx\"",
+ "__UINTMAX_MAX__=18446744073709551615ULL",
+ "__UINTMAX_TYPE__=long long unsigned int",
+ "__UINTMAX_WIDTH__=64",
+ "__UINTPTR_FMTX__=\"X\"",
+ "__UINTPTR_FMTo__=\"o\"",
+ "__UINTPTR_FMTu__=\"u\"",
+ "__UINTPTR_FMTx__=\"x\"",
+ "__UINTPTR_MAX__=4294967295U",
+ "__UINTPTR_TYPE__=unsigned int",
+ "__UINTPTR_WIDTH__=32",
+ "__UINT_FAST16_FMTX__=\"hX\"",
+ "__UINT_FAST16_FMTo__=\"ho\"",
+ "__UINT_FAST16_FMTu__=\"hu\"",
+ "__UINT_FAST16_FMTx__=\"hx\"",
+ "__UINT_FAST16_MAX__=65535",
+ "__UINT_FAST16_TYPE__=unsigned short",
+ "__UINT_FAST32_FMTX__=\"X\"",
+ "__UINT_FAST32_FMTo__=\"o\"",
+ "__UINT_FAST32_FMTu__=\"u\"",
+ "__UINT_FAST32_FMTx__=\"x\"",
+ "__UINT_FAST32_MAX__=4294967295U",
+ "__UINT_FAST32_TYPE__=unsigned int",
+ "__UINT_FAST64_FMTX__=\"llX\"",
+ "__UINT_FAST64_FMTo__=\"llo\"",
+ "__UINT_FAST64_FMTu__=\"llu\"",
+ "__UINT_FAST64_FMTx__=\"llx\"",
+ "__UINT_FAST64_MAX__=18446744073709551615ULL",
+ "__UINT_FAST64_TYPE__=long long unsigned int",
+ "__UINT_FAST8_FMTX__=\"hhX\"",
+ "__UINT_FAST8_FMTo__=\"hho\"",
+ "__UINT_FAST8_FMTu__=\"hhu\"",
+ "__UINT_FAST8_FMTx__=\"hhx\"",
+ "__UINT_FAST8_MAX__=255",
+ "__UINT_FAST8_TYPE__=unsigned char",
+ "__UINT_LEAST16_FMTX__=\"hX\"",
+ "__UINT_LEAST16_FMTo__=\"ho\"",
+ "__UINT_LEAST16_FMTu__=\"hu\"",
+ "__UINT_LEAST16_FMTx__=\"hx\"",
+ "__UINT_LEAST16_MAX__=65535",
+ "__UINT_LEAST16_TYPE__=unsigned short",
+ "__UINT_LEAST32_FMTX__=\"X\"",
+ "__UINT_LEAST32_FMTo__=\"o\"",
+ "__UINT_LEAST32_FMTu__=\"u\"",
+ "__UINT_LEAST32_FMTx__=\"x\"",
+ "__UINT_LEAST32_MAX__=4294967295U",
+ "__UINT_LEAST32_TYPE__=unsigned int",
+ "__UINT_LEAST64_FMTX__=\"llX\"",
+ "__UINT_LEAST64_FMTo__=\"llo\"",
+ "__UINT_LEAST64_FMTu__=\"llu\"",
+ "__UINT_LEAST64_FMTx__=\"llx\"",
+ "__UINT_LEAST64_MAX__=18446744073709551615ULL",
+ "__UINT_LEAST64_TYPE__=long long unsigned int",
+ "__UINT_LEAST8_FMTX__=\"hhX\"",
+ "__UINT_LEAST8_FMTo__=\"hho\"",
+ "__UINT_LEAST8_FMTu__=\"hhu\"",
+ "__UINT_LEAST8_FMTx__=\"hhx\"",
+ "__UINT_LEAST8_MAX__=255",
+ "__UINT_LEAST8_TYPE__=unsigned char",
+ "__USER_LABEL_PREFIX__=",
+ "__VERSION__=\"Clang 13.0.0 (ssh://ds-gerrit/armcompiler/llvm-project 1f5770d6f72ee4eba2159092bbf4cbb819be323a)\"",
+ "__WCHAR_MAX__=4294967295U",
+ "__WCHAR_TYPE__=unsigned int",
+ "__WCHAR_UNSIGNED__=1",
+ "__WCHAR_WIDTH__=32",
+ "__WINT_MAX__=2147483647",
+ "__WINT_TYPE__=int",
+ "__WINT_WIDTH__=32",
+ "__arm=1",
+ "__arm__=1",
+ "__clang__=1",
+ "__clang_major__=13",
+ "__clang_minor__=0",
+ "__clang_patchlevel__=0",
+ "__clang_version__=\"13.0.0 (ssh://ds-gerrit/armcompiler/llvm-project 1f5770d6f72ee4eba2159092bbf4cbb819be323a)\"",
+ "__llvm__=1"
+ ],
+ "intelliSenseMode": "${default}"
+ }
+ ],
+ "version": 4
+}
\ No newline at end of file
diff --git a/MDK/.vscode/keil-assistant.log b/MDK/.vscode/keil-assistant.log
new file mode 100644
index 0000000..a3035a8
--- /dev/null
+++ b/MDK/.vscode/keil-assistant.log
@@ -0,0 +1,2 @@
+[info] Log at : 2026/4/2|16:51:37|GMT+0800
+
diff --git a/MDK/.vscode/uv4.log.lock b/MDK/.vscode/uv4.log.lock
new file mode 100644
index 0000000..e69de29
diff --git a/MDK/EventRecorderStub.scvd b/MDK/EventRecorderStub.scvd
new file mode 100644
index 0000000..2956b29
--- /dev/null
+++ b/MDK/EventRecorderStub.scvd
@@ -0,0 +1,9 @@
+
+
+
+
+
+
+
+
+
diff --git a/MDK/JLinkSettings.ini b/MDK/JLinkSettings.ini
new file mode 100644
index 0000000..0276dfb
--- /dev/null
+++ b/MDK/JLinkSettings.ini
@@ -0,0 +1,40 @@
+[BREAKPOINTS]
+ForceImpTypeAny = 0
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+MonModeVTableAddr = 0xFFFFFFFF
+MonModeDebug = 0
+MaxNumAPs = 0
+LowPowerHandlingMode = 0
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+EraseType = 0x00
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 1
+Device="CORTEX-M0+"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF
diff --git a/MDK/RTE/_HC32L17X/RTE_Components.h b/MDK/RTE/_HC32L17X/RTE_Components.h
new file mode 100644
index 0000000..4e84c89
--- /dev/null
+++ b/MDK/RTE/_HC32L17X/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'hc32l17x'
+ * Target: 'HC32L17X'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "HC32L170JATA.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/MDK/RTE/__FEATURE__Release/RTE_Components.h b/MDK/RTE/__FEATURE__Release/RTE_Components.h
new file mode 100644
index 0000000..a2dd5ef
--- /dev/null
+++ b/MDK/RTE/__FEATURE__Release/RTE_Components.h
@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'ddl_template'
+ * Target: '{FEATURE}_Release'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM0plus.h"
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/MDK/RTE/_template_Release/RTE_Components.h b/MDK/RTE/_template_Release/RTE_Components.h
new file mode 100644
index 0000000..97bd6b0
--- /dev/null
+++ b/MDK/RTE/_template_Release/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'hc32l17x'
+ * Target: 'template_Release'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM0plus.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/MDK/hc32l17x.uvoptx b/MDK/hc32l17x.uvoptx
new file mode 100644
index 0000000..b6015ea
--- /dev/null
+++ b/MDK/hc32l17x.uvoptx
@@ -0,0 +1,438 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc; *.md
+ *.plm
+ *.cpp; *.cc; *.cxx
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ HC32L17X
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\output\release\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 255
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 12
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ CMSIS_AGDI
+ -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L17X_128K.FLM -FS00 -FL020000 -FP0($$Device:HC32L170JATA$Flash\FlashHC32L17X_128K.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0FlashHC32L17X_128K -FL020000 -FS00 -FP0($$Device:HC32L170JATA$Flash\FlashHC32L17X_128K.FLM)
+
+
+ 0
+ JL2CM3
+ -U4294967295 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8027 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L17X_128K.FLM -FS00 -FL020000 -FP0($$Device:HC32L170JATA$Flash\FlashHC32L17X_128K.FLM)
+
+
+ 0
+ DLGUARM
+
+
+
+ 0
+ ARMRTXEVENTFLAGS
+ -L70 -Z18 -C0 -M0 -T1
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+
+
+
+ 0
+ 1
+ SFBTC.ColletAltitude
+
+
+ 1
+ 1
+ BLE.AtCmd
+
+
+ 2
+ 1
+ BLE.RxBuff
+
+
+ 3
+ 1
+ BeaMac
+
+
+ 4
+ 1
+ BL.RxBuff
+
+
+ 5
+ 1
+ sData
+
+
+ 6
+ 1
+ BL.Status,0x0A
+
+
+
+
+ 1
+ 0
+ 0x00002800
+ 0
+
+
+
+
+ 2
+ 2
+ 0x20000f35
+ 0
+
+
+
+ 0
+
+
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 2
+ 1000000
+
+
+
+
+
+ common
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 1
+ 2
+ 0
+ 0
+ 0
+ .\startup_hc32l17x.s
+ startup_hc32l17x.s
+ 0
+ 0
+
+
+ 1
+ 2
+ 1
+ 0
+ 0
+ 0
+ ..\mcu\common\system_hc32l17x.c
+ system_hc32l17x.c
+ 0
+ 0
+
+
+ 1
+ 3
+ 1
+ 0
+ 0
+ 0
+ ..\mcu\common\interrupts_hc32l17x.c
+ interrupts_hc32l17x.c
+ 0
+ 0
+
+
+
+
+ source
+ 1
+ 0
+ 0
+ 0
+
+ 2
+ 4
+ 1
+ 0
+ 0
+ 0
+ ..\source\Src\main.c
+ main.c
+ 0
+ 0
+
+
+ 2
+ 5
+ 1
+ 1
+ 0
+ 0
+ ..\source\src\bsp.c
+ bsp.c
+ 0
+ 0
+
+
+
+
+ driver
+ 1
+ 0
+ 0
+ 0
+
+ 3
+ 6
+ 1
+ 0
+ 0
+ 0
+ ..\driver\src\flash.c
+ flash.c
+ 0
+ 0
+
+
+ 3
+ 7
+ 1
+ 0
+ 0
+ 0
+ ..\driver\src\gpio.c
+ gpio.c
+ 0
+ 0
+
+
+ 3
+ 8
+ 1
+ 0
+ 0
+ 0
+ ..\driver\src\wdt.c
+ wdt.c
+ 0
+ 0
+
+
+ 3
+ 9
+ 1
+ 0
+ 0
+ 0
+ ..\driver\src\ddl.c
+ ddl.c
+ 0
+ 0
+
+
+ 3
+ 10
+ 1
+ 0
+ 0
+ 0
+ ..\driver\src\sysctrl.c
+ sysctrl.c
+ 0
+ 0
+
+
+ 3
+ 11
+ 1
+ 0
+ 0
+ 0
+ ..\driver\src\bt.c
+ bt.c
+ 0
+ 0
+
+
+ 3
+ 12
+ 1
+ 0
+ 0
+ 0
+ ..\driver\src\lpuart.c
+ lpuart.c
+ 0
+ 0
+
+
+
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
+
diff --git a/MDK/hc32l17x.uvprojx b/MDK/hc32l17x.uvprojx
new file mode 100644
index 0000000..ce405c7
--- /dev/null
+++ b/MDK/hc32l17x.uvprojx
@@ -0,0 +1,490 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ HC32L17X
+ 0x4
+ ARM-ADS
+ 6160000::V6.16::ARMCLANG
+ 6160000::V6.16::ARMCLANG
+ 1
+
+
+ HC32L170JATA
+ HDSC
+ HDSC.HC32L17X.1.0.1
+ https://raw.githubusercontent.com/hdscmcu/pack/master/
+ IRAM(0x20000000,0x4000) IROM(0x00000000,0x20000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L17X_128K -FS00 -FL020000 -FP0($$Device:HC32L170JATA$Flash\FlashHC32L17X_128K.FLM))
+ 0
+ $$Device:HC32L170JATA$Device\Include\HC32L170JATA.h
+
+
+
+
+
+
+
+
+
+ $$Device:HC32L170JATA$SVD\HC32L170JATA.sfr
+ 1
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\output\
+ hc32l17x
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\output\release\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+ D:\Program Files (x86)\Keil_v5\ARM\ARMCC\bin\fromelf.exe --bin -o .\output\app.bin .\output\hc32l17x.axf
+ D:\Keil_v5\ARM\ARMCC\bin\fromelf.exe --bin -o .\output\app.bin .\output\hc32l17x.axf
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+
+ DARMCM1.DLL
+ -pCM0+
+ SARMCM3.DLL
+
+ TARMCM1.DLL
+ -pCM0+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ "Cortex-M0+"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 8
+ 1
+ 0
+ 0
+ 0
+ 3
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x4000
+
+
+ 1
+ 0x0
+ 0x20000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x20000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x4000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 4
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+ ..\mcu\common;..\source;..\driver\inc;..\source\inc;..\Module\LIS2HH12;..\Module\Debug;..\Module\GPS;..\Module\spl06;..\Module\CAT1;..\Module\WH-BLE106
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 4
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x20000000
+
+ template.sct
+
+
+ --keep=*Handler
+
+
+
+
+
+
+
+ common
+
+
+ startup_hc32l17x.s
+ 2
+ .\startup_hc32l17x.s
+
+
+ system_hc32l17x.c
+ 1
+ ..\mcu\common\system_hc32l17x.c
+
+
+ interrupts_hc32l17x.c
+ 1
+ ..\mcu\common\interrupts_hc32l17x.c
+
+
+
+
+ source
+
+
+ main.c
+ 1
+ ..\source\Src\main.c
+
+
+ bsp.c
+ 1
+ ..\source\src\bsp.c
+
+
+
+
+ driver
+
+
+ flash.c
+ 1
+ ..\driver\src\flash.c
+
+
+ gpio.c
+ 1
+ ..\driver\src\gpio.c
+
+
+ wdt.c
+ 1
+ ..\driver\src\wdt.c
+
+
+ ddl.c
+ 1
+ ..\driver\src\ddl.c
+
+
+ sysctrl.c
+ 1
+ ..\driver\src\sysctrl.c
+
+
+ bt.c
+ 1
+ ..\driver\src\bt.c
+
+
+ lpuart.c
+ 1
+ ..\driver\src\lpuart.c
+
+
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <Project Info>
+ 0
+ 1
+
+
+
+
+
diff --git a/MDK/output/hc32l17x.sct b/MDK/output/hc32l17x.sct
new file mode 100644
index 0000000..3af1861
--- /dev/null
+++ b/MDK/output/hc32l17x.sct
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00020000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x00004000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/MDK/startup_hc32l17x.s b/MDK/startup_hc32l17x.s
new file mode 100644
index 0000000..dc8e9d1
--- /dev/null
+++ b/MDK/startup_hc32l17x.s
@@ -0,0 +1,298 @@
+;/******************************************************************************
+;* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+;*
+;* This software is owned and published by:
+;* Huada Semiconductor Co.,Ltd ("HDSC").
+;*
+;* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+;* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+;*
+;* This software contains source code for use with HDSC
+;* components. This software is licensed by HDSC to be adapted only
+;* for use in systems utilizing HDSC components. HDSC shall not be
+;* responsible for misuse or illegal use of this software for devices not
+;* supported herein. HDSC is providing this software "AS IS" and will
+;* not be responsible for issues arising from incorrect user implementation
+;* of the software.
+;*
+;* Disclaimer:
+;* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+;* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+;* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+;* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+;* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+;* WARRANTY OF NONINFRINGEMENT.
+;* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+;* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+;* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+;* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+;* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+;* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+;* SAVINGS OR PROFITS,
+;* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+;* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+;* FROM, THE SOFTWARE.
+;*
+;* This software may be replicated in part or whole for the licensed use,
+;* with the restriction that this Disclaimer and Copyright notice must be
+;* included with each copy of this software, whether used in part or whole,
+;* at all times.
+;*/
+;/*****************************************************************************/
+
+;/*****************************************************************************/
+;/* Startup for ARM */
+;/* Version V1.0 */
+;/* Date 2019-03-01 */
+;/* Target-mcu {MCU_PN_H} */
+;/*****************************************************************************/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Stack_Size EQU 0x00001000
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors
+ DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset
+ DCD NMI_Handler ; NMI
+ DCD HardFault_Handler ; Hard Fault
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV
+ DCD SysTick_Handler ; SysTick
+
+ DCD PORTA_IRQHandler
+ DCD PORTB_IRQHandler
+ DCD PORTC_E_IRQHandler
+ DCD PORTD_F_IRQHandler
+ DCD DMAC_IRQHandler
+ DCD TIM3_IRQHandler
+ DCD UART0_2_IRQHandler
+ DCD UART1_3_IRQHandler
+ DCD LPUART0_IRQHandler
+ DCD LPUART1_IRQHandler
+ DCD SPI0_IRQHandler
+ DCD SPI1_IRQHandler
+ DCD I2C0_IRQHandler
+ DCD I2C1_IRQHandler
+ DCD TIM0_IRQHandler
+ DCD TIM1_IRQHandler
+ DCD TIM2_IRQHandler
+ DCD LPTIM0_1_IRQHandler
+ DCD TIM4_IRQHandler
+ DCD TIM5_IRQHandler
+ DCD TIM6_IRQHandler
+ DCD PCA_IRQHandler
+ DCD WDT_IRQHandler
+ DCD RTC_IRQHandler
+ DCD ADC_DAC_IRQHandler
+ DCD PCNT_IRQHandler
+ DCD VC0_IRQHandler
+ DCD VC1_2_IRQHandler
+ DCD LVD_IRQHandler
+ DCD LCD_IRQHandler
+ DCD FLASH_RAM_IRQHandler
+ DCD CLKTRIM_IRQHandler
+
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ ;reset NVIC if in rom debug
+ LDR R0, =0x20000000
+ LDR R2, =0x0
+ MOVS R1, #0 ; for warning,
+ ADD R1, PC,#0 ; for A1609W,
+ CMP R1, R0
+ BLS RAMCODE
+
+ ; ram code base address.
+ ADD R2, R0,R2
+RAMCODE
+ ; reset Vector table address.
+ LDR R0, =0xE000ED08
+ STR R2, [R0]
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+
+
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT PORTC_E_IRQHandler [WEAK]
+ EXPORT PORTD_F_IRQHandler [WEAK]
+ EXPORT DMAC_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT UART0_2_IRQHandler [WEAK]
+ EXPORT UART1_3_IRQHandler [WEAK]
+ EXPORT LPUART0_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT TIM0_IRQHandler [WEAK]
+ EXPORT TIM1_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT LPTIM0_1_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT PCA_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT ADC_DAC_IRQHandler [WEAK]
+ EXPORT PCNT_IRQHandler [WEAK]
+ EXPORT VC0_IRQHandler [WEAK]
+ EXPORT VC1_2_IRQHandler [WEAK]
+ EXPORT LVD_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT FLASH_RAM_IRQHandler [WEAK]
+ EXPORT CLKTRIM_IRQHandler [WEAK]
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_E_IRQHandler
+PORTD_F_IRQHandler
+DMAC_IRQHandler
+TIM3_IRQHandler
+UART0_2_IRQHandler
+UART1_3_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+TIM0_IRQHandler
+TIM1_IRQHandler
+TIM2_IRQHandler
+LPTIM0_1_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+PCA_IRQHandler
+WDT_IRQHandler
+RTC_IRQHandler
+ADC_DAC_IRQHandler
+PCNT_IRQHandler
+VC0_IRQHandler
+VC1_2_IRQHandler
+LVD_IRQHandler
+LCD_IRQHandler
+FLASH_RAM_IRQHandler
+CLKTRIM_IRQHandler
+
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/driver/inc/adc.h b/driver/inc/adc.h
new file mode 100644
index 0000000..f1eccb9
--- /dev/null
+++ b/driver/inc/adc.h
@@ -0,0 +1,470 @@
+/******************************************************************************
+* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file adc.h
+ **
+ ** Header file for AD Converter functions
+ ** @link ADC Group Some description @endlink
+ **
+ ** - 2017-06-28 Alex First Version
+ **
+ ******************************************************************************/
+
+#ifndef __ADC_H__
+#define __ADC_H__
+
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "ddl.h"
+
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ ******************************************************************************
+ ** \defgroup AdcGroup AD Converter (ADC)
+ **
+ ******************************************************************************/
+
+//@{
+
+/******************************************************************************
+ * Global definitions
+ ******************************************************************************/
+#define ADC_SCAN_CH0_EN (0x1u) /*!< SCAN模式使用ADC CH0 */
+#define ADC_SCAN_CH1_EN (0x1u<<1) /*!< SCAN模式使用ADC CH1 */
+#define ADC_SCAN_CH2_EN (0x1u<<2) /*!< SCAN模式使用ADC CH2 */
+#define ADC_SCAN_CH3_EN (0x1u<<3) /*!< SCAN模式使用ADC CH3 */
+#define ADC_SCAN_CH4_EN (0x1u<<4) /*!< SCAN模式使用ADC CH4 */
+#define ADC_SCAN_CH5_EN (0x1u<<5) /*!< SCAN模式使用ADC CH5 */
+#define ADC_SCAN_CH6_EN (0x1u<<6) /*!< SCAN模式使用ADC CH6 */
+#define ADC_SCAN_CH7_EN (0x1u<<7) /*!< SCAN模式使用ADC CH7 */
+
+
+/******************************************************************************
+ ** Global type definitions
+ *****************************************************************************/
+
+ /**
+ ******************************************************************************
+ ** \brief ADC转换模式
+ *****************************************************************************/
+typedef enum en_adc_mode
+{
+ AdcSglMode = 0u, /*!< 单输入通道单次转换模式 */
+ AdcScanMode = 1u, /*!< 多输入通道顺序/插队扫描转换模式*/
+}en_adc_mode_t;
+
+/**
+ ******************************************************************************
+ ** \brief ADC时钟分频选择
+ *****************************************************************************/
+typedef enum en_adc_clk_sel
+{
+ AdcMskClkDiv1 = 0u<<2, /*!< PCLK */
+ AdcMskClkDiv2 = 1u<<2, /*!< 1/2 PCLK */
+ AdcMskClkDiv4 = 2u<<2, /*!< 1/4 PCLK */
+ AdcMskClkDiv8 = 3u<<2, /*!< 1/8 PCLK */
+} en_adc_clk_div_t;
+
+/**
+ ******************************************************************************
+ ** \brief ADC参考电压
+ *****************************************************************************/
+typedef enum en_adc_ref_vol_sel
+{
+ AdcMskRefVolSelInBgr1p5 = 0u<<9, /*!<内部参考电压1.5V(SPS<=200kHz)*/
+ AdcMskRefVolSelInBgr2p5 = 1u<<9, /*!<内部参考电压2.5V(avdd>3V,SPS<=200kHz)*/
+ AdcMskRefVolSelExtern1 = 2u<<9, /*!<外部输入(max avdd) PB01*/
+ AdcMskRefVolSelAVDD = 3u<<9, /*!>4)*10) + ((x)&0x0F))
+
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+ ******************************************************************************
+ ** Global Device Series List
+ ******************************************************************************/
+#define DDL_DEVICE_SERIES_HC32L17X (0u)
+
+/**
+ ******************************************************************************
+ ** Global Device Package List
+ ******************************************************************************/
+// package definitions of HC device.
+#define DDL_DEVICE_PACKAGE_HC_C (0x00u)
+#define DDL_DEVICE_PACKAGE_HC_F (0x10u)
+#define DDL_DEVICE_PACKAGE_HC_J (0x20u)
+#define DDL_DEVICE_PACKAGE_HC_K (0x30u)
+
+/******************************************************************************/
+/* User Device Setting Include file */
+/******************************************************************************/
+#include "ddl_device.h" // MUST be included here!
+
+/******************************************************************************/
+/* Global type definitions ('typedef') */
+/******************************************************************************/
+/**
+ ******************************************************************************
+ ** \brief Level
+ **
+ ** Specifies levels.
+ **
+ ******************************************************************************/
+typedef enum en_level
+{
+ DdlLow = 0u, ///< Low level '0'
+ DdlHigh = 1u ///< High level '1'
+} en_level_t;
+
+/**
+ ******************************************************************************
+ ** \brief Generic Flag Code
+ **
+ ** Specifies flags.
+ **
+ ******************************************************************************/
+typedef enum en_flag
+{
+ DdlClr = 0u, ///< Flag clr '0'
+ DdlSet = 1u ///< Flag set '1'
+} en_stat_flag_t, en_irq_flag_t;
+/******************************************************************************/
+/* Global variable declarations ('extern', definition in C source) */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Global function prototypes ('extern', definition in C source) */
+/******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes
+ ******************************************************************************/
+extern void ddl_memclr(void* pu8Address, uint32_t u32Count);
+uint32_t Log2(uint32_t u32Val);
+/**
+ *******************************************************************************
+ ** This hook is part of wait loops.
+ ******************************************************************************/
+void delay1ms(uint32_t u32Cnt);
+void delay100us(uint32_t u32Cnt);
+void delay10us(uint32_t u32Cnt);
+void SetBit(uint32_t addr, uint32_t offset, boolean_t bFlag);
+void ClrBit(uint32_t addr, uint32_t offset);
+boolean_t GetBit(uint32_t addr, uint32_t offset);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DDL_H__ */
+
+/******************************************************************************/
+/* EOF (not truncated) */
+/******************************************************************************/
+
diff --git a/driver/inc/debug.h b/driver/inc/debug.h
new file mode 100644
index 0000000..4f33fde
--- /dev/null
+++ b/driver/inc/debug.h
@@ -0,0 +1,129 @@
+/*******************************************************************************
+* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file debug.h
+ **
+ ** Headerfile for DEBUG functions
+ ** @link Debug Group Some description @endlink
+ **
+ ** History:
+ ** - 2018-04-15 Lux First Version
+ **
+ ******************************************************************************/
+
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "ddl.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ ******************************************************************************
+ ** \defgroup DebugGroup (DEBUG)
+ **
+ ******************************************************************************/
+//@{
+
+/**
+ *******************************************************************************
+ ** function prototypes.
+ ******************************************************************************/
+
+/******************************************************************************
+ * Global type definitions
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief 调试模式下各模块工作状态类型定义
+ ** \note
+ ******************************************************************************/
+typedef enum en_debug_module_active
+{
+ DebugMskTim0 = 0x0001u, ///< TIM0
+ DebugMskTim1 = 0x0002u, ///< TIM1
+ DebugMskTim2 = 0x0004u, ///< TIM2
+ DebugMskLpTim0 = 0x0008u, ///< LPTIM0
+ DebugMskTim4 = 0x0010u, ///< TIM4
+ DebugMskTim5 = 0x0020u, ///< TIM5
+ DebugMskTim6 = 0x0040u, ///< TIM6
+ DebugMskPca = 0x0080u, ///< PCA
+ DebugMskWdt = 0x0100u, ///< WDT
+ DebugMskRtc = 0x0200u, ///< RTC
+ DebugMskTim3 = 0x0800u, ///< TIM3
+ DebugMskLpTim1 = 0x1000u, ///< LPTIM1
+}en_debug_module_active_t;
+
+/*******************************************************************************
+ * Global definitions
+ ******************************************************************************/
+
+/******************************************************************************
+ * Global variable declarations ('extern', definition in C source)
+ ******************************************************************************/
+
+/******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+///< 在SWD调试模式下，使能模块计数功能
+en_result_t Debug_ActiveEnable(en_debug_module_active_t enModule);
+///< 在SWD调试模式下，暂停模块计数功能
+en_result_t Debug_ActiveDisable(en_debug_module_active_t enModule);
+
+//@} // Debug Group
+
+#ifdef __cplusplus
+#endif
+
+#endif /* __DEBUG_H__ */
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
+
diff --git a/driver/inc/dmac.h b/driver/inc/dmac.h
new file mode 100644
index 0000000..bdd93b0
--- /dev/null
+++ b/driver/inc/dmac.h
@@ -0,0 +1,356 @@
+/*****************************************************************************
+* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file dma.h
+**
+** A detailed description is available at
+** @link DmacGroup Dmac description @endlink
+**
+** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac.
+**
+******************************************************************************/
+#ifndef __DMAC_H__
+#define __DMAC_H__
+
+/*******************************************************************************
+* Include files
+******************************************************************************/
+#include "ddl.h"
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+ /**
+ *******************************************************************************
+ ** \defgroup DmacGroup Direct Memory Access Control(DMAC)
+ **
+ ******************************************************************************/
+ //@{
+
+ /*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+ /**
+ *******************************************************************************
+ ** \brief DMA 通道
+ **
+ ******************************************************************************/
+ typedef enum en_dma_channel
+ {
+ DmaCh0 = 0x00, ///< DMA 通道0
+ DmaCh1 = 0x04, ///< DMA 通道1
+ } en_dma_channel_t;
+ /**
+ *******************************************************************************
+ ** \brief DMA 优先级
+ **
+ ******************************************************************************/
+ typedef enum en_dma_priority
+ {
+ DmaMskPriorityFix = 0x00000000, ///< DMA 各通道优先级固定 (CH0>CH1)
+ DmaMskPriorityLoop = 0x10000000, ///< DMA 各通道优先级采用轮询方式
+ } en_dma_priority_t;
+
+ /**
+ *******************************************************************************
+ ** \brief DMA 传输数据宽度
+ **
+ ******************************************************************************/
+ typedef enum en_dma_transfer_width
+ {
+ DmaMsk8Bit = 0x00000000, ///< 8 bit 字节传输
+ DmaMsk16Bit = 0x04000000, ///< 16 bit 半字传输
+ DmaMsk32Bit = 0x08000000 ///< 32 bit 字传输
+ } en_dma_transfer_width_t;
+
+ /**
+ *******************************************************************************
+ ** \brief DMA 传输模式：块(Block)传输或者突发(Burst)传输
+ **
+ ******************************************************************************/
+ typedef enum en_dma_transfer_mode
+ {
+ DmaMskBlock = 0x00000000, ///< 块(Block)传输
+ DmaMskBurst = 0x10000000, ///< 突发(Burst)传输
+ } en_dma_transfer_mode_t;
+
+ /**
+ *******************************************************************************
+ ** \brief DMA传输当前状态
+ **
+ ******************************************************************************/
+ typedef enum en_dma_stat
+ {
+ DmaDefault = 0U, ///< 初始值
+ DmaAddOverflow = 1U, ///< 传输错误引起中止（地址溢出）
+ DmaHALT = 2U, ///< 传输停止请求引起中止（外设停止请求引起的停止或者EB/DE位引起的禁止传输）
+ DmaAccSCRErr = 3U, ///< 传输错误引起中止（传输源地址访问错误）
+ DmaAccDestErr = 4U, ///< 传输错误引起中止（传输目的地址访问错误）
+ DmaTransferComplete = 5U, ///< 成功传输完成
+ DmaTransferPause = 7U, ///< 传输暂停
+ } en_dma_stat_t;
+
+ /**
+ *******************************************************************************
+ ** \brief DMA源地址控制模式：自增或固定
+ **
+ ******************************************************************************/
+ typedef enum en_src_address_mode
+ {
+ DmaMskSrcAddrInc = 0x00000000, ///< 地址自增
+ DmaMskSrcAddrFix = 0x02000000, ///< 地址固定
+ } en_src_address_mode_t;
+
+ /**
+ *******************************************************************************
+ ** \brief DMA目的地址控制模式：自增或固定
+ **
+ ******************************************************************************/
+ typedef enum en_dst_address_mode
+ {
+ DmaMskDstAddrInc = 0x00000000, ///< 地址自增
+ DmaMskDstAddrFix = 0x01000000, ///< 地址固定
+ } en_dst_address_mode_t;
+
+ /**
+ *******************************************************************************
+ ** \brief DMA CONFA:BC[3:0]和CONFA:TC[15:0]的重载功能
+ **
+ ******************************************************************************/
+ typedef enum en_bc_tc_reload_mode
+ {
+ DmaMskBcTcReloadDisable = 0x00000000, ///< 禁止重载
+ DmaMskBcTcReloadEnable = 0x00800000, ///< 使能重载
+ } en_bc_tc_reload_mode_t;
+
+ /**
+ *******************************************************************************
+ ** \brief DMA源地址重载功能：使能或禁止
+ **
+ ******************************************************************************/
+ typedef enum en_src_address_reload_mode
+ {
+ DmaMskSrcAddrReloadDisable = 0x00000000, ///< 禁止DMA源地址重载
+ DmaMskSrcAddrReloadEnable = 0x00400000, ///< 使能DMA源地址重载
+ } en_src_address_reload_mode_t;
+
+ /**
+ *******************************************************************************
+ ** \brief DMA目的地址重载功能：使能或禁止
+ **
+ ******************************************************************************/
+ typedef enum en_dst_address_reload_mode
+ {
+ DmaMskDstAddrReloadDisable = 0x00000000, ///< 禁止DMA目的地址重载
+ DmaMskDstAddrReloadEnable = 0x00200000, ///< 使能DMA目的地址重载
+ } en_dst_address_reload_mode_t;
+
+
+
+ /**
+ *******************************************************************************
+ ** \brief DMA 连续传输设置
+ **
+ ******************************************************************************/
+ typedef enum en_dma_msk
+ {
+ DmaMskOneTransfer = 0x00000000, ///< 传输一次，DMAC传输完成时清除CONFA:ENS位
+ DmaMskContinuousTransfer = 0x00000001, ///< 连续传输，DMAC传输完成时不清除CONFA:ENS位
+ } en_dma_msk_t;
+ /**
+ *******************************************************************************
+ ** \brief DMA 触发源选择
+ **
+ ******************************************************************************/
+ typedef enum stc_dma_trig_sel
+ {
+ DmaSWTrig = 0U, ///< Select DMA software trig
+ DmaSPI0RXTrig = 64U, ///< Select DMA hardware trig 0
+ DmaSPI0TXTrig = 65U, ///< Select DMA hardware trig 1
+ DmaSPI1RXTrig = 66U, ///< Select DMA hardware trig 2
+ DmaSPI1TXTrig = 67U, ///< Select DMA hardware trig 3
+ DmaADCJQRTrig = 68U, ///< Select DMA hardware trig 4
+ DmaADCSQRTrig = 69U, ///< Select DMA hardware trig 5
+ DmaLCDTxTrig = 70U, ///< Select DMA hardware trig 6
+ DmaUart0RxTrig = 72U, ///< Select DMA hardware trig 8
+ DmaUart0TxTrig = 73U, ///< Select DMA hardware trig 9
+ DmaUart1RxTrig = 74U, ///< Select DMA hardware trig 10
+ DmaUart1TxTrig = 75U, ///< Select DMA hardware trig 11
+ DmaLpUart0RxTrig = 76U, ///< Select DMA hardware trig 12
+ DmaLpUart0TxTrig = 77U, ///< Select DMA hardware trig 13
+ DmaLpUart1RxTrig = 78U, ///< Select DMA hardware trig 14
+ DmaLpUart1TxTrig = 79U, ///< Select DMA hardware trig 15
+ DmaDAC0Trig = 80U, ///< Select DMA hardware trig 16
+ DmaDAC1Trig = 81U, ///< Select DMA hardware trig 17
+ DmaTIM0ATrig = 82U, ///< Select DMA hardware trig 18
+ DmaTIM0BTrig = 83U, ///< Select DMA hardware trig 19
+ DmaTIM1ATrig = 84U, ///< Select DMA hardware trig 20
+ DmaTIM1BTrig = 85U, ///< Select DMA hardware trig 21
+ DmaTIM2ATrig = 86U, ///< Select DMA hardware trig 22
+ DmaTIM2BTrig = 87U, ///< Select DMA hardware trig 23
+ DmaTIM3ATrig = 88U, ///< Select DMA hardware trig 24
+ DmaTIM3BTrig = 89U, ///< Select DMA hardware trig 25
+ DmaTIM4ATrig = 90U, ///< Select DMA hardware trig 26
+ DmaTIM4BTrig = 91U, ///< Select DMA hardware trig 27
+ DmaTIM5ATrig = 92U, ///< Select DMA hardware trig 28
+ DmaTIM5BTrig = 93U, ///< Select DMA hardware trig 29
+ DmaTIM6ATrig = 94U, ///< Select DMA hardware trig 30
+ DmaTIM6BTrig = 95U, ///< Select DMA hardware trig 31
+ DmaUart2RxTrig = 96U, ///< Select DMA hardware trig 32
+ DmaUart2TxTrig = 97U, ///< Select DMA hardware trig 33
+ DmaUart3RxTrig = 98U, ///< Select DMA hardware trig 34
+ DmaUart3TxTrig = 99U, ///< Select DMA hardware trig 35
+ }en_dma_trig_sel_t;
+
+ /**
+ *******************************************************************************
+ ** \brief DMA通道初始化配置结构体
+ **
+ ******************************************************************************/
+ typedef struct stc_dma_cfg
+ {
+ en_dma_transfer_mode_t enMode;
+
+ uint16_t u16BlockSize; ///< 块传输个数
+ uint16_t u16TransferCnt; ///< 传输块次数
+ en_dma_transfer_width_t enTransferWidth; ///< 传输数据字节宽度 具体参考枚举定义:en_dma_transfer_width_t
+
+ en_src_address_mode_t enSrcAddrMode; ///< DMA源地址控制模式：自增或固定
+ en_dst_address_mode_t enDstAddrMode; ///< DMA目的地址控制模式：自增或固定
+
+ en_src_address_reload_mode_t enSrcAddrReloadCtl; ///< 源地址重载 具体参考枚举定义:en_src_address_reload_mode_t
+ en_dst_address_reload_mode_t enDestAddrReloadCtl;///< 目的地址重载 具体参考枚举定义:en_dst_address_reload_mode_t
+ en_bc_tc_reload_mode_t enSrcBcTcReloadCtl; ///< Bc/Tc值重载功能 具体参考枚举定义:en_bc_tc_reload_mode_t
+
+ uint32_t u32SrcAddress; ///< 源地址>
+ uint32_t u32DstAddress; ///< 目的地址>
+
+ en_dma_msk_t enTransferMode; ///DMA 连续传输设置 具体参考枚举定义:en_dma_msk_t
+ en_dma_priority_t enPriority; ///DMA 优先级设定 具体参考枚举定义:en_dma_priority_t
+ en_dma_trig_sel_t enRequestNum; ///PCLK=HCLK=SystemClk=RCH4MHz
+en_result_t Sysctrl_ClkDeInit(void);
+
+///< 系统时钟模块的基本功能设置
+///< 注意：使能需要使用的时钟源之前，必须优先设置目标内部时钟源的TRIM值或外部时钟源的频率范围
+en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag);
+
+///<外部晶振驱动配置：系统初始化Sysctrl_ClkInit()之后，可根据需要配置外部晶振的驱动能力，时钟初始化Sysctrl_ClkInit()默认为最大值;
+en_result_t Sysctrl_XTHDriverCfg(en_sysctrl_xtal_driver_t enDriver);
+en_result_t Sysctrl_XTLDriverCfg(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver);
+
+///<时钟稳定周期设置:系统初始化Sysctrl_ClkInit()之后，可根据需要配置时钟开启后的稳定之间，默认为最大值;
+en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle);
+en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle);
+en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle);
+en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle);
+
+///<系统时钟源切换并更新系统时钟：如果需要在系统时钟初始化Sysctrl_ClkInit()之后切换主频时钟源，则使用该函数；
+///< 时钟切换前后，必须根据目标频率值设置Flash读等待周期，可配置插入周期为0、1、2，
+///< 注意!!!：当HCLK大于24MHz时，FLASH等待周期插入必须至少为1,否则程序运行可能产生未知错误
+en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource);
+
+///< 时钟源频率设定：根据系统情况，单独设置不同时钟源的频率值;
+///< 时钟频率设置前，必须根据目标频率值设置Flash读等待周期，可配置插入周期为0、1、2，
+///< 其中XTL的时钟由外部晶振决定，无需设置。
+en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq);
+en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq);
+en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq);
+en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_cfg_t *pstcPLLCfg);
+
+///< 时钟分频设置:根据系统情况，单独设置HCLK、PCLK的分配值;
+en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv);
+en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv);
+
+///< 时钟频率获取：根据系统需要，获取当前HCLK及PCLK的频率值
+uint32_t Sysctrl_GetHClkFreq(void);
+uint32_t Sysctrl_GetPClkFreq(void);
+
+///< 外设门控开关/状态获取：用于控制外设模块的使能，使用该模块的功能之前，必须使能该模块的门控时钟；
+en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag);
+boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral);
+
+///< 系统功能配置：用于设置其他系统相关特殊功能；
+en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag);
+
+///< RTC高速时钟补偿:用于设置RTC高速时钟下的频率补偿
+en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj);
+
+//@} // Sysctrl Group
+
+#ifdef __cplusplus
+#endif
+
+#endif /* __SYSCTRL_H__ */
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
+
diff --git a/driver/inc/timer3.h b/driver/inc/timer3.h
new file mode 100644
index 0000000..fbe59fc
--- /dev/null
+++ b/driver/inc/timer3.h
@@ -0,0 +1,781 @@
+/*******************************************************************************
+* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file timer3.h
+ **
+ ** 基本定时器数据结构及API声明
+ ** @link Timer3 Group Some description @endlink
+ **
+ ** History:
+ ** - 2019-04-18 Husj First Version
+ **
+ *****************************************************************************/
+
+#ifndef __TIMER3_H__
+#define __TIMER3_H__
+
+/*****************************************************************************
+ * Include files
+ *****************************************************************************/
+#include "ddl.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ ******************************************************************************
+ ** \defgroup Tim3Group Timer3 (TIM3)
+ **
+ ******************************************************************************/
+//@{
+
+/******************************************************************************/
+/* Global pre-processor symbols/macros ('#define') */
+/******************************************************************************/
+
+/******************************************************************************
+ * Global type definitions
+ ******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Timer3 通道定义
+ *****************************************************************************/
+typedef enum en_tim3_channel
+{
+ Tim3CH0 = 0u, ///< Timer3通道0
+ Tim3CH1 = 1u, ///< Timer3通道1
+ Tim3CH2 = 2u, ///< Timer3通道2
+}en_tim3_channel_t;
+
+/**
+ ******************************************************************************
+ ** \brief 工作模式选择数据类型重定义 (MODE)(模式0/1/23)
+ *****************************************************************************/
+typedef enum en_tim3_work_mode
+{
+ Tim3WorkMode0 = 0u, ///< 定时器模式
+ Tim3WorkMode1 = 1u, ///< PWC模式
+ Tim3WorkMode2 = 2u, ///< 锯齿波模式
+ Tim3WorkMode3 = 3u, ///< 三角波模式
+}en_tim3_work_mode_t;
+
+/**
+ ******************************************************************************
+ ** \brief 极性控制数据类型重定义 (GATE_P)(模式0)
+ *****************************************************************************/
+typedef enum en_tim3_m0cr_gatep
+{
+ Tim3GatePositive = 0u, ///< 高电平有效
+ Tim3GateOpposite = 1u, ///< 低电平有效
+}en_tim3_m0cr_gatep_t;
+
+/**
+ ******************************************************************************
+ ** \brief TIM3 预除频选择 (PRS)(模式0/1/23)
+ *****************************************************************************/
+typedef enum en_tim3_cr_timclkdiv
+{
+ Tim3PCLKDiv1 = 0u, ///< Div 1
+ Tim3PCLKDiv2 = 1u, ///< Div 2
+ Tim3PCLKDiv4 = 2u, ///< Div 4
+ Tim3PCLKDiv8 = 3u, ///< Div 8
+ Tim3PCLKDiv16 = 4u, ///< Div 16
+ Tim3PCLKDiv32 = 5u, ///< Div 32
+ Tim3PCLKDiv64 = 6u, ///< Div 64
+ Tim3PCLKDiv256 = 7u, ///< Div 256
+}en_tim3_cr_timclkdiv_t;
+
+/**
+ ******************************************************************************
+ ** \brief 计数/定时器功能选择数据类型重定义 (CT)(模式0/1/23)
+ *****************************************************************************/
+typedef enum en_tim3_cr_ct
+{
+ Tim3Timer = 0u, ///< 定时器功能，计数时钟为内部PCLK
+ Tim3Counter = 1u, ///< 计数器功能，计数时钟为外部ETR
+}en_tim3_cr_ct_t;
+
+
+/**
+ ******************************************************************************
+ ** \brief 定时器工作模式数据类型重定义 (MD)(模式0)
+ *****************************************************************************/
+typedef enum en_tim3_m0cr_md
+{
+ Tim332bitFreeMode = 0u, ///< 32位计数器/定时器
+ Tim316bitArrMode = 1u, ///< 自动重装载16位计数器/定时器
+}en_tim3_m0cr_md_t;
+
+/**
+ ******************************************************************************
+** \brief TIM3中断类型数据类型重定义(模式0/1/23)
+ *****************************************************************************/
+typedef enum en_tim3_irq_type
+{
+ Tim3UevIrq = 0u, ///< 溢出/事件更新中断
+ Tim3CA0Irq = 2u, ///< CH0A捕获/比较中断(仅模式1/23存在)
+ Tim3CA1Irq = 3u, ///< CH1A捕获/比较中断(仅模式23存在)
+ Tim3CA2Irq = 4u, ///< CH2A捕获/比较中断(仅模式23存在)
+ Tim3CB0Irq = 5u, ///< CH0B捕获/比较中断(仅模式23存在)
+ Tim3CB1Irq = 6u, ///< CH1B捕获/比较中断(仅模式23存在)
+ Tim3CB2Irq = 7u, ///< CH2B捕获/比较中断(仅模式23存在)
+ Tim3CA0E = 8u, ///< CH0A捕获数据丢失标志(仅模式23存在)(不是中断)
+ Tim3CA1E = 9u, ///< CH1A捕获数据丢失标志(仅模式23存在)(不是中断)
+ Tim3CA2E = 10u, ///< CH2A捕获数据丢失标志(仅模式23存在)(不是中断)
+ Tim3CB0E = 11u, ///< CH0B捕获数据丢失标志(仅模式23存在)(不是中断)
+ Tim3CB1E = 12u, ///< CH1B捕获数据丢失标志(仅模式23存在)(不是中断)
+ Tim3CB2E = 13u, ///< CH2B捕获数据丢失标志(仅模式23存在)(不是中断)
+ Tim3BkIrq = 14u, ///< 刹车中断(仅模式23存在）
+ Tim3TrigIrq = 15u, ///< 触发中断(仅模式23存在）
+}en_tim3_irq_type_t;
+
+/**
+ ******************************************************************************
+ ** \brief 测量开始结束数据类型重定义 (Edg1stEdg2nd)(模式1)
+ *****************************************************************************/
+typedef enum en_tim3_m1cr_Edge
+{
+ Tim3PwcRiseToRise = 0u, ///< 上升沿到上升沿(周期)
+ Tim3PwcFallToRise = 1u, ///< 下降沿到上升沿(低电平)
+ Tim3PwcRiseToFall = 2u, ///< 上升沿到下降沿(高电平)
+ Tim3PwcFallToFall = 3u, ///< 下降沿到下降沿(周期)
+}en_tim3_m1cr_Edge_t;
+
+/**
+ ******************************************************************************
+ ** \brief PWC测量测试模式选择数据类型重定义 (Oneshot)(模式1)
+ *****************************************************************************/
+typedef enum en_tim3_m1cr_oneshot
+{
+ Tim3PwcCycleDetect = 0u, ///< PWC循环测量
+ Tim3PwcOneShotDetect = 1u, ///< PWC单次测量
+}en_tim3_m1cr_oneshot_t;
+
+/**
+ ******************************************************************************
+ ** \brief PWC IA0选择数据类型重定义 (IA0S)(模式1)
+ *****************************************************************************/
+typedef enum en_tim3_m1_mscr_ia0s
+{
+ Tim3IA0Input = 0u, ///< IAO输入
+ Tim3XORInput = 1u, ///< IA0 ETR GATE XOR(TIM0/1/2)/IA0 IA1 IA2 XOR(TIM3)
+}en_tim3_m1_mscr_ia0s_t;
+
+/**
+ ******************************************************************************
+ ** \brief PWC IB0选择数据类型重定义 (IA0S)(模式1)
+ *****************************************************************************/
+typedef enum en_tim3_m1_mscr_ib0s
+{
+ Tim3IB0Input = 0u, ///< IBO输入
+ Tim3TsInput = 1u, ///< 内部触发TS选择信号
+}en_tim3_m1_mscr_ib0s_t;
+
+/**
+ ******************************************************************************
+ ** \brief 输出极性、输入相位 数据类型重定义 (CCPA0/CCPB0/ETP/BKP)(模式1/23)
+ *****************************************************************************/
+typedef enum en_tim3_port_polarity
+{
+ Tim3PortPositive = 0u, ///< 正常输入输出
+ Tim3PortOpposite = 1u, ///< 反向输入输出
+}en_tim3_port_polarity_t;
+
+/**
+ ******************************************************************************
+ ** \brief 滤波选择数据类型重定义 (FLTET/FLTA0/FLAB0)(模式1/23)
+ *****************************************************************************/
+typedef enum en_tim3_flt
+{
+ Tim3FltNone = 0u, ///< 无滤波
+ Tim3FltPCLKCnt3 = 4u, ///< PCLK 3个连续有效
+ Tim3FltPCLKDiv4Cnt3 = 5u, ///< PCLK/4 3个连续有效
+ Tim3FltPCLKDiv16Cnt3 = 6u, ///< PCLK/16 3个连续有效
+ Tim3FltPCLKDiv64Cnt3 = 7u, ///< PCLK/64 3个连续有效
+}en_tim3_flt_t;
+
+/**
+ ******************************************************************************
+ ** \brief 通道比较控制 数据类型重定义 (OCMA/OCMB)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23_fltr_ocm
+{
+ Tim3ForceLow = 0u, ///< 强制为0
+ Tim3ForceHigh = 1u, ///< 强制为1
+ Tim3CMPForceLow = 2u, ///< 比较匹配时强制为0
+ Tim3CMPForceHigh = 3u, ///< 比较匹配时强制为1
+ Tim3CMPInverse = 4u, ///< 比较匹配时翻转电平
+ Tim3CMPOnePrdHigh = 5u, ///< 比较匹配时输出一个计数周期的高电平
+ Tim3PWMMode1 = 6u, ///< 通道控制为PWM mode 1
+ Tim3PWMMode2 = 7u, ///< 通道控制为PWM mode 2
+}en_tim3_m23_fltr_ocm_t;
+
+/**
+ ******************************************************************************
+ ** \brief 主从模式TS数据类型重定义 (TS)(模式1/23)
+ *****************************************************************************/
+typedef enum en_tim3_mscr_ts
+{
+ Tim3Ts0ETR = 0u, ///< ETR外部输入滤波后的相位选择信号
+ Tim3Ts1TIM0TRGO = 1u, ///< Timer0的TRGO输出信号
+ Tim3Ts2TIM1TRGO = 2u, ///< Timer1的TRGO输出信号
+ Tim3Ts3TIM2TRGO = 3u, ///< Timer2的TRGO输出信号
+ Tim3Ts4TIM3TRGO = 4u, ///< Timer3的TRGO输出信号
+ //Tim3Ts5IA0ED = 5u, ///< 无效
+ Tim3Ts6IAFP = 6u, ///< CH0A 外部输输入滤波后的相位选择信号
+ Tim3Ts7IBFP = 7u, ///< CH0B 外部输输入滤波后的相位选择信
+}en_tim3_mscr_ts_t;
+
+/**
+ ******************************************************************************
+ ** \brief PWM输出模式选择数据类型重定义 (COMP)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23cr_comp
+{
+ Tim3IndependentPWM = 0u, ///< 独立PWM输出
+ Tim3ComplementaryPWM = 1u, ///< 互补PWM输出
+}en_tim3_m23cr_comp_t;
+
+/**
+ ******************************************************************************
+ ** \brief 计数方向选择数据类型重定义 (DIR)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23cr_dir
+{
+ Tim3CntUp = 0u, ///< 向上计数
+ Tim3CntDown = 1u, ///< 向下计数
+}en_tim3_m23cr_dir_t;
+
+/**
+ ******************************************************************************
+ ** \brief 计数方向选择数据类型重定义 (PWM2S)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23cr_pwm2s
+{
+ Tim3DoublePointCmp = 0u, ///< 双点比较使能，使用CCRA,CCRB比较控制OCREFA输出
+ Tim3SinglePointCmp = 1u, ///< 单点比较使能，使用CCRA比较控制OCREFA输出
+}en_tim3_m23cr_pwm2s_t;
+
+/**
+ ******************************************************************************
+ ** \brief GATE在PWM互补模式下捕获或比较功能 选择数据类型重定义 (CSG)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23cr_csg
+{
+ Tim3PWMCompGateCmpOut = 0u, ///< 在PWM互补模式下，Gate作为比较输出
+ Tim3PWMCompGateCapIn = 1u, ///< 在PWM互补模式下，Gate作为捕获输入
+}en_tim3_m23cr_csg_t;
+
+
+/**
+ ******************************************************************************
+ ** \brief 比较捕获寄存器 数据类型重定义 (CCR0A,CCR0B)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23_ccrx
+{
+ Tim3CCR0A = 0u, ///< CCR0A比较捕获寄存器
+ Tim3CCR0B = 1u, ///< CCR0B比较捕获寄存器
+ Tim3CCR1A = 2u, ///< CCR1A比较捕获寄存器
+ Tim3CCR1B = 3u, ///< CCR1B比较捕获寄存器
+ Tim3CCR2A = 4u, ///< CCR2A比较捕获寄存器
+ Tim3CCR2B = 5u, ///< CCR2B比较捕获寄存器
+}en_tim3_m23_ccrx_t;
+
+/**
+ ******************************************************************************
+ ** \brief OCREF清除源 选择数据类型重定义 (OCCS)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23ce_occs
+{
+ Tim3OC_Ref_Clr = 0u, ///< 来自VC的OC_Ref_Clr
+ Tim3ETRf = 1u, ///< 外部ETRf
+}en_tim3_m23ce_occs_t;
+
+/**
+ ******************************************************************************
+ ** \brief 比较匹配中断模式 选择数据类型重定义 (CIS/CISB)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23_cisa_cisb
+{
+ Tim3CmpIntNone = 0u, ///< 无比较匹配中断
+ Tim3CmpIntRise = 1u, ///< 比较匹配上升沿中断
+ Tim3CmpIntFall = 2u, ///< 比较匹配下降沿中断
+ Tim3CmpIntRiseFall = 3u, ///< 比较匹配上升沿下降沿中断
+}en_tim3_m23_cisa_cisb_t;
+
+/**
+ ******************************************************************************
+ ** \brief TIM3端口控制 - 刹车时CHx输出状态控制(BKSA/BKSB)(模式23)
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_tim3_m23_crchx_bks
+{
+ Tim3CHxBksHiZ = 0u, ///< 刹车使能时，CHx端口输出高阻态
+ Tim3CHxBksNorm = 1u, ///< 刹车使能时，CHx端口正常输出
+ Tim3CHxBksLow = 2u, ///< 刹车使能时，CHx端口输出低电平
+ Tim3CHxBksHigh = 3u, ///< 刹车使能时，CHx端口输出高电平
+}en_tim3_m23_crchx_bks_t;
+
+/**
+ ******************************************************************************
+** \brief TIM3端口控制 - CHx上升沿下降沿捕获(CRx/CFx)(模式23)
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_tim3_m23_crch0_cfx_crx
+{
+ Tim3CHxCapNone = 0u, ///< CHx通道捕获禁止
+ Tim3CHxCapRise = 1u, ///< CHx通道上升沿捕获使能
+ Tim3CHxCapFall = 2u, ///< CHx通道下降沿捕获使能
+ Tim3CHxCapFallRise = 3u, ///< CHx通道上升沿下降沿捕获都使能
+}en_tim3_m23_crch0_cfx_crx_t;
+
+/**
+ ******************************************************************************
+** \brief TIM3端口控制 - CHx比较捕获模式(CSA/CSB)(模式23)
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_tim3_m23_crch0_csa_csb
+{
+ Tim3CHxCmpMode = 0u, ///< CHx通道设置为比较模式
+ Tim3CHxCapMode = 1u, ///< CHx通道设置为捕获模式
+}en_tim3_m23_crch0_csa_csb_t;
+
+/**
+ ******************************************************************************
+ ** \brief 比较模式下 DMA比较触发选择 数据类型重定义 (CCDS)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23_mscr_ccds
+{
+ Tim3CmpTrigDMA = 0u, ///< 比较匹配触发DMA
+ Tim3UEVTrigDMA = 1u, ///< 事件更新代替比较匹配触发DMA
+}en_tim3_m23_mscr_ccds_t;
+
+/**
+ ******************************************************************************
+ ** \brief 主从模式选择 数据类型重定义 (MSM)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23_mscr_msm
+{
+ Tim3SlaveMode = 0u, ///< 从模式
+ Tim3MasterMode = 1u, ///< 主模式
+}en_tim3_m23_mscr_msm_t;
+
+/**
+ ******************************************************************************
+ ** \brief 触发主模式输出源 数据类型重定义 (MMS)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23_mscr_mms
+{
+ Tim3MasterUG = 0u, ///< UG(软件更新)源
+ Tim3MasterCTEN = 1u, ///< CTEN源
+ Tim3MasterUEV = 2u, ///< UEV更新源
+ Tim3MasterCMPSO = 3u, ///< 比较匹配选择输出源
+ Tim3MasterOCA0Ref = 4u, ///< OCA0_Ref源
+ Tim3MasterOCB0Ref = 5u, ///< OCB0_Ref源
+ //Tim3MasterOCB0Ref = 6u,
+ //Tim3MasterOCB0Ref = 7u,
+}en_tim3_m23_mscr_mms_t;
+
+/**
+ ******************************************************************************
+ ** \brief 触发从模式选择 数据类型重定义 (SMS)(模式23)
+ *****************************************************************************/
+typedef enum en_tim3_m23_mscr_sms
+{
+ Tim3SlaveIClk = 0u, ///< 使用内部时钟
+ Tim3SlaveResetTIM = 1u, ///< 复位功能
+ Tim3SlaveTrigMode = 2u, ///< 触发模式
+ Tim3SlaveEClk = 3u, ///< 外部时钟模式
+ Tim3SlaveCodeCnt1 = 4u, ///< 正交编码计数模式1
+ Tim3SlaveCodeCnt2 = 5u, ///< 正交编码计数模式2
+ Tim3SlaveCodeCnt3 = 6u, ///< 正交编码计数模式3
+ Tim3SlaveGateCtrl = 7u, ///< 门控功能
+}en_tim3_m23_mscr_sms_t;
+
+/**
+ ******************************************************************************
+ ** \brief 定时器运行控制数据类型重定义 (CTEN)
+ *****************************************************************************/
+typedef enum en_tim3_start
+{
+ Tim3CTENDisable = 0u, ///< 停止
+ Tim3CTENEnable = 1u, ///< 运行
+}en_tim3_start_t;
+
+/**
+ ******************************************************************************
+ ** \brief TIM3 mode0 配置结构体定义(模式0)
+ *****************************************************************************/
+typedef struct stc_tim3_mode0_cfg
+{
+ en_tim3_work_mode_t enWorkMode; ///< 工作模式设置
+ en_tim3_m0cr_gatep_t enGateP; ///< 门控极性控制
+ boolean_t bEnGate; ///< 门控使能
+ en_tim3_cr_timclkdiv_t enPRS; ///< 预除频配置
+ boolean_t bEnTog; ///< 翻转输出使能
+ en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择
+ en_tim3_m0cr_md_t enCntMode; ///< 计数模式配置
+}stc_tim3_mode0_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief TIM3 mode1 配置结构体定义(模式1)
+ *****************************************************************************/
+typedef struct stc_tim3_mode1_cfg
+{
+ en_tim3_work_mode_t enWorkMode; ///< 工作模式设置
+ en_tim3_cr_timclkdiv_t enPRS; ///< 预除频配置
+ en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择
+ en_tim3_m1cr_oneshot_t enOneShot; ///< 单次测量/循环测量选择
+}stc_tim3_mode1_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief PWC输入配置结构体定义(模式1)
+ *****************************************************************************/
+typedef struct stc_tim3_pwc_input_cfg
+{
+ en_tim3_mscr_ts_t enTsSel; ///< 触发输入源选择
+ en_tim3_m1_mscr_ia0s_t enIA0Sel; ///< CHA0输入选择
+ en_tim3_m1_mscr_ib0s_t enIB0Sel; ///< CHB0输入选择
+ en_tim3_port_polarity_t enETRPhase; ///< ETR相位选择
+ en_tim3_flt_t enFltETR; ///< ETR滤波设置
+ en_tim3_flt_t enFltIA0; ///< CHA0滤波设置
+ en_tim3_flt_t enFltIB0; ///< CHB0滤波设置
+}stc_tim3_pwc_input_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief TIM3 mode23 配置结构体定义(模式23)
+ *****************************************************************************/
+typedef struct stc_tim3_mode23_cfg
+{
+ en_tim3_work_mode_t enWorkMode; ///< 工作模式设置
+ en_tim3_m23cr_dir_t enCntDir; ///< 计数方向
+ en_tim3_cr_timclkdiv_t enPRS; ///< 时钟预除频配置
+ en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择
+ en_tim3_m23cr_comp_t enPWMTypeSel; ///< PWM模式选择（独立/互补）
+ en_tim3_m23cr_pwm2s_t enPWM2sSel; ///< OCREFA双点比较功能选择
+ boolean_t bOneShot; ///< 单次触发模式使能/禁止
+ boolean_t bURSSel; ///< 更新源选择
+}stc_tim3_mode23_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief GATE在PWM互补模式下捕获或比较功能 配置结构体定义(模式23)
+ *****************************************************************************/
+typedef struct stc_tim3_m23_gate_cfg
+{
+ en_tim3_m23cr_csg_t enGateFuncSel; ///< Gate比较、捕获功能选择
+ boolean_t bGateRiseCap; ///< GATE作为捕获功能时，上沿捕获有效控制
+ boolean_t bGateFallCap; ///< GATE作为捕获功能时，下沿捕获有效控制
+}stc_tim3_m23_gate_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief CHA/CHB通道比较控制 配置结构体定义(模式23)
+ *****************************************************************************/
+typedef struct stc_tim3_m23_compare_cfg
+{
+ en_tim3_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/捕获功能选择
+ en_tim3_m23_fltr_ocm_t enCHxACmpCtrl; ///< CH0A通道比较控制
+ en_tim3_port_polarity_t enCHxAPolarity; ///< CH0A输出极性控制
+ boolean_t bCHxACmpBufEn; ///< 比较A缓存功能 使能/禁止
+ en_tim3_m23_cisa_cisb_t enCHxACmpIntSel; ///< CHA比较匹配中断选择
+
+ en_tim3_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0B比较/捕获功能选择
+ en_tim3_m23_fltr_ocm_t enCHxBCmpCtrl; ///< CH0B通道比较控制
+ en_tim3_port_polarity_t enCHxBPolarity; ///< CH0B输出极性控制
+ boolean_t bCHxBCmpBufEn; ///< 比较B缓存功能 使能/禁止
+ en_tim3_m23_cisa_cisb_t enCHxBCmpIntSel; ///< CHB0比较匹配中断选择
+}stc_tim3_m23_compare_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief CHA/CHB通道捕获控制 配置结构体定义(模式23)
+ *****************************************************************************/
+typedef struct stc_tim3_m23_input_cfg
+{
+ en_tim3_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/捕获功能选择
+ en_tim3_m23_crch0_cfx_crx_t enCHxACapSel; ///< CH0A捕获边沿选择
+ en_tim3_flt_t enCHxAInFlt; ///< CH0A通道捕获滤波控制
+ en_tim3_port_polarity_t enCHxAPolarity; ///< CH0A输入相位
+
+ en_tim3_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0A比较/捕获功能选择
+ en_tim3_m23_crch0_cfx_crx_t enCHxBCapSel; ///< CH0B捕获边沿选择
+ en_tim3_flt_t enCHxBInFlt; ///< CH0B通道捕获滤波控制
+ en_tim3_port_polarity_t enCHxBPolarity; ///< CH0B输入相位
+
+}stc_tim3_m23_input_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief ETR输入相位滤波配置结构体定义(模式23)
+ *****************************************************************************/
+typedef struct stc_tim3_m23_etr_input_cfg
+{
+ en_tim3_port_polarity_t enETRPolarity; ///< ETR输入极性设置
+ en_tim3_flt_t enETRFlt; ///< ETR滤波设置
+}stc_tim3_m23_etr_input_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief 刹车BK输入相位滤波配置结构体定义(模式23)
+ *****************************************************************************/
+typedef struct stc_tim3_m23_bk_input_cfg
+{
+ boolean_t bEnBrake; ///< 刹车使能
+ boolean_t bEnVCBrake; ///< 使能VC刹车
+ boolean_t bEnSafetyBk; ///< 使能safety刹车
+ boolean_t bEnBKSync; ///< TIM0/TIM1/TIM2刹车同步使能
+ en_tim3_m23_crchx_bks_t enBkCH0AStat; ///< 刹车时CHA端口状态设置
+ en_tim3_m23_crchx_bks_t enBkCH0BStat; ///< 刹车时CHB端口状态设置
+ en_tim3_m23_crchx_bks_t enBkCH1AStat; ///< 刹车时CHA端口状态设置
+ en_tim3_m23_crchx_bks_t enBkCH1BStat; ///< 刹车时CHB端口状态设置
+ en_tim3_m23_crchx_bks_t enBkCH2AStat; ///< 刹车时CHA端口状态设置
+ en_tim3_m23_crchx_bks_t enBkCH2BStat; ///< 刹车时CHB端口状态设置
+ en_tim3_port_polarity_t enBrakePolarity; ///< 刹车BK输入极性设置
+ en_tim3_flt_t enBrakeFlt; ///< 刹车BK滤波设置
+}stc_tim3_m23_bk_input_cfg_t;
+
+/**
+ ******************************************************************************
+** \brief 死区功能配置结构体定义(模式23)
+ *****************************************************************************/
+typedef struct stc_tim3_m23_dt_cfg
+{
+ boolean_t bEnDeadTime; ///< 刹车时CHA端口状态设置
+ uint8_t u8DeadTimeValue; ///< 刹车时CHA端口状态设置
+}stc_tim3_m23_dt_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief 触发ADC配置结构体定义(模式23)
+ *****************************************************************************/
+typedef struct stc_tim3_m23_adc_trig_cfg
+{
+ boolean_t bEnTrigADC; ///< 触发ADC全局控制
+ boolean_t bEnUevTrigADC; ///< 事件更新触发ADC
+ boolean_t bEnCH0ACmpTrigADC; ///< CH0A比较匹配触发ADC
+ boolean_t bEnCH0BCmpTrigADC; ///< CH0B比较匹配触发ADC
+ boolean_t bEnCH1ACmpTrigADC; ///< CH0A比较匹配触发ADC
+ boolean_t bEnCH1BCmpTrigADC; ///< CH0B比较匹配触发ADC
+ boolean_t bEnCH2ACmpTrigADC; ///< CH0A比较匹配触发ADC
+ boolean_t bEnCH2BCmpTrigADC; ///< CH0B比较匹配触发ADC
+}stc_tim3_m23_adc_trig_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief DMA触发 配置结构体定义(模式23)
+ *****************************************************************************/
+typedef struct stc_tim3_m23_trig_dma_cfg
+{
+ boolean_t bUevTrigDMA; ///< 更新 触发DMA使能
+ boolean_t bTITrigDMA; ///< Trig 触发DMA功能
+ boolean_t bCmpA0TrigDMA; ///< CH0A捕获比较触发DMA使能
+ boolean_t bCmpB0TrigDMA; ///< CH0B捕获比较触发DMA使能
+ boolean_t bCmpA1TrigDMA; ///< CH1A捕获比较触发DMA使能
+ boolean_t bCmpB1TrigDMA; ///< CH1B捕获比较触发DMA使能
+ boolean_t bCmpA2TrigDMA; ///< CH2A捕获比较触发DMA使能
+ boolean_t bCmpB2TrigDMA; ///< CH2B捕获比较触发DMA使能
+ en_tim3_m23_mscr_ccds_t enCmpUevTrigDMA; ///< 比较模式下DMA比较触发选择
+}stc_tim3_m23_trig_dma_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief 主从模式 配置结构体定义(模式23)
+ *****************************************************************************/
+typedef struct stc_tim3_m23_master_slave_cfg
+{
+ en_tim3_m23_mscr_msm_t enMasterSlaveSel; ///< 主从模式选择
+ en_tim3_m23_mscr_mms_t enMasterSrc; ///< 主模式触发源选择
+ en_tim3_m23_mscr_sms_t enSlaveModeSel; ///< 从模式选择
+ en_tim3_mscr_ts_t enTsSel; ///< 触发输入源选择
+}stc_tim3_m23_master_slave_cfg_t;
+
+/**
+ ******************************************************************************
+ ** \brief OCREF清除功能 配置结构体定义(模式23)
+ *****************************************************************************/
+typedef struct stc_tim3_m23_OCREF_Clr_cfg
+{
+ en_tim3_m23ce_occs_t enOCRefClrSrcSel; ///< OCREF清除源选择
+ boolean_t bVCClrEn; ///< 是否使能来自VC的OCREF_Clr
+}stc_tim3_m23_OCREF_Clr_cfg_t;
+
+/******************************************************************************
+ * Global variable declarations ('extern', definition in C source)
+ *****************************************************************************/
+
+/******************************************************************************
+ * Global function prototypes (definition in C source)
+ *****************************************************************************/
+//中断相关函数
+
+//中断标志获取
+boolean_t Tim3_GetIntFlag(en_tim3_irq_type_t enTim3Irq);
+//中断标志清除
+en_result_t Tim3_ClearIntFlag(en_tim3_irq_type_t enTim3Irq);
+//所有中断标志清除
+en_result_t Tim3_ClearAllIntFlag(void);
+//模式0中断使能
+en_result_t Tim3_Mode0_EnableIrq(void);
+//模式1中断使能
+en_result_t Tim3_Mode1_EnableIrq (en_tim3_irq_type_t enTim3Irq);
+//模式2中断使能
+en_result_t Tim3_Mode23_EnableIrq (en_tim3_irq_type_t enTim3Irq);
+//模式0中断禁止
+en_result_t Tim3_Mode0_DisableIrq(void);
+//模式1中断禁止
+en_result_t Tim3_Mode1_DisableIrq (en_tim3_irq_type_t enTim3Irq);
+//模式2中断禁止
+en_result_t Tim3_Mode23_DisableIrq (en_tim3_irq_type_t enTim3Irq);
+
+
+//模式0初始化及相关功能操作
+
+//timer配置及初始化
+en_result_t Tim3_Mode0_Init(stc_tim3_mode0_cfg_t* pstcCfg);
+//timer 启动/停止
+en_result_t Tim3_M0_Run(void);
+en_result_t Tim3_M0_Stop(void);
+//重载值设置
+en_result_t Tim3_M0_ARRSet(uint16_t u16Data);
+//16位计数值设置/获取
+en_result_t Tim3_M0_Cnt16Set(uint16_t u16Data);
+uint16_t Tim3_M0_Cnt16Get(void);
+//32位计数值设置/获取
+en_result_t Tim3_M0_Cnt32Set(uint32_t u32Data);
+uint32_t Tim3_M0_Cnt32Get(void);
+//端口输出使能/禁止设定
+en_result_t Tim3_M0_Enable_Output(boolean_t bEnOutput);
+//翻转使能/禁止（低电平）设定
+en_result_t Tim3_M0_EnTOG(boolean_t bEnTOG);
+
+//模式1初始化及相关功能操作
+
+//timer配置及初始化
+en_result_t Tim3_Mode1_Init(stc_tim3_mode1_cfg_t* pstcCfg);
+//PWC 输入配置
+en_result_t Tim3_M1_Input_Cfg(stc_tim3_pwc_input_cfg_t* pstcCfg);
+//PWC测量边沿起始结束选择
+en_result_t Tim3_M1_PWC_Edge_Sel(en_tim3_m1cr_Edge_t enEdgeSel);
+//timer 启动/停止
+en_result_t Tim3_M1_Run(void);
+en_result_t Tim3_M1_Stop(void);
+//16位计数值设置/获取
+en_result_t Tim3_M1_Cnt16Set(uint16_t u16Data);
+uint16_t Tim3_M1_Cnt16Get(void);
+//脉冲宽度测量结果数值获取
+uint16_t Tim3_M1_PWC_CapValueGet(void);
+
+
+//模式23初始化及相关功能操作
+
+//timer配置及初始化
+en_result_t Tim3_Mode23_Init(stc_tim3_mode23_cfg_t* pstcCfg);
+//timer 启动/停止
+en_result_t Tim3_M23_Run(void);
+en_result_t Tim3_M23_Stop(void);
+//PWM输出使能
+en_result_t Tim3_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput);
+//重载值设置
+en_result_t Tim3_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn);
+//16位计数值设置/获取
+en_result_t Tim3_M23_Cnt16Set(uint16_t u16Data);
+uint16_t Tim3_M23_Cnt16Get(void);
+//比较捕获寄存器CCR0A/CCR0B设置/读取
+en_result_t Tim3_M23_CCR_Set(en_tim3_m23_ccrx_t enCCRSel, uint16_t u16Data);
+uint16_t Tim3_M23_CCR_Get(en_tim3_m23_ccrx_t enCCRSel);
+//PWM互补输出模式下，GATE功能选择
+en_result_t Tim3_M23_GateFuncSel(stc_tim3_m23_gate_cfg_t* pstcCfg);
+//主从模式配置
+en_result_t Tim3_M23_MasterSlave_Set(stc_tim3_m23_master_slave_cfg_t* pstcCfg);
+//CH0A/CH0B比较通道控制
+en_result_t Tim3_M23_PortOutput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_compare_cfg_t* pstcCfg);
+//CH0A/CH0B输入控制
+en_result_t Tim3_M23_PortInput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_input_cfg_t* pstcCfg);
+//ERT输入控制
+en_result_t Tim3_M23_ETRInput_Cfg(stc_tim3_m23_etr_input_cfg_t* pstcCfg);
+//刹车BK输入控制
+en_result_t Tim3_M23_BrakeInput_Cfg(stc_tim3_m23_bk_input_cfg_t* pstcBkCfg);
+//触发ADC控制
+en_result_t Tim3_M23_TrigADC_Cfg(stc_tim3_m23_adc_trig_cfg_t* pstcCfg);
+//死区功能
+en_result_t Tim3_M23_DT_Cfg(stc_tim3_m23_dt_cfg_t* pstcCfg);
+//重复周期设置
+en_result_t Tim3_M23_SetValidPeriod(uint8_t u8ValidPeriod);
+//OCREF清除功能
+en_result_t Tim3_M23_OCRefClr(stc_tim3_m23_OCREF_Clr_cfg_t* pstcCfg);
+//使能DMA传输
+en_result_t Tim3_M23_EnDMA(stc_tim3_m23_trig_dma_cfg_t* pstcCfg);
+//捕获比较A软件触发
+en_result_t Tim3_M23_EnSwTrigCapCmpA(en_tim3_channel_t enTim3Chx);
+//捕获比较B软件触发
+en_result_t Tim3_M23_EnSwTrigCapCmpB(en_tim3_channel_t enTim3Chx);
+//软件更新使能
+en_result_t Tim3_M23_EnSwUev(void);
+//软件触发使能
+en_result_t Tim3_M23_EnSwTrig(void);
+//软件刹车使能
+en_result_t Tim3_M23_EnSwBk(void);
+
+
+//@} // Tim3Group
+
+#ifdef __cplusplus
+#endif
+
+
+#endif /* __BT_H__ */
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
+
+
diff --git a/driver/inc/trim.h b/driver/inc/trim.h
new file mode 100644
index 0000000..5b8e7ef
--- /dev/null
+++ b/driver/inc/trim.h
@@ -0,0 +1,184 @@
+/******************************************************************************
+* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/*****************************************************************************/
+/** \file trim.h
+ **
+ ** TRIM 数据结构及API声明
+ **
+ **
+ ** History:
+ ** - 2018-04-21 Lux V1.0
+ **
+ *****************************************************************************/
+
+#ifndef __TRIM_H__
+#define __TRIM_H__
+
+/*****************************************************************************
+ * Include files
+ *****************************************************************************/
+#include "ddl.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ ******************************************************************************
+ ** \defgroup TrimGroup Clock Trimming (TRIM)
+ **
+ ******************************************************************************/
+//@{
+
+/******************************************************************************
+ ** Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Global type definitions
+ ******************************************************************************/
+
+ /**
+ ******************************************************************************
+ ** \brief 监测模式使能枚举重定义 (MON_EN)
+ *****************************************************************************/
+typedef enum en_trim_monitor
+{
+ TrimMonDisable = 0u, ///< 禁止
+ TrimMonEnable = 0x40u, ///< 使能
+}en_trim_monitor_t;
+
+ /**
+ ******************************************************************************
+ ** \brief 待校准/监测时钟选择枚举重定义 (CALCLK_SEL)
+ *****************************************************************************/
+typedef enum en_trim_calclksel
+{
+ TrimCalMskRCH = 0x000u, ///< RCH
+ TrimCalMskXTH = 0x010u, ///< XTH
+ TrimCalMskRCL = 0x020u, ///< RCL
+ TrimCalMskXTL = 0x030u, ///< XTL
+ TrimCalMskPLL = 0x100u, ///< PLL
+}en_trim_calclksel_t;
+
+/**
+ ******************************************************************************
+ ** \brief 参考时钟选择枚举重定义 (REFCLK_SEL)
+ *****************************************************************************/
+typedef enum en_trim_refclksel
+{
+ TrimRefMskRCH = 0x0u, ///< RCH
+ TrimRefMskXTH = 0x2u, ///< XTH
+ TrimRefMskRCL = 0x4u, ///< RCL
+ TrimRefMskXTL = 0x6u, ///< XTL
+ TrimRefMskIRC10K = 0x8u, ///< IRC10K
+ TrimRefMskExtClk = 0xau, ///< 外部输入时钟
+}en_trim_refclksel_t;
+
+/**
+ ******************************************************************************
+ ** \brief 中断标志类型枚举重定义
+ *****************************************************************************/
+typedef enum en_trim_inttype
+{
+ TrimStop = 0x01u, ///< 参考计数器停止标志
+ TrimCalCntOf = 0x02u, ///< 校准计数器溢出标志
+ TrimXTLFault = 0x04u, ///< XTL 失效标志
+ TrimXTHFault = 0x08u, ///< XTH 失效标志
+ TrimPLLFault = 0x10u, ///< PLL 失效标志
+}en_trim_inttype_t;
+
+/**
+ ******************************************************************************
+ ** \brief TRIM 配置结构体定义
+ *****************************************************************************/
+typedef struct stc_trim_cfg
+{
+ en_trim_monitor_t enMON; ///< 监测模式使能
+ en_trim_calclksel_t enCALCLK; ///< 校准时钟选择
+ uint32_t u32CalCon; ///< 校准计数器溢出值配置
+ en_trim_refclksel_t enREFCLK; ///< 参考时钟选择
+ uint32_t u32RefCon; ///< 参考计数器初值配置
+}stc_trim_cfg_t;
+
+/******************************************************************************
+ * Global variable declarations ('extern', definition in C source)
+ *****************************************************************************/
+
+/******************************************************************************
+ * Global function prototypes (definition in C source)
+ *****************************************************************************/
+///<<功能配置及操作函数
+///IFR&enAdcIrq)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+}
+
+/**
+ * \brief
+ * 获取ADC中断状态
+ *
+ * \param [in] enAdcIrq ADC中断类型 @ref en_adc_irq_type_t
+ *
+ * \retval Null
+ */
+void Adc_ClrIrqStatus(en_adc_irq_type_t enAdcIrq)
+{
+ M0P_ADC->ICR &= ~(uint32_t)enAdcIrq;
+}
+
+/**
+ * \brief
+ * ADC中断使能
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+void Adc_EnableIrq(void)
+{
+ M0P_ADC->CR0_f.IE = 1u;
+}
+
+/**
+ * \brief
+ * ADC中断禁止
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+void Adc_DisableIrq(void)
+{
+ M0P_ADC->CR0_f.IE = 0u;
+}
+
+/**
+ * \brief
+ * ADC初始化
+ *
+ * \param [in] pstcAdcCfg ADC配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ */
+en_result_t Adc_Init(stc_adc_cfg_t* pstcAdcCfg)
+{
+ if (NULL == pstcAdcCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ M0P_ADC->CR0 = 0x1u; ///< ADC 使能
+ delay10us(2);
+
+ M0P_ADC->CR0 |= (uint32_t)pstcAdcCfg->enAdcClkDiv |
+ (uint32_t)pstcAdcCfg->enAdcRefVolSel |
+ (uint32_t)pstcAdcCfg->enAdcOpBuf |
+ (uint32_t)pstcAdcCfg->enAdcSampCycleSel |
+ (uint32_t)pstcAdcCfg->enInRef;
+
+ M0P_ADC->CR1_f.MODE = pstcAdcCfg->enAdcMode;
+ M0P_ADC->CR1_f.ALIGN = pstcAdcCfg->enAdcAlign;
+
+ return Ok;
+}
+
+
+/**
+ * \brief
+ * ADC单次转换外部中断触发源配置
+ *
+ * \param [in] enAdcTrigSel 触发源
+ *
+ * \retval en_result_t Null
+ */
+void Adc_SglExtTrigCfg(en_adc_trig_sel_t enAdcTrigSel, boolean_t bValue)
+{
+ if(TRUE == bValue)
+ {
+ M0P_ADC->EXTTRIGGER0 |= (uint32_t)enAdcTrigSel;
+ }
+ else
+ {
+ M0P_ADC->EXTTRIGGER0 &= ~(uint32_t)enAdcTrigSel;
+ }
+
+}
+
+/**
+ * \brief
+ * ADC顺序扫描转换外部中断触发源配置
+ *
+ * \param [in] enAdcTrigSel 触发源
+ * \param [in] TRUE or FALSE
+ *
+ * \retval en_result_t Null
+ */
+void Adc_SqrExtTrigCfg(en_adc_trig_sel_t enAdcTrigSel, boolean_t bValue)
+{
+ if(TRUE == bValue)
+ {
+ M0P_ADC->EXTTRIGGER0 |= (uint32_t)enAdcTrigSel;
+ }
+ else
+ {
+ M0P_ADC->EXTTRIGGER0 &= ~(uint32_t)enAdcTrigSel;
+ }
+
+}
+
+/**
+ * \brief
+ * ADC插队扫描转换外部中断触发源配置
+ *
+ * \param [in] enAdcTrigSel 触发源
+ * \param [in] TRUE or FALSE
+ *
+ * \retval en_result_t Null
+ */
+void Adc_JqrExtTrigCfg(en_adc_trig_sel_t enAdcTrigSel, boolean_t bValue)
+{
+ if(TRUE == bValue)
+ {
+ M0P_ADC->EXTTRIGGER1 |= (uint32_t)enAdcTrigSel;
+ }
+ else
+ {
+ M0P_ADC->EXTTRIGGER1 &= ~(uint32_t)enAdcTrigSel;
+ }
+
+}
+
+
+/**
+ * \brief
+ * ADC 单次转换开始
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+
+void Adc_SGL_Start(void)
+{
+ M0P_ADC->SGLSTART = 1u;
+}
+
+/**
+ * \brief
+ * ADC 单次转换停止
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+void Adc_SGL_Stop(void)
+{
+ M0P_ADC->SGLSTART = 0u;
+}
+
+/**
+ * \brief
+ * ADC 单次转换一直转换开始
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+
+void Adc_SGL_Always_Start(void)
+{
+ M0P_ADC->ALLSTART = 1u;
+}
+
+/**
+ * \brief
+ * ADC 单次转换一直转换停止
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+
+void Adc_SGL_Always_Stop(void)
+{
+ M0P_ADC->ALLSTART = 0u;
+}
+
+/**
+ * \brief
+ * ADC 顺序扫描转换开始
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+
+void Adc_SQR_Start(void)
+{
+ M0P_ADC->SQRSTART = 1u;
+}
+
+/**
+ * \brief
+ * ADC 顺序扫描转换停止
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+void Adc_SQR_Stop(void)
+{
+ M0P_ADC->SQRSTART = 0u;
+}
+/**
+ * \brief
+ * ADC 插队扫描转换开始
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+
+void Adc_JQR_Start(void)
+{
+ M0P_ADC->JQRSTART = 1u;
+}
+
+/**
+ * \brief
+ * ADC 插队扫描转换停止
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+void Adc_JQR_Stop(void)
+{
+ M0P_ADC->JQRSTART = 0u;
+}
+
+/**
+ * \brief
+ * ADC使能
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+void Adc_Enable(void)
+{
+ M0P_ADC->CR0_f.EN = 1u;
+}
+
+/**
+ * \brief
+ * ADC除能
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+void Adc_Disable(void)
+{
+ M0P_ADC->CR0_f.EN = 0u;
+}
+
+/**
+ * \brief
+ * 配置顺序扫描转换模式
+ *
+ * \param [in] pstcAdcCfg ADC配置指针
+ * \param [in] pstcAdcNormCfg 连续转换模式配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ */
+en_result_t Adc_SqrModeCfg(stc_adc_sqr_cfg_t* pstcAdcSqrCfg)
+{
+ if ((NULL == pstcAdcSqrCfg) || (pstcAdcSqrCfg->u8SqrCnt > 16))
+ {
+ return ErrorInvalidParameter;
+ }
+
+ M0P_ADC->CR1_f.RACCCLR = 0; //ADC转换结果累加寄存器（ADC_ResultAcc）清零
+ M0P_ADC->CR1_f.RACCEN = pstcAdcSqrCfg->enResultAcc;
+ M0P_ADC->CR1_f.DMASQR = pstcAdcSqrCfg->bSqrDmaTrig;
+
+ M0P_ADC->SQR2_f.CNT = pstcAdcSqrCfg->u8SqrCnt - 1;
+
+ return Ok;
+}
+
+/**
+ * \brief
+ * 配置插队扫描转换模式
+ *
+ * \param [in] pstcAdcCfg ADC配置指针
+ * \param [in] pstcAdcNormCfg 扫描转换模式配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ */
+en_result_t Adc_JqrModeCfg(stc_adc_jqr_cfg_t* pstcAdcJqrCfg)
+{
+ if ((NULL == pstcAdcJqrCfg) || (pstcAdcJqrCfg->u8JqrCnt > 4))
+ {
+ return ErrorInvalidParameter;
+ }
+
+ M0P_ADC->CR1_f.DMASQR = pstcAdcJqrCfg->bJqrDmaTrig;
+
+ M0P_ADC->JQR_f.CNT = pstcAdcJqrCfg->u8JqrCnt - 1;
+
+ return Ok;
+}
+
+/**
+ * \brief
+ * 配置单次转换通道
+ *
+ * \param [in]enstcAdcSampCh 转换通道
+ *
+ * \retval en_result_t Ok: 成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ */
+en_result_t Adc_CfgSglChannel( en_adc_samp_ch_sel_t enstcAdcSampCh)
+{
+ M0P_ADC->CR0_f.SGLMUX = enstcAdcSampCh;
+
+ return Ok;
+}
+
+/**
+ * \brief
+ * 配置顺序扫描转换通道
+ *
+ * \param [in]enstcAdcSqrChMux 顺序扫描转换通道顺序
+ * \param [in]enstcAdcSampCh 转换通道
+ *
+ * \retval en_result_t Ok: 成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ */
+en_result_t Adc_CfgSqrChannel(en_adc_sqr_chmux_t enstcAdcSqrChMux, en_adc_samp_ch_sel_t enstcAdcSampCh)
+{
+ en_result_t enResult = Ok;
+
+ switch(enstcAdcSqrChMux)
+ {
+ case AdcSQRCH0MUX:
+ M0P_ADC->SQR0_f.CH0MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH1MUX:
+ M0P_ADC->SQR0_f.CH1MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH2MUX:
+ M0P_ADC->SQR0_f.CH2MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH3MUX:
+ M0P_ADC->SQR0_f.CH3MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH4MUX:
+ M0P_ADC->SQR0_f.CH4MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH5MUX:
+ M0P_ADC->SQR0_f.CH5MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH6MUX:
+ M0P_ADC->SQR1_f.CH6MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH7MUX:
+ M0P_ADC->SQR1_f.CH7MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH8MUX:
+ M0P_ADC->SQR1_f.CH8MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH9MUX:
+ M0P_ADC->SQR1_f.CH9MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH10MUX:
+ M0P_ADC->SQR1_f.CH10MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH11MUX:
+ M0P_ADC->SQR1_f.CH11MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH12MUX:
+ M0P_ADC->SQR2_f.CH12MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH13MUX:
+ M0P_ADC->SQR2_f.CH13MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH14MUX:
+ M0P_ADC->SQR2_f.CH14MUX = enstcAdcSampCh;
+ break;
+ case AdcSQRCH15MUX:
+ M0P_ADC->SQR2_f.CH15MUX = enstcAdcSampCh;
+ break;
+ default:
+ enResult = ErrorInvalidParameter;
+ break;
+
+ }
+
+ return enResult;
+}
+/**
+ * \brief
+ * 配置插队扫描转换通道
+ *
+ * \param [in]enstcAdcSqrChMux 插队扫描转换通道顺序
+ * \param [in]enstcAdcSampCh 转换通道
+ *
+ * \retval en_result_t Ok: 成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ */
+en_result_t Adc_CfgJqrChannel(en_adc_jqr_chmux_t enstcAdcJqrChMux, en_adc_samp_ch_sel_t enstcAdcSampCh)
+{
+ en_result_t enResult = Ok;
+
+ switch(enstcAdcJqrChMux)
+ {
+ case AdcJQRCH0MUX:
+ M0P_ADC->JQR_f.CH0MUX = enstcAdcSampCh;
+ break;
+ case AdcJQRCH1MUX:
+ M0P_ADC->JQR_f.CH1MUX = enstcAdcSampCh;
+ break;
+ case AdcJQRCH2MUX:
+ M0P_ADC->JQR_f.CH2MUX = enstcAdcSampCh;
+ break;
+ case AdcJQRCH3MUX:
+ M0P_ADC->JQR_f.CH3MUX = enstcAdcSampCh;
+ break;
+ default:
+ enResult = ErrorInvalidParameter;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ * \brief
+ * 获取采样值
+ *
+ *
+ * \retval en_result_t 采样值
+ */
+uint32_t Adc_GetSglResult(void)
+{
+ return M0P_ADC->RESULT;
+}
+
+/**
+ * \brief
+ * 获取采样值
+ *
+ * \param [in] enstcAdcSqrChMux 顺序扫描通道序号 @ref en_adc_sqr_chmux_t
+ *
+ * \retval en_result_t 采样值
+ */
+uint32_t Adc_GetSqrResult(en_adc_sqr_chmux_t enstcAdcSqrChMux)
+{
+ volatile uint32_t *BaseSqrResultAddress = &(M0P_ADC->SQRRESULT0);
+
+ return *(BaseSqrResultAddress + enstcAdcSqrChMux);
+
+}
+
+/**
+ * \brief
+ * 获取插队扫描采样值
+ *
+ * \param [in] enstcAdcJqrChMux 插队扫描通道序号@ref en_adc_jqr_chmux_t
+ *
+ * \retval en_result_t 采样值
+ */
+uint32_t Adc_GetJqrResult(en_adc_jqr_chmux_t enstcAdcJqrChMux)
+{
+ volatile uint32_t *BaseJqrResultAddress = &(M0P_ADC->JQRRESULT0);
+
+ return *(BaseJqrResultAddress + enstcAdcJqrChMux);
+
+}
+
+/**
+ * \brief
+ * 获取累加采样值
+ *
+ *
+ * \retval en_result_t 累加采样结果
+ */
+uint32_t Adc_GetAccResult(void)
+{
+ return M0P_ADC->RESULTACC;
+
+}
+
+/**
+ * \brief
+ * 清零累加采样值
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+void Adc_ClrAccResult(void)
+{
+ M0P_ADC->CR1_f.RACCCLR = 0u;
+}
+
+/**
+ * \brief
+ * ADC比较使能(比较中断)
+ *
+ * \param [in] pstcAdcIrqCfg ADC比较配置 @ref stc_adc_threshold_cfg_t
+ *
+ * \retval 无
+ */
+
+void Adc_ThresholdCfg(stc_adc_threshold_cfg_t* pstcAdcThrCfg)
+{
+ M0P_ADC->HT = pstcAdcThrCfg->u32AdcHighThd;
+ M0P_ADC->LT = pstcAdcThrCfg->u32AdcLowThd;
+
+ M0P_ADC->CR1_f.THCH = pstcAdcThrCfg->enSampChSel;
+
+ M0P_ADC->CR1_f.REGCMP = pstcAdcThrCfg->bAdcRegCmp;
+ M0P_ADC->CR1_f.HTCMP = pstcAdcThrCfg->bAdcHtCmp;
+ M0P_ADC->CR1_f.LTCMP = pstcAdcThrCfg->bAdcLtCmp;
+
+}
+
+
+//@} // AdcGroup
+
+
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
diff --git a/driver/src/adt.c b/driver/src/adt.c
new file mode 100644
index 0000000..5bcf38f
--- /dev/null
+++ b/driver/src/adt.c
@@ -0,0 +1,1657 @@
+/******************************************************************************
+* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file adt.c
+ **
+ ** Low Voltage Detect driver API.
+ ** @link Lvd Group Some description @endlink
+ **
+ ** - 2019-04-19 Husj First Version
+ **
+ ******************************************************************************/
+
+/******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "adt.h"
+
+/**
+ ******************************************************************************
+ ** \addtogroup AdtGroup
+ ******************************************************************************/
+//@{
+
+/******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+#define IS_VALID_ADT_STATE(x) ( AdtCMAF == (x)||\
+ AdtCMBF == (x)||\
+ AdtCMCF == (x)||\
+ AdtCMDF == (x)||\
+ AdtOVFF == (x)||\
+ AdtUDFF == (x)||\
+ AdtDTEF == (x)||\
+ AdtCMSAUF == (x)||\
+ AdtCMSADF == (x)||\
+ AdtCMSBUF == (x)||\
+ AdtCMSBDF == (x)||\
+ AdtCntDir == (x) )
+#define ADTIM_HW_STASTPCLR_EN 31
+#define ADTIM_HW_STASTPCLR_DIS 0x7FFFFFFF
+#define ADTIM_SS_TIM4 1
+#define ADTIM_SS_TIM5 2
+#define ADTIM_SS_TIM6 4
+#define ADTIM_PORT_BKE_NUM 15
+/******************************************************************************
+ * Global variable definitions (declared in header file with 'extern') *
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*****************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ *****************************************************************************/
+
+
+
+/*****************************************************************
+ * \brief
+ * 配置中断
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtIrq 中断类型
+ * \param [in] bEn 中断使能/禁止
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ ****************************************************************/
+en_result_t Adt_CfgIrq(M0P_ADTIM_TypeDef *ADTx,
+ en_adt_irq_type_t enAdtIrq,
+ boolean_t bEn)
+{
+ uint32_t u32Val;
+
+ u32Val = ADTx->ICONR;
+ if (bEn)
+ {
+ u32Val |= 1u<ICONR = u32Val;
+ return Ok;
+}
+
+/*******************************************************************
+ * \brief
+ * 获取中断标志
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtIrq 中断类型
+ *
+ *
+ * \retval TRUE/FALSE
+ *
+ *****************************************************************/
+boolean_t Adt_GetIrqFlag(M0P_ADTIM_TypeDef *ADTx,
+ en_adt_irq_type_t enAdtIrq)
+{
+ uint32_t u32Val;
+ boolean_t bEn;
+
+ ASSERT(IS_VALID_ADT_UNIT(enAdtUnit));
+
+ u32Val = ADTx->IFR;
+ bEn = (u32Val>>enAdtIrq) & 0x1;
+
+ return bEn;
+}
+
+/****************************************************************
+ * \brief
+ * 清除中断标志
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtIrq 中断类型
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ ****************************************************************/
+en_result_t Adt_ClearIrqFlag(M0P_ADTIM_TypeDef *ADTx,
+ en_adt_irq_type_t enAdtIrq)
+{
+ ADTx->ICLR = ~(1u<ICLR = 0;
+ return Ok;
+}
+
+/**************************************************************
+ * \brief
+ * 配置硬件递加事件
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtHwCntUp 硬件递加事件
+ *
+ * \retval en_result_t Ok: 设置成功
+ *
+ ****************************************************************/
+en_result_t Adt_CfgHwCntUp(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_cnt_t enAdtHwCntUp)
+{
+ uint32_t u32Val;
+
+
+ if (AdtHwCntMax <= enAdtHwCntUp)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ u32Val = ADTx->HCUPR;
+ ADTx->HCUPR = u32Val | (1u<HCUPR = 0;
+ return Ok;
+}
+
+
+/**********************************************************
+ * \brief
+ * 配置硬件递减事件
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtHwCntDwn 硬件递减事件
+ *
+ * \retval en_result_t Ok: 设置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ***********************************************************/
+en_result_t Adt_CfgHwCntDwn(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_cnt_t enAdtHwCntDwn)
+{
+ uint32_t u32Val;
+
+
+ if(AdtHwCntMax <= enAdtHwCntDwn)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ u32Val = ADTx->HCDOR;
+ ADTx->HCDOR = u32Val | (1u<HCDOR = 0;
+ return Ok;
+}
+
+/******************************************************************
+ * \brief
+ * 配置硬件启动事件
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtHwStart 硬件启动事件
+ *
+ * \retval en_result_t Ok: 设置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ *******************************************************************/
+en_result_t Adt_CfgHwStart(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwStart)
+{
+ uint32_t u32Val;
+
+
+ if(AdtHwTrigEnd <= enAdtHwStart)
+ {
+ return ErrorInvalidParameter;
+ }
+ u32Val = ADTx->HSTAR;
+ ADTx->HSTAR = u32Val | (1u<HSTAR = 0;
+ return Ok;
+}
+
+/*********************************************************************
+ * \brief
+ * 使能硬件启动
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ * \retval en_result_t Ok: 设置成功
+ *
+ *********************************************************************/
+en_result_t Adt_EnableHwStart(M0P_ADTIM_TypeDef *ADTx)
+{
+ uint32_t u32Val;
+
+ u32Val = ADTx->HSTAR;
+ ADTx->HSTAR = u32Val | (1u<HSTAR;
+ ADTx->HSTAR = u32Val & ADTIM_HW_STASTPCLR_DIS;
+ return Ok;
+}
+
+/****************************************************************
+ * \brief
+ * 配置硬件停止事件
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtHwStop 硬件停止事件
+ *
+ * \retval en_result_t Ok: 设置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ***************************************************************/
+en_result_t Adt_CfgHwStop(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwStop)
+{
+ uint32_t u32Val;
+
+ if(AdtHwTrigEnd <= enAdtHwStop)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ u32Val = ADTx->HSTPR;
+ ADTx->HSTPR = u32Val | (1u<HSTPR = 0;
+ return Ok;
+}
+
+/*************************************************************
+ * \brief
+ * 使能硬件停止
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ * \retval en_result_t Ok: 设置成功
+ *
+ **********************************************************/
+en_result_t Adt_EnableHwStop(M0P_ADTIM_TypeDef *ADTx)
+{
+ uint32_t u32Val;
+
+ u32Val = ADTx->HSTPR;
+ ADTx->HSTPR = u32Val | (1u<HSTPR;
+ ADTx->HSTPR = u32Val & ADTIM_HW_STASTPCLR_DIS;
+ return Ok;
+}
+
+/**************************************************************************
+ * \brief
+ * 配置硬件清零事件
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtHwClear 硬件清零事件
+ *
+ * \retval en_result_t Ok: 设置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ *************************************************************************/
+en_result_t Adt_CfgHwClear(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwClear)
+{
+ uint32_t u32Val;
+
+
+ if(AdtHwTrigEnd <= enAdtHwClear)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ u32Val = ADTx->HCELR;
+ ADTx->HCELR = u32Val | (1u<HCELR = 0;
+ return Ok;
+}
+
+/***************************************************************************
+ * \brief
+ * 使能硬件清零
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ * \retval en_result_t Ok: 设置成功
+ *
+ *************************************************************************/
+en_result_t Adt_EnableHwClear(M0P_ADTIM_TypeDef *ADTx)
+{
+ uint32_t u32Val;
+
+ u32Val = ADTx->HCELR;
+ ADTx->HCELR = u32Val | (1u<HCELR;
+ ADTx->HCELR = u32Val & ADTIM_HW_STASTPCLR_DIS;
+ return Ok;
+}
+
+/*******************************************************************
+ * \brief
+ * 配置硬件捕获A事件
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtHwCaptureA 硬件捕获A事件选择
+ *
+ * \retval en_result_t Ok: 设置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ *******************************************************************/
+en_result_t Adt_CfgHwCaptureA(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwCaptureA)
+{
+ uint32_t u32Val;
+
+
+ if(AdtHwTrigEnd <= enAdtHwCaptureA)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ u32Val = ADTx->HCPAR;
+ ADTx->HCPAR = u32Val | (1u<PCONR_f.CAPCA = 1;
+ return Ok;
+}
+
+/************************************************************************
+ * \brief
+ * 清除硬件捕获A事件
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ * \retval en_result_t Ok: 设置成功
+ *
+ ***********************************************************************/
+en_result_t Adt_ClearHwCaptureA(M0P_ADTIM_TypeDef *ADTx)
+{
+ ADTx->HCPAR = 0;
+ return Ok;
+}
+
+/*********************************************************************
+ * \brief
+ * 配置硬件捕获B事件
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtHwCaptureB 硬件捕获B事件选择
+ *
+ * \retval en_result_t Ok: 设置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ********************************************************************/
+en_result_t Adt_CfgHwCaptureB(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwCaptureB)
+{
+ uint32_t u32Val;
+
+
+ if(AdtHwTrigEnd <= enAdtHwCaptureB)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ u32Val = ADTx->HCPBR;
+ ADTx->HCPBR = u32Val | (1u<PCONR_f.CAPCB = 1;
+ return Ok;
+}
+
+/********************************************************************
+ * \brief
+ * 清除硬件捕获B事件
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ * \retval en_result_t Ok: 设置成功
+ *
+ *******************************************************************/
+en_result_t Adt_ClearHwCaptureB(M0P_ADTIM_TypeDef *ADTx)
+{
+ ADTx->HCPBR = 0;
+ return Ok;
+}
+
+/*****************************************************************
+ * \brief
+ * 软件同步开始
+ *
+ * \param [in] pstcAdtSwSyncStart 软件同步开始指针
+ *
+ * \retval en_result_t Ok: 设置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ***************************************************************/
+en_result_t Adt_SwSyncStart(stc_adt_sw_sync_t* pstcAdtSwSyncStart)
+{
+ uint32_t u32Val = 0;
+
+ if (NULL == pstcAdtSwSyncStart)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ if (pstcAdtSwSyncStart->bAdTim4)
+ {
+ u32Val |= ADTIM_SS_TIM4;
+ }
+ if (pstcAdtSwSyncStart->bAdTim5)
+ {
+ u32Val |= ADTIM_SS_TIM5;
+ }
+ if (pstcAdtSwSyncStart->bAdTim6)
+ {
+ u32Val |= ADTIM_SS_TIM6;
+ }
+
+ M0P_ADTIM4->SSTAR = u32Val;
+ return Ok;
+}
+
+/***************************************************************
+ * \brief
+ * 软件同步停止
+ *
+ * \param [in] pstcAdtSwSyncStop 软件同步停止指针
+ *
+ * \retval en_result_t Ok: 设置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ***************************************************************/
+en_result_t Adt_SwSyncStop(stc_adt_sw_sync_t* pstcAdtSwSyncStop)
+{
+ uint32_t u32Val = 0;
+
+ if (NULL == pstcAdtSwSyncStop)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ if (pstcAdtSwSyncStop->bAdTim4)
+ {
+ u32Val |= ADTIM_SS_TIM4;
+ }
+ if (pstcAdtSwSyncStop->bAdTim5)
+ {
+ u32Val |= ADTIM_SS_TIM5;
+ }
+ if (pstcAdtSwSyncStop->bAdTim6)
+ {
+ u32Val |= ADTIM_SS_TIM6;
+ }
+
+ M0P_ADTIM4->SSTPR = u32Val;
+ return Ok;
+}
+
+/*****************************************************************
+ * \brief
+ * 软件同步清零
+ *
+ * \param [in] pstcAdtSwSyncClear 软件同步清零指针
+ *
+ * \retval en_result_t Ok: 设置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ *******************************************************************/
+en_result_t Adt_SwSyncClear(stc_adt_sw_sync_t* pstcAdtSwSyncClear)
+{
+ uint32_t u32Val = 0;
+
+ if (NULL == pstcAdtSwSyncClear)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ if (pstcAdtSwSyncClear->bAdTim4)
+ {
+ u32Val |= ADTIM_SS_TIM4;
+ }
+ if (pstcAdtSwSyncClear->bAdTim5)
+ {
+ u32Val |= ADTIM_SS_TIM5;
+ }
+ if (pstcAdtSwSyncClear->bAdTim6)
+ {
+ u32Val |= ADTIM_SS_TIM6;
+ }
+
+ M0P_ADTIM4->SCLRR = u32Val;
+ return Ok;
+}
+
+/*******************************************************************
+ * \brief
+ * 获取软件同步运行状态
+ *
+ * \param [in] pstcAdtSwSyncState ADV Timer软件同步运行状态指针
+ *
+ * \retval en_result_t Ok: 设置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ *******************************************************************/
+en_result_t Adt_GetSwSyncState(stc_adt_sw_sync_t* pstcAdtSwSyncState)
+{
+ if (NULL == pstcAdtSwSyncState)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ if (M0P_ADTIM4->SSTAR & ADTIM_SS_TIM4)
+ {
+ pstcAdtSwSyncState->bAdTim4 = TRUE;
+ }
+ else
+ {
+ pstcAdtSwSyncState->bAdTim4 = FALSE;
+ }
+ if (M0P_ADTIM4->SSTAR & ADTIM_SS_TIM5)
+ {
+ pstcAdtSwSyncState->bAdTim5 = TRUE;
+ }
+ else
+ {
+ pstcAdtSwSyncState->bAdTim5 = FALSE;
+ }
+ if (M0P_ADTIM4->SSTAR & ADTIM_SS_TIM6)
+ {
+ pstcAdtSwSyncState->bAdTim6 = TRUE;
+ }
+ else
+ {
+ pstcAdtSwSyncState->bAdTim6 = FALSE;
+ }
+ return Ok;
+}
+
+/************************************************************************
+ * \brief
+ * AOS触发配置
+ *
+ * \param [in] pstcAdtAosTrigCfg 触发配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ************************************************************************/
+en_result_t Adt_AosTrigCfg(stc_adt_aos_trig_cfg_t* pstcAdtAosTrigCfg)
+{
+ if (NULL == pstcAdtAosTrigCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ M0P_ADTIM4->ITRIG_f.IAOS0S = pstcAdtAosTrigCfg->enAos0TrigSrc;
+ M0P_ADTIM4->ITRIG_f.IAOS1S = pstcAdtAosTrigCfg->enAos1TrigSrc;
+ M0P_ADTIM4->ITRIG_f.IAOS2S = pstcAdtAosTrigCfg->enAos2TrigSrc;
+ M0P_ADTIM4->ITRIG_f.IAOS3S = pstcAdtAosTrigCfg->enAos3TrigSrc;
+ return Ok;
+}
+
+/**********************************************************************
+ * \brief
+ * 中断触发配置
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] pstcAdtIrqTrigCfg 触发配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ***********************************************************************/
+en_result_t Adt_IrqTrigCfg(M0P_ADTIM_TypeDef *ADTx,
+ stc_adt_irq_trig_cfg_t* pstcAdtIrqTrigCfg)
+{
+ if(NULL == pstcAdtIrqTrigCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ ADTx->CR_f.CMAE = pstcAdtIrqTrigCfg->bAdtCntMatchATrigEn;
+ ADTx->CR_f.CMBE = pstcAdtIrqTrigCfg->bAdtCntMatchBTrigEn;
+ ADTx->CR_f.CMCE = pstcAdtIrqTrigCfg->bAdtCntMatchCTrigEn;
+ ADTx->CR_f.CMDE = pstcAdtIrqTrigCfg->bAdtCntMatchDTrigEn;
+ ADTx->CR_f.OVFE = pstcAdtIrqTrigCfg->bAdtOverFlowTrigEn;
+ ADTx->CR_f.UDFE = pstcAdtIrqTrigCfg->bAdtUnderFlowTrigEn;
+ ADTx->CR_f.DMA_G_CMA = pstcAdtIrqTrigCfg->bAdtCntMatchATrigDmaEn;
+ ADTx->CR_f.DMA_G_CMB = pstcAdtIrqTrigCfg->bAdtCntMatchBTrigDmaEn;
+ ADTx->CR_f.DMA_G_CMC = pstcAdtIrqTrigCfg->bAdtCntMatchCTrigDmaEn;
+ ADTx->CR_f.DMA_G_CMD = pstcAdtIrqTrigCfg->bAdtCntMatchDTrigDmaEn;
+ ADTx->CR_f.DMA_G_OVF = pstcAdtIrqTrigCfg->bAdtOverFlowTrigDmaEn;
+ ADTx->CR_f.DMA_G_UDF = pstcAdtIrqTrigCfg->bAdtUnderFlowTrigDmaEn;
+ ADTx->CR_f.DMA_S_CMA = pstcAdtIrqTrigCfg->bAdtSpecilMatchATrigDmaEn;
+ ADTx->CR_f.DMA_S_CMB = pstcAdtIrqTrigCfg->bAdtSpecilMatchBTrigDmaEn;
+
+ return Ok;
+}
+
+/*************************************************************************
+ * \brief
+ * 端口触发配置
+ *
+ * \param [in] enAdtTrigPort 触发端口
+ * \param [in] pstcAdtPortTrigCfg 触发配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ *************************************************************************/
+en_result_t Adt_PortTrigCfg(en_adt_trig_port_t enAdtTrigPort,
+ stc_adt_port_trig_cfg_t* pstcAdtPortTrigCfg)
+{
+ if (NULL == pstcAdtPortTrigCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ switch (enAdtTrigPort)
+ {
+ case AdtTrigA:
+ M0P_ADTIM4->TTRIG_f.TRIGAS = pstcAdtPortTrigCfg->enTrigSrc;
+ M0P_ADTIM4->FCONR_f.NOFIENTA = pstcAdtPortTrigCfg->bFltEn;
+ M0P_ADTIM4->FCONR_f.NOFICKTA = pstcAdtPortTrigCfg->enFltClk;
+ break;
+
+ case AdtTrigB:
+ M0P_ADTIM4->TTRIG_f.TRIGBS = pstcAdtPortTrigCfg->enTrigSrc;
+ M0P_ADTIM4->FCONR_f.NOFIENTB = pstcAdtPortTrigCfg->bFltEn;
+ M0P_ADTIM4->FCONR_f.NOFICKTB = pstcAdtPortTrigCfg->enFltClk;
+ break;
+
+ case AdtTrigC:
+ M0P_ADTIM4->TTRIG_f.TRIGCS = pstcAdtPortTrigCfg->enTrigSrc;
+ M0P_ADTIM4->FCONR_f.NOFIENTC = pstcAdtPortTrigCfg->bFltEn;
+ M0P_ADTIM4->FCONR_f.NOFICKTC = pstcAdtPortTrigCfg->enFltClk;
+ break;
+
+ case AdtTrigD:
+ M0P_ADTIM4->TTRIG_f.TRIGDS = pstcAdtPortTrigCfg->enTrigSrc;
+ M0P_ADTIM4->FCONR_f.NOFIENTD = pstcAdtPortTrigCfg->bFltEn;
+ M0P_ADTIM4->FCONR_f.NOFICKTD = pstcAdtPortTrigCfg->enFltClk;
+ break;
+
+ default:
+ return ErrorInvalidParameter;
+ }
+
+ return Ok;
+}
+
+/***********************************************************************
+ * \brief
+ * CHxX端口配置
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtCHxXPort CHxX端口
+ * \param [in] pstcAdtCHxXCfg CHxX端口配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ *********************************************************************/
+en_result_t Adt_CHxXPortCfg(M0P_ADTIM_TypeDef *ADTx,
+ en_adt_CHxX_port_t enAdtCHxXPort,
+ stc_adt_CHxX_port_cfg_t* pstcAdtCHxXCfg)
+{
+ if(NULL == pstcAdtCHxXCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ switch (enAdtCHxXPort)
+ {
+ case AdtCHxA:
+ ADTx->PCONR_f.CAPCA = pstcAdtCHxXCfg->enCap;
+ ADTx->PCONR_f.STACA = pstcAdtCHxXCfg->enStaOut;
+ ADTx->PCONR_f.STPCA = pstcAdtCHxXCfg->enStpOut;
+ ADTx->PCONR_f.STASTPSA = pstcAdtCHxXCfg->enStaStp;
+ ADTx->PCONR_f.CMPCA = pstcAdtCHxXCfg->enCmpc;
+ ADTx->PCONR_f.PERCA = pstcAdtCHxXCfg->enPerc;
+ ADTx->PCONR_f.OUTENA = pstcAdtCHxXCfg->bOutEn;
+ ADTx->PCONR_f.DISSELA = pstcAdtCHxXCfg->enDisSel;
+ ADTx->PCONR_f.DISVALA = pstcAdtCHxXCfg->enDisVal;
+ ADTx->FCONR_f.NOFIENGA = pstcAdtCHxXCfg->bFltEn;
+ ADTx->FCONR_f.NOFICKGA = pstcAdtCHxXCfg->enFltClk;
+ break;
+
+ case AdtCHxB:
+ ADTx->PCONR_f.CAPCB = pstcAdtCHxXCfg->enCap;
+ ADTx->PCONR_f.STACB = pstcAdtCHxXCfg->enStaOut;
+ ADTx->PCONR_f.STPCB = pstcAdtCHxXCfg->enStpOut;
+ ADTx->PCONR_f.STASTPSB = pstcAdtCHxXCfg->enStaStp;
+ ADTx->PCONR_f.CMPCB = pstcAdtCHxXCfg->enCmpc;
+ ADTx->PCONR_f.PERCB = pstcAdtCHxXCfg->enPerc;
+ ADTx->PCONR_f.OUTENB = pstcAdtCHxXCfg->bOutEn;
+ ADTx->PCONR_f.DISSELB = pstcAdtCHxXCfg->enDisSel;
+ ADTx->PCONR_f.DISVALB = pstcAdtCHxXCfg->enDisVal;
+ ADTx->FCONR_f.NOFIENGB = pstcAdtCHxXCfg->bFltEn;
+ ADTx->FCONR_f.NOFICKGB = pstcAdtCHxXCfg->enFltClk;
+ break;
+
+ default:
+ return ErrorInvalidParameter;
+ }
+
+ return Ok;
+}
+
+/************************************************************************
+ * \brief
+ * 使能端口刹车
+ *
+ * \param [in] port 端口
+ * \param [in] pstcAdtBrkPtCfg 端口刹车配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ************************************************************************/
+en_result_t Adt_EnableBrakePort(uint8_t port, stc_adt_break_port_cfg_t* pstcAdtBrkPtCfg)
+{
+ uint32_t u32Val;
+
+ if (NULL == pstcAdtBrkPtCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ u32Val = M0P_ADTIM4->PTBKP;
+ u32Val &= ~(1u<PTBKP = u32Val | (pstcAdtBrkPtCfg->enPol<PTBKS;
+ M0P_ADTIM4->PTBKS = u32Val | (1u<PTBKS = 0;
+}
+
+/*********************************************************************
+ * \brief
+ * 无效条件3配置
+ *
+ * \param [in] pstcAdtDisable3 无效条件3配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ********************************************************************/
+en_result_t Adt_Disable3Cfg(stc_adt_disable_3_cfg_t* pstcAdtDisable3)
+{
+ uint8_t i;
+
+ if (NULL == pstcAdtDisable3)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ Adt_ClearBrakePort();
+ for (i = 0; i <= ADTIM_PORT_BKE_NUM; i++)
+ {
+ if (TRUE == pstcAdtDisable3->stcBrkPtCfg[i].bPortEn)
+ {
+ Adt_EnableBrakePort(i, &pstcAdtDisable3->stcBrkPtCfg[i]);
+ }
+ }
+
+ M0P_ADTIM4->AOSSR_f.BFILTEN = pstcAdtDisable3->bFltEn;
+ M0P_ADTIM4->AOSSR_f.BFILTS = pstcAdtDisable3->enFltClk;
+
+ return Ok;
+}
+
+/*********************************************************************
+ * \brief 软件刹车 Enable/Disable(仅适用于无效条件3使能的情况下)
+ *
+ * \param [in] bSwBrk 软件刹车使能/禁止
+ *
+ * \retval en_result_t Ok: 配置成功
+ ********************************************************************/
+en_result_t Adt_SwBrake(boolean_t bSwBrk)
+{
+ M0P_ADTIM4->AOSSR_f.SOFTBK = bSwBrk;
+
+ return Ok;
+}
+
+/*******************************************************************
+ * \brief
+ * 获取端口刹车标志
+ *
+ * \param none
+ *
+ * \retval TRUE or FALSE
+ ******************************************************************/
+boolean_t Adt_GetPortBrakeFlag(void)
+{
+ return M0P_ADTIM4->AOSSR_f.FBRAKE;
+}
+
+/******************************************************************
+ * \brief
+ * 清除端口刹车标志
+ *
+ * \param none
+ *
+ * \retval none
+ ******************************************************************/
+void Adt_ClearPortBrakeFlag(void)
+{
+ M0P_ADTIM4->AOSCL_f.FBRAKE = 0;
+}
+
+/********************************************************************
+ * \brief
+ * 无效条件1配置
+ *
+ * \param [in] pstcAdtDisable1 无效条件1配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ********************************************************************/
+en_result_t Adt_Disable1Cfg(stc_adt_disable_1_cfg_t* pstcAdtDisable1)
+{
+
+ if (NULL == pstcAdtDisable1)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ M0P_ADTIM4->AOSSR_f.SMH2 = pstcAdtDisable1->bTim6OutSH;
+ M0P_ADTIM4->AOSSR_f.SMH1 = pstcAdtDisable1->bTim5OutSH;
+ M0P_ADTIM4->AOSSR_f.SMH0 = pstcAdtDisable1->bTim4OutSH;
+ M0P_ADTIM4->AOSSR_f.SML2 = pstcAdtDisable1->bTim6OutSL;
+ M0P_ADTIM4->AOSSR_f.SML1 = pstcAdtDisable1->bTim5OutSL;
+ M0P_ADTIM4->AOSSR_f.SML0 = pstcAdtDisable1->bTim4OutSL;
+
+ return Ok;
+}
+
+/********************************************************************
+ * \brief
+ * 获取同高同低刹车标志
+ *
+ * \param none
+ *
+ * \retval TRUE or FALSE
+ ********************************************************************/
+boolean_t Adt_GetSameBrakeFlag(void)
+{
+ return M0P_ADTIM4->AOSSR_f.FSAME;
+}
+
+/*********************************************************************
+ * \brief
+ * 清除同高同低刹车标志
+ *
+ * \param none
+ *
+ * \retval none
+ *********************************************************************/
+void Adt_ClearSameBrakeFlag(void)
+{
+ M0P_ADTIM4->AOSCL_f.FSAME = 0;
+}
+
+/********************************************************************
+ * \brief
+ * PWM展频配置
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] pstcAdtPwmDitherCfg PWM展频配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ *********************************************************************/
+en_result_t Adt_PwmDitherCfg(M0P_ADTIM_TypeDef *ADTx, stc_adt_pwm_dither_cfg_t* pstcAdtPwmDitherCfg)
+{
+
+
+ if (NULL == pstcAdtPwmDitherCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ ADTx->CR_f.DITENS = pstcAdtPwmDitherCfg->enAdtPDType;
+ ADTx->CR_f.DITENB = pstcAdtPwmDitherCfg->bTimxBPDEn;
+ ADTx->CR_f.DITENA = pstcAdtPwmDitherCfg->bTimxAPDEn;
+
+ return Ok;
+}
+
+/**********************************************************************
+ * \brief
+ * ADT初始化
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] pstcAdtBaseCntCfg 计数配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ **********************************************************************/
+en_result_t Adt_Init(M0P_ADTIM_TypeDef *ADTx, stc_adt_basecnt_cfg_t* pstcAdtBaseCntCfg)
+{
+
+
+ if(NULL == pstcAdtBaseCntCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ if (AdtTriangleModeB < pstcAdtBaseCntCfg->enCntMode)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ ADTx->GCONR_f.MODE = pstcAdtBaseCntCfg->enCntMode;
+ ADTx->GCONR_f.DIR = pstcAdtBaseCntCfg->enCntDir;
+ ADTx->GCONR_f.CKDIV = pstcAdtBaseCntCfg->enCntClkDiv;
+
+ return Ok;
+}
+
+/************************************************************************
+ * \brief
+ * ADT Deinit
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ ***********************************************************************/
+en_result_t Adt_DeInit(M0P_ADTIM_TypeDef *ADTx)
+{
+ ADTx->GCONR_f.START = 0;
+ ADTx->CNTER = 0;
+ ADTx->PCONR = 0;
+ ADTx->GCONR = 0x00000100;
+ ADTx->DCONR = 0;
+ ADTx->ICONR = 0;
+ ADTx->BCONR = 0;
+ ADTx->FCONR = 0;
+ ADTx->VPERR = 0;
+ ADTx->PERAR = 0xFFFF;
+ ADTx->PERBR = 0xFFFF;
+ ADTx->GCMAR = 0xFFFF;
+ ADTx->GCMBR = 0xFFFF;
+ ADTx->GCMCR = 0xFFFF;
+ ADTx->GCMDR = 0xFFFF;
+ ADTx->DTDAR = 0xFFFF;
+ ADTx->DTUAR = 0xFFFF;
+ ADTx->HSTAR = 0;
+ ADTx->HSTPR = 0;
+ ADTx->HCELR = 0;
+ ADTx->HCPAR = 0;
+ ADTx->HCPBR = 0;
+ ADTx->HCUPR = 0;
+ ADTx->HCDOR = 0;
+ ADTx->SSTAR = 0;
+ ADTx->SSTPR = 0;
+ ADTx->SCLRR = 0;
+ ADTx->IFR = 0;
+ ADTx->CR = 0x00000300;
+ ADTx->AOSSR = 0;
+ ADTx->AOSCL = 0;
+ ADTx->PTBKS = 0;
+ ADTx->PTBKP = 0;
+ ADTx->TTRIG = 0;
+ ADTx->ITRIG = 0;
+
+ return Ok;
+}
+
+/***********************************************************************
+ * \brief
+ * 开始计数
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ ***********************************************************************/
+en_result_t Adt_StartCount(M0P_ADTIM_TypeDef *ADTx)
+{
+
+ ADTx->GCONR_f.START = 1;
+
+ return Ok;
+}
+
+/***********************************************************************
+ * \brief
+ * 停止计数
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ **********************************************************************/
+en_result_t Adt_StopCount(M0P_ADTIM_TypeDef *ADTx)
+{
+ ADTx->GCONR_f.START = 0;
+
+ return Ok;
+}
+
+/********************************************************************
+ * \brief
+ * 设置计数值
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] u16Value 计数值
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ *******************************************************************/
+en_result_t Adt_SetCount(M0P_ADTIM_TypeDef *ADTx, uint16_t u16Value)
+{
+ ADTx->CNTER_f.CNT = u16Value;
+ return Ok;
+}
+
+/********************************************************************
+ * \brief
+ * 获取计数值
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ *
+ * \retval uint16_t u16Value: 当前计数值
+ *
+ *******************************************************************/
+uint16_t Adt_GetCount(M0P_ADTIM_TypeDef *ADTx)
+{
+ uint16_t u16Value;
+
+ ASSERT(IS_VALID_ADT_UNIT(enAdtUnit));
+
+ u16Value = ADTx->CNTER_f.CNT;
+
+ return u16Value;
+}
+
+/**************************************************************************
+ * \brief
+ * 清除计数值
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ **************************************************************************/
+en_result_t Adt_ClearCount(M0P_ADTIM_TypeDef *ADTx)
+{
+ ADTx->CNTER_f.CNT = 0;
+ return Ok;
+}
+
+/*************************************************************************
+ * \brief
+ * 获取有效周期计数值
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ * \retval uint8_t u8TempCnt: 有效周期值
+ *
+ *************************************************************************/
+uint8_t Adt_GetVperNum(M0P_ADTIM_TypeDef *ADTx)
+{
+ uint8_t u8TempCnt;
+
+
+ ASSERT(IS_VALID_ADT_UNIT(enAdtUnit));
+
+ u8TempCnt = ADTx->STFLR_f.VPERNUM;
+
+ return u8TempCnt;
+}
+
+/*************************************************************************
+ * \brief
+ * 获取状态标志
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+* \param [in] enstate 状态标志类型
+ *
+ * \retval TURE/FALSE
+ *
+ *************************************************************************/
+boolean_t Adt_GetState(M0P_ADTIM_TypeDef *ADTx, en_adt_state_type_t enstate)
+{
+
+
+ ASSERT(IS_VALID_ADT_UNIT(enAdtUnit));
+ ASSERT(IS_VALID_ADT_STATE(enstate));
+
+ return GetBit(((uint32_t)&ADTx->STFLR), enstate);
+}
+
+/***********************************************************************
+ * \brief
+ * 配置计数周期
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] u16Period 计数周期值
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ ***********************************************************************/
+en_result_t Adt_SetPeriod(M0P_ADTIM_TypeDef *ADTx, uint16_t u16Period)
+{
+ ADTx->PERAR = u16Period;
+
+ return Ok;
+}
+
+/***********************************************************************
+ * \brief
+ * 配置计数周期缓冲
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] u16PeriodBuf 计数周期缓冲值
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ ***********************************************************************/
+en_result_t Adt_SetPeriodBuf(M0P_ADTIM_TypeDef *ADTx, uint16_t u16PeriodBuf)
+{
+ ADTx->PERBR = u16PeriodBuf;
+ ADTx->BCONR_f.BENP = 1u;
+
+ return Ok;
+}
+
+/**********************************************************************
+ * \brief
+ * 清除计数周期缓冲
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ **********************************************************************/
+en_result_t Adt_ClearPeriodBuf(M0P_ADTIM_TypeDef *ADTx)
+{
+ ADTx->BCONR_f.BENP = 0;
+ ADTx->PERBR = 0;
+
+ return Ok;
+}
+
+/***********************************************************************
+ * \brief
+ * 配置有效计数周期
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] pstcAdtValidPerCfg 有效计数周期配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ***********************************************************************/
+en_result_t Adt_SetValidPeriod(M0P_ADTIM_TypeDef *ADTx,
+ stc_adt_validper_cfg_t* pstcAdtValidPerCfg)
+{
+
+
+ if(NULL == pstcAdtValidPerCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ ADTx->VPERR_f.PCNTS = pstcAdtValidPerCfg->enValidCnt;
+ ADTx->VPERR_f.PCNTE = pstcAdtValidPerCfg->enValidCdt;
+ ADTx->VPERR_f.GEPERID = pstcAdtValidPerCfg->bPeriodD;
+ ADTx->VPERR_f.GEPERIC = pstcAdtValidPerCfg->bPeriodC;
+ ADTx->VPERR_f.GEPERIB = pstcAdtValidPerCfg->bPeriodB;
+ ADTx->VPERR_f.GEPERIA = pstcAdtValidPerCfg->bPeriodA;
+
+ return Ok;
+}
+
+/************************************************************************
+ * \brief
+ * 配置比较输出计数基准值
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtCompare 通用比较基准寄存器
+ * \param [in] u16Compare 比较基准值
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ *************************************************************************/
+en_result_t Adt_SetCompareValue(M0P_ADTIM_TypeDef *ADTx,
+ en_adt_compare_t enAdtCompare,
+ uint16_t u16Compare)
+{
+ if (AdtCompareA == enAdtCompare)
+ {
+ ADTx->GCMAR = u16Compare;
+ }
+ else if (AdtCompareB == enAdtCompare)
+ {
+ ADTx->GCMBR = u16Compare;
+ }
+ else if (AdtCompareC == enAdtCompare)
+ {
+ ADTx->GCMCR = u16Compare;
+ }
+ else if (AdtCompareD == enAdtCompare)
+ {
+ ADTx->GCMDR = u16Compare;
+ }
+ else
+ {
+ return ErrorInvalidParameter;
+ }
+
+ return Ok;
+}
+
+/************************************************************************
+ * \brief
+ * 配置专用比较计数基准值
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtSpclCmp 专用比较基准值寄存器
+ * \param [in] u16SpclCmp 比较基准值
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ *************************************************************************/
+en_result_t Adt_SetSpecilCompareValue(M0P_ADTIM_TypeDef *ADTx,
+ en_adt_special_compare_t enAdtSpclCmp,
+ uint16_t u16SpclCmp)
+{
+ if (AdtSpclCompA == enAdtSpclCmp)
+ {
+ ADTx->SCMAR_f.SCMA = u16SpclCmp;
+ }
+ else if (AdtSpclCompB == enAdtSpclCmp)
+ {
+ ADTx->SCMBR_f.SCMB = u16SpclCmp;
+ }
+ else
+ {
+ return ErrorInvalidParameter;
+ }
+
+ return Ok;
+}
+
+/**********************************************************************
+ * \brief
+ * 配置通用比较值/捕获值缓存传送
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtCHxXPort TIMxX通道
+ * \param [in] bCompareBufEn 通用比较值缓存传送使能
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ **********************************************************************/
+en_result_t Adt_EnableValueBuf(M0P_ADTIM_TypeDef *ADTx,
+ en_adt_CHxX_port_t enAdtCHxXPort,
+ boolean_t bCompareBufEn)
+{
+ if (AdtCHxA == enAdtCHxXPort)
+ {
+ ADTx->BCONR_f.BENA = bCompareBufEn;
+ }
+ else if (AdtCHxB == enAdtCHxXPort)
+ {
+ ADTx->BCONR_f.BENB = bCompareBufEn;
+ }
+ else
+ {
+ return ErrorInvalidParameter;
+ }
+
+ return Ok;
+}
+
+/***********************************************************************
+ * \brief
+ * 清除比较输出计数值/捕获值缓存
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtCHxXPort TIMxX通道
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ **********************************************************************/
+en_result_t Adt_ClearValueBuf(M0P_ADTIM_TypeDef *ADTx,
+ en_adt_CHxX_port_t enAdtCHxXPort)
+{
+ if (AdtCHxA == enAdtCHxXPort)
+ {
+ ADTx->GCMCR = 0;
+ }
+ else if (AdtCHxB == enAdtCHxXPort)
+ {
+ ADTx->GCMDR = 0;
+ }
+ else
+ {
+ return ErrorInvalidParameter;
+ }
+
+ return Ok;
+}
+
+/***********************************************************************
+ * \brief
+ * 获取捕获值
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtCHxXPort TIMxX通道
+ * \param [in] pu16Capture 捕获值指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ***********************************************************************/
+en_result_t Adt_GetCaptureValue(M0P_ADTIM_TypeDef *ADTx,
+ en_adt_CHxX_port_t enAdtCHxXPort,
+ uint16_t* pu16Capture)
+{
+ if (AdtCHxA == enAdtCHxXPort)
+ {
+ *pu16Capture = ADTx->GCMAR_f.GCMA;
+ }
+ else if (AdtCHxB == enAdtCHxXPort)
+ {
+ *pu16Capture = ADTx->GCMBR_f.GCMB;
+ }
+ else
+ {
+ return ErrorInvalidParameter;
+ }
+ return Ok;
+}
+
+/**********************************************************************
+ * \brief
+ * 获取捕获缓存值
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] enAdtCHxXPort TIMxX通道
+ * \param [in] pu16CaptureBuf 捕获缓存值指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ ***********************************************************************/
+en_result_t Adt_GetCaptureBuf(M0P_ADTIM_TypeDef *ADTx,
+ en_adt_CHxX_port_t enAdtCHxXPort,
+ uint16_t* pu16CaptureBuf)
+{
+ if (AdtCHxA == enAdtCHxXPort)
+ {
+ *pu16CaptureBuf = ADTx->GCMCR_f.GCMC;
+ }
+ else if (AdtCHxB == enAdtCHxXPort)
+ {
+ *pu16CaptureBuf = ADTx->GCMDR_f.GCMD;
+ }
+ else
+ {
+ return ErrorInvalidParameter;
+ }
+ return Ok;
+}
+
+/***********************************************************************
+ * \brief
+ * 设置死区时间上基准值
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] u16Value 死区时间上基准值
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ ************************************************************************/
+en_result_t Adt_SetDTUA(M0P_ADTIM_TypeDef *ADTx,
+ uint16_t u16Value)
+{
+ ADTx->DTUAR = u16Value;
+
+ return Ok;
+}
+
+/***********************************************************************
+ * \brief
+ * 设置死区时间下基准值
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] u16Value 死区时间下基准值
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ ***********************************************************************/
+en_result_t Adt_SetDTDA(M0P_ADTIM_TypeDef *ADTx,
+ uint16_t u16Value)
+{
+ ADTx->DTDAR = u16Value;
+
+ return Ok;
+}
+
+/******************************************************************
+ * \brief
+ * 配置死区时间功能
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] bDTEn 死区功能使能
+ * \param [in] bEqual DTDAR的值和DTUAR的值自动相等
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ *****************************************************************/
+en_result_t Adt_CfgDT(M0P_ADTIM_TypeDef *ADTx,
+ boolean_t bDTEn,
+ boolean_t bEqual)
+{
+ ADTx->DCONR_f.DTCEN = bDTEn;
+ ADTx->DCONR_f.SEPA = bEqual;
+
+ return Ok;
+}
+
+/*************************************************************************
+ * \brief
+ * Z相输入屏蔽设置
+ *
+ * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6)
+ * \param [in] pstcAdtZMaskCfg Z相输入屏蔽功能配置指针
+ *
+ * \retval en_result_t Ok: 配置成功
+ *
+ *************************************************************************/
+en_result_t Adt_CfgZMask(M0P_ADTIM_TypeDef *ADTx, stc_adt_zmask_cfg_t* pstcAdtZMaskCfg)
+{
+ if(NULL == pstcAdtZMaskCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ ADTx->GCONR_f.ZMSK = pstcAdtZMaskCfg->enZMaskCycle;
+ ADTx->GCONR_f.ZMSKPOS = pstcAdtZMaskCfg->bFltPosCntMaksEn;
+ ADTx->GCONR_f.ZMSKREV = pstcAdtZMaskCfg->bFltRevCntMaksEn;
+
+ return Ok;
+}
+
+//@} // AdtGroup
+
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
diff --git a/driver/src/aes.c b/driver/src/aes.c
new file mode 100644
index 0000000..63fb2e7
--- /dev/null
+++ b/driver/src/aes.c
@@ -0,0 +1,206 @@
+/******************************************************************************
+*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file aes.c
+ **
+ ** Common API of AES.
+ ** @link AesGroup Some description @endlink
+ **
+ ** - 2019-04-16
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "aes.h"
+/**
+ *******************************************************************************
+ ** \addtogroup AesGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * \brief
+ * AES 加密
+ *
+ * \param [in] pstcAesCfg AES 配置结构体 @ref stc_aes_cfg_t
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ */
+en_result_t AES_Encrypt(stc_aes_cfg_t* pstcAesCfg)
+{
+ if (NULL == pstcAesCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ M0P_AES->CR_f.KEYSIZE = pstcAesCfg->enKeyLen;
+
+ //Key cfg
+ M0P_AES->KEY0 = pstcAesCfg->pu32Key[0];
+ M0P_AES->KEY1 = pstcAesCfg->pu32Key[1];
+ M0P_AES->KEY2 = pstcAesCfg->pu32Key[2];
+ M0P_AES->KEY3 = pstcAesCfg->pu32Key[3];
+
+ if(AesKey192 == pstcAesCfg->enKeyLen)
+ {
+ M0P_AES->KEY4 = pstcAesCfg->pu32Key[4];
+ M0P_AES->KEY5 = pstcAesCfg->pu32Key[5];
+ }
+
+ if(AesKey256 == pstcAesCfg->enKeyLen)
+ {
+ M0P_AES->KEY4 = pstcAesCfg->pu32Key[4];
+ M0P_AES->KEY5 = pstcAesCfg->pu32Key[5];
+ M0P_AES->KEY6 = pstcAesCfg->pu32Key[6];
+ M0P_AES->KEY7 = pstcAesCfg->pu32Key[7];
+ }
+
+ //Data cfg
+ M0P_AES->DATA0 = pstcAesCfg->pu32Plaintext[0];
+ M0P_AES->DATA1 = pstcAesCfg->pu32Plaintext[1];
+ M0P_AES->DATA2 = pstcAesCfg->pu32Plaintext[2];
+ M0P_AES->DATA3 = pstcAesCfg->pu32Plaintext[3];
+
+ M0P_AES->CR_f.MODE = 0;//Encry
+ M0P_AES->CR_f.START = 1;
+ while(M0P_AES->CR_f.START == 1)
+ {
+ ;
+ }
+ pstcAesCfg->pu32Cipher[0] = M0P_AES->DATA0;
+ pstcAesCfg->pu32Cipher[1] = M0P_AES->DATA1;
+ pstcAesCfg->pu32Cipher[2] = M0P_AES->DATA2;
+ pstcAesCfg->pu32Cipher[3] = M0P_AES->DATA3;
+ return Ok;
+}
+
+
+/**
+ * \brief
+ * AES 解密
+ *
+ * \param [in] pstcAesCfg AES 配置结构体 @ref stc_aes_cfg_t
+ *
+ * \retval en_result_t Ok: 配置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效参数
+ */
+en_result_t AES_Decrypt(stc_aes_cfg_t* pstcAesCfg)
+{
+ if (NULL == pstcAesCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ M0P_AES->CR_f.KEYSIZE = pstcAesCfg->enKeyLen;
+
+ //Key cfg
+ M0P_AES->KEY0 = pstcAesCfg->pu32Key[0];
+ M0P_AES->KEY1 = pstcAesCfg->pu32Key[1];
+ M0P_AES->KEY2 = pstcAesCfg->pu32Key[2];
+ M0P_AES->KEY3 = pstcAesCfg->pu32Key[3];
+
+ if(AesKey192 == pstcAesCfg->enKeyLen)
+ {
+ M0P_AES->KEY4 = pstcAesCfg->pu32Key[4];
+ M0P_AES->KEY5 = pstcAesCfg->pu32Key[5];
+ }
+
+ if(AesKey256 == pstcAesCfg->enKeyLen)
+ {
+ M0P_AES->KEY4 = pstcAesCfg->pu32Key[4];
+ M0P_AES->KEY5 = pstcAesCfg->pu32Key[5];
+ M0P_AES->KEY6 = pstcAesCfg->pu32Key[6];
+ M0P_AES->KEY7 = pstcAesCfg->pu32Key[7];
+ }
+
+ //Data cfg
+ M0P_AES->DATA0 = pstcAesCfg->pu32Cipher[0];
+ M0P_AES->DATA1 = pstcAesCfg->pu32Cipher[1];
+ M0P_AES->DATA2 = pstcAesCfg->pu32Cipher[2];
+ M0P_AES->DATA3 = pstcAesCfg->pu32Cipher[3];
+
+ M0P_AES->CR_f.MODE = 1;//UnEncry
+ M0P_AES->CR_f.START = 1;
+ while(M0P_AES->CR_f.START == 1)
+ {
+ ;
+ }
+ pstcAesCfg->pu32Plaintext[0] = M0P_AES->DATA0;
+ pstcAesCfg->pu32Plaintext[1] = M0P_AES->DATA1;
+ pstcAesCfg->pu32Plaintext[2] = M0P_AES->DATA2;
+ pstcAesCfg->pu32Plaintext[3] = M0P_AES->DATA3;
+ return Ok;
+}
+
+//@} // AesGroup
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/bgr.c b/driver/src/bgr.c
new file mode 100644
index 0000000..c500c87
--- /dev/null
+++ b/driver/src/bgr.c
@@ -0,0 +1,143 @@
+/******************************************************************************
+*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file bgr.c
+ **
+ ** Common API of bgr.
+ ** @link flashGroup Some description @endlink
+ **
+ ** - 2018-05-08
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "bgr.h"
+/**
+ *******************************************************************************
+ ** \addtogroup FlashGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *****************************************************************************
+ ** \brief BGR 使能
+ **
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Bgr_BgrEnable(void)
+{
+ M0P_BGR->CR |= 0x1u;
+
+ delay10us(2);
+}
+
+/**
+ *****************************************************************************
+ ** \brief BGR 禁止
+ **
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Bgr_BgrDisable(void)
+{
+ M0P_BGR->CR &= 0x2u;
+}
+
+/**
+ *****************************************************************************
+ ** \brief BGR 温度传感器使能(需要先开启BGR)
+ **
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Bgr_TempSensorEnable(void)
+{
+ M0P_BGR->CR |= 0x2u;
+
+ delay10us(2);
+}
+
+/**
+ *****************************************************************************
+ ** \brief BGR 温度传感器禁止
+ **
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Bgr_TempSensorDisable(void)
+{
+ M0P_BGR->CR &= 0x1u;
+}
+
+
+//@} // BgrGroup
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/bt.c b/driver/src/bt.c
new file mode 100644
index 0000000..27ecd1d
--- /dev/null
+++ b/driver/src/bt.c
@@ -0,0 +1,1381 @@
+/******************************************************************************
+*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file bt.c
+ **
+ ** Common API of base timer.
+ ** @link btGroup Some description @endlink
+ **
+ ** - 2019-04-15 Husj First Version
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "bt.h"
+/**
+ *******************************************************************************
+ ** \addtogroup BtGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+#define IS_VALID_TIM(x) (TIM0 == (x) ||\
+ TIM1 == (x) ||\
+ TIM2 == (x))
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 中断标志获取(模式0/1/23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] enBtIrq 中断类型
+ **
+ ** \retval TRUE or FALSE
+ *****************************************************************************/
+boolean_t Bt_GetIntFlag(en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq)
+{
+ boolean_t bRetVal = FALSE;
+ uint32_t u32Val;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ u32Val = pstcM0PBt->IFR;
+ bRetVal = (u32Val>>enBtIrq) & 0x1;
+
+ return bRetVal;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 中断标志清除(模式0/1/23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] enBtIrq 中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_ClearIntFlag(en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->ICLR = ~(1u<ICLR = 0;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 中断使能(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_Mode0_EnableIrq(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M0CR_f.UIE = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 中断禁止(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_Mode0_DisableIrq(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M0CR_f.UIE = FALSE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 中断使能(模式1)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] enBtIrq 中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_Mode1_EnableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ switch (enBtIrq)
+ {
+ case BtUevIrq:
+ pstcM0PBt->M1CR_f.UIE = TRUE;
+ break;
+ case BtCA0Irq:
+ pstcM0PBt->CR0_f.CIEA = TRUE;
+ break;
+ default:
+ enResult = Error;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 中断禁止(模式1)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] enBtIrq 中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_Mode1_DisableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+
+ switch (enBtIrq)
+ {
+ case BtUevIrq:
+ pstcM0PBt->M1CR_f.UIE = FALSE;
+ break;
+ case BtCA0Irq:
+ pstcM0PBt->CR0_f.CIEA = FALSE;
+ break;
+ default:
+ enResult = Error;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 中断使能(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] enBtIrq 中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_Mode23_EnableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+
+ switch (enBtIrq)
+ {
+ case BtUevIrq:
+ pstcM0PBt->M23CR_f.UIE = TRUE;
+ break;
+ case BtCA0Irq:
+ pstcM0PBt->CRCH0_f.CIEA = TRUE;
+ break;
+ case BtCB0Irq:
+ pstcM0PBt->CRCH0_f.CIEB = TRUE;
+ break;
+ case BtBkIrq:
+ pstcM0PBt->M23CR_f.BIE = TRUE;
+ break;
+ case BtTrigIrq:
+ pstcM0PBt->M23CR_f.TIE = TRUE;
+ break;
+ default:
+ enResult = Error;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 中断禁止(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] enBtIrq 中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_Mode23_DisableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+
+ switch (enBtIrq)
+ {
+ case BtUevIrq:
+ pstcM0PBt->M23CR_f.UIE = FALSE;
+ break;
+ case BtCA0Irq:
+ pstcM0PBt->CRCH0_f.CIEA = FALSE;
+ break;
+ case BtCB0Irq:
+ pstcM0PBt->CRCH0_f.CIEB = FALSE;
+ break;
+ case BtBkIrq:
+ pstcM0PBt->M23CR_f.BIE = FALSE;
+ break;
+ case BtTrigIrq:
+ pstcM0PBt->M23CR_f.TIE = FALSE;
+ break;
+ default:
+ enResult = Error;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 初始化配置(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_Mode0_Init(en_bt_unit_t enUnit, stc_bt_mode0_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M0CR_f.MODE = pstcCfg->enWorkMode;
+ pstcM0PBt->M0CR_f.GATEP = pstcCfg->enGateP;
+ pstcM0PBt->M0CR_f.GATE = pstcCfg->bEnGate;
+ pstcM0PBt->M0CR_f.PRS = pstcCfg->enPRS;
+ pstcM0PBt->M0CR_f.TOGEN = pstcCfg->bEnTog;
+ pstcM0PBt->M0CR_f.CT = pstcCfg->enCT;
+ pstcM0PBt->M0CR_f.MD = pstcCfg->enCntMode;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 启动运行(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M0_Run(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M0CR_f.CTEN = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 停止运行(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M0_Stop(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M0CR_f.CTEN = FALSE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 翻转输出使能/禁止（低电平）设定(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] bEnTOG 翻转输出设定 TRUE:使能, FALSE:禁止
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M0_EnTOG_Output(en_bt_unit_t enUnit, boolean_t bEnTOG)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M0CR_f.TOGEN = bEnTOG;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 端口输出使能/禁止设定(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] bEnOutput 端口输出设定 TRUE:使能, FALSE:禁止
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M0_Enable_Output(en_bt_unit_t enUnit, boolean_t bEnOutput)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->DTR_f.MOE = bEnOutput;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 16位计数器初值设置(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] u16Data 16位初值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M0_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data)
+{
+ en_result_t enResult = Ok;
+
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->CNT_f.CNT = u16Data;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 16位计数值获取(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval 16bits计数值
+ *****************************************************************************/
+uint16_t Bt_M0_Cnt16Get(en_bt_unit_t enUnit)
+{
+ uint16_t u16CntData = 0;
+
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ u16CntData = pstcM0PBt->CNT_f.CNT;
+
+ return u16CntData;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 重载值设置(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] u16Data 16bits重载值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M0_ARRSet(en_bt_unit_t enUnit, uint16_t u16Data)
+{
+ en_result_t enResult = Ok;
+
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->ARR_f.ARR = u16Data;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 32位计数器初值设置(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] u32Data 32位初值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M0_Cnt32Set(en_bt_unit_t enUnit, uint32_t u32Data)
+{
+ en_result_t enResult = Ok;
+
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->CNT32_f.CNT32 = u32Data;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 32位计数值获取(模式0)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval 32bits计数值
+ *****************************************************************************/
+uint32_t Bt_M0_Cnt32Get(en_bt_unit_t enUnit)
+{
+ uint32_t u32CntData = 0;
+
+ volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ u32CntData = pstcM0PBt->CNT32_f.CNT32;
+
+ return u32CntData;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 初始化配置(模式1)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_Mode1_Init(en_bt_unit_t enUnit, stc_bt_mode1_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M1CR_f.MODE = pstcCfg->enWorkMode;
+ pstcM0PBt->M1CR_f.PRS = pstcCfg->enPRS;
+ pstcM0PBt->M1CR_f.CT = pstcCfg->enCT;
+ pstcM0PBt->M1CR_f.ONESHOT = pstcCfg->enOneShot;
+
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer PWC 输入配置(模式1)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M1_Input_Cfg(en_bt_unit_t enUnit, stc_bt_pwc_input_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->MSCR_f.TS = pstcCfg->enTsSel;
+ pstcM0PBt->MSCR_f.IA0S = pstcCfg->enIA0Sel;
+ pstcM0PBt->MSCR_f.IB0S = pstcCfg->enIB0Sel;
+ pstcM0PBt->FLTR_f.ETP = pstcCfg->enETRPhase;
+ pstcM0PBt->FLTR_f.FLTET = pstcCfg->enFltETR;
+ pstcM0PBt->FLTR_f.FLTA0 = pstcCfg->enFltIA0;
+ pstcM0PBt->FLTR_f.FLTB0 = pstcCfg->enFltIB0;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer PWC测量边沿起始结束选择(模式1)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] enEdgeSel pwc测量起始终止电平
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M1_PWC_Edge_Sel(en_bt_unit_t enUnit,en_bt_m1cr_Edge_t enEdgeSel)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ switch (enEdgeSel)
+ {
+ case 0: ///< 上升沿到上升沿(周期)
+ pstcM0PBt->M1CR_f.EDG1ST = 0; //上升沿
+ pstcM0PBt->M1CR_f.EDG2ND = 0; //上升沿
+ break;
+ case 1: ///< 下降沿到上升沿(低电平)
+ pstcM0PBt->M1CR_f.EDG1ST = 1; //下降沿
+ pstcM0PBt->M1CR_f.EDG2ND = 0; //上升沿
+ break;
+ case 2: ///< 上升沿到下降沿(高电平)
+ pstcM0PBt->M1CR_f.EDG1ST = 0; //上升沿
+ pstcM0PBt->M1CR_f.EDG2ND = 1; //下降沿
+ break;
+ case 3: ///< 下降沿到下降沿(周期)
+ pstcM0PBt->M1CR_f.EDG1ST = 1; //下降沿
+ pstcM0PBt->M1CR_f.EDG2ND = 1; //下降沿
+ break;
+ default:
+ ;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 启动运行(模式1)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M1_Run(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M1CR_f.CTEN = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 停止运行(模式1)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M1_Stop(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M1CR_f.CTEN = FALSE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 16位计数器初值设置(模式1)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] u16Data 16位初值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M1_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data)
+{
+ en_result_t enResult = Ok;
+
+ volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->CNT_f.CNT = u16Data;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 16位计数值获取(模式1)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval 16bits计数值
+ *****************************************************************************/
+uint16_t Bt_M1_Cnt16Get(en_bt_unit_t enUnit)
+{
+ uint16_t u16CntData = 0;
+
+ volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ u16CntData = pstcM0PBt->CNT_f.CNT;
+
+ return u16CntData;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 脉冲宽度测量结果数值获取(模式1)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval 16bits脉冲宽度测量结果
+ *****************************************************************************/
+uint16_t Bt_M1_PWC_CapValueGet(en_bt_unit_t enUnit)
+{
+ uint16_t u16CapData = 0;
+
+ volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ u16CapData = pstcM0PBt->CCR0A_f.CCR0A;
+
+ return u16CapData;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 初始化配置(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_Mode23_Init(en_bt_unit_t enUnit, stc_bt_mode23_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M23CR_f.MODE = pstcCfg->enWorkMode;
+
+ pstcM0PBt->M23CR_f.PRS = pstcCfg->enPRS;
+ pstcM0PBt->M23CR_f.CT = pstcCfg->enCT;
+ pstcM0PBt->M23CR_f.COMP = pstcCfg->enPWMTypeSel;
+ pstcM0PBt->M23CR_f.PWM2S = pstcCfg->enPWM2sSel;
+ pstcM0PBt->M23CR_f.ONESHOT = pstcCfg->bOneShot;
+ pstcM0PBt->M23CR_f.URS = pstcCfg->bURSSel;
+ pstcM0PBt->M23CR_f.DIR = pstcCfg->enCntDir;
+
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer PWM输出使能/禁止(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] bEnOutput PWM输出使能/禁止设定
+ ** \param [in] bEnAutoOutput PWM自动输出使能/禁止设定
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_EnPWM_Output(en_bt_unit_t enUnit, boolean_t bEnOutput, boolean_t bEnAutoOutput)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->DTR_f.MOE = bEnOutput;
+ pstcM0PBt->DTR_f.AOE = bEnAutoOutput;
+
+ return enResult;
+}
+
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 启动运行(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_Run(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M23CR_f.CTEN = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 停止运行(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_Stop(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M23CR_f.CTEN = FALSE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 重载值设置(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] u16Data 16bits重载值
+ ** \param [in] bArrBufEn ARR重载缓存使能TRUE/禁止FALSE
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_ARRSet(en_bt_unit_t enUnit, uint16_t u16Data, boolean_t bArrBufEn)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->ARR_f.ARR = u16Data;
+ pstcM0PBt->M23CR_f.BUFPEN = bArrBufEn;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 16位计数器初值设置(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] u16Data 16位初值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->CNT_f.CNT = u16Data;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 16位计数值获取(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval 16bits计数值
+ *****************************************************************************/
+uint16_t Bt_M23_Cnt16Get(en_bt_unit_t enUnit)
+{
+ uint16_t u16CntData = 0;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ u16CntData = pstcM0PBt->CNT_f.CNT;
+
+ return u16CntData;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 比较捕获寄存器CCR0A/CCR0B设置(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] enCCRSel CCR0A/CCR0B设定
+ ** \param [in] u16Data CCR0A/CCR0B 16位初始值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_CCR_Set(en_bt_unit_t enUnit, en_bt_m23_ccrx_t enCCRSel, uint16_t u16Data)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ if(BtCCR0A == enCCRSel)
+ {
+ pstcM0PBt->CCR0A_f.CCR0A = u16Data;
+ }
+ else if(BtCCR0B == enCCRSel)
+ {
+ pstcM0PBt->CCR0B_f.CCR0B = u16Data;
+ }
+ else
+ {
+ enResult = Error;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 比较捕获寄存器CCR0A/CCR0B读取(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] enCCRSel CCR0A/CCR0B设定
+ **
+ ** \retval 16bitsCCR0A捕获值
+ *****************************************************************************/
+uint16_t Bt_M23_CCR_Get(en_bt_unit_t enUnit, en_bt_m23_ccrx_t enCCRSel)
+{
+ uint16_t u16Data = 0;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ if(BtCCR0A == enCCRSel)
+ {
+ u16Data = pstcM0PBt->CCR0A_f.CCR0A;
+ }
+ else if(BtCCR0B == enCCRSel)
+ {
+ u16Data = pstcM0PBt->CCR0B_f.CCR0B;
+ }
+ else
+ {
+ u16Data = 0;
+ }
+
+ return u16Data;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer PWM互补输出模式下，GATE功能选择(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_GateFuncSel(en_bt_unit_t enUnit,stc_bt_m23_gate_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M23CR_f.CSG = pstcCfg->enGateFuncSel;
+ pstcM0PBt->M23CR_f.CRG = pstcCfg->bGateRiseCap;
+ pstcM0PBt->M23CR_f.CFG = pstcCfg->bGateFallCap;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 主从模式配置(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_MasterSlave_Set(en_bt_unit_t enUnit, stc_bt_m23_master_slave_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->MSCR_f.MSM = pstcCfg->enMasterSlaveSel;
+ pstcM0PBt->MSCR_f.MMS = pstcCfg->enMasterSrc;
+ pstcM0PBt->MSCR_f.SMS = pstcCfg->enSlaveModeSel;
+ pstcM0PBt->MSCR_f.TS = pstcCfg->enTsSel;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer CH0A/CH0B比较通道输出控制(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_PortOutput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_compare_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->CRCH0_f.CSA = 0;
+ pstcM0PBt->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCH0ACmpCtrl;
+ pstcM0PBt->FLTR_f.CCPA0 = pstcCfg->enCH0APolarity;
+ pstcM0PBt->CRCH0_f.BUFEA = pstcCfg->bCh0ACmpBufEn;
+ pstcM0PBt->M23CR_f.CIS = pstcCfg->enCh0ACmpIntSel;
+
+ pstcM0PBt->CRCH0_f.CSB = 0;
+ pstcM0PBt->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCH0BCmpCtrl;
+ pstcM0PBt->FLTR_f.CCPB0 = pstcCfg->enCH0BPolarity;
+ pstcM0PBt->CRCH0_f.BUFEB = pstcCfg->bCH0BCmpBufEn;
+ pstcM0PBt->CRCH0_f.CISB = pstcCfg->enCH0BCmpIntSel;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer CH0A/CH0B输入控制(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_PortInput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_input_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->CRCH0_f.CSA = 1;
+ pstcM0PBt->CRCH0_f.CFA_CRA_BKSA = pstcCfg->enCH0ACapSel;
+ pstcM0PBt->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCH0AInFlt;
+ pstcM0PBt->FLTR_f.CCPA0 = pstcCfg->enCH0APolarity;
+
+ pstcM0PBt->CRCH0_f.CSB = 1;
+ pstcM0PBt->CRCH0_f.CFB_CRB_BKSB = pstcCfg->enCH0BCapSel;
+ pstcM0PBt->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCH0BInFlt;
+ pstcM0PBt->FLTR_f.CCPB0 = pstcCfg->enCH0BPolarity;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer ERT输入控制(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_ETRInput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_etr_input_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->FLTR_f.ETP = pstcCfg->enETRPolarity;
+ pstcM0PBt->FLTR_f.FLTET = pstcCfg->enETRFlt;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 刹车BK输入控制(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_BrakeInput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_bk_input_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->DTR_f.BKE = pstcCfg->bEnBrake;
+ pstcM0PBt->DTR_f.VCE = pstcCfg->bEnVCBrake;
+ pstcM0PBt->DTR_f.SAFEEN = pstcCfg->bEnSafetyBk;
+ pstcM0PBt->DTR_f.BKSEL = pstcCfg->bEnBKSync;
+ pstcM0PBt->CRCH0_f.CFA_CRA_BKSA = pstcCfg->enBkCH0AStat;
+ pstcM0PBt->CRCH0_f.CFB_CRB_BKSB = pstcCfg->enBkCH0BStat;
+ pstcM0PBt->FLTR_f.BKP = pstcCfg->enBrakePolarity;
+ pstcM0PBt->FLTR_f.FLTBK = pstcCfg->enBrakeFlt;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 触发ADC控制(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_TrigADC_Cfg(en_bt_unit_t enUnit, stc_bt_m23_adc_trig_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->ADTR_f.ADTE = pstcCfg->bEnTrigADC;
+ pstcM0PBt->ADTR_f.UEVE = pstcCfg->bEnUevTrigADC;
+ pstcM0PBt->ADTR_f.CMA0E = pstcCfg->bEnCH0ACmpTrigADC;
+ pstcM0PBt->ADTR_f.CMB0E = pstcCfg->bEnCH0BCmpTrigADC;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+** \brief Base Timer 死区功能(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_DT_Cfg(en_bt_unit_t enUnit, stc_bt_m23_dt_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->DTR_f.DTEN = pstcCfg->bEnDeadTime;
+ pstcM0PBt->DTR_f.DTR = pstcCfg->u8DeadTimeValue;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+** \brief Base Timer 重复周期设置(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] u8ValidPeriod 重复周期值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_SetValidPeriod(en_bt_unit_t enUnit, uint8_t u8ValidPeriod)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->RCR_f.RCR = u8ValidPeriod;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer OCREF清除功能(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_OCRefClr(en_bt_unit_t enUnit, stc_bt_m23_OCREF_Clr_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M23CR_f.OCCS = pstcCfg->enOCRefClrSrcSel;
+ pstcM0PBt->M23CR_f.OCCE = pstcCfg->bVCClrEn;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 使能DMA传输(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_EnDMA(en_bt_unit_t enUnit, stc_bt_m23_trig_dma_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M23CR_f.UDE = pstcCfg->bUevTrigDMA;
+ pstcM0PBt->M23CR_f.TDE = pstcCfg->bTITrigDMA;
+ pstcM0PBt->CRCH0_f.CDEA = pstcCfg->bCmpATrigDMA;
+ pstcM0PBt->CRCH0_f.CDEB = pstcCfg->bCmpBTrigDMA;
+ pstcM0PBt->MSCR_f.CCDS = pstcCfg->enCmpUevTrigDMA;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 捕获比较A软件触发(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_EnSwTrigCapCmpA(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->CRCH0_f.CCGA = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 捕获比较B软件触发(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_EnSwTrigCapCmpB(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->CRCH0_f.CCGB = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 软件更新使能(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_EnSwUev(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M23CR_f.UG = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 软件触发使能(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_EnSwTrig(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M23CR_f.TG = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer 软件刹车使能(模式23)
+ **
+ **
+ ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Bt_M23_EnSwBk(en_bt_unit_t enUnit)
+{
+ en_result_t enResult = Ok;
+ volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit);
+ ASSERT(IS_VALID_TIM(enUnit));
+
+ pstcM0PBt->M23CR_f.BG = TRUE;
+
+ return enResult;
+}
+
+//@} // BtGroup
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/crc.c b/driver/src/crc.c
new file mode 100644
index 0000000..aab257f
--- /dev/null
+++ b/driver/src/crc.c
@@ -0,0 +1,438 @@
+/******************************************************************************
+*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file crc.c
+ **
+ ** Common API of crc.
+ ** @link crcGroup Some description @endlink
+ **
+ ** - 2017-05-16
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "crc.h"
+/**
+ *******************************************************************************
+ ** \addtogroup CrcGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 编码(字节填充方式)
+ **
+ ** 该函数主要用于生成CRC16编码.
+ **
+ ** \param [in] pu8Data 待编码数据指针（字节方式输入）
+ ** \param [in] u32Len 待编码数据长度（字节数）
+ **
+ ** \retval CRC16 CRC16编码值.
+ *****************************************************************************/
+uint16_t CRC16_Get8(uint8_t* pu8Data, uint32_t u32Len)
+{
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 0;
+ M0P_CRC->RESULT = 0xFFFF;
+ for(u32Index = 0;u32IndexDATA))) = pu8Data[u32Index];
+ }
+
+ return (M0P_CRC->RESULT_f.RESULT);
+}
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 编码(半字填充方式)
+ **
+ ** 该函数主要用于生成CRC16编码.
+ **
+ ** \param [in] pu16Data 待编码数据指针（半字方式输入）
+ ** \param [in] u32Len 待编码数据长度（半字数）
+ **
+ ** \retval CRC16 CRC16编码值.
+ *****************************************************************************/
+uint16_t CRC16_Get16(uint16_t* pu16Data, uint32_t u32Len)
+{
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 0;
+ M0P_CRC->RESULT_f.RESULT = 0xFFFF;
+ for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index];
+ }
+
+ return (M0P_CRC->RESULT_f.RESULT);
+}
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 编码(字填充方式)
+ **
+ ** 该函数主要用于生成CRC16编码.
+ **
+ ** \param [in] pu32Data 待编码数据指针（字方式输入）
+ ** \param [in] u32Len 待编码数据长度（字数）
+ **
+ ** \retval CRC16 CRC16编码值.
+ *****************************************************************************/
+uint16_t CRC16_Get32(uint32_t* pu32Data, uint32_t u32Len)
+{
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 0;
+ M0P_CRC->RESULT_f.RESULT = 0xFFFF;
+ for (u32Index=0; u32IndexDATA_f.DATA = pu32Data[u32Index];
+ }
+
+ return (M0P_CRC->RESULT_f.RESULT);
+}
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 校验(字节填充方式)
+ **
+ ** 该函数主要用于对数据及CRC16值进行校验.
+ **
+ ** \param [in] pu8Data 待校验数据指针（字节方式输入）
+ ** \param [in] u32Len 待校验数据长度（字节数）
+ ** \param [in] u16CRC 待校验CRC16值
+ **
+ ** \retval Ok CRC校验正确
+ ** \retval Error CRC校验错误
+ *****************************************************************************/
+en_result_t CRC16_Check8(uint8_t* pu8Data, uint32_t u32Len, uint16_t u16CRC)
+{
+ en_result_t enResult = Ok;
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 0;
+ M0P_CRC->RESULT_f.RESULT = 0xFFFF;
+ for (u32Index=0; u32IndexDATA))) = pu8Data[u32Index];
+ }
+
+ *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((((uint32_t)u16CRC)>>0)&0xFF);
+ *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)(((uint32_t)u16CRC>>8)&0xFF);
+
+ enResult = M0P_CRC->CR_f.FLAG ? Ok : Error;
+
+ return (enResult);
+}
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 校验(半字填充方式)
+ **
+ ** 该函数主要用于对数据及CRC16值进行校验.
+ **
+ ** \param [in] pu16Data 待校验数据指针（半字方式输入）
+ ** \param [in] u32Len 待校验数据长度（半字数）
+ ** \param [in] u16CRC 待校验CRC16值
+ **
+ ** \retval Ok CRC校验正确
+ ** \retval Error CRC校验错误
+ *****************************************************************************/
+en_result_t CRC16_Check16(uint16_t* pu16Data, uint32_t u32Len, uint16_t u16CRC)
+{
+ en_result_t enResult = Ok;
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 0;
+ M0P_CRC->RESULT_f.RESULT = 0xFFFF;
+ for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index];
+ }
+
+ *((volatile uint16_t*)(&(M0P_CRC->DATA))) = u16CRC;
+
+ enResult = M0P_CRC->CR_f.FLAG ? Ok : Error;
+
+ return (enResult);
+}
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 校验(字填充方式)
+ **
+ ** 该函数主要用于对数据及CRC16值进行校验.
+ **
+ ** \param [in] pu32Data 待校验数据指针（字方式输入）
+ ** \param [in] u32Len 待校验数据长度（字数）
+ ** \param [in] u16CRC 待校验CRC16值
+ **
+ ** \retval Ok CRC校验正确
+ ** \retval Error CRC校验错误
+ *****************************************************************************/
+en_result_t CRC16_Check32(uint32_t* pu32Data, uint32_t u32Len, uint16_t u16CRC)
+{
+ en_result_t enResult = Ok;
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 0;
+ M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu;
+ for (u32Index=0; u32IndexDATA))) = pu32Data[u32Index];
+ }
+
+ *((volatile uint16_t*)(&(M0P_CRC->DATA))) = ((uint16_t)u16CRC);
+
+ enResult = M0P_CRC->CR_f.FLAG ? Ok : Error;
+
+ return (enResult);
+}
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 编码(字节填充方式)
+ **
+ ** 该函数主要用于生成CRC16编码.
+ **
+ ** \param [in] pu8Data 待编码数据指针（字节方式输入）
+ ** \param [in] u32Len 待编码数据长度（字节数）
+ **
+ ** \retval CRC16 CRC16编码值.
+ *****************************************************************************/
+uint32_t CRC32_Get8(uint8_t* pu8Data, uint32_t u32Len)
+{
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 1;
+ M0P_CRC->RESULT = 0xFFFFFFFFu;
+ for(u32Index = 0;u32IndexDATA))) = pu8Data[u32Index];
+ }
+
+ return (M0P_CRC->RESULT_f.RESULT);
+}
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 编码(半字填充方式)
+ **
+ ** 该函数主要用于生成CRC16编码.
+ **
+ ** \param [in] pu16Data 待编码数据指针（半字方式输入）
+ ** \param [in] u32Len 待编码数据长度（半字数）
+ **
+ ** \retval CRC16 CRC16编码值.
+ *****************************************************************************/
+uint32_t CRC32_Get16(uint16_t* pu16Data, uint32_t u32Len)
+{
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 1;
+ M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu;
+ for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index];
+ }
+
+ return (M0P_CRC->RESULT_f.RESULT);
+}
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 编码(字填充方式)
+ **
+ ** 该函数主要用于生成CRC16编码.
+ **
+ ** \param [in] pu32Data 待编码数据指针（字方式输入）
+ ** \param [in] u32Len 待编码数据长度（字数）
+ **
+ ** \retval CRC16 CRC16编码值.
+ *****************************************************************************/
+uint32_t CRC32_Get32(uint32_t* pu32Data, uint32_t u32Len)
+{
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 1;
+ M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu;
+ for (u32Index=0; u32IndexDATA_f.DATA = pu32Data[u32Index];
+ }
+
+ return (M0P_CRC->RESULT_f.RESULT);
+}
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 校验(字节填充方式)
+ **
+ ** 该函数主要用于对数据及CRC16值进行校验.
+ **
+ ** \param [in] pu8Data 待校验数据指针（字节方式输入）
+ ** \param [in] u32Len 待校验数据长度（字节数）
+ ** \param [in] u16CRC 待校验CRC16值
+ **
+ ** \retval Ok CRC校验正确
+ ** \retval Error CRC校验错误
+ *****************************************************************************/
+en_result_t CRC32_Check8(uint8_t* pu8Data, uint32_t u32Len, uint32_t u32CRC)
+{
+ en_result_t enResult = Ok;
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 1;
+ M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu;
+ for (u32Index=0; u32IndexDATA))) = pu8Data[u32Index];
+ }
+
+ *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>0)&0xFF);
+ *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>8)&0xFF);
+ *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>16)&0xFF);
+ *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>24)&0xFF);
+
+ enResult = M0P_CRC->CR_f.FLAG ? Ok : Error;
+
+ return (enResult);
+}
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 校验(半字填充方式)
+ **
+ ** 该函数主要用于对数据及CRC16值进行校验.
+ **
+ ** \param [in] pu16Data 待校验数据指针（半字方式输入）
+ ** \param [in] u32Len 待校验数据长度（半字数）
+ ** \param [in] u16CRC 待校验CRC16值
+ **
+ ** \retval Ok CRC校验正确
+ ** \retval Error CRC校验错误
+ *****************************************************************************/
+en_result_t CRC32_Check16(uint16_t* pu16Data, uint32_t u32Len, uint32_t u32CRC)
+{
+ en_result_t enResult = Ok;
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 1;
+ M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu;
+ for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index];
+ }
+
+ *((volatile uint16_t*)(&(M0P_CRC->DATA))) = (uint16_t)((u32CRC>>0)&0xFFFF);
+ *((volatile uint16_t*)(&(M0P_CRC->DATA))) = (uint16_t)((u32CRC>>16)&0xFFFF);
+
+
+ enResult = M0P_CRC->CR_f.FLAG ? Ok : Error;
+
+ return (enResult);
+}
+
+/**
+ *****************************************************************************
+ ** \brief CRC16 校验(字填充方式)
+ **
+ ** 该函数主要用于对数据及CRC16值进行校验.
+ **
+ ** \param [in] pu32Data 待校验数据指针（字方式输入）
+ ** \param [in] u32Len 待校验数据长度（字数）
+ ** \param [in] u16CRC 待校验CRC16值
+ **
+ ** \retval Ok CRC校验正确
+ ** \retval Error CRC校验错误
+ *****************************************************************************/
+en_result_t CRC32_Check32(uint32_t* pu32Data, uint32_t u32Len, uint32_t u32CRC)
+{
+ en_result_t enResult = Ok;
+ uint32_t u32Index = 0;
+
+ M0P_CRC->CR_f.CR = 1;
+ M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu;
+ for (u32Index=0; u32IndexDATA))) = pu32Data[u32Index];
+ }
+
+ *((volatile uint32_t*)(&(M0P_CRC->DATA))) = u32CRC;
+
+ enResult = M0P_CRC->CR_f.FLAG ? Ok : Error;
+
+ return (enResult);
+}
+//@} // CrcGroup
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/dac.c b/driver/src/dac.c
new file mode 100644
index 0000000..9fb01fa
--- /dev/null
+++ b/driver/src/dac.c
@@ -0,0 +1,253 @@
+/******************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file dac.c
+ **
+ ** dac driver API.
+ **
+ ** - 2019-04-10 First Version
+ **
+ ******************************************************************************/
+
+/******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "dac.h"
+
+/**
+ ******************************************************************************
+ ** \addtogroup AdcGroup
+ ******************************************************************************/
+//@{
+
+/******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*****************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ *****************************************************************************/
+
+/**
+******************************************************************************
+ ** \brief 使能相关通道的DMA DMA_CR0中的DMAEN0
+ **
+ ** @param NewState : TRUE 或者 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Dac_DmaCmd(boolean_t NewState)
+{
+ SetBit((uint32_t)(&(M0P_DAC->CR0)), 12, NewState);
+}
+
+/**
+******************************************************************************
+ ** \brief 配置DAC的DMA下溢中断， DMA_CR0中的DMAUDRIE0
+ **
+ ** @param NewState : TRUE 或者 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Dac_DmaITCfg(boolean_t NewState)
+{
+ SetBit((uint32_t)(&(M0P_DAC->CR0)), 13, NewState);
+}
+
+/**
+******************************************************************************
+ ** \brief 获取DAC的DMA下溢中断标志位状态， DMA_SR中的DMAUDR0
+ **
+ ** @param 无
+ ** \retval TRUE 或 FALSE
+ **
+******************************************************************************/
+boolean_t Dac_GetITStatus(void)
+{
+ return GetBit((uint32_t)(&(M0P_DAC->SR)), 13);
+}
+
+/**
+******************************************************************************
+ ** \brief 配置DAC的使能与禁止， DMA_CR0中的EN0
+ **
+ ** @param NewState : TRUE 或者 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Dac_Cmd(boolean_t NewState)
+{
+ SetBit((uint32_t)(&(M0P_DAC->CR0)), 0, NewState);
+}
+
+/**
+******************************************************************************
+ ** \brief 软件触发寄存器，触发DAC转换 DMA_SWTRIGR中的SWTRIG0
+ **
+ ** @param 无
+ ** \retval 无
+ **
+******************************************************************************/
+void Dac_SoftwareTriggerCmd(void)
+{
+ SetBit((uint32_t)(&(M0P_DAC->SWTRIGR)), 0, 1);
+}
+
+/**
+******************************************************************************
+** \brief 初始化DAC0
+ **
+ ** @param DAC_InitStruct : 用于初始化DAC0的结构体
+ ** \retval 无
+ **
+******************************************************************************/
+void Dac_Init(stc_dac_cfg_t* DAC_InitStruct)
+{
+ M0P_DAC->CR0_f.BOFF0 = DAC_InitStruct->boff_t;
+ M0P_DAC->CR0_f.TEN0 = DAC_InitStruct->ten_t;
+ M0P_DAC->CR0_f.TSEL0 = DAC_InitStruct->tsel_t;
+ M0P_DAC->CR0_f.WAVE0 = DAC_InitStruct->wave_t;
+ M0P_DAC->CR0_f.MAMP0 = DAC_InitStruct->mamp_t;
+ M0P_DAC->CR0_f.SREF0 = DAC_InitStruct->sref_t;
+
+ if(DAC_InitStruct->align == DacLeftAlign)
+ {
+ M0P_DAC->DHR12L0_f.DHR0 = DAC_InitStruct->dhr12;
+ }
+ else if(DAC_InitStruct->align == DacRightAlign)
+ {
+ M0P_DAC->DHR12R0_f.DHR0 = DAC_InitStruct->dhr12;
+ }
+ else
+ {
+ M0P_DAC->DHR8R0_f.DHR0 = DAC_InitStruct->dhr8;
+ }
+}
+
+/**
+******************************************************************************
+** \brief 向DAC0的数据保持寄存器写数据
+ **
+ ** @param DAC_Channel: Dac_0
+ ** @param DAC_Align : Right_Align 与Left_Align
+ ** @param DAC_Bit : Bit8 与Bit12
+ ** @param Data : 所要发送的数据
+ ** \retval 无
+ **
+******************************************************************************/
+void Dac_SetChannelData(en_align_t DAC_Align, en_bitno_t DAC_Bit, uint16_t Data)
+{
+ if(DAC_Align == DacRightAlign)
+ {
+ if(DAC_Bit == DacBit8)
+ {
+ M0P_DAC->DHR8R0_f.DHR0 = (uint8_t)Data;
+ }
+ else if(DAC_Bit == DacBit12)
+ {
+ M0P_DAC->DHR12R0_f.DHR0 = Data;
+ }
+ else
+ {
+ return;
+ }
+ }
+ else if(DAC_Align == DacLeftAlign)
+ {
+ if(DAC_Bit == DacBit8)
+ {
+ return;
+ }
+ else if(DAC_Bit == DacBit12)
+ {
+ M0P_DAC->DHR12L0_f.DHR0 = Data;
+ }
+ else
+ {
+ return;
+ }
+ }
+ else
+ {
+ return;
+ }
+}
+
+
+
+/**
+******************************************************************************
+ ** \brief 获取DAC数据输出寄存器DAC_DOR0
+ **
+ ** @param 无
+ ** \retval DAC_DOR0的值
+ **
+******************************************************************************/
+uint16_t Dac_GetDataOutputValue(void)
+{
+ uint16_t tmp;
+
+ tmp = M0P_DAC->DOR0_f.DOR0;
+ return tmp&0x0fff;
+}
+
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
+
diff --git a/driver/src/ddl.c b/driver/src/ddl.c
new file mode 100644
index 0000000..f2457e4
--- /dev/null
+++ b/driver/src/ddl.c
@@ -0,0 +1,250 @@
+/*******************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file ddl.c
+ **
+ ** Common API of DDL.
+ ** @link ddlGroup Some description @endlink
+ **
+ ** - 2019-03-03
+ **
+ ******************************************************************************/
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "ddl.h"
+
+/**
+ ******************************************************************************
+ ** \addtogroup DDL Common Functions
+ ******************************************************************************/
+//@{
+
+/******************************************************************************/
+/* Local pre-processor symbols/macros ('#define') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Global variable definitions (declared in header file with 'extern') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Local type definitions ('typedef') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Local variable definitions ('static') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Local function prototypes ('static') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Function implementation - global ('extern') and local ('static') */
+/******************************************************************************/
+#ifndef __DEBUG
+#define __DEBUG
+//#define __CC_ARM
+#endif
+
+uint32_t Log2(uint32_t u32Val)
+{
+ uint32_t u32V1 = 0;
+
+ if(0u == u32Val)
+ {
+ return 0;
+ }
+
+ while(u32Val > 1u)
+ {
+ u32V1++;
+ u32Val /=2;
+ }
+
+ return u32V1;
+}
+
+
+/**
+ *******************************************************************************
+ ** \brief Memory clear function for DDL_ZERO_STRUCT()
+ ******************************************************************************/
+void ddl_memclr(void *pu8Address, uint32_t u32Count)
+{
+ uint8_t *pu8Addr = (uint8_t *)pu8Address;
+
+ if(NULL == pu8Addr)
+ {
+ return;
+ }
+
+ while (u32Count--)
+ {
+ *pu8Addr++ = 0;
+ }
+}
+
+/**
+ * \brief delay1ms
+ * delay approximately 1ms.
+ * \param [in] u32Cnt
+ * \retval void
+ */
+void delay1ms(uint32_t u32Cnt)
+{
+ uint32_t u32end;
+
+ SysTick->LOAD = 0xFFFFFF;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk;
+
+ while(u32Cnt-- > 0)
+ {
+ SysTick->VAL = 0;
+ u32end = 0x1000000 - SystemCoreClock/1000;
+ while(SysTick->VAL > u32end)
+ {
+ ;
+ }
+ }
+
+ SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk));
+}
+
+/**
+ * \brief delay100us
+ * delay approximately 100us.
+ * \param [in] u32Cnt
+ * \retval void
+ */
+void delay100us(uint32_t u32Cnt)
+{
+ uint32_t u32end;
+
+ SysTick->LOAD = 0xFFFFFF;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk;
+
+ while(u32Cnt-- > 0)
+ {
+ SysTick->VAL = 0;
+
+ u32end = 0x1000000 - SystemCoreClock/10000;
+ while(SysTick->VAL > u32end)
+ {
+ ;
+ }
+ }
+
+ SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk));
+}
+
+/**
+ * \brief delay10us
+ * delay approximately 10us.
+ * \param [in] u32Cnt
+ * \retval void
+ */
+void delay10us(uint32_t u32Cnt)
+{
+ uint32_t u32end;
+
+ SysTick->LOAD = 0xFFFFFF;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk;
+
+ while(u32Cnt-- > 0)
+ {
+ SysTick->VAL = 0;
+
+ u32end = 0x1000000 - SystemCoreClock/100000;
+ while(SysTick->VAL > u32end)
+ {
+ ;
+ }
+ }
+
+ SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk));
+}
+
+/**
+ * \brief set register bit
+ *
+ * \param [in] addr
+ * \param [in] offset
+ * \retval void
+ */
+void SetBit(uint32_t addr, uint32_t offset, boolean_t bFlag)
+{
+ if(TRUE == bFlag)
+ {
+ *((volatile uint32_t *)(addr)) |= ((1UL)<<(offset));
+ }
+ else
+ {
+ *((volatile uint32_t *)(addr)) &= (~(1UL<<(offset)));
+ }
+
+
+}
+
+
+/**
+ * \brief get register bit
+ *
+ * \param [in] addr
+ * \param [in] offset
+ * \retval void
+ */
+boolean_t GetBit(uint32_t addr, uint32_t offset)
+{
+ return ((((*((volatile uint32_t *)(addr))) >> (offset)) & 1u) > 0) ? TRUE : FALSE;
+}
+//@} // DDL Functions
+
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
diff --git a/driver/src/debug.c b/driver/src/debug.c
new file mode 100644
index 0000000..c7fb0fc
--- /dev/null
+++ b/driver/src/debug.c
@@ -0,0 +1,119 @@
+/******************************************************************************
+*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file debug.c
+ **
+ ** Common API of debug.
+ ** @link flashGroup Some description @endlink
+ **
+ ** - 2018-05-08
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "debug.h"
+/**
+ *******************************************************************************
+ ** \addtogroup FlashGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *****************************************************************************
+ ** \brief 调试模式下模块功能计数使能
+ **
+ **
+ ** \retval TRUE or FALSE
+ *****************************************************************************/
+en_result_t Debug_ActiveEnable(en_debug_module_active_t enModule)
+{
+ M0P_DEBUG_ACTIVE->DEBUG_ACTIVE &= ~(uint32_t)enModule;
+
+ return Ok;
+}
+
+/**
+ *****************************************************************************
+ ** \brief 调试模式下模块功能计数暂停
+ **
+ **
+ ** \retval TRUE or FALSE
+ *****************************************************************************/
+en_result_t Debug_ActiveDisable(en_debug_module_active_t enModule)
+{
+ M0P_DEBUG_ACTIVE->DEBUG_ACTIVE |= (uint32_t)enModule;
+
+ return Ok;
+}
+
+
+//@} // BgrGroup
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/dmac.c b/driver/src/dmac.c
new file mode 100644
index 0000000..7bb6234
--- /dev/null
+++ b/driver/src/dmac.c
@@ -0,0 +1,624 @@
+/******************************************************************************
+* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file dmac.c
+**
+** A detailed description is available at
+** @link DmacGroup Dmac description @endlink
+**
+** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac.
+**
+******************************************************************************/
+
+/*******************************************************************************
+* Include files
+******************************************************************************/
+#include "dmac.h"
+
+/**
+*******************************************************************************
+** \addtogroup DmacGroup
+******************************************************************************/
+//@{
+
+/*******************************************************************************
+* Local type definitions ('typedef')
+******************************************************************************/
+
+/*******************************************************************************
+* Local pre-processor symbols/macros ('#define')
+******************************************************************************/
+
+/******************************************************************************/
+/* DMA */
+/******************************************************************************/
+
+/************** Bits definition for DMA_CONFBx(x=0~1) register *************/
+#define DMA_TRANSFER_WIDTH_Pos (26U) /*!< DMAC_CONFBx: ERR_IE Position */
+#define DMA_TRANSFER_WIDTH_Msk (0x03U << DMA_TRANSFER_WIDTH_Pos) /*!< DMAC_CONFBx: ERR_IE Mask 0x0C000000 */
+
+/************** Bits definition for DMA_CONFBx(x=0~1) register *************/
+#define DMA_ERR_IE_Pos (20U) /*!< DMAC_CONFBx: ERR_IE Position */
+#define DMA_ERR_IE_Msk (0x01U << DMA_ERR_IE_Pos) /*!< DMAC_CONFBx: ERR_IE Mask 0x00000010 */
+
+/************** Bits definition for DMA_CONFBx(x=0~1) register *************/
+#define DMA_FIS_IE_Pos (19U) /*!< DMAC_CONFBx: FIS_IE Position */
+#define DMA_FIS_IE_Msk (0x01U << DMA_FIS_IE_Pos) /*!< DMAC_CONFBx: FIS_IE Mask 0x00000010 */
+
+/************** Bits definition for DMA_CONFBx(x=0~1) register *************/
+#define DMA_STAT_Pos (16U) /*!< DMAC_CONFBx: STAT Position */
+#define DMA_STAT_Msk (0x07U << DMA_STAT_Pos) /*!< DMAC_CONFBx: STAT Mask 0x00070000 */
+
+/************** Bits definition for DMA_CONFBx(x=0~1) register *************/
+#define DMA_TRANSFER_RELOAD_Pos (0U) /*!< DMAC_CONFBx: MSK Position */
+#define DMA_TRANSFER_RELOAD_Msk (0x01U << DMA_TRANSFER_RELOAD_Pos) /*!< DMAC_CONFBx: MSK Mask 0x00000010 */
+
+/************** Bits definition for DMA_CONFAx(x=0~1) register *************/
+#define DMA_CH_ENABLE_Pos (31U) /*!< DMAC_CONFAx: ENS Position */
+#define DMA_CH_ENABLE_Msk (0x01U << DMA_CH_ENABLE_Pos) /*!< DMAC_CONFAx: ENS Mask 0x80000000 */
+
+/************** Bits definition for DMA_CONFAx(x=0~1) register *************/
+#define DMA_CH_PAUSE_Pos (30U) /*!< DMAC_CONFAx: PAS Position */
+#define DMA_CH_PAUSE_Msk (0x01U << DMA_CH_PAUSE_Pos) /*!< DMAC_CONFAx: PAS Mask 0x40000000 */
+
+/************** Bits definition for DMA_CONFAx(x=0~1) register *************/
+#define DMA_SOFTWARE_START_Pos (29U) /*!< DMAC_CONFAx: ENS Position */
+#define DMA_SOFTWARE_START_Msk (0x01U << DMA_SOFTWARE_START_Pos) /*!< DMAC_CONFAx: ENS Mask 0x20000000 */
+
+/************** Bits definition for DMA_CONFAx(x=0~1) register *************/
+#define DMA_TRI_SEL_Pos (22U) /*!< DMAC_CONFAx: TRISEL Position */
+#define DMA_TRI_SEL_Msk (0x7FU << DMA_TRI_SEL_Pos) /*!< DMAC_CONFAx: TRISEL Mask 0x1FC00000 */
+
+/************** Bits definition for DMA_CONFAx(x=0~1) register *************/
+#define DMA_BC_SEL_Pos (16U) /*!< DMAC_CONFAx: TRISEL Position */
+#define DMA_BC_SEL_Msk (0x0FU << DMA_BC_SEL_Pos) /*!< DMAC_CONFAx: TRISEL Mask 0x000F0000 */
+
+/************** Bits definition for DMA_CONFAx(x=0~1) register *************/
+#define DMA_TC_SEL_Pos (0U) /*!< DMAC_CONFAx: TRISEL Position */
+#define DMA_TC_SEL_Msk (0xFFFFU << DMA_TC_SEL_Pos) /*!< DMAC_CONFAx: TRISEL Mask 0x0000FFFF */
+
+/************** Bits definition for DMA_CONF register *************/
+#define DMA_ENABLE_Pos (31U) /*!< DMAC_CONF: TRISEL Position */
+#define DMA_ENABLE_Msk (0x01U << DMA_ENABLE_Pos) /*!< DMAC_CONF: TRISEL Mask 0x80000000 */
+
+/************** Bits definition for DMA_CONF register *************/
+#define DMA_PRIORITY_Pos (28U) /*!< DMAC_CONF: TRISEL Position */
+#define DMA_PRIORITY_Msk (0x01U << DMA_PRIORITY_Pos) /*!< DMAC_CONF: TRISEL Mask 0x10000000 */
+
+
+/*! Dmac通道参数有效性检查. */
+#define IS_VALID_CH(x) \
+( (DmaCh0 == (x)) || \
+ (DmaCh1 == (x)))
+
+/*! DMA 传输数据宽度，参数有效性检查. */
+#define IS_VALID_TRN_WIDTH(x) \
+( (DmaMsk8Bit == (x)) || \
+ (DmaMsk16Bit == (x)) || \
+ (DmaMsk32Bit == (x)))
+
+/*! DMA源地址控制模式，参数有效性检查. */
+#define IS_VALID_SRC_ADDR_MODE(x) \
+( (DmaMskSrcAddrFix == (x)) || \
+ (DmaMskSrcAddrInc == (x)))
+
+/*! DMA目的地址控制模式，参数有效性检查. */
+#define IS_VALID_DST_ADDR_MODE(x) \
+( (DmaMskDstAddrFix == (x)) || \
+ (DmaMskDstAddrInc == (x)))
+
+/*! DMA 优先级, 参数有效性检查. */
+#define IS_VALID_PRIO_MODE(x) \
+( (DmaMskPriorityFix == (x)) || \
+ (DmaMskPriorityLoop == (x)))
+
+/*! DMA 传输模式，参数有效性检查. */
+#define IS_VALID_TRANSFER_MODE(x) \
+( (DmaMskOneTransfer == (x)) || \
+ (DmaMskContinuousTransfer == (x)))
+
+/*! 块传输大小，参数有效性检查. */
+#define IS_VALID_BLKSIZE(x) ((!((x) & ~(DMA_BC_SEL_Msk >> DMA_BC_SEL_Pos)))&&((x)>0))
+
+/*! 块传输次数，参数有效性检查. */
+#define IS_VALID_TRNCNT(x) (!((x) & ~(DMA_TC_SEL_Msk >> DMA_TC_SEL_Pos)))
+
+/*******************************************************************************
+* Global variable definitions (declared in header file with 'extern')
+******************************************************************************/
+
+/*******************************************************************************
+* Local function prototypes ('static')
+******************************************************************************/
+
+/*******************************************************************************
+* Local variable definitions ('static')
+******************************************************************************/
+
+/*******************************************************************************
+* Function implementation - global ('extern') and local ('static')
+******************************************************************************/
+
+/**
+*******************************************************************************
+** \brief 初始化DMAC通道
+**
+** \param [in] enCh 指定通道.
+** \param [in] pstcCfg DMAC通道初始化配置结构体指针.
+**
+** \retval Ok 初始化成功.
+** \retval ErrorInvalidParameter pstcCfg是空指针.
+**
+** \note None
+**
+******************************************************************************/
+en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_cfg_t* pstcCfg)
+{
+ ASSERT(IS_VALID_CH(enCh));
+ ASSERT(NULL != pstcCfg);
+ ASSERT(IS_VALID_BLKSIZE(pstcCfg->u16BlockSize));
+ ASSERT(IS_VALID_TRNCNT(pstcCfg->u16TransferCnt));
+ ASSERT(IS_VALID_TRN_WIDTH(pstcCfg->enTransferWidth));
+ ASSERT(IS_VALID_SRC_ADDR_MODE(pstcCfg->enSrcAddrMode));
+ ASSERT(IS_VALID_DST_ADDR_MODE(pstcCfg->enDstAddrMode));
+ ASSERT(IS_VALID_PRIO_MODE(pstcCfg->enPriority));
+ ASSERT(IS_VALID_TRANSFER_MODE(pstcCfg->enTransferMode));
+
+ /* 检查通道值有效性和pstcCfg是否空指针 */
+ if (NULL == pstcCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ *(&M0P_DMAC->CONFB0+enCh) = 0;
+ *(&M0P_DMAC->CONFB0+enCh) = (uint32_t)pstcCfg->enMode |
+ (uint32_t)pstcCfg->enTransferWidth |
+ (uint32_t)pstcCfg->enSrcAddrMode |
+ (uint32_t)pstcCfg->enDstAddrMode |
+ (uint32_t)pstcCfg->enSrcAddrReloadCtl |
+ (uint32_t)pstcCfg->enDestAddrReloadCtl|
+ (uint32_t)pstcCfg->enSrcBcTcReloadCtl |
+ (uint32_t)pstcCfg->enTransferMode;
+
+ /*首先把TRI_SEL[6:0] BC[3:0] TC[15:0]这些位清零，然后再赋值*/
+ *(&M0P_DMAC->CONFA0+enCh) &= ((uint32_t)~(DMA_TRI_SEL_Msk | DMA_BC_SEL_Msk | DMA_TC_SEL_Msk));
+ *(&M0P_DMAC->CONFA0+enCh) |= (uint32_t)(pstcCfg->u16TransferCnt - 1) |
+ ((uint32_t)(pstcCfg->u16BlockSize - 1)<<16)|
+ (uint32_t)(pstcCfg->enRequestNum<<22);
+
+ M0P_DMAC->CONF |= (uint32_t)(pstcCfg->enPriority);
+
+ *(&M0P_DMAC->SRCADR0+enCh) = (uint32_t)(pstcCfg->u32SrcAddress);
+ *(&M0P_DMAC->DSTADR0+enCh) = (uint32_t)(pstcCfg->u32DstAddress);
+
+ return Ok;
+}
+/**
+*******************************************************************************
+** \brief DMA模块使能函数，使能所有通道的操作，每个通道按照各自设置工作.
+**
+** \param None
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_Enable(void)
+{
+ M0P_DMAC->CONF |= DMA_ENABLE_Msk;
+}
+
+/**
+*******************************************************************************
+** \brief DMA模块功能禁止函数，所有通道禁止工作.
+**
+** \param None
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_Disable(void)
+{
+ M0P_DMAC->CONF &= (~DMA_ENABLE_Msk);
+}
+/**
+*******************************************************************************
+** \brief 触发指定DMA通道软件传输功能.
+**
+** \param [输入] enCh 指定dma通道.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_SwStart(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFA0+enCh) |= DMA_SOFTWARE_START_Msk;
+}
+
+/**
+*******************************************************************************
+** \brief 停止指定DMA通道软件传输功能.
+**
+** \param [输入] enCh 指定dma通道.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_SwStop(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFA0+enCh) &= (~DMA_SOFTWARE_START_Msk);
+}
+/**
+*******************************************************************************
+** \brief 使能指定dma通道的（传输完成）中断.
+**
+** \param [输入] enCh 指定dma通道.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_EnableChannelIrq(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFB0+enCh) |= DMA_FIS_IE_Msk;
+}
+
+/**
+*******************************************************************************
+** \brief 禁用指定dma通道的（传输完成）中断.
+**
+** \param [输入] enCh 指定dma通道.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_DisableChannelIrq(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_FIS_IE_Msk);
+}
+/**
+*******************************************************************************
+** \brief 使能指定dma通道的（传输错误）中断..
+**
+** \param [输入] enCh 指定dma通道.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_EnableChannelErrIrq(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFB0+enCh) |= DMA_ERR_IE_Msk;
+}
+
+/**
+*******************************************************************************
+** \brief 禁用指定dma通道的（传输错误）中断..
+**
+** \param [输入] enCh 指定dma通道.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_DisableChannelErrIrq(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_ERR_IE_Msk);
+}
+
+/**
+*******************************************************************************
+** \brief 使能指定dma通道
+**
+** \param [输入] enCh 指定dma通道.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_EnableChannel(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFA0+enCh) |= DMA_CH_ENABLE_Msk;
+}
+
+/**
+*******************************************************************************
+** \brief 禁用指定dma通道
+**
+** \param [输入] enCh 指定dma通道.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_DisableChannel(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFA0+enCh) &= (~DMA_CH_ENABLE_Msk);
+}
+
+/**
+*******************************************************************************
+** \brief 设定指定通道的块(Block)尺寸
+**
+** \param [输入] enCh 指定通道
+** \param [输入] u16BlkSize 块(Block)尺寸.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_SetBlockSize(en_dma_channel_t enCh, uint16_t u16BlkSize)
+{
+ volatile uint32_t *pReg = (&M0P_DMAC->CONFA0+enCh);
+
+ *pReg = ((*pReg) & ((uint32_t)~DMA_BC_SEL_Msk)) | ((((uint32_t)u16BlkSize-1)&0x0f)<CONFA0+enCh);
+
+ *pReg = ((*pReg)&((uint32_t)~DMA_TC_SEL_Msk))|(((uint32_t)(u16TrnCnt-1)<CONFB0+enCh) |= DMA_TRANSFER_RELOAD_Msk;
+}
+
+/**
+*******************************************************************************
+** \brief 禁止指定通道连续传输，即DMAC在传输完成时清除.
+**
+** \param [输入] enCh 指定通道.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_DisableContinusTranfer(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_TRANSFER_RELOAD_Msk);
+}
+/**
+*******************************************************************************
+** \brief 暂停所有dma通道.
+**
+** \param None
+**
+** \retval None.
+**
+** \note None
+**
+******************************************************************************/
+void Dma_HaltTranfer(void)
+{
+ M0P_DMAC->CONF_f.HALT = 0x1;
+}
+/**
+*******************************************************************************
+** \brief 恢复（之前暂停的）所有dma通道.
+**
+** \param None
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_RecoverTranfer(void)
+{
+ M0P_DMAC->CONF_f.HALT = 0x0;
+}
+/**
+*******************************************************************************
+** \brief 暂停指定dma通道.
+**
+** \param [输入] enCh 指定通道.
+**
+** \retval void
+**
+** \note None
+**
+******************************************************************************/
+void Dma_PauseChannelTranfer(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFA0+enCh) |= DMA_CH_PAUSE_Msk;
+}
+/**
+*******************************************************************************
+** \brief 恢复（之前暂定的）指定dma通道.
+**
+** \param [输入] enCh 指定通道.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_RecoverChannelTranfer(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFA0+enCh) &= (~DMA_CH_PAUSE_Msk);
+}
+/**
+*******************************************************************************
+** \brief 设定指定通道传输数据宽度.
+**
+** \param [输入] enCh 指定dma通道.
+** \param [输入] enWidth 指定数据宽度.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_SetTransferWidth(en_dma_channel_t enCh, en_dma_transfer_width_t enWidth)
+{
+ volatile uint32_t *pReg = (&M0P_DMAC->CONFA0+enCh);
+
+ *pReg = ((*pReg)&((uint32_t)~DMA_TRANSFER_WIDTH_Msk))|((uint32_t)enWidth);
+}
+/**
+*******************************************************************************
+** \brief 设定dma通道优先级.
+**
+** \param [输入] enPrio 通道优先级设定参数.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_SetChPriority(en_dma_priority_t enPrio)
+{
+ M0P_DMAC->CONF = ((M0P_DMAC->CONF)&((uint32_t)~DMA_PRIORITY_Msk))|((uint32_t)enPrio);
+}
+/**
+*******************************************************************************
+** \brief 获取指定DMA通道的状态.
+**
+** \param [输入] enCh 指定dma通道.
+**
+** \retval en_dma_stat_t DMA传输当前状态
+**
+** \note None
+**
+******************************************************************************/
+en_dma_stat_t Dma_GetStat(en_dma_channel_t enCh)
+{
+ return (en_dma_stat_t)((*(&M0P_DMAC->CONFB0+enCh)&(DMA_STAT_Msk))>>DMA_STAT_Pos);
+}
+/**
+*******************************************************************************
+** \brief 清除指定DMA通道的状态值.
+**
+** \param [输入] enCh 指定dma通道.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_ClrStat(en_dma_channel_t enCh)
+{
+ *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_STAT_Msk);
+}
+
+
+/**
+*******************************************************************************
+** \brief 设定指定通道源地址
+**
+** \param [输入] enCh 指定dma通道.
+** \param [输入] u32Address 传输源地址.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_SetSourceAddress(en_dma_channel_t enCh, uint32_t u32Address)
+{
+ *(&M0P_DMAC->SRCADR0+enCh) = u32Address;
+}
+
+/**
+*******************************************************************************
+** \brief 设定指定通道目标地址.
+**
+** \param [输入] enCh 指定dma通道.
+** \param [输入] u32Address 传输目标地址.
+**
+** \retval None
+**
+** \note None
+**
+******************************************************************************/
+void Dma_SetDestinationAddress(en_dma_channel_t enCh, uint32_t u32Address)
+{
+ *(&M0P_DMAC->DSTADR0+enCh) = u32Address;
+}
+
+//@} // DmacGroup
+
+/*******************************************************************************
+* EOF (not truncated)
+******************************************************************************/
diff --git a/driver/src/flash.c b/driver/src/flash.c
new file mode 100644
index 0000000..22d436a
--- /dev/null
+++ b/driver/src/flash.c
@@ -0,0 +1,696 @@
+/******************************************************************************
+*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file flash.c
+ **
+ ** Common API of flash.
+ ** @link flashGroup Some description @endlink
+ **
+ ** - 2018-05-08
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "flash.h"
+/**
+ *******************************************************************************
+ ** \addtogroup FlashGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+#define FLASH_END_ADDR (0x0001FFFFu)
+#define FLASH_BYPASS() M0P_FLASH->BYPASS = 0x5A5A;\
+ M0P_FLASH->BYPASS = 0xA5A5;
+#define FLASH_IE_TRUE (0x03)
+#define FLASH_IE_FALSE (0x00)
+
+#define FLASH_TIMEOUT_INIT (0xFFFFFFu)
+#define FLASH_TIMEOUT_PGM (0xFFFFFFu)
+#define FLASH_TIMEOUT_ERASE (0xFFFFFFu)
+
+#define FLASH_LOCK_ALL (0u)
+#define FLASH_UNLOCK_ALL (0xFFFFFFFFu)
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+/**
+ ******************************************************************************
+ ** \brief FLASH OP
+ **
+ ** Flash 操作控制数据类型重定义
+ ******************************************************************************/
+typedef enum en_flash_op
+{
+ Read = 0u, ///<读配置值
+ Program = 1u, ///<编程配置值
+ SectorErase = 2u, ///<扇区擦除配置值
+ ChipErase = 3u, ///<全片擦除配置值
+} en_flash_op_t;
+
+/**
+ ******************************************************************************
+ ** \brief FLASH 编程时间参数配置
+ **
+ ** FLASH编程时间参数配置数组定义 (4MHz)
+ ******************************************************************************/
+const uint32_t pu32PcgTimer4M[] = {
+ 0x20u, //Tnvs
+ 0x17u, //Tpgs
+ 0x1Bu, //Tprog
+ 0x4650u, //Tserase
+ 0x222E0u, //Tmerase
+ 0x18u, //Tprcv
+ 0xF0u, //Tsrcv
+ 0x3E8u //Tmrcv
+ };
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *****************************************************************************
+ ** \brief Flash中断标志获取
+ **
+ **
+ ** \param [in] enFlashIntType Flash中断类型
+ **
+ ** \retval TRUE or FALSE
+ *****************************************************************************/
+boolean_t Flash_GetIntFlag(en_flash_int_type_t enFlashIntType)
+{
+ boolean_t bRetVal = FALSE;
+
+ if(M0P_FLASH->IFR & enFlashIntType)
+ {
+ bRetVal = TRUE;
+ }
+
+ return bRetVal;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Flash中断标志清除
+ **
+ **
+ ** \param [in] enFlashIntType Flash中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Flash_ClearIntFlag(en_flash_int_type_t enFlashIntType)
+{
+ en_result_t enResult = Error;
+
+ M0P_FLASH->ICLR &= ~(uint32_t)enFlashIntType;
+ enResult = Ok;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Flash中断使能
+ **
+ **
+ ** \param [in] enFlashIntType Flash中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Flash_EnableIrq (en_flash_int_type_t enFlashIntType)
+{
+ en_result_t enResult = Error;
+
+ FLASH_BYPASS();
+ M0P_FLASH->CR_f.IE |= enFlashIntType;
+
+ enResult = Ok;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Flash中断禁止
+ **
+ **
+ ** \param [in] enFlashIntType Flash中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Flash_DisableIrq(en_flash_int_type_t enFlashIntType)
+{
+ en_result_t enResult = Error;
+
+ FLASH_BYPASS();
+ M0P_FLASH->CR_f.IE &= ~(uint32_t)enFlashIntType;
+
+ enResult = Ok;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief FLASH 初始化函数——中断服务程序、编程时间配置及低功耗模式
+ **
+ ** 该函数用于配置中断服务函数、低功耗模式、根据系统时钟配置FLASH编程时间相关寄存器.
+ **
+ ** \param [in] u8FreqCfg FLASH编程时钟频率配置(根据HCLK的频率选择配置值)：
+ ** 1 - 4MHz;
+ ** 2 - 8MHz;
+ ** 4 - 16MHz;
+ ** 6 - 24MHz;
+ ** 8 - 32MHz;
+ ** 12 - 48MHz;
+ ** other - 无效值
+ ** \param [in] bDpstbEn TRUE - 当系统进入DeepSleep模式，FLASH进入低功耗模式;
+ ** FALSE - 当系统进入DeepSleep模式，FLASH不进入低功耗模式;
+ **
+ ** \retval Ok 操作成功.
+ ** \retval ErrorInvalidParameter 参数无效.
+ ** \retval ErrorUninitialized 初始化失败。
+ *****************************************************************************/
+en_result_t Flash_Init(uint8_t u8FreqCfg, boolean_t bDpstbEn)
+{
+ uint32_t u32Index = 0;
+ volatile uint32_t u32TimeOut = FLASH_TIMEOUT_INIT;
+ en_result_t enResult = Ok;
+ uint32_t u32PrgTimer[8] = {0};
+ volatile uint32_t *pu32PrgTimerReg = (volatile uint32_t*)M0P_FLASH;
+
+ if ((1 != u8FreqCfg) && (2 != u8FreqCfg) &&
+ (4 != u8FreqCfg) && (6 != u8FreqCfg) &&
+ (8 != u8FreqCfg) && (12 != u8FreqCfg))
+ {
+ enResult = ErrorInvalidParameter;
+ return (enResult);
+ }
+
+ M0P_FLASH->CR_f.DPSTB_EN = bDpstbEn;
+
+ //flash时间参数配置值计算
+ for(u32Index=0; u32Index<8; u32Index++)
+ {
+ u32PrgTimer[u32Index] = u8FreqCfg * pu32PcgTimer4M[u32Index];
+ }
+
+ //flash时间参数寄存器配置
+ for(u32Index=0; u32Index<8; u32Index++)
+ {
+ u32TimeOut = FLASH_TIMEOUT_INIT;
+ while(pu32PrgTimerReg[u32Index] != u32PrgTimer[u32Index])
+ {
+ if(u32TimeOut--)
+ {
+ FLASH_BYPASS();
+ pu32PrgTimerReg[u32Index] = u32PrgTimer[u32Index];
+ }
+ else
+ {
+ return ErrorUninitialized;
+ }
+ }
+ }
+
+ return (enResult);
+}
+
+/**
+ *****************************************************************************
+ ** \brief FLASH 字节写
+ **
+ ** 用于向FLASH写入1字节数据.
+ **
+ ** \param [in] u32Addr Flash地址
+ ** \param [in] u8Data 1字节数据
+ **
+ ** \retval Ok 写入成功.
+ ** \retval ErrorInvalidParameter FLASH地址无效
+ ** \retval ErrorTimeout 操作超时
+ *****************************************************************************/
+en_result_t Flash_WriteByte(uint32_t u32Addr, uint8_t u8Data)
+{
+ en_result_t enResult = Ok;
+ volatile uint32_t u32TimeOut = FLASH_TIMEOUT_PGM;
+
+ if (FLASH_END_ADDR < u32Addr)
+ {
+ enResult = ErrorInvalidParameter;
+ return (enResult);
+ }
+
+ //busy?
+ u32TimeOut = FLASH_TIMEOUT_PGM;
+ while (TRUE == M0P_FLASH->CR_f.BUSY)
+ {
+ if(0 == u32TimeOut--)
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //set OP
+ u32TimeOut = FLASH_TIMEOUT_PGM;
+ while(Program != M0P_FLASH->CR_f.OP)
+ {
+ if(u32TimeOut--)
+ {
+ FLASH_BYPASS();
+ M0P_FLASH->CR_f.OP = Program;
+ }
+ else
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //Flash 解锁
+ Flash_UnlockAll();
+
+ //write data
+ *((volatile uint8_t*)u32Addr) = u8Data;
+
+ //busy?
+ u32TimeOut = FLASH_TIMEOUT_PGM;
+ while (TRUE == M0P_FLASH->CR_f.BUSY)
+ {
+ if(0 == u32TimeOut--)
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //Flash 加锁
+ Flash_LockAll();
+
+ return (enResult);
+}
+
+/**
+ *****************************************************************************
+ ** \brief FLASH 半字写
+ **
+ ** 用于向FLASH写入半字（2字节）数据.
+ **
+ ** \param [in] u32Addr Flash地址
+ ** \param [in] u16Data 半字（2字节）数据
+ **
+ ** \retval Ok 写入成功.
+ ** \retval ErrorInvalidParameter FLASH地址无效
+ ** \retval ErrorTimeout 操作超时
+ *****************************************************************************/
+en_result_t Flash_WriteHalfWord(uint32_t u32Addr, uint16_t u16Data)
+{
+ en_result_t enResult = Ok;
+ volatile uint32_t u32TimeOut = FLASH_TIMEOUT_PGM;
+
+ if (FLASH_END_ADDR < u32Addr)
+ {
+ enResult = ErrorInvalidParameter;
+ return (enResult);
+ }
+
+ //busy?
+ u32TimeOut = FLASH_TIMEOUT_PGM;
+ while (TRUE == M0P_FLASH->CR_f.BUSY)
+ {
+ if(0 == u32TimeOut--)
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //set OP
+ u32TimeOut = FLASH_TIMEOUT_PGM;
+ while(Program != M0P_FLASH->CR_f.OP)
+ {
+ if(u32TimeOut--)
+ {
+ FLASH_BYPASS();
+ M0P_FLASH->CR_f.OP = Program;
+ }
+ else
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //Flash 解锁
+ Flash_UnlockAll();
+
+ //write data
+ *((volatile uint16_t*)u32Addr) = u16Data;
+
+ //busy?
+ u32TimeOut = FLASH_TIMEOUT_PGM;
+ while (TRUE == M0P_FLASH->CR_f.BUSY)
+ {
+ if(0 == u32TimeOut--)
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //Flash 加锁
+ Flash_LockAll();
+
+ return (enResult);
+}
+
+/**
+ *****************************************************************************
+ ** \brief FLASH 字写
+ **
+ ** 用于向FLASH写入1个字的数据.
+ **
+ ** \param [in] u32Addr Flash地址
+ ** \param [in] u32Data 1个字数据
+ **
+ ** \retval Ok 写入成功.
+ ** \retval ErrorInvalidParameter FLASH地址无效
+ ** \retval ErrorTimeout 操作超时
+ *****************************************************************************/
+en_result_t Flash_WriteWord(uint32_t u32Addr, uint32_t u32Data)
+{
+ en_result_t enResult = Ok;
+ volatile uint32_t u32TimeOut = FLASH_TIMEOUT_PGM;
+
+ if (FLASH_END_ADDR < u32Addr)
+ {
+ enResult = ErrorInvalidParameter;
+ return (enResult);
+ }
+
+ //busy?
+ u32TimeOut = FLASH_TIMEOUT_PGM;
+ while (TRUE == M0P_FLASH->CR_f.BUSY)
+ {
+ if(0 == u32TimeOut--)
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //Flash 解锁
+ Flash_UnlockAll();
+
+ //set OP
+ u32TimeOut = FLASH_TIMEOUT_PGM;
+ while(Program != M0P_FLASH->CR_f.OP)
+ {
+ if(u32TimeOut--)
+ {
+ FLASH_BYPASS();
+ M0P_FLASH->CR_f.OP = Program;
+ }
+ else
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //write data
+ *((volatile uint32_t*)u32Addr) = u32Data;
+
+ //busy?
+ u32TimeOut = FLASH_TIMEOUT_PGM;
+ while (TRUE == M0P_FLASH->CR_f.BUSY)
+ {
+ if(0 == u32TimeOut--)
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //Flash 加锁
+ Flash_LockAll();
+
+ return (enResult);
+}
+
+/**
+ *****************************************************************************
+ ** \brief FLASH 扇区擦除
+ **
+ ** FLASH 扇区擦除.
+ **
+ ** \param [in] u32SectorAddr 所擦除扇区内的地址
+ **
+ ** \retval Ok 擦除成功.
+ ** \retval ErrorInvalidParameter FLASH地址无效
+ ** \retval ErrorTimeout 操作超时
+ *****************************************************************************/
+en_result_t Flash_SectorErase(uint32_t u32SectorAddr)
+{
+ en_result_t enResult = Ok;
+ volatile uint32_t u32TimeOut = FLASH_TIMEOUT_ERASE;
+
+ if (FLASH_END_ADDR < u32SectorAddr)
+ {
+ enResult = ErrorInvalidParameter;
+ return (enResult);
+ }
+
+ //busy?
+ u32TimeOut = FLASH_TIMEOUT_ERASE;
+ while (TRUE == M0P_FLASH->CR_f.BUSY)
+ {
+ if(0 == u32TimeOut--)
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //Flash 解锁
+ Flash_UnlockAll();
+
+ //set OP
+ u32TimeOut = FLASH_TIMEOUT_ERASE;
+ while(SectorErase != M0P_FLASH->CR_f.OP)
+ {
+ if(u32TimeOut--)
+ {
+ FLASH_BYPASS();
+ M0P_FLASH->CR_f.OP = SectorErase;
+ }
+ else
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //write data
+ *((volatile uint8_t*)u32SectorAddr) = 0;
+
+ //busy?
+ u32TimeOut = FLASH_TIMEOUT_ERASE;
+ while (TRUE == M0P_FLASH->CR_f.BUSY)
+ {
+ if(0 == u32TimeOut--)
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //Flash 加锁
+ Flash_LockAll();
+
+ return (enResult);
+}
+
+/**
+ *****************************************************************************
+ ** \brief FLASH 全片擦除(该函数仅限RAM中运行！！！)
+ **
+ ** FLASH 全片擦除.
+ **
+ **
+ ** \retval Ok 擦除成功.
+ ** \retval ErrorTimeout 操作超时
+ **
+ *****************************************************************************/
+en_result_t Flash_ChipErase(void)
+{
+ en_result_t enResult = Ok;
+ volatile uint32_t u32TimeOut = FLASH_TIMEOUT_ERASE;
+
+ //busy?
+ u32TimeOut = FLASH_TIMEOUT_ERASE;
+ while (TRUE == M0P_FLASH->CR_f.BUSY)
+ {
+ if(0 == u32TimeOut--)
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //set OP
+ u32TimeOut = FLASH_TIMEOUT_ERASE;
+ while(ChipErase != M0P_FLASH->CR_f.OP)
+ {
+ if(u32TimeOut--)
+ {
+ FLASH_BYPASS();
+ M0P_FLASH->CR_f.OP = ChipErase;
+ }
+ else
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //Flash 解锁
+ Flash_UnlockAll();
+
+ //write data
+ *((volatile uint8_t*)0) = 0;
+
+ //busy?
+ u32TimeOut = FLASH_TIMEOUT_ERASE;
+ while (TRUE == M0P_FLASH->CR_f.BUSY)
+ {
+ if(0 == u32TimeOut--)
+ {
+ return ErrorTimeout;
+ }
+ }
+
+ //Flash 加锁
+ Flash_LockAll();
+
+ return (enResult);
+}
+
+/**
+ *****************************************************************************
+ ** \brief FLASH 编程保护加锁
+ **
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Flash_LockAll(void)
+{
+ FLASH_BYPASS();
+ M0P_FLASH->SLOCK0 = FLASH_LOCK_ALL;
+ FLASH_BYPASS();
+ M0P_FLASH->SLOCK1 = FLASH_LOCK_ALL;
+
+}
+
+/**
+ *****************************************************************************
+ ** \brief FLASH 编程保护解锁
+ **
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Flash_UnlockAll(void)
+{
+
+ FLASH_BYPASS();
+ M0P_FLASH->SLOCK0 = FLASH_UNLOCK_ALL;
+ FLASH_BYPASS();
+ M0P_FLASH->SLOCK1 = FLASH_UNLOCK_ALL;
+
+}
+
+/**
+ *****************************************************************************
+ ** \brief FLASH 读等待周期设置
+ **
+ ** \param [in] enWaitCycle 插入FLASH读等待周期数枚举类型
+ **
+ ** \retval Ok 解锁成功
+ ** \retval ErrorInvalidParameter 参数错误
+ *****************************************************************************/
+en_result_t Flash_WaitCycle(en_flash_waitcycle_t enWaitCycle)
+{
+ en_result_t enResult = Ok;
+
+ FLASH_BYPASS();
+ M0P_FLASH->CR_f.WAIT = enWaitCycle;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief FLASH LOCK 设置
+ **
+ ** \param [in] enLock @ref en_flash_lock_t
+ ** \param [in] u32LockValue 32bits，对应bit=0：加锁，对应Sector不允许擦写；对应bit=1：解锁。
+ ** \note 加解锁范围Sector：[enLock*128 + i*4, enLock*128 + i*4+3]
+ ** (i表示u32LockValue的bit位置，0~31)
+ ** 例如：enLock = FlashLock1, u32LockValue = 0x00000002,
+ ** 则加解锁范围为：[Sector128,Sector131]
+ ** \retval Ok 解锁成功
+ ** \retval ErrorInvalidParameter 参数错误
+ *****************************************************************************/
+en_result_t Flash_LockSet(en_flash_lock_t enLock, uint32_t u32LockValue)
+{
+ FLASH_BYPASS();
+ *((&M0P_FLASH->SLOCK0) + enLock) = u32LockValue;
+
+ return Ok;
+}
+//@} // FlashGroup
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/gpio.c b/driver/src/gpio.c
new file mode 100644
index 0000000..e639cc4
--- /dev/null
+++ b/driver/src/gpio.c
@@ -0,0 +1,582 @@
+/******************************************************************************
+* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file Gpio.c
+ **
+ ** GPIO driver API.
+ ** @link Driver Group Some description @endlink
+ **
+ ** - 2018-04-22 1.0 Lux First version
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "gpio.h"
+
+/**
+ *******************************************************************************
+ ** \addtogroup GpioGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+#define IS_VALID_PIN(port,pin) ( )
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern') *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *******************************************************************************
+ ** \brief GPIO 初始化
+ **
+ ** \param [in] enPort IO Port口
+ ** \param [in] enPin IO Pin脚
+ ** \param [in] pstcGpioCfg IO 配置结构体指针
+ **
+ ** \retval Ok 设置成功
+ ** 其他值 设置失败
+ ******************************************************************************/
+en_result_t Gpio_Init(en_gpio_port_t enPort, en_gpio_pin_t enPin, stc_gpio_cfg_t *pstcGpioCfg)
+{
+ //配置为默认值,GPIO功能
+ SetBit((uint32_t)&M0P_GPIO->PAADS + enPort, enPin, FALSE);
+ *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + enPort) + (((uint32_t)enPin)<<2))) = GpioAf0;
+
+ //默认输出值配置
+ SetBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin, pstcGpioCfg->bOutputVal);
+ //方向配置
+ SetBit(((uint32_t)&M0P_GPIO->PADIR + enPort), enPin, (boolean_t)(pstcGpioCfg->enDir));
+ //驱动能力配置
+ SetBit(((uint32_t)&M0P_GPIO->PADR + enPort), enPin, (boolean_t)(pstcGpioCfg->enDrv));
+ //上拉/下拉配置
+ SetBit(((uint32_t)&M0P_GPIO->PAPU + enPort), enPin, (boolean_t)(pstcGpioCfg->enPu));
+ SetBit(((uint32_t)&M0P_GPIO->PAPD + enPort), enPin, (boolean_t)(pstcGpioCfg->enPd));
+ //开漏输出功能
+ SetBit(((uint32_t)&M0P_GPIO->PAOD + enPort), enPin, (boolean_t)(pstcGpioCfg->enOD));
+
+ M0P_GPIO->CTRL2_f.AHB_SEL = pstcGpioCfg->enCtrlMode;
+
+ return Ok;
+}
+
+
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO输入值获取
+ **
+ ** \param [in] enPort IO Port口
+ ** \param [in] enPin IO Pin脚
+ **
+ ** \retval boolean_t IO电平高低
+ ******************************************************************************/
+boolean_t Gpio_GetInputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin)
+{
+ return GetBit(((uint32_t)&M0P_GPIO->PAIN + enPort), enPin);
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO Port输入数据获取
+ **
+ ** \param [in] enPort IO Port
+ **
+ ** \retval boolean_t IO Port数据
+ ******************************************************************************/
+uint16_t Gpio_GetInputData(en_gpio_port_t enPort)
+{
+ return (uint16_t)(*((uint32_t *)((uint32_t)&M0P_GPIO->PAIN + enPort)));
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO输出值写入
+ **
+ ** \param [in] enPort IO Port口
+ ** \param [in] enPin IO Pin脚
+ ** \param [out] bVal 输出值
+ **
+ ** \retval en_result_t Ok 设置成功
+ ** 其他值 设置失败
+ ******************************************************************************/
+en_result_t Gpio_WriteOutputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin, boolean_t bVal)
+{
+ SetBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin, bVal);
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO输出值获取
+ **
+ ** \param [in] enPort IO Port口
+ ** \param [in] enPin IO Pin脚
+ **
+ ** \retval boolean_t IO电平高低
+ ******************************************************************************/
+boolean_t Gpio_ReadOutputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin)
+{
+ return GetBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin);
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO Port设置，可同时设置一组Port中的多个PIN
+ **
+ ** \param [in] enPort IO Port
+ ** \param [in] u16ValMsk 该Port的16个PIN掩码值,将需要设置的PIN对应的bit写1有效
+ **
+ ** \retval boolean_t IO Port数据
+ ******************************************************************************/
+en_result_t Gpio_SetPort(en_gpio_port_t enPort, uint16_t u16ValMsk)
+{
+ *((uint16_t*)(((uint32_t)&(M0P_GPIO->PABSET)) + enPort)) = u16ValMsk;
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO设置
+ **
+ ** \param [in] enPort IO Port口
+ ** \param [in] enPin IO Pin脚
+ **
+ ** \retval en_result_t Ok 设置成功
+ ** 其他值 设置失败
+ ******************************************************************************/
+en_result_t Gpio_SetIO(en_gpio_port_t enPort, en_gpio_pin_t enPin)
+{
+ SetBit(((uint32_t)&M0P_GPIO->PABSET + enPort), enPin, TRUE);
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO Port清零，可同时清零一组Port中的多个PIN
+ **
+ ** \param [in] enPort IO Port
+ ** \param [in] u16ValMsk 该Port的16个PIN掩码值,将需要清零的PIN对应的bit写1有效
+ **
+ ** \retval boolean_t IO Port数据
+ ******************************************************************************/
+en_result_t Gpio_ClrPort(en_gpio_port_t enPort, uint16_t u16ValMsk)
+{
+ *((uint16_t*)(((uint32_t)&(M0P_GPIO->PABCLR)) + enPort)) = u16ValMsk;
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO清零
+ **
+ ** \param [in] enPort IO Port口
+ ** \param [in] enPin IO Pin脚
+ **
+ ** \retval en_result_t Ok 设置成功
+ ** 其他值 设置失败
+ ******************************************************************************/
+en_result_t Gpio_ClrIO(en_gpio_port_t enPort, en_gpio_pin_t enPin)
+{
+ SetBit(((uint32_t)&M0P_GPIO->PABCLR + enPort), enPin, TRUE);
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO Port置位/清零，可同时置位/清零一组Port中的多个PIN
+ **
+ ** \param [in] enPort IO Port
+ ** \param [in] u32ValMsk 高16bits表示该Port的16个PIN置位掩码值,
+ ** 低16bits表示该Port的16个PIN清零掩码值,
+ ** 将需要设置的PIN对应的bit写1,同一个PIN的掩码同时为1,则该PIN清零。
+ **
+ ** \retval en_result_t Ok 设置成功
+ ** 其他值 设置失败
+ ******************************************************************************/
+en_result_t Gpio_SetClrPort(en_gpio_port_t enPort, uint32_t u32ValMsk)
+{
+ *((uint32_t*)(((uint32_t)&(M0P_GPIO->PABSETCLR)) + enPort)) = u32ValMsk;
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO配置为模拟功能模式
+ **
+ ** \param [in] enPort IO Port口
+ ** \param [in] enPin IO Pin脚
+ **
+ ** \retval Ok 设置成功
+ ** 其他值 设置失败
+ ******************************************************************************/
+en_result_t Gpio_SetAnalogMode(en_gpio_port_t enPort, en_gpio_pin_t enPin)
+{
+ SetBit((uint32_t)&M0P_GPIO->PAADS + enPort, enPin, TRUE);
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+** \brief GPIO IO复用功能设置
+ **
+ ** \param [in] enPort IO Port口
+ ** \param [in] enPin IO Pin脚
+ ** \param [in] enAf 复用功能枚举类型选择
+ ** \retval Ok 设置成功
+ ** 其他值 设置失败
+ ******************************************************************************/
+en_result_t Gpio_SetAfMode(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_af_t enAf)
+{
+ *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + enPort) + (((uint32_t)enPin)<<2))) = enAf;
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO复用功能设置
+ **
+ ** \param [in] PinMux 复用功能宏定义
+ ** \retval Null
+ **
+ ******************************************************************************/
+void Gpio_SetAfMode_Lite(GpioPinMux PinMux)
+{
+ *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + ((PinMux>>16u)&0xFFFFu)) + (((uint32_t)((PinMux>>8u)&0xFFu))<<2))) = (uint32_t)(PinMux&0x7u);
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO中断使能
+ **
+ ** \param [in] enPort IO Port口
+ ** \param [in] enPin IO Pin脚
+ ** \param [in] enType 中断使能类型
+ **
+ ** \retval Ok 设置成功
+ ******************************************************************************/
+en_result_t Gpio_EnableIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_irqtype_t enType)
+{
+ uint32_t u32PieAddr;
+
+ u32PieAddr = ((uint32_t)((&M0P_GPIO->PAHIE) + enType)) + enPort;
+
+ SetBit(u32PieAddr, enPin, TRUE);
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO IO中断关闭
+ **
+ ** \param [in] enPort IO Port口
+ ** \param [in] enPin IO Pin脚
+ ** \param [in] enType 中断使能类型
+ **
+ ** \retval Ok 设置成功
+ ******************************************************************************/
+en_result_t Gpio_DisableIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_irqtype_t enType)
+{
+ uint32_t u32PieAddr;
+
+ u32PieAddr = ((uint32_t)((&M0P_GPIO->PAHIE) + enType)) + enPort;
+
+ SetBit(u32PieAddr, enPin, FALSE);
+
+ return Ok;
+}
+
+
+/**
+ *******************************************************************************
+ ** \brief GPIO 获得IO中断状态
+ **
+ ** \param [in] u8Port IO Port口
+ ** \param [in] u8Pin IO Pin脚
+ **
+ ** \retval IO中断状态开关
+ ******************************************************************************/
+boolean_t Gpio_GetIrqStatus(en_gpio_port_t enPort, en_gpio_pin_t enPin)
+{
+ return GetBit((uint32_t)&M0P_GPIO->PA_STAT + enPort, enPin);
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO 清除IO中断状态
+ **
+ ** \param [in] u8Port IO Port口
+ ** \param [in] u8Pin IO Pin脚
+ **
+ ** \retval Ok 设置成功
+ ******************************************************************************/
+en_result_t Gpio_ClearIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin)
+{
+ SetBit((uint32_t)&M0P_GPIO->PA_ICLR + enPort, enPin, FALSE);
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO 端口辅助功能配置——中断模式配置
+ **
+ ** \param [in] enIrqMode 端口中断模式（深度休眠是否响应中断）
+ **
+ ** \retval Ok 设置成功
+ ******************************************************************************/
+en_result_t Gpio_SfIrqModeCfg(en_gpio_sf_irqmode_t enIrqMode)
+{
+ M0P_GPIO->CTRL0_f.IESEL = enIrqMode;
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO 端口辅助功能配置——IR输出极性配置
+ **
+ ** \param [in] enIrPolMode IR输出极性配置枚举
+ **
+ ** \retval Ok 设置成功
+ ******************************************************************************/
+en_result_t Gpio_SfIrPolCfg(en_gpio_sf_irpol_t enIrPolMode)
+{
+ M0P_GPIO->CTRL1_f.IR_POL = enIrPolMode;
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO 端口辅助功能配置——HCLK输出配置
+ **
+ ** \param [in] enGate HCLK输出使能
+ ** \param [in] enDiv 输出分频枚举值
+ **
+ ** \retval Ok 设置成功
+ ******************************************************************************/
+en_result_t Gpio_SfHClkOutputCfg(en_gpio_sf_hclkout_g_t enGate, en_gpio_sf_hclkout_div_t enDiv)
+{
+ M0P_GPIO->CTRL1_f.HCLK_EN = enGate;
+ M0P_GPIO->CTRL1_f.HCLK_SEL = enDiv;
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO 端口辅助功能配置——PCLK输出配置
+ **
+ ** \param [in] enGate PCLK输出使能
+ ** \param [in] enDiv 输出分频枚举值
+ **
+ ** \retval Ok 设置成功
+ ******************************************************************************/
+en_result_t Gpio_SfPClkOutputCfg(en_gpio_sf_pclkout_g_t enGate, en_gpio_sf_pclkout_div_t enDiv)
+{
+ M0P_GPIO->CTRL1_f.PCLK_EN = enGate;
+ M0P_GPIO->CTRL1_f.PCLK_SEL = enDiv;
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO 端口辅助功能配置——外部时钟输入来源配置
+ **
+ ** \param [in] enExtClk 外部时钟信号来源选择枚举
+ **
+ ** \retval Ok 设置成功
+ ******************************************************************************/
+en_result_t Gpio_SfExtClkCfg(en_gpio_sf_ssn_extclk_t enExtClk)
+{
+ M0P_GPIO->CTRL1_f.EXT_CLK_SEL = enExtClk;
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO 端口辅助功能配置——SSN 通道信号来源配置
+ **
+ ** \param [in] enSpi SSN SPI通道选择枚举
+ ** \param [in] enSsn SSN 信号来源选择枚举
+ **
+ ** \retval Ok 设置成功
+ ******************************************************************************/
+en_result_t Gpio_SfSsnCfg(en_gpio_sf_ssnspi_t enSpi, en_gpio_sf_ssn_extclk_t enSsn)
+{
+ //SPI0
+ if(enSpi == GpioSpi0)
+ {
+ M0P_GPIO->CTRL1_f.SSN0_SEL = enSsn;
+ }
+ //SPI1
+ if(enSpi == GpioSpi1)
+ {
+ M0P_GPIO->CTRL2_f.SSN1_SEL = enSsn;
+ }
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO 端口辅助功能配置——Timer 门控输入配置
+ **
+ ** \param [in] enTimG Timer类型选择枚举
+ ** \param [in] enSf Timer互联功能选择枚举
+ **
+ ** \retval Ok 设置成功
+ ******************************************************************************/
+en_result_t Gpio_SfTimGCfg(en_gpio_sf_tim_g_t enTimG, en_gpio_sf_t enSf)
+{
+ if(enTimG&0x20u)
+ {
+ enTimG &= ~0x20u;
+ M0P_GPIO->PCAS &= (uint32_t)(~(0x07U<PCAS |= (uint32_t)(enSf<TIMGS &= (uint32_t)(~(0x07U<TIMGS |= (uint32_t)(enSf<PCAS &= (uint32_t)(~(0x07U<PCAS |= (uint32_t)(enSf<TIMES &= (uint32_t)(~(0x07U<TIMES |= (uint32_t)(enSf<TIMCPS &= (uint32_t)(~(0x07u<TIMCPS |= (uint32_t)(enSf<PCAS &= (uint32_t)(~(0x07u<PCAS |= (uint32_t)(enSf<TM = u8Tm;
+
+ enRet = Ok;
+ return enRet;
+ }
+ /**
+ ******************************************************************************
+ ** \brief I2C功能设置相关函数
+ **
+ ** \param [in] enFunc功能参数
+ **
+ ** \retval enRet 成功或失败
+ **
+ ******************************************************************************/
+en_result_t I2C_SetFunc(M0P_I2C_TypeDef* I2Cx, en_i2c_func_t enFunc)
+{
+ en_result_t enRet = Error;
+
+ SetBit((uint32_t)&I2Cx->CR, enFunc, TRUE);
+
+ enRet = Ok;
+ return enRet;
+}
+ /**
+ ******************************************************************************
+ ** \brief I2C功能清除相关函数
+ **
+ ** \param [in] enFunc功能参数
+ **
+ ** \retval enRet 成功或失败
+ **
+ ******************************************************************************/
+ en_result_t I2C_ClearFunc(M0P_I2C_TypeDef* I2Cx, en_i2c_func_t enFunc)
+ {
+ en_result_t enRet = Error;
+
+ SetBit((uint32_t)&I2Cx->CR, enFunc, FALSE);
+
+ enRet = Ok;
+ return enRet;
+ }
+ /**
+ ******************************************************************************
+ ** \brief I2C获取中断标记函数
+ **
+ ** \param 无
+ **
+ ** \retval bIrq中断标记
+ **
+ ******************************************************************************/
+boolean_t I2C_GetIrq(M0P_I2C_TypeDef* I2Cx)
+{
+ if(I2Cx->CR&0x8)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+}
+/**
+ ******************************************************************************
+ ** \brief I2C清除中断标记函数
+ **
+ ** \param 无
+ **
+ ** \retval bIrq中断标记
+ **
+ ******************************************************************************/
+en_result_t I2C_ClearIrq(M0P_I2C_TypeDef* I2Cx)
+{
+ en_result_t enRet = Error;
+
+ I2Cx->CR &= ~0x8u;
+
+ enRet = Ok;
+ return enRet;
+}
+ /**
+ ******************************************************************************
+ ** \brief I2C获取相关状态
+ **
+ ** \param 无
+ **
+ ** \retval I2C状态
+ **
+ ******************************************************************************/
+uint8_t I2C_GetState(M0P_I2C_TypeDef* I2Cx)
+{
+ uint8_t u8State = 0;
+
+ u8State = I2Cx->STAT;
+
+ return u8State;
+}
+
+/**
+ ******************************************************************************
+ ** \brief 字节数据写函数
+ **
+ ** \param u8Data写数据
+ **
+ ** \retval 写数据是否成功
+ **
+ ******************************************************************************/
+en_result_t I2C_WriteByte(M0P_I2C_TypeDef* I2Cx, uint8_t u8Data)
+{
+ en_result_t enRet = Error;
+
+ I2Cx->DATA = u8Data;
+
+ enRet = Ok;
+ return enRet;
+}
+/**
+ ******************************************************************************
+ ** \brief 字节数据读函数
+ **
+ ** \param 无
+ **
+ ** \retval 读取数据
+ **
+ ******************************************************************************/
+uint8_t I2C_ReadByte(M0P_I2C_TypeDef* I2Cx)
+{
+ uint8_t u8Data = 0;
+
+ u8Data = I2Cx->DATA;
+
+ return u8Data;
+}
+
+/**
+ ******************************************************************************
+ ** \brief I2C模块初始化
+ **
+ ** \param pstcI2CCfg初始化配置结构体
+ **
+ ** \retval 初始化是否成功
+ **
+ ******************************************************************************/
+en_result_t I2C_Init(M0P_I2C_TypeDef* I2Cx, stc_i2c_cfg_t *pstcI2CCfg)
+{
+ en_result_t enRet = Error;
+ uint8_t u8Tm;
+
+ if(M0P_I2C0 == I2Cx)
+ {
+ M0P_RESET->PERI_RESET0 &= ~(uint32_t)0x10u;
+ M0P_RESET->PERI_RESET0 |= (uint32_t)0x10u;
+ }
+ else
+ {
+ M0P_RESET->PERI_RESET0 &= ~(uint32_t)0x20u;
+ M0P_RESET->PERI_RESET0 |= (uint32_t)0x20u;
+ }
+
+ I2Cx->CR = 0;
+ I2Cx->CR = pstcI2CCfg->enMode;
+
+ if((pstcI2CCfg->u32Baud<<4) > pstcI2CCfg->u32Pclk)
+ {
+ return Error;
+ }
+
+ if(I2cMasterMode == pstcI2CCfg->enMode)
+ {
+ I2Cx->TMRUN = TRUE;
+ ///< Fsck = Fpclk/8*(Tm+1)
+ u8Tm = ((pstcI2CCfg->u32Pclk / pstcI2CCfg->u32Baud) >> 3) - 1;
+ if(9 > u8Tm)
+ {
+ I2C_SetFunc(I2Cx,I2cHlm_En);
+ }
+ enRet = I2C_SetBaud(I2Cx, u8Tm);
+ }
+ else
+ {
+ I2Cx->TMRUN = FALSE;
+ pstcI2CCfg->u8SlaveAddr = (uint8_t)(((uint32_t)pstcI2CCfg->u8SlaveAddr<<1)|(pstcI2CCfg->bGc));
+ I2Cx->ADDR = pstcI2CCfg->u8SlaveAddr;
+ }
+
+ return enRet;
+}
+
+//@} // I2cGroup
diff --git a/driver/src/lcd.c b/driver/src/lcd.c
new file mode 100644
index 0000000..dfbab6e
--- /dev/null
+++ b/driver/src/lcd.c
@@ -0,0 +1,289 @@
+/******************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file lcd.c
+ **
+ ** lcd driver API.
+ **
+ ** - 2019-04-02 First Version
+ **
+ ******************************************************************************/
+
+/******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "lcd.h"
+
+
+/**
+ ******************************************************************************
+ ** \addtogroup AdcGroup
+ ******************************************************************************/
+//@{
+
+/******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*****************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ *****************************************************************************/
+
+/**
+******************************************************************************
+ ** \brief 获取LCD中断标志位INTF
+ **
+ ** @param 无
+ ** \retval 无
+ **
+******************************************************************************/
+boolean_t Lcd_GetItStatus(void)
+{
+ return (((M0P_LCD->CR1)>>11)&0x01)? TRUE : FALSE;
+}
+
+/**
+******************************************************************************
+ ** \brief 清除中断标志位INTF
+ **
+ ** @param 无
+ ** \retval 无
+ **
+******************************************************************************/
+void Lcd_ClearItPendingBit(void)
+{
+ SetBit((uint32_t)(&(M0P_LCD->INTCLR)), 10, 0);
+}
+
+/**
+******************************************************************************
+ ** \brief 根据LCD显示模式获取端口配置
+ **
+ ** \param pstcSegComPara：显示方式， stcSegCom获取端口参数
+ **
+ ** \retval enRet 成功或失败
+ **
+******************************************************************************/
+en_result_t Lcd_GetSegCom(stc_lcd_segcompara_t *pstcSegComPara,stc_lcd_segcom_t *pstcSegCom)
+{
+ en_result_t enRet = Error;
+ pstcSegCom->stc_seg32_51_com0_8_t.seg32_51_com0_8 = 0xffffffffu;
+ pstcSegCom->u32Seg0_31 = 0xffffffffu;
+ if(pstcSegComPara->u8MaxSeg>51)
+ {
+ return ErrorInvalidParameter;
+ }
+ switch(pstcSegComPara->LcdBiasSrc)
+ {
+ case LcdInResHighPower:
+ case LcdInResLowPower:
+ case LcdInResMidPower:
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Mux = 1;
+ break;
+ case LcdExtCap:
+ case LcdExtRes:
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Mux = 0;
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg32_35 = 0;
+ break;
+ default:
+ return ErrorInvalidParameter;
+ }
+ switch(pstcSegComPara->LcdDuty)
+ {
+ case LcdStatic:
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~1u)&0x0fu;
+ break;
+ case LcdDuty2:
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~3u)&0x0fu;
+ break;
+ case LcdDuty3:
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~7u)&0x0fu;
+ break;
+ case LcdDuty4:
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~15u)&0x0fu;
+ break;
+ case LcdDuty6:
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = 0;
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg39Com4 = 0;
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg38Com5 = 0;
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg37Com6 = 1;
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg36Com7 = 1;
+ break;
+ case LcdDuty8:
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = 0;
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg39Com4 = 0;
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg38Com5 = 0;
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg37Com6 = 0;
+ pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg36Com7 = 0;
+ break;
+ default:
+ return ErrorInvalidParameter;
+ }
+ enRet = Ok;
+ return enRet;
+}
+
+/**
+******************************************************************************
+ ** \brief LCD COMSEG端口配置，使用该函数之前需要先使能相应的Seg
+ **
+ ** \param [in] pstcSegCom端口配置结构体
+ **
+ ** \retval enRet 成功或失败
+ **
+******************************************************************************/
+void Lcd_SetSegCom(stc_lcd_segcom_t *pstcSegCom)
+{
+ M0P_LCD->POEN0 = pstcSegCom->u32Seg0_31;
+ M0P_LCD->POEN1 = pstcSegCom->stc_seg32_51_com0_8_t.seg32_51_com0_8;
+}
+
+/**
+******************************************************************************
+ ** \brief LCD模块初始化函数
+ **
+ ** \param stcLcdCfg配置初始化结构体
+ **
+ ** \retval 无
+ **
+******************************************************************************/
+void Lcd_Init(stc_lcd_cfg_t *pstcLcdCfg)
+{
+ M0P_LCD->CR0_f.BSEL = pstcLcdCfg->LcdBiasSrc;
+ M0P_LCD->CR0_f.DUTY = pstcLcdCfg->LcdDuty;
+ M0P_LCD->CR0_f.BIAS = pstcLcdCfg->LcdBias;
+ M0P_LCD->CR0_f.CPCLK = pstcLcdCfg->LcdCpClk;
+ M0P_LCD->CR0_f.LCDCLK = pstcLcdCfg->LcdScanClk;
+ M0P_LCD->CR1_f.MODE = pstcLcdCfg->LcdMode;
+ M0P_LCD->CR1_f.CLKSRC = pstcLcdCfg->LcdClkSrc;
+ M0P_LCD->CR0_f.EN = pstcLcdCfg->LcdEn;
+}
+
+/**
+******************************************************************************
+ ** \brief 液晶全显
+ **
+ ** \param 无
+ **
+ ** \retval 无
+ **
+******************************************************************************/
+void Lcd_FullDisp(void)
+{
+ uint8_t tmp;
+ volatile uint32_t *ram = NULL;
+ ram = &M0P_LCD->RAM0;
+ for(tmp=0;tmp<16;tmp++)
+ {
+ *ram = 0xffffffffu;
+ ram++;
+ }
+}
+
+/**
+******************************************************************************
+ ** \brief 清屏
+ **
+ ** \param 无
+ **
+ ** \retval 无
+ **
+******************************************************************************/
+void Lcd_ClearDisp(void)
+{
+ uint8_t tmp;
+ volatile uint32_t *ram = NULL;
+ ram = &M0P_LCD->RAM0;
+ for(tmp=0;tmp<16;tmp++)
+ {
+ *ram = 0;
+ ram++;
+ }
+}
+
+/**
+ ******************************************************************************
+ ** \brief LCD RAM 0-f寄存器设置函数
+ **
+ ** \param u8Row RAM地址索引，范围：0-15，u8Data写入寄存器数值
+ **
+ ** \retval enRet 成功或失败
+ **
+ ******************************************************************************/
+en_result_t Lcd_WriteRam(uint8_t u8Row,uint32_t u32Data)
+{
+ en_result_t enRet = Error;
+ volatile uint32_t *ram = NULL;
+ ram = (volatile uint32_t*)&M0P_LCD->RAM0;
+
+ if (u8Row > 15)
+ {
+ enRet = ErrorInvalidParameter;
+ return enRet;
+ }
+
+ ram += u8Row;
+ *ram = u32Data;
+ enRet = Ok;
+ return enRet;
+}
+
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
diff --git a/driver/src/lpm.c b/driver/src/lpm.c
new file mode 100644
index 0000000..93bcf7a
--- /dev/null
+++ b/driver/src/lpm.c
@@ -0,0 +1,122 @@
+/******************************************************************************
+*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file lpm.c
+ **
+ ** Common API of lpm.
+ ** @link LpmGroup Some description @endlink
+ **
+ ** - 2017-06-06
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "lpm.h"
+/**
+ *******************************************************************************
+ ** \addtogroup LpmGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *****************************************************************************
+ ** \brief 进入深度睡眠模式
+ **
+ ** \input bOnExit - TRUE:当退出异常处理后，自动再次进入休眠；
+ ** FALSE：唤醒后不再自动进入休眠
+ **
+ ** \retval NULL
+ *****************************************************************************/
+void Lpm_GotoDeepSleep(boolean_t bOnExit)
+{
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ SCB->SCR |= 1u<SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ SCB->SCR |= 1u<CR)), 10, NewStatus);
+}
+
+/**
+******************************************************************************
+ ** \brief 定时器LPTIMx的启动/停止控制
+ ** @param Lptimx : LPTIM0 或LPTIM1
+ ** @param NewStatus : TRUE 或 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Lptim_Cmd(M0P_LPTIMER_TypeDef* Lptimx, boolean_t NewStatus)
+{
+ SetBit((uint32_t)(&(Lptimx->CR)), 0, NewStatus);
+}
+
+/**
+******************************************************************************
+ ** \brief 定时器LPTIMx的中断标志位获取
+ ** @param Lptimx : LPTIM0 或LPTIM1
+ ** \retval TRUE 或 FALSE
+ **
+******************************************************************************/
+boolean_t Lptim_GetItStatus(M0P_LPTIMER_TypeDef* Lptimx)
+{
+ return GetBit((uint32_t)(&(Lptimx->IFR)), 0);
+}
+
+/**
+******************************************************************************
+ ** \brief 定时器LPTIMx的中断标志位清除
+ ** @param Lptimx : LPTIM0 或LPTIM1
+ ** \retval 无
+ **
+******************************************************************************/
+void Lptim_ClrItStatus(M0P_LPTIMER_TypeDef* Lptimx)
+{
+ SetBit((uint32_t)(&(Lptimx->ICLR)), 0, 0);
+}
+
+/**
+******************************************************************************
+ ** \brief 定时器LPTIMx的初始化配置
+ ** @param Lptimx : LPTIM0 或LPTIM1
+ ** @param InitStruct : 初始化LPTIMx的结构体
+ ** \retval en_result_t类型数据
+ **
+******************************************************************************/
+en_result_t Lptim_Init(M0P_LPTIMER_TypeDef* Lptimx, stc_lptim_cfg_t* InitStruct)
+{
+ uint16_t u16TimeOut;
+ u16TimeOut = 1000;
+ Lptimx->CR_f.PRS = InitStruct->enPrs;
+ Lptimx->CR_f.TCK_SEL = InitStruct->enTcksel;
+ Lptimx->CR_f.GATE_P = InitStruct->enGatep;
+ Lptimx->CR_f.GATE = InitStruct->enGate;
+ Lptimx->CR_f.TOG_EN = InitStruct->enTogen;
+ Lptimx->CR_f.CT = InitStruct->enCt;
+ Lptimx->CR_f.MD = InitStruct->enMd;
+ while(u16TimeOut--)
+ {
+ if(Lptimx->CR_f.WT_FLAG)
+ {
+ break;
+ }
+ }
+ if(u16TimeOut == 0)
+ {
+ return ErrorTimeout;
+ }
+ Lptimx->ARR_f.ARR = InitStruct->u16Arr;
+ return Ok;
+}
+
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/lpuart.c b/driver/src/lpuart.c
new file mode 100644
index 0000000..5e8828f
--- /dev/null
+++ b/driver/src/lpuart.c
@@ -0,0 +1,409 @@
+/*************************************************************************************
+* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file lpuart.c
+ **
+ ** LPUART function driver API.
+ ** @link SampleGroup Some description @endlink
+ **
+ ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module.
+ **
+ ******************************************************************************/
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "lpuart.h"
+/**
+ ******************************************************************************
+ ** \addtogroup LPUartGroup
+ ******************************************************************************/
+//@{
+/******************************************************************************/
+/* Local pre-processor symbols/macros ('#define') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Local function prototypes ('static') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Local variable definitions ('static') */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通信中断使能函数设置
+ **
+ ** \param [in] LPUARTx通道号，enIrqSel发送or接收中断使能
+ **
+ ** \retval OK配置成功
+ **\retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t LPUart_EnableIrq(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_irq_sel_t enIrqSel)
+{
+
+ SetBit((uint32_t)(&(LPUARTx->SCON)), enIrqSel, TRUE);
+
+ return Ok;
+}
+/**
+ ******************************************************************************
+ ** \brief LPUART通信中断禁止函数设置
+ **
+ ** \param [in] LPUARTx通道号，enIrqSel发送or接收中断禁止
+ **
+ ** \retval OK配置成功
+ **\retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t LPUart_DisableIrq(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_irq_sel_t enIrqSel)
+{
+
+ SetBit((uint32_t)(&(LPUARTx->SCON)), enIrqSel, FALSE);
+
+ return Ok;
+}
+/**
+ ******************************************************************************
+ ** \brief lpuart通信时钟源选择
+ **
+ ** \param [in] LPUARTx通道号，enClk 时钟源选项
+ **
+ ** \retval Ok 设置成功
+ **\retval ErrorInvalidParameter设置失败
+ ******************************************************************************/
+en_result_t LPUart_SelSclk(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_sclksel_t enSclk)
+{
+ ASSERT(IS_VALID_CLK(enSclk));
+
+ LPUARTx->SCON_f.SCLKSEL = enSclk;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道多主机模式配置
+ **
+ ** \param [in] LPUARTx通道号，stcMultiCfg多主机模式结构
+ **
+ ** \retval OK配置成功
+ **\retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t LPUart_SetMultiMode(M0P_LPUART_TypeDef* LPUARTx, stc_lpuart_multimode_t* pstcMultiCfg)
+{
+
+ if(NULL != pstcMultiCfg)
+ {
+ LPUARTx->SCON_f.ADRDET = TRUE;
+ LPUARTx->SADDR = pstcMultiCfg->u8SlaveAddr;
+ LPUARTx->SADEN = pstcMultiCfg->u8SaddEn;
+ }
+ else
+ {
+ return ErrorInvalidParameter;
+ }
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART单线半双工模式使能
+ **
+ ** \param [in] LPUARTx 通道号
+ **
+ ** \retval Null
+ ******************************************************************************/
+void LPUart_HdModeEnable(M0P_LPUART_TypeDef* LPUARTx)
+{
+ LPUARTx->SCON_f.HDSEL = TRUE;
+}
+
+
+/**
+ ******************************************************************************
+ ** \brief LPUART单线半双工模式关闭
+ **
+ ** \param [in] LPUARTx 通道号
+ **
+ ** \retval Null
+ ******************************************************************************/
+void LPUart_HdModeDisable(M0P_LPUART_TypeDef* LPUARTx)
+{
+ LPUARTx->SCON_f.HDSEL = FALSE;
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道多机模式发送数据/地址帧配置TB8
+ **
+ ** \param [in] LPUARTx 通道号
+ ** \param [in] TRUE-TB8为地址帧标志；FALSE-TB8为数据帧标志；
+ **
+ ** \retval Null
+ ******************************************************************************/
+void LPUart_SetTb8(M0P_LPUART_TypeDef* LPUARTx, boolean_t bTB8Value)
+{
+ LPUARTx->SCON_f.B8CONT = bTB8Value;
+
+}
+
+/**
+ ******************************************************************************
+ ** \brief 获取RB8数值
+ **
+ ** \param [in] LPUARTx 通道号
+ **
+ ** \retval RB8
+ **\retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+boolean_t LPUart_GetRb8(M0P_LPUART_TypeDef* LPUARTx)
+{
+ return (LPUARTx->SBUF_f.DATA8);
+}
+/**
+ ******************************************************************************
+ ** \brief LPUART通道多主机模式从机地址配置函数
+ **
+ ** \param [in] LPUARTx 通道号，addr地址
+ **
+ ** \retval OK配置成功
+ **\retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t LPUart_SetSaddr(M0P_LPUART_TypeDef* LPUARTx,uint8_t u8Addr)
+{
+ LPUARTx->SADDR = u8Addr;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道发送或接收等功能使能设置
+ **
+ ** \param [in] u8Idx通道号，enFunc功能
+ **
+ ** \retval OK配置成功
+ **\retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t LPUart_EnableFunc(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_func_t enFunc)
+{
+ SetBit((uint32_t)(&(LPUARTx->SCON)), enFunc, TRUE);
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道发送或接收等功能禁止设置
+ **
+ ** \param [in] u8Idx通道号，enFunc功能
+ **
+ ** \retval OK配置成功
+ **\retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t LPUart_DisableFunc(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_func_t enFunc)
+{
+ SetBit((uint32_t)(&(LPUARTx->SCON)), enFunc, FALSE);
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道通信状态获取
+ **
+ ** \param [in] u8Idx通道号
+ **
+ ** \retval 状态值
+ ******************************************************************************/
+uint8_t LPUart_GetIsr(M0P_LPUART_TypeDef* LPUARTx)
+{
+ return (LPUARTx->ISR);
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道通信状态获取
+ **
+ ** \param [in] u8Idx通道号，enStatus获取哪个状态
+ **
+ ** \retval 状态值
+ **\retval ErrorInvalidParameter获取失败
+ ******************************************************************************/
+boolean_t LPUart_GetStatus(M0P_LPUART_TypeDef* LPUARTx,en_lpuart_status_t enStatus)
+{
+ boolean_t bStatus = FALSE;
+
+ ASSERT(IS_VALID_STATUS(enStatus));
+
+ bStatus = GetBit((uint32_t)(&(LPUARTx->ISR)), enStatus);
+
+ return bStatus;
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道通信状态全部清除
+ **
+ ** \param [in] u8Idx通道号
+ **
+ ** \retval OK
+ ******************************************************************************/
+en_result_t LPUart_ClrIsr(M0P_LPUART_TypeDef* LPUARTx)
+{
+ LPUARTx->ICR = 0u;
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道通信状态清除
+ **
+ ** \param [in] u8Idx通道号，enStatus清除哪个状态
+ **
+ ** \retval 状态值
+ **\retval ErrorInvalidParameter清除失败
+ ******************************************************************************/
+en_result_t LPUart_ClrStatus(M0P_LPUART_TypeDef* LPUARTx,en_lpuart_status_t enStatus)
+{
+ ASSERT(IS_VALID_STATUS(enStatus));
+
+ SetBit((uint32_t)(&(LPUARTx->ICR)), enStatus, FALSE);
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道发送数据函数,查询方式调用此函数，中断方式发送不适用
+ **
+ ** \param [in] u8Idx通道号，Data发送数据
+ **
+ ** \retval Ok发送成功
+ **\retval ErrorInvalidParameter发送失败
+ ******************************************************************************/
+en_result_t LPUart_SendData(M0P_LPUART_TypeDef* LPUARTx, uint8_t u8Data)
+{
+ while(FALSE == LPUart_GetStatus(LPUARTx,LPUartTxe))
+ {}
+ LPUARTx->SBUF_f.DATA = u8Data;
+ while(FALSE == LPUart_GetStatus(LPUARTx,LPUartTC))
+ {}
+ LPUart_ClrStatus(LPUARTx,LPUartTC);
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道发送数据函数,中断方式调用此函数
+ **
+ ** \param [in] u8Idx通道号，Data发送数据
+ **
+ ** \retval Ok发送成功
+ **\retval ErrorInvalidParameter发送失败
+ ******************************************************************************/
+en_result_t LPUart_SendDataIt(M0P_LPUART_TypeDef* LPUARTx, uint8_t u8Data)
+{
+ LPUARTx->SBUF_f.DATA = u8Data;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道接收数据函数
+ **
+ ** \param [in] u8Idx通道号
+ **
+ ** \retval 接收数据
+ **\retval ErrorInvalidParameter接收失败
+ ******************************************************************************/
+uint8_t LPUart_ReceiveData(M0P_LPUART_TypeDef* LPUARTx)
+{
+ return (LPUARTx->SBUF_f.DATA);
+}
+
+/**
+ ******************************************************************************
+ ** \brief LPUART通道初始化函数
+ **
+ ** \param [in] u8Idx通道号，pstcCfg初始化结构体 @ref stc_lpuart_cfg_t
+ **
+ ** \retval OK配置成功
+ **\retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t LPUart_Init(M0P_LPUART_TypeDef* LPUARTx,stc_lpuart_cfg_t* pstcCfg)
+{
+ en_result_t enRet = Error;
+ const uint32_t u32Over[3] = {0x4, 0x3, 0x2};
+ uint16_t u16OverShift;
+ float32_t f32Scnt=0;
+
+ if(NULL == pstcCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ LPUARTx->SCON = 0;
+
+ LPUARTx->SCON = (uint32_t)pstcCfg->enStopBit |
+ (uint32_t)pstcCfg->enMmdorCk |
+ (uint32_t)pstcCfg->stcBaud.enSclkDiv |
+ (uint32_t)pstcCfg->stcBaud.enSclkSel |
+ (uint32_t)pstcCfg->enRunMode;
+
+ if((LPUartMskMode1 == pstcCfg->enRunMode) || (LPUartMskMode3 == pstcCfg->enRunMode))
+ {
+ u16OverShift = u32Over[pstcCfg->stcBaud.enSclkDiv/LPUartMsk8Or16Div];
+ f32Scnt = (float32_t)(pstcCfg->stcBaud.u32Sclk)/(float32_t)(pstcCfg->stcBaud.u32Baud<SCNT = (uint16_t)(float32_t)(f32Scnt + 0.5f);
+ LPUart_EnableFunc(LPUARTx,LPUartRenFunc); ///<使能收发
+ }
+
+
+
+ enRet = Ok;
+ return enRet;
+}
+//@} // LPUartGroup
diff --git a/driver/src/lvd.c b/driver/src/lvd.c
new file mode 100644
index 0000000..c41a48a
--- /dev/null
+++ b/driver/src/lvd.c
@@ -0,0 +1,216 @@
+/******************************************************************************
+* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file lvd.c
+ **
+ ** Low Voltage Detect driver API.
+ ** @link Lvd Group Some description @endlink
+ **
+ ** - 2017-06-28 Alex First Version
+ **
+ ******************************************************************************/
+
+/******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "lvd.h"
+
+/**
+ ******************************************************************************
+ ** \addtogroup LvdGroup
+ ******************************************************************************/
+//@{
+
+/******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+#define IS_VALID_INPUT(x) ( (x) <= LvdInputPB07 )
+
+#define IS_VALID_THRESHOLD(x) ( (x) <= LvdTH3p3V )
+
+#define IS_VALID_FILTER(x) ( (x) <= LvdFilter29ms )
+
+#define IS_VALID_IRQTYPE(x) ( (x) <= LvdIrqFall )
+
+
+/******************************************************************************
+ * Global variable definitions (declared in header file with 'extern') *
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+// static void LvdEnableNvic(void);
+// static void LvdDisableNvic(void);
+// static en_result_t LvdEnable(en_lvd_type_t enType, boolean_t bFlag);
+
+/******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*****************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ *****************************************************************************/
+/**
+ * \brief
+ * 使能LVD中断
+ *
+ * \param [in] enType LVD中断类型
+ *
+ * \retval en_result_t Ok: 设置成功
+ * \retval en_result_t ErrorInvalidParameter: 无效类型
+ */
+void Lvd_EnableIrq(void)
+{
+ M0P_LVD->CR_f.IE = TRUE;
+}
+
+/**
+ * \brief
+ * 除能LVD中断
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+void Lvd_DisableIrq(void)
+{
+ M0P_LVD->CR_f.IE = FALSE;
+}
+
+/**
+ * \brief
+ * LVD初始化
+ *
+ * \param [in] pstcCfg LVD配置指针
+ *
+ * \retval 无
+ */
+void Lvd_Init(stc_lvd_cfg_t *pstcCfg)
+{
+ M0P_LVD->CR = 0;
+
+ M0P_LVD->CR = (uint32_t)pstcCfg->enAct |
+ (uint32_t)pstcCfg->enFilter |
+ (uint32_t)pstcCfg->enFilterTime |
+ (uint32_t)pstcCfg->enInputSrc |
+ (uint32_t)pstcCfg->enIrqType |
+ (uint32_t)pstcCfg->enThreshold;
+}
+
+/**
+ * \brief
+ * 使能LVD
+ *
+ * \param 无
+ *
+ * \retval 无
+ *
+ */
+void Lvd_Enable(void)
+{
+ M0P_LVD->CR_f.LVDEN = 1u;
+}
+
+/**
+ * \brief
+ * 除能LVD
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+void Lvd_Disable(void)
+{
+ M0P_LVD->CR_f.LVDEN = 0u;
+}
+
+/**
+ * \brief
+ * 获取LVD中断标志
+ *
+ * \param 无
+ *
+ * \retval boolean_t 中断标志
+ */
+boolean_t Lvd_GetIrqStat(void)
+{
+ return M0P_LVD->IFR_f.INTF;
+
+}
+
+/**
+ * \brief
+ * 清除LVD中断标志
+ *
+ * \param 无
+ *
+ * \retval 无
+ */
+void Lvd_ClearIrq(void)
+{
+ M0P_LVD->IFR_f.INTF = 0u;
+}
+
+/**
+ * \brief
+ * 获取Filter结果
+ *
+ * \param 无
+ *
+ * \retval boolean_t Fliter结果
+ */
+boolean_t Lvd_GetFilterResult(void)
+{
+ return (boolean_t)M0P_LVD->IFR_f.FILTER;
+}
+//@} // LvdGroup
+
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
diff --git a/driver/src/opa.c b/driver/src/opa.c
new file mode 100644
index 0000000..142db0a
--- /dev/null
+++ b/driver/src/opa.c
@@ -0,0 +1,153 @@
+/******************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file opa.c
+ **
+ ** opa driver API.
+ ** @link opa Group Some description @endlink
+ **
+ ** - 2019-04-11 First Version
+ **
+ ******************************************************************************/
+
+/******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "opa.h"
+
+/**
+ ******************************************************************************
+ ** \addtogroup OPAGroup
+ ******************************************************************************/
+//@{
+
+/******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+
+/******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+
+/******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*****************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ *****************************************************************************/
+
+/**
+******************************************************************************
+ ** \brief OPA 通道使能
+ **
+ ** \param NewStatus : TRUE FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Opa_Cmd(boolean_t NewStatus)
+{
+ SetBit((uint32_t)(&(M0P_OPA->CR0)), 0, NewStatus);
+}
+
+void Opa_CmdBuf(boolean_t NewStatus)
+{
+ SetBit((uint32_t)(&(M0P_OPA->CR0)), 2, NewStatus);
+}
+
+/**
+******************************************************************************
+ ** \brief OPA零点校准配置
+ **
+ ** \param InitZero :
+ ** \retval 无
+ **
+******************************************************************************/
+void Opa_SetZero(stc_opa_zcfg_t* InitZero)
+{
+ M0P_OPA->CR0_f.AZEN = InitZero->bAzen;
+ M0P_OPA->CR1_f.CLK_SW_SET = InitZero->bClk_sw_set;
+ M0P_OPA->CR1_f.AZ_PULSE = InitZero->bAz_pulse;
+ M0P_OPA->CR1_f.TRIGGER = InitZero->bTrigger;
+ M0P_OPA->CR1_f.ADCTR_EN = InitZero->bAdctr_en;
+}
+
+/**
+******************************************************************************
+ ** \brief 使能输出OUTX
+ **
+ ** \param onex : en_opa_oenx_t定义的元素
+ ** \retval 无
+ **
+******************************************************************************/
+void Opa_CmdOnex(en_opa_oenx_t onex, boolean_t NewState)
+{
+ SetBit((uint32_t)(&(M0P_OPA->CR0)), onex, NewState); //使能OP3输出X使能
+}
+
+/**
+******************************************************************************
+ ** \brief 配置校零相关的位
+ **
+ ** \param CtrlBit : en_opa_set0ctrl_t定义的元素
+ ** \param NewState: TRUE 或 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Opa_ZeroBitCtrl(en_opa_set0ctrl_t CtrlBit, boolean_t NewState)
+{
+ SetBit((uint32_t)(&(M0P_OPA->CR1)), CtrlBit, NewState);
+}
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
diff --git a/driver/src/pca.c b/driver/src/pca.c
new file mode 100644
index 0000000..39de82d
--- /dev/null
+++ b/driver/src/pca.c
@@ -0,0 +1,555 @@
+/******************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file pca.c
+ **
+ ** pca driver API.
+ ** @link pcnt Group Some description @endlink
+ **
+ ** - 2019-04-09 First Version
+ **
+ ******************************************************************************/
+
+/******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "pca.h"
+
+/**
+ ******************************************************************************
+ ** \addtogroup PCNTGroup
+ ******************************************************************************/
+//@{
+
+/******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+
+/******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/**
+******************************************************************************
+ ** \brief 获取中断源的标志位
+ ** @param IT_Src : 中断源标志位
+ ** \retval FALSE 或TRUE
+ **
+******************************************************************************/
+boolean_t Pca_GetItStatus(en_pca_ccficlr_t It_Src)
+{
+ return (((M0P_PCA->CCON)>>It_Src) & 1) > 0? TRUE : FALSE;
+}
+
+/**
+******************************************************************************
+ ** \brief 清除中断源的标志位
+ ** @param IT_Src : 中断源标志位
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_ClrItStatus(en_pca_ccficlr_t It_Src)
+{
+ M0P_PCA->ICLR &= ~(uint32_t)(1<CCON)), 6, NewStatus);
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 空闲模式IDLE下，PCA是否停止工作设置
+ ** @param NewStatus : TRUE 或 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_SetCidl(boolean_t NewStatus)
+{
+ SetBit((uint32_t)(&(M0P_PCA->CMOD)), 7, NewStatus);
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 模块4的看门狗使能控制
+ ** @param NewStatus : TRUE 或 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_Set4Wdte(boolean_t NewStatus)
+{
+ SetBit((uint32_t)(&(M0P_PCA->CMOD)), 6, NewStatus);
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 计数器中断控制PCA_CMOD中CFIE，对应的控制中断位PCA_CCON中的CF与PCA_ICLR中的CF
+ ** @param NewStatus : TRUE 或 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_ConfPcaIt(boolean_t NewStatus)
+{
+ SetBit((uint32_t)(&(M0P_PCA->CMOD)), 0, NewStatus);
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 比较捕获中断使能控制 PCA_CCAPMx的CCIE
+ ** @param Modulex : pca_module0~4
+ ** @param NewStatus : TRUE 或 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_ConfModulexIt(en_pca_module_t Modulex, boolean_t NewStatus)
+{
+ switch(Modulex)
+ {
+ case PcaModule0:
+ SetBit((uint32_t)(&(M0P_PCA->CCAPM0)), 0, NewStatus);
+ break;
+ case PcaModule1:
+ SetBit((uint32_t)(&(M0P_PCA->CCAPM1)), 0, NewStatus);
+ break;
+ case PcaModule2:
+ SetBit((uint32_t)(&(M0P_PCA->CCAPM2)), 0, NewStatus);
+ break;
+ case PcaModule3:
+ SetBit((uint32_t)(&(M0P_PCA->CCAPM3)), 0, NewStatus);
+ break;
+ case PcaModule4:
+ SetBit((uint32_t)(&(M0P_PCA->CCAPM4)), 0, NewStatus);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 模块0的初始化
+ ** @param InitStruct : PCA初始化配置的结构体
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_M0Init(stc_pcacfg_t* InitStruct)
+{
+ M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc;
+ M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl;
+ M0P_PCA->CCAPM0_f.ECOM = InitStruct->pca_ecom;
+ M0P_PCA->CCAPM0_f.CAPP = InitStruct->pca_capp;
+ M0P_PCA->CCAPM0_f.CAPN = InitStruct->pca_capn;
+ M0P_PCA->CCAPM0_f.MAT = InitStruct->pca_mat;
+ M0P_PCA->CCAPM0_f.TOG = InitStruct->pca_tog;
+ M0P_PCA->CCAPM0_f.PWM = InitStruct->pca_pwm;
+ M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm;
+ if(InitStruct->pca_pwm == PcaPwm8bitEnable)
+ {
+ M0P_PCA->CCAP0L_f.CCAP0 = InitStruct->pca_ccapl;
+ M0P_PCA->CCAP0H_f.CCAP0 = InitStruct->pca_ccaph;
+ }
+ else
+ {
+ M0P_PCA->CCAP0_f.CCAP0 = InitStruct->pca_ccap;
+ }
+ M0P_PCA->CARR_f.CARR = InitStruct->pca_carr;
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 模块1的初始化
+ ** @param InitStruct : PCA初始化配置的结构体
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_M1Init(stc_pcacfg_t* InitStruct)
+{
+ M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc;
+ M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl;
+ M0P_PCA->CCAPM1_f.ECOM = InitStruct->pca_ecom;
+ M0P_PCA->CCAPM1_f.CAPP = InitStruct->pca_capp;
+ M0P_PCA->CCAPM1_f.CAPN = InitStruct->pca_capn;
+ M0P_PCA->CCAPM1_f.MAT = InitStruct->pca_mat;
+ M0P_PCA->CCAPM1_f.TOG = InitStruct->pca_tog;
+ M0P_PCA->CCAPM1_f.PWM = InitStruct->pca_pwm;
+ M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm;
+ if(InitStruct->pca_pwm == PcaPwm8bitEnable)
+ {
+ M0P_PCA->CCAP1L_f.CCAP1 = InitStruct->pca_ccapl;
+ M0P_PCA->CCAP1H_f.CCAP1 = InitStruct->pca_ccaph;
+ }
+ else
+ {
+ M0P_PCA->CCAP1_f.CCAP1 = InitStruct->pca_ccap;
+ }
+ M0P_PCA->CARR_f.CARR = InitStruct->pca_carr;
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 模块2的初始化
+ ** @param InitStruct : PCA初始化配置的结构体
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_M2Init(stc_pcacfg_t* InitStruct)
+{
+ M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc;
+ M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl;
+ M0P_PCA->CCAPM2_f.ECOM = InitStruct->pca_ecom;
+ M0P_PCA->CCAPM2_f.CAPP = InitStruct->pca_capp;
+ M0P_PCA->CCAPM2_f.CAPN = InitStruct->pca_capn;
+ M0P_PCA->CCAPM2_f.MAT = InitStruct->pca_mat;
+ M0P_PCA->CCAPM2_f.TOG = InitStruct->pca_tog;
+ M0P_PCA->CCAPM2_f.PWM = InitStruct->pca_pwm;
+ M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm;
+ if(InitStruct->pca_pwm == PcaPwm8bitEnable)
+ {
+ M0P_PCA->CCAP2L_f.CCAP2 = InitStruct->pca_ccapl;
+ M0P_PCA->CCAP2H_f.CCAP2 = InitStruct->pca_ccaph;
+ }
+ else
+ {
+ M0P_PCA->CCAP2_f.CCAP2 = InitStruct->pca_ccap;
+ }
+ M0P_PCA->CARR_f.CARR = InitStruct->pca_carr;
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 模块3的初始化
+ ** @param InitStruct : PCA初始化配置的结构体
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_M3Init(stc_pcacfg_t* InitStruct)
+{
+ M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc;
+ M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl;
+ M0P_PCA->CCAPM3_f.ECOM = InitStruct->pca_ecom;
+ M0P_PCA->CCAPM3_f.CAPP = InitStruct->pca_capp;
+ M0P_PCA->CCAPM3_f.CAPN = InitStruct->pca_capn;
+ M0P_PCA->CCAPM3_f.MAT = InitStruct->pca_mat;
+ M0P_PCA->CCAPM3_f.TOG = InitStruct->pca_tog;
+ M0P_PCA->CCAPM3_f.PWM = InitStruct->pca_pwm;
+ M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm;
+ if(InitStruct->pca_pwm == PcaPwm8bitEnable)
+ {
+ M0P_PCA->CCAP3L_f.CCAP3 = InitStruct->pca_ccapl;
+ M0P_PCA->CCAP3H_f.CCAP3 = InitStruct->pca_ccaph;
+ }
+ else
+ {
+ M0P_PCA->CCAP3_f.CCAP3 = InitStruct->pca_ccap;
+ }
+ M0P_PCA->CARR_f.CARR = InitStruct->pca_carr;
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 模块4的初始化
+ ** @param InitStruct : PCA初始化配置的结构体
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_M4Init(stc_pcacfg_t* InitStruct)
+{
+ M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc;
+ M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl;
+ M0P_PCA->CCAPM4_f.ECOM = InitStruct->pca_ecom;
+ M0P_PCA->CCAPM4_f.CAPP = InitStruct->pca_capp;
+ M0P_PCA->CCAPM4_f.CAPN = InitStruct->pca_capn;
+ M0P_PCA->CCAPM4_f.MAT = InitStruct->pca_mat;
+ M0P_PCA->CCAPM4_f.TOG = InitStruct->pca_tog;
+ M0P_PCA->CCAPM4_f.PWM = InitStruct->pca_pwm;
+ M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm;
+ if(InitStruct->pca_pwm == PcaPwm8bitEnable)
+ {
+ M0P_PCA->CCAP4L_f.CCAP4 = InitStruct->pca_ccapl;
+ M0P_PCA->CCAP4H_f.CCAP4 = InitStruct->pca_ccaph;
+ }
+ else
+ {
+ M0P_PCA->CCAP4_f.CCAP4 = InitStruct->pca_ccap;
+ }
+ M0P_PCA->CARR_f.CARR = InitStruct->pca_carr;
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 读取CNT寄存器的数值
+ ** @param 无
+ ** \retval CNT的低半字值
+ **
+******************************************************************************/
+uint16_t Pca_GetCnt(void)
+{
+ return (uint16_t)(M0P_PCA->CNT);
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 向CNT寄存器写入数值
+ ** @param cnt : 所要写入的数值
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_SetCnt(uint16_t cnt)
+{
+ if(GetBit((uint32_t)(&(M0P_PCA->CCON)), 6)==TRUE)
+ {
+ Pca_StartPca(FALSE);
+ M0P_PCA->CNT_f.CNT = cnt;
+ Pca_StartPca(TRUE);
+ }
+ else
+ {
+ M0P_PCA->CNT_f.CNT = cnt;
+ }
+
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 返回指定通道比较高速输出标志寄存器的值
+ ** @param Modulex : 通道号x=0、1、2、3、4
+ ** \retval TRUE 或 FALSE
+ **
+******************************************************************************/
+boolean_t Pca_GetOut(en_pca_module_t Modulex)
+{
+ return GetBit((uint32_t)(&(M0P_PCA->CCAPO)), Modulex);
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 设置比较捕获16位寄存器CCAPx数值
+ ** @param Modulex : 通道号x=0、1、2、3、4
+ ** @param Value: 所要设置的值
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_SetCcap(en_pca_module_t Modulex, uint16_t Value)
+{
+ switch(Modulex)
+ {
+ case 0:
+ M0P_PCA->CCAP0_f.CCAP0 = Value;
+ break;
+ case 1:
+ M0P_PCA->CCAP1_f.CCAP1 = Value;
+ break;
+ case 2:
+ M0P_PCA->CCAP2_f.CCAP2 = Value;
+ break;
+ case 3:
+ M0P_PCA->CCAP3_f.CCAP3 = Value;
+ break;
+ case 4:
+ M0P_PCA->CCAP4_f.CCAP4 = Value;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 读取比较捕获16位寄存器CCAPx数值
+ ** @param Modulex : 通道号x=0、1、2、3、4
+ ** \retval CCAPx的值，x=0、1、2、3、4
+ **
+******************************************************************************/
+uint16_t Pca_GetCcap(en_pca_module_t Modulex)
+{
+ uint16_t tmp;
+ switch(Modulex)
+ {
+ case 0:
+ tmp = M0P_PCA->CCAP0_f.CCAP0;
+ break;
+ case 1:
+ tmp = M0P_PCA->CCAP1_f.CCAP1;
+ break;
+ case 2:
+ tmp = M0P_PCA->CCAP2_f.CCAP2;
+ break;
+ case 3:
+ tmp = M0P_PCA->CCAP3_f.CCAP3;
+ break;
+ case 4:
+ tmp = M0P_PCA->CCAP4_f.CCAP4;
+ break;
+ default:
+ break;
+ }
+ return tmp;
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 设置自动重装载寄存器数值
+ ** @param 无
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_SetCarr(uint16_t Value)
+{
+ M0P_PCA->CARR_f.CARR = Value;
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 获取自动重装载寄存器数值
+ ** @param 无
+ ** \retval 无
+ **
+******************************************************************************/
+uint16_t Pca_GetCarr(void)
+{
+ return M0P_PCA->CARR_f.CARR;
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 设置比较捕获寄存器的高8位和低8位
+ ** @param Modulex : 通道号x=0、1、2、3、4
+ ** @param ValueH : 要写入高8位的数值
+ ** @param ValueL : 要写入低8位的数值
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_SetCcapHL(en_pca_module_t Modulex, uint8_t ValueH, uint8_t ValueL)
+{
+ switch(Modulex)
+ {
+ case 0:
+ M0P_PCA->CCAP0H_f.CCAP0 = ValueH;
+ M0P_PCA->CCAP0L_f.CCAP0 = ValueL;
+ break;
+ case 1:
+ M0P_PCA->CCAP1H_f.CCAP1 = ValueH;
+ M0P_PCA->CCAP1L_f.CCAP1 = ValueL;
+ break;
+ case 2:
+ M0P_PCA->CCAP2H_f.CCAP2 = ValueH;
+ M0P_PCA->CCAP2L_f.CCAP2 = ValueL;
+ break;
+ case 3:
+ M0P_PCA->CCAP3H_f.CCAP3 = ValueH;
+ M0P_PCA->CCAP3L_f.CCAP3 = ValueL;
+ break;
+ case 4:
+ M0P_PCA->CCAP4H_f.CCAP4 = ValueH;
+ M0P_PCA->CCAP4L_f.CCAP4 = ValueL;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+******************************************************************************
+ ** \brief PCA 读取比较捕获寄存器的高8位和低8位
+ ** @param Modulex : 通道号x=0、1、2、3、4
+ ** @param ValueH : CCAPx高8位的数值
+ ** @param ValueL : CCAPx低8位的数值
+ ** \retval 无
+ **
+******************************************************************************/
+void Pca_GetCcapHL(en_pca_module_t Modulex, uint8_t *ValueH, uint8_t *ValueL)
+{
+ switch(Modulex)
+ {
+ case 0:
+ *ValueH = M0P_PCA->CCAP0H_f.CCAP0;
+ *ValueL = M0P_PCA->CCAP0L_f.CCAP0;
+ break;
+ case 1:
+ *ValueH = M0P_PCA->CCAP1H_f.CCAP1;
+ *ValueL = M0P_PCA->CCAP1L_f.CCAP1;
+ break;
+ case 2:
+ *ValueH = M0P_PCA->CCAP2H_f.CCAP2;
+ *ValueL = M0P_PCA->CCAP2L_f.CCAP2;
+ break;
+ case 3:
+ *ValueH = M0P_PCA->CCAP3H_f.CCAP3;
+ *ValueL = M0P_PCA->CCAP3L_f.CCAP3;
+ break;
+ case 4:
+ *ValueH = M0P_PCA->CCAP4H_f.CCAP4;
+ *ValueL = M0P_PCA->CCAP4L_f.CCAP4;
+ break;
+ default:
+ break;
+ }
+}
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
+
+
+
+
diff --git a/driver/src/pcnt.c b/driver/src/pcnt.c
new file mode 100644
index 0000000..cdcf160
--- /dev/null
+++ b/driver/src/pcnt.c
@@ -0,0 +1,316 @@
+/******************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file pcnt.c
+ **
+ ** pcnt driver API.
+ ** @link pcnt Group Some description @endlink
+ **
+ ** - 2019-04-08 First Version
+ **
+ ******************************************************************************/
+
+/******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "pcnt.h"
+
+/**
+ ******************************************************************************
+ ** \addtogroup PCNTGroup
+ ******************************************************************************/
+//@{
+
+/******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+
+/******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+
+/**
+******************************************************************************
+ ** \brief PCNT的启动和停止控制
+ ** @param NewState : Run_Enable 或者 Run_Disable
+ ** @param NewState : FALSE或者TRUE
+ ** \retval 无
+ **
+******************************************************************************/
+boolean_t Pcnt_Cmd(boolean_t NewState)
+{
+ SetBit((uint32_t)(&(M0P_PCNT->RUN)), 0, NewState);
+ return GetBit((uint32_t)(&(M0P_PCNT->RUN)), 0);
+}
+
+
+/**
+******************************************************************************
+ ** \brief 将BUF中的值同步到CNT
+ ** @param value : 要同步到TOP的数值
+ ** \retval ok 或 ErrorTimeout
+ **
+******************************************************************************/
+en_result_t Pcnt_SetB2T(uint16_t value)
+{
+ uint16_t u16TimeOut;
+
+ u16TimeOut = 1000;
+ M0P_PCNT->BUF = value;
+ M0P_PCNT->CMD_f.B2T = 1;
+
+ while(u16TimeOut--)
+ {
+ if(M0P_PCNT->SR2_f.B2T == FALSE)
+ {
+ break;
+ }
+ }
+ if(u16TimeOut == 0)
+ {
+ return ErrorTimeout;
+ }
+ return Ok;
+}
+
+/**
+******************************************************************************
+ ** \brief 将BUF中的值同步到CNT
+ ** @param value : 要同步到CNT的数值
+ ** \retval ok 或 ErrorTimeout
+ **
+******************************************************************************/
+en_result_t Pcnt_SetB2C(uint16_t value)
+{
+ uint16_t u16TimeOut;
+ u16TimeOut = 1000;
+ M0P_PCNT->BUF = value;
+ M0P_PCNT->CMD_f.B2C = 1;
+
+ while(u16TimeOut--)
+ {
+ if(M0P_PCNT->SR2_f.B2C == FALSE)
+ {
+ break;
+ }
+ }
+ if(u16TimeOut == 0)
+ {
+ return ErrorTimeout;
+ }
+ return Ok;
+}
+
+/**
+******************************************************************************
+ ** \brief 将TOP中的值同步到CNT
+ ** @param value : 要同步到CNT的数值
+ ** \retval ok 或 ErrorTimeout
+ **
+******************************************************************************/
+en_result_t Pcnt_SetT2C(void)
+{
+ uint16_t u16TimeOut;
+ u16TimeOut = 1000;
+ M0P_PCNT->CMD_f.T2C = 1;
+ while(u16TimeOut--)
+ {
+ if(M0P_PCNT->SR2_f.T2C == FALSE)
+ {
+ break;
+ }
+ }
+ if(u16TimeOut == 0)
+ {
+ return ErrorTimeout;
+ }
+ return Ok;
+}
+
+
+/**
+******************************************************************************
+ ** \brief 赋值BUF
+ ** @param value : 要赋值给BUF的数值
+ ** \retval 无
+ **
+******************************************************************************/
+void Pcnt_SetBuf(uint16_t value)
+{
+ M0P_PCNT->TOP_f.TOP = value;
+}
+
+/**
+******************************************************************************
+ ** \brief 初始化
+ ** @param start : 要同步到TOP的数值
+ ** @param end : 要同步到CNT的数值
+ ** \retval ok 或 ErrorTimeout
+ **
+******************************************************************************/
+void Pcnt_Init(stc_pcnt_initstruct_t* InitStruct)
+{
+ M0P_PCNT->CTRL_f.S1P = InitStruct->Pcnt_S1Sel;
+ M0P_PCNT->CTRL_f.S0P = InitStruct->Pcnt_S0Sel;
+ M0P_PCNT->CTRL_f.CLKSEL = InitStruct->Pcnt_Clk;
+ M0P_PCNT->CTRL_f.MODE = InitStruct->Pcnt_Mode;
+ if(InitStruct->Pcnt_Mode == PcntDoubleMode)//如果是双通道正交脉冲计数模式
+ {
+ M0P_PCNT->SR1_f.DIR = InitStruct->Pcnt_Dir;
+ }
+ else
+ {
+ M0P_PCNT->CTRL_f.DIR = InitStruct->Pcnt_Dir;
+ }
+ M0P_PCNT->FLT_f.EN = InitStruct->Pcnt_FltEn;
+ M0P_PCNT->FLT_f.DEBTOP = InitStruct->Pcnt_DebTop;
+ M0P_PCNT->FLT_f.CLKDIV = InitStruct->Pcnt_ClkDiv;
+ M0P_PCNT->TOCR_f.EN = InitStruct->Pcnt_TocrEn;
+ M0P_PCNT->TOCR_f.TH = InitStruct->Pcnt_TocrTh;
+
+ M0P_PCNT->DBG_f.DBG = InitStruct->Pcnt_Dbg;
+}
+
+/**
+******************************************************************************
+ ** \brief 配置中断源的使能
+ ** @param IT_Src : 中断源再PCNT_IEN内部的位位置
+ ** @param NewState : FALSE 或TRUE
+ ** \retval 无
+ **
+******************************************************************************/
+void Pcnt_ItCfg(en_pcnt_itfce_t IT_Src, boolean_t NewState)
+{
+ if(NewState == TRUE)
+ {
+ M0P_PCNT->IEN |= (uint32_t)(1<IEN &= ~(uint32_t)(1<IFR >> IT_Src) & 1u) > 0 ? TRUE : FALSE;
+}
+
+/**
+******************************************************************************
+ ** \brief 清除中断源的标志位
+ ** @param IT_Src : 中断源标志位
+ ** \retval 无
+ **
+******************************************************************************/
+void Pcnt_ClrItStatus(en_pcnt_itfce_t IT_Src)
+{
+ M0P_PCNT->ICR &= ~(uint32_t)(1<<(uint32_t)IT_Src);
+}
+
+
+/**
+******************************************************************************
+ ** \brief 获取PCNT_CNT寄存器的数值
+ ** @param 无
+ ** \retval PCNT_CNT数值
+ **
+******************************************************************************/
+uint16_t Pcnt_GetCnt(void)
+{
+ return (uint16_t)(M0P_PCNT->CNT);
+}
+
+/**
+******************************************************************************
+ ** \brief 获取PCNT_TOP寄存器的数值
+ ** @param 无
+ ** \retval PCNT_TOP数值
+ **
+******************************************************************************/
+uint16_t Pcnt_GetTop(void)
+{
+ return (uint16_t)(M0P_PCNT->TOP);
+}
+
+/**
+******************************************************************************
+ ** \brief 获取PCNT_BUF寄存器的数值
+ ** @param 无
+ ** \retval PCNT_BUF数值
+ **
+******************************************************************************/
+uint16_t Pcnt_GetBuf(void)
+{
+ return (uint16_t)(M0P_PCNT->BUF);
+}
+
+//@} // Group
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
diff --git a/driver/src/ram.c b/driver/src/ram.c
new file mode 100644
index 0000000..44081b6
--- /dev/null
+++ b/driver/src/ram.c
@@ -0,0 +1,156 @@
+/******************************************************************************
+*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file ram.c
+ **
+ ** Common API of ram.
+ ** @link RamGroup Some description @endlink
+ **
+ ** - 2018-05-08
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "ram.h"
+/**
+ *******************************************************************************
+ ** \addtogroup ramGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *****************************************************************************
+ ** \brief Ram奇偶校验出错地址获取
+ **
+ **
+ ** \retval ERROR ADDRESS
+ *****************************************************************************/
+uint32_t Ram_ErrAddrGet(void)
+{
+ return M0P_RAM->ERRADDR;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Ram中断标志获取
+ **
+ **
+ ** \retval TRUE or FALSE
+ *****************************************************************************/
+boolean_t Ram_GetIntFlag(void)
+{
+ if(M0P_RAM->IFR & 0x1)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+}
+
+/**
+ *****************************************************************************
+ ** \brief Ram中断标志清除
+ **
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Ram_ClearIntFlag(void)
+{
+ M0P_RAM->ICLR = 0u;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Ram中断使能
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Ram_EnableIrq (void)
+{
+ M0P_RAM->CR |= 0x2u;
+}
+
+/**
+ *****************************************************************************
+ ** \brief ram中断禁止
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Ram_DisableIrq(void)
+{
+ M0P_RAM->CR &= 0x1;
+}
+
+
+//@} // RamGroup
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/reset.c b/driver/src/reset.c
new file mode 100644
index 0000000..41d0321
--- /dev/null
+++ b/driver/src/reset.c
@@ -0,0 +1,184 @@
+/******************************************************************************
+*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file reset.c
+ **
+ ** Common API of reset.
+ ** @link resetGroup Some description @endlink
+ **
+ ** - 2017-05-04
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "reset.h"
+
+/**
+ *******************************************************************************
+ ** \addtogroup ResetGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *******************************************************************************
+ ** \brief 获取复位源类型.
+ **
+ ** \param [out] enRstFlg @ref en_reset_flag_t
+ **
+ ** \retval TRUE or FALSE
+ ******************************************************************************/
+boolean_t Reset_GetFlag(en_reset_flag_t enRstFlg)
+{
+ if(M0P_RESET->RESET_FLAG&enRstFlg)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+}
+
+/**
+ *******************************************************************************
+ ** \brief 清除复位源类型.
+ **
+ ** \param [in] pstcFlag @ref en_reset_flag_t
+ **
+ ** \retval Null
+ ******************************************************************************/
+void Reset_ClearFlag(en_reset_flag_t enRstFlg)
+{
+ M0P_RESET->RESET_FLAG &= ~(uint32_t)enRstFlg;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 清除所有复位源类型.
+ **
+ ** \param Null
+ **
+ ** \retval Null
+ ******************************************************************************/
+void Reset_ClearFlagAll(void)
+{
+ M0P_RESET->RESET_FLAG = 0;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 所有模块进行一次复位.
+ **
+ **
+ ** \retval Null
+ ******************************************************************************/
+void Reset_RstPeripheralAll(void)
+{
+ M0P_RESET->PERI_RESET0 = 0u;
+ M0P_RESET->PERI_RESET0 = 0xFFFFFFFFu;
+ M0P_RESET->PERI_RESET1 = 0u;
+ M0P_RESET->PERI_RESET1 = 0xFFFFFFFFu;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 对外设源0模块进行一次复位.
+ **
+ ** \param [in] enPeri @ref en_reset_peripheral0_t
+ **
+ ** \retval Null
+ ******************************************************************************/
+void Reset_RstPeripheral0(en_reset_peripheral0_t enPeri)
+{
+ M0P_RESET->PERI_RESET0 &= ~(uint32_t)enPeri;
+ M0P_RESET->PERI_RESET0 |= (uint32_t)enPeri;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 对外设源1模块进行一次复位.
+ **
+ ** \param [in] enPeri @ref en_reset_peripheral1_t
+ **
+ ** \retval Null
+ ******************************************************************************/
+void Reset_RstPeripheral1(en_reset_peripheral1_t enPeri)
+{
+ M0P_RESET->PERI_RESET1 &= ~(uint32_t)enPeri;
+ M0P_RESET->PERI_RESET1 |= (uint32_t)enPeri;
+}
+
+//@} // ResetGroup
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
+
diff --git a/driver/src/rtc.c b/driver/src/rtc.c
new file mode 100644
index 0000000..6d25249
--- /dev/null
+++ b/driver/src/rtc.c
@@ -0,0 +1,520 @@
+/*************************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file rtc.c
+ **
+ ** RTC function driver API.
+ ** @link SampleGroup Some description @endlink
+ **
+ ** - 2019-04-10 First version
+ **
+ ******************************************************************************/
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "rtc.h"
+/**
+ ******************************************************************************
+ ** \addtogroup RtcGroup
+ ******************************************************************************/
+//@{
+
+/******************************************************************************/
+/* Local pre-processor symbols/macros ('#define') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Local function prototypes ('const') */
+/******************************************************************************/
+const uint8_t Leap_Month_Base[] = {3,6,0,3,5,1,3,6,2,4,0,2};
+const uint8_t NonLeap_Month_Base[] = {4,0,0,3,5,1,3,6,2,4,0,2};
+const uint8_t Cnst_Month_Tbl[12]={0x31,0x28,0x31,0x30,0x31,0x30,0x31,0x31,0x30,0x31,0x30,0x31};
+/******************************************************************************/
+/* Local function prototypes ('static') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Local variable prototypes ('static') */
+/******************************************************************************/
+
+/*****************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ *****************************************************************************/
+
+/**
+******************************************************************************
+ ** \brief RTC计数器的使能或停止
+ **
+ ** @param NewState : TRUE 或 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Rtc_Cmd(boolean_t NewState)
+{
+ SetBit((uint32_t)(&(M0P_RTC->CR0)), 7, NewState);
+}
+
+/**
+******************************************************************************
+ ** \brief RTC计数器启动等待函数，如启动RTC计数器后立即进入低功耗模式，
+ ** 进入低功耗模式之前需执行此函数，以确保RTC已启动完成
+ **
+ ** @param NewState : TRUE 或 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Rtc_StartWait(void)
+{
+ M0P_RTC->CR1_f.WAIT = 1;
+ while (M0P_RTC->CR1_f.WAITF != 1) //等待直到WAITF=1
+ {
+ ;
+ }
+ M0P_RTC->CR1_f.WAIT = 0;
+ while (M0P_RTC->CR1_f.WAITF != 0) //等待直到WAITF=0
+ {
+ ;
+ }
+}
+
+/**
+******************************************************************************
+ ** \brief RTC的1Hz输出的使能或停止
+ ** @param pricision : RtcHz1selGeneralPricision 或 RtcHz1selHighPricision
+ ** @param NewState : Hz1o_Disable 或 HZ1o_Enable
+ ** \retval 无
+ **
+******************************************************************************/
+void Rtc_Hz1Cmd(en_rtc_hz1sel_t pricision, boolean_t NewState)
+{
+ SetBit((uint32_t)(&(M0P_RTC->CR0)), 6, pricision); //设置普通精度或者高精度1Hz输出
+ SetBit((uint32_t)(&(M0P_RTC->CR0)), 5, NewState); //设置1Hz输出使能或禁止
+}
+
+/**
+******************************************************************************
+ ** \brief 设置周期中断的类型(PRDSEL)及其所选类型的时间(PRDS或PRDX)
+ **
+ ** @param pstCyc: 根据结构体的定义设置PRDSEL、PRDS与PRDX
+ ** \retval Ok、Error 或 ErrorInvalidParameter
+ **
+******************************************************************************/
+en_result_t Rtc_SetCyc(stc_rtc_cyccfg_t* pstCyc)
+{
+ en_result_t enRet = Error;
+ M0P_RTC->CR0_f.PRDSEL = pstCyc->rtcPrdsel;
+ if(pstCyc->rtcPrdsel == RtcPrds)
+ {
+ M0P_RTC->CR0_f.PRDS = pstCyc->rtcPrds;
+ }
+ else if(pstCyc->rtcPrdsel == RtcPrdx)
+ {
+ if(pstCyc->rtcPrdx>=64)
+ {
+ enRet = ErrorInvalidParameter;
+ return enRet;
+ }
+ M0P_RTC->CR0_f.PRDX = pstCyc->rtcPrdx;
+ }
+ else
+ {
+ ;
+ }
+ enRet = Ok;
+ return enRet;
+}
+
+/**
+******************************************************************************
+ ** \brief RTC闹钟中断的使能或停止
+ **
+ ** @param NewState : TRUE 或 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Rtc_AlmIeCmd(boolean_t NewState)
+{
+ SetBit((uint32_t)(&(M0P_RTC->CR1)), 3, 0); //清除周期中断标志位
+ SetBit((uint32_t)(&(M0P_RTC->CR1)), 4, 0); //清除周期中断标志位
+ SetBit((uint32_t)(&(M0P_RTC->CR1)), 6, NewState);
+}
+
+/**
+******************************************************************************
+ ** \brief RTC闹钟的使能或停止
+ **
+ ** @param NewState : Almen_Disable 或 Almen_Enable
+ ** \retval 无
+ **
+******************************************************************************/
+void Rtc_AlmEnCmd(boolean_t NewState)
+{
+ SetBit((uint32_t)(&(M0P_RTC->CR1)), 7, NewState);
+}
+
+/**
+******************************************************************************
+ ** \brief 获取RTC闹钟中断状态位
+ **
+ ** @param 无
+ ** \retval TRUE 或 FALSE
+ **
+******************************************************************************/
+boolean_t Rtc_GetAlmfItStatus(void)
+{
+ return GetBit((uint32_t)(&(M0P_RTC->CR1)), 4);
+}
+
+/**
+******************************************************************************
+ ** \brief 清除RTC闹钟中断状态位
+ **
+ ** @param 无
+ ** \retval 无
+ **
+******************************************************************************/
+void Rtc_ClearAlmfItStatus(void)
+{
+ SetBit((uint32_t)(&(M0P_RTC->CR1)), 4, 0);
+}
+
+/**
+******************************************************************************
+ ** \brief 清除RTC周期中断状态位
+ **
+ ** @param 无
+ ** \retval 无
+ **
+******************************************************************************/
+void Rtc_ClearPrdfItStatus(void)
+{
+ SetBit((uint32_t)(&(M0P_RTC->CR1)), 3, 0);
+}
+
+/**
+******************************************************************************
+ ** \brief 获取RTC周期中断状态位
+ **
+ ** @param 无
+ ** \retval TRUE 或 FALSE
+ **
+******************************************************************************/
+boolean_t Rtc_GetPridItStatus(void)
+{
+ return GetBit((uint32_t)(&(M0P_RTC->CR1)), 3);
+}
+
+/**
+******************************************************************************
+ ** \brief 配置RTC的误差补偿寄存器
+ **
+ ** @param CompValue:数值的范围为：32-256
+ ** @param NewStatus: RtcCompenDisable 或 RtcAmCompenEnable
+ ** \retval Ok ErrorInvalidParameter
+ **
+******************************************************************************/
+en_result_t Rtc_CompCfg(uint16_t CompVlue, en_rtc_compen_t NewStatus)
+{
+ en_result_t enRet = Error;
+ if(CompVlue<=256)
+ {
+ M0P_RTC->COMPEN_f.EN = NewStatus;
+ M0P_RTC->COMPEN_f.CR = CompVlue;
+ }
+ else
+ {
+ enRet = ErrorInvalidParameter;
+ }
+ return enRet;
+}
+
+/**
+ ******************************************************************************
+ ** \brief RTC根据日期计算周数
+ **
+ ** \param pu8buf时间数据
+ ** \param u8limit_min最小值
+ ** \param u8limit_max最大值
+ **
+ ** \retval Error 错误，Ok校验正确
+ **
+ ******************************************************************************/
+en_result_t Check_BCD_Format(uint8_t u8data,uint8_t u8limit_min, uint8_t u8limit_max)
+{
+
+ if (((u8data & 0x0F) > 0x09) || ((u8data & 0xF0) > 0x90)
+ ||(u8data > u8limit_max) || (u8data < u8limit_min))
+ {
+ return Error;
+ }
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief RTC 平、闰年检测
+ **
+** \param u8year:年十进制低两位:0-99
+ **
+ ** \retval 1:闰年 0：平年
+ **
+ ******************************************************************************/
+uint8_t Rtc_CheckLeapYear(uint8_t u8year)
+{
+ uint16_t tmp;
+ tmp=2000+u8year;
+ if((((tmp % 4)==0) && ((tmp % 100) !=0))|| ((tmp % 400) ==0))
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ ******************************************************************************
+ ** \brief RTC根据年获取二月的天数
+ **
+ ** \param [in] u8month月份，u8year年份
+ **
+** \retval u8day天数:28或29
+ **
+ ******************************************************************************/
+uint8_t Get_Month2_Day( uint8_t u8year)
+{
+ uint8_t u8day = 0;
+
+ u8day = 28;
+ if(Rtc_CheckLeapYear(u8year) == 1)
+ {
+ u8day++;
+ }
+ return u8day;
+}
+
+/**
+ ******************************************************************************
+ ** \brief RTC获取时间函数
+ **
+ ** \param time: 用于存放读取自时间寄存器的时间数据，格式为BCD码格式
+ **
+ ** \retval Ok 获取正常
+ ** \retval ErrorTimeout 时间溢出错误
+ ******************************************************************************/
+en_result_t Rtc_ReadDateTime(stc_rtc_time_t* time)
+{
+ uint32_t u32TimeOut;
+ ASSERT(NULL != pstcTimeDate);
+ u32TimeOut = 1000;
+ if(1 == M0P_RTC->CR0_f.START)
+ {
+ M0P_RTC->CR1_f.WAIT = 1;
+ while(u32TimeOut--)
+ {
+ if(M0P_RTC->CR1_f.WAITF)
+ {
+ break;
+ }
+ }
+ if(u32TimeOut==0)
+ {
+ return ErrorTimeout;
+ }
+ }
+ time->u8Second = M0P_RTC->SEC;
+ time->u8Minute = M0P_RTC->MIN;
+ if(1 == M0P_RTC->CR0_f.AMPM)
+ {
+ time->u8Hour = M0P_RTC->HOUR;
+ }
+ else
+ {
+ time->u8Hour = M0P_RTC->HOUR&0x1f;
+ }
+ time->u8Day = M0P_RTC->DAY;
+ time->u8DayOfWeek = M0P_RTC->WEEK;
+ time->u8Month = M0P_RTC->MON;
+ time->u8Year = M0P_RTC->YEAR;
+
+ M0P_RTC->CR1_f.WAIT = 0;
+ if(1 == M0P_RTC->CR0_f.START)
+ {
+ while(M0P_RTC->CR1_f.WAITF)
+ {}
+ }
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief 向RTC时间寄存器写入时间
+ **
+ ** \param time： 存放时间的结构体，各个时间均为BCD码格式
+ **
+ ** \retval ErrorTimeout 或 Ok
+ **
+ ******************************************************************************/
+en_result_t Rtc_SetTime(stc_rtc_time_t* time)
+{
+ en_result_t enRet = Ok;
+ uint16_t u16TimeOut;
+ u16TimeOut = 1000;
+ if(M0P_RTC->CR0_f.START == 1)
+ {
+ M0P_RTC->CR1_f.WAIT = 1;
+ while(--u16TimeOut)
+ {
+ if(M0P_RTC->CR1_f.WAITF)
+ {
+ break;
+ }
+ }
+ if(u16TimeOut==0)
+ {
+ return ErrorTimeout;
+ }
+ }
+ M0P_RTC->SEC = time->u8Second;
+ M0P_RTC->MIN = time->u8Minute;
+ M0P_RTC->HOUR = time->u8Hour;
+ M0P_RTC->DAY = time->u8Day;
+ M0P_RTC->MON = time->u8Month;
+ M0P_RTC->YEAR = time->u8Year;
+ M0P_RTC->WEEK = time->u8DayOfWeek;
+
+ M0P_RTC->CR1_f.WAIT = 0;
+ if(M0P_RTC->CR0_f.START == 1)
+ {
+ while(M0P_RTC->CR1_f.WAITF)
+ {}
+ }
+ enRet = Ok;
+ return enRet;
+}
+
+/**
+ ******************************************************************************
+ ** \brief RTC闹钟中断时间获取
+ **
+ ** \param pstcAlarmTime：存放闹钟时间寄存器数据：秒 分 时 周
+ **
+ ** \retval 无
+ **
+ ******************************************************************************/
+void Rtc_GetAlarmTime(stc_rtc_alarmtime_t* pstcAlarmTime)
+{
+ pstcAlarmTime->RtcAlarmSec = M0P_RTC->ALMSEC;
+ pstcAlarmTime->RtcAlarmMinute = M0P_RTC->ALMMIN;
+ pstcAlarmTime->RtcAlarmHour = M0P_RTC->ALMHOUR;
+ pstcAlarmTime->RtcAlarmWeek = M0P_RTC->ALMWEEK;
+}
+
+/**
+ ******************************************************************************
+ ** \brief RTC闹钟设置
+ **
+ ** \param [in] pstcAlarmTime闹钟时间：秒 分 时 周
+ **
+ ** \retval Ok 设置正常
+ **
+ ******************************************************************************/
+en_result_t Rtc_SetAlarmTime(stc_rtc_alarmtime_t* pstcAlarmTime)
+{
+ en_result_t enRet = Ok;
+// ASSERT(NULL != pstcAlarmTime);
+ Rtc_AlmEnCmd(FALSE); //闹钟禁止以后再设置闹钟时间
+ enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmSec,0x00,0x59);
+ if(M0P_RTC->CR0_f.AMPM == RtcAm)
+ {
+ enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmHour,0x00,0x12);
+ }
+ else
+ {
+ enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmHour,0x00,0x24);
+ }
+ if(enRet != Ok)
+ {
+ return enRet;
+ }
+ enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmMinute,0x00,0x59);
+ if(enRet != Ok)
+ {
+ return enRet;
+ }
+
+ if(enRet != Ok)
+ {
+ return enRet;
+ }
+ M0P_RTC->ALMSEC = pstcAlarmTime->RtcAlarmSec & 0x7f;
+ M0P_RTC->ALMMIN = pstcAlarmTime->RtcAlarmMinute & 0x7f;
+ M0P_RTC->ALMHOUR = pstcAlarmTime->RtcAlarmHour & 0x3f;
+ M0P_RTC->ALMWEEK = pstcAlarmTime->RtcAlarmWeek;
+ Rtc_AlmEnCmd(TRUE); //闹钟许可
+ enRet = Ok;
+ return enRet;
+}
+
+/**
+******************************************************************************
+ ** \brief 初始化RTC
+ **
+ ** @param Rtc_InitStruct 存放stc_rtc_initstruct_t类型的结构体
+ ** \retval 无
+ **
+******************************************************************************/
+void Rtc_Init(stc_rtc_initstruct_t* Rtc_InitStruct)
+{
+ Rtc_Cmd(FALSE);
+ M0P_RTC->CR0_f.AMPM = Rtc_InitStruct->rtcAmpm; //实时时钟小时的时制
+ Rtc_SetCyc(&Rtc_InitStruct->rtcPrdsel); //设置周期中断的类型(PRDSEL)及其所选类型的时间(PRDS或PRDX)
+ M0P_RTC->CR1_f.CKSEL = Rtc_InitStruct->rtcClksrc; //实时时钟RTC的时钟源
+ Rtc_CompCfg(Rtc_InitStruct->rtcCompValue, Rtc_InitStruct->rtcCompen); //配置时钟误差补偿寄存器
+ Rtc_SetTime(&Rtc_InitStruct->rtcTime); //设置初始时钟
+}
+
+
+
diff --git a/driver/src/spi.c b/driver/src/spi.c
new file mode 100644
index 0000000..a833ccd
--- /dev/null
+++ b/driver/src/spi.c
@@ -0,0 +1,363 @@
+/******************************************************************************
+* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with eaenCh copy of this software, whether used in part or whole,
+* at all times.
+*/
+/*****************************************************************************/
+/** \file spi.c
+ **
+ ** SPI driver API.
+ ** @link Driver Group Some description @endlink
+ **
+ ** - 2018-05-17 1.0 Devi First version for Device Driver Library of
+ ** Module.
+ **
+ *****************************************************************************/
+
+/******************************************************************************
+ * Include files
+ *****************************************************************************/
+#include "spi.h"
+
+/**
+ ******************************************************************************
+ ** \addtogroup SpiGroup
+ *****************************************************************************/
+//@{
+
+/******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ *****************************************************************************/
+
+#define IS_VALID_STAT(x) ( SpiIf == (x)||\
+ SpiSserr == (x)||\
+ SpiBusy == (x)||\
+ SpiMdf == (x)||\
+ SpiTxe == (x)||\
+ SpiRxne == (x))
+
+
+/******************************************************************************/
+/* Local function prototypes ('static') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Local variable prototypes ('static') */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief SPI 请求状态获取
+ **
+ ** \param [in]SPIx 通道， enStatus 获取请求
+ **
+ ** \retval 请求状态
+ **
+ ******************************************************************************/
+boolean_t Spi_GetStatus(M0P_SPI_TypeDef* SPIx, en_spi_status_t enStatus)
+{
+ ASSERT(IS_VALID_STAT(enStatus));
+
+ if(SPIx->STAT&enStatus)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+
+}
+/**
+ ******************************************************************************
+ ** \brief SPI中断清除
+ **
+ ** \param [in]SPIx 通道选择
+ **
+ ** \retval 请求状态
+ **
+ ******************************************************************************/
+en_result_t Spi_ClearStatus(M0P_SPI_TypeDef* SPIx)
+{
+ SPIx->ICLR = 0;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief SPI 中断使能函数
+ **
+ ** \param [in] SPIx 通道
+ **
+ ** \retval Ok成功
+ **
+ ******************************************************************************/
+en_result_t Spi_IrqEnable(M0P_SPI_TypeDef* SPIx)
+{
+ SPIx->CR2 |= 0x4u;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief SPI 中断禁止函数
+ **
+ ** \param [in] enCh通道
+ **
+ ** \retval Ok成功
+ **
+ ******************************************************************************/
+en_result_t Spi_IrqDisable(M0P_SPI_TypeDef* SPIx)
+{
+ SPIx->CR2 &= ~0x4u;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief SPI 功能使能函数
+ **
+ ** \param [in] SPIx 通道，enFunc功能
+ **
+ ** \retval Ok初始化成功
+ **
+ ******************************************************************************/
+en_result_t Spi_FuncEnable(M0P_SPI_TypeDef* SPIx, en_spi_func_t enFunc)
+{
+ SPIx->CR2 |= enFunc;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief SPI 功能禁止函数
+ **
+ ** \param [in] SPIx 通道，enFunc功能
+ **
+ ** \retval Ok初始化成功
+ **
+ ******************************************************************************/
+en_result_t Spi_FuncDisable(M0P_SPI_TypeDef* SPIx, en_spi_func_t enFunc)
+{
+ SPIx->CR2 &= ~(uint32_t)enFunc;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief SPI 总体初始化函数
+ **
+ ** \param [in] SPIx 通道
+ ** \param [in] pstcSpiCfg 初始化结构体
+ **
+ ** \retval Ok初始化成功
+ ** \retval ErrorInvalidParameter 初始化错误
+ ******************************************************************************/
+en_result_t Spi_Init(M0P_SPI_TypeDef* SPIx, stc_spi_cfg_t *pstcSpiCfg)
+{
+ ASSERT(NULL != pstcSpiCfg);
+
+ SPIx->CR = 0;
+
+ SPIx->SSN = TRUE;
+
+ SPIx->CR = (uint32_t)pstcSpiCfg->enSpiMode |
+ (uint32_t)pstcSpiCfg->enPclkDiv |
+ (uint32_t)pstcSpiCfg->enCPOL |
+ (uint32_t)pstcSpiCfg->enCPHA |
+ (uint32_t)0x40;
+
+ SPIx->STAT = 0x00;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief SPI 配置主发送的电平
+ **
+ ** \param [in] SPIx 通道选择，bFlag高低电平
+ **
+ ** \retval 无
+ **
+ ******************************************************************************/
+void Spi_SetCS(M0P_SPI_TypeDef* SPIx, boolean_t bFlag)
+{
+ SPIx->SSN = bFlag;
+}
+/**
+ ******************************************************************************
+ ** \brief SPI 发送一字节函数
+ **
+ ** \param [in] SPIx 通道选择，u8Data发送字节
+ **
+ ** \retval Ok发送成功
+ **
+ ******************************************************************************/
+en_result_t Spi_SendData(M0P_SPI_TypeDef* SPIx, uint8_t u8Data)
+{
+ SPIx->DATA = u8Data;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief SPI 读/写一字节函数
+ **
+ ** \param [in] SPIx 通道选择
+ ** \param [in] u8Data 发送一字节数据
+ **
+ ** \retval 接收一字节数据
+ **
+ ******************************************************************************/
+uint8_t Spi_RWByte(M0P_SPI_TypeDef* SPIx, uint8_t u8Data)
+{
+ uint16_t Dly = 0xffff;
+
+ while(FALSE == SPIx->STAT_f.TXE) {
+ Dly--;
+ if(Dly == 0)
+ break;
+ }
+ Dly = 0xffff;
+ SPIx->DATA = u8Data;
+ while(FALSE == SPIx->STAT_f.RXNE) {
+ Dly--;
+ if(Dly == 0)
+ break;
+ }
+ return SPIx->DATA;
+}
+
+/**
+ ******************************************************************************
+** \brief SPI 从机预准备第一字节数据
+ **
+ ** \param [in] SPIx 通道选择
+ ** \param [in] u8Data 预准备第一字节数据
+ **
+ ** \retval None
+ **
+ ******************************************************************************/
+void Spi_Slave_DummyWriteData(M0P_SPI_TypeDef* SPIx, uint8_t u8Data)
+{
+ while(FALSE == SPIx->STAT_f.TXE){;}
+ SPIx->DATA = u8Data;
+}
+
+/**
+ ******************************************************************************
+ ** \brief SPI 连续发送多字节函数
+ **
+ ** \param [in] SPIx 通道选择
+ ** \param [in] pu8Buf 发送数据指针
+ **
+ ** \retval Ok发送成功
+ **
+ ******************************************************************************/
+en_result_t Spi_SendBuf(M0P_SPI_TypeDef* SPIx, uint8_t* pu8Buf, uint32_t u32Len)
+{
+ uint32_t u32Index=0;
+
+ for(u32Index=0; u32IndexSTAT_f.TXE){;}
+ SPIx->DATA = pu8Buf[u32Index];
+ while(FALSE == SPIx->STAT_f.RXNE){;}
+ pu8Buf[u32Index] = SPIx->DATA;
+ }
+
+ while(FALSE == SPIx->STAT_f.TXE){;}
+ while(TRUE == SPIx->STAT_f.BUSY){;}
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief SPI 接收一字节函数
+ **
+ ** \param [in] SPIx接收通道
+ **
+ ** \retval 接收一字节数据
+ **
+ ******************************************************************************/
+uint8_t Spi_ReceiveData(M0P_SPI_TypeDef* SPIx)
+{
+ return SPIx->DATA;
+}
+
+/**
+ ******************************************************************************
+ ** \brief SPI 连续接收多字节函数
+ **
+ ** \param [in] SPIx 通道选择
+ ** \param [in] pu8Buf 发送数据指针
+ **
+ ** \retval Ok发送成功
+ **
+ ******************************************************************************/
+en_result_t Spi_ReceiveBuf(M0P_SPI_TypeDef* SPIx, uint8_t* pu8Buf, uint32_t u32Len)
+{
+ uint32_t u32Index=0;
+
+ for(u32Index=0; u32IndexSTAT_f.TXE){;}
+ SPIx->DATA = 0x00;
+ while(FALSE == SPIx->STAT_f.RXNE){;}
+ pu8Buf[u32Index] = SPIx->DATA;
+ }
+
+ while(TRUE == SPIx->STAT_f.BUSY){;}
+
+ return Ok;
+}
+
+//@} // SpiGroup
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
+
diff --git a/driver/src/sysctrl.c b/driver/src/sysctrl.c
new file mode 100644
index 0000000..83f00be
--- /dev/null
+++ b/driver/src/sysctrl.c
@@ -0,0 +1,746 @@
+/******************************************************************************
+*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file sysctrl.c
+ **
+ ** Common API of sysctrl.
+ ** @link SysctrlGroup Some description @endlink
+ **
+ ** - 2018-04-22 Lux
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "sysctrl.h"
+
+/**
+ *******************************************************************************
+ ** \addtogroup SysctrlGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+#define CLK_TIMEOUT (1000000u)
+
+#define IS_VALID_SRC(x) ( ClkRCH == (x)||\
+ ClkXTH == (x)||\
+ ClkRCL == (x)||\
+ ClkXTL == (x) )
+
+
+#define IS_VALID_FUNC(x) ( ClkFuncWkupRCH == (x)||\
+ ClkFuncXTHEn == (x)||\
+ ClkFuncXTLEn == (x)||\
+ ClkFuncXTLAWSON == (x)||\
+ ClkFuncFaultEn == (x)||\
+ ClkFuncRtcLPWEn == (x)||\
+ ClkFuncLockUpEn == (x)||\
+ ClkFuncRstPinIOEn == (x)||\
+ ClkFuncSwdPinIOEn == (x) )
+
+#define RC_TRIM_BASE_ADDR ((volatile uint16_t*) (0x00100C00ul))
+#define RCH_CR_TRIM_24M_VAL (*((volatile uint16_t*) (0x00100C00ul)))
+#define RCH_CR_TRIM_22_12M_VAL (*((volatile uint16_t*) (0x00100C02ul)))
+#define RCH_CR_TRIM_16M_VAL (*((volatile uint16_t*) (0x00100C04ul)))
+#define RCH_CR_TRIM_8M_VAL (*((volatile uint16_t*) (0x00100C06ul)))
+#define RCH_CR_TRIM_4M_VAL (*((volatile uint16_t*) (0x00100C08ul)))
+
+#define RCL_CR_TRIM_38400_VAL (*((volatile uint16_t*) (0x00100C20ul)))
+#define RCL_CR_TRIM_32768_VAL (*((volatile uint16_t*) (0x00100C22ul)))
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+extern uint32_t SystemCoreClock;
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *******************************************************************************
+ ** \brief SYSCTRL0\SYSCTRL1寄存器操作解锁
+ **
+ ** \retval None
+ ******************************************************************************/
+static void _SysctrlUnlock(void)
+{
+ M0P_SYSCTRL->SYSCTRL2 = 0x5A5A;
+ M0P_SYSCTRL->SYSCTRL2 = 0xA5A5;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 系统时钟源使能
+ ** \param [in] enSource 目标时钟源
+ ** \param [in] bFlag 使能1-开/0-关
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag)
+{
+ en_result_t enRet = Ok;
+ uint32_t u32Temp;
+
+ _SysctrlUnlock();
+ bFlag = !!bFlag;
+
+ u32Temp = M0P_SYSCTRL->PERI_CLKEN0;
+ switch (enSource)
+ {
+ case SysctrlClkRCH:
+ M0P_SYSCTRL->SYSCTRL0_f.RCH_EN = bFlag;
+ while(bFlag && (1 != M0P_SYSCTRL->RCH_CR_f.STABLE))
+ {
+ ;
+ }
+ break;
+
+ case SysctrlClkXTH:
+ M0P_SYSCTRL->PERI_CLKEN0_f.GPIO = TRUE;
+ M0P_GPIO->PFADS |= 3u;
+ M0P_SYSCTRL->SYSCTRL0_f.XTH_EN = bFlag;
+ while(bFlag && (1 != M0P_SYSCTRL->XTH_CR_f.STABLE))
+ {
+ ;
+ }
+ break;
+
+ case SysctrlClkRCL:
+
+ M0P_SYSCTRL->SYSCTRL0_f.RCL_EN = bFlag;
+ while(bFlag && (1 != M0P_SYSCTRL->RCL_CR_f.STABLE))
+ {
+ ;
+ }
+ break;
+
+ case SysctrlClkXTL:
+ M0P_SYSCTRL->PERI_CLKEN0_f.GPIO = TRUE;
+ M0P_GPIO->PCADS |= 0xC000;
+ M0P_SYSCTRL->SYSCTRL0_f.XTL_EN = bFlag;
+ while(bFlag && (1 != M0P_SYSCTRL->XTL_CR_f.STABLE))
+ {
+ ;
+ }
+ break;
+
+ case SysctrlClkPLL:
+ M0P_SYSCTRL->PERI_CLKEN0_f.ADC = TRUE;
+ M0P_BGR->CR_f.BGR_EN = TRUE;
+ delay10us(20);
+ M0P_SYSCTRL->SYSCTRL0_f.PLL_EN = bFlag;
+ while(bFlag && (1 != M0P_SYSCTRL->PLL_CR_f.STABLE))
+ {
+ ;
+ }
+ break;
+
+ default:
+ enRet = ErrorInvalidParameter;
+ break;
+ }
+ M0P_SYSCTRL->PERI_CLKEN0 = u32Temp;
+
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 外部高速晶振驱动配置
+ ** \param [in] enFreq 外部高速晶振频率范围选择
+ ** \param [in] enDriver 外部高速晶振驱动能力选择
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_XTHDriverCfg(en_sysctrl_xtal_driver_t enDriver)
+{
+ en_result_t enRet = Ok;
+
+ M0P_SYSCTRL->XTH_CR_f.DRIVER = enDriver;
+
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 外部低速晶振驱动配置
+ ** \param [in] enFreq 外部低速晶振频率范围选择
+ ** \param [in] enDriver 外部低速晶振驱动能力选择
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_XTLDriverCfg(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver)
+{
+ en_result_t enRet = Ok;
+
+ M0P_SYSCTRL->XTL_CR_f.AMP_SEL = enAmp;
+ M0P_SYSCTRL->XTL_CR_f.DRIVER = enDriver;
+
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 外部高速时钟稳定周期配置
+ ** \param [in] enCycle 外部高速时钟稳定周期设置
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle)
+{
+ en_result_t enRet = Ok;
+ M0P_SYSCTRL->XTH_CR_f.STARTUP = enCycle;
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 内部低速时钟稳定周期配置
+ ** \param [in] enCycle 内部低速时钟稳定周期设置
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle)
+{
+ en_result_t enRet = Ok;
+ M0P_SYSCTRL->RCL_CR_f.STARTUP = enCycle;
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 外部低速时钟稳定周期配置
+ ** \param [in] enCycle 外部低速时钟稳定周期设置
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle)
+{
+ en_result_t enRet = Ok;
+ M0P_SYSCTRL->XTL_CR_f.STARTUP = enCycle;
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief PLL稳定周期配置
+ ** \param [in] enCycle PLL稳定周期设置
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle)
+{
+ en_result_t enRet = Ok;
+ M0P_SYSCTRL->PLL_CR_f.STARTUP = enCycle;
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 时钟源切换，该函数执行后会开启新时钟源
+ ** \note 选择时钟源之前，需根据需要配置目标时钟源的频率/驱动参数/使能时钟源等
+ ** \param [in] enSource 新时钟源
+ **
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource)
+{
+ en_result_t enRet = Ok;
+
+ en_sysctrl_clk_source_t ClkNew = enSource;
+
+ _SysctrlUnlock();
+ M0P_SYSCTRL->SYSCTRL0_f.CLKSW = ClkNew;
+
+ //更新Core时钟（HCLK）
+ SystemCoreClockUpdate();
+
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 获得系统时钟（HCLK）频率值
+ ** \retval uint32_t HCLK频率值
+ **
+ ******************************************************************************/
+uint32_t Sysctrl_GetHClkFreq(void)
+{
+ uint32_t u32Val = 0;
+ const uint32_t u32hcr_tbl[] = { 4000000, 8000000, 16000000, 22120000, 24000000};
+ const uint16_t u32lcr_tbl[] = { 32768, 38400};
+ en_sysctrl_clk_source_t enSrc;
+ uint16_t u16Trim[5] = {0};
+ u16Trim[4] = RCH_CR_TRIM_24M_VAL;
+ u16Trim[3] = RCH_CR_TRIM_22_12M_VAL;
+ u16Trim[2] = RCH_CR_TRIM_16M_VAL;
+ u16Trim[1] = RCH_CR_TRIM_8M_VAL;
+ u16Trim[0] = RCL_CR_TRIM_38400_VAL;
+
+ //获取当前系统时钟
+ enSrc = (en_sysctrl_clk_source_t)(M0P_SYSCTRL->SYSCTRL0_f.CLKSW);
+
+ switch (enSrc)
+ {
+ case SysctrlClkRCH:
+ {
+
+ if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[4]))
+ {
+ u32Val = u32hcr_tbl[4];
+ }
+ else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[3]))
+ {
+ u32Val = u32hcr_tbl[3];
+ }
+ else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[2]))
+ {
+ u32Val = u32hcr_tbl[2];
+ }
+ else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[1]))
+ {
+ u32Val = u32hcr_tbl[1];
+ }
+ else
+ {
+ u32Val = u32hcr_tbl[0];
+ }
+ }
+ break;
+ case SysctrlClkXTH:
+ u32Val = SYSTEM_XTH;
+ break;
+ case SysctrlClkRCL:
+ {
+ if(u16Trim[0] == (M0P_SYSCTRL->RCL_CR_f.TRIM))
+ {
+ u32Val = u32lcr_tbl[1];
+ }
+ else
+ {
+ u32Val = u32lcr_tbl[0];
+ }
+ }
+ break;
+ case SysctrlClkXTL:
+ u32Val = SYSTEM_XTL;
+ break;
+ case SysctrlClkPLL:
+ {
+ if (SysctrlPllRch == M0P_SYSCTRL->PLL_CR_f.REFSEL)
+ {
+ if(u16Trim[4] == M0P_SYSCTRL->RCH_CR_f.TRIM)
+ {
+ u32Val = u32hcr_tbl[4];
+ }
+ else if(u16Trim[3] == M0P_SYSCTRL->RCH_CR_f.TRIM)
+ {
+ u32Val = u32hcr_tbl[3];
+ }
+ else if(u16Trim[2] == M0P_SYSCTRL->RCH_CR_f.TRIM)
+ {
+ u32Val = u32hcr_tbl[2];
+ }
+ else if(u16Trim[1] == M0P_SYSCTRL->RCH_CR_f.TRIM)
+ {
+ u32Val = u32hcr_tbl[1];
+ }
+ else
+ {
+ u32Val = u32hcr_tbl[0];
+ }
+ }
+ else
+ {
+ u32Val = SYSTEM_XTH;
+ }
+
+ u32Val = (u32Val * M0P_SYSCTRL->PLL_CR_f.DIVN);
+ }
+ break;
+ default:
+ u32Val = 0u;
+ break;
+ }
+
+ u32Val = (u32Val >> M0P_SYSCTRL->SYSCTRL0_f.HCLK_PRS);
+
+ return u32Val;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 获得外设时钟（PCLK）频率值
+ ** \retval uint32_t PCLK频率值(Hz)
+ **
+ ******************************************************************************/
+uint32_t Sysctrl_GetPClkFreq(void)
+{
+ uint32_t u32Val = 0;
+
+ u32Val = Sysctrl_GetHClkFreq();
+ u32Val = (u32Val >> (M0P_SYSCTRL->SYSCTRL0_f.PCLK_PRS));
+
+ return u32Val;
+}
+
+
+/**
+ *******************************************************************************
+ ** \brief 时钟初始化函数
+ ** \param [in] pstcCfg 初始化配置参数
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_ClkInit(stc_sysctrl_clk_cfg_t *pstcCfg)
+{
+ en_result_t enRet = Ok;
+
+ //系统时钟参数配置
+ switch(pstcCfg->enClkSrc)
+ {
+ case SysctrlClkRCH:
+
+ break;
+ case SysctrlClkXTH:
+ Sysctrl_XTHDriverCfg(SysctrlXtalDriver3);
+ Sysctrl_SetXTHStableTime(SysctrlXthStableCycle16384);
+ break;
+ case SysctrlClkRCL:
+ Sysctrl_SetRCLStableTime(SysctrlRclStableCycle256);
+ break;
+ case SysctrlClkXTL:
+ Sysctrl_XTLDriverCfg(SysctrlXtlAmp3, SysctrlXtalDriver3);
+ Sysctrl_SetXTLStableTime(SysctrlXtlStableCycle16384);
+ break;
+ case SysctrlClkPLL:
+ Sysctrl_SetPLLStableTime(SysctrlPllStableCycle16384);
+ break;
+ default:
+ enRet = ErrorInvalidParameter;
+ break;
+ }
+
+ //时钟源使能
+ Sysctrl_ClkSourceEnable(pstcCfg->enClkSrc, TRUE);
+
+ //时钟源切换
+ Sysctrl_SysClkSwitch(pstcCfg->enClkSrc);
+
+ //时钟分频设置
+ Sysctrl_SetHCLKDiv(pstcCfg->enHClkDiv);
+ Sysctrl_SetPCLKDiv(pstcCfg->enPClkDiv);
+
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 时钟去初始化函数
+ ** \param [in]
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_ClkDeInit(void)
+{
+ en_result_t enRet = Ok;
+
+ //配置RCH为内部4Hz
+ Sysctrl_SetRCHTrim(SysctrlRchFreq4MHz);
+
+ //时钟源使能
+ Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE);
+
+ //时钟源切换
+ Sysctrl_SysClkSwitch(SysctrlClkRCH);
+
+ //其它时钟源使能关闭
+ Sysctrl_ClkSourceEnable(SysctrlClkXTH, FALSE);
+ Sysctrl_ClkSourceEnable(SysctrlClkRCL, FALSE);
+ Sysctrl_ClkSourceEnable(SysctrlClkXTL, FALSE);
+ Sysctrl_ClkSourceEnable(SysctrlClkPLL, FALSE);
+
+ //时钟分频设置
+ Sysctrl_SetHCLKDiv(SysctrlHclkDiv1);
+ Sysctrl_SetPCLKDiv(SysctrlPclkDiv1);
+
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 内部高速时钟频率TRIM值加载
+ ** \param [in] enRCHFreq 设定的RCH目标频率值
+ ** \retval Ok 设定成功
+ ** 其他 设定失败或时钟未稳定
+ ******************************************************************************/
+en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq)
+{
+ //加载RCH Trim值
+ M0P_SYSCTRL->RCH_CR_f.TRIM = *(RC_TRIM_BASE_ADDR + enRCHFreq);
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 外部高速时钟频率范围设定
+ ** \param [in] enXTHFreq 设定的频率值
+ ** \retval Ok 设定成功
+ ** 其他 设定失败或时钟未稳定
+ ******************************************************************************/
+en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq)
+{
+ en_result_t enRet = Ok;
+
+ M0P_SYSCTRL->XTH_CR_f.XTH_FSEL = enXTHFreq;
+
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief PLL时钟配置
+ ** \param [in] pstcPLLCfg PLL配置结构体指针
+ ** \retval Ok 设定成功
+ ** 其他 设定失败或参数值不匹配
+ ******************************************************************************/
+en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_cfg_t *pstcPLLCfg)
+{
+ en_result_t enRet = Ok;
+
+ uint16_t u16Trim[5] = {0};
+ u16Trim[4] = RCH_CR_TRIM_24M_VAL;
+ u16Trim[3] = RCH_CR_TRIM_22_12M_VAL;
+ u16Trim[2] = RCH_CR_TRIM_16M_VAL;
+ u16Trim[1] = RCH_CR_TRIM_8M_VAL;
+
+ ////PLL最高时钟不能超过48MHz
+ //RCH作为PLL输入
+ if (SysctrlPllRch == pstcPLLCfg->enPllClkSrc)
+ {
+ if( ((u16Trim[4] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 2)) ||
+ ((u16Trim[3] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 2)) ||
+ ((u16Trim[2] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 3)) ||
+ ((u16Trim[1] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 6)))
+ {
+ return ErrorInvalidMode;
+ }
+ }
+ else //XTH作为PLL输入
+ {
+ if ((SYSTEM_XTH * pstcPLLCfg->enPllMul) > 48*1000*1000)
+ {
+ return ErrorInvalidMode;
+ }
+ }
+
+ M0P_SYSCTRL->PLL_CR_f.FRSEL = pstcPLLCfg->enInFreq;
+ M0P_SYSCTRL->PLL_CR_f.FOSC = pstcPLLCfg->enOutFreq;
+ M0P_SYSCTRL->PLL_CR_f.DIVN = pstcPLLCfg->enPllMul;
+ M0P_SYSCTRL->PLL_CR_f.REFSEL = pstcPLLCfg->enPllClkSrc;
+
+ return enRet;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 内部低速时钟频率TRIM值加载
+ ** \param [in] enRCLFreq 设定的RCL目标频率值
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq)
+{
+ M0P_SYSCTRL->RCL_CR_f.TRIM = *(RC_TRIM_BASE_ADDR + enRCLFreq);
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 系统时钟（HCLK）分频设定
+ ** \param [in] enHCLKDiv 分频设定值
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv)
+{
+ _SysctrlUnlock();
+ M0P_SYSCTRL->SYSCTRL0_f.HCLK_PRS = enHCLKDiv;
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 外设时钟（PCLK）分频设定
+ ** \param [in] enPCLKDiv 分频设定值
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv)
+{
+ _SysctrlUnlock();
+ M0P_SYSCTRL->SYSCTRL0_f.PCLK_PRS = enPCLKDiv;
+
+ return Ok;
+}
+
+///<< for Sysctrl_SetPeripheralGate() & Sysctrl_GetPeripheralGate()
+static volatile boolean_t bDacPeriBac = FALSE;
+
+/**
+ *******************************************************************************
+ ** \brief 设置外设时钟门控开关
+ ** \param [in] enPeripheral 目标外设
+ ** \param [in] bFlag 使能开关
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag)
+{
+ if(enPeripheral&0x20u)
+ {
+ enPeripheral &= ~0x20u;
+ SetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN1)), enPeripheral, bFlag);
+
+ if((SysctrlPeripheralDac & ~0x20u) == enPeripheral)
+ {
+ bDacPeriBac = bFlag;
+ }
+ else
+ {
+ SetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN1)), (SysctrlPeripheralDac & ~0x20u), bDacPeriBac);
+ }
+ }
+ else
+ {
+ SetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN0)), enPeripheral, bFlag);
+ }
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 获得外设时钟门控开关状态
+ ** \param [in] enPeripheral 目标外设
+ ** \retval TRUE 开
+ ** FALSE 关
+ ******************************************************************************/
+boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral)
+{
+ if(enPeripheral&0x20u)
+ {
+ if(SysctrlPeripheralDac == enPeripheral)
+ {
+ return bDacPeriBac;
+ }
+ else
+ {
+ enPeripheral &= ~0x20u;
+ return GetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN1)), enPeripheral);
+ }
+
+ }
+ else
+ {
+ return GetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN0)), enPeripheral);
+ }
+
+}
+
+/**
+ *******************************************************************************
+ ** \brief 系统功能设定
+ ** \param [in] enFunc 系统功能枚举类型
+ ** \param [in] bFlag 1-开/0-关
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag)
+{
+ _SysctrlUnlock();
+ SetBit((uint32_t)(&(M0P_SYSCTRL->SYSCTRL1)), enFunc, bFlag);
+
+ return Ok;
+}
+
+/**
+ *******************************************************************************
+ ** \brief 设定RTC校准时钟频率
+ ** \param [in] enRtcAdj 校准频率值
+ ** \retval Ok 设定成功
+ ** 其他 设定失败
+ ******************************************************************************/
+en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj)
+{
+ _SysctrlUnlock();
+ M0P_SYSCTRL->SYSCTRL1_f.RTC_FREQ_ADJUST = enRtcAdj;
+
+ return Ok;
+}
+
+//@} // SysctrlGroup
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/timer3.c b/driver/src/timer3.c
new file mode 100644
index 0000000..c45059a
--- /dev/null
+++ b/driver/src/timer3.c
@@ -0,0 +1,1368 @@
+/******************************************************************************
+*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file timer3.c
+ **
+ ** Common API of base timer.
+ ** @link Tiemr3 Group Some description @endlink
+ **
+ ** - 2019-04-18 Husj First Version
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "timer3.h"
+/**
+ *******************************************************************************
+ ** \addtogroup Tim3Group
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 中断标志获取(模式0/1/23)
+ **
+ **
+ ** \param [in] enTim3Irq 中断类型
+ **
+ ** \retval TRUE or FALSE
+ *****************************************************************************/
+boolean_t Tim3_GetIntFlag(en_tim3_irq_type_t enTim3Irq)
+{
+ boolean_t bRetVal = FALSE;
+ uint32_t u32Val;
+
+ u32Val = M0P_TIM3_MODE23->IFR;
+ bRetVal = (u32Val>>enTim3Irq) & 0x1;
+
+ return bRetVal;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 中断标志清除(模式0/1/23)
+ **
+ **
+ ** \param [in] enTim3Irq 中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_ClearIntFlag(en_tim3_irq_type_t enTim3Irq)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->ICLR = ~(1u<ICLR = 0;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 中断使能(模式0)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_Mode0_EnableIrq(void)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE0->M0CR_f.UIE = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 中断禁止(模式0)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_Mode0_DisableIrq(void)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE0->M0CR_f.UIE = FALSE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 中断使能(模式1)
+ **
+ **
+ ** \param [in] enTim3Irq 中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_Mode1_EnableIrq (en_tim3_irq_type_t enTim3Irq)
+{
+ en_result_t enResult = Ok;
+
+
+ switch (enTim3Irq)
+ {
+ case Tim3UevIrq:
+ M0P_TIM3_MODE1->M1CR_f.UIE = TRUE;
+ break;
+ case Tim3CA0Irq:
+ M0P_TIM3_MODE1->CR0_f.CIEA = TRUE;
+ break;
+ default:
+ enResult = Error;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 中断禁止(模式1)
+ **
+ **
+ ** \param [in] enTim3Irq 中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_Mode1_DisableIrq (en_tim3_irq_type_t enTim3Irq)
+{
+ en_result_t enResult = Ok;
+
+
+ switch (enTim3Irq)
+ {
+ case Tim3UevIrq:
+ M0P_TIM3_MODE1->M1CR_f.UIE = FALSE;
+ break;
+ case Tim3CA0Irq:
+ M0P_TIM3_MODE1->CR0_f.CIEA = FALSE;
+ break;
+ default:
+ enResult = Error;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 中断使能(模式23)
+ **
+ **
+ ** \param [in] enTim3Irq 中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_Mode23_EnableIrq (en_tim3_irq_type_t enTim3Irq)
+{
+ en_result_t enResult = Ok;
+
+
+ switch (enTim3Irq)
+ {
+ case Tim3UevIrq:
+ M0P_TIM3_MODE23->M23CR_f.UIE = TRUE;
+ break;
+ case Tim3CA0Irq:
+ M0P_TIM3_MODE23->CRCH0_f.CIEA = TRUE;
+ break;
+ case Tim3CB0Irq:
+ M0P_TIM3_MODE23->CRCH0_f.CIEB = TRUE;
+ break;
+ case Tim3CA1Irq:
+ M0P_TIM3_MODE23->CRCH1_f.CIEA = TRUE;
+ break;
+ case Tim3CB1Irq:
+ M0P_TIM3_MODE23->CRCH1_f.CIEB = TRUE;
+ break;
+ case Tim3CA2Irq:
+ M0P_TIM3_MODE23->CRCH2_f.CIEA = TRUE;
+ break;
+ case Tim3CB2Irq:
+ M0P_TIM3_MODE23->CRCH2_f.CIEB = TRUE;
+ break;
+ case Tim3BkIrq:
+ M0P_TIM3_MODE23->M23CR_f.BIE = TRUE;
+ break;
+ case Tim3TrigIrq:
+ M0P_TIM3_MODE23->M23CR_f.TIE = TRUE;
+ break;
+ default:
+ enResult = Error;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 中断禁止(模式23)
+ **
+ **
+ ** \param [in] enTim3Irq 中断类型
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_Mode23_DisableIrq (en_tim3_irq_type_t enTim3Irq)
+{
+ en_result_t enResult = Ok;
+
+
+ switch (enTim3Irq)
+ {
+ case Tim3UevIrq:
+ M0P_TIM3_MODE23->M23CR_f.UIE = FALSE;
+ break;
+ case Tim3CA0Irq:
+ M0P_TIM3_MODE23->CRCH0_f.CIEA = FALSE;
+ break;
+ case Tim3CB0Irq:
+ M0P_TIM3_MODE23->CRCH0_f.CIEB = FALSE;
+ break;
+ case Tim3CA1Irq:
+ M0P_TIM3_MODE23->CRCH1_f.CIEA = FALSE;
+ break;
+ case Tim3CB1Irq:
+ M0P_TIM3_MODE23->CRCH1_f.CIEB = FALSE;
+ break;
+ case Tim3CA2Irq:
+ M0P_TIM3_MODE23->CRCH2_f.CIEA = FALSE;
+ break;
+ case Tim3CB2Irq:
+ M0P_TIM3_MODE23->CRCH2_f.CIEB = FALSE;
+ break;
+ case Tim3BkIrq:
+ M0P_TIM3_MODE23->M23CR_f.BIE = FALSE;
+ break;
+ case Tim3TrigIrq:
+ M0P_TIM3_MODE23->M23CR_f.TIE = FALSE;
+ break;
+ default:
+ enResult = Error;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 初始化配置(模式0)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_Mode0_Init(stc_tim3_mode0_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE0->M0CR_f.MODE = pstcCfg->enWorkMode;
+ M0P_TIM3_MODE0->M0CR_f.GATEP = pstcCfg->enGateP;
+ M0P_TIM3_MODE0->M0CR_f.GATE = pstcCfg->bEnGate;
+ M0P_TIM3_MODE0->M0CR_f.PRS = pstcCfg->enPRS;
+ M0P_TIM3_MODE0->M0CR_f.TOGEN = pstcCfg->bEnTog;
+ M0P_TIM3_MODE0->M0CR_f.CT = pstcCfg->enCT;
+ M0P_TIM3_MODE0->M0CR_f.MD = pstcCfg->enCntMode;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 启动运行(模式0)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M0_Run(void)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE0->M0CR_f.CTEN = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 停止运行(模式0)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M0_Stop(void)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE0->M0CR_f.CTEN = FALSE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 端口输出使能/禁止设定(模式0)
+ **
+ **
+ ** \param [in] bEnOutput 翻转输出设定 TRUE:使能, FALSE:禁止
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M0_Enable_Output(boolean_t bEnOutput)
+{
+ en_result_t enResult = Ok;
+
+
+ M0P_TIM3_MODE0->DTR_f.MOE = bEnOutput;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 翻转使能/禁止（低电平）设定(模式0)
+ **
+ **
+ ** \param [in] bEnTOG 翻转输出设定 TRUE:使能, FALSE:禁止
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M0_EnTOG(boolean_t bEnTOG)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE0->M0CR_f.TOGEN = bEnTOG;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 16位计数器初值设置(模式0)
+ **
+ **
+ ** \param [in] u16Data CNT 16位初值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M0_Cnt16Set(uint16_t u16Data)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE0->CNT_f.CNT = u16Data;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 16位计数值获取(模式0)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval 16bits计数值
+ *****************************************************************************/
+uint16_t Tim3_M0_Cnt16Get(void)
+{
+ uint16_t u16CntData = 0;
+
+ u16CntData = M0P_TIM3_MODE0->CNT_f.CNT;
+
+ return u16CntData;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 重载值设置(模式0)
+ **
+ **
+ ** \param [in] u16Data 16bits重载值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M0_ARRSet(uint16_t u16Data)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE0->ARR_f.ARR = u16Data;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 32位计数器初值设置(模式0)
+ **
+ **
+ ** \param [in] u32Data 32位初值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M0_Cnt32Set(uint32_t u32Data)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE0->CNT32_f.CNT32 = u32Data;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 32位计数值获取(模式0)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval 32bits计数值
+ *****************************************************************************/
+uint32_t Tim3_M0_Cnt32Get(void)
+{
+ uint32_t u32CntData = 0;
+
+ u32CntData = M0P_TIM3_MODE0->CNT32_f.CNT32;
+
+ return u32CntData;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 初始化配置(模式1)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_Mode1_Init(stc_tim3_mode1_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE1->M1CR_f.MODE = pstcCfg->enWorkMode;
+ M0P_TIM3_MODE1->M1CR_f.PRS = pstcCfg->enPRS;
+ M0P_TIM3_MODE1->M1CR_f.CT = pstcCfg->enCT;
+ M0P_TIM3_MODE1->M1CR_f.ONESHOT = pstcCfg->enOneShot;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 PWC 输入配置(模式1)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M1_Input_Cfg(stc_tim3_pwc_input_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE1->MSCR_f.TS = pstcCfg->enTsSel;
+ M0P_TIM3_MODE1->MSCR_f.IA0S = pstcCfg->enIA0Sel;
+ M0P_TIM3_MODE1->MSCR_f.IB0S = pstcCfg->enIB0Sel;
+ M0P_TIM3_MODE1->FLTR_f.ETP = pstcCfg->enETRPhase;
+ M0P_TIM3_MODE1->FLTR_f.FLTET = pstcCfg->enFltETR;
+ M0P_TIM3_MODE1->FLTR_f.FLTA0 = pstcCfg->enFltIA0;
+ M0P_TIM3_MODE1->FLTR_f.FLTB0 = pstcCfg->enFltIB0;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 PWC测量边沿起始结束选择(模式1)
+ **
+ **
+ ** \param [in] enEdgeSel pwc测量起始终止电平
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M1_PWC_Edge_Sel(en_tim3_m1cr_Edge_t enEdgeSel)
+{
+ en_result_t enResult = Ok;
+
+ switch (enEdgeSel)
+ {
+ case 0: ///< 上升沿到上升沿(周期)
+ M0P_TIM3_MODE1->M1CR_f.EDG1ST = 0; //上升沿
+ M0P_TIM3_MODE1->M1CR_f.EDG2ND = 0; //上升沿
+ break;
+ case 1: ///< 下降沿到上升沿(低电平)
+ M0P_TIM3_MODE1->M1CR_f.EDG1ST = 1; //下降沿
+ M0P_TIM3_MODE1->M1CR_f.EDG2ND = 0; //上升沿
+ break;
+ case 2: ///< 上升沿到下降沿(高电平)
+ M0P_TIM3_MODE1->M1CR_f.EDG1ST = 0; //上升沿
+ M0P_TIM3_MODE1->M1CR_f.EDG2ND = 1; //下降沿
+ break;
+ case 3: ///< 下降沿到下降沿(周期)
+ M0P_TIM3_MODE1->M1CR_f.EDG1ST = 1; //下降沿
+ M0P_TIM3_MODE1->M1CR_f.EDG2ND = 1; //下降沿
+ break;
+ default:
+ ;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 启动运行(模式1)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M1_Run(void)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE1->M1CR_f.CTEN = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 停止运行(模式1)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M1_Stop(void)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE1->M1CR_f.CTEN = FALSE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 16位计数器初值设置(模式1)
+ **
+ **
+ ** \param [in] u16Data 16位初值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M1_Cnt16Set(uint16_t u16Data)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE1->CNT_f.CNT = u16Data;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 16位计数值获取(模式1)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval 16bits计数值
+ *****************************************************************************/
+uint16_t Tim3_M1_Cnt16Get(void)
+{
+ uint16_t u16CntData = 0;
+
+ u16CntData = M0P_TIM3_MODE1->CNT_f.CNT;
+
+ return u16CntData;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 脉冲宽度测量结果数值获取(模式1)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval 16bits脉冲宽度测量结果
+ *****************************************************************************/
+uint16_t Tim3_M1_PWC_CapValueGet(void)
+{
+ uint16_t u16CapData = 0;
+
+ u16CapData = M0P_TIM3_MODE1->CCR0A_f.CCR0A;
+
+ return u16CapData;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 初始化配置(模式23)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_Mode23_Init(stc_tim3_mode23_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->M23CR_f.MODE = pstcCfg->enWorkMode;
+
+ M0P_TIM3_MODE23->M23CR_f.PRS = pstcCfg->enPRS;
+ M0P_TIM3_MODE23->M23CR_f.CT = pstcCfg->enCT;
+ M0P_TIM3_MODE23->M23CR_f.COMP = pstcCfg->enPWMTypeSel;
+ M0P_TIM3_MODE23->M23CR_f.PWM2S = pstcCfg->enPWM2sSel;
+ M0P_TIM3_MODE23->M23CR_f.ONESHOT = pstcCfg->bOneShot;
+ M0P_TIM3_MODE23->M23CR_f.URS = pstcCfg->bURSSel;
+ M0P_TIM3_MODE23->M23CR_f.DIR = pstcCfg->enCntDir;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 PWM输出使能(模式23)
+ **
+ **
+ ** \param [in] bEnOutput PWM输出使能/禁止设定
+ ** \param [in] bEnAutoOutput PWM自动输出使能/禁止设定
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->DTR_f.MOE = bEnOutput;
+ M0P_TIM3_MODE23->DTR_f.AOE = bEnAutoOutput;
+
+ return enResult;
+}
+
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 启动运行(模式23)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_Run(void)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->M23CR_f.CTEN = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 停止运行(模式23)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_Stop(void)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->M23CR_f.CTEN = FALSE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 重载值设置(模式23)
+ **
+ **
+ ** \param [in] u16Data 16bits重载值
+ ** \param [in] bArrBufEn ARR重载缓存使能TRUE/禁止FALSE
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->ARR_f.ARR = u16Data;
+ M0P_TIM3_MODE23->M23CR_f.BUFPEN = bArrBufEn;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 16位计数器初值设置(模式23)
+ **
+ **
+ ** \param [in] u16Data 16位初值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_Cnt16Set(uint16_t u16Data)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->CNT_f.CNT = u16Data;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 16位计数值获取(模式23)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval 16bits计数值
+ *****************************************************************************/
+uint16_t Tim3_M23_Cnt16Get(void)
+{
+ uint16_t u16CntData = 0;
+
+ u16CntData = M0P_TIM3_MODE23->CNT_f.CNT;
+
+ return u16CntData;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 比较捕获寄存器CCRxA/CCRxB设置(模式23)
+ **
+ **
+ ** \param [in] enCCRSel CCRxA/CCRxB设定
+ ** \param [in] u16Data CCRxA/CCRxB 16位初始值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_CCR_Set(en_tim3_m23_ccrx_t enCCRSel, uint16_t u16Data)
+{
+ en_result_t enResult = Ok;
+
+ if(Tim3CCR0A == enCCRSel)
+ {
+ M0P_TIM3_MODE23->CCR0A_f.CCR0A = u16Data;
+ }
+ else if(Tim3CCR0B == enCCRSel)
+ {
+ M0P_TIM3_MODE23->CCR0B_f.CCR0B = u16Data;
+ }
+ else if(Tim3CCR1A == enCCRSel)
+ {
+ M0P_TIM3_MODE23->CCR1A_f.CCR1A = u16Data;
+ }
+ else if(Tim3CCR1B == enCCRSel)
+ {
+ M0P_TIM3_MODE23->CCR1B_f.CCR1B = u16Data;
+ }
+ else if(Tim3CCR2A == enCCRSel)
+ {
+ M0P_TIM3_MODE23->CCR2A_f.CCR2A = u16Data;
+ }
+ else if(Tim3CCR2B == enCCRSel)
+ {
+ M0P_TIM3_MODE23->CCR2B_f.CCR2B = u16Data;
+ }
+ else
+ {
+ enResult = Error;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 比较捕获寄存器CCRxA/CCRxB读取(模式23)
+ **
+ **
+ ** \param [in] enCCRSel CCRxA/CCRxB设定
+ **
+ ** \retval 16bitsCCRxA/CCRxB捕获值
+ *****************************************************************************/
+uint16_t Tim3_M23_CCR_Get(en_tim3_m23_ccrx_t enCCRSel)
+{
+ uint16_t u16Data = 0;
+
+ if(Tim3CCR0A == enCCRSel)
+ {
+ u16Data = M0P_TIM3_MODE23->CCR0A_f.CCR0A;
+ }
+ else if(Tim3CCR0B == enCCRSel)
+ {
+ u16Data = M0P_TIM3_MODE23->CCR0B_f.CCR0B;
+ }
+ else if(Tim3CCR1A == enCCRSel)
+ {
+ u16Data = M0P_TIM3_MODE23->CCR1A_f.CCR1A;
+ }
+ else if(Tim3CCR1B == enCCRSel)
+ {
+ u16Data = M0P_TIM3_MODE23->CCR1B_f.CCR1B;
+ }
+ else if(Tim3CCR2A == enCCRSel)
+ {
+ u16Data = M0P_TIM3_MODE23->CCR2A_f.CCR2A;
+ }
+ else if(Tim3CCR2B == enCCRSel)
+ {
+ u16Data = M0P_TIM3_MODE23->CCR2B_f.CCR2B;
+ }
+ else
+ {
+ u16Data = 0;
+ }
+
+ return u16Data;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 PWM互补输出模式下，GATE功能选择(模式23)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_GateFuncSel(stc_tim3_m23_gate_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->M23CR_f.CSG = pstcCfg->enGateFuncSel;
+ M0P_TIM3_MODE23->M23CR_f.CRG = pstcCfg->bGateRiseCap;
+ M0P_TIM3_MODE23->M23CR_f.CFG = pstcCfg->bGateFallCap;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 主从模式配置(模式23)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_MasterSlave_Set(stc_tim3_m23_master_slave_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->MSCR_f.MSM = pstcCfg->enMasterSlaveSel;
+ M0P_TIM3_MODE23->MSCR_f.MMS = pstcCfg->enMasterSrc;
+ M0P_TIM3_MODE23->MSCR_f.SMS = pstcCfg->enSlaveModeSel;
+ M0P_TIM3_MODE23->MSCR_f.TS = pstcCfg->enTsSel;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 CHxA/CHxB比较通道控制(模式23)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ ** \param [in] enTim3Chx Timer3通道(Tim3CH0, Tim3CH1, Tim3CH2)
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_PortOutput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_compare_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ switch (enTim3Chx)
+ {
+ case Tim3CH0:
+ M0P_TIM3_MODE23->CRCH0_f.CSA = 0;
+ M0P_TIM3_MODE23->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCHxACmpCtrl;
+ M0P_TIM3_MODE23->FLTR_f.CCPA0 = pstcCfg->enCHxAPolarity;
+ M0P_TIM3_MODE23->CRCH0_f.BUFEA = pstcCfg->bCHxACmpBufEn;
+ M0P_TIM3_MODE23->M23CR_f.CIS = pstcCfg->enCHxACmpIntSel;
+
+ M0P_TIM3_MODE23->CRCH0_f.CSB = 0;
+ M0P_TIM3_MODE23->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCHxBCmpCtrl;
+ M0P_TIM3_MODE23->FLTR_f.CCPB0 = pstcCfg->enCHxBPolarity;
+ M0P_TIM3_MODE23->CRCH0_f.BUFEB = pstcCfg->bCHxBCmpBufEn;
+ M0P_TIM3_MODE23->CRCH0_f.CISB = pstcCfg->enCHxBCmpIntSel;
+ break;
+ case Tim3CH1:
+ M0P_TIM3_MODE23->CRCH1_f.CSA = 0;
+ M0P_TIM3_MODE23->FLTR_f.OCMA1_FLTA1 = pstcCfg->enCHxACmpCtrl;
+ M0P_TIM3_MODE23->FLTR_f.CCPA1 = pstcCfg->enCHxAPolarity;
+ M0P_TIM3_MODE23->CRCH1_f.BUFEA = pstcCfg->bCHxACmpBufEn;
+ M0P_TIM3_MODE23->M23CR_f.CIS = pstcCfg->enCHxACmpIntSel;
+
+ M0P_TIM3_MODE23->CRCH1_f.CSB = 0;
+ M0P_TIM3_MODE23->FLTR_f.OCMB1_FLTB1 = pstcCfg->enCHxBCmpCtrl;
+ M0P_TIM3_MODE23->FLTR_f.CCPB1 = pstcCfg->enCHxBPolarity;
+ M0P_TIM3_MODE23->CRCH1_f.BUFEB = pstcCfg->bCHxBCmpBufEn;
+ M0P_TIM3_MODE23->CRCH1_f.CISB = pstcCfg->enCHxBCmpIntSel;
+ break;
+ case Tim3CH2:
+ M0P_TIM3_MODE23->CRCH2_f.CSA = 0;
+ M0P_TIM3_MODE23->FLTR_f.OCMA2_FLTA2 = pstcCfg->enCHxACmpCtrl;
+ M0P_TIM3_MODE23->FLTR_f.CCPA2 = pstcCfg->enCHxAPolarity;
+ M0P_TIM3_MODE23->CRCH2_f.BUFEA = pstcCfg->bCHxACmpBufEn;
+ M0P_TIM3_MODE23->M23CR_f.CIS = pstcCfg->enCHxACmpIntSel;
+
+ M0P_TIM3_MODE23->CRCH2_f.CSB = 0;
+ M0P_TIM3_MODE23->FLTR_f.OCMB2_FLTB2 = pstcCfg->enCHxBCmpCtrl;
+ M0P_TIM3_MODE23->FLTR_f.CCPB2 = pstcCfg->enCHxBPolarity;
+ M0P_TIM3_MODE23->CRCH2_f.BUFEB = pstcCfg->bCHxBCmpBufEn;
+ M0P_TIM3_MODE23->CRCH2_f.CISB = pstcCfg->enCHxBCmpIntSel;
+ break;
+ default:
+ enResult = Error;
+ break;
+ }
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 CHxA/CHxB输入控制(模式23)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ ** \param [in] enTim3Chx Timer3通道(Tim3CH0, Tim3CH1, Tim3CH2)
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_PortInput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_input_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ switch (enTim3Chx)
+ {
+ case Tim3CH0:
+ M0P_TIM3_MODE23->CRCH0_f.CSA = 1;
+ M0P_TIM3_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcCfg->enCHxACapSel;
+ M0P_TIM3_MODE23->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCHxAInFlt;
+ M0P_TIM3_MODE23->FLTR_f.CCPA0 = pstcCfg->enCHxAPolarity;
+
+ M0P_TIM3_MODE23->CRCH0_f.CSB = 1;
+ M0P_TIM3_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcCfg->enCHxBCapSel;
+ M0P_TIM3_MODE23->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCHxBInFlt;
+ M0P_TIM3_MODE23->FLTR_f.CCPB0 = pstcCfg->enCHxBPolarity;
+ break;
+ case Tim3CH1:
+ M0P_TIM3_MODE23->CRCH1_f.CSA = 1;
+ M0P_TIM3_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcCfg->enCHxACapSel;
+ M0P_TIM3_MODE23->FLTR_f.OCMA1_FLTA1 = pstcCfg->enCHxAInFlt;
+ M0P_TIM3_MODE23->FLTR_f.CCPA1 = pstcCfg->enCHxAPolarity;
+
+ M0P_TIM3_MODE23->CRCH1_f.CSB = 1;
+ M0P_TIM3_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcCfg->enCHxBCapSel;
+ M0P_TIM3_MODE23->FLTR_f.OCMB1_FLTB1 = pstcCfg->enCHxBInFlt;
+ M0P_TIM3_MODE23->FLTR_f.CCPB1 = pstcCfg->enCHxBPolarity;
+ break;
+ case Tim3CH2:
+ M0P_TIM3_MODE23->CRCH2_f.CSA = 1;
+ M0P_TIM3_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcCfg->enCHxACapSel;
+ M0P_TIM3_MODE23->FLTR_f.OCMA2_FLTA2 = pstcCfg->enCHxAInFlt;
+ M0P_TIM3_MODE23->FLTR_f.CCPA2 = pstcCfg->enCHxAPolarity;
+
+ M0P_TIM3_MODE23->CRCH2_f.CSB = 1;
+ M0P_TIM3_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcCfg->enCHxBCapSel;
+ M0P_TIM3_MODE23->FLTR_f.OCMB2_FLTB2 = pstcCfg->enCHxBInFlt;
+ M0P_TIM3_MODE23->FLTR_f.CCPB2 = pstcCfg->enCHxBPolarity;
+ break;
+ default:
+ enResult = Error;
+ break;
+ }
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 ERT输入控制(模式23)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_ETRInput_Cfg(stc_tim3_m23_etr_input_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->FLTR_f.ETP = pstcCfg->enETRPolarity;
+ M0P_TIM3_MODE23->FLTR_f.FLTET = pstcCfg->enETRFlt;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 刹车BK输入控制(模式23)
+ **
+ **
+ ** \param [in] pstcBkCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_BrakeInput_Cfg(stc_tim3_m23_bk_input_cfg_t* pstcBkCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->DTR_f.BKE = pstcBkCfg->bEnBrake;
+ M0P_TIM3_MODE23->DTR_f.VCE = pstcBkCfg->bEnVCBrake;
+ M0P_TIM3_MODE23->DTR_f.SAFEEN = pstcBkCfg->bEnSafetyBk;
+ M0P_TIM3_MODE23->DTR_f.BKSEL = pstcBkCfg->bEnBKSync;
+ M0P_TIM3_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcBkCfg->enBkCH0AStat;
+ M0P_TIM3_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcBkCfg->enBkCH0BStat;
+ M0P_TIM3_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcBkCfg->enBkCH1AStat;
+ M0P_TIM3_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcBkCfg->enBkCH1BStat;
+ M0P_TIM3_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcBkCfg->enBkCH2AStat;
+ M0P_TIM3_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcBkCfg->enBkCH2BStat;
+ M0P_TIM3_MODE23->FLTR_f.BKP = pstcBkCfg->enBrakePolarity;
+ M0P_TIM3_MODE23->FLTR_f.FLTBK = pstcBkCfg->enBrakeFlt;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Base Timer3 触发ADC控制(模式23)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_TrigADC_Cfg(stc_tim3_m23_adc_trig_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->ADTR_f.ADTE = pstcCfg->bEnTrigADC;
+ M0P_TIM3_MODE23->ADTR_f.UEVE = pstcCfg->bEnUevTrigADC;
+ M0P_TIM3_MODE23->ADTR_f.CMA0E = pstcCfg->bEnCH0ACmpTrigADC;
+ M0P_TIM3_MODE23->ADTR_f.CMB0E = pstcCfg->bEnCH0BCmpTrigADC;
+ M0P_TIM3_MODE23->ADTR_f.CMA1E = pstcCfg->bEnCH1ACmpTrigADC;
+ M0P_TIM3_MODE23->ADTR_f.CMB1E = pstcCfg->bEnCH1BCmpTrigADC;
+ M0P_TIM3_MODE23->ADTR_f.CMA2E = pstcCfg->bEnCH2ACmpTrigADC;
+ M0P_TIM3_MODE23->ADTR_f.CMB2E = pstcCfg->bEnCH2BCmpTrigADC;
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+** \brief Timer3 死区功能(模式23)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_DT_Cfg(stc_tim3_m23_dt_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->DTR_f.DTEN = pstcCfg->bEnDeadTime;
+ M0P_TIM3_MODE23->DTR_f.DTR = pstcCfg->u8DeadTimeValue;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+** \brief Timer3 重复周期设置(模式23)
+ **
+ **
+ ** \param [in] u8ValidPeriod 重复周期值
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_SetValidPeriod(uint8_t u8ValidPeriod)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->RCR_f.RCR = u8ValidPeriod;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 OCREF清除功能(模式23)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_OCRefClr(stc_tim3_m23_OCREF_Clr_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->M23CR_f.OCCS = pstcCfg->enOCRefClrSrcSel;
+ M0P_TIM3_MODE23->M23CR_f.OCCE = pstcCfg->bVCClrEn;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 使能DMA传输(模式23)
+ **
+ **
+ ** \param [in] pstcCfg 初始化配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_EnDMA(stc_tim3_m23_trig_dma_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->M23CR_f.UDE = pstcCfg->bUevTrigDMA;
+ M0P_TIM3_MODE23->M23CR_f.TDE = pstcCfg->bTITrigDMA;
+ M0P_TIM3_MODE23->CRCH0_f.CDEA = pstcCfg->bCmpA0TrigDMA;
+ M0P_TIM3_MODE23->CRCH0_f.CDEB = pstcCfg->bCmpB0TrigDMA;
+ M0P_TIM3_MODE23->CRCH1_f.CDEA = pstcCfg->bCmpA1TrigDMA;
+ M0P_TIM3_MODE23->CRCH1_f.CDEB = pstcCfg->bCmpB1TrigDMA;
+ M0P_TIM3_MODE23->CRCH2_f.CDEA = pstcCfg->bCmpA2TrigDMA;
+ M0P_TIM3_MODE23->CRCH2_f.CDEB = pstcCfg->bCmpB2TrigDMA;
+ M0P_TIM3_MODE23->MSCR_f.CCDS = pstcCfg->enCmpUevTrigDMA;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 捕获比较A软件触发(模式23)
+ **
+ **
+ ** \param [in] enTim3Chx Timer3通道(Tim3CH0, Tim3CH1, Tim3CH2)
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_EnSwTrigCapCmpA(en_tim3_channel_t enTim3Chx)
+{
+ en_result_t enResult = Ok;
+ if(Tim3CH0 == enTim3Chx)
+ {
+ M0P_TIM3_MODE23->CRCH0_f.CCGA = TRUE;
+ }
+ else if(Tim3CH1 == enTim3Chx)
+ {
+ M0P_TIM3_MODE23->CRCH1_f.CCGA = TRUE;
+ }
+ else if(Tim3CH2 == enTim3Chx)
+ {
+ M0P_TIM3_MODE23->CRCH2_f.CCGA = TRUE;
+ }
+ else
+ {
+ enResult = Error;
+ }
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 捕获比较B软件触发(模式23)
+ **
+ **
+ ** \param [in] enTim3Chx Timer3通道(Tim3CH0, Tim3CH1, Tim3CH2)
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_EnSwTrigCapCmpB(en_tim3_channel_t enTim3Chx)
+{
+ en_result_t enResult = Ok;
+ if(Tim3CH0 == enTim3Chx)
+ {
+ M0P_TIM3_MODE23->CRCH0_f.CCGB = TRUE;
+ }
+ else if(Tim3CH1 == enTim3Chx)
+ {
+ M0P_TIM3_MODE23->CRCH1_f.CCGB = TRUE;
+ }
+ else if(Tim3CH2 == enTim3Chx)
+ {
+ M0P_TIM3_MODE23->CRCH2_f.CCGB = TRUE;
+ }
+ else
+ {
+ enResult = Error;
+ }
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 软件更新使能(模式23)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_EnSwUev(void)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->M23CR_f.UG = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 软件触发使能(模式23)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_EnSwTrig(void)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->M23CR_f.TG = TRUE;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Timer3 软件刹车使能(模式23)
+ **
+ **
+ ** \param [in] none
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Tim3_M23_EnSwBk(void)
+{
+ en_result_t enResult = Ok;
+
+ M0P_TIM3_MODE23->M23CR_f.BG = TRUE;
+
+ return enResult;
+}
+
+//@} // Tim3Group
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/trim.c b/driver/src/trim.c
new file mode 100644
index 0000000..91d1b97
--- /dev/null
+++ b/driver/src/trim.c
@@ -0,0 +1,248 @@
+/******************************************************************************
+*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file trim.c
+ **
+ ** Common API of trim.
+ ** @link trimGroup Some description @endlink
+ **
+ ** - 2017-05-16
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "trim.h"
+/**
+ *******************************************************************************
+ ** \addtogroup TrimGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+#define IS_VALID_TRIMINT(x) (TrimStop == (x) ||\
+ TrimCalCntOf == (x) ||\
+ TrimXTLFault == (x) ||\
+ TrimXTHFault == (x) ||\
+ TrimPLLFault == (x))
+
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ *****************************************************************************
+ ** \brief Trim中断标志获取
+ **
+ **
+ ** \param [in] enIntType 中断类型（RefStop、CalCntOf、XTAL32KFault、XTAL32MFault）
+ **
+ ** \retval TRUE or FALSE
+ *****************************************************************************/
+boolean_t Trim_GetIntFlag(en_trim_inttype_t enIntType)
+{
+ ASSERT(IS_VALID_TRIMINT(enIntType));
+
+ if(M0P_CLK_TRIM->IFR&enIntType)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+
+}
+
+/**
+ *****************************************************************************
+ ** \brief Trim中断标志清除
+ **
+ **
+ ** \param [in] enIntType 中断类型（RefStop、CalCntOf、XTAL32KFault、XTAL32MFault）
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Trim_ClearIntFlag(en_trim_inttype_t enIntType)
+{
+ en_result_t enResult = Error;
+
+ ASSERT(IS_VALID_TRIMINT(enIntType));
+
+ M0P_CLK_TRIM->ICLR &= ~(uint32_t)enIntType;
+
+ return enResult;
+}
+
+
+
+/**
+ *****************************************************************************
+ ** \brief Trim中断使能
+ **
+ **
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Trim_EnableIrq (void)
+{
+ M0P_CLK_TRIM->CR_f.IE = TRUE;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Trim中断禁止
+ **
+ **
+ **
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+void Trim_DisableIrq(void)
+{
+ M0P_CLK_TRIM->CR_f.IE = FALSE;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Trim初始化配置
+ **
+ **
+ ** \param [in] pstcCfg Trim配置结构体指针
+ **
+ ** \retval Ok or Error
+ *****************************************************************************/
+en_result_t Trim_Init(stc_trim_cfg_t* pstcCfg)
+{
+ en_result_t enResult = Error;
+
+ M0P_CLK_TRIM->CR = 0;
+
+ M0P_CLK_TRIM->CR = (uint32_t)pstcCfg->enCALCLK |
+ (uint32_t)pstcCfg->enREFCLK |
+ (uint32_t)pstcCfg->enMON;
+
+ M0P_CLK_TRIM->REFCON = pstcCfg->u32RefCon;
+ M0P_CLK_TRIM->CALCON = pstcCfg->u32CalCon;
+
+ enResult = Ok;
+
+ return enResult;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Trim校准/监测启动运行
+ **
+ **
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Trim_Run(void)
+{
+ M0P_CLK_TRIM->CR_f.TRIM_START = TRUE;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Trim校准/监测停止
+ **
+ **
+ **
+ **
+ ** \retval Null
+ *****************************************************************************/
+void Trim_Stop(void)
+{
+ M0P_CLK_TRIM->CR_f.TRIM_START = FALSE;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Trim参考计数器计数值获取
+ **
+ **
+ ** \retval u32Data 参考计数器计数值
+ *****************************************************************************/
+uint32_t Trim_RefCntGet(void)
+{
+ return (uint32_t)M0P_CLK_TRIM->REFCNT;
+}
+
+/**
+ *****************************************************************************
+ ** \brief Trim校准计数器计数值获取
+ **
+ **
+ **
+ **
+ ** \retval u32Data 校准计数器计数值
+ *****************************************************************************/
+uint32_t Trim_CalCntGet(void)
+{
+ return (uint32_t)M0P_CLK_TRIM->CALCNT;
+}
+
+//@} // TrimGroup
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/trng.c b/driver/src/trng.c
new file mode 100644
index 0000000..3cc7842
--- /dev/null
+++ b/driver/src/trng.c
@@ -0,0 +1,191 @@
+/******************************************************************************
+*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+
+/** \file rng.c
+ **
+ ** Common API of rng.
+ ** @link flashGroup Some description @endlink
+ **
+ ** - 2018-05-08
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "trng.h"
+/**
+ *******************************************************************************
+ ** \addtogroup FlashGroup
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ *****************************************************************************
+ ** \brief 随机数初始化(上电第一次生成随机数）
+ **
+ **
+ ** \retval TRUE or FALSE
+ *****************************************************************************/
+en_result_t Trng_Init(void)
+{
+ //==>>生成64bits随机数（上电第一次）
+ M0P_TRNG->CR_f.RNGCIR_EN = 1;
+ //模式配置0
+ M0P_TRNG->MODE_f.LOAD = 1;
+ M0P_TRNG->MODE_f.FDBK = 1;
+ M0P_TRNG->MODE_f.CNT = 6;
+ //生成随机数0
+ M0P_TRNG->CR_f.RNG_RUN = 1;
+ while(M0P_TRNG->CR_f.RNG_RUN)
+ {
+ ;
+ }
+
+ //模式配置1
+ M0P_TRNG->MODE_f.LOAD = 0;
+ M0P_TRNG->MODE_f.FDBK = 0;
+ M0P_TRNG->MODE_f.CNT = 4;
+ //生成随机数1
+ M0P_TRNG->CR_f.RNG_RUN = 1;
+ while(M0P_TRNG->CR_f.RNG_RUN)
+ {
+ ;
+ }
+
+ //关闭随机源电路，节省功耗
+ M0P_TRNG->CR_f.RNGCIR_EN = 0;
+
+ return Ok;
+}
+
+/**
+ *****************************************************************************
+ ** \brief 生成随机数（非上电第一次生成随机数）
+ **
+ **
+ ** \retval TRUE or FALSE
+ *****************************************************************************/
+en_result_t Trng_Generate(void)
+{
+ //==>>生成64bits随机数（非上电第一次生成）
+ M0P_TRNG->CR_f.RNGCIR_EN = 1;
+
+ //模式配置0
+ M0P_TRNG->MODE_f.LOAD = 0;
+ M0P_TRNG->MODE_f.FDBK = 1;
+ M0P_TRNG->MODE_f.CNT = 6;
+ //生成随机数0
+ M0P_TRNG->CR_f.RNG_RUN = 1;
+ while(M0P_TRNG->CR_f.RNG_RUN)
+ {
+ ;
+ }
+
+ //模式配置1
+ M0P_TRNG->MODE_f.FDBK = 0;
+ M0P_TRNG->MODE_f.CNT = 4;
+ M0P_TRNG->MODE_f.CNT = 4;
+ //生成随机数1
+ M0P_TRNG->CR_f.RNG_RUN = 1;
+ while(M0P_TRNG->CR_f.RNG_RUN)
+ {
+ ;
+ }
+
+ //关闭随机源电路，节省功耗
+ M0P_TRNG->CR_f.RNGCIR_EN = 0;
+
+ return Ok;
+}
+
+/**
+ *****************************************************************************
+ ** \brief 随机数获取
+ **
+ ** \retval data0
+ *****************************************************************************/
+uint32_t Trng_GetData0(void)
+{
+ return M0P_TRNG->DATA0;
+}
+
+/**
+ *****************************************************************************
+ ** \brief 随机数获取
+ **
+ ** \retval data1
+ *****************************************************************************/
+uint32_t Trng_GetData1(void)
+{
+ return M0P_TRNG->DATA1;
+}
+
+//@} // TrngGroup
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/driver/src/uart.c b/driver/src/uart.c
new file mode 100644
index 0000000..30ea02d
--- /dev/null
+++ b/driver/src/uart.c
@@ -0,0 +1,383 @@
+/*************************************************************************************
+* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file uart.c
+ **
+ ** UART function driver API.
+ ** @link SampleGroup Some description @endlink
+ **
+ ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module.
+ **
+ ******************************************************************************/
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "uart.h"
+/**
+ ******************************************************************************
+ ** \addtogroup UartGroup
+ ******************************************************************************/
+//@{
+/******************************************************************************/
+/* Local pre-processor symbols/macros ('#define') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Local function prototypes ('static') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Local variable definitions ('static') */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief UART通信中断使能函数设置
+ **
+ ** \param [in] UARTx通道号，enIrqSel发送or接收中断使能
+ **
+ ** \retval OK配置成功
+ ** \retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t Uart_EnableIrq(M0P_UART_TypeDef* UARTx, en_uart_irq_sel_t enIrqSel)
+{
+ SetBit((uint32_t)(&(UARTx->SCON)), enIrqSel, TRUE);
+
+ return Ok;
+}
+/**
+ ******************************************************************************
+ ** \brief UART通信中断禁止函数设置
+ **
+ ** \param [in] UARTx通道号，enIrqSel发送or接收中断禁止
+ **
+ ** \retval OK配置成功
+ ** \retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t Uart_DisableIrq(M0P_UART_TypeDef* UARTx, en_uart_irq_sel_t enIrqSel)
+{
+ SetBit((uint32_t)(&(UARTx->SCON)), enIrqSel, FALSE);
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief UART通道多主机模式配置
+ **
+ ** \param [in] UARTx通道号，stcMultiCfg多主机模式结构
+ **
+ ** \retval OK配置成功
+ ** \retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t Uart_SetMultiMode(M0P_UART_TypeDef* UARTx, stc_uart_multimode_t* pstcMultiCfg)
+{
+ if(NULL != pstcMultiCfg)
+ {
+ UARTx->SCON_f.ADRDET = TRUE;
+ UARTx->SADDR = pstcMultiCfg->u8SlaveAddr;
+ UARTx->SADEN = pstcMultiCfg->u8SaddEn;
+
+ }
+ else
+ {
+ return ErrorInvalidParameter;
+ }
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief UART单线半双工模式使能
+ **
+ ** \param [in] UARTx 通道号
+ **
+ ** \retval Null
+ ******************************************************************************/
+void Uart_HdModeEnable(M0P_UART_TypeDef* UARTx)
+{
+ UARTx->SCON_f.HDSEL = TRUE;
+}
+
+/**
+ ******************************************************************************
+ ** \brief UART单线半双工模式关闭
+ **
+ ** \param [in] UARTx 通道号
+ **
+ ** \retval Null
+ ******************************************************************************/
+void Uart_HdModeDisable(M0P_UART_TypeDef* UARTx)
+{
+ UARTx->SCON_f.HDSEL = FALSE;
+}
+
+/**
+ ******************************************************************************
+ ** \brief UART通道多机模式发送数据/地址帧配置TB8
+ **
+ ** \param [in] UARTx 通道号
+ ** \param [in] TRUE-TB8为地址帧标志；FALSE-TB8为数据帧标志；
+ **
+ ** \retval Null
+ ******************************************************************************/
+void Uart_SetTb8(M0P_UART_TypeDef* UARTx, boolean_t bTB8Value)
+{
+ UARTx->SCON_f.B8CONT = bTB8Value;
+
+}
+
+/**
+ ******************************************************************************
+ ** \brief 获取RB8数值
+ **
+ ** \param [in] UARTx通道号
+ **
+ ** \retval RB8
+ ******************************************************************************/
+boolean_t Uart_GetRb8(M0P_UART_TypeDef* UARTx)
+{
+ return (UARTx->SBUF_f.DATA8);
+}
+
+/**
+ ******************************************************************************
+ ** \brief UART通道多主机模式从机地址配置函数
+ **
+ ** \param [in] UARTx通道号，addr地址
+ **
+ ** \retval OK配置成功
+ ** \retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t Uart_SetSaddr(M0P_UART_TypeDef* UARTx,uint8_t u8Addr)
+{
+ UARTx->SADDR = u8Addr;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief UART通道发送或接收等功能使能设置
+ **
+ ** \param [in] UARTx通道号，enFunc功能
+ **
+ ** \retval OK配置成功
+ ** \retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t Uart_EnableFunc(M0P_UART_TypeDef* UARTx, en_uart_func_t enFunc)
+{
+ SetBit((uint32_t)(&(UARTx->SCON)), enFunc, TRUE);
+
+ return Ok;
+}
+/**
+ ******************************************************************************
+ ** \brief UART通道发送或接收等功能禁止设置
+ **
+ ** \param [in] UARTx通道号，enFunc功能
+ **
+ ** \retval OK配置成功
+ ** \retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t Uart_DisableFunc(M0P_UART_TypeDef* UARTx, en_uart_func_t enFunc)
+{
+ SetBit((uint32_t)(&(UARTx->SCON)), enFunc, FALSE);
+
+ return Ok;
+}
+/**
+ ******************************************************************************
+ ** \brief UART通道通信状态获取
+ **
+ ** \param [in] UARTx通道号
+ **
+ ** \retval 状态值
+ ******************************************************************************/
+uint8_t Uart_GetIsr(M0P_UART_TypeDef* UARTx)
+{
+ return (UARTx->ISR);
+}
+
+/**
+ ******************************************************************************
+ ** \brief UART通道通信状态获取
+ **
+ ** \param [in] UARTx通道号，enStatus获取哪个状态
+ **
+ ** \retval 状态值
+ ******************************************************************************/
+boolean_t Uart_GetStatus(M0P_UART_TypeDef* UARTx, en_uart_status_t enStatus)
+{
+ boolean_t bStatus = FALSE;
+
+
+ ASSERT(IS_VALID_STATUS(enStatus));
+
+ bStatus = GetBit((uint32_t)(&(UARTx->ISR)), enStatus);
+
+ return bStatus;
+}
+/**
+ ******************************************************************************
+ ** \brief UART通道通信状态清除
+ **
+ ** \param [in] UARTx通道号
+ **
+ ** \retval OK
+ ** \retval ErrorInvalidParameter清除失败
+ ******************************************************************************/
+en_result_t Uart_ClrIsr(M0P_UART_TypeDef* UARTx)
+{
+ UARTx->ICR = 0u;
+ return Ok;
+}
+/**
+ ******************************************************************************
+ ** \brief UART通道通信状态清除
+ **
+ ** \param [in] UARTx通道号，enStatus清除哪个状态
+ **
+ ** \retval OK
+ ** \retval ErrorInvalidParameter清除失败
+ ******************************************************************************/
+en_result_t Uart_ClrStatus(M0P_UART_TypeDef* UARTx,en_uart_status_t enStatus)
+{
+ ASSERT(IS_VALID_STATUS(enStatus));
+
+ SetBit((uint32_t)(&(UARTx->ICR)), enStatus, FALSE);
+
+ return Ok;
+}
+/**
+ ******************************************************************************
+ ** \brief UART通道发送数据函数,查询方式调用此函数，中断方式发送不适用
+ **
+ ** \param [in] UARTx通道号，Data发送数据
+ **
+ ** \retval Ok发送成功
+ ** \retval ErrorInvalidParameter发送失败
+ ******************************************************************************/
+en_result_t Uart_SendDataPoll(M0P_UART_TypeDef* UARTx, uint8_t u8Data)
+{
+ while(FALSE == Uart_GetStatus(UARTx,UartTxe))
+ {}
+ UARTx->SBUF_f.DATA = u8Data;
+ while(FALSE == Uart_GetStatus(UARTx,UartTC))
+ {}
+ Uart_ClrStatus(UARTx,UartTC);
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief UART通道发送数据函数,中断方式调用此函数
+ **
+ ** \param [in] UARTx通道号，Data发送数据
+ **
+ ** \retval Ok发送成功
+ ** \retval ErrorInvalidParameter发送失败
+ ******************************************************************************/
+en_result_t Uart_SendDataIt(M0P_UART_TypeDef* UARTx, uint8_t u8Data)
+{
+ UARTx->SBUF_f.DATA = u8Data;
+
+ return Ok;
+}
+
+/**
+ ******************************************************************************
+ ** \brief UART通道接收数据函数
+ **
+ ** \param [in] UARTx通道号
+ **
+ ** \retval 接收数据
+ ******************************************************************************/
+uint8_t Uart_ReceiveData(M0P_UART_TypeDef* UARTx)
+{
+ return (UARTx->SBUF_f.DATA);
+}
+
+/**
+ ******************************************************************************
+ ** \brief UART通道初始化函数
+ **
+ ** \param [in] UARTx通道号，pstcCfg初始化结构体 @ref stc_uart_cfg_t
+ **
+ ** \retval OK配置成功
+ ** \retval ErrorInvalidParameter配置失败
+ ******************************************************************************/
+en_result_t Uart_Init(M0P_UART_TypeDef* UARTx, stc_uart_cfg_t* pstcCfg)
+{
+ en_result_t enRet = Error;
+ uint32_t u32Over[2] = {0x4, 0x3};
+ uint16_t u16OverShift;
+ float32_t f32Scnt=0;
+
+ if(NULL == pstcCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ UARTx->SCON = 0;
+
+ UARTx->SCON = (uint32_t)pstcCfg->enStopBit |
+ (uint32_t)pstcCfg->enMmdorCk |
+ (uint32_t)pstcCfg->stcBaud.enClkDiv |
+ (uint32_t)pstcCfg->enRunMode;
+
+ if((UartMskMode1 == pstcCfg->enRunMode) || (UartMskMode3 == pstcCfg->enRunMode))
+ {
+ u16OverShift = u32Over[pstcCfg->stcBaud.enClkDiv/UartMsk8Or16Div];
+ f32Scnt = (float32_t)(pstcCfg->stcBaud.u32Pclk)/(float32_t)(pstcCfg->stcBaud.u32Baud<SCNT = (uint16_t)(float32_t)(f32Scnt + 0.5f);
+ Uart_EnableFunc(UARTx,UartRenFunc); ///<使能收发
+ }
+
+
+
+ enRet = Ok;
+ return enRet;
+}
+//@} // UartGroup
diff --git a/driver/src/vc.c b/driver/src/vc.c
new file mode 100644
index 0000000..8e09495
--- /dev/null
+++ b/driver/src/vc.c
@@ -0,0 +1,298 @@
+/******************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file vc.c
+ **
+ ** voltage comparator driver API.
+ ** @link VC Group Some description @endlink
+ **
+ ** - 2019-04-10 First Version
+ **
+ ******************************************************************************/
+
+/******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "vc.h"
+
+/**
+ ******************************************************************************
+ ** \addtogroup VcGroup
+ ******************************************************************************/
+//@{
+
+/******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+
+/******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*****************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ *****************************************************************************/
+
+/**
+******************************************************************************
+ ** \brief 配置VC中断触发方式
+ **
+ ** @param Channelx : VcChannelx x=0、1、2
+ ** @param enSel : VcIrqRise、VcIrqFall、VcIrqHigh
+ ** \retval 无
+ **
+******************************************************************************/
+void Vc_CfgItType(en_vc_channel_t Channelx, en_vc_irq_sel_t ItType)
+{
+ stc_vc_vc0_cr_field_t *stcVcnCr;
+ switch(Channelx)
+ {
+ case VcChannel0:
+ stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC0_CR_f;
+ break;
+ case VcChannel1:
+ stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC1_CR_f;
+ break;
+ case VcChannel2:
+ stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC2_CR_f;
+ break;
+ default:
+ break;
+ }
+ switch (ItType)
+ {
+ case VcIrqNone:
+ stcVcnCr->RISING = 0u;
+ stcVcnCr->FALLING = 0u;
+ stcVcnCr->LEVEL = 0u;
+ break;
+ case VcIrqRise:
+ stcVcnCr->RISING = 1u;
+ break;
+ case VcIrqFall:
+ stcVcnCr->FALLING = 1u;
+ break;
+ case VcIrqHigh:
+ stcVcnCr->LEVEL = 1u;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+******************************************************************************
+ ** \brief VC 中断使能与禁止
+ **
+ ** @param Channelx : VcChannelx x=0、1、2
+ ** @param NewStatus : TRUE 或 FALSE
+ ** \retval 无
+ **
+******************************************************************************/
+void Vc_ItCfg(en_vc_channel_t Channelx, boolean_t NewStatus)
+{
+ switch(Channelx)
+ {
+ case VcChannel0:
+ SetBit((uint32_t)(&(M0P_VC->VC0_CR)), 15, NewStatus);
+ break;
+ case VcChannel1:
+ SetBit((uint32_t)(&(M0P_VC->VC1_CR)), 15, NewStatus);
+ break;
+ case VcChannel2:
+ SetBit((uint32_t)(&(M0P_VC->VC2_CR)), 15, NewStatus);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+******************************************************************************
+ ** \brief VC 比较结果获取，包含中断标志位和滤波结果
+ **
+ ** @param Result : 所要读取的结果
+ ** \retval TRUE 或 FALSE
+ **
+******************************************************************************/
+boolean_t Vc_GetItStatus(en_vc_ifr_t Result)
+{
+ boolean_t bFlag;
+ bFlag = GetBit((uint32_t)(&(M0P_VC->IFR)), Result);
+ return bFlag;
+}
+
+/**
+******************************************************************************
+ ** \brief VC 清除中断标志位
+ **
+ ** @param NewStatus : Vc0_Intf、Vc1_Intf、Vc2_Intf
+ ** \retval 无
+ **
+******************************************************************************/
+void Vc_ClearItStatus(en_vc_ifr_t NewStatus)
+{
+ SetBit((uint32_t)(&(M0P_VC->IFR)), NewStatus, 0);
+}
+
+/**
+******************************************************************************
+ ** \brief VC 配置DAC相关的内容 VC_CR中 VC_REF2P5_SEL VC_DIV_EN VC_DIV
+ **
+ ** @param pstcDacCfg :
+ ** \retval Ok 或 ErrorInvalidParameter
+ **
+******************************************************************************/
+en_result_t Vc_DacInit(stc_vc_dac_cfg_t *pstcDacCfg)
+{
+ if (NULL == pstcDacCfg)
+ {
+ return ErrorInvalidParameter;
+ }
+
+ M0P_VC->CR_f.DIV_EN = pstcDacCfg->bDivEn;
+ M0P_VC->CR_f.REF2P5_SEL = pstcDacCfg->enDivVref;
+
+ if (pstcDacCfg->u8DivVal < 0x40)
+ {
+ M0P_VC->CR_f.DIV = pstcDacCfg->u8DivVal;
+ }
+ else
+ {
+ return ErrorInvalidParameter;
+ }
+
+ return Ok;
+}
+
+/**
+******************************************************************************
+ ** \brief VC通道初始化
+ **
+ ** @param pstcDacCfg :
+ ** \retval 无
+ **
+******************************************************************************/
+void Vc_Init(stc_vc_channel_cfg_t *pstcChannelCfg)
+{
+ if (VcChannel0 == pstcChannelCfg->enVcChannel)
+ {
+ M0P_VC->CR_f.VC0_HYS_SEL = pstcChannelCfg->enVcCmpDly;
+ M0P_VC->CR_f.VC0_BIAS_SEL = pstcChannelCfg->enVcBiasCurrent;
+ M0P_VC->VC0_CR_f.DEBOUNCE_TIME = pstcChannelCfg->enVcFilterTime;
+ M0P_VC->VC0_CR_f.P_SEL = pstcChannelCfg->enVcInPin_P;
+ M0P_VC->VC0_CR_f.N_SEL = pstcChannelCfg->enVcInPin_N;
+ M0P_VC->VC0_CR_f.FLTEN = pstcChannelCfg->bFlten;
+ M0P_VC->VC0_OUT_CFG = 1<enVcOutCfg;
+ }
+ else if (VcChannel1 == pstcChannelCfg->enVcChannel)
+ {
+ M0P_VC->CR_f.VC1_HYS_SEL = pstcChannelCfg->enVcCmpDly;
+ M0P_VC->CR_f.VC1_BIAS_SEL = pstcChannelCfg->enVcBiasCurrent;
+ M0P_VC->VC1_CR_f.DEBOUNCE_TIME = pstcChannelCfg->enVcFilterTime;
+ M0P_VC->VC1_CR_f.P_SEL = pstcChannelCfg->enVcInPin_P;
+ M0P_VC->VC1_CR_f.N_SEL = pstcChannelCfg->enVcInPin_N;
+ M0P_VC->VC1_CR_f.FLTEN = pstcChannelCfg->bFlten;
+ M0P_VC->VC1_OUT_CFG = 1<enVcOutCfg;
+ }
+ else if(VcChannel2 == pstcChannelCfg->enVcChannel)
+ {
+ M0P_VC->CR_f.VC2_HYS_SEL = pstcChannelCfg->enVcCmpDly;
+ M0P_VC->CR_f.VC2_BIAS_SEL = pstcChannelCfg->enVcBiasCurrent;
+ M0P_VC->VC2_CR_f.DEBOUNCE_TIME = pstcChannelCfg->enVcFilterTime;
+ M0P_VC->VC2_CR_f.P_SEL = pstcChannelCfg->enVcInPin_P;
+ M0P_VC->VC2_CR_f.N_SEL = pstcChannelCfg->enVcInPin_N;
+ M0P_VC->VC2_CR_f.FLTEN = pstcChannelCfg->bFlten;
+ M0P_VC->VC2_OUT_CFG = 1<enVcOutCfg;
+ }
+ else
+ {
+ ;
+ }
+}
+
+/**
+******************************************************************************
+ ** \brief VC 通道使能
+ **
+ ** \param enChannel : 通道号VcChannel0 VcChannel1 VcChannel2
+ ** \param NewStatus : TRUE FALSE
+ ** \retval NewStatus : TRUE FALSE
+ **
+******************************************************************************/
+void Vc_Cmd(en_vc_channel_t enChannel, boolean_t NewStatus)
+{
+ switch(enChannel)
+ {
+ case VcChannel0:
+ SetBit((uint32_t)(&(M0P_VC->VC0_CR)), 16, NewStatus);
+ break;
+ case VcChannel1:
+ SetBit((uint32_t)(&(M0P_VC->VC1_CR)), 16, NewStatus);
+ break;
+ case VcChannel2:
+ SetBit((uint32_t)(&(M0P_VC->VC2_CR)), 16, NewStatus);
+ break;
+ default:
+ break;
+ }
+}
+
+//@} // VcGroup
+
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
diff --git a/driver/src/wdt.c b/driver/src/wdt.c
new file mode 100644
index 0000000..4d07496
--- /dev/null
+++ b/driver/src/wdt.c
@@ -0,0 +1,203 @@
+/*************************************************************************************
+* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file wdt.c
+ **
+ ** WDT function driver API.
+ ** @link WdtGroup Some description @endlink
+ **
+ ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module.
+ **
+ ******************************************************************************/
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "wdt.h"
+
+/**
+ ******************************************************************************
+ ** \defgroup WdtGroup
+ **
+ ******************************************************************************/
+//@{
+
+/******************************************************************************/
+/* Local function prototypes ('static') */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief WDT溢出时间设置函数
+ **
+ ** \param [in] u8LoadValue 溢出时间
+ **
+ ** \retval 无
+ **
+ ******************************************************************************/
+void Wdt_WriteWdtLoad(uint8_t u8LoadValue)
+{
+ M0P_WDT->CON_f.WOV = u8LoadValue;
+}
+/**
+ ******************************************************************************
+ ** \brief WDT初始化函数
+ **
+ ** \param [in] enFunc @ref en_wdt_func_t
+ ** \param [in] enTime @ref en_wdt_time_t
+ **
+ ** \retval Ok
+ **
+ ******************************************************************************/
+en_result_t Wdt_Init(en_wdt_func_t enFunc, en_wdt_time_t enTime)
+{
+ en_result_t enRet = Error;
+
+ Wdt_WriteWdtLoad(enTime);
+ M0P_WDT->CON_f.WINT_EN = enFunc;
+ enRet = Ok;
+ return enRet;
+}
+/**
+ ******************************************************************************
+ ** \brief WDT复位及启动函数
+ **
+ ** \param [in] 无
+ **
+ ** \retval 无
+ **
+ ******************************************************************************/
+void Wdt_Start(void)
+{
+ M0P_WDT->RST = 0x1E;
+ M0P_WDT->RST = 0xE1;
+}
+
+/**
+ ******************************************************************************
+ ** \brief WDT喂狗
+ **
+ ** \param [in] 无
+ **
+ ** \retval Ok
+ **
+ ******************************************************************************/
+void Wdt_Feed(void)
+{
+ M0P_WDT->RST = 0x1E;
+ M0P_WDT->RST = 0xE1;
+}
+
+/**
+ ******************************************************************************
+ ** \brief WDT中断标志清除
+ **
+ ** \param [in] 无
+ **
+ ** \retval Ok
+ **
+ ******************************************************************************/
+void Wdt_IrqClr(void)
+{
+ M0P_WDT->RST = 0x1E;
+ M0P_WDT->RST = 0xE1;
+}
+
+/**
+ ******************************************************************************
+ ** \brief WDT读取当前计数值函数
+ **
+ ** \param [in] 无
+ **
+ ** \retval 计数值
+ **
+ ******************************************************************************/
+uint8_t Wdt_ReadWdtValue(void)
+{
+ uint8_t u8Count;
+
+ u8Count = M0P_WDT->CON_f.WCNTL;
+
+ return u8Count;
+}
+/**
+ ******************************************************************************
+ ** \brief WDT读取当前运行状态
+ **
+ ** \param [in] 无
+ **
+ ** \retval 状态值
+ **
+ ******************************************************************************/
+boolean_t Wdt_ReadwdtStatus(void)
+{
+ if(M0P_WDT->CON&0x10u)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+}
+
+/**
+ *******************************************************************************
+ ** \brief WDT 中断状态标记获取
+ **
+ **
+ ** \retval 中断状态
+ ******************************************************************************/
+boolean_t Wdt_GetIrqStatus(void)
+{
+ if(M0P_WDT->CON&0x80u)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+}
+
+
+//@} // WdtGroup
diff --git a/mcu/EWARM/HC32L17X.svd b/mcu/EWARM/HC32L17X.svd
new file mode 100644
index 0000000..85deab5
--- /dev/null
+++ b/mcu/EWARM/HC32L17X.svd
@@ -0,0 +1,37132 @@
+
+
+ HDSC Co.Ltd
+ HDSC
+ HDSC_HC32L17X
+ ARMCM0P
+ 1.2
+
+ CM0
+ r0p0
+ little
+ false
+ false
+ 3
+ false
+
+ 8
+ 32
+ 32
+ read-write
+ 0x0
+ 0x0
+
+
+ ADC
+ desc ADC
+ 0x40002400
+
+ 0x0
+ 0xD0
+
+
+
+ CR0
+ desc CR0
+ 0x4
+ 32
+ read-write
+ 0x67F0
+ 0xBFFF
+
+
+ EN
+ desc EN
+ 0
+ 0
+ read-write
+
+
+ CLKDIV
+ desc CLKDIV
+ 3
+ 2
+ read-write
+
+
+ SGLMUX
+ desc SGLMUX
+ 8
+ 4
+ read-write
+
+
+ REF
+ desc REF
+ 10
+ 9
+ read-write
+
+
+ BUF
+ desc BUF
+ 11
+ 11
+ read-write
+
+
+ SAM
+ desc SAM
+ 13
+ 12
+ read-write
+
+
+ INREFEN
+ desc INREFEN
+ 14
+ 14
+ read-write
+
+
+ IE
+ desc IE
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CR1
+ desc CR1
+ 0x8
+ 32
+ read-write
+ 0x8000
+ 0xFFFC
+
+
+ ALIGN
+ desc ALIGN
+ 2
+ 2
+ read-write
+
+
+ THCH
+ desc THCH
+ 7
+ 3
+ read-write
+
+
+ DMASQR
+ desc DMASQR
+ 8
+ 8
+ read-write
+
+
+ DMAJQR
+ desc DMAJQR
+ 9
+ 9
+ read-write
+
+
+ MODE
+ desc MODE
+ 10
+ 10
+ read-write
+
+
+ RACCEN
+ desc RACCEN
+ 11
+ 11
+ read-write
+
+
+ LTCMP
+ desc LTCMP
+ 12
+ 12
+ read-write
+
+
+ HTCMP
+ desc HTCMP
+ 13
+ 13
+ read-write
+
+
+ REGCMP
+ desc REGCMP
+ 14
+ 14
+ read-write
+
+
+ RACCCLR
+ desc RACCCLR
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQR0
+ desc SQR0
+ 0x40
+ 32
+ read-write
+ 0x0
+ 0x3FFFFFFF
+
+
+ CH0MUX
+ desc CH0MUX
+ 4
+ 0
+ read-write
+
+
+ CH1MUX
+ desc CH1MUX
+ 9
+ 5
+ read-write
+
+
+ CH2MUX
+ desc CH2MUX
+ 14
+ 10
+ read-write
+
+
+ CH3MUX
+ desc CH3MUX
+ 19
+ 15
+ read-write
+
+
+ CH4MUX
+ desc CH4MUX
+ 24
+ 20
+ read-write
+
+
+ CH5MUX
+ desc CH5MUX
+ 29
+ 25
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQR1
+ desc SQR1
+ 0x44
+ 32
+ read-write
+ 0x0
+ 0x3FFFFFFF
+
+
+ CH6MUX
+ desc CH6MUX
+ 4
+ 0
+ read-write
+
+
+ CH7MUX
+ desc CH7MUX
+ 9
+ 5
+ read-write
+
+
+ CH8MUX
+ desc CH8MUX
+ 14
+ 10
+ read-write
+
+
+ CH9MUX
+ desc CH9MUX
+ 19
+ 15
+ read-write
+
+
+ CH10MUX
+ desc CH10MUX
+ 24
+ 20
+ read-write
+
+
+ CH11MUX
+ desc CH11MUX
+ 29
+ 25
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQR2
+ desc SQR2
+ 0x48
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFF
+
+
+ CH12MUX
+ desc CH12MUX
+ 4
+ 0
+ read-write
+
+
+ CH13MUX
+ desc CH13MUX
+ 9
+ 5
+ read-write
+
+
+ CH14MUX
+ desc CH14MUX
+ 14
+ 10
+ read-write
+
+
+ CH15MUX
+ desc CH15MUX
+ 19
+ 15
+ read-write
+
+
+ CNT
+ desc CNT
+ 23
+ 20
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ JQR
+ desc JQR
+ 0x4C
+ 32
+ read-write
+ 0x0
+ 0x3FFFFFF
+
+
+ CH0MUX
+ desc CH0MUX
+ 4
+ 0
+ read-write
+
+
+ CH1MUX
+ desc CH1MUX
+ 9
+ 5
+ read-write
+
+
+ CH2MUX
+ desc CH2MUX
+ 14
+ 10
+ read-write
+
+
+ CH3MUX
+ desc CH3MUX
+ 19
+ 15
+ read-write
+
+
+ CNT
+ desc CNT
+ 21
+ 20
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT0
+ desc SQRRESULT0
+ 0x50
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT1
+ desc SQRRESULT1
+ 0x54
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT2
+ desc SQRRESULT2
+ 0x58
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT3
+ desc SQRRESULT3
+ 0x5C
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT4
+ desc SQRRESULT4
+ 0x60
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT5
+ desc SQRRESULT5
+ 0x64
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT6
+ desc SQRRESULT6
+ 0x68
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT7
+ desc SQRRESULT7
+ 0x6C
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT8
+ desc SQRRESULT8
+ 0x70
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT9
+ desc SQRRESULT9
+ 0x74
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT10
+ desc SQRRESULT10
+ 0x78
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT11
+ desc SQRRESULT11
+ 0x7C
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT12
+ desc SQRRESULT12
+ 0x80
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQR_RESULT13
+ desc SQR_RESULT13
+ 0x84
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT14
+ desc SQRRESULT14
+ 0x88
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRRESULT15
+ desc SQRRESULT15
+ 0x8C
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ JQRRESULT0
+ desc JQRRESULT0
+ 0x90
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ JQRRESULT1
+ desc JQRRESULT1
+ 0x94
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ JQRRESULT2
+ desc JQRRESULT2
+ 0x98
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ JQRRESULT3
+ desc JQRRESULT3
+ 0x9C
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ RESULT
+ desc RESULT
+ 0xA0
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ RESULT
+ desc RESULT
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ RESULTACC
+ desc RESULTACC
+ 0xA4
+ 32
+ read-only
+ 0x0
+ 0xFFFFF
+
+
+ RESULTACC
+ desc RESULTACC
+ 19
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ HT
+ desc HT
+ 0xA8
+ 32
+ read-write
+ 0xFFF
+ 0xFFF
+
+
+ HT
+ desc HT
+ 11
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ LT
+ desc LT
+ 0xAC
+ 32
+ read-write
+ 0x0
+ 0xFFF
+
+
+ LT
+ desc LT
+ 11
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0xB0
+ 32
+ read-only
+ 0x0
+ 0x3F
+
+
+ SGLIF
+ desc SGLIF
+ 0
+ 0
+ read-only
+
+
+ LTIF
+ desc LTIF
+ 1
+ 1
+ read-only
+
+
+ HTIF
+ desc HTIF
+ 2
+ 2
+ read-only
+
+
+ REGIF
+ desc REGIF
+ 3
+ 3
+ read-only
+
+
+ SQRIF
+ desc SQRIF
+ 4
+ 4
+ read-only
+
+
+ JQRIF
+ desc JQRIF
+ 5
+ 5
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICR
+ desc ICR
+ 0xB4
+ 32
+ write-only
+ 0x3F
+ 0x3F
+
+
+ SGLIC
+ desc SGLIC
+ 0
+ 0
+ write-only
+
+
+ LTIC
+ desc LTIC
+ 1
+ 1
+ write-only
+
+
+ HTIC
+ desc HTIC
+ 2
+ 2
+ write-only
+
+
+ REGIC
+ desc REGIC
+ 3
+ 3
+ write-only
+
+
+ SQRIC
+ desc SQRIC
+ 4
+ 4
+ write-only
+
+
+ JQRIC
+ desc JQRIC
+ 5
+ 5
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ EXTTRIGGER0
+ desc EXTTRIGGER0
+ 0xB8
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ TIM0
+ desc TIM0
+ 0
+ 0
+ read-write
+
+
+ TIM1
+ desc TIM1
+ 1
+ 1
+ read-write
+
+
+ TIM2
+ desc TIM2
+ 2
+ 2
+ read-write
+
+
+ TIM3
+ desc TIM3
+ 3
+ 3
+ read-write
+
+
+ TIM4
+ desc TIM4
+ 4
+ 4
+ read-write
+
+
+ TIM5
+ desc TIM5
+ 5
+ 5
+ read-write
+
+
+ TIM6
+ desc TIM6
+ 6
+ 6
+ read-write
+
+
+ UART0
+ desc UART0
+ 7
+ 7
+ read-write
+
+
+ UART1
+ desc UART1
+ 8
+ 8
+ read-write
+
+
+ LPUART0
+ desc LPUART0
+ 9
+ 9
+ read-write
+
+
+ LPUART1
+ desc LPUART1
+ 10
+ 10
+ read-write
+
+
+ VC0
+ desc VC0
+ 11
+ 11
+ read-write
+
+
+ VC1
+ desc VC1
+ 12
+ 12
+ read-write
+
+
+ RTC
+ desc RTC
+ 13
+ 13
+ read-write
+
+
+ PCA
+ desc PCA
+ 14
+ 14
+ read-write
+
+
+ SPI0
+ desc SPI0
+ 15
+ 15
+ read-write
+
+
+ SPI1
+ desc SPI1
+ 16
+ 16
+ read-write
+
+
+ DMA
+ desc DMA
+ 17
+ 17
+ read-write
+
+
+ PA03
+ desc PA03
+ 18
+ 18
+ read-write
+
+
+ PB03
+ desc PB03
+ 19
+ 19
+ read-write
+
+
+ PC03
+ desc PC03
+ 20
+ 20
+ read-write
+
+
+ PD03
+ desc PD03
+ 21
+ 21
+ read-write
+
+
+ PA07
+ desc PA07
+ 22
+ 22
+ read-write
+
+
+ PB07
+ desc PB07
+ 23
+ 23
+ read-write
+
+
+ PC07
+ desc PC07
+ 24
+ 24
+ read-write
+
+
+ PD07
+ desc PD07
+ 25
+ 25
+ read-write
+
+
+ PA11
+ desc PA11
+ 26
+ 26
+ read-write
+
+
+ PB11
+ desc PB11
+ 27
+ 27
+ read-write
+
+
+ PC11
+ desc PC11
+ 28
+ 28
+ read-write
+
+
+ PA15
+ desc PA15
+ 29
+ 29
+ read-write
+
+
+ PB15
+ desc PB15
+ 30
+ 30
+ read-write
+
+
+ PC15
+ desc PC15
+ 31
+ 31
+ read-write
+
+
+
+
+ EXTTRIGGER1
+ desc EXTTRIGGER1
+ 0xBC
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ TIM0
+ desc TIM0
+ 0
+ 0
+ read-write
+
+
+ TIM1
+ desc TIM1
+ 1
+ 1
+ read-write
+
+
+ TIM2
+ desc TIM2
+ 2
+ 2
+ read-write
+
+
+ TIM3
+ desc TIM3
+ 3
+ 3
+ read-write
+
+
+ TIM4
+ desc TIM4
+ 4
+ 4
+ read-write
+
+
+ TIM5
+ desc TIM5
+ 5
+ 5
+ read-write
+
+
+ TIM6
+ desc TIM6
+ 6
+ 6
+ read-write
+
+
+ UART0
+ desc UART0
+ 7
+ 7
+ read-write
+
+
+ UART1
+ desc UART1
+ 8
+ 8
+ read-write
+
+
+ LPUART0
+ desc LPUART0
+ 9
+ 9
+ read-write
+
+
+ LPUART1
+ desc LPUART1
+ 10
+ 10
+ read-write
+
+
+ VC0
+ desc VC0
+ 11
+ 11
+ read-write
+
+
+ VC1
+ desc VC1
+ 12
+ 12
+ read-write
+
+
+ RTC
+ desc RTC
+ 13
+ 13
+ read-write
+
+
+ PCA
+ desc PCA
+ 14
+ 14
+ read-write
+
+
+ SPI0
+ desc SPI0
+ 15
+ 15
+ read-write
+
+
+ SPI1
+ desc SPI1
+ 16
+ 16
+ read-write
+
+
+ DMA
+ desc DMA
+ 17
+ 17
+ read-write
+
+
+ PA03
+ desc PA03
+ 18
+ 18
+ read-write
+
+
+ PB03
+ desc PB03
+ 19
+ 19
+ read-write
+
+
+ PC03
+ desc PC03
+ 20
+ 20
+ read-write
+
+
+ PD03
+ desc PD03
+ 21
+ 21
+ read-write
+
+
+ PA07
+ desc PA07
+ 22
+ 22
+ read-write
+
+
+ PB07
+ desc PB07
+ 23
+ 23
+ read-write
+
+
+ PC07
+ desc PC07
+ 24
+ 24
+ read-write
+
+
+ PD07
+ desc PD07
+ 25
+ 25
+ read-write
+
+
+ PA11
+ desc PA11
+ 26
+ 26
+ read-write
+
+
+ PB11
+ desc PB11
+ 27
+ 27
+ read-write
+
+
+ PC11
+ desc PC11
+ 28
+ 28
+ read-write
+
+
+ PA15
+ desc PA15
+ 29
+ 29
+ read-write
+
+
+ PB15
+ desc PB15
+ 30
+ 30
+ read-write
+
+
+ PC15
+ desc PC15
+ 31
+ 31
+ read-write
+
+
+
+
+ SGLSTART
+ desc SGLSTART
+ 0xC0
+ 32
+ read-write
+ 0x0
+ 0x1
+
+
+ START
+ desc START
+ 0
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SQRSTART
+ desc SQRSTART
+ 0xC4
+ 32
+ read-write
+ 0x0
+ 0x1
+
+
+ START
+ desc START
+ 0
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ JQRSTART
+ desc JQRSTART
+ 0xC8
+ 32
+ read-write
+ 0x0
+ 0x1
+
+
+ START
+ desc START
+ 0
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ALLSTART
+ desc ALLSTART
+ 0xCC
+ 32
+ read-write
+ 0x0
+ 0x1
+
+
+ START
+ desc START
+ 0
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ ADTIM4
+ desc ADTIM
+ 0x40003000
+
+ 0x0
+ 0x400
+
+
+
+ CNTER
+ desc CNTER
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PERAR
+ desc PERAR
+ 0x4
+ 32
+ read-write
+ 0xFFFF
+ 0xFFFF
+
+
+ PERA
+ desc PERA
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PERBR
+ desc PERBR
+ 0x8
+ 32
+ read-write
+ 0xFFFF
+ 0xFFFF
+
+
+ PERB
+ desc PERB
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ GCMAR
+ desc GCMAR
+ 0x10
+ 32
+ read-write
+ 0xFFFF
+ 0xFFFF
+
+
+ GCMA
+ desc GCMA
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ GCMBR
+ desc GCMBR
+ 0x14
+ 32
+ read-write
+ 0xFFFF
+ 0xFFFF
+
+
+ GCMB
+ desc GCMB
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ GCMCR
+ desc GCMCR
+ 0x18
+ 32
+ read-write
+ 0xFFFF
+ 0xFFFF
+
+
+ GCMC
+ desc GCMC
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ GCMDR
+ desc GCMDR
+ 0x1C
+ 32
+ read-write
+ 0xFFFF
+ 0xFFFF
+
+
+ GCMD
+ desc GCMD
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SCMAR
+ desc SCMAR
+ 0x28
+ 32
+ read-write
+ 0xFFFF
+ 0xFFFF
+
+
+ SCMA
+ desc SCMA
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SCMBR
+ desc SCMBR
+ 0x2C
+ 32
+ read-write
+ 0xFFFF
+ 0xFFFF
+
+
+ SCMB
+ desc SCMB
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DTUAR
+ desc DTUAR
+ 0x40
+ 32
+ read-write
+ 0xFFFF
+ 0xFFFF
+
+
+ DTUA
+ desc DTUA
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DTDAR
+ desc DTDAR
+ 0x44
+ 32
+ read-write
+ 0xFFFF
+ 0xFFFF
+
+
+ DTDA
+ desc DTDA
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ GCONR
+ desc GCONR
+ 0x50
+ 32
+ read-write
+ 0x100
+ 0xF017F
+
+
+ START
+ desc START
+ 0
+ 0
+ read-write
+
+
+ MODE
+ desc MODE
+ 3
+ 1
+ read-write
+
+
+ CKDIV
+ desc CKDIV
+ 6
+ 4
+ read-write
+
+
+ DIR
+ desc DIR
+ 8
+ 8
+ read-write
+
+
+ ZMSKREV
+ desc ZMSKREV
+ 16
+ 16
+ read-write
+
+
+ ZMSKPOS
+ desc ZMSKPOS
+ 17
+ 17
+ read-write
+
+
+ ZMSK
+ desc ZMSK
+ 19
+ 18
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICONR
+ desc ICONR
+ 0x54
+ 32
+ read-write
+ 0x0
+ 0xFC1CF
+
+
+ INTENA
+ desc INTENA
+ 0
+ 0
+ read-write
+
+
+ INTENB
+ desc INTENB
+ 1
+ 1
+ read-write
+
+
+ INTENC
+ desc INTENC
+ 2
+ 2
+ read-write
+
+
+ INTEND
+ desc INTEND
+ 3
+ 3
+ read-write
+
+
+ INTENOVF
+ desc INTENOVF
+ 6
+ 6
+ read-write
+
+
+ INTENUDF
+ desc INTENUDF
+ 7
+ 7
+ read-write
+
+
+ INTENDE
+ desc INTENDE
+ 8
+ 8
+ read-write
+
+
+ INTENSAML
+ desc INTENSAML
+ 14
+ 14
+ read-write
+
+
+ INTENSAMH
+ desc INTENSAMH
+ 15
+ 15
+ read-write
+
+
+ INTENSAU
+ desc INTENSAU
+ 16
+ 16
+ read-write
+
+
+ INTENSAD
+ desc INTENSAD
+ 17
+ 17
+ read-write
+
+
+ INTENSBU
+ desc INTENSBU
+ 18
+ 18
+ read-write
+
+
+ INTENSBD
+ desc INTENSBD
+ 19
+ 19
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCONR
+ desc PCONR
+ 0x58
+ 32
+ read-write
+ 0x0
+ 0x1FFF1FFF
+
+
+ CAPCA
+ desc CAPCA
+ 0
+ 0
+ read-write
+
+
+ STACA
+ desc STACA
+ 1
+ 1
+ read-write
+
+
+ STPCA
+ desc STPCA
+ 2
+ 2
+ read-write
+
+
+ STASTPSA
+ desc STASTPSA
+ 3
+ 3
+ read-write
+
+
+ CMPCA
+ desc CMPCA
+ 5
+ 4
+ read-write
+
+
+ PERCA
+ desc PERCA
+ 7
+ 6
+ read-write
+
+
+ OUTENA
+ desc OUTENA
+ 8
+ 8
+ read-write
+
+
+ DISSELA
+ desc DISSELA
+ 10
+ 9
+ read-write
+
+
+ DISVALA
+ desc DISVALA
+ 12
+ 11
+ read-write
+
+
+ CAPCB
+ desc CAPCB
+ 16
+ 16
+ read-write
+
+
+ STACB
+ desc STACB
+ 17
+ 17
+ read-write
+
+
+ STPCB
+ desc STPCB
+ 18
+ 18
+ read-write
+
+
+ STASTPSB
+ desc STASTPSB
+ 19
+ 19
+ read-write
+
+
+ CMPCB
+ desc CMPCB
+ 21
+ 20
+ read-write
+
+
+ PERCB
+ desc PERCB
+ 23
+ 22
+ read-write
+
+
+ OUTENB
+ desc OUTENB
+ 24
+ 24
+ read-write
+
+
+ DISSELB
+ desc DISSELB
+ 26
+ 25
+ read-write
+
+
+ DISVALB
+ desc DISVALB
+ 28
+ 27
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ BCONR
+ desc BCONR
+ 0x5C
+ 32
+ read-write
+ 0x0
+ 0x105
+
+
+ BENA
+ desc BENA
+ 0
+ 0
+ read-write
+
+
+ BENB
+ desc BENB
+ 2
+ 2
+ read-write
+
+
+ BENP
+ desc BENP
+ 8
+ 8
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DCONR
+ desc DCONR
+ 0x60
+ 32
+ read-write
+ 0x0
+ 0x101
+
+
+ DTCEN
+ desc DTCEN
+ 0
+ 0
+ read-write
+
+
+ SEPA
+ desc SEPA
+ 8
+ 8
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ FCONR
+ desc FCONR
+ 0x68
+ 32
+ read-write
+ 0x0
+ 0x77770077
+
+
+ NOFIENGA
+ desc NOFIENGA
+ 0
+ 0
+ read-write
+
+
+ NOFICKGA
+ desc NOFICKGA
+ 2
+ 1
+ read-write
+
+
+ NOFIENGB
+ desc NOFIENGB
+ 4
+ 4
+ read-write
+
+
+ NOFICKGB
+ desc NOFICKGB
+ 6
+ 5
+ read-write
+
+
+ NOFIENTA
+ desc NOFIENTA
+ 16
+ 16
+ read-write
+
+
+ NOFICKTA
+ desc NOFICKTA
+ 18
+ 17
+ read-write
+
+
+ NOFIENTB
+ desc NOFIENTB
+ 20
+ 20
+ read-write
+
+
+ NOFICKTB
+ desc NOFICKTB
+ 22
+ 21
+ read-write
+
+
+ NOFIENTC
+ desc NOFIENTC
+ 24
+ 24
+ read-write
+
+
+ NOFICKTC
+ desc NOFICKTC
+ 26
+ 25
+ read-write
+
+
+ NOFIENTD
+ desc NOFIENTD
+ 28
+ 28
+ read-write
+
+
+ NOFICKTD
+ desc NOFICKTD
+ 30
+ 29
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ VPERR
+ desc VPERR
+ 0x6C
+ 32
+ read-write
+ 0x0
+ 0x1F000F
+
+
+ GEPERIA
+ desc GEPERIA
+ 0
+ 0
+ read-write
+
+
+ GEPERIB
+ desc GEPERIB
+ 1
+ 1
+ read-write
+
+
+ GEPERIC
+ desc GEPERIC
+ 2
+ 2
+ read-write
+
+
+ GEPERID
+ desc GEPERID
+ 3
+ 3
+ read-write
+
+
+ PCNTE
+ desc PCNTE
+ 17
+ 16
+ read-write
+
+
+ PCNTS
+ desc PCNTS
+ 20
+ 18
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ STFLR
+ desc STFLR
+ 0x70
+ 32
+ read-write
+ 0x0
+ 0x80E01FCF
+
+
+ CMAF
+ desc CMAF
+ 0
+ 0
+ read-write
+
+
+ CMBF
+ desc CMBF
+ 1
+ 1
+ read-write
+
+
+ CMCF
+ desc CMCF
+ 2
+ 2
+ read-write
+
+
+ CMDF
+ desc CMDF
+ 3
+ 3
+ read-write
+
+
+ OVFF
+ desc OVFF
+ 6
+ 6
+ read-write
+
+
+ UDFF
+ desc UDFF
+ 7
+ 7
+ read-write
+
+
+ DTEF
+ desc DTEF
+ 8
+ 8
+ read-write
+
+
+ CMSAUF
+ desc CMSAUF
+ 9
+ 9
+ read-write
+
+
+ CMSADF
+ desc CMSADF
+ 10
+ 10
+ read-write
+
+
+ CMSBUF
+ desc CMSBUF
+ 11
+ 11
+ read-write
+
+
+ CMSBDF
+ desc CMSBDF
+ 12
+ 12
+ read-write
+
+
+ VPERNUM
+ desc VPERNUM
+ 23
+ 21
+ read-only
+
+
+ DIRF
+ desc DIRF
+ 31
+ 31
+ read-only
+
+
+
+
+ HSTAR
+ desc HSTAR
+ 0x74
+ 32
+ read-write
+ 0x0
+ 0x8000FFFF
+
+
+ HSTA0
+ desc HSTA0
+ 0
+ 0
+ read-write
+
+
+ HSTA1
+ desc HSTA1
+ 1
+ 1
+ read-write
+
+
+ HSTA2
+ desc HSTA2
+ 2
+ 2
+ read-write
+
+
+ HSTA3
+ desc HSTA3
+ 3
+ 3
+ read-write
+
+
+ HSTA4
+ desc HSTA4
+ 4
+ 4
+ read-write
+
+
+ HSTA5
+ desc HSTA5
+ 5
+ 5
+ read-write
+
+
+ HSTA6
+ desc HSTA6
+ 6
+ 6
+ read-write
+
+
+ HSTA7
+ desc HSTA7
+ 7
+ 7
+ read-write
+
+
+ HSTA8
+ desc HSTA8
+ 8
+ 8
+ read-write
+
+
+ HSTA9
+ desc HSTA9
+ 9
+ 9
+ read-write
+
+
+ HSTA10
+ desc HSTA10
+ 10
+ 10
+ read-write
+
+
+ HSTA11
+ desc HSTA11
+ 11
+ 11
+ read-write
+
+
+ HSTA12
+ desc HSTA12
+ 12
+ 12
+ read-write
+
+
+ HSTA13
+ desc HSTA13
+ 13
+ 13
+ read-write
+
+
+ HSTA14
+ desc HSTA14
+ 14
+ 14
+ read-write
+
+
+ HSTA15
+ desc HSTA15
+ 15
+ 15
+ read-write
+
+
+ STARTS
+ desc STARTS
+ 31
+ 31
+ read-write
+
+
+
+
+ HSTPR
+ desc HSTPR
+ 0x78
+ 32
+ read-write
+ 0x0
+ 0x8000FFFF
+
+
+ HSTP0
+ desc HSTP0
+ 0
+ 0
+ read-write
+
+
+ HSTP1
+ desc HSTP1
+ 1
+ 1
+ read-write
+
+
+ HSTP2
+ desc HSTP2
+ 2
+ 2
+ read-write
+
+
+ HSTP3
+ desc HSTP3
+ 3
+ 3
+ read-write
+
+
+ HSTP4
+ desc HSTP4
+ 4
+ 4
+ read-write
+
+
+ HSTP5
+ desc HSTP5
+ 5
+ 5
+ read-write
+
+
+ HSTP6
+ desc HSTP6
+ 6
+ 6
+ read-write
+
+
+ HSTP7
+ desc HSTP7
+ 7
+ 7
+ read-write
+
+
+ HSTP8
+ desc HSTP8
+ 8
+ 8
+ read-write
+
+
+ HSTP9
+ desc HSTP9
+ 9
+ 9
+ read-write
+
+
+ HSTP10
+ desc HSTP10
+ 10
+ 10
+ read-write
+
+
+ HSTP11
+ desc HSTP11
+ 11
+ 11
+ read-write
+
+
+ HSTP12
+ desc HSTP12
+ 12
+ 12
+ read-write
+
+
+ HSTP13
+ desc HSTP13
+ 13
+ 13
+ read-write
+
+
+ HSTP14
+ desc HSTP14
+ 14
+ 14
+ read-write
+
+
+ HSTP15
+ desc HSTP15
+ 15
+ 15
+ read-write
+
+
+ STOPS
+ desc STOPS
+ 31
+ 31
+ read-write
+
+
+
+
+ HCELR
+ desc HCELR
+ 0x7C
+ 32
+ read-write
+ 0x0
+ 0x8000FFFF
+
+
+ HCEL0
+ desc HCEL0
+ 0
+ 0
+ read-write
+
+
+ HCEL1
+ desc HCEL1
+ 1
+ 1
+ read-write
+
+
+ HCEL2
+ desc HCEL2
+ 2
+ 2
+ read-write
+
+
+ HCEL3
+ desc HCEL3
+ 3
+ 3
+ read-write
+
+
+ HCEL4
+ desc HCEL4
+ 4
+ 4
+ read-write
+
+
+ HCEL5
+ desc HCEL5
+ 5
+ 5
+ read-write
+
+
+ HCEL6
+ desc HCEL6
+ 6
+ 6
+ read-write
+
+
+ HCEL7
+ desc HCEL7
+ 7
+ 7
+ read-write
+
+
+ HCEL8
+ desc HCEL8
+ 8
+ 8
+ read-write
+
+
+ HCEL9
+ desc HCEL9
+ 9
+ 9
+ read-write
+
+
+ HCEL10
+ desc HCEL10
+ 10
+ 10
+ read-write
+
+
+ HCEL11
+ desc HCEL11
+ 11
+ 11
+ read-write
+
+
+ HCEL12
+ desc HCEL12
+ 12
+ 12
+ read-write
+
+
+ HCEL13
+ desc HCEL13
+ 13
+ 13
+ read-write
+
+
+ HCEL14
+ desc HCEL14
+ 14
+ 14
+ read-write
+
+
+ HCEL15
+ desc HCEL15
+ 15
+ 15
+ read-write
+
+
+ CLEARS
+ desc CLEARS
+ 31
+ 31
+ read-write
+
+
+
+
+ HCPAR
+ desc HCPAR
+ 0x80
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ HCPA0
+ desc HCPA0
+ 0
+ 0
+ read-write
+
+
+ HCPA1
+ desc HCPA1
+ 1
+ 1
+ read-write
+
+
+ HCPA2
+ desc HCPA2
+ 2
+ 2
+ read-write
+
+
+ HCPA3
+ desc HCPA3
+ 3
+ 3
+ read-write
+
+
+ HCPA4
+ desc HCPA4
+ 4
+ 4
+ read-write
+
+
+ HCPA5
+ desc HCPA5
+ 5
+ 5
+ read-write
+
+
+ HCPA6
+ desc HCPA6
+ 6
+ 6
+ read-write
+
+
+ HCPA7
+ desc HCPA7
+ 7
+ 7
+ read-write
+
+
+ HCPA8
+ desc HCPA8
+ 8
+ 8
+ read-write
+
+
+ HCPA9
+ desc HCPA9
+ 9
+ 9
+ read-write
+
+
+ HCPA10
+ desc HCPA10
+ 10
+ 10
+ read-write
+
+
+ HCPA11
+ desc HCPA11
+ 11
+ 11
+ read-write
+
+
+ HCPA12
+ desc HCPA12
+ 12
+ 12
+ read-write
+
+
+ HCPA13
+ desc HCPA13
+ 13
+ 13
+ read-write
+
+
+ HCPA14
+ desc HCPA14
+ 14
+ 14
+ read-write
+
+
+ HCPA15
+ desc HCPA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ HCPBR
+ desc HCPBR
+ 0x84
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ HCPB0
+ desc HCPB0
+ 0
+ 0
+ read-write
+
+
+ HCPB1
+ desc HCPB1
+ 1
+ 1
+ read-write
+
+
+ HCPB2
+ desc HCPB2
+ 2
+ 2
+ read-write
+
+
+ HCPB3
+ desc HCPB3
+ 3
+ 3
+ read-write
+
+
+ HCPB4
+ desc HCPB4
+ 4
+ 4
+ read-write
+
+
+ HCPB5
+ desc HCPB5
+ 5
+ 5
+ read-write
+
+
+ HCPB6
+ desc HCPB6
+ 6
+ 6
+ read-write
+
+
+ HCPB7
+ desc HCPB7
+ 7
+ 7
+ read-write
+
+
+ HCPB8
+ desc HCPB8
+ 8
+ 8
+ read-write
+
+
+ HCPB9
+ desc HCPB9
+ 9
+ 9
+ read-write
+
+
+ HCPB10
+ desc HCPB10
+ 10
+ 10
+ read-write
+
+
+ HCPB11
+ desc HCPB11
+ 11
+ 11
+ read-write
+
+
+ HCPB12
+ desc HCPB12
+ 12
+ 12
+ read-write
+
+
+ HCPB13
+ desc HCPB13
+ 13
+ 13
+ read-write
+
+
+ HCPB14
+ desc HCPB14
+ 14
+ 14
+ read-write
+
+
+ HCPB15
+ desc HCPB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ HCUPR
+ desc HCUPR
+ 0x88
+ 32
+ read-write
+ 0x0
+ 0xFFFFF
+
+
+ HCUP0
+ desc HCUP0
+ 0
+ 0
+ read-write
+
+
+ HCUP1
+ desc HCUP1
+ 1
+ 1
+ read-write
+
+
+ HCUP2
+ desc HCUP2
+ 2
+ 2
+ read-write
+
+
+ HCUP3
+ desc HCUP3
+ 3
+ 3
+ read-write
+
+
+ HCUP4
+ desc HCUP4
+ 4
+ 4
+ read-write
+
+
+ HCUP5
+ desc HCUP5
+ 5
+ 5
+ read-write
+
+
+ HCUP6
+ desc HCUP6
+ 6
+ 6
+ read-write
+
+
+ HCUP7
+ desc HCUP7
+ 7
+ 7
+ read-write
+
+
+ HCUP8
+ desc HCUP8
+ 8
+ 8
+ read-write
+
+
+ HCUP9
+ desc HCUP9
+ 9
+ 9
+ read-write
+
+
+ HCUP10
+ desc HCUP10
+ 10
+ 10
+ read-write
+
+
+ HCUP11
+ desc HCUP11
+ 11
+ 11
+ read-write
+
+
+ HCUP12
+ desc HCUP12
+ 12
+ 12
+ read-write
+
+
+ HCUP13
+ desc HCUP13
+ 13
+ 13
+ read-write
+
+
+ HCUP14
+ desc HCUP14
+ 14
+ 14
+ read-write
+
+
+ HCUP15
+ desc HCUP15
+ 15
+ 15
+ read-write
+
+
+ HCUP16
+ desc HCUP16
+ 16
+ 16
+ read-write
+
+
+ HCUP17
+ desc HCUP17
+ 17
+ 17
+ read-write
+
+
+ HCUP18
+ desc HCUP18
+ 18
+ 18
+ read-write
+
+
+ HCUP19
+ desc HCUP19
+ 19
+ 19
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ HCDOR
+ desc HCDOR
+ 0x8C
+ 32
+ read-write
+ 0x0
+ 0xFFFFF
+
+
+ HCDO0
+ desc HCDO0
+ 0
+ 0
+ read-write
+
+
+ HCDO1
+ desc HCDO1
+ 1
+ 1
+ read-write
+
+
+ HCDO2
+ desc HCDO2
+ 2
+ 2
+ read-write
+
+
+ HCDO3
+ desc HCDO3
+ 3
+ 3
+ read-write
+
+
+ HCDO4
+ desc HCDO4
+ 4
+ 4
+ read-write
+
+
+ HCDO5
+ desc HCDO5
+ 5
+ 5
+ read-write
+
+
+ HCDO6
+ desc HCDO6
+ 6
+ 6
+ read-write
+
+
+ HCDO7
+ desc HCDO7
+ 7
+ 7
+ read-write
+
+
+ HCDO8
+ desc HCDO8
+ 8
+ 8
+ read-write
+
+
+ HCDO9
+ desc HCDO9
+ 9
+ 9
+ read-write
+
+
+ HCDO10
+ desc HCDO10
+ 10
+ 10
+ read-write
+
+
+ HCDO11
+ desc HCDO11
+ 11
+ 11
+ read-write
+
+
+ HCDO12
+ desc HCDO12
+ 12
+ 12
+ read-write
+
+
+ HCDO13
+ desc HCDO13
+ 13
+ 13
+ read-write
+
+
+ HCDO14
+ desc HCDO14
+ 14
+ 14
+ read-write
+
+
+ HCDO15
+ desc HCDO15
+ 15
+ 15
+ read-write
+
+
+ HCDO16
+ desc HCDO16
+ 16
+ 16
+ read-write
+
+
+ HCDO17
+ desc HCDO17
+ 17
+ 17
+ read-write
+
+
+ HCDO18
+ desc HCDO18
+ 18
+ 18
+ read-write
+
+
+ HCDO19
+ desc HCDO19
+ 19
+ 19
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x100
+ 32
+ read-only
+ 0x0
+ 0xC1CF
+
+
+ CMAF
+ desc CMAF
+ 0
+ 0
+ read-only
+
+
+ CMBF
+ desc CMBF
+ 1
+ 1
+ read-only
+
+
+ CMCF
+ desc CMCF
+ 2
+ 2
+ read-only
+
+
+ CMDF
+ desc CMDF
+ 3
+ 3
+ read-only
+
+
+ OVFF
+ desc OVFF
+ 6
+ 6
+ read-only
+
+
+ UDFF
+ desc UDFF
+ 7
+ 7
+ read-only
+
+
+ DTEF
+ desc DTEF
+ 8
+ 8
+ read-only
+
+
+ SAMLF
+ desc SAMLF
+ 14
+ 14
+ read-only
+
+
+ SAMHF
+ desc SAMHF
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x104
+ 32
+ write-only
+ 0x0
+ 0xC1CF
+
+
+ CMAC
+ desc CMAC
+ 0
+ 0
+ write-only
+
+
+ CMBC
+ desc CMBC
+ 1
+ 1
+ write-only
+
+
+ CMCC
+ desc CMCC
+ 2
+ 2
+ write-only
+
+
+ CMDC
+ desc CMDC
+ 3
+ 3
+ write-only
+
+
+ OVFC
+ desc OVFC
+ 6
+ 6
+ write-only
+
+
+ UDFC
+ desc UDFC
+ 7
+ 7
+ write-only
+
+
+ DTEC
+ desc DTEC
+ 8
+ 8
+ write-only
+
+
+ SAMLC
+ desc SAMLC
+ 14
+ 14
+ write-only
+
+
+ SAMHC
+ desc SAMHC
+ 15
+ 15
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CR
+ desc CR
+ 0x108
+ 32
+ read-write
+ 0x300
+ 0x79FFCF
+
+
+ CMAE
+ desc CMAE
+ 0
+ 0
+ read-write
+
+
+ CMBE
+ desc CMBE
+ 1
+ 1
+ read-write
+
+
+ CMCE
+ desc CMCE
+ 2
+ 2
+ read-write
+
+
+ CMDE
+ desc CMDE
+ 3
+ 3
+ read-write
+
+
+ OVFE
+ desc OVFE
+ 6
+ 6
+ read-write
+
+
+ UDFE
+ desc UDFE
+ 7
+ 7
+ read-write
+
+
+ DITENA
+ desc DITENA
+ 8
+ 8
+ read-write
+
+
+ DITENB
+ desc DITENB
+ 9
+ 9
+ read-write
+
+
+ DITENS
+ desc DITENS
+ 10
+ 10
+ read-write
+
+
+ CMSAE
+ desc CMSAE
+ 11
+ 11
+ read-write
+
+
+ CMSBE
+ desc CMSBE
+ 12
+ 12
+ read-write
+
+
+ DMA_G_CMA
+ desc DMA_G_CMA
+ 13
+ 13
+ read-write
+
+
+ DMA_G_CMB
+ desc DMA_G_CMB
+ 14
+ 14
+ read-write
+
+
+ DMA_G_CMC
+ desc DMA_G_CMC
+ 15
+ 15
+ read-write
+
+
+ DMA_G_CMD
+ desc DMA_G_CMD
+ 16
+ 16
+ read-write
+
+
+ DMA_G_OVF
+ desc DMA_G_OVF
+ 19
+ 19
+ read-write
+
+
+ DMA_G_UDF
+ desc DMA_G_UDF
+ 20
+ 20
+ read-write
+
+
+ DMA_S_CMA
+ desc DMA_S_CMA
+ 21
+ 21
+ read-write
+
+
+ DMA_S_CMB
+ desc DMA_S_CMB
+ 22
+ 22
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ AOSSR
+ desc AOSSR
+ 0x110
+ 32
+ read-write
+ 0x0
+ 0x3F9F
+
+
+ FBRAKE
+ desc FBRAKE
+ 0
+ 0
+ read-only
+
+
+ FSAME
+ desc FSAME
+ 1
+ 1
+ read-only
+
+
+ BFILTS
+ desc BFILTS
+ 3
+ 2
+ read-write
+
+
+ BFILTEN
+ desc BFILTEN
+ 4
+ 4
+ read-write
+
+
+ SOFTBK
+ desc SOFTBK
+ 7
+ 7
+ read-write
+
+
+ SML0
+ desc SML0
+ 8
+ 8
+ read-write
+
+
+ SML1
+ desc SML1
+ 9
+ 9
+ read-write
+
+
+ SML2
+ desc SML2
+ 10
+ 10
+ read-write
+
+
+ SMH0
+ desc SMH0
+ 11
+ 11
+ read-write
+
+
+ SMH1
+ desc SMH1
+ 12
+ 12
+ read-write
+
+
+ SMH2
+ desc SMH2
+ 13
+ 13
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ AOSCL
+ desc AOSCL
+ 0x114
+ 32
+ write-only
+ 0x0
+ 0x3
+
+
+ FBRAKE
+ desc FBRAKE
+ 0
+ 0
+ write-only
+
+
+ FSAME
+ desc FSAME
+ 1
+ 1
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PTBKS
+ desc PTBKS
+ 0x118
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ EN0
+ desc EN0
+ 0
+ 0
+ read-write
+
+
+ EN1
+ desc EN1
+ 1
+ 1
+ read-write
+
+
+ EN2
+ desc EN2
+ 2
+ 2
+ read-write
+
+
+ EN3
+ desc EN3
+ 3
+ 3
+ read-write
+
+
+ EN4
+ desc EN4
+ 4
+ 4
+ read-write
+
+
+ EN5
+ desc EN5
+ 5
+ 5
+ read-write
+
+
+ EN6
+ desc EN6
+ 6
+ 6
+ read-write
+
+
+ EN7
+ desc EN7
+ 7
+ 7
+ read-write
+
+
+ EN8
+ desc EN8
+ 8
+ 8
+ read-write
+
+
+ EN9
+ desc EN9
+ 9
+ 9
+ read-write
+
+
+ EN10
+ desc EN10
+ 10
+ 10
+ read-write
+
+
+ EN11
+ desc EN11
+ 11
+ 11
+ read-write
+
+
+ EN12
+ desc EN12
+ 12
+ 12
+ read-write
+
+
+ EN13
+ desc EN13
+ 13
+ 13
+ read-write
+
+
+ EN14
+ desc EN14
+ 14
+ 14
+ read-write
+
+
+ EN15
+ desc EN15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ TTRIG
+ desc TTRIG
+ 0x11C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ TRIGAS
+ desc TRIGAS
+ 3
+ 0
+ read-write
+
+
+ TRIGBS
+ desc TRIGBS
+ 7
+ 4
+ read-write
+
+
+ TRIGCS
+ desc TRIGCS
+ 11
+ 8
+ read-write
+
+
+ TRIGDS
+ desc TRIGDS
+ 15
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ITRIG
+ desc ITRIG
+ 0x120
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ IAOS0S
+ desc IAOS0S
+ 3
+ 0
+ read-write
+
+
+ IAOS1S
+ desc IAOS1S
+ 7
+ 4
+ read-write
+
+
+ IAOS2S
+ desc IAOS2S
+ 11
+ 8
+ read-write
+
+
+ IAOS3S
+ desc IAOS3S
+ 15
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PTBKP
+ desc PTBKP
+ 0x124
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ POL0
+ desc POL0
+ 0
+ 0
+ read-write
+
+
+ POL1
+ desc POL1
+ 1
+ 1
+ read-write
+
+
+ POL2
+ desc POL2
+ 2
+ 2
+ read-write
+
+
+ POL3
+ desc POL3
+ 3
+ 3
+ read-write
+
+
+ POL4
+ desc POL4
+ 4
+ 4
+ read-write
+
+
+ POL5
+ desc POL5
+ 5
+ 5
+ read-write
+
+
+ POL6
+ desc POL6
+ 6
+ 6
+ read-write
+
+
+ POL7
+ desc POL7
+ 7
+ 7
+ read-write
+
+
+ POL8
+ desc POL8
+ 8
+ 8
+ read-write
+
+
+ POL9
+ desc POL9
+ 9
+ 9
+ read-write
+
+
+ POL10
+ desc POL10
+ 10
+ 10
+ read-write
+
+
+ POL11
+ desc POL11
+ 11
+ 11
+ read-write
+
+
+ POL12
+ desc POL12
+ 12
+ 12
+ read-write
+
+
+ POL13
+ desc POL13
+ 13
+ 13
+ read-write
+
+
+ POL14
+ desc POL14
+ 14
+ 14
+ read-write
+
+
+ POL15
+ desc POL15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SSTAR
+ desc SSTAR
+ 0x3F4
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SSTA0
+ desc SSTA0
+ 0
+ 0
+ read-write
+
+
+ SSTA1
+ desc SSTA1
+ 1
+ 1
+ read-write
+
+
+ SSTA2
+ desc SSTA2
+ 2
+ 2
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SSTPR
+ desc SSTPR
+ 0x3F8
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SSTP0
+ desc SSTP0
+ 0
+ 0
+ read-write
+
+
+ SSTP1
+ desc SSTP1
+ 1
+ 1
+ read-write
+
+
+ SSTP2
+ desc SSTP2
+ 2
+ 2
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SCLRR
+ desc SCLRR
+ 0x3FC
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SCLR0
+ desc SCLR0
+ 0
+ 0
+ read-write
+
+
+ SCLR1
+ desc SCLR1
+ 1
+ 1
+ read-write
+
+
+ SCLR2
+ desc SCLR2
+ 2
+ 2
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ ADTIM5
+ desc ADTIM
+ 0x40003400
+
+ 0x0
+ 0x400
+
+
+
+ ADTIM6
+ desc ADTIM
+ 0x40003800
+
+ 0x0
+ 0x400
+
+
+
+ AES
+ desc AES
+ 0x40021400
+
+ 0x0
+ 0x40
+
+
+
+ CR
+ desc CR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0x3
+
+
+ START
+ desc START
+ 0
+ 0
+ read-write
+
+
+ MODE
+ desc MODE
+ 1
+ 1
+ read-write
+
+
+ KEYSIZE
+ desc KEYSIZE
+ 4
+ 3
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DATA0
+ desc DATA0
+ 0x10
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ DATA0
+ desc DATA0
+ 31
+ 0
+ read-write
+
+
+
+
+ DATA1
+ desc DATA1
+ 0x14
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ DATA0
+ desc DATA0
+ 31
+ 0
+ read-write
+
+
+
+
+ DATA2
+ desc DATA2
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ DATA0
+ desc DATA0
+ 31
+ 0
+ read-write
+
+
+
+
+ DATA3
+ desc DATA3
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ DATA0
+ desc DATA0
+ 31
+ 0
+ read-write
+
+
+
+
+ KEY0
+ desc KEY0
+ 0x20
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ KEY0
+ desc KEY0
+ 31
+ 0
+ read-write
+
+
+
+
+ KEY1
+ desc KEY1
+ 0x24
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ KEY0
+ desc KEY0
+ 31
+ 0
+ read-write
+
+
+
+
+ KEY2
+ desc KEY2
+ 0x28
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ KEY0
+ desc KEY0
+ 31
+ 0
+ read-write
+
+
+
+
+ KEY3
+ desc KEY3
+ 0x2C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ KEY0
+ desc KEY0
+ 31
+ 0
+ read-write
+
+
+
+
+ KEY4
+ desc KEY4
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ KEY0
+ desc KEY0
+ 31
+ 0
+ read-write
+
+
+
+
+ KEY5
+ desc KEY5
+ 0x34
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ KEY0
+ desc KEY0
+ 31
+ 0
+ read-write
+
+
+
+
+ KEY6
+ desc KEY6
+ 0x38
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ KEY0
+ desc KEY0
+ 31
+ 0
+ read-write
+
+
+
+
+ KEY7
+ desc KEY7
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ KEY0
+ desc KEY0
+ 31
+ 0
+ read-write
+
+
+
+
+
+
+ BGR
+ desc BGR
+ 0x40002400
+ ADC
+
+ 0x0
+ 0x4
+
+
+
+ CR
+ desc CR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0x3
+
+
+ BGR_EN
+ desc BGR_EN
+ 0
+ 0
+ read-write
+
+
+ TS_EN
+ desc TS_EN
+ 1
+ 1
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ CLK_TRIM
+ desc CLK_TRIM
+ 0x40001800
+
+ 0x0
+ 0x1C
+
+
+
+ CR
+ desc CR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ TRIM_START
+ desc TRIM_START
+ 0
+ 0
+ read-write
+
+
+ REFCLK_SEL
+ desc REFCLK_SEL
+ 3
+ 1
+ read-write
+
+
+ CALCLK_SEL
+ desc CALCLK_SEL
+ 5
+ 4
+ read-write
+
+
+ MON_EN
+ desc MON_EN
+ 6
+ 6
+ read-write
+
+
+ IE
+ desc IE
+ 7
+ 7
+ read-write
+
+
+ CALCLK_SEL2
+ desc CALCLK_SEL2
+ 8
+ 8
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ REFCON
+ desc REFCON
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ RCNTVAL
+ desc RCNTVAL
+ 31
+ 0
+ read-write
+
+
+
+
+ REFCNT
+ desc REFCNT
+ 0x8
+ 32
+ read-only
+ 0x0
+ 0xFFFFFFFF
+
+
+ REFCNT
+ desc REFCNT
+ 31
+ 0
+ read-only
+
+
+
+
+ CALCNT
+ desc CALCNT
+ 0xC
+ 32
+ read-only
+ 0x0
+ 0xFFFFFFFF
+
+
+ CALCNT
+ desc CALCNT
+ 31
+ 0
+ read-only
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0xF
+
+
+ STOP
+ desc STOP
+ 0
+ 0
+ read-only
+
+
+ CALCNT_OF
+ desc CALCNT_OF
+ 1
+ 1
+ read-only
+
+
+ XTL_FAULT
+ desc XTL_FAULT
+ 2
+ 2
+ read-only
+
+
+ XTH_FAULT
+ desc XTH_FAULT
+ 3
+ 3
+ read-only
+
+
+ PLL_FAULT
+ desc PLL_FAULT
+ 4
+ 4
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ read-write
+ 0xC
+ 0xC
+
+
+ XTL_FAULT_CLR
+ desc XTL_FAULT_CLR
+ 2
+ 2
+ read-write
+
+
+ XTH_FAULT_CLR
+ desc XTH_FAULT_CLR
+ 3
+ 3
+ read-write
+
+
+ PLL_FAULT_CLR
+ desc PLL_FAULT_CLR
+ 4
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CALCON
+ desc CALCON
+ 0x18
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFFFFFF
+
+
+ CCNTVAL
+ desc CCNTVAL
+ 31
+ 0
+ read-write
+
+
+
+
+
+
+ CRC
+ desc CRC
+ 0x40020900
+
+ 0x0
+ 0x100
+
+
+
+ CR
+ desc CR
+ 0x0
+ 32
+ read-write
+ 0x1
+ 0x3
+
+
+ CR
+ desc CR
+ 0
+ 0
+ read-write
+
+
+ FLAG
+ desc FLAG
+ 1
+ 1
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ RESULT
+ desc RESULT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ RESULT
+ desc RESULT
+ 31
+ 0
+ read-write
+
+
+
+
+ DATA
+ desc DATA
+ 0x80
+ 32
+ write-only
+ 0x0
+ 0xFFFFFFFF
+
+
+ DATA
+ desc DATA
+ 31
+ 0
+ write-only
+
+
+
+
+
+
+ DAC
+ desc DAC
+ 0x40002500
+
+ 0x0
+ 0x3C
+
+
+
+ CR0
+ desc CR0
+ 0x0
+ 32
+ read-write
+ 0xC000C000
+ 0xFFFFFFFF
+
+
+ EN0
+ desc EN0
+ 0
+ 0
+ read-write
+
+
+ BOFF0
+ desc BOFF0
+ 1
+ 1
+ read-write
+
+
+ TEN0
+ desc TEN0
+ 2
+ 2
+ read-write
+
+
+ TSEL0
+ desc TSEL0
+ 5
+ 3
+ read-write
+
+
+ WAVE0
+ desc WAVE0
+ 7
+ 6
+ read-write
+
+
+ MAMP0
+ desc MAMP0
+ 11
+ 8
+ read-write
+
+
+ DMAEN0
+ desc DMAEN0
+ 12
+ 12
+ read-write
+
+
+ DMAUDRIE0
+ desc DMAUDRIE0
+ 13
+ 13
+ read-write
+
+
+ SREF0
+ desc SREF0
+ 15
+ 14
+ read-write
+
+
+
+
+ SWTRIGR
+ desc SWTRIGR
+ 0x4
+ 32
+ write-only
+ 0x0
+ 0x3
+
+
+ SWTRIG0
+ desc SWTRIG0
+ 0
+ 0
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DHR12R0
+ desc DHR12R0
+ 0x8
+ 32
+ read-write
+ 0x0
+ 0xFFF
+
+
+ DHR0
+ desc DHR0
+ 11
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DHR12L0
+ desc DHR12L0
+ 0xC
+ 32
+ read-write
+ 0x0
+ 0xFFF0
+
+
+ DHR0
+ desc DHR0
+ 15
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DHR8R0
+ desc DHR8R0
+ 0x10
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ DHR0
+ desc DHR0
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DOR0
+ desc DOR0
+ 0x2C
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ DOR0
+ desc DOR0
+ 11
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SR
+ desc SR
+ 0x34
+ 32
+ read-write
+ 0x4000
+ 0x20002000
+
+
+ DMAUDR0
+ desc DMAUDR0
+ 13
+ 13
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ETRS
+ desc ETRS
+ 0x38
+ 32
+ read-write
+ 0x0
+ 0x70
+
+
+ PTRIGSEL
+ desc PTRIGSEL
+ 6
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ DEBUG_ACTIVE
+ desc DEBUG_ACTIVE
+ 0x40002038
+
+ 0x0
+ 0x4
+
+
+
+ DEBUG_ACTIVE
+ desc DEBUG_ACTIVE
+ 0x0
+ 32
+ read-write
+ 0xFFF
+ 0xFFF
+
+
+ TIM0
+ desc TIM0
+ 0
+ 0
+ read-write
+
+
+ TIM1
+ desc TIM1
+ 1
+ 1
+ read-write
+
+
+ TIM2
+ desc TIM2
+ 2
+ 2
+ read-write
+
+
+ LPTIM0
+ desc LPTIM0
+ 3
+ 3
+ read-write
+
+
+ TIM4
+ desc TIM4
+ 4
+ 4
+ read-write
+
+
+ TIM5
+ desc TIM5
+ 5
+ 5
+ read-write
+
+
+ TIM6
+ desc TIM6
+ 6
+ 6
+ read-write
+
+
+ PCA
+ desc PCA
+ 7
+ 7
+ read-write
+
+
+ WDT
+ desc WDT
+ 8
+ 8
+ read-write
+
+
+ RTC
+ desc RTC
+ 9
+ 9
+ read-write
+
+
+ TIM3
+ desc TIM3
+ 11
+ 11
+ read-write
+
+
+ LPTIM1
+ desc LPTIM1
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ DMAC
+ desc DMAC
+ 0x40021000
+
+ 0x0
+ 0x30
+
+
+
+ CONF
+ desc CONF
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xDF000000
+
+
+ HALT
+ desc HALT
+ 27
+ 24
+ read-write
+
+
+ PRIO
+ desc PRIO
+ 28
+ 28
+ read-write
+
+
+ ST
+ desc ST
+ 30
+ 30
+ read-write
+
+
+ EN
+ desc EN
+ 31
+ 31
+ read-write
+
+
+
+
+ CONFA0
+ desc CONFA0
+ 0x10
+ 32
+ read-write
+ 0x0
+ 0xFF8FFFFF
+
+
+ TC
+ desc TC
+ 15
+ 0
+ read-write
+
+
+ BC
+ desc BC
+ 19
+ 16
+ read-write
+
+
+ TRI_SEL
+ desc TRI_SEL
+ 28
+ 22
+ read-write
+
+
+ ST
+ desc ST
+ 29
+ 29
+ read-write
+
+
+ PAS
+ desc PAS
+ 30
+ 30
+ read-write
+
+
+ ENS
+ desc ENS
+ 31
+ 31
+ read-write
+
+
+
+
+ CONFB0
+ desc CONFB0
+ 0x14
+ 32
+ read-write
+ 0x0
+ 0x3FFFFFF1
+
+
+ MSK
+ desc MSK
+ 0
+ 0
+ read-write
+
+
+ STAT
+ desc STAT
+ 18
+ 16
+ read-write
+
+
+ FIS_IE
+ desc FIS_IE
+ 19
+ 19
+ read-write
+
+
+ ERR_IE
+ desc ERR_IE
+ 20
+ 20
+ read-write
+
+
+ RD
+ desc RD
+ 21
+ 21
+ read-write
+
+
+ RS
+ desc RS
+ 22
+ 22
+ read-write
+
+
+ RC
+ desc RC
+ 23
+ 23
+ read-write
+
+
+ FD
+ desc FD
+ 24
+ 24
+ read-write
+
+
+ FS
+ desc FS
+ 25
+ 25
+ read-write
+
+
+ WIDTH
+ desc WIDTH
+ 27
+ 26
+ read-write
+
+
+ MODE
+ desc MODE
+ 29
+ 28
+ read-write
+
+
+
+
+ SRCADR0
+ desc SRCADR0
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ SRCADR
+ desc SRCADR
+ 31
+ 0
+ read-write
+
+
+
+
+ DSTADR0
+ desc DSTADR0
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ DSTADR
+ desc DSTADR
+ 31
+ 0
+ read-write
+
+
+
+
+ CONFA1
+ desc CONFA1
+ 0x20
+ 32
+ read-write
+ 0x0
+ 0xFF8FFFFF
+
+
+ TC
+ desc TC
+ 15
+ 0
+ read-write
+
+
+ BC
+ desc BC
+ 19
+ 16
+ read-write
+
+
+ TRI_SEL
+ desc TRI_SEL
+ 28
+ 22
+ read-write
+
+
+ ST
+ desc ST
+ 29
+ 29
+ read-write
+
+
+ PAS
+ desc PAS
+ 30
+ 30
+ read-write
+
+
+ ENS
+ desc ENS
+ 31
+ 31
+ read-write
+
+
+
+
+ CONFB1
+ desc CONFB1
+ 0x24
+ 32
+ read-write
+ 0x0
+ 0x3FFFFFF1
+
+
+ MSK
+ desc MSK
+ 0
+ 0
+ read-write
+
+
+ STAT
+ desc STAT
+ 18
+ 16
+ read-write
+
+
+ FIS_IE
+ desc FIS_IE
+ 19
+ 19
+ read-write
+
+
+ ERR_IE
+ desc ERR_IE
+ 20
+ 20
+ read-write
+
+
+ RD
+ desc RD
+ 21
+ 21
+ read-write
+
+
+ RS
+ desc RS
+ 22
+ 22
+ read-write
+
+
+ RC
+ desc RC
+ 23
+ 23
+ read-write
+
+
+ FD
+ desc FD
+ 24
+ 24
+ read-write
+
+
+ FS
+ desc FS
+ 25
+ 25
+ read-write
+
+
+ WIDTH
+ desc WIDTH
+ 27
+ 26
+ read-write
+
+
+ MODE
+ desc MODE
+ 29
+ 28
+ read-write
+
+
+
+
+ SRCADR1
+ desc SRCADR1
+ 0x28
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ SRCADR
+ desc SRCADR
+ 31
+ 0
+ read-write
+
+
+
+
+ DSTADR1
+ desc DSTADR1
+ 0x2C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ DSTADR
+ desc DSTADR
+ 31
+ 0
+ read-write
+
+
+
+
+
+
+ FLASH
+ desc FLASH
+ 0x40020000
+
+ 0x0
+ 0x38
+
+
+
+ TNVS
+ desc TNVS
+ 0x0
+ 32
+ read-write
+ 0x20
+ 0x1FF
+
+
+ TNVS
+ desc TNVS
+ 8
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 9
+ read-write
+
+
+
+
+ TPGS
+ desc TPGS
+ 0x4
+ 32
+ read-write
+ 0x17
+ 0xFF
+
+
+ TPGS
+ desc TPGS
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 8
+ read-write
+
+
+
+
+ TPROG
+ desc TPROG
+ 0x8
+ 32
+ read-write
+ 0x1B
+ 0xFF
+
+
+ TPROG
+ desc TPROG
+ 8
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 9
+ read-write
+
+
+
+
+ TSERASE
+ desc TSERASE
+ 0xC
+ 32
+ read-write
+ 0x4650
+ 0x3FFFF
+
+
+ TSERASE
+ desc TSERASE
+ 17
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 18
+ read-write
+
+
+
+
+ TMERASE
+ desc TMERASE
+ 0x10
+ 32
+ read-write
+ 0x222E0
+ 0x1FFFFF
+
+
+ TMERASE
+ desc TMERASE
+ 20
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 21
+ read-write
+
+
+
+
+ TPRCV
+ desc TPRCV
+ 0x14
+ 32
+ read-write
+ 0x18
+ 0xFFF
+
+
+ TPRCV
+ desc TPRCV
+ 11
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 12
+ read-write
+
+
+
+
+ TSRCV
+ desc TSRCV
+ 0x18
+ 32
+ read-write
+ 0xF0
+ 0xFFF
+
+
+ TSRCV
+ desc TSRCV
+ 11
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 12
+ read-write
+
+
+
+
+ TMRCV
+ desc TMRCV
+ 0x1C
+ 32
+ read-write
+ 0x3E8
+ 0x1FFF
+
+
+ TMRCV
+ desc TMRCV
+ 13
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 14
+ read-write
+
+
+
+
+ CR
+ desc CR
+ 0x20
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ OP
+ desc OP
+ 1
+ 0
+ read-write
+
+
+ WAIT
+ desc WAIT
+ 3
+ 2
+ read-write
+
+
+ BUSY
+ desc BUSY
+ 4
+ 4
+ read-only
+
+
+ IE
+ desc IE
+ 6
+ 5
+ read-write
+
+
+ DPSTB_EN
+ desc DPSTB_EN
+ 9
+ 9
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 10
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x24
+ 32
+ read-only
+ 0x0
+ 0x3
+
+
+ IF0
+ desc IF0
+ 0
+ 0
+ read-only
+
+
+ IF1
+ desc IF1
+ 1
+ 1
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 2
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x28
+ 32
+ write-only
+ 0x3
+ 0xFFFFFFFF
+
+
+ ICLR0
+ desc ICLR0
+ 0
+ 0
+ write-only
+
+
+ ICLR1
+ desc ICLR1
+ 1
+ 1
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 2
+ read-write
+
+
+
+
+ BYPASS
+ desc BYPASS
+ 0x2C
+ 32
+ write-only
+ 0x0
+ 0xFFFF
+
+
+ BYSEQ
+ desc BYSEQ
+ 15
+ 0
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 16
+ read-write
+
+
+
+
+ SLOCK0
+ desc SLOCK0
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ SLOCK
+ desc SLOCK
+ 31
+ 0
+ read-write
+
+
+
+
+ SLOCK1
+ desc SLOCK1
+ 0x34
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ SLOCK
+ desc SLOCK
+ 31
+ 0
+ read-write
+
+
+
+
+
+
+ GPIO
+ desc GPIO
+ 0x40020C00
+
+ 0x0
+ 0x1250
+
+
+
+ PA00_SEL
+ desc PA00_SEL
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA01_SEL
+ desc PA01_SEL
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA02_SEL
+ desc PA02_SEL
+ 0x8
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA03_SEL
+ desc PA03_SEL
+ 0xC
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA04_SEL
+ desc PA04_SEL
+ 0x10
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA05_SEL
+ desc PA05_SEL
+ 0x14
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA06_SEL
+ desc PA06_SEL
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA07_SEL
+ desc PA07_SEL
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA08_SEL
+ desc PA08_SEL
+ 0x20
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA09_SEL
+ desc PA09_SEL
+ 0x24
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA10_SEL
+ desc PA10_SEL
+ 0x28
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA11_SEL
+ desc PA11_SEL
+ 0x2C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA12_SEL
+ desc PA12_SEL
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA13_SEL
+ desc PA13_SEL
+ 0x34
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA14_SEL
+ desc PA14_SEL
+ 0x38
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA15_SEL
+ desc PA15_SEL
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB00_SEL
+ desc PB00_SEL
+ 0x40
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB01_SEL
+ desc PB01_SEL
+ 0x44
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB02_SEL
+ desc PB02_SEL
+ 0x48
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB03_SEL
+ desc PB03_SEL
+ 0x4C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB04_SEL
+ desc PB04_SEL
+ 0x50
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB05_SEL
+ desc PB05_SEL
+ 0x54
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB06_SEL
+ desc PB06_SEL
+ 0x58
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB07_SEL
+ desc PB07_SEL
+ 0x5C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB08_SEL
+ desc PB08_SEL
+ 0x60
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB09_SEL
+ desc PB09_SEL
+ 0x64
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB10_SEL
+ desc PB10_SEL
+ 0x68
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB11_SEL
+ desc PB11_SEL
+ 0x6C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB12_SEL
+ desc PB12_SEL
+ 0x70
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB13_SEL
+ desc PB13_SEL
+ 0x74
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB14_SEL
+ desc PB14_SEL
+ 0x78
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB15_SEL
+ desc PB15_SEL
+ 0x7C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC00_SEL
+ desc PC00_SEL
+ 0x80
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC01_SEL
+ desc PC01_SEL
+ 0x84
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC02_SEL
+ desc PC02_SEL
+ 0x88
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC03_SEL
+ desc PC03_SEL
+ 0x8C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC04_SEL
+ desc PC04_SEL
+ 0x90
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC05_SEL
+ desc PC05_SEL
+ 0x94
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC06_SEL
+ desc PC06_SEL
+ 0x98
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC07_SEL
+ desc PC07_SEL
+ 0x9C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC08_SEL
+ desc PC08_SEL
+ 0xA0
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC09_SEL
+ desc PC09_SEL
+ 0xA4
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC10_SEL
+ desc PC10_SEL
+ 0xA8
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC11_SEL
+ desc PC11_SEL
+ 0xAC
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC12_SEL
+ desc PC12_SEL
+ 0xB0
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC13_SEL
+ desc PC13_SEL
+ 0xB4
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC14_SEL
+ desc PC14_SEL
+ 0xB8
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC15_SEL
+ desc PC15_SEL
+ 0xBC
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD00_SEL
+ desc PD00_SEL
+ 0xC0
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD01_SEL
+ desc PD01_SEL
+ 0xC4
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD02_SEL
+ desc PD02_SEL
+ 0xC8
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD03_SEL
+ desc PD03_SEL
+ 0xCC
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD04_SEL
+ desc PD04_SEL
+ 0xD0
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD05_SEL
+ desc PD05_SEL
+ 0xD4
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD06_SEL
+ desc PD06_SEL
+ 0xD8
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD07_SEL
+ desc PD07_SEL
+ 0xDC
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD08_SEL
+ desc PD08_SEL
+ 0xE0
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD09_SEL
+ desc PD09_SEL
+ 0xE4
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD10_SEL
+ desc PD10_SEL
+ 0xE8
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD11_SEL
+ desc PD11_SEL
+ 0xEC
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD12_SEL
+ desc PD12_SEL
+ 0xF0
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD13_SEL
+ desc PD13_SEL
+ 0xF4
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD14_SEL
+ desc PD14_SEL
+ 0xF8
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD15_SEL
+ desc PD15_SEL
+ 0xFC
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PADIR
+ desc PADIR
+ 0x100
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PAIN
+ desc PAIN
+ 0x104
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-only
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-only
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-only
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-only
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-only
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-only
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-only
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-only
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-only
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-only
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-only
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-only
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-only
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-only
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-only
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PAOUT
+ desc PAOUT
+ 0x108
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PAADS
+ desc PAADS
+ 0x10C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PABSET
+ desc PABSET
+ 0x110
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PABCLR
+ desc PABCLR
+ 0x114
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PABSETCLR
+ desc PABSETCLR
+ 0x118
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ PABCLR
+ desc PABCLR
+ 15
+ 0
+ read-write
+
+
+ PABSET
+ desc PABSET
+ 31
+ 16
+ read-write
+
+
+
+
+ PADR
+ desc PADR
+ 0x11C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PAPU
+ desc PAPU
+ 0x120
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PAPD
+ desc PAPD
+ 0x124
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PAOD
+ desc PAOD
+ 0x12C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PAHIE
+ desc PAHIE
+ 0x130
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PALIE
+ desc PALIE
+ 0x134
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PARIE
+ desc PARIE
+ 0x138
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PAFIE
+ desc PAFIE
+ 0x13C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBDIR
+ desc PBDIR
+ 0x140
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBIN
+ desc PBIN
+ 0x144
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-only
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-only
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-only
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-only
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-only
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-only
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-only
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-only
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-only
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-only
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-only
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-only
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-only
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-only
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-only
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PBOUT
+ desc PBOUT
+ 0x148
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBADS
+ desc PBADS
+ 0x14C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBBSET
+ desc PBBSET
+ 0x150
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBBCLR
+ desc PBBCLR
+ 0x154
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBBSETCLR
+ desc PBBSETCLR
+ 0x158
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ PBBCLR
+ desc PBBCLR
+ 15
+ 0
+ read-write
+
+
+ PBBSET
+ desc PBBSET
+ 31
+ 16
+ read-write
+
+
+
+
+ PBDR
+ desc PBDR
+ 0x15C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBPU
+ desc PBPU
+ 0x160
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBPD
+ desc PBPD
+ 0x164
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBOD
+ desc PBOD
+ 0x16C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBHIE
+ desc PBHIE
+ 0x170
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBLIE
+ desc PBLIE
+ 0x174
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBRIE
+ desc PBRIE
+ 0x178
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PBFIE
+ desc PBFIE
+ 0x17C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCDIR
+ desc PCDIR
+ 0x180
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCIN
+ desc PCIN
+ 0x184
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-only
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-only
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-only
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-only
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-only
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-only
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-only
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-only
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-only
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-only
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-only
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-only
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-only
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-only
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-only
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PCOUT
+ desc PCOUT
+ 0x188
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCADS
+ desc PCADS
+ 0x18C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCBSET
+ desc PCBSET
+ 0x190
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCBCLR
+ desc PCBCLR
+ 0x194
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCBSETCLR
+ desc PCBSETCLR
+ 0x198
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ PCBCLR
+ desc PCBCLR
+ 15
+ 0
+ read-write
+
+
+ PCBSET
+ desc PCBSET
+ 31
+ 16
+ read-write
+
+
+
+
+ PCDR
+ desc PCDR
+ 0x19C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCPU
+ desc PCPU
+ 0x1A0
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCPD
+ desc PCPD
+ 0x1A4
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCOD
+ desc PCOD
+ 0x1AC
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCHIE
+ desc PCHIE
+ 0x1B0
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCLIE
+ desc PCLIE
+ 0x1B4
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCRIE
+ desc PCRIE
+ 0x1B8
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCFIE
+ desc PCFIE
+ 0x1BC
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDDIR
+ desc PDDIR
+ 0x1C0
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDIN
+ desc PDIN
+ 0x1C4
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-only
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-only
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-only
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-only
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-only
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-only
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-only
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-only
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-only
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-only
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-only
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-only
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-only
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-only
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-only
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PDOUT
+ desc PDOUT
+ 0x1C8
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDADS
+ desc PDADS
+ 0x1CC
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDBSET
+ desc PDBSET
+ 0x1D0
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDBCLR
+ desc PDBCLR
+ 0x1D4
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDBSETCLR
+ desc PDBSETCLR
+ 0x1D8
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ PDBCLR
+ desc PDBCLR
+ 15
+ 0
+ read-write
+
+
+ PDBSET
+ desc PDBSET
+ 31
+ 16
+ read-write
+
+
+
+
+ PDDR
+ desc PDDR
+ 0x1DC
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDPU
+ desc PDPU
+ 0x1E0
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDPD
+ desc PDPD
+ 0x1E4
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDOD
+ desc PDOD
+ 0x1EC
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDHIE
+ desc PDHIE
+ 0x1F0
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDLIE
+ desc PDLIE
+ 0x1F4
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDRIE
+ desc PDRIE
+ 0x1F8
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PDFIE
+ desc PDFIE
+ 0x1FC
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PA_STAT
+ desc PA_STAT
+ 0x200
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-only
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-only
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-only
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-only
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-only
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-only
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-only
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-only
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-only
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-only
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-only
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-only
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-only
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-only
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-only
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PA_ICLR
+ desc PA_ICLR
+ 0x210
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PA00
+ desc PA00
+ 0
+ 0
+ read-write
+
+
+ PA01
+ desc PA01
+ 1
+ 1
+ read-write
+
+
+ PA02
+ desc PA02
+ 2
+ 2
+ read-write
+
+
+ PA03
+ desc PA03
+ 3
+ 3
+ read-write
+
+
+ PA04
+ desc PA04
+ 4
+ 4
+ read-write
+
+
+ PA05
+ desc PA05
+ 5
+ 5
+ read-write
+
+
+ PA06
+ desc PA06
+ 6
+ 6
+ read-write
+
+
+ PA07
+ desc PA07
+ 7
+ 7
+ read-write
+
+
+ PA08
+ desc PA08
+ 8
+ 8
+ read-write
+
+
+ PA09
+ desc PA09
+ 9
+ 9
+ read-write
+
+
+ PA10
+ desc PA10
+ 10
+ 10
+ read-write
+
+
+ PA11
+ desc PA11
+ 11
+ 11
+ read-write
+
+
+ PA12
+ desc PA12
+ 12
+ 12
+ read-write
+
+
+ PA13
+ desc PA13
+ 13
+ 13
+ read-write
+
+
+ PA14
+ desc PA14
+ 14
+ 14
+ read-write
+
+
+ PA15
+ desc PA15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PB_STAT
+ desc PB_STAT
+ 0x240
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-only
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-only
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-only
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-only
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-only
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-only
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-only
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-only
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-only
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-only
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-only
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-only
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-only
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-only
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-only
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PB_ICLR
+ desc PB_ICLR
+ 0x250
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PB00
+ desc PB00
+ 0
+ 0
+ read-write
+
+
+ PB01
+ desc PB01
+ 1
+ 1
+ read-write
+
+
+ PB02
+ desc PB02
+ 2
+ 2
+ read-write
+
+
+ PB03
+ desc PB03
+ 3
+ 3
+ read-write
+
+
+ PB04
+ desc PB04
+ 4
+ 4
+ read-write
+
+
+ PB05
+ desc PB05
+ 5
+ 5
+ read-write
+
+
+ PB06
+ desc PB06
+ 6
+ 6
+ read-write
+
+
+ PB07
+ desc PB07
+ 7
+ 7
+ read-write
+
+
+ PB08
+ desc PB08
+ 8
+ 8
+ read-write
+
+
+ PB09
+ desc PB09
+ 9
+ 9
+ read-write
+
+
+ PB10
+ desc PB10
+ 10
+ 10
+ read-write
+
+
+ PB11
+ desc PB11
+ 11
+ 11
+ read-write
+
+
+ PB12
+ desc PB12
+ 12
+ 12
+ read-write
+
+
+ PB13
+ desc PB13
+ 13
+ 13
+ read-write
+
+
+ PB14
+ desc PB14
+ 14
+ 14
+ read-write
+
+
+ PB15
+ desc PB15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PC_STAT
+ desc PC_STAT
+ 0x280
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-only
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-only
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-only
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-only
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-only
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-only
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-only
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-only
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-only
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-only
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-only
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-only
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-only
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-only
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-only
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PC_ICLR
+ desc PC_ICLR
+ 0x290
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PC00
+ desc PC00
+ 0
+ 0
+ read-write
+
+
+ PC01
+ desc PC01
+ 1
+ 1
+ read-write
+
+
+ PC02
+ desc PC02
+ 2
+ 2
+ read-write
+
+
+ PC03
+ desc PC03
+ 3
+ 3
+ read-write
+
+
+ PC04
+ desc PC04
+ 4
+ 4
+ read-write
+
+
+ PC05
+ desc PC05
+ 5
+ 5
+ read-write
+
+
+ PC06
+ desc PC06
+ 6
+ 6
+ read-write
+
+
+ PC07
+ desc PC07
+ 7
+ 7
+ read-write
+
+
+ PC08
+ desc PC08
+ 8
+ 8
+ read-write
+
+
+ PC09
+ desc PC09
+ 9
+ 9
+ read-write
+
+
+ PC10
+ desc PC10
+ 10
+ 10
+ read-write
+
+
+ PC11
+ desc PC11
+ 11
+ 11
+ read-write
+
+
+ PC12
+ desc PC12
+ 12
+ 12
+ read-write
+
+
+ PC13
+ desc PC13
+ 13
+ 13
+ read-write
+
+
+ PC14
+ desc PC14
+ 14
+ 14
+ read-write
+
+
+ PC15
+ desc PC15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PD_STAT
+ desc PD_STAT
+ 0x2C0
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-only
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-only
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-only
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-only
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-only
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-only
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-only
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-only
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-only
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-only
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-only
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-only
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-only
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-only
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-only
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PD_ICLR
+ desc PD_ICLR
+ 0x2D0
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PD00
+ desc PD00
+ 0
+ 0
+ read-write
+
+
+ PD01
+ desc PD01
+ 1
+ 1
+ read-write
+
+
+ PD02
+ desc PD02
+ 2
+ 2
+ read-write
+
+
+ PD03
+ desc PD03
+ 3
+ 3
+ read-write
+
+
+ PD04
+ desc PD04
+ 4
+ 4
+ read-write
+
+
+ PD05
+ desc PD05
+ 5
+ 5
+ read-write
+
+
+ PD06
+ desc PD06
+ 6
+ 6
+ read-write
+
+
+ PD07
+ desc PD07
+ 7
+ 7
+ read-write
+
+
+ PD08
+ desc PD08
+ 8
+ 8
+ read-write
+
+
+ PD09
+ desc PD09
+ 9
+ 9
+ read-write
+
+
+ PD10
+ desc PD10
+ 10
+ 10
+ read-write
+
+
+ PD11
+ desc PD11
+ 11
+ 11
+ read-write
+
+
+ PD12
+ desc PD12
+ 12
+ 12
+ read-write
+
+
+ PD13
+ desc PD13
+ 13
+ 13
+ read-write
+
+
+ PD14
+ desc PD14
+ 14
+ 14
+ read-write
+
+
+ PD15
+ desc PD15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CTRL0
+ desc CTRL0
+ 0x300
+ 32
+ read-write
+ 0x1
+ 0x1
+
+
+ IESEL
+ desc IESEL
+ 0
+ 0
+ read-write
+
+
+
+
+ CTRL1
+ desc CTRL1
+ 0x304
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ EXT_CLK_SEL
+ desc EXT_CLK_SEL
+ 3
+ 0
+ read-write
+
+
+ SSN0_SEL
+ desc SSN0_SEL
+ 7
+ 4
+ read-write
+
+
+ PCLK_SEL
+ desc PCLK_SEL
+ 9
+ 8
+ read-write
+
+
+ HCLK_SEL
+ desc HCLK_SEL
+ 11
+ 10
+ read-write
+
+
+ PCLK_EN
+ desc PCLK_EN
+ 12
+ 12
+ read-write
+
+
+ HCLK_EN
+ desc HCLK_EN
+ 13
+ 13
+ read-write
+
+
+ IR_POL
+ desc IR_POL
+ 14
+ 14
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CTRL2
+ desc CTRL2
+ 0x308
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ SSN1_SEL
+ desc SSN1_SEL
+ 3
+ 0
+ read-write
+
+
+ TCLK_SEL
+ desc TCLK_SEL
+ 5
+ 4
+ read-write
+
+
+ TCLK_DIV
+ desc TCLK_DIV
+ 7
+ 6
+ read-write
+
+
+ AHB_SEL
+ desc AHB_SEL
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ TIMGS
+ desc TIMGS
+ 0x30C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ TIM0_G
+ desc TIM0_G
+ 2
+ 0
+ read-write
+
+
+ TIM1_G
+ desc TIM1_G
+ 5
+ 3
+ read-write
+
+
+ TIM2_G
+ desc TIM2_G
+ 8
+ 6
+ read-write
+
+
+ TIM3_G
+ desc TIM3_G
+ 11
+ 9
+ read-write
+
+
+ LPTIM0_G
+ desc LPTIM0_G
+ 14
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ TIMES
+ desc TIMES
+ 0x310
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ TIM0_E
+ desc TIM0_E
+ 2
+ 0
+ read-write
+
+
+ TIM1_E
+ desc TIM1_E
+ 5
+ 3
+ read-write
+
+
+ TIM2_E
+ desc TIM2_E
+ 8
+ 6
+ read-write
+
+
+ TIM3_E
+ desc TIM3_E
+ 11
+ 9
+ read-write
+
+
+ LPTIM0_E
+ desc LPTIM0_E
+ 14
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ TIMCPS
+ desc TIMCPS
+ 0x314
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ TIM0_CA
+ desc TIM0_CA
+ 2
+ 0
+ read-write
+
+
+ TIM1_CA
+ desc TIM1_CA
+ 5
+ 3
+ read-write
+
+
+ TIM2_CA
+ desc TIM2_CA
+ 8
+ 6
+ read-write
+
+
+ TIM3_CA
+ desc TIM3_CA
+ 11
+ 9
+ read-write
+
+
+ TIM3_CB
+ desc TIM3_CB
+ 14
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCAS
+ desc PCAS
+ 0x318
+ 32
+ read-write
+ 0x0
+ 0xFFF
+
+
+ PCA_CH0
+ desc PCA_CH0
+ 2
+ 0
+ read-write
+
+
+ PCA_ECI
+ desc PCA_ECI
+ 5
+ 3
+ read-write
+
+
+ LPTIM1_G
+ desc LPTIM1_G
+ 8
+ 6
+ read-write
+
+
+ LPTIM1_E
+ desc LPTIM1_E
+ 11
+ 9
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PCNT
+ desc PCNT
+ 0x31C
+ 32
+ read-write
+ 0x0
+ 0xF
+
+
+ PCNT_S0
+ desc PCNT_S0
+ 1
+ 0
+ read-write
+
+
+ PCNT_S1
+ desc PCNT_S1
+ 3
+ 2
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE00_SEL
+ desc PE00_SEL
+ 0x1000
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE01_SEL
+ desc PE01_SEL
+ 0x1004
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE02_SEL
+ desc PE02_SEL
+ 0x1008
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE03_SEL
+ desc PE03_SEL
+ 0x100C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE04_SEL
+ desc PE04_SEL
+ 0x1010
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE05_SEL
+ desc PE05_SEL
+ 0x1014
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE06_SEL
+ desc PE06_SEL
+ 0x1018
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE07_SEL
+ desc PE07_SEL
+ 0x101C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE08_SEL
+ desc PE08_SEL
+ 0x1020
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE09_SEL
+ desc PE09_SEL
+ 0x1024
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE10_SEL
+ desc PE10_SEL
+ 0x1028
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE11_SEL
+ desc PE11_SEL
+ 0x102C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE12_SEL
+ desc PE12_SEL
+ 0x1030
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE13_SEL
+ desc PE13_SEL
+ 0x1034
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE14_SEL
+ desc PE14_SEL
+ 0x1038
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE15_SEL
+ desc PE15_SEL
+ 0x103C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF00_SEL
+ desc PF00_SEL
+ 0x1040
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF01_SEL
+ desc PF01_SEL
+ 0x1044
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF02_SEL
+ desc PF02_SEL
+ 0x1048
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF03_SEL
+ desc PF03_SEL
+ 0x104C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF04_SEL
+ desc PF04_SEL
+ 0x1050
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF05_SEL
+ desc PF05_SEL
+ 0x1054
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF06_SEL
+ desc PF06_SEL
+ 0x1058
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF07_SEL
+ desc PF07_SEL
+ 0x105C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF08_SEL
+ desc PF08_SEL
+ 0x1060
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF09_SEL
+ desc PF09_SEL
+ 0x1064
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF10_SEL
+ desc PF10_SEL
+ 0x1068
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF11_SEL
+ desc PF11_SEL
+ 0x106C
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ SEL
+ desc SEL
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PEDIR
+ desc PEDIR
+ 0x1100
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PEIN
+ desc PEIN
+ 0x1104
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-only
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-only
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-only
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-only
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-only
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-only
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-only
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-only
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-only
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-only
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-only
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-only
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-only
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-only
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-only
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PEOUT
+ desc PEOUT
+ 0x1108
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PEADS
+ desc PEADS
+ 0x110C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PEBSET
+ desc PEBSET
+ 0x1110
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PEBCLR
+ desc PEBCLR
+ 0x1114
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PEBSETCLR
+ desc PEBSETCLR
+ 0x1118
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ PEBCLR
+ desc PEBCLR
+ 15
+ 0
+ read-write
+
+
+ PEBSET
+ desc PEBSET
+ 31
+ 16
+ read-write
+
+
+
+
+ PEDR
+ desc PEDR
+ 0x111C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PEPU
+ desc PEPU
+ 0x1120
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PEPD
+ desc PEPD
+ 0x1124
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PEOD
+ desc PEOD
+ 0x112C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PEHIE
+ desc PEHIE
+ 0x1130
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PELIE
+ desc PELIE
+ 0x1134
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PERIE
+ desc PERIE
+ 0x1138
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PEFIE
+ desc PEFIE
+ 0x113C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFDIR
+ desc PFDIR
+ 0x1140
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFIN
+ desc PFIN
+ 0x1144
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-only
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-only
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-only
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-only
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-only
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-only
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-only
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-only
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-only
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-only
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-only
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PFOUT
+ desc PFOUT
+ 0x1148
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFADS
+ desc PFADS
+ 0x114C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFBSET
+ desc PFBSET
+ 0x1150
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFBCLR
+ desc PFBCLR
+ 0x1154
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFBSETCLR
+ desc PFBSETCLR
+ 0x1158
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ PFBCLR
+ desc PFBCLR
+ 11
+ 0
+ read-write
+
+
+ PFBSET
+ desc PFBSET
+ 27
+ 16
+ read-write
+
+
+
+
+ PFDR
+ desc PFDR
+ 0x115C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFPU
+ desc PFPU
+ 0x1160
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFPD
+ desc PFPD
+ 0x1164
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFOD
+ desc PFOD
+ 0x116C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFHIE
+ desc PFHIE
+ 0x1170
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFLIE
+ desc PFLIE
+ 0x1174
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFRIE
+ desc PFRIE
+ 0x1178
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PFFIE
+ desc PFFIE
+ 0x117C
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PE_STAT
+ desc PE_STAT
+ 0x1200
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-only
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-only
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-only
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-only
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-only
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-only
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-only
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-only
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-only
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-only
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-only
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-only
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-only
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-only
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-only
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PE_ICLR
+ desc PE_ICLR
+ 0x1210
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFF
+
+
+ PE00
+ desc PE00
+ 0
+ 0
+ read-write
+
+
+ PE01
+ desc PE01
+ 1
+ 1
+ read-write
+
+
+ PE02
+ desc PE02
+ 2
+ 2
+ read-write
+
+
+ PE03
+ desc PE03
+ 3
+ 3
+ read-write
+
+
+ PE04
+ desc PE04
+ 4
+ 4
+ read-write
+
+
+ PE05
+ desc PE05
+ 5
+ 5
+ read-write
+
+
+ PE06
+ desc PE06
+ 6
+ 6
+ read-write
+
+
+ PE07
+ desc PE07
+ 7
+ 7
+ read-write
+
+
+ PE08
+ desc PE08
+ 8
+ 8
+ read-write
+
+
+ PE09
+ desc PE09
+ 9
+ 9
+ read-write
+
+
+ PE10
+ desc PE10
+ 10
+ 10
+ read-write
+
+
+ PE11
+ desc PE11
+ 11
+ 11
+ read-write
+
+
+ PE12
+ desc PE12
+ 12
+ 12
+ read-write
+
+
+ PE13
+ desc PE13
+ 13
+ 13
+ read-write
+
+
+ PE14
+ desc PE14
+ 14
+ 14
+ read-write
+
+
+ PE15
+ desc PE15
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PF_STAT
+ desc PF_STAT
+ 0x1240
+ 32
+ read-only
+ 0x0
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-only
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-only
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-only
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-only
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-only
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-only
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-only
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-only
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-only
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-only
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-only
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ PF_ICLR
+ desc PF_ICLR
+ 0x1250
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFF
+
+
+ PF00
+ desc PF00
+ 0
+ 0
+ read-write
+
+
+ PF01
+ desc PF01
+ 1
+ 1
+ read-write
+
+
+ PF02
+ desc PF02
+ 2
+ 2
+ read-write
+
+
+ PF03
+ desc PF03
+ 3
+ 3
+ read-write
+
+
+ PF04
+ desc PF04
+ 4
+ 4
+ read-write
+
+
+ PF05
+ desc PF05
+ 5
+ 5
+ read-write
+
+
+ PF06
+ desc PF06
+ 6
+ 6
+ read-write
+
+
+ PF07
+ desc PF07
+ 7
+ 7
+ read-write
+
+
+ PF08
+ desc PF08
+ 8
+ 8
+ read-write
+
+
+ PF09
+ desc PF09
+ 9
+ 9
+ read-write
+
+
+ PF10
+ desc PF10
+ 10
+ 10
+ read-write
+
+
+ PF11
+ desc PF11
+ 11
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ I2C0
+ desc I2C
+ 0x40000400
+
+ 0x0
+ 0x18
+
+
+
+ TMRUN
+ desc TMRUN
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0x1
+
+
+ TME
+ desc TME
+ 0
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ TM
+ desc TM
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ TM
+ desc TM
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CR
+ desc CR
+ 0x8
+ 32
+ read-write
+ 0x0
+ 0x7D
+
+
+ H1M
+ desc H1M
+ 0
+ 0
+ read-write
+
+
+ AA
+ desc AA
+ 2
+ 2
+ read-write
+
+
+ SI
+ desc SI
+ 3
+ 3
+ read-write
+
+
+ STO
+ desc STO
+ 4
+ 4
+ read-write
+
+
+ STA
+ desc STA
+ 5
+ 5
+ read-write
+
+
+ ENS
+ desc ENS
+ 6
+ 6
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DATA
+ desc DATA
+ 0xC
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ DAT
+ desc DAT
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ADDR
+ desc ADDR
+ 0x10
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ GC
+ desc GC
+ 0
+ 0
+ read-write
+
+
+ ADR
+ desc ADR
+ 7
+ 1
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ STAT
+ desc STAT
+ 0x14
+ 32
+ read-only
+ 0x0
+ 0xFF
+
+
+ STA
+ desc STA
+ 7
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ I2C1
+ desc I2C
+ 0x40004400
+
+ 0x0
+ 0x18
+
+
+
+ LCD
+ desc LCD
+ 0x40005C00
+
+ 0x0
+ 0x80
+
+
+
+ CR0
+ desc CR0
+ 0x0
+ 32
+ read-write
+ 0xDA
+ 0xFF
+
+
+ EN
+ desc EN
+ 0
+ 0
+ read-write
+
+
+ LCDCLK
+ desc LCDCLK
+ 2
+ 1
+ read-write
+
+
+ CPCLK
+ desc CPCLK
+ 4
+ 3
+ read-write
+
+
+ BIAS
+ desc BIAS
+ 5
+ 5
+ read-write
+
+
+ DUTY
+ desc DUTY
+ 8
+ 6
+ read-write
+
+
+ BSEL
+ desc BSEL
+ 11
+ 9
+ read-write
+
+
+ CONTRAST
+ desc CONTRAST
+ 15
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CR1
+ desc CR1
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFF
+
+
+ BLINKCNT
+ desc BLINKCNT
+ 5
+ 0
+ read-write
+
+
+ BLINKEN
+ desc BLINKEN
+ 6
+ 6
+ read-write
+
+
+ CLKSRC
+ desc CLKSRC
+ 7
+ 7
+ read-write
+
+
+ MODE
+ desc MODE
+ 8
+ 8
+ read-write
+
+
+ IE
+ desc IE
+ 9
+ 9
+ read-write
+
+
+ DMAEN
+ desc DMAEN
+ 10
+ 10
+ read-write
+
+
+ INTF
+ desc INTF
+ 11
+ 11
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ INTCLR
+ desc INTCLR
+ 0x8
+ 32
+ write-only
+ 0x0
+ 0x400
+
+
+ INTF
+ desc INTF
+ 10
+ 10
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ POEN0
+ desc POEN0
+ 0xC
+ 32
+ read-write
+ 0xFFFFFFFF
+ 0xFFFFFFFF
+
+
+ S0
+ desc S0
+ 0
+ 0
+ read-write
+
+
+ S1
+ desc S1
+ 1
+ 1
+ read-write
+
+
+ S2
+ desc S2
+ 2
+ 2
+ read-write
+
+
+ S3
+ desc S3
+ 3
+ 3
+ read-write
+
+
+ S4
+ desc S4
+ 4
+ 4
+ read-write
+
+
+ S5
+ desc S5
+ 5
+ 5
+ read-write
+
+
+ S6
+ desc S6
+ 6
+ 6
+ read-write
+
+
+ S7
+ desc S7
+ 7
+ 7
+ read-write
+
+
+ S8
+ desc S8
+ 8
+ 8
+ read-write
+
+
+ S9
+ desc S9
+ 9
+ 9
+ read-write
+
+
+ S10
+ desc S10
+ 10
+ 10
+ read-write
+
+
+ S11
+ desc S11
+ 11
+ 11
+ read-write
+
+
+ S12
+ desc S12
+ 12
+ 12
+ read-write
+
+
+ S13
+ desc S13
+ 13
+ 13
+ read-write
+
+
+ S14
+ desc S14
+ 14
+ 14
+ read-write
+
+
+ S15
+ desc S15
+ 15
+ 15
+ read-write
+
+
+ S16
+ desc S16
+ 16
+ 16
+ read-write
+
+
+ S17
+ desc S17
+ 17
+ 17
+ read-write
+
+
+ S18
+ desc S18
+ 18
+ 18
+ read-write
+
+
+ S19
+ desc S19
+ 19
+ 19
+ read-write
+
+
+ S20
+ desc S20
+ 20
+ 20
+ read-write
+
+
+ S21
+ desc S21
+ 21
+ 21
+ read-write
+
+
+ S22
+ desc S22
+ 22
+ 22
+ read-write
+
+
+ S23
+ desc S23
+ 23
+ 23
+ read-write
+
+
+ S24
+ desc S24
+ 24
+ 24
+ read-write
+
+
+ S25
+ desc S25
+ 25
+ 25
+ read-write
+
+
+ S26
+ desc S26
+ 26
+ 26
+ read-write
+
+
+ S27
+ desc S27
+ 27
+ 27
+ read-write
+
+
+ S28
+ desc S28
+ 28
+ 28
+ read-write
+
+
+ S29
+ desc S29
+ 29
+ 29
+ read-write
+
+
+ S30
+ desc S30
+ 30
+ 30
+ read-write
+
+
+ S31
+ desc S31
+ 31
+ 31
+ read-write
+
+
+
+
+ POEN1
+ desc POEN1
+ 0x10
+ 32
+ read-write
+ 0x1FFF
+ 0x1FFF
+
+
+ S32
+ desc S32
+ 0
+ 0
+ read-write
+
+
+ S33
+ desc S33
+ 1
+ 1
+ read-write
+
+
+ S34
+ desc S34
+ 2
+ 2
+ read-write
+
+
+ S35
+ desc S35
+ 3
+ 3
+ read-write
+
+
+ S36C7
+ desc S36C7
+ 4
+ 4
+ read-write
+
+
+ S37C6
+ desc S37C6
+ 5
+ 5
+ read-write
+
+
+ S38C5
+ desc S38C5
+ 6
+ 6
+ read-write
+
+
+ S39C4
+ desc S39C4
+ 7
+ 7
+ read-write
+
+
+ S40
+ desc S40
+ 8
+ 8
+ read-write
+
+
+ S41
+ desc S41
+ 9
+ 9
+ read-write
+
+
+ S42
+ desc S42
+ 10
+ 10
+ read-write
+
+
+ S43
+ desc S43
+ 11
+ 11
+ read-write
+
+
+ MUX
+ desc MUX
+ 12
+ 12
+ read-write
+
+
+ S44
+ desc S44
+ 13
+ 13
+ read-write
+
+
+ S45
+ desc S45
+ 14
+ 14
+ read-write
+
+
+ S46
+ desc S46
+ 15
+ 15
+ read-write
+
+
+ S47
+ desc S47
+ 16
+ 16
+ read-write
+
+
+ S48
+ desc S48
+ 17
+ 17
+ read-write
+
+
+ S49
+ desc S49
+ 18
+ 18
+ read-write
+
+
+ S50
+ desc S50
+ 19
+ 19
+ read-write
+
+
+ S51
+ desc S51
+ 20
+ 20
+ read-write
+
+
+ C0
+ desc C0
+ 21
+ 21
+ read-write
+
+
+ C1
+ desc C1
+ 22
+ 22
+ read-write
+
+
+ C2
+ desc C2
+ 23
+ 23
+ read-write
+
+
+ C3
+ desc C3
+ 24
+ 24
+ read-write
+
+
+
+
+ RAM0
+ desc RAM0
+ 0x40
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ D24
+ desc D24
+ 24
+ 24
+ read-write
+
+
+ D25
+ desc D25
+ 25
+ 25
+ read-write
+
+
+ D26
+ desc D26
+ 26
+ 26
+ read-write
+
+
+ D27
+ desc D27
+ 27
+ 27
+ read-write
+
+
+ D28
+ desc D28
+ 28
+ 28
+ read-write
+
+
+ D29
+ desc D29
+ 29
+ 29
+ read-write
+
+
+ D30
+ desc D30
+ 30
+ 30
+ read-write
+
+
+ D31
+ desc D31
+ 31
+ 31
+ read-write
+
+
+
+
+ RAM1
+ desc RAM1
+ 0x44
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ D24
+ desc D24
+ 24
+ 24
+ read-write
+
+
+ D25
+ desc D25
+ 25
+ 25
+ read-write
+
+
+ D26
+ desc D26
+ 26
+ 26
+ read-write
+
+
+ D27
+ desc D27
+ 27
+ 27
+ read-write
+
+
+ D28
+ desc D28
+ 28
+ 28
+ read-write
+
+
+ D29
+ desc D29
+ 29
+ 29
+ read-write
+
+
+ D30
+ desc D30
+ 30
+ 30
+ read-write
+
+
+ D31
+ desc D31
+ 31
+ 31
+ read-write
+
+
+
+
+ RAM2
+ desc RAM2
+ 0x48
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ D24
+ desc D24
+ 24
+ 24
+ read-write
+
+
+ D25
+ desc D25
+ 25
+ 25
+ read-write
+
+
+ D26
+ desc D26
+ 26
+ 26
+ read-write
+
+
+ D27
+ desc D27
+ 27
+ 27
+ read-write
+
+
+ D28
+ desc D28
+ 28
+ 28
+ read-write
+
+
+ D29
+ desc D29
+ 29
+ 29
+ read-write
+
+
+ D30
+ desc D30
+ 30
+ 30
+ read-write
+
+
+ D31
+ desc D31
+ 31
+ 31
+ read-write
+
+
+
+
+ RAM3
+ desc RAM3
+ 0x4C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ D24
+ desc D24
+ 24
+ 24
+ read-write
+
+
+ D25
+ desc D25
+ 25
+ 25
+ read-write
+
+
+ D26
+ desc D26
+ 26
+ 26
+ read-write
+
+
+ D27
+ desc D27
+ 27
+ 27
+ read-write
+
+
+ D28
+ desc D28
+ 28
+ 28
+ read-write
+
+
+ D29
+ desc D29
+ 29
+ 29
+ read-write
+
+
+ D30
+ desc D30
+ 30
+ 30
+ read-write
+
+
+ D31
+ desc D31
+ 31
+ 31
+ read-write
+
+
+
+
+ RAM4
+ desc RAM4
+ 0x50
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ D24
+ desc D24
+ 24
+ 24
+ read-write
+
+
+ D25
+ desc D25
+ 25
+ 25
+ read-write
+
+
+ D26
+ desc D26
+ 26
+ 26
+ read-write
+
+
+ D27
+ desc D27
+ 27
+ 27
+ read-write
+
+
+ D28
+ desc D28
+ 28
+ 28
+ read-write
+
+
+ D29
+ desc D29
+ 29
+ 29
+ read-write
+
+
+ D30
+ desc D30
+ 30
+ 30
+ read-write
+
+
+ D31
+ desc D31
+ 31
+ 31
+ read-write
+
+
+
+
+ RAM5
+ desc RAM5
+ 0x54
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ D24
+ desc D24
+ 24
+ 24
+ read-write
+
+
+ D25
+ desc D25
+ 25
+ 25
+ read-write
+
+
+ D26
+ desc D26
+ 26
+ 26
+ read-write
+
+
+ D27
+ desc D27
+ 27
+ 27
+ read-write
+
+
+ D28
+ desc D28
+ 28
+ 28
+ read-write
+
+
+ D29
+ desc D29
+ 29
+ 29
+ read-write
+
+
+ D30
+ desc D30
+ 30
+ 30
+ read-write
+
+
+ D31
+ desc D31
+ 31
+ 31
+ read-write
+
+
+
+
+ RAM6
+ desc RAM6
+ 0x58
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ D24
+ desc D24
+ 24
+ 24
+ read-write
+
+
+ D25
+ desc D25
+ 25
+ 25
+ read-write
+
+
+ D26
+ desc D26
+ 26
+ 26
+ read-write
+
+
+ D27
+ desc D27
+ 27
+ 27
+ read-write
+
+
+ D28
+ desc D28
+ 28
+ 28
+ read-write
+
+
+ D29
+ desc D29
+ 29
+ 29
+ read-write
+
+
+ D30
+ desc D30
+ 30
+ 30
+ read-write
+
+
+ D31
+ desc D31
+ 31
+ 31
+ read-write
+
+
+
+
+ RAM7
+ desc RAM7
+ 0x5C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ D24
+ desc D24
+ 24
+ 24
+ read-write
+
+
+ D25
+ desc D25
+ 25
+ 25
+ read-write
+
+
+ D26
+ desc D26
+ 26
+ 26
+ read-write
+
+
+ D27
+ desc D27
+ 27
+ 27
+ read-write
+
+
+ D28
+ desc D28
+ 28
+ 28
+ read-write
+
+
+ D29
+ desc D29
+ 29
+ 29
+ read-write
+
+
+ D30
+ desc D30
+ 30
+ 30
+ read-write
+
+
+ D31
+ desc D31
+ 31
+ 31
+ read-write
+
+
+
+
+ RAM8
+ desc RAM8
+ 0x60
+ 32
+ read-write
+ 0x0
+ 0xFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 24
+ read-write
+
+
+
+
+ RAM9
+ desc RAM9
+ 0x64
+ 32
+ read-write
+ 0x0
+ 0xFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 24
+ read-write
+
+
+
+
+ RAMA
+ desc RAMA
+ 0x68
+ 32
+ read-write
+ 0x0
+ 0xFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 24
+ read-write
+
+
+
+
+ RAMB
+ desc RAMB
+ 0x6C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 24
+ read-write
+
+
+
+
+ RAMC
+ desc RAMC
+ 0x70
+ 32
+ read-write
+ 0x0
+ 0xFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 24
+ read-write
+
+
+
+
+ RAMD
+ desc RAMD
+ 0x74
+ 32
+ read-write
+ 0x0
+ 0xFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 24
+ read-write
+
+
+
+
+ RAME
+ desc RAME
+ 0x78
+ 32
+ read-write
+ 0x0
+ 0xFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 24
+ read-write
+
+
+
+
+ RAMF
+ desc RAMF
+ 0x7C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFF
+
+
+ D0
+ desc D0
+ 0
+ 0
+ read-write
+
+
+ D1
+ desc D1
+ 1
+ 1
+ read-write
+
+
+ D2
+ desc D2
+ 2
+ 2
+ read-write
+
+
+ D3
+ desc D3
+ 3
+ 3
+ read-write
+
+
+ D4
+ desc D4
+ 4
+ 4
+ read-write
+
+
+ D5
+ desc D5
+ 5
+ 5
+ read-write
+
+
+ D6
+ desc D6
+ 6
+ 6
+ read-write
+
+
+ D7
+ desc D7
+ 7
+ 7
+ read-write
+
+
+ D8
+ desc D8
+ 8
+ 8
+ read-write
+
+
+ D9
+ desc D9
+ 9
+ 9
+ read-write
+
+
+ D10
+ desc D10
+ 10
+ 10
+ read-write
+
+
+ D11
+ desc D11
+ 11
+ 11
+ read-write
+
+
+ D12
+ desc D12
+ 12
+ 12
+ read-write
+
+
+ D13
+ desc D13
+ 13
+ 13
+ read-write
+
+
+ D14
+ desc D14
+ 14
+ 14
+ read-write
+
+
+ D15
+ desc D15
+ 15
+ 15
+ read-write
+
+
+ D16
+ desc D16
+ 16
+ 16
+ read-write
+
+
+ D17
+ desc D17
+ 17
+ 17
+ read-write
+
+
+ D18
+ desc D18
+ 18
+ 18
+ read-write
+
+
+ D19
+ desc D19
+ 19
+ 19
+ read-write
+
+
+ D20
+ desc D20
+ 20
+ 20
+ read-write
+
+
+ D21
+ desc D21
+ 21
+ 21
+ read-write
+
+
+ D22
+ desc D22
+ 22
+ 22
+ read-write
+
+
+ D23
+ desc D23
+ 23
+ 23
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 24
+ read-write
+
+
+
+
+
+
+ LPTIMER0
+ desc LPTIMER
+ 0x40000F00
+
+ 0x0
+ 0x18
+
+
+
+ CNT
+ desc CNT
+ 0x0
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ARR
+ desc ARR
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARR
+ desc ARR
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CR
+ desc CR
+ 0xC
+ 32
+ read-write
+ 0x8
+ 0x3FBF
+
+
+ TR
+ desc TR
+ 0
+ 0
+ read-write
+
+
+ MD
+ desc MD
+ 1
+ 1
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ TOG_EN
+ desc TOG_EN
+ 3
+ 3
+ read-write
+
+
+ TCK_SEL
+ desc TCK_SEL
+ 5
+ 4
+ read-write
+
+
+ WT_FLAG
+ desc WT_FLAG
+ 7
+ 7
+ read-only
+
+
+ GATE
+ desc GATE
+ 8
+ 8
+ read-write
+
+
+ GATE_P
+ desc GATE_P
+ 9
+ 9
+ read-write
+
+
+ IE
+ desc IE
+ 10
+ 10
+ read-write
+
+
+ PRS
+ desc PRS
+ 13
+ 11
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0x1
+
+
+ TF
+ desc TF
+ 0
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0x1
+ 0x1
+
+
+ TFC
+ desc TFC
+ 0
+ 0
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ LPTIMER1
+ desc LPTIMER
+ 0x40000F40
+
+ 0x0
+ 0x18
+
+
+
+ LPUART0
+ desc LPUART
+ 0x40000200
+
+ 0x0
+ 0x1C
+
+
+
+ SBUF
+ desc SBUF
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0x1FF
+
+
+ DATA
+ desc DATA
+ 7
+ 0
+ read-write
+
+
+ DATA8
+ desc DATA8
+ 8
+ 8
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SCON
+ desc SCON
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0x7FFFFF
+
+
+ RCIE
+ desc RCIE
+ 0
+ 0
+ read-write
+
+
+ TCIE
+ desc TCIE
+ 1
+ 1
+ read-write
+
+
+ B8CONT
+ desc B8CONT
+ 3
+ 2
+ read-write
+
+
+ REN
+ desc REN
+ 4
+ 4
+ read-write
+
+
+ ADRDET
+ desc ADRDET
+ 5
+ 5
+ read-write
+
+
+ SM
+ desc SM
+ 7
+ 6
+ read-write
+
+
+ TXEIE
+ desc TXEIE
+ 8
+ 8
+ read-write
+
+
+ OVER
+ desc OVER
+ 10
+ 9
+ read-write
+
+
+ SCLKSEL
+ desc SCLKSEL
+ 12
+ 11
+ read-write
+
+
+ PEIE
+ desc PEIE
+ 13
+ 13
+ read-write
+
+
+ STOPBIT
+ desc STOPBIT
+ 15
+ 14
+ read-write
+
+
+ DMARXEN
+ desc DMARXEN
+ 16
+ 16
+ read-write
+
+
+ DMATXEN
+ desc DMATXEN
+ 17
+ 17
+ read-write
+
+
+ RTSEN
+ desc RTSEN
+ 18
+ 18
+ read-write
+
+
+ CTSEN
+ desc CTSEN
+ 19
+ 19
+ read-write
+
+
+ CTSIE
+ desc CTSIE
+ 20
+ 20
+ read-write
+
+
+ FEIE
+ desc FEIE
+ 21
+ 21
+ read-write
+
+
+ HDSEL
+ desc HDSEL
+ 22
+ 22
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SADDR
+ desc SADDR
+ 0x8
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ SADDR
+ desc SADDR
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SADEN
+ desc SADEN
+ 0xC
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ SADEN
+ desc SADEN
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ISR
+ desc ISR
+ 0x10
+ 32
+ read-only
+ 0x8
+ 0x7F
+
+
+ RC
+ desc RC
+ 0
+ 0
+ read-only
+
+
+ TC
+ desc TC
+ 1
+ 1
+ read-only
+
+
+ FE
+ desc FE
+ 2
+ 2
+ read-only
+
+
+ TXE
+ desc TXE
+ 3
+ 3
+ read-only
+
+
+ PE
+ desc PE
+ 4
+ 4
+ read-only
+
+
+ CTSIF
+ desc CTSIF
+ 5
+ 5
+ read-only
+
+
+ CTS
+ desc CTS
+ 6
+ 6
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICR
+ desc ICR
+ 0x14
+ 32
+ write-only
+ 0x0
+ 0x37
+
+
+ RCCF
+ desc RCCF
+ 0
+ 0
+ write-only
+
+
+ TCCF
+ desc TCCF
+ 1
+ 1
+ write-only
+
+
+ FECF
+ desc FECF
+ 2
+ 2
+ write-only
+
+
+ PECF
+ desc PECF
+ 4
+ 4
+ write-only
+
+
+ CTSIFCF
+ desc CTSIFCF
+ 5
+ 5
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SCNT
+ desc SCNT
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ SCNT
+ desc SCNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ LPUART1
+ desc LPUART
+ 0x40004000
+
+ 0x0
+ 0x1C
+
+
+
+ LVD
+ desc LVD
+ 0x40002400
+ ADC
+
+ 0x0
+ 0x30
+
+
+
+ CR
+ desc CR
+ 0x28
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ LVDEN
+ desc LVDEN
+ 0
+ 0
+ read-write
+
+
+ ACT
+ desc ACT
+ 1
+ 1
+ read-write
+
+
+ SOURCE_SEL
+ desc SOURCE_SEL
+ 3
+ 2
+ read-write
+
+
+ VTDS
+ desc VTDS
+ 7
+ 4
+ read-write
+
+
+ FLTEN
+ desc FLTEN
+ 8
+ 8
+ read-write
+
+
+ DEBOUNCE_TIME
+ desc DEBOUNCE_TIME
+ 11
+ 9
+ read-write
+
+
+ FTEN
+ desc FTEN
+ 12
+ 12
+ read-write
+
+
+ RTEN
+ desc RTEN
+ 13
+ 13
+ read-write
+
+
+ HTEN
+ desc HTEN
+ 14
+ 14
+ read-write
+
+
+ IE
+ desc IE
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x2C
+ 32
+ read-write
+ 0x0
+ 0x3
+
+
+ INTF
+ desc INTF
+ 0
+ 0
+ read-write
+
+
+ FILTER
+ desc FILTER
+ 1
+ 1
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ OPA
+ desc OPA
+ 0x40002400
+ ADC
+
+ 0x0
+ 0x40
+
+
+
+ CR0
+ desc CR0
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0xFFF
+
+
+ EN
+ desc EN
+ 0
+ 0
+ read-write
+
+
+ AZEN
+ desc AZEN
+ 1
+ 1
+ read-write
+
+
+ BUFEN
+ desc BUFEN
+ 2
+ 2
+ read-write
+
+
+ OEN1
+ desc OEN1
+ 3
+ 3
+ read-write
+
+
+ OEN2
+ desc OEN2
+ 4
+ 4
+ read-write
+
+
+ OEN3
+ desc OEN3
+ 5
+ 5
+ read-write
+
+
+ OEN4
+ desc OEN4
+ 6
+ 6
+ read-write
+
+
+ BIASSEL
+ desc BIASSEL
+ 9
+ 7
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CR1
+ desc CR1
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ ADCTR_EN
+ desc ADCTR_EN
+ 0
+ 0
+ read-write
+
+
+ TRIGGER
+ desc TRIGGER
+ 1
+ 1
+ read-write
+
+
+ AZ_PULSE
+ desc AZ_PULSE
+ 2
+ 2
+ read-write
+
+
+ CLK_SW_SET
+ desc CLK_SW_SET
+ 3
+ 3
+ read-write
+
+
+ CLK_SEL
+ desc CLK_SEL
+ 7
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ PCA
+ desc PCA
+ 0x40001000
+
+ 0x0
+ 0x6C
+
+
+
+ CCON
+ desc CCON
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xDF
+
+
+ CCF0
+ desc CCF0
+ 0
+ 0
+ read-write
+
+
+ CCF1
+ desc CCF1
+ 1
+ 1
+ read-write
+
+
+ CCF2
+ desc CCF2
+ 2
+ 2
+ read-write
+
+
+ CCF3
+ desc CCF3
+ 3
+ 3
+ read-write
+
+
+ CCF4
+ desc CCF4
+ 4
+ 4
+ read-write
+
+
+ CR
+ desc CR
+ 6
+ 6
+ read-write
+
+
+ CF
+ desc CF
+ 7
+ 7
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CMOD
+ desc CMOD
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xCF
+
+
+ CFIE
+ desc CFIE
+ 0
+ 0
+ read-write
+
+
+ CPS
+ desc CPS
+ 3
+ 1
+ read-write
+
+
+ WDTE
+ desc WDTE
+ 6
+ 6
+ read-write
+
+
+ CIDL
+ desc CIDL
+ 7
+ 7
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT
+ desc CNT
+ 0x8
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0xC
+ 32
+ write-only
+ 0x9F
+ 0x9F
+
+
+ CCF0
+ desc CCF0
+ 0
+ 0
+ write-only
+
+
+ CCF1
+ desc CCF1
+ 1
+ 1
+ write-only
+
+
+ CCF2
+ desc CCF2
+ 2
+ 2
+ write-only
+
+
+ CCF3
+ desc CCF3
+ 3
+ 3
+ write-only
+
+
+ CCF4
+ desc CCF4
+ 4
+ 4
+ write-only
+
+
+ CF
+ desc CF
+ 7
+ 7
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAPM0
+ desc CCAPM0
+ 0x10
+ 32
+ read-write
+ 0x0
+ 0x7F
+
+
+ CCIE
+ desc CCIE
+ 0
+ 0
+ read-write
+
+
+ PWM
+ desc PWM
+ 1
+ 1
+ read-write
+
+
+ TOG
+ desc TOG
+ 2
+ 2
+ read-write
+
+
+ MAT
+ desc MAT
+ 3
+ 3
+ read-write
+
+
+ CAPN
+ desc CAPN
+ 4
+ 4
+ read-write
+
+
+ CAPP
+ desc CAPP
+ 5
+ 5
+ read-write
+
+
+ ECOM
+ desc ECOM
+ 6
+ 6
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAPM1
+ desc CCAPM1
+ 0x14
+ 32
+ read-write
+ 0x0
+ 0x7F
+
+
+ CCIE
+ desc CCIE
+ 0
+ 0
+ read-write
+
+
+ PWM
+ desc PWM
+ 1
+ 1
+ read-write
+
+
+ TOG
+ desc TOG
+ 2
+ 2
+ read-write
+
+
+ MAT
+ desc MAT
+ 3
+ 3
+ read-write
+
+
+ CAPN
+ desc CAPN
+ 4
+ 4
+ read-write
+
+
+ CAPP
+ desc CAPP
+ 5
+ 5
+ read-write
+
+
+ ECOM
+ desc ECOM
+ 6
+ 6
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAPM2
+ desc CCAPM2
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x7F
+
+
+ CCIE
+ desc CCIE
+ 0
+ 0
+ read-write
+
+
+ PWM
+ desc PWM
+ 1
+ 1
+ read-write
+
+
+ TOG
+ desc TOG
+ 2
+ 2
+ read-write
+
+
+ MAT
+ desc MAT
+ 3
+ 3
+ read-write
+
+
+ CAPN
+ desc CAPN
+ 4
+ 4
+ read-write
+
+
+ CAPP
+ desc CAPP
+ 5
+ 5
+ read-write
+
+
+ ECOM
+ desc ECOM
+ 6
+ 6
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAPM3
+ desc CCAPM3
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0x7F
+
+
+ CCIE
+ desc CCIE
+ 0
+ 0
+ read-write
+
+
+ PWM
+ desc PWM
+ 1
+ 1
+ read-write
+
+
+ TOG
+ desc TOG
+ 2
+ 2
+ read-write
+
+
+ MAT
+ desc MAT
+ 3
+ 3
+ read-write
+
+
+ CAPN
+ desc CAPN
+ 4
+ 4
+ read-write
+
+
+ CAPP
+ desc CAPP
+ 5
+ 5
+ read-write
+
+
+ ECOM
+ desc ECOM
+ 6
+ 6
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAPM4
+ desc CCAPM4
+ 0x20
+ 32
+ read-write
+ 0x0
+ 0x7F
+
+
+ CCIE
+ desc CCIE
+ 0
+ 0
+ read-write
+
+
+ PWM
+ desc PWM
+ 1
+ 1
+ read-write
+
+
+ TOG
+ desc TOG
+ 2
+ 2
+ read-write
+
+
+ MAT
+ desc MAT
+ 3
+ 3
+ read-write
+
+
+ CAPN
+ desc CAPN
+ 4
+ 4
+ read-write
+
+
+ CAPP
+ desc CAPP
+ 5
+ 5
+ read-write
+
+
+ ECOM
+ desc ECOM
+ 6
+ 6
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP0H
+ desc CCAP0H
+ 0x24
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ CCAP0
+ desc CCAP0
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP0L
+ desc CCAP0L
+ 0x28
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ CCAP0
+ desc CCAP0
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP1H
+ desc CCAP1H
+ 0x2C
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ CCAP1
+ desc CCAP1
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP1L
+ desc CCAP1L
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ CCAP1
+ desc CCAP1
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP2H
+ desc CCAP2H
+ 0x34
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ CCAP2
+ desc CCAP2
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP2L
+ desc CCAP2L
+ 0x38
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ CCAP2
+ desc CCAP2
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP3H
+ desc CCAP3H
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ CCAP3
+ desc CCAP3
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP3L
+ desc CCAP3L
+ 0x40
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ CCAP3
+ desc CCAP3
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP4H
+ desc CCAP4H
+ 0x44
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ CCAP4
+ desc CCAP4
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP4L
+ desc CCAP4L
+ 0x48
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ CCAP4
+ desc CCAP4
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAPO
+ desc CCAPO
+ 0x4C
+ 32
+ read-write
+ 0x0
+ 0x1F
+
+
+ CCAPO0
+ desc CCAPO0
+ 0
+ 0
+ read-write
+
+
+ CCAPO1
+ desc CCAPO1
+ 1
+ 1
+ read-write
+
+
+ CCAPO2
+ desc CCAPO2
+ 2
+ 2
+ read-write
+
+
+ CCAPO3
+ desc CCAPO3
+ 3
+ 3
+ read-write
+
+
+ CCAPO4
+ desc CCAPO4
+ 4
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP0
+ desc CCAP0
+ 0x50
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCAP0
+ desc CCAP0
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP1
+ desc CCAP1
+ 0x54
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCAP1
+ desc CCAP1
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP2
+ desc CCAP2
+ 0x58
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCAP2
+ desc CCAP2
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP3
+ desc CCAP3
+ 0x5C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCAP3
+ desc CCAP3
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCAP4
+ desc CCAP4
+ 0x60
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCAP4
+ desc CCAP4
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CARR
+ desc CARR
+ 0x64
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CARR
+ desc CARR
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ EPWM
+ desc EPWM
+ 0x68
+ 32
+ read-write
+ 0x0
+ 0x1
+
+
+ EPWM
+ desc EPWM
+ 0
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ PCNT
+ desc PCNT
+ 0x40005400
+
+ 0x0
+ 0x38
+
+
+
+ RUN
+ desc RUN
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0x1
+
+
+ RUN
+ desc RUN
+ 0
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CTRL
+ desc CTRL
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0x7F
+
+
+ MODE
+ desc MODE
+ 1
+ 0
+ read-write
+
+
+ CLKSEL
+ desc CLKSEL
+ 3
+ 2
+ read-write
+
+
+ DIR
+ desc DIR
+ 4
+ 4
+ read-write
+
+
+ S0P
+ desc S0P
+ 5
+ 5
+ read-write
+
+
+ S1P
+ desc S1P
+ 6
+ 6
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ FLT
+ desc FLT
+ 0x8
+ 32
+ read-write
+ 0x2000
+ 0x1FFFF
+
+
+ CLKDIV
+ desc CLKDIV
+ 12
+ 0
+ read-write
+
+
+ DEBTOP
+ desc DEBTOP
+ 15
+ 13
+ read-write
+
+
+ EN
+ desc EN
+ 16
+ 16
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ TOCR
+ desc TOCR
+ 0xC
+ 32
+ read-write
+ 0xFFF
+ 0x1FFFF
+
+
+ TH
+ desc TH
+ 11
+ 0
+ read-write
+
+
+ EN
+ desc EN
+ 16
+ 16
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CMD
+ desc CMD
+ 0x10
+ 32
+ write-only
+ 0x0
+ 0x7
+
+
+ T2C
+ desc T2C
+ 0
+ 0
+ write-only
+
+
+ B2T
+ desc B2T
+ 1
+ 1
+ write-only
+
+
+ B2C
+ desc B2C
+ 2
+ 2
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SR1
+ desc SR1
+ 0x14
+ 32
+ read-only
+ 0x0
+ 0x1
+
+
+ DIR
+ desc DIR
+ 0
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT
+ desc CNT
+ 0x18
+ 32
+ read-only
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ TOP
+ desc TOP
+ 0x1C
+ 32
+ read-only
+ 0xFF
+ 0xFFFF
+
+
+ TOP
+ desc TOP
+ 15
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ BUF
+ desc BUF
+ 0x20
+ 32
+ read-write
+ 0xFF
+ 0xFFFF
+
+
+ BUF
+ desc BUF
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x24
+ 32
+ read-only
+ 0x0
+ 0xFF
+
+
+ UF
+ desc UF
+ 0
+ 0
+ read-only
+
+
+ OV
+ desc OV
+ 1
+ 1
+ read-only
+
+
+ TO
+ desc TO
+ 2
+ 2
+ read-only
+
+
+ DIR
+ desc DIR
+ 3
+ 3
+ read-only
+
+
+ FE
+ desc FE
+ 4
+ 4
+ read-only
+
+
+ BB
+ desc BB
+ 5
+ 5
+ read-only
+
+
+ S0E
+ desc S0E
+ 6
+ 6
+ read-only
+
+
+ S1E
+ desc S1E
+ 7
+ 7
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICR
+ desc ICR
+ 0x28
+ 32
+ write-only
+ 0x0
+ 0xFF
+
+
+ UF
+ desc UF
+ 0
+ 0
+ write-only
+
+
+ OV
+ desc OV
+ 1
+ 1
+ write-only
+
+
+ TO
+ desc TO
+ 2
+ 2
+ write-only
+
+
+ DIR
+ desc DIR
+ 3
+ 3
+ write-only
+
+
+ FE
+ desc FE
+ 4
+ 4
+ write-only
+
+
+ BB
+ desc BB
+ 5
+ 5
+ write-only
+
+
+ S0E
+ desc S0E
+ 6
+ 6
+ write-only
+
+
+ S1E
+ desc S1E
+ 7
+ 7
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IEN
+ desc IEN
+ 0x2C
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ UF
+ desc UF
+ 0
+ 0
+ read-write
+
+
+ OV
+ desc OV
+ 1
+ 1
+ read-write
+
+
+ TO
+ desc TO
+ 2
+ 2
+ read-write
+
+
+ DIR
+ desc DIR
+ 3
+ 3
+ read-write
+
+
+ FE
+ desc FE
+ 4
+ 4
+ read-write
+
+
+ BB
+ desc BB
+ 5
+ 5
+ read-write
+
+
+ S0E
+ desc S0E
+ 6
+ 6
+ read-write
+
+
+ S1E
+ desc S1E
+ 7
+ 7
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SR2
+ desc SR2
+ 0x30
+ 32
+ read-only
+ 0x0
+ 0x7
+
+
+ T2C
+ desc T2C
+ 0
+ 0
+ read-only
+
+
+ B2T
+ desc B2T
+ 1
+ 1
+ read-only
+
+
+ B2C
+ desc B2C
+ 2
+ 2
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DBG
+ desc DBG
+ 0x34
+ 32
+ read-write
+ 0x0
+ 0x3
+
+
+ DBG
+ desc DBG
+ 1
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ RAM
+ desc RAM
+ 0x40020400
+
+ 0x0
+ 0x10
+
+
+
+ CR
+ desc CR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0x3
+
+
+ IE
+ desc IE
+ 1
+ 1
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ERRADDR
+ desc ERRADDR
+ 0x4
+ 32
+ read-only
+ 0x0
+ 0x1FFF
+
+
+ ERRADDR
+ desc ERRADDR
+ 13
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x8
+ 32
+ read-only
+ 0x0
+ 0x1
+
+
+ ERR
+ desc ERR
+ 0
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+ ICLR
+ desc ICLR
+ 0xC
+ 32
+ write-only
+ 0x1
+ 0x1
+
+
+ ERRCLR
+ desc ERRCLR
+ 0
+ 0
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-only
+
+
+
+
+
+
+ RESET
+ desc RESET
+ 0x4000201C
+
+ 0x0
+ 0x10
+
+
+
+ RESET_FLAG
+ desc RESET_FLAG
+ 0x0
+ 32
+ read-write
+ 0x11
+ 0xFF
+
+
+ POR5V
+ desc POR5V
+ 0
+ 0
+ read-write
+
+
+ POR15V
+ desc POR15V
+ 1
+ 1
+ read-write
+
+
+ LVD
+ desc LVD
+ 2
+ 2
+ read-write
+
+
+ WDT
+ desc WDT
+ 3
+ 3
+ read-write
+
+
+ PCA
+ desc PCA
+ 4
+ 4
+ read-write
+
+
+ LOCKUP
+ desc LOCKUP
+ 5
+ 5
+ read-write
+
+
+ SYSREQ
+ desc SYSREQ
+ 6
+ 6
+ read-write
+
+
+ RSTB
+ desc RSTB
+ 7
+ 7
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PERI_RESET0
+ desc PERI_RESET0
+ 0xC
+ 32
+ read-write
+ 0x7F7F6FFF
+ 0x7FFF6FFF
+
+
+ UART0
+ desc UART0
+ 0
+ 0
+ read-write
+
+
+ UART1
+ desc UART1
+ 1
+ 1
+ read-write
+
+
+ LPUART0
+ desc LPUART0
+ 2
+ 2
+ read-write
+
+
+ LPUART1
+ desc LPUART1
+ 3
+ 3
+ read-write
+
+
+ I2C0
+ desc I2C0
+ 4
+ 4
+ read-write
+
+
+ I2C1
+ desc I2C1
+ 5
+ 5
+ read-write
+
+
+ SPI0
+ desc SPI0
+ 6
+ 6
+ read-write
+
+
+ SPI1
+ desc SPI1
+ 7
+ 7
+ read-write
+
+
+ BASETIM
+ desc BASETIM
+ 8
+ 8
+ read-write
+
+
+ LPTIM0
+ desc LPTIM0
+ 9
+ 9
+ read-write
+
+
+ ADVTIM
+ desc ADVTIM
+ 10
+ 10
+ read-write
+
+
+ TIM3
+ desc TIM3
+ 11
+ 11
+ read-write
+
+
+ OPA
+ desc OPA
+ 13
+ 13
+ read-write
+
+
+ PCA
+ desc PCA
+ 14
+ 14
+ read-write
+
+
+ ADC
+ desc ADC
+ 16
+ 16
+ read-write
+
+
+ VC
+ desc VC
+ 17
+ 17
+ read-write
+
+
+ RNG
+ desc RNG
+ 18
+ 18
+ read-write
+
+
+ PCNT
+ desc PCNT
+ 19
+ 19
+ read-write
+
+
+ RTC
+ desc RTC
+ 20
+ 20
+ read-write
+
+
+ TRIM
+ desc TRIM
+ 21
+ 21
+ read-write
+
+
+ LCD
+ desc LCD
+ 22
+ 22
+ read-write
+
+
+ TICK
+ desc TICK
+ 24
+ 24
+ read-write
+
+
+ SWD
+ desc SWD
+ 25
+ 25
+ read-write
+
+
+ CRC
+ desc CRC
+ 26
+ 26
+ read-write
+
+
+ AES
+ desc AES
+ 27
+ 27
+ read-write
+
+
+ GPIO
+ desc GPIO
+ 28
+ 28
+ read-write
+
+
+ DMA
+ desc DMA
+ 29
+ 29
+ read-write
+
+
+
+
+ PERI_RESET1
+ desc PERI_RESET1
+ 0x10
+ 32
+ read-write
+ 0x3FF
+ 0x3FFF
+
+
+ DAC
+ desc DAC
+ 3
+ 3
+ read-write
+
+
+ LPTIM1
+ desc LPTIM1
+ 4
+ 4
+ read-write
+
+
+ UART2
+ desc UART2
+ 8
+ 8
+ read-write
+
+
+ UART3
+ desc UART3
+ 9
+ 9
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ RTC
+ desc RTC
+ 0x40001400
+
+ 0x0
+ 0x38
+
+
+
+ CR0
+ desc CR0
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0x7FEF
+
+
+ PRDS
+ desc PRDS
+ 2
+ 0
+ read-write
+
+
+ AMPM
+ desc AMPM
+ 3
+ 3
+ read-write
+
+
+ HZ1OE
+ desc HZ1OE
+ 5
+ 5
+ read-write
+
+
+ HZ1SEL
+ desc HZ1SEL
+ 6
+ 6
+ read-write
+
+
+ START
+ desc START
+ 7
+ 7
+ read-write
+
+
+ PRDX
+ desc PRDX
+ 13
+ 8
+ read-write
+
+
+ PRDSEL
+ desc PRDSEL
+ 14
+ 14
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CR1
+ desc CR1
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0x7FB
+
+
+ WAIT
+ desc WAIT
+ 0
+ 0
+ read-write
+
+
+ WAITF
+ desc WAITF
+ 1
+ 1
+ read-write
+
+
+ PRDF
+ desc PRDF
+ 3
+ 3
+ read-write
+
+
+ ALMF
+ desc ALMF
+ 4
+ 4
+ read-write
+
+
+ ALMIE
+ desc ALMIE
+ 6
+ 6
+ read-write
+
+
+ ALMEN
+ desc ALMEN
+ 7
+ 7
+ read-write
+
+
+ CKSEL
+ desc CKSEL
+ 10
+ 8
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SEC
+ desc SEC
+ 0x8
+ 32
+ read-write
+ 0x0
+ 0x7F
+
+
+ SECL
+ desc SECL
+ 3
+ 0
+ read-write
+
+
+ SECH
+ desc SECH
+ 6
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ MIN
+ desc MIN
+ 0xC
+ 32
+ read-write
+ 0x0
+ 0x7F
+
+
+ MINL
+ desc MINL
+ 3
+ 0
+ read-write
+
+
+ MINH
+ desc MINH
+ 6
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ HOUR
+ desc HOUR
+ 0x10
+ 32
+ read-write
+ 0x0
+ 0x7F
+
+
+ HOURL
+ desc HOURL
+ 3
+ 0
+ read-write
+
+
+ HOURH
+ desc HOURH
+ 5
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ WEEK
+ desc WEEK
+ 0x14
+ 32
+ read-write
+ 0x0
+ 0x7
+
+
+ WEEK
+ desc WEEK
+ 2
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DAY
+ desc DAY
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x3F
+
+
+ DAYL
+ desc DAYL
+ 3
+ 0
+ read-write
+
+
+ DAYH
+ desc DAYH
+ 5
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ MON
+ desc MON
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0x1F
+
+
+ MON
+ desc MON
+ 4
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ YEAR
+ desc YEAR
+ 0x20
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ YEARL
+ desc YEARL
+ 3
+ 0
+ read-write
+
+
+ YEARH
+ desc YEARH
+ 7
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ALMMIN
+ desc ALMMIN
+ 0x24
+ 32
+ read-write
+ 0x0
+ 0x7F
+
+
+ ALMMINL
+ desc ALMMINL
+ 3
+ 0
+ read-write
+
+
+ ALMMINH
+ desc ALMMINH
+ 6
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ALMHOUR
+ desc ALMHOUR
+ 0x28
+ 32
+ read-write
+ 0x0
+ 0x3F
+
+
+ ALMHOURL
+ desc ALMHOURL
+ 3
+ 0
+ read-write
+
+
+ ALMHOURH
+ desc ALMHOURH
+ 5
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ALMWEEK
+ desc ALMWEEK
+ 0x2C
+ 32
+ read-write
+ 0x0
+ 0x7F
+
+
+ ALMWEEK
+ desc ALMWEEK
+ 6
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ COMPEN
+ desc COMPEN
+ 0x30
+ 32
+ read-write
+ 0x20
+ 0x81FF
+
+
+ CR
+ desc CR
+ 8
+ 0
+ read-write
+
+
+ EN
+ desc EN
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ALMSEC
+ desc ALMSEC
+ 0x34
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ ALMSECL
+ desc ALMSECL
+ 3
+ 0
+ read-write
+
+
+ ALMSECH
+ desc ALMSECH
+ 6
+ 4
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ SPI0
+ desc SPI
+ 0x40000800
+
+ 0x0
+ 0x18
+
+
+
+ CR
+ desc CR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xDF
+
+
+ SPR0
+ desc SPR0
+ 0
+ 0
+ read-write
+
+
+ SPR1
+ desc SPR1
+ 1
+ 1
+ read-write
+
+
+ CPHA
+ desc CPHA
+ 2
+ 2
+ read-write
+
+
+ CPOL
+ desc CPOL
+ 3
+ 3
+ read-write
+
+
+ MSTR
+ desc MSTR
+ 4
+ 4
+ read-write
+
+
+ SPEN
+ desc SPEN
+ 6
+ 6
+ read-write
+
+
+ SPR2
+ desc SPR2
+ 7
+ 7
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SSN
+ desc SSN
+ 0x4
+ 32
+ read-write
+ 0x1
+ 0x1
+
+
+ SSN
+ desc SSN
+ 0
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ STAT
+ desc STAT
+ 0x8
+ 32
+ read-only
+ 0x0
+ 0xBE
+
+
+ RXNE
+ desc RXNE
+ 1
+ 1
+ read-only
+
+
+ TXE
+ desc TXE
+ 2
+ 2
+ read-only
+
+
+ BUSY
+ desc BUSY
+ 3
+ 3
+ read-only
+
+
+ MDF
+ desc MDF
+ 4
+ 4
+ read-only
+
+
+ SSERR
+ desc SSERR
+ 5
+ 5
+ read-only
+
+
+ SPIF
+ desc SPIF
+ 7
+ 7
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DATA
+ desc DATA
+ 0xC
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ DAT
+ desc DAT
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CR2
+ desc CR2
+ 0x10
+ 32
+ read-write
+ 0x3
+ 0x7C
+
+
+ INT_EN
+ desc INT_EN
+ 2
+ 2
+ read-write
+
+
+ HDMA_RX
+ desc HDMA_RX
+ 3
+ 3
+ read-write
+
+
+ HDMA_TX
+ desc HDMA_TX
+ 4
+ 4
+ read-write
+
+
+ TXEIE
+ desc TXEIE
+ 5
+ 5
+ read-write
+
+
+ RXNEIE
+ desc RXNEIE
+ 6
+ 6
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFFFFFF
+ 0x1
+
+
+ INT_CLR
+ desc INT_CLR
+ 0
+ 0
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ SPI1
+ desc SPI
+ 0x40004800
+
+ 0x0
+ 0x18
+
+
+
+ SYSCTRL
+ desc SYSCTRL
+ 0x40002000
+
+ 0x0
+ 0x5C
+
+
+
+ SYSCTRL0
+ desc SYSCTRL0
+ 0x0
+ 32
+ read-write
+ 0x1
+ 0x9FFF
+
+
+ RCH_EN
+ desc RCH_EN
+ 0
+ 0
+ read-write
+
+
+ XTH_EN
+ desc XTH_EN
+ 1
+ 1
+ read-write
+
+
+ RCL_EN
+ desc RCL_EN
+ 2
+ 2
+ read-write
+
+
+ XTL_EN
+ desc XTL_EN
+ 3
+ 3
+ read-write
+
+
+ PLL_EN
+ desc PLL_EN
+ 4
+ 4
+ read-write
+
+
+ CLKSW
+ desc CLKSW
+ 7
+ 5
+ read-write
+
+
+ HCLK_PRS
+ desc HCLK_PRS
+ 10
+ 8
+ read-write
+
+
+ PCLK_PRS
+ desc PCLK_PRS
+ 12
+ 11
+ read-write
+
+
+ WAKEUP_BYRCH
+ desc WAKEUP_BYRCH
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SYSCTRL1
+ desc SYSCTRL1
+ 0x4
+ 32
+ read-write
+ 0x8
+ 0xF7E
+
+
+ EXTH_EN
+ desc EXTH_EN
+ 1
+ 1
+ read-write
+
+
+ EXTL_EN
+ desc EXTL_EN
+ 2
+ 2
+ read-write
+
+
+ XTL_ALWAYS_ON
+ desc XTL_ALWAYS_ON
+ 3
+ 3
+ read-write
+
+
+ RTC_LPW
+ desc RTC_LPW
+ 5
+ 5
+ read-write
+
+
+ LOCKUP_EN
+ desc LOCKUP_EN
+ 6
+ 6
+ read-write
+
+
+ SWD_USE_IO
+ desc SWD_USE_IO
+ 8
+ 8
+ read-write
+
+
+ RTC_FREQ_ADJUST
+ desc RTC_FREQ_ADJUST
+ 11
+ 9
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SYSCTRL2
+ desc SYSCTRL2
+ 0x8
+ 32
+ write-only
+ 0x0
+ 0xFFFF
+
+
+ SYSCTRL2
+ desc SYSCTRL2
+ 15
+ 0
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ RCH_CR
+ desc RCH_CR
+ 0xC
+ 32
+ read-write
+ 0x126
+ 0xFFF
+
+
+ TRIM
+ desc TRIM
+ 10
+ 0
+ read-write
+
+
+ STABLE
+ desc STABLE
+ 11
+ 11
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ XTH_CR
+ desc XTH_CR
+ 0x10
+ 32
+ read-write
+ 0x22
+ 0x7F
+
+
+ DRIVER
+ desc DRIVER
+ 1
+ 0
+ read-write
+
+
+ XTH_FSEL
+ desc XTH_FSEL
+ 3
+ 2
+ read-write
+
+
+ STARTUP
+ desc STARTUP
+ 5
+ 4
+ read-write
+
+
+ STABLE
+ desc STABLE
+ 6
+ 6
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ RCL_CR
+ desc RCL_CR
+ 0x14
+ 32
+ read-write
+ 0x33F
+ 0x1FFF
+
+
+ TRIM
+ desc TRIM
+ 9
+ 0
+ read-write
+
+
+ STARTUP
+ desc STARTUP
+ 11
+ 10
+ read-write
+
+
+ STABLE
+ desc STABLE
+ 12
+ 12
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ XTL_CR
+ desc XTL_CR
+ 0x18
+ 32
+ read-write
+ 0x21
+ 0x7F
+
+
+ DRIVER
+ desc DRIVER
+ 1
+ 0
+ read-write
+
+
+ AMP_SEL
+ desc AMP_SEL
+ 3
+ 2
+ read-write
+
+
+ STARTUP
+ desc STARTUP
+ 5
+ 4
+ read-write
+
+
+ STABLE
+ desc STABLE
+ 6
+ 6
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PERI_CLKEN0
+ desc PERI_CLKEN0
+ 0x20
+ 32
+ read-write
+ 0x80800000
+ 0xFF7FEFFF
+
+
+ UART0
+ desc UART0
+ 0
+ 0
+ read-write
+
+
+ UART1
+ desc UART1
+ 1
+ 1
+ read-write
+
+
+ LPUART0
+ desc LPUART0
+ 2
+ 2
+ read-write
+
+
+ LPUART1
+ desc LPUART1
+ 3
+ 3
+ read-write
+
+
+ I2C0
+ desc I2C0
+ 4
+ 4
+ read-write
+
+
+ I2C1
+ desc I2C1
+ 5
+ 5
+ read-write
+
+
+ SPI0
+ desc SPI0
+ 6
+ 6
+ read-write
+
+
+ SPI1
+ desc SPI1
+ 7
+ 7
+ read-write
+
+
+ BASETIM
+ desc BASETIM
+ 8
+ 8
+ read-write
+
+
+ LPTIM0
+ desc LPTIM0
+ 9
+ 9
+ read-write
+
+
+ ADVTIM
+ desc ADVTIM
+ 10
+ 10
+ read-write
+
+
+ TIM3
+ desc TIM3
+ 11
+ 11
+ read-write
+
+
+ OPA
+ desc OPA
+ 13
+ 13
+ read-write
+
+
+ PCA
+ desc PCA
+ 14
+ 14
+ read-write
+
+
+ WDT
+ desc WDT
+ 15
+ 15
+ read-write
+
+
+ ADC
+ desc ADC
+ 16
+ 16
+ read-write
+
+
+ VC
+ desc VC
+ 17
+ 17
+ read-write
+
+
+ RNG
+ desc RNG
+ 18
+ 18
+ read-write
+
+
+ PCNT
+ desc PCNT
+ 19
+ 19
+ read-write
+
+
+ RTC
+ desc RTC
+ 20
+ 20
+ read-write
+
+
+ TRIM
+ desc TRIM
+ 21
+ 21
+ read-write
+
+
+ LCD
+ desc LCD
+ 22
+ 22
+ read-write
+
+
+ TICK
+ desc TICK
+ 24
+ 24
+ read-write
+
+
+ SWD
+ desc SWD
+ 25
+ 25
+ read-write
+
+
+ CRC
+ desc CRC
+ 26
+ 26
+ read-write
+
+
+ AES
+ desc AES
+ 27
+ 27
+ read-write
+
+
+ GPIO
+ desc GPIO
+ 28
+ 28
+ read-write
+
+
+ DMA
+ desc DMA
+ 29
+ 29
+ read-write
+
+
+ FLASH
+ desc FLASH
+ 31
+ 31
+ read-write
+
+
+
+
+ PERI_CLKEN1
+ desc PERI_CLKEN1
+ 0x24
+ 32
+ read-write
+ 0x0
+ 0xFFF
+
+
+ DAC
+ desc DAC
+ 3
+ 3
+ read-write
+
+
+ LPTIM1
+ desc LPTIM1
+ 4
+ 4
+ read-write
+
+
+ UART2
+ desc UART2
+ 8
+ 8
+ read-write
+
+
+ UART3
+ desc UART3
+ 9
+ 9
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ PLL_CR
+ desc PLL_CR
+ 0x3C
+ 32
+ read-write
+ 0x10B0F
+ 0x3FFFF
+
+
+ REFSEL
+ desc REFSEL
+ 1
+ 0
+ read-write
+
+
+ FOSC
+ desc FOSC
+ 4
+ 2
+ read-write
+
+
+ DIVN
+ desc DIVN
+ 8
+ 5
+ read-write
+
+
+ IBSEL
+ desc IBSEL
+ 10
+ 9
+ read-write
+
+
+ LFSEL
+ desc LFSEL
+ 12
+ 11
+ read-write
+
+
+ FRSEL
+ desc FRSEL
+ 14
+ 13
+ read-write
+
+
+ STARTUP
+ desc STARTUP
+ 17
+ 15
+ read-write
+
+
+ STABLE
+ desc STABLE
+ 18
+ 18
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM0_MODE0
+ desc TIM0_MODE0
+ 0x40000C00
+
+ 0x0
+ 0x34
+
+
+
+ ARR
+ desc ARR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARR
+ desc ARR
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT32
+ desc CNT32
+ 0x8
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ CNT32
+ desc CNT32
+ 31
+ 0
+ read-write
+
+
+
+
+ M0CR
+ desc M0CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0x377F
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ MD
+ desc MD
+ 1
+ 1
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ TOGEN
+ desc TOGEN
+ 3
+ 3
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ GATE
+ desc GATE
+ 8
+ 8
+ read-write
+
+
+ GATEP
+ desc GATEP
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0x1
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0x1
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DTR
+ desc DTR
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0x1000
+
+
+ MOE
+ desc MOE
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM0_MODE1
+ desc TIM0_MODE1
+ 0x40000C00
+ TIM0_MODE0
+
+ 0x0
+ 0x40
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ M1CR
+ desc M1CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0x7775
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ EDG1ST
+ desc EDG1ST
+ 8
+ 8
+ read-write
+
+
+ EDG2ND
+ desc EDG2ND
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ ONESHOT
+ desc ONESHOT
+ 14
+ 14
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0x5
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0x5
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ MSCR
+ desc MSCR
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x18E0
+
+
+ TS
+ desc TS
+ 7
+ 5
+ read-write
+
+
+ IA0S
+ desc IA0S
+ 11
+ 11
+ read-write
+
+
+ IB0S
+ desc IB0S
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ FLTR
+ desc FLTR
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0xF0000077
+
+
+ FLTA0
+ desc FLTA0
+ 2
+ 0
+ read-write
+
+
+ FLTB0
+ desc FLTB0
+ 6
+ 4
+ read-write
+
+
+ FLTET
+ desc FLTET
+ 30
+ 28
+ read-write
+
+
+ ETP
+ desc ETP
+ 31
+ 31
+ read-write
+
+
+
+
+ CR0
+ desc CR0
+ 0x24
+ 32
+ read-write
+ 0x3000
+ 0x100
+
+
+ CIEA
+ desc CIEA
+ 8
+ 8
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0A
+ desc CCR0A
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0A
+ desc CCR0A
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM0_MODE23
+ desc TIM0_MODE23
+ 0x40000C00
+ TIM0_MODE0
+
+ 0x0
+ 0x44
+
+
+
+ ARR
+ desc ARR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARR
+ desc ARR
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ M23CR
+ desc M23CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0xFFFFFFF
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ COMP
+ desc COMP
+ 1
+ 1
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ PWM2S
+ desc PWM2S
+ 3
+ 3
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ BUFPEN
+ desc BUFPEN
+ 7
+ 7
+ read-write
+
+
+ CRG
+ desc CRG
+ 8
+ 8
+ read-write
+
+
+ CFG
+ desc CFG
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ UDE
+ desc UDE
+ 11
+ 11
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ ONESHOT
+ desc ONESHOT
+ 14
+ 14
+ read-write
+
+
+ CSG
+ desc CSG
+ 15
+ 15
+ read-write
+
+
+ OCCS
+ desc OCCS
+ 16
+ 16
+ read-write
+
+
+ URS
+ desc URS
+ 17
+ 17
+ read-write
+
+
+ TDE
+ desc TDE
+ 18
+ 18
+ read-write
+
+
+ TIE
+ desc TIE
+ 19
+ 19
+ read-write
+
+
+ BIE
+ desc BIE
+ 20
+ 20
+ read-write
+
+
+ CIS
+ desc CIS
+ 22
+ 21
+ read-write
+
+
+ OCCE
+ desc OCCE
+ 23
+ 23
+ read-write
+
+
+ TG
+ desc TG
+ 24
+ 24
+ write-only
+
+
+ UG
+ desc UG
+ 25
+ 25
+ write-only
+
+
+ BG
+ desc BG
+ 26
+ 26
+ write-only
+
+
+ DIR
+ desc DIR
+ 27
+ 27
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0xC925
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ read-only
+
+
+ CB0F
+ desc CB0F
+ 5
+ 5
+ read-only
+
+
+ CA0E
+ desc CA0E
+ 8
+ 8
+ read-only
+
+
+ CB0E
+ desc CB0E
+ 11
+ 11
+ read-only
+
+
+ BIF
+ desc BIF
+ 14
+ 14
+ read-only
+
+
+ TIF
+ desc TIF
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0xC925
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ write-only
+
+
+ CB0F
+ desc CB0F
+ 5
+ 5
+ write-only
+
+
+ CA0E
+ desc CA0E
+ 8
+ 8
+ write-only
+
+
+ CB0E
+ desc CB0E
+ 11
+ 11
+ write-only
+
+
+ BIF
+ desc BIF
+ 14
+ 14
+ write-only
+
+
+ TIF
+ desc TIF
+ 15
+ 15
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ MSCR
+ desc MSCR
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x1FFF
+
+
+ MMS
+ desc MMS
+ 2
+ 0
+ read-write
+
+
+ CCDS
+ desc CCDS
+ 3
+ 3
+ read-write
+
+
+ MSM
+ desc MSM
+ 4
+ 4
+ read-write
+
+
+ TS
+ desc TS
+ 7
+ 5
+ read-write
+
+
+ SMS
+ desc SMS
+ 10
+ 8
+ read-write
+
+
+ IA0S
+ desc IA0S
+ 11
+ 11
+ read-write
+
+
+ IB0S
+ desc IB0S
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ FLTR
+ desc FLTR
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ OCMA0_FLTA0
+ desc OCMA0_FLTA0
+ 2
+ 0
+ read-write
+
+
+ CCPA0
+ desc CCPA0
+ 3
+ 3
+ read-write
+
+
+ OCMB0_FLTB0
+ desc OCMB0_FLTB0
+ 6
+ 4
+ read-write
+
+
+ CCPB0
+ desc CCPB0
+ 7
+ 7
+ read-write
+
+
+ FLTBK
+ desc FLTBK
+ 26
+ 24
+ read-write
+
+
+ BKP
+ desc BKP
+ 27
+ 27
+ read-write
+
+
+ FLTET
+ desc FLTET
+ 30
+ 28
+ read-write
+
+
+ ETP
+ desc ETP
+ 31
+ 31
+ read-write
+
+
+
+
+ ADTR
+ desc ADTR
+ 0x20
+ 32
+ read-write
+ 0x0
+ 0x93
+
+
+ UEVE
+ desc UEVE
+ 0
+ 0
+ read-write
+
+
+ CMA0E
+ desc CMA0E
+ 1
+ 1
+ read-write
+
+
+ CMB0E
+ desc CMB0E
+ 4
+ 4
+ read-write
+
+
+ ADTE
+ desc ADTE
+ 7
+ 7
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CRCH0
+ desc CRCH0
+ 0x24
+ 32
+ read-write
+ 0x3000
+ 0xFFFF
+
+
+ CFA_CRA_BKSA
+ desc CFA_CRA_BKSA
+ 1
+ 0
+ read-write
+
+
+ CFB_CRB_BKSB
+ desc CFB_CRB_BKSB
+ 3
+ 2
+ read-write
+
+
+ CSA
+ desc CSA
+ 4
+ 4
+ read-write
+
+
+ CSB
+ desc CSB
+ 5
+ 5
+ read-write
+
+
+ BUFEA
+ desc BUFEA
+ 6
+ 6
+ read-write
+
+
+ BUFEB
+ desc BUFEB
+ 7
+ 7
+ read-write
+
+
+ CIEA
+ desc CIEA
+ 8
+ 8
+ read-write
+
+
+ CIEB
+ desc CIEB
+ 9
+ 9
+ read-write
+
+
+ CDEA
+ desc CDEA
+ 10
+ 10
+ read-write
+
+
+ CDEB
+ desc CDEB
+ 11
+ 11
+ read-write
+
+
+ CISB
+ desc CISB
+ 13
+ 12
+ read-write
+
+
+ CCGA
+ desc CCGA
+ 14
+ 14
+ read-write
+
+
+ CCGB
+ desc CCGB
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DTR
+ desc DTR
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ DTR
+ desc DTR
+ 7
+ 0
+ read-write
+
+
+ BKSEL
+ desc BKSEL
+ 8
+ 8
+ read-write
+
+
+ DTEN
+ desc DTEN
+ 9
+ 9
+ read-write
+
+
+ BKE
+ desc BKE
+ 10
+ 10
+ read-write
+
+
+ AOE
+ desc AOE
+ 11
+ 11
+ read-write
+
+
+ MOE
+ desc MOE
+ 12
+ 12
+ read-write
+
+
+ SAFEEN
+ desc SAFEEN
+ 13
+ 13
+ read-write
+
+
+ VCE
+ desc VCE
+ 14
+ 14
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ RCR
+ desc RCR
+ 0x34
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ RCR
+ desc RCR
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ARRDM
+ desc ARRDM
+ 0x38
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARRDM
+ desc ARRDM
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0A
+ desc CCR0A
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0A
+ desc CCR0A
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0B
+ desc CCR0B
+ 0x40
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0B
+ desc CCR0B
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM1_MODE0
+ desc TIM1_MODE0
+ 0x40000D00
+
+ 0x0
+ 0x34
+
+
+
+ ARR
+ desc ARR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARR
+ desc ARR
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT32
+ desc CNT32
+ 0x8
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ CNT32
+ desc CNT32
+ 31
+ 0
+ read-write
+
+
+
+
+ M0CR
+ desc M0CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0x377F
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ MD
+ desc MD
+ 1
+ 1
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ TOGEN
+ desc TOGEN
+ 3
+ 3
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ GATE
+ desc GATE
+ 8
+ 8
+ read-write
+
+
+ GATEP
+ desc GATEP
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0x1
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0x1
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DTR
+ desc DTR
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0x1000
+
+
+ MOE
+ desc MOE
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM1_MODE1
+ desc TIM1_MODE1
+ 0x40000D00
+ TIM1_MODE0
+
+ 0x0
+ 0x40
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ M1CR
+ desc M1CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0x7775
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ EDG1ST
+ desc EDG1ST
+ 8
+ 8
+ read-write
+
+
+ EDG2ND
+ desc EDG2ND
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ ONESHOT
+ desc ONESHOT
+ 14
+ 14
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0x5
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0x5
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ MSCR
+ desc MSCR
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x18E0
+
+
+ TS
+ desc TS
+ 7
+ 5
+ read-write
+
+
+ IA0S
+ desc IA0S
+ 11
+ 11
+ read-write
+
+
+ IB0S
+ desc IB0S
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ FLTR
+ desc FLTR
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0xF0000077
+
+
+ FLTA0
+ desc FLTA0
+ 2
+ 0
+ read-write
+
+
+ FLTB0
+ desc FLTB0
+ 6
+ 4
+ read-write
+
+
+ FLTET
+ desc FLTET
+ 30
+ 28
+ read-write
+
+
+ ETP
+ desc ETP
+ 31
+ 31
+ read-write
+
+
+
+
+ CR0
+ desc CR0
+ 0x24
+ 32
+ read-write
+ 0x3000
+ 0x100
+
+
+ CIEA
+ desc CIEA
+ 8
+ 8
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0A
+ desc CCR0A
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0A
+ desc CCR0A
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM1_MODE23
+ desc TIM1_MODE23
+ 0x40000D00
+ TIM1_MODE0
+
+ 0x0
+ 0x44
+
+
+
+ ARR
+ desc ARR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARR
+ desc ARR
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ M23CR
+ desc M23CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0xFFFFFFF
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ COMP
+ desc COMP
+ 1
+ 1
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ PWM2S
+ desc PWM2S
+ 3
+ 3
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ BUFPEN
+ desc BUFPEN
+ 7
+ 7
+ read-write
+
+
+ CRG
+ desc CRG
+ 8
+ 8
+ read-write
+
+
+ CFG
+ desc CFG
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ UDE
+ desc UDE
+ 11
+ 11
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ ONESHOT
+ desc ONESHOT
+ 14
+ 14
+ read-write
+
+
+ CSG
+ desc CSG
+ 15
+ 15
+ read-write
+
+
+ OCCS
+ desc OCCS
+ 16
+ 16
+ read-write
+
+
+ URS
+ desc URS
+ 17
+ 17
+ read-write
+
+
+ TDE
+ desc TDE
+ 18
+ 18
+ read-write
+
+
+ TIE
+ desc TIE
+ 19
+ 19
+ read-write
+
+
+ BIE
+ desc BIE
+ 20
+ 20
+ read-write
+
+
+ CIS
+ desc CIS
+ 22
+ 21
+ read-write
+
+
+ OCCE
+ desc OCCE
+ 23
+ 23
+ read-write
+
+
+ TG
+ desc TG
+ 24
+ 24
+ write-only
+
+
+ UG
+ desc UG
+ 25
+ 25
+ write-only
+
+
+ BG
+ desc BG
+ 26
+ 26
+ write-only
+
+
+ DIR
+ desc DIR
+ 27
+ 27
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0xC925
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ read-only
+
+
+ CB0F
+ desc CB0F
+ 5
+ 5
+ read-only
+
+
+ CA0E
+ desc CA0E
+ 8
+ 8
+ read-only
+
+
+ CB0E
+ desc CB0E
+ 11
+ 11
+ read-only
+
+
+ BIF
+ desc BIF
+ 14
+ 14
+ read-only
+
+
+ TIF
+ desc TIF
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0xC925
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ write-only
+
+
+ CB0F
+ desc CB0F
+ 5
+ 5
+ write-only
+
+
+ CA0E
+ desc CA0E
+ 8
+ 8
+ write-only
+
+
+ CB0E
+ desc CB0E
+ 11
+ 11
+ write-only
+
+
+ BIF
+ desc BIF
+ 14
+ 14
+ write-only
+
+
+ TIF
+ desc TIF
+ 15
+ 15
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ MSCR
+ desc MSCR
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x1FFF
+
+
+ MMS
+ desc MMS
+ 2
+ 0
+ read-write
+
+
+ CCDS
+ desc CCDS
+ 3
+ 3
+ read-write
+
+
+ MSM
+ desc MSM
+ 4
+ 4
+ read-write
+
+
+ TS
+ desc TS
+ 7
+ 5
+ read-write
+
+
+ SMS
+ desc SMS
+ 10
+ 8
+ read-write
+
+
+ IA0S
+ desc IA0S
+ 11
+ 11
+ read-write
+
+
+ IB0S
+ desc IB0S
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ FLTR
+ desc FLTR
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ OCMA0_FLTA0
+ desc OCMA0_FLTA0
+ 2
+ 0
+ read-write
+
+
+ CCPA0
+ desc CCPA0
+ 3
+ 3
+ read-write
+
+
+ OCMB0_FLTB0
+ desc OCMB0_FLTB0
+ 6
+ 4
+ read-write
+
+
+ CCPB0
+ desc CCPB0
+ 7
+ 7
+ read-write
+
+
+ FLTBK
+ desc FLTBK
+ 26
+ 24
+ read-write
+
+
+ BKP
+ desc BKP
+ 27
+ 27
+ read-write
+
+
+ FLTET
+ desc FLTET
+ 30
+ 28
+ read-write
+
+
+ ETP
+ desc ETP
+ 31
+ 31
+ read-write
+
+
+
+
+ ADTR
+ desc ADTR
+ 0x20
+ 32
+ read-write
+ 0x0
+ 0x93
+
+
+ UEVE
+ desc UEVE
+ 0
+ 0
+ read-write
+
+
+ CMA0E
+ desc CMA0E
+ 1
+ 1
+ read-write
+
+
+ CMB0E
+ desc CMB0E
+ 4
+ 4
+ read-write
+
+
+ ADTE
+ desc ADTE
+ 7
+ 7
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CRCH0
+ desc CRCH0
+ 0x24
+ 32
+ read-write
+ 0x3000
+ 0xFFFF
+
+
+ CFA_CRA_BKSA
+ desc CFA_CRA_BKSA
+ 1
+ 0
+ read-write
+
+
+ CFB_CRB_BKSB
+ desc CFB_CRB_BKSB
+ 3
+ 2
+ read-write
+
+
+ CSA
+ desc CSA
+ 4
+ 4
+ read-write
+
+
+ CSB
+ desc CSB
+ 5
+ 5
+ read-write
+
+
+ BUFEA
+ desc BUFEA
+ 6
+ 6
+ read-write
+
+
+ BUFEB
+ desc BUFEB
+ 7
+ 7
+ read-write
+
+
+ CIEA
+ desc CIEA
+ 8
+ 8
+ read-write
+
+
+ CIEB
+ desc CIEB
+ 9
+ 9
+ read-write
+
+
+ CDEA
+ desc CDEA
+ 10
+ 10
+ read-write
+
+
+ CDEB
+ desc CDEB
+ 11
+ 11
+ read-write
+
+
+ CISB
+ desc CISB
+ 13
+ 12
+ read-write
+
+
+ CCGA
+ desc CCGA
+ 14
+ 14
+ read-write
+
+
+ CCGB
+ desc CCGB
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DTR
+ desc DTR
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ DTR
+ desc DTR
+ 7
+ 0
+ read-write
+
+
+ BKSEL
+ desc BKSEL
+ 8
+ 8
+ read-write
+
+
+ DTEN
+ desc DTEN
+ 9
+ 9
+ read-write
+
+
+ BKE
+ desc BKE
+ 10
+ 10
+ read-write
+
+
+ AOE
+ desc AOE
+ 11
+ 11
+ read-write
+
+
+ MOE
+ desc MOE
+ 12
+ 12
+ read-write
+
+
+ SAFEEN
+ desc SAFEEN
+ 13
+ 13
+ read-write
+
+
+ VCE
+ desc VCE
+ 14
+ 14
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ RCR
+ desc RCR
+ 0x34
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ RCR
+ desc RCR
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ARRDM
+ desc ARRDM
+ 0x38
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARRDM
+ desc ARRDM
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0A
+ desc CCR0A
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0A
+ desc CCR0A
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0B
+ desc CCR0B
+ 0x40
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0B
+ desc CCR0B
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM2_MODE0
+ desc TIM2_MODE0
+ 0x40000E00
+
+ 0x0
+ 0x34
+
+
+
+ ARR
+ desc ARR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARR
+ desc ARR
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT32
+ desc CNT32
+ 0x8
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ CNT32
+ desc CNT32
+ 31
+ 0
+ read-write
+
+
+
+
+ M0CR
+ desc M0CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0x377F
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ MD
+ desc MD
+ 1
+ 1
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ TOGEN
+ desc TOGEN
+ 3
+ 3
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ GATE
+ desc GATE
+ 8
+ 8
+ read-write
+
+
+ GATEP
+ desc GATEP
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0x1
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0x1
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DTR
+ desc DTR
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0x1000
+
+
+ MOE
+ desc MOE
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM2_MODE1
+ desc TIM2_MODE1
+ 0x40000E00
+ TIM2_MODE0
+
+ 0x0
+ 0x40
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ M1CR
+ desc M1CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0x7775
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ EDG1ST
+ desc EDG1ST
+ 8
+ 8
+ read-write
+
+
+ EDG2ND
+ desc EDG2ND
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ ONESHOT
+ desc ONESHOT
+ 14
+ 14
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0x5
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0x5
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ MSCR
+ desc MSCR
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x18E0
+
+
+ TS
+ desc TS
+ 7
+ 5
+ read-write
+
+
+ IA0S
+ desc IA0S
+ 11
+ 11
+ read-write
+
+
+ IB0S
+ desc IB0S
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ FLTR
+ desc FLTR
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0xF0000077
+
+
+ FLTA0
+ desc FLTA0
+ 2
+ 0
+ read-write
+
+
+ FLTB0
+ desc FLTB0
+ 6
+ 4
+ read-write
+
+
+ FLTET
+ desc FLTET
+ 30
+ 28
+ read-write
+
+
+ ETP
+ desc ETP
+ 31
+ 31
+ read-write
+
+
+
+
+ CR0
+ desc CR0
+ 0x24
+ 32
+ read-write
+ 0x3000
+ 0x100
+
+
+ CIEA
+ desc CIEA
+ 8
+ 8
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0A
+ desc CCR0A
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0A
+ desc CCR0A
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM2_MODE23
+ desc TIM2_MODE23
+ 0x40000E00
+ TIM2_MODE0
+
+ 0x0
+ 0x44
+
+
+
+ ARR
+ desc ARR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARR
+ desc ARR
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ M23CR
+ desc M23CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0xFFFFFFF
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ COMP
+ desc COMP
+ 1
+ 1
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ PWM2S
+ desc PWM2S
+ 3
+ 3
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ BUFPEN
+ desc BUFPEN
+ 7
+ 7
+ read-write
+
+
+ CRG
+ desc CRG
+ 8
+ 8
+ read-write
+
+
+ CFG
+ desc CFG
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ UDE
+ desc UDE
+ 11
+ 11
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ ONESHOT
+ desc ONESHOT
+ 14
+ 14
+ read-write
+
+
+ CSG
+ desc CSG
+ 15
+ 15
+ read-write
+
+
+ OCCS
+ desc OCCS
+ 16
+ 16
+ read-write
+
+
+ URS
+ desc URS
+ 17
+ 17
+ read-write
+
+
+ TDE
+ desc TDE
+ 18
+ 18
+ read-write
+
+
+ TIE
+ desc TIE
+ 19
+ 19
+ read-write
+
+
+ BIE
+ desc BIE
+ 20
+ 20
+ read-write
+
+
+ CIS
+ desc CIS
+ 22
+ 21
+ read-write
+
+
+ OCCE
+ desc OCCE
+ 23
+ 23
+ read-write
+
+
+ TG
+ desc TG
+ 24
+ 24
+ write-only
+
+
+ UG
+ desc UG
+ 25
+ 25
+ write-only
+
+
+ BG
+ desc BG
+ 26
+ 26
+ write-only
+
+
+ DIR
+ desc DIR
+ 27
+ 27
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0xC925
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ read-only
+
+
+ CB0F
+ desc CB0F
+ 5
+ 5
+ read-only
+
+
+ CA0E
+ desc CA0E
+ 8
+ 8
+ read-only
+
+
+ CB0E
+ desc CB0E
+ 11
+ 11
+ read-only
+
+
+ BIF
+ desc BIF
+ 14
+ 14
+ read-only
+
+
+ TIF
+ desc TIF
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0xC925
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ write-only
+
+
+ CB0F
+ desc CB0F
+ 5
+ 5
+ write-only
+
+
+ CA0E
+ desc CA0E
+ 8
+ 8
+ write-only
+
+
+ CB0E
+ desc CB0E
+ 11
+ 11
+ write-only
+
+
+ BIF
+ desc BIF
+ 14
+ 14
+ write-only
+
+
+ TIF
+ desc TIF
+ 15
+ 15
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ MSCR
+ desc MSCR
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x1FFF
+
+
+ MMS
+ desc MMS
+ 2
+ 0
+ read-write
+
+
+ CCDS
+ desc CCDS
+ 3
+ 3
+ read-write
+
+
+ MSM
+ desc MSM
+ 4
+ 4
+ read-write
+
+
+ TS
+ desc TS
+ 7
+ 5
+ read-write
+
+
+ SMS
+ desc SMS
+ 10
+ 8
+ read-write
+
+
+ IA0S
+ desc IA0S
+ 11
+ 11
+ read-write
+
+
+ IB0S
+ desc IB0S
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ FLTR
+ desc FLTR
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ OCMA0_FLTA0
+ desc OCMA0_FLTA0
+ 2
+ 0
+ read-write
+
+
+ CCPA0
+ desc CCPA0
+ 3
+ 3
+ read-write
+
+
+ OCMB0_FLTB0
+ desc OCMB0_FLTB0
+ 6
+ 4
+ read-write
+
+
+ CCPB0
+ desc CCPB0
+ 7
+ 7
+ read-write
+
+
+ FLTBK
+ desc FLTBK
+ 26
+ 24
+ read-write
+
+
+ BKP
+ desc BKP
+ 27
+ 27
+ read-write
+
+
+ FLTET
+ desc FLTET
+ 30
+ 28
+ read-write
+
+
+ ETP
+ desc ETP
+ 31
+ 31
+ read-write
+
+
+
+
+ ADTR
+ desc ADTR
+ 0x20
+ 32
+ read-write
+ 0x0
+ 0x93
+
+
+ UEVE
+ desc UEVE
+ 0
+ 0
+ read-write
+
+
+ CMA0E
+ desc CMA0E
+ 1
+ 1
+ read-write
+
+
+ CMB0E
+ desc CMB0E
+ 4
+ 4
+ read-write
+
+
+ ADTE
+ desc ADTE
+ 7
+ 7
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CRCH0
+ desc CRCH0
+ 0x24
+ 32
+ read-write
+ 0x3000
+ 0xFFFF
+
+
+ CFA_CRA_BKSA
+ desc CFA_CRA_BKSA
+ 1
+ 0
+ read-write
+
+
+ CFB_CRB_BKSB
+ desc CFB_CRB_BKSB
+ 3
+ 2
+ read-write
+
+
+ CSA
+ desc CSA
+ 4
+ 4
+ read-write
+
+
+ CSB
+ desc CSB
+ 5
+ 5
+ read-write
+
+
+ BUFEA
+ desc BUFEA
+ 6
+ 6
+ read-write
+
+
+ BUFEB
+ desc BUFEB
+ 7
+ 7
+ read-write
+
+
+ CIEA
+ desc CIEA
+ 8
+ 8
+ read-write
+
+
+ CIEB
+ desc CIEB
+ 9
+ 9
+ read-write
+
+
+ CDEA
+ desc CDEA
+ 10
+ 10
+ read-write
+
+
+ CDEB
+ desc CDEB
+ 11
+ 11
+ read-write
+
+
+ CISB
+ desc CISB
+ 13
+ 12
+ read-write
+
+
+ CCGA
+ desc CCGA
+ 14
+ 14
+ read-write
+
+
+ CCGB
+ desc CCGB
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DTR
+ desc DTR
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ DTR
+ desc DTR
+ 7
+ 0
+ read-write
+
+
+ BKSEL
+ desc BKSEL
+ 8
+ 8
+ read-write
+
+
+ DTEN
+ desc DTEN
+ 9
+ 9
+ read-write
+
+
+ BKE
+ desc BKE
+ 10
+ 10
+ read-write
+
+
+ AOE
+ desc AOE
+ 11
+ 11
+ read-write
+
+
+ MOE
+ desc MOE
+ 12
+ 12
+ read-write
+
+
+ SAFEEN
+ desc SAFEEN
+ 13
+ 13
+ read-write
+
+
+ VCE
+ desc VCE
+ 14
+ 14
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ RCR
+ desc RCR
+ 0x34
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ RCR
+ desc RCR
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ARRDM
+ desc ARRDM
+ 0x38
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARRDM
+ desc ARRDM
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0A
+ desc CCR0A
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0A
+ desc CCR0A
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0B
+ desc CCR0B
+ 0x40
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0B
+ desc CCR0B
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM3_MODE0
+ desc TIM3_MODE0
+ 0x40005800
+
+ 0x0
+ 0x34
+
+
+
+ ARR
+ desc ARR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARR
+ desc ARR
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT32
+ desc CNT32
+ 0x8
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ CNT32
+ desc CNT32
+ 31
+ 0
+ read-write
+
+
+
+
+ M0CR
+ desc M0CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0x377F
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ MD
+ desc MD
+ 1
+ 1
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ TOGEN
+ desc TOGEN
+ 3
+ 3
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ GATE
+ desc GATE
+ 8
+ 8
+ read-write
+
+
+ GATEP
+ desc GATEP
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0x1
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0x1
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DTR
+ desc DTR
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0x1000
+
+
+ MOE
+ desc MOE
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM3_MODE1
+ desc TIM3_MODE1
+ 0x40005800
+ TIM3_MODE0
+
+ 0x0
+ 0x40
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ M1CR
+ desc M1CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0x7775
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ EDG1ST
+ desc EDG1ST
+ 8
+ 8
+ read-write
+
+
+ EDG2ND
+ desc EDG2ND
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ ONESHOT
+ desc ONESHOT
+ 14
+ 14
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0x5
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0x5
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ MSCR
+ desc MSCR
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x18E0
+
+
+ TS
+ desc TS
+ 7
+ 5
+ read-write
+
+
+ IA0S
+ desc IA0S
+ 11
+ 11
+ read-write
+
+
+ IB0S
+ desc IB0S
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ FLTR
+ desc FLTR
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0xF0000077
+
+
+ FLTA0
+ desc FLTA0
+ 2
+ 0
+ read-write
+
+
+ FLTB0
+ desc FLTB0
+ 6
+ 4
+ read-write
+
+
+ FLTET
+ desc FLTET
+ 30
+ 28
+ read-write
+
+
+ ETP
+ desc ETP
+ 31
+ 31
+ read-write
+
+
+
+
+ CR0
+ desc CR0
+ 0x24
+ 32
+ read-write
+ 0x3000
+ 0x100
+
+
+ CIEA
+ desc CIEA
+ 8
+ 8
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0A
+ desc CCR0A
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0A
+ desc CCR0A
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TIM3_MODE23
+ desc TIM3_MODE23
+ 0x40005800
+ TIM3_MODE0
+
+ 0x0
+ 0x54
+
+
+
+ ARR
+ desc ARR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARR
+ desc ARR
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CNT
+ desc CNT
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CNT
+ desc CNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ M23CR
+ desc M23CR
+ 0xC
+ 32
+ read-write
+ 0x600008
+ 0xFFFFFFF
+
+
+ CTEN
+ desc CTEN
+ 0
+ 0
+ read-write
+
+
+ COMP
+ desc COMP
+ 1
+ 1
+ read-write
+
+
+ CT
+ desc CT
+ 2
+ 2
+ read-write
+
+
+ PWM2S
+ desc PWM2S
+ 3
+ 3
+ read-write
+
+
+ PRS
+ desc PRS
+ 6
+ 4
+ read-write
+
+
+ BUFPEN
+ desc BUFPEN
+ 7
+ 7
+ read-write
+
+
+ CRG
+ desc CRG
+ 8
+ 8
+ read-write
+
+
+ CFG
+ desc CFG
+ 9
+ 9
+ read-write
+
+
+ UIE
+ desc UIE
+ 10
+ 10
+ read-write
+
+
+ UDE
+ desc UDE
+ 11
+ 11
+ read-write
+
+
+ MODE
+ desc MODE
+ 13
+ 12
+ read-write
+
+
+ ONESHOT
+ desc ONESHOT
+ 14
+ 14
+ read-write
+
+
+ CSG
+ desc CSG
+ 15
+ 15
+ read-write
+
+
+ OCCS
+ desc OCCS
+ 16
+ 16
+ read-write
+
+
+ URS
+ desc URS
+ 17
+ 17
+ read-write
+
+
+ TDE
+ desc TDE
+ 18
+ 18
+ read-write
+
+
+ TIE
+ desc TIE
+ 19
+ 19
+ read-write
+
+
+ BIE
+ desc BIE
+ 20
+ 20
+ read-write
+
+
+ CIS
+ desc CIS
+ 22
+ 21
+ read-write
+
+
+ OCCE
+ desc OCCE
+ 23
+ 23
+ read-write
+
+
+ TG
+ desc TG
+ 24
+ 24
+ write-only
+
+
+ UG
+ desc UG
+ 25
+ 25
+ write-only
+
+
+ BG
+ desc BG
+ 26
+ 26
+ write-only
+
+
+ DIR
+ desc DIR
+ 27
+ 27
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0xFFFD
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ read-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ read-only
+
+
+ CA1F
+ desc CA1F
+ 3
+ 3
+ read-only
+
+
+ CA2F
+ desc CA2F
+ 4
+ 4
+ read-only
+
+
+ CB0F
+ desc CB0F
+ 5
+ 5
+ read-only
+
+
+ CB1F
+ desc CB1F
+ 6
+ 6
+ read-only
+
+
+ CB2F
+ desc CB2F
+ 7
+ 7
+ read-only
+
+
+ CA0E
+ desc CA0E
+ 8
+ 8
+ read-only
+
+
+ CA1E
+ desc CA1E
+ 9
+ 9
+ read-only
+
+
+ CA2E
+ desc CA2E
+ 10
+ 10
+ read-only
+
+
+ CB0E
+ desc CB0E
+ 11
+ 11
+ read-only
+
+
+ CB1E
+ desc CB1E
+ 12
+ 12
+ read-only
+
+
+ CB2E
+ desc CB2E
+ 13
+ 13
+ read-only
+
+
+ BIF
+ desc BIF
+ 14
+ 14
+ read-only
+
+
+ TIF
+ desc TIF
+ 15
+ 15
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICLR
+ desc ICLR
+ 0x14
+ 32
+ write-only
+ 0xFFFF
+ 0xFFFD
+
+
+ UIF
+ desc UIF
+ 0
+ 0
+ write-only
+
+
+ CA0F
+ desc CA0F
+ 2
+ 2
+ write-only
+
+
+ CA1F
+ desc CA1F
+ 3
+ 3
+ write-only
+
+
+ CA2F
+ desc CA2F
+ 4
+ 4
+ write-only
+
+
+ CB0F
+ desc CB0F
+ 5
+ 5
+ write-only
+
+
+ CB1F
+ desc CB1F
+ 6
+ 6
+ write-only
+
+
+ CB2F
+ desc CB2F
+ 7
+ 7
+ write-only
+
+
+ CA0E
+ desc CA0E
+ 8
+ 8
+ write-only
+
+
+ CA1E
+ desc CA1E
+ 9
+ 9
+ write-only
+
+
+ CA2E
+ desc CA2E
+ 10
+ 10
+ write-only
+
+
+ CB0E
+ desc CB0E
+ 11
+ 11
+ write-only
+
+
+ CB1E
+ desc CB1E
+ 12
+ 12
+ write-only
+
+
+ CB2E
+ desc CB2E
+ 13
+ 13
+ write-only
+
+
+ BIF
+ desc BIF
+ 14
+ 14
+ write-only
+
+
+ TIF
+ desc TIF
+ 15
+ 15
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ MSCR
+ desc MSCR
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x1FFF
+
+
+ MMS
+ desc MMS
+ 2
+ 0
+ read-write
+
+
+ CCDS
+ desc CCDS
+ 3
+ 3
+ read-write
+
+
+ MSM
+ desc MSM
+ 4
+ 4
+ read-write
+
+
+ TS
+ desc TS
+ 7
+ 5
+ read-write
+
+
+ SMS
+ desc SMS
+ 10
+ 8
+ read-write
+
+
+ IA0S
+ desc IA0S
+ 11
+ 11
+ read-write
+
+
+ IB0S
+ desc IB0S
+ 12
+ 12
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ FLTR
+ desc FLTR
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0xFFFFFFFF
+
+
+ OCMA0_FLTA0
+ desc OCMA0_FLTA0
+ 2
+ 0
+ read-write
+
+
+ CCPA0
+ desc CCPA0
+ 3
+ 3
+ read-write
+
+
+ OCMB0_FLTB0
+ desc OCMB0_FLTB0
+ 6
+ 4
+ read-write
+
+
+ CCPB0
+ desc CCPB0
+ 7
+ 7
+ read-write
+
+
+ OCMA1_FLTA1
+ desc OCMA1_FLTA1
+ 10
+ 8
+ read-write
+
+
+ CCPA1
+ desc CCPA1
+ 11
+ 11
+ read-write
+
+
+ OCMB1_FLTB1
+ desc OCMB1_FLTB1
+ 14
+ 12
+ read-write
+
+
+ CCPB1
+ desc CCPB1
+ 15
+ 15
+ read-write
+
+
+ OCMA2_FLTA2
+ desc OCMA2_FLTA2
+ 18
+ 16
+ read-write
+
+
+ CCPA2
+ desc CCPA2
+ 19
+ 19
+ read-write
+
+
+ OCMB2_FLTB2
+ desc OCMB2_FLTB2
+ 22
+ 20
+ read-write
+
+
+ CCPB2
+ desc CCPB2
+ 23
+ 23
+ read-write
+
+
+ FLTBK
+ desc FLTBK
+ 26
+ 24
+ read-write
+
+
+ BKP
+ desc BKP
+ 27
+ 27
+ read-write
+
+
+ FLTET
+ desc FLTET
+ 30
+ 28
+ read-write
+
+
+ ETP
+ desc ETP
+ 31
+ 31
+ read-write
+
+
+
+
+ ADTR
+ desc ADTR
+ 0x20
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ UEVE
+ desc UEVE
+ 0
+ 0
+ read-write
+
+
+ CMA0E
+ desc CMA0E
+ 1
+ 1
+ read-write
+
+
+ CMA1E
+ desc CMA1E
+ 2
+ 2
+ read-write
+
+
+ CMA2E
+ desc CMA2E
+ 3
+ 3
+ read-write
+
+
+ CMB0E
+ desc CMB0E
+ 4
+ 4
+ read-write
+
+
+ CMB1E
+ desc CMB1E
+ 5
+ 5
+ read-write
+
+
+ CMB2E
+ desc CMB2E
+ 6
+ 6
+ read-write
+
+
+ ADTE
+ desc ADTE
+ 7
+ 7
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CRCH0
+ desc CRCH0
+ 0x24
+ 32
+ read-write
+ 0x3000
+ 0xFFFF
+
+
+ CFA_CRA_BKSA
+ desc CFA_CRA_BKSA
+ 1
+ 0
+ read-write
+
+
+ CFB_CRB_BKSB
+ desc CFB_CRB_BKSB
+ 3
+ 2
+ read-write
+
+
+ CSA
+ desc CSA
+ 4
+ 4
+ read-write
+
+
+ CSB
+ desc CSB
+ 5
+ 5
+ read-write
+
+
+ BUFEA
+ desc BUFEA
+ 6
+ 6
+ read-write
+
+
+ BUFEB
+ desc BUFEB
+ 7
+ 7
+ read-write
+
+
+ CIEA
+ desc CIEA
+ 8
+ 8
+ read-write
+
+
+ CIEB
+ desc CIEB
+ 9
+ 9
+ read-write
+
+
+ CDEA
+ desc CDEA
+ 10
+ 10
+ read-write
+
+
+ CDEB
+ desc CDEB
+ 11
+ 11
+ read-write
+
+
+ CISB
+ desc CISB
+ 13
+ 12
+ read-write
+
+
+ CCGA
+ desc CCGA
+ 14
+ 14
+ read-write
+
+
+ CCGB
+ desc CCGB
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CRCH1
+ desc CRCH1
+ 0x28
+ 32
+ read-write
+ 0x3000
+ 0xFFFF
+
+
+ CFA_CRA_BKSA
+ desc CFA_CRA_BKSA
+ 1
+ 0
+ read-write
+
+
+ CFB_CRB_BKSB
+ desc CFB_CRB_BKSB
+ 3
+ 2
+ read-write
+
+
+ CSA
+ desc CSA
+ 4
+ 4
+ read-write
+
+
+ CSB
+ desc CSB
+ 5
+ 5
+ read-write
+
+
+ BUFEA
+ desc BUFEA
+ 6
+ 6
+ read-write
+
+
+ BUFEB
+ desc BUFEB
+ 7
+ 7
+ read-write
+
+
+ CIEA
+ desc CIEA
+ 8
+ 8
+ read-write
+
+
+ CIEB
+ desc CIEB
+ 9
+ 9
+ read-write
+
+
+ CDEA
+ desc CDEA
+ 10
+ 10
+ read-write
+
+
+ CDEB
+ desc CDEB
+ 11
+ 11
+ read-write
+
+
+ CISB
+ desc CISB
+ 13
+ 12
+ read-write
+
+
+ CCGA
+ desc CCGA
+ 14
+ 14
+ read-write
+
+
+ CCGB
+ desc CCGB
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CRCH2
+ desc CRCH2
+ 0x2C
+ 32
+ read-write
+ 0x3000
+ 0xFFFF
+
+
+ CFA_CRA_BKSA
+ desc CFA_CRA_BKSA
+ 1
+ 0
+ read-write
+
+
+ CFB_CRB_BKSB
+ desc CFB_CRB_BKSB
+ 3
+ 2
+ read-write
+
+
+ CSA
+ desc CSA
+ 4
+ 4
+ read-write
+
+
+ CSB
+ desc CSB
+ 5
+ 5
+ read-write
+
+
+ BUFEA
+ desc BUFEA
+ 6
+ 6
+ read-write
+
+
+ BUFEB
+ desc BUFEB
+ 7
+ 7
+ read-write
+
+
+ CIEA
+ desc CIEA
+ 8
+ 8
+ read-write
+
+
+ CIEB
+ desc CIEB
+ 9
+ 9
+ read-write
+
+
+ CDEA
+ desc CDEA
+ 10
+ 10
+ read-write
+
+
+ CDEB
+ desc CDEB
+ 11
+ 11
+ read-write
+
+
+ CISB
+ desc CISB
+ 13
+ 12
+ read-write
+
+
+ CCGA
+ desc CCGA
+ 14
+ 14
+ read-write
+
+
+ CCGB
+ desc CCGB
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DTR
+ desc DTR
+ 0x30
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ DTR
+ desc DTR
+ 7
+ 0
+ read-write
+
+
+ BKSEL
+ desc BKSEL
+ 8
+ 8
+ read-write
+
+
+ DTEN
+ desc DTEN
+ 9
+ 9
+ read-write
+
+
+ BKE
+ desc BKE
+ 10
+ 10
+ read-write
+
+
+ AOE
+ desc AOE
+ 11
+ 11
+ read-write
+
+
+ MOE
+ desc MOE
+ 12
+ 12
+ read-write
+
+
+ SAFEEN
+ desc SAFEEN
+ 13
+ 13
+ read-write
+
+
+ VCE
+ desc VCE
+ 14
+ 14
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ RCR
+ desc RCR
+ 0x34
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ RCR
+ desc RCR
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ARRDM
+ desc ARRDM
+ 0x38
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ ARRDM
+ desc ARRDM
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0A
+ desc CCR0A
+ 0x3C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0A
+ desc CCR0A
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR0B
+ desc CCR0B
+ 0x40
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR0B
+ desc CCR0B
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR1A
+ desc CCR1A
+ 0x44
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR1A
+ desc CCR1A
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR1B
+ desc CCR1B
+ 0x48
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR1B
+ desc CCR1B
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR2A
+ desc CCR2A
+ 0x4C
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR2A
+ desc CCR2A
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CCR2B
+ desc CCR2B
+ 0x50
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ CCR2B
+ desc CCR2B
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ TRNG
+ desc TRNG
+ 0x40004C00
+
+ 0x0
+ 0x14
+
+
+
+ CR
+ desc CR
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0x3
+
+
+ RNGCIR_EN
+ desc RNGCIR_EN
+ 0
+ 0
+ read-write
+
+
+ RNG_RUN
+ desc RNG_RUN
+ 1
+ 1
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ MODE
+ desc MODE
+ 0x4
+ 32
+ read-write
+ 0x10
+ 0x1F
+
+
+ LOAD
+ desc LOAD
+ 0
+ 0
+ read-write
+
+
+ FDBK
+ desc FDBK
+ 1
+ 1
+ read-write
+
+
+ CNT
+ desc CNT
+ 4
+ 2
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ DATA0
+ desc DATA0
+ 0xC
+ 32
+ read-only
+ 0x0
+ 0xFFFFFFFF
+
+
+ DATA0
+ desc DATA0
+ 31
+ 0
+ read-only
+
+
+
+
+ DATA1
+ desc DATA1
+ 0x10
+ 32
+ read-only
+ 0x0
+ 0xFFFFFFFF
+
+
+ DATA1
+ desc DATA1
+ 31
+ 0
+ read-only
+
+
+
+
+
+
+ UART0
+ desc UART
+ 0x40000000
+
+ 0x0
+ 0x1C
+
+
+
+ SBUF
+ desc SBUF
+ 0x0
+ 32
+ read-write
+ 0x0
+ 0x1FF
+
+
+ DATA
+ desc DATA
+ 7
+ 0
+ read-write
+
+
+ DATA8
+ desc DATA8
+ 8
+ 8
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SCON
+ desc SCON
+ 0x4
+ 32
+ read-write
+ 0x0
+ 0x7FE3FF
+
+
+ RCIE
+ desc RCIE
+ 0
+ 0
+ read-write
+
+
+ TCIE
+ desc TCIE
+ 1
+ 1
+ read-write
+
+
+ B8CONT
+ desc B8CONT
+ 3
+ 2
+ read-write
+
+
+ REN
+ desc REN
+ 4
+ 4
+ read-write
+
+
+ ADRDET
+ desc ADRDET
+ 5
+ 5
+ read-write
+
+
+ SM
+ desc SM
+ 7
+ 6
+ read-write
+
+
+ TXEIE
+ desc TXEIE
+ 8
+ 8
+ read-write
+
+
+ OVER
+ desc OVER
+ 9
+ 9
+ read-write
+
+
+ PEIE
+ desc PEIE
+ 13
+ 13
+ read-write
+
+
+ STOPBIT
+ desc STOPBIT
+ 15
+ 14
+ read-write
+
+
+ DMARXEN
+ desc DMARXEN
+ 16
+ 16
+ read-write
+
+
+ DMATXEN
+ desc DMATXEN
+ 17
+ 17
+ read-write
+
+
+ RTSEN
+ desc RTSEN
+ 18
+ 18
+ read-write
+
+
+ CTSEN
+ desc CTSEN
+ 19
+ 19
+ read-write
+
+
+ CTSIE
+ desc CTSIE
+ 20
+ 20
+ read-write
+
+
+ FEIE
+ desc FEIE
+ 21
+ 21
+ read-write
+
+
+ HDSEL
+ desc HDSEL
+ 22
+ 22
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SADDR
+ desc SADDR
+ 0x8
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ SADDR
+ desc SADDR
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SADEN
+ desc SADEN
+ 0xC
+ 32
+ read-write
+ 0x0
+ 0xFF
+
+
+ SADEN
+ desc SADEN
+ 7
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ISR
+ desc ISR
+ 0x10
+ 32
+ read-only
+ 0x8
+ 0x7F
+
+
+ RC
+ desc RC
+ 0
+ 0
+ read-only
+
+
+ TC
+ desc TC
+ 1
+ 1
+ read-only
+
+
+ FE
+ desc FE
+ 2
+ 2
+ read-only
+
+
+ TXE
+ desc TXE
+ 3
+ 3
+ read-only
+
+
+ PE
+ desc PE
+ 4
+ 4
+ read-only
+
+
+ CTSIF
+ desc CTSIF
+ 5
+ 5
+ read-only
+
+
+ CTS
+ desc CTS
+ 6
+ 6
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ ICR
+ desc ICR
+ 0x14
+ 32
+ write-only
+ 0x0
+ 0x37
+
+
+ RCCF
+ desc RCCF
+ 0
+ 0
+ write-only
+
+
+ TCCF
+ desc TCCF
+ 1
+ 1
+ write-only
+
+
+ FECF
+ desc FECF
+ 2
+ 2
+ write-only
+
+
+ PECF
+ desc PECF
+ 4
+ 4
+ write-only
+
+
+ CTSIFCF
+ desc CTSIFCF
+ 5
+ 5
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ SCNT
+ desc SCNT
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0xFFFF
+
+
+ SCNT
+ desc SCNT
+ 15
+ 0
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ UART1
+ desc UART
+ 0x40000100
+
+ 0x0
+ 0x1C
+
+
+
+ UART2
+ desc UART
+ 0x40006000
+
+ 0x0
+ 0x1C
+
+
+
+ UART3
+ desc UART
+ 0x40006400
+
+ 0x0
+ 0x1C
+
+
+
+ VC
+ desc VC
+ 0x40002400
+ ADC
+
+ 0x0
+ 0x158
+
+
+
+ CR
+ desc CR
+ 0x10
+ 32
+ read-write
+ 0x20
+ 0xFFFFF
+
+
+ DIV
+ desc DIV
+ 5
+ 0
+ read-write
+
+
+ DIV_EN
+ desc DIV_EN
+ 6
+ 6
+ read-write
+
+
+ REF2P5_SEL
+ desc REF2P5_SEL
+ 7
+ 7
+ read-write
+
+
+ VC0_BIAS_SEL
+ desc VC0_BIAS_SEL
+ 9
+ 8
+ read-write
+
+
+ VC0_HYS_SEL
+ desc VC0_HYS_SEL
+ 11
+ 10
+ read-write
+
+
+ VC1_BIAS_SEL
+ desc VC1_BIAS_SEL
+ 13
+ 12
+ read-write
+
+
+ VC1_HYS_SEL
+ desc VC1_HYS_SEL
+ 15
+ 14
+ read-write
+
+
+ VC2_BIAS_SEL
+ desc VC2_BIAS_SEL
+ 17
+ 16
+ read-write
+
+
+ VC2_HYS_SEL
+ desc VC2_HYS_SEL
+ 19
+ 18
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ VC0_CR
+ desc VC0_CR
+ 0x14
+ 32
+ read-write
+ 0x0
+ 0x1FFFF
+
+
+ P_SEL
+ desc P_SEL
+ 3
+ 0
+ read-write
+
+
+ N_SEL
+ desc N_SEL
+ 7
+ 4
+ read-write
+
+
+ FLTEN
+ desc FLTEN
+ 8
+ 8
+ read-write
+
+
+ DEBOUNCE_TIME
+ desc DEBOUNCE_TIME
+ 11
+ 9
+ read-write
+
+
+ FALLING
+ desc FALLING
+ 12
+ 12
+ read-write
+
+
+ RISING
+ desc RISING
+ 13
+ 13
+ read-write
+
+
+ LEVEL
+ desc LEVEL
+ 14
+ 14
+ read-write
+
+
+ IE
+ desc IE
+ 15
+ 15
+ read-write
+
+
+ EN
+ desc EN
+ 16
+ 16
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ VC1_CR
+ desc VC1_CR
+ 0x18
+ 32
+ read-write
+ 0x0
+ 0x1FFFF
+
+
+ P_SEL
+ desc P_SEL
+ 3
+ 0
+ read-write
+
+
+ N_SEL
+ desc N_SEL
+ 7
+ 4
+ read-write
+
+
+ FLTEN
+ desc FLTEN
+ 8
+ 8
+ read-write
+
+
+ DEBOUNCE_TIME
+ desc DEBOUNCE_TIME
+ 11
+ 9
+ read-write
+
+
+ FALLING
+ desc FALLING
+ 12
+ 12
+ read-write
+
+
+ RISING
+ desc RISING
+ 13
+ 13
+ read-write
+
+
+ LEVEL
+ desc LEVEL
+ 14
+ 14
+ read-write
+
+
+ IE
+ desc IE
+ 15
+ 15
+ read-write
+
+
+ EN
+ desc EN
+ 16
+ 16
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ VC0_OUT_CFG
+ desc VC0_OUT_CFG
+ 0x1C
+ 32
+ read-write
+ 0x0
+ 0xFE3F
+
+
+ INV_TIMER
+ desc INV_TIMER
+ 0
+ 0
+ read-write
+
+
+ TIM0RCLR
+ desc TIM0RCLR
+ 1
+ 1
+ read-write
+
+
+ TIM1RCLR
+ desc TIM1RCLR
+ 2
+ 2
+ read-write
+
+
+ TIM2RCLR
+ desc TIM2RCLR
+ 3
+ 3
+ read-write
+
+
+ TIM3RCLR
+ desc TIM3RCLR
+ 4
+ 4
+ read-write
+
+
+ TIMBK
+ desc TIMBK
+ 5
+ 5
+ read-write
+
+
+ INV_TIM4
+ desc INV_TIM4
+ 9
+ 9
+ read-write
+
+
+ TIM4
+ desc TIM4
+ 10
+ 10
+ read-write
+
+
+ INV_TIM5
+ desc INV_TIM5
+ 11
+ 11
+ read-write
+
+
+ TIM5
+ desc TIM5
+ 12
+ 12
+ read-write
+
+
+ INV_TIM6
+ desc INV_TIM6
+ 13
+ 13
+ read-write
+
+
+ TIM6
+ desc TIM6
+ 14
+ 14
+ read-write
+
+
+ BRAKE
+ desc BRAKE
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ VC1_OUT_CFG
+ desc VC1_OUT_CFG
+ 0x20
+ 32
+ read-write
+ 0x0
+ 0xFEFF
+
+
+ INV_TIMER
+ desc INV_TIMER
+ 0
+ 0
+ read-write
+
+
+ TIM0RCLR
+ desc TIM0RCLR
+ 1
+ 1
+ read-write
+
+
+ TIM1RCLR
+ desc TIM1RCLR
+ 2
+ 2
+ read-write
+
+
+ TIM2RCLR
+ desc TIM2RCLR
+ 3
+ 3
+ read-write
+
+
+ TIM3RCLR
+ desc TIM3RCLR
+ 4
+ 4
+ read-write
+
+
+ TIMBK
+ desc TIMBK
+ 5
+ 5
+ read-write
+
+
+ INV_TIM4
+ desc INV_TIM4
+ 9
+ 9
+ read-write
+
+
+ TIM4
+ desc TIM4
+ 10
+ 10
+ read-write
+
+
+ INV_TIM5
+ desc INV_TIM5
+ 11
+ 11
+ read-write
+
+
+ TIM5
+ desc TIM5
+ 12
+ 12
+ read-write
+
+
+ INV_TIM6
+ desc INV_TIM6
+ 13
+ 13
+ read-write
+
+
+ TIM6
+ desc TIM6
+ 14
+ 14
+ read-write
+
+
+ BRAKE
+ desc BRAKE
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ IFR
+ desc IFR
+ 0x24
+ 32
+ read-write
+ 0x0
+ 0x3F
+
+
+ VC0_INTF
+ desc VC0_INTF
+ 0
+ 0
+ read-write
+
+
+ VC1_INTF
+ desc VC1_INTF
+ 1
+ 1
+ read-write
+
+
+ VC0_FILTER
+ desc VC0_FILTER
+ 2
+ 2
+ read-only
+
+
+ VC1_FILTER
+ desc VC1_FILTER
+ 3
+ 3
+ read-only
+
+
+ VC2_INTF
+ desc VC2_INTF
+ 4
+ 4
+ read-write
+
+
+ VC2_FILTER
+ desc VC2_FILTER
+ 5
+ 5
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ VC2_CR
+ desc VC2_CR
+ 0x150
+ 32
+ read-write
+ 0x0
+ 0x1FFFF
+
+
+ P_SEL
+ desc P_SEL
+ 3
+ 0
+ read-write
+
+
+ N_SEL
+ desc N_SEL
+ 7
+ 4
+ read-write
+
+
+ FLTEN
+ desc FLTEN
+ 8
+ 8
+ read-write
+
+
+ DEBOUNCE_TIME
+ desc DEBOUNCE_TIME
+ 11
+ 9
+ read-write
+
+
+ FALLING
+ desc FALLING
+ 12
+ 12
+ read-write
+
+
+ RISING
+ desc RISING
+ 13
+ 13
+ read-write
+
+
+ LEVEL
+ desc LEVEL
+ 14
+ 14
+ read-write
+
+
+ IE
+ desc IE
+ 15
+ 15
+ read-write
+
+
+ EN
+ desc EN
+ 16
+ 16
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ VC2_OUT_CFG
+ desc VC2_OUT_CFG
+ 0x154
+ 32
+ read-write
+ 0x0
+ 0xFEFF
+
+
+ INV_TIMER
+ desc INV_TIMER
+ 0
+ 0
+ read-write
+
+
+ TIM0RCLR
+ desc TIM0RCLR
+ 1
+ 1
+ read-write
+
+
+ TIM1RCLR
+ desc TIM1RCLR
+ 2
+ 2
+ read-write
+
+
+ TIM2RCLR
+ desc TIM2RCLR
+ 3
+ 3
+ read-write
+
+
+ TIM3RCLR
+ desc TIM3RCLR
+ 4
+ 4
+ read-write
+
+
+ TIMBK
+ desc TIMBK
+ 5
+ 5
+ read-write
+
+
+ INV_TIM4
+ desc INV_TIM4
+ 9
+ 9
+ read-write
+
+
+ TIM4
+ desc TIM4
+ 10
+ 10
+ read-write
+
+
+ INV_TIM5
+ desc INV_TIM5
+ 11
+ 11
+ read-write
+
+
+ TIM5
+ desc TIM5
+ 12
+ 12
+ read-write
+
+
+ INV_TIM6
+ desc INV_TIM6
+ 13
+ 13
+ read-write
+
+
+ TIM6
+ desc TIM6
+ 14
+ 14
+ read-write
+
+
+ BRAKE
+ desc BRAKE
+ 15
+ 15
+ read-write
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+ WDT
+ desc WDT
+ 0x40000F00
+ LPTIMER0
+
+ 0x0
+ 0x88
+
+
+
+ RST
+ desc RST
+ 0x80
+ 32
+ write-only
+ 0x0
+ 0xFF
+
+
+ RST
+ desc RST
+ 7
+ 0
+ write-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+ CON
+ desc CON
+ 0x84
+ 32
+ read-write
+ 0xF
+ 0xFFBF
+
+
+ WOV
+ desc WOV
+ 3
+ 0
+ read-write
+
+
+ R
+ desc R
+ 4
+ 4
+ read-only
+
+
+ WINT_EN
+ desc WINT_EN
+ 5
+ 5
+ read-write
+
+
+ INT
+ desc INT
+ 7
+ 7
+ read-only
+
+
+ WCNTL
+ desc WCNTL
+ 15
+ 8
+ read-only
+
+
+ RSV
+ desc RSV
+ 31
+ 31
+ read-write
+
+
+
+
+
+
+
diff --git a/mcu/EWARM/config/flashloader/FlashHC32L17X.flash b/mcu/EWARM/config/flashloader/FlashHC32L17X.flash
new file mode 100644
index 0000000..74ef3c3
--- /dev/null
+++ b/mcu/EWARM/config/flashloader/FlashHC32L17X.flash
@@ -0,0 +1,10 @@
+
+
+
+ $PROJ_DIR$\config\flashloader\FlashHC32L17X.out
+ 1
+ 256 0x200
+ 0x00000000
+ $PROJ_DIR$\config\flashloader\FlashHC32L17X.mac
+ 0
+
diff --git a/mcu/EWARM/config/flashloader/FlashHC32L17X.mac b/mcu/EWARM/config/flashloader/FlashHC32L17X.mac
new file mode 100644
index 0000000..b321dac
--- /dev/null
+++ b/mcu/EWARM/config/flashloader/FlashHC32L17X.mac
@@ -0,0 +1,23 @@
+setup()
+{
+ __message "----- setup hardware for Flashloader -----\n";
+ /*Wait*/
+ __delay(5);
+ __emulatorSpeed(0);
+
+ /*Vectors at RAM*/
+ __writeMemory32(0x20000000, 0xE000ED08, "Memory");
+}
+
+execUserPreload()
+{
+ __message "----- execUserPreload -----\n";
+ setup();
+}
+
+execUserFlashInit() // Called by debugger before loading flash loader in RAM.
+{
+ __message "----- execUserFlashInit -----\n";
+ setup();
+}
+
diff --git a/mcu/EWARM/config/flashloader/HC32L17X.board b/mcu/EWARM/config/flashloader/HC32L17X.board
new file mode 100644
index 0000000..792e0b8
--- /dev/null
+++ b/mcu/EWARM/config/flashloader/HC32L17X.board
@@ -0,0 +1,8 @@
+
+
+
+
+ $PROJ_DIR$\config\flashloader\FlashHC32L17X.flash
+ CODE 0x00000000 0x0001FFFF
+
+
diff --git a/mcu/EWARM/config/hc32l17x_ram.icf b/mcu/EWARM/config/hc32l17x_ram.icf
new file mode 100644
index 0000000..82d0b02
--- /dev/null
+++ b/mcu/EWARM/config/hc32l17x_ram.icf
@@ -0,0 +1,29 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x20001FFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20002000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/mcu/EWARM/config/reset.mac b/mcu/EWARM/config/reset.mac
new file mode 100644
index 0000000..8604cd0
--- /dev/null
+++ b/mcu/EWARM/config/reset.mac
@@ -0,0 +1,8 @@
+execUserReset()
+{
+ __message("Executing __hwReset");
+ __hwReset(0);
+ __message("__hwReset done");
+
+ __hwResetWithStrategy(0, 2);
+}
diff --git a/mcu/MDK/HC32L17X.sfr b/mcu/MDK/HC32L17X.sfr
new file mode 100644
index 0000000..ec51925
Binary files /dev/null and b/mcu/MDK/HC32L17X.sfr differ
diff --git a/mcu/MDK/config/FlashHC32L17X_128K.FLM b/mcu/MDK/config/FlashHC32L17X_128K.FLM
new file mode 100644
index 0000000..6ced45f
Binary files /dev/null and b/mcu/MDK/config/FlashHC32L17X_128K.FLM differ
diff --git a/mcu/common/base_types.h b/mcu/common/base_types.h
new file mode 100644
index 0000000..ab32088
--- /dev/null
+++ b/mcu/common/base_types.h
@@ -0,0 +1,147 @@
+/******************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file base_types.h
+ **
+ ** base type common define.
+ ** @link SampleGroup Some description @endlink
+ **
+ ** - 2019-03-01 1.0 Lux First version.
+ **
+ ******************************************************************************/
+
+#ifndef __BASE_TYPES_H__
+#define __BASE_TYPES_H__
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include
+#include
+#include
+#include
+#include
+
+
+/*****************************************************************************/
+/* Global pre-processor symbols/macros ('#define') */
+/*****************************************************************************/
+#ifndef TRUE
+ /** Value is true (boolean_t type) */
+ #define TRUE ((boolean_t) 1u)
+#endif
+
+#ifndef FALSE
+ /** Value is false (boolean_t type) */
+ #define FALSE ((boolean_t) 0u)
+#endif
+
+/** Returns the minimum value out of two values */
+#define MINIMUM( X, Y ) ((X) < (Y) ? (X) : (Y))
+
+/** Returns the maximum value out of two values */
+#define MAXIMUM( X, Y ) ((X) > (Y) ? (X) : (Y))
+
+/** Returns the dimension of an array */
+#define ARRAY_SZ( X ) (sizeof(X) / sizeof((X)[0]))
+
+#ifdef __DEBUG_ASSERT
+ #define ASSERT(x) do{ assert((x)> 0u) ; }while(0);
+#else
+ #define ASSERT(x) {}
+#endif
+/******************************************************************************
+ * Global type definitions
+ ******************************************************************************/
+
+/** logical datatype (only values are TRUE and FALSE) */
+typedef uint8_t boolean_t;
+
+/** single precision floating point number (4 byte) */
+typedef float float32_t;
+
+/** double precision floating point number (8 byte) */
+typedef double float64_t;
+
+/** ASCII character for string generation (8 bit) */
+typedef char char_t;
+
+/** function pointer type to void/void function */
+typedef void (*func_ptr_t)(void);
+
+/** function pointer type to void/uint8_t function */
+typedef void (*func_ptr_arg1_t)(uint8_t u8Param);
+
+/** generic error codes */
+typedef enum en_result
+{
+ Ok = 0u, ///< No error
+ Error = 1u, ///< Non-specific error code
+ ErrorAddressAlignment = 2u, ///< Address alignment does not match
+ ErrorAccessRights = 3u, ///< Wrong mode (e.g. user/system) mode is set
+ ErrorInvalidParameter = 4u, ///< Provided parameter is not valid
+ ErrorOperationInProgress = 5u, ///< A conflicting or requested operation is still in progress
+ ErrorInvalidMode = 6u, ///< Operation not allowed in current mode
+ ErrorUninitialized = 7u, ///< Module (or part of it) was not initialized properly
+ ErrorBufferFull = 8u, ///< Circular buffer can not be written because the buffer is full
+ ErrorTimeout = 9u, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.)
+ ErrorNotReady = 10u, ///< A requested final state is not reached
+ OperationInProgress = 11u ///< Indicator for operation in progress
+} en_result_t;
+
+
+/*****************************************************************************/
+/* Global variable declarations ('extern', definition in C source) */
+/*****************************************************************************/
+
+/*****************************************************************************/
+/* Global function prototypes ('extern', definition in C source) */
+/*****************************************************************************/
+
+#endif /* __BASE_TYPES_H__ */
+
+/******************************************************************************/
+/* EOF (not truncated) */
+/******************************************************************************/
+
+
+
diff --git a/mcu/common/board_stkhc32l17x.h b/mcu/common/board_stkhc32l17x.h
new file mode 100644
index 0000000..1ed42e7
--- /dev/null
+++ b/mcu/common/board_stkhc32l17x.h
@@ -0,0 +1,130 @@
+/******************************************************************************
+* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file stkhc32l17x.h
+ **
+ ** stk board common define.
+ ** @link SampleGroup Some description @endlink
+ **
+ ** - 2018-03-09 1.0 Lux First version.
+ **
+ ******************************************************************************/
+#ifndef __BOARD_STKHC32L17X_H__
+#define __BOARD_STKHC32L17X_H__
+
+///< STK GPIO DEFINE
+///< USER KEY
+#define STK_USER_PORT GpioPortA
+#define STK_USER_PIN GpioPin7
+
+///< LED
+#define STK_LED_PORT GpioPortD
+#define STK_LED_PIN GpioPin14
+
+///< XTH
+#define SYSTEM_XTH (8*1000*1000u) ///< 32MHz
+
+#define STK_XTHI_PORT GpioPortF
+#define STK_XTHI_PIN GpioPin0
+#define STK_XTHO_PORT GpioPortF
+#define STK_XTHO_PIN GpioPin1
+
+///< XTL
+#define SYSTEM_XTL (32768u) ///< 32768Hz
+#define STK_XTLI_PORT GpioPortC
+#define STK_XTLI_PIN GpioPin14
+#define STK_XTLO_PORT GpioPortC
+#define STK_XTLO_PIN GpioPin15
+
+///< LCD
+#define STK_LCD_COM0_PORT GpioPortA
+#define STK_LCD_COM0_PIN GpioPin9
+#define STK_LCD_COM1_PORT GpioPortA
+#define STK_LCD_COM1_PIN GpioPin10
+#define STK_LCD_COM2_PORT GpioPortA
+#define STK_LCD_COM2_PIN GpioPin11
+#define STK_LCD_COM3_PORT GpioPortA
+#define STK_LCD_COM3_PIN GpioPin12
+#define STK_LCD_SEG0_PORT GpioPortA
+#define STK_LCD_SEG0_PIN GpioPin8
+#define STK_LCD_SEG1_PORT GpioPortC
+#define STK_LCD_SEG1_PIN GpioPin9
+#define STK_LCD_SEG2_PORT GpioPortC
+#define STK_LCD_SEG2_PIN GpioPin8
+#define STK_LCD_SEG3_PORT GpioPortC
+#define STK_LCD_SEG3_PIN GpioPin7
+#define STK_LCD_SEG4_PORT GpioPortC
+#define STK_LCD_SEG4_PIN GpioPin6
+#define STK_LCD_SEG5_PORT GpioPortB
+#define STK_LCD_SEG5_PIN GpioPin15
+#define STK_LCD_SEG6_PORT GpioPortB
+#define STK_LCD_SEG6_PIN GpioPin14
+#define STK_LCD_SEG7_PORT GpioPortB
+#define STK_LCD_SEG7_PIN GpioPin13
+
+///< I2C EEPROM
+#define EVB_I2C0_EEPROM_SCL_PORT GpioPortB
+#define EVB_I2C0_EEPROM_SCL_PIN GpioPin6
+#define EVB_I2C0_EEPROM_SDA_PORT GpioPortB
+#define EVB_I2C0_EEPROM_SDA_PIN GpioPin7
+
+///< SPI0
+#define STK_SPI0_CS_PORT GpioPortE
+#define STK_SPI0_CS_PIN GpioPin12
+#define STK_SPI0_SCK_PORT GpioPortE
+#define STK_SPI0_SCK_PIN GpioPin13
+#define STK_SPI0_MISO_PORT GpioPortE
+#define STK_SPI0_MISO_PIN GpioPin14
+#define STK_SPI0_MOSI_PORT GpioPortE
+#define STK_SPI0_MOSI_PIN GpioPin15
+
+///< SPI1
+#define STK_SPI1_CS_PORT GpioPortB
+#define STK_SPI1_CS_PIN GpioPin12
+#define STK_SPI1_SCK_PORT GpioPortB
+#define STK_SPI1_SCK_PIN GpioPin13
+#define STK_SPI1_MISO_PORT GpioPortB
+#define STK_SPI1_MISO_PIN GpioPin14
+#define STK_SPI1_MOSI_PORT GpioPortB
+#define STK_SPI1_MOSI_PIN GpioPin15
+
+#endif
diff --git a/mcu/common/hc32l17x.h b/mcu/common/hc32l17x.h
new file mode 100644
index 0000000..d871b73
--- /dev/null
+++ b/mcu/common/hc32l17x.h
@@ -0,0 +1,10833 @@
+/*******************************************************************************
+* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \\file HC32L17X.h
+**
+** Auto generate.
+** Headerfile for HC32L17X series MCU
+**
+** History:
+**
+** - 2019-07-01 0.1 Lux First version.
+**
+******************************************************************************/
+
+#ifndef __HC32L17X_H__
+#define __HC32L17X_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+* Configuration of the Cortex-M0P Processor and Core Peripherals
+******************************************************************************/
+#define __MPU_PRESENT 0 /* No MPU */
+#define __NVIC_PRIO_BITS 2 /* M0P uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+
+/******************************************************************************
+* Interrupt Number Definition
+******************************************************************************/
+typedef enum IRQn
+{
+ NMI_IRQn = -14, /* 2 Non Maskable */
+ HardFault_IRQn = -13, /* 3 Hard Fault */
+ SVC_IRQn = -5, /* 11 SV Call */
+ PendSV_IRQn = -2, /* 14 Pend SV */
+ SysTick_IRQn = -1, /* 15 System Tick */
+
+ PORTA_IRQn = 0 ,
+ PORTB_IRQn = 1 ,
+ PORTC_E_IRQn = 2 ,
+ PORTD_F_IRQn = 3 ,
+ DMAC_IRQn = 4 ,
+ TIM3_IRQn = 5 ,
+ UART0_2_IRQn = 6 ,
+ UART1_3_IRQn = 7 ,
+ LPUART0_IRQn = 8 ,
+ LPUART1_IRQn = 9 ,
+ SPI0_IRQn = 10,
+ SPI1_IRQn = 11,
+ I2C0_IRQn = 12,
+ I2C1_IRQn = 13,
+ TIM0_IRQn = 14,
+ TIM1_IRQn = 15,
+ TIM2_IRQn = 16,
+ LPTIM_0_1_IRQn = 17,
+ ADTIM4_IRQn = 18,
+ ADTIM5_IRQn = 19,
+ ADTIM6_IRQn = 20,
+ PCA_IRQn = 21,
+ WDT_IRQn = 22,
+ RTC_IRQn = 23,
+ ADC_DAC_IRQn = 24,
+ PCNT_IRQn = 25,
+ VC0_IRQn = 26,
+ VC1_2_IRQn = 27,
+ LVD_IRQn = 28,
+ LCD_IRQn = 29,
+ FLASH_RAM_IRQn = 30,
+ CLKTRIM_IRQn = 31,
+
+
+} IRQn_Type;
+
+
+#include
+#include
+
+#define SUCCESS (0)
+#define ERROR (-1)
+
+#ifndef NULL
+#define NULL (0)
+#endif
+
+
+/******************************************************************************/
+/* Device Specific Peripheral Registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+typedef struct
+{
+ __IO uint32_t EN : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CLKDIV : 2;
+ __IO uint32_t SGLMUX : 5;
+ __IO uint32_t REF : 2;
+ __IO uint32_t BUF : 1;
+ __IO uint32_t SAM : 2;
+ __IO uint32_t INREFEN : 1;
+ __IO uint32_t IE : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adc_cr0_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 2;
+ __IO uint32_t ALIGN : 1;
+ __IO uint32_t THCH : 5;
+ __IO uint32_t DMASQR : 1;
+ __IO uint32_t DMAJQR : 1;
+ __IO uint32_t MODE : 1;
+ __IO uint32_t RACCEN : 1;
+ __IO uint32_t LTCMP : 1;
+ __IO uint32_t HTCMP : 1;
+ __IO uint32_t REGCMP : 1;
+ __IO uint32_t RACCCLR : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adc_cr1_field_t;
+
+typedef struct
+{
+ __IO uint32_t CH0MUX : 5;
+ __IO uint32_t CH1MUX : 5;
+ __IO uint32_t CH2MUX : 5;
+ __IO uint32_t CH3MUX : 5;
+ __IO uint32_t CH4MUX : 5;
+ __IO uint32_t CH5MUX : 5;
+ uint32_t RESERVED30 : 1;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqr0_field_t;
+
+typedef struct
+{
+ __IO uint32_t CH6MUX : 5;
+ __IO uint32_t CH7MUX : 5;
+ __IO uint32_t CH8MUX : 5;
+ __IO uint32_t CH9MUX : 5;
+ __IO uint32_t CH10MUX : 5;
+ __IO uint32_t CH11MUX : 5;
+ uint32_t RESERVED30 : 1;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqr1_field_t;
+
+typedef struct
+{
+ __IO uint32_t CH12MUX : 5;
+ __IO uint32_t CH13MUX : 5;
+ __IO uint32_t CH14MUX : 5;
+ __IO uint32_t CH15MUX : 5;
+ __IO uint32_t CNT : 4;
+ uint32_t RESERVED24 : 7;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqr2_field_t;
+
+typedef struct
+{
+ __IO uint32_t CH0MUX : 5;
+ __IO uint32_t CH1MUX : 5;
+ __IO uint32_t CH2MUX : 5;
+ __IO uint32_t CH3MUX : 5;
+ __IO uint32_t CNT : 2;
+ uint32_t RESERVED22 : 9;
+ __IO uint32_t RSV : 1;
+} stc_adc_jqr_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult0_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult1_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult2_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult3_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult4_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult5_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult6_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult7_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult8_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult9_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult10_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult11_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult12_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqr_result13_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult14_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrresult15_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_jqrresult0_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_jqrresult1_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_jqrresult2_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_jqrresult3_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_result_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULTACC :20;
+ uint32_t RESERVED20 :11;
+ __IO uint32_t RSV : 1;
+} stc_adc_resultacc_field_t;
+
+typedef struct
+{
+ __IO uint32_t HT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_ht_field_t;
+
+typedef struct
+{
+ __IO uint32_t LT :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_adc_lt_field_t;
+
+typedef struct
+{
+ __IO uint32_t SGLIF : 1;
+ __IO uint32_t LTIF : 1;
+ __IO uint32_t HTIF : 1;
+ __IO uint32_t REGIF : 1;
+ __IO uint32_t SQRIF : 1;
+ __IO uint32_t JQRIF : 1;
+ uint32_t RESERVED6 :25;
+ __IO uint32_t RSV : 1;
+} stc_adc_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t SGLIC : 1;
+ __IO uint32_t LTIC : 1;
+ __IO uint32_t HTIC : 1;
+ __IO uint32_t REGIC : 1;
+ __IO uint32_t SQRIC : 1;
+ __IO uint32_t JQRIC : 1;
+ uint32_t RESERVED6 :25;
+ __IO uint32_t RSV : 1;
+} stc_adc_icr_field_t;
+
+typedef struct
+{
+ __IO uint32_t TIM0 : 1;
+ __IO uint32_t TIM1 : 1;
+ __IO uint32_t TIM2 : 1;
+ __IO uint32_t TIM3 : 1;
+ __IO uint32_t TIM4 : 1;
+ __IO uint32_t TIM5 : 1;
+ __IO uint32_t TIM6 : 1;
+ __IO uint32_t UART0 : 1;
+ __IO uint32_t UART1 : 1;
+ __IO uint32_t LPUART0 : 1;
+ __IO uint32_t LPUART1 : 1;
+ __IO uint32_t VC0 : 1;
+ __IO uint32_t VC1 : 1;
+ __IO uint32_t RTC : 1;
+ __IO uint32_t PCA : 1;
+ __IO uint32_t SPI0 : 1;
+ __IO uint32_t SPI1 : 1;
+ __IO uint32_t DMA : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PA15 : 1;
+ __IO uint32_t PB15 : 1;
+ __IO uint32_t PC15 : 1;
+} stc_adc_exttrigger0_field_t;
+
+typedef struct
+{
+ __IO uint32_t TIM0 : 1;
+ __IO uint32_t TIM1 : 1;
+ __IO uint32_t TIM2 : 1;
+ __IO uint32_t TIM3 : 1;
+ __IO uint32_t TIM4 : 1;
+ __IO uint32_t TIM5 : 1;
+ __IO uint32_t TIM6 : 1;
+ __IO uint32_t UART0 : 1;
+ __IO uint32_t UART1 : 1;
+ __IO uint32_t LPUART0 : 1;
+ __IO uint32_t LPUART1 : 1;
+ __IO uint32_t VC0 : 1;
+ __IO uint32_t VC1 : 1;
+ __IO uint32_t RTC : 1;
+ __IO uint32_t PCA : 1;
+ __IO uint32_t SPI0 : 1;
+ __IO uint32_t SPI1 : 1;
+ __IO uint32_t DMA : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PA15 : 1;
+ __IO uint32_t PB15 : 1;
+ __IO uint32_t PC15 : 1;
+} stc_adc_exttrigger1_field_t;
+
+typedef struct
+{
+ __IO uint32_t START : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_adc_sglstart_field_t;
+
+typedef struct
+{
+ __IO uint32_t START : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_adc_sqrstart_field_t;
+
+typedef struct
+{
+ __IO uint32_t START : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_adc_jqrstart_field_t;
+
+typedef struct
+{
+ __IO uint32_t START : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_adc_allstart_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_cnter_field_t;
+
+typedef struct
+{
+ __IO uint32_t PERA :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_perar_field_t;
+
+typedef struct
+{
+ __IO uint32_t PERB :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_perbr_field_t;
+
+typedef struct
+{
+ __IO uint32_t GCMA :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_gcmar_field_t;
+
+typedef struct
+{
+ __IO uint32_t GCMB :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_gcmbr_field_t;
+
+typedef struct
+{
+ __IO uint32_t GCMC :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_gcmcr_field_t;
+
+typedef struct
+{
+ __IO uint32_t GCMD :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_gcmdr_field_t;
+
+typedef struct
+{
+ __IO uint32_t SCMA :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_scmar_field_t;
+
+typedef struct
+{
+ __IO uint32_t SCMB :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_scmbr_field_t;
+
+typedef struct
+{
+ __IO uint32_t DTUA :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_dtuar_field_t;
+
+typedef struct
+{
+ __IO uint32_t DTDA :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_dtdar_field_t;
+
+typedef struct
+{
+ __IO uint32_t START : 1;
+ __IO uint32_t MODE : 3;
+ __IO uint32_t CKDIV : 3;
+ uint32_t RESERVED7 : 1;
+ __IO uint32_t DIR : 1;
+ uint32_t RESERVED9 : 7;
+ __IO uint32_t ZMSKREV : 1;
+ __IO uint32_t ZMSKPOS : 1;
+ __IO uint32_t ZMSK : 2;
+ uint32_t RESERVED20 :11;
+ __IO uint32_t RSV : 1;
+} stc_adtim_gconr_field_t;
+
+typedef struct
+{
+ __IO uint32_t INTENA : 1;
+ __IO uint32_t INTENB : 1;
+ __IO uint32_t INTENC : 1;
+ __IO uint32_t INTEND : 1;
+ uint32_t RESERVED4 : 2;
+ __IO uint32_t INTENOVF : 1;
+ __IO uint32_t INTENUDF : 1;
+ __IO uint32_t INTENDE : 1;
+ uint32_t RESERVED9 : 5;
+ __IO uint32_t INTENSAML : 1;
+ __IO uint32_t INTENSAMH : 1;
+ __IO uint32_t INTENSAU : 1;
+ __IO uint32_t INTENSAD : 1;
+ __IO uint32_t INTENSBU : 1;
+ __IO uint32_t INTENSBD : 1;
+ uint32_t RESERVED20 :11;
+ __IO uint32_t RSV : 1;
+} stc_adtim_iconr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CAPCA : 1;
+ __IO uint32_t STACA : 1;
+ __IO uint32_t STPCA : 1;
+ __IO uint32_t STASTPSA : 1;
+ __IO uint32_t CMPCA : 2;
+ __IO uint32_t PERCA : 2;
+ __IO uint32_t OUTENA : 1;
+ __IO uint32_t DISSELA : 2;
+ __IO uint32_t DISVALA : 2;
+ uint32_t RESERVED13 : 3;
+ __IO uint32_t CAPCB : 1;
+ __IO uint32_t STACB : 1;
+ __IO uint32_t STPCB : 1;
+ __IO uint32_t STASTPSB : 1;
+ __IO uint32_t CMPCB : 2;
+ __IO uint32_t PERCB : 2;
+ __IO uint32_t OUTENB : 1;
+ __IO uint32_t DISSELB : 2;
+ __IO uint32_t DISVALB : 2;
+ uint32_t RESERVED29 : 2;
+ __IO uint32_t RSV : 1;
+} stc_adtim_pconr_field_t;
+
+typedef struct
+{
+ __IO uint32_t BENA : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t BENB : 1;
+ uint32_t RESERVED3 : 5;
+ __IO uint32_t BENP : 1;
+ uint32_t RESERVED9 :22;
+ __IO uint32_t RSV : 1;
+} stc_adtim_bconr_field_t;
+
+typedef struct
+{
+ __IO uint32_t DTCEN : 1;
+ uint32_t RESERVED1 : 7;
+ __IO uint32_t SEPA : 1;
+ uint32_t RESERVED9 :22;
+ __IO uint32_t RSV : 1;
+} stc_adtim_dconr_field_t;
+
+typedef struct
+{
+ __IO uint32_t NOFIENGA : 1;
+ __IO uint32_t NOFICKGA : 2;
+ uint32_t RESERVED3 : 1;
+ __IO uint32_t NOFIENGB : 1;
+ __IO uint32_t NOFICKGB : 2;
+ uint32_t RESERVED7 : 9;
+ __IO uint32_t NOFIENTA : 1;
+ __IO uint32_t NOFICKTA : 2;
+ uint32_t RESERVED19 : 1;
+ __IO uint32_t NOFIENTB : 1;
+ __IO uint32_t NOFICKTB : 2;
+ uint32_t RESERVED23 : 1;
+ __IO uint32_t NOFIENTC : 1;
+ __IO uint32_t NOFICKTC : 2;
+ uint32_t RESERVED27 : 1;
+ __IO uint32_t NOFIENTD : 1;
+ __IO uint32_t NOFICKTD : 2;
+ __IO uint32_t RSV : 1;
+} stc_adtim_fconr_field_t;
+
+typedef struct
+{
+ __IO uint32_t GEPERIA : 1;
+ __IO uint32_t GEPERIB : 1;
+ __IO uint32_t GEPERIC : 1;
+ __IO uint32_t GEPERID : 1;
+ uint32_t RESERVED4 :12;
+ __IO uint32_t PCNTE : 2;
+ __IO uint32_t PCNTS : 3;
+ uint32_t RESERVED21 :10;
+ __IO uint32_t RSV : 1;
+} stc_adtim_vperr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CMAF : 1;
+ __IO uint32_t CMBF : 1;
+ __IO uint32_t CMCF : 1;
+ __IO uint32_t CMDF : 1;
+ uint32_t RESERVED4 : 2;
+ __IO uint32_t OVFF : 1;
+ __IO uint32_t UDFF : 1;
+ __IO uint32_t DTEF : 1;
+ __IO uint32_t CMSAUF : 1;
+ __IO uint32_t CMSADF : 1;
+ __IO uint32_t CMSBUF : 1;
+ __IO uint32_t CMSBDF : 1;
+ uint32_t RESERVED13 : 8;
+ __IO uint32_t VPERNUM : 3;
+ uint32_t RESERVED24 : 7;
+ __IO uint32_t DIRF : 1;
+} stc_adtim_stflr_field_t;
+
+typedef struct
+{
+ __IO uint32_t HSTA0 : 1;
+ __IO uint32_t HSTA1 : 1;
+ __IO uint32_t HSTA2 : 1;
+ __IO uint32_t HSTA3 : 1;
+ __IO uint32_t HSTA4 : 1;
+ __IO uint32_t HSTA5 : 1;
+ __IO uint32_t HSTA6 : 1;
+ __IO uint32_t HSTA7 : 1;
+ __IO uint32_t HSTA8 : 1;
+ __IO uint32_t HSTA9 : 1;
+ __IO uint32_t HSTA10 : 1;
+ __IO uint32_t HSTA11 : 1;
+ __IO uint32_t HSTA12 : 1;
+ __IO uint32_t HSTA13 : 1;
+ __IO uint32_t HSTA14 : 1;
+ __IO uint32_t HSTA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t STARTS : 1;
+} stc_adtim_hstar_field_t;
+
+typedef struct
+{
+ __IO uint32_t HSTP0 : 1;
+ __IO uint32_t HSTP1 : 1;
+ __IO uint32_t HSTP2 : 1;
+ __IO uint32_t HSTP3 : 1;
+ __IO uint32_t HSTP4 : 1;
+ __IO uint32_t HSTP5 : 1;
+ __IO uint32_t HSTP6 : 1;
+ __IO uint32_t HSTP7 : 1;
+ __IO uint32_t HSTP8 : 1;
+ __IO uint32_t HSTP9 : 1;
+ __IO uint32_t HSTP10 : 1;
+ __IO uint32_t HSTP11 : 1;
+ __IO uint32_t HSTP12 : 1;
+ __IO uint32_t HSTP13 : 1;
+ __IO uint32_t HSTP14 : 1;
+ __IO uint32_t HSTP15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t STOPS : 1;
+} stc_adtim_hstpr_field_t;
+
+typedef struct
+{
+ __IO uint32_t HCEL0 : 1;
+ __IO uint32_t HCEL1 : 1;
+ __IO uint32_t HCEL2 : 1;
+ __IO uint32_t HCEL3 : 1;
+ __IO uint32_t HCEL4 : 1;
+ __IO uint32_t HCEL5 : 1;
+ __IO uint32_t HCEL6 : 1;
+ __IO uint32_t HCEL7 : 1;
+ __IO uint32_t HCEL8 : 1;
+ __IO uint32_t HCEL9 : 1;
+ __IO uint32_t HCEL10 : 1;
+ __IO uint32_t HCEL11 : 1;
+ __IO uint32_t HCEL12 : 1;
+ __IO uint32_t HCEL13 : 1;
+ __IO uint32_t HCEL14 : 1;
+ __IO uint32_t HCEL15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t CLEARS : 1;
+} stc_adtim_hcelr_field_t;
+
+typedef struct
+{
+ __IO uint32_t HCPA0 : 1;
+ __IO uint32_t HCPA1 : 1;
+ __IO uint32_t HCPA2 : 1;
+ __IO uint32_t HCPA3 : 1;
+ __IO uint32_t HCPA4 : 1;
+ __IO uint32_t HCPA5 : 1;
+ __IO uint32_t HCPA6 : 1;
+ __IO uint32_t HCPA7 : 1;
+ __IO uint32_t HCPA8 : 1;
+ __IO uint32_t HCPA9 : 1;
+ __IO uint32_t HCPA10 : 1;
+ __IO uint32_t HCPA11 : 1;
+ __IO uint32_t HCPA12 : 1;
+ __IO uint32_t HCPA13 : 1;
+ __IO uint32_t HCPA14 : 1;
+ __IO uint32_t HCPA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_hcpar_field_t;
+
+typedef struct
+{
+ __IO uint32_t HCPB0 : 1;
+ __IO uint32_t HCPB1 : 1;
+ __IO uint32_t HCPB2 : 1;
+ __IO uint32_t HCPB3 : 1;
+ __IO uint32_t HCPB4 : 1;
+ __IO uint32_t HCPB5 : 1;
+ __IO uint32_t HCPB6 : 1;
+ __IO uint32_t HCPB7 : 1;
+ __IO uint32_t HCPB8 : 1;
+ __IO uint32_t HCPB9 : 1;
+ __IO uint32_t HCPB10 : 1;
+ __IO uint32_t HCPB11 : 1;
+ __IO uint32_t HCPB12 : 1;
+ __IO uint32_t HCPB13 : 1;
+ __IO uint32_t HCPB14 : 1;
+ __IO uint32_t HCPB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_hcpbr_field_t;
+
+typedef struct
+{
+ __IO uint32_t HCUP0 : 1;
+ __IO uint32_t HCUP1 : 1;
+ __IO uint32_t HCUP2 : 1;
+ __IO uint32_t HCUP3 : 1;
+ __IO uint32_t HCUP4 : 1;
+ __IO uint32_t HCUP5 : 1;
+ __IO uint32_t HCUP6 : 1;
+ __IO uint32_t HCUP7 : 1;
+ __IO uint32_t HCUP8 : 1;
+ __IO uint32_t HCUP9 : 1;
+ __IO uint32_t HCUP10 : 1;
+ __IO uint32_t HCUP11 : 1;
+ __IO uint32_t HCUP12 : 1;
+ __IO uint32_t HCUP13 : 1;
+ __IO uint32_t HCUP14 : 1;
+ __IO uint32_t HCUP15 : 1;
+ __IO uint32_t HCUP16 : 1;
+ __IO uint32_t HCUP17 : 1;
+ __IO uint32_t HCUP18 : 1;
+ __IO uint32_t HCUP19 : 1;
+ uint32_t RESERVED20 :11;
+ __IO uint32_t RSV : 1;
+} stc_adtim_hcupr_field_t;
+
+typedef struct
+{
+ __IO uint32_t HCDO0 : 1;
+ __IO uint32_t HCDO1 : 1;
+ __IO uint32_t HCDO2 : 1;
+ __IO uint32_t HCDO3 : 1;
+ __IO uint32_t HCDO4 : 1;
+ __IO uint32_t HCDO5 : 1;
+ __IO uint32_t HCDO6 : 1;
+ __IO uint32_t HCDO7 : 1;
+ __IO uint32_t HCDO8 : 1;
+ __IO uint32_t HCDO9 : 1;
+ __IO uint32_t HCDO10 : 1;
+ __IO uint32_t HCDO11 : 1;
+ __IO uint32_t HCDO12 : 1;
+ __IO uint32_t HCDO13 : 1;
+ __IO uint32_t HCDO14 : 1;
+ __IO uint32_t HCDO15 : 1;
+ __IO uint32_t HCDO16 : 1;
+ __IO uint32_t HCDO17 : 1;
+ __IO uint32_t HCDO18 : 1;
+ __IO uint32_t HCDO19 : 1;
+ uint32_t RESERVED20 :11;
+ __IO uint32_t RSV : 1;
+} stc_adtim_hcdor_field_t;
+
+typedef struct
+{
+ __IO uint32_t CMAF : 1;
+ __IO uint32_t CMBF : 1;
+ __IO uint32_t CMCF : 1;
+ __IO uint32_t CMDF : 1;
+ uint32_t RESERVED4 : 2;
+ __IO uint32_t OVFF : 1;
+ __IO uint32_t UDFF : 1;
+ __IO uint32_t DTEF : 1;
+ uint32_t RESERVED9 : 5;
+ __IO uint32_t SAMLF : 1;
+ __IO uint32_t SAMHF : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CMAC : 1;
+ __IO uint32_t CMBC : 1;
+ __IO uint32_t CMCC : 1;
+ __IO uint32_t CMDC : 1;
+ uint32_t RESERVED4 : 2;
+ __IO uint32_t OVFC : 1;
+ __IO uint32_t UDFC : 1;
+ __IO uint32_t DTEC : 1;
+ uint32_t RESERVED9 : 5;
+ __IO uint32_t SAMLC : 1;
+ __IO uint32_t SAMHC : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CMAE : 1;
+ __IO uint32_t CMBE : 1;
+ __IO uint32_t CMCE : 1;
+ __IO uint32_t CMDE : 1;
+ uint32_t RESERVED4 : 2;
+ __IO uint32_t OVFE : 1;
+ __IO uint32_t UDFE : 1;
+ __IO uint32_t DITENA : 1;
+ __IO uint32_t DITENB : 1;
+ __IO uint32_t DITENS : 1;
+ __IO uint32_t CMSAE : 1;
+ __IO uint32_t CMSBE : 1;
+ __IO uint32_t DMA_G_CMA : 1;
+ __IO uint32_t DMA_G_CMB : 1;
+ __IO uint32_t DMA_G_CMC : 1;
+ __IO uint32_t DMA_G_CMD : 1;
+ uint32_t RESERVED17 : 2;
+ __IO uint32_t DMA_G_OVF : 1;
+ __IO uint32_t DMA_G_UDF : 1;
+ __IO uint32_t DMA_S_CMA : 1;
+ __IO uint32_t DMA_S_CMB : 1;
+ uint32_t RESERVED23 : 8;
+ __IO uint32_t RSV : 1;
+} stc_adtim_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t FBRAKE : 1;
+ __IO uint32_t FSAME : 1;
+ __IO uint32_t BFILTS : 2;
+ __IO uint32_t BFILTEN : 1;
+ uint32_t RESERVED5 : 2;
+ __IO uint32_t SOFTBK : 1;
+ __IO uint32_t SML0 : 1;
+ __IO uint32_t SML1 : 1;
+ __IO uint32_t SML2 : 1;
+ __IO uint32_t SMH0 : 1;
+ __IO uint32_t SMH1 : 1;
+ __IO uint32_t SMH2 : 1;
+ uint32_t RESERVED14 :17;
+ __IO uint32_t RSV : 1;
+} stc_adtim_aossr_field_t;
+
+typedef struct
+{
+ __IO uint32_t FBRAKE : 1;
+ __IO uint32_t FSAME : 1;
+ uint32_t RESERVED2 :29;
+ __IO uint32_t RSV : 1;
+} stc_adtim_aoscl_field_t;
+
+typedef struct
+{
+ __IO uint32_t EN0 : 1;
+ __IO uint32_t EN1 : 1;
+ __IO uint32_t EN2 : 1;
+ __IO uint32_t EN3 : 1;
+ __IO uint32_t EN4 : 1;
+ __IO uint32_t EN5 : 1;
+ __IO uint32_t EN6 : 1;
+ __IO uint32_t EN7 : 1;
+ __IO uint32_t EN8 : 1;
+ __IO uint32_t EN9 : 1;
+ __IO uint32_t EN10 : 1;
+ __IO uint32_t EN11 : 1;
+ __IO uint32_t EN12 : 1;
+ __IO uint32_t EN13 : 1;
+ __IO uint32_t EN14 : 1;
+ __IO uint32_t EN15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_ptbks_field_t;
+
+typedef struct
+{
+ __IO uint32_t TRIGAS : 4;
+ __IO uint32_t TRIGBS : 4;
+ __IO uint32_t TRIGCS : 4;
+ __IO uint32_t TRIGDS : 4;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_ttrig_field_t;
+
+typedef struct
+{
+ __IO uint32_t IAOS0S : 4;
+ __IO uint32_t IAOS1S : 4;
+ __IO uint32_t IAOS2S : 4;
+ __IO uint32_t IAOS3S : 4;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_itrig_field_t;
+
+typedef struct
+{
+ __IO uint32_t POL0 : 1;
+ __IO uint32_t POL1 : 1;
+ __IO uint32_t POL2 : 1;
+ __IO uint32_t POL3 : 1;
+ __IO uint32_t POL4 : 1;
+ __IO uint32_t POL5 : 1;
+ __IO uint32_t POL6 : 1;
+ __IO uint32_t POL7 : 1;
+ __IO uint32_t POL8 : 1;
+ __IO uint32_t POL9 : 1;
+ __IO uint32_t POL10 : 1;
+ __IO uint32_t POL11 : 1;
+ __IO uint32_t POL12 : 1;
+ __IO uint32_t POL13 : 1;
+ __IO uint32_t POL14 : 1;
+ __IO uint32_t POL15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_adtim_ptbkp_field_t;
+
+typedef struct
+{
+ __IO uint32_t SSTA0 : 1;
+ __IO uint32_t SSTA1 : 1;
+ __IO uint32_t SSTA2 : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_adtim_sstar_field_t;
+
+typedef struct
+{
+ __IO uint32_t SSTP0 : 1;
+ __IO uint32_t SSTP1 : 1;
+ __IO uint32_t SSTP2 : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_adtim_sstpr_field_t;
+
+typedef struct
+{
+ __IO uint32_t SCLR0 : 1;
+ __IO uint32_t SCLR1 : 1;
+ __IO uint32_t SCLR2 : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_adtim_sclrr_field_t;
+
+typedef struct
+{
+ __IO uint32_t START : 1;
+ __IO uint32_t MODE : 1;
+ uint32_t RESERVED2 : 1;
+ __IO uint32_t KEYSIZE : 2;
+ uint32_t RESERVED5 :26;
+ __IO uint32_t RSV : 1;
+} stc_aes_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t DATA0 :32;
+} stc_aes_data0_field_t;
+
+typedef struct
+{
+ __IO uint32_t DATA0 :32;
+} stc_aes_data1_field_t;
+
+typedef struct
+{
+ __IO uint32_t DATA0 :32;
+} stc_aes_data2_field_t;
+
+typedef struct
+{
+ __IO uint32_t DATA0 :32;
+} stc_aes_data3_field_t;
+
+typedef struct
+{
+ __IO uint32_t KEY0 :32;
+} stc_aes_key0_field_t;
+
+typedef struct
+{
+ __IO uint32_t KEY0 :32;
+} stc_aes_key1_field_t;
+
+typedef struct
+{
+ __IO uint32_t KEY0 :32;
+} stc_aes_key2_field_t;
+
+typedef struct
+{
+ __IO uint32_t KEY0 :32;
+} stc_aes_key3_field_t;
+
+typedef struct
+{
+ __IO uint32_t KEY0 :32;
+} stc_aes_key4_field_t;
+
+typedef struct
+{
+ __IO uint32_t KEY0 :32;
+} stc_aes_key5_field_t;
+
+typedef struct
+{
+ __IO uint32_t KEY0 :32;
+} stc_aes_key6_field_t;
+
+typedef struct
+{
+ __IO uint32_t KEY0 :32;
+} stc_aes_key7_field_t;
+
+typedef struct
+{
+ __IO uint32_t BGR_EN : 1;
+ __IO uint32_t TS_EN : 1;
+ uint32_t RESERVED2 :29;
+ __IO uint32_t RSV : 1;
+} stc_bgr_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t TRIM_START : 1;
+ __IO uint32_t REFCLK_SEL : 3;
+ __IO uint32_t CALCLK_SEL : 2;
+ __IO uint32_t MON_EN : 1;
+ __IO uint32_t IE : 1;
+ __IO uint32_t CALCLK_SEL2 : 1;
+ uint32_t RESERVED9 :22;
+ __IO uint32_t RSV : 1;
+} stc_clk_trim_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t RCNTVAL :32;
+} stc_clk_trim_refcon_field_t;
+
+typedef struct
+{
+ __IO uint32_t REFCNT :32;
+} stc_clk_trim_refcnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CALCNT :32;
+} stc_clk_trim_calcnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t STOP : 1;
+ __IO uint32_t CALCNT_OF : 1;
+ __IO uint32_t XTL_FAULT : 1;
+ __IO uint32_t XTH_FAULT : 1;
+ __IO uint32_t PLL_FAULT : 1;
+ uint32_t RESERVED5 :26;
+ __IO uint32_t RSV : 1;
+} stc_clk_trim_ifr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 2;
+ __IO uint32_t XTL_FAULT_CLR : 1;
+ __IO uint32_t XTH_FAULT_CLR : 1;
+ __IO uint32_t PLL_FAULT_CLR : 1;
+ uint32_t RESERVED5 :26;
+ __IO uint32_t RSV : 1;
+} stc_clk_trim_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCNTVAL :32;
+} stc_clk_trim_calcon_field_t;
+
+typedef struct
+{
+ __IO uint32_t CR : 1;
+ __IO uint32_t FLAG : 1;
+ uint32_t RESERVED2 :29;
+ __IO uint32_t RSV : 1;
+} stc_crc_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t RESULT :32;
+} stc_crc_result_field_t;
+
+typedef struct
+{
+ __IO uint32_t DATA :32;
+} stc_crc_data_field_t;
+
+typedef struct
+{
+ __IO uint32_t EN0 : 1;
+ __IO uint32_t BOFF0 : 1;
+ __IO uint32_t TEN0 : 1;
+ __IO uint32_t TSEL0 : 3;
+ __IO uint32_t WAVE0 : 2;
+ __IO uint32_t MAMP0 : 4;
+ __IO uint32_t DMAEN0 : 1;
+ __IO uint32_t DMAUDRIE0 : 1;
+ __IO uint32_t SREF0 : 2;
+} stc_dac_cr0_field_t;
+
+typedef struct
+{
+ __IO uint32_t SWTRIG0 : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_dac_swtrigr_field_t;
+
+typedef struct
+{
+ __IO uint32_t DHR0 :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_dac_dhr12r0_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 4;
+ __IO uint32_t DHR0 :12;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_dac_dhr12l0_field_t;
+
+typedef struct
+{
+ __IO uint32_t DHR0 : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_dac_dhr8r0_field_t;
+
+typedef struct
+{
+ __IO uint32_t DOR0 :12;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_dac_dor0_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 :13;
+ __IO uint32_t DMAUDR0 : 1;
+ uint32_t RESERVED14 :17;
+ __IO uint32_t RSV : 1;
+} stc_dac_sr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 4;
+ __IO uint32_t PTRIGSEL : 3;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_dac_etrs_field_t;
+
+typedef struct
+{
+ __IO uint32_t TIM0 : 1;
+ __IO uint32_t TIM1 : 1;
+ __IO uint32_t TIM2 : 1;
+ __IO uint32_t LPTIM0 : 1;
+ __IO uint32_t TIM4 : 1;
+ __IO uint32_t TIM5 : 1;
+ __IO uint32_t TIM6 : 1;
+ __IO uint32_t PCA : 1;
+ __IO uint32_t WDT : 1;
+ __IO uint32_t RTC : 1;
+ uint32_t RESERVED10 : 1;
+ __IO uint32_t TIM3 : 1;
+ __IO uint32_t LPTIM1 : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_debug_active_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 :24;
+ __IO uint32_t HALT : 4;
+ __IO uint32_t PRIO : 1;
+ uint32_t RESERVED29 : 1;
+ __IO uint32_t ST : 1;
+ __IO uint32_t EN : 1;
+} stc_dmac_conf_field_t;
+
+typedef struct
+{
+ __IO uint32_t TC :16;
+ __IO uint32_t BC : 4;
+ uint32_t RESERVED20 : 2;
+ __IO uint32_t TRI_SEL : 7;
+ __IO uint32_t ST : 1;
+ __IO uint32_t PAS : 1;
+ __IO uint32_t ENS : 1;
+} stc_dmac_confa0_field_t;
+
+typedef struct
+{
+ __IO uint32_t MSK : 1;
+ uint32_t RESERVED1 :15;
+ __IO uint32_t STAT : 3;
+ __IO uint32_t FIS_IE : 1;
+ __IO uint32_t ERR_IE : 1;
+ __IO uint32_t RD : 1;
+ __IO uint32_t RS : 1;
+ __IO uint32_t RC : 1;
+ __IO uint32_t FD : 1;
+ __IO uint32_t FS : 1;
+ __IO uint32_t WIDTH : 2;
+ __IO uint32_t MODE : 2;
+} stc_dmac_confb0_field_t;
+
+typedef struct
+{
+ __IO uint32_t SRCADR :32;
+} stc_dmac_srcadr0_field_t;
+
+typedef struct
+{
+ __IO uint32_t DSTADR :32;
+} stc_dmac_dstadr0_field_t;
+
+typedef struct
+{
+ __IO uint32_t TC :16;
+ __IO uint32_t BC : 4;
+ uint32_t RESERVED20 : 2;
+ __IO uint32_t TRI_SEL : 7;
+ __IO uint32_t ST : 1;
+ __IO uint32_t PAS : 1;
+ __IO uint32_t ENS : 1;
+} stc_dmac_confa1_field_t;
+
+typedef struct
+{
+ __IO uint32_t MSK : 1;
+ uint32_t RESERVED1 :15;
+ __IO uint32_t STAT : 3;
+ __IO uint32_t FIS_IE : 1;
+ __IO uint32_t ERR_IE : 1;
+ __IO uint32_t RD : 1;
+ __IO uint32_t RS : 1;
+ __IO uint32_t RC : 1;
+ __IO uint32_t FD : 1;
+ __IO uint32_t FS : 1;
+ __IO uint32_t WIDTH : 2;
+ __IO uint32_t MODE : 2;
+} stc_dmac_confb1_field_t;
+
+typedef struct
+{
+ __IO uint32_t SRCADR :32;
+} stc_dmac_srcadr1_field_t;
+
+typedef struct
+{
+ __IO uint32_t DSTADR :32;
+} stc_dmac_dstadr1_field_t;
+
+typedef struct
+{
+ __IO uint32_t TNVS : 9;
+ __IO uint32_t RSV :23;
+} stc_flash_tnvs_field_t;
+
+typedef struct
+{
+ __IO uint32_t TPGS : 8;
+ __IO uint32_t RSV :24;
+} stc_flash_tpgs_field_t;
+
+typedef struct
+{
+ __IO uint32_t TPROG : 9;
+ __IO uint32_t RSV :23;
+} stc_flash_tprog_field_t;
+
+typedef struct
+{
+ __IO uint32_t TSERASE :18;
+ __IO uint32_t RSV :14;
+} stc_flash_tserase_field_t;
+
+typedef struct
+{
+ __IO uint32_t TMERASE :21;
+ __IO uint32_t RSV :11;
+} stc_flash_tmerase_field_t;
+
+typedef struct
+{
+ __IO uint32_t TPRCV :12;
+ __IO uint32_t RSV :20;
+} stc_flash_tprcv_field_t;
+
+typedef struct
+{
+ __IO uint32_t TSRCV :12;
+ __IO uint32_t RSV :20;
+} stc_flash_tsrcv_field_t;
+
+typedef struct
+{
+ __IO uint32_t TMRCV :14;
+ __IO uint32_t RSV :18;
+} stc_flash_tmrcv_field_t;
+
+typedef struct
+{
+ __IO uint32_t OP : 2;
+ __IO uint32_t WAIT : 2;
+ __IO uint32_t BUSY : 1;
+ __IO uint32_t IE : 2;
+ uint32_t RESERVED7 : 2;
+ __IO uint32_t DPSTB_EN : 1;
+ __IO uint32_t RSV :22;
+} stc_flash_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t IF0 : 1;
+ __IO uint32_t IF1 : 1;
+ __IO uint32_t RSV :30;
+} stc_flash_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t ICLR0 : 1;
+ __IO uint32_t ICLR1 : 1;
+ __IO uint32_t RSV :30;
+} stc_flash_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t BYSEQ :16;
+ __IO uint32_t RSV :16;
+} stc_flash_bypass_field_t;
+
+typedef struct
+{
+ __IO uint32_t SLOCK :32;
+} stc_flash_slock0_field_t;
+
+typedef struct
+{
+ __IO uint32_t SLOCK :32;
+} stc_flash_slock1_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa00_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa01_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa02_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa03_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa04_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa05_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa06_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa07_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa08_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa09_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa10_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa11_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa12_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa13_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa14_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa15_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb00_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb01_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb02_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb03_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb04_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb05_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb06_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb07_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb08_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb09_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb10_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb11_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb12_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb13_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb14_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb15_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc00_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc01_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc02_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc03_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc04_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc05_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc06_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc07_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc08_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc09_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc10_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc11_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc12_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc13_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc14_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc15_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd00_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd01_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd02_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd03_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd04_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd05_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd06_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd07_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd08_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd09_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd10_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd11_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd12_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd13_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd14_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd15_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_padir_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pain_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_paout_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_paads_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pabset_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pabclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PABCLR :16;
+ __IO uint32_t PABSET :16;
+} stc_gpio_pabsetclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_padr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_papu_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_papd_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_paod_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pahie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_palie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_parie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pafie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbdir_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbin_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbout_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbads_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbbset_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbbclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PBBCLR :16;
+ __IO uint32_t PBBSET :16;
+} stc_gpio_pbbsetclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbdr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbpu_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbpd_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbod_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbhie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pblie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbrie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pbfie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcdir_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcin_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcout_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcads_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcbset_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcbclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PCBCLR :16;
+ __IO uint32_t PCBSET :16;
+} stc_gpio_pcbsetclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcdr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcpu_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcpd_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcod_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pchie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pclie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcrie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcfie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pddir_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdin_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdout_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdads_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdbset_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdbclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PDBCLR :16;
+ __IO uint32_t PDBSET :16;
+} stc_gpio_pdbsetclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pddr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdpu_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdpd_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdod_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdhie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdlie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdrie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pdfie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa_stat_field_t;
+
+typedef struct
+{
+ __IO uint32_t PA00 : 1;
+ __IO uint32_t PA01 : 1;
+ __IO uint32_t PA02 : 1;
+ __IO uint32_t PA03 : 1;
+ __IO uint32_t PA04 : 1;
+ __IO uint32_t PA05 : 1;
+ __IO uint32_t PA06 : 1;
+ __IO uint32_t PA07 : 1;
+ __IO uint32_t PA08 : 1;
+ __IO uint32_t PA09 : 1;
+ __IO uint32_t PA10 : 1;
+ __IO uint32_t PA11 : 1;
+ __IO uint32_t PA12 : 1;
+ __IO uint32_t PA13 : 1;
+ __IO uint32_t PA14 : 1;
+ __IO uint32_t PA15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pa_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb_stat_field_t;
+
+typedef struct
+{
+ __IO uint32_t PB00 : 1;
+ __IO uint32_t PB01 : 1;
+ __IO uint32_t PB02 : 1;
+ __IO uint32_t PB03 : 1;
+ __IO uint32_t PB04 : 1;
+ __IO uint32_t PB05 : 1;
+ __IO uint32_t PB06 : 1;
+ __IO uint32_t PB07 : 1;
+ __IO uint32_t PB08 : 1;
+ __IO uint32_t PB09 : 1;
+ __IO uint32_t PB10 : 1;
+ __IO uint32_t PB11 : 1;
+ __IO uint32_t PB12 : 1;
+ __IO uint32_t PB13 : 1;
+ __IO uint32_t PB14 : 1;
+ __IO uint32_t PB15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pb_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc_stat_field_t;
+
+typedef struct
+{
+ __IO uint32_t PC00 : 1;
+ __IO uint32_t PC01 : 1;
+ __IO uint32_t PC02 : 1;
+ __IO uint32_t PC03 : 1;
+ __IO uint32_t PC04 : 1;
+ __IO uint32_t PC05 : 1;
+ __IO uint32_t PC06 : 1;
+ __IO uint32_t PC07 : 1;
+ __IO uint32_t PC08 : 1;
+ __IO uint32_t PC09 : 1;
+ __IO uint32_t PC10 : 1;
+ __IO uint32_t PC11 : 1;
+ __IO uint32_t PC12 : 1;
+ __IO uint32_t PC13 : 1;
+ __IO uint32_t PC14 : 1;
+ __IO uint32_t PC15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pc_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd_stat_field_t;
+
+typedef struct
+{
+ __IO uint32_t PD00 : 1;
+ __IO uint32_t PD01 : 1;
+ __IO uint32_t PD02 : 1;
+ __IO uint32_t PD03 : 1;
+ __IO uint32_t PD04 : 1;
+ __IO uint32_t PD05 : 1;
+ __IO uint32_t PD06 : 1;
+ __IO uint32_t PD07 : 1;
+ __IO uint32_t PD08 : 1;
+ __IO uint32_t PD09 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+ __IO uint32_t PD12 : 1;
+ __IO uint32_t PD13 : 1;
+ __IO uint32_t PD14 : 1;
+ __IO uint32_t PD15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pd_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t IESEL : 1;
+} stc_gpio_ctrl0_field_t;
+
+typedef struct
+{
+ __IO uint32_t EXT_CLK_SEL : 4;
+ __IO uint32_t SSN0_SEL : 4;
+ __IO uint32_t PCLK_SEL : 2;
+ __IO uint32_t HCLK_SEL : 2;
+ __IO uint32_t PCLK_EN : 1;
+ __IO uint32_t HCLK_EN : 1;
+ __IO uint32_t IR_POL : 1;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_gpio_ctrl1_field_t;
+
+typedef struct
+{
+ __IO uint32_t SSN1_SEL : 4;
+ __IO uint32_t TCLK_SEL : 2;
+ __IO uint32_t TCLK_DIV : 2;
+ uint32_t RESERVED8 : 7;
+ __IO uint32_t AHB_SEL : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_ctrl2_field_t;
+
+typedef struct
+{
+ __IO uint32_t TIM0_G : 3;
+ __IO uint32_t TIM1_G : 3;
+ __IO uint32_t TIM2_G : 3;
+ __IO uint32_t TIM3_G : 3;
+ __IO uint32_t LPTIM0_G : 3;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_gpio_timgs_field_t;
+
+typedef struct
+{
+ __IO uint32_t TIM0_E : 3;
+ __IO uint32_t TIM1_E : 3;
+ __IO uint32_t TIM2_E : 3;
+ __IO uint32_t TIM3_E : 3;
+ __IO uint32_t LPTIM0_E : 3;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_gpio_times_field_t;
+
+typedef struct
+{
+ __IO uint32_t TIM0_CA : 3;
+ __IO uint32_t TIM1_CA : 3;
+ __IO uint32_t TIM2_CA : 3;
+ __IO uint32_t TIM3_CA : 3;
+ __IO uint32_t TIM3_CB : 3;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_gpio_timcps_field_t;
+
+typedef struct
+{
+ __IO uint32_t PCA_CH0 : 3;
+ __IO uint32_t PCA_ECI : 3;
+ __IO uint32_t LPTIM1_G : 3;
+ __IO uint32_t LPTIM1_E : 3;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcas_field_t;
+
+typedef struct
+{
+ __IO uint32_t PCNT_S0 : 2;
+ __IO uint32_t PCNT_S1 : 2;
+ uint32_t RESERVED4 :27;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pcnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe00_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe01_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe02_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe03_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe04_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe05_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe06_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe07_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe08_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe09_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe10_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe11_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe12_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe13_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe14_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe15_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf00_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf01_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf02_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf03_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf04_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf05_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf06_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf07_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf08_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf09_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf10_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t SEL : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf11_sel_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pedir_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pein_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_peout_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_peads_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pebset_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pebclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PEBCLR :16;
+ __IO uint32_t PEBSET :16;
+} stc_gpio_pebsetclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pedr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pepu_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pepd_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_peod_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pehie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pelie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_perie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pefie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfdir_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfin_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfout_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfads_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfbset_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfbclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PFBCLR :12;
+ uint32_t RESERVED12 : 4;
+ __IO uint32_t PFBSET :12;
+} stc_gpio_pfbsetclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfdr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfpu_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfpd_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfod_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfhie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pflie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pfrie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pffie_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe_stat_field_t;
+
+typedef struct
+{
+ __IO uint32_t PE00 : 1;
+ __IO uint32_t PE01 : 1;
+ __IO uint32_t PE02 : 1;
+ __IO uint32_t PE03 : 1;
+ __IO uint32_t PE04 : 1;
+ __IO uint32_t PE05 : 1;
+ __IO uint32_t PE06 : 1;
+ __IO uint32_t PE07 : 1;
+ __IO uint32_t PE08 : 1;
+ __IO uint32_t PE09 : 1;
+ __IO uint32_t PE10 : 1;
+ __IO uint32_t PE11 : 1;
+ __IO uint32_t PE12 : 1;
+ __IO uint32_t PE13 : 1;
+ __IO uint32_t PE14 : 1;
+ __IO uint32_t PE15 : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pe_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf_stat_field_t;
+
+typedef struct
+{
+ __IO uint32_t PF00 : 1;
+ __IO uint32_t PF01 : 1;
+ __IO uint32_t PF02 : 1;
+ __IO uint32_t PF03 : 1;
+ __IO uint32_t PF04 : 1;
+ __IO uint32_t PF05 : 1;
+ __IO uint32_t PF06 : 1;
+ __IO uint32_t PF07 : 1;
+ __IO uint32_t PF08 : 1;
+ __IO uint32_t PF09 : 1;
+ __IO uint32_t PF10 : 1;
+ __IO uint32_t PF11 : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_gpio_pf_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t TME : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_i2c_tmrun_field_t;
+
+typedef struct
+{
+ __IO uint32_t TM : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_i2c_tm_field_t;
+
+typedef struct
+{
+ __IO uint32_t H1M : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t AA : 1;
+ __IO uint32_t SI : 1;
+ __IO uint32_t STO : 1;
+ __IO uint32_t STA : 1;
+ __IO uint32_t ENS : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_i2c_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t DAT : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_i2c_data_field_t;
+
+typedef struct
+{
+ __IO uint32_t GC : 1;
+ __IO uint32_t ADR : 7;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_i2c_addr_field_t;
+
+typedef struct
+{
+ __IO uint32_t STA : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_i2c_stat_field_t;
+
+typedef struct
+{
+ __IO uint32_t EN : 1;
+ __IO uint32_t LCDCLK : 2;
+ __IO uint32_t CPCLK : 2;
+ __IO uint32_t BIAS : 1;
+ __IO uint32_t DUTY : 3;
+ __IO uint32_t BSEL : 3;
+ __IO uint32_t CONTRAST : 4;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_lcd_cr0_field_t;
+
+typedef struct
+{
+ __IO uint32_t BLINKCNT : 6;
+ __IO uint32_t BLINKEN : 1;
+ __IO uint32_t CLKSRC : 1;
+ __IO uint32_t MODE : 1;
+ __IO uint32_t IE : 1;
+ __IO uint32_t DMAEN : 1;
+ __IO uint32_t INTF : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_lcd_cr1_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 :10;
+ __IO uint32_t INTF : 1;
+ uint32_t RESERVED11 :20;
+ __IO uint32_t RSV : 1;
+} stc_lcd_intclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t S0 : 1;
+ __IO uint32_t S1 : 1;
+ __IO uint32_t S2 : 1;
+ __IO uint32_t S3 : 1;
+ __IO uint32_t S4 : 1;
+ __IO uint32_t S5 : 1;
+ __IO uint32_t S6 : 1;
+ __IO uint32_t S7 : 1;
+ __IO uint32_t S8 : 1;
+ __IO uint32_t S9 : 1;
+ __IO uint32_t S10 : 1;
+ __IO uint32_t S11 : 1;
+ __IO uint32_t S12 : 1;
+ __IO uint32_t S13 : 1;
+ __IO uint32_t S14 : 1;
+ __IO uint32_t S15 : 1;
+ __IO uint32_t S16 : 1;
+ __IO uint32_t S17 : 1;
+ __IO uint32_t S18 : 1;
+ __IO uint32_t S19 : 1;
+ __IO uint32_t S20 : 1;
+ __IO uint32_t S21 : 1;
+ __IO uint32_t S22 : 1;
+ __IO uint32_t S23 : 1;
+ __IO uint32_t S24 : 1;
+ __IO uint32_t S25 : 1;
+ __IO uint32_t S26 : 1;
+ __IO uint32_t S27 : 1;
+ __IO uint32_t S28 : 1;
+ __IO uint32_t S29 : 1;
+ __IO uint32_t S30 : 1;
+ __IO uint32_t S31 : 1;
+} stc_lcd_poen0_field_t;
+
+typedef struct
+{
+ __IO uint32_t S32 : 1;
+ __IO uint32_t S33 : 1;
+ __IO uint32_t S34 : 1;
+ __IO uint32_t S35 : 1;
+ __IO uint32_t S36C7 : 1;
+ __IO uint32_t S37C6 : 1;
+ __IO uint32_t S38C5 : 1;
+ __IO uint32_t S39C4 : 1;
+ __IO uint32_t S40 : 1;
+ __IO uint32_t S41 : 1;
+ __IO uint32_t S42 : 1;
+ __IO uint32_t S43 : 1;
+ __IO uint32_t MUX : 1;
+ __IO uint32_t S44 : 1;
+ __IO uint32_t S45 : 1;
+ __IO uint32_t S46 : 1;
+ __IO uint32_t S47 : 1;
+ __IO uint32_t S48 : 1;
+ __IO uint32_t S49 : 1;
+ __IO uint32_t S50 : 1;
+ __IO uint32_t S51 : 1;
+ __IO uint32_t C0 : 1;
+ __IO uint32_t C1 : 1;
+ __IO uint32_t C2 : 1;
+ __IO uint32_t C3 : 1;
+} stc_lcd_poen1_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t D24 : 1;
+ __IO uint32_t D25 : 1;
+ __IO uint32_t D26 : 1;
+ __IO uint32_t D27 : 1;
+ __IO uint32_t D28 : 1;
+ __IO uint32_t D29 : 1;
+ __IO uint32_t D30 : 1;
+ __IO uint32_t D31 : 1;
+} stc_lcd_ram0_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t D24 : 1;
+ __IO uint32_t D25 : 1;
+ __IO uint32_t D26 : 1;
+ __IO uint32_t D27 : 1;
+ __IO uint32_t D28 : 1;
+ __IO uint32_t D29 : 1;
+ __IO uint32_t D30 : 1;
+ __IO uint32_t D31 : 1;
+} stc_lcd_ram1_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t D24 : 1;
+ __IO uint32_t D25 : 1;
+ __IO uint32_t D26 : 1;
+ __IO uint32_t D27 : 1;
+ __IO uint32_t D28 : 1;
+ __IO uint32_t D29 : 1;
+ __IO uint32_t D30 : 1;
+ __IO uint32_t D31 : 1;
+} stc_lcd_ram2_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t D24 : 1;
+ __IO uint32_t D25 : 1;
+ __IO uint32_t D26 : 1;
+ __IO uint32_t D27 : 1;
+ __IO uint32_t D28 : 1;
+ __IO uint32_t D29 : 1;
+ __IO uint32_t D30 : 1;
+ __IO uint32_t D31 : 1;
+} stc_lcd_ram3_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t D24 : 1;
+ __IO uint32_t D25 : 1;
+ __IO uint32_t D26 : 1;
+ __IO uint32_t D27 : 1;
+ __IO uint32_t D28 : 1;
+ __IO uint32_t D29 : 1;
+ __IO uint32_t D30 : 1;
+ __IO uint32_t D31 : 1;
+} stc_lcd_ram4_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t D24 : 1;
+ __IO uint32_t D25 : 1;
+ __IO uint32_t D26 : 1;
+ __IO uint32_t D27 : 1;
+ __IO uint32_t D28 : 1;
+ __IO uint32_t D29 : 1;
+ __IO uint32_t D30 : 1;
+ __IO uint32_t D31 : 1;
+} stc_lcd_ram5_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t D24 : 1;
+ __IO uint32_t D25 : 1;
+ __IO uint32_t D26 : 1;
+ __IO uint32_t D27 : 1;
+ __IO uint32_t D28 : 1;
+ __IO uint32_t D29 : 1;
+ __IO uint32_t D30 : 1;
+ __IO uint32_t D31 : 1;
+} stc_lcd_ram6_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t D24 : 1;
+ __IO uint32_t D25 : 1;
+ __IO uint32_t D26 : 1;
+ __IO uint32_t D27 : 1;
+ __IO uint32_t D28 : 1;
+ __IO uint32_t D29 : 1;
+ __IO uint32_t D30 : 1;
+ __IO uint32_t D31 : 1;
+} stc_lcd_ram7_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t RSV : 8;
+} stc_lcd_ram8_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t RSV : 8;
+} stc_lcd_ram9_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t RSV : 8;
+} stc_lcd_rama_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t RSV : 8;
+} stc_lcd_ramb_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t RSV : 8;
+} stc_lcd_ramc_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t RSV : 8;
+} stc_lcd_ramd_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t RSV : 8;
+} stc_lcd_rame_field_t;
+
+typedef struct
+{
+ __IO uint32_t D0 : 1;
+ __IO uint32_t D1 : 1;
+ __IO uint32_t D2 : 1;
+ __IO uint32_t D3 : 1;
+ __IO uint32_t D4 : 1;
+ __IO uint32_t D5 : 1;
+ __IO uint32_t D6 : 1;
+ __IO uint32_t D7 : 1;
+ __IO uint32_t D8 : 1;
+ __IO uint32_t D9 : 1;
+ __IO uint32_t D10 : 1;
+ __IO uint32_t D11 : 1;
+ __IO uint32_t D12 : 1;
+ __IO uint32_t D13 : 1;
+ __IO uint32_t D14 : 1;
+ __IO uint32_t D15 : 1;
+ __IO uint32_t D16 : 1;
+ __IO uint32_t D17 : 1;
+ __IO uint32_t D18 : 1;
+ __IO uint32_t D19 : 1;
+ __IO uint32_t D20 : 1;
+ __IO uint32_t D21 : 1;
+ __IO uint32_t D22 : 1;
+ __IO uint32_t D23 : 1;
+ __IO uint32_t RSV : 8;
+} stc_lcd_ramf_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_lptimer_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARR :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_lptimer_arr_field_t;
+
+typedef struct
+{
+ __IO uint32_t TR : 1;
+ __IO uint32_t MD : 1;
+ __IO uint32_t CT : 1;
+ __IO uint32_t TOG_EN : 1;
+ __IO uint32_t TCK_SEL : 2;
+ uint32_t RESERVED6 : 1;
+ __IO uint32_t WT_FLAG : 1;
+ __IO uint32_t GATE : 1;
+ __IO uint32_t GATE_P : 1;
+ __IO uint32_t IE : 1;
+ __IO uint32_t PRS : 3;
+ uint32_t RESERVED14 :17;
+ __IO uint32_t RSV : 1;
+} stc_lptimer_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t TF : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_lptimer_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t TFC : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_lptimer_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t DATA : 8;
+ __IO uint32_t DATA8 : 1;
+ uint32_t RESERVED9 :22;
+ __IO uint32_t RSV : 1;
+} stc_lpuart_sbuf_field_t;
+
+typedef struct
+{
+ __IO uint32_t RCIE : 1;
+ __IO uint32_t TCIE : 1;
+ __IO uint32_t B8CONT : 2;
+ __IO uint32_t REN : 1;
+ __IO uint32_t ADRDET : 1;
+ __IO uint32_t SM : 2;
+ __IO uint32_t TXEIE : 1;
+ __IO uint32_t OVER : 2;
+ __IO uint32_t SCLKSEL : 2;
+ __IO uint32_t PEIE : 1;
+ __IO uint32_t STOPBIT : 2;
+ __IO uint32_t DMARXEN : 1;
+ __IO uint32_t DMATXEN : 1;
+ __IO uint32_t RTSEN : 1;
+ __IO uint32_t CTSEN : 1;
+ __IO uint32_t CTSIE : 1;
+ __IO uint32_t FEIE : 1;
+ __IO uint32_t HDSEL : 1;
+ uint32_t RESERVED23 : 8;
+ __IO uint32_t RSV : 1;
+} stc_lpuart_scon_field_t;
+
+typedef struct
+{
+ __IO uint32_t SADDR : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_lpuart_saddr_field_t;
+
+typedef struct
+{
+ __IO uint32_t SADEN : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_lpuart_saden_field_t;
+
+typedef struct
+{
+ __IO uint32_t RC : 1;
+ __IO uint32_t TC : 1;
+ __IO uint32_t FE : 1;
+ __IO uint32_t TXE : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t CTSIF : 1;
+ __IO uint32_t CTS : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_lpuart_isr_field_t;
+
+typedef struct
+{
+ __IO uint32_t RCCF : 1;
+ __IO uint32_t TCCF : 1;
+ __IO uint32_t FECF : 1;
+ uint32_t RESERVED3 : 1;
+ __IO uint32_t PECF : 1;
+ __IO uint32_t CTSIFCF : 1;
+ uint32_t RESERVED6 :25;
+ __IO uint32_t RSV : 1;
+} stc_lpuart_icr_field_t;
+
+typedef struct
+{
+ __IO uint32_t SCNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_lpuart_scnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t LVDEN : 1;
+ __IO uint32_t ACT : 1;
+ __IO uint32_t SOURCE_SEL : 2;
+ __IO uint32_t VTDS : 4;
+ __IO uint32_t FLTEN : 1;
+ __IO uint32_t DEBOUNCE_TIME : 3;
+ __IO uint32_t FTEN : 1;
+ __IO uint32_t RTEN : 1;
+ __IO uint32_t HTEN : 1;
+ __IO uint32_t IE : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_lvd_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t INTF : 1;
+ __IO uint32_t FILTER : 1;
+ uint32_t RESERVED2 :29;
+ __IO uint32_t RSV : 1;
+} stc_lvd_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t EN : 1;
+ __IO uint32_t AZEN : 1;
+ __IO uint32_t BUFEN : 1;
+ __IO uint32_t OEN1 : 1;
+ __IO uint32_t OEN2 : 1;
+ __IO uint32_t OEN3 : 1;
+ __IO uint32_t OEN4 : 1;
+ __IO uint32_t BIASSEL : 3;
+ uint32_t RESERVED10 :21;
+ __IO uint32_t RSV : 1;
+} stc_opa_cr0_field_t;
+
+typedef struct
+{
+ __IO uint32_t ADCTR_EN : 1;
+ __IO uint32_t TRIGGER : 1;
+ __IO uint32_t AZ_PULSE : 1;
+ __IO uint32_t CLK_SW_SET : 1;
+ __IO uint32_t CLK_SEL : 4;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_opa_cr1_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCF0 : 1;
+ __IO uint32_t CCF1 : 1;
+ __IO uint32_t CCF2 : 1;
+ __IO uint32_t CCF3 : 1;
+ __IO uint32_t CCF4 : 1;
+ uint32_t RESERVED5 : 1;
+ __IO uint32_t CR : 1;
+ __IO uint32_t CF : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccon_field_t;
+
+typedef struct
+{
+ __IO uint32_t CFIE : 1;
+ __IO uint32_t CPS : 3;
+ uint32_t RESERVED4 : 2;
+ __IO uint32_t WDTE : 1;
+ __IO uint32_t CIDL : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_cmod_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_pca_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCF0 : 1;
+ __IO uint32_t CCF1 : 1;
+ __IO uint32_t CCF2 : 1;
+ __IO uint32_t CCF3 : 1;
+ __IO uint32_t CCF4 : 1;
+ uint32_t RESERVED5 : 2;
+ __IO uint32_t CF : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCIE : 1;
+ __IO uint32_t PWM : 1;
+ __IO uint32_t TOG : 1;
+ __IO uint32_t MAT : 1;
+ __IO uint32_t CAPN : 1;
+ __IO uint32_t CAPP : 1;
+ __IO uint32_t ECOM : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccapm0_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCIE : 1;
+ __IO uint32_t PWM : 1;
+ __IO uint32_t TOG : 1;
+ __IO uint32_t MAT : 1;
+ __IO uint32_t CAPN : 1;
+ __IO uint32_t CAPP : 1;
+ __IO uint32_t ECOM : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccapm1_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCIE : 1;
+ __IO uint32_t PWM : 1;
+ __IO uint32_t TOG : 1;
+ __IO uint32_t MAT : 1;
+ __IO uint32_t CAPN : 1;
+ __IO uint32_t CAPP : 1;
+ __IO uint32_t ECOM : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccapm2_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCIE : 1;
+ __IO uint32_t PWM : 1;
+ __IO uint32_t TOG : 1;
+ __IO uint32_t MAT : 1;
+ __IO uint32_t CAPN : 1;
+ __IO uint32_t CAPP : 1;
+ __IO uint32_t ECOM : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccapm3_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCIE : 1;
+ __IO uint32_t PWM : 1;
+ __IO uint32_t TOG : 1;
+ __IO uint32_t MAT : 1;
+ __IO uint32_t CAPN : 1;
+ __IO uint32_t CAPP : 1;
+ __IO uint32_t ECOM : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccapm4_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP0 : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap0h_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP0 : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap0l_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP1 : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap1h_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP1 : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap1l_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP2 : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap2h_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP2 : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap2l_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP3 : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap3h_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP3 : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap3l_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP4 : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap4h_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP4 : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap4l_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAPO0 : 1;
+ __IO uint32_t CCAPO1 : 1;
+ __IO uint32_t CCAPO2 : 1;
+ __IO uint32_t CCAPO3 : 1;
+ __IO uint32_t CCAPO4 : 1;
+ uint32_t RESERVED5 :26;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccapo_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP0 :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap0_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP1 :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap1_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP2 :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap2_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP3 :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap3_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCAP4 :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_pca_ccap4_field_t;
+
+typedef struct
+{
+ __IO uint32_t CARR :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_pca_carr_field_t;
+
+typedef struct
+{
+ __IO uint32_t EPWM : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_pca_epwm_field_t;
+
+typedef struct
+{
+ __IO uint32_t RUN : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_run_field_t;
+
+typedef struct
+{
+ __IO uint32_t MODE : 2;
+ __IO uint32_t CLKSEL : 2;
+ __IO uint32_t DIR : 1;
+ __IO uint32_t S0P : 1;
+ __IO uint32_t S1P : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_ctrl_field_t;
+
+typedef struct
+{
+ __IO uint32_t CLKDIV :13;
+ __IO uint32_t DEBTOP : 3;
+ __IO uint32_t EN : 1;
+ uint32_t RESERVED17 :14;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_flt_field_t;
+
+typedef struct
+{
+ __IO uint32_t TH :12;
+ uint32_t RESERVED12 : 4;
+ __IO uint32_t EN : 1;
+ uint32_t RESERVED17 :14;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_tocr_field_t;
+
+typedef struct
+{
+ __IO uint32_t T2C : 1;
+ __IO uint32_t B2T : 1;
+ __IO uint32_t B2C : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_cmd_field_t;
+
+typedef struct
+{
+ __IO uint32_t DIR : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_sr1_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t TOP :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_top_field_t;
+
+typedef struct
+{
+ __IO uint32_t BUF :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_buf_field_t;
+
+typedef struct
+{
+ __IO uint32_t UF : 1;
+ __IO uint32_t OV : 1;
+ __IO uint32_t TO : 1;
+ __IO uint32_t DIR : 1;
+ __IO uint32_t FE : 1;
+ __IO uint32_t BB : 1;
+ __IO uint32_t S0E : 1;
+ __IO uint32_t S1E : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UF : 1;
+ __IO uint32_t OV : 1;
+ __IO uint32_t TO : 1;
+ __IO uint32_t DIR : 1;
+ __IO uint32_t FE : 1;
+ __IO uint32_t BB : 1;
+ __IO uint32_t S0E : 1;
+ __IO uint32_t S1E : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_icr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UF : 1;
+ __IO uint32_t OV : 1;
+ __IO uint32_t TO : 1;
+ __IO uint32_t DIR : 1;
+ __IO uint32_t FE : 1;
+ __IO uint32_t BB : 1;
+ __IO uint32_t S0E : 1;
+ __IO uint32_t S1E : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_ien_field_t;
+
+typedef struct
+{
+ __IO uint32_t T2C : 1;
+ __IO uint32_t B2T : 1;
+ __IO uint32_t B2C : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_sr2_field_t;
+
+typedef struct
+{
+ __IO uint32_t DBG : 2;
+ uint32_t RESERVED2 :29;
+ __IO uint32_t RSV : 1;
+} stc_pcnt_dbg_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 1;
+ __IO uint32_t IE : 1;
+ uint32_t RESERVED2 :29;
+ __IO uint32_t RSV : 1;
+} stc_ram_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t ERRADDR :14;
+ uint32_t RESERVED14 :17;
+ __IO uint32_t RSV : 1;
+} stc_ram_erraddr_field_t;
+
+typedef struct
+{
+ __IO uint32_t ERR : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_ram_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t ERRCLR : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_ram_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t POR5V : 1;
+ __IO uint32_t POR15V : 1;
+ __IO uint32_t LVD : 1;
+ __IO uint32_t WDT : 1;
+ __IO uint32_t PCA : 1;
+ __IO uint32_t LOCKUP : 1;
+ __IO uint32_t SYSREQ : 1;
+ __IO uint32_t RSTB : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_reset_flag_field_t;
+
+typedef struct
+{
+ __IO uint32_t UART0 : 1;
+ __IO uint32_t UART1 : 1;
+ __IO uint32_t LPUART0 : 1;
+ __IO uint32_t LPUART1 : 1;
+ __IO uint32_t I2C0 : 1;
+ __IO uint32_t I2C1 : 1;
+ __IO uint32_t SPI0 : 1;
+ __IO uint32_t SPI1 : 1;
+ __IO uint32_t BASETIM : 1;
+ __IO uint32_t LPTIM0 : 1;
+ __IO uint32_t ADVTIM : 1;
+ __IO uint32_t TIM3 : 1;
+ uint32_t RESERVED12 : 1;
+ __IO uint32_t OPA : 1;
+ __IO uint32_t PCA : 1;
+ uint32_t RESERVED15 : 1;
+ __IO uint32_t ADC : 1;
+ __IO uint32_t VC : 1;
+ __IO uint32_t RNG : 1;
+ __IO uint32_t PCNT : 1;
+ __IO uint32_t RTC : 1;
+ __IO uint32_t TRIM : 1;
+ __IO uint32_t LCD : 1;
+ uint32_t RESERVED23 : 1;
+ __IO uint32_t TICK : 1;
+ __IO uint32_t SWD : 1;
+ __IO uint32_t CRC : 1;
+ __IO uint32_t AES : 1;
+ __IO uint32_t GPIO : 1;
+ __IO uint32_t DMA : 1;
+} stc_reset_peri_reset0_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 3;
+ __IO uint32_t DAC : 1;
+ __IO uint32_t LPTIM1 : 1;
+ uint32_t RESERVED5 : 3;
+ __IO uint32_t UART2 : 1;
+ __IO uint32_t UART3 : 1;
+ uint32_t RESERVED10 :21;
+ __IO uint32_t RSV : 1;
+} stc_reset_peri_reset1_field_t;
+
+typedef struct
+{
+ __IO uint32_t PRDS : 3;
+ __IO uint32_t AMPM : 1;
+ uint32_t RESERVED4 : 1;
+ __IO uint32_t HZ1OE : 1;
+ __IO uint32_t HZ1SEL : 1;
+ __IO uint32_t START : 1;
+ __IO uint32_t PRDX : 6;
+ __IO uint32_t PRDSEL : 1;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_rtc_cr0_field_t;
+
+typedef struct
+{
+ __IO uint32_t WAIT : 1;
+ __IO uint32_t WAITF : 1;
+ uint32_t RESERVED2 : 1;
+ __IO uint32_t PRDF : 1;
+ __IO uint32_t ALMF : 1;
+ uint32_t RESERVED5 : 1;
+ __IO uint32_t ALMIE : 1;
+ __IO uint32_t ALMEN : 1;
+ __IO uint32_t CKSEL : 3;
+ uint32_t RESERVED11 :20;
+ __IO uint32_t RSV : 1;
+} stc_rtc_cr1_field_t;
+
+typedef struct
+{
+ __IO uint32_t SECL : 4;
+ __IO uint32_t SECH : 3;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_rtc_sec_field_t;
+
+typedef struct
+{
+ __IO uint32_t MINL : 4;
+ __IO uint32_t MINH : 3;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_rtc_min_field_t;
+
+typedef struct
+{
+ __IO uint32_t HOURL : 4;
+ __IO uint32_t HOURH : 2;
+ uint32_t RESERVED6 :25;
+ __IO uint32_t RSV : 1;
+} stc_rtc_hour_field_t;
+
+typedef struct
+{
+ __IO uint32_t WEEK : 3;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_rtc_week_field_t;
+
+typedef struct
+{
+ __IO uint32_t DAYL : 4;
+ __IO uint32_t DAYH : 2;
+ uint32_t RESERVED6 :25;
+ __IO uint32_t RSV : 1;
+} stc_rtc_day_field_t;
+
+typedef struct
+{
+ __IO uint32_t MON : 5;
+ uint32_t RESERVED5 :26;
+ __IO uint32_t RSV : 1;
+} stc_rtc_mon_field_t;
+
+typedef struct
+{
+ __IO uint32_t YEARL : 4;
+ __IO uint32_t YEARH : 4;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_rtc_year_field_t;
+
+typedef struct
+{
+ __IO uint32_t ALMMINL : 4;
+ __IO uint32_t ALMMINH : 3;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_rtc_almmin_field_t;
+
+typedef struct
+{
+ __IO uint32_t ALMHOURL : 4;
+ __IO uint32_t ALMHOURH : 2;
+ uint32_t RESERVED6 :25;
+ __IO uint32_t RSV : 1;
+} stc_rtc_almhour_field_t;
+
+typedef struct
+{
+ __IO uint32_t ALMWEEK : 7;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_rtc_almweek_field_t;
+
+typedef struct
+{
+ __IO uint32_t CR : 9;
+ uint32_t RESERVED9 : 6;
+ __IO uint32_t EN : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_rtc_compen_field_t;
+
+typedef struct
+{
+ __IO uint32_t ALMSECL : 4;
+ __IO uint32_t ALMSECH : 3;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_rtc_almsec_field_t;
+
+typedef struct
+{
+ __IO uint32_t SPR0 : 1;
+ __IO uint32_t SPR1 : 1;
+ __IO uint32_t CPHA : 1;
+ __IO uint32_t CPOL : 1;
+ __IO uint32_t MSTR : 1;
+ uint32_t RESERVED5 : 1;
+ __IO uint32_t SPEN : 1;
+ __IO uint32_t SPR2 : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_spi_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t SSN : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_spi_ssn_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 1;
+ __IO uint32_t RXNE : 1;
+ __IO uint32_t TXE : 1;
+ __IO uint32_t BUSY : 1;
+ __IO uint32_t MDF : 1;
+ __IO uint32_t SSERR : 1;
+ uint32_t RESERVED6 : 1;
+ __IO uint32_t SPIF : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_spi_stat_field_t;
+
+typedef struct
+{
+ __IO uint32_t DAT : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_spi_data_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 2;
+ __IO uint32_t INT_EN : 1;
+ __IO uint32_t HDMA_RX : 1;
+ __IO uint32_t HDMA_TX : 1;
+ __IO uint32_t TXEIE : 1;
+ __IO uint32_t RXNEIE : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_spi_cr2_field_t;
+
+typedef struct
+{
+ __IO uint32_t INT_CLR : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_spi_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t RCH_EN : 1;
+ __IO uint32_t XTH_EN : 1;
+ __IO uint32_t RCL_EN : 1;
+ __IO uint32_t XTL_EN : 1;
+ __IO uint32_t PLL_EN : 1;
+ __IO uint32_t CLKSW : 3;
+ __IO uint32_t HCLK_PRS : 3;
+ __IO uint32_t PCLK_PRS : 2;
+ uint32_t RESERVED13 : 2;
+ __IO uint32_t WAKEUP_BYRCH : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_sysctrl_sysctrl0_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 1;
+ __IO uint32_t EXTH_EN : 1;
+ __IO uint32_t EXTL_EN : 1;
+ __IO uint32_t XTL_ALWAYS_ON : 1;
+ uint32_t RESERVED4 : 1;
+ __IO uint32_t RTC_LPW : 1;
+ __IO uint32_t LOCKUP_EN : 1;
+ uint32_t RESERVED7 : 1;
+ __IO uint32_t SWD_USE_IO : 1;
+ __IO uint32_t RTC_FREQ_ADJUST : 3;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_sysctrl_sysctrl1_field_t;
+
+typedef struct
+{
+ __IO uint32_t SYSCTRL2 :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_sysctrl_sysctrl2_field_t;
+
+typedef struct
+{
+ __IO uint32_t TRIM :11;
+ __IO uint32_t STABLE : 1;
+ uint32_t RESERVED12 :19;
+ __IO uint32_t RSV : 1;
+} stc_sysctrl_rch_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t DRIVER : 2;
+ __IO uint32_t XTH_FSEL : 2;
+ __IO uint32_t STARTUP : 2;
+ __IO uint32_t STABLE : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_sysctrl_xth_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t TRIM :10;
+ __IO uint32_t STARTUP : 2;
+ __IO uint32_t STABLE : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_sysctrl_rcl_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t DRIVER : 2;
+ __IO uint32_t AMP_SEL : 2;
+ __IO uint32_t STARTUP : 2;
+ __IO uint32_t STABLE : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_sysctrl_xtl_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UART0 : 1;
+ __IO uint32_t UART1 : 1;
+ __IO uint32_t LPUART0 : 1;
+ __IO uint32_t LPUART1 : 1;
+ __IO uint32_t I2C0 : 1;
+ __IO uint32_t I2C1 : 1;
+ __IO uint32_t SPI0 : 1;
+ __IO uint32_t SPI1 : 1;
+ __IO uint32_t BASETIM : 1;
+ __IO uint32_t LPTIM0 : 1;
+ __IO uint32_t ADVTIM : 1;
+ __IO uint32_t TIM3 : 1;
+ uint32_t RESERVED12 : 1;
+ __IO uint32_t OPA : 1;
+ __IO uint32_t PCA : 1;
+ __IO uint32_t WDT : 1;
+ __IO uint32_t ADC : 1;
+ __IO uint32_t VC : 1;
+ __IO uint32_t RNG : 1;
+ __IO uint32_t PCNT : 1;
+ __IO uint32_t RTC : 1;
+ __IO uint32_t TRIM : 1;
+ __IO uint32_t LCD : 1;
+ uint32_t RESERVED23 : 1;
+ __IO uint32_t TICK : 1;
+ __IO uint32_t SWD : 1;
+ __IO uint32_t CRC : 1;
+ __IO uint32_t AES : 1;
+ __IO uint32_t GPIO : 1;
+ __IO uint32_t DMA : 1;
+ uint32_t RESERVED30 : 1;
+ __IO uint32_t FLASH : 1;
+} stc_sysctrl_peri_clken0_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 3;
+ __IO uint32_t DAC : 1;
+ __IO uint32_t LPTIM1 : 1;
+ uint32_t RESERVED5 : 3;
+ __IO uint32_t UART2 : 1;
+ __IO uint32_t UART3 : 1;
+ uint32_t RESERVED10 :21;
+ __IO uint32_t RSV : 1;
+} stc_sysctrl_peri_clken1_field_t;
+
+typedef struct
+{
+ __IO uint32_t REFSEL : 2;
+ __IO uint32_t FOSC : 3;
+ __IO uint32_t DIVN : 4;
+ __IO uint32_t IBSEL : 2;
+ __IO uint32_t LFSEL : 2;
+ __IO uint32_t FRSEL : 2;
+ __IO uint32_t STARTUP : 3;
+ __IO uint32_t STABLE : 1;
+ uint32_t RESERVED19 :12;
+ __IO uint32_t RSV : 1;
+} stc_sysctrl_pll_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARR :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode0_arr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode0_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT32 :32;
+} stc_tim0_mode0_cnt32_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ __IO uint32_t MD : 1;
+ __IO uint32_t CT : 1;
+ __IO uint32_t TOGEN : 1;
+ __IO uint32_t PRS : 3;
+ uint32_t RESERVED7 : 1;
+ __IO uint32_t GATE : 1;
+ __IO uint32_t GATEP : 1;
+ __IO uint32_t UIE : 1;
+ uint32_t RESERVED11 : 1;
+ __IO uint32_t MODE : 2;
+ uint32_t RESERVED14 :17;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode0_m0cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode0_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode0_iclr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 :12;
+ __IO uint32_t MOE : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode0_dtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode1_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CT : 1;
+ uint32_t RESERVED3 : 1;
+ __IO uint32_t PRS : 3;
+ uint32_t RESERVED7 : 1;
+ __IO uint32_t EDG1ST : 1;
+ __IO uint32_t EDG2ND : 1;
+ __IO uint32_t UIE : 1;
+ uint32_t RESERVED11 : 1;
+ __IO uint32_t MODE : 2;
+ __IO uint32_t ONESHOT : 1;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode1_m1cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode1_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode1_iclr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 5;
+ __IO uint32_t TS : 3;
+ uint32_t RESERVED8 : 3;
+ __IO uint32_t IA0S : 1;
+ __IO uint32_t IB0S : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode1_mscr_field_t;
+
+typedef struct
+{
+ __IO uint32_t FLTA0 : 3;
+ uint32_t RESERVED3 : 1;
+ __IO uint32_t FLTB0 : 3;
+ uint32_t RESERVED7 :21;
+ __IO uint32_t FLTET : 3;
+ __IO uint32_t ETP : 1;
+} stc_tim0_mode1_fltr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 8;
+ __IO uint32_t CIEA : 1;
+ uint32_t RESERVED9 :22;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode1_cr0_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0A :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode1_ccr0a_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARR :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_arr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ __IO uint32_t COMP : 1;
+ __IO uint32_t CT : 1;
+ __IO uint32_t PWM2S : 1;
+ __IO uint32_t PRS : 3;
+ __IO uint32_t BUFPEN : 1;
+ __IO uint32_t CRG : 1;
+ __IO uint32_t CFG : 1;
+ __IO uint32_t UIE : 1;
+ __IO uint32_t UDE : 1;
+ __IO uint32_t MODE : 2;
+ __IO uint32_t ONESHOT : 1;
+ __IO uint32_t CSG : 1;
+ __IO uint32_t OCCS : 1;
+ __IO uint32_t URS : 1;
+ __IO uint32_t TDE : 1;
+ __IO uint32_t TIE : 1;
+ __IO uint32_t BIE : 1;
+ __IO uint32_t CIS : 2;
+ __IO uint32_t OCCE : 1;
+ __IO uint32_t TG : 1;
+ __IO uint32_t UG : 1;
+ __IO uint32_t BG : 1;
+ __IO uint32_t DIR : 1;
+ uint32_t RESERVED28 : 3;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_m23cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 : 2;
+ __IO uint32_t CB0F : 1;
+ uint32_t RESERVED6 : 2;
+ __IO uint32_t CA0E : 1;
+ uint32_t RESERVED9 : 2;
+ __IO uint32_t CB0E : 1;
+ uint32_t RESERVED12 : 2;
+ __IO uint32_t BIF : 1;
+ __IO uint32_t TIF : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 : 2;
+ __IO uint32_t CB0F : 1;
+ uint32_t RESERVED6 : 2;
+ __IO uint32_t CA0E : 1;
+ uint32_t RESERVED9 : 2;
+ __IO uint32_t CB0E : 1;
+ uint32_t RESERVED12 : 2;
+ __IO uint32_t BIF : 1;
+ __IO uint32_t TIF : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t MMS : 3;
+ __IO uint32_t CCDS : 1;
+ __IO uint32_t MSM : 1;
+ __IO uint32_t TS : 3;
+ __IO uint32_t SMS : 3;
+ __IO uint32_t IA0S : 1;
+ __IO uint32_t IB0S : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_mscr_field_t;
+
+typedef struct
+{
+ __IO uint32_t OCMA0_FLTA0 : 3;
+ __IO uint32_t CCPA0 : 1;
+ __IO uint32_t OCMB0_FLTB0 : 3;
+ __IO uint32_t CCPB0 : 1;
+ uint32_t RESERVED8 :16;
+ __IO uint32_t FLTBK : 3;
+ __IO uint32_t BKP : 1;
+ __IO uint32_t FLTET : 3;
+ __IO uint32_t ETP : 1;
+} stc_tim0_mode23_fltr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UEVE : 1;
+ __IO uint32_t CMA0E : 1;
+ uint32_t RESERVED2 : 2;
+ __IO uint32_t CMB0E : 1;
+ uint32_t RESERVED5 : 2;
+ __IO uint32_t ADTE : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_adtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CFA_CRA_BKSA : 2;
+ __IO uint32_t CFB_CRB_BKSB : 2;
+ __IO uint32_t CSA : 1;
+ __IO uint32_t CSB : 1;
+ __IO uint32_t BUFEA : 1;
+ __IO uint32_t BUFEB : 1;
+ __IO uint32_t CIEA : 1;
+ __IO uint32_t CIEB : 1;
+ __IO uint32_t CDEA : 1;
+ __IO uint32_t CDEB : 1;
+ __IO uint32_t CISB : 2;
+ __IO uint32_t CCGA : 1;
+ __IO uint32_t CCGB : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_crch0_field_t;
+
+typedef struct
+{
+ __IO uint32_t DTR : 8;
+ __IO uint32_t BKSEL : 1;
+ __IO uint32_t DTEN : 1;
+ __IO uint32_t BKE : 1;
+ __IO uint32_t AOE : 1;
+ __IO uint32_t MOE : 1;
+ __IO uint32_t SAFEEN : 1;
+ __IO uint32_t VCE : 1;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_dtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t RCR : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_rcr_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARRDM :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_arrdm_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0A :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_ccr0a_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0B :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim0_mode23_ccr0b_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARR :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode0_arr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode0_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT32 :32;
+} stc_tim1_mode0_cnt32_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ __IO uint32_t MD : 1;
+ __IO uint32_t CT : 1;
+ __IO uint32_t TOGEN : 1;
+ __IO uint32_t PRS : 3;
+ uint32_t RESERVED7 : 1;
+ __IO uint32_t GATE : 1;
+ __IO uint32_t GATEP : 1;
+ __IO uint32_t UIE : 1;
+ uint32_t RESERVED11 : 1;
+ __IO uint32_t MODE : 2;
+ uint32_t RESERVED14 :17;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode0_m0cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode0_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode0_iclr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 :12;
+ __IO uint32_t MOE : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode0_dtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode1_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CT : 1;
+ uint32_t RESERVED3 : 1;
+ __IO uint32_t PRS : 3;
+ uint32_t RESERVED7 : 1;
+ __IO uint32_t EDG1ST : 1;
+ __IO uint32_t EDG2ND : 1;
+ __IO uint32_t UIE : 1;
+ uint32_t RESERVED11 : 1;
+ __IO uint32_t MODE : 2;
+ __IO uint32_t ONESHOT : 1;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode1_m1cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode1_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode1_iclr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 5;
+ __IO uint32_t TS : 3;
+ uint32_t RESERVED8 : 3;
+ __IO uint32_t IA0S : 1;
+ __IO uint32_t IB0S : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode1_mscr_field_t;
+
+typedef struct
+{
+ __IO uint32_t FLTA0 : 3;
+ uint32_t RESERVED3 : 1;
+ __IO uint32_t FLTB0 : 3;
+ uint32_t RESERVED7 :21;
+ __IO uint32_t FLTET : 3;
+ __IO uint32_t ETP : 1;
+} stc_tim1_mode1_fltr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 8;
+ __IO uint32_t CIEA : 1;
+ uint32_t RESERVED9 :22;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode1_cr0_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0A :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode1_ccr0a_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARR :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_arr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ __IO uint32_t COMP : 1;
+ __IO uint32_t CT : 1;
+ __IO uint32_t PWM2S : 1;
+ __IO uint32_t PRS : 3;
+ __IO uint32_t BUFPEN : 1;
+ __IO uint32_t CRG : 1;
+ __IO uint32_t CFG : 1;
+ __IO uint32_t UIE : 1;
+ __IO uint32_t UDE : 1;
+ __IO uint32_t MODE : 2;
+ __IO uint32_t ONESHOT : 1;
+ __IO uint32_t CSG : 1;
+ __IO uint32_t OCCS : 1;
+ __IO uint32_t URS : 1;
+ __IO uint32_t TDE : 1;
+ __IO uint32_t TIE : 1;
+ __IO uint32_t BIE : 1;
+ __IO uint32_t CIS : 2;
+ __IO uint32_t OCCE : 1;
+ __IO uint32_t TG : 1;
+ __IO uint32_t UG : 1;
+ __IO uint32_t BG : 1;
+ __IO uint32_t DIR : 1;
+ uint32_t RESERVED28 : 3;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_m23cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 : 2;
+ __IO uint32_t CB0F : 1;
+ uint32_t RESERVED6 : 2;
+ __IO uint32_t CA0E : 1;
+ uint32_t RESERVED9 : 2;
+ __IO uint32_t CB0E : 1;
+ uint32_t RESERVED12 : 2;
+ __IO uint32_t BIF : 1;
+ __IO uint32_t TIF : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 : 2;
+ __IO uint32_t CB0F : 1;
+ uint32_t RESERVED6 : 2;
+ __IO uint32_t CA0E : 1;
+ uint32_t RESERVED9 : 2;
+ __IO uint32_t CB0E : 1;
+ uint32_t RESERVED12 : 2;
+ __IO uint32_t BIF : 1;
+ __IO uint32_t TIF : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t MMS : 3;
+ __IO uint32_t CCDS : 1;
+ __IO uint32_t MSM : 1;
+ __IO uint32_t TS : 3;
+ __IO uint32_t SMS : 3;
+ __IO uint32_t IA0S : 1;
+ __IO uint32_t IB0S : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_mscr_field_t;
+
+typedef struct
+{
+ __IO uint32_t OCMA0_FLTA0 : 3;
+ __IO uint32_t CCPA0 : 1;
+ __IO uint32_t OCMB0_FLTB0 : 3;
+ __IO uint32_t CCPB0 : 1;
+ uint32_t RESERVED8 :16;
+ __IO uint32_t FLTBK : 3;
+ __IO uint32_t BKP : 1;
+ __IO uint32_t FLTET : 3;
+ __IO uint32_t ETP : 1;
+} stc_tim1_mode23_fltr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UEVE : 1;
+ __IO uint32_t CMA0E : 1;
+ uint32_t RESERVED2 : 2;
+ __IO uint32_t CMB0E : 1;
+ uint32_t RESERVED5 : 2;
+ __IO uint32_t ADTE : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_adtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CFA_CRA_BKSA : 2;
+ __IO uint32_t CFB_CRB_BKSB : 2;
+ __IO uint32_t CSA : 1;
+ __IO uint32_t CSB : 1;
+ __IO uint32_t BUFEA : 1;
+ __IO uint32_t BUFEB : 1;
+ __IO uint32_t CIEA : 1;
+ __IO uint32_t CIEB : 1;
+ __IO uint32_t CDEA : 1;
+ __IO uint32_t CDEB : 1;
+ __IO uint32_t CISB : 2;
+ __IO uint32_t CCGA : 1;
+ __IO uint32_t CCGB : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_crch0_field_t;
+
+typedef struct
+{
+ __IO uint32_t DTR : 8;
+ __IO uint32_t BKSEL : 1;
+ __IO uint32_t DTEN : 1;
+ __IO uint32_t BKE : 1;
+ __IO uint32_t AOE : 1;
+ __IO uint32_t MOE : 1;
+ __IO uint32_t SAFEEN : 1;
+ __IO uint32_t VCE : 1;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_dtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t RCR : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_rcr_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARRDM :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_arrdm_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0A :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_ccr0a_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0B :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim1_mode23_ccr0b_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARR :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode0_arr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode0_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT32 :32;
+} stc_tim2_mode0_cnt32_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ __IO uint32_t MD : 1;
+ __IO uint32_t CT : 1;
+ __IO uint32_t TOGEN : 1;
+ __IO uint32_t PRS : 3;
+ uint32_t RESERVED7 : 1;
+ __IO uint32_t GATE : 1;
+ __IO uint32_t GATEP : 1;
+ __IO uint32_t UIE : 1;
+ uint32_t RESERVED11 : 1;
+ __IO uint32_t MODE : 2;
+ uint32_t RESERVED14 :17;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode0_m0cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode0_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode0_iclr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 :12;
+ __IO uint32_t MOE : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode0_dtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode1_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CT : 1;
+ uint32_t RESERVED3 : 1;
+ __IO uint32_t PRS : 3;
+ uint32_t RESERVED7 : 1;
+ __IO uint32_t EDG1ST : 1;
+ __IO uint32_t EDG2ND : 1;
+ __IO uint32_t UIE : 1;
+ uint32_t RESERVED11 : 1;
+ __IO uint32_t MODE : 2;
+ __IO uint32_t ONESHOT : 1;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode1_m1cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode1_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode1_iclr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 5;
+ __IO uint32_t TS : 3;
+ uint32_t RESERVED8 : 3;
+ __IO uint32_t IA0S : 1;
+ __IO uint32_t IB0S : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode1_mscr_field_t;
+
+typedef struct
+{
+ __IO uint32_t FLTA0 : 3;
+ uint32_t RESERVED3 : 1;
+ __IO uint32_t FLTB0 : 3;
+ uint32_t RESERVED7 :21;
+ __IO uint32_t FLTET : 3;
+ __IO uint32_t ETP : 1;
+} stc_tim2_mode1_fltr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 8;
+ __IO uint32_t CIEA : 1;
+ uint32_t RESERVED9 :22;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode1_cr0_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0A :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode1_ccr0a_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARR :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_arr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ __IO uint32_t COMP : 1;
+ __IO uint32_t CT : 1;
+ __IO uint32_t PWM2S : 1;
+ __IO uint32_t PRS : 3;
+ __IO uint32_t BUFPEN : 1;
+ __IO uint32_t CRG : 1;
+ __IO uint32_t CFG : 1;
+ __IO uint32_t UIE : 1;
+ __IO uint32_t UDE : 1;
+ __IO uint32_t MODE : 2;
+ __IO uint32_t ONESHOT : 1;
+ __IO uint32_t CSG : 1;
+ __IO uint32_t OCCS : 1;
+ __IO uint32_t URS : 1;
+ __IO uint32_t TDE : 1;
+ __IO uint32_t TIE : 1;
+ __IO uint32_t BIE : 1;
+ __IO uint32_t CIS : 2;
+ __IO uint32_t OCCE : 1;
+ __IO uint32_t TG : 1;
+ __IO uint32_t UG : 1;
+ __IO uint32_t BG : 1;
+ __IO uint32_t DIR : 1;
+ uint32_t RESERVED28 : 3;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_m23cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 : 2;
+ __IO uint32_t CB0F : 1;
+ uint32_t RESERVED6 : 2;
+ __IO uint32_t CA0E : 1;
+ uint32_t RESERVED9 : 2;
+ __IO uint32_t CB0E : 1;
+ uint32_t RESERVED12 : 2;
+ __IO uint32_t BIF : 1;
+ __IO uint32_t TIF : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 : 2;
+ __IO uint32_t CB0F : 1;
+ uint32_t RESERVED6 : 2;
+ __IO uint32_t CA0E : 1;
+ uint32_t RESERVED9 : 2;
+ __IO uint32_t CB0E : 1;
+ uint32_t RESERVED12 : 2;
+ __IO uint32_t BIF : 1;
+ __IO uint32_t TIF : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t MMS : 3;
+ __IO uint32_t CCDS : 1;
+ __IO uint32_t MSM : 1;
+ __IO uint32_t TS : 3;
+ __IO uint32_t SMS : 3;
+ __IO uint32_t IA0S : 1;
+ __IO uint32_t IB0S : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_mscr_field_t;
+
+typedef struct
+{
+ __IO uint32_t OCMA0_FLTA0 : 3;
+ __IO uint32_t CCPA0 : 1;
+ __IO uint32_t OCMB0_FLTB0 : 3;
+ __IO uint32_t CCPB0 : 1;
+ uint32_t RESERVED8 :16;
+ __IO uint32_t FLTBK : 3;
+ __IO uint32_t BKP : 1;
+ __IO uint32_t FLTET : 3;
+ __IO uint32_t ETP : 1;
+} stc_tim2_mode23_fltr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UEVE : 1;
+ __IO uint32_t CMA0E : 1;
+ uint32_t RESERVED2 : 2;
+ __IO uint32_t CMB0E : 1;
+ uint32_t RESERVED5 : 2;
+ __IO uint32_t ADTE : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_adtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CFA_CRA_BKSA : 2;
+ __IO uint32_t CFB_CRB_BKSB : 2;
+ __IO uint32_t CSA : 1;
+ __IO uint32_t CSB : 1;
+ __IO uint32_t BUFEA : 1;
+ __IO uint32_t BUFEB : 1;
+ __IO uint32_t CIEA : 1;
+ __IO uint32_t CIEB : 1;
+ __IO uint32_t CDEA : 1;
+ __IO uint32_t CDEB : 1;
+ __IO uint32_t CISB : 2;
+ __IO uint32_t CCGA : 1;
+ __IO uint32_t CCGB : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_crch0_field_t;
+
+typedef struct
+{
+ __IO uint32_t DTR : 8;
+ __IO uint32_t BKSEL : 1;
+ __IO uint32_t DTEN : 1;
+ __IO uint32_t BKE : 1;
+ __IO uint32_t AOE : 1;
+ __IO uint32_t MOE : 1;
+ __IO uint32_t SAFEEN : 1;
+ __IO uint32_t VCE : 1;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_dtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t RCR : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_rcr_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARRDM :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_arrdm_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0A :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_ccr0a_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0B :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim2_mode23_ccr0b_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARR :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode0_arr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode0_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT32 :32;
+} stc_tim3_mode0_cnt32_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ __IO uint32_t MD : 1;
+ __IO uint32_t CT : 1;
+ __IO uint32_t TOGEN : 1;
+ __IO uint32_t PRS : 3;
+ uint32_t RESERVED7 : 1;
+ __IO uint32_t GATE : 1;
+ __IO uint32_t GATEP : 1;
+ __IO uint32_t UIE : 1;
+ uint32_t RESERVED11 : 1;
+ __IO uint32_t MODE : 2;
+ uint32_t RESERVED14 :17;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode0_m0cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode0_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 :30;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode0_iclr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 :12;
+ __IO uint32_t MOE : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode0_dtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode1_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CT : 1;
+ uint32_t RESERVED3 : 1;
+ __IO uint32_t PRS : 3;
+ uint32_t RESERVED7 : 1;
+ __IO uint32_t EDG1ST : 1;
+ __IO uint32_t EDG2ND : 1;
+ __IO uint32_t UIE : 1;
+ uint32_t RESERVED11 : 1;
+ __IO uint32_t MODE : 2;
+ __IO uint32_t ONESHOT : 1;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode1_m1cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode1_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ uint32_t RESERVED3 :28;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode1_iclr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 5;
+ __IO uint32_t TS : 3;
+ uint32_t RESERVED8 : 3;
+ __IO uint32_t IA0S : 1;
+ __IO uint32_t IB0S : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode1_mscr_field_t;
+
+typedef struct
+{
+ __IO uint32_t FLTA0 : 3;
+ uint32_t RESERVED3 : 1;
+ __IO uint32_t FLTB0 : 3;
+ uint32_t RESERVED7 :21;
+ __IO uint32_t FLTET : 3;
+ __IO uint32_t ETP : 1;
+} stc_tim3_mode1_fltr_field_t;
+
+typedef struct
+{
+ uint32_t RESERVED0 : 8;
+ __IO uint32_t CIEA : 1;
+ uint32_t RESERVED9 :22;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode1_cr0_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0A :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode1_ccr0a_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARR :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_arr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_cnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t CTEN : 1;
+ __IO uint32_t COMP : 1;
+ __IO uint32_t CT : 1;
+ __IO uint32_t PWM2S : 1;
+ __IO uint32_t PRS : 3;
+ __IO uint32_t BUFPEN : 1;
+ __IO uint32_t CRG : 1;
+ __IO uint32_t CFG : 1;
+ __IO uint32_t UIE : 1;
+ __IO uint32_t UDE : 1;
+ __IO uint32_t MODE : 2;
+ __IO uint32_t ONESHOT : 1;
+ __IO uint32_t CSG : 1;
+ __IO uint32_t OCCS : 1;
+ __IO uint32_t URS : 1;
+ __IO uint32_t TDE : 1;
+ __IO uint32_t TIE : 1;
+ __IO uint32_t BIE : 1;
+ __IO uint32_t CIS : 2;
+ __IO uint32_t OCCE : 1;
+ __IO uint32_t TG : 1;
+ __IO uint32_t UG : 1;
+ __IO uint32_t BG : 1;
+ __IO uint32_t DIR : 1;
+ uint32_t RESERVED28 : 3;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_m23cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ __IO uint32_t CA1F : 1;
+ __IO uint32_t CA2F : 1;
+ __IO uint32_t CB0F : 1;
+ __IO uint32_t CB1F : 1;
+ __IO uint32_t CB2F : 1;
+ __IO uint32_t CA0E : 1;
+ __IO uint32_t CA1E : 1;
+ __IO uint32_t CA2E : 1;
+ __IO uint32_t CB0E : 1;
+ __IO uint32_t CB1E : 1;
+ __IO uint32_t CB2E : 1;
+ __IO uint32_t BIF : 1;
+ __IO uint32_t TIF : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UIF : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t CA0F : 1;
+ __IO uint32_t CA1F : 1;
+ __IO uint32_t CA2F : 1;
+ __IO uint32_t CB0F : 1;
+ __IO uint32_t CB1F : 1;
+ __IO uint32_t CB2F : 1;
+ __IO uint32_t CA0E : 1;
+ __IO uint32_t CA1E : 1;
+ __IO uint32_t CA2E : 1;
+ __IO uint32_t CB0E : 1;
+ __IO uint32_t CB1E : 1;
+ __IO uint32_t CB2E : 1;
+ __IO uint32_t BIF : 1;
+ __IO uint32_t TIF : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_iclr_field_t;
+
+typedef struct
+{
+ __IO uint32_t MMS : 3;
+ __IO uint32_t CCDS : 1;
+ __IO uint32_t MSM : 1;
+ __IO uint32_t TS : 3;
+ __IO uint32_t SMS : 3;
+ __IO uint32_t IA0S : 1;
+ __IO uint32_t IB0S : 1;
+ uint32_t RESERVED13 :18;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_mscr_field_t;
+
+typedef struct
+{
+ __IO uint32_t OCMA0_FLTA0 : 3;
+ __IO uint32_t CCPA0 : 1;
+ __IO uint32_t OCMB0_FLTB0 : 3;
+ __IO uint32_t CCPB0 : 1;
+ __IO uint32_t OCMA1_FLTA1 : 3;
+ __IO uint32_t CCPA1 : 1;
+ __IO uint32_t OCMB1_FLTB1 : 3;
+ __IO uint32_t CCPB1 : 1;
+ __IO uint32_t OCMA2_FLTA2 : 3;
+ __IO uint32_t CCPA2 : 1;
+ __IO uint32_t OCMB2_FLTB2 : 3;
+ __IO uint32_t CCPB2 : 1;
+ __IO uint32_t FLTBK : 3;
+ __IO uint32_t BKP : 1;
+ __IO uint32_t FLTET : 3;
+ __IO uint32_t ETP : 1;
+} stc_tim3_mode23_fltr_field_t;
+
+typedef struct
+{
+ __IO uint32_t UEVE : 1;
+ __IO uint32_t CMA0E : 1;
+ __IO uint32_t CMA1E : 1;
+ __IO uint32_t CMA2E : 1;
+ __IO uint32_t CMB0E : 1;
+ __IO uint32_t CMB1E : 1;
+ __IO uint32_t CMB2E : 1;
+ __IO uint32_t ADTE : 1;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_adtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t CFA_CRA_BKSA : 2;
+ __IO uint32_t CFB_CRB_BKSB : 2;
+ __IO uint32_t CSA : 1;
+ __IO uint32_t CSB : 1;
+ __IO uint32_t BUFEA : 1;
+ __IO uint32_t BUFEB : 1;
+ __IO uint32_t CIEA : 1;
+ __IO uint32_t CIEB : 1;
+ __IO uint32_t CDEA : 1;
+ __IO uint32_t CDEB : 1;
+ __IO uint32_t CISB : 2;
+ __IO uint32_t CCGA : 1;
+ __IO uint32_t CCGB : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_crch0_field_t;
+
+typedef struct
+{
+ __IO uint32_t CFA_CRA_BKSA : 2;
+ __IO uint32_t CFB_CRB_BKSB : 2;
+ __IO uint32_t CSA : 1;
+ __IO uint32_t CSB : 1;
+ __IO uint32_t BUFEA : 1;
+ __IO uint32_t BUFEB : 1;
+ __IO uint32_t CIEA : 1;
+ __IO uint32_t CIEB : 1;
+ __IO uint32_t CDEA : 1;
+ __IO uint32_t CDEB : 1;
+ __IO uint32_t CISB : 2;
+ __IO uint32_t CCGA : 1;
+ __IO uint32_t CCGB : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_crch1_field_t;
+
+typedef struct
+{
+ __IO uint32_t CFA_CRA_BKSA : 2;
+ __IO uint32_t CFB_CRB_BKSB : 2;
+ __IO uint32_t CSA : 1;
+ __IO uint32_t CSB : 1;
+ __IO uint32_t BUFEA : 1;
+ __IO uint32_t BUFEB : 1;
+ __IO uint32_t CIEA : 1;
+ __IO uint32_t CIEB : 1;
+ __IO uint32_t CDEA : 1;
+ __IO uint32_t CDEB : 1;
+ __IO uint32_t CISB : 2;
+ __IO uint32_t CCGA : 1;
+ __IO uint32_t CCGB : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_crch2_field_t;
+
+typedef struct
+{
+ __IO uint32_t DTR : 8;
+ __IO uint32_t BKSEL : 1;
+ __IO uint32_t DTEN : 1;
+ __IO uint32_t BKE : 1;
+ __IO uint32_t AOE : 1;
+ __IO uint32_t MOE : 1;
+ __IO uint32_t SAFEEN : 1;
+ __IO uint32_t VCE : 1;
+ uint32_t RESERVED15 :16;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_dtr_field_t;
+
+typedef struct
+{
+ __IO uint32_t RCR : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_rcr_field_t;
+
+typedef struct
+{
+ __IO uint32_t ARRDM :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_arrdm_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0A :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_ccr0a_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR0B :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_ccr0b_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR1A :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_ccr1a_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR1B :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_ccr1b_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR2A :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_ccr2a_field_t;
+
+typedef struct
+{
+ __IO uint32_t CCR2B :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_tim3_mode23_ccr2b_field_t;
+
+typedef struct
+{
+ __IO uint32_t RNGCIR_EN : 1;
+ __IO uint32_t RNG_RUN : 1;
+ uint32_t RESERVED2 :29;
+ __IO uint32_t RSV : 1;
+} stc_trng_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t LOAD : 1;
+ __IO uint32_t FDBK : 1;
+ __IO uint32_t CNT : 3;
+ uint32_t RESERVED5 :26;
+ __IO uint32_t RSV : 1;
+} stc_trng_mode_field_t;
+
+typedef struct
+{
+ __IO uint32_t DATA0 :32;
+} stc_trng_data0_field_t;
+
+typedef struct
+{
+ __IO uint32_t DATA1 :32;
+} stc_trng_data1_field_t;
+
+typedef struct
+{
+ __IO uint32_t DATA : 8;
+ __IO uint32_t DATA8 : 1;
+ uint32_t RESERVED9 :22;
+ __IO uint32_t RSV : 1;
+} stc_uart_sbuf_field_t;
+
+typedef struct
+{
+ __IO uint32_t RCIE : 1;
+ __IO uint32_t TCIE : 1;
+ __IO uint32_t B8CONT : 2;
+ __IO uint32_t REN : 1;
+ __IO uint32_t ADRDET : 1;
+ __IO uint32_t SM : 2;
+ __IO uint32_t TXEIE : 1;
+ __IO uint32_t OVER : 1;
+ uint32_t RESERVED10 : 3;
+ __IO uint32_t PEIE : 1;
+ __IO uint32_t STOPBIT : 2;
+ __IO uint32_t DMARXEN : 1;
+ __IO uint32_t DMATXEN : 1;
+ __IO uint32_t RTSEN : 1;
+ __IO uint32_t CTSEN : 1;
+ __IO uint32_t CTSIE : 1;
+ __IO uint32_t FEIE : 1;
+ __IO uint32_t HDSEL : 1;
+ uint32_t RESERVED23 : 8;
+ __IO uint32_t RSV : 1;
+} stc_uart_scon_field_t;
+
+typedef struct
+{
+ __IO uint32_t SADDR : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_uart_saddr_field_t;
+
+typedef struct
+{
+ __IO uint32_t SADEN : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_uart_saden_field_t;
+
+typedef struct
+{
+ __IO uint32_t RC : 1;
+ __IO uint32_t TC : 1;
+ __IO uint32_t FE : 1;
+ __IO uint32_t TXE : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t CTSIF : 1;
+ __IO uint32_t CTS : 1;
+ uint32_t RESERVED7 :24;
+ __IO uint32_t RSV : 1;
+} stc_uart_isr_field_t;
+
+typedef struct
+{
+ __IO uint32_t RCCF : 1;
+ __IO uint32_t TCCF : 1;
+ __IO uint32_t FECF : 1;
+ uint32_t RESERVED3 : 1;
+ __IO uint32_t PECF : 1;
+ __IO uint32_t CTSIFCF : 1;
+ uint32_t RESERVED6 :25;
+ __IO uint32_t RSV : 1;
+} stc_uart_icr_field_t;
+
+typedef struct
+{
+ __IO uint32_t SCNT :16;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_uart_scnt_field_t;
+
+typedef struct
+{
+ __IO uint32_t DIV : 6;
+ __IO uint32_t DIV_EN : 1;
+ __IO uint32_t REF2P5_SEL : 1;
+ __IO uint32_t VC0_BIAS_SEL : 2;
+ __IO uint32_t VC0_HYS_SEL : 2;
+ __IO uint32_t VC1_BIAS_SEL : 2;
+ __IO uint32_t VC1_HYS_SEL : 2;
+ __IO uint32_t VC2_BIAS_SEL : 2;
+ __IO uint32_t VC2_HYS_SEL : 2;
+ uint32_t RESERVED20 :11;
+ __IO uint32_t RSV : 1;
+} stc_vc_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t P_SEL : 4;
+ __IO uint32_t N_SEL : 4;
+ __IO uint32_t FLTEN : 1;
+ __IO uint32_t DEBOUNCE_TIME : 3;
+ __IO uint32_t FALLING : 1;
+ __IO uint32_t RISING : 1;
+ __IO uint32_t LEVEL : 1;
+ __IO uint32_t IE : 1;
+ __IO uint32_t EN : 1;
+ uint32_t RESERVED17 :14;
+ __IO uint32_t RSV : 1;
+} stc_vc_vc0_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t P_SEL : 4;
+ __IO uint32_t N_SEL : 4;
+ __IO uint32_t FLTEN : 1;
+ __IO uint32_t DEBOUNCE_TIME : 3;
+ __IO uint32_t FALLING : 1;
+ __IO uint32_t RISING : 1;
+ __IO uint32_t LEVEL : 1;
+ __IO uint32_t IE : 1;
+ __IO uint32_t EN : 1;
+ uint32_t RESERVED17 :14;
+ __IO uint32_t RSV : 1;
+} stc_vc_vc1_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t INV_TIMER : 1;
+ __IO uint32_t TIM0RCLR : 1;
+ __IO uint32_t TIM1RCLR : 1;
+ __IO uint32_t TIM2RCLR : 1;
+ __IO uint32_t TIM3RCLR : 1;
+ __IO uint32_t TIMBK : 1;
+ uint32_t RESERVED6 : 3;
+ __IO uint32_t INV_TIM4 : 1;
+ __IO uint32_t TIM4 : 1;
+ __IO uint32_t INV_TIM5 : 1;
+ __IO uint32_t TIM5 : 1;
+ __IO uint32_t INV_TIM6 : 1;
+ __IO uint32_t TIM6 : 1;
+ __IO uint32_t BRAKE : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_vc_vc0_out_cfg_field_t;
+
+typedef struct
+{
+ __IO uint32_t INV_TIMER : 1;
+ __IO uint32_t TIM0RCLR : 1;
+ __IO uint32_t TIM1RCLR : 1;
+ __IO uint32_t TIM2RCLR : 1;
+ __IO uint32_t TIM3RCLR : 1;
+ __IO uint32_t TIMBK : 1;
+ uint32_t RESERVED6 : 3;
+ __IO uint32_t INV_TIM4 : 1;
+ __IO uint32_t TIM4 : 1;
+ __IO uint32_t INV_TIM5 : 1;
+ __IO uint32_t TIM5 : 1;
+ __IO uint32_t INV_TIM6 : 1;
+ __IO uint32_t TIM6 : 1;
+ __IO uint32_t BRAKE : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_vc_vc1_out_cfg_field_t;
+
+typedef struct
+{
+ __IO uint32_t VC0_INTF : 1;
+ __IO uint32_t VC1_INTF : 1;
+ __IO uint32_t VC0_FILTER : 1;
+ __IO uint32_t VC1_FILTER : 1;
+ __IO uint32_t VC2_INTF : 1;
+ __IO uint32_t VC2_FILTER : 1;
+ uint32_t RESERVED6 :25;
+ __IO uint32_t RSV : 1;
+} stc_vc_ifr_field_t;
+
+typedef struct
+{
+ __IO uint32_t P_SEL : 4;
+ __IO uint32_t N_SEL : 4;
+ __IO uint32_t FLTEN : 1;
+ __IO uint32_t DEBOUNCE_TIME : 3;
+ __IO uint32_t FALLING : 1;
+ __IO uint32_t RISING : 1;
+ __IO uint32_t LEVEL : 1;
+ __IO uint32_t IE : 1;
+ __IO uint32_t EN : 1;
+ uint32_t RESERVED17 :14;
+ __IO uint32_t RSV : 1;
+} stc_vc_vc2_cr_field_t;
+
+typedef struct
+{
+ __IO uint32_t INV_TIMER : 1;
+ __IO uint32_t TIM0RCLR : 1;
+ __IO uint32_t TIM1RCLR : 1;
+ __IO uint32_t TIM2RCLR : 1;
+ __IO uint32_t TIM3RCLR : 1;
+ __IO uint32_t TIMBK : 1;
+ uint32_t RESERVED6 : 3;
+ __IO uint32_t INV_TIM4 : 1;
+ __IO uint32_t TIM4 : 1;
+ __IO uint32_t INV_TIM5 : 1;
+ __IO uint32_t TIM5 : 1;
+ __IO uint32_t INV_TIM6 : 1;
+ __IO uint32_t TIM6 : 1;
+ __IO uint32_t BRAKE : 1;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_vc_vc2_out_cfg_field_t;
+
+typedef struct
+{
+ __IO uint32_t RST : 8;
+ uint32_t RESERVED8 :23;
+ __IO uint32_t RSV : 1;
+} stc_wdt_rst_field_t;
+
+typedef struct
+{
+ __IO uint32_t WOV : 4;
+ __IO uint32_t R : 1;
+ __IO uint32_t WINT_EN : 1;
+ uint32_t RESERVED6 : 1;
+ __IO uint32_t INT : 1;
+ __IO uint32_t WCNTL : 8;
+ uint32_t RESERVED16 :15;
+ __IO uint32_t RSV : 1;
+} stc_wdt_con_field_t;
+
+
+typedef struct
+{
+ uint8_t RESERVED0[4];
+ union
+ {
+ __IO uint32_t CR0;
+ stc_adc_cr0_field_t CR0_f;
+ };
+ union
+ {
+ __IO uint32_t CR1;
+ stc_adc_cr1_field_t CR1_f;
+ };
+ uint8_t RESERVED2[52];
+ union
+ {
+ __IO uint32_t SQR0;
+ stc_adc_sqr0_field_t SQR0_f;
+ };
+ union
+ {
+ __IO uint32_t SQR1;
+ stc_adc_sqr1_field_t SQR1_f;
+ };
+ union
+ {
+ __IO uint32_t SQR2;
+ stc_adc_sqr2_field_t SQR2_f;
+ };
+ union
+ {
+ __IO uint32_t JQR;
+ stc_adc_jqr_field_t JQR_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT0;
+ stc_adc_sqrresult0_field_t SQRRESULT0_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT1;
+ stc_adc_sqrresult1_field_t SQRRESULT1_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT2;
+ stc_adc_sqrresult2_field_t SQRRESULT2_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT3;
+ stc_adc_sqrresult3_field_t SQRRESULT3_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT4;
+ stc_adc_sqrresult4_field_t SQRRESULT4_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT5;
+ stc_adc_sqrresult5_field_t SQRRESULT5_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT6;
+ stc_adc_sqrresult6_field_t SQRRESULT6_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT7;
+ stc_adc_sqrresult7_field_t SQRRESULT7_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT8;
+ stc_adc_sqrresult8_field_t SQRRESULT8_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT9;
+ stc_adc_sqrresult9_field_t SQRRESULT9_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT10;
+ stc_adc_sqrresult10_field_t SQRRESULT10_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT11;
+ stc_adc_sqrresult11_field_t SQRRESULT11_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT12;
+ stc_adc_sqrresult12_field_t SQRRESULT12_f;
+ };
+ union
+ {
+ __IO uint32_t SQR_RESULT13;
+ stc_adc_sqr_result13_field_t SQR_RESULT13_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT14;
+ stc_adc_sqrresult14_field_t SQRRESULT14_f;
+ };
+ union
+ {
+ __IO uint32_t SQRRESULT15;
+ stc_adc_sqrresult15_field_t SQRRESULT15_f;
+ };
+ union
+ {
+ __IO uint32_t JQRRESULT0;
+ stc_adc_jqrresult0_field_t JQRRESULT0_f;
+ };
+ union
+ {
+ __IO uint32_t JQRRESULT1;
+ stc_adc_jqrresult1_field_t JQRRESULT1_f;
+ };
+ union
+ {
+ __IO uint32_t JQRRESULT2;
+ stc_adc_jqrresult2_field_t JQRRESULT2_f;
+ };
+ union
+ {
+ __IO uint32_t JQRRESULT3;
+ stc_adc_jqrresult3_field_t JQRRESULT3_f;
+ };
+ union
+ {
+ __IO uint32_t RESULT;
+ stc_adc_result_field_t RESULT_f;
+ };
+ union
+ {
+ __IO uint32_t RESULTACC;
+ stc_adc_resultacc_field_t RESULTACC_f;
+ };
+ union
+ {
+ __IO uint32_t HT;
+ stc_adc_ht_field_t HT_f;
+ };
+ union
+ {
+ __IO uint32_t LT;
+ stc_adc_lt_field_t LT_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_adc_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICR;
+ stc_adc_icr_field_t ICR_f;
+ };
+ union
+ {
+ __IO uint32_t EXTTRIGGER0;
+ stc_adc_exttrigger0_field_t EXTTRIGGER0_f;
+ };
+ union
+ {
+ __IO uint32_t EXTTRIGGER1;
+ stc_adc_exttrigger1_field_t EXTTRIGGER1_f;
+ };
+ union
+ {
+ __IO uint32_t SGLSTART;
+ stc_adc_sglstart_field_t SGLSTART_f;
+ };
+ union
+ {
+ __IO uint32_t SQRSTART;
+ stc_adc_sqrstart_field_t SQRSTART_f;
+ };
+ union
+ {
+ __IO uint32_t JQRSTART;
+ stc_adc_jqrstart_field_t JQRSTART_f;
+ };
+ union
+ {
+ __IO uint32_t ALLSTART;
+ stc_adc_allstart_field_t ALLSTART_f;
+ };
+}M0P_ADC_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CNTER;
+ stc_adtim_cnter_field_t CNTER_f;
+ };
+ union
+ {
+ __IO uint32_t PERAR;
+ stc_adtim_perar_field_t PERAR_f;
+ };
+ union
+ {
+ __IO uint32_t PERBR;
+ stc_adtim_perbr_field_t PERBR_f;
+ };
+ uint8_t RESERVED3[4];
+ union
+ {
+ __IO uint32_t GCMAR;
+ stc_adtim_gcmar_field_t GCMAR_f;
+ };
+ union
+ {
+ __IO uint32_t GCMBR;
+ stc_adtim_gcmbr_field_t GCMBR_f;
+ };
+ union
+ {
+ __IO uint32_t GCMCR;
+ stc_adtim_gcmcr_field_t GCMCR_f;
+ };
+ union
+ {
+ __IO uint32_t GCMDR;
+ stc_adtim_gcmdr_field_t GCMDR_f;
+ };
+ uint8_t RESERVED7[8];
+ union
+ {
+ __IO uint32_t SCMAR;
+ stc_adtim_scmar_field_t SCMAR_f;
+ };
+ union
+ {
+ __IO uint32_t SCMBR;
+ stc_adtim_scmbr_field_t SCMBR_f;
+ };
+ uint8_t RESERVED9[16];
+ union
+ {
+ __IO uint32_t DTUAR;
+ stc_adtim_dtuar_field_t DTUAR_f;
+ };
+ union
+ {
+ __IO uint32_t DTDAR;
+ stc_adtim_dtdar_field_t DTDAR_f;
+ };
+ uint8_t RESERVED11[8];
+ union
+ {
+ __IO uint32_t GCONR;
+ stc_adtim_gconr_field_t GCONR_f;
+ };
+ union
+ {
+ __IO uint32_t ICONR;
+ stc_adtim_iconr_field_t ICONR_f;
+ };
+ union
+ {
+ __IO uint32_t PCONR;
+ stc_adtim_pconr_field_t PCONR_f;
+ };
+ union
+ {
+ __IO uint32_t BCONR;
+ stc_adtim_bconr_field_t BCONR_f;
+ };
+ union
+ {
+ __IO uint32_t DCONR;
+ stc_adtim_dconr_field_t DCONR_f;
+ };
+ uint8_t RESERVED16[4];
+ union
+ {
+ __IO uint32_t FCONR;
+ stc_adtim_fconr_field_t FCONR_f;
+ };
+ union
+ {
+ __IO uint32_t VPERR;
+ stc_adtim_vperr_field_t VPERR_f;
+ };
+ union
+ {
+ __IO uint32_t STFLR;
+ stc_adtim_stflr_field_t STFLR_f;
+ };
+ union
+ {
+ __IO uint32_t HSTAR;
+ stc_adtim_hstar_field_t HSTAR_f;
+ };
+ union
+ {
+ __IO uint32_t HSTPR;
+ stc_adtim_hstpr_field_t HSTPR_f;
+ };
+ union
+ {
+ __IO uint32_t HCELR;
+ stc_adtim_hcelr_field_t HCELR_f;
+ };
+ union
+ {
+ __IO uint32_t HCPAR;
+ stc_adtim_hcpar_field_t HCPAR_f;
+ };
+ union
+ {
+ __IO uint32_t HCPBR;
+ stc_adtim_hcpbr_field_t HCPBR_f;
+ };
+ union
+ {
+ __IO uint32_t HCUPR;
+ stc_adtim_hcupr_field_t HCUPR_f;
+ };
+ union
+ {
+ __IO uint32_t HCDOR;
+ stc_adtim_hcdor_field_t HCDOR_f;
+ };
+ uint8_t RESERVED26[112];
+ union
+ {
+ __IO uint32_t IFR;
+ stc_adtim_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_adtim_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t CR;
+ stc_adtim_cr_field_t CR_f;
+ };
+ uint8_t RESERVED29[4];
+ union
+ {
+ __IO uint32_t AOSSR;
+ stc_adtim_aossr_field_t AOSSR_f;
+ };
+ union
+ {
+ __IO uint32_t AOSCL;
+ stc_adtim_aoscl_field_t AOSCL_f;
+ };
+ union
+ {
+ __IO uint32_t PTBKS;
+ stc_adtim_ptbks_field_t PTBKS_f;
+ };
+ union
+ {
+ __IO uint32_t TTRIG;
+ stc_adtim_ttrig_field_t TTRIG_f;
+ };
+ union
+ {
+ __IO uint32_t ITRIG;
+ stc_adtim_itrig_field_t ITRIG_f;
+ };
+ union
+ {
+ __IO uint32_t PTBKP;
+ stc_adtim_ptbkp_field_t PTBKP_f;
+ };
+ uint8_t RESERVED35[716];
+ union
+ {
+ __IO uint32_t SSTAR;
+ stc_adtim_sstar_field_t SSTAR_f;
+ };
+ union
+ {
+ __IO uint32_t SSTPR;
+ stc_adtim_sstpr_field_t SSTPR_f;
+ };
+ union
+ {
+ __IO uint32_t SCLRR;
+ stc_adtim_sclrr_field_t SCLRR_f;
+ };
+}M0P_ADTIM_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CR;
+ stc_aes_cr_field_t CR_f;
+ };
+ uint8_t RESERVED1[12];
+ union
+ {
+ __IO uint32_t DATA0;
+ stc_aes_data0_field_t DATA0_f;
+ };
+ union
+ {
+ __IO uint32_t DATA1;
+ stc_aes_data1_field_t DATA1_f;
+ };
+ union
+ {
+ __IO uint32_t DATA2;
+ stc_aes_data2_field_t DATA2_f;
+ };
+ union
+ {
+ __IO uint32_t DATA3;
+ stc_aes_data3_field_t DATA3_f;
+ };
+ union
+ {
+ __IO uint32_t KEY0;
+ stc_aes_key0_field_t KEY0_f;
+ };
+ union
+ {
+ __IO uint32_t KEY1;
+ stc_aes_key1_field_t KEY1_f;
+ };
+ union
+ {
+ __IO uint32_t KEY2;
+ stc_aes_key2_field_t KEY2_f;
+ };
+ union
+ {
+ __IO uint32_t KEY3;
+ stc_aes_key3_field_t KEY3_f;
+ };
+ union
+ {
+ __IO uint32_t KEY4;
+ stc_aes_key4_field_t KEY4_f;
+ };
+ union
+ {
+ __IO uint32_t KEY5;
+ stc_aes_key5_field_t KEY5_f;
+ };
+ union
+ {
+ __IO uint32_t KEY6;
+ stc_aes_key6_field_t KEY6_f;
+ };
+ union
+ {
+ __IO uint32_t KEY7;
+ stc_aes_key7_field_t KEY7_f;
+ };
+}M0P_AES_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CR;
+ stc_bgr_cr_field_t CR_f;
+ };
+}M0P_BGR_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CR;
+ stc_clk_trim_cr_field_t CR_f;
+ };
+ union
+ {
+ __IO uint32_t REFCON;
+ stc_clk_trim_refcon_field_t REFCON_f;
+ };
+ union
+ {
+ __IO uint32_t REFCNT;
+ stc_clk_trim_refcnt_field_t REFCNT_f;
+ };
+ union
+ {
+ __IO uint32_t CALCNT;
+ stc_clk_trim_calcnt_field_t CALCNT_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_clk_trim_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_clk_trim_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t CALCON;
+ stc_clk_trim_calcon_field_t CALCON_f;
+ };
+}M0P_CLK_TRIM_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CR;
+ stc_crc_cr_field_t CR_f;
+ };
+ union
+ {
+ __IO uint32_t RESULT;
+ stc_crc_result_field_t RESULT_f;
+ };
+ uint8_t RESERVED2[120];
+ union
+ {
+ __IO uint32_t DATA;
+ stc_crc_data_field_t DATA_f;
+ };
+}M0P_CRC_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CR0;
+ stc_dac_cr0_field_t CR0_f;
+ };
+ union
+ {
+ __IO uint32_t SWTRIGR;
+ stc_dac_swtrigr_field_t SWTRIGR_f;
+ };
+ union
+ {
+ __IO uint32_t DHR12R0;
+ stc_dac_dhr12r0_field_t DHR12R0_f;
+ };
+ union
+ {
+ __IO uint32_t DHR12L0;
+ stc_dac_dhr12l0_field_t DHR12L0_f;
+ };
+ union
+ {
+ __IO uint32_t DHR8R0;
+ stc_dac_dhr8r0_field_t DHR8R0_f;
+ };
+ uint8_t RESERVED5[24];
+ union
+ {
+ __IO uint32_t DOR0;
+ stc_dac_dor0_field_t DOR0_f;
+ };
+ uint8_t RESERVED6[4];
+ union
+ {
+ __IO uint32_t SR;
+ stc_dac_sr_field_t SR_f;
+ };
+ union
+ {
+ __IO uint32_t ETRS;
+ stc_dac_etrs_field_t ETRS_f;
+ };
+}M0P_DAC_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t DEBUG_ACTIVE;
+ stc_debug_active_field_t DEBUG_ACTIVE_f;
+ };
+}M0P_DEBUG_ACTIVE_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CONF;
+ stc_dmac_conf_field_t CONF_f;
+ };
+ uint8_t RESERVED1[12];
+ union
+ {
+ __IO uint32_t CONFA0;
+ stc_dmac_confa0_field_t CONFA0_f;
+ };
+ union
+ {
+ __IO uint32_t CONFB0;
+ stc_dmac_confb0_field_t CONFB0_f;
+ };
+ union
+ {
+ __IO uint32_t SRCADR0;
+ stc_dmac_srcadr0_field_t SRCADR0_f;
+ };
+ union
+ {
+ __IO uint32_t DSTADR0;
+ stc_dmac_dstadr0_field_t DSTADR0_f;
+ };
+ union
+ {
+ __IO uint32_t CONFA1;
+ stc_dmac_confa1_field_t CONFA1_f;
+ };
+ union
+ {
+ __IO uint32_t CONFB1;
+ stc_dmac_confb1_field_t CONFB1_f;
+ };
+ union
+ {
+ __IO uint32_t SRCADR1;
+ stc_dmac_srcadr1_field_t SRCADR1_f;
+ };
+ union
+ {
+ __IO uint32_t DSTADR1;
+ stc_dmac_dstadr1_field_t DSTADR1_f;
+ };
+}M0P_DMAC_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t TNVS;
+ stc_flash_tnvs_field_t TNVS_f;
+ };
+ union
+ {
+ __IO uint32_t TPGS;
+ stc_flash_tpgs_field_t TPGS_f;
+ };
+ union
+ {
+ __IO uint32_t TPROG;
+ stc_flash_tprog_field_t TPROG_f;
+ };
+ union
+ {
+ __IO uint32_t TSERASE;
+ stc_flash_tserase_field_t TSERASE_f;
+ };
+ union
+ {
+ __IO uint32_t TMERASE;
+ stc_flash_tmerase_field_t TMERASE_f;
+ };
+ union
+ {
+ __IO uint32_t TPRCV;
+ stc_flash_tprcv_field_t TPRCV_f;
+ };
+ union
+ {
+ __IO uint32_t TSRCV;
+ stc_flash_tsrcv_field_t TSRCV_f;
+ };
+ union
+ {
+ __IO uint32_t TMRCV;
+ stc_flash_tmrcv_field_t TMRCV_f;
+ };
+ union
+ {
+ __IO uint32_t CR;
+ stc_flash_cr_field_t CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_flash_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_flash_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t BYPASS;
+ stc_flash_bypass_field_t BYPASS_f;
+ };
+ union
+ {
+ __IO uint32_t SLOCK0;
+ stc_flash_slock0_field_t SLOCK0_f;
+ };
+ union
+ {
+ __IO uint32_t SLOCK1;
+ stc_flash_slock1_field_t SLOCK1_f;
+ };
+}M0P_FLASH_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t PA00_SEL;
+ stc_gpio_pa00_sel_field_t PA00_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA01_SEL;
+ stc_gpio_pa01_sel_field_t PA01_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA02_SEL;
+ stc_gpio_pa02_sel_field_t PA02_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA03_SEL;
+ stc_gpio_pa03_sel_field_t PA03_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA04_SEL;
+ stc_gpio_pa04_sel_field_t PA04_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA05_SEL;
+ stc_gpio_pa05_sel_field_t PA05_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA06_SEL;
+ stc_gpio_pa06_sel_field_t PA06_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA07_SEL;
+ stc_gpio_pa07_sel_field_t PA07_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA08_SEL;
+ stc_gpio_pa08_sel_field_t PA08_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA09_SEL;
+ stc_gpio_pa09_sel_field_t PA09_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA10_SEL;
+ stc_gpio_pa10_sel_field_t PA10_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA11_SEL;
+ stc_gpio_pa11_sel_field_t PA11_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA12_SEL;
+ stc_gpio_pa12_sel_field_t PA12_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA13_SEL;
+ stc_gpio_pa13_sel_field_t PA13_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA14_SEL;
+ stc_gpio_pa14_sel_field_t PA14_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PA15_SEL;
+ stc_gpio_pa15_sel_field_t PA15_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB00_SEL;
+ stc_gpio_pb00_sel_field_t PB00_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB01_SEL;
+ stc_gpio_pb01_sel_field_t PB01_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB02_SEL;
+ stc_gpio_pb02_sel_field_t PB02_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB03_SEL;
+ stc_gpio_pb03_sel_field_t PB03_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB04_SEL;
+ stc_gpio_pb04_sel_field_t PB04_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB05_SEL;
+ stc_gpio_pb05_sel_field_t PB05_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB06_SEL;
+ stc_gpio_pb06_sel_field_t PB06_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB07_SEL;
+ stc_gpio_pb07_sel_field_t PB07_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB08_SEL;
+ stc_gpio_pb08_sel_field_t PB08_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB09_SEL;
+ stc_gpio_pb09_sel_field_t PB09_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB10_SEL;
+ stc_gpio_pb10_sel_field_t PB10_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB11_SEL;
+ stc_gpio_pb11_sel_field_t PB11_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB12_SEL;
+ stc_gpio_pb12_sel_field_t PB12_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB13_SEL;
+ stc_gpio_pb13_sel_field_t PB13_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB14_SEL;
+ stc_gpio_pb14_sel_field_t PB14_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PB15_SEL;
+ stc_gpio_pb15_sel_field_t PB15_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC00_SEL;
+ stc_gpio_pc00_sel_field_t PC00_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC01_SEL;
+ stc_gpio_pc01_sel_field_t PC01_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC02_SEL;
+ stc_gpio_pc02_sel_field_t PC02_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC03_SEL;
+ stc_gpio_pc03_sel_field_t PC03_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC04_SEL;
+ stc_gpio_pc04_sel_field_t PC04_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC05_SEL;
+ stc_gpio_pc05_sel_field_t PC05_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC06_SEL;
+ stc_gpio_pc06_sel_field_t PC06_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC07_SEL;
+ stc_gpio_pc07_sel_field_t PC07_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC08_SEL;
+ stc_gpio_pc08_sel_field_t PC08_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC09_SEL;
+ stc_gpio_pc09_sel_field_t PC09_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC10_SEL;
+ stc_gpio_pc10_sel_field_t PC10_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC11_SEL;
+ stc_gpio_pc11_sel_field_t PC11_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC12_SEL;
+ stc_gpio_pc12_sel_field_t PC12_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC13_SEL;
+ stc_gpio_pc13_sel_field_t PC13_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC14_SEL;
+ stc_gpio_pc14_sel_field_t PC14_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PC15_SEL;
+ stc_gpio_pc15_sel_field_t PC15_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD00_SEL;
+ stc_gpio_pd00_sel_field_t PD00_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD01_SEL;
+ stc_gpio_pd01_sel_field_t PD01_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD02_SEL;
+ stc_gpio_pd02_sel_field_t PD02_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD03_SEL;
+ stc_gpio_pd03_sel_field_t PD03_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD04_SEL;
+ stc_gpio_pd04_sel_field_t PD04_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD05_SEL;
+ stc_gpio_pd05_sel_field_t PD05_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD06_SEL;
+ stc_gpio_pd06_sel_field_t PD06_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD07_SEL;
+ stc_gpio_pd07_sel_field_t PD07_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD08_SEL;
+ stc_gpio_pd08_sel_field_t PD08_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD09_SEL;
+ stc_gpio_pd09_sel_field_t PD09_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD10_SEL;
+ stc_gpio_pd10_sel_field_t PD10_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD11_SEL;
+ stc_gpio_pd11_sel_field_t PD11_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD12_SEL;
+ stc_gpio_pd12_sel_field_t PD12_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD13_SEL;
+ stc_gpio_pd13_sel_field_t PD13_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD14_SEL;
+ stc_gpio_pd14_sel_field_t PD14_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PD15_SEL;
+ stc_gpio_pd15_sel_field_t PD15_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PADIR;
+ stc_gpio_padir_field_t PADIR_f;
+ };
+ union
+ {
+ __IO uint32_t PAIN;
+ stc_gpio_pain_field_t PAIN_f;
+ };
+ union
+ {
+ __IO uint32_t PAOUT;
+ stc_gpio_paout_field_t PAOUT_f;
+ };
+ union
+ {
+ __IO uint32_t PAADS;
+ stc_gpio_paads_field_t PAADS_f;
+ };
+ union
+ {
+ __IO uint32_t PABSET;
+ stc_gpio_pabset_field_t PABSET_f;
+ };
+ union
+ {
+ __IO uint32_t PABCLR;
+ stc_gpio_pabclr_field_t PABCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PABSETCLR;
+ stc_gpio_pabsetclr_field_t PABSETCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PADR;
+ stc_gpio_padr_field_t PADR_f;
+ };
+ union
+ {
+ __IO uint32_t PAPU;
+ stc_gpio_papu_field_t PAPU_f;
+ };
+ union
+ {
+ __IO uint32_t PAPD;
+ stc_gpio_papd_field_t PAPD_f;
+ };
+ uint8_t RESERVED74[4];
+ union
+ {
+ __IO uint32_t PAOD;
+ stc_gpio_paod_field_t PAOD_f;
+ };
+ union
+ {
+ __IO uint32_t PAHIE;
+ stc_gpio_pahie_field_t PAHIE_f;
+ };
+ union
+ {
+ __IO uint32_t PALIE;
+ stc_gpio_palie_field_t PALIE_f;
+ };
+ union
+ {
+ __IO uint32_t PARIE;
+ stc_gpio_parie_field_t PARIE_f;
+ };
+ union
+ {
+ __IO uint32_t PAFIE;
+ stc_gpio_pafie_field_t PAFIE_f;
+ };
+ union
+ {
+ __IO uint32_t PBDIR;
+ stc_gpio_pbdir_field_t PBDIR_f;
+ };
+ union
+ {
+ __IO uint32_t PBIN;
+ stc_gpio_pbin_field_t PBIN_f;
+ };
+ union
+ {
+ __IO uint32_t PBOUT;
+ stc_gpio_pbout_field_t PBOUT_f;
+ };
+ union
+ {
+ __IO uint32_t PBADS;
+ stc_gpio_pbads_field_t PBADS_f;
+ };
+ union
+ {
+ __IO uint32_t PBBSET;
+ stc_gpio_pbbset_field_t PBBSET_f;
+ };
+ union
+ {
+ __IO uint32_t PBBCLR;
+ stc_gpio_pbbclr_field_t PBBCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PBBSETCLR;
+ stc_gpio_pbbsetclr_field_t PBBSETCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PBDR;
+ stc_gpio_pbdr_field_t PBDR_f;
+ };
+ union
+ {
+ __IO uint32_t PBPU;
+ stc_gpio_pbpu_field_t PBPU_f;
+ };
+ union
+ {
+ __IO uint32_t PBPD;
+ stc_gpio_pbpd_field_t PBPD_f;
+ };
+ uint8_t RESERVED89[4];
+ union
+ {
+ __IO uint32_t PBOD;
+ stc_gpio_pbod_field_t PBOD_f;
+ };
+ union
+ {
+ __IO uint32_t PBHIE;
+ stc_gpio_pbhie_field_t PBHIE_f;
+ };
+ union
+ {
+ __IO uint32_t PBLIE;
+ stc_gpio_pblie_field_t PBLIE_f;
+ };
+ union
+ {
+ __IO uint32_t PBRIE;
+ stc_gpio_pbrie_field_t PBRIE_f;
+ };
+ union
+ {
+ __IO uint32_t PBFIE;
+ stc_gpio_pbfie_field_t PBFIE_f;
+ };
+ union
+ {
+ __IO uint32_t PCDIR;
+ stc_gpio_pcdir_field_t PCDIR_f;
+ };
+ union
+ {
+ __IO uint32_t PCIN;
+ stc_gpio_pcin_field_t PCIN_f;
+ };
+ union
+ {
+ __IO uint32_t PCOUT;
+ stc_gpio_pcout_field_t PCOUT_f;
+ };
+ union
+ {
+ __IO uint32_t PCADS;
+ stc_gpio_pcads_field_t PCADS_f;
+ };
+ union
+ {
+ __IO uint32_t PCBSET;
+ stc_gpio_pcbset_field_t PCBSET_f;
+ };
+ union
+ {
+ __IO uint32_t PCBCLR;
+ stc_gpio_pcbclr_field_t PCBCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PCBSETCLR;
+ stc_gpio_pcbsetclr_field_t PCBSETCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PCDR;
+ stc_gpio_pcdr_field_t PCDR_f;
+ };
+ union
+ {
+ __IO uint32_t PCPU;
+ stc_gpio_pcpu_field_t PCPU_f;
+ };
+ union
+ {
+ __IO uint32_t PCPD;
+ stc_gpio_pcpd_field_t PCPD_f;
+ };
+ uint8_t RESERVED104[4];
+ union
+ {
+ __IO uint32_t PCOD;
+ stc_gpio_pcod_field_t PCOD_f;
+ };
+ union
+ {
+ __IO uint32_t PCHIE;
+ stc_gpio_pchie_field_t PCHIE_f;
+ };
+ union
+ {
+ __IO uint32_t PCLIE;
+ stc_gpio_pclie_field_t PCLIE_f;
+ };
+ union
+ {
+ __IO uint32_t PCRIE;
+ stc_gpio_pcrie_field_t PCRIE_f;
+ };
+ union
+ {
+ __IO uint32_t PCFIE;
+ stc_gpio_pcfie_field_t PCFIE_f;
+ };
+ union
+ {
+ __IO uint32_t PDDIR;
+ stc_gpio_pddir_field_t PDDIR_f;
+ };
+ union
+ {
+ __IO uint32_t PDIN;
+ stc_gpio_pdin_field_t PDIN_f;
+ };
+ union
+ {
+ __IO uint32_t PDOUT;
+ stc_gpio_pdout_field_t PDOUT_f;
+ };
+ union
+ {
+ __IO uint32_t PDADS;
+ stc_gpio_pdads_field_t PDADS_f;
+ };
+ union
+ {
+ __IO uint32_t PDBSET;
+ stc_gpio_pdbset_field_t PDBSET_f;
+ };
+ union
+ {
+ __IO uint32_t PDBCLR;
+ stc_gpio_pdbclr_field_t PDBCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PDBSETCLR;
+ stc_gpio_pdbsetclr_field_t PDBSETCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PDDR;
+ stc_gpio_pddr_field_t PDDR_f;
+ };
+ union
+ {
+ __IO uint32_t PDPU;
+ stc_gpio_pdpu_field_t PDPU_f;
+ };
+ union
+ {
+ __IO uint32_t PDPD;
+ stc_gpio_pdpd_field_t PDPD_f;
+ };
+ uint8_t RESERVED119[4];
+ union
+ {
+ __IO uint32_t PDOD;
+ stc_gpio_pdod_field_t PDOD_f;
+ };
+ union
+ {
+ __IO uint32_t PDHIE;
+ stc_gpio_pdhie_field_t PDHIE_f;
+ };
+ union
+ {
+ __IO uint32_t PDLIE;
+ stc_gpio_pdlie_field_t PDLIE_f;
+ };
+ union
+ {
+ __IO uint32_t PDRIE;
+ stc_gpio_pdrie_field_t PDRIE_f;
+ };
+ union
+ {
+ __IO uint32_t PDFIE;
+ stc_gpio_pdfie_field_t PDFIE_f;
+ };
+ union
+ {
+ __IO uint32_t PA_STAT;
+ stc_gpio_pa_stat_field_t PA_STAT_f;
+ };
+ uint8_t RESERVED125[12];
+ union
+ {
+ __IO uint32_t PA_ICLR;
+ stc_gpio_pa_iclr_field_t PA_ICLR_f;
+ };
+ uint8_t RESERVED126[44];
+ union
+ {
+ __IO uint32_t PB_STAT;
+ stc_gpio_pb_stat_field_t PB_STAT_f;
+ };
+ uint8_t RESERVED127[12];
+ union
+ {
+ __IO uint32_t PB_ICLR;
+ stc_gpio_pb_iclr_field_t PB_ICLR_f;
+ };
+ uint8_t RESERVED128[44];
+ union
+ {
+ __IO uint32_t PC_STAT;
+ stc_gpio_pc_stat_field_t PC_STAT_f;
+ };
+ uint8_t RESERVED129[12];
+ union
+ {
+ __IO uint32_t PC_ICLR;
+ stc_gpio_pc_iclr_field_t PC_ICLR_f;
+ };
+ uint8_t RESERVED130[44];
+ union
+ {
+ __IO uint32_t PD_STAT;
+ stc_gpio_pd_stat_field_t PD_STAT_f;
+ };
+ uint8_t RESERVED131[12];
+ union
+ {
+ __IO uint32_t PD_ICLR;
+ stc_gpio_pd_iclr_field_t PD_ICLR_f;
+ };
+ uint8_t RESERVED132[44];
+ union
+ {
+ __IO uint32_t CTRL0;
+ stc_gpio_ctrl0_field_t CTRL0_f;
+ };
+ union
+ {
+ __IO uint32_t CTRL1;
+ stc_gpio_ctrl1_field_t CTRL1_f;
+ };
+ union
+ {
+ __IO uint32_t CTRL2;
+ stc_gpio_ctrl2_field_t CTRL2_f;
+ };
+ union
+ {
+ __IO uint32_t TIMGS;
+ stc_gpio_timgs_field_t TIMGS_f;
+ };
+ union
+ {
+ __IO uint32_t TIMES;
+ stc_gpio_times_field_t TIMES_f;
+ };
+ union
+ {
+ __IO uint32_t TIMCPS;
+ stc_gpio_timcps_field_t TIMCPS_f;
+ };
+ union
+ {
+ __IO uint32_t PCAS;
+ stc_gpio_pcas_field_t PCAS_f;
+ };
+ union
+ {
+ __IO uint32_t PCNT;
+ stc_gpio_pcnt_field_t PCNT_f;
+ };
+ uint8_t RESERVED140[3296];
+ union
+ {
+ __IO uint32_t PE00_SEL;
+ stc_gpio_pe00_sel_field_t PE00_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE01_SEL;
+ stc_gpio_pe01_sel_field_t PE01_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE02_SEL;
+ stc_gpio_pe02_sel_field_t PE02_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE03_SEL;
+ stc_gpio_pe03_sel_field_t PE03_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE04_SEL;
+ stc_gpio_pe04_sel_field_t PE04_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE05_SEL;
+ stc_gpio_pe05_sel_field_t PE05_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE06_SEL;
+ stc_gpio_pe06_sel_field_t PE06_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE07_SEL;
+ stc_gpio_pe07_sel_field_t PE07_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE08_SEL;
+ stc_gpio_pe08_sel_field_t PE08_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE09_SEL;
+ stc_gpio_pe09_sel_field_t PE09_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE10_SEL;
+ stc_gpio_pe10_sel_field_t PE10_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE11_SEL;
+ stc_gpio_pe11_sel_field_t PE11_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE12_SEL;
+ stc_gpio_pe12_sel_field_t PE12_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE13_SEL;
+ stc_gpio_pe13_sel_field_t PE13_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE14_SEL;
+ stc_gpio_pe14_sel_field_t PE14_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PE15_SEL;
+ stc_gpio_pe15_sel_field_t PE15_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF00_SEL;
+ stc_gpio_pf00_sel_field_t PF00_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF01_SEL;
+ stc_gpio_pf01_sel_field_t PF01_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF02_SEL;
+ stc_gpio_pf02_sel_field_t PF02_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF03_SEL;
+ stc_gpio_pf03_sel_field_t PF03_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF04_SEL;
+ stc_gpio_pf04_sel_field_t PF04_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF05_SEL;
+ stc_gpio_pf05_sel_field_t PF05_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF06_SEL;
+ stc_gpio_pf06_sel_field_t PF06_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF07_SEL;
+ stc_gpio_pf07_sel_field_t PF07_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF08_SEL;
+ stc_gpio_pf08_sel_field_t PF08_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF09_SEL;
+ stc_gpio_pf09_sel_field_t PF09_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF10_SEL;
+ stc_gpio_pf10_sel_field_t PF10_SEL_f;
+ };
+ union
+ {
+ __IO uint32_t PF11_SEL;
+ stc_gpio_pf11_sel_field_t PF11_SEL_f;
+ };
+ uint8_t RESERVED168[144];
+ union
+ {
+ __IO uint32_t PEDIR;
+ stc_gpio_pedir_field_t PEDIR_f;
+ };
+ union
+ {
+ __IO uint32_t PEIN;
+ stc_gpio_pein_field_t PEIN_f;
+ };
+ union
+ {
+ __IO uint32_t PEOUT;
+ stc_gpio_peout_field_t PEOUT_f;
+ };
+ union
+ {
+ __IO uint32_t PEADS;
+ stc_gpio_peads_field_t PEADS_f;
+ };
+ union
+ {
+ __IO uint32_t PEBSET;
+ stc_gpio_pebset_field_t PEBSET_f;
+ };
+ union
+ {
+ __IO uint32_t PEBCLR;
+ stc_gpio_pebclr_field_t PEBCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PEBSETCLR;
+ stc_gpio_pebsetclr_field_t PEBSETCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PEDR;
+ stc_gpio_pedr_field_t PEDR_f;
+ };
+ union
+ {
+ __IO uint32_t PEPU;
+ stc_gpio_pepu_field_t PEPU_f;
+ };
+ union
+ {
+ __IO uint32_t PEPD;
+ stc_gpio_pepd_field_t PEPD_f;
+ };
+ uint8_t RESERVED178[4];
+ union
+ {
+ __IO uint32_t PEOD;
+ stc_gpio_peod_field_t PEOD_f;
+ };
+ union
+ {
+ __IO uint32_t PEHIE;
+ stc_gpio_pehie_field_t PEHIE_f;
+ };
+ union
+ {
+ __IO uint32_t PELIE;
+ stc_gpio_pelie_field_t PELIE_f;
+ };
+ union
+ {
+ __IO uint32_t PERIE;
+ stc_gpio_perie_field_t PERIE_f;
+ };
+ union
+ {
+ __IO uint32_t PEFIE;
+ stc_gpio_pefie_field_t PEFIE_f;
+ };
+ union
+ {
+ __IO uint32_t PFDIR;
+ stc_gpio_pfdir_field_t PFDIR_f;
+ };
+ union
+ {
+ __IO uint32_t PFIN;
+ stc_gpio_pfin_field_t PFIN_f;
+ };
+ union
+ {
+ __IO uint32_t PFOUT;
+ stc_gpio_pfout_field_t PFOUT_f;
+ };
+ union
+ {
+ __IO uint32_t PFADS;
+ stc_gpio_pfads_field_t PFADS_f;
+ };
+ union
+ {
+ __IO uint32_t PFBSET;
+ stc_gpio_pfbset_field_t PFBSET_f;
+ };
+ union
+ {
+ __IO uint32_t PFBCLR;
+ stc_gpio_pfbclr_field_t PFBCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PFBSETCLR;
+ stc_gpio_pfbsetclr_field_t PFBSETCLR_f;
+ };
+ union
+ {
+ __IO uint32_t PFDR;
+ stc_gpio_pfdr_field_t PFDR_f;
+ };
+ union
+ {
+ __IO uint32_t PFPU;
+ stc_gpio_pfpu_field_t PFPU_f;
+ };
+ union
+ {
+ __IO uint32_t PFPD;
+ stc_gpio_pfpd_field_t PFPD_f;
+ };
+ uint8_t RESERVED193[4];
+ union
+ {
+ __IO uint32_t PFOD;
+ stc_gpio_pfod_field_t PFOD_f;
+ };
+ union
+ {
+ __IO uint32_t PFHIE;
+ stc_gpio_pfhie_field_t PFHIE_f;
+ };
+ union
+ {
+ __IO uint32_t PFLIE;
+ stc_gpio_pflie_field_t PFLIE_f;
+ };
+ union
+ {
+ __IO uint32_t PFRIE;
+ stc_gpio_pfrie_field_t PFRIE_f;
+ };
+ union
+ {
+ __IO uint32_t PFFIE;
+ stc_gpio_pffie_field_t PFFIE_f;
+ };
+ uint8_t RESERVED198[128];
+ union
+ {
+ __IO uint32_t PE_STAT;
+ stc_gpio_pe_stat_field_t PE_STAT_f;
+ };
+ uint8_t RESERVED199[12];
+ union
+ {
+ __IO uint32_t PE_ICLR;
+ stc_gpio_pe_iclr_field_t PE_ICLR_f;
+ };
+ uint8_t RESERVED200[44];
+ union
+ {
+ __IO uint32_t PF_STAT;
+ stc_gpio_pf_stat_field_t PF_STAT_f;
+ };
+ uint8_t RESERVED201[12];
+ union
+ {
+ __IO uint32_t PF_ICLR;
+ stc_gpio_pf_iclr_field_t PF_ICLR_f;
+ };
+}M0P_GPIO_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t TMRUN;
+ stc_i2c_tmrun_field_t TMRUN_f;
+ };
+ union
+ {
+ __IO uint32_t TM;
+ stc_i2c_tm_field_t TM_f;
+ };
+ union
+ {
+ __IO uint32_t CR;
+ stc_i2c_cr_field_t CR_f;
+ };
+ union
+ {
+ __IO uint32_t DATA;
+ stc_i2c_data_field_t DATA_f;
+ };
+ union
+ {
+ __IO uint32_t ADDR;
+ stc_i2c_addr_field_t ADDR_f;
+ };
+ union
+ {
+ __IO uint32_t STAT;
+ stc_i2c_stat_field_t STAT_f;
+ };
+}M0P_I2C_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CR0;
+ stc_lcd_cr0_field_t CR0_f;
+ };
+ union
+ {
+ __IO uint32_t CR1;
+ stc_lcd_cr1_field_t CR1_f;
+ };
+ union
+ {
+ __IO uint32_t INTCLR;
+ stc_lcd_intclr_field_t INTCLR_f;
+ };
+ union
+ {
+ __IO uint32_t POEN0;
+ stc_lcd_poen0_field_t POEN0_f;
+ };
+ union
+ {
+ __IO uint32_t POEN1;
+ stc_lcd_poen1_field_t POEN1_f;
+ };
+ uint8_t RESERVED5[44];
+ union
+ {
+ __IO uint32_t RAM0;
+ stc_lcd_ram0_field_t RAM0_f;
+ };
+ union
+ {
+ __IO uint32_t RAM1;
+ stc_lcd_ram1_field_t RAM1_f;
+ };
+ union
+ {
+ __IO uint32_t RAM2;
+ stc_lcd_ram2_field_t RAM2_f;
+ };
+ union
+ {
+ __IO uint32_t RAM3;
+ stc_lcd_ram3_field_t RAM3_f;
+ };
+ union
+ {
+ __IO uint32_t RAM4;
+ stc_lcd_ram4_field_t RAM4_f;
+ };
+ union
+ {
+ __IO uint32_t RAM5;
+ stc_lcd_ram5_field_t RAM5_f;
+ };
+ union
+ {
+ __IO uint32_t RAM6;
+ stc_lcd_ram6_field_t RAM6_f;
+ };
+ union
+ {
+ __IO uint32_t RAM7;
+ stc_lcd_ram7_field_t RAM7_f;
+ };
+ union
+ {
+ __IO uint32_t RAM8;
+ stc_lcd_ram8_field_t RAM8_f;
+ };
+ union
+ {
+ __IO uint32_t RAM9;
+ stc_lcd_ram9_field_t RAM9_f;
+ };
+ union
+ {
+ __IO uint32_t RAMA;
+ stc_lcd_rama_field_t RAMA_f;
+ };
+ union
+ {
+ __IO uint32_t RAMB;
+ stc_lcd_ramb_field_t RAMB_f;
+ };
+ union
+ {
+ __IO uint32_t RAMC;
+ stc_lcd_ramc_field_t RAMC_f;
+ };
+ union
+ {
+ __IO uint32_t RAMD;
+ stc_lcd_ramd_field_t RAMD_f;
+ };
+ union
+ {
+ __IO uint32_t RAME;
+ stc_lcd_rame_field_t RAME_f;
+ };
+ union
+ {
+ __IO uint32_t RAMF;
+ stc_lcd_ramf_field_t RAMF_f;
+ };
+}M0P_LCD_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CNT;
+ stc_lptimer_cnt_field_t CNT_f;
+ };
+ union
+ {
+ __IO uint32_t ARR;
+ stc_lptimer_arr_field_t ARR_f;
+ };
+ uint8_t RESERVED2[4];
+ union
+ {
+ __IO uint32_t CR;
+ stc_lptimer_cr_field_t CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_lptimer_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_lptimer_iclr_field_t ICLR_f;
+ };
+}M0P_LPTIMER_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t SBUF;
+ stc_lpuart_sbuf_field_t SBUF_f;
+ };
+ union
+ {
+ __IO uint32_t SCON;
+ stc_lpuart_scon_field_t SCON_f;
+ };
+ union
+ {
+ __IO uint32_t SADDR;
+ stc_lpuart_saddr_field_t SADDR_f;
+ };
+ union
+ {
+ __IO uint32_t SADEN;
+ stc_lpuart_saden_field_t SADEN_f;
+ };
+ union
+ {
+ __IO uint32_t ISR;
+ stc_lpuart_isr_field_t ISR_f;
+ };
+ union
+ {
+ __IO uint32_t ICR;
+ stc_lpuart_icr_field_t ICR_f;
+ };
+ union
+ {
+ __IO uint32_t SCNT;
+ stc_lpuart_scnt_field_t SCNT_f;
+ };
+}M0P_LPUART_TypeDef;
+
+typedef struct
+{
+ uint8_t RESERVED0[40];
+ union
+ {
+ __IO uint32_t CR;
+ stc_lvd_cr_field_t CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_lvd_ifr_field_t IFR_f;
+ };
+}M0P_LVD_TypeDef;
+
+typedef struct
+{
+ uint8_t RESERVED0[48];
+ union
+ {
+ __IO uint32_t CR0;
+ stc_opa_cr0_field_t CR0_f;
+ };
+ uint8_t RESERVED1[8];
+ union
+ {
+ __IO uint32_t CR1;
+ stc_opa_cr1_field_t CR1_f;
+ };
+}M0P_OPA_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CCON;
+ stc_pca_ccon_field_t CCON_f;
+ };
+ union
+ {
+ __IO uint32_t CMOD;
+ stc_pca_cmod_field_t CMOD_f;
+ };
+ union
+ {
+ __IO uint32_t CNT;
+ stc_pca_cnt_field_t CNT_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_pca_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t CCAPM0;
+ stc_pca_ccapm0_field_t CCAPM0_f;
+ };
+ union
+ {
+ __IO uint32_t CCAPM1;
+ stc_pca_ccapm1_field_t CCAPM1_f;
+ };
+ union
+ {
+ __IO uint32_t CCAPM2;
+ stc_pca_ccapm2_field_t CCAPM2_f;
+ };
+ union
+ {
+ __IO uint32_t CCAPM3;
+ stc_pca_ccapm3_field_t CCAPM3_f;
+ };
+ union
+ {
+ __IO uint32_t CCAPM4;
+ stc_pca_ccapm4_field_t CCAPM4_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP0H;
+ stc_pca_ccap0h_field_t CCAP0H_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP0L;
+ stc_pca_ccap0l_field_t CCAP0L_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP1H;
+ stc_pca_ccap1h_field_t CCAP1H_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP1L;
+ stc_pca_ccap1l_field_t CCAP1L_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP2H;
+ stc_pca_ccap2h_field_t CCAP2H_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP2L;
+ stc_pca_ccap2l_field_t CCAP2L_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP3H;
+ stc_pca_ccap3h_field_t CCAP3H_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP3L;
+ stc_pca_ccap3l_field_t CCAP3L_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP4H;
+ stc_pca_ccap4h_field_t CCAP4H_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP4L;
+ stc_pca_ccap4l_field_t CCAP4L_f;
+ };
+ union
+ {
+ __IO uint32_t CCAPO;
+ stc_pca_ccapo_field_t CCAPO_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP0;
+ stc_pca_ccap0_field_t CCAP0_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP1;
+ stc_pca_ccap1_field_t CCAP1_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP2;
+ stc_pca_ccap2_field_t CCAP2_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP3;
+ stc_pca_ccap3_field_t CCAP3_f;
+ };
+ union
+ {
+ __IO uint32_t CCAP4;
+ stc_pca_ccap4_field_t CCAP4_f;
+ };
+ union
+ {
+ __IO uint32_t CARR;
+ stc_pca_carr_field_t CARR_f;
+ };
+ union
+ {
+ __IO uint32_t EPWM;
+ stc_pca_epwm_field_t EPWM_f;
+ };
+}M0P_PCA_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t RUN;
+ stc_pcnt_run_field_t RUN_f;
+ };
+ union
+ {
+ __IO uint32_t CTRL;
+ stc_pcnt_ctrl_field_t CTRL_f;
+ };
+ union
+ {
+ __IO uint32_t FLT;
+ stc_pcnt_flt_field_t FLT_f;
+ };
+ union
+ {
+ __IO uint32_t TOCR;
+ stc_pcnt_tocr_field_t TOCR_f;
+ };
+ union
+ {
+ __IO uint32_t CMD;
+ stc_pcnt_cmd_field_t CMD_f;
+ };
+ union
+ {
+ __IO uint32_t SR1;
+ stc_pcnt_sr1_field_t SR1_f;
+ };
+ union
+ {
+ __IO uint32_t CNT;
+ stc_pcnt_cnt_field_t CNT_f;
+ };
+ union
+ {
+ __IO uint32_t TOP;
+ stc_pcnt_top_field_t TOP_f;
+ };
+ union
+ {
+ __IO uint32_t BUF;
+ stc_pcnt_buf_field_t BUF_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_pcnt_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICR;
+ stc_pcnt_icr_field_t ICR_f;
+ };
+ union
+ {
+ __IO uint32_t IEN;
+ stc_pcnt_ien_field_t IEN_f;
+ };
+ union
+ {
+ __IO uint32_t SR2;
+ stc_pcnt_sr2_field_t SR2_f;
+ };
+ union
+ {
+ __IO uint32_t DBG;
+ stc_pcnt_dbg_field_t DBG_f;
+ };
+}M0P_PCNT_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CR;
+ stc_ram_cr_field_t CR_f;
+ };
+ union
+ {
+ __IO uint32_t ERRADDR;
+ stc_ram_erraddr_field_t ERRADDR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_ram_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_ram_iclr_field_t ICLR_f;
+ };
+}M0P_RAM_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t RESET_FLAG;
+ stc_reset_flag_field_t RESET_FLAG_f;
+ };
+ uint8_t RESERVED1[8];
+ union
+ {
+ __IO uint32_t PERI_RESET0;
+ stc_reset_peri_reset0_field_t PERI_RESET0_f;
+ };
+ union
+ {
+ __IO uint32_t PERI_RESET1;
+ stc_reset_peri_reset1_field_t PERI_RESET1_f;
+ };
+}M0P_RESET_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CR0;
+ stc_rtc_cr0_field_t CR0_f;
+ };
+ union
+ {
+ __IO uint32_t CR1;
+ stc_rtc_cr1_field_t CR1_f;
+ };
+ union
+ {
+ __IO uint32_t SEC;
+ stc_rtc_sec_field_t SEC_f;
+ };
+ union
+ {
+ __IO uint32_t MIN;
+ stc_rtc_min_field_t MIN_f;
+ };
+ union
+ {
+ __IO uint32_t HOUR;
+ stc_rtc_hour_field_t HOUR_f;
+ };
+ union
+ {
+ __IO uint32_t WEEK;
+ stc_rtc_week_field_t WEEK_f;
+ };
+ union
+ {
+ __IO uint32_t DAY;
+ stc_rtc_day_field_t DAY_f;
+ };
+ union
+ {
+ __IO uint32_t MON;
+ stc_rtc_mon_field_t MON_f;
+ };
+ union
+ {
+ __IO uint32_t YEAR;
+ stc_rtc_year_field_t YEAR_f;
+ };
+ union
+ {
+ __IO uint32_t ALMMIN;
+ stc_rtc_almmin_field_t ALMMIN_f;
+ };
+ union
+ {
+ __IO uint32_t ALMHOUR;
+ stc_rtc_almhour_field_t ALMHOUR_f;
+ };
+ union
+ {
+ __IO uint32_t ALMWEEK;
+ stc_rtc_almweek_field_t ALMWEEK_f;
+ };
+ union
+ {
+ __IO uint32_t COMPEN;
+ stc_rtc_compen_field_t COMPEN_f;
+ };
+ union
+ {
+ __IO uint32_t ALMSEC;
+ stc_rtc_almsec_field_t ALMSEC_f;
+ };
+}M0P_RTC_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CR;
+ stc_spi_cr_field_t CR_f;
+ };
+ union
+ {
+ __IO uint32_t SSN;
+ stc_spi_ssn_field_t SSN_f;
+ };
+ union
+ {
+ __IO uint32_t STAT;
+ stc_spi_stat_field_t STAT_f;
+ };
+ union
+ {
+ __IO uint32_t DATA;
+ stc_spi_data_field_t DATA_f;
+ };
+ union
+ {
+ __IO uint32_t CR2;
+ stc_spi_cr2_field_t CR2_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_spi_iclr_field_t ICLR_f;
+ };
+}M0P_SPI_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t SYSCTRL0;
+ stc_sysctrl_sysctrl0_field_t SYSCTRL0_f;
+ };
+ union
+ {
+ __IO uint32_t SYSCTRL1;
+ stc_sysctrl_sysctrl1_field_t SYSCTRL1_f;
+ };
+ union
+ {
+ __IO uint32_t SYSCTRL2;
+ stc_sysctrl_sysctrl2_field_t SYSCTRL2_f;
+ };
+ union
+ {
+ __IO uint32_t RCH_CR;
+ stc_sysctrl_rch_cr_field_t RCH_CR_f;
+ };
+ union
+ {
+ __IO uint32_t XTH_CR;
+ stc_sysctrl_xth_cr_field_t XTH_CR_f;
+ };
+ union
+ {
+ __IO uint32_t RCL_CR;
+ stc_sysctrl_rcl_cr_field_t RCL_CR_f;
+ };
+ union
+ {
+ __IO uint32_t XTL_CR;
+ stc_sysctrl_xtl_cr_field_t XTL_CR_f;
+ };
+ uint8_t RESERVED7[4];
+ union
+ {
+ __IO uint32_t PERI_CLKEN0;
+ stc_sysctrl_peri_clken0_field_t PERI_CLKEN0_f;
+ };
+ union
+ {
+ __IO uint32_t PERI_CLKEN1;
+ stc_sysctrl_peri_clken1_field_t PERI_CLKEN1_f;
+ };
+ uint8_t RESERVED9[20];
+ union
+ {
+ __IO uint32_t PLL_CR;
+ stc_sysctrl_pll_cr_field_t PLL_CR_f;
+ };
+}M0P_SYSCTRL_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t ARR;
+ stc_tim0_mode0_arr_field_t ARR_f;
+ };
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim0_mode0_cnt_field_t CNT_f;
+ };
+ union
+ {
+ __IO uint32_t CNT32;
+ stc_tim0_mode0_cnt32_field_t CNT32_f;
+ };
+ union
+ {
+ __IO uint32_t M0CR;
+ stc_tim0_mode0_m0cr_field_t M0CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim0_mode0_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim0_mode0_iclr_field_t ICLR_f;
+ };
+ uint8_t RESERVED6[24];
+ union
+ {
+ __IO uint32_t DTR;
+ stc_tim0_mode0_dtr_field_t DTR_f;
+ };
+}M0P_TIM0_MODE0_TypeDef;
+
+typedef struct
+{
+ uint8_t RESERVED0[4];
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim0_mode1_cnt_field_t CNT_f;
+ };
+ uint8_t RESERVED1[4];
+ union
+ {
+ __IO uint32_t M1CR;
+ stc_tim0_mode1_m1cr_field_t M1CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim0_mode1_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim0_mode1_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t MSCR;
+ stc_tim0_mode1_mscr_field_t MSCR_f;
+ };
+ union
+ {
+ __IO uint32_t FLTR;
+ stc_tim0_mode1_fltr_field_t FLTR_f;
+ };
+ uint8_t RESERVED6[4];
+ union
+ {
+ __IO uint32_t CR0;
+ stc_tim0_mode1_cr0_field_t CR0_f;
+ };
+ uint8_t RESERVED7[20];
+ union
+ {
+ __IO uint32_t CCR0A;
+ stc_tim0_mode1_ccr0a_field_t CCR0A_f;
+ };
+}M0P_TIM0_MODE1_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t ARR;
+ stc_tim0_mode23_arr_field_t ARR_f;
+ };
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim0_mode23_cnt_field_t CNT_f;
+ };
+ uint8_t RESERVED2[4];
+ union
+ {
+ __IO uint32_t M23CR;
+ stc_tim0_mode23_m23cr_field_t M23CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim0_mode23_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim0_mode23_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t MSCR;
+ stc_tim0_mode23_mscr_field_t MSCR_f;
+ };
+ union
+ {
+ __IO uint32_t FLTR;
+ stc_tim0_mode23_fltr_field_t FLTR_f;
+ };
+ union
+ {
+ __IO uint32_t ADTR;
+ stc_tim0_mode23_adtr_field_t ADTR_f;
+ };
+ union
+ {
+ __IO uint32_t CRCH0;
+ stc_tim0_mode23_crch0_field_t CRCH0_f;
+ };
+ uint8_t RESERVED9[8];
+ union
+ {
+ __IO uint32_t DTR;
+ stc_tim0_mode23_dtr_field_t DTR_f;
+ };
+ union
+ {
+ __IO uint32_t RCR;
+ stc_tim0_mode23_rcr_field_t RCR_f;
+ };
+ union
+ {
+ __IO uint32_t ARRDM;
+ stc_tim0_mode23_arrdm_field_t ARRDM_f;
+ };
+ union
+ {
+ __IO uint32_t CCR0A;
+ stc_tim0_mode23_ccr0a_field_t CCR0A_f;
+ };
+ union
+ {
+ __IO uint32_t CCR0B;
+ stc_tim0_mode23_ccr0b_field_t CCR0B_f;
+ };
+}M0P_TIM0_MODE23_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t ARR;
+ stc_tim1_mode0_arr_field_t ARR_f;
+ };
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim1_mode0_cnt_field_t CNT_f;
+ };
+ union
+ {
+ __IO uint32_t CNT32;
+ stc_tim1_mode0_cnt32_field_t CNT32_f;
+ };
+ union
+ {
+ __IO uint32_t M0CR;
+ stc_tim1_mode0_m0cr_field_t M0CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim1_mode0_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim1_mode0_iclr_field_t ICLR_f;
+ };
+ uint8_t RESERVED6[24];
+ union
+ {
+ __IO uint32_t DTR;
+ stc_tim1_mode0_dtr_field_t DTR_f;
+ };
+}M0P_TIM1_MODE0_TypeDef;
+
+typedef struct
+{
+ uint8_t RESERVED0[4];
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim1_mode1_cnt_field_t CNT_f;
+ };
+ uint8_t RESERVED1[4];
+ union
+ {
+ __IO uint32_t M1CR;
+ stc_tim1_mode1_m1cr_field_t M1CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim1_mode1_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim1_mode1_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t MSCR;
+ stc_tim1_mode1_mscr_field_t MSCR_f;
+ };
+ union
+ {
+ __IO uint32_t FLTR;
+ stc_tim1_mode1_fltr_field_t FLTR_f;
+ };
+ uint8_t RESERVED6[4];
+ union
+ {
+ __IO uint32_t CR0;
+ stc_tim1_mode1_cr0_field_t CR0_f;
+ };
+ uint8_t RESERVED7[20];
+ union
+ {
+ __IO uint32_t CCR0A;
+ stc_tim1_mode1_ccr0a_field_t CCR0A_f;
+ };
+}M0P_TIM1_MODE1_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t ARR;
+ stc_tim1_mode23_arr_field_t ARR_f;
+ };
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim1_mode23_cnt_field_t CNT_f;
+ };
+ uint8_t RESERVED2[4];
+ union
+ {
+ __IO uint32_t M23CR;
+ stc_tim1_mode23_m23cr_field_t M23CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim1_mode23_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim1_mode23_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t MSCR;
+ stc_tim1_mode23_mscr_field_t MSCR_f;
+ };
+ union
+ {
+ __IO uint32_t FLTR;
+ stc_tim1_mode23_fltr_field_t FLTR_f;
+ };
+ union
+ {
+ __IO uint32_t ADTR;
+ stc_tim1_mode23_adtr_field_t ADTR_f;
+ };
+ union
+ {
+ __IO uint32_t CRCH0;
+ stc_tim1_mode23_crch0_field_t CRCH0_f;
+ };
+ uint8_t RESERVED9[8];
+ union
+ {
+ __IO uint32_t DTR;
+ stc_tim1_mode23_dtr_field_t DTR_f;
+ };
+ union
+ {
+ __IO uint32_t RCR;
+ stc_tim1_mode23_rcr_field_t RCR_f;
+ };
+ union
+ {
+ __IO uint32_t ARRDM;
+ stc_tim1_mode23_arrdm_field_t ARRDM_f;
+ };
+ union
+ {
+ __IO uint32_t CCR0A;
+ stc_tim1_mode23_ccr0a_field_t CCR0A_f;
+ };
+ union
+ {
+ __IO uint32_t CCR0B;
+ stc_tim1_mode23_ccr0b_field_t CCR0B_f;
+ };
+}M0P_TIM1_MODE23_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t ARR;
+ stc_tim2_mode0_arr_field_t ARR_f;
+ };
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim2_mode0_cnt_field_t CNT_f;
+ };
+ union
+ {
+ __IO uint32_t CNT32;
+ stc_tim2_mode0_cnt32_field_t CNT32_f;
+ };
+ union
+ {
+ __IO uint32_t M0CR;
+ stc_tim2_mode0_m0cr_field_t M0CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim2_mode0_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim2_mode0_iclr_field_t ICLR_f;
+ };
+ uint8_t RESERVED6[24];
+ union
+ {
+ __IO uint32_t DTR;
+ stc_tim2_mode0_dtr_field_t DTR_f;
+ };
+}M0P_TIM2_MODE0_TypeDef;
+
+typedef struct
+{
+ uint8_t RESERVED0[4];
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim2_mode1_cnt_field_t CNT_f;
+ };
+ uint8_t RESERVED1[4];
+ union
+ {
+ __IO uint32_t M1CR;
+ stc_tim2_mode1_m1cr_field_t M1CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim2_mode1_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim2_mode1_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t MSCR;
+ stc_tim2_mode1_mscr_field_t MSCR_f;
+ };
+ union
+ {
+ __IO uint32_t FLTR;
+ stc_tim2_mode1_fltr_field_t FLTR_f;
+ };
+ uint8_t RESERVED6[4];
+ union
+ {
+ __IO uint32_t CR0;
+ stc_tim2_mode1_cr0_field_t CR0_f;
+ };
+ uint8_t RESERVED7[20];
+ union
+ {
+ __IO uint32_t CCR0A;
+ stc_tim2_mode1_ccr0a_field_t CCR0A_f;
+ };
+}M0P_TIM2_MODE1_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t ARR;
+ stc_tim2_mode23_arr_field_t ARR_f;
+ };
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim2_mode23_cnt_field_t CNT_f;
+ };
+ uint8_t RESERVED2[4];
+ union
+ {
+ __IO uint32_t M23CR;
+ stc_tim2_mode23_m23cr_field_t M23CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim2_mode23_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim2_mode23_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t MSCR;
+ stc_tim2_mode23_mscr_field_t MSCR_f;
+ };
+ union
+ {
+ __IO uint32_t FLTR;
+ stc_tim2_mode23_fltr_field_t FLTR_f;
+ };
+ union
+ {
+ __IO uint32_t ADTR;
+ stc_tim2_mode23_adtr_field_t ADTR_f;
+ };
+ union
+ {
+ __IO uint32_t CRCH0;
+ stc_tim2_mode23_crch0_field_t CRCH0_f;
+ };
+ uint8_t RESERVED9[8];
+ union
+ {
+ __IO uint32_t DTR;
+ stc_tim2_mode23_dtr_field_t DTR_f;
+ };
+ union
+ {
+ __IO uint32_t RCR;
+ stc_tim2_mode23_rcr_field_t RCR_f;
+ };
+ union
+ {
+ __IO uint32_t ARRDM;
+ stc_tim2_mode23_arrdm_field_t ARRDM_f;
+ };
+ union
+ {
+ __IO uint32_t CCR0A;
+ stc_tim2_mode23_ccr0a_field_t CCR0A_f;
+ };
+ union
+ {
+ __IO uint32_t CCR0B;
+ stc_tim2_mode23_ccr0b_field_t CCR0B_f;
+ };
+}M0P_TIM2_MODE23_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t ARR;
+ stc_tim3_mode0_arr_field_t ARR_f;
+ };
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim3_mode0_cnt_field_t CNT_f;
+ };
+ union
+ {
+ __IO uint32_t CNT32;
+ stc_tim3_mode0_cnt32_field_t CNT32_f;
+ };
+ union
+ {
+ __IO uint32_t M0CR;
+ stc_tim3_mode0_m0cr_field_t M0CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim3_mode0_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim3_mode0_iclr_field_t ICLR_f;
+ };
+ uint8_t RESERVED6[24];
+ union
+ {
+ __IO uint32_t DTR;
+ stc_tim3_mode0_dtr_field_t DTR_f;
+ };
+}M0P_TIM3_MODE0_TypeDef;
+
+typedef struct
+{
+ uint8_t RESERVED0[4];
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim3_mode1_cnt_field_t CNT_f;
+ };
+ uint8_t RESERVED1[4];
+ union
+ {
+ __IO uint32_t M1CR;
+ stc_tim3_mode1_m1cr_field_t M1CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim3_mode1_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim3_mode1_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t MSCR;
+ stc_tim3_mode1_mscr_field_t MSCR_f;
+ };
+ union
+ {
+ __IO uint32_t FLTR;
+ stc_tim3_mode1_fltr_field_t FLTR_f;
+ };
+ uint8_t RESERVED6[4];
+ union
+ {
+ __IO uint32_t CR0;
+ stc_tim3_mode1_cr0_field_t CR0_f;
+ };
+ uint8_t RESERVED7[20];
+ union
+ {
+ __IO uint32_t CCR0A;
+ stc_tim3_mode1_ccr0a_field_t CCR0A_f;
+ };
+}M0P_TIM3_MODE1_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t ARR;
+ stc_tim3_mode23_arr_field_t ARR_f;
+ };
+ union
+ {
+ __IO uint32_t CNT;
+ stc_tim3_mode23_cnt_field_t CNT_f;
+ };
+ uint8_t RESERVED2[4];
+ union
+ {
+ __IO uint32_t M23CR;
+ stc_tim3_mode23_m23cr_field_t M23CR_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_tim3_mode23_ifr_field_t IFR_f;
+ };
+ union
+ {
+ __IO uint32_t ICLR;
+ stc_tim3_mode23_iclr_field_t ICLR_f;
+ };
+ union
+ {
+ __IO uint32_t MSCR;
+ stc_tim3_mode23_mscr_field_t MSCR_f;
+ };
+ union
+ {
+ __IO uint32_t FLTR;
+ stc_tim3_mode23_fltr_field_t FLTR_f;
+ };
+ union
+ {
+ __IO uint32_t ADTR;
+ stc_tim3_mode23_adtr_field_t ADTR_f;
+ };
+ union
+ {
+ __IO uint32_t CRCH0;
+ stc_tim3_mode23_crch0_field_t CRCH0_f;
+ };
+ union
+ {
+ __IO uint32_t CRCH1;
+ stc_tim3_mode23_crch1_field_t CRCH1_f;
+ };
+ union
+ {
+ __IO uint32_t CRCH2;
+ stc_tim3_mode23_crch2_field_t CRCH2_f;
+ };
+ union
+ {
+ __IO uint32_t DTR;
+ stc_tim3_mode23_dtr_field_t DTR_f;
+ };
+ union
+ {
+ __IO uint32_t RCR;
+ stc_tim3_mode23_rcr_field_t RCR_f;
+ };
+ union
+ {
+ __IO uint32_t ARRDM;
+ stc_tim3_mode23_arrdm_field_t ARRDM_f;
+ };
+ union
+ {
+ __IO uint32_t CCR0A;
+ stc_tim3_mode23_ccr0a_field_t CCR0A_f;
+ };
+ union
+ {
+ __IO uint32_t CCR0B;
+ stc_tim3_mode23_ccr0b_field_t CCR0B_f;
+ };
+ union
+ {
+ __IO uint32_t CCR1A;
+ stc_tim3_mode23_ccr1a_field_t CCR1A_f;
+ };
+ union
+ {
+ __IO uint32_t CCR1B;
+ stc_tim3_mode23_ccr1b_field_t CCR1B_f;
+ };
+ union
+ {
+ __IO uint32_t CCR2A;
+ stc_tim3_mode23_ccr2a_field_t CCR2A_f;
+ };
+ union
+ {
+ __IO uint32_t CCR2B;
+ stc_tim3_mode23_ccr2b_field_t CCR2B_f;
+ };
+}M0P_TIM3_MODE23_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t CR;
+ stc_trng_cr_field_t CR_f;
+ };
+ union
+ {
+ __IO uint32_t MODE;
+ stc_trng_mode_field_t MODE_f;
+ };
+ uint8_t RESERVED2[4];
+ union
+ {
+ __IO uint32_t DATA0;
+ stc_trng_data0_field_t DATA0_f;
+ };
+ union
+ {
+ __IO uint32_t DATA1;
+ stc_trng_data1_field_t DATA1_f;
+ };
+}M0P_TRNG_TypeDef;
+
+typedef struct
+{
+ union
+ {
+ __IO uint32_t SBUF;
+ stc_uart_sbuf_field_t SBUF_f;
+ };
+ union
+ {
+ __IO uint32_t SCON;
+ stc_uart_scon_field_t SCON_f;
+ };
+ union
+ {
+ __IO uint32_t SADDR;
+ stc_uart_saddr_field_t SADDR_f;
+ };
+ union
+ {
+ __IO uint32_t SADEN;
+ stc_uart_saden_field_t SADEN_f;
+ };
+ union
+ {
+ __IO uint32_t ISR;
+ stc_uart_isr_field_t ISR_f;
+ };
+ union
+ {
+ __IO uint32_t ICR;
+ stc_uart_icr_field_t ICR_f;
+ };
+ union
+ {
+ __IO uint32_t SCNT;
+ stc_uart_scnt_field_t SCNT_f;
+ };
+}M0P_UART_TypeDef;
+
+typedef struct
+{
+ uint8_t RESERVED0[16];
+ union
+ {
+ __IO uint32_t CR;
+ stc_vc_cr_field_t CR_f;
+ };
+ union
+ {
+ __IO uint32_t VC0_CR;
+ stc_vc_vc0_cr_field_t VC0_CR_f;
+ };
+ union
+ {
+ __IO uint32_t VC1_CR;
+ stc_vc_vc1_cr_field_t VC1_CR_f;
+ };
+ union
+ {
+ __IO uint32_t VC0_OUT_CFG;
+ stc_vc_vc0_out_cfg_field_t VC0_OUT_CFG_f;
+ };
+ union
+ {
+ __IO uint32_t VC1_OUT_CFG;
+ stc_vc_vc1_out_cfg_field_t VC1_OUT_CFG_f;
+ };
+ union
+ {
+ __IO uint32_t IFR;
+ stc_vc_ifr_field_t IFR_f;
+ };
+ uint8_t RESERVED6[296];
+ union
+ {
+ __IO uint32_t VC2_CR;
+ stc_vc_vc2_cr_field_t VC2_CR_f;
+ };
+ union
+ {
+ __IO uint32_t VC2_OUT_CFG;
+ stc_vc_vc2_out_cfg_field_t VC2_OUT_CFG_f;
+ };
+}M0P_VC_TypeDef;
+
+typedef struct
+{
+ uint8_t RESERVED0[128];
+ union
+ {
+ __IO uint32_t RST;
+ stc_wdt_rst_field_t RST_f;
+ };
+ union
+ {
+ __IO uint32_t CON;
+ stc_wdt_con_field_t CON_f;
+ };
+}M0P_WDT_TypeDef;
+
+
+
+#define M0P_PERIPH_BASE (0x40000000UL)
+#define M0P_ADC_BASE (M0P_PERIPH_BASE + 0x00002400UL)
+#define M0P_ADTIM4_BASE (M0P_PERIPH_BASE + 0x00003000UL)
+#define M0P_ADTIM5_BASE (M0P_PERIPH_BASE + 0x00003400UL)
+#define M0P_ADTIM6_BASE (M0P_PERIPH_BASE + 0x00003800UL)
+#define M0P_AES_BASE (M0P_PERIPH_BASE + 0x00021400UL)
+#define M0P_BGR_BASE (M0P_PERIPH_BASE + 0x00002400UL)
+#define M0P_CLK_TRIM_BASE (M0P_PERIPH_BASE + 0x00001800UL)
+#define M0P_CRC_BASE (M0P_PERIPH_BASE + 0x00020900UL)
+#define M0P_DAC_BASE (M0P_PERIPH_BASE + 0x00002500UL)
+#define M0P_DEBUG_ACTIVE_BASE (M0P_PERIPH_BASE + 0x00002038UL)
+#define M0P_DMAC_BASE (M0P_PERIPH_BASE + 0x00021000UL)
+#define M0P_FLASH_BASE (M0P_PERIPH_BASE + 0x00020000UL)
+#define M0P_GPIO_BASE (M0P_PERIPH_BASE + 0x00020C00UL)
+#define M0P_I2C0_BASE (M0P_PERIPH_BASE + 0x00000400UL)
+#define M0P_I2C1_BASE (M0P_PERIPH_BASE + 0x00004400UL)
+#define M0P_LCD_BASE (M0P_PERIPH_BASE + 0x00005C00UL)
+#define M0P_LPTIMER0_BASE (M0P_PERIPH_BASE + 0x00000F00UL)
+#define M0P_LPTIMER1_BASE (M0P_PERIPH_BASE + 0x00000F40UL)
+#define M0P_LPUART0_BASE (M0P_PERIPH_BASE + 0x00000200UL)
+#define M0P_LPUART1_BASE (M0P_PERIPH_BASE + 0x00004000UL)
+#define M0P_LVD_BASE (M0P_PERIPH_BASE + 0x00002400UL)
+#define M0P_OPA_BASE (M0P_PERIPH_BASE + 0x00002400UL)
+#define M0P_PCA_BASE (M0P_PERIPH_BASE + 0x00001000UL)
+#define M0P_PCNT_BASE (M0P_PERIPH_BASE + 0x00005400UL)
+#define M0P_RAM_BASE (M0P_PERIPH_BASE + 0x00020400UL)
+#define M0P_RESET_BASE (M0P_PERIPH_BASE + 0x0000201CUL)
+#define M0P_RTC_BASE (M0P_PERIPH_BASE + 0x00001400UL)
+#define M0P_SPI0_BASE (M0P_PERIPH_BASE + 0x00000800UL)
+#define M0P_SPI1_BASE (M0P_PERIPH_BASE + 0x00004800UL)
+#define M0P_SYSCTRL_BASE (M0P_PERIPH_BASE + 0x00002000UL)
+#define M0P_TIM0_MODE0_BASE (M0P_PERIPH_BASE + 0x00000C00UL)
+#define M0P_TIM0_MODE1_BASE (M0P_PERIPH_BASE + 0x00000C00UL)
+#define M0P_TIM0_MODE23_BASE (M0P_PERIPH_BASE + 0x00000C00UL)
+#define M0P_TIM1_MODE0_BASE (M0P_PERIPH_BASE + 0x00000D00UL)
+#define M0P_TIM1_MODE1_BASE (M0P_PERIPH_BASE + 0x00000D00UL)
+#define M0P_TIM1_MODE23_BASE (M0P_PERIPH_BASE + 0x00000D00UL)
+#define M0P_TIM2_MODE0_BASE (M0P_PERIPH_BASE + 0x00000E00UL)
+#define M0P_TIM2_MODE1_BASE (M0P_PERIPH_BASE + 0x00000E00UL)
+#define M0P_TIM2_MODE23_BASE (M0P_PERIPH_BASE + 0x00000E00UL)
+#define M0P_TIM3_MODE0_BASE (M0P_PERIPH_BASE + 0x00005800UL)
+#define M0P_TIM3_MODE1_BASE (M0P_PERIPH_BASE + 0x00005800UL)
+#define M0P_TIM3_MODE23_BASE (M0P_PERIPH_BASE + 0x00005800UL)
+#define M0P_TRNG_BASE (M0P_PERIPH_BASE + 0x00004C00UL)
+#define M0P_UART0_BASE (M0P_PERIPH_BASE + 0x00000000UL)
+#define M0P_UART1_BASE (M0P_PERIPH_BASE + 0x00000100UL)
+#define M0P_UART2_BASE (M0P_PERIPH_BASE + 0x00006000UL)
+#define M0P_UART3_BASE (M0P_PERIPH_BASE + 0x00006400UL)
+#define M0P_VC_BASE (M0P_PERIPH_BASE + 0x00002400UL)
+#define M0P_WDT_BASE (M0P_PERIPH_BASE + 0x00000F00UL)
+
+
+#define M0P_ADC ((M0P_ADC_TypeDef *)0x40002400UL)
+#define M0P_ADTIM4 ((M0P_ADTIM_TypeDef *)0x40003000UL)
+#define M0P_ADTIM5 ((M0P_ADTIM_TypeDef *)0x40003400UL)
+#define M0P_ADTIM6 ((M0P_ADTIM_TypeDef *)0x40003800UL)
+#define M0P_AES ((M0P_AES_TypeDef *)0x40021400UL)
+#define M0P_BGR ((M0P_BGR_TypeDef *)0x40002400UL)
+#define M0P_CLK_TRIM ((M0P_CLK_TRIM_TypeDef *)0x40001800UL)
+#define M0P_CRC ((M0P_CRC_TypeDef *)0x40020900UL)
+#define M0P_DAC ((M0P_DAC_TypeDef *)0x40002500UL)
+#define M0P_DEBUG_ACTIVE ((M0P_DEBUG_ACTIVE_TypeDef *)0x40002038UL)
+#define M0P_DMAC ((M0P_DMAC_TypeDef *)0x40021000UL)
+#define M0P_FLASH ((M0P_FLASH_TypeDef *)0x40020000UL)
+#define M0P_GPIO ((M0P_GPIO_TypeDef *)0x40020C00UL)
+#define M0P_I2C0 ((M0P_I2C_TypeDef *)0x40000400UL)
+#define M0P_I2C1 ((M0P_I2C_TypeDef *)0x40004400UL)
+#define M0P_LCD ((M0P_LCD_TypeDef *)0x40005C00UL)
+#define M0P_LPTIMER0 ((M0P_LPTIMER_TypeDef *)0x40000F00UL)
+#define M0P_LPTIMER1 ((M0P_LPTIMER_TypeDef *)0x40000F40UL)
+#define M0P_LPUART0 ((M0P_LPUART_TypeDef *)0x40000200UL)
+#define M0P_LPUART1 ((M0P_LPUART_TypeDef *)0x40004000UL)
+#define M0P_LVD ((M0P_LVD_TypeDef *)0x40002400UL)
+#define M0P_OPA ((M0P_OPA_TypeDef *)0x40002400UL)
+#define M0P_PCA ((M0P_PCA_TypeDef *)0x40001000UL)
+#define M0P_PCNT ((M0P_PCNT_TypeDef *)0x40005400UL)
+#define M0P_RAM ((M0P_RAM_TypeDef *)0x40020400UL)
+#define M0P_RESET ((M0P_RESET_TypeDef *)0x4000201CUL)
+#define M0P_RTC ((M0P_RTC_TypeDef *)0x40001400UL)
+#define M0P_SPI0 ((M0P_SPI_TypeDef *)0x40000800UL)
+#define M0P_SPI1 ((M0P_SPI_TypeDef *)0x40004800UL)
+#define M0P_SYSCTRL ((M0P_SYSCTRL_TypeDef *)0x40002000UL)
+#define M0P_TIM0_MODE0 ((M0P_TIM0_MODE0_TypeDef *)0x40000C00UL)
+#define M0P_TIM0_MODE1 ((M0P_TIM0_MODE1_TypeDef *)0x40000C00UL)
+#define M0P_TIM0_MODE23 ((M0P_TIM0_MODE23_TypeDef *)0x40000C00UL)
+#define M0P_TIM1_MODE0 ((M0P_TIM1_MODE0_TypeDef *)0x40000D00UL)
+#define M0P_TIM1_MODE1 ((M0P_TIM1_MODE1_TypeDef *)0x40000D00UL)
+#define M0P_TIM1_MODE23 ((M0P_TIM1_MODE23_TypeDef *)0x40000D00UL)
+#define M0P_TIM2_MODE0 ((M0P_TIM2_MODE0_TypeDef *)0x40000E00UL)
+#define M0P_TIM2_MODE1 ((M0P_TIM2_MODE1_TypeDef *)0x40000E00UL)
+#define M0P_TIM2_MODE23 ((M0P_TIM2_MODE23_TypeDef *)0x40000E00UL)
+#define M0P_TIM3_MODE0 ((M0P_TIM3_MODE0_TypeDef *)0x40005800UL)
+#define M0P_TIM3_MODE1 ((M0P_TIM3_MODE1_TypeDef *)0x40005800UL)
+#define M0P_TIM3_MODE23 ((M0P_TIM3_MODE23_TypeDef *)0x40005800UL)
+#define M0P_TRNG ((M0P_TRNG_TypeDef *)0x40004C00UL)
+#define M0P_UART0 ((M0P_UART_TypeDef *)0x40000000UL)
+#define M0P_UART1 ((M0P_UART_TypeDef *)0x40000100UL)
+#define M0P_UART2 ((M0P_UART_TypeDef *)0x40006000UL)
+#define M0P_UART3 ((M0P_UART_TypeDef *)0x40006400UL)
+#define M0P_VC ((M0P_VC_TypeDef *)0x40002400UL)
+#define M0P_WDT ((M0P_WDT_TypeDef *)0x40000F00UL)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32L17X_H__ */
+
diff --git a/mcu/common/interrupts_hc32l17x.c b/mcu/common/interrupts_hc32l17x.c
new file mode 100644
index 0000000..a37b82b
--- /dev/null
+++ b/mcu/common/interrupts_hc32l17x.c
@@ -0,0 +1,610 @@
+/******************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file interrupts_hc32l136.c
+ **
+ ** Interrupt management
+ ** @link Driver Group Some description @endlink
+ **
+ ** - 2018-04-15 1.0 Lux First version.
+ **
+ **
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "ddl.h"
+#include "interrupts_hc32l17x.h"
+
+/*******************************************************************************
+ * IRQ WEAK DEFINE
+ ******************************************************************************/
+__WEAK void SysTick_IRQHandler(void);
+
+
+__WEAK void PortA_IRQHandler(void);
+__WEAK void PortB_IRQHandler(void);
+__WEAK void PortC_IRQHandler(void);
+__WEAK void PortD_IRQHandler(void);
+__WEAK void PortE_IRQHandler(void);
+__WEAK void PortF_IRQHandler(void);
+__WEAK void Dmac_IRQHandler(void);
+__WEAK void Tim3_IRQHandler(void);
+__WEAK void Uart0_IRQHandler(void);
+__WEAK void Uart1_IRQHandler(void);
+__WEAK void Uart2_IRQHandler(void);
+__WEAK void Uart3_IRQHandler(void);
+__WEAK void LpUart0_IRQHandler(void);
+__WEAK void LpUart1_IRQHandler(void);
+__WEAK void Spi0_IRQHandler(void);
+__WEAK void Spi1_IRQHandler(void);
+__WEAK void I2c0_IRQHandler(void);
+__WEAK void I2c1_IRQHandler(void);
+__WEAK void Tim0_IRQHandler(void);
+__WEAK void Tim1_IRQHandler(void);
+__WEAK void Tim2_IRQHandler(void);
+__WEAK void LpTim0_IRQHandler(void);
+__WEAK void LpTim1_IRQHandler(void);
+__WEAK void Tim4_IRQHandler(void);
+__WEAK void Tim5_IRQHandler(void);
+__WEAK void Tim6_IRQHandler(void);
+__WEAK void Pca_IRQHandler(void);
+__WEAK void Wdt_IRQHandler(void);
+__WEAK void Rtc_IRQHandler(void);
+__WEAK void Adc_IRQHandler(void);
+__WEAK void Dac_IRQHandler(void);
+__WEAK void Pcnt_IRQHandler(void);
+__WEAK void Vc0_IRQHandler(void);
+__WEAK void Vc1_IRQHandler(void);
+__WEAK void Vc2_IRQHandler(void);
+__WEAK void Lvd_IRQHandler(void);
+__WEAK void Lcd_IRQHandler(void);
+__WEAK void Flash_IRQHandler(void);
+__WEAK void Ram_IRQHandler(void);
+__WEAK void ClkTrim_IRQHandler(void);
+
+/**
+ *******************************************************************************
+ ** \brief NVIC 中断使能
+ **
+ ** \param [in] enIrq 中断号枚举类型
+ ** \param [in] enLevel 中断优先级枚举类型
+ ** \param [in] bEn 中断开关
+ ** \retval Ok 设置成功
+ ** 其他值 设置失败
+ ******************************************************************************/
+void EnableNvic(IRQn_Type enIrq, en_irq_level_t enLevel, boolean_t bEn)
+{
+ NVIC_ClearPendingIRQ(enIrq);
+ NVIC_SetPriority(enIrq, enLevel);
+ if (TRUE == bEn)
+ {
+ NVIC_EnableIRQ(enIrq);
+ }
+ else
+ {
+ NVIC_DisableIRQ(enIrq);
+ }
+}
+
+/**
+ *******************************************************************************
+ ** \brief NVIC hardware fault 中断实现
+ **
+ **
+ ** \retval
+ ******************************************************************************/
+void HardFault_Handler(void)
+{
+ volatile int a = 0;
+
+ while( 0 == a)
+ {
+ ;
+ }
+
+}
+
+
+/**
+ *******************************************************************************
+ ** \brief NVIC SysTick 中断实现
+ **
+ ** \retval
+ ******************************************************************************/
+void SysTick_Handler(void)
+{
+ SysTick_IRQHandler();
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO PortA 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void PORTA_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_PORTA)
+ PortA_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO PortB 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void PORTB_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_PORTB)
+ PortB_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO PortC/E 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void PORTC_E_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_PORTC)
+ PortC_IRQHandler();
+#endif
+
+#if (INT_CALLBACK_ON == INT_CALLBACK_PORTE)
+ PortE_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief GPIO PortD/F 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void PORTD_F_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_PORTD)
+ PortD_IRQHandler();
+#endif
+
+#if (INT_CALLBACK_ON == INT_CALLBACK_PORTF)
+ PortF_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief DMAC 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void DMAC_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_DMAC)
+ Dmac_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief TIM3 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void TIM3_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_TIM3)
+ Tim3_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief UART0/2 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void UART0_2_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_UART0)
+ Uart0_IRQHandler();
+#endif
+
+#if (INT_CALLBACK_ON == INT_CALLBACK_UART2)
+ Uart2_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief UART1/3 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void UART1_3_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_UART1)
+ Uart1_IRQHandler();
+#endif
+
+#if (INT_CALLBACK_ON == INT_CALLBACK_UART3)
+ Uart3_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief LPUART0 低功耗串口0 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void LPUART0_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_LPUART0)
+ LpUart0_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief LPUART1 低功耗串口1 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void LPUART1_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_LPUART1)
+ LpUart1_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief SPI0 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void SPI0_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_SPI0)
+ Spi0_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief SPI1 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void SPI1_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_SPI1)
+ Spi1_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief I2C0 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void I2C0_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_I2C0)
+ I2c0_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief I2C1 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void I2C1_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_I2C1)
+ I2c1_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief TIM0 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void TIM0_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_TIM0)
+ Tim0_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief TIM1 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void TIM1_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_TIM1)
+ Tim1_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief TIM2 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void TIM2_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_TIM2)
+ Tim2_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief LPTIM0/1 低功耗时钟 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void LPTIM0_1_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_LPTIM0)
+ LpTim0_IRQHandler();
+#endif
+
+#if (INT_CALLBACK_ON == INT_CALLBACK_LPTIM1)
+ LpTim1_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief TIM4 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void TIM4_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_TIM4)
+ Tim4_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief TIM5 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void TIM5_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_TIM5)
+ Tim5_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief TIM6 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void TIM6_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_TIM6)
+ Tim6_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief PCA 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void PCA_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_PCA)
+ Pca_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief WDT 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void WDT_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_WDT)
+ Wdt_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief RTC 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void RTC_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_RTC)
+ Rtc_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief ADC/DAC 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void ADC_DAC_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_ADC)
+ Adc_IRQHandler();
+#endif
+
+#if (INT_CALLBACK_ON == INT_CALLBACK_DAC)
+ Dac_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief PCNT 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void PCNT_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_PCNT)
+ Pcnt_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief VC0 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void VC0_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_VC0)
+ Vc0_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief VC1/2 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void VC1_2_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_VC1)
+ Vc1_IRQHandler();
+#endif
+
+#if (INT_CALLBACK_ON == INT_CALLBACK_VC2)
+ Vc2_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief LVD 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void LVD_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_LVD)
+ Lvd_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief LCD 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void LCD_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_LCD)
+ Lcd_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief FLASH/RAM 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void FLASH_RAM_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_FLASH)
+ Flash_IRQHandler();
+#endif
+
+#if (INT_CALLBACK_ON == INT_CALLBACK_RAM)
+ Ram_IRQHandler();
+#endif
+}
+
+/**
+ *******************************************************************************
+ ** \brief CLKTRIM 中断处理函数
+ **
+ ** \retval
+ ******************************************************************************/
+void CLKTRIM_IRQHandler(void)
+{
+#if (INT_CALLBACK_ON == INT_CALLBACK_CLKTRIM)
+ ClkTrim_IRQHandler();
+#endif
+}
+
+/******************************************************************************/
+/* EOF (not truncated) */
+/******************************************************************************/
diff --git a/mcu/common/interrupts_hc32l17x.h b/mcu/common/interrupts_hc32l17x.h
new file mode 100644
index 0000000..533ef30
--- /dev/null
+++ b/mcu/common/interrupts_hc32l17x.h
@@ -0,0 +1,150 @@
+/*******************************************************************************
+* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file interrupts_hc32l17x.h
+ **
+ ** Interrupt common define.
+ ** @link IRQGroup Some description @endlink
+ **
+ ** - 2019-03-01 1.0 Lux First version.
+ **
+ ******************************************************************************/
+#ifndef __INTERRUPTS_HC32L17X_H__
+#define __INTERRUPTS_HC32L17X_H__
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "ddl.h"
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/******************************************************************************/
+/* Global pre-processor symbols/macros ('#define') */
+/******************************************************************************/
+#define DDL_IRQ_LEVEL_DEFAULT 3u
+
+//<<此选项会打开interrupt_hc32xxx.c中的中断回调函数，用户如果需要实现中断服务函数，
+//<<可在源码文件中定义该文件中用"__WEAK"声明的同名中断服务函数即可。
+#define INT_CALLBACK_ON 1u //<<(默认值)
+//<<此选项会关闭interrupt_hc32xxx.c中的中断回调函数，此时用户可在该文件中自行定义中断服务函数的实现。
+#define INT_CALLBACK_OFF 0u
+/******************************************************************************
+ * Global type definitions
+ ******************************************************************************/
+#define INT_CALLBACK_PORTA INT_CALLBACK_ON
+#define INT_CALLBACK_PORTB INT_CALLBACK_ON
+#define INT_CALLBACK_PORTC INT_CALLBACK_ON
+#define INT_CALLBACK_PORTD INT_CALLBACK_ON
+#define INT_CALLBACK_PORTE INT_CALLBACK_OFF
+#define INT_CALLBACK_PORTF INT_CALLBACK_OFF
+#define INT_CALLBACK_DMAC INT_CALLBACK_ON
+#define INT_CALLBACK_TIM3 INT_CALLBACK_ON
+#define INT_CALLBACK_UART0 INT_CALLBACK_ON
+#define INT_CALLBACK_UART1 INT_CALLBACK_ON
+#define INT_CALLBACK_UART2 INT_CALLBACK_ON
+#define INT_CALLBACK_UART3 INT_CALLBACK_ON
+#define INT_CALLBACK_LPUART0 INT_CALLBACK_ON
+#define INT_CALLBACK_LPUART1 INT_CALLBACK_ON
+#define INT_CALLBACK_SPI0 INT_CALLBACK_ON
+#define INT_CALLBACK_SPI1 INT_CALLBACK_ON
+#define INT_CALLBACK_I2C0 INT_CALLBACK_ON
+#define INT_CALLBACK_I2C1 INT_CALLBACK_ON
+#define INT_CALLBACK_TIM0 INT_CALLBACK_ON
+#define INT_CALLBACK_TIM1 INT_CALLBACK_ON
+#define INT_CALLBACK_TIM2 INT_CALLBACK_ON
+#define INT_CALLBACK_LPTIM0 INT_CALLBACK_ON
+#define INT_CALLBACK_LPTIM1 INT_CALLBACK_ON
+#define INT_CALLBACK_TIM4 INT_CALLBACK_ON
+#define INT_CALLBACK_TIM5 INT_CALLBACK_ON
+#define INT_CALLBACK_TIM6 INT_CALLBACK_ON
+#define INT_CALLBACK_PCA INT_CALLBACK_ON
+#define INT_CALLBACK_WDT INT_CALLBACK_ON
+#define INT_CALLBACK_RTC INT_CALLBACK_ON
+#define INT_CALLBACK_ADC INT_CALLBACK_ON
+#define INT_CALLBACK_DAC INT_CALLBACK_ON
+#define INT_CALLBACK_PCNT INT_CALLBACK_ON
+#define INT_CALLBACK_VC0 INT_CALLBACK_ON
+#define INT_CALLBACK_VC1 INT_CALLBACK_ON
+#define INT_CALLBACK_VC2 INT_CALLBACK_ON
+#define INT_CALLBACK_LVD INT_CALLBACK_ON
+#define INT_CALLBACK_LCD INT_CALLBACK_ON
+#define INT_CALLBACK_FLASH INT_CALLBACK_ON
+#define INT_CALLBACK_RAM INT_CALLBACK_ON
+#define INT_CALLBACK_CLKTRIM INT_CALLBACK_ON
+
+
+/**
+ *******************************************************************************
+ ** \brief 中断优先级数据类型定义
+ ** \note
+ ******************************************************************************/
+typedef enum en_irq_level
+{
+ IrqLevel0 = 0u, ///< 优先级0
+ IrqLevel1 = 1u, ///< 优先级1
+ IrqLevel2 = 2u, ///< 优先级2
+ IrqLevel3 = 3u, ///< 优先级3
+} en_irq_level_t;
+
+
+/******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+///< 系统中断使能开关
+extern void EnableNvic(IRQn_Type enIrq, en_irq_level_t enLevel, boolean_t bEn);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __INTERRUPTS_HC32L17X_H__ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/mcu/common/system_hc32l17x.c b/mcu/common/system_hc32l17x.c
new file mode 100644
index 0000000..c0cb41d
--- /dev/null
+++ b/mcu/common/system_hc32l17x.c
@@ -0,0 +1,212 @@
+/*******************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file system_hc32l136.c
+ **
+ ** System clock initialization.
+ ** @link SampleGroup Some description @endlink
+ **
+ ** - 2019-03-01 1.0 Lux First version.
+ **
+ ******************************************************************************/
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "base_types.h"
+#include "hc32l17x.h"
+#include "system_hc32l17x.h"
+#include "sysctrl.h"
+
+/**
+ ******************************************************************************
+ ** System Clock Frequency (Core Clock) Variable according CMSIS
+ ******************************************************************************/
+uint32_t SystemCoreClock = 4000000;
+
+
+//add clock source.
+void SystemCoreClockUpdate (void) // Update SystemCoreClock variable
+{
+ SystemCoreClock = Sysctrl_GetHClkFreq();
+}
+
+/**
+ ******************************************************************************
+ ** \brief 对MCU未引出IO端口进行默认配置.
+ **
+ ** \param none
+ ** \return none
+ ******************************************************************************/
+static void _InitHidePin(void)
+{
+ uint32_t tmpReg = M0P_SYSCTRL->PERI_CLKEN0;
+
+ M0P_SYSCTRL->PERI_CLKEN0_f.GPIO = 1;
+
+#if defined(HC32L17xPxxx) //100PIN MCU
+ M0P_GPIO->PFADS &= 0xFF4F; ///< PF04/PF05/PF07配置为数字端口
+
+ M0P_GPIO->PFDIR |= 0x00B0; ///< PF04/PF05/PF07配置为端口输入
+
+ M0P_GPIO->PFPU |= 0x00B0; ///< PF04/PF05/PF07配置为上拉
+
+#elif defined(HC32L17xMxxx) //80PIN MCU
+ M0P_GPIO->PDADS &= 0x0F1F; ///< PD05~07/PD12~15配置为数字端口
+ M0P_GPIO->PEADS &= 0x783C; ///< PE00/PE01/PE06~10/PE15配置为数字端口
+ M0P_GPIO->PFADS &= 0xF9F3; ///< PF02/PF03/PF09/PF10配置为数字端口
+
+ M0P_GPIO->PDDIR |= 0xF0E0; ///< PD05~07/PD12~15配置为端口输入
+ M0P_GPIO->PEDIR |= 0x87C3; ///< PE00/PE01/PE06~10/PE15配置为端口输入
+ M0P_GPIO->PFDIR |= 0x060C; ///< PF02/PF03/PF09/PF10配置为数字端口
+
+
+ M0P_GPIO->PDPU |= 0xF0E0; ///< PD05~07/PD12~15配置为上拉
+ M0P_GPIO->PEPU |= 0x87C3; ///< PE00/PE01/PE06~10/PE15配置为上拉
+ M0P_GPIO->PFPU |= 0x060C; ///< PF02/PF03/PF09/PF10配置为数字端口
+
+#elif defined(HC32L17xKxxx) //64PIN MCU
+ M0P_GPIO->PDADS &= 0x0004; ///< PD00/PD01/PD03~15配置为数字端口
+ M0P_GPIO->PEADS &= 0x0000; ///< PE00~15配置为数字端口
+ M0P_GPIO->PFADS &= 0xF9F3; ///< PF02/PF03/PF09/PF10配置为数字端口
+
+ M0P_GPIO->PDDIR |= 0xFFFB; ///< PD00/PD01/PD03~15配置为端口输入
+ M0P_GPIO->PEDIR |= 0xFFFF; ///< PE00~15配置为端口输入
+ M0P_GPIO->PFDIR |= 0x060C; ///< PF02/PF03/PF09/PF10配置为数字端口
+
+ M0P_GPIO->PDPU |= 0xFFFB; ///< PD00/PD01/PD03~15配置为上拉
+ M0P_GPIO->PEPU |= 0xFFFF; ///< PE00~15配置为上拉
+ M0P_GPIO->PFPU |= 0x060C; ///< PF02/PF03/PF09/PF10配置为数字端口
+
+#elif defined(HC32L17xJxxx) //48PIN MCU
+ M0P_GPIO->PCADS &= 0xE000; ///< PC00~12配置为数字端口
+ M0P_GPIO->PDADS &= 0x0000; ///< PD00~15配置为数字端口
+ M0P_GPIO->PEADS &= 0x0000; ///< PE00~15配置为数字端口
+ M0P_GPIO->PFADS &= 0xF9C3; ///< PF02~05/PF09/PF10配置为数字端口
+
+ M0P_GPIO->PCDIR |= 0x1FFF; ///< PC00~12配置为端口输入
+ M0P_GPIO->PDDIR |= 0xFFFF; ///< PD00~15配置为端口输入
+ M0P_GPIO->PEDIR |= 0xFFFF; ///< PE00~15配置为端口输入
+ M0P_GPIO->PFDIR |= 0x063C; ///< PF02~05/PF09/PF10配置为数字端口
+
+
+ M0P_GPIO->PCPU |= 0x1FFF; ///< PC00~12配置为上拉
+ M0P_GPIO->PDPU |= 0xFFFF; ///< PD00~15配置为上拉
+ M0P_GPIO->PEPU |= 0xFFFF; ///< PE00~15配置为上拉
+ M0P_GPIO->PFPU |= 0x063C; ///< PF02~05/PF09/PF10配置为数字端口
+
+#elif defined(HC32L17xFxxx) //32PIN MCU
+ M0P_GPIO->PAADS &= 0xFFF4; ///< PA00/PA01/PA03配置为数字端口
+ M0P_GPIO->PBADS &= 0x08FB; ///< PB02/PB08~10/PB12~15配置为数字端口
+ M0P_GPIO->PCADS &= 0xC000; ///< PC00~13配置为数字端口
+ M0P_GPIO->PDADS &= 0x0000; ///< PD00~15配置为数字端口
+ M0P_GPIO->PEADS &= 0x0000; ///< PE00~15配置为数字端口
+ M0P_GPIO->PFADS &= 0xF903; ///< PF02~07/PF09/PF10配置为数字端口
+
+ M0P_GPIO->PADIR |= 0x000B; ///< PA00/PA01/PA03配置为端口输入
+ M0P_GPIO->PBDIR |= 0xF704; ///< PB02/PB08~10/PB12~15配置为端口输入
+ M0P_GPIO->PCDIR |= 0x3FFF; ///< PC00~13配置为端口输入
+ M0P_GPIO->PDDIR |= 0xFFFF; ///< PD00~15配置为端口输入
+ M0P_GPIO->PEDIR |= 0xFFFF; ///< PE00~15配置为端口输入
+ M0P_GPIO->PFDIR |= 0x06FC; ///< PF02~07/PF09/PF10配置为数字端口
+
+ M0P_GPIO->PAPU |= 0x000B; ///< PA00/PA01/PA03配置为上拉
+ M0P_GPIO->PBPU |= 0xF704; ///< PB02/PB08~10/PB12~15配置为上拉
+ M0P_GPIO->PCPU |= 0x3FFF; ///< PC00~13配置为上拉
+ M0P_GPIO->PDPU |= 0xFFFF; ///< PD00~15配置为上拉
+ M0P_GPIO->PEPU |= 0xFFFF; ///< PE00~15配置为上拉
+ M0P_GPIO->PFPU |= 0x06FC; ///< PF02~07/PF09/PF10配置为数字端口
+
+#endif
+
+ M0P_SYSCTRL->PERI_CLKEN0 = tmpReg;
+}
+
+/**
+ ******************************************************************************
+ ** \brief Setup the microcontroller system. Initialize the System and update
+ ** the SystemCoreClock variable.
+ **
+ ** \param none
+ ** \return none
+ ******************************************************************************/
+void SystemInit(void)
+{
+ M0P_SYSCTRL->RCL_CR_f.TRIM = (*((volatile uint16_t*) (0x00100C22ul)));
+ M0P_SYSCTRL->RCH_CR_f.TRIM = (*((volatile uint16_t*) (0x00100C08ul)));
+ SystemCoreClockUpdate();
+ _InitHidePin();
+}
+
+
+#if defined (__CC_ARM)
+extern int32_t $Super$$main(void);
+/* re-define main function */
+int $Sub$$main(void)
+{
+ SystemInit();
+ $Super$$main();
+ return 0;
+}
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+extern int32_t $Super$$main(void);
+/* re-define main function */
+int $Sub$$main(void)
+{
+ SystemInit();
+ $Super$$main();
+ return 0;
+}
+#elif defined(__ICCARM__)
+extern int32_t main(void);
+/* __low_level_init will auto called by IAR cstartup */
+extern void __iar_data_init3(void);
+int __low_level_init(void)
+{
+ // call IAR table copy function.
+ __iar_data_init3();
+ SystemInit();
+ main();
+ return 0;
+}
+#endif
+
diff --git a/mcu/common/system_hc32l17x.h b/mcu/common/system_hc32l17x.h
new file mode 100644
index 0000000..6ff8efb
--- /dev/null
+++ b/mcu/common/system_hc32l17x.h
@@ -0,0 +1,116 @@
+/*******************************************************************************
+* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file system_hc32l17x.h
+ **
+ ** A detailed description is available at
+ ** @link SampleGroup Some description @endlink
+ **
+ ** - 2019-03-01 1.0 Lux First version.
+ **
+ ******************************************************************************/
+
+#ifndef __SYSTEM_HC32L17X_H__
+#define __SYSTEM_HC32L17X_H__
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************/
+/* Global pre-processor symbols/macros ('define') */
+/******************************************************************************/
+#define HWWD_DISABLE (1)
+
+
+
+/**
+ ******************************************************************************
+ ** \brief Clock Setup macro definition
+ **
+ ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application
+ ** - 1: CLOCK_SETTING_CMSIS -
+ ******************************************************************************/
+#define CLOCK_SETTING_NONE 0u
+#define CLOCK_SETTING_CMSIS 1u
+
+//#define HC32L17xPxxx //100PIN
+//#define HC32L17xMxxx //80PIN
+//#define HC32L17xKxxx //64PIN
+//#define HC32L17xJxxx //48PIN
+#define HC32L17xFxxx //32PIN
+
+/******************************************************************************/
+/* */
+/* START OF USER SETTINGS HERE */
+/* =========================== */
+/* */
+/* All lines with '<<<' can be set by user. */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Global function prototypes ('extern', definition in C source) */
+/******************************************************************************/
+
+
+extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
+extern void SystemInit (void); // Initialize the system
+extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_HC32L17X _H__ */
+
+
+
+
+
+
+
diff --git a/source/ddl_device.h b/source/ddl_device.h
new file mode 100644
index 0000000..582bd95
--- /dev/null
+++ b/source/ddl_device.h
@@ -0,0 +1,76 @@
+/*******************************************************************************
+* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved.
+*
+* This software is owned and published by:
+* Huada Semiconductor Co.,Ltd ("HDSC").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with HDSC
+* components. This software is licensed by HDSC to be adapted only
+* for use in systems utilizing HDSC components. HDSC shall not be
+* responsible for misuse or illegal use of this software for devices not
+* supported herein. HDSC is providing this software "AS IS" and will
+* not be responsible for issues arising from incorrect user implementation
+* of the software.
+*
+* Disclaimer:
+* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+* WARRANTY OF NONINFRINGEMENT.
+* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+* SAVINGS OR PROFITS,
+* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+* FROM, THE SOFTWARE.
+*
+* This software may be replicated in part or whole for the licensed use,
+* with the restriction that this Disclaimer and Copyright notice must be
+* included with each copy of this software, whether used in part or whole,
+* at all times.
+*/
+/******************************************************************************/
+/** \file ddl_device.h
+ **
+ ** Device define
+ ** @link SampleGroup Some description @endlink
+ **
+ ** - 2018-04-15
+ **
+ *****************************************************************************/
+
+#ifndef __DDL_DEVICE_H__
+#define __DDL_DEVICE_H__
+
+/**
+ *******************************************************************************
+ ** \brief Global device series definition
+ **
+ ** \note
+ ******************************************************************************/
+#define DDL_MCU_SERIES DDL_DEVICE_SERIES_HC32L17X
+
+
+/**
+ *******************************************************************************
+ ** \brief Global package definition
+ **
+ ** \note This definition is used for device package settings
+ ******************************************************************************/
+#define DDL_MCU_PACKAGE DDL_DEVICE_PACKAGE_HC_K
+
+#endif /* __DDL_DEVICE_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/source/inc/bsp.h b/source/inc/bsp.h
new file mode 100644
index 0000000..85c5f51
--- /dev/null
+++ b/source/inc/bsp.h
@@ -0,0 +1,251 @@
+#ifndef _BSP_H
+#define _BSP_H
+
+#include
+#include
+#include "gpio.h"
+
+/*豸*/
+#define FORCE_6D 0x0001 //0x0001 άӦ
+#define OSMOTIC_PRESSURE 0x0002 //0x0002 ѹ
+#define ELASTIC_WAVEGUIDE 0x0003 //0x0003 Բ
+#define DIELECTRIC_MASS 0x0004 //0x0004
+#define _0x0005 0x0005 //0x0005
+#define CONT_DEFOR_3D 0x0006 //0x0006 ά
+#define COMM_UNIT 0x0007 //0x0007 ͨѶԪ
+#define FORCE_3D 0x0008 //0x0008 άӦ
+#define LASER_TRACING 0x0009 //0x0009 ʾ
+#define _0x000A 0x000A //0x000A
+#define _0x000B 0x000B //0x000B
+#define _0x000C 0x000C //0x000C
+#define MULTI_PARAMETER_FUSION 0x000D //0x000D ں
+#define CRACK_DETECTION 0x000E //0x000E ѷ
+#define _0x000F 0x000F //0x000F
+#define ATTITUDE_MONITOR 0x0010 //0x0010 ̬
+#define LASER_DISPLACE 0x0011 //0x0011 λ
+#define REBAR_STRESS 0x0012 //0x0012 ֽӦ
+#define ANCHOR_ROD_STRESS 0x0013 //0x0013 ê
+#define SURFACE_STRESS 0x0014 //0x0014 Ӧ
+#define PRESSURE 0x0015 //0x0015 ѹ
+#define MICROWAVE_DISPLACE 0x0016 //0x0016
+/*ͨѶʽ*/
+typedef enum {
+ LORA = 0x01, //0x01 LORAͨѶ
+ RS485 = 0x02, //0x02 RS485ͨѶ
+ RS232 = 0x03, //0x03 RS232ͨѶ
+ CAN = 0x04, //0x04 CANͨѶ
+ _4G = 0x05, //0x05 _4GͨѶ
+ BLE = 0x06, //0x06 BLEͨѶ
+ WIFI = 0x07, //0x07 WIFIͨѶ
+}COMM_WAY_M;
+/*豸־*/
+typedef enum {
+ MASTER = 0x000000, //0x000000 豸
+ SUBSET = 0x800000, //0x800000 豸
+}DEVICE_SIGN_M;
+
+/*豸ѡ*/
+#define DEVICE_TYPE LASER_TRACING
+/*ͨѶʽѡ*/
+#define COMM_WAY LORA
+/*豸־ѡ*/
+#define DEVICE_SIGN MASTER
+/*豸ַ*/
+#define ADD_NUMBER (0x000000 + DEVICE_SIGN) //ֲֶӦΨһַ
+
+#if(DEVICE_TYPE == LASER_TRACING)
+#define LP_UART_CH 0
+#define LPUART (M0P_LPUART0)
+#define LPUART_IRQN (LPUART0_IRQn)
+#define LPUART_PERIPHERAL_CLK (SysctrlPeripheralLpUart0)
+
+#define LPUART_TX_AF GpioAf4
+#define LPUART_TX_PORT GpioPortB
+#define LPUART_TX_PIN GpioPin10
+
+#define LPUART_RX_AF GpioAf3
+#define LPUART_RX_PORT GpioPortB
+#define LPUART_RX_PIN GpioPin11
+
+#define RS485_CTRL_PORT GpioPortB
+#define RS485_CTRL_PIN GpioPin1
+
+#define RS485_CTRL_RX() Gpio_ClrIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#define RS485_CTRL_TX() Gpio_SetIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#endif
+#if(DEVICE_TYPE == FORCE_6D)
+#define LP_UART_CH 0
+#define LPUART (M0P_LPUART0)
+#define LPUART_IRQN (LPUART0_IRQn)
+#define LPUART_PERIPHERAL_CLK (SysctrlPeripheralLpUart0)
+
+#define LPUART_TX_AF GpioAf3
+#define LPUART_TX_PORT GpioPortB
+#define LPUART_TX_PIN GpioPin0
+
+#define LPUART_RX_AF GpioAf3
+#define LPUART_RX_PORT GpioPortB
+#define LPUART_RX_PIN GpioPin11
+
+#define RS485_CTRL_PORT GpioPortB
+#define RS485_CTRL_PIN GpioPin1
+
+#define RS485_CTRL_RX() Gpio_ClrIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#define RS485_CTRL_TX() Gpio_SetIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#endif
+#if(DEVICE_TYPE == OSMOTIC_PRESSURE)
+#define LP_UART_CH 0
+#define LPUART (M0P_LPUART0)
+#define LPUART_IRQN (LPUART0_IRQn)
+#define LPUART_PERIPHERAL_CLK (SysctrlPeripheralLpUart0)
+
+#define LPUART_TX_AF GpioAf3
+#define LPUART_TX_PORT GpioPortB
+#define LPUART_TX_PIN GpioPin0
+
+#define LPUART_RX_AF GpioAf3
+#define LPUART_RX_PORT GpioPortB
+#define LPUART_RX_PIN GpioPin11
+
+#define RS485_CTRL_PORT GpioPortB
+#define RS485_CTRL_PIN GpioPin1
+
+#define RS485_CTRL_RX() Gpio_ClrIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#define RS485_CTRL_TX() Gpio_SetIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#endif
+#if(DEVICE_TYPE == CONT_DEFOR_3D)
+#define LP_UART_CH 0
+#define LPUART (M0P_LPUART0)
+#define LPUART_IRQN (LPUART0_IRQn)
+#define LPUART_PERIPHERAL_CLK (SysctrlPeripheralLpUart0)
+
+#define LPUART_TX_AF GpioAf3
+#define LPUART_TX_PORT GpioPortB
+#define LPUART_TX_PIN GpioPin0
+
+#define LPUART_RX_AF GpioAf3
+#define LPUART_RX_PORT GpioPortB
+#define LPUART_RX_PIN GpioPin11
+
+#define RS485_CTRL_PORT GpioPortB
+#define RS485_CTRL_PIN GpioPin1
+
+#define RS485_CTRL_RX() Gpio_ClrIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#define RS485_CTRL_TX() Gpio_SetIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#endif
+#if(DEVICE_TYPE == COMM_UNIT)
+#define LP_UART_CH 0
+#define LPUART (M0P_LPUART0)
+#define LPUART_IRQN (LPUART0_IRQn)
+#define LPUART_PERIPHERAL_CLK (SysctrlPeripheralLpUart0)
+
+#define LPUART_TX_AF GpioAf4
+#define LPUART_TX_PORT GpioPortB
+#define LPUART_TX_PIN GpioPin10
+
+#define LPUART_RX_AF GpioAf3
+#define LPUART_RX_PORT GpioPortB
+#define LPUART_RX_PIN GpioPin11
+
+#define RS485_CTRL_PORT GpioPortB
+#define RS485_CTRL_PIN GpioPin2
+
+#define RS485_CTRL_RX() Gpio_ClrIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#define RS485_CTRL_TX() Gpio_SetIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#endif
+#if(DEVICE_TYPE == FORCE_3D)
+#define LP_UART_CH 0
+#define LPUART (M0P_LPUART0)
+#define LPUART_IRQN (LPUART0_IRQn)
+#define LPUART_PERIPHERAL_CLK (SysctrlPeripheralLpUart0)
+
+#define LPUART_TX_AF GpioAf3
+#define LPUART_TX_PORT GpioPortB
+#define LPUART_TX_PIN GpioPin0
+
+#define LPUART_RX_AF GpioAf3
+#define LPUART_RX_PORT GpioPortB
+#define LPUART_RX_PIN GpioPin11
+
+#define RS485_CTRL_PORT GpioPortB
+#define RS485_CTRL_PIN GpioPin1
+
+#define RS485_CTRL_RX() Gpio_ClrIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#define RS485_CTRL_TX() Gpio_SetIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#endif
+#if(DEVICE_TYPE == CRACK_DETECTION)
+#define LP_UART_CH 0
+#define LPUART (M0P_LPUART0)
+#define LPUART_IRQN (LPUART0_IRQn)
+#define LPUART_PERIPHERAL_CLK (SysctrlPeripheralLpUart0)
+
+#define LPUART_TX_AF GpioAf4
+#define LPUART_TX_PORT GpioPortB
+#define LPUART_TX_PIN GpioPin10
+
+#define LPUART_RX_AF GpioAf3
+#define LPUART_RX_PORT GpioPortB
+#define LPUART_RX_PIN GpioPin11
+
+#define RS485_CTRL_PORT GpioPortB
+#define RS485_CTRL_PIN GpioPin2
+
+#define RS485_CTRL_RX() Gpio_ClrIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#define RS485_CTRL_TX() Gpio_SetIO(RS485_CTRL_PORT, RS485_CTRL_PIN)
+#endif
+
+
+#define FLASH_SECTOR_SIZE 0x200ul
+#define FLASH_BASE ((uint32_t)0x00000000)
+#define FLASH_SIZE (230u * FLASH_SECTOR_SIZE)
+
+
+#define SRAM_BASE ((uint32_t)0x20000000)
+#define RAM_SIZE 0x4000ul
+
+
+#define BOOT_SIZE (20 * FLASH_SECTOR_SIZE)
+#define APP_ADDRESS (0x2A00)//(FLASH_BASE + BOOT_SIZE)
+
+#define BOOT_PARA_ADDRESS (0x0001FC00)
+#define BOOT_PARA_SIZE (FLASH_SECTOR_SIZE)
+
+#define DEBUG 1
+#define USE_LOWPOWER 0
+#define USE_WDT 1
+
+//#define WAKEUP_TIME_ARR (65536 - (30 * 150)) //65536 - time * 38400Hz / 256Ƶ
+
+#define SYSCLK_RCH 0
+#define SYSCLK_XTH 1
+#define SYSCLK_PLL 2
+
+#define SYSCLK SYSCLK_RCH
+
+typedef struct {
+ uint32_t AppFlag;
+ uint32_t UpdateFlag;
+ uint32_t PackageCnt;
+ uint32_t AppSize;
+ uint32_t Crc32Check;
+}BootPara_t, *BootPara;
+
+typedef void (*ReadPara)(BootPara_t rPara);
+typedef void (*SavPara)(BootPara_t wPara);
+typedef void (*UartSend)(uint8_t *sData, int sLen);
+typedef void (*DataRevCallBack)(uint8_t *rData, uint8_t rLen);
+
+void BspInit(void);
+void DBGUartSendByte(uint8_t sData);
+void DBGUartSend(uint8_t *sData, int sLen);
+
+void ReadBootPara(BootPara rData);
+void WriteBootPara(BootPara wData);
+void EraseFlash(void);
+
+uint32_t GetSysTick(void);
+void delay_ms(uint32_t ms);
+void Delay(uint8_t time);
+void FeedDog(void);
+void SystemReset(void);
+#endif
diff --git a/source/inc/main.h b/source/inc/main.h
new file mode 100644
index 0000000..824f8f7
--- /dev/null
+++ b/source/inc/main.h
@@ -0,0 +1,75 @@
+#ifndef __MAIN_H
+#define __MAIN_H
+#include "bsp.h"
+#include "UartDebug.h"
+
+#define CRC16_BASE 0xA001
+
+#define APP_START_FLAG 0x55AA5A5A
+#define APP_UPDATE_FLAG 0xA5A5AA55
+
+typedef enum {
+ UPDATE_CMD_NULL,
+ UPDATE_CMD_SLAVE_RES, //ӻӦ·
+ UPDATE_CMD_SLAVE_REQ_DATA, //ӻ·
+ UPDATE_CMD_MASTER_REQ = 0x81, //
+ UPDATE_CMD_MASTRE_RES_DATA, //
+}UpdateCmd_m;
+
+//֡ͷṹ
+typedef struct {
+ uint8_t Header;
+ uint8_t DevMac[6];
+ uint8_t Cmd;
+ uint8_t PayloadLen;
+}__attribute__ ((packed))FrameHeader_t, *FrameH;
+
+//·غɽṹ
+typedef struct {
+ uint16_t PackageNum;
+ uint32_t AppSize;
+ uint32_t AppCrc32;
+}__attribute__ ((packed))UpDataRequset_t, *UDReq;
+
+//ӻ·ṹ
+typedef struct {
+ uint16_t PackageIndex;
+ uint32_t PackageNum;
+}__attribute__ ((packed))GetDataRequest_t, *GDReq;
+
+//Ӧ·ݽṹ
+typedef struct {
+ uint16_t PackageIndex;
+ uint16_t PackageNum;
+ uint8_t DataLen;
+}__attribute__ ((packed))DownResponse_t, *DownRes;
+
+typedef enum {
+ BL_IDLE,
+ BL_ERASE_FLASH,
+ BL_GET_DATA,
+ BL_WAIT_REV,
+ BL_GET_DATA_TIMEOUT,
+ BL_START_APP,
+ BL_RESET
+}BootStatus_m;
+
+typedef struct {
+ BootPara_t Para;
+ BootStatus_m Status;
+
+ uint32_t AppPackageCnt;
+ uint32_t AppPackageIdx;
+ uint32_t RevErrCnt;
+
+ uint32_t FeedDogDlyCnt;
+ uint32_t BootLoader1mSDlyCnt;
+
+ bool RxFlag;
+ uint32_t UartRevTimeOutCnt;
+ uint8_t RxBuff[260];
+ uint16_t RxLen;
+ uint16_t UpDateFlag;
+}BootLoader_t;
+
+#endif
\ No newline at end of file
diff --git a/source/src/bsp.c b/source/src/bsp.c
new file mode 100644
index 0000000..5866afd
--- /dev/null
+++ b/source/src/bsp.c
@@ -0,0 +1,315 @@
+#include "sysctrl.h"
+#include "gpio.h"
+#include "flash.h"
+#include "bsp.h"
+#include "lpuart.h"
+#include "bt.h"
+#include "wdt.h"
+
+extern void DebugUartIRQ(uint8_t Data);
+extern void BleIRQHandler(uint8_t rData);
+extern void SysTick_CallBack(void);
+extern void KeyIRQHandler(void);
+
+static __IO uint32_t SysTickCnt = 0;
+static __IO bool LpUart0_Tx_Flag;
+
+#define WAKEUP_TIME_ARR 1000
+#define USE_RCL_TRIM 0
+#define DBG_LOG(...)
+
+#if (SYSCLK == SYSCLK_RCH)
+
+static void SystemClkInit(en_sysctrl_rch_freq_t enRchFreq)
+{
+ ///< RCHʱӲͬƵʵлҪȽʱлRCL
+ Sysctrl_SetRCLTrim(SysctrlRclFreq32768);
+ Sysctrl_SetRCLStableTime(SysctrlRclStableCycle64);
+ Sysctrl_ClkSourceEnable(SysctrlClkRCL, TRUE);
+ Sysctrl_SysClkSwitch(SysctrlClkRCL);
+
+ ///< ĿƵʵRCHTRIMֵ
+ Sysctrl_SetRCHTrim(enRchFreq);
+ ///< ʹRCH
+ Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE);
+ ///< ʱлRCH
+ Sysctrl_SysClkSwitch(SysctrlClkRCH);
+
+ ///< HCLK24M˴FLASHȴΪ0 cycle
+ Flash_WaitCycle(FlashWaitCycle0);
+}
+
+#elif (SYSCLK == SYSCLK_XTH)
+
+static void SystemClkInit(en_sysctrl_xth_freq_t enXthFreq)
+{
+ ///<======================== лXTH32MHz ==============================
+ ///< ʹõʱԴHCLK24MFLASH ȴΪ1 cycle(ĬֵҲΪ1 cycle)
+ if(SysctrlXthFreq24_32MHz == enXthFreq)
+ {
+ Flash_WaitCycle(FlashWaitCycle1);
+ }
+
+ ///< лʱǰⲿپXTHƵʷΧ,þʹĿʱӣ˴ΪSYSTEM_XTH = 32MHz
+ Sysctrl_SetXTHFreq(enXthFreq);
+ Sysctrl_XTHDriverCfg(SysctrlXtalDriver3);
+ Sysctrl_SetXTHStableTime(SysctrlXthStableCycle16384);
+ Sysctrl_ClkSourceEnable(SysctrlClkXTH, TRUE);
+ delay1ms(10);
+ Sysctrl_SysClkSwitch(SysctrlClkXTH);
+
+ if(SysctrlXthFreq24_32MHz != enXthFreq)
+ {
+ Flash_WaitCycle(FlashWaitCycle0);
+ }
+ //M0P_SYSCTRL->SYSCTRL0_f.WAKEUP_BYRCH = 0; //ѱԭʱ
+}
+
+#elif (SYSCLK == SYSCLK_PLL)
+///<עⲿúꡪ[SYSTEM_XTH],ʹPLLXTHС24MHz
+static void SystemClkInit(void)
+{
+ stc_sysctrl_pll_cfg_t stcPLLCfg;
+
+ ///< лʱǰⲿپXTHƵʷΧ,þʹĿʱӣ˴ΪSYSTEM_XTH = 32MHz
+// Sysctrl_SetXTHFreq(SysctrlXthFreq4_8MHz);
+// Sysctrl_XTHDriverCfg(SysctrlXtalDriver3);
+// Sysctrl_SetXTHStableTime(SysctrlXthStableCycle16384);
+// Sysctrl_ClkSourceEnable(SysctrlClkXTH, TRUE);
+ Sysctrl_SetRCHTrim(SysctrlRchFreq8MHz);
+ Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE);
+
+ delay1ms(10);
+
+ stcPLLCfg.enInFreq = SysctrlPllInFreq6_12MHz; //XTH 8MHz
+ stcPLLCfg.enOutFreq = SysctrlPllOutFreq36_48MHz; //PLL
+ stcPLLCfg.enPllClkSrc = SysctrlPllRch; //ʱԴѡRCH
+ stcPLLCfg.enPllMul = SysctrlPllMul6; //8MHz x 6 = 48MHz
+ Sysctrl_SetPLLFreq(&stcPLLCfg);
+
+ ///< ʹõʱԴHCLK24MFLASH ȴΪ1 cycle(ĬֵҲΪ1 cycle)
+ Flash_WaitCycle(FlashWaitCycle1);
+
+ ///< ʹPLL
+ Sysctrl_ClkSourceEnable(SysctrlClkPLL, TRUE);
+ ///< ʱлPLL
+ Sysctrl_SysClkSwitch(SysctrlClkPLL);
+
+}
+#endif
+
+static void SystemRCLInit(void)
+{
+ Sysctrl_SetRCLTrim(SysctrlRclFreq38400); ///< RCLʱΪ32kHz
+ Sysctrl_SetRCLStableTime(SysctrlRclStableCycle256);
+ Sysctrl_ClkSourceEnable(SysctrlClkRCL, TRUE); ///< ʹRCLʱ
+}
+
+static void LPUartInit(void)
+{
+ stc_gpio_cfg_t stcGpioCfg;
+ stc_lpuart_cfg_t stcCfg;
+ DDL_ZERO_STRUCT(stcGpioCfg);
+
+ Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio,TRUE);
+
+ /// 0) {
+ dlyCnt--;
+ if(LpUart0_Tx_Flag)
+ break;
+ }
+ }
+ RS485_CTRL_RX();
+}
+
+#if(LP_UART_CH == 0)
+void LpUart0_IRQHandler(void)
+{
+ if(LPUart_GetStatus(LPUART, LPUartTC)) {
+ LPUart_ClrStatus(LPUART, LPUartTC); ///<巢ж
+ LpUart0_Tx_Flag = true;
+ }
+
+ if(LPUart_GetStatus(LPUART, LPUartRC)) { ///
+ LPUart_ClrStatus(LPUART, LPUartRC); ///<ж
+ uint8_t u8RxData = LPUart_ReceiveData(LPUART); ///ȡ
+ DebugUartIRQ(u8RxData);
+ }
+}
+#else
+void LpUart1_IRQHandler(void)
+{
+ if(LPUart_GetStatus(LPUART, LPUartTC)) {
+ LPUart_ClrStatus(LPUART, LPUartTC); ///<巢ж
+ LpUart0_Tx_Flag = true;
+ }
+
+ if(LPUart_GetStatus(LPUART, LPUartRC)) { ///
+ LPUart_ClrStatus(LPUART, LPUartRC); ///<ж
+ uint8_t u8RxData = LPUart_ReceiveData(LPUART); ///ȡ
+ DebugUartIRQ(u8RxData);
+ }
+}
+#endif
+
+static void GPIOInit(void)
+{
+ stc_gpio_cfg_t GpioInitStruct;
+
+ DDL_ZERO_STRUCT(GpioInitStruct);
+ Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio,TRUE);
+
+ GpioInitStruct.enDir = GpioDirOut; ///< ˿ڷ->
+ GpioInitStruct.enDrv = GpioDrvH; ///< ˿->
+ GpioInitStruct.enPu = GpioPuDisable; ///< ˿->
+ GpioInitStruct.enPd = GpioPdDisable;
+ GpioInitStruct.enOD = GpioOdDisable; ///< ˿ڿ©->©ر
+ GpioInitStruct.enCtrlMode = GpioAHB; ///< ˿/ֵĴ߿ģʽ->AHB
+ GpioInitStruct.bOutputVal = false;
+
+ Gpio_Init(RS485_CTRL_PORT, RS485_CTRL_PIN, &GpioInitStruct);
+ RS485_CTRL_RX();
+}
+
+static void WdtInit(void)
+{
+#if (USE_WDT == 1)
+ ///< WDTʱ
+ Sysctrl_SetPeripheralGate(SysctrlPeripheralWdt,TRUE);
+ ///< WDT ʼ
+ Wdt_Init(WdtResetEn, WdtT52s4);
+ Wdt_Start();
+#endif
+}
+
+static void FlashWrite(uint32_t *wData, uint8_t wLen)
+{
+ while(Ok != Flash_SectorErase(BOOT_PARA_ADDRESS));
+ for(int i = 0; i < wLen / 4; i++) {
+ Flash_WriteWord(BOOT_PARA_ADDRESS + i * 4, wData[i]);
+ }
+}
+
+static void FlashRead(uint32_t *rData, uint8_t rLen)
+{
+ uint32_t u32Addr = BOOT_PARA_ADDRESS;
+ for(int i = 0; i < rLen / 4; i++) {
+ rData[i] = *((volatile uint32_t*)(u32Addr + i * 4));
+ }
+}
+
+
+void FeedDog(void)
+{
+#if (USE_WDT == 1)
+ Wdt_Feed();
+#endif
+}
+
+
+uint32_t GetSysTick(void)
+{
+ return SysTickCnt;
+}
+
+void Delay(uint8_t time)
+{
+ while(time > 0) {
+ time --;
+ }
+}
+
+void delay_ms(uint32_t mS)
+{
+ volatile uint32_t cTick, mTick;
+
+ cTick = GetSysTick();
+ while(1){
+ mTick = GetSysTick();
+ if(mTick - cTick >= mS)
+ break;
+ }
+}
+
+void SystemReset(void)
+{
+ NVIC_SystemReset();
+}
+
+void BspInit(void)
+{
+ //SystemClkInit(SysctrlXthFreq4_8MHz);
+ SystemClkInit(SysctrlRchFreq16MHz);
+ SystemCoreClockUpdate();
+ SysTick_Config(SystemCoreClock/1000);
+ SystemRCLInit();
+ GPIOInit();
+ LPUartInit();
+ while(Ok != Flash_Init(4, TRUE));
+ WdtInit();
+}
+
+void SysTick_IRQHandler(void)
+{
+ SysTickCnt++;
+ SysTick_CallBack();
+}
+
+
+void ReadBootPara(BootPara rData)
+{
+ FlashRead((uint32_t *)rData, sizeof(BootPara_t));
+}
+
+void WriteBootPara(BootPara wData)
+{
+ FlashWrite((uint32_t *)wData, sizeof(BootPara_t));
+}
+
+void EraseFlash(void)
+{
+ for(int Addr = APP_ADDRESS; Addr < FLASH_SIZE; Addr += FLASH_SECTOR_SIZE) {
+ Flash_SectorErase(Addr);
+ }
+}
diff --git a/source/src/main.c b/source/src/main.c
new file mode 100644
index 0000000..f4e5548
--- /dev/null
+++ b/source/src/main.c
@@ -0,0 +1,324 @@
+
+/******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include
+#include "main.h"
+//#include "lis2hh12_app.h"
+#include "flash.h"
+
+//设备唯一编码，固定在0x00002800位置
+const uint8_t DevMac[6] __attribute__((section(".ARM.__at_0x00002800"))) = {DEVICE_TYPE & 0xFF, (DEVICE_TYPE >> 8) & 0xFF, COMM_WAY, (ADD_NUMBER >> 16) & 0xFF, (ADD_NUMBER >> 8) & 0xFF, ADD_NUMBER & 0xFF};
+//const uint8_t DevMac[6] __attribute__((at(DEV_MAC_ADDRESS)))= {0x19, 0x00, 0x02, 0x00, 0x00, 0x01};
+uint32_t pdwCrc32Tbl[256];
+
+void InitCrc32Table(uint32_t* Crc32Tbl)
+{
+ for (int wCnt = 0; wCnt!= 256; wCnt++){
+ uint32_t dwCrc = wCnt;
+ for (int ucCnt = 0; ucCnt != 8; ucCnt++){
+ if (dwCrc & 1){
+ dwCrc = (dwCrc >> 1) ^ 0xEDB88320;
+ }
+ else{
+ dwCrc >>= 1;
+ }
+ }
+ Crc32Tbl[wCnt] = dwCrc;
+ }
+}
+
+uint32_t GetCrc32(int dwLen)
+{
+ uint32_t Data;
+ uint32_t dwCrc32Data = 0xFFFFFFFF;
+ for (int dwCnt = 0; dwCnt!= dwLen; ++dwCnt){
+ Data = *((volatile uint8_t*)(APP_ADDRESS + dwCnt));
+ uint32_t dwTbl = (dwCrc32Data ^ Data) & 0xFF;
+ dwCrc32Data = ((dwCrc32Data >> 8) & 0xFFFFFF) ^ pdwCrc32Tbl[dwTbl];
+ }
+ return ~dwCrc32Data;
+}
+
+uint16_t CRC_Modbus(uint16_t wBase, __IO uint8_t *para, uint16_t length)
+{
+ uint16_t crc = 0xffff;
+
+ uint16_t index,i;
+
+ for(index = 0 ; index < length;index++) {
+ crc ^= para[index];
+ for(i = 0; i < 8; i++) {
+ if(crc & 1) {
+ crc >>= 1;
+ crc ^= wBase;
+ }
+ else
+ crc >>= 1;
+ }
+ }
+ return crc;
+}
+
+uint32_t JumpAddress;
+func_ptr_t JumpToApplication;
+BootLoader_t BL;
+
+static void BootLoader1mSRoutine(void)
+{
+ if(BL.BootLoader1mSDlyCnt)
+ BL.BootLoader1mSDlyCnt--;
+
+ if(BL.UartRevTimeOutCnt > 0)
+ BL.UartRevTimeOutCnt--;
+
+ BL.FeedDogDlyCnt++;
+}
+
+void FeedDogHandler(void)
+{
+ if(BL.FeedDogDlyCnt >= 200) {
+ FeedDog();
+ BL.FeedDogDlyCnt = 0;
+ }
+}
+
+void AppWriteFlash(uint32_t AddrOffset, uint8_t *wData, int wLen)
+{
+ for(int i = 0; i < wLen; i++) {
+ Flash_WriteByte(APP_ADDRESS + AddrOffset + i, wData[i]);
+ }
+}
+
+static bool JumpToApp(uint32_t AppAddr)
+{
+ uint32_t u32StackTop = *((__IO uint32_t *)AppAddr);
+
+ if ((u32StackTop > SRAM_BASE) && (u32StackTop <= (SRAM_BASE + RAM_SIZE))) {
+ JumpAddress = *(__IO uint32_t *)(AppAddr + 4);
+ JumpToApplication = (func_ptr_t)JumpAddress;
+ __set_MSP(*(__IO uint32_t *)AppAddr);
+ JumpToApplication();
+ }
+ return Error;
+}
+
+void SendGetCmd(uint8_t Cmd, uint16_t PayLoad)
+{
+ uint8_t sData[20], sLen;
+ uint16_t crc16;
+
+ FrameH Frame = (FrameH)sData;
+
+ Frame->Header = 0x7d;
+ memcpy(Frame->DevMac, DevMac, 6);
+ Frame->Cmd = Cmd & 0x7F;
+
+ if(Frame->Cmd == UPDATE_CMD_SLAVE_RES) {
+ Frame->PayloadLen = 1;
+ sData[sizeof(FrameHeader_t)] = PayLoad;
+ }
+ else if(Frame->Cmd == UPDATE_CMD_SLAVE_REQ_DATA) {
+ Frame->PayloadLen = 4;
+ GDReq GDData = (GDReq)&sData[sizeof(FrameHeader_t)];
+ GDData->PackageIndex = PayLoad;
+ GDData->PackageNum = BL.AppPackageCnt;
+ }
+ sLen = sizeof(FrameHeader_t) + Frame->PayloadLen;
+ crc16 = CRC_Modbus(CRC16_BASE, sData, sLen);
+ sData[sLen++] = crc16;
+ sData[sLen++] = (crc16 >> 8) & 0x00ff;
+
+ DBGUartSend(sData, sLen);
+}
+
+bool AnalyzeData(uint8_t *rData, uint16_t rLen)
+{
+ uint16_t crc16, check;
+
+ check = CRC_Modbus(CRC16_BASE, rData, rLen - 2);
+ crc16 = (rData[rLen - 1] << 8) | rData[rLen - 2];
+
+ if(check != crc16) {
+ return false;
+ }
+
+ FrameH Frame = (FrameH)rData;
+ int ret = memcmp(Frame->DevMac, DevMac, 6);
+ if(ret != 0)
+ return false;
+
+ if(Frame->Cmd == UPDATE_CMD_MASTER_REQ) {
+ UDReq UpData = (UDReq)&rData[sizeof(FrameHeader_t)];
+ BL.Para.AppFlag = 0;
+ BL.Para.UpdateFlag = APP_UPDATE_FLAG;
+ BL.Para.Crc32Check = UpData->AppCrc32;
+ BL.Para.PackageCnt = UpData->PackageNum;
+ BL.Para.AppSize = UpData->AppSize;
+ WriteBootPara(&BL.Para);
+ BL.BootLoader1mSDlyCnt = 20;
+ BL.Status = BL_RESET;
+ SendGetCmd(UPDATE_CMD_SLAVE_RES, 1);
+ }
+ else if(Frame->Cmd == UPDATE_CMD_MASTRE_RES_DATA) {
+ if(BL.UpDateFlag == false)
+ return false;
+ DownRes DownData = (DownRes)&rData[sizeof(FrameHeader_t)];
+ if(BL.AppPackageIdx != DownData->PackageIndex) {
+ return false;
+ }
+ AppWriteFlash(BL.AppPackageIdx * 200, &BL.RxBuff[sizeof(FrameHeader_t) + sizeof(DownResponse_t)], DownData->DataLen);
+ BL.AppPackageIdx++;
+ BL.RevErrCnt = 0;
+ if(BL.AppPackageIdx < BL.AppPackageCnt) {
+ BL.Status = BL_GET_DATA;
+ BL.BootLoader1mSDlyCnt = 5;
+ }
+ else {
+ uint32_t crc32 = GetCrc32(BL.Para.AppSize);
+ if(crc32 == BL.Para.Crc32Check) {
+ BL.Status = BL_START_APP;
+ BL.Para.AppFlag = 0; //升级成功首次启动时，把APP启动标志清除，由APP置位，下次启动便按标志启动
+ BL.Para.UpdateFlag = 0;
+ WriteBootPara(&BL.Para);
+ }
+ }
+ }
+ else
+ return false;
+ return true;
+}
+
+void BootLoaderLoopHandler(void)
+{
+ if(BL.RxFlag) {
+ BL.RxFlag = false;
+ AnalyzeData(BL.RxBuff, BL.RxLen);
+ }
+
+ switch(BL.Status) {
+ case BL_IDLE:
+ break;
+
+ case BL_RESET:
+ if(BL.BootLoader1mSDlyCnt > 0) {
+ break;
+ }
+ SystemReset();
+ break;
+
+ case BL_START_APP:
+ JumpToApp(APP_ADDRESS);
+ break;
+
+ case BL_ERASE_FLASH:
+ FeedDog();
+ EraseFlash();
+ FeedDog();
+ BL.Status = BL_GET_DATA;
+ BL.BootLoader1mSDlyCnt = 200;
+ BL.AppPackageCnt = BL.Para.PackageCnt;
+ BL.RevErrCnt = 0;
+ BL.UpDateFlag = true;
+ break;
+
+ case BL_GET_DATA:
+ if(BL.BootLoader1mSDlyCnt > 0)
+ break;
+ SendGetCmd(UPDATE_CMD_MASTRE_RES_DATA, BL.AppPackageIdx);
+ BL.Status = BL_WAIT_REV;
+ BL.BootLoader1mSDlyCnt = 500;
+ break;
+
+ case BL_WAIT_REV:
+ if(BL.BootLoader1mSDlyCnt == 0) {
+ BL.Status = BL_GET_DATA_TIMEOUT;
+ }
+ break;
+
+ case BL_GET_DATA_TIMEOUT:
+ BL.RevErrCnt++;
+ if(BL.RevErrCnt < 3) {
+ BL.Status = BL_GET_DATA;
+ }
+ else {
+ BL.Status = BL_IDLE;
+ BL.Para.AppFlag = 0;
+ BL.RevErrCnt = 0;
+ BL.Para.UpdateFlag = 0;
+ WriteBootPara(&BL.Para);
+ BL.UpDateFlag = false;
+ }
+ break;
+ }
+}
+
+int32_t main(void)
+{
+ BspInit();
+ InitCrc32Table(pdwCrc32Tbl);
+
+ ReadBootPara(&BL.Para);
+ if(BL.Para.AppFlag == APP_START_FLAG) {
+ BL.Status = BL_START_APP;
+ }
+ else if(BL.Para.UpdateFlag == APP_UPDATE_FLAG) {
+ BL.Status = BL_ERASE_FLASH;
+ }
+ while (1) {
+ FeedDogHandler();
+ BootLoaderLoopHandler();
+ }
+}
+
+
+/*******************************************************************************
+ * 中断服务函数
+ ******************************************************************************/
+void SysTick_CallBack(void)
+{
+ BootLoader1mSRoutine();
+}
+
+void DebugUartIRQ(uint8_t RxData)
+{
+ static uint16_t rLen = 0;
+ static uint8_t rBuff[300];
+ static bool Header = false;
+ static uint16_t PayLen = 0;
+
+ if(BL.UartRevTimeOutCnt == 0) {
+ Header = false;
+ rLen = 0;
+ PayLen = 0;
+ }
+ BL.UartRevTimeOutCnt = 3;
+
+ if(Header == false && (RxData == 0x7d)) {
+ Header = true;
+ rLen = 0;
+ PayLen = 0;
+ rBuff[rLen++] = RxData;
+ }
+ else {
+ rBuff[rLen++] = RxData;
+ if(rLen == 9) {
+ PayLen = RxData;
+ if(PayLen > 256) {
+ Header = false;
+ return;
+ }
+ }
+ else if(rLen == sizeof(FrameHeader_t) + PayLen + 2) {
+ BL.RxLen = rLen;
+ memcpy(BL.RxBuff, rBuff, BL.RxLen);
+ BL.RxFlag = true;
+ Header = false;
+ }
+ }
+}
+
+//void KeyIRQHandler(void)
+//{
+//
+//}