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Lora中心频率改为470.1MHz~492.6MHz, 500kHz步进共46个信道(CH0~CH45)

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YuanHongbin
2026-09-02 10:02:50 +08:00
parent 0d87d716ee
commit 46e5d0a4bd
1 changed files with 48 additions and 13 deletions
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source/User/Inc/bsp.h
+48 -13
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@@ -43,19 +43,54 @@ typedef enum {
#define CUCH_LORA (1 << CH_LORA)
#define CUCH_CAT1 (1 << CH_CAT1)
/*Lora频率：433100000ul + 200000*N，用于配置Lora频率更方便*/
/*Lora频率：470100000ul + 500000*N，N=0~45，共46个信道(470.1MHz~492.6MHz)，用于配置Lora频率更方便*/
typedef enum {
CH0 = (433100000ul + 0), //测试频率
CH1 = (433100000ul + 200000),
CH2 = (433100000ul + 400000),
CH3 = (433100000ul + 600000),
CH4 = (433100000ul + 800000),
CH5 = (433100000ul + 1000000),
CH6 = (433100000ul + 1200000),
CH7 = (433100000ul + 1400000),
CH8 = (433100000ul + 1600000),
CH9 = (433100000ul + 1800000),
CH10 = (433100000ul + 2000000),
CH0 = (470100000ul + 0), //470.1MHz
CH1 = (470100000ul + 500000),
CH2 = (470100000ul + 1000000),
CH3 = (470100000ul + 1500000),
CH4 = (470100000ul + 2000000),
CH5 = (470100000ul + 2500000),
CH6 = (470100000ul + 3000000),
CH7 = (470100000ul + 3500000),
CH8 = (470100000ul + 4000000),
CH9 = (470100000ul + 4500000),
CH10 = (470100000ul + 5000000),
CH11 = (470100000ul + 5500000),
CH12 = (470100000ul + 6000000),
CH13 = (470100000ul + 6500000),
CH14 = (470100000ul + 7000000),
CH15 = (470100000ul + 7500000),
CH16 = (470100000ul + 8000000),
CH17 = (470100000ul + 8500000),
CH18 = (470100000ul + 9000000),
CH19 = (470100000ul + 9500000),
CH20 = (470100000ul + 10000000),
CH21 = (470100000ul + 10500000),
CH22 = (470100000ul + 11000000),
CH23 = (470100000ul + 11500000),
CH24 = (470100000ul + 12000000),
CH25 = (470100000ul + 12500000),
CH26 = (470100000ul + 13000000),
CH27 = (470100000ul + 13500000),
CH28 = (470100000ul + 14000000),
CH29 = (470100000ul + 14500000),
CH30 = (470100000ul + 15000000),
CH31 = (470100000ul + 15500000),
CH32 = (470100000ul + 16000000),
CH33 = (470100000ul + 16500000),
CH34 = (470100000ul + 17000000),
CH35 = (470100000ul + 17500000),
CH36 = (470100000ul + 18000000),
CH37 = (470100000ul + 18500000),
CH38 = (470100000ul + 19000000),
CH39 = (470100000ul + 19500000),
CH40 = (470100000ul + 20000000),
CH41 = (470100000ul + 20500000),
CH42 = (470100000ul + 21000000),
CH43 = (470100000ul + 21500000),
CH44 = (470100000ul + 22000000),
CH45 = (470100000ul + 22500000), //492.6MHz
}LORA_FREQ_M;
/*当前设备版本/项目选择*/
@@ -70,7 +105,7 @@ typedef enum {
#define GATEWAY_SVR_ADDR3 147 //服务器IP[3]
#define GATEWAY_SVR_PORT 8080 //服务器端口
#define GATEWAY_LORA_FREQ CH3 //Lora中心频率(可配置为CH0~CH10)
#define GATEWAY_LORA_FREQ CH3 //Lora中心频率(可配置为CH0~CH45)
/*默认通道配置 - 在Boot中直接配置, 替代原APP硬编码默认值*/
#define GATEWAY_MUCH CH_ETH //主上传通道