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feat(lora): Lora中心频率改用CH0~CH10枚举配置, GATEWAY_LORA_FREQ默认CH0

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YuanHongbin
2026-09-01 11:14:37 +08:00
parent 8c1deedbe1
commit 0d87d716ee
1 changed files with 1 additions and 1 deletions
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source/User/Inc/bsp.h
+1 -1
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@@ -63,7 +63,7 @@ typedef enum {
#define GATEWAY_PRJ_NUM GATEWAY_PRJ_YAXIA //项目编号 #define GATEWAY_PRJ_NUM GATEWAY_PRJ_YAXIA //项目编号
#define GATEWAY_GW_NUM 0x0000 //网关编号(2字节, 1~65535) #define GATEWAY_GW_NUM 0x0000 //网关编号(2字节, 1~65535)
/*默认服务器/Lora配置 - 替代原MAC_ADDR_TYPE编译宏, 在Boot中直接配置*/ /*CAT1服务器/Lora配置 - 替代原MAC_ADDR_TYPE编译宏, 在Boot中直接配置*/
#define GATEWAY_SVR_ADDR0 39 //服务器IP[0] #define GATEWAY_SVR_ADDR0 39 //服务器IP[0]
#define GATEWAY_SVR_ADDR1 106 //服务器IP[1] #define GATEWAY_SVR_ADDR1 106 //服务器IP[1]
#define GATEWAY_SVR_ADDR2 103 //服务器IP[2] #define GATEWAY_SVR_ADDR2 103 //服务器IP[2]