初始版本
This commit is contained in:
@@ -0,0 +1,831 @@
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<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@@ -0,0 +1,711 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>Release</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060960::V5.06 update 7 (build 960)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>HC32F460PETB</Device>
|
||||
<Vendor>HDSC</Vendor>
|
||||
<PackID>HDSC.HC32F460.1.0.12</PackID>
|
||||
<PackURL>https://raw.githubusercontent.com/hdscmcu/pack/master/</PackURL>
|
||||
<Cpu>IRAM(0x1FFF8000,0x2F000) IRAM2(0x200F0000,0x1000) IROM(0x00000000,0x80000) IROM2(0x03000C00,0x003FC) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FF1HC32F460_otp -FS13000C00 -FL13FC -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:HC32F460PETB$Device\Include\HC32F460PETB.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:HC32F460PETB$SVD\HC32F460PETB.svd</SFDFile>
|
||||
<bCustSvd>1</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\output\debug\</OutputDirectory>
|
||||
<OutputName>GateWay</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\output\debug\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>1</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>fromelf --bin -o "$L@L.bin" "#L"</UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<nBranchProt>0</nBranchProt>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>1</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1fff8000</StartAddress>
|
||||
<Size>0x2f000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x3000c00</StartAddress>
|
||||
<Size>0x3fc</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1fff8000</StartAddress>
|
||||
<Size>0x2f000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x200f0000</StartAddress>
|
||||
<Size>0x1000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls>--diag_suppress=186,66</MiscControls>
|
||||
<Define>__DEBUG,HC32F460,USE_DEVICE_DRIVER_LIB,JEUA</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\driver\src;..\driver\inc;..\mcu\common;..\source\User\Src;..\source\User\Inc;..\source\Module\Debug;..\source\Module\SDCard;..\source\Module\FatFS\source;..\source\Module\SX127x</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x1FFF8000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>i2c_24c256.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>--keep=*Handler</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>common</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>system_hc32f460.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\mcu\common\system_hc32f460.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>startup_hc32f460.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>.\startup_hc32f460.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>User</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\source\User\Src\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>bsp.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\source\User\Src\bsp.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>driver</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>hc32f460_adc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_adc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_aes.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_aes.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_can.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_can.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_can1.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_can1.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_clk.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_clk.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_cmp.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_cmp.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_crc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_crc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_dcu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_dcu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_dmac.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_dmac.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_efm.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_efm.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_emb.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_emb.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_event_port.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_event_port.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_exint_nmi_swi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_exint_nmi_swi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_hash.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_hash.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_i2c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_i2c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_i2s.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_i2s.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_icg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_icg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_interrupts.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_interrupts.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_keyscan.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_keyscan.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_mpu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_mpu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_ots.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_ots.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_pwc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_pwc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_qspi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_qspi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_rmu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_rmu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_rtc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_rtc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_sdioc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_sdioc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_spi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_spi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_sram.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_sram.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_swdt.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_swdt.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_timer0.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_timer0.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_timer4_cnt.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_timer4_cnt.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_timer4_emb.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_timer4_emb.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_timer4_oco.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_timer4_oco.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_timer4_pwm.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_timer4_pwm.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_timer4_sevt.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_timer4_sevt.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_timer6.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_timer6.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_timera.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_timera.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_trng.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_trng.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_usart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_usart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_utility.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_utility.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hc32f460_wdt.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\driver\src\hc32f460_wdt.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Readme</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.5.0" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Release"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="source" name="FileSystem\Config\FS_Config.c" version="6.3.0">
|
||||
<instance index="0" removed="1">RTE\File_System\FS_Config.c</instance>
|
||||
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN Debug" Cvendor="Keil" Cversion="6.14.1" condition="CMSIS Core with RTOS and File System I/O and Event Recorder"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="FileSystem\Config\FS_Config_MC.h" version="6.2.0">
|
||||
<instance index="0" removed="1">RTE\File_System\FS_Config_MC_0.h</instance>
|
||||
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="Drive" Csub="Memory Card" Cvendor="Keil" Cversion="6.14.1" condition="File System and SD/MMC Driver" maxInstances="2"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="source" name="FileSystem\Config\FS_Debug.c" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\File_System\FS_Debug.c</instance>
|
||||
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN Debug" Cvendor="Keil" Cversion="6.14.1" condition="CMSIS Core with RTOS and File System I/O and Event Recorder"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="source" name="Network\Config\Net_Config.c" version="7.1.0">
|
||||
<instance index="0" removed="1">RTE\Network\Net_Config.c</instance>
|
||||
<component Cbundle="MDK-Plus" Cclass="Network" Cgroup="CORE" Cvariant="IPv4 Release" Cvendor="Keil" Cversion="7.15.0" condition="CMSIS Core with RTOS" isDefaultVariant="1"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="Network\Config\Net_Config_ETH.h" version="7.3.0">
|
||||
<instance index="0" removed="1">RTE\Network\Net_Config_ETH_0.h</instance>
|
||||
<component Cbundle="MDK-Plus" Cclass="Network" Cgroup="Interface" Csub="ETH" Cvendor="Keil" Cversion="7.15.0" condition="Network Driver ETH" maxInstances="2"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="Network\Config\Net_Config_TCP.h" version="7.1.1">
|
||||
<instance index="0" removed="1">RTE\Network\Net_Config_TCP.h</instance>
|
||||
<component Cbundle="MDK-Plus" Cclass="Network" Cgroup="Socket" Csub="TCP" Cvendor="Keil" Cversion="7.15.0" condition="Network Interface"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="source" name="bsp\_template\board.c" version="3.1.5">
|
||||
<instance index="0" removed="1">RTE\RTOS\board.c</instance>
|
||||
<component Cbundle="RT-Thread" Cclass="RTOS" Cgroup="kernel" Cvendor="RealThread" Cversion="3.1.5" condition="CMSIS Core with RTOS"/>
|
||||
<package name="RT-Thread" schemaVersion="1.4" url="https://www.rt-thread.org/download/mdk/" vendor="RealThread" version="3.1.5"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="bsp\_template\rtconfig.h" version="3.1.5">
|
||||
<instance index="0" removed="1">RTE\RTOS\rtconfig.h</instance>
|
||||
<component Cbundle="RT-Thread" Cclass="RTOS" Cgroup="kernel" Cvendor="RealThread" Cversion="3.1.5" condition="CMSIS Core with RTOS"/>
|
||||
<package name="RT-Thread" schemaVersion="1.4" url="https://www.rt-thread.org/download/mdk/" vendor="RealThread" version="3.1.5"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName>GateWay</LayName>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
|
||||
|
||||
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
|
||||
<events>
|
||||
</events>
|
||||
|
||||
</component_viewer>
|
||||
@@ -0,0 +1,35 @@
|
||||
[BREAKPOINTS]
|
||||
ForceImpTypeAny = 0
|
||||
ShowInfoWin = 1
|
||||
EnableFlashBP = 2
|
||||
BPDuringExecution = 0
|
||||
[CFI]
|
||||
CFISize = 0x00
|
||||
CFIAddr = 0x00
|
||||
[CPU]
|
||||
OverrideMemMap = 0
|
||||
AllowSimulation = 1
|
||||
ScriptFile=""
|
||||
[FLASH]
|
||||
CacheExcludeSize = 0x00
|
||||
CacheExcludeAddr = 0x00
|
||||
MinNumBytesFlashDL = 0
|
||||
SkipProgOnCRCMatch = 1
|
||||
VerifyDownload = 1
|
||||
AllowCaching = 1
|
||||
EnableFlashDL = 2
|
||||
Override = 1
|
||||
Device="Cortex-M4"
|
||||
[GENERAL]
|
||||
WorkRAMSize = 0x00
|
||||
WorkRAMAddr = 0x00
|
||||
RAMUsageLimit = 0x00
|
||||
[SWO]
|
||||
SWOLogFile=""
|
||||
[MEM]
|
||||
RdOverrideOrMask = 0x00
|
||||
RdOverrideAndMask = 0xFFFFFFFF
|
||||
RdOverrideAddr = 0xFFFFFFFF
|
||||
WrOverrideOrMask = 0x00
|
||||
WrOverrideAndMask = 0xFFFFFFFF
|
||||
WrOverrideAddr = 0xFFFFFFFF
|
||||
@@ -0,0 +1,78 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::File System
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: FS_Config.c
|
||||
* Purpose: File System Configuration
|
||||
* Rev.: V6.3.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>FAT File System
|
||||
// <i>Define FAT File System parameters
|
||||
|
||||
// <o>Number of open files <1-16>
|
||||
// <i>Define number of files that can be opened at the same time.
|
||||
// <i>Default: 4
|
||||
#define FAT_MAX_OPEN_FILES 4
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Embedded File System
|
||||
// <i>Define Embedded File System parameters
|
||||
|
||||
// <o>Number of open files <1-16>
|
||||
// <i>Define number of files that can be opened at the same time.
|
||||
// <i>Default: 4
|
||||
#define EFS_MAX_OPEN_FILES 4
|
||||
|
||||
// </h>
|
||||
|
||||
// <o>Initial Current Drive <0=>F0: <1=>F1:
|
||||
// <2=>M0: <3=>M1:
|
||||
// <4=>N0: <5=>N1:
|
||||
// <6=>R0: <9=>R1:
|
||||
// <7=>U0: <8=>U1:
|
||||
// <i>Set initial setting for current drive. Current drive is used for File System functions
|
||||
// <i>that are invoked with the "" string and can be altered anytime during run-time.
|
||||
#define FS_INITIAL_CDRIVE 2
|
||||
|
||||
#include "RTE_Components.h"
|
||||
|
||||
#ifdef RTE_FileSystem_Drive_RAM_0
|
||||
#include "FS_Config_RAM_0.h"
|
||||
#endif
|
||||
#ifdef RTE_FileSystem_Drive_RAM_1
|
||||
#include "FS_Config_RAM_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_FileSystem_Drive_NOR_0
|
||||
#include "FS_Config_NOR_0.h"
|
||||
#endif
|
||||
#ifdef RTE_FileSystem_Drive_NOR_1
|
||||
#include "FS_Config_NOR_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_FileSystem_Drive_NAND_0
|
||||
#include "FS_Config_NAND_0.h"
|
||||
#endif
|
||||
#ifdef RTE_FileSystem_Drive_NAND_1
|
||||
#include "FS_Config_NAND_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_FileSystem_Drive_MC_0
|
||||
#include "FS_Config_MC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_FileSystem_Drive_MC_1
|
||||
#include "FS_Config_MC_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_FileSystem_Drive_USB_0
|
||||
#include "FS_Config_USB_0.h"
|
||||
#endif
|
||||
#ifdef RTE_FileSystem_Drive_USB_1
|
||||
#include "FS_Config_USB_1.h"
|
||||
#endif
|
||||
|
||||
#include "fs_config.h"
|
||||
@@ -0,0 +1,55 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::File System:Drive
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: FS_Config_MC_0.h
|
||||
* Purpose: File System Configuration for Memory Card Drive
|
||||
* Rev.: V6.2.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>Memory Card Drive 0
|
||||
// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
|
||||
#define MC0_ENABLE 1
|
||||
|
||||
// <o>Connect to hardware via Driver_MCI# <0-255>
|
||||
// <i>Select driver control block for hardware interface
|
||||
#define MC0_MCI_DRIVER 0
|
||||
|
||||
// <o>Connect to hardware via Driver_SPI# <0-255>
|
||||
// <i>Select driver control block for hardware interface when in SPI mode
|
||||
#define MC0_SPI_DRIVER 0
|
||||
|
||||
// <o>Memory Card Interface Mode <0=>Native <1=>SPI
|
||||
// <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
|
||||
// <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
|
||||
#define MC0_SPI 0
|
||||
|
||||
// <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
||||
// <8=>8 KB <16=>16 KB <32=>32 KB
|
||||
// <i>Drive Cache stores data sectors and may be increased to speed-up
|
||||
// <i>file read/write operations on this drive (default: 4 KB)
|
||||
#define MC0_CACHE_SIZE 4
|
||||
|
||||
// <e>Locate Drive Cache and Drive Buffer
|
||||
// <i>Some microcontrollers support DMA only in specific memory areas and
|
||||
// <i>require to locate the drive buffers at a fixed address.
|
||||
#define MC0_CACHE_RELOC 0
|
||||
|
||||
// <o>Base address <0x0000-0xFFFFFE00:0x200>
|
||||
// <i>Set buffer base address to RAM areas that support DMA with the drive.
|
||||
#define MC0_CACHE_ADDR 0x7FD00000
|
||||
|
||||
// </e>
|
||||
// <o>Filename Cache Size <0-1000000>
|
||||
// <i>Define number of cached file or directory names.
|
||||
// <i>48 bytes of RAM is required for each cached name.
|
||||
#define MC0_NAME_CACHE_SIZE 0
|
||||
|
||||
// <q>Use FAT Journal
|
||||
// <i>Protect File Allocation Table and Directory Entries for
|
||||
// <i>fail-safe operation.
|
||||
#define MC0_FAT_JOURNAL 0
|
||||
|
||||
// </h>
|
||||
@@ -0,0 +1,50 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::File System
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: FS_Debug.c
|
||||
* Purpose: File System Debug Configuration
|
||||
* Rev.: V1.0.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <e>File System Debug
|
||||
// <i>Enable File System event recording
|
||||
#define FS_DEBUG_EVR_ENABLE 0
|
||||
|
||||
// <o>Core Management <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsCore: Core Management event recording
|
||||
#define FS_DEBUG_EVR_CORE 1
|
||||
|
||||
// <o>FAT File System <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsFAT: FAT File System event recording
|
||||
#define FS_DEBUG_EVR_FAT 1
|
||||
|
||||
// <o>EFS File System <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsEFS: EFS File System event recording
|
||||
#define FS_DEBUG_EVR_EFS 1
|
||||
|
||||
// <o>I/O Control Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsIOC: I/O Control Interface event recording
|
||||
#define FS_DEBUG_EVR_IOC 1
|
||||
|
||||
// <o>NAND Flash Translation Layer <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsNFTL: NAND Flash Translation Layer event recording
|
||||
#define FS_DEBUG_EVR_NFTL 1
|
||||
|
||||
// <o>NAND Device Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsNAND: NAND Device Interface event recording
|
||||
#define FS_DEBUG_EVR_NAND 1
|
||||
|
||||
// <o>Memory Card MCI <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsMcMCI: Memory Card MCI event recording
|
||||
#define FS_DEBUG_EVR_MC_MCI 1
|
||||
|
||||
// <o>Memory Card SPI <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsMcSPI: Memory Card SPI event recording
|
||||
#define FS_DEBUG_EVR_MC_SPI 1
|
||||
|
||||
// </e>
|
||||
|
||||
#include "fs_debug.h"
|
||||
@@ -0,0 +1,173 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::Network
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: Net_Config.c
|
||||
* Purpose: Network Configuration
|
||||
* Rev.: V7.1.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>Network System Settings
|
||||
// <i>Global Network System definitions
|
||||
// <s.15>Local Host Name
|
||||
// <i>This is the name under which embedded host can be
|
||||
// <i>accessed on a local area network.
|
||||
// <i>Default: "my_host"
|
||||
#define NET_HOST_NAME "my_host"
|
||||
|
||||
// <o>Memory Pool Size <1536-262144:4>
|
||||
// <i>This is the size of a memory pool in bytes. Buffers for
|
||||
// <i>network packets are allocated from this memory pool.
|
||||
// <i>Default: 12000 bytes
|
||||
#define NET_MEM_POOL_SIZE 12000
|
||||
|
||||
// <q>Start System Services
|
||||
// <i>If enabled, the system will automatically start server services
|
||||
// <i>(HTTP, FTP, TFTP server, ...) when initializing the network system.
|
||||
// <i>Default: Enabled
|
||||
#define NET_START_SERVICE 1
|
||||
|
||||
// <h>OS Resource Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Core Thread Stack Size <512-65535:4>
|
||||
// <i>Default: 1024 bytes
|
||||
#define NET_THREAD_STACK_SIZE 1024
|
||||
|
||||
// Core Thread Priority
|
||||
#define NET_THREAD_PRIORITY osPriorityNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
//------------- <<< end of configuration section >>> ---------------------------
|
||||
|
||||
#include "RTE_Components.h"
|
||||
|
||||
#ifdef RTE_Network_Interface_ETH_0
|
||||
#include "Net_Config_ETH_0.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_Interface_ETH_1
|
||||
#include "Net_Config_ETH_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Interface_WiFi_0
|
||||
#include "Net_Config_WiFi_0.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Interface_WiFi_1
|
||||
#include "Net_Config_WiFi_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Interface_PPP
|
||||
#include "Net_Config_PPP.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Interface_SLIP
|
||||
#include "Net_Config_SLIP.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Socket_UDP
|
||||
#include "Net_Config_UDP.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_Socket_TCP
|
||||
#include "Net_Config_TCP.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_Socket_BSD
|
||||
#include "Net_Config_BSD.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Web_Server_RO
|
||||
#include "Net_Config_HTTP_Server.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_Web_Server_FS
|
||||
#include "Net_Config_HTTP_Server.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Telnet_Server
|
||||
#include "Net_Config_Telnet_Server.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_TFTP_Server
|
||||
#include "Net_Config_TFTP_Server.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_TFTP_Client
|
||||
#include "Net_Config_TFTP_Client.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_FTP_Server
|
||||
#include "Net_Config_FTP_Server.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_FTP_Client
|
||||
#include "Net_Config_FTP_Client.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_DNS_Client
|
||||
#include "Net_Config_DNS_Client.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_SMTP_Client
|
||||
#include "Net_Config_SMTP_Client.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_SNMP_Agent
|
||||
#include "Net_Config_SNMP_Agent.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_SNTP_Client
|
||||
#include "Net_Config_SNTP_Client.h"
|
||||
#endif
|
||||
|
||||
#include "net_config.h"
|
||||
|
||||
/**
|
||||
\addtogroup net_genFunc
|
||||
@{
|
||||
*/
|
||||
/**
|
||||
\fn void net_sys_error (NET_ERROR error)
|
||||
\ingroup net_cores
|
||||
\brief Network system error handler.
|
||||
*/
|
||||
void net_sys_error (NET_ERROR error) {
|
||||
/* This function is called when a fatal error is encountered. */
|
||||
/* The normal program execution is not possible anymore. */
|
||||
|
||||
switch (error) {
|
||||
case NET_ERROR_MEM_ALLOC:
|
||||
/* Out of memory */
|
||||
break;
|
||||
|
||||
case NET_ERROR_MEM_FREE:
|
||||
/* Trying to release non existing memory block */
|
||||
break;
|
||||
|
||||
case NET_ERROR_MEM_CORRUPT:
|
||||
/* Memory Link pointer corrupted */
|
||||
/* More data written than the size of allocated memory block */
|
||||
break;
|
||||
|
||||
case NET_ERROR_CONFIG:
|
||||
/* Network configuration error detected */
|
||||
break;
|
||||
|
||||
case NET_ERROR_UDP_ALLOC:
|
||||
/* Out of UDP Sockets */
|
||||
break;
|
||||
|
||||
case NET_ERROR_TCP_ALLOC:
|
||||
/* Out of TCP Sockets */
|
||||
break;
|
||||
|
||||
case NET_ERROR_TCP_STATE:
|
||||
/* TCP State machine in undefined state */
|
||||
break;
|
||||
}
|
||||
|
||||
/* End-less loop */
|
||||
while (1);
|
||||
}
|
||||
/**
|
||||
@}
|
||||
*/
|
||||
@@ -0,0 +1,253 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::Network:Interface
|
||||
* Copyright (c) 2004-2020 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: Net_Config_ETH_0.h
|
||||
* Purpose: Network Configuration for ETH Interface
|
||||
* Rev.: V7.3.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>Ethernet Network Interface 0
|
||||
#define ETH0_ENABLE 1
|
||||
|
||||
// <o>Connect to hardware via Driver_ETH# <0-255>
|
||||
// <i>Select driver control block for MAC and PHY interface
|
||||
#define ETH0_DRIVER 0
|
||||
|
||||
// <s.17>MAC Address
|
||||
// <i>Ethernet MAC Address in text representation
|
||||
// <i>Value FF-FF-FF-FF-FF-FF is not allowed,
|
||||
// <i>LSB of first byte must be 0 (an ethernet Multicast bit).
|
||||
// <i>Default: "1E-30-6C-A2-45-5E"
|
||||
#define ETH0_MAC_ADDR "1E-30-6C-A2-45-5E"
|
||||
|
||||
// <e>VLAN
|
||||
// <i>Enable or disable Virtual LAN
|
||||
#define ETH0_VLAN_ENABLE 0
|
||||
|
||||
// <o>VLAN Identifier <1-4093>
|
||||
// <i>A unique 12-bit numeric value
|
||||
// <i>Default: 1
|
||||
#define ETH0_VLAN_ID 1
|
||||
// </e>
|
||||
|
||||
// <e>IPv4
|
||||
// <i>Enable IPv4 Protocol for Network Interface
|
||||
#define ETH0_IP4_ENABLE 1
|
||||
|
||||
// <s.15>IP Address
|
||||
// <i>Static IPv4 Address in text representation
|
||||
// <i>Default: "192.168.0.100"
|
||||
#define ETH0_IP4_ADDR "192.168.0.100"
|
||||
|
||||
// <s.15>Subnet mask
|
||||
// <i>Local Subnet mask in text representation
|
||||
// <i>Default: "255.255.255.0"
|
||||
#define ETH0_IP4_MASK "255.255.255.0"
|
||||
|
||||
// <s.15>Default Gateway
|
||||
// <i>IP Address of Default Gateway in text representation
|
||||
// <i>Default: "192.168.0.254"
|
||||
#define ETH0_IP4_GATEWAY "192.168.0.254"
|
||||
|
||||
// <s.15>Primary DNS Server
|
||||
// <i>IP Address of Primary DNS Server in text representation
|
||||
// <i>Default: "8.8.8.8"
|
||||
#define ETH0_IP4_PRIMARY_DNS "8.8.8.8"
|
||||
|
||||
// <s.15>Secondary DNS Server
|
||||
// <i>IP Address of Secondary DNS Server in text representation
|
||||
// <i>Default: "8.8.4.4"
|
||||
#define ETH0_IP4_SECONDARY_DNS "8.8.4.4"
|
||||
|
||||
// <e>IP Fragmentation
|
||||
// <i>This option enables fragmentation of outgoing IP datagrams,
|
||||
// <i>and reassembling the fragments of incoming IP datagrams.
|
||||
// <i>Default: enabled
|
||||
#define ETH0_IP4_FRAG_ENABLE 1
|
||||
|
||||
// <o>MTU size <576-1500>
|
||||
// <i>Maximum Transmission Unit in bytes
|
||||
// <i>Default: 1500
|
||||
#define ETH0_IP4_MTU 1500
|
||||
// </e>
|
||||
|
||||
// <h>ARP Address Resolution
|
||||
// <i>ARP cache and node address resolver settings
|
||||
// <o>Cache Table size <5-100>
|
||||
// <i>Number of cached MAC/IP addresses
|
||||
// <i>Default: 10
|
||||
#define ETH0_ARP_TAB_SIZE 10
|
||||
|
||||
// <o>Cache Timeout in seconds <5-255>
|
||||
// <i>A timeout for cached hardware/IP addresses
|
||||
// <i>Default: 150
|
||||
#define ETH0_ARP_CACHE_TOUT 150
|
||||
|
||||
// <o>Number of Retries <0-20>
|
||||
// <i>Number of Retries to resolve an IP address
|
||||
// <i>before ARP module gives up
|
||||
// <i>Default: 4
|
||||
#define ETH0_ARP_MAX_RETRY 4
|
||||
|
||||
// <o>Resend Timeout in seconds <1-10>
|
||||
// <i>A timeout to resend the ARP Request
|
||||
// <i>Default: 2
|
||||
#define ETH0_ARP_RESEND_TOUT 2
|
||||
|
||||
// <q>Send Notification on Address changes
|
||||
// <i>When this option is enabled, the embedded host
|
||||
// <i>will send a Gratuitous ARP notification at startup,
|
||||
// <i>or when the device IP address has changed.
|
||||
// <i>Default: Disabled
|
||||
#define ETH0_ARP_NOTIFY 0
|
||||
// </h>
|
||||
|
||||
// <e>IGMP Group Management
|
||||
// <i>Enable or disable Internet Group Management Protocol
|
||||
#define ETH0_IGMP_ENABLE 0
|
||||
|
||||
// <o>Membership Table size <2-50>
|
||||
// <i>Number of Groups this host can join
|
||||
// <i>Default: 5
|
||||
#define ETH0_IGMP_TAB_SIZE 5
|
||||
// </e>
|
||||
|
||||
// <q>NetBIOS Name Service
|
||||
// <i>When this option is enabled, the embedded host can be
|
||||
// <i>accessed by its name on local LAN using NBNS protocol.
|
||||
#define ETH0_NBNS_ENABLE 1
|
||||
|
||||
// <e>Dynamic Host Configuration
|
||||
// <i>When this option is enabled, local IP address, Net Mask
|
||||
// <i>and Default Gateway are obtained automatically from
|
||||
// <i>the DHCP Server on local LAN.
|
||||
#define ETH0_DHCP_ENABLE 1
|
||||
|
||||
// <s.40>Vendor Class Identifier
|
||||
// <i>This value is optional. If specified, it is added
|
||||
// <i>to DHCP request message, identifying vendor type.
|
||||
// <i>Default: ""
|
||||
#define ETH0_DHCP_VCID ""
|
||||
|
||||
// <q>Bootfile Name
|
||||
// <i>This value is optional. If enabled, the Bootfile Name
|
||||
// <i>(option 67) is also requested from DHCP server.
|
||||
// <i>Default: disabled
|
||||
#define ETH0_DHCP_BOOTFILE 0
|
||||
|
||||
// <q>NTP Servers
|
||||
// <i>This value is optional. If enabled, a list of NTP Servers
|
||||
// <i>(option 42) is also requested from DHCP server.
|
||||
// <i>Default: disabled
|
||||
#define ETH0_DHCP_NTP_SERVERS 0
|
||||
// </e>
|
||||
|
||||
// Disable ICMP Echo response
|
||||
#define ETH0_ICMP_NO_ECHO 0
|
||||
// </e>
|
||||
|
||||
// <e>IPv6
|
||||
// <i>Enable IPv6 Protocol for Network Interface
|
||||
#define ETH0_IP6_ENABLE 1
|
||||
|
||||
// <s.40>IPv6 Address
|
||||
// <i>Static IPv6 Address in text representation
|
||||
// <i>Use unspecified address "::" when static
|
||||
// <i>IPv6 address is not used.
|
||||
// <i>Default: "fec0::2"
|
||||
#define ETH0_IP6_ADDR "fec0::2"
|
||||
|
||||
// <o>Subnet prefix-length <1-128>
|
||||
// <i>Number of bits that define network address
|
||||
// <i>Default: 64
|
||||
#define ETH0_IP6_PREFIX_LEN 64
|
||||
|
||||
// <s.40>Default Gateway
|
||||
// <i>Default Gateway IPv6 Address in text representation
|
||||
// <i>Default: "fec0::1"
|
||||
#define ETH0_IP6_GATEWAY "fec0::1"
|
||||
|
||||
// <s.40>Primary DNS Server
|
||||
// <i>Primary DNS Server IPv6 Address in text representation
|
||||
// <i>Default: "2001:4860:4860::8888"
|
||||
#define ETH0_IP6_PRIMARY_DNS "2001:4860:4860::8888"
|
||||
|
||||
// <s.40>Secondary DNS Server
|
||||
// <i>Secondary DNS Server IPv6 Address in text representation
|
||||
// <i>Default: "2001:4860:4860::8844"
|
||||
#define ETH0_IP6_SECONDARY_DNS "2001:4860:4860::8844"
|
||||
|
||||
// <h>Neighbor Discovery
|
||||
// <i>Neighbor cache and node address resolver settings
|
||||
// <o>Cache Table size <5-100>
|
||||
// <i>Number of cached node addresses
|
||||
// <i>Default: 5
|
||||
#define ETH0_NDP_TAB_SIZE 5
|
||||
|
||||
// <o>Cache Timeout in seconds <5-255>
|
||||
// <i>Timeout for cached node addresses
|
||||
// <i>Default: 150
|
||||
#define ETH0_NDP_CACHE_TOUT 150
|
||||
|
||||
// <o>Number of Retries <0-20>
|
||||
// <i>Number of retries to resolve an IP address
|
||||
// <i>before NDP module gives up
|
||||
// <i>Default: 4
|
||||
#define ETH0_NDP_MAX_RETRY 4
|
||||
|
||||
// <o>Resend Timeout in seconds <1-10>
|
||||
// <i>A timeout to resend Neighbor Solicitation
|
||||
// <i>Default: 2
|
||||
#define ETH0_NDP_RESEND_TOUT 2
|
||||
// </h>
|
||||
|
||||
// <e>Dynamic Host Configuration
|
||||
// <i>When this option is enabled, local IPv6 address is
|
||||
// <i>automatically configured.
|
||||
#define ETH0_DHCP6_ENABLE 1
|
||||
|
||||
// <o>DHCPv6 Client Mode <0=>Stateless Mode <1=>Statefull Mode
|
||||
// <i>Stateless DHCPv6 Client uses router advertisements
|
||||
// <i>for IPv6 address autoconfiguration (SLAAC).
|
||||
// <i>Statefull DHCPv6 Client connects to DHCPv6 server for a
|
||||
// <i>leased IPv6 address and DNS server IPv6 addresses.
|
||||
#define ETH0_DHCP6_MODE 1
|
||||
|
||||
// <e>Vendor Class Option
|
||||
// <i>If enabled, Vendor Class option is added to DHCPv6
|
||||
// <i>request message, identifying vendor type.
|
||||
// <i>Default: disabled
|
||||
#define ETH0_DHCP6_VCLASS_ENABLE 0
|
||||
|
||||
// <o>Enterprise ID
|
||||
// <i>Enterprise-number as registered with IANA.
|
||||
// <i>Default: 0 (Reserved)
|
||||
#define ETH0_DHCP6_VCLASS_EID 0
|
||||
|
||||
// <s.40>Vendor Class Data
|
||||
// <i>This string identifies vendor type.
|
||||
// <i>Default: ""
|
||||
#define ETH0_DHCP6_VCLASS_DATA ""
|
||||
// </e>
|
||||
// </e>
|
||||
|
||||
// Disable ICMP6 Echo response
|
||||
#define ETH0_ICMP6_NO_ECHO 0
|
||||
// </e>
|
||||
|
||||
// <h>OS Resource Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Interface Thread Stack Size <512-65535:4>
|
||||
// <i>Default: 512 bytes
|
||||
#define ETH0_THREAD_STACK_SIZE 512
|
||||
|
||||
// Interface Thread Priority
|
||||
#define ETH0_THREAD_PRIORITY osPriorityAboveNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
//------------- <<< end of configuration section >>> ---------------------------
|
||||
@@ -0,0 +1,69 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::Network:Socket
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: Net_Config_TCP.h
|
||||
* Purpose: Network Configuration for TCP Sockets
|
||||
* Rev.: V7.1.1
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>TCP Sockets
|
||||
#define TCP_ENABLE 1
|
||||
|
||||
// <o>Number of TCP Sockets <1-20>
|
||||
// <i>Number of available TCP sockets
|
||||
// <i>Default: 6
|
||||
#define TCP_NUM_SOCKS 6
|
||||
|
||||
// <o>Number of Retries <0-20>
|
||||
// <i>How many times TCP module will try to retransmit data
|
||||
// <i>before giving up. Increase this value for high-latency
|
||||
// <i>and low throughput networks.
|
||||
// <i>Default: 5
|
||||
#define TCP_MAX_RETRY 5
|
||||
|
||||
// <o>Retry Timeout in seconds <1-10>
|
||||
// <i>If data frame not acknowledged within this time frame,
|
||||
// <i>TCP module will try to resend the data again.
|
||||
// <i>Default: 4
|
||||
#define TCP_RETRY_TOUT 4
|
||||
|
||||
// <o>Default Connect Timeout in seconds <1-65535>
|
||||
// <i>If no TCP data frame has been exchanged during this time,
|
||||
// <i>the TCP connection is either closed or a keep-alive frame
|
||||
// <i>is sent to verify that the connection still exists.
|
||||
// <i>Default: 120
|
||||
#define TCP_DEFAULT_TOUT 120
|
||||
|
||||
// <o>Maximum Segment Size <536-1440>
|
||||
// <i>The Maximum Segment Size specifies the maximum
|
||||
// <i>number of bytes in the TCP segment's Data field.
|
||||
// <i>Default: 1440
|
||||
#define TCP_MAX_SEG_SIZE 1440
|
||||
|
||||
// <o>Receive Window Size <536-65535>
|
||||
// <i>Receive Window Size specifies the size of data,
|
||||
// <i>that the socket is able to buffer in flow-control mode.
|
||||
// <i>Default: 4320
|
||||
#define TCP_RECEIVE_WIN_SIZE 4320
|
||||
|
||||
// </h>
|
||||
|
||||
// TCP Initial Retransmit period in seconds
|
||||
#define TCP_INITIAL_RETRY_TOUT 1
|
||||
|
||||
// TCP SYN frame retransmit period in seconds
|
||||
#define TCP_SYN_RETRY_TOUT 2
|
||||
|
||||
// Number of retries to establish a connection
|
||||
#define TCP_CONNECT_RETRY 7
|
||||
|
||||
// Dynamic port start (default 49152)
|
||||
#define TCP_DYN_PORT_START 49152
|
||||
|
||||
// Dynamic port end (default 65535)
|
||||
#define TCP_DYN_PORT_END 65535
|
||||
|
||||
//------------- <<< end of configuration section >>> ---------------------------
|
||||
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-05-24 the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "bsp.h"
|
||||
|
||||
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
|
||||
/*
|
||||
* Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP
|
||||
* the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes
|
||||
*/
|
||||
#define RT_HEAP_SIZE (32*1024)
|
||||
static rt_uint8_t rt_heap[RT_HEAP_SIZE];
|
||||
|
||||
RT_WEAK void *rt_heap_begin_get(void)
|
||||
{
|
||||
return rt_heap;
|
||||
}
|
||||
|
||||
RT_WEAK void *rt_heap_end_get(void)
|
||||
{
|
||||
return rt_heap + RT_HEAP_SIZE;
|
||||
}
|
||||
#endif
|
||||
|
||||
void rt_os_tick_callback(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void SysTick_IrqHandler(void)
|
||||
{
|
||||
rt_os_tick_callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial your board.
|
||||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
//#error "TODO 1: OS Tick Configuration."
|
||||
BSP_Init();
|
||||
/*
|
||||
* TODO 1: OS Tick Configuration
|
||||
* Enable the hardware timer and call the rt_os_tick_callback function
|
||||
* periodically with the frequency RT_TICK_PER_SECOND.
|
||||
*/
|
||||
|
||||
/* Call components board initial (use INIT_BOARD_EXPORT()) */
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
|
||||
rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
|
||||
static int uart_init(void)
|
||||
{
|
||||
//#error "TODO 2: Enable the hardware uart and config baudrate."
|
||||
DbgUart_Config(500000);
|
||||
return 0;
|
||||
}
|
||||
INIT_BOARD_EXPORT(uart_init);
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
//#error "TODO 3: Output the string 'str' through the uart."
|
||||
rt_enter_critical();
|
||||
DebugUartSend((uint8_t *)str, strlen(str));
|
||||
rt_exit_critical();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-05-24 the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
|
||||
/*
|
||||
* Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP
|
||||
* the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes
|
||||
*/
|
||||
#define RT_HEAP_SIZE (15*1024)
|
||||
static rt_uint8_t rt_heap[RT_HEAP_SIZE];
|
||||
|
||||
RT_WEAK void *rt_heap_begin_get(void)
|
||||
{
|
||||
return rt_heap;
|
||||
}
|
||||
|
||||
RT_WEAK void *rt_heap_end_get(void)
|
||||
{
|
||||
return rt_heap + RT_HEAP_SIZE;
|
||||
}
|
||||
#endif
|
||||
|
||||
void rt_os_tick_callback(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial your board.
|
||||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
#error "TODO 1: OS Tick Configuration."
|
||||
/*
|
||||
* TODO 1: OS Tick Configuration
|
||||
* Enable the hardware timer and call the rt_os_tick_callback function
|
||||
* periodically with the frequency RT_TICK_PER_SECOND.
|
||||
*/
|
||||
|
||||
/* Call components board initial (use INIT_BOARD_EXPORT()) */
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
|
||||
rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
|
||||
static int uart_init(void)
|
||||
{
|
||||
#error "TODO 2: Enable the hardware uart and config baudrate."
|
||||
return 0;
|
||||
}
|
||||
INIT_BOARD_EXPORT(uart_init);
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
#error "TODO 3: Output the string 'str' through the uart."
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,139 @@
|
||||
/* RT-Thread config file */
|
||||
|
||||
#ifndef __RTTHREAD_CFG_H__
|
||||
#define __RTTHREAD_CFG_H__
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h>Basic Configuration
|
||||
// <o>Maximal level of thread priority <8-256>
|
||||
// <i>Default: 32
|
||||
#define RT_THREAD_PRIORITY_MAX 16
|
||||
// <o>OS tick per second
|
||||
// <i>Default: 1000 (1ms)
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
// <o>Alignment size for CPU architecture data access
|
||||
// <i>Default: 4
|
||||
#define RT_ALIGN_SIZE 4
|
||||
// <o>the max length of object name<2-16>
|
||||
// <i>Default: 8
|
||||
#define RT_NAME_MAX 10
|
||||
// <c1>Using RT-Thread components initialization
|
||||
// <i>Using RT-Thread components initialization
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
// </c>
|
||||
|
||||
#define RT_USING_USER_MAIN
|
||||
|
||||
// <o>the stack size of main thread<1-4086>
|
||||
// <i>Default: 512
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 512
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Debug Configuration
|
||||
// <c1>enable kernel debug configuration
|
||||
// <i>Default: enable kernel debug configuration
|
||||
//#define RT_DEBUG
|
||||
// </c>
|
||||
// <o>enable components initialization debug configuration<0-1>
|
||||
// <i>Default: 0
|
||||
#define RT_DEBUG_INIT 0
|
||||
// <c1>thread stack over flow detect
|
||||
// <i> Diable Thread stack over flow detect
|
||||
//#define RT_USING_OVERFLOW_CHECK
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Hook Configuration
|
||||
// <c1>using hook
|
||||
// <i>using hook
|
||||
//#define RT_USING_HOOK
|
||||
// </c>
|
||||
// <c1>using idle hook
|
||||
// <i>using idle hook
|
||||
//#define RT_USING_IDLE_HOOK
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <e>Software timers Configuration
|
||||
// <i> Enables user timers
|
||||
#define RT_USING_TIMER_SOFT 0
|
||||
#if RT_USING_TIMER_SOFT == 0
|
||||
#undef RT_USING_TIMER_SOFT
|
||||
#endif
|
||||
// <o>The priority level of timer thread <0-31>
|
||||
// <i>Default: 4
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
// <o>The stack size of timer thread <0-8192>
|
||||
// <i>Default: 512
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||
// </e>
|
||||
|
||||
// <h>IPC(Inter-process communication) Configuration
|
||||
// <c1>Using Semaphore
|
||||
// <i>Using Semaphore
|
||||
#define RT_USING_SEMAPHORE
|
||||
// </c>
|
||||
// <c1>Using Mutex
|
||||
// <i>Using Mutex
|
||||
#define RT_USING_MUTEX
|
||||
// </c>
|
||||
// <c1>Using Event
|
||||
// <i>Using Event
|
||||
//#define RT_USING_EVENT
|
||||
// </c>
|
||||
// <c1>Using MailBox
|
||||
// <i>Using MailBox
|
||||
#define RT_USING_MAILBOX
|
||||
// </c>
|
||||
// <c1>Using Message Queue
|
||||
// <i>Using Message Queue
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Memory Management Configuration
|
||||
// <c1>Memory Pool Management
|
||||
// <i>Memory Pool Management
|
||||
//#define RT_USING_MEMPOOL
|
||||
// </c>
|
||||
// <c1>Dynamic Heap Management(Algorithm: small memory )
|
||||
// <i>Dynamic Heap Management
|
||||
#define RT_USING_HEAP
|
||||
#define RT_USING_SMALL_MEM
|
||||
// </c>
|
||||
// <c1>using tiny size of memory
|
||||
// <i>using tiny size of memory
|
||||
//#define RT_USING_TINY_SIZE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Console Configuration
|
||||
// <c1>Using console
|
||||
// <i>Using console
|
||||
#define RT_USING_CONSOLE
|
||||
// </c>
|
||||
// <o>the buffer size of console <1-1024>
|
||||
// <i>the buffer size of console
|
||||
// <i>Default: 128 (128Byte)
|
||||
#define RT_CONSOLEBUF_SIZE 512
|
||||
// </h>
|
||||
|
||||
// <h>FinSH Configuration
|
||||
// <c1>include finsh config
|
||||
// <i>Select this choice if you using FinSH
|
||||
//#include "finsh_config.h"
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Device Configuration
|
||||
// <c1>using device framework
|
||||
// <i>using device framework
|
||||
//#define RT_USING_DEVICE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,139 @@
|
||||
/* RT-Thread config file */
|
||||
|
||||
#ifndef __RTTHREAD_CFG_H__
|
||||
#define __RTTHREAD_CFG_H__
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h>Basic Configuration
|
||||
// <o>Maximal level of thread priority <8-256>
|
||||
// <i>Default: 32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
// <o>OS tick per second
|
||||
// <i>Default: 1000 (1ms)
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
// <o>Alignment size for CPU architecture data access
|
||||
// <i>Default: 4
|
||||
#define RT_ALIGN_SIZE 4
|
||||
// <o>the max length of object name<2-16>
|
||||
// <i>Default: 8
|
||||
#define RT_NAME_MAX 8
|
||||
// <c1>Using RT-Thread components initialization
|
||||
// <i>Using RT-Thread components initialization
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
// </c>
|
||||
|
||||
#define RT_USING_USER_MAIN
|
||||
|
||||
// <o>the stack size of main thread<1-4086>
|
||||
// <i>Default: 512
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 256
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Debug Configuration
|
||||
// <c1>enable kernel debug configuration
|
||||
// <i>Default: enable kernel debug configuration
|
||||
//#define RT_DEBUG
|
||||
// </c>
|
||||
// <o>enable components initialization debug configuration<0-1>
|
||||
// <i>Default: 0
|
||||
#define RT_DEBUG_INIT 0
|
||||
// <c1>thread stack over flow detect
|
||||
// <i> Diable Thread stack over flow detect
|
||||
//#define RT_USING_OVERFLOW_CHECK
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Hook Configuration
|
||||
// <c1>using hook
|
||||
// <i>using hook
|
||||
//#define RT_USING_HOOK
|
||||
// </c>
|
||||
// <c1>using idle hook
|
||||
// <i>using idle hook
|
||||
//#define RT_USING_IDLE_HOOK
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <e>Software timers Configuration
|
||||
// <i> Enables user timers
|
||||
#define RT_USING_TIMER_SOFT 0
|
||||
#if RT_USING_TIMER_SOFT == 0
|
||||
#undef RT_USING_TIMER_SOFT
|
||||
#endif
|
||||
// <o>The priority level of timer thread <0-31>
|
||||
// <i>Default: 4
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
// <o>The stack size of timer thread <0-8192>
|
||||
// <i>Default: 512
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||
// </e>
|
||||
|
||||
// <h>IPC(Inter-process communication) Configuration
|
||||
// <c1>Using Semaphore
|
||||
// <i>Using Semaphore
|
||||
#define RT_USING_SEMAPHORE
|
||||
// </c>
|
||||
// <c1>Using Mutex
|
||||
// <i>Using Mutex
|
||||
//#define RT_USING_MUTEX
|
||||
// </c>
|
||||
// <c1>Using Event
|
||||
// <i>Using Event
|
||||
//#define RT_USING_EVENT
|
||||
// </c>
|
||||
// <c1>Using MailBox
|
||||
// <i>Using MailBox
|
||||
#define RT_USING_MAILBOX
|
||||
// </c>
|
||||
// <c1>Using Message Queue
|
||||
// <i>Using Message Queue
|
||||
//#define RT_USING_MESSAGEQUEUE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Memory Management Configuration
|
||||
// <c1>Memory Pool Management
|
||||
// <i>Memory Pool Management
|
||||
//#define RT_USING_MEMPOOL
|
||||
// </c>
|
||||
// <c1>Dynamic Heap Management(Algorithm: small memory )
|
||||
// <i>Dynamic Heap Management
|
||||
#define RT_USING_HEAP
|
||||
#define RT_USING_SMALL_MEM
|
||||
// </c>
|
||||
// <c1>using tiny size of memory
|
||||
// <i>using tiny size of memory
|
||||
//#define RT_USING_TINY_SIZE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Console Configuration
|
||||
// <c1>Using console
|
||||
// <i>Using console
|
||||
//#define RT_USING_CONSOLE
|
||||
// </c>
|
||||
// <o>the buffer size of console <1-1024>
|
||||
// <i>the buffer size of console
|
||||
// <i>Default: 128 (128Byte)
|
||||
#define RT_CONSOLEBUF_SIZE 256
|
||||
// </h>
|
||||
|
||||
// <h>FinSH Configuration
|
||||
// <c1>include finsh config
|
||||
// <i>Select this choice if you using FinSH
|
||||
//#include "finsh_config.h"
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Device Configuration
|
||||
// <c1>using device framework
|
||||
// <i>using device framework
|
||||
//#define RT_USING_DEVICE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'BootLoader'
|
||||
* Target: 'Debug'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'BootLoader'
|
||||
* Target: 'Release'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'DigitalModule_4Ch'
|
||||
* Target: 'i2c_24c256_Debug'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'DigitalModule_4Ch'
|
||||
* Target: 'i2c_24c256_Release'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'DigitalModule_4Ch'
|
||||
* Target: 'template_Debug'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,621 @@
|
||||
;/******************************************************************************
|
||||
; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
; *
|
||||
; * This software component is licensed by HDSC under BSD 3-Clause license
|
||||
; * (the "License"); You may not use this file except in compliance with the
|
||||
; * License. You may obtain a copy of the License at:
|
||||
; * opensource.org/licenses/BSD-3-Clause
|
||||
;/*****************************************************************************/
|
||||
;/* Startup for ARM */
|
||||
;/* Version V1.0 */
|
||||
;/* Date 2018-10-13 */
|
||||
;/* Target-mcu HC32F460 */
|
||||
;/*****************************************************************************/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00008000
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; Peripheral Interrupts
|
||||
DCD IRQ000_Handler ; IRQ000_Handler
|
||||
DCD IRQ001_Handler ; IRQ001_Handler
|
||||
DCD IRQ002_Handler ; IRQ002_Handler
|
||||
DCD IRQ003_Handler ; IRQ003_Handler
|
||||
DCD IRQ004_Handler ; IRQ004_Handler
|
||||
DCD IRQ005_Handler ; IRQ005_Handler
|
||||
DCD IRQ006_Handler ; IRQ006_Handler
|
||||
DCD IRQ007_Handler ; IRQ007_Handler
|
||||
DCD IRQ008_Handler ; IRQ008_Handler
|
||||
DCD IRQ009_Handler ; IRQ009_Handler
|
||||
DCD IRQ010_Handler ; IRQ010_Handler
|
||||
DCD IRQ011_Handler ; IRQ011_Handler
|
||||
DCD IRQ012_Handler ; IRQ012_Handler
|
||||
DCD IRQ013_Handler ; IRQ013_Handler
|
||||
DCD IRQ014_Handler ; IRQ014_Handler
|
||||
DCD IRQ015_Handler ; IRQ015_Handler
|
||||
DCD IRQ016_Handler ; IRQ016_Handler
|
||||
DCD IRQ017_Handler ; IRQ017_Handler
|
||||
DCD IRQ018_Handler ; IRQ018_Handler
|
||||
DCD IRQ019_Handler ; IRQ019_Handler
|
||||
DCD IRQ020_Handler ; IRQ020_Handler
|
||||
DCD IRQ021_Handler ; IRQ021_Handler
|
||||
DCD IRQ022_Handler ; IRQ022_Handler
|
||||
DCD IRQ023_Handler ; IRQ023_Handler
|
||||
DCD IRQ024_Handler ; IRQ024_Handler
|
||||
DCD IRQ025_Handler ; IRQ025_Handler
|
||||
DCD IRQ026_Handler ; IRQ026_Handler
|
||||
DCD IRQ027_Handler ; IRQ027_Handler
|
||||
DCD IRQ028_Handler ; IRQ028_Handler
|
||||
DCD IRQ029_Handler ; IRQ029_Handler
|
||||
DCD IRQ030_Handler ; IRQ030_Handler
|
||||
DCD IRQ031_Handler ; IRQ031_Handler
|
||||
DCD IRQ032_Handler ; IRQ032_Handler
|
||||
DCD IRQ033_Handler ; IRQ033_Handler
|
||||
DCD IRQ034_Handler ; IRQ034_Handler
|
||||
DCD IRQ035_Handler ; IRQ035_Handler
|
||||
DCD IRQ036_Handler ; IRQ036_Handler
|
||||
DCD IRQ037_Handler ; IRQ037_Handler
|
||||
DCD IRQ038_Handler ; IRQ038_Handler
|
||||
DCD IRQ039_Handler ; IRQ039_Handler
|
||||
DCD IRQ040_Handler ; IRQ040_Handler
|
||||
DCD IRQ041_Handler ; IRQ041_Handler
|
||||
DCD IRQ042_Handler ; IRQ042_Handler
|
||||
DCD IRQ043_Handler ; IRQ043_Handler
|
||||
DCD IRQ044_Handler ; IRQ044_Handler
|
||||
DCD IRQ045_Handler ; IRQ045_Handler
|
||||
DCD IRQ046_Handler ; IRQ046_Handler
|
||||
DCD IRQ047_Handler ; IRQ047_Handler
|
||||
DCD IRQ048_Handler ; IRQ048_Handler
|
||||
DCD IRQ049_Handler ; IRQ049_Handler
|
||||
DCD IRQ050_Handler ; IRQ050_Handler
|
||||
DCD IRQ051_Handler ; IRQ051_Handler
|
||||
DCD IRQ052_Handler ; IRQ052_Handler
|
||||
DCD IRQ053_Handler ; IRQ053_Handler
|
||||
DCD IRQ054_Handler ; IRQ054_Handler
|
||||
DCD IRQ055_Handler ; IRQ055_Handler
|
||||
DCD IRQ056_Handler ; IRQ056_Handler
|
||||
DCD IRQ057_Handler ; IRQ057_Handler
|
||||
DCD IRQ058_Handler ; IRQ058_Handler
|
||||
DCD IRQ059_Handler ; IRQ059_Handler
|
||||
DCD IRQ060_Handler ; IRQ060_Handler
|
||||
DCD IRQ061_Handler ; IRQ061_Handler
|
||||
DCD IRQ062_Handler ; IRQ062_Handler
|
||||
DCD IRQ063_Handler ; IRQ063_Handler
|
||||
DCD IRQ064_Handler ; IRQ064_Handler
|
||||
DCD IRQ065_Handler ; IRQ065_Handler
|
||||
DCD IRQ066_Handler ; IRQ066_Handler
|
||||
DCD IRQ067_Handler ; IRQ067_Handler
|
||||
DCD IRQ068_Handler ; IRQ068_Handler
|
||||
DCD IRQ069_Handler ; IRQ069_Handler
|
||||
DCD IRQ070_Handler ; IRQ070_Handler
|
||||
DCD IRQ071_Handler ; IRQ071_Handler
|
||||
DCD IRQ072_Handler ; IRQ072_Handler
|
||||
DCD IRQ073_Handler ; IRQ073_Handler
|
||||
DCD IRQ074_Handler ; IRQ074_Handler
|
||||
DCD IRQ075_Handler ; IRQ075_Handler
|
||||
DCD IRQ076_Handler ; IRQ076_Handler
|
||||
DCD IRQ077_Handler ; IRQ077_Handler
|
||||
DCD IRQ078_Handler ; IRQ078_Handler
|
||||
DCD IRQ079_Handler ; IRQ079_Handler
|
||||
DCD IRQ080_Handler ; IRQ080_Handler
|
||||
DCD IRQ081_Handler ; IRQ081_Handler
|
||||
DCD IRQ082_Handler ; IRQ082_Handler
|
||||
DCD IRQ083_Handler ; IRQ083_Handler
|
||||
DCD IRQ084_Handler ; IRQ084_Handler
|
||||
DCD IRQ085_Handler ; IRQ085_Handler
|
||||
DCD IRQ086_Handler ; IRQ086_Handler
|
||||
DCD IRQ087_Handler ; IRQ087_Handler
|
||||
DCD IRQ088_Handler ; IRQ088_Handler
|
||||
DCD IRQ089_Handler ; IRQ089_Handler
|
||||
DCD IRQ090_Handler ; IRQ090_Handler
|
||||
DCD IRQ091_Handler ; IRQ091_Handler
|
||||
DCD IRQ092_Handler ; IRQ092_Handler
|
||||
DCD IRQ093_Handler ; IRQ093_Handler
|
||||
DCD IRQ094_Handler ; IRQ094_Handler
|
||||
DCD IRQ095_Handler ; IRQ095_Handler
|
||||
DCD IRQ096_Handler ; IRQ096_Handler
|
||||
DCD IRQ097_Handler ; IRQ097_Handler
|
||||
DCD IRQ098_Handler ; IRQ098_Handler
|
||||
DCD IRQ099_Handler ; IRQ099_Handler
|
||||
DCD IRQ100_Handler ; IRQ100_Handler
|
||||
DCD IRQ101_Handler ; IRQ101_Handler
|
||||
DCD IRQ102_Handler ; IRQ102_Handler
|
||||
DCD IRQ103_Handler ; IRQ103_Handler
|
||||
DCD IRQ104_Handler ; IRQ104_Handler
|
||||
DCD IRQ105_Handler ; IRQ105_Handler
|
||||
DCD IRQ106_Handler ; IRQ106_Handler
|
||||
DCD IRQ107_Handler ; IRQ107_Handler
|
||||
DCD IRQ108_Handler ; IRQ108_Handler
|
||||
DCD IRQ109_Handler ; IRQ109_Handler
|
||||
DCD IRQ110_Handler ; IRQ110_Handler
|
||||
DCD IRQ111_Handler ; IRQ111_Handler
|
||||
DCD IRQ112_Handler ; IRQ112_Handler
|
||||
DCD IRQ113_Handler ; IRQ113_Handler
|
||||
DCD IRQ114_Handler ; IRQ114_Handler
|
||||
DCD IRQ115_Handler ; IRQ115_Handler
|
||||
DCD IRQ116_Handler ; IRQ116_Handler
|
||||
DCD IRQ117_Handler ; IRQ117_Handler
|
||||
DCD IRQ118_Handler ; IRQ118_Handler
|
||||
DCD IRQ119_Handler ; IRQ119_Handler
|
||||
DCD IRQ120_Handler ; IRQ120_Handler
|
||||
DCD IRQ121_Handler ; IRQ121_Handler
|
||||
DCD IRQ122_Handler ; IRQ122_Handler
|
||||
DCD IRQ123_Handler ; IRQ123_Handler
|
||||
DCD IRQ124_Handler ; IRQ124_Handler
|
||||
DCD IRQ125_Handler ; IRQ125_Handler
|
||||
DCD IRQ126_Handler ; IRQ126_Handler
|
||||
DCD IRQ127_Handler ; IRQ127_Handler
|
||||
DCD IRQ128_Handler ; IRQ128_Handler
|
||||
DCD IRQ129_Handler ; IRQ129_Handler
|
||||
DCD IRQ130_Handler ; IRQ130_Handler
|
||||
DCD IRQ131_Handler ; IRQ131_Handler
|
||||
DCD IRQ132_Handler ; IRQ132_Handler
|
||||
DCD IRQ133_Handler ; IRQ133_Handler
|
||||
DCD IRQ134_Handler ; IRQ134_Handler
|
||||
DCD IRQ135_Handler ; IRQ135_Handler
|
||||
DCD IRQ136_Handler ; IRQ136_Handler
|
||||
DCD IRQ137_Handler ; IRQ137_Handler
|
||||
DCD IRQ138_Handler ; IRQ138_Handler
|
||||
DCD IRQ139_Handler ; IRQ139_Handler
|
||||
DCD IRQ140_Handler ; IRQ140_Handler
|
||||
DCD IRQ141_Handler ; IRQ141_Handler
|
||||
DCD IRQ142_Handler ; IRQ142_Handler
|
||||
DCD IRQ143_Handler ; IRQ143_Handler
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
SET_SRAM3_WAIT
|
||||
LDR R0, =0x40050804
|
||||
MOV R1, #0x77
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x4005080C
|
||||
MOV R1, #0x77
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x40050800
|
||||
MOV R1, #0x1100
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x40050804
|
||||
MOV R1, #0x76
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x4005080C
|
||||
MOV R1, #0x76
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT IRQ000_Handler [WEAK]
|
||||
EXPORT IRQ001_Handler [WEAK]
|
||||
EXPORT IRQ002_Handler [WEAK]
|
||||
EXPORT IRQ003_Handler [WEAK]
|
||||
EXPORT IRQ004_Handler [WEAK]
|
||||
EXPORT IRQ005_Handler [WEAK]
|
||||
EXPORT IRQ006_Handler [WEAK]
|
||||
EXPORT IRQ007_Handler [WEAK]
|
||||
EXPORT IRQ008_Handler [WEAK]
|
||||
EXPORT IRQ009_Handler [WEAK]
|
||||
EXPORT IRQ010_Handler [WEAK]
|
||||
EXPORT IRQ011_Handler [WEAK]
|
||||
EXPORT IRQ012_Handler [WEAK]
|
||||
EXPORT IRQ013_Handler [WEAK]
|
||||
EXPORT IRQ014_Handler [WEAK]
|
||||
EXPORT IRQ015_Handler [WEAK]
|
||||
EXPORT IRQ016_Handler [WEAK]
|
||||
EXPORT IRQ017_Handler [WEAK]
|
||||
EXPORT IRQ018_Handler [WEAK]
|
||||
EXPORT IRQ019_Handler [WEAK]
|
||||
EXPORT IRQ020_Handler [WEAK]
|
||||
EXPORT IRQ021_Handler [WEAK]
|
||||
EXPORT IRQ022_Handler [WEAK]
|
||||
EXPORT IRQ023_Handler [WEAK]
|
||||
EXPORT IRQ024_Handler [WEAK]
|
||||
EXPORT IRQ025_Handler [WEAK]
|
||||
EXPORT IRQ026_Handler [WEAK]
|
||||
EXPORT IRQ027_Handler [WEAK]
|
||||
EXPORT IRQ028_Handler [WEAK]
|
||||
EXPORT IRQ029_Handler [WEAK]
|
||||
EXPORT IRQ030_Handler [WEAK]
|
||||
EXPORT IRQ031_Handler [WEAK]
|
||||
EXPORT IRQ032_Handler [WEAK]
|
||||
EXPORT IRQ033_Handler [WEAK]
|
||||
EXPORT IRQ034_Handler [WEAK]
|
||||
EXPORT IRQ035_Handler [WEAK]
|
||||
EXPORT IRQ036_Handler [WEAK]
|
||||
EXPORT IRQ037_Handler [WEAK]
|
||||
EXPORT IRQ038_Handler [WEAK]
|
||||
EXPORT IRQ039_Handler [WEAK]
|
||||
EXPORT IRQ040_Handler [WEAK]
|
||||
EXPORT IRQ041_Handler [WEAK]
|
||||
EXPORT IRQ042_Handler [WEAK]
|
||||
EXPORT IRQ043_Handler [WEAK]
|
||||
EXPORT IRQ044_Handler [WEAK]
|
||||
EXPORT IRQ045_Handler [WEAK]
|
||||
EXPORT IRQ046_Handler [WEAK]
|
||||
EXPORT IRQ047_Handler [WEAK]
|
||||
EXPORT IRQ048_Handler [WEAK]
|
||||
EXPORT IRQ049_Handler [WEAK]
|
||||
EXPORT IRQ050_Handler [WEAK]
|
||||
EXPORT IRQ051_Handler [WEAK]
|
||||
EXPORT IRQ052_Handler [WEAK]
|
||||
EXPORT IRQ053_Handler [WEAK]
|
||||
EXPORT IRQ054_Handler [WEAK]
|
||||
EXPORT IRQ055_Handler [WEAK]
|
||||
EXPORT IRQ056_Handler [WEAK]
|
||||
EXPORT IRQ057_Handler [WEAK]
|
||||
EXPORT IRQ058_Handler [WEAK]
|
||||
EXPORT IRQ059_Handler [WEAK]
|
||||
EXPORT IRQ060_Handler [WEAK]
|
||||
EXPORT IRQ061_Handler [WEAK]
|
||||
EXPORT IRQ062_Handler [WEAK]
|
||||
EXPORT IRQ063_Handler [WEAK]
|
||||
EXPORT IRQ064_Handler [WEAK]
|
||||
EXPORT IRQ065_Handler [WEAK]
|
||||
EXPORT IRQ066_Handler [WEAK]
|
||||
EXPORT IRQ067_Handler [WEAK]
|
||||
EXPORT IRQ068_Handler [WEAK]
|
||||
EXPORT IRQ069_Handler [WEAK]
|
||||
EXPORT IRQ070_Handler [WEAK]
|
||||
EXPORT IRQ071_Handler [WEAK]
|
||||
EXPORT IRQ072_Handler [WEAK]
|
||||
EXPORT IRQ073_Handler [WEAK]
|
||||
EXPORT IRQ074_Handler [WEAK]
|
||||
EXPORT IRQ075_Handler [WEAK]
|
||||
EXPORT IRQ076_Handler [WEAK]
|
||||
EXPORT IRQ077_Handler [WEAK]
|
||||
EXPORT IRQ078_Handler [WEAK]
|
||||
EXPORT IRQ079_Handler [WEAK]
|
||||
EXPORT IRQ080_Handler [WEAK]
|
||||
EXPORT IRQ081_Handler [WEAK]
|
||||
EXPORT IRQ082_Handler [WEAK]
|
||||
EXPORT IRQ083_Handler [WEAK]
|
||||
EXPORT IRQ084_Handler [WEAK]
|
||||
EXPORT IRQ085_Handler [WEAK]
|
||||
EXPORT IRQ086_Handler [WEAK]
|
||||
EXPORT IRQ087_Handler [WEAK]
|
||||
EXPORT IRQ088_Handler [WEAK]
|
||||
EXPORT IRQ089_Handler [WEAK]
|
||||
EXPORT IRQ090_Handler [WEAK]
|
||||
EXPORT IRQ091_Handler [WEAK]
|
||||
EXPORT IRQ092_Handler [WEAK]
|
||||
EXPORT IRQ093_Handler [WEAK]
|
||||
EXPORT IRQ094_Handler [WEAK]
|
||||
EXPORT IRQ095_Handler [WEAK]
|
||||
EXPORT IRQ096_Handler [WEAK]
|
||||
EXPORT IRQ097_Handler [WEAK]
|
||||
EXPORT IRQ098_Handler [WEAK]
|
||||
EXPORT IRQ099_Handler [WEAK]
|
||||
EXPORT IRQ100_Handler [WEAK]
|
||||
EXPORT IRQ101_Handler [WEAK]
|
||||
EXPORT IRQ102_Handler [WEAK]
|
||||
EXPORT IRQ103_Handler [WEAK]
|
||||
EXPORT IRQ104_Handler [WEAK]
|
||||
EXPORT IRQ105_Handler [WEAK]
|
||||
EXPORT IRQ106_Handler [WEAK]
|
||||
EXPORT IRQ107_Handler [WEAK]
|
||||
EXPORT IRQ108_Handler [WEAK]
|
||||
EXPORT IRQ109_Handler [WEAK]
|
||||
EXPORT IRQ110_Handler [WEAK]
|
||||
EXPORT IRQ111_Handler [WEAK]
|
||||
EXPORT IRQ112_Handler [WEAK]
|
||||
EXPORT IRQ113_Handler [WEAK]
|
||||
EXPORT IRQ114_Handler [WEAK]
|
||||
EXPORT IRQ115_Handler [WEAK]
|
||||
EXPORT IRQ116_Handler [WEAK]
|
||||
EXPORT IRQ117_Handler [WEAK]
|
||||
EXPORT IRQ118_Handler [WEAK]
|
||||
EXPORT IRQ119_Handler [WEAK]
|
||||
EXPORT IRQ120_Handler [WEAK]
|
||||
EXPORT IRQ121_Handler [WEAK]
|
||||
EXPORT IRQ122_Handler [WEAK]
|
||||
EXPORT IRQ123_Handler [WEAK]
|
||||
EXPORT IRQ124_Handler [WEAK]
|
||||
EXPORT IRQ125_Handler [WEAK]
|
||||
EXPORT IRQ126_Handler [WEAK]
|
||||
EXPORT IRQ127_Handler [WEAK]
|
||||
EXPORT IRQ128_Handler [WEAK]
|
||||
EXPORT IRQ129_Handler [WEAK]
|
||||
EXPORT IRQ130_Handler [WEAK]
|
||||
EXPORT IRQ131_Handler [WEAK]
|
||||
EXPORT IRQ132_Handler [WEAK]
|
||||
EXPORT IRQ133_Handler [WEAK]
|
||||
EXPORT IRQ134_Handler [WEAK]
|
||||
EXPORT IRQ135_Handler [WEAK]
|
||||
EXPORT IRQ136_Handler [WEAK]
|
||||
EXPORT IRQ137_Handler [WEAK]
|
||||
EXPORT IRQ138_Handler [WEAK]
|
||||
EXPORT IRQ139_Handler [WEAK]
|
||||
EXPORT IRQ140_Handler [WEAK]
|
||||
EXPORT IRQ141_Handler [WEAK]
|
||||
EXPORT IRQ142_Handler [WEAK]
|
||||
EXPORT IRQ143_Handler [WEAK]
|
||||
IRQ000_Handler
|
||||
IRQ001_Handler
|
||||
IRQ002_Handler
|
||||
IRQ003_Handler
|
||||
IRQ004_Handler
|
||||
IRQ005_Handler
|
||||
IRQ006_Handler
|
||||
IRQ007_Handler
|
||||
IRQ008_Handler
|
||||
IRQ009_Handler
|
||||
IRQ010_Handler
|
||||
IRQ011_Handler
|
||||
IRQ012_Handler
|
||||
IRQ013_Handler
|
||||
IRQ014_Handler
|
||||
IRQ015_Handler
|
||||
IRQ016_Handler
|
||||
IRQ017_Handler
|
||||
IRQ018_Handler
|
||||
IRQ019_Handler
|
||||
IRQ020_Handler
|
||||
IRQ021_Handler
|
||||
IRQ022_Handler
|
||||
IRQ023_Handler
|
||||
IRQ024_Handler
|
||||
IRQ025_Handler
|
||||
IRQ026_Handler
|
||||
IRQ027_Handler
|
||||
IRQ028_Handler
|
||||
IRQ029_Handler
|
||||
IRQ030_Handler
|
||||
IRQ031_Handler
|
||||
IRQ032_Handler
|
||||
IRQ033_Handler
|
||||
IRQ034_Handler
|
||||
IRQ035_Handler
|
||||
IRQ036_Handler
|
||||
IRQ037_Handler
|
||||
IRQ038_Handler
|
||||
IRQ039_Handler
|
||||
IRQ040_Handler
|
||||
IRQ041_Handler
|
||||
IRQ042_Handler
|
||||
IRQ043_Handler
|
||||
IRQ044_Handler
|
||||
IRQ045_Handler
|
||||
IRQ046_Handler
|
||||
IRQ047_Handler
|
||||
IRQ048_Handler
|
||||
IRQ049_Handler
|
||||
IRQ050_Handler
|
||||
IRQ051_Handler
|
||||
IRQ052_Handler
|
||||
IRQ053_Handler
|
||||
IRQ054_Handler
|
||||
IRQ055_Handler
|
||||
IRQ056_Handler
|
||||
IRQ057_Handler
|
||||
IRQ058_Handler
|
||||
IRQ059_Handler
|
||||
IRQ060_Handler
|
||||
IRQ061_Handler
|
||||
IRQ062_Handler
|
||||
IRQ063_Handler
|
||||
IRQ064_Handler
|
||||
IRQ065_Handler
|
||||
IRQ066_Handler
|
||||
IRQ067_Handler
|
||||
IRQ068_Handler
|
||||
IRQ069_Handler
|
||||
IRQ070_Handler
|
||||
IRQ071_Handler
|
||||
IRQ072_Handler
|
||||
IRQ073_Handler
|
||||
IRQ074_Handler
|
||||
IRQ075_Handler
|
||||
IRQ076_Handler
|
||||
IRQ077_Handler
|
||||
IRQ078_Handler
|
||||
IRQ079_Handler
|
||||
IRQ080_Handler
|
||||
IRQ081_Handler
|
||||
IRQ082_Handler
|
||||
IRQ083_Handler
|
||||
IRQ084_Handler
|
||||
IRQ085_Handler
|
||||
IRQ086_Handler
|
||||
IRQ087_Handler
|
||||
IRQ088_Handler
|
||||
IRQ089_Handler
|
||||
IRQ090_Handler
|
||||
IRQ091_Handler
|
||||
IRQ092_Handler
|
||||
IRQ093_Handler
|
||||
IRQ094_Handler
|
||||
IRQ095_Handler
|
||||
IRQ096_Handler
|
||||
IRQ097_Handler
|
||||
IRQ098_Handler
|
||||
IRQ099_Handler
|
||||
IRQ100_Handler
|
||||
IRQ101_Handler
|
||||
IRQ102_Handler
|
||||
IRQ103_Handler
|
||||
IRQ104_Handler
|
||||
IRQ105_Handler
|
||||
IRQ106_Handler
|
||||
IRQ107_Handler
|
||||
IRQ108_Handler
|
||||
IRQ109_Handler
|
||||
IRQ110_Handler
|
||||
IRQ111_Handler
|
||||
IRQ112_Handler
|
||||
IRQ113_Handler
|
||||
IRQ114_Handler
|
||||
IRQ115_Handler
|
||||
IRQ116_Handler
|
||||
IRQ117_Handler
|
||||
IRQ118_Handler
|
||||
IRQ119_Handler
|
||||
IRQ120_Handler
|
||||
IRQ121_Handler
|
||||
IRQ122_Handler
|
||||
IRQ123_Handler
|
||||
IRQ124_Handler
|
||||
IRQ125_Handler
|
||||
IRQ126_Handler
|
||||
IRQ127_Handler
|
||||
IRQ128_Handler
|
||||
IRQ129_Handler
|
||||
IRQ130_Handler
|
||||
IRQ131_Handler
|
||||
IRQ132_Handler
|
||||
IRQ133_Handler
|
||||
IRQ134_Handler
|
||||
IRQ135_Handler
|
||||
IRQ136_Handler
|
||||
IRQ137_Handler
|
||||
IRQ138_Handler
|
||||
IRQ139_Handler
|
||||
IRQ140_Handler
|
||||
IRQ141_Handler
|
||||
IRQ142_Handler
|
||||
IRQ143_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
BIN
Binary file not shown.
@@ -0,0 +1,509 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_adc.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link AdcGroup Adc description @endlink
|
||||
**
|
||||
** - 2018-11-30 CDT First version for Device Driver Library of Adc.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_ADC_H__
|
||||
#define __HC32F460_ADC_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_ADC_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup AdcGroup Analog-to-Digital Converter(ADC)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ADC average count.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_avcnt
|
||||
{
|
||||
AdcAvcnt_2 = 0x0, ///< Average after 2 conversions.
|
||||
AdcAvcnt_4 = 0x1, ///< Average after 4 conversions.
|
||||
AdcAvcnt_8 = 0x2, ///< Average after 8 conversions.
|
||||
AdcAvcnt_16 = 0x3, ///< Average after 16 conversions.
|
||||
AdcAvcnt_32 = 0x4, ///< Average after 32 conversions.
|
||||
AdcAvcnt_64 = 0x5, ///< Average after 64 conversions.
|
||||
AdcAvcnt_128 = 0x6, ///< Average after 128 conversions.
|
||||
AdcAvcnt_256 = 0x7, ///< Average after 256 conversions.
|
||||
} en_adc_avcnt_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ADC data alignment
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_data_align
|
||||
{
|
||||
AdcDataAlign_Right = 0x0, ///< Data right alignment.
|
||||
AdcDataAlign_Left = 0x1, ///< Data left alignment.
|
||||
} en_adc_data_align_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Automatically clear data registers after reading data.
|
||||
** The auto clear function is mainly used to detect whether the data register
|
||||
** is updated.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_clren
|
||||
{
|
||||
AdcClren_Disable = 0x0, ///< Automatic clear function disable.
|
||||
AdcClren_Enable = 0x1, ///< Automatic clear function enable.
|
||||
} en_adc_clren_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ADC resolution.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_resolution
|
||||
{
|
||||
AdcResolution_12Bit = 0x0, ///< Resolution is 12 bit.
|
||||
AdcResolution_10Bit = 0x1, ///< Resolution is 10 bit.
|
||||
AdcResolution_8Bit = 0x2, ///< Resolution is 8 bit.
|
||||
} en_adc_resolution_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ADC scan mode.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_scan_mode
|
||||
{
|
||||
AdcMode_SAOnce = 0x0, ///< Sequence A works once.
|
||||
AdcMode_SAContinuous = 0x1, ///< Sequence A works always.
|
||||
AdcMode_SAOnceSBOnce = 0x2, ///< Sequence A and sequence B work once.
|
||||
AdcMode_SAContinuousSBOnce = 0x3, ///< Sequence A works always, sequence works once.
|
||||
} en_adc_scan_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ADC sequence A restart position.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_rschsel
|
||||
{
|
||||
AdcRschsel_Continue = 0x0, ///< After sequence A is interrupted by sequence B,
|
||||
///< sequence A continues to scan from the interrupt
|
||||
///< when it restarts.
|
||||
|
||||
AdcRschsel_Restart = 0x1, ///< After sequence A is interrupted by sequence B,
|
||||
///< sequence A restarts scanning from the first channel
|
||||
///< when it restarts.
|
||||
} en_adc_rschsel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ADC external or internal trigger source enable/disable .
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_trgen
|
||||
{
|
||||
AdcTrgen_Disable = 0x0, ///< External or internal trigger source disable.
|
||||
AdcTrgen_Enable = 0x1, ///< External or internal trigger source enable.
|
||||
} en_adc_trgen_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ADC sequence trigger source selection.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_trgsel
|
||||
{
|
||||
AdcTrgsel_ADTRGX = 0x0, ///< X = 1(use ADC1) / 2(use ADC2), same as below.
|
||||
AdcTrgsel_TRGX0 = 0x1, ///< Pin IN_TRG10 / IN_TRG20.
|
||||
AdcTrgsel_TRGX1 = 0x2, ///< Pin IN_TRG11 / IN_TRG21.
|
||||
AdcTrgsel_TRGX0_TRGX1 = 0x3, ///< Pin IN_TRG10 + IN_TRG11 / IN_TRG20 + IN_TRG21.
|
||||
} en_adc_trgsel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Sequence A/B conversion completion interrupt enable/disable.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_eocien
|
||||
{
|
||||
AdcEocien_Disable = 0x0, ///< Conversion completion interrupt disable.
|
||||
AdcEocien_Enable = 0x1, ///< Conversion completion interrupt enable.
|
||||
} en_adc_eocien_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ADC sync mode.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_sync_mode
|
||||
{
|
||||
AdcSync_SingleSerial = 0x0u, ///< Single: ADC1 and ADC2 only sample and convert once after triggering.
|
||||
///< Serial: ADC2 start after ADC1 N PCLK4 cycles.
|
||||
AdcSync_SingleParallel = 0x2u, ///< Parallel: ADC1 and ADC2 start at the same time.
|
||||
AdcSync_ContinuousSerial = 0x4u, ///< Continuous: ADC1 and ADC2 continuously sample and convert after triggering.
|
||||
AdcSync_ContinuousParallel = 0x6u,
|
||||
} en_adc_sync_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ADC sync enable/disable.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_syncen
|
||||
{
|
||||
AdcSync_Disable = 0x0, ///< Disable sync mode.
|
||||
AdcSync_Enable = 0x1, ///< Enable sync mode.
|
||||
} en_adc_syncen_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Analog watchdog interrupt enable/disable.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_awdien
|
||||
{
|
||||
AdcAwdInt_Disable = 0x0, ///< Disable AWD interrupt.
|
||||
AdcAwdInt_Enable = 0x1, ///< Enable AWD interrupt.
|
||||
} en_adc_awdien_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Analog watchdog interrupt event sequence selection.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_awdss
|
||||
{
|
||||
AdcAwdSel_SA_SB = 0x0, ///< Sequence A and B output interrupt event -- ADC_SEQCMP.
|
||||
AdcAwdSel_SA = 0x1, ///< Sequence A output interrupt event -- ADC_SEQCMP.
|
||||
AdcAwdSel_SB = 0x2, ///< Sequence B output interrupt event -- ADC_SEQCMP.
|
||||
AdcAwdSel_SB_SA = 0x3, ///< Same as AdcAwdSel_SA_SB.
|
||||
} en_adc_awdss_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Analog watchdog comparison mode selection.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_awdmd
|
||||
{
|
||||
AdcAwdCmpMode_0 = 0x0, ///< Upper limit is AWDDR0, lower limit is AWDDR1.
|
||||
///< If AWDDR0 > result or result > AWDDR1,
|
||||
///< the interrupt will be occur.
|
||||
|
||||
AdcAwdCmpMode_1 = 0x1, ///< The range is [AWDDR0, AWDDR1].
|
||||
///< If AWDDR0 <= result <= AWDDR1, the interrupt will be occur.
|
||||
} en_adc_awdmd_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Analog watchdog enable/disable.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_awden
|
||||
{
|
||||
AdcAwd_Disable = 0x0, ///< Disable AWD.
|
||||
AdcAwd_Enable = 0x1, ///< Enable AWD.
|
||||
} en_adc_awden_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief PGA control.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_pga_ctl
|
||||
{
|
||||
AdcPgaCtl_Invalid = 0x0, ///< Amplifier is invalid.
|
||||
AdcPgaCtl_Amplify = 0xE, ///< Amplifier effective.
|
||||
} en_adc_pga_ctl_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The amplification factor of the amplifier is as follows.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_pga_factor
|
||||
{
|
||||
AdcPgaFactor_2 = 0x0, ///< PGA magnification 2.
|
||||
AdcPgaFactor_2P133 = 0x1, ///< PGA magnification 2.133.
|
||||
AdcPgaFactor_2P286 = 0x2, ///< PGA magnification 2.286.
|
||||
AdcPgaFactor_2P667 = 0x3, ///< PGA magnification 2.667.
|
||||
AdcPgaFactor_2P909 = 0x4, ///< PGA magnification 2.909.
|
||||
AdcPgaFactor_3P2 = 0x5, ///< PGA magnification 3.2.
|
||||
AdcPgaFactor_3P556 = 0x6, ///< PGA magnification 3.556.
|
||||
AdcPgaFactor_4 = 0x7, ///< PGA magnification 4.
|
||||
AdcPgaFactor_4P571 = 0x8, ///< PGA magnification 4.571.
|
||||
AdcPgaFactor_5P333 = 0x9, ///< PGA magnification 5.333.
|
||||
AdcPgaFactor_6P4 = 0xA, ///< PGA magnification 6.4.
|
||||
AdcPgaFactor_8 = 0xB, ///< PGA magnification 8.
|
||||
AdcPgaFactor_10P667 = 0xC, ///< PGA magnification 10.667.
|
||||
AdcPgaFactor_16 = 0xD, ///< PGA magnification 16.
|
||||
AdcPgaFactor_32 = 0xE, ///< PGA magnification 32.
|
||||
} en_adc_pga_factor_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Negative phase input selection
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_pga_negative
|
||||
{
|
||||
AdcPgaNegative_PGAVSS = 0x0, ///< Use external port PGAVSS as PGA negative input.
|
||||
AdcPgaNegative_VSSA = 0x1, ///< Use internal analog ground VSSA as PGA negative input.
|
||||
} en_adc_pga_negative_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ADC common trigger source select
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_adc_com_trigger
|
||||
{
|
||||
AdcComTrigger_1 = 0x1, ///< Select common trigger 1.
|
||||
AdcComTrigger_2 = 0x2, ///< Select common trigger 2.
|
||||
AdcComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2.
|
||||
} en_adc_com_trigger_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Structure definition of ADC
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_adc_ch_cfg
|
||||
{
|
||||
uint32_t u32Channel; ///< ADC channels mask.
|
||||
uint8_t u8Sequence; ///< The sequence which the channel(s) belong to.
|
||||
uint8_t *pu8SampTime; ///< Pointer to sampling time.
|
||||
} stc_adc_ch_cfg_t;
|
||||
|
||||
typedef struct stc_adc_awd_cfg
|
||||
{
|
||||
en_adc_awdmd_t enAwdmd; ///< Comparison mode of the values.
|
||||
en_adc_awdss_t enAwdss; ///< Interrupt output select.
|
||||
uint16_t u16AwdDr0; ///< Your range DR0.
|
||||
uint16_t u16AwdDr1; ///< Your range DR1.
|
||||
} stc_adc_awd_cfg_t;
|
||||
|
||||
typedef struct stc_adc_trg_cfg
|
||||
{
|
||||
uint8_t u8Sequence; ///< The sequence will be configured trigger source.
|
||||
en_adc_trgsel_t enTrgSel; ///< Trigger source type.
|
||||
en_event_src_t enInTrg0; ///< Internal trigger 0 source number
|
||||
///< (event number @ref en_event_src_t).
|
||||
en_event_src_t enInTrg1; ///< Internal trigger 1 source number
|
||||
///< (event number @ref en_event_src_t).
|
||||
} stc_adc_trg_cfg_t;
|
||||
|
||||
typedef struct stc_adc_init
|
||||
{
|
||||
en_adc_resolution_t enResolution; ///< ADC resolution 12bit/10bit/8bit.
|
||||
en_adc_data_align_t enDataAlign; ///< ADC data alignment.
|
||||
en_adc_clren_t enAutoClear; ///< Automatically clear data register.
|
||||
///< after reading data register(enable/disable).
|
||||
en_adc_scan_mode_t enScanMode; ///< ADC scan mode.
|
||||
en_adc_rschsel_t enRschsel; ///< Restart or continue.
|
||||
} stc_adc_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ADC sequence definition.
|
||||
**
|
||||
******************************************************************************/
|
||||
/* ADC sequence definition */
|
||||
#define ADC_SEQ_A ((uint8_t)0)
|
||||
#define ADC_SEQ_B ((uint8_t)1)
|
||||
|
||||
/* ADC pin definition */
|
||||
#define ADC1_IN0 ((uint8_t)0)
|
||||
#define ADC1_IN1 ((uint8_t)1)
|
||||
#define ADC1_IN2 ((uint8_t)2)
|
||||
#define ADC1_IN3 ((uint8_t)3)
|
||||
#define ADC12_IN4 ((uint8_t)4)
|
||||
#define ADC12_IN5 ((uint8_t)5)
|
||||
#define ADC12_IN6 ((uint8_t)6)
|
||||
#define ADC12_IN7 ((uint8_t)7)
|
||||
#define ADC12_IN8 ((uint8_t)8)
|
||||
#define ADC12_IN9 ((uint8_t)9)
|
||||
#define ADC12_IN10 ((uint8_t)10)
|
||||
#define ADC12_IN11 ((uint8_t)11)
|
||||
#define ADC1_IN12 ((uint8_t)12)
|
||||
#define ADC1_IN13 ((uint8_t)13)
|
||||
#define ADC1_IN14 ((uint8_t)14)
|
||||
#define ADC1_IN15 ((uint8_t)15)
|
||||
#define ADC_PIN_INVALID ((uint8_t)0xFF)
|
||||
|
||||
/* ADC channel index definition */
|
||||
#define ADC_CH_IDX0 (0u)
|
||||
#define ADC_CH_IDX1 (1u)
|
||||
#define ADC_CH_IDX2 (2u)
|
||||
#define ADC_CH_IDX3 (3u)
|
||||
#define ADC_CH_IDX4 (4u)
|
||||
#define ADC_CH_IDX5 (5u)
|
||||
#define ADC_CH_IDX6 (6u)
|
||||
#define ADC_CH_IDX7 (7u)
|
||||
#define ADC_CH_IDX8 (8u)
|
||||
#define ADC_CH_IDX9 (9u)
|
||||
#define ADC_CH_IDX10 (10u)
|
||||
#define ADC_CH_IDX11 (11u)
|
||||
#define ADC_CH_IDX12 (12u)
|
||||
#define ADC_CH_IDX13 (13u)
|
||||
#define ADC_CH_IDX14 (14u)
|
||||
#define ADC_CH_IDX15 (15u)
|
||||
#define ADC_CH_IDX16 (16u)
|
||||
|
||||
/* ADC1 channel mask definition */
|
||||
#define ADC1_CH0 (0x1ul << 0u) ///< Default mapping pin ADC1_IN0
|
||||
#define ADC1_CH1 (0x1ul << 1u) ///< Default mapping pin ADC1_IN1
|
||||
#define ADC1_CH2 (0x1ul << 2u) ///< Default mapping pin ADC1_IN2
|
||||
#define ADC1_CH3 (0x1ul << 3u) ///< Default mapping pin ADC1_IN3
|
||||
#define ADC1_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN4
|
||||
#define ADC1_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN5
|
||||
#define ADC1_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN6
|
||||
#define ADC1_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN7
|
||||
#define ADC1_CH8 (0x1ul << 8u) ///< Default mapping pin ADC12_IN8
|
||||
#define ADC1_CH9 (0x1ul << 9u) ///< Default mapping pin ADC12_IN9
|
||||
#define ADC1_CH10 (0x1ul << 10u) ///< Default mapping pin ADC12_IN10
|
||||
#define ADC1_CH11 (0x1ul << 11u) ///< Default mapping pin ADC12_IN11
|
||||
#define ADC1_CH12 (0x1ul << 12u) ///< Default mapping pin ADC12_IN12
|
||||
#define ADC1_CH13 (0x1ul << 13u) ///< Default mapping pin ADC12_IN13
|
||||
#define ADC1_CH14 (0x1ul << 14u) ///< Default mapping pin ADC12_IN14
|
||||
#define ADC1_CH15 (0x1ul << 15u) ///< Default mapping pin ADC12_IN15
|
||||
#define ADC1_CH16 (0x1ul << 16u)
|
||||
#define ADC1_CH_INTERNAL (ADC1_CH16) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC
|
||||
#define ADC1_CH_ALL (0x0001FFFFul)
|
||||
#define ADC1_PIN_MASK_ALL (ADC1_CH_ALL & ~ADC1_CH_INTERNAL)
|
||||
|
||||
/* ADC2 channel definition */
|
||||
#define ADC2_CH0 (0x1ul << 0u) ///< Default mapping pin ADC12_IN4
|
||||
#define ADC2_CH1 (0x1ul << 1u) ///< Default mapping pin ADC12_IN5
|
||||
#define ADC2_CH2 (0x1ul << 2u) ///< Default mapping pin ADC12_IN6
|
||||
#define ADC2_CH3 (0x1ul << 3u) ///< Default mapping pin ADC12_IN7
|
||||
#define ADC2_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN8
|
||||
#define ADC2_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN9
|
||||
#define ADC2_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN10
|
||||
#define ADC2_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN11
|
||||
#define ADC2_CH8 (0x1ul << 8u)
|
||||
#define ADC2_CH_INTERNAL (ADC2_CH8) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC
|
||||
#define ADC2_CH_ALL (0x000001FFul)
|
||||
#define ADC2_PIN_MASK_ALL (ADC2_CH_ALL & ~ADC2_CH_INTERNAL)
|
||||
|
||||
/*
|
||||
* PGA channel definition.
|
||||
* NOTE: The PGA channel directly maps external pins and does not correspond to the ADC channel.
|
||||
*/
|
||||
#define PGA_CH0 (0x1ul << ADC1_IN0) ///< Mapping pin ADC1_IN0
|
||||
#define PGA_CH1 (0x1ul << ADC1_IN1) ///< Mapping pin ADC1_IN1
|
||||
#define PGA_CH2 (0x1ul << ADC1_IN2) ///< Mapping pin ADC1_IN2
|
||||
#define PGA_CH3 (0x1ul << ADC1_IN3) ///< Mapping pin ADC1_IN3
|
||||
#define PGA_CH4 (0x1ul << ADC12_IN4) ///< Mapping pin ADC12_IN4
|
||||
#define PGA_CH5 (0x1ul << ADC12_IN5) ///< Mapping pin ADC12_IN5
|
||||
#define PGA_CH6 (0x1ul << ADC12_IN6) ///< Mapping pin ADC12_IN6
|
||||
#define PGA_CH7 (0x1ul << ADC12_IN7) ///< Mapping pin ADC12_IN7
|
||||
#define PGA_CH8 (0x1ul << ADC12_IN8) ///< Mapping internal 8bit DAC1 output
|
||||
#define PGA_CH_ALL (0x000001FFul)
|
||||
|
||||
/* ADC1 has up to 17 channels */
|
||||
#define ADC1_CH_COUNT (17u)
|
||||
|
||||
/* ADC2 has up to 9 channels */
|
||||
#define ADC2_CH_COUNT (9u)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit);
|
||||
en_result_t ADC_DeInit(M4_ADC_TypeDef *ADCx);
|
||||
|
||||
en_result_t ADC_SetScanMode(M4_ADC_TypeDef *ADCx, en_adc_scan_mode_t enMode);
|
||||
en_result_t ADC_ConfigTriggerSrc(M4_ADC_TypeDef *ADCx, const stc_adc_trg_cfg_t *pstcTrgCfg);
|
||||
en_result_t ADC_TriggerSrcCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState);
|
||||
void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, en_adc_trgsel_t enTrgSel, \
|
||||
en_adc_com_trigger_t enComTrigger, en_functional_state_t enState);
|
||||
|
||||
en_result_t ADC_AddAdcChannel(M4_ADC_TypeDef *ADCx, const stc_adc_ch_cfg_t *pstcChCfg);
|
||||
en_result_t ADC_DelAdcChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
|
||||
en_result_t ADC_SeqITCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState);
|
||||
|
||||
en_result_t ADC_ConfigAvg(M4_ADC_TypeDef *ADCx, en_adc_avcnt_t enAvgCnt);
|
||||
en_result_t ADC_AddAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
|
||||
en_result_t ADC_DelAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
|
||||
|
||||
en_result_t ADC_ConfigAwd(M4_ADC_TypeDef *ADCx, const stc_adc_awd_cfg_t *pstcAwdCfg);
|
||||
en_result_t ADC_AwdCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState);
|
||||
en_result_t ADC_AwdITCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState);
|
||||
en_result_t ADC_AddAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
|
||||
en_result_t ADC_DelAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
|
||||
|
||||
void ADC_ConfigPga(en_adc_pga_factor_t enFactor, en_adc_pga_negative_t enNegativeIn);
|
||||
void ADC_PgaCmd(en_functional_state_t enState);
|
||||
void ADC_AddPgaChannel(uint32_t u32Channel);
|
||||
void ADC_DelPgaChannel(uint32_t u32Channel);
|
||||
|
||||
void ADC_ConfigSync(en_adc_sync_mode_t enMode, uint8_t u8TrgDelay);
|
||||
void ADC_SyncCmd(en_functional_state_t enState);
|
||||
|
||||
en_result_t ADC_StartConvert(M4_ADC_TypeDef *ADCx);
|
||||
en_result_t ADC_StopConvert(M4_ADC_TypeDef *ADCx);
|
||||
en_flag_status_t ADC_GetEocFlag(const M4_ADC_TypeDef *ADCx, uint8_t u8Seq);
|
||||
void ADC_ClrEocFlag(M4_ADC_TypeDef *ADCx, uint8_t u8Seq);
|
||||
en_result_t ADC_PollingSa(M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length, uint32_t u32Timeout);
|
||||
|
||||
en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length);
|
||||
en_result_t ADC_GetChData(const M4_ADC_TypeDef *ADCx, uint32_t u32TargetCh, uint16_t *pu16AdcData, uint8_t u8Length);
|
||||
uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex);
|
||||
|
||||
uint32_t ADC_GetAwdFlag(const M4_ADC_TypeDef *ADCx);
|
||||
void ADC_ClrAwdFlag(M4_ADC_TypeDef *ADCx);
|
||||
void ADC_ClrAwdChFlag(M4_ADC_TypeDef *ADCx, uint32_t u32AwdCh);
|
||||
|
||||
en_result_t ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, uint32_t u32DestChannel, uint8_t u8AdcPin);
|
||||
uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex);
|
||||
|
||||
//@} // AdcGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_ADC_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_ADC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,81 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_aes.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link AesGroup Aes description @endlink
|
||||
**
|
||||
** - 2018-10-20 CDT First version for Device Driver Library of Aes.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_AES_H__
|
||||
#define __HC32F460_AES_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_AES_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup AesGroup Advanced Encryption Standard(AES)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* AES key length in bytes is 16. */
|
||||
#define AES_KEYLEN ((uint8_t)16)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t AES_Encrypt(const uint8_t *pu8Plaintext,
|
||||
uint32_t u32PlaintextSize,
|
||||
const uint8_t *pu8Key,
|
||||
uint8_t *pu8Ciphertext);
|
||||
|
||||
en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext,
|
||||
uint32_t u32CiphertextSize,
|
||||
const uint8_t *pu8Key,
|
||||
uint8_t *pu8Plaintext);
|
||||
|
||||
//@} // AesGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_AES_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_AES_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,518 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_can.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link CanGroup CAN description @endlink
|
||||
**
|
||||
** - 2018-11-27 CDT First version for Device Driver Library of CAN
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_CAN_H__
|
||||
#define __HC32F460_CAN_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_CAN_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup CanGroup Controller Area Network(CAN)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can error types.
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
NO_ERROR = 0U,
|
||||
BIT_ERROR = 1U,
|
||||
FORM_ERROR = 2U,
|
||||
STUFF_ERROR = 3U,
|
||||
ACK_ERROR = 4U,
|
||||
CRC_ERROR = 5U,
|
||||
UNKOWN_ERROR = 6U,
|
||||
}en_can_error_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can transmit buffer select.(TCMD)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanPTBSel = 0U, ///< high-priority buffer
|
||||
CanSTBSel = 1U, ///< secondary buffer
|
||||
}en_can_buffer_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can warning limits.(AFWL)
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_warning_limit
|
||||
{
|
||||
uint8_t CanWarningLimitVal; ///< Receive buffer almost full warning limit
|
||||
uint8_t CanErrorWarningLimitVal; ///< Programmable error warning limit
|
||||
}stc_can_warning_limit_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Acceptance Filters Frame Format Check.(ACF)
|
||||
******************************************************************************/
|
||||
typedef enum en_can_acf_format_en
|
||||
{
|
||||
CanStdFrames = 0x02u, ///< Accepts only Standard frames
|
||||
CanExtFrames = 0x03u, ///< Accepts only Extended frames
|
||||
CanAllFrames = 0x00u, ///< Accepts both standard or extended frames
|
||||
}en_can_acf_format_en_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Acceptance Filters Enable.(ACFEN)
|
||||
******************************************************************************/
|
||||
typedef enum en_can_filter_sel
|
||||
{
|
||||
CanFilterSel1 = 0u, ///< The Acceptance Filter 1 Enable
|
||||
CanFilterSel2 = 1u, ///< The Acceptance Filter 2 Enable
|
||||
CanFilterSel3 = 2u, ///< The Acceptance Filter 3 Enable
|
||||
CanFilterSel4 = 3u, ///< The Acceptance Filter 4 Enable
|
||||
CanFilterSel5 = 4u, ///< The Acceptance Filter 5 Enable
|
||||
CanFilterSel6 = 5u, ///< The Acceptance Filter 6 Enable
|
||||
CanFilterSel7 = 6u, ///< The Acceptance Filter 7 Enable
|
||||
CanFilterSel8 = 7u, ///< The Acceptance Filter 8 Enable
|
||||
}en_can_filter_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The can interrupt enable.(IE)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
//<<Can Rx or Tx Irq En
|
||||
CanRxIrqEn = 0x00000080, ///< Receive interrupt enable
|
||||
CanRxOverIrqEn = 0x00000040, ///< RB overrun interrupt enable
|
||||
CanRxBufFullIrqEn = 0x00000020, ///< RB full interrupt enable
|
||||
CanRxBufAlmostFullIrqEn = 0x00000010, ///< RB almost full interrupt enable
|
||||
CanTxPrimaryIrqEn = 0x00000008, ///< Transmission primary interrupt enable
|
||||
CanTxSecondaryIrqEn = 0x00000004, ///< Transmission secondary enable
|
||||
CanErrorIrqEn = 0x00000002, ///< Error interrupt enable
|
||||
|
||||
//<<Can Error Irq En
|
||||
CanErrorPassiveIrqEn = 0x00200000, ///< Error passive mode active enable
|
||||
CanArbiLostIrqEn = 0x00080000, ///< Arbitration lost interrupt enable
|
||||
CanBusErrorIrqEn = 0x00020000, ///< Bus error interrupt enable
|
||||
}en_can_irq_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The can interrupt flag.(IF)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
//<<Can Tx or Tx Irq Flg
|
||||
CanTxBufFullIrqFlg = 0x00000001, ///<
|
||||
CanRxIrqFlg = 0x00008000, ///< Receive interrupt flag
|
||||
CanRxOverIrqFlg = 0x00004000, ///< RB overrun interrupt flag
|
||||
CanRxBufFullIrqFlg = 0x00002000, ///< RB full interrupt flag
|
||||
CanRxBufAlmostFullIrqFlg = 0x00001000, ///< RB almost full interrupt flag
|
||||
CanTxPrimaryIrqFlg = 0x00000800, ///< Transmission primary interrupt flag
|
||||
CanTxSecondaryIrqFlg = 0x00000400, ///< Transmission secondary interrupt flag
|
||||
CanErrorIrqFlg = 0x00000200, ///< Error interrupt flag
|
||||
CanAbortIrqFlg = 0x00000100, ///< Abort interrupt flag
|
||||
|
||||
//<< Can Error Irq Flg
|
||||
CanErrorWarningIrqFlg = 0x00800000, ///< Error warning limit reached flag
|
||||
CanErrorPassivenodeIrqFlg = 0x00400000, ///< Error passive mode active flag
|
||||
CanErrorPassiveIrqFlg = 0x00100000, ///< Error passive interrupt flag
|
||||
CanArbiLostIrqFlg = 0x00040000, ///< Arbitration lost interrupt flag
|
||||
CanBusErrorIrqFlg = 0x00010000, ///< Bus error interrupt flag
|
||||
}en_can_irq_flag_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The can mode.(TCMD)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanExternalLoopBackMode = 0x40, ///< Loop back mode, external
|
||||
CanInternalLoopBackMode = 0x20, ///< Loop back mode, internal
|
||||
CanTxSignalPrimaryMode = 0x10, ///< Transmission primary single shot mode for PTB
|
||||
CanTxSignalSecondaryMode = 0x08, ///< Transmission secondary single shot mode for STB
|
||||
CanListenOnlyMode = 0xFF, ///< Listen only mode
|
||||
}en_can_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The can status.(STAT)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanRxActive = 0x04, ///< Reception active
|
||||
CanTxActive = 0x02, ///< Transmission active
|
||||
CanBusoff = 0x01, ///< Bus off
|
||||
}en_can_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Tx Command.(TCMD)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanPTBTxCmd = 0x10, ///< Transmit primary for PTB
|
||||
CanPTBTxAbortCmd = 0x08, ///< Transmit primary abort for PTB
|
||||
CanSTBTxOneCmd = 0x04, ///< Transmit secondary one frame for STB
|
||||
CanSTBTxAllCmd = 0x02, ///< Transmit secondary all frames for STB
|
||||
CanSTBTxAbortCmd = 0x01, ///< Transmit secondary abort for STB
|
||||
}en_can_tx_cmd_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Transmit buffer secondary operation mode.(TCTRL)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanSTBFifoMode = 0, ///< FIFO mode
|
||||
CanSTBPrimaryMode = 1, ///< Priority decision mode
|
||||
}en_can_stb_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Self-ACKnowledge.(RCTRL)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanSelfAckEnable = 1, ///< Self-ACK when LBME=1
|
||||
CanSelfAckDisable = 0, ///< no self-ACK
|
||||
}en_can_self_ack_en_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Receive Buffer Overflow Mode.(RCTRL)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanRxBufOverwritten = 0, ///< The oldest message will be overwritten
|
||||
CanRxBufNotStored = 1, ///< The new message will not be stored
|
||||
}en_can_rx_buf_mode_en_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Receive Buffer Stores All data frames.(RCTRL)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanRxNormal = 0, ///< Normal operation
|
||||
CanRxAll = 1, ///< RB stores correct data frames as well as data frames with error
|
||||
}en_can_rx_buf_all_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Receive Buffer Status.(RSTAT)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanRxBufEmpty = 0, ///< Empty
|
||||
CanRxBufnotAlmostFull = 1, ///< >empty and <almost full
|
||||
CanRxBufAlmostFull = 2, ///< >=almost full, but not full and no overflow
|
||||
CanRxBufFull = 3, ///< full
|
||||
}en_can_rx_buf_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Transmission secondary Status.(TSSTAT)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanTxBufEmpty = 0, ///< TTEN=0 or TTTBM=0: STB is empty
|
||||
///< TTEN=1 and TTTBM=1: PTB and STB are empty
|
||||
CanTxBufnotHalfFull = 1, ///< TTEN=0 or TTTBM=0: STB is less than or equal to half full
|
||||
///< TTEN=1 and TTTBM=1: PTB and STB are not empty and not full
|
||||
CanTxBufHalfFull = 2, ///< TTEN=0 or TTTBM=0: STB is more than half full
|
||||
///< TTEN=1 and TTTBM=1: None
|
||||
CanTxBufFull = 3, ///< TTEN=0 or TTTBM=0: STB is full
|
||||
///< TTEN=1 and TTTBM=1: PTB and STB are full
|
||||
}en_can_tx_buf_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Acceptance Filter Code and Mask.
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_filter
|
||||
{
|
||||
uint32_t u32CODE; ///< Acceptance CODE
|
||||
uint32_t u32MASK; ///< Acceptance MASK
|
||||
en_can_filter_sel_t enFilterSel; ///< The Acceptance Filters Enable
|
||||
en_can_acf_format_en_t enAcfFormat; ///< The Acceptance Filters Frame Format Check.
|
||||
}stc_can_filter_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Bit Timing.
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_bt
|
||||
{
|
||||
uint8_t SEG_1; ///< Bit timing segment 1(Tseg_1 = (SEG_1 + 2)*TQ)
|
||||
uint8_t SEG_2; ///< Bit timing segment 2(Tseg_2 = (SEG_2 + 1)*TQ)
|
||||
uint8_t SJW; ///< Synchronization jump width(Tsjw = (SJW + 1)*TQ)
|
||||
uint8_t PRESC; ///< The Prescaler divides the system clock to get the time quanta clock tq_clk(TQ)
|
||||
}stc_can_bt_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Control Frame.
|
||||
******************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DLC : 4; ///< Data length code
|
||||
uint32_t RESERVED0 : 2; ///< Ignore
|
||||
uint32_t RTR : 1; ///< Remote transmission request
|
||||
uint32_t IDE : 1; ///< IDentifier extension
|
||||
uint32_t RESERVED1 : 24; ///< Ignore
|
||||
}stc_can_txcontrol_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Tx Frame.
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_txframe
|
||||
{
|
||||
union
|
||||
{
|
||||
uint32_t TBUF32_0; ///< Ignore
|
||||
uint32_t StdID; ///< Standard ID
|
||||
uint32_t ExtID; ///< Extended ID
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t TBUF32_1; ///< Ignore
|
||||
stc_can_txcontrol_t Control_f; ///< CAN Tx Control
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t TBUF32_2[2]; ///< Ignore
|
||||
uint8_t Data[8]; ///< CAN data
|
||||
};
|
||||
en_can_buffer_sel_t enBufferSel; ///< CAN Tx buffer select
|
||||
}stc_can_txframe_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Rx Ctrl.
|
||||
******************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DLC : 4; ///< Data length code
|
||||
uint8_t RESERVED0 : 2; ///< Ignore
|
||||
uint8_t RTR : 1; ///< Remote transmission request
|
||||
uint8_t IDE : 1; ///< IDentifier extension
|
||||
}stc_can_rxcontrol_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN status.
|
||||
******************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RESERVED0 : 4; ///< Ignore
|
||||
uint8_t TX : 1; ///< TX is set to 1 if the loop back mode is activated
|
||||
uint8_t KOER : 3; ///< Kind of error
|
||||
}stc_can_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN control, status and cycletime.
|
||||
******************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
stc_can_rxcontrol_t Control_f; ///< @ref stc_can_rxcontrol_t
|
||||
stc_can_status_t Status_f; ///< @ref stc_can_status_t
|
||||
uint16_t CycleTime; ///< TTCAN cycletime
|
||||
}stc_can_cst_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Rx frame.
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_rxframe
|
||||
{
|
||||
union
|
||||
{
|
||||
uint32_t RBUF32_0; ///< Ignore
|
||||
uint32_t StdID; ///< Standard ID
|
||||
uint32_t ExtID; ///< Extended ID
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t RBUF32_1; ///< Ignore
|
||||
stc_can_cst_t Cst; ///< @ref stc_can_cst_t
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t RBUF32_2[2]; ///< Ignore
|
||||
uint8_t Data[8]; ///< CAN data
|
||||
};
|
||||
}stc_can_rxframe_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Rx frame.
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_init_config
|
||||
{
|
||||
en_can_rx_buf_all_t enCanRxBufAll; ///< @ref en_can_rx_buf_all_t
|
||||
en_can_rx_buf_mode_en_t enCanRxBufMode; ///< @ref en_can_rx_buf_mode_en_t
|
||||
en_can_self_ack_en_t enCanSAck; ///< @ref en_can_self_ack_en_t
|
||||
en_can_stb_mode_t enCanSTBMode; ///< @ref en_can_stb_mode_t
|
||||
stc_can_bt_t stcCanBt; ///< @ref stc_can_bt_t
|
||||
stc_can_warning_limit_t stcWarningLimit; ///< @ref stc_can_warning_limit_t
|
||||
stc_can_filter_t *pstcFilter; ///< @ref stc_can_filter_t Pointer to a stc_can_filter_t type array that \
|
||||
///< contains the configuration informations of the acceptance filters.
|
||||
uint8_t u8FilterCount; ///< Number of filters that to to initialized.
|
||||
}stc_can_init_config_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CAN TTCAN
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN TTCAN pointer to a TB message slot
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanTTcanPTBSel = 0x00u, ///< PTB
|
||||
CanTTcanSTB1Sel = 0x01u, ///< STB1
|
||||
CanTTcanSTB2Sel = 0x02u, ///< STB2
|
||||
CanTTcanSTB3Sel = 0x03u, ///< STB3
|
||||
CanTTcanSTB4Sel = 0x04u, ///< STB4
|
||||
}en_can_ttcan_tbslot_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN TTCAN Timer prescaler
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanTTcanTprescDiv1 = 0x00u, ///< Div1
|
||||
CanTTcanTprescDiv2 = 0x01u, ///< Div2
|
||||
CanTTcanTprescDiv3 = 0x02u, ///< Div3
|
||||
CanTTcanTprescDiv4 = 0x03u, ///< Div4
|
||||
}en_can_ttcan_Tpresc_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN TTCAN Trigger type
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanTTcanImmediate = 0x00, ///< Immediate trigger for immediate transmission
|
||||
CanTTcanTime = 0x01, ///< Time trigger for receive trigger
|
||||
CanTTcanSingle = 0x02, ///< Single shot transmit trigger for exclusive time windows
|
||||
CanTTcanTransStart = 0x03, ///< Transmit start trigger for merged arbitrating time windows
|
||||
CanTTcanTransStop = 0x04, ///< Transmit stop trigger for merged arbitrating time windows
|
||||
}en_can_ttcan_trigger_type_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
CanTTcanWdtTriggerIrq = 0x80, ///< Watch trigger interrupt
|
||||
CanTTcanTimTriggerIrq = 0x10, ///< Time trigger interrupt
|
||||
}en_can_ttcan_irq_type_t;
|
||||
|
||||
|
||||
typedef struct stc_can_ttcan_ref_msg
|
||||
{
|
||||
uint8_t u8IDE; ///< Reference message IDE:1-Extended; 0-Standard;
|
||||
union ///< Reference message ID
|
||||
{
|
||||
uint32_t RefStdID; ///< Reference standard ID
|
||||
uint32_t RefExtID; ///< Reference Extended ID
|
||||
};
|
||||
}stc_can_ttcan_ref_msg_t;
|
||||
|
||||
typedef struct stc_can_ttcan_trigger_config
|
||||
{
|
||||
en_can_ttcan_tbslot_t enTbSlot; ///< Transmit trigger TB slot pointer
|
||||
en_can_ttcan_trigger_type_t enTrigType; ///< Trigger type
|
||||
en_can_ttcan_Tpresc_t enTpresc; ///< Timer prescaler
|
||||
uint8_t u8Tew; ///< Transmit enable window
|
||||
uint16_t u16TrigTime; ///< TTCAN trigger time
|
||||
uint16_t u16WatchTrigTime; ///< TTCAN watch trigger time register
|
||||
}stc_can_ttcan_trigger_config_t;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void CAN_Init(const stc_can_init_config_t *pstcCanInitCfg);
|
||||
void CAN_DeInit(void);
|
||||
void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState);
|
||||
bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType);
|
||||
void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType);
|
||||
void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState);
|
||||
en_can_error_t CAN_ErrorStatusGet(void);
|
||||
bool CAN_StatusGet(en_can_status_t enCanStatus);
|
||||
|
||||
void CAN_FilterConfig(const stc_can_filter_t pstcFilter[], uint8_t u8FilterCount);
|
||||
void CAN_FilterCmd(en_can_filter_sel_t enFilter, en_functional_state_t enNewState);
|
||||
|
||||
void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame);
|
||||
en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd);
|
||||
en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame);
|
||||
|
||||
uint8_t CAN_ArbitrationLostCap(void);
|
||||
uint8_t CAN_RxErrorCntGet(void);
|
||||
uint8_t CAN_TxErrorCntGet(void);
|
||||
|
||||
|
||||
//<< void CAN_TTCAN_Enable(void);
|
||||
//<< void CAN_TTCAN_Disable(void);
|
||||
//<< void CAN_TTCAN_IrqCmd(void);
|
||||
//<< void CAN_TTCAN_ReferenceMsgSet(stc_can_ttcan_ref_msg_t *pstcRefMsg);
|
||||
//<< void CAN_TTCAN_TriggerConfig(stc_can_ttcan_trigger_config_t *pstcTriggerCfg);
|
||||
|
||||
//@} // CanGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_CAN_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_CAN_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
||||
@@ -0,0 +1,514 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_can.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link CanGroup CAN description @endlink
|
||||
**
|
||||
** - 2018-11-27 CDT First version for Device Driver Library of CAN
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_CAN_H__
|
||||
#define __HC32F460_CAN_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_CAN_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup CanGroup Controller Area Network(CAN)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can error types.
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
NO_ERROR = 0U,
|
||||
BIT_ERROR = 1U,
|
||||
FORM_ERROR = 2U,
|
||||
STUFF_ERROR = 3U,
|
||||
ACK_ERROR = 4U,
|
||||
CRC_ERROR = 5U,
|
||||
UNKOWN_ERROR = 6U,
|
||||
}en_can_error_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can transmit buffer select.(TCMD)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanPTBSel = 0U, ///< high-priority buffer
|
||||
CanSTBSel = 1U, ///< secondary buffer
|
||||
}en_can_buffer_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can warning limits.(AFWL)
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_warning_limit
|
||||
{
|
||||
uint8_t CanWarningLimitVal; ///< Receive buffer almost full warning limit
|
||||
uint8_t CanErrorWarningLimitVal; ///< Programmable error warning limit
|
||||
}stc_can_warning_limit_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Acceptance Filters Frame Format Check.(ACF)
|
||||
******************************************************************************/
|
||||
typedef enum en_can_acf_format_en
|
||||
{
|
||||
CanStdFrames = 0x02u, ///< Accepts only Standard frames
|
||||
CanExtFrames = 0x03u, ///< Accepts only Extended frames
|
||||
CanAllFrames = 0x00u, ///< Accepts both standard or extended frames
|
||||
}en_can_acf_format_en_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Acceptance Filters Enable.(ACFEN)
|
||||
******************************************************************************/
|
||||
typedef enum en_can_filter_sel
|
||||
{
|
||||
CanFilterSel1 = 0u, ///< The Acceptance Filter 1 Enable
|
||||
CanFilterSel2 = 1u, ///< The Acceptance Filter 2 Enable
|
||||
CanFilterSel3 = 2u, ///< The Acceptance Filter 3 Enable
|
||||
CanFilterSel4 = 3u, ///< The Acceptance Filter 4 Enable
|
||||
CanFilterSel5 = 4u, ///< The Acceptance Filter 5 Enable
|
||||
CanFilterSel6 = 5u, ///< The Acceptance Filter 6 Enable
|
||||
CanFilterSel7 = 6u, ///< The Acceptance Filter 7 Enable
|
||||
CanFilterSel8 = 7u, ///< The Acceptance Filter 8 Enable
|
||||
}en_can_filter_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The can interrupt enable.(IE)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
//<<Can Rx or Tx Irq En
|
||||
CanRxIrqEn = 0x00000080, ///< Receive interrupt enable
|
||||
CanRxOverIrqEn = 0x00000040, ///< RB overrun interrupt enable
|
||||
CanRxBufFullIrqEn = 0x00000020, ///< RB full interrupt enable
|
||||
CanRxBufAlmostFullIrqEn = 0x00000010, ///< RB almost full interrupt enable
|
||||
CanTxPrimaryIrqEn = 0x00000008, ///< Transmission primary interrupt enable
|
||||
CanTxSecondaryIrqEn = 0x00000004, ///< Transmission secondary enable
|
||||
CanErrorIrqEn = 0x00000002, ///< Error interrupt enable
|
||||
|
||||
//<<Can Error Irq En
|
||||
CanErrorPassiveIrqEn = 0x00200000, ///< Error passive mode active enable
|
||||
CanArbiLostIrqEn = 0x00080000, ///< Arbitration lost interrupt enable
|
||||
CanBusErrorIrqEn = 0x00020000, ///< Bus error interrupt enable
|
||||
|
||||
}en_can_irq_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The can interrupt flag.(IF)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
//<<Can Tx or Tx Irq Flg
|
||||
CanTxBufFullIrqFlg = 0x00000001, ///<
|
||||
CanRxIrqFlg = 0x00008000, ///< Receive interrupt flag
|
||||
CanRxOverIrqFlg = 0x00004000, ///< RB overrun interrupt flag
|
||||
CanRxBufFullIrqFlg = 0x00002000, ///< RB full interrupt flag
|
||||
CanRxBufAlmostFullIrqFlg = 0x00001000, ///< RB almost full interrupt flag
|
||||
CanTxPrimaryIrqFlg = 0x00000800, ///< Transmission primary interrupt flag
|
||||
CanTxSecondaryIrqFlg = 0x00000400, ///< Transmission secondary interrupt flag
|
||||
CanErrorIrqFlg = 0x00000200, ///< Error interrupt flag
|
||||
CanAbortIrqFlg = 0x00000100, ///< Abort interrupt flag
|
||||
|
||||
//<< Can Error Irq Flg
|
||||
CanErrorWarningIrqFlg = 0x00800000, ///< Error warning limit reached flag
|
||||
CanErrorPassivenodeIrqFlg = 0x00400000, ///< Error passive mode active flag
|
||||
CanErrorPassiveIrqFlg = 0x00100000, ///< Error passive interrupt flag
|
||||
CanArbiLostIrqFlg = 0x00040000, ///< Arbitration lost interrupt flag
|
||||
CanBusErrorIrqFlg = 0x00010000, ///< Bus error interrupt flag
|
||||
}en_can_irq_flag_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The can mode.(TCMD)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanExternalLoopBackMode = 0x40, ///< Loop back mode, external
|
||||
CanInternalLoopBackMode = 0x20, ///< Loop back mode, internal
|
||||
CanTxSignalPrimaryMode = 0x10, ///< Transmission primary single shot mode for PTB
|
||||
CanTxSignalSecondaryMode = 0x08, ///< Transmission secondary single shot mode for STB
|
||||
CanListenOnlyMode = 0xFF, ///< Listen only mode
|
||||
}en_can_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The can status.(STAT)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanRxActive = 0x04, ///< Reception active
|
||||
CanTxActive = 0x02, ///< Transmission active
|
||||
CanBusoff = 0x01, ///< Bus off
|
||||
}en_can_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Tx Command.(TCMD)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanPTBTxCmd = 0x10, ///< Transmit primary for PTB
|
||||
CanPTBTxAbortCmd = 0x08, ///< Transmit primary abort for PTB
|
||||
CanSTBTxOneCmd = 0x04, ///< Transmit secondary one frame for STB
|
||||
CanSTBTxAllCmd = 0x02, ///< Transmit secondary all frames for STB
|
||||
CanSTBTxAbortCmd = 0x01, ///< Transmit secondary abort for STB
|
||||
}en_can_tx_cmd_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Transmit buffer secondary operation mode.(TCTRL)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanSTBFifoMode = 0, ///< FIFO mode
|
||||
CanSTBPrimaryMode = 1, ///< Priority decision mode
|
||||
}en_can_stb_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Self-ACKnowledge.(RCTRL)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanSelfAckEnable = 1, ///< Self-ACK when LBME=1
|
||||
CanSelfAckDisable = 0, ///< no self-ACK
|
||||
}en_can_self_ack_en_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Receive Buffer Overflow Mode.(RCTRL)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanRxBufOverwritten = 0, ///< The oldest message will be overwritten
|
||||
CanRxBufNotStored = 1, ///< The new message will not be stored
|
||||
}en_can_rx_buf_mode_en_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Receive Buffer Stores All data frames.(RCTRL)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanRxNormal = 0, ///< Normal operation
|
||||
CanRxAll = 1, ///< RB stores correct data frames as well as data frames with error
|
||||
}en_can_rx_buf_all_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Receive Buffer Status.(RSTAT)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanRxBufEmpty = 0, ///< Empty
|
||||
CanRxBufnotAlmostFull = 1, ///< >empty and <almost full
|
||||
CanRxBufAlmostFull = 2, ///< >=almost full, but not full and no overflow
|
||||
CanRxBufFull = 3, ///< full
|
||||
}en_can_rx_buf_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The Can Transmission secondary Status.(TSSTAT)
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanTxBufEmpty = 0, ///< TTEN=0 or TTTBM=0: STB is empty
|
||||
///< TTEN=1 and TTTBM=1: PTB and STB are empty
|
||||
CanTxBufnotHalfFull = 1, ///< TTEN=0 or TTTBM=0: STB is less than or equal to half full
|
||||
///< TTEN=1 and TTTBM=1: PTB and STB are not empty and not full
|
||||
CanTxBufHalfFull = 2, ///< TTEN=0 or TTTBM=0: STB is more than half full
|
||||
///< TTEN=1 and TTTBM=1: None
|
||||
CanTxBufFull = 3, ///< TTEN=0 or TTTBM=0: STB is full
|
||||
///< TTEN=1 and TTTBM=1: PTB and STB are full
|
||||
}en_can_tx_buf_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Acceptance Filter Code and Mask.
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_filter
|
||||
{
|
||||
uint32_t u32CODE; ///< Acceptance CODE
|
||||
uint32_t u32MASK; ///< Acceptance MASK
|
||||
en_can_filter_sel_t enFilterSel; ///< The Acceptance Filters Enable
|
||||
en_can_acf_format_en_t enAcfFormat; ///< The Acceptance Filters Frame Format Check.
|
||||
}stc_can_filter_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Bit Timing.
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_bt
|
||||
{
|
||||
uint8_t SEG_1; ///< Bit timing segment 1(Tseg_1 = (SEG_1 + 2)*TQ)
|
||||
uint8_t SEG_2; ///< Bit timing segment 2(Tseg_2 = (SEG_2 + 1)*TQ)
|
||||
uint8_t SJW; ///< Synchronization jump width(Tsjw = (SJW + 1)*TQ)
|
||||
uint8_t PRESC; ///< The Prescaler divides the system clock to get the time quanta clock tq_clk(TQ)
|
||||
}stc_can_bt_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Control Frame.
|
||||
******************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DLC : 4; ///< Data length code
|
||||
uint32_t RESERVED0 : 2; ///< Ignore
|
||||
uint32_t RTR : 1; ///< Remote transmission request
|
||||
uint32_t IDE : 1; ///< IDentifier extension
|
||||
uint32_t RESERVED1 : 24; ///< Ignore
|
||||
}stc_can_txcontrol_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Tx Frame.
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_txframe
|
||||
{
|
||||
union
|
||||
{
|
||||
uint32_t TBUF32_0; ///< Ignore
|
||||
uint32_t StdID; ///< Standard ID
|
||||
uint32_t ExtID; ///< Extended ID
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t TBUF32_1; ///< Ignore
|
||||
stc_can_txcontrol_t Control_f; ///< CAN Tx Control
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t TBUF32_2[2]; ///< Ignore
|
||||
uint8_t Data[8]; ///< CAN data
|
||||
};
|
||||
en_can_buffer_sel_t enBufferSel; ///< CAN Tx buffer select
|
||||
}stc_can_txframe_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Rx Ctrl.
|
||||
******************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DLC : 4; ///< Data length code
|
||||
uint8_t RESERVED0 : 2; ///< Ignore
|
||||
uint8_t RTR : 1; ///< Remote transmission request
|
||||
uint8_t IDE : 1; ///< IDentifier extension
|
||||
}stc_can_rxcontrol_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN status.
|
||||
******************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RESERVED0 : 4; ///< Ignore
|
||||
uint8_t TX : 1; ///< TX is set to 1 if the loop back mode is activated
|
||||
uint8_t KOER : 3; ///< Kind of error
|
||||
}stc_can_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN control, status and cycletime.
|
||||
******************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
stc_can_rxcontrol_t Control_f; ///< @ref stc_can_rxcontrol_t
|
||||
stc_can_status_t Status_f; ///< @ref stc_can_status_t
|
||||
uint16_t CycleTime; ///< TTCAN cycletime
|
||||
}stc_can_cst_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Rx frame.
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_rxframe
|
||||
{
|
||||
union
|
||||
{
|
||||
uint32_t RBUF32_0; ///< Ignore
|
||||
uint32_t StdID; ///< Standard ID
|
||||
uint32_t ExtID; ///< Extended ID
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t RBUF32_1; ///< Ignore
|
||||
stc_can_cst_t Cst; ///< @ref stc_can_cst_t
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t RBUF32_2[2]; ///< Ignore
|
||||
uint8_t Data[8]; ///< CAN data
|
||||
};
|
||||
}stc_can_rxframe_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN Rx frame.
|
||||
******************************************************************************/
|
||||
typedef struct stc_can_init_config
|
||||
{
|
||||
en_can_rx_buf_all_t enCanRxBufAll; ///< @ref en_can_rx_buf_all_t
|
||||
en_can_rx_buf_mode_en_t enCanRxBufMode; ///< @ref en_can_rx_buf_mode_en_t
|
||||
en_can_self_ack_en_t enCanSAck; ///< @ref en_can_self_ack_en_t
|
||||
en_can_stb_mode_t enCanSTBMode; ///< @ref en_can_stb_mode_t
|
||||
stc_can_bt_t stcCanBt; ///< @ref stc_can_bt_t
|
||||
stc_can_warning_limit_t stcWarningLimit; ///< @ref stc_can_warning_limit_t
|
||||
}stc_can_init_config_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CAN TTCAN
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN TTCAN pointer to a TB message slot
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanTTcanPTBSel = 0x00u, ///< PTB
|
||||
CanTTcanSTB1Sel = 0x01u, ///< STB1
|
||||
CanTTcanSTB2Sel = 0x02u, ///< STB2
|
||||
CanTTcanSTB3Sel = 0x03u, ///< STB3
|
||||
CanTTcanSTB4Sel = 0x04u, ///< STB4
|
||||
}en_can_ttcan_tbslot_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN TTCAN Timer prescaler
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanTTcanTprescDiv1 = 0x00u, ///< Div1
|
||||
CanTTcanTprescDiv2 = 0x01u, ///< Div2
|
||||
CanTTcanTprescDiv3 = 0x02u, ///< Div3
|
||||
CanTTcanTprescDiv4 = 0x03u, ///< Div4
|
||||
}en_can_ttcan_Tpresc_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of CAN TTCAN Trigger type
|
||||
******************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
CanTTcanImmediate = 0x00, ///< Immediate trigger for immediate transmission
|
||||
CanTTcanTime = 0x01, ///< Time trigger for receive trigger
|
||||
CanTTcanSingle = 0x02, ///< Single shot transmit trigger for exclusive time windows
|
||||
CanTTcanTransStart = 0x03, ///< Transmit start trigger for merged arbitrating time windows
|
||||
CanTTcanTransStop = 0x04, ///< Transmit stop trigger for merged arbitrating time windows
|
||||
}en_can_ttcan_trigger_type_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
CanTTcanWdtTriggerIrq = 0x80, ///< Watch trigger interrupt
|
||||
CanTTcanTimTriggerIrq = 0x10, ///< Time trigger interrupt
|
||||
}en_can_ttcan_irq_type_t;
|
||||
|
||||
|
||||
typedef struct stc_can_ttcan_ref_msg
|
||||
{
|
||||
uint8_t u8IDE; ///< Reference message IDE:1-Extended; 0-Standard;
|
||||
union ///< Reference message ID
|
||||
{
|
||||
uint32_t RefStdID; ///< Reference standard ID
|
||||
uint32_t RefExtID; ///< Reference Extended ID
|
||||
};
|
||||
}stc_can_ttcan_ref_msg_t;
|
||||
|
||||
typedef struct stc_can_ttcan_trigger_config
|
||||
{
|
||||
en_can_ttcan_tbslot_t enTbSlot; ///< Transmit trigger TB slot pointer
|
||||
en_can_ttcan_trigger_type_t enTrigType; ///< Trigger type
|
||||
en_can_ttcan_Tpresc_t enTpresc; ///< Timer prescaler
|
||||
uint8_t u8Tew; ///< Transmit enable window
|
||||
uint16_t u16TrigTime; ///< TTCAN trigger time
|
||||
uint16_t u16WatchTrigTime; ///< TTCAN watch trigger time register
|
||||
}stc_can_ttcan_trigger_config_t;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void CAN_Init(stc_can_init_config_t *pstcCanInitCfg);
|
||||
void CAN_DeInit(void);
|
||||
void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState);
|
||||
bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType);
|
||||
void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType);
|
||||
void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState);
|
||||
en_can_error_t CAN_ErrorStatusGet(void);
|
||||
bool CAN_StatusGet(en_can_status_t enCanStatus);
|
||||
|
||||
void CAN_FilterConfig(const stc_can_filter_t *pstcFilter, en_functional_state_t enNewState);
|
||||
void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame);
|
||||
en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd);
|
||||
en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame);
|
||||
|
||||
uint8_t CAN_ArbitrationLostCap(void);
|
||||
uint8_t CAN_RxErrorCntGet(void);
|
||||
uint8_t CAN_TxErrorCntGet(void);
|
||||
|
||||
|
||||
//<< void CAN_TTCAN_Enable(void);
|
||||
//<< void CAN_TTCAN_Disable(void);
|
||||
//<< void CAN_TTCAN_IrqCmd(void);
|
||||
//<< void CAN_TTCAN_ReferenceMsgSet(stc_can_ttcan_ref_msg_t *pstcRefMsg);
|
||||
//<< void CAN_TTCAN_TriggerConfig(stc_can_ttcan_trigger_config_t *pstcTriggerCfg);
|
||||
|
||||
//@} // CanGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_CAN_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_CAN_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
||||
@@ -0,0 +1,647 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_clk.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link CmuGroup Clock description @endlink
|
||||
**
|
||||
** - 2018-10-13 CDT First version for Device Driver Library of CMU.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_CLK_H__
|
||||
#define __HC32F460_CLK_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_CLK_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup CmuGroup Clock Manage Unit(CMU)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The system clock source.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_sys_source
|
||||
{
|
||||
ClkSysSrcHRC = 0u, ///< The system clock source is HRC.
|
||||
ClkSysSrcMRC = 1u, ///< The system clock source is MRC.
|
||||
ClkSysSrcLRC = 2u, ///< The system clock source is LRC.
|
||||
ClkSysSrcXTAL = 3u, ///< The system clock source is XTAL.
|
||||
ClkSysSrcXTAL32 = 4u, ///< The system clock source is XTAL32.
|
||||
CLKSysSrcMPLL = 5u, ///< The system clock source is MPLL.
|
||||
}en_clk_sys_source_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The pll clock source.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_pll_source
|
||||
{
|
||||
ClkPllSrcXTAL = 0u, ///< The pll clock source is XTAL.
|
||||
ClkPllSrcHRC = 1u, ///< The pll clock source is HRC.
|
||||
}en_clk_pll_source_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The usb clock source.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_usb_source
|
||||
{
|
||||
ClkUsbSrcSysDiv2 = 2u, ///< The usb clock source is 1/2 system clock.
|
||||
ClkUsbSrcSysDiv3 = 3u, ///< The usb clock source is 1/3 system clock.
|
||||
ClkUsbSrcSysDiv4 = 4u, ///< The usb clock source is 1/4 system clock.
|
||||
ClkUsbSrcMpllp = 8u, ///< The usb clock source is MPLLP.
|
||||
ClkUsbSrcMpllq = 9u, ///< The usb clock source is MPLLQ.
|
||||
ClkUsbSrcMpllr = 10u, ///< The usb clock source is MPLLR.
|
||||
ClkUsbSrcUpllp = 11u, ///< The usb clock source is UPLLP.
|
||||
ClkUsbSrcUpllq = 12u, ///< The usb clock source is UPLLQ.
|
||||
ClkUsbSrcUpllr = 13u, ///< The usb clock source is UPLLR.
|
||||
}en_clk_usb_source_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The peripheral(adc/trng/I2S) clock source.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_peri_source
|
||||
{
|
||||
ClkPeriSrcPclk = 0u, ///< The peripheral(adc/trng/I2S) clock source is division from system clock.
|
||||
ClkPeriSrcMpllp = 8u, ///< The peripheral(adc/trng/I2S) clock source is MPLLP.
|
||||
ClkPeriSrcMpllq = 9u, ///< The peripheral(adc/trng/I2S) clock source is MPLLQ.
|
||||
ClkPeriSrcMpllr = 10u, ///< The peripheral(adc/trng/I2S) clock source is MPLLR.
|
||||
ClkPeriSrcUpllp = 11u, ///< The peripheral(adc/trng/I2S) clock source is UPLLP.
|
||||
ClkPeriSrcUpllq = 12u, ///< The peripheral(adc/trng/I2S) clock source is UPLLQ.
|
||||
ClkPeriSrcUpllr = 13u, ///< The peripheral(adc/trng/I2S) clock source is UPLLR.
|
||||
}en_clk_peri_source_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The clock output source.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_output_source
|
||||
{
|
||||
ClkOutputSrcHrc = 0u, ///< The clock output source is HRC
|
||||
ClkOutputSrcMrc = 1u, ///< The clock output source is MRC.
|
||||
ClkOutputSrcLrc = 2u, ///< The clock output source is LRC.
|
||||
ClkOutputSrcXtal = 3u, ///< The clock output source is XTAL.
|
||||
ClkOutputSrcXtal32 = 4u, ///< The clock output source is XTAL32
|
||||
ClkOutputSrcMpllp = 6u, ///< The clock output source is MPLLP.
|
||||
ClkOutputSrcUpllp = 7u, ///< The clock output source is UPLLP.
|
||||
ClkOutputSrcMpllq = 8u, ///< The clock output source is MPLLQ.
|
||||
ClkOutputSrcUpllq = 9u, ///< The clock output source is UPLLQ.
|
||||
ClkOutputSrcSysclk = 11u, ///< The clock output source is system clock.
|
||||
}en_clk_output_source_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The clock frequency source for measure or reference.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_fcm_source
|
||||
{
|
||||
ClkFcmSrcXtal = 0u, ///< The clock frequency measure or reference source is XTAL
|
||||
ClkFcmSrcXtal32 = 1u, ///< The clock frequency measure or reference source is XTAL32.
|
||||
ClkFcmSrcHrc = 2u, ///< The clock frequency measure or reference source is HRC.
|
||||
ClkFcmSrcLrc = 3u, ///< The clock frequency measure or reference source is LRC.
|
||||
ClkFcmSrcSwdtrc = 4u, ///< The clock frequency measure or reference source is SWDTRC
|
||||
ClkFcmSrcPclk1 = 5u, ///< The clock frequency measure or reference source is PCLK1.
|
||||
ClkFcmSrcUpllp = 6u, ///< The clock frequency measure or reference source is UPLLP.
|
||||
ClkFcmSrcMrc = 7u, ///< The clock frequency measure or reference source is MRC.
|
||||
ClkFcmSrcMpllp = 8u, ///< The clock frequency measure or reference source is MPLLP.
|
||||
ClkFcmSrcRtcLrc = 9u, ///< The clock frequency measure or reference source is RTCLRC.
|
||||
}en_clk_fcm_intref_source_t,en_clk_fcm_measure_source_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The clock flag status.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_flag
|
||||
{
|
||||
ClkFlagHRCRdy = 0u, ///< The clock flag is HRC ready.
|
||||
ClkFlagXTALRdy = 1u, ///< The clock flag is XTAL ready.
|
||||
ClkFlagMPLLRdy = 2u, ///< The clock flag is MPLL ready.
|
||||
ClkFlagUPLLRdy = 3u, ///< The clock flag is UPLL ready.
|
||||
ClkFlagXTALStoppage = 4u, ///< The clock flag is XTAL stoppage.
|
||||
}en_clk_flag_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The clock frequency measure flag status.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_fcm_flag
|
||||
{
|
||||
ClkFcmFlagErrf = 0u, ///< The clock frequency flag is frequency abnormal.
|
||||
ClkFcmFlagMendf = 1u, ///< The clock frequency flag is end of measurement.
|
||||
ClkFcmFlagOvf = 2u, ///< The clock frequency flag is counter overflow.
|
||||
}en_clk_fcm_flag_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The source of xtal.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_xtal_mode
|
||||
{
|
||||
ClkXtalModeOsc = 0u, ///< Use external high speed osc as source.
|
||||
ClkXtalModeExtClk = 1u, ///< Use external clk as source.
|
||||
}en_clk_xtal_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The drive capability of xtal.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_xtal_drv
|
||||
{
|
||||
ClkXtalHighDrv = 0u, ///< High drive capability.20MHz~24MHz.
|
||||
ClkXtalMidDrv = 1u, ///< Middle drive capability.16MHz~20MHz.
|
||||
ClkXtalLowDrv = 2u, ///< Low drive capability.8MHz~16MHz.
|
||||
ClkXtalTinyDrv = 3u, ///< Tiny drive capability.8MHz.
|
||||
}en_clk_xtal_drv_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The stable time of XTAL.
|
||||
**
|
||||
** \note It depends on SUPDRV bit.
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_xtal_stb_cycle
|
||||
{
|
||||
ClkXtalStbCycle35 = 1u, ///< stable time is 35(36) cycle.
|
||||
ClkXtalStbCycle67 = 2u, ///< stable time is 67(68) cycle.
|
||||
ClkXtalStbCycle131 = 3u, ///< stable time is 131(132) cycle.
|
||||
ClkXtalStbCycle259 = 4u, ///< stable time is 259(260) cycle.
|
||||
ClkXtalStbCycle547 = 5u, ///< stable time is 547(548) cycle.
|
||||
ClkXtalStbCycle1059 = 6u, ///< stable time is 1059(1060) cycle.
|
||||
ClkXtalStbCycle2147 = 7u, ///< stable time is 2147(2148) cycle.
|
||||
ClkXtalStbCycle4291 = 8u, ///< stable time is 4291(4292) cycle.
|
||||
ClkXtalStbCycle8163 = 9u, ///< stable time is 8163(8164) cycle.
|
||||
}en_clk_xtal_stb_cycle_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The handle of xtal stoppage.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_xtal_stp_mode
|
||||
{
|
||||
ClkXtalStpModeInt = 0u, ///< The handle of stoppage is interrupt.
|
||||
ClkXtalStpModeReset = 1u, ///< The handle of stoppage is reset.
|
||||
}en_clk_xtal_stp_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The drive capability of xtal32.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_xtal32_drv
|
||||
{
|
||||
ClkXtal32MidDrv = 0u, ///< Middle drive capability.32.768KHz.
|
||||
ClkXtal32HighDrv = 1u, ///< High drive capability.32.768KHz.
|
||||
}en_clk_xtal32_drv_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The filter mode of xtal32.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_xtal32_filter_mode
|
||||
{
|
||||
ClkXtal32FilterModeFull = 0u, ///< Valid in run,stop,power down mode.
|
||||
ClkXtal32FilterModePart = 2u, ///< Valid in run mode.
|
||||
ClkXtal32FilterModeNone = 3u, ///< Invalid in run,stop,power down mode.
|
||||
}en_clk_xtal32_filter_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The division factor of system clock.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_sysclk_div_factor
|
||||
{
|
||||
ClkSysclkDiv1 = 0u, ///< 1 division.
|
||||
ClkSysclkDiv2 = 1u, ///< 2 division.
|
||||
ClkSysclkDiv4 = 2u, ///< 4 division.
|
||||
ClkSysclkDiv8 = 3u, ///< 8 division.
|
||||
ClkSysclkDiv16 = 4u, ///< 16 division.
|
||||
ClkSysclkDiv32 = 5u, ///< 32 division.
|
||||
ClkSysclkDiv64 = 6u, ///< 64 division.
|
||||
}en_clk_sysclk_div_factor_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The division factor of system clock.It will be used for debug clock.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_tpiuclk_div_factor
|
||||
{
|
||||
ClkTpiuclkDiv1 = 0u, ///< 1 division.
|
||||
ClkTpiuclkDiv2 = 1u, ///< 2 division.
|
||||
ClkTpiuclkDiv4 = 2u, ///< 4 division.
|
||||
}en_clk_tpiuclk_div_factor_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The division factor of clock output.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_output_div_factor
|
||||
{
|
||||
ClkOutputDiv1 = 0u, ///< 1 division.
|
||||
ClkOutputDiv2 = 1u, ///< 2 division.
|
||||
ClkOutputDiv4 = 2u, ///< 4 division.
|
||||
ClkOutputDiv8 = 3u, ///< 8 division.
|
||||
ClkOutputDiv16 = 4u, ///< 16 division.
|
||||
ClkOutputDiv32 = 5u, ///< 32 division.
|
||||
ClkOutputDiv64 = 6u, ///< 64 division.
|
||||
ClkOutputDiv128 = 7u, ///< 128 division.
|
||||
}en_clk_output_div_factor_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The division factor of fcm measure source.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_fcm_measure_div_factor
|
||||
{
|
||||
ClkFcmMeaDiv1 = 0u, ///< 1 division.
|
||||
ClkFcmMeaDiv4 = 1u, ///< 4 division.
|
||||
ClkFcmMeaDiv8 = 2u, ///< 8 division.
|
||||
ClkFcmMeaDiv32 = 3u, ///< 32 division.
|
||||
}en_clk_fcm_measure_div_factor_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The division factor of fcm reference source.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_fcm_intref_div_factor
|
||||
{
|
||||
ClkFcmIntrefDiv32 = 0u, ///< 32 division.
|
||||
ClkFcmIntrefDiv128 = 1u, ///< 128 division.
|
||||
ClkFcmIntrefDiv1024 = 2u, ///< 1024 division.
|
||||
ClkFcmIntrefDiv8192 = 3u, ///< 8192 division.
|
||||
}en_clk_fcm_intref_div_factor_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The edge of the fcm reference source.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_fcm_edge
|
||||
{
|
||||
ClkFcmEdgeRising = 0u, ///< Rising edge.
|
||||
ClkFcmEdgeFalling = 1u, ///< Falling edge.
|
||||
ClkFcmEdgeBoth = 2u, ///< Both edge.
|
||||
}en_clk_fcm_edge_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The filter clock of the fcm reference source.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_fcm_filter_clk
|
||||
{
|
||||
ClkFcmFilterClkNone = 0u, ///< None filter.
|
||||
ClkFcmFilterClkFcmSrc = 1u, ///< Use fcm measurement source as filter clock.
|
||||
ClkFcmFilterClkFcmSrcDiv4 = 2u, ///< Use 1/4 fcm measurement source as filter clock.
|
||||
ClkFcmFilterClkFcmSrcDiv16 = 3u, ///< Use 1/16 fcm measurement source as filter clock.
|
||||
}en_clk_fcm_filter_clk_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The fcm reference source.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_fcm_refer
|
||||
{
|
||||
ClkFcmExtRef = 0u, ///< Use external reference.
|
||||
ClkFcmInterRef = 1u, ///< Use internal reference.
|
||||
}en_clk_fcm_refer_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The handle of fcm abnormal.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_fcm_abnormal_handle
|
||||
{
|
||||
ClkFcmHandleInterrupt = 0u, ///< The handle of fcm abnormal is interrupt.
|
||||
ClkFcmHandleReset = 1u, ///< The handle of fcm abnormal is reset.
|
||||
}en_clk_fcm_abnormal_handle_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The channel of clock output.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clk_output_ch
|
||||
{
|
||||
ClkOutputCh1 = 1u, ///< The output of clk is MCO_1.
|
||||
ClkOutputCh2 = 2u, ///< The output of clk is MCO_2.
|
||||
}en_clk_output_ch_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of XTAL.
|
||||
**
|
||||
** \note Configures the XTAL if needed.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_xtal_cfg
|
||||
{
|
||||
en_functional_state_t enFastStartup; ///< Enable fast start up or not.
|
||||
en_clk_xtal_mode_t enMode; ///< Select xtal mode.
|
||||
en_clk_xtal_drv_t enDrv; ///< Select xtal drive capability.
|
||||
}stc_clk_xtal_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of XTAL stoppage.
|
||||
**
|
||||
** \note Configures the XTAL stoppage if needed.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_xtal_stp_cfg
|
||||
{
|
||||
en_functional_state_t enDetect; ///< Enable detect stoppage or not.
|
||||
en_clk_xtal_stp_mode_t enMode; ///< Select the handle of xtal stoppage.
|
||||
en_functional_state_t enModeReset; ///< Enable reset for handle the xtal stoppage.
|
||||
en_functional_state_t enModeInt; ///< Enable interrupt for handle the xtal stoppage.
|
||||
}stc_clk_xtal_stp_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of XTAL32.
|
||||
**
|
||||
** \note Configures the XTAL32 if needed.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_xtal32_cfg
|
||||
{
|
||||
en_clk_xtal32_drv_t enDrv; ///< Select xtal32 drive capability.
|
||||
en_clk_xtal32_filter_mode_t enFilterMode; ///< The filter mode of xtal32.
|
||||
}stc_clk_xtal32_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of PLL.
|
||||
**
|
||||
** \note Configures the PLL if needed.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_pll_cfg
|
||||
{
|
||||
uint32_t PllpDiv; ///< Pllp clk, division factor of VCO out.
|
||||
uint32_t PllqDiv; ///< Pllq clk, division factor of VCO out.
|
||||
uint32_t PllrDiv; ///< Pllr clk, division factor of VCO out.
|
||||
uint32_t plln; ///< Multiplication factor of vco out, ensure between 240M~480M
|
||||
uint32_t pllmDiv; ///< Division factor of VCO in, ensure between 1M~12M.
|
||||
}stc_clk_mpll_cfg_t, stc_clk_upll_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of system clock.
|
||||
**
|
||||
** \note Configures the system clock if needed.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_sysclk_cfg
|
||||
{
|
||||
en_clk_sysclk_div_factor_t enHclkDiv; ///< Division for hclk.
|
||||
en_clk_sysclk_div_factor_t enExclkDiv; ///< Division for exclk.
|
||||
en_clk_sysclk_div_factor_t enPclk0Div; ///< Division for pclk0.
|
||||
en_clk_sysclk_div_factor_t enPclk1Div; ///< Division for pclk1.
|
||||
en_clk_sysclk_div_factor_t enPclk2Div; ///< Division for pclk2.
|
||||
en_clk_sysclk_div_factor_t enPclk3Div; ///< Division for pclk3.
|
||||
en_clk_sysclk_div_factor_t enPclk4Div; ///< Division for pclk4.
|
||||
}stc_clk_sysclk_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of clock output.
|
||||
**
|
||||
** \note Configures the clock output if needed.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_output_cfg
|
||||
{
|
||||
en_clk_output_source_t enOutputSrc; ///< The clock output source.
|
||||
en_clk_output_div_factor_t enOutputDiv; ///< The division factor of clock output source.
|
||||
}stc_clk_output_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of fcm window.
|
||||
**
|
||||
** \note Configures the fcm window if needed.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_fcm_window_cfg
|
||||
{
|
||||
uint16_t windowLower; ///< The lower value of the window.
|
||||
uint16_t windowUpper; ///< The upper value of the window.
|
||||
}stc_clk_fcm_window_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of fcm measurement.
|
||||
**
|
||||
** \note Configures the fcm measurement if needed.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_fcm_measure_cfg
|
||||
{
|
||||
en_clk_fcm_measure_source_t enSrc; ///< The measurement source.
|
||||
en_clk_fcm_measure_div_factor_t enSrcDiv; ///< The division factor of measurement source.
|
||||
}stc_clk_fcm_measure_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of fcm reference.
|
||||
**
|
||||
** \note Configures the fcm reference if needed.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_fcm_reference_cfg
|
||||
{
|
||||
en_functional_state_t enExtRef; ///< Enable external reference or not.
|
||||
en_clk_fcm_edge_t enEdge; ///< The edge of internal reference.
|
||||
en_clk_fcm_filter_clk_t enFilterClk; ///< The filter clock of internal reference.
|
||||
en_clk_fcm_refer_t enRefSel; ///< Select reference.
|
||||
en_clk_fcm_intref_source_t enIntRefSrc; ///< Select internal reference.
|
||||
en_clk_fcm_intref_div_factor_t enIntRefDiv; ///< The division factor of internal reference.
|
||||
}stc_clk_fcm_reference_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of fcm interrupt.
|
||||
**
|
||||
** \note Configures the fcm interrupt if needed.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_fcm_interrupt_cfg
|
||||
{
|
||||
en_clk_fcm_abnormal_handle_t enHandleSel; ///< Use interrupt or reset.
|
||||
en_functional_state_t enHandleReset; ///< Enable reset or not.
|
||||
en_functional_state_t enHandleInterrupt; ///< Enable interrupt or not.
|
||||
en_functional_state_t enOvfInterrupt; ///< Enable overflow interrupt or not.
|
||||
en_functional_state_t enEndInterrupt; ///< Enable measurement end interrupt or not.
|
||||
}stc_clk_fcm_interrupt_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configuration structure of fcm.
|
||||
**
|
||||
** \note Configures the fcm if needed.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_fcm_cfg
|
||||
{
|
||||
stc_clk_fcm_window_cfg_t *pstcFcmWindowCfg; ///< Window configuration struct.
|
||||
stc_clk_fcm_measure_cfg_t *pstcFcmMeaCfg; ///< Measurement configuration struct.
|
||||
stc_clk_fcm_reference_cfg_t *pstcFcmRefCfg; ///< Reference configuration struct.
|
||||
stc_clk_fcm_interrupt_cfg_t *pstcFcmIntCfg; ///< Interrupt configuration struct.
|
||||
}stc_clk_fcm_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clock frequency structure.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clk_freq
|
||||
{
|
||||
uint32_t sysclkFreq; ///< System clock frequency.
|
||||
uint32_t hclkFreq; ///< Hclk frequency.
|
||||
uint32_t exckFreq; ///< Exclk frequency.
|
||||
uint32_t pclk0Freq; ///< Pclk0 frequency.
|
||||
uint32_t pclk1Freq; ///< Pclk1 frequency.
|
||||
uint32_t pclk2Freq; ///< Pclk2 frequency.
|
||||
uint32_t pclk3Freq; ///< Pclk3 frequency.
|
||||
uint32_t pclk4Freq; ///< Pclk4 frequency.
|
||||
}stc_clk_freq_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief PLL Clock frequency structure.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_pll_clk_freq
|
||||
{
|
||||
uint32_t mpllp; ///< mpllp clock frequency.
|
||||
uint32_t mpllq; ///< mpllq clock frequency.
|
||||
uint32_t mpllr; ///< mpllr clock frequency.
|
||||
uint32_t upllp; ///< upllp clock frequency.
|
||||
uint32_t upllq; ///< upllq clock frequency.
|
||||
uint32_t upllr; ///< upllr clock frequency.
|
||||
}stc_pll_clk_freq_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void CLK_XtalConfig(const stc_clk_xtal_cfg_t *pstcXtalCfg);
|
||||
void CLK_XtalStbConfig(const en_clk_xtal_stb_cycle_t enXtalStb);
|
||||
void CLK_XtalStpConfig(const stc_clk_xtal_stp_cfg_t *pstcXtalStpCfg);
|
||||
en_result_t CLK_XtalCmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_Xtal32Config(const stc_clk_xtal32_cfg_t *pstcXtal32Cfg);
|
||||
en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_HrcTrim(int8_t trimValue);
|
||||
en_result_t CLK_HrcCmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_MrcTrim(int8_t trimValue);
|
||||
en_result_t CLK_MrcCmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_LrcTrim(int8_t trimValue);
|
||||
en_result_t CLK_LrcCmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_SetPllSource(en_clk_pll_source_t enPllSrc);
|
||||
void CLK_MpllConfig(const stc_clk_mpll_cfg_t *pstcMpllCfg);
|
||||
en_result_t CLK_MpllCmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_UpllConfig(const stc_clk_upll_cfg_t *pstcUpllCfg);
|
||||
en_result_t CLK_UpllCmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_SetSysClkSource(en_clk_sys_source_t enTargetSysSrc);
|
||||
en_clk_sys_source_t CLK_GetSysClkSource(void);
|
||||
|
||||
void CLK_SysClkConfig(const stc_clk_sysclk_cfg_t *pstcSysclkCfg);
|
||||
void CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq);
|
||||
void CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq);
|
||||
|
||||
void CLK_SetUsbClkSource(en_clk_usb_source_t enTargetUsbSrc);
|
||||
void CLK_SetPeriClkSource(en_clk_peri_source_t enTargetPeriSrc);
|
||||
void CLK_SetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg, en_clk_peri_source_t enTargetPeriSrc);
|
||||
en_clk_peri_source_t CLK_GetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg);
|
||||
|
||||
void CLK_TpiuClkConfig(const en_clk_tpiuclk_div_factor_t enTpiuDiv);
|
||||
void CLK_TpiuClkCmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_OutputClkConfig(en_clk_output_ch_t enCh, const stc_clk_output_cfg_t *pstcOutputCfg);
|
||||
void CLK_OutputClkCmd(en_clk_output_ch_t enCh, en_functional_state_t enNewState);
|
||||
en_flag_status_t CLK_GetFlagStatus(en_clk_flag_t enClkFlag);
|
||||
|
||||
void CLK_FcmConfig(const stc_clk_fcm_cfg_t *pstcClkFcmCfg);
|
||||
void CLK_FcmCmd(en_functional_state_t enNewState);
|
||||
|
||||
uint16_t CLK_GetFcmCounter(void);
|
||||
en_flag_status_t CLK_GetFcmFlag(en_clk_fcm_flag_t enFcmFlag);
|
||||
void CLK_ClearFcmFlag(en_clk_fcm_flag_t enFcmFlag);
|
||||
|
||||
void CLK_ClearXtalStdFlag(void);
|
||||
|
||||
//@} // CmuGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_CLK_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_CLK_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,279 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_cmp.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link CmpGroup CMP @endlink
|
||||
**
|
||||
** - 2018-10-22 CDT First version for Device Driver Library of CMP.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_CMP_H__
|
||||
#define __HC32F460_CMP_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_CMP_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup CmpGroup Comparator(CMP)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP function enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_func
|
||||
{
|
||||
CmpVcoutOutput = (1u << 12), ///< CMP vcout output enable function
|
||||
CmpOutpuInv = (1u << 13), ///< CMP output invert enable function
|
||||
CmpOutput = (1u << 14), ///< CMP output enable function
|
||||
} en_cmp_func_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP edge selection enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_edge_sel
|
||||
{
|
||||
CmpNoneEdge = 0u, ///< None edge detection
|
||||
CmpRisingEdge = 1u, ///< Rising edge detection
|
||||
CmpFaillingEdge = 2u, ///< Falling edge detection
|
||||
CmpBothEdge = 3u, ///< Falling or Rising edge detection
|
||||
} en_cmp_edge_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP filter sample clock division enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_fltclk_div
|
||||
{
|
||||
CmpNoneFlt = 0u, ///< Unuse filter
|
||||
CmpFltPclk3Div1 = 1u, ///< PCLK3/1
|
||||
CmpFltPclk3Div2 = 2u, ///< PCLK3/2
|
||||
CmpFltPclk3Div4 = 3u, ///< PCLK3/4
|
||||
CmpFltPclk3Div8 = 4u, ///< PCLK3/8
|
||||
CmpFltPclk3Div16 = 5u, ///< PCLK3/16
|
||||
CmpFltPclk3Div32 = 6u, ///< PCLK3/32
|
||||
CmpFltPclk3Div64 = 7u, ///< PCLK3/64
|
||||
} en_cmp_fltclk_div_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP INP4 input enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_inp4_sel
|
||||
{
|
||||
CmpInp4None = 0u, ///< None input
|
||||
CmpInp4PGAO = 1u, ///< PGAO output
|
||||
CmpInp4PGAO_BP = 2u, ///< PGAO_BP output
|
||||
CmpInp4CMP1_INP4 = 4u, ///< CMP1_INP4
|
||||
} en_cmp_inp4_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP INP input enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_inp_sel
|
||||
{
|
||||
CmpInpNone = 0u, ///< None input
|
||||
CmpInp1 = 1u, ///< INP1 input
|
||||
CmpInp2 = 2u, ///< INP2 input
|
||||
CmpInp1_Inp2 = 3u, ///< INP1 INP2 input
|
||||
CmpInp3 = 4u, ///< INP3 input
|
||||
CmpInp1_Inp3 = 5u, ///< INP1 INP3 input
|
||||
CmpInp2_Inp3 = 6u, ///< INP2 INP3 input
|
||||
CmpInp1_Inp2_Inp3 = 7u, ///< INP1 INP2 INP3 input
|
||||
CmpInp4 = 8u, ///< INP4 input
|
||||
CmpInp1_Inp4 = 9u, ///< INP1 INP4 input
|
||||
CmpInp2_Inp4 = 10u, ///< INP2 INP4 input
|
||||
CmpInp1_Inp2_Inp4 = 11u, ///< INP1 INP2 INP4 input
|
||||
CmpInp3_Inp4 = 12u, ///< INP3 INP4 input
|
||||
CmpInp1_Inp3_Inp4 = 13u, ///< INP1 INP3 INP4 input
|
||||
CmpInp2_Inp3_Inp4 = 14u, ///< INP2 INP3 INP4 input
|
||||
CmpInp1_Inp2_Inp3_Inp4 = 15u, ///< INP1 INP2 INP3 INP4 input
|
||||
} en_cmp_inp_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP INM input enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_inm_sel
|
||||
{
|
||||
CmpInmNone = 0u, ///< None input
|
||||
CmpInm1 = 1u, ///< INM1 input
|
||||
CmpInm2 = 2u, ///< INM2 input
|
||||
CmpInm3 = 4u, ///< INM3 input
|
||||
CmpInm4 = 8u, ///< INM4 input
|
||||
} en_cmp_inm_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP INP State enumeration (read only)
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_inp_state
|
||||
{
|
||||
CmpInpNoneState = 0u, ///< none input state
|
||||
CmpInp1State = 1u, ///< INP1 input state
|
||||
CmpInp2State = 2u, ///< INP2 input state
|
||||
CmpInp3State = 4u, ///< INP3 input state
|
||||
CmpInp4State = 8u, ///< INP4 input state
|
||||
} en_cmp_inp_state_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP Output State enumeration (read only)
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_output_state
|
||||
{
|
||||
CmpOutputLow = 0u, ///< Compare output Low "0"
|
||||
CmpOutputHigh = 1u, ///< Compare output High "1"
|
||||
} en_cmp_output_state_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP input selection
|
||||
******************************************************************************/
|
||||
typedef struct stc_cmp_input_sel
|
||||
{
|
||||
en_cmp_inm_sel_t enInmSel; ///< CMP INM sel
|
||||
|
||||
en_cmp_inp_sel_t enInpSel; ///< CMP INP sel
|
||||
|
||||
en_cmp_inp4_sel_t enInp4Sel; ///< CMP INP4 sel
|
||||
} stc_cmp_input_sel_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief DAC channel
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_dac_ch
|
||||
{
|
||||
CmpDac1 = 0u, ///< DAC1
|
||||
CmpDac2 = 1u, ///< DAC2
|
||||
} en_cmp_dac_ch_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief ADC internal reference voltage path
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_adc_int_ref_volt_path
|
||||
{
|
||||
CmpAdcRefVoltPathDac1 = (1u << 0u), ///< ADC internal reference voltage path: DAC1
|
||||
CmpAdcRefVoltPathDac2 = (1u << 1u), ///< ADC internal reference voltage path: DAC2
|
||||
CmpAdcRefVoltPathVref = (1u << 4u), ///< ADC internal reference voltage path: VREF
|
||||
} en_cmp_adc_int_ref_volt_path_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP initialization structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_cmp_init
|
||||
{
|
||||
en_cmp_edge_sel_t enEdgeSel; ///< CMP edge sel
|
||||
|
||||
en_cmp_fltclk_div_t enFltClkDiv; ///< CMP FLTclock division
|
||||
|
||||
en_functional_state_t enCmpOutputEn; ///< CMP Output enable
|
||||
|
||||
en_functional_state_t enCmpVcoutOutputEn; ///< CMP output result enable
|
||||
|
||||
en_functional_state_t enCmpInvEn; ///< CMP INV sel for output
|
||||
|
||||
en_functional_state_t enCmpIntEN; ///< CMP interrupt enable
|
||||
} stc_cmp_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP DAC initialization structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_cmp_dac_init
|
||||
{
|
||||
uint8_t u8DacData; ///< CMP DAC Data register value
|
||||
|
||||
en_functional_state_t enCmpDacEN; ///< CMP DAC enable
|
||||
} stc_cmp_dac_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t CMP_Init(M4_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcInitCfg);
|
||||
en_result_t CMP_DeInit(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_Cmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd);
|
||||
en_result_t CMP_IrqCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd);
|
||||
en_result_t CMP_SetScanTime(M4_CMP_TypeDef *CMPx,
|
||||
uint8_t u8ScanStable,
|
||||
uint8_t u8ScanPeriod);
|
||||
en_result_t CMP_FuncCmd(M4_CMP_TypeDef *CMPx,
|
||||
en_cmp_func_t enFunc,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t CMP_StartScan(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_StopScan(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_SetFilterClkDiv(M4_CMP_TypeDef *CMPx,
|
||||
en_cmp_fltclk_div_t enFltClkDiv);
|
||||
en_cmp_fltclk_div_t CMP_GetFilterClkDiv(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_SetEdgeSel(M4_CMP_TypeDef *CMPx,
|
||||
en_cmp_edge_sel_t enEdgeSel);
|
||||
en_cmp_edge_sel_t CMP_GetEdgeSel(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_InputSel(M4_CMP_TypeDef *CMPx,
|
||||
const stc_cmp_input_sel_t *pstcInputSel);
|
||||
en_result_t CMP_SetInp(M4_CMP_TypeDef *CMPx, en_cmp_inp_sel_t enInputSel);
|
||||
en_cmp_inp_sel_t CMP_GetInp(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_SetInm(M4_CMP_TypeDef *CMPx, en_cmp_inm_sel_t enInputSel);
|
||||
en_cmp_inm_sel_t CMP_GetInm(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_SetInp4(M4_CMP_TypeDef *CMPx,en_cmp_inp4_sel_t enInputSel);
|
||||
en_cmp_inp4_sel_t CMP_GetInp4(M4_CMP_TypeDef *CMPx);
|
||||
en_cmp_output_state_t CMP_GetOutputState(M4_CMP_TypeDef *CMPx);
|
||||
en_cmp_inp_state_t CMP_GetInpState(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_DAC_Init(en_cmp_dac_ch_t enCh,
|
||||
const stc_cmp_dac_init_t *pstcInitCfg);
|
||||
en_result_t CMP_DAC_DeInit(en_cmp_dac_ch_t enCh);
|
||||
en_result_t CMP_DAC_Cmd(en_cmp_dac_ch_t enCh, en_functional_state_t enCmd);
|
||||
en_result_t CMP_DAC_SetData(en_cmp_dac_ch_t enCh, uint8_t u8DacData);
|
||||
uint8_t CMP_DAC_GetData(en_cmp_dac_ch_t enCh);
|
||||
en_result_t CMP_ADC_SetRefVoltPath(en_cmp_adc_int_ref_volt_path_t enRefVoltPath);
|
||||
|
||||
//@} // CmpGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_CMP_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_CMP_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,118 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_crc.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link CrcGroup Crc description @endlink
|
||||
**
|
||||
** - 2019-03-07 CDT First version for Device Driver Library of Crc.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_CRC_H__
|
||||
#define __HC32F460_CRC_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_CRC_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup CrcGroup Cyclic Redundancy Check(CRC)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/* Bits definitions of CRC control register(CRC_CR). */
|
||||
/*
|
||||
* Definitions of CRC protocol.
|
||||
* NOTE: CRC16 polynomial is X16 + X12 + X5 + 1
|
||||
* CRC32 polynomial is X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + \
|
||||
* X8 + X7 + X5 + X4 + X2 + X + 1
|
||||
*/
|
||||
#define CRC_SEL_16B ((uint32_t)0x0)
|
||||
#define CRC_SEL_32B ((uint32_t)(0x1ul << 1u))
|
||||
|
||||
/*
|
||||
* Identifies the transpose configuration of the source data.
|
||||
* If this function is enabled, the source data's bits in bytes are transposed.
|
||||
* e.g. There's a source data 0x1234 which will be calculated checksum and this
|
||||
* function is enabled, the final data be calculated is 0x482C.
|
||||
* 0x12: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x48.
|
||||
* 0x48: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x2C.
|
||||
* The same to 32 bit data while using CRC32.
|
||||
*/
|
||||
#define CRC_REFIN_DISABLE ((uint32_t)0x0)
|
||||
#define CRC_REFIN_ENABLE ((uint32_t)(0x1ul << 2u))
|
||||
|
||||
/*
|
||||
* Identifies the transpose configuration of the checksum.
|
||||
* If this function is enabled, bits of the checksum will be transposed.
|
||||
* e.g. There is a CRC16 checksum is 0x5678 before this function enabled, then
|
||||
* this function is enabled, the checksum will be 0x1E6A.
|
||||
* 0x5678: bit0->bit15, bit1->bit14, ..., bit15->bit0, the final data is 0x1E6A.
|
||||
* The same to CRC32 checksum while using CRC32.
|
||||
*/
|
||||
#define CRC_REFOUT_DISABLE ((uint32_t)0x0)
|
||||
#define CRC_REFOUT_ENABLE ((uint32_t)(0x1ul << 3u))
|
||||
|
||||
/*
|
||||
* XORs the CRC checksum with 0xFFFF(CRC16) or 0xFFFFFFFF(CRC32).
|
||||
* e.g. There is a CRC16 checksum is 0x5678 before this function enabled.
|
||||
* If this function enabled, the checksum will be 0xA987.
|
||||
* The same to CRC32 checksum while using CRC32.
|
||||
*/
|
||||
#define CRC_XOROUT_DISABLE ((uint32_t)0x0)
|
||||
#define CRC_XOROUT_ENABLE ((uint32_t)(0x1ul << 4u))
|
||||
|
||||
#define CRC_CONFIG_MASK ((uint32_t)(0x1Eu))
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void CRC_Init(uint32_t u32Config);
|
||||
uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length);
|
||||
uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length);
|
||||
bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16CheckSum, const uint16_t *pu16Data, uint32_t u32Length);
|
||||
bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32CheckSum, const uint32_t *pu32Data, uint32_t u32Length);
|
||||
|
||||
//@} // CrcGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_CRC_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_CRC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,216 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_dcu.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link DcuGroup DCU description @endlink
|
||||
**
|
||||
** - 2018-10-15 CDT First version for Device Driver Library of DCU.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_DCU_H__
|
||||
#define __HC32F460_DCU_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_DCU_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup DcuGroup Data Computing Unit(DCU)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU register data enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_data_register
|
||||
{
|
||||
DcuRegisterData0 = 0u, ///< DCU DATA0
|
||||
DcuRegisterData1 = 1u, ///< DCU DATA1
|
||||
DcuRegisterData2 = 2u, ///< DCU DATA2
|
||||
} en_dcu_data_register_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU operation enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_operation_mode
|
||||
{
|
||||
DcuInvalid = 0u, ///< DCU Invalid
|
||||
DcuOpAdd = 1u, ///< DCU operation: Add
|
||||
DcuOpSub = 2u, ///< DCU operation: Sub
|
||||
DcuHwTrigOpAdd = 3u, ///< DCU operation: Hardware trigger Add
|
||||
DcuHwTrigOpSub = 4u, ///< DCU operation: Hardware trigger Sub
|
||||
DcuOpCompare = 5u, ///< DCU operation: Compare
|
||||
} en_dcu_operation_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU data size enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_data_size
|
||||
{
|
||||
DcuDataBit8 = 0u, ///< DCU data size: 8 bit
|
||||
DcuDataBit16 = 1u, ///< DCU data size: 16 bit
|
||||
DcuDataBit32 = 2u, ///< DCU data size: 32 bit
|
||||
} en_dcu_data_size_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU compare operation trigger mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_cmp_trigger_mode
|
||||
{
|
||||
DcuCmpTrigbyData0 = 0u, ///< DCU compare triggered by DATA0
|
||||
DcuCmpTrigbyData012 = 1u, ///< DCU compare triggered by DATA0 or DATA1 or DATA2
|
||||
} en_dcu_cmp_trigger_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU interrupt selection enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_int_sel
|
||||
{
|
||||
DcuIntOp = (1ul << 0), ///< DCU overflow or underflow interrupt
|
||||
DcuIntLs2 = (1ul << 1), ///< DCU DATA0 < DATA2 interrupt
|
||||
DcuIntEq2 = (1ul << 2), ///< DCU DATA0 = DATA2 interrupt
|
||||
DcuIntGt2 = (1ul << 3), ///< DCU DATA0 > DATA2 interrupt
|
||||
DcuIntLs1 = (1ul << 4), ///< DCU DATA0 < DATA1 interrupt
|
||||
DcuIntEq1 = (1ul << 5), ///< DCU DATA0 = DATA1 interrupt
|
||||
DcuIntGt1 = (1ul << 6), ///< DCU DATA0 > DATA1 interrupt
|
||||
} en_dcu_int_sel_t, en_dcu_flag_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU window interrupt mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_int_win_mode
|
||||
{
|
||||
DcuIntInvalid = 0u, ///< DCU don't occur interrupt
|
||||
DcuWinIntInvalid = 1u, ///< DCU window interrupt is invalid.
|
||||
DcuInsideWinCmpInt = 2u, ///< DCU occur interrupt when DATA2 ¡Ü DATA0 ¡Ü DATA2
|
||||
DcuOutsideWinCmpInt = 3u, ///< DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2
|
||||
} en_dcu_int_win_mode_t;
|
||||
|
||||
/* DCU common trigger source select */
|
||||
typedef enum en_dcu_com_trigger
|
||||
{
|
||||
DcuComTrigger_1 = 1u, ///< Select common trigger 1.
|
||||
DcuComTrigger_2 = 2u, ///< Select common trigger 2.
|
||||
DcuComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2.
|
||||
} en_dcu_com_trigger_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dcu_init
|
||||
{
|
||||
uint32_t u32IntSel; ///< Specifies interrupt selection and This parameter can be a value of @ref en_dcu_int_sel_t
|
||||
|
||||
en_functional_state_t enIntCmd; ///< Select DCU interrupt function. Enable:Enable DCU interrupt function; Disable:Disable DCU interrupt function
|
||||
|
||||
en_dcu_int_win_mode_t enIntWinMode; ///< Specifies interrupt window mode and This parameter can be a value of @ref en_dcu_int_win_mode_t
|
||||
|
||||
en_dcu_data_size_t enDataSize; ///< Specifies DCU data size and This parameter can be a value of @ref en_dcu_data_size_t
|
||||
|
||||
en_dcu_operation_mode_t enOperation; ///< Specifies DCU operation and This parameter can be a value of @ref en_dcu_operation_mode_t
|
||||
|
||||
en_dcu_cmp_trigger_mode_t enCmpTriggerMode; ///< Specifies DCU compare operation trigger mode size and This parameter can be a value of @ref en_dcu_cmp_trigger_mode_t
|
||||
|
||||
} stc_dcu_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg);
|
||||
en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_operation_mode_t enMode);
|
||||
en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize);
|
||||
en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_int_win_mode_t enIntWinMode);
|
||||
en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_cmp_trigger_mode_t enTriggerMode);
|
||||
en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_EnableInterrupt(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_DisableInterrupt(M4_DCU_TypeDef *DCUx);
|
||||
en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag);
|
||||
en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag);
|
||||
en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_int_sel_t enIntSel,
|
||||
en_functional_state_t enCmd);
|
||||
uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg);
|
||||
en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg, uint8_t u8Data);
|
||||
uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg);
|
||||
en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg,
|
||||
uint16_t u16Data);
|
||||
uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg);
|
||||
en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg,
|
||||
uint32_t u32Data);
|
||||
en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx,
|
||||
en_event_src_t enTriggerSrc);
|
||||
void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_com_trigger_t enComTrigger,
|
||||
en_functional_state_t enState);
|
||||
|
||||
//@} // DcuGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_DCU_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_DCU_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,363 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_dmac.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link DmacGroup DMAC description @endlink
|
||||
**
|
||||
** - 2018-11-18 CDT First version for Device Driver Library of DMAC.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_DMAC_H__
|
||||
#define __HC32F460_DMAC_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_DMAC_ENABLE == DDL_ON)
|
||||
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup DmacGroup Direct Memory Access Control(DMAC)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA Channel
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_channel
|
||||
{
|
||||
DmaCh0 = 0u, ///< DMA channel 0
|
||||
DmaCh1 = 1u, ///< DMA channel 1
|
||||
DmaCh2 = 2u, ///< DMA channel 2
|
||||
DmaCh3 = 3u, ///< DMA channel 3
|
||||
DmaChMax = 4u ///< DMA channel max
|
||||
}en_dma_channel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA transfer data width
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_transfer_width
|
||||
{
|
||||
Dma8Bit = 0u, ///< 8 bit transfer via DMA
|
||||
Dma16Bit = 1u, ///< 16 bit transfer via DMA
|
||||
Dma32Bit = 2u ///< 32 bit transfer via DMA
|
||||
}en_dma_transfer_width_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA flag
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_flag
|
||||
{
|
||||
DmaTransferComplete = 0u, ///< DMA transfer complete
|
||||
DmaBlockComplete = 1u, ///< DMA block transfer complete
|
||||
DmaTransferErr = 2u, ///< DMA transfer error
|
||||
DmaReqErr = 3u, ///< DMA transfer request error
|
||||
DmaFlagMax = 4u
|
||||
}en_dma_flag_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA address mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_address_mode
|
||||
{
|
||||
AddressFix = 0u, ///< Address fixed
|
||||
AddressIncrease = 1u, ///< Address increased
|
||||
AddressDecrease = 2u, ///< Address decreased
|
||||
}en_dma_address_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA link list pointer mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_llp_mode
|
||||
{
|
||||
LlpWaitNextReq = 0u, ///< DMA trigger transfer after wait next request
|
||||
LlpRunNow = 1u, ///< DMA trigger transfer now
|
||||
}en_dma_llp_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA interrupt selection
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_irq_sel
|
||||
{
|
||||
TrnErrIrq = 0u, ///< Select DMA transfer error interrupt
|
||||
TrnReqErrIrq = 1u, ///< Select DMA transfer req over error interrupt
|
||||
TrnCpltIrq = 2u, ///< Select DMA transfer completion interrupt
|
||||
BlkTrnCpltIrq = 3u, ///< Select DMA block completion interrupt
|
||||
DmaIrqSelMax = 4u
|
||||
}en_dma_irq_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA re_config count mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_recfg_cnt_mode
|
||||
{
|
||||
CntFix = 0u, ///< Fix
|
||||
CntSrcAddr = 1u, ///< Source address mode
|
||||
CntDesAddr = 2u, ///< Destination address mode
|
||||
}en_dma_recfg_cnt_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA re_config destination address mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_recfg_daddr_mode
|
||||
{
|
||||
DaddrFix = 0u, ///< Fix
|
||||
DaddrNseq = 1u, ///< No_sequence address
|
||||
DaddrRep = 2u, ///< Repeat address
|
||||
}en_dma_recfg_daddr_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA re_config source address mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_recfg_saddr_mode
|
||||
{
|
||||
SaddrFix = 0u, ///< Fix
|
||||
SaddrNseq = 1u, ///< No_sequence address
|
||||
SaddrRep = 2u, ///< Repeat address
|
||||
}en_dma_recfg_saddr_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA channel status
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_ch_flag
|
||||
{
|
||||
DmaSta = 0u, ///< DMA status.
|
||||
ReCfgSta = 1u, ///< DMA re_configuration status.
|
||||
DmaCh0Sta = 2u, ///< DMA channel 0 status.
|
||||
DmaCh1Sta = 3u, ///< DMA channel 1 status.
|
||||
DmaCh2Sta = 4u, ///< DMA channel 2 status.
|
||||
DmaCh3Sta = 5u, ///< DMA channel 3 status.
|
||||
}en_dma_ch_flag_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA common trigger source select
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_com_trigger
|
||||
{
|
||||
DmaComTrigger_1 = 0x1, ///< Select common trigger 1.
|
||||
DmaComTrigger_2 = 0x2, ///< Select common trigger 2.
|
||||
DmaComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2.
|
||||
} en_dma_com_trigger_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA llp descriptor
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_llp_descriptor
|
||||
{
|
||||
uint32_t SARx; ///< DMA source address register
|
||||
uint32_t DARx; ///< DMA destination address register
|
||||
union
|
||||
{
|
||||
uint32_t DTCTLx;
|
||||
stc_dma_dtctl_field_t DTCTLx_f; ///< DMA data control register
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t RPTx;
|
||||
stc_dma_rpt_field_t RPTx_f; ///< DMA repeat control register
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t SNSEQCTLx;
|
||||
stc_dma_snseqctl_field_t SNSEQCTLx_f; ///< DMA source no-sequence control register
|
||||
};
|
||||
union
|
||||
{
|
||||
__IO uint32_t DNSEQCTLx;
|
||||
stc_dma_dnseqctl_field_t DNSEQCTLx_f; ///< DMA destination no-sequence control register
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t LLPx;
|
||||
stc_dma_llp_field_t LLPx_f; ///< DMA link-list-pointer register
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t CHxCTL;
|
||||
stc_dma_ch0ctl_field_t CHxCTL_f; ///< DMA channel control register
|
||||
};
|
||||
}stc_dma_llp_descriptor_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA no-sequence function configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_nseq_cfg
|
||||
{
|
||||
uint32_t u32Offset; ///< DMA no-sequence offset.
|
||||
uint16_t u16Cnt; ///< DMA no-sequence count.
|
||||
}stc_dma_nseq_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA no-sequence function configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_nseqb_cfg
|
||||
{
|
||||
uint32_t u32NseqDist; ///< DMA no-sequence district interval.
|
||||
uint16_t u16CntB; ///< DMA no-sequence count.
|
||||
}stc_dma_nseqb_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA re_config configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_recfg_ctl
|
||||
{
|
||||
uint16_t u16SrcRptBSize; ///< The source repeat size.
|
||||
uint16_t u16DesRptBSize; ///< The destination repeat size.
|
||||
en_dma_recfg_saddr_mode_t enSaddrMd; ///< DMA re_config source address mode.
|
||||
en_dma_recfg_daddr_mode_t enDaddrMd; ///< DMA re_config destination address mode.
|
||||
en_dma_recfg_cnt_mode_t enCntMd; ///< DMA re_config count mode.
|
||||
stc_dma_nseq_cfg_t stcSrcNseqBCfg; ///< The source no_sequence re_config.
|
||||
stc_dma_nseq_cfg_t stcDesNseqBCfg; ///< The destination no_sequence re_config.
|
||||
}stc_dma_recfg_ctl_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA channel configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_ch_cfg
|
||||
{
|
||||
en_dma_address_mode_t enSrcInc; ///< DMA source address update mode.
|
||||
en_dma_address_mode_t enDesInc; ///< DMA destination address update mode.
|
||||
en_functional_state_t enSrcRptEn; ///< Enable source repeat function or not.
|
||||
en_functional_state_t enDesRptEn; ///< Enable destination repeat function or not.
|
||||
en_functional_state_t enSrcNseqEn; ///< Enable source no_sequence function or not.
|
||||
en_functional_state_t enDesNseqEn; ///< Enable destination no_sequence function or not.
|
||||
en_dma_transfer_width_t enTrnWidth; ///< DMA transfer data width.
|
||||
en_functional_state_t enLlpEn; ///< Enable linked list pointer function or not.
|
||||
en_dma_llp_mode_t enLlpMd; ///< Dma linked list pointer mode.
|
||||
en_functional_state_t enIntEn; ///< Enable interrupt function or not.
|
||||
}stc_dma_ch_cfg_t;
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_config
|
||||
{
|
||||
uint16_t u16BlockSize; ///< Transfer block size = 1024, when 0 is set.
|
||||
uint16_t u16TransferCnt; ///< Transfer counter.
|
||||
uint32_t u32SrcAddr; ///< The source address.
|
||||
uint32_t u32DesAddr; ///< The destination address.
|
||||
uint16_t u16SrcRptSize; ///< The source repeat size.
|
||||
uint16_t u16DesRptSize; ///< The destination repeat size.
|
||||
uint32_t u32DmaLlp; ///< The Dma linked list pointer address
|
||||
stc_dma_nseq_cfg_t stcSrcNseqCfg; ///< The source no_sequence configuration.
|
||||
stc_dma_nseq_cfg_t stcDesNseqCfg; ///< The destination no_sequence configuration.
|
||||
stc_dma_ch_cfg_t stcDmaChCfg; ///< The Dma channel configuration.
|
||||
}stc_dma_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState);
|
||||
en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
|
||||
en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
|
||||
en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
|
||||
en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
|
||||
en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_recfg_ctl_t* pstcDmaReCfg);
|
||||
void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg,en_functional_state_t enNewState);
|
||||
en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag);
|
||||
|
||||
en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address);
|
||||
en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address);
|
||||
en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize);
|
||||
en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt);
|
||||
en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
|
||||
en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
|
||||
en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
|
||||
en_result_t DMA_SetDesRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
|
||||
en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstcSrcNseqCfg);
|
||||
en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg);
|
||||
en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstDesNseqCfg);
|
||||
en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstDesNseqBCfg);
|
||||
en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer);
|
||||
|
||||
void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc);
|
||||
void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc);
|
||||
void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState);
|
||||
void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState);
|
||||
|
||||
void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_ch_cfg_t* pstcChCfg);
|
||||
void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_config_t* pstcDmaCfg);
|
||||
void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch);
|
||||
|
||||
|
||||
|
||||
//@} // DmacGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_DMAC_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_DMAC_H__*/
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,209 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_efm.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link EfmGroup EFM description @endlink
|
||||
**
|
||||
** - 2018-10-29 CDT First version for Device Driver Library of EFM.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_EFM_H__
|
||||
#define __HC32F460_EFM_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_EFM_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup EfmGroup Embedded Flash Management unit(EFM)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The flash status.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_efm_flash_status
|
||||
{
|
||||
FlashReady = 1u, ///< The flash ready flag.
|
||||
FlashRWErr = 2u, ///< The flash read/write error flag.
|
||||
FlashEOP = 3u, ///< The flash end of operation flag.
|
||||
FlashPgMissMatch = 4u, ///< The flash program miss match flag.
|
||||
FlashPgSizeErr = 5u, ///< The flash program size error flag.
|
||||
FlashPgareaPErr = 6u, ///< The flash program protect area error flag.
|
||||
FlashWRPErr = 7u, ///< The flash write protect error flag.
|
||||
}en_efm_flash_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The flash read mode.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_efm_read_md
|
||||
{
|
||||
NormalRead = 0u, ///< The flash normal read mode.
|
||||
UltraPowerRead = 1u, ///< The flash ultra power read mode.
|
||||
}en_efm_read_md_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The flash interrupt select.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_efm_int_sel
|
||||
{
|
||||
PgmErsErrInt = 0u, ///< The flash program / erase error interrupt.
|
||||
EndPgmInt = 1u, ///< The flash end of program interrupt.
|
||||
ColErrInt = 2u, ///< The flash read collided error interrupt.
|
||||
}en_efm_int_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The bus state while flash program & erase.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_efm_bus_sta
|
||||
{
|
||||
BusBusy = 0u, ///< The bus busy while flash program & erase.
|
||||
BusRelease = 1u, ///< The bus release while flash program & erase.
|
||||
}en_efm_bus_sta_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Structure of windows protect address.
|
||||
**
|
||||
** \note None.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_efm_win_protect_addr
|
||||
{
|
||||
uint32_t StartAddr; ///< The protect start address.
|
||||
uint32_t EndAddr; ///< The protect end address.
|
||||
}stc_efm_win_protect_addr_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Structure of unique ID.
|
||||
**
|
||||
** \note None.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_efm_unique_id
|
||||
{
|
||||
uint32_t uniqueID1; ///< unique ID 1.
|
||||
uint32_t uniqueID2; ///< unique ID 2.
|
||||
uint32_t uniqueID3; ///< unique ID 3.
|
||||
}stc_efm_unique_id_t;
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Flach latency cycle (0~15) */
|
||||
#define EFM_LATENCY_0 (0ul)
|
||||
#define EFM_LATENCY_1 (1ul)
|
||||
#define EFM_LATENCY_2 (2ul)
|
||||
#define EFM_LATENCY_3 (3ul)
|
||||
#define EFM_LATENCY_4 (4ul)
|
||||
#define EFM_LATENCY_5 (5ul)
|
||||
#define EFM_LATENCY_6 (6ul)
|
||||
#define EFM_LATENCY_7 (7ul)
|
||||
#define EFM_LATENCY_8 (8ul)
|
||||
#define EFM_LATENCY_9 (9ul)
|
||||
#define EFM_LATENCY_10 (10ul)
|
||||
#define EFM_LATENCY_11 (11ul)
|
||||
#define EFM_LATENCY_12 (12ul)
|
||||
#define EFM_LATENCY_13 (13ul)
|
||||
#define EFM_LATENCY_14 (14ul)
|
||||
#define EFM_LATENCY_15 (15ul)
|
||||
|
||||
/* Flash flag */
|
||||
#define EFM_FLAG_WRPERR (0x00000001ul)
|
||||
#define EFM_FLAG_PEPRTERR (0x00000002ul)
|
||||
#define EFM_FLAG_PGSZERR (0x00000004ul)
|
||||
#define EFM_FLAG_PGMISMTCH (0x00000008ul)
|
||||
#define EFM_FLAG_EOP (0x00000010ul)
|
||||
#define EFM_FLAG_COLERR (0x00000020ul)
|
||||
#define EFM_FLAG_RDY (0x00000100ul)
|
||||
|
||||
/* Flash operate mode */
|
||||
#define EFM_MODE_READONLY (0ul)
|
||||
#define EFM_MODE_SINGLEPROGRAM (1ul)
|
||||
#define EFM_MODE_SINGLEPROGRAMRB (2ul)
|
||||
#define EFM_MODE_SEQUENCEPROGRAM (3ul)
|
||||
#define EFM_MODE_SECTORERASE (4ul)
|
||||
#define EFM_MODE_CHIPERASE (5ul)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void EFM_Unlock(void);
|
||||
void EFM_Lock(void);
|
||||
|
||||
void EFM_FlashCmd(en_functional_state_t enNewState);
|
||||
void EFM_SetLatency(uint32_t u32Latency);
|
||||
void EFM_InstructionCacheCmd(en_functional_state_t enNewState);
|
||||
void EFM_DataCacheRstCmd(en_functional_state_t enNewState);
|
||||
void EFM_SetReadMode(en_efm_read_md_t enReadMD);
|
||||
void EFM_ErasePgmCmd(en_functional_state_t enNewState);
|
||||
en_result_t EFM_SetErasePgmMode(uint32_t u32Mode);
|
||||
void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState);
|
||||
|
||||
en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag);
|
||||
en_flag_status_t EFM_GetSwitchStatus(void);
|
||||
void EFM_ClearFlag(uint32_t u32flag);
|
||||
en_efm_flash_status_t EFM_GetStatus(void);
|
||||
void EFM_SetBusState(en_efm_bus_sta_t enState);
|
||||
|
||||
void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr);
|
||||
|
||||
en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data);
|
||||
en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data);
|
||||
en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf);
|
||||
en_result_t EFM_SectorErase(uint32_t u32Addr);
|
||||
en_result_t EFM_MassErase(uint32_t u32Addr);
|
||||
|
||||
en_result_t EFM_OtpLock(uint32_t u32Addr);
|
||||
stc_efm_unique_id_t EFM_ReadUID(void);
|
||||
|
||||
|
||||
//@} // EfmGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_EFM_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_EFM_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
||||
@@ -0,0 +1,205 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_emb.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link EMBGroup EMB description @endlink
|
||||
**
|
||||
** - 2018-11-24 CDT First version for Device Driver Library of EMB.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_EMB_H__
|
||||
#define __HC32F460_EMB_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_EMB_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup EMBGroup Emergency Brake(EMB)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB status enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_emb_status
|
||||
{
|
||||
EMBFlagPortIn = 0u, ///< EMB port in brake flag
|
||||
EMBFlagPWMSame = 1u, ///< EMB PWM same brake flag
|
||||
EMBFlagCmp = 2u, ///< EMB CMP brake flag
|
||||
EMBFlagOSCFail = 3u, ///< EMB oscillator fail brake flag
|
||||
EMBPortInState = 4u, ///< EMB port in state
|
||||
EMBPWMState = 5u, ///< EMB PWM same state
|
||||
} en_emb_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB status clear(recover) enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_emb_status_clr
|
||||
{
|
||||
EMBPortInFlagClr = 0u, ///< EMB port in brake flag clear
|
||||
EMBPWMSameFlagCLr = 1u, ///< EMB PWM same brake flag clear
|
||||
EMBCmpFlagClr = 2u, ///< EMB CMP brake flag clear
|
||||
EMBOSCFailFlagCLr = 3u, ///< EMB oscillator fail brake flag clear
|
||||
} en_emb_status_clr_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB irq enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_emb_irq_type
|
||||
{
|
||||
PORTBrkIrq = 0u, ///< EMB port brake interrupt
|
||||
PWMSmBrkIrq = 1u, ///< EMB PWM same brake interrupt
|
||||
CMPBrkIrq = 2u, ///< EMB CMP brake interrupt
|
||||
OSCFailBrkIrq = 3u, ///< EMB oscillator fail brake interrupt
|
||||
} en_emb_irq_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB port in filter enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_emb_port_filter
|
||||
{
|
||||
EMBPortFltDiv0 = 0u, ///< EMB port in filter with PCLK clock
|
||||
EMBPortFltDiv8 = 1u, ///< EMB port in filter with PCLK/8 clock
|
||||
EMBPortFltDiv32 = 2u, ///< EMB port in filter with PCLK/32 clock
|
||||
EMBPortFltDiv128 = 3u, ///< EMB port in filter with PCLK/128 clock
|
||||
} en_emb_port_filter_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB CR0 for timer6 config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_emb_ctrl_timer6
|
||||
{
|
||||
bool bEnPortBrake; ///< Enable port brake
|
||||
bool bEnCmp1Brake; ///< Enable CMP1 brake
|
||||
bool bEnCmp2Brake; ///< Enable CMP2 brake
|
||||
bool bEnCmp3Brake; ///< Enable CMP3 brake
|
||||
bool bEnOSCFailBrake; ///< Enable OSC fail brake
|
||||
bool bEnTimer61PWMSBrake; ///< Enable tiemr61 PWM same brake
|
||||
bool bEnTimer62PWMSBrake; ///< Enable tiemr62 PWM same brake
|
||||
bool bEnTimer63PWMSBrake; ///< Enable tiemr63 PWM same brake
|
||||
en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection
|
||||
bool bEnPorInFlt; ///< Enable port in filter
|
||||
bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel
|
||||
}stc_emb_ctrl_timer6_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB CR1~3 for timer4x config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_emb_ctrl_timer4
|
||||
{
|
||||
bool bEnPortBrake; ///< Enable port brake
|
||||
bool bEnCmp1Brake; ///< Enable CMP1 brake
|
||||
bool bEnCmp2Brake; ///< Enable CMP2 brake
|
||||
bool bEnCmp3Brake; ///< Enable CMP3 brake
|
||||
bool bEnOSCFailBrake; ///< Enable OS fail brake
|
||||
bool bEnTimer4xWHLSammeBrake; ///< Enable tiemr4x PWM WH WL same brake
|
||||
bool bEnTimer4xVHLSammeBrake; ///< Enable tiemr4x PWM VH VL same brake
|
||||
bool bEnTimer4xUHLSammeBrake; ///< Enable tiemr4x PWM UH UL same brake
|
||||
en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection
|
||||
bool bEnPorInFlt; ///< Enable port in filter
|
||||
bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel
|
||||
}stc_emb_ctrl_timer4_t;
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB PWM level detect timer6 config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_emb_pwm_level_timer6
|
||||
{
|
||||
bool bEnTimer61HighLevelDect; ///< Enable tiemr61 active detected level 1:HighLevel 0:LowLevel
|
||||
bool bEnTimer62HighLevelDect; ///< Enable tiemr62 active detected level 1:HighLevel 0:LowLevel
|
||||
bool bEnTimer63HighLevelDect; ///< Enable tiemr63 active detected level 1:HighLevel 0:LowLevel
|
||||
}stc_emb_pwm_level_timer6_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB PWM level detect timer4x config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_emb_pwm_level_timer4
|
||||
{
|
||||
bool bEnUHLPhaseHighLevelDect; ///< Enable tiemr4x UH UL active detected level 1:HighLevel 0:LowLevel
|
||||
bool bEnVHLPhaseHighLevelDect; ///< Enable tiemr4x VH VL active detected level 1:HighLevel 0:LowLevel
|
||||
bool bEnWHLphaseHighLevelDect; ///< Enable tiemr4x WH WL active detected level 1:HighLevel 0:LowLevel
|
||||
}stc_emb_pwm_level_timer4_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/* IRQ config */
|
||||
en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx,
|
||||
en_emb_irq_type_t enEMBIrq,
|
||||
bool bEn);
|
||||
/* Get status(flag) */
|
||||
bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus);
|
||||
/* Status(flag) clear (recover) */
|
||||
en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx,
|
||||
en_emb_status_clr_t enStatusClr);
|
||||
/* Control Register(CTL) config for timer6 */
|
||||
en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR);
|
||||
/* Control Register(CTL) config for timer4 */
|
||||
en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx,
|
||||
const stc_emb_ctrl_timer4_t* pstcEMBConfigCR);
|
||||
/* PWM level detect (short detection) selection config for timer6 */
|
||||
en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv);
|
||||
/* PWM level detect (short detection) selection config for timer4 */
|
||||
en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx,
|
||||
const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv);
|
||||
/* Software brake */
|
||||
en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn);
|
||||
|
||||
//@} // EMBGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_EMB_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_EMB_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,176 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_event_port.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link EventPortGroup EventPort description @endlink
|
||||
**
|
||||
** - 2018-12-07 CDT First version for Device Driver Library of EventPort.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HC32F460_EVENT_PORT_H__
|
||||
#define __HC32F460_EVENT_PORT_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_EVENT_PORT_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup EventPortGroup Event Port (EventPort)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event Port Index enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_event_port
|
||||
{
|
||||
EventPort1 = 0, ///< Event port 1
|
||||
EventPort2 = 1, ///< Event port 2
|
||||
EventPort3 = 2, ///< Event port 3
|
||||
EventPort4 = 3, ///< Event port 4
|
||||
}en_event_port_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event Port Pin enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_event_pin
|
||||
{
|
||||
EventPin00 = 1u << 0, ///< Event port Pin 00
|
||||
EventPin01 = 1u << 1, ///< Event port Pin 01
|
||||
EventPin02 = 1u << 2, ///< Event port Pin 02
|
||||
EventPin03 = 1u << 3, ///< Event port Pin 03
|
||||
EventPin04 = 1u << 4, ///< Event port Pin 04
|
||||
EventPin05 = 1u << 5, ///< Event port Pin 05
|
||||
EventPin06 = 1u << 6, ///< Event port Pin 06
|
||||
EventPin07 = 1u << 7, ///< Event port Pin 07
|
||||
EventPin08 = 1u << 8, ///< Event port Pin 08
|
||||
EventPin09 = 1u << 9, ///< Event port Pin 09
|
||||
EventPin10 = 1u << 10, ///< Event port Pin 10
|
||||
EventPin11 = 1u << 11, ///< Event port Pin 11
|
||||
EventPin12 = 1u << 12, ///< Event port Pin 12
|
||||
EventPin13 = 1u << 13, ///< Event port Pin 13
|
||||
EventPin14 = 1u << 14, ///< Event port Pin 14
|
||||
EventPin15 = 1u << 15, ///< Event port Pin 15
|
||||
EventPinAll= 0xFFFF, ///< All event pins are selected
|
||||
}en_event_pin_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event Port common trigger source select
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_event_port_com_trigger
|
||||
{
|
||||
EpComTrigger_1 = 0x1, ///< Select common trigger 1.
|
||||
EpComTrigger_2 = 0x2, ///< Select common trigger 2.
|
||||
EpComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2.
|
||||
} en_event_port_com_trigger_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event Port direction enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_event_port_dir
|
||||
{
|
||||
EventPortIn = 0, ///< Event Port direction 'IN'
|
||||
EventPortOut = 1, ///< Event Port direction 'OUT'
|
||||
}en_event_port_dir_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to filter clock setting for Event port detect
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_ep_flt_clk
|
||||
{
|
||||
Pclk1Div1 = 0u, ///< PCLK1 as EP filter clock source
|
||||
Pclk1Div8 = 1u, ///< PCLK1 div8 as EP filter clock source
|
||||
Pclk1Div32 = 2u, ///< PCLK1 div32 as EP filter clock source
|
||||
Pclk1Div64 = 3u, ///< PCLK1 div64 as EP filter clock source
|
||||
}en_ep_flt_clk_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event port init structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_event_port_init
|
||||
{
|
||||
en_event_port_dir_t enDirection; ///< Input/Output setting
|
||||
en_functional_state_t enReset; ///< Corresponding pin reset after triggered
|
||||
en_functional_state_t enSet; ///< Corresponding pin set after triggered
|
||||
en_functional_state_t enRisingDetect; ///< Rising edge detect enable
|
||||
en_functional_state_t enFallingDetect;///< Falling edge detect enable
|
||||
en_functional_state_t enFilter; ///< Filter clock source select
|
||||
en_ep_flt_clk_t enFilterClk; ///< Filter clock, ref@ en_ep_flt_clk_t for details
|
||||
}stc_event_port_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
extern en_result_t EVENTPORT_Init(en_event_port_t enEventPort, \
|
||||
uint16_t u16EventPin, const stc_event_port_init_t *pstcEventPortInit);
|
||||
extern en_result_t EVENTPORT_DeInit(void);
|
||||
extern en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort, \
|
||||
en_event_src_t enTriggerSrc);
|
||||
void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort, \
|
||||
en_event_port_com_trigger_t enComTrigger, \
|
||||
en_functional_state_t enState);
|
||||
extern uint16_t EVENTPORT_GetData(en_event_port_t enEventPort);
|
||||
extern en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort, \
|
||||
en_event_pin_t enEventPin);
|
||||
extern en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort, \
|
||||
en_event_pin_t u16EventPin);
|
||||
extern en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort, \
|
||||
en_event_pin_t u16EventPin);
|
||||
|
||||
//@} // EventPortGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_EVENT_PORT_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_EVENT_PORT_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,257 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_exint_nmi_swi.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link ExintNmiSwiGroup Exint/Nmi/Swi description @endlink
|
||||
**
|
||||
** - 2018-10-17 CDT First version for Device Driver Library of exint, Nmi, SW interrupt.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HC32F460_EXINT_NMI_SWI_H__
|
||||
#define __HC32F460_EXINT_NMI_SWI_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup ExintNmiSwiGroup External Interrupts (External Interrupt), \
|
||||
** NMI (Non-Maskable Interrupt), SWI (Software Interrupt)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to filter clock setting for EXINT and NMI
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_ei_flt_clk
|
||||
{
|
||||
Pclk3Div1 = 0u, ///< PCLK3 as EP filter clock source
|
||||
Pclk3Div8 = 1u, ///< PCLK3 div8 as EP filter clock source
|
||||
Pclk3Div32 = 2u, ///< PCLK3 div32 as EP filter clock source
|
||||
Pclk3Div64 = 3u, ///< PCLK3 div64 as EP filter clock source
|
||||
}en_ei_flt_clk_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to NMI detection
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_nmi_lvl
|
||||
{
|
||||
NmiFallingEdge = 0u, ///< Falling edge detection
|
||||
NmiRisingEdge = 1u, ///< Rising edge detection
|
||||
}en_nmi_lvl_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to EXTI detection
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_exti_lvl
|
||||
{
|
||||
ExIntFallingEdge = 0u, ///< Falling edge detection
|
||||
ExIntRisingEdge = 1u, ///< Rising edge detection
|
||||
ExIntBothEdge = 2u, ///< Falling or Rising edge detection
|
||||
ExIntLowLevel = 3u, ///< "L" level detection
|
||||
}en_exti_lvl_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to define an index for EXINT
|
||||
******************************************************************************/
|
||||
typedef enum en_exti_ch
|
||||
{
|
||||
ExtiCh00 = 0u,
|
||||
ExtiCh01 = 1u,
|
||||
ExtiCh02 = 2u,
|
||||
ExtiCh03 = 3u,
|
||||
ExtiCh04 = 4u,
|
||||
ExtiCh05 = 5u,
|
||||
ExtiCh06 = 6u,
|
||||
ExtiCh07 = 7u,
|
||||
ExtiCh08 = 8u,
|
||||
ExtiCh09 = 9u,
|
||||
ExtiCh10 = 10u,
|
||||
ExtiCh11 = 11u,
|
||||
ExtiCh12 = 12u,
|
||||
ExtiCh13 = 13u,
|
||||
ExtiCh14 = 14u,
|
||||
ExtiCh15 = 15u,
|
||||
}en_exti_ch_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to define the SWI channel
|
||||
******************************************************************************/
|
||||
typedef enum en_swi_ch
|
||||
{
|
||||
SwiCh00 = 1u << 0,
|
||||
SwiCh01 = 1u << 1,
|
||||
SwiCh02 = 1u << 2,
|
||||
SwiCh03 = 1u << 3,
|
||||
SwiCh04 = 1u << 4,
|
||||
SwiCh05 = 1u << 5,
|
||||
SwiCh06 = 1u << 6,
|
||||
SwiCh07 = 1u << 7,
|
||||
SwiCh08 = 1u << 8,
|
||||
SwiCh09 = 1u << 9,
|
||||
SwiCh10 = 1u << 10,
|
||||
SwiCh11 = 1u << 11,
|
||||
SwiCh12 = 1u << 12,
|
||||
SwiCh13 = 1u << 13,
|
||||
SwiCh14 = 1u << 14,
|
||||
SwiCh15 = 1u << 15,
|
||||
SwiCh16 = 1u << 16,
|
||||
SwiCh17 = 1u << 17,
|
||||
SwiCh18 = 1u << 18,
|
||||
SwiCh19 = 1u << 19,
|
||||
SwiCh20 = 1u << 20,
|
||||
SwiCh21 = 1u << 21,
|
||||
SwiCh22 = 1u << 22,
|
||||
SwiCh23 = 1u << 23,
|
||||
SwiCh24 = 1u << 24,
|
||||
SwiCh25 = 1u << 25,
|
||||
SwiCh26 = 1u << 26,
|
||||
SwiCh27 = 1u << 27,
|
||||
SwiCh28 = 1u << 28,
|
||||
SwiCh29 = 1u << 29,
|
||||
SwiCh30 = 1u << 30,
|
||||
SwiCh31 = 1u << 31,
|
||||
}en_swi_ch_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief External Interrupt configuration
|
||||
**
|
||||
** \note The EXINT configuration
|
||||
******************************************************************************/
|
||||
typedef struct stc_exint_config
|
||||
{
|
||||
en_exti_ch_t enExitCh; ///< External Int CH.0~15 ref@ en_exti_ch_t
|
||||
en_functional_state_t enFilterEn; ///< TRUE: Enable filter function
|
||||
en_ei_flt_clk_t enFltClk; ///< Filter clock, ref@ en_ei_flt_clk_t for details
|
||||
en_exti_lvl_t enExtiLvl; ///< Detection level, ref@ en_exti_lvl_t for details
|
||||
}stc_exint_config_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to NMI Trigger source
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_nmi_src
|
||||
{
|
||||
NmiSrcNmi = 1u << 0, ///< NMI pin
|
||||
NmiSrcSwdt = 1u << 1, ///< Special watch dog timer
|
||||
NmiSrcVdu1 = 1u << 2, ///< Voltage detect 1
|
||||
NmiSrcVdu2 = 1u << 3, ///< Voltage detect 2
|
||||
NmiSrcXtalStop = 1u << 5, ///< Xtal stop
|
||||
NmiSrcSramPE = 1u << 8, ///< SRAM1/2/HS/Ret parity error
|
||||
NmiSrcSramDE = 1u << 9, ///< SRAM3 ECC error
|
||||
NmiSrcMpu = 1u << 10, ///< MPU error
|
||||
NmiSrcWdt = 1u << 11, ///< Watch dog timer
|
||||
}en_nmi_src_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to software interrupt or event
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_swi_type
|
||||
{
|
||||
SwEvent = 0u, ///< software event
|
||||
SwInt = 1u, ///< software interrupt
|
||||
}en_swi_type_t;
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief NMI configuration
|
||||
**
|
||||
** \note The NMI configuration
|
||||
******************************************************************************/
|
||||
typedef struct stc_nmi_config
|
||||
{
|
||||
en_functional_state_t enFilterEn; ///< TRUE: Enable filter function
|
||||
en_ei_flt_clk_t enFilterClk; ///< Filter clock, ref@ en_flt_clk_t for details
|
||||
en_nmi_lvl_t enNmiLvl; ///< Detection level, ref@ en_nmi_lvl_t for details
|
||||
uint16_t u16NmiSrc; ///< NMI trigger source, ref@ en_nmi_src_t for details
|
||||
func_ptr_t pfnNmiCallback; ///< Callback pointers
|
||||
}stc_nmi_config_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SWI configuration
|
||||
**
|
||||
** \note The SWI configuration
|
||||
******************************************************************************/
|
||||
typedef struct stc_swi_config
|
||||
{
|
||||
en_swi_ch_t enSwiCh; ///< SWI channel
|
||||
en_swi_type_t enSwiType; ///< Select software interrupt or event
|
||||
func_ptr_t pfnSwiCallback; ///< Callback pointers
|
||||
}stc_swi_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
extern en_result_t EXINT_Init(const stc_exint_config_t *pstcExtiConfig);
|
||||
extern en_int_status_t EXINT_IrqFlgGet(en_exti_ch_t enExint);
|
||||
extern en_result_t EXINT_IrqFlgClr(en_exti_ch_t enExint);
|
||||
extern en_result_t NMI_Init(const stc_nmi_config_t *pstcNmiConfig);
|
||||
extern en_result_t NMI_DeInit(void);
|
||||
extern en_int_status_t NMI_IrqFlgGet(en_nmi_src_t enNmiSrc);
|
||||
extern en_result_t NMI_IrqFlgClr(uint16_t u16NmiSrc);
|
||||
extern en_result_t SWI_Enable(uint32_t u32SwiCh);
|
||||
extern en_result_t SWI_Disable(uint32_t u32SwiCh);
|
||||
|
||||
//@} // ExintNmiSwiGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_EXINT_NMI_SWI_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_EXINT_NMI_SWI_H__ */
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,294 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_gpio.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link GpioGroup Gpio description @endlink
|
||||
**
|
||||
** - 2018-10-12 CDT First version for Device Driver Library of Gpio.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HC32F460_GPIO_H__
|
||||
#define __HC32F460_GPIO_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_GPIO_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup GpioGroup General Purpose Input/Output(GPIO)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief GPIO Configuration Mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pin_mode
|
||||
{
|
||||
Pin_Mode_In = 0, ///< GPIO Input mode
|
||||
Pin_Mode_Out = 1, ///< GPIO Output mode
|
||||
Pin_Mode_Ana = 2, ///< GPIO Analog mode
|
||||
}en_pin_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief GPIO Drive Capacity enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pin_drv
|
||||
{
|
||||
Pin_Drv_L = 0, ///< Low Drive Capacity
|
||||
Pin_Drv_M = 1, ///< Middle Drive Capacity
|
||||
Pin_Drv_H = 2, ///< High Drive Capacity
|
||||
}en_pin_drv_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief GPIO Output Type enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_pin_o_type
|
||||
{
|
||||
Pin_OType_Cmos = 0, ///< CMOS
|
||||
Pin_OType_Od = 1, ///< Open Drain
|
||||
}en_pin_o_type_t;
|
||||
|
||||
|
||||
typedef enum en_debug_port
|
||||
{
|
||||
TCK_SWCLK = 1 << 0, ///< TCK or SWCLK
|
||||
TMS_SWDIO = 1 << 1, ///< TMS or SWDIO
|
||||
TDO_SWO = 1 << 2, ///< TOD or SWD
|
||||
TDI = 1 << 3, ///< TDI
|
||||
TRST = 1 << 4, ///< TRest
|
||||
ALL_DBG_PIN = 0x1Fu ///< All above
|
||||
}en_debug_port_t;
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief GPIO Port Index enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_port
|
||||
{
|
||||
PortA = 0, ///< port group A
|
||||
PortB = 1, ///< port group B
|
||||
PortC = 2, ///< port group C
|
||||
PortD = 3, ///< port group D
|
||||
PortE = 4, ///< port group E
|
||||
PortH = 5, ///< port group H
|
||||
}en_port_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief GPIO Pin Index enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_pin
|
||||
{
|
||||
Pin00 = (1 << 0), ///< Pin index 00 of each port group
|
||||
Pin01 = (1 << 1), ///< Pin index 01 of each port group
|
||||
Pin02 = (1 << 2), ///< Pin index 02 of each port group
|
||||
Pin03 = (1 << 3), ///< Pin index 03 of each port group
|
||||
Pin04 = (1 << 4), ///< Pin index 04 of each port group
|
||||
Pin05 = (1 << 5), ///< Pin index 05 of each port group
|
||||
Pin06 = (1 << 6), ///< Pin index 06 of each port group
|
||||
Pin07 = (1 << 7), ///< Pin index 07 of each port group
|
||||
Pin08 = (1 << 8), ///< Pin index 08 of each port group
|
||||
Pin09 = (1 << 9), ///< Pin index 09 of each port group
|
||||
Pin10 = (1 << 10), ///< Pin index 10 of each port group
|
||||
Pin11 = (1 << 11), ///< Pin index 11 of each port group
|
||||
Pin12 = (1 << 12), ///< Pin index 12 of each port group
|
||||
Pin13 = (1 << 13), ///< Pin index 13 of each port group
|
||||
Pin14 = (1 << 14), ///< Pin index 14 of each port group
|
||||
Pin15 = (1 << 15), ///< Pin index 15 of each port group
|
||||
PinAll= 0xFFFF, ///< All pins selected
|
||||
}en_pin_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief GPIO Pin read wait cycle enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_read_wait
|
||||
{
|
||||
WaitCycle0 = 0, ///< no wait cycle, operation freq. lower than 42MHz
|
||||
WaitCycle1 = 1, ///< one wait cycle, operation freq. @[42~84)MHz
|
||||
WaitCycle2 = 2, ///< two wait cycles, operation freq. @[84~126)MHz
|
||||
WaitCycle3 = 3, ///< three wait cycles, operation freq. @[126~200)MHz
|
||||
}en_read_wait_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief GPIO Function enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_port_func
|
||||
{
|
||||
Func_Gpio = 0u, ///< function set to gpio
|
||||
Func_Fcmref = 1u, ///< function set to fcm reference
|
||||
Func_Rtcout = 1u, ///< function set to rtc output
|
||||
Func_Vcout = 1u, ///< function set to vc output
|
||||
Func_Adtrg = 1u, ///< function set to adc trigger
|
||||
Func_Mclkout = 1u, ///< function set to mclk output
|
||||
Func_Tim4 = 2u, ///< function set to timer4
|
||||
Func_Tim6 = 3u, ///< function set to timer6
|
||||
Func_Tima0 = 4u, ///< function set to timerA
|
||||
Func_Tima1 = 5u, ///< function set to timerA
|
||||
Func_Tima2 = 6u, ///< function set to timerA
|
||||
Func_Emb = 6u, ///< function set to emb
|
||||
Func_Usart_Ck = 7u, ///< function set to usart clk
|
||||
Func_Spi_Nss = 7u, ///< function set to spi nss
|
||||
Func_Qspi = 7u, ///< function set to qspi
|
||||
Func_Key = 8u, ///< function set to key
|
||||
Func_Sdio = 9u, ///< function set to sdio
|
||||
Func_I2s = 10u, ///< function set to i2s
|
||||
Func_UsbF = 10u, ///< function set to usb full speed
|
||||
Func_Evnpt = 14u, ///< function set to event port
|
||||
Func_Eventout = 15u, ///< function set to event out
|
||||
Func_Usart1_Tx = 32u, ///< function set to usart tx of ch.1
|
||||
Func_Usart3_Tx = 32u, ///< function set to usart tx of ch.3
|
||||
Func_Usart1_Rx = 33u, ///< function set to usart rx of ch.1
|
||||
Func_Usart3_Rx = 33u, ///< function set to usart rx of ch.3
|
||||
Func_Usart1_Rts = 34u, ///< function set to usart rts of ch.1
|
||||
Func_Usart3_Rts = 34u, ///< function set to usart rts of ch.3
|
||||
Func_Usart1_Cts = 35u, ///< function set to usart cts of ch.1
|
||||
Func_Usart3_Cts = 35u, ///< function set to usart cts of ch.3
|
||||
Func_Usart2_Tx = 36u, ///< function set to usart tx of ch.2
|
||||
Func_Usart4_Tx = 36u, ///< function set to usart tx of ch.4
|
||||
Func_Usart2_Rx = 37u, ///< function set to usart rx of ch.2
|
||||
Func_Usart4_Rx = 37u, ///< function set to usart rx of ch.4
|
||||
Func_Usart2_Rts = 38u, ///< function set to usart rts of ch.2
|
||||
Func_Usart4_Rts = 38u, ///< function set to usart rts of ch.4
|
||||
Func_Usart2_Cts = 39u, ///< function set to usart cts of ch.2
|
||||
Func_Usart4_Cts = 39u, ///< function set to usart cts of ch.4
|
||||
Func_Spi1_Mosi = 40u, ///< function set to spi mosi of ch.1
|
||||
Func_Spi3_Mosi = 40u, ///< function set to spi mosi of ch.3
|
||||
Func_Spi1_Miso = 41u, ///< function set to spi miso of ch.1
|
||||
Func_Spi3_Miso = 41u, ///< function set to spi miso of ch.3
|
||||
Func_Spi1_Nss0 = 42u, ///< function set to spi nss0 of ch.1
|
||||
Func_Spi3_Nss0 = 42u, ///< function set to spi nss0 of ch.3
|
||||
Func_Spi1_Sck = 43u, ///< function set to spi sck of ch.1
|
||||
Func_Spi3_Sck = 43u, ///< function set to spi sck of ch.3
|
||||
Func_Spi2_Mosi = 44u, ///< function set to spi mosi of ch.2
|
||||
Func_Spi4_Mosi = 44u, ///< function set to spi mosi of ch.2
|
||||
Func_Spi2_Miso = 45u, ///< function set to spi miso of ch.4
|
||||
Func_Spi4_Miso = 45u, ///< function set to spi miso of ch.4
|
||||
Func_Spi2_Nss0 = 46u, ///< function set to spi nss0 of ch.2
|
||||
Func_Spi4_Nss0 = 46u, ///< function set to spi nss0 of ch.4
|
||||
Func_Spi2_Sck = 47u, ///< function set to spi sck of ch.2
|
||||
Func_Spi4_Sck = 47u, ///< function set to spi sck of ch.4
|
||||
Func_I2c1_Sda = 48u, ///< function set to i2c sda of ch.1
|
||||
Func_I2c3_Sda = 48u, ///< function set to i2c sda of ch.3
|
||||
Func_I2c1_Scl = 49u, ///< function set to i2c scl of ch.1
|
||||
Func_I2c3_Scl = 49u, ///< function set to i2c scl of ch.3
|
||||
Func_I2c2_Sda = 50u, ///< function set to i2c sda of ch.2
|
||||
Func_Can1_Tx = 50u, ///< function set to can tx of ch.1
|
||||
Func_I2c2_Scl = 51u, ///< function set to i2c scl of ch.2
|
||||
Func_Can1_Rx = 51u, ///< function set to can rx of ch.1
|
||||
Func_I2s1_Sd = 52u, ///< function set to i2s sd of ch.1
|
||||
Func_I2s3_Sd = 52u, ///< function set to i2s sd of ch.3
|
||||
Func_I2s1_Sdin = 53u, ///< function set to i2s sdin of ch.1
|
||||
Func_I2s3_Sdin = 53u, ///< function set to i2s sdin of ch.3
|
||||
Func_I2s1_Ws = 54u, ///< function set to i2s ws of ch.1
|
||||
Func_I2s3_Ws = 54u, ///< function set to i2s ws of ch.3
|
||||
Func_I2s1_Ck = 55u, ///< function set to i2s ck of ch.1
|
||||
Func_I2s3_Ck = 55u, ///< function set to i2s ck of ch.3
|
||||
Func_I2s2_Sd = 56u, ///< function set to i2s sd of ch.2
|
||||
Func_I2s4_Sd = 56u, ///< function set to i2s sd of ch.4
|
||||
Func_I2s2_Sdin = 57u, ///< function set to i2s sdin of ch.2
|
||||
Func_I2s4_Sdin = 57u, ///< function set to i2s sdin of ch.4
|
||||
Func_I2s2_Ws = 58u, ///< function set to i2s ws of ch.2
|
||||
Func_I2s4_Ws = 58u, ///< function set to i2s ws of ch.4
|
||||
Func_I2s2_Ck = 59u, ///< function set to i2s ck of ch.2
|
||||
Func_I2s4_Ck = 59u, ///< function set to i2s ck of ch.4
|
||||
}en_port_func_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief GPIO init structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_port_init
|
||||
{
|
||||
en_pin_mode_t enPinMode; ///< Set pin mode @ref en_pin_mode_t
|
||||
en_functional_state_t enLatch; ///< Pin output latch enable
|
||||
en_functional_state_t enExInt; ///< External int enable
|
||||
en_functional_state_t enInvert; ///< Pin input/output invert enable
|
||||
en_functional_state_t enPullUp; ///< Internal pull-up resistor enable
|
||||
en_pin_drv_t enPinDrv; ///< Drive capacity setting @ref en_pin_drv_t
|
||||
en_pin_o_type_t enPinOType; ///< Output mode setting @ref en_pin_o_type_t
|
||||
en_functional_state_t enPinSubFunc; ///< Pin sub-function enable
|
||||
}stc_port_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief GPIO public setting structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_port_pub_set
|
||||
{
|
||||
en_port_func_t enSubFuncSel; ///< Sub-function setting @ref en_port_func_t
|
||||
en_read_wait_t enReadWait; ///< Read wait cycle setting @ref en_read_wait_t
|
||||
}stc_port_pub_set_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
extern en_result_t PORT_Init(en_port_t enPort, uint16_t u16Pin, \
|
||||
const stc_port_init_t *pstcPortInit);
|
||||
extern en_result_t PORT_DeInit(void);
|
||||
extern void PORT_Unlock(void);
|
||||
extern void PORT_Lock(void);
|
||||
extern en_result_t PORT_DebugPortSetting(uint8_t u8DebugPort, en_functional_state_t enFunc);
|
||||
extern en_result_t PORT_PubSetting(const stc_port_pub_set_t *pstcPortPubSet);
|
||||
extern uint16_t PORT_GetData(en_port_t enPort);
|
||||
extern en_flag_status_t PORT_GetBit(en_port_t enPort, en_pin_t enPin);
|
||||
extern en_result_t PORT_SetPortData(en_port_t enPort, uint16_t u16Pin);
|
||||
extern en_result_t PORT_ResetPortData(en_port_t enPort, uint16_t u16Pin);
|
||||
extern en_result_t PORT_OE(en_port_t enPort, uint16_t u16Pin, en_functional_state_t enNewState);
|
||||
extern en_result_t PORT_SetBits(en_port_t enPort, uint16_t u16Pin);
|
||||
extern en_result_t PORT_ResetBits(en_port_t enPort, uint16_t u16Pin);
|
||||
extern en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin);
|
||||
extern en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin, \
|
||||
en_port_func_t enFuncSel, en_functional_state_t enSubFunc);
|
||||
extern en_result_t PORT_SetSubFunc(en_port_func_t enFuncSel);
|
||||
|
||||
//@} // GpioGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_GPIO_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_GPIO_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,72 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_hash.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link HashGroup Hash description @endlink
|
||||
**
|
||||
** - 2018-10-18 CDT First version for Device Driver Library of Hash.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_HASH_H__
|
||||
#define __HC32F460_HASH_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_HASH_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup HashGroup Hash(HASH)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void HASH_Init(void);
|
||||
void HASH_DeInit(void);
|
||||
en_result_t HASH_Start(const uint8_t *pu8SrcData,
|
||||
uint32_t u32SrcDataSize,
|
||||
uint8_t *pu8MsgDigest,
|
||||
uint32_t u32Timeout);
|
||||
|
||||
//@} // HashGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_HASH_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_HASH_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,270 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_i2c.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link I2cGroup Inter-Integrated Circuit(I2C) description @endlink
|
||||
**
|
||||
** - 2018-10-16 CDT First version for Device Driver Library of I2C.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HC32F460_I2C_H__
|
||||
#define __HC32F460_I2C_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_I2C_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup I2cGroup Inter-Integrated Circuit (I2C)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2c configuration structure
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_i2c_init
|
||||
{
|
||||
uint32_t u32ClockDiv; ///< I2C clock division for i2c source clock
|
||||
uint32_t u32Baudrate; ///< I2C baudrate config
|
||||
uint32_t u32SclTime; ///< The SCL rising and falling time, count of T(i2c source clock after frequency divider)
|
||||
}stc_i2c_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2c SMBUS configuration structure
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_i2c_smbus_init
|
||||
{
|
||||
en_functional_state_t enHostAdrMatchFunc; ///< SMBUS host address matching function
|
||||
en_functional_state_t enDefaultAdrMatchFunc; ///< SMBUS default address matching function
|
||||
en_functional_state_t enAlarmAdrMatchFunc; ///< SMBUS Alarm address matching function
|
||||
}stc_i2c_smbus_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2c digital filter mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_i2c_digital_filter_mode
|
||||
{
|
||||
Filter1BaseCycle = 0u, ///< I2C digital filter ability 1 base cycle
|
||||
Filter2BaseCycle = 1u, ///< I2C digital filter ability 2 base cycle
|
||||
Filter3BaseCycle = 2u, ///< I2C digital filter ability 3 base cycle
|
||||
Filter4BaseCycle = 3u, ///< I2C digital filter ability 4 base cycle
|
||||
}en_i2c_digital_filter_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2c address bit enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_address_bit
|
||||
{
|
||||
Adr7bit = 0u, ///< I2C address length is 7 bits
|
||||
Adr10bit = 1u, ///< I2C address length is 10 bits
|
||||
}en_address_bit_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2c transfer direction enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_trans_direction
|
||||
{
|
||||
I2CDirTrans = 0u,
|
||||
I2CDirReceive = 1u,
|
||||
}en_trans_direction_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2c clock timeout switch enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_clock_timeout_switch
|
||||
{
|
||||
TimeoutFunOff = 0u, ///< I2C SCL pin time out function off
|
||||
LowTimerOutOn = 3u, ///< I2C SCL pin high level time out function on
|
||||
HighTimeOutOn = 5u, ///< I2C SCL pin low level time out function on
|
||||
BothTimeOutOn = 7u, ///< I2C SCL pin both(low and high) level time out function on
|
||||
}en_clock_timeout_switch_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2c clock timeout initialize structure
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_clock_timeout_init
|
||||
{
|
||||
en_clock_timeout_switch_t enClkTimeOutSwitch; ///< I2C clock timeout function switch
|
||||
uint16_t u16TimeOutHigh; ///< I2C clock timeout period for High level
|
||||
uint16_t u16TimeOutLow; ///< I2C clock timeout period for Low level
|
||||
}stc_clock_timeout_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2c ACK config enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_i2c_ack_config
|
||||
{
|
||||
I2c_ACK = 0u,
|
||||
I2c_NACK = 1u,
|
||||
}en_i2c_ack_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* define interrupt enable bit for I2C_CR2 register */
|
||||
#define I2C_CR2_STARTIE (0x00000001ul)
|
||||
#define I2C_CR2_SLADDR0EN (0x00000002ul)
|
||||
#define I2C_CR2_SLADDR1EN (0x00000004ul)
|
||||
#define I2C_CR2_TENDIE (0x00000008ul)
|
||||
#define I2C_CR2_STOPIE (0x00000010ul)
|
||||
#define I2C_CR2_RFULLIE (0x00000040ul)
|
||||
#define I2C_CR2_TEMPTYIE (0x00000080ul)
|
||||
#define I2C_CR2_ARLOIE (0x00000200ul)
|
||||
#define I2C_CR2_NACKIE (0x00001000ul)
|
||||
#define I2C_CR2_TMOURIE (0x00004000ul)
|
||||
#define I2C_CR2_GENCALLIE (0x00100000ul)
|
||||
#define I2C_CR2_SMBDEFAULTIE (0x00200000ul)
|
||||
#define I2C_CR2_SMBHOSTIE (0x00400000ul)
|
||||
#define I2C_CR2_SMBALRTIE (0x00800000ul)
|
||||
|
||||
/* define status bit for I2C_SR register */
|
||||
#define I2C_SR_STARTF (0x00000001ul)
|
||||
#define I2C_SR_SLADDR0F (0x00000002ul)
|
||||
#define I2C_SR_SLADDR1F (0x00000004ul)
|
||||
#define I2C_SR_TENDF (0x00000008ul)
|
||||
#define I2C_SR_STOPF (0x00000010ul)
|
||||
#define I2C_SR_RFULLF (0x00000040ul)
|
||||
#define I2C_SR_TEMPTYF (0x00000080ul)
|
||||
#define I2C_SR_ARLOF (0x00000200ul)
|
||||
#define I2C_SR_ACKRF (0x00000400ul)
|
||||
#define I2C_SR_NACKF (0x00001000ul)
|
||||
#define I2C_SR_TMOUTF (0x00004000ul)
|
||||
#define I2C_SR_MSL (0x00010000ul)
|
||||
#define I2C_SR_BUSY (0x00020000ul)
|
||||
#define I2C_SR_TRA (0x00040000ul)
|
||||
#define I2C_SR_GENCALLF (0x00100000ul)
|
||||
#define I2C_SR_SMBDEFAULTF (0x00200000ul)
|
||||
#define I2C_SR_SMBHOSTF (0x00400000ul)
|
||||
#define I2C_SR_SMBALRTF (0x00800000ul)
|
||||
|
||||
/* define status clear bit for I2C_CLR register*/
|
||||
#define I2C_CLR_STARTFCLR (0x00000001ul)
|
||||
#define I2C_CLR_SLADDR0FCLR (0x00000002ul)
|
||||
#define I2C_CLR_SLADDR1FCLR (0x00000004ul)
|
||||
#define I2C_CLR_TENDFCLR (0x00000008ul)
|
||||
#define I2C_CLR_STOPFCLR (0x00000010ul)
|
||||
#define I2C_CLR_RFULLFCLR (0x00000040ul)
|
||||
#define I2C_CLR_TEMPTYFCLR (0x00000080ul)
|
||||
#define I2C_CLR_ARLOFCLR (0x00000200ul)
|
||||
#define I2C_CLR_NACKFCLR (0x00001000ul)
|
||||
#define I2C_CLR_TMOUTFCLR (0x00004000ul)
|
||||
#define I2C_CLR_GENCALLFCLR (0x00100000ul)
|
||||
#define I2C_CLR_SMBDEFAULTFCLR (0x00200000ul)
|
||||
#define I2C_CLR_SMBHOSTFCLR (0x00400000ul)
|
||||
#define I2C_CLR_SMBALRTFCLR (0x00800000ul)
|
||||
#define I2C_CLR_MASK (0x00F056DFul)
|
||||
|
||||
/* I2C_Clock_Division I2C clock division */
|
||||
#define I2C_CLK_DIV1 (0ul) /* I2c source clock/1 */
|
||||
#define I2C_CLK_DIV2 (1ul) /* I2c source clock/2 */
|
||||
#define I2C_CLK_DIV4 (2ul) /* I2c source clock/4 */
|
||||
#define I2C_CLK_DIV8 (3ul) /* I2c source clock/8 */
|
||||
#define I2C_CLK_DIV16 (4ul) /* I2c source clock/16 */
|
||||
#define I2C_CLK_DIV32 (5ul) /* I2c source clock/32 */
|
||||
#define I2C_CLK_DIV64 (6ul) /* I2c source clock/64 */
|
||||
#define I2C_CLK_DIV128 (7ul) /* I2c source clock/128 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error);
|
||||
en_result_t I2C_DeInit(M4_I2C_TypeDef* pstcI2Cx);
|
||||
en_result_t I2C_Init(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error);
|
||||
void I2C_Cmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
|
||||
en_result_t I2C_SmbusConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_smbus_init_t* pstcI2C_SmbusInitStruct);
|
||||
void I2C_SmBusCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
|
||||
void I2C_SoftwareResetCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_DigitalFilterConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_digital_filter_mode_t enDigiFilterMode);
|
||||
void I2C_DigitalFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
|
||||
void I2C_AnalogFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
|
||||
void I2C_GeneralCallCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
|
||||
void I2C_SlaveAdr0Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr);
|
||||
void I2C_SlaveAdr1Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr);
|
||||
en_result_t I2C_ClkTimeOutConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_clock_timeout_init_t* pstcTimoutInit);
|
||||
void I2C_IntCmd(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32IntEn, en_functional_state_t enNewState);
|
||||
void I2C_FastAckCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
|
||||
void I2C_BusWaitCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_GenerateStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
|
||||
void I2C_GenerateReStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
|
||||
void I2C_GenerateStop(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
|
||||
void I2C_WriteData(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Data);
|
||||
uint8_t I2C_ReadData(M4_I2C_TypeDef* pstcI2Cx);
|
||||
void I2C_AckConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_ack_config_t u32AckConfig);
|
||||
en_flag_status_t I2C_GetStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit);
|
||||
void I2C_ClearStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit);
|
||||
|
||||
/* High level functions for reference ********************************/
|
||||
en_result_t I2C_Start(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout);
|
||||
en_result_t I2C_Restart(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout);
|
||||
en_result_t I2C_TransAddr(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Addr, en_trans_direction_t enDir, uint32_t u32Timeout);
|
||||
en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* pstcI2Cx, uint16_t u16Addr, en_trans_direction_t enDir, uint32_t u32Timeout);
|
||||
en_result_t I2C_TransData(M4_I2C_TypeDef* pstcI2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout);
|
||||
en_result_t I2C_ReceiveData(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
|
||||
en_result_t I2C_Stop(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout);
|
||||
en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *pstcI2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout);
|
||||
en_result_t I2C_MasterDataReceiveAndStop(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
|
||||
|
||||
//@} // I2cGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_I2C_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_I2C_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,206 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_i2s.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link I2sGroup Inter-IC Sound Bus description @endlink
|
||||
**
|
||||
** - 2018-10-28 CDT First version for Device Driver Library of I2S.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HC32F460_I2S_H__
|
||||
#define __HC32F460_I2S_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_I2S_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup I2sGroup Inter-IC Sound(I2S)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2S function
|
||||
******************************************************************************/
|
||||
typedef enum en_i2s_func
|
||||
{
|
||||
TxEn = 0u, ///< Transfer enable function
|
||||
TxIntEn = 1u, ///< Transfer interrupt enable function
|
||||
RxEn = 2u, ///< receive enable function
|
||||
RxIntEn = 3u, ///< receive interrupt enable function
|
||||
ErrIntEn = 4u, ///< error interrupt enable function
|
||||
}en_i2s_func_t;
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2S status flag
|
||||
******************************************************************************/
|
||||
typedef enum en_i2s_std
|
||||
{
|
||||
TxBufAlarmFlag = 0u,
|
||||
RxBufAlarmFlag = 1u,
|
||||
TxBufEmptFlag = 2u,
|
||||
TxBufFullFlag = 3u,
|
||||
RxBufEmptFlag = 4u,
|
||||
RxBufFullFlag = 5u,
|
||||
}en_i2s_std_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2S clr flag
|
||||
******************************************************************************/
|
||||
typedef enum en_i2s_err_flag
|
||||
{
|
||||
ClrTxErrFlag = 0u,
|
||||
ClrRxErrFlag = 1u,
|
||||
}en_i2s_err_flag_t;
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2S mode
|
||||
******************************************************************************/
|
||||
typedef enum en_i2s_mode
|
||||
{
|
||||
I2sMaster = 0u, ///< I2S Master mode
|
||||
I2sSlave = 1u, ///< I2S Slave mode
|
||||
}en_i2s_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2S full duplex mode
|
||||
******************************************************************************/
|
||||
typedef enum en_i2s_full_duplex_mode
|
||||
{
|
||||
I2s_HalfDuplex = 0u, ///< I2S half duplex
|
||||
I2s_FullDuplex = 1u, ///< I2S full duplex
|
||||
}en_i2s_full_duplex_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2S standard
|
||||
******************************************************************************/
|
||||
typedef enum en_i2s_standard
|
||||
{
|
||||
Std_Philips = 0u, ///< I2S Philips standard
|
||||
Std_MSBJust = 1u, ///< I2S MSB justified standart
|
||||
Std_LSBJust = 2u, ///< I2S LSB justified standart
|
||||
Std_PCM = 3u, ///< I2S PCM standart
|
||||
}en_i2s_standard_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2S channel data length
|
||||
******************************************************************************/
|
||||
typedef enum en_i2s_ch_len
|
||||
{
|
||||
I2s_ChLen_16Bit = 0u,
|
||||
I2s_ChLen_32Bit = 1u,
|
||||
}en_i2s_ch_len_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2S data length
|
||||
******************************************************************************/
|
||||
typedef enum en_i2s_data_len
|
||||
{
|
||||
I2s_DataLen_16Bit = 0u,
|
||||
I2s_DataLen_24Bit = 1u,
|
||||
I2s_DataLen_32Bit = 2u,
|
||||
}en_i2s_data_len_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2S configuration structure
|
||||
******************************************************************************/
|
||||
typedef struct stc_i2s_config
|
||||
{
|
||||
en_i2s_mode_t enMode; ///< I2S mode
|
||||
en_i2s_full_duplex_mode_t enFullDuplexMode; ///< I2S full duplex mode
|
||||
uint32_t u32I2sInterClkFreq; ///< I2S internal clock frequency
|
||||
en_i2s_standard_t enStandrad; ///< I2S standard
|
||||
en_i2s_data_len_t enDataBits; ///< I2S data format, data bits
|
||||
en_i2s_ch_len_t enChanelLen; ///< I2S channel length
|
||||
en_functional_state_t enMcoOutEn; ///< I2S MCK output config
|
||||
en_functional_state_t enExckEn; ///< I2S EXCK function config
|
||||
uint32_t u32AudioFreq; ///< I2S audio frequecy
|
||||
}stc_i2s_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* define audio frequency */
|
||||
#define I2S_AudioFreq_192k (192000ul)
|
||||
#define I2S_AudioFreq_96k (96000ul)
|
||||
#define I2S_AudioFreq_48k (48000ul)
|
||||
#define I2S_AudioFreq_44k (44100ul)
|
||||
#define I2S_AudioFreq_32k (32000ul)
|
||||
#define I2S_AudioFreq_22k (22050ul)
|
||||
#define I2S_AudioFreq_16k (16000ul)
|
||||
#define I2S_AudioFreq_11k (11025ul)
|
||||
#define I2S_AudioFreq_8k (8000ul)
|
||||
#define I2S_AudioFreq_Default (2ul)
|
||||
|
||||
/* if use external clock open this define */
|
||||
#define I2S_EXTERNAL_CLOCK_VAL (12288000ul)
|
||||
|
||||
/* 0,1 or 2 config for tx or tx buffer interrupt warning level */
|
||||
#define RXBUF_IRQ_WL (1ul)
|
||||
#define TXBUF_IRQ_WL (1ul)
|
||||
|
||||
/* 0: Short frame synchronization; 1: Long frame synchronization */
|
||||
#define PCM_SYNC_FRAME (0ul)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t I2s_Init(M4_I2S_TypeDef* pstcI2sReg, const stc_i2s_config_t* pstcI2sCfg);
|
||||
void I2S_SendData(M4_I2S_TypeDef* pstcI2sReg, uint32_t u32Data);
|
||||
uint32_t I2S_RevData(const M4_I2S_TypeDef* pstcI2sReg);
|
||||
void I2S_FuncCmd(M4_I2S_TypeDef* pstcI2sReg, en_i2s_func_t enFunc, en_functional_state_t enNewState);
|
||||
en_flag_status_t I2S_GetStatus(M4_I2S_TypeDef* pstcI2sReg, en_i2s_std_t enStd);
|
||||
en_flag_status_t I2S_GetErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag);
|
||||
void I2S_ClrErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag);
|
||||
en_result_t I2s_DeInit(M4_I2S_TypeDef* pstcI2sReg);
|
||||
|
||||
//@} // I2sGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_I2S_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_I2S_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,406 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_icg.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link IcgGroup Initialize configure description @endlink
|
||||
**
|
||||
** - 2018-10-15 CDT First version for Device Driver Library of ICG.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_ICG_H__
|
||||
#define __HC32F460_ICG_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_ICG_ENABLE == DDL_ON)
|
||||
|
||||
#define WATCH_DOG 1
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup IcgGroup Initialize Configure(ICG)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SWDT running state after reset
|
||||
******************************************************************************/
|
||||
#define SWDT_AUTO_START_AFTER_RESET ((uint16_t)0x0000) ///< SWDT Auto Start after reset
|
||||
#define SWDT_STOP_AFTER_RESET ((uint16_t)0x0001) ///< SWDT stop after reset
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SWDT count underflow or refresh error trigger event type
|
||||
******************************************************************************/
|
||||
#define SWDT_INTERRUPT_REQUEST ((uint16_t)0x0000) ///< WDT trigger interrupt request
|
||||
#define SWDT_RESET_REQUEST ((uint16_t)0x0002) ///< WDT trigger reset request
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SWDT count underflow cycle
|
||||
******************************************************************************/
|
||||
#define SWDT_COUNT_UNDERFLOW_CYCLE_256 ((uint16_t)0x0000) ///< 256 clock cycle
|
||||
#define SWDT_COUNT_UNDERFLOW_CYCLE_4096 ((uint16_t)0x0004) ///< 4096 clock cycle
|
||||
#define SWDT_COUNT_UNDERFLOW_CYCLE_16384 ((uint16_t)0x0008) ///< 16384 clock cycle
|
||||
#define SWDT_COUNT_UNDERFLOW_CYCLE_65536 ((uint16_t)0x000C) ///< 65536 clock cycle
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SWDT count clock division
|
||||
******************************************************************************/
|
||||
#define SWDT_COUNT_SWDTCLK_DIV1 ((uint16_t)0x0000) ///< SWDTCLK
|
||||
#define SWDT_COUNT_SWDTCLK_DIV16 ((uint16_t)0x0040) ///< SWDTCLK/16
|
||||
#define SWDT_COUNT_SWDTCLK_DIV32 ((uint16_t)0x0050) ///< SWDTCLK/32
|
||||
#define SWDT_COUNT_SWDTCLK_DIV64 ((uint16_t)0x0060) ///< SWDTCLK/64
|
||||
#define SWDT_COUNT_SWDTCLK_DIV128 ((uint16_t)0x0070) ///< SWDTCLK/128
|
||||
#define SWDT_COUNT_SWDTCLK_DIV256 ((uint16_t)0x0080) ///< SWDTCLK/256
|
||||
#define SWDT_COUNT_SWDTCLK_DIV2048 ((uint16_t)0x00B0) ///< SWDTCLK/2048
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SWDT allow refresh percent range
|
||||
******************************************************************************/
|
||||
#define SWDT_100PCT ((uint16_t)0x0000) ///< 100%
|
||||
#define SWDT_0To25PCT ((uint16_t)0x0100) ///< 0%~25%
|
||||
#define SWDT_25To50PCT ((uint16_t)0x0200) ///< 25%~50%
|
||||
#define SWDT_0To50PCT ((uint16_t)0x0300) ///< 0%~50%
|
||||
#define SWDT_50To75PCT ((uint16_t)0x0400) ///< 50%~75%
|
||||
#define SWDT_0To25PCT_50To75PCT ((uint16_t)0x0500) ///< 0%~25% & 50%~75%
|
||||
#define SWDT_25To75PCT ((uint16_t)0x0600) ///< 25%~75%
|
||||
#define SWDT_0To75PCT ((uint16_t)0x0700) ///< 0%~75%
|
||||
#define SWDT_75To100PCT ((uint16_t)0x0800) ///< 75%~100%
|
||||
#define SWDT_0To25PCT_75To100PCT ((uint16_t)0x0900) ///< 0%~25% & 75%~100%
|
||||
#define SWDT_25To50PCT_75To100PCT ((uint16_t)0x0A00) ///< 25%~50% & 75%~100%
|
||||
#define SWDT_0To50PCT_75To100PCT ((uint16_t)0x0B00) ///< 0%~50% & 75%~100%
|
||||
#define SWDT_50To100PCT ((uint16_t)0x0C00) ///< 50%~100%
|
||||
#define SWDT_0To25PCT_50To100PCT ((uint16_t)0x0D00) ///< 0%~25% & 50%~100%
|
||||
#define SWDT_25To100PCT ((uint16_t)0x0E00) ///< 25%~100%
|
||||
#define SWDT_0To100PCT ((uint16_t)0x0F00) ///< 0%~100%
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SWDT count control in the sleep/stop mode
|
||||
******************************************************************************/
|
||||
#define SWDT_SPECIAL_MODE_COUNT_CONTINUE ((uint16_t)0x0000) ///< SWDT count continue in the sleep/stop mode
|
||||
#define SWDT_SPECIAL_MODE_COUNT_STOP ((uint16_t)0x1000) ///< SWDT count stop in the sleep/stop mode
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT running state after reset
|
||||
******************************************************************************/
|
||||
#define WDT_AUTO_START_AFTER_RESET ((uint16_t)0x0000) ///< WDT Auto Start after reset
|
||||
#define WDT_STOP_AFTER_RESET ((uint16_t)0x0001) ///< WDT stop after reset
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT count underflow or refresh error trigger event type
|
||||
******************************************************************************/
|
||||
#define WDT_INTERRUPT_REQUEST ((uint16_t)0x0000) ///< WDT trigger interrupt request
|
||||
#define WDT_RESET_REQUEST ((uint16_t)0x0002) ///< WDT trigger reset request
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT count underflow cycle
|
||||
******************************************************************************/
|
||||
#define WDT_COUNT_UNDERFLOW_CYCLE_256 ((uint16_t)0x0000) ///< 256 clock cycle
|
||||
#define WDT_COUNT_UNDERFLOW_CYCLE_4096 ((uint16_t)0x0004) ///< 4096 clock cycle
|
||||
#define WDT_COUNT_UNDERFLOW_CYCLE_16384 ((uint16_t)0x0008) ///< 16384 clock cycle
|
||||
#define WDT_COUNT_UNDERFLOW_CYCLE_65536 ((uint16_t)0x000C) ///< 65536 clock cycle
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT count clock division
|
||||
******************************************************************************/
|
||||
#define WDT_COUNT_PCLK3_DIV4 ((uint16_t)0x0020) ///< PCLK3/4
|
||||
#define WDT_COUNT_PCLK3_DIV64 ((uint16_t)0x0060) ///< PCLK3/64
|
||||
#define WDT_COUNT_PCLK3_DIV128 ((uint16_t)0x0070) ///< PCLK3/128
|
||||
#define WDT_COUNT_PCLK3_DIV256 ((uint16_t)0x0080) ///< PCLK3/256
|
||||
#define WDT_COUNT_PCLK3_DIV512 ((uint16_t)0x0090) ///< PCLK3/512
|
||||
#define WDT_COUNT_PCLK3_DIV1024 ((uint16_t)0x00A0) ///< PCLK3/1024
|
||||
#define WDT_COUNT_PCLK3_DIV2048 ((uint16_t)0x00B0) ///< PCLK3/2048
|
||||
#define WDT_COUNT_PCLK3_DIV8192 ((uint16_t)0x00D0) ///< PCLK3/8192
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT allow refresh percent range
|
||||
******************************************************************************/
|
||||
#define WDT_100PCT ((uint16_t)0x0000) ///< 100%
|
||||
#define WDT_0To25PCT ((uint16_t)0x0100) ///< 0%~25%
|
||||
#define WDT_25To50PCT ((uint16_t)0x0200) ///< 25%~50%
|
||||
#define WDT_0To50PCT ((uint16_t)0x0300) ///< 0%~50%
|
||||
#define WDT_50To75PCT ((uint16_t)0x0400) ///< 50%~75%
|
||||
#define WDT_0To25PCT_50To75PCT ((uint16_t)0x0500) ///< 0%~25% & 50%~75%
|
||||
#define WDT_25To75PCT ((uint16_t)0x0600) ///< 25%~75%
|
||||
#define WDT_0To75PCT ((uint16_t)0x0700) ///< 0%~75%
|
||||
#define WDT_75To100PCT ((uint16_t)0x0800) ///< 75%~100%
|
||||
#define WDT_0To25PCT_75To100PCT ((uint16_t)0x0900) ///< 0%~25% & 75%~100%
|
||||
#define WDT_25To50PCT_75To100PCT ((uint16_t)0x0A00) ///< 25%~50% & 75%~100%
|
||||
#define WDT_0To50PCT_75To100PCT ((uint16_t)0x0B00) ///< 0%~50% & 75%~100%
|
||||
#define WDT_50To100PCT ((uint16_t)0x0C00) ///< 50%~100%
|
||||
#define WDT_0To25PCT_50To100PCT ((uint16_t)0x0D00) ///< 0%~25% & 50%~100%
|
||||
#define WDT_25To100PCT ((uint16_t)0x0E00) ///< 25%~100%
|
||||
#define WDT_0To100PCT ((uint16_t)0x0F00) ///< 0%~100%
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT count control in the sleep mode
|
||||
******************************************************************************/
|
||||
#define WDT_SPECIAL_MODE_COUNT_CONTINUE ((uint16_t)0x0000) ///< WDT count continue in the sleep mode
|
||||
#define WDT_SPECIAL_MODE_COUNT_STOP ((uint16_t)0x1000) ///< WDT count stop in the sleep mode
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief HRC frequency select
|
||||
******************************************************************************/
|
||||
#define HRC_FREQUENCY_20MHZ ((uint16_t)0x0000) ///< HRC frequency 20MHZ
|
||||
#define HRC_FREQUENCY_16MHZ ((uint16_t)0x0001) ///< HRC frequency 16MHZ
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief HRC oscillation state control
|
||||
******************************************************************************/
|
||||
#define HRC_OSCILLATION_START ((uint16_t)0x0000) ///< HRC oscillation start
|
||||
#define HRC_OSCILLATION_STOP ((uint16_t)0x0100) ///< HRC oscillation stop
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief VDU0 threshold voltage select
|
||||
******************************************************************************/
|
||||
#define VDU0_VOLTAGE_THRESHOLD_1P5 ((uint8_t)0x00) ///< VDU0 voltage threshold 1.9V
|
||||
#define VDU0_VOLTAGE_THRESHOLD_2P0 ((uint8_t)0x01) ///< VDU0 voltage threshold 2.0V
|
||||
#define VDU0_VOLTAGE_THRESHOLD_2P1 ((uint8_t)0x02) ///< VDU0 voltage threshold 2.1V
|
||||
#define VDU0_VOLTAGE_THRESHOLD_2P3 ((uint8_t)0x03) ///< VDU0 voltage threshold 2.3V
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief VDU0 running state after reset
|
||||
******************************************************************************/
|
||||
#define VDU0_START_AFTER_RESET ((uint8_t)0x00) ///< VDU0 start after reset
|
||||
#define VDU0_STOP_AFTER_RESET ((uint8_t)0x04) ///< VDU0 stop after reset
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief NMI pin filter sample clock division
|
||||
******************************************************************************/
|
||||
#define NMI_PIN_FILTER_PCLK3_DIV1 ((uint8_t)0x00) ///< PCLK3
|
||||
#define NMI_PIN_FILTER_PCLK3_DIV8 ((uint8_t)0x04) ///< PCLK3/8
|
||||
#define NMI_PIN_FILTER_PCLK3_DIV32 ((uint8_t)0x08) ///< PCLK3/32
|
||||
#define NMI_PIN_FILTER_PCLK3_DIV64 ((uint8_t)0x0C) ///< PCLK3/64
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief NMI pin trigger edge type
|
||||
******************************************************************************/
|
||||
#define NMI_PIN_TRIGGER_EDGE_FALLING ((uint8_t)0x00) ///< Falling edge trigger
|
||||
#define NMI_PIN_TRIGGER_EDGE_RISING ((uint8_t)0x10) ///< Rising edge trigger
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable NMI pin interrupt request
|
||||
******************************************************************************/
|
||||
#define NMI_PIN_IRQ_DISABLE ((uint8_t)0x00) ///< Disable NMI pin interrupt request
|
||||
#define NMI_PIN_IRQ_ENABLE ((uint8_t)0x20) ///< Enable NMI pin interrupt request
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable NMI digital filter function
|
||||
******************************************************************************/
|
||||
#define NMI_DIGITAL_FILTER_DISABLE ((uint8_t)0x00) ///< Disable NMI digital filter
|
||||
#define NMI_DIGITAL_FILTER_ENABLE ((uint8_t)0x40) ///< Enable NMI digital filter
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable NMI pin ICG function
|
||||
******************************************************************************/
|
||||
#define NMI_PIN_ICG_FUNCTION_DISABLE ((uint8_t)0x80) ///< Disable NMI pin ICG function
|
||||
#define NMI_PIN_ICG_FUNCTION_ENABLE ((uint8_t)0x00) ///< Enable NMI pin ICG function
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ICG start configure function on/off
|
||||
******************************************************************************/
|
||||
#ifndef ICG_FUNCTION_ON
|
||||
#define ICG_FUNCTION_ON (1u)
|
||||
#endif
|
||||
|
||||
#ifndef ICG_FUNCTION_OFF
|
||||
#define ICG_FUNCTION_OFF (0u)
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SWDT hardware start configuration
|
||||
******************************************************************************/
|
||||
/*!< Enable or disable SWDT hardware start */
|
||||
#if (WATCH_DOG == 1)
|
||||
#define ICG0_SWDT_HARDWARE_START (ICG_FUNCTION_ON)
|
||||
#else
|
||||
#define ICG0_SWDT_HARDWARE_START (ICG_FUNCTION_OFF)
|
||||
#endif
|
||||
|
||||
/*!< SWDT register config */
|
||||
#define ICG0_SWDT_AUTS (SWDT_AUTO_START_AFTER_RESET)
|
||||
#define ICG0_SWDT_ITS (SWDT_RESET_REQUEST)
|
||||
#define ICG0_SWDT_PERI (SWDT_COUNT_UNDERFLOW_CYCLE_65536) // λʱ 0.8
|
||||
#define ICG0_SWDT_CKS (SWDT_COUNT_SWDTCLK_DIV16)
|
||||
#define ICG0_SWDT_WDPT (SWDT_0To100PCT)
|
||||
#define ICG0_SWDT_SLTPOFF (SWDT_SPECIAL_MODE_COUNT_CONTINUE)
|
||||
|
||||
/*!< SWDT register config value */
|
||||
#if ICG0_SWDT_HARDWARE_START == ICG_FUNCTION_ON
|
||||
#define ICG0_SWDT_REG_CONFIG (ICG0_SWDT_AUTS | ICG0_SWDT_ITS | ICG0_SWDT_PERI | \
|
||||
ICG0_SWDT_CKS | ICG0_SWDT_WDPT | ICG0_SWDT_SLTPOFF)
|
||||
#else
|
||||
#define ICG0_SWDT_REG_CONFIG ((uint16_t)0xFFFF)
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT hardware start configuration
|
||||
******************************************************************************/
|
||||
/*!< Enable or disable WDT hardware start */
|
||||
#define ICG0_WDT_HARDWARE_START (ICG_FUNCTION_OFF)
|
||||
|
||||
/*!< WDT register config */
|
||||
#define ICG0_WDT_AUTS (WDT_STOP_AFTER_RESET)
|
||||
#define ICG0_WDT_ITS (WDT_RESET_REQUEST)
|
||||
#define ICG0_WDT_PERI (WDT_COUNT_UNDERFLOW_CYCLE_16384)
|
||||
#define ICG0_WDT_CKS (WDT_COUNT_PCLK3_DIV8192)
|
||||
#define ICG0_WDT_WDPT (WDT_0To100PCT)
|
||||
#define ICG0_WDT_SLPOFF (WDT_SPECIAL_MODE_COUNT_STOP)
|
||||
|
||||
/*!< WDT register config value */
|
||||
#if ICG0_WDT_HARDWARE_START == ICG_FUNCTION_ON
|
||||
#define ICG0_WDT_REG_CONFIG (ICG0_WDT_AUTS | ICG0_WDT_ITS | ICG0_WDT_PERI | \
|
||||
ICG0_WDT_CKS | ICG0_WDT_WDPT | ICG0_WDT_SLPOFF)
|
||||
#else
|
||||
#define ICG0_WDT_REG_CONFIG ((uint16_t)0xFFFF)
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief HRC hardware start configuration
|
||||
******************************************************************************/
|
||||
/*!< Enable or disable HRC hardware start */
|
||||
#define ICG1_HRC_HARDWARE_START (ICG_FUNCTION_ON)
|
||||
|
||||
/*!< HRC register config */
|
||||
#define ICG1_HRC_FREQSEL (HRC_FREQUENCY_16MHZ)
|
||||
#define ICG1_HRC_STOP (HRC_OSCILLATION_START)
|
||||
|
||||
/*!< HRC register config value */
|
||||
#if ICG1_HRC_HARDWARE_START == ICG_FUNCTION_ON
|
||||
#define ICG1_HRC_REG_CONFIG (ICG1_HRC_FREQSEL | ICG1_HRC_STOP)
|
||||
#else
|
||||
#define ICG1_HRC_REG_CONFIG ((uint16_t)0xFFFF)
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief VDU0 hardware start configuration
|
||||
******************************************************************************/
|
||||
/*!< Enable or disable VDU0 hardware start */
|
||||
#define ICG1_VDU0_HARDWARE_START (ICG_FUNCTION_OFF)
|
||||
|
||||
/*!< VDU0 register config */
|
||||
#define ICG1_VDU0_BOR_LEV (VDU0_VOLTAGE_THRESHOLD_2P3)
|
||||
#define ICG1_VDU0_BORDIS (VDU0_STOP_AFTER_RESET)
|
||||
|
||||
/*!< VDU0 register config value */
|
||||
#if ICG1_VDU0_HARDWARE_START == ICG_FUNCTION_ON
|
||||
#define ICG1_VDU0_REG_CONFIG (ICG1_VDU0_BOR_LEV | ICG1_VDU0_BORDIS)
|
||||
#else
|
||||
#define ICG1_VDU0_REG_CONFIG ((uint8_t)0xFF)
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief NMI hardware start configuration
|
||||
******************************************************************************/
|
||||
/*!< Enable or disable NMI hardware start */
|
||||
#define ICG1_NMI_HARDWARE_START (ICG_FUNCTION_OFF)
|
||||
|
||||
/*!< NMI register config */
|
||||
#define ICG1_NMI_SMPCLK (NMI_PIN_FILTER_PCLK3_DIV1)
|
||||
#define ICG1_NMI_TRG (NMI_PIN_TRIGGER_EDGE_RISING)
|
||||
#define ICG1_NMI_IMR (NMI_PIN_IRQ_DISABLE)
|
||||
#define ICG1_NMI_NFEN (NMI_DIGITAL_FILTER_DISABLE)
|
||||
#define ICG1_NMI_ICGENA (NMI_PIN_ICG_FUNCTION_DISABLE)
|
||||
|
||||
/*!< NMI register config value */
|
||||
#if ICG1_NMI_HARDWARE_START == ICG_FUNCTION_ON
|
||||
#define ICG1_NMI_REG_CONFIG (ICG1_NMI_SMPCLK | ICG1_NMI_TRG | \
|
||||
ICG1_NMI_IMR | ICG1_NMI_NFEN | ICG1_NMI_ICGENA)
|
||||
#else
|
||||
#define ICG1_NMI_REG_CONFIG ((uint8_t)0xFF)
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ICG registers configuration
|
||||
******************************************************************************/
|
||||
/*!< ICG0 register value */
|
||||
#define ICG0_REGISTER_CONSTANT (((uint32_t)ICG0_WDT_REG_CONFIG << 16) | \
|
||||
((uint32_t)ICG0_SWDT_REG_CONFIG) | \
|
||||
((uint32_t)0xE000E000ul))
|
||||
/*!< ICG1 register value */
|
||||
#define ICG1_REGISTER_CONSTANT (((uint32_t)ICG1_NMI_REG_CONFIG << 24) | \
|
||||
((uint32_t)ICG1_VDU0_REG_CONFIG << 16) | \
|
||||
((uint32_t)ICG1_HRC_REG_CONFIG) | \
|
||||
((uint32_t)0x03F8FEFEul))
|
||||
/*!< ICG2~7 register reserved value */
|
||||
#define ICG2_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul)
|
||||
#define ICG3_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul)
|
||||
#define ICG4_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul)
|
||||
#define ICG5_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul)
|
||||
#define ICG6_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul)
|
||||
#define ICG7_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
//@} // IcgGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_ICG_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_ICG_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,542 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_interrupts.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link InterruptGroup Interrupt description @endlink
|
||||
**
|
||||
** - 2018-10-12 CDT First version for Device Driver Library of interrupt.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_INTERRUPTS_H___
|
||||
#define __HC32F460_INTERRUPTS_H___
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_INTERRUPTS_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup InterruptGroup Interrupt
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief IRQ registration structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_irq_regi_conf
|
||||
{
|
||||
en_int_src_t enIntSrc;
|
||||
IRQn_Type enIRQn;
|
||||
func_ptr_t pfnCallback;
|
||||
}stc_irq_regi_conf_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief stop mode interrupt wakeup source enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_int_wkup_src
|
||||
{
|
||||
Extint0WU = 1u << 0,
|
||||
Extint1WU = 1u << 1,
|
||||
Extint2WU = 1u << 2,
|
||||
Extint3WU = 1u << 3,
|
||||
Extint4WU = 1u << 4,
|
||||
Extint5WU = 1u << 5,
|
||||
Extint6WU = 1u << 6,
|
||||
Extint7WU = 1u << 7,
|
||||
Extint8WU = 1u << 8,
|
||||
Extint9WU = 1u << 9,
|
||||
Extint10WU = 1u << 10,
|
||||
Extint11WU = 1u << 11,
|
||||
Extint12WU = 1u << 12,
|
||||
Extint13WU = 1u << 13,
|
||||
Extint14WU = 1u << 14,
|
||||
Extint15WU = 1u << 15,
|
||||
SwdtWU = 1u << 16,
|
||||
Vdu1WU = 1u << 17,
|
||||
Vdu2WU = 1u << 18,
|
||||
CmpWU = 1u << 19,
|
||||
WakeupTimerWU = 1u << 20,
|
||||
RtcAlarmWU = 1u << 21,
|
||||
RtcPeriodWU = 1u << 22,
|
||||
Timer0WU = 1u << 23,
|
||||
Usart1RxWU = 1u << 25,
|
||||
}en_int_wkup_src_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief event enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_evt
|
||||
{
|
||||
Event0 = 1u << 0,
|
||||
Event1 = 1u << 1,
|
||||
Event2 = 1u << 2,
|
||||
Event3 = 1u << 3,
|
||||
Event4 = 1u << 4,
|
||||
Event5 = 1u << 5,
|
||||
Event6 = 1u << 6,
|
||||
Event7 = 1u << 7,
|
||||
Event8 = 1u << 8,
|
||||
Event9 = 1u << 9,
|
||||
Event10 = 1u << 10,
|
||||
Event11 = 1u << 11,
|
||||
Event12 = 1u << 12,
|
||||
Event13 = 1u << 13,
|
||||
Event14 = 1u << 14,
|
||||
Event15 = 1u << 15,
|
||||
Event16 = 1u << 16,
|
||||
Event17 = 1u << 17,
|
||||
Event18 = 1u << 18,
|
||||
Event19 = 1u << 19,
|
||||
Event20 = 1u << 20,
|
||||
Event21 = 1u << 21,
|
||||
Event22 = 1u << 22,
|
||||
Event23 = 1u << 23,
|
||||
Event24 = 1u << 24,
|
||||
Event25 = 1u << 25,
|
||||
Event26 = 1u << 26,
|
||||
Event27 = 1u << 27,
|
||||
Event28 = 1u << 28,
|
||||
Event29 = 1u << 29,
|
||||
Event30 = 1u << 30,
|
||||
Event31 = 1u << 31,
|
||||
}en_evt_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief interrupt enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_int
|
||||
{
|
||||
Int0 = 1u << 0,
|
||||
Int1 = 1u << 1,
|
||||
Int2 = 1u << 2,
|
||||
Int3 = 1u << 3,
|
||||
Int4 = 1u << 4,
|
||||
Int5 = 1u << 5,
|
||||
Int6 = 1u << 6,
|
||||
Int7 = 1u << 7,
|
||||
Int8 = 1u << 8,
|
||||
Int9 = 1u << 9,
|
||||
Int10 = 1u << 10,
|
||||
Int11 = 1u << 11,
|
||||
Int12 = 1u << 12,
|
||||
Int13 = 1u << 13,
|
||||
Int14 = 1u << 14,
|
||||
Int15 = 1u << 15,
|
||||
Int16 = 1u << 16,
|
||||
Int17 = 1u << 17,
|
||||
Int18 = 1u << 18,
|
||||
Int19 = 1u << 19,
|
||||
Int20 = 1u << 20,
|
||||
Int21 = 1u << 21,
|
||||
Int22 = 1u << 22,
|
||||
Int23 = 1u << 23,
|
||||
Int24 = 1u << 24,
|
||||
Int25 = 1u << 25,
|
||||
Int26 = 1u << 26,
|
||||
Int27 = 1u << 27,
|
||||
Int28 = 1u << 28,
|
||||
Int29 = 1u << 29,
|
||||
Int30 = 1u << 30,
|
||||
Int31 = 1u << 31,
|
||||
}en_int_t;
|
||||
|
||||
|
||||
/*! Bit mask definition*/
|
||||
#define BIT_MASK_00 (1ul << 0)
|
||||
#define BIT_MASK_01 (1ul << 1)
|
||||
#define BIT_MASK_02 (1ul << 2)
|
||||
#define BIT_MASK_03 (1ul << 3)
|
||||
#define BIT_MASK_04 (1ul << 4)
|
||||
#define BIT_MASK_05 (1ul << 5)
|
||||
#define BIT_MASK_06 (1ul << 6)
|
||||
#define BIT_MASK_07 (1ul << 7)
|
||||
#define BIT_MASK_08 (1ul << 8)
|
||||
#define BIT_MASK_09 (1ul << 9)
|
||||
#define BIT_MASK_10 (1ul << 10)
|
||||
#define BIT_MASK_11 (1ul << 11)
|
||||
#define BIT_MASK_12 (1ul << 12)
|
||||
#define BIT_MASK_13 (1ul << 13)
|
||||
#define BIT_MASK_14 (1ul << 14)
|
||||
#define BIT_MASK_15 (1ul << 15)
|
||||
#define BIT_MASK_16 (1ul << 16)
|
||||
#define BIT_MASK_17 (1ul << 17)
|
||||
#define BIT_MASK_18 (1ul << 18)
|
||||
#define BIT_MASK_19 (1ul << 19)
|
||||
#define BIT_MASK_20 (1ul << 20)
|
||||
#define BIT_MASK_21 (1ul << 21)
|
||||
#define BIT_MASK_22 (1ul << 22)
|
||||
#define BIT_MASK_23 (1ul << 23)
|
||||
#define BIT_MASK_24 (1ul << 24)
|
||||
#define BIT_MASK_25 (1ul << 25)
|
||||
#define BIT_MASK_26 (1ul << 26)
|
||||
#define BIT_MASK_27 (1ul << 27)
|
||||
#define BIT_MASK_28 (1ul << 28)
|
||||
#define BIT_MASK_29 (1ul << 29)
|
||||
#define BIT_MASK_30 (1ul << 30)
|
||||
#define BIT_MASK_31 (1ul << 31)
|
||||
|
||||
/*! Default Priority for IRQ, Possible values are 0 (high priority) to 15 (low priority) */
|
||||
#define DDL_IRQ_PRIORITY_DEFAULT 15u
|
||||
|
||||
/*! Interrupt priority level 00 ~ 15*/
|
||||
#define DDL_IRQ_PRIORITY_00 (0u)
|
||||
#define DDL_IRQ_PRIORITY_01 (1u)
|
||||
#define DDL_IRQ_PRIORITY_02 (2u)
|
||||
#define DDL_IRQ_PRIORITY_03 (3u)
|
||||
#define DDL_IRQ_PRIORITY_04 (4u)
|
||||
#define DDL_IRQ_PRIORITY_05 (5u)
|
||||
#define DDL_IRQ_PRIORITY_06 (6u)
|
||||
#define DDL_IRQ_PRIORITY_07 (7u)
|
||||
#define DDL_IRQ_PRIORITY_08 (8u)
|
||||
#define DDL_IRQ_PRIORITY_09 (9u)
|
||||
#define DDL_IRQ_PRIORITY_10 (10u)
|
||||
#define DDL_IRQ_PRIORITY_11 (11u)
|
||||
#define DDL_IRQ_PRIORITY_12 (12u)
|
||||
#define DDL_IRQ_PRIORITY_13 (13u)
|
||||
#define DDL_IRQ_PRIORITY_14 (14u)
|
||||
#define DDL_IRQ_PRIORITY_15 (15u)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief AOS software trigger function
|
||||
**
|
||||
******************************************************************************/
|
||||
__STATIC_INLINE void AOS_SW_Trigger(void)
|
||||
{
|
||||
bM4_AOS_INT_SFTTRG_STRG = 1u;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief AOS common trigger source 1 config.
|
||||
**
|
||||
******************************************************************************/
|
||||
__STATIC_INLINE void AOS_COM_Trigger1(en_event_src_t enTrig)
|
||||
{
|
||||
M4_AOS->COMTRG1 = enTrig;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief AOS common trigger source 2 config.
|
||||
**
|
||||
******************************************************************************/
|
||||
__STATIC_INLINE void AOS_COM_Trigger2(en_event_src_t enTrig)
|
||||
{
|
||||
M4_AOS->COMTRG2 = enTrig;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
extern en_result_t enIrqRegistration(const stc_irq_regi_conf_t *pstcIrqRegiConf);
|
||||
extern en_result_t enIrqResign(IRQn_Type enIRQn);
|
||||
extern en_result_t enShareIrqEnable(en_int_src_t enIntSrc);
|
||||
extern en_result_t enShareIrqDisable(en_int_src_t enIntSrc);
|
||||
extern en_result_t enIntWakeupEnable(uint32_t u32WakeupSrc);
|
||||
extern en_result_t enIntWakeupDisable(uint32_t u32WakeupSrc);
|
||||
extern en_result_t enEventEnable(uint32_t u32Event);
|
||||
extern en_result_t enEventDisable(uint32_t u32Event);
|
||||
extern en_result_t enIntEnable(uint32_t u32Int);
|
||||
extern en_result_t enIntDisable(uint32_t u32Int);
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
__WEAKDEF void NMI_IrqHandler(void);
|
||||
__WEAKDEF void HardFault_IrqHandler(void);
|
||||
__WEAKDEF void MemManage_IrqHandler(void);
|
||||
__WEAKDEF void BusFault_IrqHandler(void);
|
||||
__WEAKDEF void UsageFault_IrqHandler(void);
|
||||
__WEAKDEF void SVC_IrqHandler(void);
|
||||
__WEAKDEF void DebugMon_IrqHandler(void);
|
||||
__WEAKDEF void PendSV_IrqHandler(void);
|
||||
__WEAKDEF void SysTick_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Extint00_IrqHandler(void);
|
||||
__WEAKDEF void Extint01_IrqHandler(void);
|
||||
__WEAKDEF void Extint02_IrqHandler(void);
|
||||
__WEAKDEF void Extint03_IrqHandler(void);
|
||||
__WEAKDEF void Extint04_IrqHandler(void);
|
||||
__WEAKDEF void Extint05_IrqHandler(void);
|
||||
__WEAKDEF void Extint06_IrqHandler(void);
|
||||
__WEAKDEF void Extint07_IrqHandler(void);
|
||||
__WEAKDEF void Extint08_IrqHandler(void);
|
||||
__WEAKDEF void Extint09_IrqHandler(void);
|
||||
__WEAKDEF void Extint10_IrqHandler(void);
|
||||
__WEAKDEF void Extint11_IrqHandler(void);
|
||||
__WEAKDEF void Extint12_IrqHandler(void);
|
||||
__WEAKDEF void Extint13_IrqHandler(void);
|
||||
__WEAKDEF void Extint14_IrqHandler(void);
|
||||
__WEAKDEF void Extint15_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Dma1Tc0_IrqHandler(void);
|
||||
__WEAKDEF void Dma1Tc1_IrqHandler(void);
|
||||
__WEAKDEF void Dma1Tc2_IrqHandler(void);
|
||||
__WEAKDEF void Dma1Tc3_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Tc0_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Tc1_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Tc2_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Tc3_IrqHandler(void);
|
||||
__WEAKDEF void Dma1Btc0_IrqHandler(void);
|
||||
__WEAKDEF void Dma1Btc1_IrqHandler(void);
|
||||
__WEAKDEF void Dma1Btc2_IrqHandler(void);
|
||||
__WEAKDEF void Dma1Btc3_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Btc0_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Btc1_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Btc2_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Btc3_IrqHandler(void);
|
||||
__WEAKDEF void Dma1Err0_IrqHandler(void);
|
||||
__WEAKDEF void Dma1Err1_IrqHandler(void);
|
||||
__WEAKDEF void Dma1Err2_IrqHandler(void);
|
||||
__WEAKDEF void Dma1Err3_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Err0_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Err1_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Err2_IrqHandler(void);
|
||||
__WEAKDEF void Dma2Err3_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void EfmPgmEraseErr_IrqHandler(void);
|
||||
__WEAKDEF void EfmColErr_IrqHandler(void);
|
||||
__WEAKDEF void EfmOpEnd_IrqHandler(void);
|
||||
__WEAKDEF void QspiInt_IrqHandler(void);
|
||||
__WEAKDEF void Dcu1_IrqHandler(void);
|
||||
__WEAKDEF void Dcu2_IrqHandler(void);
|
||||
__WEAKDEF void Dcu3_IrqHandler(void);
|
||||
__WEAKDEF void Dcu4_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Timer01GCMA_IrqHandler(void);
|
||||
__WEAKDEF void Timer01GCMB_IrqHandler(void);
|
||||
__WEAKDEF void Timer02GCMA_IrqHandler(void);
|
||||
__WEAKDEF void Timer02GCMB_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void MainOscStop_IrqHandler(void);
|
||||
__WEAKDEF void WakeupTimer_IrqHandler(void);
|
||||
__WEAKDEF void Swdt_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Timer61GCMA_IrqHandler(void);
|
||||
__WEAKDEF void Timer61GCMB_IrqHandler(void);
|
||||
__WEAKDEF void Timer61GCMC_IrqHandler(void);
|
||||
__WEAKDEF void Timer61GCMD_IrqHandler(void);
|
||||
__WEAKDEF void Timer61GCME_IrqHandler(void);
|
||||
__WEAKDEF void Timer61GCMF_IrqHandler(void);
|
||||
__WEAKDEF void Timer61GOV_IrqHandler(void);
|
||||
__WEAKDEF void Timer61GUD_IrqHandler(void);
|
||||
__WEAKDEF void Timer61GDT_IrqHandler(void);
|
||||
__WEAKDEF void Timer61SCMA_IrqHandler(void);
|
||||
__WEAKDEF void Timer61SCMB_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Timer62GCMA_IrqHandler(void);
|
||||
__WEAKDEF void Timer62GCMB_IrqHandler(void);
|
||||
__WEAKDEF void Timer62GCMC_IrqHandler(void);
|
||||
__WEAKDEF void Timer62GCMD_IrqHandler(void);
|
||||
__WEAKDEF void Timer62GCME_IrqHandler(void);
|
||||
__WEAKDEF void Timer62GCMF_IrqHandler(void);
|
||||
__WEAKDEF void Timer62GOV_IrqHandler(void);
|
||||
__WEAKDEF void Timer62GUD_IrqHandler(void);
|
||||
__WEAKDEF void Timer62GDT_IrqHandler(void);
|
||||
__WEAKDEF void Timer62SCMA_IrqHandler(void);
|
||||
__WEAKDEF void Timer62SCMB_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Timer63GCMA_IrqHandler(void);
|
||||
__WEAKDEF void Timer63GCMB_IrqHandler(void);
|
||||
__WEAKDEF void Timer63GCMC_IrqHandler(void);
|
||||
__WEAKDEF void Timer63GCMD_IrqHandler(void);
|
||||
__WEAKDEF void Timer63GCME_IrqHandler(void);
|
||||
__WEAKDEF void Timer63GCMF_IrqHandler(void);
|
||||
__WEAKDEF void Timer63GOV_IrqHandler(void);
|
||||
__WEAKDEF void Timer63GUD_IrqHandler(void);
|
||||
__WEAKDEF void Timer63GDT_IrqHandler(void);
|
||||
__WEAKDEF void Timer63SCMA_IrqHandler(void);
|
||||
__WEAKDEF void Timer63SCMB_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void TimerA1OV_IrqHandler(void);
|
||||
__WEAKDEF void TimerA1UD_IrqHandler(void);
|
||||
__WEAKDEF void TimerA1CMP_IrqHandler(void);
|
||||
__WEAKDEF void TimerA2OV_IrqHandler(void);
|
||||
__WEAKDEF void TimerA2UD_IrqHandler(void);
|
||||
__WEAKDEF void TimerA2CMP_IrqHandler(void);
|
||||
__WEAKDEF void TimerA3OV_IrqHandler(void);
|
||||
__WEAKDEF void TimerA3UD_IrqHandler(void);
|
||||
__WEAKDEF void TimerA3CMP_IrqHandler(void);
|
||||
__WEAKDEF void TimerA4OV_IrqHandler(void);
|
||||
__WEAKDEF void TimerA4UD_IrqHandler(void);
|
||||
__WEAKDEF void TimerA4CMP_IrqHandler(void);
|
||||
__WEAKDEF void TimerA5OV_IrqHandler(void);
|
||||
__WEAKDEF void TimerA5UD_IrqHandler(void);
|
||||
__WEAKDEF void TimerA5CMP_IrqHandler(void);
|
||||
__WEAKDEF void TimerA6OV_IrqHandler(void);
|
||||
__WEAKDEF void TimerA6UD_IrqHandler(void);
|
||||
__WEAKDEF void TimerA6CMP_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void UsbGlobal_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Usart1RxErr_IrqHandler(void);
|
||||
__WEAKDEF void Usart1RxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Usart1TxEmpty_IrqHandler(void);
|
||||
__WEAKDEF void Usart1TxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Usart1RxTO_IrqHandler(void);
|
||||
__WEAKDEF void Usart2RxErr_IrqHandler(void);
|
||||
__WEAKDEF void Usart2RxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Usart2TxEmpty_IrqHandler(void);
|
||||
__WEAKDEF void Usart2TxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Usart2RxTO_IrqHandler(void);
|
||||
__WEAKDEF void Usart3RxErr_IrqHandler(void);
|
||||
__WEAKDEF void Usart3RxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Usart3TxEmpty_IrqHandler(void);
|
||||
__WEAKDEF void Usart3TxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Usart3RxTO_IrqHandler(void);
|
||||
__WEAKDEF void Usart4RxErr_IrqHandler(void);
|
||||
__WEAKDEF void Usart4RxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Usart4TxEmpty_IrqHandler(void);
|
||||
__WEAKDEF void Usart4TxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Usart4RxTO_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Spi1RxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Spi1TxEmpty_IrqHandler(void);
|
||||
__WEAKDEF void Spi1Err_IrqHandler(void);
|
||||
__WEAKDEF void Spi1Idle_IrqHandler(void);
|
||||
__WEAKDEF void Spi2RxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Spi2TxEmpty_IrqHandler(void);
|
||||
__WEAKDEF void Spi2Err_IrqHandler(void);
|
||||
__WEAKDEF void Spi2Idle_IrqHandler(void);
|
||||
__WEAKDEF void Spi3RxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Spi3TxEmpty_IrqHandler(void);
|
||||
__WEAKDEF void Spi3Err_IrqHandler(void);
|
||||
__WEAKDEF void Spi3Idle_IrqHandler(void);
|
||||
__WEAKDEF void Spi4RxEnd_IrqHandler(void);
|
||||
__WEAKDEF void Spi4TxEmpty_IrqHandler(void);
|
||||
__WEAKDEF void Spi4Err_IrqHandler(void);
|
||||
__WEAKDEF void Spi4Idle_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Timer41GCMUH_IrqHandler(void);
|
||||
__WEAKDEF void Timer41GCMUL_IrqHandler(void);
|
||||
__WEAKDEF void Timer41GCMVH_IrqHandler(void);
|
||||
__WEAKDEF void Timer41GCMVL_IrqHandler(void);
|
||||
__WEAKDEF void Timer41GCMWH_IrqHandler(void);
|
||||
__WEAKDEF void Timer41GCMWL_IrqHandler(void);
|
||||
__WEAKDEF void Timer41GOV_IrqHandler(void);
|
||||
__WEAKDEF void Timer41GUD_IrqHandler(void);
|
||||
__WEAKDEF void Timer41ReloadU_IrqHandler(void);
|
||||
__WEAKDEF void Timer41ReloadV_IrqHandler(void);
|
||||
__WEAKDEF void Timer41ReloadW_IrqHandler(void);
|
||||
__WEAKDEF void Timer42GCMUH_IrqHandler(void);
|
||||
__WEAKDEF void Timer42GCMUL_IrqHandler(void);
|
||||
__WEAKDEF void Timer42GCMVH_IrqHandler(void);
|
||||
__WEAKDEF void Timer42GCMVL_IrqHandler(void);
|
||||
__WEAKDEF void Timer42GCMWH_IrqHandler(void);
|
||||
__WEAKDEF void Timer42GCMWL_IrqHandler(void);
|
||||
__WEAKDEF void Timer42GOV_IrqHandler(void);
|
||||
__WEAKDEF void Timer42GUD_IrqHandler(void);
|
||||
__WEAKDEF void Timer42ReloadU_IrqHandler(void);
|
||||
__WEAKDEF void Timer42ReloadV_IrqHandler(void);
|
||||
__WEAKDEF void Timer42ReloadW_IrqHandler(void);
|
||||
__WEAKDEF void Timer43GCMUH_IrqHandler(void);
|
||||
__WEAKDEF void Timer43GCMUL_IrqHandler(void);
|
||||
__WEAKDEF void Timer43GCMVH_IrqHandler(void);
|
||||
__WEAKDEF void Timer43GCMVL_IrqHandler(void);
|
||||
__WEAKDEF void Timer43GCMWH_IrqHandler(void);
|
||||
__WEAKDEF void Timer43GCMWL_IrqHandler(void);
|
||||
__WEAKDEF void Timer43GOV_IrqHandler(void);
|
||||
__WEAKDEF void Timer43GUD_IrqHandler(void);
|
||||
__WEAKDEF void Timer43ReloadU_IrqHandler(void);
|
||||
__WEAKDEF void Timer43ReloadV_IrqHandler(void);
|
||||
__WEAKDEF void Timer43ReloadW_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Emb1_IrqHandler(void);
|
||||
__WEAKDEF void Emb2_IrqHandler(void);
|
||||
__WEAKDEF void Emb3_IrqHandler(void);
|
||||
__WEAKDEF void Emb4_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void I2s1Tx_IrqHandler(void);
|
||||
__WEAKDEF void I2s1Rx_IrqHandler(void);
|
||||
__WEAKDEF void I2s1Err_IrqHandler(void);
|
||||
__WEAKDEF void I2s2Tx_IrqHandler(void);
|
||||
__WEAKDEF void I2s2Rx_IrqHandler(void);
|
||||
__WEAKDEF void I2s2Err_IrqHandler(void);
|
||||
__WEAKDEF void I2s3Tx_IrqHandler(void);
|
||||
__WEAKDEF void I2s3Rx_IrqHandler(void);
|
||||
__WEAKDEF void I2s3Err_IrqHandler(void);
|
||||
__WEAKDEF void I2s4Tx_IrqHandler(void);
|
||||
__WEAKDEF void I2s4Rx_IrqHandler(void);
|
||||
__WEAKDEF void I2s4Err_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void I2c1RxEnd_IrqHandler(void);
|
||||
__WEAKDEF void I2c1TxEnd_IrqHandler(void);
|
||||
__WEAKDEF void I2c1TxEmpty_IrqHandler(void);
|
||||
__WEAKDEF void I2c1Err_IrqHandler(void);
|
||||
__WEAKDEF void I2c2RxEnd_IrqHandler(void);
|
||||
__WEAKDEF void I2c2TxEnd_IrqHandler(void);
|
||||
__WEAKDEF void I2c2TxEmpty_IrqHandler(void);
|
||||
__WEAKDEF void I2c2Err_IrqHandler(void);
|
||||
__WEAKDEF void I2c3RxEnd_IrqHandler(void);
|
||||
__WEAKDEF void I2c3TxEnd_IrqHandler(void);
|
||||
__WEAKDEF void I2c3TxEmpty_IrqHandler(void);
|
||||
__WEAKDEF void I2c3Err_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Pvd1_IrqHandler(void);
|
||||
__WEAKDEF void Pvd2_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void FcmErr_IrqHandler(void);
|
||||
__WEAKDEF void FcmEnd_IrqHandler(void);
|
||||
__WEAKDEF void FcmOV_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Wdt_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void ADC1A_IrqHandler(void);
|
||||
__WEAKDEF void ADC1B_IrqHandler(void);
|
||||
__WEAKDEF void ADC1ChCmp_IrqHandler(void);
|
||||
__WEAKDEF void ADC1SeqCmp_IrqHandler(void);
|
||||
__WEAKDEF void ADC2A_IrqHandler(void);
|
||||
__WEAKDEF void ADC2B_IrqHandler(void);
|
||||
__WEAKDEF void ADC2ChCmp_IrqHandler(void);
|
||||
__WEAKDEF void ADC2SeqCmp_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Sdio1_IrqHandler(void);
|
||||
__WEAKDEF void Sdio2_IrqHandler(void);
|
||||
|
||||
__WEAKDEF void Can_IrqHandler(void);
|
||||
|
||||
//@} // InterruptGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_INTERRUPTS_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_INTERRUPTS_H___ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,191 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_keyscan.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link KeyscanGroup Keyscan description @endlink
|
||||
**
|
||||
** - 2018-10-17 CDT First version for Device Driver Library of keyscan.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HC32F460_KEYSCAN_H__
|
||||
#define __HC32F460_KEYSCAN_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_KEYSCAN_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
* \defgroup KeyscanGroup Matrix Key Scan Module (KeyScan)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to hi-z state cycles of each keyout
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_hiz_cycle
|
||||
{
|
||||
Hiz4 = 0u,
|
||||
Hiz8 = 1u,
|
||||
Hiz16 = 2u,
|
||||
Hiz32 = 3u,
|
||||
Hiz64 = 4u,
|
||||
Hiz256 = 5u,
|
||||
Hiz512 = 6u,
|
||||
Hiz1K = 7u,
|
||||
}en_hiz_cycle_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to low state cycles of each keyout
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_low_cycle
|
||||
{
|
||||
Low8 = 3u,
|
||||
Low16 = 4u,
|
||||
Low32 = 5u,
|
||||
Low64 = 6u,
|
||||
Low128 = 7u,
|
||||
Low256 = 8u,
|
||||
Low512 = 9u,
|
||||
Low1K = 10u,
|
||||
Low2K = 11u,
|
||||
Low4K = 12u,
|
||||
Low8K = 13u,
|
||||
Low16K = 14u,
|
||||
Low32K = 15u,
|
||||
Low64K = 16u,
|
||||
Low128K = 17u,
|
||||
Low256K = 18u,
|
||||
Low512K = 19u,
|
||||
Low1M = 20u,
|
||||
Low2M = 21u,
|
||||
Low4M = 22u,
|
||||
Low8M = 23u,
|
||||
Low16M = 24u,
|
||||
}en_low_cycle_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to key scan clock
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_keyscan_clk
|
||||
{
|
||||
KeyscanHclk = 0u, ///< use HCLK as scan clock
|
||||
KeyscanLrc = 1u, ///< use internal Low RC as scan clock
|
||||
KeyscanXtal32 = 2u, ///< use external XTAL32 as scan clock
|
||||
}en_keyscan_clk_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to KEYOUT combination
|
||||
******************************************************************************/
|
||||
typedef enum en_keyout_sel
|
||||
{
|
||||
Keyout0To1 = 1u, ///< KEYOUT 0 to 1 are selected
|
||||
Keyout0To2 = 2u, ///< KEYOUT 0 to 2 are selected
|
||||
Keyout0To3 = 3u, ///< KEYOUT 0 to 3 are selected
|
||||
Keyout0To4 = 4u, ///< KEYOUT 0 to 4 are selected
|
||||
Keyout0To5 = 5u, ///< KEYOUT 0 to 5 are selected
|
||||
Keyout0To6 = 6u, ///< KEYOUT 0 to 6 are selected
|
||||
Keyout0To7 = 7u, ///< KEYOUT 0 to 7 are selected
|
||||
}en_keyout_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to KEYIN combination
|
||||
******************************************************************************/
|
||||
typedef enum en_keyin_sel
|
||||
{
|
||||
Keyin00 = 1u << 0, ///< KEYIN 0 is selected
|
||||
Keyin01 = 1u << 1, ///< KEYIN 1 is selected
|
||||
Keyin02 = 1u << 2, ///< KEYIN 2 is selected
|
||||
Keyin03 = 1u << 3, ///< KEYIN 3 is selected
|
||||
Keyin04 = 1u << 4, ///< KEYIN 4 is selected
|
||||
Keyin05 = 1u << 5, ///< KEYIN 5 is selected
|
||||
Keyin06 = 1u << 6, ///< KEYIN 6 is selected
|
||||
Keyin07 = 1u << 7, ///< KEYIN 7 is selected
|
||||
Keyin08 = 1u << 8, ///< KEYIN 8 is selected
|
||||
Keyin09 = 1u << 9, ///< KEYIN 9 is selected
|
||||
Keyin10 = 1u << 10, ///< KEYIN 10 is selected
|
||||
Keyin11 = 1u << 11, ///< KEYIN 11 is selected
|
||||
Keyin12 = 1u << 12, ///< KEYIN 12 is selected
|
||||
Keyin13 = 1u << 13, ///< KEYIN 13 is selected
|
||||
Keyin14 = 1u << 14, ///< KEYIN 14 is selected
|
||||
Keyin15 = 1u << 15, ///< KEYIN 15 is selected
|
||||
}en_keyin_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Keyscan configuration
|
||||
**
|
||||
** \note The Keyscan configuration structure
|
||||
******************************************************************************/
|
||||
typedef struct stc_keyscan_config
|
||||
{
|
||||
en_hiz_cycle_t enHizCycle; ///< KEYOUT Hiz state cycles, ref @ en_hiz_cycle_t for details
|
||||
en_low_cycle_t enLowCycle; ///< KEYOUT Low state cycles, ref @ en_low_cycle_t for details
|
||||
en_keyscan_clk_t enKeyscanClk; ///< Key scan clock, ref @ en_keyscan_clk_t for details
|
||||
en_keyout_sel_t enKeyoutSel; ///< KEYOUT selection, ref @ en_keyout_sel_t for details
|
||||
uint16_t u16KeyinSel; ///< KEYIN selection, ref @ en_keyin_sel_t for details
|
||||
}stc_keyscan_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
extern en_result_t KEYSCAN_Init(const stc_keyscan_config_t *pstcKeyscanConfig);
|
||||
extern en_result_t KEYSCAN_DeInit(void);
|
||||
extern en_result_t KEYSCAN_Start(void);
|
||||
extern en_result_t KEYSCAN_Stop(void);
|
||||
extern uint8_t KEYSCAN_GetColIdx(void);
|
||||
|
||||
//@} // KeyscanGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_KEYSCAN_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_KEYSCAN_H__ */
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,293 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_mpu.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link MpuGroup MPU description @endlink
|
||||
**
|
||||
** - 2018-10-20 CDT First version for Device Driver Library of MPU.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_MPU_H__
|
||||
#define __HC32F460_MPU_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_MPU_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup MpuGroup Memory Protection Unit(MPU)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief MPU region number enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_mpu_region_num
|
||||
{
|
||||
MpuRegionNum0 = 0u, ///< MPU region number 0
|
||||
MpuRegionNum1 = 1u, ///< MPU region number 1
|
||||
MpuRegionNum2 = 2u, ///< MPU region number 2
|
||||
MpuRegionNum3 = 3u, ///< MPU region number 3
|
||||
MpuRegionNum4 = 4u, ///< MPU region number 4
|
||||
MpuRegionNum5 = 5u, ///< MPU region number 5
|
||||
MpuRegionNum6 = 6u, ///< MPU region number 6
|
||||
MpuRegionNum7 = 7u, ///< MPU region number 7
|
||||
MpuRegionNum8 = 8u, ///< MPU region number 8
|
||||
MpuRegionNum9 = 9u, ///< MPU region number 9
|
||||
MpuRegionNum10 = 10u, ///< MPU region number 10
|
||||
MpuRegionNum11 = 11u, ///< MPU region number 11
|
||||
MpuRegionNum12 = 12u, ///< MPU region number 12
|
||||
MpuRegionNum13 = 13u, ///< MPU region number 13
|
||||
MpuRegionNum14 = 14u, ///< MPU region number 14
|
||||
MpuRegionNum15 = 15u, ///< MPU region number 15
|
||||
} en_mpu_region_num_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief MPU region size enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_mpu_region_size
|
||||
{
|
||||
MpuRegionSize32Byte = 4u, ///< 32 Byte
|
||||
MpuRegionSize64Byte = 5u, ///< 64 Byte
|
||||
MpuRegionSize128Byte = 6u, ///< 126 Byte
|
||||
MpuRegionSize256Byte = 7u, ///< 256 Byte
|
||||
MpuRegionSize512Byte = 8u, ///< 512 Byte
|
||||
MpuRegionSize1KByte = 9u, ///< 1K Byte
|
||||
MpuRegionSize2KByte = 10u, ///< 2K Byte
|
||||
MpuRegionSize4KByte = 11u, ///< 4K Byte
|
||||
MpuRegionSize8KByte = 12u, ///< 8K Byte
|
||||
MpuRegionSize16KByte = 13u, ///< 16K Byte
|
||||
MpuRegionSize32KByte = 14u, ///< 32K Byte
|
||||
MpuRegionSize64KByte = 15u, ///< 64K Byte
|
||||
MpuRegionSize128KByte = 16u, ///< 128K Byte
|
||||
MpuRegionSize256KByte = 17u, ///< 256K Byte
|
||||
MpuRegionSize512KByte = 18u, ///< 512K Byte
|
||||
MpuRegionSize1MByte = 19u, ///< 1M Byte
|
||||
MpuRegionSize2MByte = 20u, ///< 2M Byte
|
||||
MpuRegionSize4MByte = 21u, ///< 4M Byte
|
||||
MpuRegionSize8MByte = 22u, ///< 8M Byte
|
||||
MpuRegionSize16MByte = 23u, ///< 16M Byte
|
||||
MpuRegionSize32MByte = 24u, ///< 32M Byte
|
||||
MpuRegionSize64MByte = 25u, ///< 64M Byte
|
||||
MpuRegionSize128MByte = 26u, ///< 128M Byte
|
||||
MpuRegionSize256MByte = 27u, ///< 256M Byte
|
||||
MpuRegionSize512MByte = 28u, ///< 512M Byte
|
||||
MpuRegionSize1GByte = 29u, ///< 1G Byte
|
||||
MpuRegionSize2GByte = 30u, ///< 2G Byte
|
||||
MpuRegionSize4GByte = 31u, ///< 4G Byte
|
||||
} en_mpu_region_size_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief MPU region enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_mpu_region_type
|
||||
{
|
||||
SMPU1Region = 0u, ///< System DMA_1 MPU
|
||||
SMPU2Region = 1u, ///< System DMA_2 MPU
|
||||
FMPURegion = 2u, ///< System USBFS_DMA MPU
|
||||
} en_mpu_region_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief MPU action selection enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_mpu_action_sel
|
||||
{
|
||||
MpuNoneAction = 0u, ///< MPU don't action.
|
||||
MpuTrigBusError = 1u, ///< MPU trigger bus error
|
||||
MpuTrigNmi = 2u, ///< MPU trigger bus NMI interrupt
|
||||
MpuTrigReset = 3u, ///< MPU trigger reset
|
||||
} en_mpu_action_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief MPU IP protection mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_mpu_ip_prot_mode
|
||||
{
|
||||
AesReadProt = (1ul << 0), ///< AES read protection
|
||||
AesWriteProt = (1ul << 1), ///< AES write protection
|
||||
HashReadProt = (1ul << 2), ///< HASH read protection
|
||||
HashWriteProt = (1ul << 3), ///< HASH write protection
|
||||
TrngReadProt = (1ul << 4), ///< TRNG read protection
|
||||
TrngWriteProt = (1ul << 5), ///< TRNG write protection
|
||||
CrcReadProt = (1ul << 6), ///< CRC read protection
|
||||
CrcWriteProt = (1ul << 7), ///< CRC write protection
|
||||
FmcReadProt = (1ul << 8), ///< FMC read protection
|
||||
FmcWriteProt = (1ul << 9), ///< FMC write protection
|
||||
WdtReadProt = (1ul << 12), ///< WDT read protection
|
||||
WdtWriteProt = (1ul << 13), ///< WDT write protection
|
||||
SwdtReadProt = (1ul << 14), ///< WDT read protection
|
||||
SwdtWriteProt = (1ul << 15), ///< WDT write protection
|
||||
BksramReadProt = (1ul << 16), ///< BKSRAM read protection
|
||||
BksramWriteProt = (1ul << 17), ///< BKSRAM write protection
|
||||
RtcReadProt = (1ul << 18), ///< RTC read protection
|
||||
RtcWriteProt = (1ul << 19), ///< RTC write protection
|
||||
DmpuReadProt = (1ul << 20), ///< DMPU read protection
|
||||
DmpuWriteProt = (1ul << 21), ///< DMPU write protection
|
||||
SramcReadProt = (1ul << 22), ///< SRAMC read protection
|
||||
SramcWriteProt = (1ul << 23), ///< SRAMC write protection
|
||||
IntcReadProt = (1ul << 24), ///< INTC read protection
|
||||
IntcWriteProt = (1ul << 25), ///< INTC write protection
|
||||
SyscReadProt = (1ul << 26), ///< SYSC read protection
|
||||
SyscWriteProt = (1ul << 27), ///< SYSC write protection
|
||||
MstpReadProt = (1ul << 28), ///< MSTP read protection
|
||||
MstpWriteProt = (1ul << 29), ///< MSTP write protection
|
||||
BusErrProt = (1ul << 31), ///< BUSERR write protection
|
||||
} en_mpu_ip_prot_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief MPU protection region permission
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_mpu_prot_region_permission
|
||||
{
|
||||
en_mpu_action_sel_t enAction; ///< Specifies MPU action
|
||||
|
||||
en_functional_state_t enRegionEnable; ///< Disable: Disable region protection; Enable:Enable region protection
|
||||
|
||||
en_functional_state_t enWriteEnable; ///< Disable: Prohibited to write; Enable:permitted to write
|
||||
|
||||
en_functional_state_t enReadEnable; ///< Disable: Prohibited to read; Enable:permitted to read
|
||||
|
||||
} stc_mpu_prot_region_permission_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief MPU background region permission
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_mpu_bkgd_region_permission
|
||||
{
|
||||
en_functional_state_t enWriteEnable; ///< Disable: Prohibited to write; Enable:permitted to write
|
||||
|
||||
en_functional_state_t enReadEnable; ///< Disable: Prohibited to read; Enable:permitted to read
|
||||
} stc_mpu_bkgd_region_permission_t_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief MPU background region initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_mpu_bkgd_region_init
|
||||
{
|
||||
stc_mpu_bkgd_region_permission_t_t stcSMPU1BkgdPermission; ///< Specifies SMPU1 background permission and this stuctrue detail refer of @ref stc_mpu_bkgd_region_permission_t_t
|
||||
|
||||
stc_mpu_bkgd_region_permission_t_t stcSMPU2BkgdPermission; ///< Specifies SMPU2 background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t
|
||||
|
||||
stc_mpu_bkgd_region_permission_t_t stcFMPUBkgdPermission; ///< Specifies FMPU background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t
|
||||
} stc_mpu_bkgd_region_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief MPU protect region initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_mpu_prot_region_init
|
||||
{
|
||||
uint32_t u32RegionBaseAddress; ///< Specifies region base address
|
||||
|
||||
en_mpu_region_size_t enRegionSize; ///< Specifies region size and This parameter can be a value of @ref en_mpu_region_size_t
|
||||
|
||||
stc_mpu_prot_region_permission_t stcSMPU1Permission; ///< Specifies DMA1 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t
|
||||
|
||||
stc_mpu_prot_region_permission_t stcSMPU2Permission; ///< Specifies DMA2 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t
|
||||
|
||||
stc_mpu_prot_region_permission_t stcFMPUPermission; ///< Specifies USBFS-DMA MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t
|
||||
} stc_mpu_prot_region_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t MPU_ProtRegionInit(en_mpu_region_num_t enRegionNum,
|
||||
const stc_mpu_prot_region_init_t *pstcInitCfg);
|
||||
en_result_t MPU_BkgdRegionInit(const stc_mpu_bkgd_region_init_t *pstcInitCfg);
|
||||
en_result_t MPU_SetRegionSize(en_mpu_region_num_t enRegionNum,
|
||||
en_mpu_region_size_t enRegionSize);
|
||||
en_mpu_region_size_t MPU_GetRegionSize(en_mpu_region_num_t enRegionNum);
|
||||
en_result_t MPU_SetRegionBaseAddress(en_mpu_region_num_t enRegionNum,
|
||||
uint32_t u32RegionBaseAddr);
|
||||
uint32_t MPU_GetRegionBaseAddress(en_mpu_region_num_t enRegionNum);
|
||||
en_result_t MPU_SetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType,
|
||||
en_mpu_action_sel_t enActionSel);
|
||||
en_mpu_action_sel_t MPU_GetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType);
|
||||
en_result_t MPU_ProtRegionCmd(en_mpu_region_num_t enRegionNum,
|
||||
en_mpu_region_type_t enMpuRegionType,
|
||||
en_functional_state_t enState);
|
||||
en_result_t MPU_RegionTypeCmd(en_mpu_region_type_t enMpuRegionType,
|
||||
en_functional_state_t enState);
|
||||
en_flag_status_t MPU_GetStatus(en_mpu_region_type_t enMpuRegionType);
|
||||
en_result_t MPU_ClearStatus(en_mpu_region_type_t enMpuRegionType);
|
||||
en_result_t MPU_SetProtRegionReadPermission(en_mpu_region_num_t enRegionNum,
|
||||
en_mpu_region_type_t enMpuRegionType,
|
||||
en_functional_state_t enState);
|
||||
en_functional_state_t MPU_GetProtRegionReadPermission(en_mpu_region_num_t enRegionNum,
|
||||
en_mpu_region_type_t enMpuRegionType);
|
||||
en_result_t MPU_SetProtRegionWritePermission(en_mpu_region_num_t enRegionNum,
|
||||
en_mpu_region_type_t enMpuRegionType,
|
||||
en_functional_state_t enState);
|
||||
en_functional_state_t MPU_GetProtRegionWritePermission(en_mpu_region_num_t enRegionNum,
|
||||
en_mpu_region_type_t enMpuRegionType);
|
||||
en_result_t MPU_SetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType,
|
||||
en_functional_state_t enState);
|
||||
en_functional_state_t MPU_GetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType);
|
||||
en_result_t MPU_SetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType,
|
||||
en_functional_state_t enState);
|
||||
en_functional_state_t MPU_GetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType);
|
||||
en_result_t MPU_WriteProtCmd(en_functional_state_t enState);
|
||||
en_result_t MPU_IpProtCmd(uint32_t u32ProtMode,
|
||||
en_functional_state_t enState);
|
||||
|
||||
//@} // MpuGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_MPU_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_MPU_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,139 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_ots.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link OtsGroup Ots description @endlink
|
||||
**
|
||||
** - 2018-10-26 CDT First version for Device Driver Library of Ots.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_OTS_H__
|
||||
#define __HC32F460_OTS_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_OTS_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup OtsGroup On-chip Temperature Sensor(OTS)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/* Automatically turn off the analog temperature sensor after the temperature
|
||||
measurement is over. */
|
||||
typedef enum en_ots_auto_off
|
||||
{
|
||||
OtsAutoOff_Disable = 0x0, ///< Disable automatically turn off OTS.
|
||||
OtsAutoOff_Enable = 0x1, ///< Enable automatically turn off OTS.
|
||||
} en_ots_auto_off_t;
|
||||
|
||||
/* Temperature measurement end interrupt request. */
|
||||
typedef enum en_ots_ie
|
||||
{
|
||||
OtsInt_Disable = 0x0, ///< Disable OTS interrupt.
|
||||
OtsInt_Enable = 0x1, ///< Enable OTS interrupt.
|
||||
} en_ots_ie_t;
|
||||
|
||||
/* OTS clock selection. */
|
||||
typedef enum en_ots_clk_sel
|
||||
{
|
||||
OtsClkSel_Xtal = 0x0, ///< Select XTAL as OTS clock.
|
||||
OtsClkSel_Hrc = 0x1, ///< Select HRC as OTS clock.
|
||||
} en_ots_clk_sel_t;
|
||||
|
||||
/* OTS OTS initialization structure definition. */
|
||||
typedef struct stc_ots_init
|
||||
{
|
||||
en_ots_auto_off_t enAutoOff; ///< @ref en_ots_auto_off_t.
|
||||
en_ots_clk_sel_t enClkSel; ///< @ref en_ots_clk_sel_t.
|
||||
float32_t f32SlopeK; ///< K: Temperature slope (calculated by calibration experiment). */
|
||||
float32_t f32OffsetM; ///< M: Temperature offset (calculated by calibration experiment). */
|
||||
} stc_ots_init_t;
|
||||
|
||||
/* OTS common trigger source select */
|
||||
typedef enum en_ots_com_trigger
|
||||
{
|
||||
OtsComTrigger_1 = 0x1, ///< Select common trigger 1.
|
||||
OtsComTrigger_2 = 0x2, ///< Select common trigger 2.
|
||||
OtsComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2.
|
||||
} en_ots_com_trigger_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Start OTS.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void OTS_Start(void)
|
||||
{
|
||||
bM4_OTS_CTL_OTSST = (uint32_t)1u;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop OTS.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void OTS_Stop(void)
|
||||
{
|
||||
bM4_OTS_CTL_OTSST = (uint32_t)0u;
|
||||
}
|
||||
|
||||
en_result_t OTS_Init(const stc_ots_init_t *pstcInit);
|
||||
void OTS_DeInit(void);
|
||||
|
||||
en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout);
|
||||
|
||||
void OTS_IntCmd(en_functional_state_t enNewState);
|
||||
void OTS_SetTriggerSrc(en_event_src_t enEvent);
|
||||
void OTS_ComTriggerCmd(en_ots_com_trigger_t enComTrigger, en_functional_state_t enState);
|
||||
|
||||
en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \
|
||||
uint16_t *pu16Ecr, float32_t *pf32A, \
|
||||
uint32_t u32Timeout);
|
||||
|
||||
float OTS_CalculateTemp(void);
|
||||
|
||||
//@} // OtsGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_OTS_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_OTS_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,567 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_pwc.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link PwcGroup PWC description @endlink
|
||||
**
|
||||
** - 2018-10-28 CDT First version for Device Driver Library of PWC.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_PWC_H__
|
||||
#define __HC32F460_PWC_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_PWC_ENABLE == DDL_ON)
|
||||
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup PwcGroup Power Control(PWC)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The power down mode.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_powerdown_md
|
||||
{
|
||||
PowerDownMd1 = 0u, ///< Power down mode 1.
|
||||
PowerDownMd2 = 1u, ///< Power down mode 2.
|
||||
PowerDownMd3 = 2u, ///< Power down mode 3.
|
||||
PowerDownMd4 = 3u, ///< Power down mode 4.
|
||||
}en_pwc_powerdown_md_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The IO retain status under power down mode.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_iortn
|
||||
{
|
||||
IoPwrDownRetain = 0u, ///< Io keep under power down mode.
|
||||
IoPwrRstRetain = 1u, ///< Io keep after power reset.
|
||||
IoHighImp = 2u, ///< IO high impedance either power down or power reset.
|
||||
}en_pwc_iortn_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The driver ability while different speed mode enter stop mode.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_stopdas
|
||||
{
|
||||
StopHighspeed = 0u, ///< The driver ability while high speed mode enter stop mode.
|
||||
StopUlowspeed = 3u, ///< The driver ability while ultra_low speed mode enter stop mode.
|
||||
}en_pwc_stopdas_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The dynamic power driver voltage select.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_rundrvs
|
||||
{
|
||||
RunUHighspeed = 0u, ///< The ultra_high speed.
|
||||
RunUlowspeed = 2u, ///< The ultra_low speed.
|
||||
RunHighspeed = 3u, ///< The high speed.
|
||||
}en_pwc_rundrvs_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The dynamic power driver ability scaling.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_drvability_sca
|
||||
{
|
||||
Ulowspeed = 8u, ///< The ultra_low speed.
|
||||
HighSpeed = 15u, ///< The high speed.
|
||||
}en_pwc_drvability_sca_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The power down wake up time select.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_waketime_sel
|
||||
{
|
||||
Vcap01 = 0u, ///< Wake up while vcap capacitance 2*0.1uf.
|
||||
Vcap0047 = 1u, ///< Wake up while vcap capacitance 2*0.047uf.
|
||||
}en_pwc_waketime_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The wait or not wait flash stable while stop mode awake.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_stop_flash_sel
|
||||
{
|
||||
Wait = 0u, ///< wait flash stable.
|
||||
NotWait = 1u, ///< Not Wait flash stable.
|
||||
}en_pwc_stop_flash_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The clk value while stop mode awake.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_stop_clk_sel
|
||||
{
|
||||
ClkFix = 0u, ///< clock fix.
|
||||
ClkMrc = 1u, ///< clock source is MRC, only ram code.
|
||||
}en_pwc_stop_clk_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The power down wake up event edge select.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_edge_sel
|
||||
{
|
||||
EdgeFalling = 0u, ///< Falling edge.
|
||||
EdgeRising = 1u, ///< Rising edge.
|
||||
}en_pwc_edge_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The voltage detect edge select.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_pvdedge_sel
|
||||
{
|
||||
OverVcc = 0u, ///< PVD > VCC.
|
||||
BelowVcc = 1u, ///< PVD < VCC.
|
||||
}en_pwc_pvdedge_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The flag of wake_up timer compare result.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_wkover_flag
|
||||
{
|
||||
UnEqual = 0u, ///< Timer value unequal with the wake_up compare value whitch set.
|
||||
Equal = 1u, ///< Timer value equal with the wake_up compare value whitch set..
|
||||
}en_pwc_wkover_flag_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The RAM operating mode.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_ram_op_md
|
||||
{
|
||||
HighSpeedMd = 0x8043, ///< Work at high speed.
|
||||
UlowSpeedMd = 0x9062, ///< Work at ultra low speed.
|
||||
}en_pwc_ram_op_md_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The wake up clock select.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_wkclk_sel
|
||||
{
|
||||
Wk64hz = 0u, ///< 64Hz.
|
||||
WkXtal32 = 1u, ///< Xtal32.
|
||||
WkLrc = 2u, ///< Lrc.
|
||||
}en_pwc_wkclk_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The pvd digital filtering sampling clock select.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_pvdfiltclk_sel
|
||||
{
|
||||
PvdLrc025 = 0u, ///< 0.25 LRC cycle.
|
||||
PvdLrc05 = 1u, ///< 0.5 LRC cycle.
|
||||
PvdLrc1 = 2u, ///< LRC 1 div.
|
||||
PvdLrc2 = 3u, ///< LRC 2 div.
|
||||
}en_pwc_pvdfiltclk_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The pvd2 level select.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_pvd2level_sel
|
||||
{
|
||||
Pvd2Level0 = 0u, ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode.
|
||||
Pvd2Level1 = 1u, ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode.
|
||||
Pvd2Level2 = 2u, ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode.
|
||||
Pvd2Level3 = 3u, ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode.
|
||||
Pvd2Level4 = 4u, ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode.
|
||||
Pvd2Level5 = 5u, ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode.
|
||||
Pvd2Level6 = 6u, ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode.
|
||||
Pvd2Level7 = 7u, ///< 1.1V.while high_speed & ultra_low speed mode, 1.15V.while ultra_high speed mode.
|
||||
}en_pwc_pvd2level_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The pvd1 level select.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_pvd1level_sel
|
||||
{
|
||||
Pvd1Level0 = 0u, ///< 2.0V.while high_speed & ultra_low speed mode, 2.09V.while ultra_high speed mode.
|
||||
Pvd1Level1 = 1u, ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode.
|
||||
Pvd1Level2 = 2u, ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode.
|
||||
Pvd1Level3 = 3u, ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode.
|
||||
Pvd1Level4 = 4u, ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode.
|
||||
Pvd1Level5 = 5u, ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode.
|
||||
Pvd1Level6 = 6u, ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode.
|
||||
Pvd1Level7 = 7u, ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode.
|
||||
}en_pwc_pvd1level_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The pvd interrupt select.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_pvd_int_sel
|
||||
{
|
||||
NonMskInt = 0u, ///< Non-maskable Interrupt.
|
||||
MskInt = 1u, ///< Maskable Interrupt.
|
||||
}en_pwc_pvd_int_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The handle of pvd mode.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_pvd_md
|
||||
{
|
||||
PvdInt = 0u, ///< The handle of pvd is interrupt.
|
||||
PvdReset = 1u, ///< The handle of pvd is reset.
|
||||
}en_pwc_pvd_md_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The unit of pvd detect.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_pwc_pvd
|
||||
{
|
||||
PvdU1 = 0u, ///< The uint1 of pvd detect.
|
||||
PvdU2 = 1u, ///< The unit2 of pvd detect.
|
||||
}en_pwc_pvd_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The power mode configuration.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_pwc_pwr_mode_cfg
|
||||
{
|
||||
en_pwc_powerdown_md_t enPwrDownMd; ///< Power down mode.
|
||||
en_functional_state_t enRLdo; ///< Enable or disable RLDO.
|
||||
en_functional_state_t enRetSram; ///< Enable or disable Ret_Sram.
|
||||
en_pwc_iortn_t enIoRetain; ///< IO retain.
|
||||
en_pwc_waketime_sel_t enPwrDWkupTm; ///< The power down wake up time select.
|
||||
}stc_pwc_pwr_mode_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The stop mode configuration.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_pwc_stop_mode_cfg
|
||||
{
|
||||
en_pwc_stopdas_t enStpDrvAbi; ///< Driver ability while enter stop mode.
|
||||
en_pwc_stop_flash_sel_t enStopFlash; ///< Flash mode while stop mode awake.
|
||||
en_pwc_stop_clk_sel_t enStopClk; ///< Clock value while stop mode awake.
|
||||
en_functional_state_t enPll; ///< Whether the PLL enable or disable while enter stop mode.
|
||||
}stc_pwc_stop_mode_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The power down wake_up timer control.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_pwc_wktm_ctl
|
||||
{
|
||||
uint16_t u16WktmCmp; ///< The wake_up timer compare value.
|
||||
en_pwc_wkover_flag_t enWkOverFlag; ///< The flag of compare result.
|
||||
en_pwc_wkclk_sel_t enWkclk; ///< The clock of wake_up timer.
|
||||
en_functional_state_t enWktmEn; ///< Enable or disable wake_up timer.
|
||||
}stc_pwc_wktm_ctl_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The pvd control.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_pwc_pvd_ctl
|
||||
{
|
||||
en_functional_state_t enPvdIREn; ///< Enable or disable pvd interrupt(reset).
|
||||
en_pwc_pvd_md_t enPvdMode; ///< The handle of pvd is interrupt or reset.
|
||||
en_functional_state_t enPvdCmpOutEn; ///< Enable or disable pvd output compare result .
|
||||
}stc_pwc_pvd_ctl_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The power down wake_up event configuration.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_pwc_pvd_cfg
|
||||
{
|
||||
stc_pwc_pvd_ctl_t stcPvd1Ctl; ///< Pvd1 control configuration.
|
||||
stc_pwc_pvd_ctl_t stcPvd2Ctl; ///< Pvd2 control configuration.
|
||||
en_functional_state_t enPvd1FilterEn; ///< Pvd1 filtering enable or disable.
|
||||
en_functional_state_t enPvd2FilterEn; ///< Pvd2 filtering enable or disable.
|
||||
en_pwc_pvdfiltclk_sel_t enPvd1Filtclk; ///< Pvd1 filtering sampling clock.
|
||||
en_pwc_pvdfiltclk_sel_t enPvd2Filtclk; ///< Pvd2 filtering sampling clock.
|
||||
en_pwc_pvd1level_sel_t enPvd1Level; ///< Pvd1 voltage.
|
||||
en_pwc_pvd2level_sel_t enPvd2Level; ///< Pvd2 voltage.
|
||||
en_pwc_pvd_int_sel_t enPvd1Int; ///< Pvd1 interrupt.
|
||||
en_pwc_pvd_int_sel_t enPvd2Int; ///< Pvd2 interrupt.
|
||||
}stc_pwc_pvd_cfg_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
#define PWC_PDWKEN0_WKUP00 ((uint8_t)0x01)
|
||||
#define PWC_PDWKEN0_WKUP01 ((uint8_t)0x02)
|
||||
#define PWC_PDWKEN0_WKUP02 ((uint8_t)0x04)
|
||||
#define PWC_PDWKEN0_WKUP03 ((uint8_t)0x08)
|
||||
#define PWC_PDWKEN0_WKUP10 ((uint8_t)0x10)
|
||||
#define PWC_PDWKEN0_WKUP11 ((uint8_t)0x20)
|
||||
#define PWC_PDWKEN0_WKUP12 ((uint8_t)0x40)
|
||||
#define PWC_PDWKEN0_WKUP13 ((uint8_t)0x80)
|
||||
|
||||
#define PWC_PDWKEN1_WKUP20 ((uint8_t)0x01)
|
||||
#define PWC_PDWKEN1_WKUP21 ((uint8_t)0x02)
|
||||
#define PWC_PDWKEN1_WKUP22 ((uint8_t)0x04)
|
||||
#define PWC_PDWKEN1_WKUP23 ((uint8_t)0x08)
|
||||
#define PWC_PDWKEN1_WKUP30 ((uint8_t)0x10)
|
||||
#define PWC_PDWKEN1_WKUP31 ((uint8_t)0x20)
|
||||
#define PWC_PDWKEN1_WKUP32 ((uint8_t)0x40)
|
||||
#define PWC_PDWKEN1_WKUP33 ((uint8_t)0x80)
|
||||
|
||||
#define PWC_PDWKEN2_PVD1 ((uint8_t)0x01)
|
||||
#define PWC_PDWKEN2_PVD2 ((uint8_t)0x02)
|
||||
#define PWC_PDWKEN2_NMI ((uint8_t)0x04)
|
||||
#define PWC_PDWKEN2_RTCPRD ((uint8_t)0x10)
|
||||
#define PWC_PDWKEN2_RTCAL ((uint8_t)0x20)
|
||||
#define PWC_PDWKEN2_WKTM ((uint8_t)0x80)
|
||||
|
||||
#define PWC_PDWKUP_EDGE_WKP0 ((uint8_t)0x01)
|
||||
#define PWC_PDWKUP_EDGE_WKP1 ((uint8_t)0x02)
|
||||
#define PWC_PDWKUP_EDGE_WKP2 ((uint8_t)0x04)
|
||||
#define PWC_PDWKUP_EDGE_WKP3 ((uint8_t)0x08)
|
||||
#define PWC_PDWKUP_EDGE_PVD1 ((uint8_t)0x10)
|
||||
#define PWC_PDWKUP_EDGE_PVD2 ((uint8_t)0x20)
|
||||
#define PWC_PDWKUP_EDGE_NMI ((uint8_t)0x40)
|
||||
|
||||
#define PWC_RAMPWRDOWN_SRAM1 ((uint32_t)0x00000001)
|
||||
#define PWC_RAMPWRDOWN_SRAM2 ((uint32_t)0x00000002)
|
||||
#define PWC_RAMPWRDOWN_SRAM3 ((uint32_t)0x00000004)
|
||||
#define PWC_RAMPWRDOWN_SRAMH ((uint32_t)0x00000008)
|
||||
#define PWC_RAMPWRDOWN_USBFS ((uint32_t)0x00000010)
|
||||
#define PWC_RAMPWRDOWN_SDIOC0 ((uint32_t)0x00000020)
|
||||
#define PWC_RAMPWRDOWN_SDIOC1 ((uint32_t)0x00000040)
|
||||
#define PWC_RAMPWRDOWN_CAN ((uint32_t)0x00000080)
|
||||
#define PWC_RAMPWRDOWN_CACHE ((uint32_t)0x00000100)
|
||||
#define PWC_RAMPWRDOWN_FULL ((uint32_t)0x000001FF)
|
||||
|
||||
#define PWC_STOPWKUPEN_EIRQ0 ((uint32_t)0x00000001)
|
||||
#define PWC_STOPWKUPEN_EIRQ1 ((uint32_t)0x00000002)
|
||||
#define PWC_STOPWKUPEN_EIRQ2 ((uint32_t)0x00000004)
|
||||
#define PWC_STOPWKUPEN_EIRQ3 ((uint32_t)0x00000008)
|
||||
#define PWC_STOPWKUPEN_EIRQ4 ((uint32_t)0x00000010)
|
||||
#define PWC_STOPWKUPEN_EIRQ5 ((uint32_t)0x00000020)
|
||||
#define PWC_STOPWKUPEN_EIRQ6 ((uint32_t)0x00000040)
|
||||
#define PWC_STOPWKUPEN_EIRQ7 ((uint32_t)0x00000080)
|
||||
#define PWC_STOPWKUPEN_EIRQ8 ((uint32_t)0x00000100)
|
||||
#define PWC_STOPWKUPEN_EIRQ9 ((uint32_t)0x00000200)
|
||||
#define PWC_STOPWKUPEN_EIRQ10 ((uint32_t)0x00000400)
|
||||
#define PWC_STOPWKUPEN_EIRQ11 ((uint32_t)0x00000800)
|
||||
#define PWC_STOPWKUPEN_EIRQ12 ((uint32_t)0x00001000)
|
||||
#define PWC_STOPWKUPEN_EIRQ13 ((uint32_t)0x00002000)
|
||||
#define PWC_STOPWKUPEN_EIRQ14 ((uint32_t)0x00004000)
|
||||
#define PWC_STOPWKUPEN_EIRQ15 ((uint32_t)0x00008000)
|
||||
#define PWC_STOPWKUPEN_SWDT ((uint32_t)0x00010000)
|
||||
#define PWC_STOPWKUPEN_VDU1 ((uint32_t)0x00020000)
|
||||
#define PWC_STOPWKUPEN_VDU2 ((uint32_t)0x00040000)
|
||||
#define PWC_STOPWKUPEN_CMPI0 ((uint32_t)0x00080000)
|
||||
#define PWC_STOPWKUPEN_WKTM ((uint32_t)0x00100000)
|
||||
#define PWC_STOPWKUPEN_RTCAL ((uint32_t)0x00200000)
|
||||
#define PWC_STOPWKUPEN_RTCPRD ((uint32_t)0x00400000)
|
||||
#define PWC_STOPWKUPEN_TMR0 ((uint32_t)0x00800000)
|
||||
#define PWC_STOPWKUPEN_USARTRXD ((uint32_t)0x02000000)
|
||||
|
||||
#define PWC_PTWK0_WKUPFLAG ((uint8_t)0x01)
|
||||
#define PWC_PTWK1_WKUPFLAG ((uint8_t)0x02)
|
||||
#define PWC_PTWK2_WKUPFLAG ((uint8_t)0x04)
|
||||
#define PWC_PTWK3_WKUPFLAG ((uint8_t)0x08)
|
||||
#define PWC_PVD1_WKUPFLAG ((uint8_t)0x10)
|
||||
#define PWC_PVD2_WKUPFLAG ((uint8_t)0x20)
|
||||
#define PWC_NMI_WKUPFLAG ((uint8_t)0x40)
|
||||
|
||||
#define PWC_RTCPRD_WKUPFALG ((uint8_t)0x10)
|
||||
#define PWC_RTCAL_WKUPFLAG ((uint8_t)0x20)
|
||||
#define PWC_WKTM_WKUPFLAG ((uint8_t)0x80)
|
||||
|
||||
#define PWC_WKTMCMP_MSK ((uint16_t)0x0FFF)
|
||||
|
||||
#define PWC_FCG0_PERIPH_SRAMH ((uint32_t)0x00000001)
|
||||
#define PWC_FCG0_PERIPH_SRAM12 ((uint32_t)0x00000010)
|
||||
#define PWC_FCG0_PERIPH_SRAM3 ((uint32_t)0x00000100)
|
||||
#define PWC_FCG0_PERIPH_SRAMRET ((uint32_t)0x00000400)
|
||||
#define PWC_FCG0_PERIPH_DMA1 ((uint32_t)0x00004000)
|
||||
#define PWC_FCG0_PERIPH_DMA2 ((uint32_t)0x00008000)
|
||||
#define PWC_FCG0_PERIPH_FCM ((uint32_t)0x00010000)
|
||||
#define PWC_FCG0_PERIPH_AOS ((uint32_t)0x00020000)
|
||||
#define PWC_FCG0_PERIPH_AES ((uint32_t)0x00100000)
|
||||
#define PWC_FCG0_PERIPH_HASH ((uint32_t)0x00200000)
|
||||
#define PWC_FCG0_PERIPH_TRNG ((uint32_t)0x00400000)
|
||||
#define PWC_FCG0_PERIPH_CRC ((uint32_t)0x00800000)
|
||||
#define PWC_FCG0_PERIPH_DCU1 ((uint32_t)0x01000000)
|
||||
#define PWC_FCG0_PERIPH_DCU2 ((uint32_t)0x02000000)
|
||||
#define PWC_FCG0_PERIPH_DCU3 ((uint32_t)0x04000000)
|
||||
#define PWC_FCG0_PERIPH_DCU4 ((uint32_t)0x08000000)
|
||||
#define PWC_FCG0_PERIPH_KEY ((uint32_t)0x80000000)
|
||||
|
||||
|
||||
#define PWC_FCG1_PERIPH_CAN ((uint32_t)0x00000001)
|
||||
#define PWC_FCG1_PERIPH_QSPI ((uint32_t)0x00000008)
|
||||
#define PWC_FCG1_PERIPH_I2C1 ((uint32_t)0x00000010)
|
||||
#define PWC_FCG1_PERIPH_I2C2 ((uint32_t)0x00000020)
|
||||
#define PWC_FCG1_PERIPH_I2C3 ((uint32_t)0x00000040)
|
||||
#define PWC_FCG1_PERIPH_USBFS ((uint32_t)0x00000100)
|
||||
#define PWC_FCG1_PERIPH_SDIOC1 ((uint32_t)0x00000400)
|
||||
#define PWC_FCG1_PERIPH_SDIOC2 ((uint32_t)0x00000800)
|
||||
#define PWC_FCG1_PERIPH_I2S1 ((uint32_t)0x00001000)
|
||||
#define PWC_FCG1_PERIPH_I2S2 ((uint32_t)0x00002000)
|
||||
#define PWC_FCG1_PERIPH_I2S3 ((uint32_t)0x00004000)
|
||||
#define PWC_FCG1_PERIPH_I2S4 ((uint32_t)0x00008000)
|
||||
#define PWC_FCG1_PERIPH_SPI1 ((uint32_t)0x00010000)
|
||||
#define PWC_FCG1_PERIPH_SPI2 ((uint32_t)0x00020000)
|
||||
#define PWC_FCG1_PERIPH_SPI3 ((uint32_t)0x00040000)
|
||||
#define PWC_FCG1_PERIPH_SPI4 ((uint32_t)0x00080000)
|
||||
#define PWC_FCG1_PERIPH_USART1 ((uint32_t)0x01000000)
|
||||
#define PWC_FCG1_PERIPH_USART2 ((uint32_t)0x02000000)
|
||||
#define PWC_FCG1_PERIPH_USART3 ((uint32_t)0x04000000)
|
||||
#define PWC_FCG1_PERIPH_USART4 ((uint32_t)0x08000000)
|
||||
|
||||
#define PWC_FCG2_PERIPH_TIM01 ((uint32_t)0x00000001)
|
||||
#define PWC_FCG2_PERIPH_TIM02 ((uint32_t)0x00000002)
|
||||
#define PWC_FCG2_PERIPH_TIMA1 ((uint32_t)0x00000004)
|
||||
#define PWC_FCG2_PERIPH_TIMA2 ((uint32_t)0x00000008)
|
||||
#define PWC_FCG2_PERIPH_TIMA3 ((uint32_t)0x00000010)
|
||||
#define PWC_FCG2_PERIPH_TIMA4 ((uint32_t)0x00000020)
|
||||
#define PWC_FCG2_PERIPH_TIMA5 ((uint32_t)0x00000040)
|
||||
#define PWC_FCG2_PERIPH_TIMA6 ((uint32_t)0x00000080)
|
||||
#define PWC_FCG2_PERIPH_TIM41 ((uint32_t)0x00000100)
|
||||
#define PWC_FCG2_PERIPH_TIM42 ((uint32_t)0x00000200)
|
||||
#define PWC_FCG2_PERIPH_TIM43 ((uint32_t)0x00000400)
|
||||
#define PWC_FCG2_PERIPH_EMB ((uint32_t)0x00008000)
|
||||
#define PWC_FCG2_PERIPH_TIM61 ((uint32_t)0x00010000)
|
||||
#define PWC_FCG2_PERIPH_TIM62 ((uint32_t)0x00020000)
|
||||
#define PWC_FCG2_PERIPH_TIM63 ((uint32_t)0x00040000)
|
||||
|
||||
#define PWC_FCG3_PERIPH_ADC1 ((uint32_t)0x00000001)
|
||||
#define PWC_FCG3_PERIPH_ADC2 ((uint32_t)0x00000002)
|
||||
#define PWC_FCG3_PERIPH_CMP ((uint32_t)0x00000100)
|
||||
#define PWC_FCG3_PERIPH_OTS ((uint32_t)0x00001000)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void PWC_PowerModeCfg(const stc_pwc_pwr_mode_cfg_t* pstcPwrMdCfg);
|
||||
void PWC_EnterPowerDownMd(void);
|
||||
|
||||
void PWC_PdWakeup0Cmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState);
|
||||
void PWC_PdWakeup1Cmd(uint32_t u32Wkup1Event, en_functional_state_t enNewState);
|
||||
void PWC_PdWakeup2Cmd(uint32_t u32Wkup2Event, en_functional_state_t enNewState);
|
||||
void PWC_PdWakeupEvtEdgeCfg(uint8_t u8WkupEvent, en_pwc_edge_sel_t enEdge);
|
||||
|
||||
en_flag_status_t PWC_GetWakeup0Flag(uint8_t u8WkupFlag);
|
||||
en_flag_status_t PWC_GetWakeup1Flag(uint8_t u8WkupFlag);
|
||||
void PWC_ClearWakeup0Flag(uint8_t u8WkupFlag);
|
||||
void PWC_ClearWakeup1Flag(uint8_t u8WkupFlag);
|
||||
void PWC_PwrMonitorCmd(en_functional_state_t enNewState);
|
||||
|
||||
void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState);
|
||||
void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState);
|
||||
void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState);
|
||||
void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState);
|
||||
|
||||
en_result_t PWC_StopModeCfg(const stc_pwc_stop_mode_cfg_t* pstcStpMdCfg);
|
||||
void PWC_StopWkupCmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState);
|
||||
|
||||
void PWC_EnterStopMd(void);
|
||||
void PWC_EnterSleepMd(void);
|
||||
|
||||
void PWC_Xtal32CsCmd(en_functional_state_t enNewState);
|
||||
void PWC_HrcPwrCmd(en_functional_state_t enNewState);
|
||||
void PWC_PllPwrCmd(en_functional_state_t enNewState);
|
||||
void PWC_RamPwrdownCmd(uint32_t u32RamCtlBit, en_functional_state_t enNewState);
|
||||
void PWC_RamOpMdConfig(en_pwc_ram_op_md_t enRamOpMd);
|
||||
|
||||
void PWC_WktmControl(const stc_pwc_wktm_ctl_t* pstcWktmCtl);
|
||||
|
||||
void PWC_PvdCfg(const stc_pwc_pvd_cfg_t* pstcPvdCfg);
|
||||
void PWC_Pvd1Cmd(en_functional_state_t enNewState);
|
||||
void PWC_Pvd2Cmd(en_functional_state_t enNewState);
|
||||
void PWC_ExVccCmd(en_functional_state_t enNewState);
|
||||
void PWC_ClearPvdFlag(en_pwc_pvd_t enPvd);
|
||||
en_flag_status_t PWC_GetPvdFlag(en_pwc_pvd_t enPvd);
|
||||
en_flag_status_t PWC_GetPvdStatus(en_pwc_pvd_t enPvd);
|
||||
|
||||
void PWC_enNvicBackup(void);
|
||||
void PWC_enNvicRecover(void);
|
||||
void PWC_ClkBackup(void);
|
||||
void PWC_ClkRecover(void);
|
||||
void PWC_IrqClkBackup(void);
|
||||
void PWC_IrqClkRecover(void);
|
||||
|
||||
en_result_t PWC_HS2LS(void);
|
||||
en_result_t PWC_LS2HS(void);
|
||||
en_result_t PWC_HS2HP(void);
|
||||
en_result_t PWC_HP2HS(void);
|
||||
en_result_t PWC_LS2HP(void);
|
||||
en_result_t PWC_HP2LS(void);
|
||||
|
||||
//@} // PwcGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_PWC_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_PWC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,402 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_qspi.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link QspiGroup Queued SPI description @endlink
|
||||
**
|
||||
** - 2018-11-20 CDT First version for Device Driver Library of Qspi.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_QSPI_H__
|
||||
#define __HC32F460_QSPI_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_QSPI_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup QspiGroup Queued SPI(QSPI)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI spi protocol enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_spi_protocol
|
||||
{
|
||||
QspiProtocolExtendSpi = 0u, ///< Extend spi protocol
|
||||
QspiProtocolTwoWiresSpi = 1u, ///< Two wires spi protocol
|
||||
QspiProtocolFourWiresSpi = 2u, ///< Four wires spi protocol
|
||||
} en_qspi_spi_protocol_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI spi Mode enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_spi_mode
|
||||
{
|
||||
QspiSpiMode0 = 0u, ///< Spi mode 0(QSCK normalcy is Low level)
|
||||
QspiSpiMode3 = 1u, ///< Spi mode 3(QSCK normalcy is High level)
|
||||
} en_qspi_spi_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI bus communication mode enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_bus_mode
|
||||
{
|
||||
QspiBusModeRomAccess = 0u, ///< Rom access mode
|
||||
QspiBusModeDirectAccess = 1u, ///< Direct communication mode
|
||||
} en_qspi_bus_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI prefetch data stop config enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_prefetch_config
|
||||
{
|
||||
QspiPrefetchStopComplete = 0u, ///< Stop after prefetch data complete
|
||||
QspiPrefetchStopImmediately = 1u, ///< Immediately stop prefetch
|
||||
} en_qspi_prefetch_config_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI read mode enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_read_mode
|
||||
{
|
||||
QspiReadModeStandard = 0u, ///< Standard read
|
||||
QspiReadModeFast = 1u, ///< Fast read
|
||||
QspiReadModeTwoWiresOutput = 2u, ///< Two wires output fast read
|
||||
QspiReadModeTwoWiresIO = 3u, ///< Two wires input/output fast read
|
||||
QspiReadModeFourWiresOutput = 4u, ///< Four wires output fast read
|
||||
QspiReadModeFourWiresIO = 5u, ///< Four wires input/output fast read
|
||||
QspiReadModeCustomStandard = 6u, ///< Custom standard read
|
||||
QspiReadModeCustomFast = 7u, ///< Custom fast read
|
||||
} en_qspi_read_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI QSSN valid extend time enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_qssn_valid_extend_time
|
||||
{
|
||||
QspiQssnValidExtendNot = 0u, ///< Don't extend QSSN valid time
|
||||
QspiQssnValidExtendSck32 = 1u, ///< QSSN valid time extend 32 QSCK cycles
|
||||
QspiQssnValidExtendSck128 = 2u, ///< QSSN valid time extend 138 QSCK cycles
|
||||
QspiQssnValidExtendSckEver = 3u, ///< QSSN valid time extend to ever
|
||||
} en_qspi_qssn_valid_extend_time_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI QSCK duty cycle correction enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_qsck_duty_correction
|
||||
{
|
||||
QspiQsckDutyCorrNot = 0u, ///< Don't correction duty cycle
|
||||
QspiQsckDutyCorrHalfHclk = 1u, ///< QSCK's rising edge delay 0.5 HCLK cycle when Qsck select HCLK is odd
|
||||
} en_qspi_qsck_duty_correction_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI WP Pin output level enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_wp_pin_level
|
||||
{
|
||||
QspiWpPinOutputLow = 0u, ///< WP pin(QIO2) output low level
|
||||
QspiWpPinOutputHigh = 1u, ///< WP pin(QIO2) output high level
|
||||
} en_qspi_wp_pin_level_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI QSSN setup delay time enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_qssn_setup_delay
|
||||
{
|
||||
QspiQssnSetupDelayHalfQsck = 0u, ///< QSSN setup delay 0.5 QSCK output than QSCK first rising edge
|
||||
QspiQssnSetupDelay1Dot5Qsck = 1u, ///< QSSN setup delay 1.5 QSCK output than QSCK first rising edge
|
||||
} en_qspi_qssn_setup_delay_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI QSSN hold delay time enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_qssn_hold_delay
|
||||
{
|
||||
QspiQssnHoldDelayHalfQsck = 0u, ///< QSSN hold delay 0.5 QSCK release than QSCK last rising edge
|
||||
QspiQssnHoldDelay1Dot5Qsck = 1u, ///< QSSN hold delay 1.5 QSCK release than QSCK last rising edge
|
||||
} en_qspi_qssn_hold_delay_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI address width enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_addr_width
|
||||
{
|
||||
QspiAddressByteOne = 0u, ///< One byte address
|
||||
QspiAddressByteTwo = 1u, ///< Two byte address
|
||||
QspiAddressByteThree = 2u, ///< Three byte address
|
||||
QspiAddressByteFour = 3u, ///< Four byte address
|
||||
} en_qspi_addr_width_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI flag type enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_flag_type
|
||||
{
|
||||
QspiFlagBusBusy = 0u, ///< QSPI bus work status flag in direct communication mode
|
||||
QspiFlagXipMode = 1u, ///< XIP mode status signal
|
||||
QspiFlagRomAccessError = 2u, ///< Trigger rom access error flag in direct communication mode
|
||||
QspiFlagPrefetchBufferFull = 3u, ///< Prefetch buffer area status signal
|
||||
QspiFlagPrefetchStop = 4u, ///< Prefetch action status signal
|
||||
} en_qspi_flag_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI clock division enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_clk_div
|
||||
{
|
||||
QspiHclkDiv2 = 0u, ///< Clock source: HCLK/2
|
||||
QspiHclkDiv3 = 2u, ///< Clock source: HCLK/3
|
||||
QspiHclkDiv4 = 3u, ///< Clock source: HCLK/4
|
||||
QspiHclkDiv5 = 4u, ///< Clock source: HCLK/5
|
||||
QspiHclkDiv6 = 5u, ///< Clock source: HCLK/6
|
||||
QspiHclkDiv7 = 6u, ///< Clock source: HCLK/7
|
||||
QspiHclkDiv8 = 7u, ///< Clock source: HCLK/8
|
||||
QspiHclkDiv9 = 8u, ///< Clock source: HCLK/9
|
||||
QspiHclkDiv10 = 9u, ///< Clock source: HCLK/10
|
||||
QspiHclkDiv11 = 10u, ///< Clock source: HCLK/11
|
||||
QspiHclkDiv12 = 11u, ///< Clock source: HCLK/12
|
||||
QspiHclkDiv13 = 12u, ///< Clock source: HCLK/13
|
||||
QspiHclkDiv14 = 13u, ///< Clock source: HCLK/14
|
||||
QspiHclkDiv15 = 14u, ///< Clock source: HCLK/15
|
||||
QspiHclkDiv16 = 15u, ///< Clock source: HCLK/16
|
||||
QspiHclkDiv17 = 16u, ///< Clock source: HCLK/17
|
||||
QspiHclkDiv18 = 17u, ///< Clock source: HCLK/18
|
||||
QspiHclkDiv19 = 18u, ///< Clock source: HCLK/19
|
||||
QspiHclkDiv20 = 19u, ///< Clock source: HCLK/20
|
||||
QspiHclkDiv21 = 20u, ///< Clock source: HCLK/21
|
||||
QspiHclkDiv22 = 21u, ///< Clock source: HCLK/22
|
||||
QspiHclkDiv23 = 22u, ///< Clock source: HCLK/23
|
||||
QspiHclkDiv24 = 23u, ///< Clock source: HCLK/24
|
||||
QspiHclkDiv25 = 24u, ///< Clock source: HCLK/25
|
||||
QspiHclkDiv26 = 25u, ///< Clock source: HCLK/26
|
||||
QspiHclkDiv27 = 26u, ///< Clock source: HCLK/27
|
||||
QspiHclkDiv28 = 27u, ///< Clock source: HCLK/28
|
||||
QspiHclkDiv29 = 28u, ///< Clock source: HCLK/29
|
||||
QspiHclkDiv30 = 29u, ///< Clock source: HCLK/30
|
||||
QspiHclkDiv31 = 30u, ///< Clock source: HCLK/31
|
||||
QspiHclkDiv32 = 31u, ///< Clock source: HCLK/32
|
||||
QspiHclkDiv33 = 32u, ///< Clock source: HCLK/33
|
||||
QspiHclkDiv34 = 33u, ///< Clock source: HCLK/34
|
||||
QspiHclkDiv35 = 34u, ///< Clock source: HCLK/35
|
||||
QspiHclkDiv36 = 35u, ///< Clock source: HCLK/36
|
||||
QspiHclkDiv37 = 36u, ///< Clock source: HCLK/37
|
||||
QspiHclkDiv38 = 37u, ///< Clock source: HCLK/38
|
||||
QspiHclkDiv39 = 38u, ///< Clock source: HCLK/39
|
||||
QspiHclkDiv40 = 39u, ///< Clock source: HCLK/40
|
||||
QspiHclkDiv41 = 40u, ///< Clock source: HCLK/41
|
||||
QspiHclkDiv42 = 41u, ///< Clock source: HCLK/42
|
||||
QspiHclkDiv43 = 42u, ///< Clock source: HCLK/43
|
||||
QspiHclkDiv44 = 43u, ///< Clock source: HCLK/44
|
||||
QspiHclkDiv45 = 44u, ///< Clock source: HCLK/45
|
||||
QspiHclkDiv46 = 45u, ///< Clock source: HCLK/46
|
||||
QspiHclkDiv47 = 46u, ///< Clock source: HCLK/47
|
||||
QspiHclkDiv48 = 47u, ///< Clock source: HCLK/48
|
||||
QspiHclkDiv49 = 48u, ///< Clock source: HCLK/49
|
||||
QspiHclkDiv50 = 49u, ///< Clock source: HCLK/50
|
||||
QspiHclkDiv51 = 50u, ///< Clock source: HCLK/51
|
||||
QspiHclkDiv52 = 51u, ///< Clock source: HCLK/52
|
||||
QspiHclkDiv53 = 52u, ///< Clock source: HCLK/53
|
||||
QspiHclkDiv54 = 53u, ///< Clock source: HCLK/54
|
||||
QspiHclkDiv55 = 54u, ///< Clock source: HCLK/55
|
||||
QspiHclkDiv56 = 55u, ///< Clock source: HCLK/56
|
||||
QspiHclkDiv57 = 56u, ///< Clock source: HCLK/57
|
||||
QspiHclkDiv58 = 57u, ///< Clock source: HCLK/58
|
||||
QspiHclkDiv59 = 58u, ///< Clock source: HCLK/59
|
||||
QspiHclkDiv60 = 59u, ///< Clock source: HCLK/60
|
||||
QspiHclkDiv61 = 60u, ///< Clock source: HCLK/61
|
||||
QspiHclkDiv62 = 61u, ///< Clock source: HCLK/62
|
||||
QspiHclkDiv63 = 62u, ///< Clock source: HCLK/63
|
||||
QspiHclkDiv64 = 63u, ///< Clock source: HCLK/64
|
||||
} en_qspi_clk_div_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI QSSN minimum interval time enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_qssn_interval_time
|
||||
{
|
||||
QspiQssnIntervalQsck1 = 0u, ///< QSSN signal min interval time 1 QSCK
|
||||
QspiQssnIntervalQsck2 = 1u, ///< QSSN signal min interval time 2 QSCK
|
||||
QspiQssnIntervalQsck3 = 2u, ///< QSSN signal min interval time 3 QSCK
|
||||
QspiQssnIntervalQsck4 = 3u, ///< QSSN signal min interval time 4 QSCK
|
||||
QspiQssnIntervalQsck5 = 4u, ///< QSSN signal min interval time 5 QSCK
|
||||
QspiQssnIntervalQsck6 = 5u, ///< QSSN signal min interval time 6 QSCK
|
||||
QspiQssnIntervalQsck7 = 6u, ///< QSSN signal min interval time 7 QSCK
|
||||
QspiQssnIntervalQsck8 = 7u, ///< QSSN signal min interval time 8 QSCK
|
||||
QspiQssnIntervalQsck9 = 8u, ///< QSSN signal min interval time 9 QSCK
|
||||
QspiQssnIntervalQsck10 = 9u, ///< QSSN signal min interval time 10 QSCK
|
||||
QspiQssnIntervalQsck11 = 10u, ///< QSSN signal min interval time 11 QSCK
|
||||
QspiQssnIntervalQsck12 = 11u, ///< QSSN signal min interval time 12 QSCK
|
||||
QspiQssnIntervalQsck13 = 12u, ///< QSSN signal min interval time 13 QSCK
|
||||
QspiQssnIntervalQsck14 = 13u, ///< QSSN signal min interval time 14 QSCK
|
||||
QspiQssnIntervalQsck15 = 14u, ///< QSSN signal min interval time 15 QSCK
|
||||
QspiQssnIntervalQsck16 = 15u, ///< QSSN signal min interval time 16 QSCK
|
||||
} en_qspi_qssn_interval_time_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI virtual period enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_qspi_virtual_period
|
||||
{
|
||||
QspiVirtualPeriodQsck3 = 0u, ///< Virtual period select 3 QSCK
|
||||
QspiVirtualPeriodQsck4 = 1u, ///< Virtual period select 4 QSCK
|
||||
QspiVirtualPeriodQsck5 = 2u, ///< Virtual period select 5 QSCK
|
||||
QspiVirtualPeriodQsck6 = 3u, ///< Virtual period select 6 QSCK
|
||||
QspiVirtualPeriodQsck7 = 4u, ///< Virtual period select 7 QSCK
|
||||
QspiVirtualPeriodQsck8 = 5u, ///< Virtual period select 8 QSCK
|
||||
QspiVirtualPeriodQsck9 = 6u, ///< Virtual period select 9 QSCK
|
||||
QspiVirtualPeriodQsck10 = 7u, ///< Virtual period select 10 QSCK
|
||||
QspiVirtualPeriodQsck11 = 8u, ///< Virtual period select 11 QSCK
|
||||
QspiVirtualPeriodQsck12 = 9u, ///< Virtual period select 12 QSCK
|
||||
QspiVirtualPeriodQsck13 = 10u, ///< Virtual period select 13 QSCK
|
||||
QspiVirtualPeriodQsck14 = 11u, ///< Virtual period select 14 QSCK
|
||||
QspiVirtualPeriodQsck15 = 12u, ///< Virtual period select 15 QSCK
|
||||
QspiVirtualPeriodQsck16 = 13u, ///< Virtual period select 16 QSCK
|
||||
QspiVirtualPeriodQsck17 = 14u, ///< Virtual period select 17 QSCK
|
||||
QspiVirtualPeriodQsck18 = 15u, ///< Virtual period select 18 QSCK
|
||||
} en_qspi_virtual_period_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI communication protocol structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_qspi_comm_protocol
|
||||
{
|
||||
en_qspi_spi_protocol_t enReceProtocol; ///< Receive data stage SPI protocol
|
||||
en_qspi_spi_protocol_t enTransAddrProtocol; ///< Transmit address stage SPI protocol
|
||||
en_qspi_spi_protocol_t enTransInstrProtocol; ///< Transmit instruction stage SPI protocol
|
||||
en_qspi_read_mode_t enReadMode; ///< Serial interface read mode
|
||||
} stc_qspi_comm_protocol_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief QSPI init structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_qspi_init
|
||||
{
|
||||
en_qspi_clk_div_t enClkDiv; ///< Clock division
|
||||
en_qspi_spi_mode_t enSpiMode; ///< Specifies SPI mode
|
||||
en_qspi_bus_mode_t enBusCommMode; ///< Bus communication mode
|
||||
en_qspi_prefetch_config_t enPrefetchMode; ///< Config prefetch stop location
|
||||
en_functional_state_t enPrefetchFuncEn; ///< Disable: disable prefetch function, Enable: enable prefetch function
|
||||
stc_qspi_comm_protocol_t stcCommProtocol; ///< Qspi communication protocol config
|
||||
en_qspi_qssn_valid_extend_time_t enQssnValidExtendTime; ///< QSSN valid extend time function select after QSPI access bus
|
||||
en_qspi_qssn_interval_time_t enQssnIntervalTime; ///< QSSN minimum interval time
|
||||
en_qspi_qsck_duty_correction_t enQsckDutyCorr; ///< QSCK output duty cycles correction
|
||||
en_qspi_virtual_period_t enVirtualPeriod; ///< Virtual period config
|
||||
en_qspi_wp_pin_level_t enWpPinLevel; ///< WP pin(QIO2) level select
|
||||
en_qspi_qssn_setup_delay_t enQssnSetupDelayTime; ///< QSSN setup delay time choose
|
||||
en_qspi_qssn_hold_delay_t enQssnHoldDelayTime; ///< QSSN hold delay time choose
|
||||
en_functional_state_t enFourByteAddrReadEn; ///< Read instruction code select when set address width is four bytes
|
||||
en_qspi_addr_width_t enAddrWidth; ///< Serial interface address width choose
|
||||
uint8_t u8RomAccessInstr; ///< Rom access mode instruction
|
||||
} stc_qspi_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*!< 4-byte instruction mode using instruction set */
|
||||
#define QSPI_4BINSTR_STANDARD_READ 0x13u
|
||||
#define QSPI_4BINSTR_FAST_READ 0x0Cu
|
||||
#define QSPI_4BINSTR_TWO_WIRES_OUTPUT_READ 0x3Cu
|
||||
#define QSPI_4BINSTR_TWO_WIRES_IO_READ 0xBCu
|
||||
#define QSPI_4BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Cu
|
||||
#define QSPI_4BINSTR_FOUR_WIRES_IO_READ 0xECu
|
||||
#define QSPI_4BINSTR_EXIT_4BINSTR_MODE 0xB7u
|
||||
|
||||
/*!< 3-byte instruction mode using instruction set */
|
||||
#define QSPI_3BINSTR_STANDARD_READ 0x03u
|
||||
#define QSPI_3BINSTR_FAST_READ 0x0Bu
|
||||
#define QSPI_3BINSTR_TWO_WIRES_OUTPUT_READ 0x3Bu
|
||||
#define QSPI_3BINSTR_TWO_WIRES_IO_READ 0xBBu
|
||||
#define QSPI_3BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Bu
|
||||
#define QSPI_3BINSTR_FOUR_WIRES_IO_READ 0xEBu
|
||||
#define QSPI_3BINSTR_ENTER_4BINSTR_MODE 0xE9u
|
||||
|
||||
/*!< General instruction set */
|
||||
#define QSPI_WRITE_MODE_ENABLE 0x06u
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/* Base functions */
|
||||
en_result_t QSPI_DeInit(void);
|
||||
en_result_t QSPI_Init(const stc_qspi_init_t *pstcQspiInitCfg);
|
||||
en_result_t QSPI_SetAddrWidth(en_qspi_addr_width_t enAddrWidth);
|
||||
en_result_t QSPI_SetExtendAddress(uint8_t u8Addr);
|
||||
en_result_t QSPI_CommProtocolConfig(const stc_qspi_comm_protocol_t *pstcCommProtocol);
|
||||
en_result_t QSPI_PrefetchCmd(en_functional_state_t enNewSta);
|
||||
en_result_t QSPI_SetClockDiv(en_qspi_clk_div_t enClkDiv);
|
||||
en_result_t QSPI_SetWPPinLevel(en_qspi_wp_pin_level_t enWpLevel);
|
||||
|
||||
/* Rom access mode functions */
|
||||
en_result_t QSPI_SetRomAccessInstruct(uint8_t u8Instr);
|
||||
en_result_t QSPI_XipModeCmd(uint8_t u8Instr, en_functional_state_t enNewSta);
|
||||
|
||||
/* Direct communication mode functions */
|
||||
en_result_t QSPI_WriteDirectCommValue(uint8_t u8Val);
|
||||
uint8_t QSPI_ReadDirectCommValue(void);
|
||||
en_result_t QSPI_EnterDirectCommMode(void);
|
||||
en_result_t QSPI_ExitDirectCommMode(void);
|
||||
|
||||
/* Flags and get buffer functions */
|
||||
uint8_t QSPI_GetPrefetchBufferNum(void);
|
||||
en_flag_status_t QSPI_GetFlag(en_qspi_flag_type_t enFlag);
|
||||
en_result_t QSPI_ClearFlag(en_qspi_flag_type_t enFlag);
|
||||
|
||||
//@} // QspiGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_QSPI_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_QSPI_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,96 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_rmu.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link RmuGroup RMU description @endlink
|
||||
**
|
||||
** - 2018-10-28 CDT First version for Device Driver Library of RMU
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_RMU_H__
|
||||
#define __HC32F460_RMU_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_RMU_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup RmuGroup Reset Management Unit(RMU)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief system reset cause flag
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_rmu_rstcause
|
||||
{
|
||||
en_flag_status_t enMultiRst; ///< Multiply reset cause
|
||||
en_flag_status_t enXtalErr; ///< Xtal error reset
|
||||
en_flag_status_t enClkFreqErr; ///< Clk freqence error reset
|
||||
en_flag_status_t enRamEcc; ///< Ram ECC reset
|
||||
en_flag_status_t enRamParityErr; ///< Ram parity error reset
|
||||
en_flag_status_t enMpuErr; ///< Mpu error reset
|
||||
en_flag_status_t enSoftware; ///< Software reset
|
||||
en_flag_status_t enPowerDown; ///< Power down reset
|
||||
en_flag_status_t enSwdt; ///< Special watchdog timer reset
|
||||
en_flag_status_t enWdt; ///< Watchdog timer reset
|
||||
en_flag_status_t enPvd2; ///< Program voltage Dectection 2 reset
|
||||
en_flag_status_t enPvd1; ///< Program voltage Dectection 1 reset
|
||||
en_flag_status_t enBrownOut; ///< Brown out reset
|
||||
en_flag_status_t enRstPin; ///< Reset pin reset
|
||||
en_flag_status_t enPowerOn; ///< Power on reset
|
||||
}stc_rmu_rstcause_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t RMU_GetResetCause(stc_rmu_rstcause_t *pstcData);
|
||||
en_result_t RMU_ClrResetFlag(void);
|
||||
|
||||
//@} // RmuGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_RMU_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_RMU_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
||||
@@ -0,0 +1,274 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_rtc.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link RtcGroup Real-Time Clock description @endlink
|
||||
**
|
||||
** - 2018-11-22 CDT First version for Device Driver Library of RTC.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_RTC_H__
|
||||
#define __HC32F460_RTC_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_RTC_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup RtcGroup Real-Time Clock(RTC)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC period interrupt type enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_rtc_period_int_type
|
||||
{
|
||||
RtcPeriodIntInvalid = 0u, ///< Period interrupt invalid
|
||||
RtcPeriodIntHalfSec = 1u, ///< 0.5 second period interrupt
|
||||
RtcPeriodIntOneSec = 2u, ///< 1 second period interrupt
|
||||
RtcPeriodIntOneMin = 3u, ///< 1 minute period interrupt
|
||||
RtcPeriodIntOneHour = 4u, ///< 1 hour period interrupt
|
||||
RtcPeriodIntOneDay = 5u, ///< 1 day period interrupt
|
||||
RtcPeriodIntOneMon = 6u ///< 1 month period interrupt
|
||||
} en_rtc_period_int_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC time format enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_rtc_time_format
|
||||
{
|
||||
RtcTimeFormat12Hour = 0u, ///< 12 hours mode
|
||||
RtcTimeFormat24Hour = 1u, ///< 24 hours mode
|
||||
} en_rtc_time_format_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC 1Hz output compensation way enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_rtc_output_compen
|
||||
{
|
||||
RtcOutputCompenDistributed = 0u, ///< Distributed compensation 1hz output
|
||||
RtcOutputCompenUniform = 1u, ///< Uniform Compensation 1hz output
|
||||
} en_rtc_output_compen_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC work mode enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_rtc_work_mode
|
||||
{
|
||||
RtcModeNormalCount = 0u, ///< Normal count mode
|
||||
RtcModeReadOrWrite = 1u, ///< Read or write mode
|
||||
} en_rtc_work_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC count clock source enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_rtc_clk_source
|
||||
{
|
||||
RtcClkXtal32 = 0u, ///< XTAL32 as clock source
|
||||
RtcClkLrc = 1u, ///< LRC as clock source
|
||||
} en_rtc_clk_source_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC data format enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_rtc_data_format
|
||||
{
|
||||
RtcDataFormatDec = 0u, ///< Decimal format
|
||||
RtcDataFormatBcd = 1u, ///< BCD format
|
||||
} en_rtc_data_format_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC 12 hour AM/PM enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_rtc_hour12_ampm
|
||||
{
|
||||
RtcHour12Am = 0u, ///< Ante meridiem
|
||||
RtcHour12Pm = 1u, ///< Post meridiem
|
||||
} en_rtc_hour12_ampm_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC month enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_rtc_month
|
||||
{
|
||||
RtcMonthJanuary = 1u, ///< January
|
||||
RtcMonthFebruary = 2u, ///< February
|
||||
RtcMonthMarch = 3u, ///< March
|
||||
RtcMonthApril = 4u, ///< April
|
||||
RtcMonthMay = 5u, ///< May
|
||||
RtcMonthJune = 6u, ///< June
|
||||
RtcMonthJuly = 7u, ///< July
|
||||
RtcMonthAugust = 8u, ///< August
|
||||
RtcMonthSeptember = 9u, ///< September
|
||||
RtcMonthOctober = 10u, ///< October
|
||||
RtcMonthNovember = 11u, ///< November
|
||||
RtcMonthDecember = 12u, ///< December
|
||||
} en_rtc_month_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC weekday enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_rtc_weekday
|
||||
{
|
||||
RtcWeekdaySunday = 0u, ///< Sunday
|
||||
RtcWeekdayMonday = 1u, ///< Monday
|
||||
RtcWeekdayTuesday = 2u, ///< Tuesday
|
||||
RtcWeekdayWednesday = 3u, ///< Wednesday
|
||||
RtcWeekdayThursday = 4u, ///< Thursday
|
||||
RtcWeekdayFriday = 5u, ///< Friday
|
||||
RtcWeekdaySaturday = 6u ///< Saturday
|
||||
} en_rtc_weekday_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC alarm weekday enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_rtc_alarm_weekday
|
||||
{
|
||||
RtcAlarmWeekdaySunday = 0x01u, ///< Sunday
|
||||
RtcAlarmWeekdayMonday = 0x02u, ///< Monday
|
||||
RtcAlarmWeekdayTuesday = 0x04u, ///< Tuesday
|
||||
RtcAlarmWeekdayWednesday = 0x08u, ///< Wednesday
|
||||
RtcAlarmWeekdayThursday = 0x10u, ///< Thursday
|
||||
RtcAlarmWeekdayFriday = 0x20u, ///< Friday
|
||||
RtcAlarmWeekdaySaturday = 0x40u, ///< Saturday
|
||||
} en_rtc_alarm_weekday_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC interrupt request type enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_rtc_irq_type_
|
||||
{
|
||||
RtcIrqPeriod = 0u, ///< Period count interrupt request
|
||||
RtcIrqAlarm = 1u, ///< Alarm interrupt request
|
||||
} en_rtc_irq_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC date and time structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_rtc_date_time
|
||||
{
|
||||
uint8_t u8Year; ///< Year (range 0-99)
|
||||
uint8_t u8Month; ///< Month (range 1-12)
|
||||
uint8_t u8Day; ///< Day (range 1-31)
|
||||
uint8_t u8Hour; ///< Hours (range 1-12 when 12 hour format; range 0-23 when 24 hour format)
|
||||
uint8_t u8Minute; ///< Minutes (range 0-59)
|
||||
uint8_t u8Second; ///< Seconds (range 0-59)
|
||||
uint8_t u8Weekday; ///< Weekday (range 0-6)
|
||||
en_rtc_hour12_ampm_t enAmPm; ///< The value is valid when 12-hour format
|
||||
} stc_rtc_date_time_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC alarm time structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_rtc_alarm_time
|
||||
{
|
||||
uint8_t u8Minute; ///< Minutes (range 0-59)
|
||||
uint8_t u8Hour; ///< Hours (range 1-12 when 12 hour format; range 0-23 when 24 hour format)
|
||||
uint8_t u8Weekday; ///< Weekday (range RtcAlarmWeekdaySunday to RtcAlarmWeekdaySaturday)
|
||||
en_rtc_hour12_ampm_t enAmPm; ///< The value is valid when 12-hour format
|
||||
} stc_rtc_alarm_time_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC init structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_rtc_init
|
||||
{
|
||||
en_rtc_clk_source_t enClkSource; ///< Clock source
|
||||
en_rtc_period_int_type_t enPeriodInt; ///< Period interrupt condition
|
||||
en_rtc_time_format_t enTimeFormat; ///< RTC time format
|
||||
en_rtc_output_compen_t enCompenWay; ///< 1HZ output compensation way
|
||||
uint16_t u16CompenVal; ///< Clock error compensation value
|
||||
en_functional_state_t enCompenEn; ///< Enable/Disable clock error compensation
|
||||
} stc_rtc_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/* Base functions */
|
||||
en_result_t RTC_DeInit(void);
|
||||
en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit);
|
||||
en_result_t RTC_Cmd(en_functional_state_t enNewSta);
|
||||
en_result_t RTC_EnterRwMode(void);
|
||||
en_result_t RTC_ExitRwMode(void);
|
||||
|
||||
/* Extend functions */
|
||||
en_result_t RTC_PeriodIntConfig(en_rtc_period_int_type_t enIntType);
|
||||
en_result_t RTC_LowPowerSwitch(void);
|
||||
en_result_t RTC_SetClkCompenValue(uint16_t u16CompenVal);
|
||||
en_result_t RTC_ClkCompenCmd(en_functional_state_t enNewSta);
|
||||
en_result_t RTC_OneHzOutputCmd(en_functional_state_t enNewSta);
|
||||
|
||||
/* Date and time functions */
|
||||
en_result_t RTC_SetDateTime(en_rtc_data_format_t enFormat, const stc_rtc_date_time_t *pstcRtcDateTime,
|
||||
en_functional_state_t enUpdateDateEn, en_functional_state_t enUpdateTimeEn);
|
||||
en_result_t RTC_GetDateTime(en_rtc_data_format_t enFormat, stc_rtc_date_time_t *pstcRtcDateTime);
|
||||
|
||||
/* Alarm functions */
|
||||
en_result_t RTC_SetAlarmTime(en_rtc_data_format_t enFormat, const stc_rtc_alarm_time_t *pstcRtcAlarmTime);
|
||||
en_result_t RTC_GetAlarmTime(en_rtc_data_format_t enFormat, stc_rtc_alarm_time_t *pstcRtcAlarmTime);
|
||||
en_result_t RTC_AlarmCmd(en_functional_state_t enNewSta);
|
||||
|
||||
/* Interrupt and flags management functions ******************************************/
|
||||
en_result_t RTC_IrqCmd(en_rtc_irq_type_t enIrq, en_functional_state_t enNewSta);
|
||||
en_flag_status_t RTC_GetAlarmFlag(void);
|
||||
en_result_t RTC_ClearAlarmFlag(void);
|
||||
|
||||
//@} // RtcGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_RTC_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_RTC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,559 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_sdioc.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link SdiocGroup SDIOC description @endlink
|
||||
**
|
||||
** - 2018-11-11 CDT First version for Device Driver Library of SDIOC.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_SDIOC_H__
|
||||
#define __HC32F460_SDIOC_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_SDIOC_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup SdiocGroup Secure Digital Input and Output Controller(SDIOC)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_mode
|
||||
{
|
||||
SdiocModeSD = 0u, ///< The SD mode
|
||||
SdiocModeMMC = 1u, ///< The MMC mode
|
||||
} en_sdioc_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC transfer bus width enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_bus_width
|
||||
{
|
||||
SdiocBusWidth4Bit = 0u, ///< The SDIOC bus width 4 bit
|
||||
SdiocBusWidth8Bit = 1u, ///< The SDIOC bus width 8 bit
|
||||
SdiocBusWidth1Bit = 2u, ///< The SDIOC bus width 1 bit
|
||||
} en_sdioc_bus_width_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC clock division enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_clk_div
|
||||
{
|
||||
SdiocClkDiv_1 = 0x00u, ///< EXCLK/1
|
||||
SdiocClkDiv_2 = 0x01u, ///< EXCLK/2
|
||||
SdiocClkDiv_4 = 0x02u, ///< EXCLK/4
|
||||
SdiocClkDiv_8 = 0x04u, ///< EXCLK/8
|
||||
SdiocClkDiv_16 = 0x08u, ///< EXCLK/16
|
||||
SdiocClkDiv_32 = 0x10u, ///< EXCLK/32
|
||||
SdiocClkDiv_64 = 0x20u, ///< EXCLK/64
|
||||
SdiocClkDiv_128 = 0x40u, ///< EXCLK/128
|
||||
SdiocClkDiv_256 = 0x80u, ///< EXCLK/256
|
||||
} en_sdioc_clk_div_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC response type enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_response_type
|
||||
{
|
||||
SdiocResponseNoneBit = 0u, ///< No Response
|
||||
SdiocResponse136Bit = 1u, ///< Response Length 136
|
||||
SdiocResponse48Bit = 2u, ///< Response Length 48
|
||||
SdiocResponse48BitCheckBusy = 3u, ///< Response Length 48 check Busy after response
|
||||
} en_sdioc_response_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC response index enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_response_index
|
||||
{
|
||||
SdiocCmdNoRsp = 0u, ///< No Response
|
||||
SdiocCmdRspR1 = 1u, ///< Command Response 1
|
||||
SdiocCmdRspR1b = 2u, ///< Command Response 1 with busy
|
||||
SdiocCmdRspR2 = 3u, ///< Command Response 2
|
||||
SdiocCmdRspR3 = 4u, ///< Command Response 3
|
||||
SdiocCmdRspR4 = 5u, ///< Command Response 4
|
||||
SdiocCmdRspR5 = 6u, ///< Command Response 5
|
||||
SdiocCmdRspR5b = 7u, ///< Command Response 5 with busy
|
||||
SdiocCmdRspR6 = 8u, ///< Command Response 6
|
||||
SdiocCmdRspR7 = 9u, ///< Command Response 7
|
||||
} en_sdioc_response_index_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC command type enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_cmd_type
|
||||
{
|
||||
SdiocCmdNormal = 0u, ///< Other commands
|
||||
SdiocCmdSuspend = 1u, ///< CMD52 for writing "Bus Suspend" in CCCR
|
||||
SdiocCmdResume = 2u, ///< CMD52 for writing "Function Select" in CCCR
|
||||
SdiocCmdAbort = 3u, ///< CMD12, CMD52 for writing "I/O Abort" in CCCR
|
||||
} en_sdioc_cmd_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC data transfer direction enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_transfer_dir
|
||||
{
|
||||
SdiocTransferToCard = 0u, ///< Write (Host to Card)
|
||||
SdiocTransferToHost = 1u, ///< Read (Card to Host)
|
||||
} en_sdioc_transfer_dir_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC data transfer mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_transfer_mode
|
||||
{
|
||||
SdiocTransferSingle = 0u, ///< Single Block transfer
|
||||
SdiocTransferInfinite = 1u, ///< Infinite Block transfer
|
||||
SdiocTransferMultiple = 2u, ///< Multiple Block transfer
|
||||
SdiocTransferStopMultiple = 3u, ///< Stop Multiple Block transfer
|
||||
} en_sdioc_transfer_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SD data timeout time enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sd_data_timeout
|
||||
{
|
||||
SdiocDtoSdclk_2_13 = 0u, ///< Timeout time: SDCLK*2^13
|
||||
SdiocDtoSdclk_2_14 = 1u, ///< Timeout time: SDCLK*2^14
|
||||
SdiocDtoSdclk_2_15 = 2u, ///< Timeout time: SDCLK*2^15
|
||||
SdiocDtoSdclk_2_16 = 3u, ///< Timeout time: SDCLK*2^16
|
||||
SdiocDtoSdclk_2_17 = 4u, ///< Timeout time: SDCLK*2^17
|
||||
SdiocDtoSdclk_2_18 = 5u, ///< Timeout time: SDCLK*2^18
|
||||
SdiocDtoSdclk_2_19 = 6u, ///< Timeout time: SDCLK*2^19
|
||||
SdiocDtoSdclk_2_20 = 7u, ///< Timeout time: SDCLK*2^20
|
||||
SdiocDtoSdclk_2_21 = 8u, ///< Timeout time: SDCLK*2^21
|
||||
SdiocDtoSdclk_2_22 = 9u, ///< Timeout time: SDCLK*2^22
|
||||
SdiocDtoSdclk_2_23 = 10u, ///< Timeout time: SDCLK*2^23
|
||||
SdiocDtoSdclk_2_24 = 11u, ///< Timeout time: SDCLK*2^24
|
||||
SdiocDtoSdclk_2_25 = 12u, ///< Timeout time: SDCLK*2^25
|
||||
SdiocDtoSdclk_2_26 = 13u, ///< Timeout time: SDCLK*2^26
|
||||
SdiocDtoSdclk_2_27 = 14u, ///< Timeout time: SDCLK*2^27
|
||||
} en_sdioc_data_timeout_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC dat line type enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_dat_line_type
|
||||
{
|
||||
SdiocDat0Line = 0u, ///< DAT0 Line
|
||||
SdiocDat1Line = 1u, ///< DAT1 Line
|
||||
SdiocDat2Line = 2u, ///< DAT2 Line
|
||||
SdiocDat3Line = 3u, ///< DAT3 Line
|
||||
} en_sdioc_dat_line_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC software reset type enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_sw_reset
|
||||
{
|
||||
SdiocSwResetDatLine = 0u, ///< Only part of data circuit is reset.
|
||||
SdiocSwResetCmdLine = 1u, ///< Only part of command circuit is reset.
|
||||
SdiocSwResetAll = 2u, ///< Reset the entire Host Controller except for the card detection circuit.
|
||||
} en_sdioc_sw_reset_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC host status enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_host_status
|
||||
{
|
||||
SdiocCommandInhibitCmd = (1u << 0), ///< Command Inhibit(CMD). 1: Cannot issue command; 0:Can issue command using only CMD line
|
||||
SdiocCommandInhibitData = (1u << 1), ///< Command Inhibit(DAT). 1: Cannot issue command which uses the DAT line; 0:Can issue command which uses the DAT line
|
||||
SdiocDataLineActive = (1u << 2), ///< 1: DAT Line Active; 0: DAT Line Inactive
|
||||
SdiocWriteTransferActive = (1u << 8), ///< Write Transfer Active.1: Transferring data; 0: No valid data
|
||||
SdiocReadTransferActive = (1u << 9), ///< Read Transfer Active.1: Transferring data; 0: No valid data
|
||||
SdiocBufferWriteEnble = (1u << 10), ///< 1: Write enable; 0: Write Disable
|
||||
SdiocBufferReadEnble = (1u << 11), ///< 1: Read enable; 0: Read Disable
|
||||
SdiocCardInserted = (1u << 16), ///< 1: Card Inserted; 0: Reset or Debouncing or No Card
|
||||
SdiocCardStateStable = (1u << 17), ///< 1: No Card or Inserted; 0: Reset or Debouncing
|
||||
SdiocCardDetectPinLvl = (1u << 18), ///< 1: Card present; 0: No card present
|
||||
SdiocWriteProtectPinLvl = (1u << 19), ///< 1: Write enabled; 0: Write protected
|
||||
SdiocData0PinLvl = (1u << 20), ///< 1: DAT0 line signal level high; 0: DAT0 line signal level low
|
||||
SdiocData1PinLvl = (1u << 21), ///< 1: DAT1 line signal level high; 0: DAT1 line signal level low
|
||||
SdiocData2PinLvl = (1u << 22), ///< 1: DAT2 line signal level high; 0: DAT2 line signal level low
|
||||
SdiocData3PinLvl = (1u << 23), ///< 1: DAT3 line signal level high; 0: DAT3 line signal level low
|
||||
SdiocCmdPinLvl = (1u << 24), ///< 1: CMD line signal level high; 0: CMD line signal level low
|
||||
} en_sdioc_host_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC normal interrupt selection enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_nor_int_sel
|
||||
{
|
||||
SdiocCommandComplete = (1u << 0), ///< Command Complete. 1: Command complete; 0:No command complete
|
||||
SdiocTransferComplete = (1u << 1), ///< Transfer Complete. 1: Data transfer complete; 0:No transfer complete
|
||||
SdiocBlockGapEvent = (1u << 2), ///< Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event
|
||||
SdiocBufferWriteReady = (1u << 4), ///< Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer
|
||||
SdiocBufferReadReady = (1u << 5), ///< Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer
|
||||
SdiocCardInsertedInt = (1u << 6), ///< Write Transfer Active.1: Transferring data; 0: No valid data
|
||||
SdiocCardRemoval = (1u << 7), ///< Card Removal. 1: Card removed; 0: Card state stable or Debouncing
|
||||
SdiocCardInt = (1u << 8), ///< Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt
|
||||
SdiocErrorInt = (1u << 15), ///< Error Interrupt. 1: Error; 0: No Error
|
||||
} en_sdioc_nor_int_sel_t, en_sdioc_nor_int_flag_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC error interrupt selection enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_err_int_sel
|
||||
{
|
||||
SdiocCmdTimeoutErr = (1u << 0), ///< Command Timeout Error. 1: Timer out; 0:No Error
|
||||
SdiocCmdCrcErr = (1u << 1), ///< Command CRC Error. 1: Command CRC Error Generated; 0:No Error
|
||||
SdiocCmdEndBitErr = (1u << 2), ///< Command End Bit Error. 1: End Bit Error Generated; 0:No Error
|
||||
SdiocCmdIndexErr = (1u << 3), ///< Command Index Error. 1: Command Index Error Generatedr; 0:No Error
|
||||
SdiocDataTimeoutErr = (1u << 4), ///< Data Timeout Error. 1: Timer out; 0:No Error
|
||||
SdiocDataCrcErr = (1u << 5), ///< Data CRC Error. 1: Data CRC Error Generated; 0:No Error
|
||||
SdiocDataEndBitErr = (1u << 6), ///< Data End Bit Error. 1: End Bit Error Generated; 0:No Error
|
||||
SdiocAutoCmd12Err = (1u << 8), ///< Auto CMD12 Error. 1: Error; 0:No Error
|
||||
} en_sdioc_err_int_sel_t, en_sdioc_err_int_flag_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC auto CMD12 error status enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_atuo_cmd_err_status
|
||||
{
|
||||
SdiocAutoCmd12NotExecuted = (1u << 0), ///< Auto CMD12 Not Executed. 1: Not executed; 0:Executed
|
||||
SdiocAutoCmd12Timeout = (1u << 1), ///< Auto CMD12 Timeout Error. 1: Time out; 0:No error
|
||||
SdiocAutoCmd12CrcErr = (1u << 2), ///< Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error
|
||||
SdiocAutoCmd12EndBitErr = (1u << 3), ///< Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer
|
||||
SdiocAutoCmd12IndexErr = (1u << 4), ///< Auto CMD12 Index Error. 1: Error; 0: No error
|
||||
SdiocCmdNotIssuedErr = (1u << 7), ///< Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error
|
||||
} en_sdioc_atuo_cmd_err_sel_t, en_sdioc_atuo_cmd_err_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC speed mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_speed_mode
|
||||
{
|
||||
SdiocNormalSpeedMode = 0u, ///< Normal speed mode
|
||||
SdiocHighSpeedMode = 1u, ///< High speed mode
|
||||
} en_sdioc_speed_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC response register enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_response_reg
|
||||
{
|
||||
SdiocRegResp01 = 0x00u, ///< Response 0/1 Register
|
||||
SdiocRegResp23 = 0x04u, ///< Response 2/3 Register
|
||||
SdiocRegResp45 = 0x08u, ///< Response 4/5 Register
|
||||
SdiocRegResp67 = 0x0Cu, ///< Response 5/6 Register
|
||||
} en_sdioc_response_reg_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief SDIOC output clock frequency enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_clk_freq
|
||||
{
|
||||
SdiocClk400K = 400000u, ///< SDIOC clock: 40KHz
|
||||
SdiocClk20M = 20000000u, ///< SDIOC clock: 20MHz
|
||||
SdiocClk25M = 25000000u, ///< SDIOC clock: 25MHz
|
||||
SdiocClk40M = 40000000u, ///< SDIOC clock: 40MHz
|
||||
SdiocClk50M = 50000000u, ///< SDIOC clock: 50MHz
|
||||
} en_sdioc_clk_freq_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief SDIOC detect the source of card enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_sdioc_detect_signal
|
||||
{
|
||||
SdiocSdcdPinLevel = 0u, ///< SDCD# is selected (for normal use)
|
||||
SdiocCardDetectTestLevel = 1u, ///< The Card Detect Test Level is selected(for test purpose)
|
||||
} en_sdioc_detect_signal_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC Command configure structure
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_sdioc_cmd_cfg
|
||||
{
|
||||
uint8_t u8CmdIndex; ///< Command index
|
||||
|
||||
uint32_t u32Argument; ///< The argument of command
|
||||
|
||||
en_sdioc_cmd_type_t enCmdType; ///< Command type
|
||||
|
||||
en_sdioc_response_index_t enRspIndex; ///< Response index, refer @ref en_sdioc_response_index_t for details
|
||||
|
||||
en_functional_state_t enDataPresentEnable; ///< Enable: Data is present and shall be transferred using the DAT line, Disable: Commands using only CMD line
|
||||
} stc_sdioc_cmd_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC Data configure structure
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_sdioc_data_cfg
|
||||
{
|
||||
uint16_t u16BlkSize; ///< Block size
|
||||
|
||||
uint16_t u16BlkCnt; ///< Block count
|
||||
|
||||
en_functional_state_t enAutoCmd12Enable; ///< Enable: Auto CMD12 enable, Disable: Auto CMD12 disable
|
||||
|
||||
en_sdioc_transfer_dir_t enTransferDir; ///< Specifies the data transfer direction of the SDIOC controller.
|
||||
///< This parameter can be a value of @ref en_sdioc_transfer_dir_t.
|
||||
|
||||
en_sdioc_data_timeout_t enDataTimeOut; ///< Specifies the data timeout period in card bus clock periods.
|
||||
///< This parameter can be a value of @ref en_sdioc_data_timeout_t.
|
||||
|
||||
en_sdioc_transfer_mode_t enTransferMode; ///< Specifies the data transfer mode of the SDIOC controller.
|
||||
///< This parameter can be a value of @ref en_sdioc_transfer_mode_t.
|
||||
} stc_sdioc_data_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC normal interrupt enable structure
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_sdioc_normal_irq_en
|
||||
{
|
||||
union
|
||||
{
|
||||
uint16_t u16NormalIntsgEn; ///< SDIOC normal interrupt enable
|
||||
stc_sdioc_errintsgen_field_t stcNormalIntsgEn; ///< SDIOC normal interrupt enable bit-field structure
|
||||
};
|
||||
} stc_sdioc_normal_irq_en_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC normal interrupt enable structure
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_sdioc_error_irq_en
|
||||
{
|
||||
union
|
||||
{
|
||||
uint16_t u16ErrorIntsgEn; ///< SDIOC error interrupt enable
|
||||
stc_sdioc_errintsgen_field_t stcErrorIntsgEn; ///< SDIOC error interrupt enable bit-field structure
|
||||
};
|
||||
} stc_sdioc_error_irq_en_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC error status callback functions
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_sdioc_normal_irq_cb
|
||||
{
|
||||
func_ptr_t pfnCommandCompleteIrqCb; ///< Pointer to command complete callback function
|
||||
|
||||
func_ptr_t pfnTransferCompleteIrqCb; ///< Pointer to transfer complete callback function
|
||||
|
||||
func_ptr_t pfnBlockGapIrqCb; ///< Pointer to Block gap callback function
|
||||
|
||||
func_ptr_t pfnBufferWriteReadyIrqCb; ///< Pointer to buffer write ready callback function
|
||||
|
||||
func_ptr_t pfnBufferReadReadyIrqCb; ///< Pointer to buffer read ready callback function
|
||||
|
||||
func_ptr_t pfnCardInsertIrqCb; ///< Pointer to card insertion callback function
|
||||
|
||||
func_ptr_t pfnCardRemovalIrqCb; ///< Pointer to card removal callback function
|
||||
|
||||
func_ptr_t pfnCardIrqCb; ///< Pointer to card interrupt callback function
|
||||
} stc_sdioc_normal_irq_cb_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC error status callback functions
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_sdioc_error_irq_cb
|
||||
{
|
||||
func_ptr_t pfnCmdTimeoutErrIrqCb; ///< Pointer to command timeout error interrupt callback function
|
||||
|
||||
func_ptr_t pfnCmdCrcErrIrqCb; ///< Pointer to command CRC error interrupt callback function
|
||||
|
||||
func_ptr_t pfnCmdEndBitErrIrqCb; ///< Pointer to command end bit error interrupt callback function
|
||||
|
||||
func_ptr_t pfnCmdIndexErrIrqCb; ///< Pointer to command index error interrupt callback function
|
||||
|
||||
func_ptr_t pfnDataTimeoutErrIrqCb; ///< Pointer to data timeout error interrupt callback function
|
||||
|
||||
func_ptr_t pfnDataCrcErrIrqCb; ///< Pointer to data CRC error interrupt callback function
|
||||
|
||||
func_ptr_t pfnDataEndBitErrIrqCb; ///< Pointer to data end bit error interrupt callback function
|
||||
|
||||
func_ptr_t pfnAutoCmdErrIrqCb; ///< Pointer to command error interrupt callback function
|
||||
} stc_sdioc_error_irq_cb_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SDIOC initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_sdioc_init
|
||||
{
|
||||
stc_sdioc_normal_irq_en_t *pstcNormalIrqEn; ///< Pointer to normal interrupt enable structure
|
||||
|
||||
stc_sdioc_normal_irq_cb_t *pstcNormalIrqCb; ///< Pointer to normal interrupt callback function structure
|
||||
|
||||
stc_sdioc_error_irq_en_t *pstcErrorIrqEn; ///< Pointer to error interrupt enable structure
|
||||
|
||||
stc_sdioc_error_irq_cb_t *pstcErrorIrqCb; ///< Pointer to error interrupt callback structure
|
||||
} stc_sdioc_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void SDIOC_IrqHandler(M4_SDIOC_TypeDef *SDIOCx);
|
||||
en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx,
|
||||
const stc_sdioc_init_t *pstcInitCfg);
|
||||
en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx);
|
||||
void SDIOC_SetMode(const M4_SDIOC_TypeDef *SDIOCx, en_sdioc_mode_t enMode);
|
||||
en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx,
|
||||
const stc_sdioc_cmd_cfg_t *pstcCmdCfg);
|
||||
uint32_t SDIOC_GetResponse(const M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_response_reg_t enRespReg);
|
||||
en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx,
|
||||
uint8_t au8Data[],
|
||||
uint32_t u32Len);
|
||||
en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx,
|
||||
uint8_t au8Data[],
|
||||
uint32_t u32Len);
|
||||
en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx,
|
||||
const stc_sdioc_data_cfg_t *pstcDataCfg);
|
||||
en_result_t SDIOC_SdclkCmd(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t SDIOC_SetClkDiv(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_clk_div_t enClkDiv);
|
||||
en_sdioc_clk_div_t SDIOC_GetClkDiv(M4_SDIOC_TypeDef *SDIOCx);
|
||||
en_result_t SDIOC_SetClk(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ClkFreq);
|
||||
en_result_t SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_bus_width_t enBusWidth);
|
||||
en_sdioc_bus_width_t SDIOC_GetBusWidth(M4_SDIOC_TypeDef *SDIOCx);
|
||||
en_result_t SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_speed_mode_t enSpeedMode);
|
||||
en_sdioc_speed_mode_t SDIOC_GetSpeedMode(M4_SDIOC_TypeDef *SDIOCx);
|
||||
en_result_t SDIOC_SetDataTimeout(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_data_timeout_t enTimeout);
|
||||
en_sdioc_data_timeout_t SDIOC_GetDataTimeout(M4_SDIOC_TypeDef *SDIOCx);
|
||||
en_result_t SDIOC_SetCardDetectSignal(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_detect_signal_t enDetectSignal);
|
||||
en_flag_status_t SDIOC_GetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx);
|
||||
en_result_t SDIOC_BusPowerOn(M4_SDIOC_TypeDef *SDIOCx);
|
||||
en_result_t SDIOC_BusPowerOff(M4_SDIOC_TypeDef *SDIOCx);
|
||||
en_result_t SDIOC_StopAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx);
|
||||
en_result_t SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t SDIOC_InterruptAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_sw_reset_t enSwResetType);
|
||||
en_flag_status_t SDIOC_GetStatus(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_host_status_t enHostStatus);
|
||||
en_result_t SDIOC_NormalIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_nor_int_sel_t enNorInt,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t SDIOC_NormalIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_nor_int_sel_t enNorInt,
|
||||
en_functional_state_t enCmd);
|
||||
en_flag_status_t SDIOC_GetNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_nor_int_flag_t enNorInt);
|
||||
en_result_t SDIOC_ClearNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_nor_int_flag_t enNorInt);
|
||||
en_result_t SDIOC_ErrIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_err_int_sel_t enErrInt,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t SDIOC_ErrIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_err_int_sel_t enErrInt,
|
||||
en_functional_state_t enCmd);
|
||||
en_flag_status_t SDIOC_GetErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_err_int_flag_t enErrInt);
|
||||
en_result_t SDIOC_ClearErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_err_int_flag_t enErrInt);
|
||||
en_result_t SDIOC_ForceErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_err_int_sel_t enErrInt);
|
||||
en_flag_status_t SDIOC_GetAutoCmdErrStatus(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_atuo_cmd_err_status_t enAutoCmdErr);
|
||||
en_result_t SDIOC_ForceAutoCmdErr(M4_SDIOC_TypeDef *SDIOCx,
|
||||
en_sdioc_atuo_cmd_err_sel_t enAutoCmdErr);
|
||||
|
||||
//@} // SdiocGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_SDIOC_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_SDIOC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,426 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_spi.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link SpiGroup Serial Peripheral Interface description @endlink
|
||||
**
|
||||
** - 2018-10-29 CDT First version for Device Driver Library of Spi.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_SPI_H__
|
||||
#define __HC32F460_SPI_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_SPI_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup SpiGroup Serial Peripheral Interface(SPI)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI parity enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_parity
|
||||
{
|
||||
SpiParityEven = 0u, ///< Select even parity send and receive
|
||||
SpiParityOdd = 1u, ///< Select odd parity send and receive
|
||||
} en_spi_parity_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI master/slave mode enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_master_slave_mode
|
||||
{
|
||||
SpiModeSlave = 0u, ///< Spi slave mode
|
||||
SpiModeMaster = 1u, ///< Spi master mode
|
||||
} en_spi_master_slave_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI transmission mode enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_trans_mode
|
||||
{
|
||||
SpiTransFullDuplex = 0u, ///< Full duplex sync serial communication
|
||||
SpiTransOnlySend = 1u, ///< Only send serial communication
|
||||
} en_spi_trans_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI work mode enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_work_mode
|
||||
{
|
||||
SpiWorkMode4Line = 0u, ///< 4 lines spi work mode
|
||||
SpiWorkMode3Line = 1u, ///< 3 lines spi work mode(clock sync running)
|
||||
} en_spi_work_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI SS interval time enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_ss_interval_time
|
||||
{
|
||||
SpiSsIntervalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1
|
||||
SpiSsIntervalSck2PlusPck2 = 1u, ///< Spi SS interval time 2 SCK plus 2 PCLK1
|
||||
SpiSsIntervalSck3PlusPck2 = 2u, ///< Spi SS interval time 3 SCK plus 2 PCLK1
|
||||
SpiSsIntervalSck4PlusPck2 = 3u, ///< Spi SS interval time 4 SCK plus 2 PCLK1
|
||||
SpiSsIntervalSck5PlusPck2 = 4u, ///< Spi SS interval time 5 SCK plus 2 PCLK1
|
||||
SpiSsIntervalSck6PlusPck2 = 5u, ///< Spi SS interval time 6 SCK plus 2 PCLK1
|
||||
SpiSsIntervalSck7PlusPck2 = 6u, ///< Spi SS interval time 7 SCK plus 2 PCLK1
|
||||
SpiSsIntervalSck8PlusPck2 = 7u, ///< Spi SS interval time 8 SCK plus 2 PCLK1
|
||||
} en_spi_ss_interval_time_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI SS setup delay SCK enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_ss_setup_delay
|
||||
{
|
||||
SpiSsSetupDelaySck1 = 0u, ///< Spi SS setup delay 1 SCK
|
||||
SpiSsSetupDelaySck2 = 1u, ///< Spi SS setup delay 2 SCK
|
||||
SpiSsSetupDelaySck3 = 2u, ///< Spi SS setup delay 3 SCK
|
||||
SpiSsSetupDelaySck4 = 3u, ///< Spi SS setup delay 4 SCK
|
||||
SpiSsSetupDelaySck5 = 4u, ///< Spi SS setup delay 5 SCK
|
||||
SpiSsSetupDelaySck6 = 5u, ///< Spi SS setup delay 6 SCK
|
||||
SpiSsSetupDelaySck7 = 6u, ///< Spi SS setup delay 7 SCK
|
||||
SpiSsSetupDelaySck8 = 7u, ///< Spi SS setup delay 8 SCK
|
||||
} en_spi_ss_setup_delay_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI SS hold delay SCK enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_ss_hold_delay
|
||||
{
|
||||
SpiSsHoldDelaySck1 = 0u, ///< Spi SS hold delay 1 SCK
|
||||
SpiSsHoldDelaySck2 = 1u, ///< Spi SS hold delay 2 SCK
|
||||
SpiSsHoldDelaySck3 = 2u, ///< Spi SS hold delay 3 SCK
|
||||
SpiSsHoldDelaySck4 = 3u, ///< Spi SS hold delay 4 SCK
|
||||
SpiSsHoldDelaySck5 = 4u, ///< Spi SS hold delay 5 SCK
|
||||
SpiSsHoldDelaySck6 = 5u, ///< Spi SS hold delay 6 SCK
|
||||
SpiSsHoldDelaySck7 = 6u, ///< Spi SS hold delay 7 SCK
|
||||
SpiSsHoldDelaySck8 = 7u, ///< Spi SS hold delay 8 SCK
|
||||
} en_spi_ss_hold_delay_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI slave select polarity enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_ss_polarity
|
||||
{
|
||||
SpiSsLowValid = 0u, ///< SS0~3 signal low level valid
|
||||
SpiSsHighValid = 1u, ///< SS0~3 signal high level valid
|
||||
} en_spi_ss_polarity_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI data register read object enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_read_object
|
||||
{
|
||||
SpiReadReceiverBuffer = 0u, ///< Read receive buffer
|
||||
SpiReadSendBuffer = 1u, ///< Read send buffer(must be read when TDEF=1)
|
||||
} en_spi_read_object_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI frame number enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_frame_number
|
||||
{
|
||||
SpiFrameNumber1 = 0u, ///< 1 frame data
|
||||
SpiFrameNumber2 = 1u, ///< 2 frame data
|
||||
SpiFrameNumber3 = 2u, ///< 3 frame data
|
||||
SpiFrameNumber4 = 3u, ///< 4 frame data
|
||||
} en_spi_frame_number_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI SS setup delay SCK option enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_ss_setup_delay_option
|
||||
{
|
||||
SpiSsSetupDelayTypicalSck1 = 0u, ///< SS setup delay 1 SCK
|
||||
SpiSsSetupDelayCustomValue = 1u, ///< SS setup delay SCKDL register set value
|
||||
} en_spi_ss_setup_delay_option_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI SS hold delay SCK option enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_ss_hold_delay_option
|
||||
{
|
||||
SpiSsHoldDelayTypicalSck1 = 0u, ///< SS hold delay 1 SCK
|
||||
SpiSsHoldDelayCustomValue = 1u, ///< SS hold delay SSDL register set value
|
||||
} en_spi_ss_hold_delay_option_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI SS interval time option enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_ss_interval_time_option
|
||||
{
|
||||
SpiSsIntervalTypicalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1
|
||||
SpiSsIntervalCustomValue = 1u, ///< Spi SS interval time NXTDL register set value
|
||||
} en_spi_ss_interval_time_option_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI first bit position enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_first_bit_position
|
||||
{
|
||||
SpiFirstBitPositionMSB = 0u, ///< Spi first bit to MSB
|
||||
SpiFirstBitPositionLSB = 1u, ///< Spi first bit to LSB
|
||||
} en_spi_first_bit_position_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI data length enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_data_length
|
||||
{
|
||||
SpiDataLengthBit4 = 0u, ///< 4 bits
|
||||
SpiDataLengthBit5 = 1u, ///< 5 bits
|
||||
SpiDataLengthBit6 = 2u, ///< 6 bits
|
||||
SpiDataLengthBit7 = 3u, ///< 7 bits
|
||||
SpiDataLengthBit8 = 4u, ///< 8 bits
|
||||
SpiDataLengthBit9 = 5u, ///< 9 bits
|
||||
SpiDataLengthBit10 = 6u, ///< 10 bits
|
||||
SpiDataLengthBit11 = 7u, ///< 11 bits
|
||||
SpiDataLengthBit12 = 8u, ///< 12 bits
|
||||
SpiDataLengthBit13 = 9u, ///< 13 bits
|
||||
SpiDataLengthBit14 = 10u, ///< 14 bits
|
||||
SpiDataLengthBit15 = 11u, ///< 15 bits
|
||||
SpiDataLengthBit16 = 12u, ///< 16 bits
|
||||
SpiDataLengthBit20 = 13u, ///< 20 bits
|
||||
SpiDataLengthBit24 = 14u, ///< 24 bits
|
||||
SpiDataLengthBit32 = 15u, ///< 32 bits
|
||||
} en_spi_data_length_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI SS valid channel select enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_ss_valid_channel
|
||||
{
|
||||
SpiSsValidChannel0 = 0u, ///< Select SS0 valid
|
||||
SpiSsValidChannel1 = 1u, ///< Select SS1 valid
|
||||
SpiSsValidChannel2 = 2u, ///< Select SS2 valid
|
||||
SpiSsValidChannel3 = 3u, ///< Select SS3 valid
|
||||
} en_spi_ss_valid_channel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI clock division enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_clk_div
|
||||
{
|
||||
SpiClkDiv2 = 0u, ///< Spi pclk1 division 2
|
||||
SpiClkDiv4 = 1u, ///< Spi pclk1 division 4
|
||||
SpiClkDiv8 = 2u, ///< Spi pclk1 division 8
|
||||
SpiClkDiv16 = 3u, ///< Spi pclk1 division 16
|
||||
SpiClkDiv32 = 4u, ///< Spi pclk1 division 32
|
||||
SpiClkDiv64 = 5u, ///< Spi pclk1 division 64
|
||||
SpiClkDiv128 = 6u, ///< Spi pclk1 division 128
|
||||
SpiClkDiv256 = 7u, ///< Spi pclk1 division 256
|
||||
} en_spi_clk_div_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI SCK polarity enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_sck_polarity
|
||||
{
|
||||
SpiSckIdleLevelLow = 0u, ///< SCK is low level when SCK idle
|
||||
SpiSckIdleLevelHigh = 1u, ///< SCK is high level when SCK idle
|
||||
} en_spi_sck_polarity_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI SCK phase enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_sck_phase
|
||||
{
|
||||
SpiSckOddSampleEvenChange = 0u, ///< SCK Odd edge data sample,even edge data change
|
||||
SpiSckOddChangeEvenSample = 1u, ///< SCK Odd edge data change,even edge data sample
|
||||
} en_spi_sck_phase_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI interrupt request type enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_irq_type
|
||||
{
|
||||
SpiIrqIdle = 0u, ///< Spi idle interrupt request
|
||||
SpiIrqReceive = 1u, ///< Spi receive interrupt request
|
||||
SpiIrqSend = 2u, ///< Spi send interrupt request
|
||||
SpiIrqError = 3u, ///< Spi error interrupt request
|
||||
} en_spi_irq_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI flag type enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_flag_type
|
||||
{
|
||||
SpiFlagReceiveBufferFull = 0u, ///< Receive buffer full flag
|
||||
SpiFlagSendBufferEmpty = 1u, ///< Send buffer empty flag
|
||||
SpiFlagUnderloadError = 2u, ///< Underload error flag
|
||||
SpiFlagParityError = 3u, ///< Parity error flag
|
||||
SpiFlagModeFaultError = 4u, ///< Mode fault error flag
|
||||
SpiFlagSpiIdle = 5u, ///< SPI idle flag
|
||||
SpiFlagOverloadError = 6u, ///< Overload error flag
|
||||
} en_spi_flag_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI SS channel enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_spi_ss_channel
|
||||
{
|
||||
SpiSsChannel0 = 0u, ///< SS0 channel
|
||||
SpiSsChannel1 = 1u, ///< SS1 channel
|
||||
SpiSsChannel2 = 2u, ///< SS2 channel
|
||||
SpiSsChannel3 = 3u, ///< SS3 channel
|
||||
} en_spi_ss_channel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI bus delay structure definition
|
||||
**
|
||||
** \note Slave mode stc_spi_delay_config_t is invalid
|
||||
******************************************************************************/
|
||||
typedef struct stc_spi_delay_config
|
||||
{
|
||||
en_spi_ss_setup_delay_option_t enSsSetupDelayOption; ///< SS setup delay time option
|
||||
en_spi_ss_setup_delay_t enSsSetupDelayTime; ///< SS setup delay time(the value valid when enSsSetupDelayOption is custom)
|
||||
en_spi_ss_hold_delay_option_t enSsHoldDelayOption; ///< SS hold delay time option
|
||||
en_spi_ss_hold_delay_t enSsHoldDelayTime; ///< SS hold delay time(the value valid when enSsHoldDelayOption is custom)
|
||||
en_spi_ss_interval_time_option_t enSsIntervalTimeOption; ///< SS interval time option
|
||||
en_spi_ss_interval_time_t enSsIntervalTime; ///< SS interval time(the value valid when enSsIntervalTimeOption is custom)
|
||||
} stc_spi_delay_config_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI SS config structure definition
|
||||
**
|
||||
** \note 3 lines mode stc_spi_ss_config_t is invalid
|
||||
******************************************************************************/
|
||||
typedef struct stc_spi_ss_config
|
||||
{
|
||||
en_spi_ss_valid_channel_t enSsValidBit; ///< SS valid channel select
|
||||
en_spi_ss_polarity_t enSs0Polarity; ///< SS0 signal polarity
|
||||
en_spi_ss_polarity_t enSs1Polarity; ///< SS1 signal polarity
|
||||
en_spi_ss_polarity_t enSs2Polarity; ///< SS2 signal polarity
|
||||
en_spi_ss_polarity_t enSs3Polarity; ///< SS3 signal polarity
|
||||
} stc_spi_ss_config_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPI init structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_spi_init_t
|
||||
{
|
||||
stc_spi_delay_config_t stcDelayConfig; ///< SPI delay structure(Slave mode is invalid)
|
||||
stc_spi_ss_config_t stcSsConfig; ///< SS polarity and channel structure(3 lines mode invalid)
|
||||
en_spi_read_object_t enReadBufferObject; ///< Data register read object select(must be read when TDEF=1)
|
||||
en_spi_sck_polarity_t enSckPolarity; ///< Sck polarity
|
||||
en_spi_sck_phase_t enSckPhase; ///< Sck phase(This value must be SpiSckOddChangeEvenSample in 3-line mode)
|
||||
en_spi_clk_div_t enClkDiv; ///< SPI clock division
|
||||
en_spi_data_length_t enDataLength; ///< Data length
|
||||
en_spi_first_bit_position_t enFirstBitPosition; ///< Data first bit position
|
||||
en_spi_frame_number_t enFrameNumber; ///< Data frame number
|
||||
en_spi_work_mode_t enWorkMode; ///< Spi work mode
|
||||
en_spi_trans_mode_t enTransMode; ///< transmission mode
|
||||
en_spi_master_slave_mode_t enMasterSlaveMode; ///< Spi master/slave mode
|
||||
en_functional_state_t enCommAutoSuspendEn; ///< Enable/disable Communication auto suspend
|
||||
en_functional_state_t enModeFaultErrorDetectEn; ///< Enable/disable Mode fault error detect
|
||||
en_functional_state_t enParitySelfDetectEn; ///< Enable/disable Parity self detect
|
||||
en_functional_state_t enParityEn; ///< Enable/disable Parity(if enable parity and SPI_CR1.TXMDS=1, receive data don't parity)
|
||||
en_spi_parity_t enParity; ///< Parity mode select
|
||||
} stc_spi_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/* Base functions */
|
||||
en_result_t SPI_DeInit(M4_SPI_TypeDef *SPIx);
|
||||
en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInitCfg);
|
||||
en_result_t SPI_GeneralLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta);
|
||||
en_result_t SPI_ReverseLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta);
|
||||
en_result_t SPI_Cmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta);
|
||||
|
||||
/* Send and receive data functions */
|
||||
en_result_t SPI_SendData8(M4_SPI_TypeDef *SPIx, uint8_t u8Data);
|
||||
en_result_t SPI_SendData16(M4_SPI_TypeDef *SPIx, uint16_t u16Data);
|
||||
en_result_t SPI_SendData32(M4_SPI_TypeDef *SPIx, uint32_t u32Data);
|
||||
uint8_t SPI_ReceiveData8(const M4_SPI_TypeDef *SPIx);
|
||||
uint16_t SPI_ReceiveData16(const M4_SPI_TypeDef *SPIx);
|
||||
uint32_t SPI_ReceiveData32(const M4_SPI_TypeDef *SPIx);
|
||||
|
||||
/* Communication configure functions */
|
||||
en_result_t SPI_SetSsPolarity(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel,
|
||||
en_spi_ss_polarity_t enPolarity);
|
||||
en_result_t SPI_SetSsValidChannel(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel);
|
||||
en_result_t SPI_SetReadDataRegObject(M4_SPI_TypeDef *SPIx, en_spi_read_object_t enObject);
|
||||
en_result_t SPI_SetFrameNumber(M4_SPI_TypeDef *SPIx, en_spi_frame_number_t enFrameNum);
|
||||
en_result_t SPI_SetDataLength(M4_SPI_TypeDef *SPIx, en_spi_data_length_t enDataLength);
|
||||
en_result_t SPI_SetFirstBitPosition(M4_SPI_TypeDef *SPIx, en_spi_first_bit_position_t enPosition);
|
||||
en_result_t SPI_SetClockDiv(M4_SPI_TypeDef *SPIx, en_spi_clk_div_t enClkDiv);
|
||||
|
||||
/* Interrupt and flags functions */
|
||||
en_result_t SPI_IrqCmd(M4_SPI_TypeDef *SPIx, en_spi_irq_type_t enIrq,
|
||||
en_functional_state_t enNewSta);
|
||||
en_flag_status_t SPI_GetFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag);
|
||||
en_result_t SPI_ClearFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag);
|
||||
|
||||
//@} // SpiGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_SPI_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_SPI_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,190 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_sram.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link SramGroup Internal SRAM description @endlink
|
||||
**
|
||||
** - 2018-10-17 CDT First version for Device Driver Library of SRAM.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HC32F460_SRAM_H__
|
||||
#define __HC32F460_SRAM_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_SRAM_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
* \defgroup SramGroup Internal SRAM
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
///< SRAM wait cycle register, parity/ECC check register protect code definition
|
||||
#define SRAM_PROTECT_CODE (0x0000003Bu)
|
||||
|
||||
/*******************************************************************************
|
||||
Start addr. End addr. Size Function
|
||||
SRAM1 0x20000000 0x2000FFFF 64KB Even Parity Check
|
||||
SRAM2 0x20010000 0x2001FFFF 64KB Even Parity Check
|
||||
SRAM3 0x20020000 0x20026FFF 28KB ECC Check
|
||||
SRAM_Ret 0x200F0000 0x200F0FFF 4KB Even Parity Check
|
||||
SRAM_HS 0x1FFF8000 0x1FFFFFFF 32KB Even Parity Check
|
||||
******************************************************************************/
|
||||
///< SRAM1 base address definition
|
||||
#define SRAM1_BASE_ADDR (*((volatile unsigned int*)(0x20000000UL)))
|
||||
|
||||
///< SRAM2 base address definition
|
||||
#define SRAM2_BASE_ADDR (*((volatile unsigned int*)(0x20010000UL)))
|
||||
|
||||
///< SRAM3 base address definition
|
||||
#define SRAM3_BASE_ADDR (*((volatile unsigned int*)(0x20020000UL)))
|
||||
|
||||
///< Retention SRAM base address definition
|
||||
#define SRAMRET_BASE_ADDR (*((volatile unsigned int*)(0x200F0000UL)))
|
||||
|
||||
///< High speed SRAM base address definition
|
||||
#define SRAMHS_BASE_ADDR (*((volatile unsigned int*)(0x1FFF8000UL)))
|
||||
|
||||
|
||||
typedef enum en_sram_index
|
||||
{
|
||||
Sram12Idx = 1u << 0,
|
||||
Sram3Idx = 1u << 1,
|
||||
SramHsIdx = 1u << 2,
|
||||
SramRetIdx = 1u << 3,
|
||||
}en_sram_index_t;
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to the write/read cycles of SRAM
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_sram_rw_cycle
|
||||
{
|
||||
SramCycle1 = 0u,
|
||||
SramCycle2 = 1u,
|
||||
SramCycle3 = 2u,
|
||||
SramCycle4 = 3u,
|
||||
SramCycle5 = 4u,
|
||||
SramCycle6 = 5u,
|
||||
SramCycle7 = 6u,
|
||||
SramCycle8 = 7u,
|
||||
}en_sram_rw_cycle_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to ECC check mode
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_ecc_mode
|
||||
{
|
||||
EccMode0 = 0u, ///< disable ECC check function
|
||||
EccMode1 = 1u, ///< no 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected
|
||||
///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected
|
||||
EccMode2 = 2u, ///< generate 1 bit ECC flag, but no interrupt/reset if 1 bit-ECC is detected
|
||||
///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected
|
||||
EccMode3 = 3u, ///< generate 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected
|
||||
///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected
|
||||
}en_ecc_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to operation after ECC/Parity error
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_ecc_py_err_op
|
||||
{
|
||||
SramNmi = 0u, ///< Generate NMI after ECC/Parity error detected
|
||||
SramReset = 1u, ///< Generate Reset after ECC/Parity error detected
|
||||
}en_ecc_py_err_op_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to the ECC/Parity error status of each SRAM
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_sram_err_status
|
||||
{
|
||||
Sram3EccErr1 = 1u << 0, ///< SRAM3 1 bit ECC error
|
||||
Sram3EccErr2 = 1u << 1, ///< SRAM3 2 bit ECC error
|
||||
Sram12ParityErr = 1u << 2, ///< SRAM1/2 parity error
|
||||
SramHSParityErr = 1u << 3, ///< High speed SRAM parity error
|
||||
SramRetParityErr = 1u << 4, ///< Retention SRAM parity error
|
||||
}en_sram_err_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SRAM configuration
|
||||
**
|
||||
** \note The SRAM configuration structure
|
||||
******************************************************************************/
|
||||
typedef struct stc_sram_config
|
||||
{
|
||||
uint8_t u8SramIdx; ///< SRAM index, ref @ en_sram_index_t for details
|
||||
en_sram_rw_cycle_t enSramRC; ///< SRAM read wait cycle setting
|
||||
en_sram_rw_cycle_t enSramWC; ///< SRAM write wait cycle setting
|
||||
en_ecc_mode_t enSramEccMode; ///< SRAM ECC mode setting
|
||||
en_ecc_py_err_op_t enSramEccOp; ///< SRAM3 ECC error handling setting
|
||||
en_ecc_py_err_op_t enSramPyOp; ///< SRAM1/2/HS/Ret Parity error handling setting
|
||||
|
||||
}stc_sram_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
extern en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig);
|
||||
extern en_result_t SRAM_DeInit(void);
|
||||
extern en_result_t SRAM_WT_Disable(void);
|
||||
extern en_result_t SRAM_WT_Enable(void);
|
||||
extern en_result_t SRAM_CK_Disable(void);
|
||||
extern en_result_t SRAM_CK_Enable(void);
|
||||
extern en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus);
|
||||
extern en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus);
|
||||
|
||||
//@} // SramGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_SRAM_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_SRAM_H__ */
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,86 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_swdt.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link SwdtGroup Special Watchdog Counter description @endlink
|
||||
**
|
||||
** - 2018-10-16 CDT First version for Device Driver Library of SWDT.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_SWDT_H__
|
||||
#define __HC32F460_SWDT_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_SWDT_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup SwdtGroup Special Watchdog Counter(SWDT)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SWDT flag type enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_swdt_flag_type
|
||||
{
|
||||
SwdtFlagCountUnderflow = 0u, ///< Count underflow flag
|
||||
SwdtFlagRefreshError = 1u, ///< Refresh error flag
|
||||
} en_swdt_flag_type_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/* Base functions */
|
||||
en_result_t SWDT_RefreshCounter(void);
|
||||
uint16_t SWDT_GetCountValue(void);
|
||||
|
||||
/* Flags functions */
|
||||
en_flag_status_t SWDT_GetFlag(en_swdt_flag_type_t enFlag);
|
||||
en_result_t SWDT_ClearFlag(en_swdt_flag_type_t enFlag);
|
||||
|
||||
//@} // SwdtGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_SWDT_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_SWDT_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,209 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer0.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer0Group description @endlink
|
||||
**
|
||||
** - 2018-10-11 CDT First version for Device Driver Library of TIMER0.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HC32F460_TIMER0_H__
|
||||
#define __HC32F460_TIMER0_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_TIMER0_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup Timer0Group Timer0
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 channel enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_tim0_channel
|
||||
{
|
||||
Tim0_ChannelA = 0x00u,
|
||||
Tim0_ChannelB = 0x01u
|
||||
}en_tim0_channel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 Async Mode clock enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_tim0_async_clock_src
|
||||
{
|
||||
Tim0_LRC = 0x00u,
|
||||
Tim0_XTAL32 = 0x01u
|
||||
}en_tim0_async_clock_src_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 Sync Mode clock enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_tim0_sync_clock_src
|
||||
{
|
||||
Tim0_Pclk1 = 0x00u,
|
||||
Tim0_InsideHardTrig = 0x01u
|
||||
}en_tim0_sync_clock_src_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 counter mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_tim0_counter_mode
|
||||
{
|
||||
Tim0_Sync = 0x00u,
|
||||
Tim0_Async = 0x01u
|
||||
}en_tim0_counter_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 trigger event mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_tim0_function
|
||||
{
|
||||
Tim0_OutputCapare = 0x00u,
|
||||
Tim0_InputCaptrue = 0x01u
|
||||
}en_tim0_function_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 clock division enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_tim0_clock_div
|
||||
{
|
||||
Tim0_ClkDiv0 = 0u,
|
||||
Tim0_ClkDiv2,
|
||||
Tim0_ClkDiv4,
|
||||
Tim0_ClkDiv8,
|
||||
Tim0_ClkDiv16,
|
||||
Tim0_ClkDiv32,
|
||||
Tim0_ClkDiv64,
|
||||
Tim0_ClkDiv128,
|
||||
Tim0_ClkDiv256,
|
||||
Tim0_ClkDiv512,
|
||||
Tim0_ClkDiv1024
|
||||
}en_tim0_clock_div_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 common trigger source select enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_tim0_com_trigger
|
||||
{
|
||||
Tim0ComTrigger_1 = 1u, ///< Select common trigger 1.
|
||||
Tim0ComTrigger_2 = 2u, ///< Select common trigger 2.
|
||||
Tim0ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2.
|
||||
} en_tim0_com_trigger_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 trigger function init structrue definition
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_tim0_trigger_init
|
||||
{
|
||||
en_tim0_function_t Tim0_OCMode; ///<specifies the TIM mode value of @ref en_tim0_function_t
|
||||
en_event_src_t Tim0_SelTrigSrc; ///<specifies the TIM Clk Src, and this parameter can be a value of @ref en_event_src_t
|
||||
bool Tim0_InTrigEnable;///<specifies the TIM enable trigger
|
||||
bool Tim0_InTrigClear; ///<specifies the TIM enable trigger clear
|
||||
bool Tim0_InTrigStop; ///<specifies the TIM enable trigger stop
|
||||
bool Tim0_InTrigStart; ///<specifies the TIM enable trigger start
|
||||
}stc_tim0_trigger_init_t;
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 base counter function init structrue definition
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_tim0_base_init
|
||||
{
|
||||
en_tim0_clock_div_t Tim0_ClockDivision; ///<specifies the TIM clock division, and this parameter can be a value of @ref en_tim0_clock_div_t*/
|
||||
en_tim0_sync_clock_src_t Tim0_SyncClockSource; ///<specifies the TIM sync clock source, and this parameter can be a value of @ref en_tim0_sync_clock_src_t*/
|
||||
en_tim0_async_clock_src_t Tim0_AsyncClockSource;///<specifies the TIM async clock source, and this parameter can be a value of @ref en_tim0_async_clock_src_t*/
|
||||
en_tim0_counter_mode_t Tim0_CounterMode; ///<specifies the TIM counter mode, and this parameter can be a value of @ref en_tim0_counter_mode_t*/
|
||||
uint16_t Tim0_CmpValue; ///<specifies the TIM counter value This value can be set 0-0xFFFF
|
||||
}stc_tim0_base_init_t;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_flag_status_t TIMER0_GetFlag(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh);
|
||||
en_result_t TIMER0_ClearFlag(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh);
|
||||
en_result_t TIMER0_Cmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t TIMER0_SetFunc(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,
|
||||
en_tim0_function_t enFunc);
|
||||
en_result_t TIMER0_IntCmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,
|
||||
en_functional_state_t enCmd);
|
||||
uint16_t TIMER0_GetCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh);
|
||||
en_result_t TIMER0_WriteCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh,uint16_t u16Cnt);
|
||||
uint16_t TIMER0_GetCmpReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh);
|
||||
en_result_t TIMER0_WriteCmpReg(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,uint16_t u16Cnt);
|
||||
en_result_t TIMER0_BaseInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh,
|
||||
const stc_tim0_base_init_t* pstcBaseInit);
|
||||
en_result_t TIMER0_DeInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh);
|
||||
en_result_t TIMER0_HardTriggerInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh,
|
||||
const stc_tim0_trigger_init_t* pStcInit);
|
||||
void TIMER0_SetTriggerSrc(en_event_src_t enEvent);
|
||||
void TIMER0_ComTriggerCmd(en_tim0_com_trigger_t enComTrigger, en_functional_state_t enState);
|
||||
|
||||
//@} // Timer0Group
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_TIMER0_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_TIMER0_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,209 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer4_cnt.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer4CntGroup Timer4CNT description @endlink
|
||||
**
|
||||
** - 2018-11-02 CDT First version for Device Driver Library of Timer4CNT.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_TIMER4_CNT_H__
|
||||
#define __HC32F460_TIMER4_CNT_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_TIMER4_CNT_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup Timer4CntGroup Timer4 Counter(Timer4CNT)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 count mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_cnt_mode
|
||||
{
|
||||
Timer4CntSawtoothWave = 0u, ///< Timer4 count mode:sawtooth wave
|
||||
Timer4CntTriangularWave = 1u, ///< Timer4 count mode:triangular wave
|
||||
} en_timer4_cnt_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CNT Clock Setting
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 CNT clock division enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_cnt_clk_div
|
||||
{
|
||||
Timer4CntPclkDiv1 = 0u, ///< Timer4 clock: PCLK
|
||||
Timer4CntPclkDiv2 = 1u, ///< Timer4 clock: PCLK/2
|
||||
Timer4CntPclkDiv4 = 2u, ///< Timer4 clock: PCLK/4
|
||||
Timer4CntPclkDiv8 = 3u, ///< Timer4 clock: PCLK/8
|
||||
Timer4CntPclkDiv16 = 4u, ///< Timer4 clock: PCLK/16
|
||||
Timer4CntPclkDiv32 = 5u, ///< Timer4 clock: PCLK/32
|
||||
Timer4CntPclkDiv64 = 6u, ///< Timer4 clock: PCLK/64
|
||||
Timer4CntPclkDiv128 = 7u, ///< Timer4 clock: PCLK/128
|
||||
Timer4CntPclkDiv256 = 8u, ///< Timer4 clock: PCLK/256
|
||||
Timer4CntPclkDiv512 = 9u, ///< Timer4 clock: PCLK/512
|
||||
Timer4CntPclkDiv1024 = 10u, ///< Timer4 clock: PCLK/1024
|
||||
} en_timer4_cnt_clk_div_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 CNT clock soucre selection enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_cnt_clk
|
||||
{
|
||||
Timer4CntPclk = 0u, ///< Uses the internal clock (PCLK) as CNT's count clock.
|
||||
Timer4CntExtclk = 1u, ///< Uses an external input clock (EXCK) as CNT's count clock.
|
||||
} en_timer4_cnt_clk_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 CNT interrupt selection enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_cnt_int
|
||||
{
|
||||
Timer4CntZeroMatchInt = (1ul << 8), ///< zero match interrupt
|
||||
Timer4CntPeakMatchInt = (1ul << 13), ///< peak match interrupt
|
||||
} en_timer4_cnt_int_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 CNT interrupt mask times enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_cnt_int_mask
|
||||
{
|
||||
Timer4CntIntMask0 = 0u, ///< CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak.
|
||||
Timer4CntIntMask1 = 1u, ///< CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count).
|
||||
Timer4CntIntMask2 = 2u, ///< CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count).
|
||||
Timer4CntIntMask3 = 3u, ///< CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count).
|
||||
Timer4CntIntMask4 = 4u, ///< CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count).
|
||||
Timer4CntIntMask5 = 5u, ///< CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count).
|
||||
Timer4CntIntMask6 = 6u, ///< CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count).
|
||||
Timer4CntIntMask7 = 7u, ///< CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count).
|
||||
Timer4CntIntMask8 = 8u, ///< CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count).
|
||||
Timer4CntIntMask9 = 9u, ///< CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count).
|
||||
Timer4CntIntMask10 = 10u, ///< CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count).
|
||||
Timer4CntIntMask11 = 11u, ///< CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count).
|
||||
Timer4CntIntMask12 = 12u, ///< CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count).
|
||||
Timer4CntIntMask13 = 13u, ///< CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count).
|
||||
Timer4CntIntMask14 = 14u, ///< CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count).
|
||||
Timer4CntIntMask15 = 15u, ///< CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count).
|
||||
} en_timer4_cnt_int_mask_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 CNT initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer4_cnt_init
|
||||
{
|
||||
uint16_t u16Cycle; ///< CNT cycle
|
||||
|
||||
en_timer4_cnt_mode_t enCntMode; ///< CNT count mode and this parameter can be a value of @ref en_timer4_cnt_mode_t
|
||||
|
||||
en_timer4_cnt_clk_t enClk; ///< CNT Count clock and this parameter can be a value of @ref en_timer4_cnt_clk_t
|
||||
|
||||
en_timer4_cnt_clk_div_t enClkDiv; ///< CNT clock divide and this parameter can be a value of @ref en_timer4_cnt_clk_div_t
|
||||
|
||||
en_functional_state_t enBufferCmd; ///< Disable: Disable buffer function; Enable:Enable buffer function
|
||||
|
||||
en_functional_state_t enZeroIntCmd; ///< Disable: Disable zero match interrupt; Enable:zero match interrupt
|
||||
|
||||
en_functional_state_t enPeakIntCmd; ///< Disable: Disable peak match interrupt; Enable:peak match interrupt
|
||||
|
||||
en_timer4_cnt_int_mask_t enZeroIntMsk; ///< CNT zero interrupt mask times and this parameter can be a value of @ref en_timer4_cnt_int_mask_t
|
||||
|
||||
en_timer4_cnt_int_mask_t enPeakIntMsk; ///< CNT peak interrupt mask times and this parameter can be a value of @ref en_timer4_cnt_int_mask_t
|
||||
|
||||
} stc_timer4_cnt_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_Init(M4_TMR4_TypeDef *TMR4x,
|
||||
const stc_timer4_cnt_init_t *pstcInitCfg);
|
||||
en_result_t TIMER4_CNT_DeInit(M4_TMR4_TypeDef *TMR4x);
|
||||
en_result_t TIMER4_CNT_SetClock(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_clk_t enCntClk);
|
||||
en_timer4_cnt_clk_t TIMER4_CNT_GetClock(M4_TMR4_TypeDef *TMR4x);
|
||||
en_result_t TIMER4_CNT_SetClockDiv(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_clk_div_t enClkDiv);
|
||||
en_timer4_cnt_clk_div_t TIMER4_CNT_GetClockDiv(M4_TMR4_TypeDef *TMR4x);
|
||||
en_result_t TIMER4_CNT_SetMode(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_mode_t enMode);
|
||||
en_timer4_cnt_mode_t TIMER4_CNT_GetMode(M4_TMR4_TypeDef *TMR4x);
|
||||
en_result_t TIMER4_CNT_Start(M4_TMR4_TypeDef *TMR4x);
|
||||
en_result_t TIMER4_CNT_Stop(M4_TMR4_TypeDef *TMR4x);
|
||||
en_result_t TIMER4_CNT_IrqCmd(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_int_t enIntType,
|
||||
en_functional_state_t enCmd);
|
||||
en_flag_status_t TIMER4_CNT_GetIrqFlag(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_int_t enIntType);
|
||||
en_result_t TIMER4_CNT_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_int_t enIntType);
|
||||
en_result_t TIMER4_CNT_SetCycleVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Cycle);
|
||||
uint16_t TIMER4_CNT_GetCycleVal(const M4_TMR4_TypeDef *TMR4x);
|
||||
en_result_t TIMER4_CNT_ClearCountVal(M4_TMR4_TypeDef *TMR4x);
|
||||
en_result_t TIMER4_CNT_SetCountVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Count);
|
||||
uint16_t TIMER4_CNT_GetCountVal(const M4_TMR4_TypeDef *TMR4x);
|
||||
en_result_t TIMER4_CNT_SetIntMaskTimes(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_int_t enIntType,
|
||||
en_timer4_cnt_int_mask_t enMaskTimes);
|
||||
en_timer4_cnt_int_mask_t TIMER4_CNT_GetIntMaskTimes(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_int_t enIntType);
|
||||
|
||||
//@} // Timer4CntGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_TIMER4_CNT_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_TIMER4_CNT_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,115 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer4_emb.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer4EmbGroup Timer4EMB description @endlink
|
||||
**
|
||||
** - 2018-11-02 CDT First version for Device Driver Library of Timer4EMB.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_TIMER4_EMB_H__
|
||||
#define __HC32F460_TIMER4_EMB_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_TIMER4_EMB_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup Timer4EmbGroup Timer4 Emergency Brake(Timer4EMB)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 EMB hold function selection enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_emb_hold_mode
|
||||
{
|
||||
EmbChangePwm = 0u, ///< Don't hold PWM output when EMB signal occurs
|
||||
EmbHoldPwm = 1u, ///< Hold PWM output when EMB signal occurs
|
||||
} en_timer4_emb_hold_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 EMB state selection enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_emb_state
|
||||
{
|
||||
EmbTrigPwmOutputNormal = 0u, ///< PWM output signal normally.
|
||||
EmbTrigPwmOutputHiz = 1u, ///< PWM output Hiz signal.
|
||||
EmbTrigPwmOutputLowLevel = 2u, ///< PWM output low level signal.
|
||||
EmbTrigPwmOutputHighLevel = 3u, ///< PWM output high level signal.
|
||||
} en_timer4_emb_state_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 EMB configure
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer4_emb_init
|
||||
{
|
||||
en_timer4_emb_state_t enEmbState; ///< Timer4 EMB state selection and this parameter can be a value of @ref en_timer4_emb_state_t
|
||||
|
||||
en_timer4_emb_hold_mode_t enPwmHold; ///< Timer4 EMB hold function selection and this parameter can be a value of @ref en_timer4_emb_hold_mode_t
|
||||
} stc_timer4_emb_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_EMB_Init(M4_TMR4_TypeDef *TMR4x,
|
||||
const stc_timer4_emb_init_t *pstcInitCfg);
|
||||
en_result_t TIMER4_EMB_DeInit(M4_TMR4_TypeDef *TMR4x);
|
||||
en_result_t TIMER4_EMB_SetHoldMode(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_emb_hold_mode_t enHoldMode);
|
||||
en_timer4_emb_hold_mode_t TIMER4_EMB_GetHoldMode(M4_TMR4_TypeDef *TMR4x);
|
||||
en_result_t TIMER4_EMB_SetState(const M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_emb_state_t enEmbState);
|
||||
en_timer4_emb_state_t TIMER4_EMB_GetState(const M4_TMR4_TypeDef *TMR4x);
|
||||
|
||||
//@} // Timer4EmbGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_TIMER4_EMB_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_TIMER4_EMB_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,273 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer4_oco.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer4OcoGroup Timer4OCO description @endlink
|
||||
**
|
||||
** - 2018-11-02 CDT First version for Device Driver Library of Timer4OCO.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_TIMER4_OCO_H__
|
||||
#define __HC32F460_TIMER4_OCO_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_TIMER4_OCO_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup Timer4OcoGroup Timer4 Output Compare(Timer4OCO)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 OCO channel enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_oco_ch
|
||||
{
|
||||
Timer4OcoOuh = 0u, ///< Timer4 OCO channel:OUH
|
||||
Timer4OcoOul = 1u, ///< Timer4 OCO channel:OUL
|
||||
Timer4OcoOvh = 2u, ///< Timer4 OCO channel:OVH
|
||||
Timer4OcoOvl = 3u, ///< Timer4 OCO channel:OVL
|
||||
Timer4OcoOwh = 4u, ///< Timer4 OCO channel:OWH
|
||||
Timer4OcoOwl = 5u, ///< Timer4 OCO channel:OWL
|
||||
} en_timer4_oco_ch_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief output level of the OC port enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_oco_port_level
|
||||
{
|
||||
OcPortLevelLow = 0u, ///< Output low level to OC port
|
||||
OcPortLevelHigh = 1u, ///< Output high level to OC port
|
||||
} en_timer4_oco_port_level_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief buffer register function of OCCR
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_oco_occr_buf
|
||||
{
|
||||
OccrBufDisable = 0u, ///< Disable the register buffer function
|
||||
OccrBufTrsfByCntZero = 1u, ///< Register buffer transfer when counter value is 0x0000
|
||||
OccrBufTrsfByCntPeak = 2u, ///< Register buffer transfer when counter value is CPSR
|
||||
OccrBufTrsfByCntZeroOrCntPeak = 3u, ///< Register buffer transfer when the value is both 0 and CPSR
|
||||
OccrBufTrsfByCntZeroZicZero = 4u, ///< Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0
|
||||
OccrBufTrsfByCntPeakPicZero = 5u, ///< Register buffer transfer when counter value is CPSR and peak value detection mask counter value is 0
|
||||
OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero = 6u, ///< Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 or
|
||||
///< when counter value is CPSR and peak value detection mask counter value is 0
|
||||
} en_timer4_oco_occr_buf_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief buffer register function of OCMR
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_oco_ocmr_buf
|
||||
{
|
||||
OcmrBufDisable = 0u, ///< Disable the register buffer function
|
||||
OcmrBufTrsfByCntZero = 1u, ///< Register buffer transfer when counter value is 0x0000
|
||||
OcmrBufTrsfByCntPeak = 2u, ///< Register buffer transfer when counter value is CPSR
|
||||
OcmrBufTrsfByCntZeroOrCntPeak = 3u, ///< Register buffer transfer when the value is both 0 and CPSR
|
||||
OcmrBufTrsfByCntZeroZicZero = 4u, ///< Register buffer transfer when CNT counter value is 0x0000 and zero value detection mask counter value is 0
|
||||
OcmrBufTrsfByCntPeakPicZero = 5u, ///< Register buffer transfer when CNT counter value is CPSR and peak value detection mask counter value is 0
|
||||
OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero = 6u, ///< Register buffer transfer when CNT counter value is 0x0000 and zero value detection mask counter value is 0 or
|
||||
///< when CNT counter value is CPSR and peak value detection mask counter value is 0
|
||||
} en_timer4_oco_ocmr_buf_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief OP output status enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_oco_op_state
|
||||
{
|
||||
OcoOpOutputHold = 0u, ///< OP output hold
|
||||
OcoOpOutputHigh = 1u, ///< OP output high
|
||||
OcoOpOutputLow = 2u, ///< OP output low
|
||||
OcoOpOutputReverse = 3u, ///< OP output reverse
|
||||
} en_timer4_oco_op_state_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The condition for OCF set
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_oco_ocf_state
|
||||
{
|
||||
OcoOcfHold = 0u, ///< OCF hold
|
||||
OcoOcfSet = 1u, ///< OCF set
|
||||
} en_timer4_oco_ocf_state_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The configuration of OCO high channel(OUH/OVH/OWH)
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_oco_high_ch_compare_mode
|
||||
{
|
||||
en_timer4_oco_op_state_t enCntZeroMatchOpState; ///< b11~b10 High channel's OP output status when high channel match occurs at the condition of CNT count=0x0000
|
||||
en_timer4_oco_op_state_t enCntZeroNotMatchOpState; ///< b15~b14 High channel's OP output status when high channel match doesn't occur at the condition of CNT count=0x0000
|
||||
|
||||
en_timer4_oco_op_state_t enCntUpCntMatchOpState; ///< b9~b8 High channel's OP output status when high channel match occurs at the condition of CNT is counting up
|
||||
|
||||
en_timer4_oco_op_state_t enCntPeakMatchOpState; ///< b7~b6 High channel's OP output status when high channel match occurs at the condition of CNT count=Peak
|
||||
en_timer4_oco_op_state_t enCntPeakNotMatchOpState; ///< b13~b12 High channel's OP output status when high channel match doesn't occur at the condition of CNT count=Peak
|
||||
|
||||
en_timer4_oco_op_state_t enCntDownCntMatchOpState; ///< b5~b4 High channel's OP output status when high channel match occurs at the condition of CNT is counting down
|
||||
|
||||
en_timer4_oco_ocf_state_t enCntZeroMatchOcfState; ///< b3 High channel's OCF status when high channel match occurs at the condition of CNT count=0x0000
|
||||
en_timer4_oco_ocf_state_t enCntUpCntMatchOcfState; ///< b2 High channel's OCF status when high channel match occurs at the condition of CNT is counting up
|
||||
en_timer4_oco_ocf_state_t enCntPeakMatchOcfState; ///< b1 High channel's OCF status when high channel match occurs at the condition of CNT count=Peak
|
||||
en_timer4_oco_ocf_state_t enCntDownCntMatchOcfState; ///< b0 High channel's OCF status when high channel match occurs at the condition of CNT is counting down
|
||||
|
||||
en_functional_state_t enMatchConditionExtendCmd; ///< Enable: Extend the match condition
|
||||
///< Disable: Don't extend the match conditio
|
||||
} stc_oco_high_ch_compare_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The configuration of OCO low channel(OUL/OVL/OWL)
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_oco_low_ch_compare_mode
|
||||
{
|
||||
en_timer4_oco_op_state_t enCntZeroLowMatchHighMatchLowChOpState; ///< b27~b26 Low channel's OP output status when high channel and low channel match occurs at the condition of CNT count=0x0000
|
||||
en_timer4_oco_op_state_t enCntZeroLowMatchHighNotMatchLowChOpState; ///< b11~b10 Low channel's OP output status when high channel not match and low channel match occurs at the condition of CNT count=0x0000
|
||||
en_timer4_oco_op_state_t enCntZeroLowNotMatchHighMatchLowChOpState; ///< b31~b30 Low channel's OP output status when high channel match and low channel not match occurs at the condition of CNT count=0x0000
|
||||
en_timer4_oco_op_state_t enCntZeroLowNotMatchHighNotMatchLowChOpState; ///< b15~b14 Low channel's OP output status when high channel not match and low channel not match occurs at the condition of CNT count=0x0000
|
||||
|
||||
en_timer4_oco_op_state_t enCntUpCntLowMatchHighMatchLowChOpState; ///< b25~b24 Low channel's OP output status when high channel and low channel match occurs at the condition of CNT is counting up
|
||||
en_timer4_oco_op_state_t enCntUpCntLowMatchHighNotMatchLowChOpState; ///< b9~b8 Low channel's OP output status when high channel not match and low channel match occurs at the condition of CNT is counting up
|
||||
en_timer4_oco_op_state_t enCntUpCntLowNotMatchHighMatchLowChOpState; ///< b19~b18 Low channel's OP output status when high channel match and low channel not match occurs at the condition of CNT is counting up
|
||||
|
||||
en_timer4_oco_op_state_t enCntPeakLowMatchHighMatchLowChOpState; ///< b23~b22 Low channel's OP output status when high channel and low channel match occurs at the condition of CNT count=Peak
|
||||
en_timer4_oco_op_state_t enCntPeakLowMatchHighNotMatchLowChOpState; ///< b7~b6 Low channel's OP output status when high channel not match and low channel match occurs at the condition of CNT count=Peak
|
||||
en_timer4_oco_op_state_t enCntPeakLowNotMatchHighMatchLowChOpState; ///< b29~b28 Low channel's OP output status when high channel match and low channel not match occurs at the condition of CNT count=Peak
|
||||
en_timer4_oco_op_state_t enCntPeakLowNotMatchHighNotMatchLowChOpState; ///< b13~b12 Low channel's OP output status when high channel not match and low channel not match occurs at the condition of CNT count=Peak
|
||||
|
||||
en_timer4_oco_op_state_t enCntDownLowMatchHighMatchLowChOpState; ///< b21~b20 Low channel's OP output status when high channel and low channel match occurs at the condition of CNT is counting down
|
||||
en_timer4_oco_op_state_t enCntDownLowMatchHighNotMatchLowChOpState; ///< b5~b4 Low channel's OP output status when high channel not match and low channel match occurs at the condition of CNT is counting down
|
||||
en_timer4_oco_op_state_t enCntDownLowNotMatchHighMatchLowChOpState; ///< b17~b16 Low channel's OP output status when high channel match and low channel not match occurs at the condition of CNT is coutning down
|
||||
|
||||
en_timer4_oco_ocf_state_t enCntZeroMatchOcfState; ///< b3 Low channel's OCF status when low channel match occurs at the condition of CNT count=0x0000
|
||||
en_timer4_oco_ocf_state_t enCntUpCntMatchOcfState; ///< b2 Low channel's OCF status when low channel match occurs at the condition of CNT is counting up
|
||||
en_timer4_oco_ocf_state_t enCntPeakMatchOcfState; ///< b1 Low channel's OCF status when low channel match occurs at the condition of CNT count=Peak
|
||||
en_timer4_oco_ocf_state_t enCntDownCntMatchOcfState; ///< b0 Low channel's OCF status when low channel match occurs at the condition of CNT is counting down
|
||||
|
||||
en_functional_state_t enMatchConditionExtendCmd; ///< Enable: Extend the match condition
|
||||
///< Disable: Don't extend the match conditio
|
||||
} stc_oco_low_ch_compare_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 OCO initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer4_oco_init
|
||||
{
|
||||
en_timer4_oco_occr_buf_t enOccrBufMode; ///< buffer register function of OCCR
|
||||
|
||||
en_timer4_oco_ocmr_buf_t enOcmrBufMode; ///< buffer register function of OCMR
|
||||
|
||||
en_timer4_oco_port_level_t enPortLevel; ///< OP output level state
|
||||
|
||||
en_functional_state_t enOcoIntCmd; ///< Disable: Disable interrupt; Enable:Enable interrupt
|
||||
} stc_timer4_oco_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_OCO_Init(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh,
|
||||
const stc_timer4_oco_init_t* pstcInitCfg);
|
||||
en_result_t TIMER4_OCO_DeInit(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh);
|
||||
en_result_t TIMER4_OCO_SetOccrBufMode(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh,
|
||||
en_timer4_oco_occr_buf_t enOccrBufMode);
|
||||
en_result_t TIMER4_OCO_SetOcmrBufMode(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh,
|
||||
en_timer4_oco_ocmr_buf_t enOcmrBufMode);
|
||||
en_result_t TIMER4_OCO_ExtMatchCondCmd(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t TIMER4_OCO_SetHighChCompareMode(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh,
|
||||
const stc_oco_high_ch_compare_mode_t *pstcMode);
|
||||
en_result_t TIMER4_OCO_SetLowChCompareMode(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh,
|
||||
const stc_oco_low_ch_compare_mode_t *pstcMode);
|
||||
en_result_t TIMER4_OCO_OutputCompareCmd(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t TIMER4_OCO_IrqCmd(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh,
|
||||
en_functional_state_t enCmd);
|
||||
en_flag_status_t TIMER4_OCO_GetIrqFlag(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh);
|
||||
en_result_t TIMER4_OCO_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh);
|
||||
en_result_t TIMER4_OCO_SetOpPortLevel(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh,
|
||||
en_timer4_oco_port_level_t enLevel);
|
||||
en_timer4_oco_port_level_t TIMER4_OCO_GetOpPinLevel(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh);
|
||||
en_result_t TIMER4_OCO_WriteOccr(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh,
|
||||
uint16_t u16Occr);
|
||||
uint16_t TIMER4_OCO_ReadOccr(const M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_oco_ch_t enCh);
|
||||
|
||||
//@} // Timer4OcoGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_TIMER4_OCO_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_TIMER4_OCO_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,158 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer4_pwm.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer4PwmGroup Timer4PWM description @endlink
|
||||
**
|
||||
** - 2018-11-02 CDT First version for Device Driver Library of Timer4PWM.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_TIMER4_PWM_H__
|
||||
#define __HC32F460_TIMER4_PWM_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_TIMER4_PWM_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup Timer4PwmGroup Timer4 Pulse-Width Modulation(Timer4PWM)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
** \brief Timer4 PWM channel enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_pwm_ch
|
||||
{
|
||||
Timer4PwmU = 0u, ///< Timer4 PWM couple channel: U
|
||||
Timer4PwmV = 1u, ///< Timer4 PWM couple channel: V
|
||||
Timer4PwmW = 2u, ///< Timer4 PWM couple channel: W
|
||||
} en_timer4_pwm_ch_t;
|
||||
|
||||
/*******************************************************************************
|
||||
** \brief Timer4 PWM operation mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_pwm_mode
|
||||
{
|
||||
PwmThroughMode = 0u, ///< through mode
|
||||
PwmDeadTimerMode = 1u, ///< Dead timer mode
|
||||
PwmDeadTimerFilterMode = 2u, ///< Dead timer filter mode
|
||||
} en_timer4_pwm_mode_t;
|
||||
|
||||
/*******************************************************************************
|
||||
** \brief Timer4 PWM DMOD bit setting enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_pwm_output_state
|
||||
{
|
||||
PwmHPwmLHold = 0u, ///< Output PWML and PWMH signals without changing the level
|
||||
PwmHPwmLReverse = 1u, ///< Output both PWML and PWMH signals reversed
|
||||
PwmHReversePwmLHold = 2u, ///< Output the PWMH signal reversed, outputs the PWML signal without changing the level.
|
||||
PwmHHoldPwmLReverse = 3u, ///< Output the PWMH signal without changing the level, Outputs the PWML signal reversed.
|
||||
} en_timer4_pwm_output_state_t;
|
||||
|
||||
/*******************************************************************************
|
||||
** \brief Timer4 PWM count clock prescaler enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_pwm_timer_clk_div
|
||||
{
|
||||
PwmPlckDiv1 = 0u, ///< PWM timer clock prescaler: None
|
||||
PwmPlckDiv2 = 1u, ///< PWM timer clock prescaler: 1/2
|
||||
PwmPlckDiv4 = 2u, ///< PWM timer clock prescaler: 1/4
|
||||
PwmPlckDiv8 = 3u, ///< PWM timer clock prescaler: 1/8
|
||||
PwmPlckDiv16 = 4u, ///< PWM timer clock prescaler: 1/16
|
||||
PwmPlckDiv32 = 5u, ///< PWM timer clock prescaler: 1/32
|
||||
PwmPlckDiv64 = 6u, ///< PWM timer clock prescaler: 1/64
|
||||
PwmPlckDiv128 = 7u, ///< PWM timer clock prescaler: 1/128
|
||||
} en_timer4_pwm_timer_clk_div_t;
|
||||
|
||||
/*******************************************************************************
|
||||
** \brief Timer4 PWM initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer4_pwm_init
|
||||
{
|
||||
en_timer4_pwm_mode_t enMode; ///< Select PWM mode and this parameter can be a value of @ref en_timer4_pwm_mode_t
|
||||
|
||||
en_timer4_pwm_timer_clk_div_t enClkDiv; ///< Clock division of PWM timer and this parameter can be a value of @ref en_timer4_pwm_timer_clk_div_t
|
||||
|
||||
en_timer4_pwm_output_state_t enOutputState; ///< Polarity for PWMH and PWML signal output and this parameter can be a value of @ref en_timer4_pwm_output_state_t
|
||||
|
||||
en_functional_state_t enRtIntMaskCmd; ///< Enable: Enable mask reload-timer interrupt, FALSE: don't mask reload-timer interrupt
|
||||
} stc_timer4_pwm_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_PWM_Init(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh,
|
||||
const stc_timer4_pwm_init_t *pstcInitCfg);
|
||||
en_result_t TIMER4_PWM_DeInit(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh);
|
||||
en_result_t TIMER4_PWM_StartTimer(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh);
|
||||
en_result_t TIMER4_PWM_StopTimer(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh);
|
||||
en_flag_status_t TIMER4_PWM_GetIrqFlag(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh);
|
||||
en_result_t TIMER4_PWM_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh);
|
||||
en_result_t TIMER4_PWM_WriteDeadRegionValue(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh,
|
||||
uint16_t u16PDAR,
|
||||
uint16_t u16PDBR);
|
||||
en_result_t TIMER4_PWM_ReadDeadRegionValue(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh,
|
||||
uint16_t* u16PDAR,
|
||||
uint16_t* u16PDBR);
|
||||
en_result_t TIMER4_PWM_SetFilterCountValue(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh,
|
||||
uint16_t u16Count);
|
||||
|
||||
//@} // Timer4PwmGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_TIMER4_PWM_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_TIMER4_PWM_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,221 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer4_sevt.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer4SevtGroup Timer4SEVT description @endlink
|
||||
**
|
||||
** - 2018-11-02 CDT First version for Device Driver Library of Timer4SEVT.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_TIMER4_SEVT_H__
|
||||
#define __HC32F460_TIMER4_SEVT_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_TIMER4_SEVT_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup Timer4SevtGroup Timer4 Special Event(Timer4SEVT)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 SEVT channel enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_sevt_ch
|
||||
{
|
||||
Timer4SevtCh0 = 0u, ///< Timer4 SEVT channel:0
|
||||
Timer4SevtCh1 = 1u, ///< Timer4 SEVT channel:1
|
||||
Timer4SevtCh2 = 2u, ///< Timer4 SEVT channel:2
|
||||
Timer4SevtCh3 = 3u, ///< Timer4 SEVT channel:3
|
||||
Timer4SevtCh4 = 4u, ///< Timer4 SEVT channel:4
|
||||
Timer4SevtCh5 = 5u, ///< Timer4 SEVT channel:5
|
||||
} en_timer4_sevt_ch_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 Special-EVT buffer type of SCCR and SCMR
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_sevt_buf
|
||||
{
|
||||
SevtBufDisable = 0u, ///< Disable Timer4 Special-EVT buffer function
|
||||
SevtBufCntZero = 1u, ///< Timer4 Special-EVT transfer buffer register of SCCR and SCMR when counter value of Cnt connected= 0x0000
|
||||
SevtBufCntPeak = 2u, ///< Timer4 Special-EVT transfer buffer register of SCCR and SCMR when counter value of Cnt connected= TCCP
|
||||
SevtBufCntZeroOrCntPeak = 3u, ///< Timer4 Special-EVT transfer buffer register of SCCR and SCMR both when counter value of Cnt connected= 0x0000 and TCCP
|
||||
SevtBufCntZeroZicZero = 4u, ///< Timer4 Special-EVT transfer buffer register of SCCR and SCMR when counter value of Cnt connected= 0x0000 and zero value detection mask counter value is 0
|
||||
SevtBufCntPeakPicZero = 5u, ///< Timer4 Special-EVT transfer buffer register of SCCR and SCMR when counter value of Cnt connected= peak and peak value detection mask counter value is 0
|
||||
SevtBufCntZeroZicZeroOrCntPeakPicZero = 6u, ///< Timer4 Special-EVT transfer buffer register of SCCR and SCMR when counter value of Cnt connected= 0x0000 and zero value detection mask counter value is 0
|
||||
///< or counter value of CNT connected= peak and peak value detection mask counter value is 0
|
||||
} en_timer4_sevt_buf_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 Special-EVT output trigger signal type
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_sevt_trigger_evt
|
||||
{
|
||||
SevtTrgEvtSCMUH = 0u, ///< Timer4 Special-EVT Event: TMR4_Ux_SCMUH
|
||||
SevtTrgEvtSCMUL = 1u, ///< Timer4 Special-EVT Event: TMR4_Ux_SCMUL
|
||||
SevtTrgEvtSCMVH = 2u, ///< Timer4 Special-EVT Event: TMR4_Ux_SCMVH
|
||||
SevtTrgEvtSCMVL = 3u, ///< Timer4 Special-EVT Event: TMR4_Ux_SCMVL
|
||||
SevtTrgEvtSCMWH = 4u, ///< Timer4 Special-EVT Event: TMR4_Ux_SCMWH
|
||||
SevtTrgEvtSCMWL = 5u, ///< Timer4 Special-EVT Event: TMR4_Ux_SCMWL
|
||||
} en_timer4_sevt_trigger_evt_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 Special-EVT OCCRx select type
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_sevt_occr_sel
|
||||
{
|
||||
SevtSelOCCRxh = 0u, ///< Select OCCRxh of high channel
|
||||
SevtSelOCCRxl = 1u, ///< Select OCCRxl of low channel
|
||||
} en_timer4_sevt_occr_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 Special-EVT running mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_sevt_mode
|
||||
{
|
||||
SevtCompareTrigMode = 0u, ///< Select Timer4 Special-EVT compare mode
|
||||
SevtDelayTrigMode = 1u, ///< Select Timer4 Special-EVT delay mode
|
||||
} en_timer4_sevt_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 SEVT mask times enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer4_sevt_mask
|
||||
{
|
||||
Timer4SevtMask0 = 0u, ///< Mask 0 time.
|
||||
Timer4SevtMask1 = 1u, ///< Mask 1 times.
|
||||
Timer4SevtMask2 = 2u, ///< Mask 2 times.
|
||||
Timer4SevtMask3 = 3u, ///< Mask 3 times.
|
||||
Timer4SevtMask4 = 4u, ///< Mask 4 times.
|
||||
Timer4SevtMask5 = 5u, ///< Mask 5 times.
|
||||
Timer4SevtMask6 = 6u, ///< Mask 6 times.
|
||||
Timer4SevtMask7 = 7u, ///< Mask 7 times.
|
||||
Timer4SevtMask8 = 8u, ///< Mask 8 times.
|
||||
Timer4SevtMask9 = 9u, ///< Mask 9 times.
|
||||
Timer4SevtMask10 = 10u, ///< Mask 10 times.
|
||||
Timer4SevtMask11 = 11u, ///< Mask 11 times.
|
||||
Timer4SevtMask12 = 12u, ///< Mask 12 times.
|
||||
Timer4SevtMask13 = 13u, ///< Mask 13 times.
|
||||
Timer4SevtMask14 = 14u, ///< Mask 14 times.
|
||||
Timer4SevtMask15 = 15u, ///< Mask 15 times.
|
||||
} en_timer4_sevt_mask_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 Special-EVT trigger condition
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer4_sevt_trigger_cond
|
||||
{
|
||||
en_functional_state_t enDownMatchCmd; ///< Enable: Send trigger signal when match with SCCR&SCMR and Timer4CNT count down.
|
||||
///< Disable: Don't send trigger signal when match with SCCR&SCMR and Timer4CNT count down.
|
||||
|
||||
en_functional_state_t enPeakMatchCmd; ///< Enable: Send trigger signal when match with SCCR&SCMR and Timer4CNT count peak.
|
||||
///< Disable: Don't send trigger signal when match with SCCR&SCMR and Timer4CNT count peak.
|
||||
|
||||
en_functional_state_t enUpMatchCmd; ///< Enable: Send trigger signal when match with SCCR&SCMR and Timer4CNT count up.
|
||||
///< Disable: Don't send trigger signal when match with SCCR&SCMR and Timer4CNT count up.
|
||||
|
||||
en_functional_state_t enZeroMatchCmd; ///< Enable: Send trigger signal when match with SCCR&SCMR and Timer4CNT count zero.
|
||||
///< Disable: Don't send trigger signal when match with SCCR&SCMR and Timer4CNT count zero.
|
||||
} stc_timer4_sevt_trigger_cond_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer4 Special-EVT initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer4_sevt_init
|
||||
{
|
||||
en_timer4_sevt_buf_t enBuf; ///< Configure Timer4 Special-EVT Buffer transfer type and this parameter can be a value of @ref en_timer4_sevt_buf_t
|
||||
|
||||
en_timer4_sevt_mode_t enMode; ///< Configure Timer4 Special-EVT Running mode and this parameter can be a value of @ref en_timer4_sevt_mode_t
|
||||
|
||||
en_timer4_sevt_occr_sel_t enOccrSel; ///< Select Timer4 Special-EVT Occr channel and this parameter can be a value of @ref en_timer4_sevt_occr_sel_t
|
||||
|
||||
en_timer4_sevt_trigger_evt_t enTrigEvt; ///< Configure Timer4 Special-EVT Trigger type and this parameter can be a value of @ref en_timer4_sevt_trigger_evt_t
|
||||
|
||||
en_functional_state_t enCmpAmcZicCmd; ///< Enable: Comparison is performed with the CNT zero interrupt mask counter.
|
||||
///< Disable: Comparison is not performed with the CNT zero interrupt mask counter.
|
||||
en_functional_state_t enCmpAmcPicCmd; ///< Enable: Comparison is performed with the CNT peak interrupt mask counter.
|
||||
///< Disable: Comparison is not performed with the CNT peak interrupt mask counter.
|
||||
en_timer4_sevt_mask_t enMaskTimes; ///< Specifies start time by the value to be compared with the CNT interrupt mask counter. And this parameter can be a value of @ref en_timer4_sevt_mask_t
|
||||
} stc_timer4_sevt_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_SEVT_Init(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh,
|
||||
const stc_timer4_sevt_init_t *pstcInitCfg);
|
||||
en_result_t TIMER4_SEVT_DeInit(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh);
|
||||
en_result_t TIMER4_SEVT_SetTriggerEvent(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh,
|
||||
en_timer4_sevt_trigger_evt_t enTrgEvt);
|
||||
en_result_t TIMER4_SEVT_SetTriggerCond(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh,
|
||||
const stc_timer4_sevt_trigger_cond_t *pstcTrigCond);
|
||||
en_result_t TIMER4_SEVT_WriteSCCR(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh,
|
||||
uint16_t u16SccrVal);
|
||||
uint16_t TIMER4_SEVT_ReadSCCR(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh);
|
||||
|
||||
//@} // Timer4SevtGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_TIMER4_SEVT_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_TIMER4_SEVT_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,734 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer6.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer6Group Timer 6 description @endlink
|
||||
**
|
||||
** - 2018-11-19 CDT First version for Device Driver Library of Timer6.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_TIMER6_H__
|
||||
#define __HC32F460_TIMER6_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_TIMER6_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup Timer6Group Timer6
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer6 channel enumeration
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 PWMx port define
|
||||
*****************************************************************************/
|
||||
typedef enum en_timer6_chx_port
|
||||
{
|
||||
Timer6PWMA = 0u, ///< PWM A port
|
||||
Timer6PWMB = 1u, ///< PWM B port
|
||||
}en_timer6_chx_port_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 TRIG port define
|
||||
*****************************************************************************/
|
||||
typedef enum en_timer6_input_port
|
||||
{
|
||||
Timer6xCHA = 0u, ///< PWM A port
|
||||
Timer6xCHB = 1u, ///< PWM B port
|
||||
Timer6TrigA = 2u, ///< Timer6x trigger A port
|
||||
Timer6TrigB = 3u, ///< Timer6x trigger B port
|
||||
}en_timer6_input_port_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 general control - Z Phase input mask periods
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_gconr_zmsk
|
||||
{
|
||||
Timer6ZMaskDis = 0u, ///< Z Phase input mask disable
|
||||
Timer6ZMask4Cyl = 1u, ///< Mask Z phase input during 4 periods when over fllow or under fllow of position count
|
||||
Timer6ZMask8Cyl = 2u, ///< Mask Z phase input during 8 periods when over fllow or under fllow of position count
|
||||
Tiemr6ZMask16Cyl = 3u, ///< Mask Z phase input during 16 periods when over fllow or under fllow of position count
|
||||
}en_timer6_gconr_zmsk_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clock division enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_clk_div
|
||||
{
|
||||
Timer6PclkDiv1 = 0u, ///< Count clock: pclk
|
||||
Timer6PclkDiv2 = 1u, ///< Count clock: pclk/2
|
||||
Timer6PclkDiv4 = 2u, ///< Count clock: pclk/4
|
||||
Timer6PclkDiv8 = 3u, ///< Count clock: pclk/8
|
||||
Timer6PclkDiv16 = 4u, ///< Count clock: pclk/16
|
||||
Timer6PclkDiv64 = 5u, ///< Count clock: pclk/64
|
||||
Timer6PclkDiv256 = 6u, ///< Count clock: pclk/256
|
||||
Timer6PclkDiv1024 = 7u, ///< Count clock: pclk/1024
|
||||
} en_timer6_clk_div_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Count mode enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_count_mode
|
||||
{
|
||||
Timer6CntSawtoothMode = 0u, ///< Sawtooth wave mode
|
||||
Timer6CntTriangularModeA = 4u, ///< Triangular wave mode
|
||||
Timer6CntTriangularModeB = 5u, ///< Triangular wave mode
|
||||
} en_timer6_count_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Count direction enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_count_dir
|
||||
{
|
||||
Timer6CntDirDown = 0u, ///< Counter counting up
|
||||
Timer6CntDirUp = 1u, ///< Counter counting down
|
||||
} en_timer6_count_dir_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 period register
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_period
|
||||
{
|
||||
Timer6PeriodA = 0u, ///< Period Register A
|
||||
Timer6PeriodB = 1u, ///< Period Register B
|
||||
Timer6PeriodC = 2u, ///< Period Register C
|
||||
}en_timer6_period_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 general compare match register
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_compare
|
||||
{
|
||||
Timer6GenCompareA = 0u, ///< General Compare Match A Register
|
||||
Timer6GenCompareB = 1u, ///< General Compare Match B Register
|
||||
Timer6GenCompareC = 2u, ///< General Compare Match C Register
|
||||
Timer6GenCompareD = 3u, ///< General Compare Match D Register
|
||||
Timer6GenCompareE = 4u, ///< General Compare Match E Register
|
||||
Timer6GenCompareF = 5u, ///< General Compare Match F Register
|
||||
}en_timer6_compare_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 special compare match register
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_special_compare
|
||||
{
|
||||
Timer6SpclCompA = 0u, ///< Special Compare Match A Register
|
||||
Timer6SpclCompB = 1u, ///< Special Compare Match B Register
|
||||
Timer6SpclCompC = 2u, ///< Special Compare Match C Register
|
||||
Timer6SpclCompD = 3u, ///< Special Compare Match D Register
|
||||
Timer6SpclCompE = 4u, ///< Special Compare Match E Register
|
||||
Timer6SpclCompF = 5u, ///< Special Compare Match F Register
|
||||
}en_timer6_special_compare_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 dead timer value register
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_dead_time_reg
|
||||
{
|
||||
Timer6DeadTimUpAR = 0u, ///< Dead timer for up count A Register
|
||||
Timer6DeadTimUpBR = 1u, ///< Dead timer for up count B Register
|
||||
Timer6DeadTimDwnAR = 2u, ///< Dead timer for down count A Register
|
||||
Timer6DeadTimDwnBR = 3u, ///< Dead timer for down count B Register
|
||||
}en_timer6_dead_time_reg_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 port control - port output control of brake status
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_pconr_disval
|
||||
{
|
||||
Timer6PWMxDisValNorm = 0u, ///< PWMx port output normal when brake
|
||||
Timer6PWMxDisValHiZ = 1u, ///< PWMx port Hi-z when brake
|
||||
Timer6PWMxDisValLow = 2u, ///< PWMx port output low level when brake
|
||||
Timer6PWMxDisValHigh = 3u, ///< PWMx port output high level when brake
|
||||
}en_timer6_pconr_disval_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 port - PWMx port output status when CNTER value match GCMxR or PERAR
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_pconr_cmpc
|
||||
{
|
||||
Timer6PWMxCompareLow = 0u, ///< PWMx port output Low level when CNTER value match with GCMxR or PERAR
|
||||
Timer6PWMxCompareHigh = 1u, ///< PWMx port output high level when CNTER value match with GCMxR or PERAR
|
||||
Timer6PWMxCompareKeep = 2u, ///< PWMx port output keep former level when CNTER value match GCMxR or PERAR
|
||||
Timer6PWMxCompareInv = 3u, ///< PWMx port output inverse level when CNTER value match with GCMxR or PERAR
|
||||
}en_timer6_pconr_cmpc_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 port- PWMx port output set(STA STP)
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_pconr_port_out
|
||||
{
|
||||
Timer6PWMxPortOutLow = 0u, ///< PWMx port output set low level
|
||||
Timer6PWMxPortOutHigh = 1u, ///< PWMx port output set high level
|
||||
}en_timer6_pconr_port_out_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer6 function mode selection enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_func_mode
|
||||
{
|
||||
Timer6ModeCompareOutput = 0u, ///< Compare output function
|
||||
Timer6ModeCaptureInput = 1u, ///< Capture input function
|
||||
} en_timer6_func_mode_t;
|
||||
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 port - PWMx STA STP function selection
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_pconr_stastps
|
||||
{
|
||||
Timer6PWMxStateSelSS = 0u, ///< PWMx output status is decide by STACx STPCx when CNTER start and stop
|
||||
Timer6PWMxStateSelKeep = 1u, ///< PWMx output status keep former level when CNTER start and stop
|
||||
}en_timer6_pconr_stastps_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 buffer - General compare register / Period register transfer function selection
|
||||
**
|
||||
** \note
|
||||
** For General compare register:
|
||||
** Single buffer stransfer: Compare Ouput: GCMCR-->GCMAR / GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR / GCMDR-->GCMBR
|
||||
** Double buffer stransfer: Compare Ouput: GCMER-->GCMCR-->GCMAR / GCMFR-->GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR-->GCMER /GCMFR-->GCMDR-->GCMBR
|
||||
** For Period register:
|
||||
** Single buffer stransfer: PERBR-->PERAR
|
||||
** Double buffer stransfer: PERCR-->PERBR-->PERAR
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_buf_gcmp_prd
|
||||
{
|
||||
Timer6GcmpPrdSingleBuf = 0u, ///< Single buffer stransfer
|
||||
Timer6GcmpPrdDoubleBuf = 1u, ///< Double buffer stransfer
|
||||
}en_timer6_buf_gcmp_prd_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 buffer - Special compare register transfer function selection
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_buf_spcl_cmp
|
||||
{
|
||||
Timer6SpclSingleBuf = 0u, ///< Single buffer stransfer: Compare Ouput: SCMCR-->SCMAR / SCMDR-->SCMBR
|
||||
Timer6SpclDoubleBuf = 1u, ///< Double buffer stransfer: Compare Ouput: SCMER-->SCMCR-->SCMAR / SCMFR-->SCMDR-->SCMBR
|
||||
}en_timer6_buf_spcl_cmp_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 buffer - Special compare register transfer opportunity selection
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_buf_spcl_opt
|
||||
{
|
||||
Timer6SplcOptNone = 0u, ///< No transfer
|
||||
Timer6SplcOptOverFlow = 1u, ///< Transfer when over flow (About sawtooth mode,accord to the count direction)
|
||||
Timer6SplcOptUnderFlow = 2u, ///< Transfer when under flow (About sawtooth mode,accord to the count direction)
|
||||
Timer6SplcOptBoth = 3u, ///< Transfer when over flow or under flow (About sawtooth mode,accord to the count direction)
|
||||
}en_timer6_buf_spcl_opt_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief ADT dead timer control - PWMx dead timer separate set
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_dconr_sepa
|
||||
{
|
||||
Timer6PWMxDtSeparate = 0u, ///< The dead timer of up count and down count separate set by DTUAR and DTDAR
|
||||
Timer6PWMxDtEqual = 1u, ///< the values of DTUAR and DTDAR are equal automatically
|
||||
}en_timer6_dconr_sepa_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief ADT filter control- TRIx/PWMx port filter sample clock selection
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_fconr_fltclk
|
||||
{
|
||||
Timer6FltClkPclk0Div1 = 0u, ///< PCLK0
|
||||
Timer6FltClkPclk0Div4 = 1u, ///< PCLK0/4
|
||||
Timer6FltClkPclk0Div16 = 2u, ///< PCLK0/16
|
||||
Timer6FltClkPclk0Div64 = 3u, ///< PCLK0/64
|
||||
}en_timer6_fconr_fltclk_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 valid period repeat- TIMx valid period repeat function selection(trigger interrupt or AOS event)
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_vperr_pcnts
|
||||
{
|
||||
Timer6PeriodCnts0 = 0u, ///< Valid period repeat function disable
|
||||
Timer6PeriodCnts1 = 1u, ///< Enable every other one period
|
||||
Timer6PeriodCnts2 = 2u, ///< Enable every other two periods
|
||||
Timer6PeriodCnts3 = 3u, ///< Enable every other three periods
|
||||
Timer6PeriodCnts4 = 4u, ///< Enable every other four periods
|
||||
Timer6PeriodCnts5 = 5u, ///< Enable every other five periods
|
||||
Timer6PeriodCnts6 = 6u, ///< Enable every other six periods
|
||||
Timer6PeriodCnts7 = 7u, ///< Enable every other seven periods
|
||||
}en_timer6_vperr_pcnts_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 valid period repeat- Count condition select
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_vperr_pcnte
|
||||
{
|
||||
Timer6PeriodCnteDisable = 0u, ///< Valid period repeat function disable
|
||||
Timer6PeriodCnteMin = 1u, ///< Over flow and under flow point of Sawtooth wave mode, or under flow point of Triangular wave mode
|
||||
Timer6PeriodCnteMax = 2u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow point of Triangular wave mode
|
||||
Timer6PeriodCnteBoth = 3u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow and under flow point of Triangular wave mode
|
||||
}en_timer6_vperr_pcnte_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 Hardware(Start/Stop/Clear/Capture) event trigger select
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
|
||||
typedef enum en_timer6_hw_trig
|
||||
{
|
||||
Timer6HwTrigAos0 = 0u, ///< Hardware trigger event from AOS0(HTSSR0)
|
||||
Timer6HwTrigAos1 = 1u, ///< Hardware trigger event from AOS1(HTSSR1)
|
||||
Timer6HwTrigPWMARise = 4u, ///< Hardware trigger event from PWMA rising
|
||||
Timer6HwTrigPWMAFall = 5u, ///< Hardware trigger event from PWMA falling
|
||||
Timer6HwTrigPWMBRise = 6u, ///< Hardware trigger event from PWMA rising
|
||||
Timer6HwTrigPWMBFall = 7u, ///< Hardware trigger event from PWMA falling
|
||||
Timer6HwTrigTimTriARise = 8u, ///< Hardware trigger event from TRIGA rising
|
||||
Timer6HwTrigTimTriAFall = 9u, ///< Hardware trigger event from TRIGA falling
|
||||
Timer6HwTrigTimTriBRise = 10u, ///< Hardware trigger event from TRIGB rising
|
||||
Timer6HwTrigTimTriBFall = 11u, ///< Hardware trigger event from TRIGB falling
|
||||
Timer6HwTrigEnd = 16u,
|
||||
}en_timer6_hw_trig_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 hardware (up count/down count) event trigger select
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
|
||||
typedef enum en_timer6_hw_cnt
|
||||
{
|
||||
Timer6HwCntPWMALowPWMBRise = 0u, ///< PWMB Rising trigger when PWMA is low level
|
||||
Timer6HwCntPWMALowPWMBFall = 1u, ///< PWMB falling trigger when PWMA is low level
|
||||
Timer6HwCntPWMAHighPWMBRise = 2u, ///< PWMB Rising trigger when PWMA is high level
|
||||
Timer6HwCntPWMAHighPWMBFall = 3u, ///< PWMB falling trigger when PWMA is high level
|
||||
Timer6HwCntPWMBLowPWMARise = 4u, ///< PWMA Rising trigger when PWMB is low level
|
||||
Timer6HwCntPWMBLowPWMAFall = 5u, ///< PWMA falling trigger when PWMB is low level
|
||||
Timer6HwCntPWMBHighPWMARise = 6u, ///< PWMA Rising trigger when PWMB is high level
|
||||
Timer6HwCntPWMBHighPWMAFall = 7u, ///< PWMA falling trigger when PWMB is high level
|
||||
Timer6HwCntTRIGARise = 8u, ///< TRIGA rising trigger
|
||||
Timer6HwCntTRIGAFall = 9u, ///< TRIGA falling trigger
|
||||
Timer6HwCntTRIGBRise = 10u, ///< TRIGB rising trigger
|
||||
Timer6HwCntTRIGBFall = 11u, ///< TRIGB falling trigger
|
||||
Timer6HwCntAos0 = 16u, ///< AOS0 trigger
|
||||
Timer6HwCntAos1 = 17u, ///< AOS1 trigger
|
||||
Timer6HwCntMax = 18u,
|
||||
}en_timer6_hw_cnt_t;
|
||||
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 interrupt type
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_irq_type
|
||||
{
|
||||
Timer6INTENA = 0u, ///< Interrupt of count equal to GCMA (or capture input A)
|
||||
Timer6INTENB = 1u, ///< Interrupt of count equal to GCMB (or capture input B)
|
||||
Timer6INTENC = 2u, ///< Interrupt of count equal to GCMC
|
||||
Timer6INTEND = 3u, ///< Interrupt of count equal to GCMD
|
||||
Timer6INTENE = 4u, ///< Interrupt of count equal to GCME
|
||||
Timer6INTENF = 5u, ///< Interrupt of count equal to GCMF
|
||||
Timer6INTENOVF = 6u, ///< Interrupt of over flow of sawtooth wave mode or peak point of triangular wave mode
|
||||
Timer6INTENUDF = 7u, ///< Interrupt of under flow of sawtooth wave mode or valley point of triangular wave mode
|
||||
Timer6INTENDTE = 8u, ///< Interrupt of dead timer error
|
||||
Timer6INTENSAU = 16u, ///< Interrupt of count up equally compared with SCMA
|
||||
Timer6INTENSAD = 17u, ///< Interrupt of count down equally compared with SCMA
|
||||
Timer6INTENSBU = 18u, ///< Interrupt of count up equally compared with SCMB
|
||||
Timer6INTENSBD = 19u, ///< Interrupt of count down equally compared with SCMB
|
||||
}en_timer6_irq_type_t;
|
||||
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 status flag
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_status
|
||||
{
|
||||
Timer6CMAF = 0u, ///< Status flag of count equal to GCMA (or capture input A)
|
||||
Timer6CMBF = 1u, ///< Status flag of count equal to GCMB (or capture input B)
|
||||
Timer6CMCF = 2u, ///< Status flag of count equal to GCMC
|
||||
Timer6CMDF = 3u, ///< Status flag of count equal to GCMD
|
||||
Timer6CMEF = 4u, ///< Status flag of count equal to GCME
|
||||
Timer6CMFF = 5u, ///< Status flag of count equal to GCMF
|
||||
Timer6OVFF = 6u, ///< Status flag of over flow of sawtooth wave mode or peak point of triangular wave mode
|
||||
Timer6UDFF = 7u, ///< Status flag of under flow of sawtooth wave mode or valley point of triangular wave mode
|
||||
Timer6DTEF = 8u, ///< Status flag of dead timer error
|
||||
Timer6CMSAUF = 9u, ///< Status flag of count up equally compared with SCMA
|
||||
Timer6CMSADF = 10u, ///< Status flag of count down equally compared with SCMA
|
||||
Timer6CMSBUF = 11u, ///< Status flag of count up equally compared with SCMB
|
||||
Timer6CMSBDF = 12u, ///< Status flag of count down equally compared with SCMB
|
||||
Timer6VPERNUM = 21, ///< Number of valid period
|
||||
Timer6DIRF = 31, ///< Count direction
|
||||
}en_timer6_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer6 common trigger source select enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_timer6_com_trigger
|
||||
{
|
||||
Timer6ComTrigger_1 = 1u, ///< Select common trigger 1.
|
||||
Timer6ComTrigger_2 = 2u, ///< Select common trigger 2.
|
||||
Timer6ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2.
|
||||
} en_timer6_com_trigger_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 software synchronous config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer6_sw_sync
|
||||
{
|
||||
bool bTimer61; ///< Timer6 unit1
|
||||
bool bTimer62; ///< Timer6 unit2
|
||||
bool bTimer63; ///< Timer6 unit3
|
||||
}stc_timer6_sw_sync_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 base init structure definition
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer6_basecnt_cfg
|
||||
{
|
||||
en_timer6_count_mode_t enCntMode; ///< Count mode
|
||||
en_timer6_count_dir_t enCntDir; ///< Count direction
|
||||
en_timer6_clk_div_t enCntClkDiv; ///< Count clock division select
|
||||
}stc_timer6_basecnt_cfg_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 Trig port config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer6_port_trig_cfg
|
||||
{
|
||||
bool bFltEn; ///< trig source capture input filter enable
|
||||
en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock
|
||||
}stc_tiemr6_port_trig_cfg_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 port output config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer6_port_output_cfg
|
||||
{
|
||||
en_timer6_func_mode_t enPortMode; ///< Port mode
|
||||
bool bOutEn; ///< Output enable / disable
|
||||
en_timer6_pconr_cmpc_t enPerc; ///< Port state when counter match the period
|
||||
en_timer6_pconr_cmpc_t enCmpc; ///< Port state when counter match GCMAR(GCMBR)
|
||||
en_timer6_pconr_stastps_t enStaStp; ///< Post state selection when count start/stop
|
||||
en_timer6_pconr_port_out_t enStaOut; ///< Port state when count start
|
||||
en_timer6_pconr_port_out_t enStpOut; ///< port stop when count stop
|
||||
en_timer6_pconr_disval_t enDisVal; ///< Port output state when brake
|
||||
}stc_timer6_port_output_cfg_t;
|
||||
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 port input config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer6_port_input_cfg
|
||||
{
|
||||
en_timer6_input_port_t enPortSel; ///< Port select
|
||||
en_timer6_func_mode_t enPortMode; ///< Port mode
|
||||
bool bFltEn; ///< trig source capture input filter enable
|
||||
en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock
|
||||
}stc_timer6_port_input_cfg_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 hardware dead time function config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer6_deadtime_cfg
|
||||
{
|
||||
bool bEnDeadtime; ///< Enable hardware dead time function
|
||||
bool bEnDtBufUp; ///< Enable buffer transfer for up count dead time register(DTUBR-->DTUAR)
|
||||
bool bEnDtBufDwn; ///< Enable buffer transfer for down count dead time register(DTDBR-->DTDAR)
|
||||
bool bEnDtEqualUpDwn; ///< Enable down count dead time register equal to up count DT register
|
||||
}stc_timer6_deadtime_cfg_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 valid period config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer6_validper_cfg
|
||||
{
|
||||
en_timer6_vperr_pcnts_t enValidCntNum; ///< Valid period selection
|
||||
en_timer6_vperr_pcnte_t enValidCdtEn; ///< Count condition of valid period
|
||||
bool bPeriodSCMA; ///< Sepcial signal A valid period selection enable
|
||||
bool bPeriodSCMB; ///< Sepcial signal A valid period selection enable
|
||||
}stc_timer6_validper_cfg_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 general compare register buffer transfer config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer6_gcmp_buf_cfg
|
||||
{
|
||||
bool bEnGcmpTransBuf; ///< Enable/Disable buffer transfer
|
||||
en_timer6_buf_gcmp_prd_t enGcmpBufTransType; ///< Sigle or double buffer transfer
|
||||
}stc_timer6_gcmp_buf_cfg_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 period register buffer transfer config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer6_period_buf_cfg
|
||||
{
|
||||
bool bEnPeriodTransBuf; ///< Enable/Disable buffer transfer
|
||||
en_timer6_buf_gcmp_prd_t enPeriodBufTransType; ///< Sigle or double buffer transfer
|
||||
}stc_timer6_period_buf_cfg_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 Specila compare register buffer transfer config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer6_spcl_buf_cfg
|
||||
{
|
||||
bool bEnSpclTransBuf; ///< Enable/Disable buffer transfer
|
||||
en_timer6_buf_spcl_cmp_t enSpclBufTransType; ///< Sigle or double buffer transfer
|
||||
en_timer6_buf_spcl_opt_t enSpclBufOptType; ///< Buffer transfer opportunity
|
||||
}stc_timer6_spcl_buf_cfg_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Timer6 Z phase input mask config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_timer6_zmask_cfg
|
||||
{
|
||||
en_timer6_gconr_zmsk_t enZMaskCycle; ///< Z phase input mask periods selection
|
||||
bool bFltPosCntMaksEn; ///< As position count timer, position counter clear function enable(TRUE) or disable(FALSE) during the time of Z phase input mask
|
||||
bool bFltRevCntMaksEn; ///< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) during the time of Z phase input mask
|
||||
}stc_timer6_zmask_cfg_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/* IRQ config */
|
||||
en_result_t Timer6_ConfigIrq(M4_TMR6_TypeDef *TMR6x, en_timer6_irq_type_t enTimer6Irq, bool bEn);
|
||||
/* Get status(flag) */
|
||||
uint8_t Timer6_GetStatus(M4_TMR6_TypeDef *TMR6x, en_timer6_status_t enStatus);
|
||||
|
||||
/* Base functions */
|
||||
en_result_t Timer6_DeInit(M4_TMR6_TypeDef *TMR6x);
|
||||
en_result_t Timer6_Init(M4_TMR6_TypeDef *TMR6x, const stc_timer6_basecnt_cfg_t* pstcTimer6BaseCntCfg);
|
||||
/* Timer6 unit start count*/
|
||||
en_result_t Timer6_StartCount(M4_TMR6_TypeDef *TMR6x);
|
||||
/* Timer6 unit stop count*/
|
||||
en_result_t Timer6_StopCount(M4_TMR6_TypeDef *TMR6x);
|
||||
/* Timer6 unit Set Count Value*/
|
||||
en_result_t Timer6_SetCount(M4_TMR6_TypeDef *TMR6x, uint16_t u16Value);
|
||||
/* Timer6 unit Get Count Value*/
|
||||
uint16_t Timer6_GetCount(M4_TMR6_TypeDef *TMR6x);
|
||||
/* Timer6 unit Clear Count Value*/
|
||||
en_result_t Timer6_ClearCount(M4_TMR6_TypeDef *TMR6x);
|
||||
|
||||
/* Timer6 unit Set Period and buffer Value*/
|
||||
en_result_t Timer6_SetPeriod(M4_TMR6_TypeDef *TMR6x, en_timer6_period_t enTimer6Periodx, uint16_t u16Period);
|
||||
/* Timer6 unit set general compare register value*/
|
||||
en_result_t Timer6_SetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare, uint16_t u16Compare);
|
||||
/* Timer6 unit set specoal compare register value*/
|
||||
en_result_t Timer6_SetSpecialCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_special_compare_t enTimer6SpclCmp, uint16_t u16SpclCmp);
|
||||
/* Timer6 unit get general compare register value*/
|
||||
uint16_t Timer6_GetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare);
|
||||
|
||||
/* Timer6 unit set period buffer transfer function*/
|
||||
en_result_t Timer6_SetPeriodBuf(M4_TMR6_TypeDef *TMR6x, const stc_timer6_period_buf_cfg_t* pstcTimer6PrdBufCfg);
|
||||
/* Timer6 unit set general compare buffer transfer function*/
|
||||
en_result_t Timer6_SetGeneralBuf(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_gcmp_buf_cfg_t* pstcTimer6GenBufCfg);
|
||||
/* Timer6 unit set special compare buffer transfer function*/
|
||||
en_result_t Timer6_SetSpecialBuf(M4_TMR6_TypeDef *TMR6x,en_timer6_special_compare_t enTimer6SpclCmp, const stc_timer6_spcl_buf_cfg_t* pstcTimer6SpclBufCfg);
|
||||
|
||||
/* Timer6 unit Set valid period Value*/
|
||||
en_result_t Timer6_SetValidPeriod(M4_TMR6_TypeDef *TMR6x, const stc_timer6_validper_cfg_t* pstcTimer6ValidPerCfg);
|
||||
|
||||
/* Config Input prot and filter function */
|
||||
en_result_t Timer6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, const stc_timer6_port_input_cfg_t* pstcTimer6PortInputCfg);
|
||||
/* Config output prot function */
|
||||
en_result_t Timer6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_port_output_cfg_t* pstcTimer6PortOutCfg);
|
||||
|
||||
/* Set dead time register value */
|
||||
en_result_t Timer6_SetDeadTimeValue(M4_TMR6_TypeDef *TMR6x, en_timer6_dead_time_reg_t enTimer6DTReg, uint16_t u16DTValue);
|
||||
/* Config dead time function */
|
||||
en_result_t Timer6_ConfigDeadTime(M4_TMR6_TypeDef *TMR6x, const stc_timer6_deadtime_cfg_t* pstcTimer6DTCfg);
|
||||
|
||||
/* Config Software Synchrony Stop */
|
||||
en_result_t Timer6_SwSyncStart(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStart);
|
||||
/* Config Software Synchrony Start */
|
||||
en_result_t Timer6_SwSyncStop(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStop);
|
||||
/* Config Software Synchrony Clear */
|
||||
en_result_t Timer6_SwSyncClear(const stc_timer6_sw_sync_t* pstcTimer6SwSyncClear);
|
||||
/* Get Software Synchrony Status */
|
||||
en_result_t Timer6_GetSwSyncState(stc_timer6_sw_sync_t* pstcTimer6SwSyncState);
|
||||
|
||||
/* Config Hardware up count event */
|
||||
en_result_t Timer6_ConfigHwCntUp(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntUp);
|
||||
/* Clear Hardware up count event */
|
||||
en_result_t Timer6_ClearHwCntUp(M4_TMR6_TypeDef *TMR6x);
|
||||
/* Config Hardware down count event */
|
||||
en_result_t Timer6_ConfigHwCntDwn(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntDwn);
|
||||
/* Clear Hardware down count event */
|
||||
en_result_t Timer6_ClearHwCntDwn(M4_TMR6_TypeDef *TMR6x);
|
||||
|
||||
|
||||
/* Config Hardware start event */
|
||||
en_result_t Timer6_ConfigHwStart(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStart);
|
||||
/* Clear Hardware start event */
|
||||
en_result_t Timer6_ClearHwStart(M4_TMR6_TypeDef *TMR6x);
|
||||
/* Enable Hardware start event */
|
||||
en_result_t Timer6_EnableHwStart(M4_TMR6_TypeDef *TMR6x);
|
||||
/* Dsiable Hardware start event */
|
||||
en_result_t Timer6_DisableHwStart(M4_TMR6_TypeDef *TMR6x);
|
||||
|
||||
/* Config Hardware stop event */
|
||||
en_result_t Timer6_ConfigHwStop(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStop);
|
||||
/* Clear Hardware stop event */
|
||||
en_result_t Timer6_ClearHwStop(M4_TMR6_TypeDef *TMR6x);
|
||||
/* Enable Hardware stop event */
|
||||
en_result_t Timer6_EnableHwStop(M4_TMR6_TypeDef *TMR6x);
|
||||
/* Disable Hardware stop event */
|
||||
en_result_t Timer6_DisableHwStop(M4_TMR6_TypeDef *TMR6x);
|
||||
|
||||
/* Config Hardware clear event */
|
||||
en_result_t Timer6_ConfigHwClear(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwClear);
|
||||
/* Clear Hardware clear event */
|
||||
en_result_t Timer6_ClearHwClear(M4_TMR6_TypeDef *TMR6x);
|
||||
/* Enable Hardware clear event */
|
||||
en_result_t Timer6_EnableHwClear(M4_TMR6_TypeDef *TMR6x);
|
||||
/* Dsiable Hardware clear event */
|
||||
en_result_t Timer6_DisableHwClear(M4_TMR6_TypeDef *TMR6x);
|
||||
|
||||
|
||||
/* Config Hardware capture event A */
|
||||
en_result_t Timer6_ConfigHwCaptureA(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureA);
|
||||
/* Clear Hardware capture event A */
|
||||
en_result_t Timer6_ClearHwCaptureA(M4_TMR6_TypeDef *TMR6x);
|
||||
/* Config Hardware capture event B */
|
||||
en_result_t Timer6_ConfigHwCaptureB(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureB);
|
||||
/* Clear Hardware capture event B */
|
||||
en_result_t Timer6_ClearHwCaptureB(M4_TMR6_TypeDef *TMR6x);
|
||||
|
||||
|
||||
/* Set trigger source 0 of hardware event */
|
||||
en_result_t Timer6_SetTriggerSrc0(en_event_src_t enTriggerSrc);
|
||||
/* Set trigger source 1 of hardware event */
|
||||
en_result_t Timer6_SetTriggerSrc1(en_event_src_t enTriggerSrc);
|
||||
/* Enable or disable Timer6 common trigger for Hardware trigger source 0 */
|
||||
void TIMER6_ComTriggerCmd0(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState);
|
||||
/* Enable or disable Timer6 common trigger for Hardware trigger source 1 */
|
||||
void TIMER6_ComTriggerCmd1(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState);
|
||||
|
||||
/* Z phase input mask config */
|
||||
en_result_t Timer6_ConfigZMask(M4_TMR6_TypeDef *TMR6x, const stc_timer6_zmask_cfg_t* pstcTimer6ZMaskCfg);
|
||||
|
||||
//@} // Timer6Group
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_TIMER6_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_TIMER6_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,493 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timera.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link TimeraGroup Timer A description @endlink
|
||||
**
|
||||
** - 2018-11-08 CDT First version for Device Driver Library of
|
||||
** Timera.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_TIMERA_H__
|
||||
#define __HC32F460_TIMERA_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_TIMERA_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup TimeraGroup Timer A(Timera)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera channel enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_channel
|
||||
{
|
||||
TimeraCh1 = 0u, ///< Timera channel 1
|
||||
TimeraCh2 = 1u, ///< Timera channel 2
|
||||
TimeraCh3 = 2u, ///< Timera channel 3
|
||||
TimeraCh4 = 3u, ///< Timera channel 4
|
||||
TimeraCh5 = 4u, ///< Timera channel 5
|
||||
TimeraCh6 = 5u, ///< Timera channel 6
|
||||
TimeraCh7 = 6u, ///< Timera channel 7
|
||||
TimeraCh8 = 7u, ///< Timera channel 8
|
||||
} en_timera_channel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clock division enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_clk_div
|
||||
{
|
||||
TimeraPclkDiv1 = 0u, ///< Count clock: pclk
|
||||
TimeraPclkDiv2 = 1u, ///< Count clock: pclk/2
|
||||
TimeraPclkDiv4 = 2u, ///< Count clock: pclk/4
|
||||
TimeraPclkDiv8 = 3u, ///< Count clock: pclk/8
|
||||
TimeraPclkDiv16 = 4u, ///< Count clock: pclk/16
|
||||
TimeraPclkDiv32 = 5u, ///< Count clock: pclk/32
|
||||
TimeraPclkDiv64 = 6u, ///< Count clock: pclk/64
|
||||
TimeraPclkDiv128 = 7u, ///< Count clock: pclk/128
|
||||
TimeraPclkDiv256 = 8u, ///< Count clock: pclk/256
|
||||
TimeraPclkDiv512 = 9u, ///< Count clock: pclk/512
|
||||
TimeraPclkDiv1024 = 10u, ///< Count clock: pclk/1024
|
||||
} en_timera_clk_div_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Count mode enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_count_mode
|
||||
{
|
||||
TimeraCountModeSawtoothWave = 0u, ///< Sawtooth wave mode
|
||||
TimeraCountModeTriangularWave = 1u, ///< Triangular wave mode
|
||||
} en_timera_count_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Count direction enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_count_dir
|
||||
{
|
||||
TimeraCountDirDown = 0u, ///< Counter counting down
|
||||
TimeraCountDirUp = 1u, ///< Counter counting up
|
||||
} en_timera_count_dir_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Input port filter clock division enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_filter_clk_div
|
||||
{
|
||||
TimeraFilterPclkDiv1 = 0u, ///< Filter clock: pclk
|
||||
TimeraFilterPclkDiv4 = 1u, ///< Filter clock: pclk/4
|
||||
TimeraFilterPclkDiv16 = 2u, ///< Filter clock: pclk/16
|
||||
TimeraFilterPclkDiv64 = 3u, ///< Filter clock: pclk/64
|
||||
} en_timera_filter_clk_div_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Input port filter source enumeration
|
||||
**
|
||||
** \note _<t>_ is unit number,range 1~6
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_filter_source
|
||||
{
|
||||
TimeraFilterSourceCh1 = 0u, ///< TIMA_<t>_PWM1 input port
|
||||
TimeraFilterSourceCh2 = 1u, ///< TIMA_<t>_PWM2 input port
|
||||
TimeraFilterSourceCh3 = 2u, ///< TIMA_<t>_PWM3 input port
|
||||
TimeraFilterSourceCh4 = 3u, ///< TIMA_<t>_PWM4 input port
|
||||
TimeraFilterSourceCh5 = 4u, ///< TIMA_<t>_PWM5 input port
|
||||
TimeraFilterSourceCh6 = 5u, ///< TIMA_<t>_PWM6 input port
|
||||
TimeraFilterSourceCh7 = 6u, ///< TIMA_<t>_PWM7 input port
|
||||
TimeraFilterSourceCh8 = 7u, ///< TIMA_<t>_PWM8 input port
|
||||
TimeraFilterSourceClkA = 8u, ///< TIMA_<t>_CLKA input port
|
||||
TimeraFilterSourceClkB = 9u, ///< TIMA_<t>_CLKB input port
|
||||
TimeraFilterSourceTrig = 10u, ///< TIMA_<t>_TRIG input port
|
||||
} en_timera_filter_source_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera interrupt request type enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_irq_type
|
||||
{
|
||||
TimeraIrqCaptureOrCompareCh1 = 0u, ///< Interrupt request when channel 1 trigger capture event or compare value equal count value
|
||||
TimeraIrqCaptureOrCompareCh2 = 1u, ///< Interrupt request when channel 2 trigger capture event or compare value equal count value
|
||||
TimeraIrqCaptureOrCompareCh3 = 2u, ///< Interrupt request when channel 3 trigger capture event or compare value equal count value
|
||||
TimeraIrqCaptureOrCompareCh4 = 3u, ///< Interrupt request when channel 4 trigger capture event or compare value equal count value
|
||||
TimeraIrqCaptureOrCompareCh5 = 4u, ///< Interrupt request when channel 5 trigger capture event or compare value equal count value
|
||||
TimeraIrqCaptureOrCompareCh6 = 5u, ///< Interrupt request when channel 6 trigger capture event or compare value equal count value
|
||||
TimeraIrqCaptureOrCompareCh7 = 6u, ///< Interrupt request when channel 7 trigger capture event or compare value equal count value
|
||||
TimeraIrqCaptureOrCompareCh8 = 7u, ///< Interrupt request when channel 8 trigger capture event or compare value equal count value
|
||||
TimeraIrqOverflow = 8u, ///< Count overflow interrupt request
|
||||
TimeraIrqUnderflow = 9u, ///< Count underflow interrupt request
|
||||
} en_timera_irq_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera flag type enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_flag_type
|
||||
{
|
||||
TimeraFlagCaptureOrCompareCh1 = 0u, ///< Match flag when channel 1 trigger capture complete or compare value equal count value
|
||||
TimeraFlagCaptureOrCompareCh2 = 1u, ///< Match flag when channel 2 trigger capture complete or compare value equal count value
|
||||
TimeraFlagCaptureOrCompareCh3 = 2u, ///< Match flag when channel 3 trigger capture complete or compare value equal count value
|
||||
TimeraFlagCaptureOrCompareCh4 = 3u, ///< Match flag when channel 4 trigger capture complete or compare value equal count value
|
||||
TimeraFlagCaptureOrCompareCh5 = 4u, ///< Match flag when channel 5 trigger capture complete or compare value equal count value
|
||||
TimeraFlagCaptureOrCompareCh6 = 5u, ///< Match flag when channel 6 trigger capture complete or compare value equal count value
|
||||
TimeraFlagCaptureOrCompareCh7 = 6u, ///< Match flag when channel 7 trigger capture complete or compare value equal count value
|
||||
TimeraFlagCaptureOrCompareCh8 = 7u, ///< Match flag when channel 8 trigger capture complete or compare value equal count value
|
||||
TimeraFlagOverflow = 8u, ///< Count overflow flag
|
||||
TimeraFlagUnderflow = 9u, ///< Count underflow flag
|
||||
} en_timera_flag_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera function mode selection enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_func_mode
|
||||
{
|
||||
TimeraModeCompareOutput = 0u, ///< Compare output function
|
||||
TimeraModeCaptureInput = 1u, ///< Capture input function
|
||||
} en_timera_func_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera count start port output status enumeration
|
||||
**
|
||||
** \note _<t>_ is unit number,range 1~6
|
||||
** \note PWMn is channel of unit,range 1-8
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_count_start_output
|
||||
{
|
||||
TimeraCountStartOutputLow = 0u, ///< TIMA_<t>_PWMn port output low level
|
||||
TimeraCountStartOutputHigh = 1u, ///< TIMA_<t>_PWMn port output high level
|
||||
TimeraCountStartOutputKeep = 2u, ///< TIMA_<t>_PWMn port output to keep
|
||||
} en_timera_count_start_output_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera count stop port output status enumeration
|
||||
**
|
||||
** \note _<t>_ is unit number,range 1~6
|
||||
** \note PWMn is channel of unit,range 1-8
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_count_stop_output
|
||||
{
|
||||
TimeraCountStopOutputLow = 0u, ///< TIMA_<t>_PWMn port output low level
|
||||
TimeraCountStopOutputHigh = 1u, ///< TIMA_<t>_PWMn port output high level
|
||||
TimeraCountStopOutputKeep = 2u, ///< TIMA_<t>_PWMn port output to keep
|
||||
} en_timera_count_stop_output_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera compare value match output status enumeration
|
||||
**
|
||||
** \note _<t>_ is unit number,range 1~6
|
||||
** \note PWMn is channel of unit,range 1-8
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_compare_match_output
|
||||
{
|
||||
TimeraCompareMatchOutputLow = 0u, ///< TIMA_<t>_PWMn port output low level
|
||||
TimeraCompareMatchOutputHigh = 1u, ///< TIMA_<t>_PWMn port output high level
|
||||
TimeraCompareMatchOutputKeep = 2u, ///< TIMA_<t>_PWMn port output to keep
|
||||
TimeraCompareMatchOutputReverse = 3u, ///< TIMA_<t>_PWMn port output reverse
|
||||
} en_timera_compare_match_output_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera period value match output status enumeration
|
||||
**
|
||||
** \note _<t>_ is unit number,range 1~6
|
||||
** \note PWMn is channel of unit,range 1-8
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_period_match_output
|
||||
{
|
||||
TimeraPeriodMatchOutputLow = 0u, ///< TIMA_<t>_PWMn port output low level
|
||||
TimeraPeriodMatchOutputHigh = 1u, ///< TIMA_<t>_PWMn port output high level
|
||||
TimeraPeriodMatchOutputKeep = 2u, ///< TIMA_<t>_PWMn port output to keep
|
||||
TimeraPeriodMatchOutputReverse = 3u, ///< TIMA_<t>_PWMn port output reverse
|
||||
} en_timera_period_match_output_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera specify output status enumeration
|
||||
**
|
||||
** \note _<t>_ is unit number,range 1~6
|
||||
** \note PWMn is channel of unit,range 1-8
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_specify_output
|
||||
{
|
||||
TimeraSpecifyOutputInvalid = 0u, ///< TIMA_<t>_PWMn port output invalid
|
||||
TimeraSpecifyOutputLow = 2u, ///< TIMA_<t>_PWMn port output low level from next period
|
||||
TimeraSpecifyOutputHigh = 3u, ///< TIMA_<t>_PWMn port output high level from next period
|
||||
} en_timera_specify_output_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera common trigger source enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_timera_com_trigger
|
||||
{
|
||||
TimeraComTrigger_1 = 1u, ///< Select common trigger 1.
|
||||
TimeraComTrigger_2 = 2u, ///< Select common trigger 2.
|
||||
TimeraComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2.
|
||||
} en_timera_com_trigger_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera base init structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_timera_base_init
|
||||
{
|
||||
en_timera_clk_div_t enClkDiv; ///< Count clock division select,This is invalid when counting internal or external event
|
||||
en_timera_count_mode_t enCntMode; ///< Timera count mode
|
||||
en_timera_count_dir_t enCntDir; ///< Timera count direction
|
||||
en_functional_state_t enSyncStartupEn; ///< Enable/disable synchronization startup when unit 1 startup,unit 1 set bit invalid
|
||||
uint16_t u16PeriodVal; ///< Period value
|
||||
} stc_timera_base_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera compare output init structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_timera_compare_init
|
||||
{
|
||||
uint16_t u16CompareVal; ///< Compare value
|
||||
en_timera_count_start_output_t enStartCountOutput; ///< Port status set when count start
|
||||
en_timera_count_stop_output_t enStopCountOutput; ///< Port status set when count stop
|
||||
en_timera_compare_match_output_t enCompareMatchOutput; ///< Port status set when compare value match
|
||||
en_timera_period_match_output_t enPeriodMatchOutput; ///< Port status set when period value match
|
||||
en_timera_specify_output_t enSpecifyOutput; ///< Specify port status,next period valid,priority more than other port status set
|
||||
en_functional_state_t enCacheEn; ///< Enable/Disable cache，Only unit 1、3、5、7 valid
|
||||
en_functional_state_t enTriangularTroughTransEn; ///< Enable/Disable triangular wave trough transmit cache value，Only unit 1、3、5、7 valid
|
||||
en_functional_state_t enTriangularCrestTransEn; ///< Enable/Disable triangular wave crest transmit cache value，Only unit 1、3、5、7 valid
|
||||
uint16_t u16CompareCacheVal; ///< Compare cache value,Only unit 1、3、5、7 valid
|
||||
} stc_timera_compare_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera capture input init structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_timera_capture_init
|
||||
{
|
||||
en_functional_state_t enCapturePwmRisingEn; ///< Enable/Disable capture channel n active when TIMA_<t>_PWMn sample rising
|
||||
en_functional_state_t enCapturePwmFallingEn; ///< Enable/Disable capture channel n active when TIMA_<t>_PWMn sample falling
|
||||
en_functional_state_t enCaptureSpecifyEventEn; ///< Enable/Disable capture channel n active when specify event trigger,event value is TMRA_HTSSR1
|
||||
en_timera_filter_clk_div_t enPwmClkDiv; ///< TIMA_<t>_PWMn filter clock select
|
||||
en_functional_state_t enPwmFilterEn; ///< Enable/Disable TIMA_<t>_PWMn filter functions
|
||||
en_functional_state_t enCaptureTrigRisingEn; ///< Enable/Disable capture channel 4 active when TIMA_<t>_TRIG sample rising, only CCONR4 valid
|
||||
en_functional_state_t enCaptureTrigFallingEn; ///< Enable/Disable capture channel 4 active when TIMA_<t>_TRIG sample falling, only CCONR4 valid
|
||||
en_timera_filter_clk_div_t enTrigClkDiv; ///< TIMA_<t>_TRIG filter clock select, only CCONR4 valid
|
||||
en_functional_state_t enTrigFilterEn; ///< Enable/Disable TIMA_<t>_TRIG filter functions , only CCONR4 valid
|
||||
} stc_timera_capture_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera Orthogonal coding init structure definition
|
||||
**
|
||||
** \note _<t>_ is unit number,range 1~6
|
||||
** \note PWMn is channel of unit,range 1-8
|
||||
** \note n=2、4、6 when m=1、3、5 or n=1、3、5 when m=2、4、6
|
||||
******************************************************************************/
|
||||
typedef struct stc_timera_orthogonal_coding_init
|
||||
{
|
||||
en_functional_state_t enIncClkALowAndClkBRisingEn; ///< TIMA_<t>_CLKB sample rising edge hardware increase when TIMA_<t>_CLKA is low level
|
||||
en_functional_state_t enIncClkALowAndClkBFallingEn; ///< TIMA_<t>_CLKB sample falling edge hardware increase when TIMA_<t>_CLKA is low level
|
||||
en_functional_state_t enIncClkAHighAndClkBRisingEn; ///< TIMA_<t>_CLKB sample rising edge hardware increase when TIMA_<t>_CLKA is high level
|
||||
en_functional_state_t enIncClkAHighAndClkBFallingEn; ///< TIMA_<t>_CLKB sample falling edge hardware increase when TIMA_<t>_CLKA is high level
|
||||
en_functional_state_t enIncClkBLowAndClkARisingEn; ///< TIMA_<t>_CLKA sample rising edge hardware increase when TIMA_<t>_CLKB is low level
|
||||
en_functional_state_t enIncClkBLowAndClkAFallingEn; ///< TIMA_<t>_CLKA sample falling edge hardware increase when TIMA_<t>_CLKB is low level
|
||||
en_functional_state_t enIncClkBHighAndClkARisingEn; ///< TIMA_<t>_CLKA sample rising edge hardware increase when TIMA_<t>_CLKB is high level
|
||||
en_functional_state_t enIncClkBHighAndClkAFallingEn; ///< TIMA_<t>_CLKA sample falling edge hardware increase when TIMA_<t>_CLKB is high level
|
||||
en_functional_state_t enIncTrigRisingEn; ///< TIMA_<t>_TRIG sample rising edge hardware increase
|
||||
en_functional_state_t enIncTrigFallingEn; ///< TIMA_<t>_TRIG sample falling edge hardware increase
|
||||
en_functional_state_t enIncSpecifyEventTriggerEn; ///< TIMA_HTSSR0 register Specify event trigger hardware increase
|
||||
en_functional_state_t enIncAnotherUnitOverflowEn; ///< Unit n generate count overflow hardware increase when current unit is m.
|
||||
en_functional_state_t enIncAnotherUnitUnderflowEn; ///< Unit n generate count underflow hardware increase when current unit is m.
|
||||
en_functional_state_t enDecClkALowAndClkBRisingEn; ///< TIMA_<t>_CLKB sample rising edge hardware increase when TIMA_<t>_CLKA is low level
|
||||
en_functional_state_t enDecClkALowAndClkBFallingEn; ///< TIMA_<t>_CLKB sample falling edge hardware increase when TIMA_<t>_CLKA is low level
|
||||
en_functional_state_t enDecClkAHighAndClkBRisingEn; ///< TIMA_<t>_CLKB sample rising edge hardware increase when TIMA_<t>_CLKA is high level
|
||||
en_functional_state_t enDecClkAHighAndClkBFallingEn; ///< TIMA_<t>_CLKB sample falling edge hardware increase when TIMA_<t>_CLKA is high level
|
||||
en_functional_state_t enDecClkBLowAndClkARisingEn; ///< TIMA_<t>_CLKA sample rising edge hardware increase when TIMA_<t>_CLKB is low level
|
||||
en_functional_state_t enDecClkBLowAndClkAFallingEn; ///< TIMA_<t>_CLKA sample falling edge hardware increase when TIMA_<t>_CLKB is low level
|
||||
en_functional_state_t enDecClkBHighAndClkARisingEn; ///< TIMA_<t>_CLKA sample rising edge hardware increase when TIMA_<t>_CLKB is high level
|
||||
en_functional_state_t enDecClkBHighAndClkAFallingEn; ///< TIMA_<t>_CLKA sample falling edge hardware increase when TIMA_<t>_CLKB is high level
|
||||
en_functional_state_t enDecTrigRisingEn; ///< TIMA_<t>_TRIG sample rising edge hardware increase
|
||||
en_functional_state_t enDecTrigFallingEn; ///< TIMA_<t>_TRIG sample falling edge hardware increase
|
||||
en_functional_state_t enDecSpecifyEventTriggerEn; ///< TIMA_HTSSR0 register Specify event trigger hardware increase
|
||||
en_functional_state_t enDecAnotherUnitUnderflowEn; ///< Unit n generate count overflow hardware increase when current unit is m.
|
||||
en_functional_state_t enDecAnotherUnitOverflowEn; ///< Unit n generate count underflow hardware increase when current unit is m.
|
||||
en_timera_filter_clk_div_t enClkAClkDiv; ///< TIMA_<t>_CLKA filter clock select
|
||||
en_functional_state_t enClkAFilterEn; ///< Enable/Disable TIMA_<t>_CLKA filter functions
|
||||
en_timera_filter_clk_div_t enClkBClkDiv; ///< TIMA_<t>_CLKB filter clock select
|
||||
en_functional_state_t enClkBFilterEn; ///< Enable/Disable TIMA_<t>_CLKB filter functions
|
||||
en_timera_filter_clk_div_t enTrigClkDiv; ///< TIMA_<t>_TRIG filter clock select
|
||||
en_functional_state_t enTrigFilterEn; ///< Enable/Disable TIMA_<t>_TRIG filter functions
|
||||
} stc_timera_orthogonal_coding_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera hardware startup config structure definition
|
||||
**
|
||||
** \note _<t>_ is unit number,range 1~6
|
||||
** \note TMRA_HTSSR0 trigger startup only when unit 2~6 valid,unit 1 is invalid
|
||||
******************************************************************************/
|
||||
typedef struct stc_timera_hw_startup_config
|
||||
{
|
||||
en_functional_state_t enTrigRisingStartupEn; ///< Hardware startup TIMA_<t> when TIMA_<t>_TRIG sample rising edge(sync start valid)
|
||||
en_functional_state_t enTrigFallingStartupEn; ///< Hardware startup TIMA_<t> when TIMA_<t>_TRIG sample falling edge(sync start valid)
|
||||
en_functional_state_t enSpecifyEventStartupEn; ///< Hardware startup TIMA_<t> when TIMA_HTSSR0 register Specify event trigger
|
||||
} stc_timera_hw_startup_config_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera hardware stop config structure definition
|
||||
**
|
||||
** \note _<t>_ is unit number,range 1~6
|
||||
******************************************************************************/
|
||||
typedef struct stc_timera_hw_stop_config
|
||||
{
|
||||
en_functional_state_t enTrigRisingStopEn; ///< Hardware stop TIMA_<t> when TIMA_<t>_TRIG sample rising edge
|
||||
en_functional_state_t enTrigFallingStopEn; ///< Hardware stop TIMA_<t> when TIMA_<t>_TRIG sample falling edge
|
||||
en_functional_state_t enSpecifyEventStopEn; ///< Hardware stop TIMA_<t> when TIMA_HTSSR0 register Specify event trigger
|
||||
} stc_timera_hw_stop_config_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera hardware clear config structure definition
|
||||
**
|
||||
** \note _<t>_ is unit number,range 1~6
|
||||
** \note n=2、4、6 when m=1、3、5 or n=1、3、5 when m=2、4、6
|
||||
******************************************************************************/
|
||||
typedef struct stc_timera_hw_clear_config
|
||||
{
|
||||
en_functional_state_t enTrigRisingClearEn; ///< Hardware clear TIMA_<t> when TIMA_<t>_TRIG sample rising edge
|
||||
en_functional_state_t enTrigFallingClearEn; ///< Hardware clear TIMA_<t> when TIMA_<t>_TRIG sample falling edge
|
||||
en_functional_state_t enSpecifyEventClearEn; ///< Hardware clear TIMA_<t> when TIMA_HTSSR0 register Specify event trigger
|
||||
en_functional_state_t enAnotherUnitTrigRisingClearEn; ///< Hardware clear TIMA_<t> when unit n TRIG port sample rising when current unit is m.
|
||||
en_functional_state_t enAnotherUnitTrigFallingClearEn; ///< Hardware clear TIMA_<t> when unit n TRIG port sample falling when current unit is m.
|
||||
en_functional_state_t enChannel3RisingClearEn; ///< Hardware clear TIMA_<t> when TIMA_<t>_PWM3 sample rising edge
|
||||
en_functional_state_t enChannel3FallingClearEn; ///< Hardware clear TIMA_<t> when TIMA_<t>_PWM3 sample falling edge
|
||||
} stc_timera_hw_clear_config_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timera hardware trigger init structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_timera_hw_trigger_init
|
||||
{
|
||||
stc_timera_hw_startup_config_t stcHwStartup; ///< Hardware startup condition config
|
||||
stc_timera_hw_stop_config_t stcHwStop; ///< Hardware stop condition config
|
||||
stc_timera_hw_clear_config_t stcHwClear; ///< Hardware clear condition config
|
||||
} stc_timera_hw_trigger_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/* Base functions */
|
||||
en_result_t TIMERA_DeInit(M4_TMRA_TypeDef *TIMERAx);
|
||||
en_result_t TIMERA_BaseInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_base_init_t *pstcBaseInit);
|
||||
en_result_t TIMERA_SetCurrCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Cnt);
|
||||
uint16_t TIMERA_GetCurrCount(M4_TMRA_TypeDef *TIMERAx);
|
||||
en_result_t TIMERA_SetPeriodValue(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Period);
|
||||
uint16_t TIMERA_GetPeriodValue(M4_TMRA_TypeDef *TIMERAx);
|
||||
en_result_t TIMERA_SyncStartupCmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta);
|
||||
en_result_t TIMERA_Cmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta);
|
||||
|
||||
/* Compare output functions */
|
||||
en_result_t TIMERA_CompareInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel,
|
||||
const stc_timera_compare_init_t *pstcCompareInit);
|
||||
en_result_t TIMERA_SetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel,
|
||||
uint16_t u16CompareVal);
|
||||
uint16_t TIMERA_GetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel);
|
||||
en_result_t TIMERA_SetCacheValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel,
|
||||
uint16_t u16CompareCache);
|
||||
en_result_t TIMERA_CompareCacheCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel,
|
||||
en_functional_state_t enNewSta);
|
||||
en_result_t TIMERA_SpecifyOutputSta(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel,
|
||||
en_timera_specify_output_t enOutputSta);
|
||||
en_result_t TIMERA_CompareCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel,
|
||||
en_functional_state_t enNewSta);
|
||||
|
||||
/* Capture input functions */
|
||||
en_result_t TIMERA_CaptureInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel,
|
||||
const stc_timera_capture_init_t *pstcCapInit);
|
||||
en_result_t TIMERA_CaptureFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort,
|
||||
en_functional_state_t enNewSta);
|
||||
uint16_t TIMERA_GetCaptureValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel);
|
||||
|
||||
/* Orthogonal coding functions */
|
||||
en_result_t TIMERA_OrthogonalCodingInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_orthogonal_coding_init_t *pstcCodingInit);
|
||||
en_result_t TIMERA_SetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16CodingCnt);
|
||||
uint16_t TIMERA_GetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx);
|
||||
en_result_t TIMERA_OrthogonalCodingFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort,
|
||||
en_functional_state_t enNewSta);
|
||||
|
||||
/* Hardware control functions */
|
||||
en_result_t TIMERA_HwTriggerInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_trigger_init_t *pstcHwTriggerInit);
|
||||
en_result_t TIMERA_HwStartupConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_startup_config_t *pstcHwStartup);
|
||||
en_result_t TIMERA_HwStopConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_stop_config_t *pstcHwStop);
|
||||
en_result_t TIMERA_HwClearConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_clear_config_t *pstcHwClear);
|
||||
|
||||
/* interrupt and flags functions */
|
||||
en_result_t TIMERA_IrqCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_irq_type_t enIrq,
|
||||
en_functional_state_t enNewSta);
|
||||
en_flag_status_t TIMERA_GetFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag);
|
||||
en_result_t TIMERA_ClearFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag);
|
||||
|
||||
/* Event config functions */
|
||||
en_result_t TIMERA_EventCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel,
|
||||
en_functional_state_t enNewSta);
|
||||
en_result_t TIMERA_SetCountTriggerSrc(en_event_src_t enTriggerSrc);
|
||||
en_result_t TIMERA_SetCaptureTriggerSrc(en_event_src_t enTriggerSrc);
|
||||
en_result_t TIMERA_CountComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta);
|
||||
en_result_t TIMERA_CaptureComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta);
|
||||
|
||||
//@} // TimeraGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_TIMERA_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_TIMERA_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,100 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_trng.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link TrngGroup Trng description @endlink
|
||||
**
|
||||
** - 2018-10-20 CDT First version for Device Driver Library of Trng.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_TRNG_H__
|
||||
#define __HC32F460_TRNG_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_TRNG_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup TrngGroup True Random Number Generator(TRNG)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* The data register loads the new initial value from the random number
|
||||
generator before the random number is generated. */
|
||||
typedef enum en_trng_load_ctrl
|
||||
{
|
||||
TrngLoadNewInitValue_Disable = 0x0, ///< Disable load new initial values.
|
||||
TrngLoadNewInitValue_Enable = 0x1, ///< Enable load new initial values.
|
||||
} en_trng_load_ctrl_t;
|
||||
|
||||
/* Shift n times when capturing random noise. */
|
||||
typedef enum en_trng_shift_cnt
|
||||
{
|
||||
TrngShiftCount_32 = 0x3, ///< Shift 32 times when capturing random noise.
|
||||
TrngShiftCount_64 = 0x4, ///< Shift 64 times when capturing random noise.
|
||||
TrngShiftCount_128 = 0x5, ///< Shift 128 times when capturing random noise.
|
||||
TrngShiftCount_256 = 0x6, ///< Shift 256 times when capturing random noise.
|
||||
} en_trng_shift_cnt_t;
|
||||
|
||||
/* TRNG initialization structure definition. */
|
||||
typedef struct stc_trng_init
|
||||
{
|
||||
en_trng_load_ctrl_t enLoadCtrl; ///< @ref en_trng_load_ctrl_t.
|
||||
en_trng_shift_cnt_t enShiftCount; ///< @ref en_trng_shift_cnt_t.
|
||||
} stc_trng_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
en_result_t TRNG_Init(const stc_trng_init_t *pstcInit);
|
||||
void TRNG_DeInit(void);
|
||||
en_result_t TRNG_Generate(uint32_t *pu32Random, uint8_t u8Length, uint32_t u32Timeout);
|
||||
|
||||
void TRNG_StartIT(void);
|
||||
void TRNG_GetRandomNum(uint32_t *pu32Random, uint8_t u8Length);
|
||||
|
||||
//@} // TrngGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_TRNG_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_TRNG_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,359 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_usart.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link UsartGroup USART description @endlink
|
||||
**
|
||||
** - 2018-11-27 CDT First version for Device Driver Library of USART.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_USART_H__
|
||||
#define __HC32F460_USART_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_USART_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup UsartGroup Universal Synchronous Asynchronous Receiver \
|
||||
** Transmitter(USART)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief USART tx mode in multiple processor mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_mp_tx_mode
|
||||
{
|
||||
UsartMpTxData = 0u, ///< USART Send data in multiple-processor mode
|
||||
UsartMpTxId = 1u, ///< USART Send ID in multiple-processor mode
|
||||
} en_usart_mp_tx_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief USART clock prescale enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_clk_div
|
||||
{
|
||||
UsartClkDiv_1 = 0u, ///< PCLK/1
|
||||
UsartClkDiv_4 = 1u, ///< PCLK/4
|
||||
UsartClkDiv_16 = 2u, ///< PCLK/16
|
||||
UsartClkDiv_64 = 3u, ///< PCLK/64
|
||||
} en_usart_clk_div_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief USART mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_mode
|
||||
{
|
||||
UsartUartMode = 0u, ///< UART mode
|
||||
UsartClkSyncMode = 1u, ///< Clock sync mode
|
||||
UsartSmartCardMode = 2u, ///< Smart card mode
|
||||
} en_usart_mode_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief USART data direction
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_data_dir
|
||||
{
|
||||
UsartDataLsbFirst = 0u, ///< LSB first
|
||||
UsartDataMsbFirst = 1u, ///< MSB first
|
||||
} en_usart_data_dir_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief USART sample mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_sample_mode
|
||||
{
|
||||
UsartSampleBit16 = 0u, ///< 16 Bit
|
||||
UsartSampleBit8 = 1u, ///< 8 Bit
|
||||
} en_usart_sample_mode_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief USART data length enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_data_len
|
||||
{
|
||||
UsartDataBits8 = 0u, ///< 8 Bit
|
||||
UsartDataBits9 = 1u, ///< 9 Bit
|
||||
} en_usart_data_len_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief USART parity format enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_parity
|
||||
{
|
||||
UsartParityNone = 0u, ///< No parity bit is used.
|
||||
UsartParityEven = 1u, ///< Even parity bit is used.
|
||||
UsartParityOdd = 2u, ///< Odd parity bit is used.
|
||||
} en_usart_parity_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief USART functions enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_func
|
||||
{
|
||||
UsartRx = 0u, ///< UART RX function
|
||||
UsartRxInt = 1u, ///< USART RX interrupt function
|
||||
UsartTx = 2u, ///< UART TX function
|
||||
UsartTxEmptyInt = 3u, ///< USART TX empty interrupt function
|
||||
UsartTimeOut = 4u, ///< UART RX timeout function
|
||||
UsartTimeOutInt = 5u, ///< UART RX timeout interrupt function
|
||||
UsartSilentMode = 6u, ///< USART silent function
|
||||
UsartTxCmpltInt = 7u, ///< USART TX complete interrupt function
|
||||
UsartTxAndTxEmptyInt = 8u, ///< USART TX function and USART TX empty interrupt function
|
||||
UsartParityCheck = 9u, ///< USART Parity check function
|
||||
UsartNoiseFilter = 10u, ///< USART noise filter function
|
||||
UsartFracBaudrate = 11u, ///< USART fractional baudrate function
|
||||
UsartMulProcessor = 12u, ///< USART multiple processor function
|
||||
UsartSmartCard = 13u, ///< USART smart card mode function
|
||||
UsartCts = 14u, ///< USART CTS function
|
||||
} en_usart_func_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief USART status type enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_status
|
||||
{
|
||||
UsartParityErr = (1u << 0), ///< USART parity error
|
||||
UsartFrameErr = (1u << 1), ///< USART receive frame error
|
||||
UsartOverrunErr = (1u << 3), ///< USART receive over-run error
|
||||
UsartRxNoEmpty = (1u << 5), ///< USART data receive register is not empty
|
||||
UsartTxComplete = (1u << 6), ///< USART transfer completely
|
||||
UsartTxEmpty = (1u << 7), ///< USART data transfer register is empty
|
||||
UsartRxTimeOut = (1u << 8), ///< USART data receive timeout
|
||||
UsartRxMpb = (1u << 16), ///< USART multiple processor id or normal data, 0: receive date; 1: received ID
|
||||
} en_usart_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief USART Stop bit length select enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_stop_bit
|
||||
{
|
||||
UsartOneStopBit = 0u, ///< 1 Stop Bit
|
||||
UsartTwoStopBit = 1u, ///< 2 Stop Bit
|
||||
} en_usart_stop_bit_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief USART start bit detect mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_sb_detect_mode
|
||||
{
|
||||
UsartStartBitLowLvl = 0u, ///< Start bit: RD pin low level
|
||||
UsartStartBitFallEdge = 1u, ///< Start bit: RD pin falling edge
|
||||
} en_usart_sb_detect_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief USART clock mode selection enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_clk_mode
|
||||
{
|
||||
UsartIntClkCkNoOutput = 0u, ///< Select internal clock source and don't output clock.
|
||||
UsartIntClkCkOutput = 1u, ///< Select internal clock source and output clock.
|
||||
UsartExtClk = 2u, ///< Select external clock source.
|
||||
} en_usart_clk_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief USART smart-card mode selection enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_hw_flow_ctrl
|
||||
{
|
||||
UsartRtsEnable = 0u, ///< Enable RTS function.
|
||||
UsartCtsEnable = 1u, ///< Enable CTS function.
|
||||
} en_usart_hw_flow_ctrl_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief USART etu clocks of smart card enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_usart_sc_etu_clk
|
||||
{
|
||||
UsartScEtuClk32 = 0u, ///< 1 etu = 32/f
|
||||
UsartScEtuClk64 = 1u, ///< 1 etu = 64/f
|
||||
UsartScEtuClk128 = 3u, ///< 1 etu = 128/f
|
||||
UsartScEtuClk256 = 5u, ///< 1 etu = 256/f
|
||||
UsartScEtuClk372 = 6u, ///< 1 etu = 372/f
|
||||
} en_usart_sc_etu_clk_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Uart mode initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_usart_uart_init
|
||||
{
|
||||
en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t
|
||||
|
||||
en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t
|
||||
|
||||
en_usart_data_len_t enDataLength; ///< 8/9 Bit character length and this parameter can be a value of @ref en_usart_data_len_t
|
||||
|
||||
en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t
|
||||
|
||||
en_usart_stop_bit_t enStopBit; ///< Stop bit and this parameter can be a value of @ref en_usart_stop_bit_t
|
||||
|
||||
en_usart_parity_t enParity; ///< Parity format and this parameter can be a value of @ref en_usart_parity_t
|
||||
|
||||
en_usart_sample_mode_t enSampleMode; ///< USART sample mode, and this parameter can be a value of @ref en_usart_sample_mode_t
|
||||
|
||||
en_usart_sb_detect_mode_t enDetectMode; ///< USART start bit detect mode and this parameter can be a value of @ref en_usart_sb_detect_mode_t
|
||||
|
||||
en_usart_hw_flow_ctrl_t enHwFlow; ///< Hardware flow control and this parameter can be a value of @ref en_usart_hw_flow_ctrl_t
|
||||
} stc_usart_uart_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clock sync mode initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_usart_clksync_init
|
||||
{
|
||||
en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t
|
||||
|
||||
en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t
|
||||
|
||||
en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t
|
||||
|
||||
en_usart_hw_flow_ctrl_t enHwFlow; ///< Hardware flow control and this parameter can be a value of @ref en_usart_hw_flow_ctrl_t
|
||||
} stc_usart_clksync_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Smart card mode initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_usart_sc_init
|
||||
{
|
||||
en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t
|
||||
|
||||
en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t
|
||||
|
||||
en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t
|
||||
} stc_usart_sc_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t USART_UART_Init(M4_USART_TypeDef *USARTx,
|
||||
const stc_usart_uart_init_t *pstcInitCfg);
|
||||
en_result_t USART_CLKSYNC_Init(M4_USART_TypeDef *USARTx,
|
||||
const stc_usart_clksync_init_t *pstcInitCfg);
|
||||
en_result_t USART_SC_Init(M4_USART_TypeDef *USARTx,
|
||||
const stc_usart_sc_init_t *pstcInitCfg);
|
||||
en_result_t USART_DeInit(M4_USART_TypeDef *USARTx);
|
||||
en_flag_status_t USART_GetStatus(M4_USART_TypeDef *USARTx,
|
||||
en_usart_status_t enStatus);
|
||||
en_result_t USART_ClearStatus(M4_USART_TypeDef *USARTx,
|
||||
en_usart_status_t enStatus);
|
||||
en_result_t USART_FuncCmd(M4_USART_TypeDef *USARTx,
|
||||
en_usart_func_t enFunc,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t USART_SetParity(M4_USART_TypeDef *USARTx,
|
||||
en_usart_parity_t enParity);
|
||||
en_usart_parity_t USART_GetParity(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SetOverSampling(M4_USART_TypeDef *USARTx,
|
||||
en_usart_sample_mode_t enSampleMode);
|
||||
en_usart_sample_mode_t USART_GetOverSampling(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SetDataDirection(M4_USART_TypeDef *USARTx,
|
||||
en_usart_data_dir_t enDir);
|
||||
en_usart_data_dir_t USART_GetTransferDirection(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SetDataLength(M4_USART_TypeDef *USARTx,
|
||||
en_usart_data_len_t enDataLen);
|
||||
en_usart_data_len_t USART_GetDataLength(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SetClkMode(M4_USART_TypeDef *USARTx,
|
||||
en_usart_clk_mode_t enClkMode);
|
||||
en_usart_clk_mode_t USART_GetClkMode(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SetMode(M4_USART_TypeDef *USARTx,
|
||||
en_usart_mode_t enMode);
|
||||
en_usart_mode_t USART_GetMode(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SetStopBitsLength(M4_USART_TypeDef *USARTx,
|
||||
en_usart_stop_bit_t enStopBit);
|
||||
en_usart_stop_bit_t USART_GetStopBitsLength(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SetSbDetectMode(M4_USART_TypeDef *USARTx,
|
||||
en_usart_sb_detect_mode_t enDetectMode);
|
||||
en_usart_sb_detect_mode_t USART_GetSbDetectMode(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx,
|
||||
en_usart_hw_flow_ctrl_t enHwFlowCtrl);
|
||||
en_usart_hw_flow_ctrl_t USART_GetHwFlowCtrl(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SetClockDiv(M4_USART_TypeDef *USARTx,
|
||||
en_usart_clk_div_t enClkPrescale);
|
||||
en_usart_clk_div_t USART_GetClockDiv(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SetScEtuClk(M4_USART_TypeDef *USARTx,
|
||||
en_usart_sc_etu_clk_t enEtuClk);
|
||||
en_usart_sc_etu_clk_t USART_GetScEtuClk(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data);
|
||||
uint16_t USART_RecData(M4_USART_TypeDef *USARTx);
|
||||
en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx,
|
||||
uint32_t u32Baudrate);
|
||||
|
||||
//@} // UsartGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_USART_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_USART_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,108 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_utility.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link DdlUtilityGroup Ddl Utility description @endlink
|
||||
**
|
||||
** - 2018-11-02 CDT First version for Device Driver Library Utility.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_UTILITY_H__
|
||||
#define __HC32F460_UTILITY_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_UTILITY_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup DdlUtilityGroup Device Driver Library Utility(DDLUTILITY)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/* A approximate delay */
|
||||
void Ddl_Delay1ms(uint32_t u32Cnt);
|
||||
void Ddl_Delay1us(uint32_t u32Cnt);
|
||||
|
||||
/* Systick functions */
|
||||
en_result_t SysTick_Init(uint32_t u32Freq);
|
||||
void SysTick_Delay(uint32_t u32Delay);
|
||||
void SysTick_IncTick(void);
|
||||
uint32_t SysTick_GetTick(void);
|
||||
void SysTick_Suspend(void);
|
||||
void SysTick_Resume(void);
|
||||
|
||||
/*! Ddl assert, you can add your own assert functions by implement the function
|
||||
Ddl_AssertHook definition follow the function Ddl_AssertHook declaration */
|
||||
#ifdef __DEBUG
|
||||
#define DDL_ASSERT(x) \
|
||||
do{ \
|
||||
((x) ? (void)0 : Ddl_AssertHandler((uint8_t *)__FILE__, __LINE__)); \
|
||||
}while(0)
|
||||
/* Exported function */
|
||||
void Ddl_AssertHandler(uint8_t *file, int16_t line);
|
||||
#else
|
||||
#define DDL_ASSERT(x) (void)(0)
|
||||
#endif /* __DEBUG */
|
||||
|
||||
#if (DDL_PRINT_ENABLE == DDL_ON)
|
||||
#include <stdio.h>
|
||||
|
||||
en_result_t UART_PrintfInit(M4_USART_TypeDef *UARTx,
|
||||
uint32_t u32Baudrate,
|
||||
void (*PortInit)(void));
|
||||
|
||||
#define DDL_PrintfInit (void)UART_PrintfInit
|
||||
#define DDL_Printf (void)printf
|
||||
#else
|
||||
#define DDL_PrintfInit(x, y, z)
|
||||
#define DDL_Printf(fmt, ...)
|
||||
#endif
|
||||
|
||||
//@} // DdlUtilityGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_UTILITY_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_UTILITY_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,162 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_wdt.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link WdtGroup Watchdog Counter description @endlink
|
||||
**
|
||||
** - 2018-10-18 CDT First version for Device Driver Library of WDT.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_WDT_H__
|
||||
#define __HC32F460_WDT_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_WDT_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup WdtGroup WatchDog Counter(WDT)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT count cycle enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_wdt_count_cycle
|
||||
{
|
||||
WdtCountCycle256 = 0u, ///< 256 cycle
|
||||
WdtCountCycle4096 = 1u, ///< 4096 cycle
|
||||
WdtCountCycle16384 = 2u, ///< 16384 cycle
|
||||
WdtCountCycle65536 = 3u, ///< 65536 cycle
|
||||
} en_wdt_count_cycle_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT count clock division enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_wdt_clk_div
|
||||
{
|
||||
WdtPclk3Div4 = 2u, ///< PCLK3/4
|
||||
WdtPclk3Div64 = 6u, ///< PCLK3/64
|
||||
WdtPclk3Div128 = 7u, ///< PCLK3/128
|
||||
WdtPclk3Div256 = 8u, ///< PCLK3/256
|
||||
WdtPclk3Div512 = 9u, ///< PCLK3/512
|
||||
WdtPclk3Div1024 = 10u, ///< PCLK3/1024
|
||||
WdtPclk3Div2048 = 11u, ///< PCLK3/2048
|
||||
WdtPclk3Div8192 = 13u, ///< PCLK3/8192
|
||||
} en_wdt_clk_div_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT allow refresh percent range enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_wdt_refresh_range
|
||||
{
|
||||
WdtRefresh100Pct = 0u, ///< 100%
|
||||
WdtRefresh0To25Pct = 1u, ///< 0%~25%
|
||||
WdtRefresh25To50Pct = 2u, ///< 25%~50%
|
||||
WdtRefresh0To50Pct = 3u, ///< 0%~50%
|
||||
WdtRefresh50To75Pct = 4u, ///< 50%~75%
|
||||
WdtRefresh0To25PctAnd50To75Pct = 5u, ///< 0%~25% & 50%~75%
|
||||
WdtRefresh25To75Pct = 6u, ///< 25%~75%
|
||||
WdtRefresh0To75Pct = 7u, ///< 0%~75%
|
||||
WdtRefresh75To100Pct = 8u, ///< 75%~100%
|
||||
WdtRefresh0To25PctAnd75To100Pct = 9u, ///< 0%~25% & 75%~100%
|
||||
WdtRefresh25To50PctAnd75To100Pct = 10u, ///< 25%~50% & 75%~100%
|
||||
WdtRefresh0To50PctAnd75To100Pct = 11u, ///< 0%~50% & 75%~100%
|
||||
WdtRefresh50To100Pct = 12u, ///< 50%~100%
|
||||
WdtRefresh0To25PctAnd50To100Pct = 13u, ///< 0%~25% & 50%~100%
|
||||
WdtRefresh25To100Pct = 14u, ///< 25%~100%
|
||||
WdtRefresh0To100Pct = 15u, ///< 0%~100%
|
||||
} en_wdt_refresh_range_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT refresh error or count underflow trigger event type enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_wdt_event_request_type
|
||||
{
|
||||
WdtTriggerInterruptRequest = 0u, ///< Interrupt request
|
||||
WdtTriggerResetRequest = 1u, ///< Reset request
|
||||
} en_wdt_event_request_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT flag type enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_wdt_flag_type
|
||||
{
|
||||
WdtFlagCountUnderflow = 0u, ///< Count underflow flag
|
||||
WdtFlagRefreshError = 1u, ///< Refresh error flag
|
||||
} en_wdt_flag_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief WDT init structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_wdt_init
|
||||
{
|
||||
en_wdt_count_cycle_t enCountCycle; ///< Count cycle
|
||||
en_wdt_clk_div_t enClkDiv; ///< Count clock division
|
||||
en_wdt_refresh_range_t enRefreshRange; ///< Allow refresh percent range
|
||||
en_functional_state_t enSleepModeCountEn; ///< Enable/disable count in the sleep mode
|
||||
en_wdt_event_request_type_t enRequestType; ///< Refresh error or count underflow trigger event type
|
||||
} stc_wdt_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/* Base functions */
|
||||
en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit);
|
||||
en_result_t WDT_RefreshCounter(void);
|
||||
uint16_t WDT_GetCountValue(void);
|
||||
|
||||
/* Flags functions */
|
||||
en_flag_status_t WDT_GetFlag(en_wdt_flag_type_t enFlag);
|
||||
en_result_t WDT_ClearFlag(en_wdt_flag_type_t enFlag);
|
||||
|
||||
//@} // WdtGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_WDT_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_WDT_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,311 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_aes.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link AesGroup Aes description @endlink
|
||||
**
|
||||
** - 2018-10-20 CDT First version for Device Driver Library of Aes.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_aes.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_AES_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup AesGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* AES block length in bytes is 16. */
|
||||
#define AES_BLOCK_LEN ((uint8_t)16)
|
||||
|
||||
/* Each encryption operation takes 440 system clock cycles. */
|
||||
#define AES_ENCRYPT_TIMEOUT (440u)
|
||||
|
||||
/* Each decryption operation takes 580 system clock cycles. */
|
||||
#define AES_DECRYPT_TIMEOUT (580u)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
static void AES_WriteData(const uint8_t *pu8SrcData);
|
||||
static void AES_ReadData(uint8_t *pu8Dest);
|
||||
static void AES_WriteKey(const uint8_t *pu8Key);
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief AES128 encryption(ECB mode).
|
||||
**
|
||||
** \param [in] pu8Plaintext Pointer to plaintext(the source data which will be encrypted)
|
||||
**
|
||||
** \param [in] u32PlaintextSize Length of plaintext in bytes.
|
||||
**
|
||||
** \param [in] pu8Key Pointer to the AES key.
|
||||
**
|
||||
** \param [out] pu8Ciphertext The destination address to store the result of the encryption.
|
||||
**
|
||||
** \retval Ok No error occurred.
|
||||
** \retval ErrorTimeout AES works timeout.
|
||||
** \retval ErrorInvalidParameter Parameter error.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t AES_Encrypt(const uint8_t *pu8Plaintext,
|
||||
uint32_t u32PlaintextSize,
|
||||
const uint8_t *pu8Key,
|
||||
uint8_t *pu8Ciphertext)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
uint32_t u32BlockOffset;
|
||||
uint32_t u32Index;
|
||||
__IO uint32_t u32TimeCount;
|
||||
|
||||
if ((NULL != pu8Plaintext) &&
|
||||
(0u != u32PlaintextSize) &&
|
||||
(NULL != pu8Key) &&
|
||||
(NULL != pu8Ciphertext) &&
|
||||
(0u == (u32PlaintextSize & 0xFu)) && /* u32PlaintextSize % AES_BLOCK_LEN */
|
||||
(0u == ((uint32_t)pu8Plaintext & 0x3u)) && /* (uint32_t)pu8Ciphertext % 4u */
|
||||
(0u == ((uint32_t)pu8Key & 0x3u)) && /* (uint32_t)pu8Key % 4u */
|
||||
(0u == ((uint32_t)pu8Ciphertext & 0x3u))) /* (uint32_t)pu8Plaintext % 4u */
|
||||
{
|
||||
/* Write the key to the register. */
|
||||
AES_WriteKey(pu8Key);
|
||||
u32BlockOffset = 0u;
|
||||
while (0u != u32PlaintextSize)
|
||||
{
|
||||
/* Stop AES calculating. */
|
||||
bM4_AES_CR_START = 0u;
|
||||
|
||||
/* Write data. */
|
||||
u32Index = u32BlockOffset * AES_BLOCK_LEN;
|
||||
AES_WriteData(&pu8Plaintext[u32Index]);
|
||||
|
||||
/* Set AES encrypt. */
|
||||
bM4_AES_CR_MODE = 0u;
|
||||
|
||||
/* Start AES calculating. */
|
||||
bM4_AES_CR_START = 1u;
|
||||
|
||||
enRet = ErrorTimeout;
|
||||
u32TimeCount = 0u;
|
||||
while (u32TimeCount < AES_ENCRYPT_TIMEOUT)
|
||||
{
|
||||
if (bM4_AES_CR_START == 0u)
|
||||
{
|
||||
enRet = Ok;
|
||||
break;
|
||||
}
|
||||
u32TimeCount++;
|
||||
}
|
||||
|
||||
if (enRet == ErrorTimeout)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
AES_ReadData(&pu8Ciphertext[u32Index]);
|
||||
u32PlaintextSize -= AES_BLOCK_LEN;
|
||||
u32BlockOffset++;
|
||||
}
|
||||
|
||||
/* Stop AES calculating. */
|
||||
bM4_AES_CR_START = 0u;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief AES128 decryption(ECB mode).
|
||||
**
|
||||
** \param [in] pu8Ciphertext Pointer to ciphertext(the source data which will be decrypted)
|
||||
**
|
||||
** \param [in] u32CiphertextSize Length of ciphertext in bytes.
|
||||
**
|
||||
** \param [in] pu8Key Pointer to the AES key.
|
||||
**
|
||||
** \param [out] pu8Plaintext The destination address to store the result of the decryption.
|
||||
**
|
||||
** \retval Ok No error occurred.
|
||||
** \retval ErrorTimeout AES works timeout.
|
||||
** \retval ErrorInvalidParameter Parameter error.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext,
|
||||
uint32_t u32CiphertextSize,
|
||||
const uint8_t *pu8Key,
|
||||
uint8_t *pu8Plaintext)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
uint32_t u32BlockOffset;
|
||||
uint32_t u32Index;
|
||||
__IO uint32_t u32TimeCount;
|
||||
|
||||
if ((NULL != pu8Ciphertext) &&
|
||||
(0u != u32CiphertextSize) &&
|
||||
(NULL != pu8Key) &&
|
||||
(NULL != pu8Plaintext) &&
|
||||
(0u == (u32CiphertextSize & 0xFu)) && /* u32CiphertextSize % AES_BLOCK_LEN */
|
||||
(0u == ((uint32_t)pu8Ciphertext & 0x3u)) && /* (uint32_t)pu8Ciphertext % 4u */
|
||||
(0u == ((uint32_t)pu8Key & 0x3u)) && /* (uint32_t)pu8Key % 4u */
|
||||
(0u == ((uint32_t)pu8Plaintext & 0x3u))) /* (uint32_t)pu8Plaintext % 4u */
|
||||
{
|
||||
/* Write the key to the register. */
|
||||
AES_WriteKey(pu8Key);
|
||||
u32BlockOffset = 0u;
|
||||
while (0u != u32CiphertextSize)
|
||||
{
|
||||
/* Stop AES calculating. */
|
||||
bM4_AES_CR_START = 0u;
|
||||
|
||||
/* Write data. */
|
||||
u32Index = u32BlockOffset * AES_BLOCK_LEN;
|
||||
AES_WriteData(&pu8Ciphertext[u32Index]);
|
||||
|
||||
/* Set AES decrypt. */
|
||||
bM4_AES_CR_MODE = 1u;
|
||||
|
||||
/* Start AES calculating. */
|
||||
bM4_AES_CR_START = 1u;
|
||||
|
||||
enRet = ErrorTimeout;
|
||||
u32TimeCount = 0u;
|
||||
while (u32TimeCount < AES_DECRYPT_TIMEOUT)
|
||||
{
|
||||
if (bM4_AES_CR_START == 0u)
|
||||
{
|
||||
enRet = Ok;
|
||||
break;
|
||||
}
|
||||
u32TimeCount++;
|
||||
}
|
||||
|
||||
if (enRet == ErrorTimeout)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
AES_ReadData(&pu8Plaintext[u32Index]);
|
||||
u32CiphertextSize -= AES_BLOCK_LEN;
|
||||
u32BlockOffset++;
|
||||
}
|
||||
|
||||
/* Stop AES calculating. */
|
||||
bM4_AES_CR_START = 0u;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Writes the input buffer in data register.
|
||||
**
|
||||
** \param [in] pu8SrcData Pointer to source data buffer.
|
||||
**
|
||||
** \retval None.
|
||||
**
|
||||
******************************************************************************/
|
||||
static void AES_WriteData(const uint8_t *pu8SrcData)
|
||||
{
|
||||
uint8_t i;
|
||||
uint32_t u32SrcAddr = (uint32_t)pu8SrcData;
|
||||
uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0);
|
||||
|
||||
for (i = 0u; i < 4u; i++)
|
||||
{
|
||||
*(__IO uint32_t *)u32DrAddr = *(uint32_t*)u32SrcAddr;
|
||||
u32SrcAddr += 4u;
|
||||
u32DrAddr += 4u;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Reads the from data register.
|
||||
**
|
||||
** \param [out] pu8Dest Pointer to the destination buffer.
|
||||
**
|
||||
** \retval None.
|
||||
**
|
||||
******************************************************************************/
|
||||
static void AES_ReadData(uint8_t *pu8Dest)
|
||||
{
|
||||
uint8_t i;
|
||||
uint32_t u32DestAddr = (uint32_t)pu8Dest;
|
||||
uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0);
|
||||
|
||||
for (i = 0u; i < 4u; i++)
|
||||
{
|
||||
*(uint32_t*)u32DestAddr = *(__IO uint32_t *)u32DrAddr;
|
||||
u32DestAddr += 4u;
|
||||
u32DrAddr += 4u;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Writes the input buffer in key register.
|
||||
**
|
||||
** \param [in] pu8Key Pointer to AES key.
|
||||
**
|
||||
** \retval None.
|
||||
**
|
||||
******************************************************************************/
|
||||
static void AES_WriteKey(const uint8_t *pu8Key)
|
||||
{
|
||||
uint8_t i;
|
||||
uint32_t u32SrcKeyAddr = (uint32_t)pu8Key;
|
||||
uint32_t u32KeyAddr = (uint32_t)&(M4_AES->KR0);
|
||||
|
||||
for (i = 0u; i < 4u; i++)
|
||||
{
|
||||
*(__IO uint32_t *)u32KeyAddr = *(uint32_t*)u32SrcKeyAddr;
|
||||
u32SrcKeyAddr += 4u;
|
||||
u32KeyAddr += 4u;
|
||||
}
|
||||
}
|
||||
|
||||
//@} // AesGroup
|
||||
|
||||
#endif /* DDL_AES_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,562 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_can.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link CanGroup CAN description @endlink
|
||||
**
|
||||
** - 2018-12-13 CDT First version for Device Driver Library of CAN.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_can.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_CAN_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup CanGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
#define CAN_RESET_ENABLE() (M4_CAN->CFG_STAT_f.RESET = 1u)
|
||||
#define CAN_RESET_DISABLE() \
|
||||
do{ \
|
||||
do{ \
|
||||
M4_CAN->CFG_STAT_f.RESET = 0u; \
|
||||
}while(M4_CAN->CFG_STAT_f.RESET); \
|
||||
}while(0)
|
||||
|
||||
#define CAN_RW_MEM32(addr) (*(__IO uint32_t *)(addr))
|
||||
|
||||
#define CAN_ACF_ID_REG_SEL ((uint8_t)0x00u)
|
||||
#define CAN_ACF_MASK_REG_SEL ((uint8_t)0x01u)
|
||||
|
||||
|
||||
/*! Parameter validity check for CAN Mode \a CanMode. */
|
||||
#define IS_CAN_MODE_VALID(CanMode) \
|
||||
( (CanExternalLoopBackMode == (CanMode)) || \
|
||||
(CanInternalLoopBackMode == (CanMode)) || \
|
||||
(CanTxSignalPrimaryMode == (CanMode)) || \
|
||||
(CanTxSignalSecondaryMode == (CanMode)) || \
|
||||
(CanListenOnlyMode == (CanMode)) \
|
||||
)
|
||||
|
||||
/*! Parameter validity check for CAN Tx Cmd \a TxCmd. */
|
||||
#define IS_TX_CMD_VALID(TxCmd) \
|
||||
( (CanPTBTxCmd == (TxCmd)) || \
|
||||
(CanPTBTxAbortCmd == (TxCmd)) || \
|
||||
(CanSTBTxOneCmd == (TxCmd)) || \
|
||||
(CanSTBTxAllCmd == (TxCmd)) || \
|
||||
(CanSTBTxAbortCmd == (TxCmd)) \
|
||||
)
|
||||
|
||||
/*! Parameter validity check for CAN status \a enCanStatus. */
|
||||
#define IS_CAN_STATUS_VALID(enCanStatus) \
|
||||
( (CanRxActive == (enCanStatus)) || \
|
||||
(CanTxActive == (enCanStatus)) || \
|
||||
(CanBusoff == (enCanStatus)) \
|
||||
)
|
||||
|
||||
/*! Parameter validity check for CAN Irq type \a enCanIrqType. */
|
||||
#define IS_CAN_IRQ_TYPE_VALID(enCanIrqType) \
|
||||
( (CanRxIrqEn == (enCanIrqType)) || \
|
||||
(CanRxOverIrqEn == (enCanIrqType)) || \
|
||||
(CanRxBufFullIrqEn == (enCanIrqType)) || \
|
||||
(CanRxBufAlmostFullIrqEn == (enCanIrqType)) || \
|
||||
(CanTxPrimaryIrqEn == (enCanIrqType)) || \
|
||||
(CanTxSecondaryIrqEn == (enCanIrqType)) || \
|
||||
(CanErrorIrqEn == (enCanIrqType)) || \
|
||||
(CanErrorPassiveIrqEn == (enCanIrqType)) || \
|
||||
(CanArbiLostIrqEn == (enCanIrqType)) || \
|
||||
(CanBusErrorIrqEn == (enCanIrqType)) \
|
||||
)
|
||||
|
||||
/*! Parameter validity check for CAN Irq flag type \a enCanIrqFLg. */
|
||||
#define IS_CAN_IRQ_FLAG_VALID(enCanIrqFLg) \
|
||||
( (CanTxBufFullIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanRxIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanRxOverIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanRxBufFullIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanRxBufAlmostFullIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanTxPrimaryIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanTxSecondaryIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanErrorIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanAbortIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanErrorWarningIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanErrorPassivenodeIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanErrorPassiveIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanArbiLostIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanBusErrorIrqFlg == (enCanIrqFLg)) \
|
||||
)
|
||||
|
||||
/*! Parameter validity check for CAN filter \a enCanFilter. */
|
||||
#define IS_CAN_FILTER_VALID(enCanFilter) \
|
||||
( (enCanFilter) <= CanFilterSel8)
|
||||
|
||||
/*! Parameter validity check for CAN filter count \a u8Count. */
|
||||
#define IS_CAN_FILTER_COUNT_VALID(u8Count) \
|
||||
( (u8Count) <= 8u)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can base functions
|
||||
**
|
||||
** \param [in] pstcCanInitCfg The can initial config struct.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_Init(const stc_can_init_config_t *pstcCanInitCfg)
|
||||
{
|
||||
uint8_t i;
|
||||
if (NULL != pstcCanInitCfg)
|
||||
{
|
||||
DDL_ASSERT(IS_CAN_FILTER_COUNT_VALID(pstcCanInitCfg->u8FilterCount));
|
||||
|
||||
CAN_RESET_ENABLE();
|
||||
M4_CAN->BT_f.PRESC = pstcCanInitCfg->stcCanBt.PRESC;
|
||||
M4_CAN->BT_f.SEG_1 = pstcCanInitCfg->stcCanBt.SEG_1;
|
||||
M4_CAN->BT_f.SEG_2 = pstcCanInitCfg->stcCanBt.SEG_2;
|
||||
M4_CAN->BT_f.SJW = pstcCanInitCfg->stcCanBt.SJW;
|
||||
M4_CAN->TCTRL_f.TSMODE = pstcCanInitCfg->enCanSTBMode;
|
||||
CAN_FilterConfig(pstcCanInitCfg->pstcFilter, pstcCanInitCfg->u8FilterCount);
|
||||
|
||||
CAN_RESET_DISABLE();
|
||||
M4_CAN->RCTRL_f.RBALL = pstcCanInitCfg->enCanRxBufAll;
|
||||
M4_CAN->RCTRL_f.ROM = pstcCanInitCfg->enCanRxBufMode;
|
||||
M4_CAN->RCTRL_f.SACK = pstcCanInitCfg->enCanSAck;
|
||||
M4_CAN->LIMIT_f.AFWL = pstcCanInitCfg->stcWarningLimit.CanWarningLimitVal;
|
||||
M4_CAN->LIMIT_f.EWL = pstcCanInitCfg->stcWarningLimit.CanErrorWarningLimitVal;
|
||||
|
||||
// Enable filters.
|
||||
for (i=0u; i<pstcCanInitCfg->u8FilterCount; i++)
|
||||
{
|
||||
CAN_FilterCmd(pstcCanInitCfg->pstcFilter[i].enFilterSel, Enable);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-Init (RESET CAN register)
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_DeInit(void)
|
||||
{
|
||||
CAN_RESET_ENABLE();
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can Mode
|
||||
**
|
||||
** \param [in] enMode The can mode enum. @ref en_can_mode_t
|
||||
** \param [in] enNewState The new state of the can filter chanel.
|
||||
** \arg Enable Enable filter.
|
||||
** \arg Disable Disable filter.
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState)
|
||||
{
|
||||
DDL_ASSERT(IS_CAN_MODE_VALID(enMode));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
|
||||
if(CanListenOnlyMode == enMode)
|
||||
{
|
||||
M4_CAN->TCMD_f.LOM = enNewState;
|
||||
}else
|
||||
{
|
||||
if(Enable == enNewState)
|
||||
{
|
||||
M4_CAN->CFG_STAT |= enMode;
|
||||
}else
|
||||
{
|
||||
M4_CAN->CFG_STAT &= ~enMode;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can acceptance filter
|
||||
**
|
||||
** \param [in] pstcFilter Pointer to a stc_can_filter_t type array.
|
||||
** @ref stc_can_filter_t
|
||||
** \param [in] u8FilterCount Number of filters that to be configured.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_FilterConfig(const stc_can_filter_t pstcFilter[], uint8_t u8FilterCount)
|
||||
{
|
||||
uint8_t i;
|
||||
|
||||
if(NULL != pstcFilter)
|
||||
{
|
||||
DDL_ASSERT(IS_CAN_FILTER_COUNT_VALID(u8FilterCount));
|
||||
|
||||
for (i=0u; i<u8FilterCount; i++)
|
||||
{
|
||||
DDL_ASSERT(IS_CAN_FILTER_VALID(pstcFilter[i].enFilterSel));
|
||||
//<<Acceptance filter address
|
||||
M4_CAN->ACFCTRL_f.ACFADR = pstcFilter[i].enFilterSel;
|
||||
//<<ID config
|
||||
M4_CAN->ACFCTRL_f.SELMASK = CAN_ACF_ID_REG_SEL;
|
||||
M4_CAN->ACF = pstcFilter[i].u32CODE;
|
||||
//<<MASK config
|
||||
M4_CAN->ACFCTRL_f.SELMASK = CAN_ACF_MASK_REG_SEL;
|
||||
M4_CAN->ACF = pstcFilter[i].u32MASK;
|
||||
//<<Frame format config
|
||||
M4_CAN->ACF_f.AIDEE = ((pstcFilter[i].enAcfFormat >> 1ul) & 0x01u);
|
||||
M4_CAN->ACF_f.AIDE = (pstcFilter[i].enAcfFormat & 0x01ul);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable the specified can acceptance filter.
|
||||
**
|
||||
** \param [in] enFilter Specifies a filter.
|
||||
** @ref en_can_filter_sel_t
|
||||
** \param [in] enNewState The new state of the specified filter.
|
||||
** \arg Enable Enable.
|
||||
** \arg Disable Disable.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_FilterCmd(en_can_filter_sel_t enFilter, en_functional_state_t enNewState)
|
||||
{
|
||||
uint8_t u8FilterSel;
|
||||
|
||||
DDL_ASSERT(IS_CAN_FILTER_VALID(enFilter));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
|
||||
u8FilterSel = (uint8_t)(1ul << enFilter);
|
||||
|
||||
if(Enable == enNewState)
|
||||
{
|
||||
M4_CAN->ACFEN |= u8FilterSel;
|
||||
}else
|
||||
{
|
||||
M4_CAN->ACFEN &= (uint8_t)(~u8FilterSel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can Tx frame set
|
||||
**
|
||||
** \param [in] pstcTxFrame The can Tx frame struct.
|
||||
** @ref stc_can_txframe_t
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame)
|
||||
{
|
||||
uint32_t u32TBUFAddr;
|
||||
|
||||
if(NULL != pstcTxFrame)
|
||||
{
|
||||
u32TBUFAddr = (uint32_t)&M4_CAN->TBUF;
|
||||
M4_CAN->TCMD_f.TBSEL = pstcTxFrame->enBufferSel;
|
||||
CAN_RW_MEM32(u32TBUFAddr) = pstcTxFrame->TBUF32_0;
|
||||
CAN_RW_MEM32(u32TBUFAddr+4) = pstcTxFrame->TBUF32_1;
|
||||
CAN_RW_MEM32(u32TBUFAddr+8) = pstcTxFrame->TBUF32_2[0];
|
||||
CAN_RW_MEM32(u32TBUFAddr+12) = pstcTxFrame->TBUF32_2[1];
|
||||
|
||||
if(CanSTBSel == pstcTxFrame->enBufferSel)
|
||||
{
|
||||
M4_CAN->TCTRL_f.TSNEXT = Enable;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can Tx Command
|
||||
**
|
||||
** \param [in] enTxCmd The can Tx Command.
|
||||
**
|
||||
** \retval Can Tx buffer status @ref en_can_tx_buf_status_t
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd)
|
||||
{
|
||||
DDL_ASSERT(IS_TX_CMD_VALID(enTxCmd));
|
||||
|
||||
M4_CAN->TCMD |= enTxCmd;
|
||||
|
||||
return (en_can_tx_buf_status_t)M4_CAN->TCTRL_f.TSSTAT;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can Rx frame
|
||||
**
|
||||
** \param [in] pstcRxFrame The can Rx frame.
|
||||
** @ref stc_can_rxframe_t
|
||||
** \retval Can rx buffer status @ref en_can_rx_buf_status_t
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame)
|
||||
{
|
||||
uint32_t u32RBUFAddr;
|
||||
|
||||
if(NULL != pstcRxFrame)
|
||||
{
|
||||
u32RBUFAddr = (uint32_t)&M4_CAN->RBUF;
|
||||
pstcRxFrame->RBUF32_0 = CAN_RW_MEM32(u32RBUFAddr);
|
||||
pstcRxFrame->RBUF32_1 = CAN_RW_MEM32(u32RBUFAddr+4);
|
||||
pstcRxFrame->RBUF32_2[0] = CAN_RW_MEM32(u32RBUFAddr+8);
|
||||
pstcRxFrame->RBUF32_2[1] = CAN_RW_MEM32(u32RBUFAddr+12);
|
||||
|
||||
M4_CAN->RCTRL_f.RREL = 1u;
|
||||
}
|
||||
return (en_can_rx_buf_status_t)M4_CAN->RCTRL_f.RSSTAT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Error Status
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval en_can_error_t The can error status
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_can_error_t CAN_ErrorStatusGet(void)
|
||||
{
|
||||
en_can_error_t enRet = UNKOWN_ERROR;
|
||||
|
||||
if(6u > M4_CAN->EALCAP_f.KOER)
|
||||
{
|
||||
enRet = (en_can_error_t)M4_CAN->EALCAP_f.KOER;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Status
|
||||
**
|
||||
** \param enCanStatus The can status
|
||||
** \arg true
|
||||
** \arg false
|
||||
** \retval bool
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
bool CAN_StatusGet(en_can_status_t enCanStatus)
|
||||
{
|
||||
bool bRet = false;
|
||||
DDL_ASSERT(IS_CAN_STATUS_VALID(enCanStatus));
|
||||
|
||||
if(M4_CAN->CFG_STAT & enCanStatus)
|
||||
{
|
||||
bRet = true;
|
||||
}
|
||||
return bRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can Interrupt enable
|
||||
**
|
||||
** \param [in] enCanIrqType The can interrupt type.
|
||||
** \param [in] enNewState The new state of the can interrupt.
|
||||
** \arg Enable Enable.
|
||||
** \arg Disable Disable.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState)
|
||||
{
|
||||
volatile uint32_t *u32pIE;
|
||||
|
||||
DDL_ASSERT(IS_CAN_IRQ_TYPE_VALID(enCanIrqType));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
|
||||
u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE);
|
||||
|
||||
if(Enable == enNewState)
|
||||
{
|
||||
*u32pIE |= enCanIrqType;
|
||||
}else
|
||||
{
|
||||
*u32pIE &= ~((uint32_t)enCanIrqType);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Interrupt Flag
|
||||
**
|
||||
** \param [in] enCanIrqFlgType The can interrupt Flag.
|
||||
**
|
||||
** \retval bool
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType)
|
||||
{
|
||||
volatile uint32_t *u32pIE = NULL;
|
||||
bool bRet = false;
|
||||
|
||||
DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType));
|
||||
|
||||
u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE);
|
||||
|
||||
if( *u32pIE & enCanIrqFlgType)
|
||||
{
|
||||
bRet = true;
|
||||
}
|
||||
return bRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear the can Interrupt Flag
|
||||
**
|
||||
** \param [in] enCanIrqFlgType The can interrupt type.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType)
|
||||
{
|
||||
volatile uint32_t *u32pIE = NULL;
|
||||
uint32_t u32IETempMsk = 0xFF2A00FF;
|
||||
|
||||
DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType));
|
||||
|
||||
u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE);
|
||||
|
||||
*u32pIE = (((*u32pIE)&u32IETempMsk) | (uint32_t)enCanIrqFlgType);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Rx Error Counter
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Error Counter(0~255)
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
uint8_t CAN_RxErrorCntGet(void)
|
||||
{
|
||||
return M4_CAN->RECNT;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Tx Error Counter
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Error Counter(0~255)
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
uint8_t CAN_TxErrorCntGet(void)
|
||||
{
|
||||
return M4_CAN->TECNT;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Arbitration lost captrue
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval address(0~31)
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
uint8_t CAN_ArbitrationLostCap(void)
|
||||
{
|
||||
return M4_CAN->EALCAP_f.ALC;
|
||||
}
|
||||
|
||||
|
||||
//@} // CanGroup
|
||||
|
||||
#endif /* DDL_CAN_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
||||
@@ -0,0 +1,532 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_can.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link CanGroup CAN description @endlink
|
||||
**
|
||||
** - 2018-12-13 CDT First version for Device Driver Library of CAN.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_can.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_CAN_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup CanGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
#define CAN_RESET_ENABLE() (M4_CAN->CFG_STAT_f.RESET = 1u)
|
||||
#define CAN_RESET_DISABLE() \
|
||||
do{ \
|
||||
do{ \
|
||||
M4_CAN->CFG_STAT_f.RESET = 0u; \
|
||||
}while(M4_CAN->CFG_STAT_f.RESET); \
|
||||
}while(0)
|
||||
|
||||
#define CAN_RW_MEM32(addr) (*(__IO uint32_t *)(addr))
|
||||
|
||||
#define CAN_ACF_ID_REG_SEL ((uint8_t)0x00u)
|
||||
#define CAN_ACF_MASK_REG_SEL ((uint8_t)0x01u)
|
||||
|
||||
|
||||
/*! Parameter validity check for CAN Mode \a CanMode. */
|
||||
#define IS_CAN_MODE_VALID(CanMode) \
|
||||
( (CanExternalLoopBackMode == (CanMode)) || \
|
||||
(CanInternalLoopBackMode == (CanMode)) || \
|
||||
(CanTxSignalPrimaryMode == (CanMode)) || \
|
||||
(CanTxSignalSecondaryMode == (CanMode)) || \
|
||||
(CanListenOnlyMode == (CanMode)) \
|
||||
)
|
||||
|
||||
/*! Parameter validity check for CAN Tx Cmd \a TxCmd. */
|
||||
#define IS_TX_CMD_VALID(TxCmd) \
|
||||
( (CanPTBTxCmd == (TxCmd)) || \
|
||||
(CanPTBTxAbortCmd == (TxCmd)) || \
|
||||
(CanSTBTxOneCmd == (TxCmd)) || \
|
||||
(CanSTBTxAllCmd == (TxCmd)) || \
|
||||
(CanSTBTxAbortCmd == (TxCmd)) \
|
||||
)
|
||||
|
||||
/*! Parameter validity check for CAN status \a enCanStatus. */
|
||||
#define IS_CAN_STATUS_VALID(enCanStatus) \
|
||||
( (CanRxActive == (enCanStatus)) || \
|
||||
(CanTxActive == (enCanStatus)) || \
|
||||
(CanBusoff == (enCanStatus)) \
|
||||
)
|
||||
|
||||
/*! Parameter validity check for CAN Irq type \a enCanIrqType. */
|
||||
#define IS_CAN_IRQ_TYPE_VALID(enCanIrqType) \
|
||||
( (CanRxIrqEn == (enCanIrqType)) || \
|
||||
(CanRxOverIrqEn == (enCanIrqType)) || \
|
||||
(CanRxBufFullIrqEn == (enCanIrqType)) || \
|
||||
(CanRxBufAlmostFullIrqEn == (enCanIrqType)) || \
|
||||
(CanTxPrimaryIrqEn == (enCanIrqType)) || \
|
||||
(CanTxSecondaryIrqEn == (enCanIrqType)) || \
|
||||
(CanErrorIrqEn == (enCanIrqType)) || \
|
||||
(CanErrorPassiveIrqEn == (enCanIrqType)) || \
|
||||
(CanArbiLostIrqEn == (enCanIrqType)) || \
|
||||
(CanBusErrorIrqEn == (enCanIrqType)) \
|
||||
)
|
||||
|
||||
/*! Parameter validity check for CAN Irq flag type \a enCanIrqFLg. */
|
||||
#define IS_CAN_IRQ_FLAG_VALID(enCanIrqFLg) \
|
||||
( (CanTxBufFullIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanRxIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanRxOverIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanRxBufFullIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanRxBufAlmostFullIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanTxPrimaryIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanTxSecondaryIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanErrorIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanAbortIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanErrorWarningIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanErrorPassivenodeIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanErrorPassiveIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanArbiLostIrqFlg == (enCanIrqFLg)) || \
|
||||
(CanBusErrorIrqFlg == (enCanIrqFLg)) \
|
||||
)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can base functions
|
||||
**
|
||||
** \param [in] pstcCanInitCfg The can initial config struct.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_Init(stc_can_init_config_t *pstcCanInitCfg)
|
||||
{
|
||||
if (NULL != pstcCanInitCfg)
|
||||
{
|
||||
M4_CAN->RCTRL_f.SACK = pstcCanInitCfg->enCanSAck;
|
||||
M4_CAN->TCTRL_f.TSMODE = pstcCanInitCfg->enCanSTBMode;
|
||||
M4_CAN->RCTRL_f.RBALL = pstcCanInitCfg->enCanRxBufAll;
|
||||
M4_CAN->RCTRL_f.ROM = pstcCanInitCfg->enCanRxBufMode;
|
||||
|
||||
M4_CAN->RTIE = 0x00u;
|
||||
|
||||
CAN_RESET_ENABLE();
|
||||
|
||||
M4_CAN->BT_f.PRESC = pstcCanInitCfg->stcCanBt.PRESC;
|
||||
M4_CAN->BT_f.SEG_1 = pstcCanInitCfg->stcCanBt.SEG_1;
|
||||
M4_CAN->BT_f.SEG_2 = pstcCanInitCfg->stcCanBt.SEG_2;
|
||||
M4_CAN->BT_f.SJW = pstcCanInitCfg->stcCanBt.SJW;
|
||||
|
||||
M4_CAN->LIMIT_f.AFWL = pstcCanInitCfg->stcWarningLimit.CanWarningLimitVal;
|
||||
M4_CAN->LIMIT_f.EWL = pstcCanInitCfg->stcWarningLimit.CanErrorWarningLimitVal;
|
||||
|
||||
CAN_RESET_DISABLE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-Init (RESET CAN register)
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_DeInit(void)
|
||||
{
|
||||
CAN_RESET_ENABLE();
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can Mode
|
||||
**
|
||||
** \param [in] enMode The can mode enum. @ref en_can_mode_t
|
||||
** \param [in] enNewState The new state of the can filter chanel.
|
||||
** \arg Enable Enable filter.
|
||||
** \arg Disable Disable filter.
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState)
|
||||
{
|
||||
DDL_ASSERT(IS_CAN_MODE_VALID(enMode));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
|
||||
if(CanListenOnlyMode == enMode)
|
||||
{
|
||||
M4_CAN->TCMD_f.LOM = enNewState;
|
||||
}else
|
||||
{
|
||||
if(Enable == enNewState)
|
||||
{
|
||||
M4_CAN->CFG_STAT |= enMode;
|
||||
}else
|
||||
{
|
||||
M4_CAN->CFG_STAT &= ~enMode;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can acceptance filter
|
||||
**
|
||||
** \param [in] pstcFilter The can filter config struct.
|
||||
** @ref stc_can_filter_t
|
||||
** \param [in] enNewState The new state of the can filter chanel.
|
||||
** \arg Enable Enable filter.
|
||||
** \arg Disable Disable filter.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_FilterConfig(const stc_can_filter_t *pstcFilter, en_functional_state_t enNewState)
|
||||
{
|
||||
if(NULL != pstcFilter)
|
||||
{
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
|
||||
CAN_RESET_ENABLE();
|
||||
|
||||
//<<Acceptance filter address
|
||||
M4_CAN->ACFCTRL_f.ACFADR = pstcFilter->enFilterSel;
|
||||
|
||||
//<<ID config
|
||||
M4_CAN->ACFCTRL_f.SELMASK = CAN_ACF_ID_REG_SEL;
|
||||
M4_CAN->ACF = pstcFilter->u32CODE;
|
||||
|
||||
//<<MASK config
|
||||
M4_CAN->ACFCTRL_f.SELMASK = CAN_ACF_MASK_REG_SEL;
|
||||
M4_CAN->ACF = pstcFilter->u32MASK;
|
||||
|
||||
//<<Frame format config
|
||||
M4_CAN->ACF_f.AIDEE = ((pstcFilter->enAcfFormat >> 1ul) & 0x01u);
|
||||
M4_CAN->ACF_f.AIDE = (pstcFilter->enAcfFormat & 0x01ul);
|
||||
|
||||
if(Enable == enNewState)
|
||||
{
|
||||
M4_CAN->ACFEN |= (uint8_t)(1ul << pstcFilter->enFilterSel);
|
||||
}else
|
||||
{
|
||||
M4_CAN->ACFEN &= (uint8_t)(~(1ul << (pstcFilter->enFilterSel)));
|
||||
}
|
||||
|
||||
CAN_RESET_DISABLE();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can Tx frame set
|
||||
**
|
||||
** \param [in] pstcTxFrame The can Tx frame struct.
|
||||
** @ref stc_can_txframe_t
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame)
|
||||
{
|
||||
uint32_t u32TBUFAddr;
|
||||
|
||||
if(NULL != pstcTxFrame)
|
||||
{
|
||||
u32TBUFAddr = (uint32_t)&M4_CAN->TBUF;
|
||||
M4_CAN->TCMD_f.TBSEL = pstcTxFrame->enBufferSel;
|
||||
CAN_RW_MEM32(u32TBUFAddr) = pstcTxFrame->TBUF32_0;
|
||||
CAN_RW_MEM32(u32TBUFAddr+4) = pstcTxFrame->TBUF32_1;
|
||||
CAN_RW_MEM32(u32TBUFAddr+8) = pstcTxFrame->TBUF32_2[0];
|
||||
CAN_RW_MEM32(u32TBUFAddr+12) = pstcTxFrame->TBUF32_2[1];
|
||||
|
||||
if(CanSTBSel == pstcTxFrame->enBufferSel)
|
||||
{
|
||||
M4_CAN->TCTRL_f.TSNEXT = Enable;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can Tx Command
|
||||
**
|
||||
** \param [in] enTxCmd The can Tx Command.
|
||||
**
|
||||
** \retval Can Tx buffer status @ref en_can_tx_buf_status_t
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd)
|
||||
{
|
||||
DDL_ASSERT(IS_TX_CMD_VALID(enTxCmd));
|
||||
|
||||
M4_CAN->TCMD |= enTxCmd;
|
||||
|
||||
return (en_can_tx_buf_status_t)M4_CAN->TCTRL_f.TSSTAT;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can Rx frame
|
||||
**
|
||||
** \param [in] pstcRxFrame The can Rx frame.
|
||||
** @ref stc_can_rxframe_t
|
||||
** \retval Can rx buffer status @ref en_can_rx_buf_status_t
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame)
|
||||
{
|
||||
uint32_t u32RBUFAddr;
|
||||
|
||||
if(NULL != pstcRxFrame)
|
||||
{
|
||||
u32RBUFAddr = (uint32_t)&M4_CAN->RBUF;
|
||||
pstcRxFrame->RBUF32_0 = CAN_RW_MEM32(u32RBUFAddr);
|
||||
pstcRxFrame->RBUF32_1 = CAN_RW_MEM32(u32RBUFAddr+4);
|
||||
pstcRxFrame->RBUF32_2[0] = CAN_RW_MEM32(u32RBUFAddr+8);
|
||||
pstcRxFrame->RBUF32_2[1] = CAN_RW_MEM32(u32RBUFAddr+12);
|
||||
|
||||
M4_CAN->RCTRL_f.RREL = 1u;
|
||||
}
|
||||
return (en_can_rx_buf_status_t)M4_CAN->RCTRL_f.RSSTAT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Error Status
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval en_can_error_t The can error status
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_can_error_t CAN_ErrorStatusGet(void)
|
||||
{
|
||||
en_can_error_t enRet = UNKOWN_ERROR;
|
||||
|
||||
if(6u > M4_CAN->EALCAP_f.KOER)
|
||||
{
|
||||
enRet = (en_can_error_t)M4_CAN->EALCAP_f.KOER;
|
||||
}
|
||||
return enRet;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Status
|
||||
**
|
||||
** \param enCanStatus The can status
|
||||
** \arg true
|
||||
** \arg false
|
||||
** \retval bool
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
bool CAN_StatusGet(en_can_status_t enCanStatus)
|
||||
{
|
||||
bool bRet = false;
|
||||
DDL_ASSERT(IS_CAN_STATUS_VALID(enCanStatus));
|
||||
|
||||
if(M4_CAN->CFG_STAT & enCanStatus)
|
||||
{
|
||||
bRet = true;
|
||||
}
|
||||
return bRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Configures the can Interrupt enable
|
||||
**
|
||||
** \param [in] enCanIrqType The can interrupt type.
|
||||
** \param [in] enNewState The new state of the can interrupt.
|
||||
** \arg Enable Enable.
|
||||
** \arg Disable Disable.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState)
|
||||
{
|
||||
volatile uint32_t *u32pIE;
|
||||
|
||||
DDL_ASSERT(IS_CAN_IRQ_TYPE_VALID(enCanIrqType));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
|
||||
u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE);
|
||||
|
||||
if(Enable == enNewState)
|
||||
{
|
||||
*u32pIE |= enCanIrqType;
|
||||
}else
|
||||
{
|
||||
*u32pIE &= ~((uint32_t)enCanIrqType);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Interrupt Flag
|
||||
**
|
||||
** \param [in] enCanIrqFlgType The can interrupt Flag.
|
||||
**
|
||||
** \retval bool
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType)
|
||||
{
|
||||
volatile uint32_t *u32pIE = NULL;
|
||||
bool bRet = false;
|
||||
|
||||
DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType));
|
||||
|
||||
u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE);
|
||||
|
||||
if( *u32pIE & enCanIrqFlgType)
|
||||
{
|
||||
bRet = true;
|
||||
}
|
||||
return bRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear the can Interrupt Flag
|
||||
**
|
||||
** \param [in] enCanIrqFlgType The can interrupt type.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType)
|
||||
{
|
||||
volatile uint32_t *u32pIE = NULL;
|
||||
uint32_t u32IETempMsk = 0xFF2A00FF;
|
||||
|
||||
DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType));
|
||||
|
||||
u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE);
|
||||
|
||||
*u32pIE = (((*u32pIE)&u32IETempMsk) | (uint32_t)enCanIrqFlgType);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Rx Error Counter
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Error Counter(0~255)
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
uint8_t CAN_RxErrorCntGet(void)
|
||||
{
|
||||
return M4_CAN->RECNT;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Tx Error Counter
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Error Counter(0~255)
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
uint8_t CAN_TxErrorCntGet(void)
|
||||
{
|
||||
return M4_CAN->TECNT;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the can Arbitration lost captrue
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval address(0~31)
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
uint8_t CAN_ArbitrationLostCap(void)
|
||||
{
|
||||
return M4_CAN->EALCAP_f.ALC;
|
||||
}
|
||||
|
||||
|
||||
//@} // CanGroup
|
||||
|
||||
#endif /* DDL_CAN_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,327 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_crc.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link CrcGroup Crc description @endlink
|
||||
**
|
||||
** - 2019-03-07 CDT First version for Device Driver Library of Crc.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_crc.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_CRC_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup CrcGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Definition of CRC16 data register. */
|
||||
#define M4_CRC16_DAT (*((__IO uint16_t *)&M4_CRC->DAT0))
|
||||
|
||||
/* Definition of CRC16 checksum register. */
|
||||
#define M4_CRC16_RSLT (*((__IO uint16_t *)&M4_CRC->RESLT))
|
||||
|
||||
/* Definition of CRC16 initial value register. */
|
||||
#define M4_CRC16_INIT (M4_CRC16_RSLT)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
static uint32_t CRC_ProcChecksum(uint32_t u32Checksum);
|
||||
static uint32_t CRC_ReverseBits(uint32_t u32Data);
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Initialize the CRC.
|
||||
**
|
||||
** \param [in] u32Config Bit[1]: CRC_SEL_16B or CRC_SEL_32B.
|
||||
** Bit[2]: CRC_REFIN_DISABLE or CRC_REFIN_ENABLE.
|
||||
** Bit[3]: CRC_REFOUT_DISABLE or CRC_REFOUT_ENABLE.
|
||||
** Bit[4]: CRC_XOROUT_DISABLE or CRC_XOROUT_ENABLE.
|
||||
** See the definitions for details.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CRC_Init(uint32_t u32Config)
|
||||
{
|
||||
u32Config &= CRC_CONFIG_MASK;
|
||||
|
||||
M4_CRC->CR = u32Config;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CRC16 calculation.
|
||||
**
|
||||
** \param [in] u16InitVal Initial value of CRC16.
|
||||
**
|
||||
** \param [in] pu16Data Pointer to the buffer containing the data to be computed.
|
||||
**
|
||||
** \param [in] u32Length Length of the buffer to be computed.
|
||||
**
|
||||
** \retval 16-bit CRC checksum.
|
||||
**
|
||||
******************************************************************************/
|
||||
uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length)
|
||||
{
|
||||
uint16_t u16Ret = 0u;
|
||||
uint32_t u32Count;
|
||||
|
||||
if (NULL != pu16Data)
|
||||
{
|
||||
M4_CRC16_INIT = u16InitVal;
|
||||
|
||||
for (u32Count = 0u; u32Count < u32Length; u32Count++)
|
||||
{
|
||||
M4_CRC16_DAT = pu16Data[u32Count];
|
||||
}
|
||||
|
||||
u16Ret = M4_CRC16_RSLT;
|
||||
}
|
||||
|
||||
return u16Ret;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CRC32 calculation.
|
||||
**
|
||||
** \param [in] u32InitVal Initial value of CRC32.
|
||||
**
|
||||
** \param [in] pu32Data Pointer to the buffer containing the data to be computed.
|
||||
**
|
||||
** \param [in] u32Length Length of the buffer to be computed.
|
||||
**
|
||||
** \retval 32-bit CRC checksum.
|
||||
**
|
||||
******************************************************************************/
|
||||
uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length)
|
||||
{
|
||||
uint32_t u32Ret = 0u;
|
||||
uint32_t u32Count;
|
||||
|
||||
M4_CRC->RESLT = u32InitVal;
|
||||
|
||||
if (NULL != pu32Data)
|
||||
{
|
||||
for (u32Count = 0u; u32Count < u32Length; u32Count++)
|
||||
{
|
||||
M4_CRC->DAT0 = pu32Data[u32Count];
|
||||
}
|
||||
|
||||
u32Ret = M4_CRC->RESLT;
|
||||
}
|
||||
|
||||
return u32Ret;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CRC16 check.
|
||||
**
|
||||
** \param [in] u16InitVal Initial value of CRC16.
|
||||
**
|
||||
** \param [in] u16Checksum CRC16 checksum of the source data.
|
||||
**
|
||||
** \param [in] pu16Data Pointer to the buffer containing the data to be checked.
|
||||
**
|
||||
** \param [in] u32Length Length of the buffer to be checked.
|
||||
**
|
||||
** \retval true CRC16 checks successfully.
|
||||
** \retval false CRC16 checks unsuccessfully.
|
||||
**
|
||||
******************************************************************************/
|
||||
bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16Checksum, const uint16_t *pu16Data, uint32_t u32Length)
|
||||
{
|
||||
bool bRet = false;
|
||||
uint32_t u32Count;
|
||||
uint16_t u16CrcChecksum;
|
||||
|
||||
if (NULL != pu16Data)
|
||||
{
|
||||
u16CrcChecksum = (uint16_t)CRC_ProcChecksum((uint32_t)u16Checksum);
|
||||
M4_CRC16_INIT = u16InitVal;
|
||||
|
||||
for (u32Count = 0u; u32Count < u32Length; u32Count++)
|
||||
{
|
||||
M4_CRC16_DAT = pu16Data[u32Count];
|
||||
}
|
||||
|
||||
M4_CRC16_DAT = u16CrcChecksum;
|
||||
|
||||
if (bM4_CRC_FLG_FLAG)
|
||||
{
|
||||
bRet = true;
|
||||
}
|
||||
}
|
||||
|
||||
return bRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CRC32 check.
|
||||
**
|
||||
** \param [in] u32InitVal Initial value of CRC32.
|
||||
**
|
||||
** \param [in] u32Checksum CRC32 checksum of the source data.
|
||||
**
|
||||
** \param [in] pu32Data Pointer to the buffer containing the data to be checked.
|
||||
**
|
||||
** \param [in] u32Length Length of the buffer to be checked.
|
||||
**
|
||||
** \retval true CRC32 checks successfully.
|
||||
** \retval false CRC32 checks unsuccessfully.
|
||||
**
|
||||
******************************************************************************/
|
||||
bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32Checksum, const uint32_t *pu32Data, uint32_t u32Length)
|
||||
{
|
||||
bool bRet = false;
|
||||
uint32_t u32Count;
|
||||
uint32_t u32CrcChecksum;
|
||||
|
||||
if (NULL != pu32Data)
|
||||
{
|
||||
u32CrcChecksum = CRC_ProcChecksum(u32Checksum);
|
||||
M4_CRC->RESLT = u32InitVal;
|
||||
|
||||
for (u32Count = 0u; u32Count < u32Length; u32Count++)
|
||||
{
|
||||
M4_CRC->DAT0 = pu32Data[u32Count];
|
||||
}
|
||||
|
||||
M4_CRC->DAT0 = u32CrcChecksum;
|
||||
|
||||
if (bM4_CRC_FLG_FLAG)
|
||||
{
|
||||
bRet = true;
|
||||
}
|
||||
}
|
||||
|
||||
return bRet;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Processes the checksum of CRC.
|
||||
**
|
||||
** \param [in] u32Checksum The checksum of CRC16 or CRC32.
|
||||
**
|
||||
** \retval 32-bit new checksum will be used by CRC checking.
|
||||
**
|
||||
******************************************************************************/
|
||||
static uint32_t CRC_ProcChecksum(uint32_t u32Checksum)
|
||||
{
|
||||
uint8_t i;
|
||||
uint8_t u8Size = 16u;
|
||||
uint8_t u8Offset;
|
||||
uint32_t u32Config;
|
||||
uint32_t u32FinalChecksum;
|
||||
uint32_t u32Temp;
|
||||
|
||||
u32Config = M4_CRC->CR;
|
||||
u32FinalChecksum = u32Checksum;
|
||||
|
||||
if ((u32Config & CRC_SEL_32B) == CRC_SEL_32B)
|
||||
{
|
||||
u8Size = 32u;
|
||||
}
|
||||
|
||||
if ((u32Config & CRC_REFOUT_ENABLE) == CRC_REFOUT_DISABLE)
|
||||
{
|
||||
/* Bits reversing. */
|
||||
u32FinalChecksum = CRC_ReverseBits(u32Checksum);
|
||||
if (u8Size == 16u)
|
||||
{
|
||||
u32FinalChecksum >>= 16u;
|
||||
u32FinalChecksum &= 0xFFFFu;
|
||||
}
|
||||
}
|
||||
|
||||
if ((u32Config & CRC_XOROUT_ENABLE) == CRC_XOROUT_DISABLE)
|
||||
{
|
||||
/* Bits NOT. */
|
||||
u32FinalChecksum = ~u32FinalChecksum;
|
||||
}
|
||||
|
||||
if ((u32Config & CRC_REFIN_ENABLE) == CRC_REFIN_DISABLE)
|
||||
{
|
||||
u8Size /= 8u;
|
||||
/* Bits reversing in bytes. */
|
||||
for (i = 0u; i < u8Size; i++)
|
||||
{
|
||||
u8Offset = i * 8u;
|
||||
u32Temp = (u32FinalChecksum >> u8Offset) & 0xFFul;
|
||||
u32Temp = CRC_ReverseBits(u32Temp);
|
||||
u32Temp = u32Temp >> (24u - u8Offset);
|
||||
u32FinalChecksum &= ~((uint32_t)0xFF << u8Offset);
|
||||
u32FinalChecksum |= u32Temp;
|
||||
}
|
||||
}
|
||||
|
||||
return u32FinalChecksum;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Reverse bits.
|
||||
**
|
||||
** \param [in] u32Data The data to be reversed bits.
|
||||
**
|
||||
** \retval 32-bit new data.
|
||||
**
|
||||
******************************************************************************/
|
||||
static uint32_t CRC_ReverseBits(uint32_t u32Data)
|
||||
{
|
||||
u32Data = (((u32Data & 0xAAAAAAAAul) >> 1u) | ((u32Data & 0x55555555ul) << 1u));
|
||||
u32Data = (((u32Data & 0xCCCCCCCCul) >> 2u) | ((u32Data & 0x33333333ul) << 2u));
|
||||
u32Data = (((u32Data & 0xF0F0F0F0ul) >> 4u) | ((u32Data & 0x0F0F0F0Ful) << 4u));
|
||||
u32Data = (((u32Data & 0xFF00FF00ul) >> 8u) | ((u32Data & 0x00FF00FFul) << 8u));
|
||||
|
||||
return ((u32Data >> 16u) | (u32Data << 16u));
|
||||
}
|
||||
|
||||
//@} // CrcGroup
|
||||
|
||||
#endif /* DDL_CRC_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,975 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_dcu.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link DcuGroup DCU description @endlink
|
||||
**
|
||||
** - 2018-10-15 CDT First version for Device Driver Library of DCU.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_dcu.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_DCU_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup DcuGroup
|
||||
******************************************************************************/
|
||||
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*!< Parameter valid check for DCU Instances. */
|
||||
#define IS_VALID_DCU(__DCUx__) \
|
||||
( (M4_DCU1 == (__DCUx__)) || \
|
||||
(M4_DCU2 == (__DCUx__)) || \
|
||||
(M4_DCU3 == (__DCUx__)) || \
|
||||
(M4_DCU4 == (__DCUx__)))
|
||||
|
||||
/*!< Parameter valid check for DCU DATA register. */
|
||||
#define IS_VALID_DCU_DATA_REG(x) \
|
||||
( (DcuRegisterData0 == (x)) || \
|
||||
(DcuRegisterData1 == (x)) || \
|
||||
(DcuRegisterData2 == (x)))
|
||||
|
||||
/*!< Parameter valid check for DCU operation mode. */
|
||||
#define IS_VALID_DCU_OPERATION(x) \
|
||||
( (DcuOpAdd == (x)) || \
|
||||
(DcuOpSub == (x)) || \
|
||||
(DcuInvalid == (x)) || \
|
||||
(DcuOpCompare == (x)) || \
|
||||
(DcuHwTrigOpAdd == (x)) || \
|
||||
(DcuHwTrigOpSub == (x)))
|
||||
|
||||
/*!< Parameter valid check for DCU data size. */
|
||||
#define IS_VALID_DCU_DATAZ_SIZE(x) \
|
||||
( (DcuDataBit8 == (x)) || \
|
||||
(DcuDataBit16 == (x)) || \
|
||||
(DcuDataBit32 == (x)))
|
||||
|
||||
/*!< Parameter valid check for DCU compare trigger mode type. */
|
||||
#define IS_VALID_DCU_CMP_TRIG_MODE(x) \
|
||||
( (DcuCmpTrigbyData0 == (x)) || \
|
||||
(DcuCmpTrigbyData012 == (x)))
|
||||
|
||||
/*!< Parameter valid check for DCU interrupt. */
|
||||
#define IS_VALID_DCU_INT(x) \
|
||||
( (DcuIntOp == (x)) || \
|
||||
(DcuIntLs2 == (x)) || \
|
||||
(DcuIntEq2 == (x)) || \
|
||||
(DcuIntGt2 == (x)) || \
|
||||
(DcuIntLs1 == (x)) || \
|
||||
(DcuIntEq1 == (x)) || \
|
||||
(DcuIntGt1 == (x)))
|
||||
|
||||
/*!< Parameter valid check for DCU interrupt mode. */
|
||||
#define IS_VALID_DCU_INT_WIN_MODE(x) \
|
||||
( (DcuIntInvalid == (x)) || \
|
||||
(DcuWinIntInvalid == (x)) || \
|
||||
(DcuInsideWinCmpInt == (x)) || \
|
||||
(DcuOutsideWinCmpInt == (x)))
|
||||
|
||||
/*!< Parameter valid check for external trigger event. */
|
||||
#define IS_VALID_TRG_SRC_EVENT(x) \
|
||||
( (((x) >= EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \
|
||||
(((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \
|
||||
(((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \
|
||||
(((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \
|
||||
(((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \
|
||||
(((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \
|
||||
(((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \
|
||||
(((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \
|
||||
(((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \
|
||||
(((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \
|
||||
(((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \
|
||||
(((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \
|
||||
(((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \
|
||||
(((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \
|
||||
(((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \
|
||||
(((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \
|
||||
(((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \
|
||||
(((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \
|
||||
(((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \
|
||||
(((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \
|
||||
(((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \
|
||||
(((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \
|
||||
(((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \
|
||||
(((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \
|
||||
(((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \
|
||||
(((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \
|
||||
((x) == EVT_WDT_REFUDF) || \
|
||||
(((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \
|
||||
(((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \
|
||||
(((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \
|
||||
((x) == EVT_MAX))
|
||||
|
||||
/*! Parameter valid check for DCU common trigger. */
|
||||
#define IS_DCU_COM_TRIGGER(x) \
|
||||
( ((x) == DcuComTrigger_1) || \
|
||||
((x) == DcuComTrigger_2) || \
|
||||
((x) == DcuComTrigger_1_2))
|
||||
|
||||
/*!< Get the specified DATA register address of the specified DCU unit */
|
||||
#define DCU_DATAx(__DCUx__, __DATAx__) ((uint32_t)(&(__DCUx__)->DATA0) + ((uint32_t)(__DATAx__)) * 4u)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx);
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Initializes a DCU.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] pstcInitCfg Pointer to DCU configure structure
|
||||
** \arg This parameter detail refer @ref stc_dcu_init_t
|
||||
**
|
||||
** \retval Ok DCU is initialized normally
|
||||
** \retval ErrorInvalidParameter If one of following cases matches:
|
||||
** - DCUx is invalid
|
||||
** - pstcInitCfg == NULL
|
||||
** - Other invalid configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check for DCUx && pstcInitCfg pointer */
|
||||
if ((IS_VALID_DCU(DCUx)) && (NULL != pstcInitCfg))
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enIntCmd));
|
||||
DDL_ASSERT(IS_VALID_DCU_OPERATION(pstcInitCfg->enOperation));
|
||||
DDL_ASSERT(IS_VALID_DCU_DATAZ_SIZE(pstcInitCfg->enDataSize));
|
||||
DDL_ASSERT(IS_VALID_DCU_INT_WIN_MODE(pstcInitCfg->enIntWinMode));
|
||||
DDL_ASSERT(IS_VALID_DCU_CMP_TRIG_MODE(pstcInitCfg->enCmpTriggerMode));
|
||||
|
||||
/* De-initialize dcu register value */
|
||||
DCUx->CTL = 0ul;
|
||||
DCUx->INTSEL = 0ul;
|
||||
DCUx->FLAGCLR = 0x7Ful;
|
||||
|
||||
/* Set dcu operation mode */
|
||||
DCUx->CTL_f.MODE = (uint32_t)pstcInitCfg->enOperation;
|
||||
|
||||
/* Set dcu data sieze */
|
||||
DCUx->CTL_f.DATASIZE = (uint32_t)pstcInitCfg->enDataSize;
|
||||
|
||||
/* Set dcu compare trigger mode */
|
||||
DCUx->CTL_f.COMP_TRG = (uint32_t)pstcInitCfg->enCmpTriggerMode;
|
||||
|
||||
/* Set dcu interrupt window mode */
|
||||
DCUx->INTSEL_f.INT_WIN = (uint32_t)pstcInitCfg->enIntWinMode;
|
||||
|
||||
DCUx->INTSEL = pstcInitCfg->u32IntSel;
|
||||
DCUx->CTL_f.INTEN = (uint32_t)(pstcInitCfg->enIntCmd);
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-Initializes a DCU.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
**
|
||||
** \retval Ok De-Initialized successfully.
|
||||
** \retval ErrorInvalidParameter DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
__IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx);
|
||||
|
||||
/* Check for DCUx pointer */
|
||||
if (IS_VALID_DCU(DCUx))
|
||||
{
|
||||
/* De-initialize dcu register value */
|
||||
DCUx->CTL = 0u;
|
||||
DCUx->INTSEL = 0u;
|
||||
DCUx->FLAGCLR = 0x7Fu;
|
||||
*TRGSELx = EVT_MAX;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set DCU operation mode.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enMode DCU operation mode
|
||||
** \arg DcuInvalid Invalid
|
||||
** \arg DcuOpAdd Operation: Add
|
||||
** \arg DcuOpSub Operation: Sub
|
||||
** \arg DcuHwTrigOpAdd Operation: Hardware trigger Add
|
||||
** \arg DcuHwTrigOpSub Operation: Hardware trigger Sub
|
||||
** \arg DcuOpCompare Operation: Compare
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_operation_mode_t enMode)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check for DCUx pointer */
|
||||
if (IS_VALID_DCU(DCUx))
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU_OPERATION(enMode));
|
||||
|
||||
DCUx->CTL_f.MODE = (uint32_t)enMode;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get DCU operation mode.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
**
|
||||
** \retval DcuInvalid Invalid
|
||||
** \retval DcuOpAdd Operation: Add
|
||||
** \retval DcuOpSub Operation: Sub
|
||||
** \retval DcuHwTrigOpAdd Operation: Hardware trigger Add
|
||||
** \retval DcuHwTrigOpSub Operation: Hardware trigger Sub
|
||||
** \retval DcuOpCompare Operation: Compare
|
||||
**
|
||||
******************************************************************************/
|
||||
en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx)
|
||||
{
|
||||
/* Check for DCUx pointer */
|
||||
DDL_ASSERT(IS_VALID_DCU(DCUx));
|
||||
|
||||
return (en_dcu_operation_mode_t)DCUx->CTL_f.MODE;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set DCU data size.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enSize DCU data size
|
||||
** \arg DcuDataBit8 8 bit
|
||||
** \arg DcuDataBit16 16 bit
|
||||
** \arg DcuDataBit32 32 bit
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check for DCUx pointer */
|
||||
if (IS_VALID_DCU(DCUx))
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU_DATAZ_SIZE(enSize));
|
||||
|
||||
DCUx->CTL_f.DATASIZE = (uint32_t)enSize;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get DCU data size.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
**
|
||||
** \retval DcuDataBit8 8 bit
|
||||
** \retval DcuDataBit16 16 bit
|
||||
** \retval DcuDataBit32 32 bit
|
||||
**
|
||||
******************************************************************************/
|
||||
en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx)
|
||||
{
|
||||
/* Check for DCUx pointer */
|
||||
DDL_ASSERT(IS_VALID_DCU(DCUx));
|
||||
|
||||
return (en_dcu_data_size_t)(DCUx->CTL_f.DATASIZE);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set DCU interrup window.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enIntWinMode Interrupt window mode
|
||||
** \arg DcuIntInvalid DCU don't occur interrupt
|
||||
** \arg DcuWinIntInvalid DCU window interrupt is invalid.
|
||||
** \arg DcuInsideWinCmpInt DCU occur interrupt when DATA2 <= DATA0 <= DATA2
|
||||
** \arg DcuOutsideWinCmpInt DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_int_win_mode_t enIntWinMode)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU_INT_WIN_MODE(enIntWinMode));
|
||||
|
||||
/* Check for DCUx pointer */
|
||||
if (IS_VALID_DCU(DCUx))
|
||||
{
|
||||
DCUx->INTSEL_f.INT_WIN = (uint32_t)enIntWinMode;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get DCU interrup window.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
**
|
||||
** \retval DcuIntInvalid DCU don't occur interrupt
|
||||
** \retval DcuWinIntInvalid DCU window interrupt is invalid.
|
||||
** \retval DcuInsideWinCmpInt DCU occur interrupt when DATA2 <= DATA0 <= DATA2
|
||||
** \retval DcuOutsideWinCmpInt DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2
|
||||
**
|
||||
******************************************************************************/
|
||||
en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx)
|
||||
{
|
||||
/* Check for DCUx pointer */
|
||||
DDL_ASSERT(IS_VALID_DCU(DCUx));
|
||||
|
||||
return (en_dcu_int_win_mode_t)(DCUx->INTSEL_f.INT_WIN);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set DCU compare trigger mode.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enTriggerMode DCU compare trigger mode
|
||||
** \arg DcuCmpTrigbyData0 DCU compare triggered by DATA0
|
||||
** \arg DcuCmpTrigbyData012 DCU compare triggered by DATA0 or DATA1 or DATA2
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_cmp_trigger_mode_t enTriggerMode)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check for DCUx pointer */
|
||||
if (IS_VALID_DCU(DCUx))
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU_CMP_TRIG_MODE(enTriggerMode));
|
||||
|
||||
DCUx->CTL_f.COMP_TRG = (uint32_t)enTriggerMode;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get DCU compare trigger mode.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
**
|
||||
** \retval DcuCmpTrigbyData0 DCU compare triggered by DATA0
|
||||
** \retval DcuCmpTrigbyData012 DCU compare triggered by DATA0 or DATA1 or DATA2
|
||||
**
|
||||
******************************************************************************/
|
||||
en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx)
|
||||
{
|
||||
/* Check for DCUx pointer */
|
||||
DDL_ASSERT(IS_VALID_DCU(DCUx));
|
||||
|
||||
return (en_dcu_cmp_trigger_mode_t)(DCUx->CTL_f.COMP_TRG);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable DCU interrupt.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enCmd DCU interrupt state
|
||||
** \arg Enable Enable the DCU interrupt function
|
||||
** \arg Disable Disable the DCU interrupt function
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_IrqCmd(M4_DCU_TypeDef *DCUx, en_functional_state_t enCmd)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check for DCUx pointer */
|
||||
if (IS_VALID_DCU(DCUx))
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd));
|
||||
|
||||
DCUx->CTL_f.INTEN = (uint32_t)(enCmd);
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the specified DCU flag
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enFlag The specified DCU flag
|
||||
** \arg DcuIntOp DCU overflow or underflow
|
||||
** \arg DcuIntLs2 DCU DATA0 < DATA2
|
||||
** \arg DcuIntEq2 DCU DATA0 = DATA2
|
||||
** \arg DcuIntGt2 DCU DATA0 > DATA2
|
||||
** \arg DcuIntLs1 DCU DATA0 < DATA1
|
||||
** \arg DcuIntEq1 DCU DATA0 = DATA1
|
||||
** \arg DcuIntGt1 DCU DATA0 > DATA1
|
||||
**
|
||||
** \retval Set Flag is set.
|
||||
** \retval Reset Flag is reset or enStatus is invalid.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag)
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU(DCUx));
|
||||
DDL_ASSERT(IS_VALID_DCU_INT(enFlag));
|
||||
|
||||
return ((DCUx->FLAG & enFlag) ? Set : Reset);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear the specified DCU flag
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enFlag the specified DCU flag
|
||||
** \arg DcuIntOp DCU overflow or underflow
|
||||
** \arg DcuIntLs2 DCU DATA0 < DATA2
|
||||
** \arg DcuIntEq2 DCU DATA0 = DATA2
|
||||
** \arg DcuIntGt2 DCU DATA0 > DATA2
|
||||
** \arg DcuIntLs1 DCU DATA0 < DATA1
|
||||
** \arg DcuIntEq1 DCU DATA0 = DATA1
|
||||
** \arg DcuIntGt1 DCU DATA0 > DATA1
|
||||
**
|
||||
** \retval Ok Clear flag successfully.
|
||||
** \retval ErrorInvalidParameter DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check for DCUx pointer */
|
||||
if (IS_VALID_DCU(DCUx))
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU_INT(enFlag));
|
||||
DCUx->FLAGCLR = (uint32_t)enFlag;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable/Disable DCU interrupt.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enIntSel DCU interrupt selection
|
||||
** \arg DcuIntOp DCU overflow or underflow
|
||||
** \arg DcuIntLs2 DCU DATA0 < DATA2
|
||||
** \arg DcuIntEq2 DCU DATA0 = DATA2
|
||||
** \arg DcuIntGt2 DCU DATA0 > DATA2
|
||||
** \arg DcuIntLs1 DCU DATA0 < DATA1
|
||||
** \arg DcuIntEq1 DCU DATA0 = DATA1
|
||||
** \arg DcuIntGt1 DCU DATA0 > DATA1
|
||||
** \param [in] enCmd DCU interrupt functional state
|
||||
** \arg Enable Enable the specified DCU interrupt function
|
||||
** \arg Disable Disable the specified DCU interrupt function
|
||||
**
|
||||
** \retval Ok Configure successfully.
|
||||
** \retval ErrorInvalidParameter If one of following cases matches:
|
||||
** - DCUx is invalid
|
||||
** - enIntSel is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_int_sel_t enIntSel,
|
||||
en_functional_state_t enCmd)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check for DCUx pointer */
|
||||
if (IS_VALID_DCU(DCUx))
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU_INT(enIntSel));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd));
|
||||
|
||||
enRet = Ok;
|
||||
switch(enIntSel)
|
||||
{
|
||||
case DcuIntOp:
|
||||
DCUx->INTSEL_f.INT_OP = (uint32_t)enCmd;
|
||||
break;
|
||||
case DcuIntLs2:
|
||||
DCUx->INTSEL_f.INT_LS2 = (uint32_t)enCmd;
|
||||
break;
|
||||
case DcuIntEq2:
|
||||
DCUx->INTSEL_f.INT_EQ2 = (uint32_t)enCmd;
|
||||
break;
|
||||
case DcuIntGt2:
|
||||
DCUx->INTSEL_f.INT_GT2 = (uint32_t)enCmd;
|
||||
break;
|
||||
case DcuIntLs1:
|
||||
DCUx->INTSEL_f.INT_LS1 = (uint32_t)enCmd;
|
||||
break;
|
||||
case DcuIntEq1:
|
||||
DCUx->INTSEL_f.INT_EQ1 = (uint32_t)enCmd;
|
||||
break;
|
||||
case DcuIntGt1:
|
||||
DCUx->INTSEL_f.INT_GT1 = (uint32_t)enCmd;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Read DCU register DATAx
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enDataReg The specified DATA register.
|
||||
** \arg DcuRegisterData0 DCU register DATA0
|
||||
** \arg DcuRegisterData1 DCU register DATA1
|
||||
** \arg DcuRegisterData2 DCU register DATA2
|
||||
**
|
||||
** \retval DCU register DATAx value
|
||||
**
|
||||
******************************************************************************/
|
||||
uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg)
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU(DCUx));
|
||||
DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg));
|
||||
|
||||
return *(uint8_t *)DCU_DATAx(DCUx, enDataReg);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Write DCU register DATAx
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enDataReg The specified DATA register.
|
||||
** \arg DcuRegisterData0 DCU register DATA0
|
||||
** \arg DcuRegisterData1 DCU register DATA1
|
||||
** \arg DcuRegisterData2 DCU register DATA2
|
||||
** \param [in] u8Data The data will be written.
|
||||
**
|
||||
** \retval Ok Write successfully.
|
||||
** \retval ErrorInvalidParameter DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg,
|
||||
uint8_t u8Data)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check for DCUx pointer */
|
||||
if (IS_VALID_DCU(DCUx))
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg));
|
||||
|
||||
*(uint8_t *)DCU_DATAx(DCUx, enDataReg) = u8Data;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Read DCU register DATAx
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enDataReg The specified DATA register.
|
||||
** \arg DcuRegisterData0 DCU register DATA0
|
||||
** \arg DcuRegisterData1 DCU register DATA1
|
||||
** \arg DcuRegisterData2 DCU register DATA2
|
||||
**
|
||||
** \retval DCU register DATAx value
|
||||
**
|
||||
******************************************************************************/
|
||||
uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg)
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU(DCUx));
|
||||
DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg));
|
||||
|
||||
return *(uint16_t *)DCU_DATAx(DCUx, enDataReg);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Write DCU register DATAx
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enDataReg The specified DATA register.
|
||||
** \arg DcuRegisterData0 DCU register DATA0
|
||||
** \arg DcuRegisterData1 DCU register DATA1
|
||||
** \arg DcuRegisterData2 DCU register DATA2
|
||||
** \param [in] u16Data The data will be written.
|
||||
**
|
||||
** \retval Ok Write successfully.
|
||||
** \retval ErrorInvalidParameter DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg,
|
||||
uint16_t u16Data)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check for DCUx pointer */
|
||||
if (IS_VALID_DCU(DCUx))
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg));
|
||||
|
||||
*(uint16_t *)DCU_DATAx(DCUx, enDataReg) = u16Data;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Read DCU register DATAx
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enDataReg The specified DATA register.
|
||||
** \arg DcuRegisterData0 DCU register DATA0
|
||||
** \arg DcuRegisterData1 DCU register DATA1
|
||||
** \arg DcuRegisterData2 DCU register DATA2
|
||||
**
|
||||
** \retval DCU register DATAx value
|
||||
**
|
||||
******************************************************************************/
|
||||
uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg)
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU(DCUx));
|
||||
DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg));
|
||||
|
||||
return *(uint32_t *)DCU_DATAx(DCUx, enDataReg);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Write DCU register DATAx
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enDataReg The specified DATA register.
|
||||
** \arg DcuRegisterData0 DCU register DATA0
|
||||
** \arg DcuRegisterData1 DCU register DATA1
|
||||
** \arg DcuRegisterData2 DCU register DATA2
|
||||
** \param [in] u32Data The data will be written.
|
||||
**
|
||||
** \retval Ok Write successfully.
|
||||
** \retval ErrorInvalidParameter DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg,
|
||||
uint32_t u32Data)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check for DCUx pointer */
|
||||
if (IS_VALID_DCU(DCUx))
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg));
|
||||
|
||||
*(uint32_t *)DCU_DATAx(DCUx, enDataReg) = u32Data;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set DCU trigger source number
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enTriggerSrc The trigger source.
|
||||
** \arg This parameter can be any value of @ref en_event_src_t
|
||||
**
|
||||
** \retval Ok Write successfully.
|
||||
** \retval ErrorInvalidParameter DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx,
|
||||
en_event_src_t enTriggerSrc)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
__IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx);
|
||||
|
||||
if (NULL != TRGSELx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
DDL_ASSERT(IS_VALID_TRG_SRC_EVENT(enTriggerSrc));
|
||||
|
||||
*TRGSELx = (*TRGSELx & (~((uint32_t)EVT_MAX))) | (uint32_t)enTriggerSrc;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable DCU common trigger.
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
** \param [in] enComTrigger DCU common trigger selection. See @ref en_dcu_com_trigger_t for details.
|
||||
** \param [in] enState Enable or disable the specified common trigger.
|
||||
**
|
||||
** \retval None.
|
||||
**
|
||||
******************************************************************************/
|
||||
void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_com_trigger_t enComTrigger,
|
||||
en_functional_state_t enState)
|
||||
{
|
||||
uint32_t u32ComTrig = (uint32_t)enComTrigger;
|
||||
__IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx);
|
||||
|
||||
if (NULL != TRGSELx)
|
||||
{
|
||||
DDL_ASSERT(IS_DCU_COM_TRIGGER(enComTrigger));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enState));
|
||||
|
||||
if (enState == Enable)
|
||||
{
|
||||
*TRGSELx |= (u32ComTrig << 30u);
|
||||
}
|
||||
else
|
||||
{
|
||||
*TRGSELx &= ~(u32ComTrig << 30u);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get DCU trigger source register address
|
||||
**
|
||||
** \param [in] DCUx Pointer to DCU instance register base
|
||||
** \arg M4_DCU1 DCU unit 1 instance register base
|
||||
** \arg M4_DCU2 DCU unit 2 instance register base
|
||||
** \arg M4_DCU3 DCU unit 3 instance register base
|
||||
** \arg M4_DCU4 DCU unit 4 instance register base
|
||||
**
|
||||
** \retval DCUx_TRGSEL address DCUx is valid
|
||||
** \retval NULL DCUx is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx)
|
||||
{
|
||||
__IO uint32_t *TRGSELx = NULL;
|
||||
|
||||
if (M4_DCU1 == DCUx)
|
||||
{
|
||||
TRGSELx = &M4_AOS->DCU1_TRGSEL;
|
||||
}
|
||||
else if (M4_DCU2 == DCUx)
|
||||
{
|
||||
TRGSELx = &M4_AOS->DCU2_TRGSEL;
|
||||
}
|
||||
else if (M4_DCU3 == DCUx)
|
||||
{
|
||||
TRGSELx = &M4_AOS->DCU3_TRGSEL;
|
||||
}
|
||||
else if (M4_DCU4 == DCUx)
|
||||
{
|
||||
TRGSELx = &M4_AOS->DCU4_TRGSEL;
|
||||
}
|
||||
else
|
||||
{
|
||||
TRGSELx = NULL;
|
||||
}
|
||||
|
||||
return TRGSELx;
|
||||
}
|
||||
|
||||
//@} // DcuGroup
|
||||
|
||||
#endif /* DDL_DCU_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,942 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_efm.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link EfmGroup EFM description @endlink
|
||||
**
|
||||
** - 2018-10-29 CDT First version for Device Driver Library of EFM.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_efm.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_EFM_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup EfmGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
#define EFM_LOCK (0x00000000u)
|
||||
#define EFM_UNLOCK (0x00000001u)
|
||||
#define EFM_KEY1 (0x0123ul)
|
||||
#define EFM_KEY2 (0x3210ul)
|
||||
|
||||
#define EFM_PROTECT_ADDR_MSK (0x000FFFFFu)
|
||||
|
||||
/* Parameter validity check for pointer. */
|
||||
#define IS_VALID_POINTER(x) (NULL != (x))
|
||||
|
||||
/* Parameter validity check for flash latency. */
|
||||
#define IS_VALID_FLASH_LATENCY(x) \
|
||||
( ((x) == EFM_LATENCY_0) || \
|
||||
((x) == EFM_LATENCY_1) || \
|
||||
((x) == EFM_LATENCY_2) || \
|
||||
((x) == EFM_LATENCY_3) || \
|
||||
((x) == EFM_LATENCY_4) || \
|
||||
((x) == EFM_LATENCY_5) || \
|
||||
((x) == EFM_LATENCY_6) || \
|
||||
((x) == EFM_LATENCY_7) || \
|
||||
((x) == EFM_LATENCY_8) || \
|
||||
((x) == EFM_LATENCY_9) || \
|
||||
((x) == EFM_LATENCY_10) || \
|
||||
((x) == EFM_LATENCY_11) || \
|
||||
((x) == EFM_LATENCY_12) || \
|
||||
((x) == EFM_LATENCY_13) || \
|
||||
((x) == EFM_LATENCY_14) || \
|
||||
((x) == EFM_LATENCY_15))
|
||||
|
||||
/* Parameter validity check for read mode. */
|
||||
#define IS_VALID_READ_MD(MD) \
|
||||
( ((MD) == NormalRead) || \
|
||||
((MD) == UltraPowerRead))
|
||||
|
||||
/* Parameter validity check for erase/program mode. */
|
||||
#define IS_VALID_ERASE_PGM_MD(MD) \
|
||||
( ((MD) == EFM_MODE_READONLY) || \
|
||||
((MD) == EFM_MODE_SINGLEPROGRAM) || \
|
||||
((MD) == EFM_MODE_SINGLEPROGRAMRB) || \
|
||||
((MD) == EFM_MODE_SEQUENCEPROGRAM) || \
|
||||
((MD) == EFM_MODE_SECTORERASE) || \
|
||||
((MD) == EFM_MODE_CHIPERASE))
|
||||
|
||||
/* Parameter validity check for flash flag. */
|
||||
#define IS_VALID_FLASH_FLAG(flag) \
|
||||
( ((flag) == EFM_FLAG_WRPERR) || \
|
||||
((flag) == EFM_FLAG_PEPRTERR) || \
|
||||
((flag) == EFM_FLAG_PGSZERR) || \
|
||||
((flag) == EFM_FLAG_PGMISMTCH) || \
|
||||
((flag) == EFM_FLAG_EOP) || \
|
||||
((flag) == EFM_FLAG_COLERR) || \
|
||||
((flag) == EFM_FLAG_RDY))
|
||||
|
||||
/* Parameter validity check for flash clear flag. */
|
||||
#define IS_VALID_CLEAR_FLASH_FLAG(flag) \
|
||||
( ((flag) == EFM_FLAG_WRPERR) || \
|
||||
((flag) == EFM_FLAG_PEPRTERR) || \
|
||||
((flag) == EFM_FLAG_PGSZERR) || \
|
||||
((flag) == EFM_FLAG_PGMISMTCH) || \
|
||||
((flag) == EFM_FLAG_EOP) || \
|
||||
((flag) == EFM_FLAG_COLERR))
|
||||
|
||||
/* Parameter validity check for flash interrupt. */
|
||||
#define IS_VALID_EFM_INT_SEL(int) \
|
||||
( ((int) == PgmErsErrInt) || \
|
||||
((int) == EndPgmInt) || \
|
||||
((int) == ColErrInt))
|
||||
|
||||
/* Parameter validity check for flash address. */
|
||||
#define IS_VALID_FLASH_ADDR(addr) \
|
||||
( ((addr) == 0x00000000u) || \
|
||||
(((addr) >= 0x00000001u) && \
|
||||
((addr) <= 0x0007FFDFu)))
|
||||
|
||||
/* Parameter validity check for flash address. */
|
||||
#define IS_VALID_OTP_LOCK_ADDR(addr) \
|
||||
( ((addr) >= 0x03000FC0u) || \
|
||||
((addr) <= 0x03000FF8u))
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Unlock the flash.
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_Unlock(void)
|
||||
{
|
||||
M4_EFM->FAPRT = EFM_KEY1;
|
||||
M4_EFM->FAPRT = EFM_KEY2;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Lock the flash.
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_Lock(void)
|
||||
{
|
||||
if(EFM_UNLOCK == M4_EFM->FAPRT)
|
||||
{
|
||||
M4_EFM->FAPRT = EFM_KEY2;
|
||||
M4_EFM->FAPRT = EFM_KEY2;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable the flash.
|
||||
**
|
||||
** \param [in] enNewState The new state of the flash.
|
||||
** \arg Enable Enable flash.
|
||||
** \arg Disable Stop flash.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_FlashCmd(en_functional_state_t enNewState)
|
||||
{
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
|
||||
M4_EFM->FSTP_f.FSTP = ((Enable == enNewState) ? 0ul : 1ul);
|
||||
}
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Sets the code latency value..
|
||||
**
|
||||
** \param [in] u32Latency specifies the FLASH Latency value.
|
||||
** \arg EFM_LATENCY_0 FLASH 0 Latency cycle
|
||||
** \arg EFM_LATENCY_1 FLASH 1 Latency cycle
|
||||
** \arg EFM_LATENCY_2 FLASH 2 Latency cycles
|
||||
** \arg EFM_LATENCY_3 FLASH 3 Latency cycles
|
||||
** \arg EFM_LATENCY_4 FLASH 4 Latency cycles
|
||||
** \arg EFM_LATENCY_5 FLASH 5 Latency cycles
|
||||
** \arg EFM_LATENCY_6 FLASH 6 Latency cycles
|
||||
** \arg EFM_LATENCY_7 FLASH 7 Latency cycles
|
||||
** \arg EFM_LATENCY_8 FLASH 8 Latency cycles
|
||||
** \arg EFM_LATENCY_9 FLASH 9 Latency cycles
|
||||
** \arg EFM_LATENCY_10 FLASH 10 Latency cycles
|
||||
** \arg EFM_LATENCY_11 FLASH 11 Latency cycles
|
||||
** \arg EFM_LATENCY_12 FLASH 12 Latency cycles
|
||||
** \arg EFM_LATENCY_13 FLASH 13 Latency cycles
|
||||
** \arg EFM_LATENCY_14 FLASH 14 Latency cycles
|
||||
** \arg EFM_LATENCY_15 FLASH 15 Latency cycles
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_SetLatency(uint32_t u32Latency)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_FLASH_LATENCY(u32Latency));
|
||||
|
||||
M4_EFM->FRMC_f.FLWT = u32Latency;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable the flash instruction cache.
|
||||
**
|
||||
** \param [in] enNewState The new state of the flash instruction cache.
|
||||
** \arg Enable Enable flash instruction cache.
|
||||
** \arg Disable Disable flash instruction cache.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_InstructionCacheCmd(en_functional_state_t enNewState)
|
||||
{
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
|
||||
M4_EFM->FRMC_f.CACHE = enNewState;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable the data cache reset.
|
||||
**
|
||||
** \param [in] enNewState The new state of the data cache reset.
|
||||
** \arg Enable Enable data cache reset.
|
||||
** \arg Disable Disable data cache reset.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_DataCacheRstCmd(en_functional_state_t enNewState)
|
||||
{
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
|
||||
M4_EFM->FRMC_f.CRST = enNewState;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set the flash read mode.
|
||||
**
|
||||
** \param [in] enReadMD The flash read mode.
|
||||
** \arg NormalRead Normal read mode.
|
||||
** \arg UltraPowerRead Ultra_Low power read mode.
|
||||
**
|
||||
** \retval None.
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_SetReadMode(en_efm_read_md_t enReadMD)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_READ_MD(enReadMD));
|
||||
M4_EFM->FRMC_f.SLPMD = enReadMD;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable erase / program.
|
||||
**
|
||||
** \param [in] enNewState The new state of the erase / program.
|
||||
** \arg Enable Enable erase / program.
|
||||
** \arg Disable Disable erase / program.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_ErasePgmCmd(en_functional_state_t enNewState)
|
||||
{
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
|
||||
M4_EFM->FWMC_f.PEMODE = enNewState;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set the flash erase program mode.
|
||||
**
|
||||
** \param [in] u32Mode The flash erase program mode.
|
||||
** \arg EFM_MODE_READONLY The flash read only.
|
||||
** \arg EFM_MODE_SINGLEPROGRAM The flash single program.
|
||||
** \arg EFM_MODE_SINGLEPROGRAMRB The flash single program with read back.
|
||||
** \arg EFM_MODE_SEQUENCEPROGRAM The flash sequence program.
|
||||
** \arg EFM_MODE_SECTORERASE The flash sector erase.
|
||||
** \arg EFM_MODE_CHIPERASE The flash mass erase.
|
||||
**
|
||||
** \retval en_result_t.
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EFM_SetErasePgmMode(uint32_t u32Mode)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
uint16_t u16Timeout = 0u;
|
||||
|
||||
DDL_ASSERT(IS_VALID_ERASE_PGM_MD(u32Mode));
|
||||
|
||||
while(1ul != M4_EFM->FSR_f.RDY)
|
||||
{
|
||||
u16Timeout++;
|
||||
if(u16Timeout > 0x1000u)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(Ok == enRet)
|
||||
{
|
||||
M4_EFM->FWMC_f.PEMODE = Enable;
|
||||
M4_EFM->FWMC_f.PEMOD = u32Mode;
|
||||
M4_EFM->FWMC_f.PEMODE = Disable;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable the specified interrupt.
|
||||
**
|
||||
** \param [in] enInt The specified interrupt.
|
||||
** \arg PgmErsErrInt Program erase error interrupt.
|
||||
** \arg EndPgmInt End of Program interrupt.
|
||||
** \arg ReadErrInt Read collided error flag.
|
||||
**
|
||||
** \param [in] enNewState The new state of the specified interrupt.
|
||||
** \arg Enable Enable the specified interrupt.
|
||||
** \arg Disable Disable the specified interrupt.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState)
|
||||
{
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
DDL_ASSERT(IS_VALID_EFM_INT_SEL(enInt));
|
||||
|
||||
switch(enInt)
|
||||
{
|
||||
case PgmErsErrInt:
|
||||
M4_EFM->FITE_f.PEERRITE = enNewState;
|
||||
break;
|
||||
case EndPgmInt:
|
||||
M4_EFM->FITE_f.OPTENDITE = enNewState;
|
||||
break;
|
||||
case ColErrInt:
|
||||
M4_EFM->FITE_f.COLERRITE = enNewState;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Checks whether the specified FLASH flag is set or not..
|
||||
**
|
||||
** \param [in] u32flag Specifies the FLASH flag to check.
|
||||
** \arg EFM_FLAG_WRPERR Flash write protect error flag.
|
||||
** \arg EFM_FLAG_PEPRTERR Flash program protect area error flag.
|
||||
** \arg EFM_FLAG_PGSZERR Flash program size error flag.
|
||||
** \arg EFM_FLAG_PGMISMTCH Flash program miss match flag.
|
||||
** \arg EFM_FLAG_EOP Flash end of program flag.
|
||||
** \arg EFM_FLAG_COLERR Flash collision error flag.
|
||||
** \arg EFM_FLAG_RDY Flash ready flag.
|
||||
**
|
||||
** \retval The flash status.
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_FLASH_FLAG(u32flag));
|
||||
|
||||
return ((0ul == (M4_EFM->FSR & u32flag)) ? Reset :Set);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Checks whether the specified FLASH flag is set or not..
|
||||
**
|
||||
** \param [in] u32flag Specifies the FLASH flag to clear.
|
||||
** \arg EFM_FLAG_WRPERR Flash write protect error flag.
|
||||
** \arg EFM_FLAG_PEPRTERR Flash program protect area error flag.
|
||||
** \arg EFM_FLAG_PGSZERR Flash program size error flag.
|
||||
** \arg EFM_FLAG_PGMISMTCH Flash program miss match flag.
|
||||
** \arg EFM_FLAG_EOP Flash end of program flag.
|
||||
** \arg EFM_FLAG_COLERR Flash collision error flag.
|
||||
**
|
||||
** \retval The flash status.
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_ClearFlag(uint32_t u32flag)
|
||||
{
|
||||
//DDL_ASSERT(IS_VALID_CLEAR_FLASH_FLAG(u32flag));
|
||||
|
||||
M4_EFM->FSCLR = u32flag;
|
||||
}
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the flash status.
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval The flash status.
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_efm_flash_status_t EFM_GetStatus(void)
|
||||
{
|
||||
en_efm_flash_status_t enFlashStatus = FlashEOP;
|
||||
|
||||
if(1ul == M4_EFM->FSR_f.RDY )
|
||||
{
|
||||
enFlashStatus = FlashReady;
|
||||
}
|
||||
else if(1ul == M4_EFM->FSR_f.COLERR)
|
||||
{
|
||||
enFlashStatus = FlashRWErr;
|
||||
}
|
||||
else if(1ul == M4_EFM->FSR_f.OPTEND)
|
||||
{
|
||||
enFlashStatus = FlashEOP;
|
||||
}
|
||||
else if(1ul == M4_EFM->FSR_f.PGMISMTCH)
|
||||
{
|
||||
enFlashStatus = FlashPgMissMatch;
|
||||
}
|
||||
else if(1ul == M4_EFM->FSR_f.PGSZERR)
|
||||
{
|
||||
enFlashStatus = FlashPgSizeErr;
|
||||
}
|
||||
else if(1ul == M4_EFM->FSR_f.PEPRTERR)
|
||||
{
|
||||
enFlashStatus = FlashPgareaPErr;
|
||||
}
|
||||
else if(1ul == M4_EFM->FSR_f.PEWERR)
|
||||
{
|
||||
enFlashStatus = FlashWRPErr;
|
||||
}
|
||||
else
|
||||
{
|
||||
//else
|
||||
}
|
||||
|
||||
return enFlashStatus;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set flash the windows protect address.
|
||||
**
|
||||
** \param [in] stcAddr The specified windows protect address.
|
||||
** \arg StartAddr The start of windows protect address.
|
||||
** \arg EndAddr The end of windows protect address.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr)
|
||||
{
|
||||
M4_EFM->FPMTSW_f.FPMTSW = (stcAddr.StartAddr & EFM_PROTECT_ADDR_MSK);
|
||||
M4_EFM->FPMTEW_f.FPMTEW = (stcAddr.EndAddr & EFM_PROTECT_ADDR_MSK);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set bus state while flash program & erase.
|
||||
**
|
||||
** \param [in] enState The specified bus state while flash program & erase.
|
||||
** \arg BusBusy The bus busy.
|
||||
** \arg BusRelease The bus release.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
void EFM_SetBusState(en_efm_bus_sta_t enState)
|
||||
{
|
||||
M4_EFM->FWMC_f.BUSHLDCTL = enState;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Flash single program without read back.
|
||||
**
|
||||
** \param [in] u32Addr The specified program address.
|
||||
** \param [in] u32Data The specified program data.
|
||||
**
|
||||
** \retval en_result_t
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
uint8_t u8tmp;
|
||||
uint16_t u16Timeout = 0u;
|
||||
|
||||
DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr));
|
||||
|
||||
/* CLear the error flag. */
|
||||
EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR |
|
||||
EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR);
|
||||
|
||||
/* read back CACHE */
|
||||
u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE;
|
||||
|
||||
M4_EFM->FRMC_f.CACHE = Disable;
|
||||
|
||||
/* Enable program. */
|
||||
EFM_ErasePgmCmd(Enable);
|
||||
/* Set single program mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAM;
|
||||
/* program data. */
|
||||
*(uint32_t*)u32Addr = u32Data;
|
||||
|
||||
while(1ul != M4_EFM->FSR_f.RDY)
|
||||
{
|
||||
u16Timeout++;
|
||||
if(u16Timeout > 0x1000u)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
}
|
||||
|
||||
if(u32Data != *(uint32_t*)u32Addr)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
|
||||
EFM_ClearFlag(EFM_FLAG_EOP);
|
||||
/* Set read only mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY;
|
||||
EFM_ErasePgmCmd(Disable);
|
||||
|
||||
/* recover CACHE */
|
||||
M4_EFM->FRMC_f.CACHE = u8tmp;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Flash single program with read back.
|
||||
**
|
||||
** \param [in] u32Addr The specified program address.
|
||||
** \param [in] u32Data The specified program data.
|
||||
**
|
||||
** \retval en_result_t
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
uint8_t u8tmp = 0u;
|
||||
uint16_t u16Timeout = 0u;
|
||||
|
||||
DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr));
|
||||
|
||||
/* CLear the error flag. */
|
||||
EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR |
|
||||
EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR);
|
||||
|
||||
/* read back CACHE */
|
||||
u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE;
|
||||
|
||||
M4_EFM->FRMC_f.CACHE = Disable;
|
||||
|
||||
/* Enable program. */
|
||||
EFM_ErasePgmCmd(Enable);
|
||||
/* Set single program with read back mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAMRB;
|
||||
/* program data. */
|
||||
*(uint32_t*)u32Addr = u32Data;
|
||||
|
||||
while(1ul != M4_EFM->FSR_f.RDY)
|
||||
{
|
||||
u16Timeout++;
|
||||
if(u16Timeout > 0x1000u)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
}
|
||||
|
||||
if(1ul == M4_EFM->FSR_f.PGMISMTCH)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
|
||||
EFM_ClearFlag(EFM_FLAG_EOP);
|
||||
/* Set read only mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY;
|
||||
EFM_ErasePgmCmd(Disable);
|
||||
|
||||
/* recover CACHE */
|
||||
M4_EFM->FRMC_f.CACHE = u8tmp;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
static void *EFM_Memcpy(void *pvDst, void *pvSrc, uint32_t u32Count)
|
||||
{
|
||||
uint8_t *u8TmpDst = (uint8_t *)pvDst;
|
||||
uint8_t *u8TmpSrc = (uint8_t *)pvSrc;
|
||||
|
||||
DDL_ASSERT(IS_VALID_POINTER(pvDst));
|
||||
DDL_ASSERT(IS_VALID_POINTER(pvSrc));
|
||||
|
||||
while (u32Count--)
|
||||
{
|
||||
*u8TmpDst++ = *u8TmpSrc++;
|
||||
}
|
||||
|
||||
return pvDst;
|
||||
}
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Flash sequence program.
|
||||
**
|
||||
** \param [in] u32Addr The specified program address.
|
||||
** \param [in] u32Len The len of specified program data.
|
||||
** \param [in] *pBuf The pointer of specified program data.
|
||||
**
|
||||
** \retval en_result_t
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
uint8_t u8tmp;
|
||||
uint32_t i;
|
||||
uint16_t u16Timeout = 0u;
|
||||
uint32_t u32Tmp = 0xFFFFFFFFul;
|
||||
uint32_t *u32pSrc = pBuf;
|
||||
uint32_t *u32pDest = (uint32_t *)u32Addr;
|
||||
uint32_t u32LoopWords = u32Len >> 2ul;
|
||||
uint32_t u32RemainBytes = u32Len % 4ul;
|
||||
|
||||
DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr));
|
||||
DDL_ASSERT(IS_VALID_POINTER(pBuf));
|
||||
|
||||
/* CLear the error flag. */
|
||||
EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR |
|
||||
EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR);
|
||||
|
||||
/* read back CACHE */
|
||||
u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE;
|
||||
|
||||
M4_EFM->FRMC_f.CACHE = Disable;
|
||||
|
||||
/* Enable program. */
|
||||
EFM_ErasePgmCmd(Enable);
|
||||
/* Set sequence program mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_SEQUENCEPROGRAM;
|
||||
/* clear read collided error flag.*/
|
||||
EFM_ClearFlag(EFM_FLAG_COLERR);
|
||||
EFM_ClearFlag(EFM_FLAG_WRPERR);
|
||||
|
||||
/* program data. */
|
||||
for(i = 0ul; i < u32LoopWords; i++)
|
||||
{
|
||||
*u32pDest++ = *u32pSrc++;
|
||||
/* wait operate end. */
|
||||
while(1ul != M4_EFM->FSR_f.OPTEND)
|
||||
{
|
||||
u16Timeout++;
|
||||
if(u16Timeout > 0x1000u)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
}
|
||||
/* clear end flag. */
|
||||
EFM_ClearFlag(EFM_FLAG_EOP);
|
||||
}
|
||||
if(u32RemainBytes)
|
||||
{
|
||||
EFM_Memcpy(&u32Tmp, u32pSrc, u32RemainBytes);
|
||||
*u32pDest++ = u32Tmp;
|
||||
}
|
||||
|
||||
/* Set read only mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY;
|
||||
|
||||
u16Timeout = 0u;
|
||||
while(1ul != M4_EFM->FSR_f.RDY)
|
||||
{
|
||||
u16Timeout++;
|
||||
if(u16Timeout > 0x1000u)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
}
|
||||
|
||||
EFM_ClearFlag(EFM_FLAG_EOP);
|
||||
EFM_ErasePgmCmd(Disable);
|
||||
|
||||
/* recover CACHE */
|
||||
M4_EFM->FRMC_f.CACHE = u8tmp;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Flash sector erase.
|
||||
**
|
||||
** \param [in] u32Addr The uncertain(random) address in the specified sector.
|
||||
**
|
||||
** \retval en_result_t
|
||||
**
|
||||
** \note The address should be word align.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EFM_SectorErase(uint32_t u32Addr)
|
||||
{
|
||||
uint8_t u8tmp;
|
||||
uint16_t u16Timeout = 0u;
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr));
|
||||
|
||||
/* CLear the error flag. */
|
||||
EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR |
|
||||
EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR);
|
||||
|
||||
/* read back CACHE */
|
||||
u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE;
|
||||
|
||||
M4_EFM->FRMC_f.CACHE = Disable;
|
||||
|
||||
/* Enable erase. */
|
||||
EFM_ErasePgmCmd(Enable);
|
||||
/* Set sector erase mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_SECTORERASE;
|
||||
|
||||
*(uint32_t*)u32Addr = 0x12345678u;
|
||||
|
||||
while(1ul != M4_EFM->FSR_f.RDY)
|
||||
{
|
||||
u16Timeout++;
|
||||
if(u16Timeout > 0x1000u)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
}
|
||||
|
||||
EFM_ClearFlag(EFM_FLAG_EOP);
|
||||
/* Set read only mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY;
|
||||
EFM_ErasePgmCmd(Disable);
|
||||
|
||||
/* recover CACHE */
|
||||
M4_EFM->FRMC_f.CACHE = u8tmp;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Flash mass erase.
|
||||
**
|
||||
** \param [in] u32Addr The uncertain(random) address in the flash.
|
||||
**
|
||||
** \retval en_result_t
|
||||
**
|
||||
** \note The address should be word align.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EFM_MassErase(uint32_t u32Addr)
|
||||
{
|
||||
uint8_t u8tmp;
|
||||
uint16_t u16Timeout = 0u;
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr));
|
||||
|
||||
/* CLear the error flag. */
|
||||
EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR |
|
||||
EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR);
|
||||
|
||||
/* read back CACHE */
|
||||
u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE;
|
||||
|
||||
M4_EFM->FRMC_f.CACHE = Disable;
|
||||
|
||||
/* Enable erase. */
|
||||
EFM_ErasePgmCmd(Enable);
|
||||
/* Set sector erase mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_CHIPERASE;
|
||||
|
||||
*(uint32_t*)u32Addr = 0x12345678u;
|
||||
|
||||
while(1ul != M4_EFM->FSR_f.RDY)
|
||||
{
|
||||
u16Timeout++;
|
||||
if(u16Timeout > 0x1000u)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
}
|
||||
|
||||
EFM_ClearFlag(EFM_FLAG_EOP);
|
||||
/* Set read only mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY;
|
||||
EFM_ErasePgmCmd(Disable);
|
||||
|
||||
/* recover CACHE */
|
||||
M4_EFM->FRMC_f.CACHE = u8tmp;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get flash switch status.
|
||||
**
|
||||
** \param None.
|
||||
**
|
||||
** \retval en_flag_status_t
|
||||
** \arg Set The flash has switched, the start address is sector1.
|
||||
** \arg Reset The flash did not switch, the start address is sector0.
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t EFM_GetSwitchStatus(void)
|
||||
{
|
||||
return ((0u == M4_EFM->FSWP_f.FSWP) ? Set : Reset);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Lock OTP data block.
|
||||
**
|
||||
** \param u32Addr The addr to lock.
|
||||
**
|
||||
** \retval en_result_t
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EFM_OtpLock(uint32_t u32Addr)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_OTP_LOCK_ADDR(u32Addr));
|
||||
uint16_t u16Timeout = 0u;
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Enable program. */
|
||||
EFM_ErasePgmCmd(Enable);
|
||||
/* Set single program mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAM;
|
||||
|
||||
/* Lock the otp block. */
|
||||
*(uint32_t*)u32Addr = 0ul;
|
||||
|
||||
while(1ul != M4_EFM->FSR_f.RDY)
|
||||
{
|
||||
u16Timeout++;
|
||||
if(u16Timeout > 0x1000u)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
}
|
||||
|
||||
EFM_ClearFlag(EFM_FLAG_EOP);
|
||||
/* Set read only mode. */
|
||||
M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY;
|
||||
EFM_ErasePgmCmd(Disable);
|
||||
|
||||
return enRet;
|
||||
}
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief read unique ID.
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval uint32_t
|
||||
**
|
||||
** \note None
|
||||
**
|
||||
******************************************************************************/
|
||||
stc_efm_unique_id_t EFM_ReadUID(void)
|
||||
{
|
||||
stc_efm_unique_id_t stcUID;
|
||||
|
||||
stcUID.uniqueID1 = M4_EFM->UQID1;
|
||||
stcUID.uniqueID2 = M4_EFM->UQID2;
|
||||
stcUID.uniqueID3 = M4_EFM->UQID3;
|
||||
|
||||
return stcUID;
|
||||
}
|
||||
|
||||
//@} // EfmGroup
|
||||
|
||||
#endif /* DDL_EFM_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,487 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_emb.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link EMBGroup EMB description @endlink
|
||||
**
|
||||
** - 2018-11-24 CDT First version for Device Driver Library of EMB.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_emb.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_EMB_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup EMBGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*!< Parameter valid check for emb unit */
|
||||
#define IS_VALID_EMB_UNIT(__EMBx__) \
|
||||
( (M4_EMB1 == (__EMBx__)) || \
|
||||
(M4_EMB2 == (__EMBx__)) || \
|
||||
(M4_EMB3 == (__EMBx__)) || \
|
||||
(M4_EMB4 == (__EMBx__)))
|
||||
|
||||
/*!< Parameter valid check for emb status*/
|
||||
#define IS_VALID_EMB_STATUS_TYPE(x) \
|
||||
( (EMBFlagPortIn == (x)) || \
|
||||
(EMBFlagPWMSame == (x)) || \
|
||||
(EMBFlagCmp == (x)) || \
|
||||
(EMBFlagOSCFail == (x)) || \
|
||||
(EMBPortInState == (x)) || \
|
||||
(EMBPWMState == (x)))
|
||||
|
||||
/*!< Parameter valid check for emb status clear*/
|
||||
#define IS_VALID_EMB_STATUS_CLR(x) \
|
||||
( (EMBPortInFlagClr == (x)) || \
|
||||
(EMBPWMSameFlagCLr == (x)) || \
|
||||
(EMBCmpFlagClr == (x)) || \
|
||||
(EMBOSCFailFlagCLr == (x)))
|
||||
|
||||
/*!< Parameter valid check for emb irq enable*/
|
||||
#define IS_VALID_EMB_IRQ(x) \
|
||||
( (PORTBrkIrq == (x)) || \
|
||||
(PWMSmBrkIrq == (x)) || \
|
||||
(CMPBrkIrq == (x)) || \
|
||||
(OSCFailBrkIrq == (x)))
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* \brief EMB interrupt request enable or disable
|
||||
*
|
||||
* \param [in] EMBx EMB unit
|
||||
* \param [in] enEMBIrq Irq type
|
||||
* \param [in] bEn true/false
|
||||
*
|
||||
* \retval en_result_t Ok: config success
|
||||
******************************************************************************/
|
||||
en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx,
|
||||
en_emb_irq_type_t enEMBIrq,
|
||||
bool bEn)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
if (IS_VALID_EMB_UNIT(EMBx))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_EMB_IRQ(enEMBIrq));
|
||||
|
||||
enRet = Ok;
|
||||
switch (enEMBIrq)
|
||||
{
|
||||
case PORTBrkIrq:
|
||||
EMBx->INTEN_f.PORTINTEN = (uint32_t)bEn;
|
||||
break;
|
||||
case PWMSmBrkIrq:
|
||||
EMBx->INTEN_f.PWMINTEN = (uint32_t)bEn;
|
||||
break;
|
||||
case CMPBrkIrq:
|
||||
EMBx->INTEN_f.CMPINTEN = (uint32_t)bEn;
|
||||
break;
|
||||
case OSCFailBrkIrq:
|
||||
EMBx->INTEN_f.OSINTEN = (uint32_t)bEn;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get EMB status
|
||||
**
|
||||
** \param [in] EMBx EMB unit
|
||||
**
|
||||
** \param [in] enStatus EMB status type
|
||||
**
|
||||
** \retval EMB status
|
||||
**
|
||||
******************************************************************************/
|
||||
bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus)
|
||||
{
|
||||
bool status = false;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_EMB_UNIT(EMBx));
|
||||
DDL_ASSERT(IS_VALID_EMB_STATUS_TYPE(enStatus));
|
||||
|
||||
switch (enStatus)
|
||||
{
|
||||
case EMBFlagPortIn:
|
||||
status = EMBx->STAT_f.PORTINF;
|
||||
break;
|
||||
case EMBFlagPWMSame:
|
||||
status = EMBx->STAT_f.PWMSF;
|
||||
break;
|
||||
case EMBFlagCmp:
|
||||
status = EMBx->STAT_f.CMPF;
|
||||
break;
|
||||
case EMBFlagOSCFail:
|
||||
status = EMBx->STAT_f.OSF;
|
||||
break;
|
||||
case EMBPortInState:
|
||||
status = EMBx->STAT_f.PORTINST;
|
||||
break;
|
||||
case EMBPWMState:
|
||||
status = EMBx->STAT_f.PWMST;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB clear status(Recover from protection state)
|
||||
**
|
||||
** \param [in] EMBx EMB unit
|
||||
**
|
||||
** \param [in] enStatusClr EMB status clear type
|
||||
**
|
||||
** \retval en_result_t Ok: Config Success
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx,
|
||||
en_emb_status_clr_t enStatusClr)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
if (IS_VALID_EMB_UNIT(EMBx))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_EMB_STATUS_CLR(enStatusClr));
|
||||
|
||||
enRet = Ok;
|
||||
switch (enStatusClr)
|
||||
{
|
||||
case EMBPortInFlagClr:
|
||||
EMBx->STATCLR_f.PORTINFCLR = 1ul;
|
||||
break;
|
||||
case EMBPWMSameFlagCLr:
|
||||
EMBx->STATCLR_f.PWMSFCLR = 1ul;
|
||||
break;
|
||||
case EMBCmpFlagClr:
|
||||
EMBx->STATCLR_f.CMPFCLR = 1ul;
|
||||
break;
|
||||
case EMBOSCFailFlagCLr:
|
||||
EMBx->STATCLR_f.OSFCLR = 1ul;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* \brief EMB Control Register(CR) for timer6
|
||||
*
|
||||
* \param [in] EMBx EMB unit
|
||||
* \param [in] pstcEMBConfigCR EMB Config CR pointer
|
||||
*
|
||||
* \retval en_result_t Ok: Set successfully
|
||||
* \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid
|
||||
******************************************************************************/
|
||||
en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR)
|
||||
{
|
||||
uint32_t u32Val = 0ul;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
if (NULL != pstcEMBConfigCR)
|
||||
{
|
||||
if (pstcEMBConfigCR->bEnPortBrake)
|
||||
{
|
||||
u32Val |= 1ul;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnCmp1Brake)
|
||||
{
|
||||
u32Val |= 1ul << 1;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnCmp2Brake)
|
||||
{
|
||||
u32Val |= 1ul << 2;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnCmp3Brake)
|
||||
{
|
||||
u32Val |= 1ul << 3;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnOSCFailBrake)
|
||||
{
|
||||
u32Val |= 1ul << 5;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnTimer61PWMSBrake)
|
||||
{
|
||||
u32Val |= 1ul << 6;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnTimer62PWMSBrake)
|
||||
{
|
||||
u32Val |= 1ul << 7;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnTimer63PWMSBrake)
|
||||
{
|
||||
u32Val |= 1ul << 8;
|
||||
}
|
||||
if (EMBPortFltDiv0 == pstcEMBConfigCR->enPortInFltClkSel)
|
||||
{
|
||||
}
|
||||
if (EMBPortFltDiv8 == pstcEMBConfigCR->enPortInFltClkSel)
|
||||
{
|
||||
u32Val |= 1ul << 28;
|
||||
}
|
||||
if (EMBPortFltDiv32 == pstcEMBConfigCR->enPortInFltClkSel)
|
||||
{
|
||||
u32Val |= 2ul << 28;
|
||||
}
|
||||
if (EMBPortFltDiv128 == pstcEMBConfigCR->enPortInFltClkSel)
|
||||
{
|
||||
u32Val |= 3ul << 28;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnPorInFlt)
|
||||
{
|
||||
u32Val |= 1ul << 30;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnPortInLevelSel_Low)
|
||||
{
|
||||
u32Val |= 1ul << 31;
|
||||
}
|
||||
|
||||
M4_EMB1->CTL = u32Val;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* \brief EMB Control Register(CR) for timer4
|
||||
*
|
||||
* \param [in] EMBx EMB unit
|
||||
* \param [in] pstcEMBConfigCR EMB Config CR pointer
|
||||
*
|
||||
* \retval en_result_t Ok: Set successfully
|
||||
* \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid
|
||||
******************************************************************************/
|
||||
en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx,
|
||||
const stc_emb_ctrl_timer4_t* pstcEMBConfigCR)
|
||||
{
|
||||
uint32_t u32Val = 0ul;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
if ((M4_EMB1 != EMBx) && \
|
||||
(IS_VALID_EMB_UNIT(EMBx)) && \
|
||||
(NULL != pstcEMBConfigCR))
|
||||
{
|
||||
if (pstcEMBConfigCR->bEnPortBrake)
|
||||
{
|
||||
u32Val |= 1ul;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnCmp1Brake)
|
||||
{
|
||||
u32Val |= 1ul << 1;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnCmp2Brake)
|
||||
{
|
||||
u32Val |= 1ul << 2;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnCmp3Brake)
|
||||
{
|
||||
u32Val |= 1ul << 3;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnOSCFailBrake)
|
||||
{
|
||||
u32Val |= 1ul << 5;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnTimer4xWHLSammeBrake)
|
||||
{
|
||||
u32Val |= 1ul << 6;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnTimer4xVHLSammeBrake)
|
||||
{
|
||||
u32Val |= 1ul << 7;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnTimer4xUHLSammeBrake)
|
||||
{
|
||||
u32Val |= 1ul << 8;
|
||||
}
|
||||
if (EMBPortFltDiv0 == pstcEMBConfigCR->enPortInFltClkSel)
|
||||
{
|
||||
}
|
||||
if (EMBPortFltDiv8 == pstcEMBConfigCR->enPortInFltClkSel)
|
||||
{
|
||||
u32Val |= 1ul << 28;
|
||||
}
|
||||
if (EMBPortFltDiv32 == pstcEMBConfigCR->enPortInFltClkSel)
|
||||
{
|
||||
u32Val |= 2ul << 28;
|
||||
}
|
||||
if (EMBPortFltDiv128 == pstcEMBConfigCR->enPortInFltClkSel)
|
||||
{
|
||||
u32Val |= 3ul << 28;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnPorInFlt)
|
||||
{
|
||||
u32Val |= 1ul << 30;
|
||||
}
|
||||
if (pstcEMBConfigCR->bEnPortInLevelSel_Low)
|
||||
{
|
||||
u32Val |= 1ul << 31;
|
||||
}
|
||||
|
||||
EMBx->CTL = u32Val;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* \brief EMB detect PWM atcive level (short detection) selection for timer6
|
||||
*
|
||||
* \param [in] EMBx EMB unit
|
||||
* \param [in] pstcEMBPWMlv EMB en detect active level pointer
|
||||
*
|
||||
* \retval en_result_t Ok: Set successfully
|
||||
* \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid
|
||||
******************************************************************************/
|
||||
en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv)
|
||||
{
|
||||
uint32_t u32Val = 0ul;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
if (NULL != pstcEMBPWMlv)
|
||||
{
|
||||
if (pstcEMBPWMlv->bEnTimer61HighLevelDect)
|
||||
{
|
||||
u32Val |= 0x1ul;
|
||||
}
|
||||
if (pstcEMBPWMlv->bEnTimer62HighLevelDect)
|
||||
{
|
||||
u32Val |= 0x2ul;
|
||||
}
|
||||
if (pstcEMBPWMlv->bEnTimer63HighLevelDect)
|
||||
{
|
||||
u32Val |= 0x4ul;
|
||||
}
|
||||
|
||||
M4_EMB1->PWMLV = u32Val;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* \brief EMB detect PWM atcive level (short detection) selection for timer4
|
||||
*
|
||||
* \param [in] EMBx EMB unit
|
||||
* \param [in] pstcEMBPWMlv EMB en detect active level pointer
|
||||
*
|
||||
* \retval en_result_t Ok: Set successfully
|
||||
* \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid
|
||||
******************************************************************************/
|
||||
en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx,
|
||||
const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv)
|
||||
{
|
||||
uint32_t u32Val = 0ul;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
if ((IS_VALID_EMB_UNIT(EMBx)) && \
|
||||
(M4_EMB1 != EMBx) && \
|
||||
(NULL != pstcEMBPWMlv))
|
||||
{
|
||||
if (pstcEMBPWMlv->bEnWHLphaseHighLevelDect)
|
||||
{
|
||||
u32Val |= 0x1ul;
|
||||
}
|
||||
if (pstcEMBPWMlv->bEnVHLPhaseHighLevelDect)
|
||||
{
|
||||
u32Val |= 0x2ul;
|
||||
}
|
||||
if (pstcEMBPWMlv->bEnUHLPhaseHighLevelDect)
|
||||
{
|
||||
u32Val |= 0x4ul;
|
||||
}
|
||||
|
||||
EMBx->PWMLV = u32Val;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB Software brake
|
||||
**
|
||||
** \param [in] EMBx EMB unit
|
||||
**
|
||||
** \param [in] bEn true: Software Brake Enable / false: Software Brake Disable
|
||||
**
|
||||
** \retval en_result_t Ok: Config Success
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_EMB_UNIT(EMBx));
|
||||
|
||||
EMBx->SOE_f.SOE = (uint32_t)bEn;
|
||||
|
||||
return Ok;
|
||||
}
|
||||
|
||||
//@} // EMBGroup
|
||||
|
||||
#endif /* DDL_EMB_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,468 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_event_port.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link EventPortGroup EventPort description @endlink
|
||||
**
|
||||
** - 2018-12-07 CDT First version for Device Driver Library of EventPort.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_event_port.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_EVENT_PORT_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup EventPortGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
#define EP1_BASE 0x40010800ul + 0x0100ul
|
||||
#define EP2_BASE 0x40010800ul + 0x011Cul
|
||||
#define EP3_BASE 0x40010800ul + 0x0138ul
|
||||
#define EP4_BASE 0x40010800ul + 0x0154ul
|
||||
#define EP1_DIR_BASE 0x00ul
|
||||
#define EP1_IDR_BASE 0x04ul
|
||||
#define EP1_ODR_BASE 0x08ul
|
||||
#define EP1_ORR_BASE 0x0Cul
|
||||
#define EP1_OSR_BASE 0x10ul
|
||||
#define EP1_RISR_BASE 0x14ul
|
||||
#define EP1_FAL_BASE 0x18ul
|
||||
#define EP_NFCR_BASE 0x40010800ul + 0x0170ul
|
||||
|
||||
|
||||
/*! Parameter validity check for port group. */
|
||||
#define IS_VALID_EVENT_PORT(x) \
|
||||
( ((x) == EventPort1) || \
|
||||
((x) == EventPort2) || \
|
||||
((x) == EventPort3) || \
|
||||
((x) == EventPort4))
|
||||
|
||||
/*! Parameter validity check for pin. */
|
||||
#define IS_VALID_EVENT_PIN(x) \
|
||||
( ((x) == EventPin00) || \
|
||||
((x) == EventPin01) || \
|
||||
((x) == EventPin02) || \
|
||||
((x) == EventPin03) || \
|
||||
((x) == EventPin04) || \
|
||||
((x) == EventPin05) || \
|
||||
((x) == EventPin06) || \
|
||||
((x) == EventPin07) || \
|
||||
((x) == EventPin08) || \
|
||||
((x) == EventPin09) || \
|
||||
((x) == EventPin10) || \
|
||||
((x) == EventPin11) || \
|
||||
((x) == EventPin12) || \
|
||||
((x) == EventPin13) || \
|
||||
((x) == EventPin14) || \
|
||||
((x) == EventPin15))
|
||||
|
||||
/*! Parameter valid check for Event Port common trigger. */
|
||||
#define IS_EP_COM_TRIGGER(x) \
|
||||
( ((x) == EpComTrigger_1) || \
|
||||
((x) == EpComTrigger_2) || \
|
||||
((x) == EpComTrigger_1_2))
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event Port init
|
||||
**
|
||||
** \param [in] enEventPort Event port index, This parameter can be
|
||||
** any value of @ref en_event_port_t
|
||||
** \param [in] u16EventPin Event pin index, This parameter can be
|
||||
** any composed value of @ref en_event_pin_t
|
||||
** \param [in] pstcEventPortInit Structure pointer of event port configuration
|
||||
**
|
||||
** \retval Ok Init successful
|
||||
** ErrorInvalidParameter Event port index invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EVENTPORT_Init(en_event_port_t enEventPort, uint16_t u16EventPin, \
|
||||
const stc_event_port_init_t *pstcEventPortInit)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
uint32_t *EPDIRx; ///< Direction register
|
||||
uint32_t *EPORRx; ///< Reset after trigger enable register
|
||||
uint32_t *EPOSRx; ///< Set after trigger enable register
|
||||
uint32_t *EPRISRx; ///< Rising edge detect enable register
|
||||
uint32_t *EPFALx; ///< Falling edge detect enable register
|
||||
|
||||
EPDIRx = (uint32_t *)(EP1_BASE + EP1_DIR_BASE + (0x1C * enEventPort));
|
||||
EPORRx = (uint32_t *)(EP1_BASE + EP1_ORR_BASE + (0x1C * enEventPort));
|
||||
EPOSRx = (uint32_t *)(EP1_BASE + EP1_OSR_BASE + (0x1C * enEventPort));
|
||||
EPRISRx= (uint32_t *)(EP1_BASE + EP1_RISR_BASE+ (0x1C * enEventPort));
|
||||
EPFALx = (uint32_t *)(EP1_BASE + EP1_FAL_BASE + (0x1C * enEventPort));
|
||||
|
||||
/* Direction configure */
|
||||
if (EventPortOut == pstcEventPortInit->enDirection)
|
||||
{
|
||||
*EPDIRx |= u16EventPin;
|
||||
}
|
||||
else
|
||||
{
|
||||
*EPDIRx &= (~(uint32_t)u16EventPin) & 0xFFFFul;
|
||||
}
|
||||
|
||||
/* Reset if be triggered */
|
||||
if (Enable == pstcEventPortInit->enReset)
|
||||
{
|
||||
*EPORRx |= u16EventPin;
|
||||
}
|
||||
else
|
||||
{
|
||||
*EPORRx &= (~(uint32_t)u16EventPin) & 0xFFFFul;
|
||||
}
|
||||
|
||||
/* Set if be triggered */
|
||||
if (Enable == pstcEventPortInit->enSet)
|
||||
{
|
||||
*EPOSRx |= u16EventPin;
|
||||
}
|
||||
else
|
||||
{
|
||||
*EPOSRx &= (~(uint32_t)u16EventPin) & 0xFFFFul;
|
||||
}
|
||||
|
||||
/* Rising edge detect setting */
|
||||
if (Enable == pstcEventPortInit->enRisingDetect)
|
||||
{
|
||||
*EPRISRx |= u16EventPin;
|
||||
}
|
||||
else
|
||||
{
|
||||
*EPRISRx &= (~(uint32_t)u16EventPin) & 0xFFFFul;
|
||||
}
|
||||
|
||||
/* Falling edge detect setting */
|
||||
if (Enable == pstcEventPortInit->enFallingDetect)
|
||||
{
|
||||
*EPFALx |= u16EventPin;
|
||||
}
|
||||
else
|
||||
{
|
||||
*EPFALx &= (~(uint32_t)u16EventPin) & 0xFFFFul;
|
||||
}
|
||||
|
||||
/* Noise filter setting */
|
||||
switch (enEventPort)
|
||||
{
|
||||
case EventPort1:
|
||||
M4_AOS->PEVNTNFCR_f.NFEN1 = pstcEventPortInit->enFilter;
|
||||
M4_AOS->PEVNTNFCR_f.DIVS1 = pstcEventPortInit->enFilterClk;
|
||||
break;
|
||||
case EventPort2:
|
||||
M4_AOS->PEVNTNFCR_f.NFEN2 = pstcEventPortInit->enFilter;
|
||||
M4_AOS->PEVNTNFCR_f.DIVS2 = pstcEventPortInit->enFilterClk;
|
||||
break;
|
||||
case EventPort3:
|
||||
M4_AOS->PEVNTNFCR_f.NFEN3 = pstcEventPortInit->enFilter;
|
||||
M4_AOS->PEVNTNFCR_f.DIVS3 = pstcEventPortInit->enFilterClk;
|
||||
break;
|
||||
case EventPort4:
|
||||
M4_AOS->PEVNTNFCR_f.NFEN4 = pstcEventPortInit->enFilter;
|
||||
M4_AOS->PEVNTNFCR_f.DIVS4 = pstcEventPortInit->enFilterClk;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event Port de-init, restore all registers to default value
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok De-init successful
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EVENTPORT_DeInit(void)
|
||||
{
|
||||
uint32_t EPDIRx ;
|
||||
uint32_t EPODRx ;
|
||||
uint32_t EPORRx ;
|
||||
uint32_t EPOSRx ;
|
||||
uint32_t EPRISRx;
|
||||
uint32_t EPFALx ;
|
||||
uint8_t u8EPCnt;
|
||||
|
||||
EPDIRx = (uint32_t)(EP1_BASE + EP1_DIR_BASE);
|
||||
EPODRx = (uint32_t)(EP1_BASE + EP1_ODR_BASE);
|
||||
EPORRx = (uint32_t)(EP1_BASE + EP1_ORR_BASE);
|
||||
EPOSRx = (uint32_t)(EP1_BASE + EP1_OSR_BASE);
|
||||
EPRISRx = (uint32_t)(EP1_BASE + EP1_RISR_BASE);
|
||||
EPFALx = (uint32_t)(EP1_BASE + EP1_FAL_BASE);
|
||||
|
||||
/* Restore all registers to default value */
|
||||
M4_AOS->PORT_PEVNTTRGSR12 = 0x1FFul;
|
||||
M4_AOS->PORT_PEVNTTRGSR34 = 0x1FFul;
|
||||
M4_AOS->PEVNTNFCR = 0ul;
|
||||
for (u8EPCnt = 0u; u8EPCnt < 4u; u8EPCnt++)
|
||||
{
|
||||
*(uint32_t *)(EPDIRx + 0x1Cul * u8EPCnt) = 0ul;
|
||||
*(uint32_t *)(EPODRx + 0x1Cul * u8EPCnt) = 0ul;
|
||||
*(uint32_t *)(EPORRx + 0x1Cul * u8EPCnt) = 0ul;
|
||||
*(uint32_t *)(EPOSRx + 0x1Cul * u8EPCnt) = 0ul;
|
||||
*(uint32_t *)(EPRISRx + 0x1Cul * u8EPCnt) = 0ul;
|
||||
*(uint32_t *)(EPFALx + 0x1Cul * u8EPCnt) = 0ul;
|
||||
}
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event Port trigger source select
|
||||
**
|
||||
** \param [in] enEventPort Event port index, This parameter can be
|
||||
** any value of @ref en_event_port_t
|
||||
** \param [in] enTriggerSrc Event port trigger source. This parameter
|
||||
** can be any value of @ref en_event_src_t
|
||||
** \retval Ok Trigger source is set
|
||||
** ErrorInvalidParameter Invalid event port enum
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort, \
|
||||
en_event_src_t enTriggerSrc)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort));
|
||||
|
||||
if ((EventPort1 == enEventPort) || (EventPort2 == enEventPort))
|
||||
{
|
||||
M4_AOS->PORT_PEVNTTRGSR12 = enTriggerSrc;
|
||||
}
|
||||
else if ((EventPort3 == enEventPort) || (EventPort4 == enEventPort))
|
||||
{
|
||||
M4_AOS->PORT_PEVNTTRGSR34 = enTriggerSrc;
|
||||
}
|
||||
else
|
||||
{
|
||||
enRet = ErrorInvalidParameter;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable Event Port common trigger.
|
||||
**
|
||||
** \param [in] enEventPort Event port index, This parameter can be
|
||||
** any value of @ref en_event_port_t
|
||||
** \param [in] enComTrigger Event port common trigger selection.
|
||||
** See @ref en_event_port_com_trigger_t for details.
|
||||
** \param [in] enState Enable or disable the specified common trigger.
|
||||
**
|
||||
** \retval None.
|
||||
**
|
||||
******************************************************************************/
|
||||
void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort, \
|
||||
en_event_port_com_trigger_t enComTrigger, \
|
||||
en_functional_state_t enState)
|
||||
{
|
||||
uint32_t u32ComTrig = (uint32_t)enComTrigger;
|
||||
__IO uint32_t *TRGSELx;
|
||||
|
||||
TRGSELx = (__IO uint32_t *)((uint32_t)&M4_AOS->PORT_PEVNTTRGSR12 + (4UL * ((uint32_t)enEventPort/2UL)));
|
||||
|
||||
if (NULL != TRGSELx)
|
||||
{
|
||||
DDL_ASSERT(IS_EP_COM_TRIGGER(enComTrigger));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enState));
|
||||
|
||||
if (enState == Enable)
|
||||
{
|
||||
*TRGSELx |= (u32ComTrig << 30u);
|
||||
}
|
||||
else
|
||||
{
|
||||
*TRGSELx &= ~(u32ComTrig << 30u);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Read Event Port value after be triggered
|
||||
**
|
||||
** \param [in] enEventPort Event port index, This parameter can be
|
||||
** any value of @ref en_event_port_t
|
||||
**
|
||||
** \retval uint16_t The output port value
|
||||
**
|
||||
******************************************************************************/
|
||||
uint16_t EVENTPORT_GetData(en_event_port_t enEventPort)
|
||||
{
|
||||
uint16_t u16Data = 0u;
|
||||
DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort));
|
||||
switch (enEventPort)
|
||||
{
|
||||
case EventPort1:
|
||||
u16Data = (uint16_t)(M4_AOS->PEVNTIDR1 & 0xFFFFul);
|
||||
break;
|
||||
case EventPort2:
|
||||
u16Data = (uint16_t)(M4_AOS->PEVNTIDR2 & 0xFFFFul);
|
||||
break;
|
||||
case EventPort3:
|
||||
u16Data = (uint16_t)(M4_AOS->PEVNTIDR3 & 0xFFFFul);
|
||||
break;
|
||||
case EventPort4:
|
||||
u16Data = (uint16_t)(M4_AOS->PEVNTIDR4 & 0xFFFFul);
|
||||
break;
|
||||
}
|
||||
return u16Data;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Read Event Pin value after triggered
|
||||
**
|
||||
** \param [in] enEventPort Event port index, This parameter can be
|
||||
** any value of @ref en_event_port_t
|
||||
** \param [in] enEventPin GPIO pin index, This parameter can be
|
||||
** any value of @ref en_event_pin_t
|
||||
** \retval en_flag_status_t The output port pin value
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort, en_event_pin_t enEventPin)
|
||||
{
|
||||
bool bBitValue = false;
|
||||
|
||||
switch (enEventPort)
|
||||
{
|
||||
case EventPort1:
|
||||
bBitValue = M4_AOS->PEVNTIDR1 & enEventPin;
|
||||
break;
|
||||
case EventPort2:
|
||||
bBitValue = M4_AOS->PEVNTIDR2 & enEventPin;
|
||||
break;
|
||||
case EventPort3:
|
||||
bBitValue = M4_AOS->PEVNTIDR3 & enEventPin;
|
||||
break;
|
||||
case EventPort4:
|
||||
bBitValue = M4_AOS->PEVNTIDR4 & enEventPin;
|
||||
break;
|
||||
}
|
||||
return (en_flag_status_t)(bool)((!!bBitValue));
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Event Port Pin
|
||||
**
|
||||
** \param [in] enEventPort Event port index, This parameter can be
|
||||
** any value of @ref en_event_port_t
|
||||
** \param [in] u16EventPin Event pin index, This parameter can be
|
||||
** any composed value of @ref en_event_pin_t
|
||||
** \retval Ok Set successful
|
||||
** ErrorInvalidParameter Event port index invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort, en_event_pin_t u16EventPin)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort));
|
||||
|
||||
switch (enEventPort)
|
||||
{
|
||||
case EventPort1:
|
||||
M4_AOS->PEVNTODR1 |= u16EventPin;
|
||||
break;
|
||||
case EventPort2:
|
||||
M4_AOS->PEVNTODR2 |= u16EventPin;
|
||||
break;
|
||||
case EventPort3:
|
||||
M4_AOS->PEVNTODR3 |= u16EventPin;
|
||||
break;
|
||||
case EventPort4:
|
||||
M4_AOS->PEVNTODR4 |= u16EventPin;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Reset Event Port Pin
|
||||
**
|
||||
** \param [in] enEventPort Event port index, This parameter can be
|
||||
** any value of @ref en_event_port_t
|
||||
** \param [in] u16EventPin Event pin index, This parameter can be
|
||||
** any composed value of @ref en_event_pin_t
|
||||
** \retval Ok Reset successful
|
||||
** ErrorInvalidParameter Event port index invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort, en_event_pin_t u16EventPin)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort));
|
||||
|
||||
switch (enEventPort)
|
||||
{
|
||||
case EventPort1:
|
||||
M4_AOS->PEVNTODR1 &= (~(uint32_t)u16EventPin) & 0xFFFFul;
|
||||
break;
|
||||
case EventPort2:
|
||||
M4_AOS->PEVNTODR2 &= (~(uint32_t)u16EventPin) & 0xFFFFul;
|
||||
break;
|
||||
case EventPort3:
|
||||
M4_AOS->PEVNTODR3 &= (~(uint32_t)u16EventPin) & 0xFFFFul;
|
||||
break;
|
||||
case EventPort4:
|
||||
M4_AOS->PEVNTODR4 &= (~(uint32_t)u16EventPin) & 0xFFFFul;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
//@} // EventPortGroup
|
||||
|
||||
#endif /* DDL_EVENT_PORT_ENABLE */
|
||||
|
||||
/******************************************************************************
|
||||
* EOF (not truncated)
|
||||
*****************************************************************************/
|
||||
@@ -0,0 +1,337 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_exint_nmi_swi.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link ExintNmiSwiGroup Exint/Nmi/Swi description @endlink
|
||||
**
|
||||
** - 2018-10-17 CDT First version for Device Driver Library of exint, Nmi, SW interrupt.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_exint_nmi_swi.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup ExintNmiSwiGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*! Parameter validity check for external interrupt channel. */
|
||||
#define IS_VALID_CH(x) \
|
||||
( ((x) == ExtiCh00) || \
|
||||
((x) == ExtiCh01) || \
|
||||
((x) == ExtiCh02) || \
|
||||
((x) == ExtiCh03) || \
|
||||
((x) == ExtiCh04) || \
|
||||
((x) == ExtiCh05) || \
|
||||
((x) == ExtiCh06) || \
|
||||
((x) == ExtiCh07) || \
|
||||
((x) == ExtiCh08) || \
|
||||
((x) == ExtiCh09) || \
|
||||
((x) == ExtiCh10) || \
|
||||
((x) == ExtiCh11) || \
|
||||
((x) == ExtiCh12) || \
|
||||
((x) == ExtiCh13) || \
|
||||
((x) == ExtiCh14) || \
|
||||
((x) == ExtiCh15))
|
||||
|
||||
/*! Parameter validity check for null pointer. */
|
||||
#define IS_NULL_POINT(x) (NULL != (x))
|
||||
|
||||
/*! Parameter validity check for external interrupt trigger method. */
|
||||
#define IS_VALID_LEVEL(x) \
|
||||
( ((x) == ExIntLowLevel) || \
|
||||
((x) == ExIntBothEdge) || \
|
||||
((x) == ExIntRisingEdge) || \
|
||||
((x) == ExIntFallingEdge))
|
||||
|
||||
/*! Parameter validity check for NMI interrupt source. */
|
||||
#define IS_VALID_NMI_SRC(x) \
|
||||
( ((x) == NmiSrcNmi) || \
|
||||
((x) == NmiSrcSwdt) || \
|
||||
((x) == NmiSrcVdu1) || \
|
||||
((x) == NmiSrcVdu2) || \
|
||||
((x) == NmiSrcXtalStop) || \
|
||||
((x) == NmiSrcSramPE) || \
|
||||
((x) == NmiSrcSramDE) || \
|
||||
((x) == NmiSrcMpu) || \
|
||||
((x) == NmiSrcWdt))
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
static func_ptr_t pfnNmiCallback;
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief External Int initialization
|
||||
**
|
||||
** \param [in] pstcExtiConfig EXTI configure structure
|
||||
**
|
||||
** \retval Ok EXTI initialized
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EXINT_Init(const stc_exint_config_t *pstcExtiConfig)
|
||||
{
|
||||
stc_intc_eirqcr_field_t *EIRQCRx;
|
||||
|
||||
DDL_ASSERT(IS_VALID_CH(pstcExtiConfig->enExitCh));
|
||||
|
||||
EIRQCRx = (stc_intc_eirqcr_field_t *)((uint32_t)(&M4_INTC->EIRQCR0) + \
|
||||
(uint32_t)(4ul * (uint32_t)(pstcExtiConfig->enExitCh)));
|
||||
|
||||
/* Set filter function */
|
||||
EIRQCRx->EFEN = pstcExtiConfig->enFilterEn;
|
||||
EIRQCRx->EISMPCLK = pstcExtiConfig->enFltClk;
|
||||
|
||||
/* Set detection level */
|
||||
EIRQCRx->EIRQTRG = pstcExtiConfig->enExtiLvl;
|
||||
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get External interrupt request flag
|
||||
**
|
||||
** \param [in] enExint NMI Int source, This parameter can be
|
||||
** any value of @ref en_exti_ch_t
|
||||
**
|
||||
** \retval Set Corresponding Ex.Int request flag be set
|
||||
** Reset Corresponding Ex.Int request flag not be set
|
||||
**
|
||||
******************************************************************************/
|
||||
en_int_status_t EXINT_IrqFlgGet(en_exti_ch_t enExint)
|
||||
{
|
||||
en_int_status_t enRet;
|
||||
DDL_ASSERT(IS_VALID_CH(enExint));
|
||||
|
||||
enRet = (1u == !!(M4_INTC->EIFR & (1ul<<enExint)) ? Set : Reset);
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear External interrupt request flag
|
||||
**
|
||||
** \param [in] enExint Ext. interrupt channel, This parameter can be
|
||||
** any value of @ref en_exti_ch_t
|
||||
**
|
||||
** \retval Ok Interrupt source be cleared
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t EXINT_IrqFlgClr(en_exti_ch_t enExint)
|
||||
{
|
||||
M4_INTC->EICFR |= (uint32_t)(1ul << enExint);
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief NMI initialization
|
||||
**
|
||||
** \param [in] pstcNmiConfig NMI configure structure
|
||||
**
|
||||
** \retval Ok NMI initialized
|
||||
** ErrorInvalidParameter NMI configuration pointer is null
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t NMI_Init(const stc_nmi_config_t *pstcNmiConfig)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
if (NULL != pstcNmiConfig)
|
||||
{
|
||||
/* NMI callback function */
|
||||
pfnNmiCallback = pstcNmiConfig->pfnNmiCallback;
|
||||
/* Set filter function */
|
||||
M4_INTC->NMICR_f.NFEN = pstcNmiConfig->enFilterEn;
|
||||
/* Set filter clock */
|
||||
M4_INTC->NMICR_f.NSMPCLK = pstcNmiConfig->enFilterClk;
|
||||
/* Set detection level */
|
||||
M4_INTC->NMICR_f.NMITRG = pstcNmiConfig->enNmiLvl;
|
||||
/* Set NMI source */
|
||||
M4_INTC->NMIENR = (uint32_t)pstcNmiConfig->u16NmiSrc;
|
||||
enRet = Ok;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-Init Non-Maskable Interrupt (NMI)
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok NMI De-initialized
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t NMI_DeInit(void)
|
||||
{
|
||||
/* Set internal data */
|
||||
pfnNmiCallback = NULL;
|
||||
|
||||
/* clear NMI control register */
|
||||
M4_INTC->NMICR = 0u;
|
||||
|
||||
/* clear NMI enable register */
|
||||
M4_INTC->NMIENR = 0u;
|
||||
|
||||
/* clear all NMI flags */
|
||||
M4_INTC->NMIFR = 0u;
|
||||
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get NMI interrupt request flag
|
||||
**
|
||||
** \param [in] enNmiSrc NMI Int source, This parameter can be
|
||||
** any value of @ref en_nmi_src_t
|
||||
**
|
||||
** \retval Set Corresponding NMI flag be set
|
||||
** Reset Corresponding NMI flag not be set
|
||||
**
|
||||
******************************************************************************/
|
||||
en_int_status_t NMI_IrqFlgGet(en_nmi_src_t enNmiSrc)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_NMI_SRC(enNmiSrc));
|
||||
|
||||
en_int_status_t enRet = Reset;
|
||||
switch (enNmiSrc)
|
||||
{
|
||||
case NmiSrcNmi:
|
||||
enRet = (en_int_status_t)(M4_INTC->NMIFR_f.NMIFR);
|
||||
break;
|
||||
case NmiSrcSwdt:
|
||||
enRet = (en_int_status_t)(M4_INTC->NMIFR_f.SWDTFR);
|
||||
break;
|
||||
case NmiSrcVdu1:
|
||||
enRet = (en_int_status_t)(M4_INTC->NMIFR_f.PVD1FR);
|
||||
break;
|
||||
case NmiSrcVdu2:
|
||||
enRet = (en_int_status_t)(M4_INTC->NMIFR_f.PVD2FR);
|
||||
break;
|
||||
case NmiSrcXtalStop:
|
||||
enRet = (en_int_status_t)(M4_INTC->NMIFR_f.XTALSTPFR);
|
||||
break;
|
||||
case NmiSrcSramPE:
|
||||
enRet = (en_int_status_t)(M4_INTC->NMIFR_f.REPFR);
|
||||
break;
|
||||
case NmiSrcSramDE:
|
||||
enRet = (en_int_status_t)(M4_INTC->NMIFR_f.RECCFR);
|
||||
break;
|
||||
case NmiSrcMpu:
|
||||
enRet = (en_int_status_t)(M4_INTC->NMIFR_f.BUSMFR);
|
||||
break;
|
||||
case NmiSrcWdt:
|
||||
enRet = (en_int_status_t)(M4_INTC->NMIFR_f.WDTFR);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear NMI interrupt request flag
|
||||
**
|
||||
** \param [in] u16NmiSrc NMI Int source, This parameter can be
|
||||
** any composited value of @ref en_nmi_src_t
|
||||
**
|
||||
** \retval Ok Interrupt source be cleared
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t NMI_IrqFlgClr(uint16_t u16NmiSrc)
|
||||
{
|
||||
M4_INTC->NMICFR |= u16NmiSrc;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief ISR for NMI
|
||||
**
|
||||
******************************************************************************/
|
||||
void NMI_IrqHandler(void)
|
||||
{
|
||||
DDL_ASSERT(IS_NULL_POINT(pfnNmiCallback));
|
||||
|
||||
pfnNmiCallback();
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable Softeware Interrupt (SWI)
|
||||
**
|
||||
* \param [in] u32SwiCh This parameter can be any composited
|
||||
* value of @ref en_swi_ch_t
|
||||
**
|
||||
** \retval Ok SWI initialized
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t SWI_Enable(uint32_t u32SwiCh)
|
||||
{
|
||||
M4_INTC->SWIER |= u32SwiCh;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-Init Softeware Interrupt (SWI)
|
||||
**
|
||||
* \param [in] u32SwiCh This parameter can be any composited
|
||||
* value of @ref en_swi_ch_t
|
||||
**
|
||||
** \retval Ok SWI de-initialized
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t SWI_Disable(uint32_t u32SwiCh)
|
||||
{
|
||||
/* clear software interrupt enable register */
|
||||
M4_INTC->SWIER &= ~u32SwiCh;
|
||||
|
||||
return Ok;
|
||||
}
|
||||
|
||||
//@} // ExintNmiSwiGroup
|
||||
|
||||
#endif /* DDL_EXINT_NMI_SWI_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,671 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_gpio.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link GpioGroup Gpio description @endlink
|
||||
**
|
||||
** - 2018-10-12 CDT First version for Device Driver Library of Gpio.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_gpio.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_GPIO_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup GpioGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
#define GPIO_BASE (0x40053800ul)
|
||||
#define PODR_BASE (0x0004ul)
|
||||
#define POER_BASE (0x0006ul)
|
||||
#define POSR_BASE (0x0008ul)
|
||||
#define PORR_BASE (0x000Aul)
|
||||
#define PCR_BASE (0x0400ul)
|
||||
#define PFSR_BASE (0x0402ul)
|
||||
|
||||
/*! Parameter validity check for port group. */
|
||||
#define IS_VALID_PORT(x) \
|
||||
( ((x) == PortA) || \
|
||||
((x) == PortB) || \
|
||||
((x) == PortC) || \
|
||||
((x) == PortD) || \
|
||||
((x) == PortE) || \
|
||||
((x) == PortH))
|
||||
|
||||
/*! Parameter validity check for pin. */
|
||||
#define IS_VALID_PIN(x) \
|
||||
( ((x) == Pin00) || \
|
||||
((x) == Pin01) || \
|
||||
((x) == Pin02) || \
|
||||
((x) == Pin03) || \
|
||||
((x) == Pin04) || \
|
||||
((x) == Pin05) || \
|
||||
((x) == Pin06) || \
|
||||
((x) == Pin07) || \
|
||||
((x) == Pin08) || \
|
||||
((x) == Pin09) || \
|
||||
((x) == Pin10) || \
|
||||
((x) == Pin11) || \
|
||||
((x) == Pin12) || \
|
||||
((x) == Pin13) || \
|
||||
((x) == Pin14) || \
|
||||
((x) == Pin15))
|
||||
|
||||
/*! Parameter validity check for debug pins. */
|
||||
#define IS_VALID_DEBUGPIN(x) ((x) <= 0x1Fu)
|
||||
|
||||
/*! Parameter validity check for pin mode. */
|
||||
#define IS_VALID_PINMODE(x) \
|
||||
( ((x) == Pin_Mode_In) || \
|
||||
((x) == Pin_Mode_Out) || \
|
||||
((x) == Pin_Mode_Ana))
|
||||
|
||||
/*! Parameter validity check for pin drive capacity. */
|
||||
#define IS_VALID_PINDRV(x) \
|
||||
( ((x) == Pin_Drv_L) || \
|
||||
((x) == Pin_Drv_M) || \
|
||||
((x) == Pin_Drv_H))
|
||||
|
||||
/*! Parameter validity check for pin output type. */
|
||||
#define IS_VALID_PINTYPE(x) \
|
||||
( ((x) == Pin_OType_Cmos) || \
|
||||
((x) == Pin_OType_Od))
|
||||
|
||||
/*! Parameter validity check for pin read wait cycle. */
|
||||
#define IS_VALID_READWAIT(x) \
|
||||
( ((x) == WaitCycle0) || \
|
||||
((x) == WaitCycle1) || \
|
||||
((x) == WaitCycle2) || \
|
||||
((x) == WaitCycle3))
|
||||
|
||||
/*! Parameter validity check for pin function */
|
||||
#define IS_VALID_FUNC(x) \
|
||||
( ((x) == Func_Gpio) || \
|
||||
(((x) >= Func_Fcmref) && \
|
||||
((x) <= Func_I2s)) || \
|
||||
((x) == Func_Evnpt) || \
|
||||
((x) == Func_Eventout) || \
|
||||
(((x) >= Func_Usart1_Tx) && \
|
||||
((x) <= Func_I2s2_Ck)))
|
||||
|
||||
/*! Parameter validity check for pin sub-function */
|
||||
#define IS_VALID_SUBFUNC(x) \
|
||||
( ((x) == Func_Gpio) || \
|
||||
((x) == Func_Fcmref) || \
|
||||
((x) == Func_Rtcout) || \
|
||||
((x) == Func_Vcout) || \
|
||||
((x) == Func_Adtrg) || \
|
||||
((x) == Func_Mclkout) || \
|
||||
((x) == Func_Tim4) || \
|
||||
((x) == Func_Tim6) || \
|
||||
((x) == Func_Tima0) || \
|
||||
((x) == Func_Tima1) || \
|
||||
((x) == Func_Tima2) || \
|
||||
((x) == Func_Emb) || \
|
||||
((x) == Func_Usart_Ck) || \
|
||||
((x) == Func_Spi_Nss) || \
|
||||
((x) == Func_Qspi) || \
|
||||
((x) == Func_Key) || \
|
||||
((x) == Func_Sdio) || \
|
||||
((x) == Func_I2s) || \
|
||||
((x) == Func_UsbF) || \
|
||||
((x) == Func_Evnpt) || \
|
||||
((x) == Func_Eventout))
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Port init
|
||||
**
|
||||
** \param [in] enPort GPIO port index, This parameter can be
|
||||
** any value of @ref en_port_t
|
||||
** \param [in] u16Pin GPIO pin index, This parameter can be
|
||||
** any composed value of @ref en_pin_t
|
||||
** \param [in] pstcPortInit Structure pointer of port configuration
|
||||
**
|
||||
** \retval Ok Port initial successful
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_Init(en_port_t enPort, uint16_t u16Pin, const stc_port_init_t *pstcPortInit)
|
||||
{
|
||||
stc_port_pcr_field_t *PCRx;
|
||||
stc_port_pfsr_field_t * PFSRx;
|
||||
uint8_t u8PinPos = 0u;
|
||||
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_PORT(enPort));
|
||||
|
||||
DDL_ASSERT(IS_VALID_PINMODE(pstcPortInit->enPinMode));
|
||||
DDL_ASSERT(IS_VALID_PINDRV(pstcPortInit->enPinDrv));
|
||||
DDL_ASSERT(IS_VALID_PINTYPE(pstcPortInit->enPinOType));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enLatch));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enExInt));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enInvert));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enPullUp));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enPinSubFunc));
|
||||
|
||||
PORT_Unlock();
|
||||
for (u8PinPos = 0u; u8PinPos < 16u; u8PinPos ++)
|
||||
{
|
||||
if (u16Pin & (1ul<<u8PinPos))
|
||||
{
|
||||
PCRx = (stc_port_pcr_field_t *)((uint32_t)(&M4_PORT->PCRA0) + \
|
||||
enPort * 0x40ul + u8PinPos * 0x04ul);
|
||||
PFSRx = (stc_port_pfsr_field_t *)((uint32_t)(&M4_PORT->PFSRA0) + \
|
||||
enPort * 0x40ul + u8PinPos * 0x04ul);
|
||||
|
||||
/* Input latch function setting */
|
||||
PCRx->LTE = pstcPortInit->enLatch;
|
||||
|
||||
/* External interrupt input enable setting */
|
||||
PCRx->INTE = pstcPortInit->enExInt;
|
||||
|
||||
/* In_Out invert setting */
|
||||
PCRx->INVE = pstcPortInit->enInvert;
|
||||
|
||||
/* Pin pull-up setting */
|
||||
PCRx->PUU = pstcPortInit->enPullUp;
|
||||
|
||||
/* CMOS/OD output setting */
|
||||
PCRx->NOD = pstcPortInit->enPinOType;
|
||||
|
||||
/* Pin drive mode setting */
|
||||
PCRx->DRV = pstcPortInit->enPinDrv;
|
||||
|
||||
/* Pin mode setting */
|
||||
switch (pstcPortInit->enPinMode)
|
||||
{
|
||||
case Pin_Mode_In:
|
||||
PCRx->DDIS = 0u;
|
||||
PCRx->POUTE = 0u;
|
||||
break;
|
||||
case Pin_Mode_Out:
|
||||
PCRx->DDIS = 0u;
|
||||
PCRx->POUTE = 1u;
|
||||
break;
|
||||
case Pin_Mode_Ana:
|
||||
PCRx->DDIS = 1u;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
/* Sub function enable setting */
|
||||
PFSRx->BFE = pstcPortInit->enPinSubFunc;
|
||||
}
|
||||
}
|
||||
PORT_Lock();
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Port de-init
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok GPIO de-initial successful
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_DeInit(void)
|
||||
{
|
||||
uint8_t u8PortIdx, u8PinIdx;
|
||||
PORT_Unlock();
|
||||
|
||||
for (u8PortIdx = (uint8_t)PortA; u8PortIdx <= (uint8_t)PortH; u8PortIdx++)
|
||||
{
|
||||
*(uint16_t *)(GPIO_BASE + PODR_BASE + u8PortIdx * 0x10ul) = 0u;
|
||||
*(uint16_t *)(GPIO_BASE + POER_BASE + u8PortIdx * 0x10ul) = 0u;
|
||||
*(uint16_t *)(GPIO_BASE + POSR_BASE + u8PortIdx * 0x10ul) = 0u;
|
||||
*(uint16_t *)(GPIO_BASE + PORR_BASE + u8PortIdx * 0x10ul) = 0u;
|
||||
for (u8PinIdx = 0u; u8PinIdx < 16u; u8PinIdx++)
|
||||
{
|
||||
if (((uint8_t)PortH == u8PortIdx) && (3u == u8PinIdx))
|
||||
{
|
||||
break;
|
||||
}
|
||||
*(uint16_t *)(GPIO_BASE + PCR_BASE + u8PortIdx * 0x40ul + u8PinIdx * 0x4ul) = 0u;
|
||||
*(uint16_t *)(GPIO_BASE + PFSR_BASE + u8PortIdx * 0x40ul + u8PinIdx * 0x4ul) = 0u;
|
||||
}
|
||||
}
|
||||
M4_PORT->PCCR = 0u;
|
||||
M4_PORT->PINAER = 0u;
|
||||
M4_PORT->PSPCR = 0x1Fu;
|
||||
|
||||
PORT_Lock();
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Special control register Setting
|
||||
**
|
||||
** \param [in] u8DebugPort Debug port setting register, This parameter
|
||||
** can be any composed value of @ref en_debug_port_t
|
||||
**
|
||||
** \param [in] enFunc The new state of the debug ports.
|
||||
** \arg Enable Enable.
|
||||
** \arg Disable Disable.
|
||||
**
|
||||
** \retval Ok Debug port set successful
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_DebugPortSetting(uint8_t u8DebugPort, en_functional_state_t enFunc)
|
||||
{
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_DEBUGPIN(u8DebugPort));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enFunc));
|
||||
|
||||
PORT_Unlock();
|
||||
|
||||
if (Enable == enFunc)
|
||||
{
|
||||
M4_PORT->PSPCR |= (uint16_t)(u8DebugPort & 0x1Ful);
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_PORT->PSPCR &= (uint16_t)(~(u8DebugPort & 0x1Ful));
|
||||
}
|
||||
|
||||
PORT_Lock();
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Port Public Setting
|
||||
**
|
||||
** \param [in] pstcPortPubSet Structure pointer of public setting (PCCR)
|
||||
**
|
||||
** \retval Ok Port public register set successful
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_PubSetting(const stc_port_pub_set_t *pstcPortPubSet)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_FUNC(pstcPortPubSet->enSubFuncSel));
|
||||
DDL_ASSERT(IS_VALID_READWAIT(pstcPortPubSet->enReadWait));
|
||||
PORT_Unlock();
|
||||
|
||||
/* PCCR setting */
|
||||
/* Sub function setting */
|
||||
M4_PORT->PCCR_f.BFSEL = pstcPortPubSet->enSubFuncSel;
|
||||
|
||||
/* PIDRx, PCRxy read wait cycle setting */
|
||||
M4_PORT->PCCR_f.RDWT = pstcPortPubSet->enReadWait;
|
||||
|
||||
PORT_Lock();
|
||||
return Ok;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
void PORT_Unlock(void)
|
||||
{
|
||||
M4_PORT->PWPR = 0xA501u;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SPCR, PCCR, PINAER, PCRxy, PFSRxy write disable
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
void PORT_Lock(void)
|
||||
{
|
||||
M4_PORT->PWPR = 0xA500u;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Read Port value
|
||||
**
|
||||
** \param [in] enPort GPIO port index, This parameter can be
|
||||
** any value of @ref en_port_t
|
||||
**
|
||||
** \retval uint16_t The output port value
|
||||
**
|
||||
******************************************************************************/
|
||||
uint16_t PORT_GetData(en_port_t enPort)
|
||||
{
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_PORT(enPort));
|
||||
|
||||
uint32_t *PIDRx;
|
||||
PIDRx = (uint32_t *)((uint32_t)(&M4_PORT->PIDRA) + 0x10u * enPort);
|
||||
return (uint16_t)(*PIDRx);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Read Pin value
|
||||
**
|
||||
** \param [in] enPort GPIO port index, This parameter can be
|
||||
** any value of @ref en_port_t
|
||||
** \param [in] enPin GPIO pin index, This parameter can be
|
||||
** any value of @ref en_pin_t
|
||||
** \retval en_flag_status_t The output port pin value
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t PORT_GetBit(en_port_t enPort, en_pin_t enPin)
|
||||
{
|
||||
uint32_t *PIDRx;
|
||||
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_PORT(enPort));
|
||||
DDL_ASSERT(IS_VALID_PIN(enPin));
|
||||
|
||||
PIDRx = (uint32_t *)((uint32_t)(&M4_PORT->PIDRA) + 0x10u * enPort);
|
||||
return (en_flag_status_t)((bool)(!!(*PIDRx & (enPin))));
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Port value
|
||||
**
|
||||
** \param [in] enPort GPIO port index, This parameter can be
|
||||
** any value of @ref en_port_t
|
||||
** \param [in] u16Pin GPIO pin index, This parameter can be
|
||||
** any composed value of @ref en_pin_t
|
||||
**
|
||||
** \retval Ok Data be set to corresponding port
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_SetPortData(en_port_t enPort, uint16_t u16Pin)
|
||||
{
|
||||
uint16_t *PODRx;
|
||||
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_PORT(enPort));
|
||||
|
||||
PODRx = (uint16_t *)((uint32_t)(&M4_PORT->PODRA) + 0x10u * enPort);
|
||||
*PODRx |= u16Pin;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Port value
|
||||
**
|
||||
** \param [in] enPort GPIO port index, This parameter can be
|
||||
** any value of @ref en_port_t
|
||||
** \param [in] u16Pin GPIO pin index, This parameter can be
|
||||
** any composed value of @ref en_pin_t
|
||||
**
|
||||
** \retval Ok Data be reset to corresponding port
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_ResetPortData(en_port_t enPort, uint16_t u16Pin)
|
||||
{
|
||||
uint16_t *PODRx;
|
||||
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_PORT(enPort));
|
||||
|
||||
PODRx = (uint16_t *)((uint32_t)(&M4_PORT->PODRA) + 0x10u * enPort);
|
||||
*PODRx &= (uint16_t)(~u16Pin);
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Port Pin Output enable
|
||||
**
|
||||
** \param [in] enPort GPIO port index, This parameter can be
|
||||
** any value of @ref en_port_t
|
||||
** \param [in] u16Pin GPIO pin index, This parameter can be
|
||||
** any composed value of @ref en_pin_t
|
||||
** \param [in] enNewState The new state of pin direction setting
|
||||
** \retval Ok Set successful to corresponding port/pin
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_OE(en_port_t enPort, uint16_t u16Pin, en_functional_state_t enNewState)
|
||||
{
|
||||
uint16_t *POERx;
|
||||
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_PORT(enPort));
|
||||
|
||||
POERx = (uint16_t *)((uint32_t)(&M4_PORT->POERA) + 0x10ul * enPort);
|
||||
if (Enable == enNewState)
|
||||
{
|
||||
*POERx |= u16Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
*POERx &= (uint16_t)(~u16Pin);
|
||||
}
|
||||
return Ok;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Port Pin
|
||||
**
|
||||
** \param [in] enPort GPIO port index, This parameter can be
|
||||
** any value of @ref en_port_t
|
||||
** \param [in] u16Pin GPIO pin index, This parameter can be
|
||||
** any composed value of @ref en_pin_t
|
||||
** \retval Ok Set successful to corresponding pins
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_SetBits(en_port_t enPort, uint16_t u16Pin)
|
||||
{
|
||||
uint16_t *POSRx;
|
||||
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_PORT(enPort));
|
||||
|
||||
POSRx = (uint16_t *)((uint32_t)(&M4_PORT->POSRA) + 0x10u * enPort);
|
||||
*POSRx |= u16Pin;
|
||||
return Ok;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Reset Port Pin
|
||||
**
|
||||
** \param [in] enPort GPIO port index, This parameter can be
|
||||
** any value of @ref en_port_t
|
||||
** \param [in] u16Pin GPIO pin index, This parameter can be
|
||||
** any composed value of @ref en_pin_t
|
||||
** \retval Ok Set successful to corresponding pins
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_ResetBits(en_port_t enPort, uint16_t u16Pin)
|
||||
{
|
||||
uint16_t *PORRx;
|
||||
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_PORT(enPort));
|
||||
|
||||
PORRx = (uint16_t *)((uint32_t)(&M4_PORT->PORRA) + 0x10u * enPort);
|
||||
*PORRx |= u16Pin;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Toggle Port Pin
|
||||
**
|
||||
** \param [in] enPort GPIO port index, This parameter can be
|
||||
** any value of @ref en_port_t
|
||||
** \param [in] u16Pin GPIO pin index, This parameter can be
|
||||
** any composed value of @ref en_pin_t
|
||||
** \retval Ok Set successful to corresponding pins
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin)
|
||||
{
|
||||
uint16_t *POTRx;
|
||||
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_PORT(enPort));
|
||||
|
||||
POTRx = (uint16_t *)((uint32_t)(&M4_PORT->POTRA) + 0x10u * enPort);
|
||||
*POTRx |= u16Pin;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set port always ON
|
||||
**
|
||||
** \param [in] enPort GPIO port index, This parameter can be
|
||||
** any value of @ref en_port_t
|
||||
** \param [in] enNewState The new state of the port always ON function.
|
||||
** \arg Enable Enable.
|
||||
** \arg Disable Disable.
|
||||
**
|
||||
** \retval Ok Set successful to corresponding pins
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_AlwaysOn(en_port_t enPort, en_functional_state_t enNewState)
|
||||
{
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_PORT(enPort));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
||||
|
||||
PORT_Unlock();
|
||||
|
||||
if (Enable == enNewState)
|
||||
{
|
||||
M4_PORT->PINAER |= Enable << (uint8_t)enPort;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_PORT->PINAER &= (uint16_t)(~(((1ul << (uint8_t)enPort)) & 0x1Ful));
|
||||
}
|
||||
|
||||
PORT_Lock();
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Port Pin function
|
||||
**
|
||||
** \param [in] enPort GPIO port index, This parameter can be
|
||||
** any value of @ref en_port_t
|
||||
** \param [in] u16Pin GPIO pin index, This parameter can be
|
||||
** any value of @ref en_pin_t
|
||||
** \param [in] enFuncSel Function selection, This parameter can be
|
||||
** any value of @ref en_port_func_t
|
||||
**
|
||||
** \param [in] enSubFunc The new state of the gpio sub-function.
|
||||
** \arg Enable Enable.
|
||||
** \arg Disable Disable.
|
||||
**
|
||||
** \retval Ok Set successful to corresponding pins
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin, en_port_func_t enFuncSel, \
|
||||
en_functional_state_t enSubFunc)
|
||||
{
|
||||
stc_port_pfsr_field_t *PFSRx;
|
||||
uint8_t u8PinPos = 0u;
|
||||
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_PORT(enPort));
|
||||
DDL_ASSERT(IS_VALID_FUNC(enFuncSel));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enSubFunc));
|
||||
|
||||
PORT_Unlock();
|
||||
|
||||
for (u8PinPos = 0u; u8PinPos < 16u; u8PinPos ++)
|
||||
{
|
||||
if (u16Pin & (uint16_t)(1ul<<u8PinPos))
|
||||
{
|
||||
PFSRx = (stc_port_pfsr_field_t *)((uint32_t)(&M4_PORT->PFSRA0) \
|
||||
+ 0x40ul * enPort + 0x4ul * u8PinPos);
|
||||
|
||||
/* main function setting */
|
||||
PFSRx->FSEL = enFuncSel;
|
||||
|
||||
/* sub function enable setting */
|
||||
PFSRx->BFE = (Enable == enSubFunc ? Enable : Disable);
|
||||
}
|
||||
}
|
||||
|
||||
PORT_Lock();
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set global sub-function
|
||||
**
|
||||
** \param [in] enFuncSel Function selection, This parameter can be
|
||||
** some values of @ref en_port_func_t, cannot
|
||||
** large than 15u
|
||||
**
|
||||
** \retval Ok Set successful to corresponding pins
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t PORT_SetSubFunc(en_port_func_t enFuncSel)
|
||||
{
|
||||
/* parameter check */
|
||||
DDL_ASSERT(IS_VALID_SUBFUNC(enFuncSel));
|
||||
|
||||
PORT_Unlock();
|
||||
|
||||
M4_PORT->PCCR_f.BFSEL = enFuncSel;
|
||||
|
||||
PORT_Lock();
|
||||
return Ok;
|
||||
}
|
||||
|
||||
//@} // GpioGroup
|
||||
|
||||
#endif /* DDL_GPIO_ENABLE */
|
||||
|
||||
/******************************************************************************
|
||||
* EOF (not truncated)
|
||||
*****************************************************************************/
|
||||
@@ -0,0 +1,301 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_hash.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link HashGroup HASH description @endlink
|
||||
**
|
||||
** - 2018-10-18 CDT First version for Device Driver Library of HASH.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_hash.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_HASH_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup HashGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Constants definitions. */
|
||||
#define HASH_GROUP_LEN (64u)
|
||||
#define LAST_GROUP_MAX_LEN (56u)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
static void HASH_WriteData(const uint8_t *pu8SrcData);
|
||||
static void HASH_GetMsgDigest(uint8_t *pu8MsgDigest);
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Initialize the HASH.
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
void HASH_Init(void)
|
||||
{
|
||||
/* Stop hash calculating */
|
||||
bM4_HASH_CR_START = 0u;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DeInitialize the HASH.
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
void HASH_DeInit(void)
|
||||
{
|
||||
/* Stop hash calculating */
|
||||
bM4_HASH_CR_START = 0u;
|
||||
|
||||
/* Reset register CR. */
|
||||
M4_HASH->CR = 0u;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief HASH(SHA256) processes pu8SrcData.
|
||||
**
|
||||
** \param [in] pu8SrcData Pointer to the source data buffer (buffer to
|
||||
** be hashed).
|
||||
**
|
||||
** \param [in] u32SrcDataSize Length of the input buffer in bytes.
|
||||
**
|
||||
** \param [out] pu8MsgDigest Pointer to the computed digest. Its size
|
||||
** must be 32 bytes.
|
||||
**
|
||||
** \param [in] u32Timeout Timeout value.
|
||||
**
|
||||
** \retval Ok No error occurred.
|
||||
** \retval ErrorTimeout HASH works timeout.
|
||||
** \retval ErrorInvalidParameter Parameter error.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t HASH_Start(const uint8_t *pu8SrcData,
|
||||
uint32_t u32SrcDataSize,
|
||||
uint8_t *pu8MsgDigest,
|
||||
uint32_t u32Timeout)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
uint8_t u8FillBuffer[HASH_GROUP_LEN];
|
||||
uint8_t u8FirstGroup = 0u;
|
||||
uint8_t u8HashEnd = 0u;
|
||||
uint8_t u8DataEndMark = 0u;
|
||||
uint32_t u32Index = 0u;
|
||||
uint32_t u32BitLenHi;
|
||||
uint32_t u32BitLenLo;
|
||||
uint32_t u32HashTimeout;
|
||||
__IO uint32_t u32TimeCount;
|
||||
|
||||
if ((NULL != pu8SrcData) &&
|
||||
(0u != u32SrcDataSize) &&
|
||||
(NULL != pu8MsgDigest) &&
|
||||
(0u != u32Timeout))
|
||||
{
|
||||
/* 10 is the number of required instructions cycles for the below loop statement. */
|
||||
u32HashTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u);
|
||||
u32BitLenHi = (u32SrcDataSize >> 29u) & 0x7u;
|
||||
u32BitLenLo = (u32SrcDataSize << 3u);
|
||||
|
||||
while (1u)
|
||||
{
|
||||
/* Stop hash calculating. */
|
||||
bM4_HASH_CR_START = 0u;
|
||||
|
||||
if (u32SrcDataSize >= HASH_GROUP_LEN)
|
||||
{
|
||||
HASH_WriteData(&pu8SrcData[u32Index]);
|
||||
u32SrcDataSize -= HASH_GROUP_LEN;
|
||||
u32Index += HASH_GROUP_LEN;
|
||||
}
|
||||
else if (u32SrcDataSize >= LAST_GROUP_MAX_LEN)
|
||||
{
|
||||
memset(u8FillBuffer, 0, HASH_GROUP_LEN);
|
||||
memcpy(u8FillBuffer, &pu8SrcData[u32Index], u32SrcDataSize);
|
||||
u8FillBuffer[u32SrcDataSize] = 0x80u;
|
||||
u8DataEndMark = 1u;
|
||||
HASH_WriteData(u8FillBuffer);
|
||||
u32SrcDataSize = 0u;
|
||||
}
|
||||
else
|
||||
{
|
||||
u8HashEnd = 1u;
|
||||
}
|
||||
|
||||
if (u8HashEnd != 0u)
|
||||
{
|
||||
memset(u8FillBuffer, 0, HASH_GROUP_LEN);
|
||||
if (u32SrcDataSize > 0u)
|
||||
{
|
||||
memcpy(u8FillBuffer, &pu8SrcData[u32Index], u32SrcDataSize);
|
||||
}
|
||||
if (u8DataEndMark == 0u)
|
||||
{
|
||||
u8FillBuffer[u32SrcDataSize] = 0x80u;
|
||||
}
|
||||
u8FillBuffer[63u] = (uint8_t)(u32BitLenLo);
|
||||
u8FillBuffer[62u] = (uint8_t)(u32BitLenLo >> 8u);
|
||||
u8FillBuffer[61u] = (uint8_t)(u32BitLenLo >> 16u);
|
||||
u8FillBuffer[60u] = (uint8_t)(u32BitLenLo >> 24u);
|
||||
u8FillBuffer[59u] = (uint8_t)(u32BitLenHi);
|
||||
u8FillBuffer[58u] = (uint8_t)(u32BitLenHi >> 8u);
|
||||
u8FillBuffer[57u] = (uint8_t)(u32BitLenHi >> 16u);
|
||||
u8FillBuffer[56u] = (uint8_t)(u32BitLenHi >> 24u);
|
||||
HASH_WriteData(u8FillBuffer);
|
||||
}
|
||||
|
||||
/* check if first group */
|
||||
if (0u == u8FirstGroup)
|
||||
{
|
||||
u8FirstGroup = 1u;
|
||||
/* Set first group. */
|
||||
bM4_HASH_CR_FST_GRP = 1u;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set continuous group. */
|
||||
bM4_HASH_CR_FST_GRP = 0u;
|
||||
}
|
||||
|
||||
/* Start hash calculating. */
|
||||
bM4_HASH_CR_START = 1u;
|
||||
|
||||
u32TimeCount = 0u;
|
||||
enRet = ErrorTimeout;
|
||||
while (u32TimeCount < u32HashTimeout)
|
||||
{
|
||||
if (bM4_HASH_CR_START == 0u)
|
||||
{
|
||||
enRet = Ok;
|
||||
break;
|
||||
}
|
||||
u32TimeCount++;
|
||||
}
|
||||
|
||||
if ((ErrorTimeout == enRet) || (u8HashEnd != 0u))
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (Ok == enRet)
|
||||
{
|
||||
/* HASH calculated done */
|
||||
HASH_GetMsgDigest(pu8MsgDigest);
|
||||
}
|
||||
|
||||
/* Stop hash calculating. */
|
||||
bM4_HASH_CR_START = 0u;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Writes the input buffer in data register.
|
||||
**
|
||||
** \param [in] pu8SrcData Pointer to source data buffer.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
static void HASH_WriteData(const uint8_t *pu8SrcData)
|
||||
{
|
||||
uint8_t i;
|
||||
uint8_t j;
|
||||
uint32_t u32Temp;
|
||||
__IO uint32_t *io32HashDr = &(M4_HASH->DR15);
|
||||
|
||||
for (i = 0u; i < 16u; i++)
|
||||
{
|
||||
j = i * 4u + 3u;
|
||||
u32Temp = (uint32_t)pu8SrcData[j];
|
||||
u32Temp |= ((uint32_t)pu8SrcData[j-1u]) << 8u;
|
||||
u32Temp |= ((uint32_t)pu8SrcData[j-2u]) << 16u;
|
||||
u32Temp |= ((uint32_t)pu8SrcData[j-3u]) << 24u;
|
||||
|
||||
*io32HashDr = u32Temp;
|
||||
io32HashDr++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Provides the message digest result.
|
||||
**
|
||||
** \param [out] pu8MsgDigest Pointer to the message digest.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
static void HASH_GetMsgDigest(uint8_t *pu8MsgDigest)
|
||||
{
|
||||
uint8_t i;
|
||||
uint8_t j;
|
||||
uint32_t u32Temp;
|
||||
__IO uint32_t *io32HashHr = &(M4_HASH->HR7);
|
||||
|
||||
for (i = 0u; i < 8u; i++)
|
||||
{
|
||||
j = i * 4u + 3u;
|
||||
u32Temp = *io32HashHr;
|
||||
|
||||
pu8MsgDigest[j] = (uint8_t)u32Temp;
|
||||
pu8MsgDigest[j-1u] = (uint8_t)(u32Temp >> 8u);
|
||||
pu8MsgDigest[j-2u] = (uint8_t)(u32Temp >> 16u);
|
||||
pu8MsgDigest[j-3u] = (uint8_t)(u32Temp >> 24u);
|
||||
|
||||
io32HashHr++;
|
||||
}
|
||||
}
|
||||
|
||||
//@} // HashGroup
|
||||
|
||||
#endif /* DDL_HASH_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,437 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_i2s.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link I2sGroup Inter-IC Sound Bus description @endlink
|
||||
**
|
||||
** - 2018-10-28 CDT First version for Device Driver Library of I2S.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_i2s.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_I2S_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup I2sGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*!< Parameter valid check for I2S register pointer */
|
||||
#define IS_VALID_I2S_REG(x) \
|
||||
( (M4_I2S1 == (x)) || \
|
||||
(M4_I2S2 == (x)) || \
|
||||
(M4_I2S3 == (x)) || \
|
||||
(M4_I2S4 == (x)))
|
||||
|
||||
/*!< Parameter valid check for I2S function */
|
||||
#define IS_VALID_I2S_FUNCTION(x) \
|
||||
( (TxEn == (x)) || \
|
||||
(TxIntEn == (x)) || \
|
||||
(RxEn == (x)) || \
|
||||
(RxIntEn == (x)) || \
|
||||
(ErrIntEn == (x)))
|
||||
|
||||
/*!< Parameter valid check for I2S status bits */
|
||||
#define IS_VALID_I2S_STATUS(x) \
|
||||
( (TxBufAlarmFlag == (x)) || \
|
||||
(RxBufAlarmFlag == (x)) || \
|
||||
(TxBufEmptFlag == (x)) || \
|
||||
(TxBufFullFlag == (x)) || \
|
||||
(RxBufEmptFlag == (x)) || \
|
||||
(RxBufFullFlag == (x)))
|
||||
|
||||
/*!< Parameter valid check for I2S error flag */
|
||||
#define IS_VALID_I2S_ERR_FLAG(x) \
|
||||
( (ClrTxErrFlag == (x)) || \
|
||||
(ClrRxErrFlag == (x)))
|
||||
|
||||
/*!< Parameter valid check for I2S mode */
|
||||
#define IS_VALID_I2S_MODE(x) \
|
||||
( (I2sMaster == (x)) || \
|
||||
(I2sSlave == (x)))
|
||||
|
||||
/*!< Parameter valid check for I2S full duplex mode */
|
||||
#define IS_VALID_I2S_DUPLEX_MODE(x) \
|
||||
( (I2s_HalfDuplex == (x)) || \
|
||||
(I2s_FullDuplex == (x)))
|
||||
|
||||
/*!< Parameter valid check for I2S standard */
|
||||
#define IS_VALID_I2S_STANDARD(x) \
|
||||
( (Std_Philips == (x)) || \
|
||||
(Std_MSBJust == (x)) || \
|
||||
(Std_LSBJust == (x)) || \
|
||||
(Std_PCM == (x)))
|
||||
|
||||
/*!< Parameter valid check for I2S data length */
|
||||
#define IS_VALID_I2S_DATA_LEN(x) \
|
||||
( (I2s_DataLen_16Bit == (x)) || \
|
||||
(I2s_DataLen_24Bit == (x)) || \
|
||||
(I2s_DataLen_32Bit == (x)))
|
||||
|
||||
/*!< Parameter valid check for I2S channel data length */
|
||||
#define IS_VALID_I2S_CHANNEL_LEN(x) \
|
||||
( (I2s_ChLen_16Bit == (x)) || \
|
||||
(I2s_ChLen_32Bit == (x)))
|
||||
|
||||
/*!< Parameter valid check for I2S MCK output config */
|
||||
#define IS_VALID_I2S_MCKOUT(x) \
|
||||
( (Disable == (x)) || \
|
||||
(Enable == (x)))
|
||||
|
||||
/*!< Parameter valid check for I2S EXCK config */
|
||||
#define IS_VALID_I2S_EXCK(x) \
|
||||
( (Disable == (x)) || \
|
||||
(Enable == (x)))
|
||||
|
||||
/*!< Parameter valid check for I2S audio frequecy */
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) \
|
||||
( (((FREQ) >= I2S_AudioFreq_8k) && ((FREQ) <= I2S_AudioFreq_192k)) || \
|
||||
((FREQ) == I2S_AudioFreq_Default))
|
||||
|
||||
/*! I2S registers reset value */
|
||||
#define I2S_REG_CTRL_RESET_VALUE (0x00002200ul)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief I2S function command
|
||||
**
|
||||
** \param [in] pstcI2sReg Pointer to I2S register
|
||||
** \param [in] enFunc I2S function
|
||||
** \arg Refer @ref en_i2s_func_t
|
||||
** \param [in] enNewState New status
|
||||
** \arg Refer @ref en_functional_state_t
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
void I2S_FuncCmd(M4_I2S_TypeDef* pstcI2sReg, en_i2s_func_t enFunc,
|
||||
en_functional_state_t enNewState)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg));
|
||||
DDL_ASSERT(IS_VALID_I2S_FUNCTION(enFunc));
|
||||
|
||||
if(Enable == enNewState)
|
||||
{
|
||||
if(0ul == (pstcI2sReg->CTRL & (1ul << enFunc)))
|
||||
{
|
||||
pstcI2sReg->CTRL |= (1ul << enFunc);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(0ul != (pstcI2sReg->CTRL & (1ul << enFunc)))
|
||||
{
|
||||
pstcI2sReg->CTRL &= ~(1ul << (uint8_t)enFunc);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get I2S status bit
|
||||
**
|
||||
** \param [in] pstcI2sReg Pointer to I2S register
|
||||
** \param [in] enStd I2S status bit
|
||||
** \arg Refer @ref en_i2s_std_t
|
||||
**
|
||||
** \retval Set flag is set
|
||||
** \retval Reset flag is reset
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t I2S_GetStatus(M4_I2S_TypeDef* pstcI2sReg, en_i2s_std_t enStd)
|
||||
{
|
||||
en_flag_status_t enRet = Reset;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg));
|
||||
DDL_ASSERT(IS_VALID_I2S_STATUS(enStd));
|
||||
|
||||
if (0ul != ((uint32_t)(pstcI2sReg->SR & (1ul << (uint8_t)enStd))))
|
||||
{
|
||||
enRet = Set;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear I2S error flag
|
||||
**
|
||||
** \param [in] pstcI2sReg Pointer to I2S register
|
||||
** \param [in] enErrFlag I2S Error flag
|
||||
** \arg Refer @ref en_i2s_err_flag_t
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
void I2S_ClrErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg));
|
||||
DDL_ASSERT(IS_VALID_I2S_ERR_FLAG(enErrFlag));
|
||||
|
||||
pstcI2sReg->ER |= (1ul << (uint8_t)enErrFlag);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get I2S error flag
|
||||
**
|
||||
** \param [in] pstcI2sReg Pointer to I2S register
|
||||
** \param [in] enErrFlag I2S Error flag
|
||||
** \arg Refer @ref en_i2s_err_flag_t
|
||||
**
|
||||
** \retval Set flag is set
|
||||
** \retval Reset flag is reset
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t I2S_GetErrFlag(M4_I2S_TypeDef* pstcI2sReg,
|
||||
en_i2s_err_flag_t enErrFlag)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg));
|
||||
DDL_ASSERT(IS_VALID_I2S_ERR_FLAG(enErrFlag));
|
||||
|
||||
return (en_flag_status_t)((uint32_t)(pstcI2sReg->ER | (1ul << (uint8_t)enErrFlag)));
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Write data to I2s data send register
|
||||
**
|
||||
** \param [in] pstcI2sReg Pointer to I2S register
|
||||
** \param [in] u32Data Data to be send
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
void I2S_SendData(M4_I2S_TypeDef* pstcI2sReg, uint32_t u32Data)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg));
|
||||
|
||||
pstcI2sReg->TXBUF = u32Data;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Read data from I2s data receive register
|
||||
**
|
||||
** \param [in] pstcI2sReg Pointer to I2S register
|
||||
**
|
||||
** \retval uint32_t The data read out
|
||||
**
|
||||
******************************************************************************/
|
||||
uint32_t I2S_RevData(const M4_I2S_TypeDef* pstcI2sReg)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg));
|
||||
|
||||
return pstcI2sReg->RXBUF;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Initialize I2S module
|
||||
**
|
||||
** \param [in] pstcI2sReg Pointer to I2S register
|
||||
** \arg M4_I2S1 I2s channel 1
|
||||
** \arg M4_I2S2 I2s channel 2
|
||||
** \arg M4_I2S3 I2s channel 3
|
||||
** \arg M4_I2S4 I2s channel 4
|
||||
** \param [in] pstcI2sCfg Pointer to I2S configuration structure
|
||||
**
|
||||
** \retval Ok Initialize successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t I2s_Init(M4_I2S_TypeDef* pstcI2sReg, const stc_i2s_config_t* pstcI2sCfg)
|
||||
{
|
||||
uint32_t i2sclk = 0ul, tmp=0ul;
|
||||
uint8_t u8ChanelDataBit,u8ChanMul;
|
||||
uint16_t i2sdiv, i2sodd;
|
||||
stc_i2s_cfgr_field_t stcCFGR_Tmp = {0};
|
||||
stc_i2s_ctrl_field_t stcCTRL_Tmp = {0};
|
||||
en_result_t enRes = Ok;
|
||||
uint32_t u32AdrTmp = 0ul;
|
||||
|
||||
if((NULL == pstcI2sReg)||(NULL == pstcI2sCfg))
|
||||
{
|
||||
enRes = ErrorInvalidParameter;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg));
|
||||
DDL_ASSERT(IS_VALID_I2S_MODE(pstcI2sCfg->enMode));
|
||||
DDL_ASSERT(IS_VALID_I2S_DUPLEX_MODE(pstcI2sCfg->enFullDuplexMode));
|
||||
DDL_ASSERT(IS_VALID_I2S_STANDARD(pstcI2sCfg->enStandrad));
|
||||
DDL_ASSERT(IS_VALID_I2S_DATA_LEN(pstcI2sCfg->enDataBits));
|
||||
DDL_ASSERT(IS_VALID_I2S_CHANNEL_LEN(pstcI2sCfg->enChanelLen));
|
||||
DDL_ASSERT(IS_VALID_I2S_MCKOUT(pstcI2sCfg->enMcoOutEn));
|
||||
DDL_ASSERT(IS_VALID_I2S_EXCK(pstcI2sCfg->enExckEn));
|
||||
DDL_ASSERT(IS_I2S_AUDIO_FREQ(pstcI2sCfg->u32AudioFreq));
|
||||
|
||||
/* Set config register to default value*/
|
||||
pstcI2sReg->CTRL = I2S_REG_CTRL_RESET_VALUE;
|
||||
/* Clear status register*/
|
||||
pstcI2sReg->ER_f.TXERR = 1ul;
|
||||
pstcI2sReg->ER_f.RXERR = 1ul;
|
||||
|
||||
//*(uint32_t*)&stcCTRL_Tmp = pstcI2sReg->CTRL;
|
||||
u32AdrTmp = (uint32_t)&stcCTRL_Tmp;
|
||||
*(uint32_t*)u32AdrTmp = pstcI2sReg->CTRL;
|
||||
|
||||
/* ---- config I2s clock source---- */
|
||||
if(Enable == pstcI2sCfg->enExckEn)
|
||||
{
|
||||
/* Set external clock as I2S clock source */
|
||||
stcCTRL_Tmp.CLKSEL = 1ul;
|
||||
stcCTRL_Tmp.I2SPLLSEL = 0ul;
|
||||
/* Set the I2S clock to the external clock value */
|
||||
i2sclk = I2S_EXTERNAL_CLOCK_VAL;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set internal clock as I2S clock source */
|
||||
stcCTRL_Tmp.CLKSEL = 0ul;
|
||||
stcCTRL_Tmp.I2SPLLSEL = 1ul;
|
||||
/* Get i2s clock internal frequency */
|
||||
i2sclk = pstcI2sCfg->u32I2sInterClkFreq;
|
||||
}
|
||||
/* config audio sampple rate */
|
||||
if(I2s_ChLen_16Bit == pstcI2sCfg->enChanelLen)
|
||||
{
|
||||
u8ChanelDataBit = 16u;
|
||||
u8ChanMul = 8u;
|
||||
}
|
||||
else
|
||||
{
|
||||
u8ChanelDataBit = 32u;
|
||||
u8ChanMul = 4u;
|
||||
}
|
||||
|
||||
/*config I2S clock*/
|
||||
if(true == pstcI2sCfg->enMcoOutEn)
|
||||
{
|
||||
/* MCLK output is enabled */
|
||||
tmp = i2sclk/(pstcI2sCfg->u32AudioFreq * u8ChanelDataBit * 2ul * u8ChanMul);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* MCLK output is disabled */
|
||||
tmp = i2sclk/(pstcI2sCfg->u32AudioFreq * u8ChanelDataBit * 2ul);
|
||||
}
|
||||
i2sodd = (uint16_t)(tmp & 0x0001ul);
|
||||
i2sdiv = (uint16_t)((tmp - (uint32_t)i2sodd) / 2ul);
|
||||
|
||||
/* Test if the divider is 1 or 0 or greater than 0xFF */
|
||||
if ((i2sdiv < 2u) || (i2sdiv > 0xFFu))
|
||||
{
|
||||
/* Set the default values */
|
||||
i2sdiv = 2u;
|
||||
i2sodd = 0u;
|
||||
}
|
||||
|
||||
/* Write I2SPR register */
|
||||
pstcI2sReg->PR_f.I2SDIV = (uint8_t)i2sdiv;
|
||||
|
||||
/* Config and write I2S_CFGR */
|
||||
stcCFGR_Tmp.CHLEN = pstcI2sCfg->enChanelLen;
|
||||
stcCFGR_Tmp.DATLEN = pstcI2sCfg->enDataBits;
|
||||
stcCFGR_Tmp.I2SSTD = pstcI2sCfg->enStandrad;
|
||||
stcCFGR_Tmp.PCMSYNC = PCM_SYNC_FRAME;
|
||||
pstcI2sReg->CFGR_f = stcCFGR_Tmp;
|
||||
|
||||
/* Config CTRL register */
|
||||
stcCTRL_Tmp.WMS = pstcI2sCfg->enMode;
|
||||
stcCTRL_Tmp.DUPLEX = pstcI2sCfg->enFullDuplexMode;
|
||||
if(I2sMaster == pstcI2sCfg->enMode)
|
||||
{
|
||||
stcCTRL_Tmp.CKOE = 1u;
|
||||
stcCTRL_Tmp.LRCKOE = 1u;
|
||||
}
|
||||
stcCTRL_Tmp.SDOE = 1u;
|
||||
stcCTRL_Tmp.MCKOE = pstcI2sCfg->enMcoOutEn;
|
||||
stcCTRL_Tmp.ODD = (uint8_t)i2sodd;
|
||||
stcCTRL_Tmp.RXBIRQWL = RXBUF_IRQ_WL;
|
||||
stcCTRL_Tmp.TXBIRQWL = TXBUF_IRQ_WL;
|
||||
//pstcI2sReg->CTRL = *(uint32_t*)&stcCTRL_Tmp;
|
||||
u32AdrTmp = (uint32_t)&stcCTRL_Tmp;
|
||||
pstcI2sReg->CTRL = *(uint32_t*)u32AdrTmp;
|
||||
}
|
||||
return enRes;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-Initialize I2S module
|
||||
**
|
||||
** \param [in] pstcI2sReg Pointer to I2S register
|
||||
** \arg M4_I2S1 I2s channel 1
|
||||
** \arg M4_I2S2 I2s channel 2
|
||||
** \arg M4_I2S3 I2s channel 3
|
||||
** \arg M4_I2S4 I2s channel 4
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t I2s_DeInit(M4_I2S_TypeDef* pstcI2sReg)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg));
|
||||
|
||||
/* Set config register to default value*/
|
||||
pstcI2sReg->CTRL = I2S_REG_CTRL_RESET_VALUE;
|
||||
/* Clear status register*/
|
||||
pstcI2sReg->ER_f.TXERR = 1u;
|
||||
pstcI2sReg->ER_f.RXERR = 1u;
|
||||
|
||||
return Ok;
|
||||
}
|
||||
|
||||
//@} // I2sGroup
|
||||
|
||||
#endif /* DDL_I2S_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,83 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_icg.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link IcgGroup Initialize Configure description @endlink
|
||||
**
|
||||
** - 2018-10-15 CDT First version for Device Driver Library of ICG.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_icg.h"
|
||||
|
||||
#if (DDL_ICG_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup IcgGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
const uint32_t u32ICG[] __attribute__((section(".icg_sec"))) =
|
||||
#elif defined (__CC_ARM)
|
||||
const uint32_t u32ICG[] __attribute__((at(0x400))) =
|
||||
#elif defined (__ICCARM__)
|
||||
__root const uint32_t u32ICG[] @ 0x400 =
|
||||
#else
|
||||
#error "unsupported compiler!!"
|
||||
#endif
|
||||
{
|
||||
/* ICG 0~ 3 */
|
||||
ICG0_REGISTER_CONSTANT,
|
||||
ICG1_REGISTER_CONSTANT,
|
||||
ICG2_REGISTER_CONSTANT,
|
||||
ICG3_REGISTER_CONSTANT,
|
||||
/* ICG 4~ 7 */
|
||||
ICG4_REGISTER_CONSTANT,
|
||||
ICG5_REGISTER_CONSTANT,
|
||||
ICG6_REGISTER_CONSTANT,
|
||||
ICG7_REGISTER_CONSTANT,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
|
||||
//@} // IcgGroup
|
||||
|
||||
#endif /* DDL_ICG_ENABLE */
|
||||
|
||||
/******************************************************************************
|
||||
* EOF (not truncated)
|
||||
*****************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,207 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_keyscan.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link KeyscanGroup Keyscan module description @endlink
|
||||
**
|
||||
** - 2018-10-17 CDT First version for Device Driver Library of keyscan.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_keyscan.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_KEYSCAN_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup KeyscanGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*! Parameter validity check for Hiz cycle */
|
||||
#define IS_VALID_HIZ_CLCYE(x) \
|
||||
( ((x) == Hiz4) || \
|
||||
((x) == Hiz8) || \
|
||||
((x) == Hiz16) || \
|
||||
((x) == Hiz32) || \
|
||||
((x) == Hiz64) || \
|
||||
((x) == Hiz256) || \
|
||||
((x) == Hiz512) || \
|
||||
((x) == Hiz1K))
|
||||
|
||||
/*! Parameter validity check for Low cycle */
|
||||
#define IS_VALID_LOW_CLCYE(x) \
|
||||
( ((x) == Low8) || \
|
||||
((x) == Low16) || \
|
||||
((x) == Low32) || \
|
||||
((x) == Low64) || \
|
||||
((x) == Low128) || \
|
||||
((x) == Low256) || \
|
||||
((x) == Low512) || \
|
||||
((x) == Low1K) || \
|
||||
((x) == Low2K) || \
|
||||
((x) == Low4K) || \
|
||||
((x) == Low8K) || \
|
||||
((x) == Low16K) || \
|
||||
((x) == Low32K) || \
|
||||
((x) == Low64K) || \
|
||||
((x) == Low128K) || \
|
||||
((x) == Low256K) || \
|
||||
((x) == Low512K) || \
|
||||
((x) == Low1M) || \
|
||||
((x) == Low2M) || \
|
||||
((x) == Low4M) || \
|
||||
((x) == Low8M) || \
|
||||
((x) == Low16M))
|
||||
|
||||
/*! Parameter validity check for scan clock */
|
||||
#define IS_VALID_SCAN_CLK(x) \
|
||||
( ((x) == KeyscanHclk) || \
|
||||
((x) == KeyscanLrc) || \
|
||||
((x) == KeyscanXtal32))
|
||||
|
||||
/*! Parameter validity check for keyout selection */
|
||||
#define IS_VALID_KEY_OUT(x) \
|
||||
( ((x) == Keyout0To1) || \
|
||||
((x) == Keyout0To2) || \
|
||||
((x) == Keyout0To3) || \
|
||||
((x) == Keyout0To4) || \
|
||||
((x) == Keyout0To5) || \
|
||||
((x) == Keyout0To6) || \
|
||||
((x) == Keyout0To7))
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief KEYSCAN initialization
|
||||
**
|
||||
** \param [in] pstcKeyscanConfig KEYSCAN configure structure
|
||||
**
|
||||
** \retval Ok KEYSCAN initialized
|
||||
** ErrorInvalidMode Uninitialized, cannot configure it properly
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t KEYSCAN_Init(const stc_keyscan_config_t *pstcKeyscanConfig)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
DDL_ASSERT(IS_VALID_HIZ_CLCYE(pstcKeyscanConfig->enHizCycle));
|
||||
DDL_ASSERT(IS_VALID_LOW_CLCYE(pstcKeyscanConfig->enLowCycle));
|
||||
DDL_ASSERT(IS_VALID_SCAN_CLK(pstcKeyscanConfig->enKeyscanClk));
|
||||
DDL_ASSERT(IS_VALID_KEY_OUT(pstcKeyscanConfig->enKeyoutSel));
|
||||
|
||||
/* cannot configure keyscan control register when running */
|
||||
if (Set == M4_KEYSCAN->SER_f.SEN)
|
||||
{
|
||||
enRet = ErrorInvalidMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_KEYSCAN->SCR_f.T_HIZ = pstcKeyscanConfig->enHizCycle;
|
||||
M4_KEYSCAN->SCR_f.T_LLEVEL = pstcKeyscanConfig->enLowCycle;
|
||||
M4_KEYSCAN->SCR_f.CKSEL = pstcKeyscanConfig->enKeyscanClk;
|
||||
M4_KEYSCAN->SCR_f.KEYOUTSEL = pstcKeyscanConfig->enKeyoutSel;
|
||||
M4_KEYSCAN->SCR_f.KEYINSEL = pstcKeyscanConfig->u16KeyinSel;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief KEYSCAN de-initialization
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok KEYSCAN de-initialized
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t KEYSCAN_DeInit(void)
|
||||
{
|
||||
M4_KEYSCAN->SER = 0ul;
|
||||
M4_KEYSCAN->SCR = 0ul;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Start keyscan function
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok Keyscan function started
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t KEYSCAN_Start(void)
|
||||
{
|
||||
M4_KEYSCAN->SER_f.SEN = Set;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Stop keyscan function
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok Keyscan function stopped
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t KEYSCAN_Stop(void)
|
||||
{
|
||||
M4_KEYSCAN->SER_f.SEN = Reset;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Key column index
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval uint8_t Index of KEYOUT
|
||||
**
|
||||
******************************************************************************/
|
||||
uint8_t KEYSCAN_GetColIdx(void)
|
||||
{
|
||||
return (uint8_t)(M4_KEYSCAN->SSR_f.INDEX);
|
||||
}
|
||||
|
||||
//@} // KeyscanGroup
|
||||
|
||||
#endif /* DDL_KEYSCAN_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,386 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_ots.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link OtsGroup Ots description @endlink
|
||||
**
|
||||
** - 2018-10-26 CDT First version for Device Driver Library of Ots.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_ots.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_OTS_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup OtsGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*! Parameter validity check for OTS auto off configuration value. */
|
||||
#define IS_OTS_AUTO_OFF(EN) \
|
||||
( ((EN) == OtsAutoOff_Disable) || \
|
||||
((EN) == OtsAutoOff_Enable))
|
||||
|
||||
/*! Parameter validity check for OTS interrupt enable/disable. */
|
||||
#define IS_OTS_IE(IE) \
|
||||
( ((IE) == OtsInt_Disable) || \
|
||||
((IE) == OtsInt_Enable))
|
||||
|
||||
/*! Parameter validity check for OTS clock selection configuration value. */
|
||||
#define IS_OTS_CLK_SEL(CLK) \
|
||||
( ((CLK) == OtsClkSel_Xtal) || \
|
||||
((CLK) == OtsClkSel_Hrc))
|
||||
|
||||
/*! Parameter validity check for OTS trigger source event . */
|
||||
#define IS_OTS_TRIG_SRC_EVENT(x) \
|
||||
( (((x) >= EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \
|
||||
(((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \
|
||||
(((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \
|
||||
(((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \
|
||||
(((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \
|
||||
(((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \
|
||||
(((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \
|
||||
(((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \
|
||||
(((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \
|
||||
(((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \
|
||||
(((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \
|
||||
(((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \
|
||||
(((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \
|
||||
(((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \
|
||||
(((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \
|
||||
(((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \
|
||||
(((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \
|
||||
(((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \
|
||||
(((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \
|
||||
(((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \
|
||||
(((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \
|
||||
(((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \
|
||||
(((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \
|
||||
(((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \
|
||||
(((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \
|
||||
(((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \
|
||||
((x) == EVT_WDT_REFUDF) || \
|
||||
(((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \
|
||||
(((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \
|
||||
(((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \
|
||||
((x) == EVT_MAX))
|
||||
|
||||
/*! Parameter validity check for OTS common trigger. */
|
||||
#define IS_OTS_COM_TRIGGER(x) \
|
||||
( ((x) == OtsComTrigger_1) || \
|
||||
((x) == OtsComTrigger_2) || \
|
||||
((x) == OtsComTrigger_1_2))
|
||||
|
||||
#define EXPERIMENT_COUNT ((uint8_t)10)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
static float32_t m_f32SlopeK = 0.0f;
|
||||
static float32_t m_f32OffsetM = 0.0f;
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Initializes the OTS.
|
||||
**
|
||||
** \param [in] pstcInit See @ref stc_ots_init_t for details.
|
||||
**
|
||||
** \retval Ok No error occurred.
|
||||
** \retval ErrorInvalidParameter Parameter error.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t OTS_Init(const stc_ots_init_t *pstcInit)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
if (NULL != pstcInit)
|
||||
{
|
||||
DDL_ASSERT(IS_OTS_AUTO_OFF(pstcInit->enAutoOff));
|
||||
DDL_ASSERT(IS_OTS_CLK_SEL(pstcInit->enClkSel));
|
||||
|
||||
/* Stop ots sampling. */
|
||||
bM4_OTS_CTL_OTSST = 0u;
|
||||
/* Disable OTS interrupt default. */
|
||||
bM4_OTS_CTL_OTSIE = OtsInt_Disable;
|
||||
|
||||
bM4_OTS_CTL_TSSTP = pstcInit->enAutoOff;
|
||||
bM4_OTS_CTL_OTSCK = pstcInit->enClkSel;
|
||||
m_f32SlopeK = pstcInit->f32SlopeK;
|
||||
m_f32OffsetM = pstcInit->f32OffsetM;
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Deinitializes the TRNG.
|
||||
**
|
||||
** \param None.
|
||||
**
|
||||
** \retval None.
|
||||
**
|
||||
******************************************************************************/
|
||||
void OTS_DeInit(void)
|
||||
{
|
||||
/* Stop ots sampling. */
|
||||
bM4_OTS_CTL_OTSST = 0u;
|
||||
|
||||
/* Set the value of all registers to the reset value. */
|
||||
M4_OTS->CTL = 0u;
|
||||
M4_OTS->DR1 = 0u;
|
||||
M4_OTS->DR2 = 0u;
|
||||
M4_OTS->ECR = 0u;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get temperature via normal mode.
|
||||
**
|
||||
** \param [out] pf32Temp The address to store the temperature value.
|
||||
**
|
||||
** \param [in] u32Timeout Timeout value.
|
||||
**
|
||||
** \retval Ok No error occurred.
|
||||
** \retval ErrorTimeout OTS works timeout.
|
||||
** \retval ErrorInvalidParameter Parameter error.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
if (pf32Temp != NULL)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
|
||||
OTS_Start();
|
||||
do
|
||||
{
|
||||
if (bM4_OTS_CTL_OTSST == 0ul)
|
||||
{
|
||||
*pf32Temp = OTS_CalculateTemp();
|
||||
enRet = Ok;
|
||||
break;
|
||||
}
|
||||
} while (u32Timeout-- != 0ul);
|
||||
OTS_Stop();
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable OTS interrupt.
|
||||
**
|
||||
** \param [in] enState Enable or disable OTS interrupt.
|
||||
**
|
||||
** \retval None.
|
||||
**
|
||||
******************************************************************************/
|
||||
void OTS_IntCmd(en_functional_state_t enState)
|
||||
{
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enState));
|
||||
|
||||
bM4_OTS_CTL_OTSIE = (uint32_t)enState;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set OTS AOS trigger source.
|
||||
**
|
||||
** \param [in] enEvent See @ref en_event_src_t for details.
|
||||
**
|
||||
** \retval None.
|
||||
**
|
||||
******************************************************************************/
|
||||
void OTS_SetTriggerSrc(en_event_src_t enEvent)
|
||||
{
|
||||
uint32_t u32OtrTrg = M4_AOS->OTS_TRG;
|
||||
|
||||
DDL_ASSERT(IS_OTS_TRIG_SRC_EVENT(enEvent) && (EVT_OTS != enEvent));
|
||||
|
||||
u32OtrTrg &= ~0x1FFul;
|
||||
u32OtrTrg |= enEvent;
|
||||
|
||||
M4_AOS->OTS_TRG = u32OtrTrg;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable OTS common trigger.
|
||||
**
|
||||
** \param [in] enComTrigger OTS common trigger selection. See @ref en_ots_com_trigger_t for details.
|
||||
**
|
||||
** \param [in] enState Enable or disable the specified common trigger.
|
||||
**
|
||||
** \retval None.
|
||||
**
|
||||
******************************************************************************/
|
||||
void OTS_ComTriggerCmd(en_ots_com_trigger_t enComTrigger, en_functional_state_t enState)
|
||||
{
|
||||
uint32_t u32ComTrig = enComTrigger;
|
||||
|
||||
DDL_ASSERT(IS_OTS_COM_TRIGGER(enComTrigger));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enState));
|
||||
|
||||
u32ComTrig <<= 30u;
|
||||
|
||||
if (enState == Enable)
|
||||
{
|
||||
M4_AOS->OTS_TRG |= u32ComTrig;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_AOS->OTS_TRG &= ~u32ComTrig;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief OTS scaling experiment. If you want to get a more accurate temperature value,
|
||||
** you need to do a calibration experiment.
|
||||
**
|
||||
** \param [out] pu16Dr1 Address to store OTS data register 1.
|
||||
**
|
||||
** \param [out] pu16Dr2 Address to store OTS data register 2.
|
||||
**
|
||||
** \param [out] pu16Ecr Address to store OTS error compensation register.
|
||||
**
|
||||
** \param [out] pf32A Address to store parameter A(for calibration experiments).
|
||||
**
|
||||
** \param [in] u32Timeout Timeout value.
|
||||
**
|
||||
** \retval Ok No error occurred.
|
||||
** \retval ErrorTimeout OTS works timeout.
|
||||
** \retval ErrorInvalidParameter Parameter error.
|
||||
******************************************************************************/
|
||||
en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \
|
||||
uint16_t *pu16Ecr, float32_t *pf32A, \
|
||||
uint32_t u32Timeout)
|
||||
{
|
||||
float32_t f32Dr1;
|
||||
float32_t f32Dr2;
|
||||
float32_t f32Ecr;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
if ((NULL != pu16Dr1) && (NULL != pu16Dr2) && \
|
||||
(NULL != pu16Ecr) && (NULL != pf32A))
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
OTS_Start();
|
||||
do
|
||||
{
|
||||
if (bM4_OTS_CTL_OTSST == 0ul)
|
||||
{
|
||||
enRet = Ok;
|
||||
break;
|
||||
}
|
||||
} while (u32Timeout-- != 0ul);
|
||||
OTS_Stop();
|
||||
|
||||
if (enRet == Ok)
|
||||
{
|
||||
*pu16Dr1 = M4_OTS->DR1;
|
||||
*pu16Dr2 = M4_OTS->DR2;
|
||||
|
||||
f32Dr1 = (float32_t)(*pu16Dr1);
|
||||
f32Dr2 = (float32_t)(*pu16Dr2);
|
||||
|
||||
if (bM4_OTS_CTL_OTSCK == OtsClkSel_Hrc)
|
||||
{
|
||||
*pu16Ecr = M4_OTS->ECR;
|
||||
f32Ecr = (float32_t)(*pu16Ecr);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pu16Ecr = 1U;
|
||||
f32Ecr = 1.0f;
|
||||
}
|
||||
|
||||
if ((*pu16Dr1 != 0U) && (*pu16Dr2 != 0U) && (*pu16Ecr != 0U))
|
||||
{
|
||||
*pf32A = ((1.0f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Calculate the value of temperature.
|
||||
**
|
||||
** \retval A float32_t type value of temperature value.
|
||||
******************************************************************************/
|
||||
float OTS_CalculateTemp(void)
|
||||
{
|
||||
float32_t f32Ret = 0.0f;
|
||||
uint16_t u16Dr1 = M4_OTS->DR1;
|
||||
uint16_t u16Dr2 = M4_OTS->DR2;
|
||||
uint16_t u16Ecr = M4_OTS->ECR;
|
||||
float32_t f32Dr1 = (float32_t)u16Dr1;
|
||||
float32_t f32Dr2 = (float32_t)u16Dr2;
|
||||
float32_t f32Ecr = (float32_t)u16Ecr;
|
||||
|
||||
if (bM4_OTS_CTL_OTSCK == OtsClkSel_Xtal)
|
||||
{
|
||||
f32Ecr = 1.0f;
|
||||
}
|
||||
|
||||
if ((u16Dr1 != 0U) && (u16Dr2 != 0U) && (u16Ecr != 0U))
|
||||
{
|
||||
f32Ret = m_f32SlopeK * ((1.0f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr + m_f32OffsetM;
|
||||
}
|
||||
|
||||
return f32Ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
//@} // OtsGroup
|
||||
|
||||
#endif /* DDL_OTS_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,756 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_qspi.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link QspiGroup Queued SPI description @endlink
|
||||
**
|
||||
** - 2018-11-20 CDT First version for Device Driver Library of Qspi.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_qspi.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_QSPI_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup QspiGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*!< Parameter valid check for clock division */
|
||||
#define IS_VALID_CLK_DIV(x) \
|
||||
( ((x) == QspiHclkDiv2) || \
|
||||
(((x) >= QspiHclkDiv3) && ((x) <= QspiHclkDiv64)))
|
||||
|
||||
/*!< Parameter valid check for spi mode */
|
||||
#define IS_VALID_SPI_MODE(x) \
|
||||
( (QspiSpiMode0 == (x)) || \
|
||||
(QspiSpiMode3 == (x)))
|
||||
|
||||
/*!< Parameter valid check for bus communication mode */
|
||||
#define IS_VALID_BUS_COMM_MODE(x) \
|
||||
( (QspiBusModeRomAccess == (x)) || \
|
||||
(QspiBusModeDirectAccess == (x)))
|
||||
|
||||
/*!< Parameter valid check for prefetch stop location */
|
||||
#define IS_VALID_PREFETCH_STOP_LOCATION(x) \
|
||||
( (QspiPrefetchStopComplete == (x)) || \
|
||||
(QspiPrefetchStopImmediately == (x)))
|
||||
|
||||
/*!< Parameter valid check for receive data protocol */
|
||||
#define IS_VALID_RECE_DATA_PROTOCOL(x) \
|
||||
( (QspiProtocolExtendSpi == (x)) || \
|
||||
(QspiProtocolTwoWiresSpi == (x)) || \
|
||||
(QspiProtocolFourWiresSpi == (x)))
|
||||
|
||||
/*!< Parameter valid check for transmit address protocol */
|
||||
#define IS_VALID_TRANS_ADDR_PROTOCOL(x) \
|
||||
( (QspiProtocolExtendSpi == (x)) || \
|
||||
(QspiProtocolTwoWiresSpi == (x)) || \
|
||||
(QspiProtocolFourWiresSpi == (x)))
|
||||
|
||||
/*!< Parameter valid check for transmit instruction protocol */
|
||||
#define IS_VALID_TRANS_INSTRUCT_PROTOCOL(x) \
|
||||
( (QspiProtocolExtendSpi == (x)) || \
|
||||
(QspiProtocolTwoWiresSpi == (x)) || \
|
||||
(QspiProtocolFourWiresSpi == (x)))
|
||||
|
||||
/*!< Parameter valid check for serial interface read mode */
|
||||
#define IS_VALID_INTERFACE_READ_MODE(x) \
|
||||
( (QspiReadModeStandard == (x)) || \
|
||||
(QspiReadModeFast == (x)) || \
|
||||
(QspiReadModeTwoWiresOutput == (x)) || \
|
||||
(QspiReadModeTwoWiresIO == (x)) || \
|
||||
(QspiReadModeFourWiresOutput == (x)) || \
|
||||
(QspiReadModeFourWiresIO == (x)) || \
|
||||
(QspiReadModeCustomStandard == (x)) || \
|
||||
(QspiReadModeCustomFast == (x)))
|
||||
|
||||
/*!< Parameter valid check for QSSN valid extend delay time */
|
||||
#define IS_VALID_QSSN_VALID_EXTEND_TIME(x) \
|
||||
( (QspiQssnValidExtendNot == (x)) || \
|
||||
(QspiQssnValidExtendSck32 == (x)) || \
|
||||
(QspiQssnValidExtendSck128 == (x)) || \
|
||||
(QspiQssnValidExtendSckEver == (x)))
|
||||
|
||||
/*!< Parameter valid check for QSSN minimum interval time */
|
||||
#define IS_VALID_QSSN_INTERVAL_TIME(x) \
|
||||
( (QspiQssnIntervalQsck1 == (x)) || \
|
||||
(QspiQssnIntervalQsck2 == (x)) || \
|
||||
(QspiQssnIntervalQsck3 == (x)) || \
|
||||
(QspiQssnIntervalQsck4 == (x)) || \
|
||||
(QspiQssnIntervalQsck5 == (x)) || \
|
||||
(QspiQssnIntervalQsck6 == (x)) || \
|
||||
(QspiQssnIntervalQsck7 == (x)) || \
|
||||
(QspiQssnIntervalQsck8 == (x)) || \
|
||||
(QspiQssnIntervalQsck9 == (x)) || \
|
||||
(QspiQssnIntervalQsck10 == (x)) || \
|
||||
(QspiQssnIntervalQsck11 == (x)) || \
|
||||
(QspiQssnIntervalQsck12 == (x)) || \
|
||||
(QspiQssnIntervalQsck13 == (x)) || \
|
||||
(QspiQssnIntervalQsck14 == (x)) || \
|
||||
(QspiQssnIntervalQsck15 == (x)) || \
|
||||
(QspiQssnIntervalQsck16 <= (x)))
|
||||
|
||||
/*!< Parameter valid check for QSCK duty correction */
|
||||
#define IS_VALID_QSCK_DUTY_CORR(x) \
|
||||
( (QspiQsckDutyCorrNot == (x)) || \
|
||||
(QspiQsckDutyCorrHalfHclk == (x)))
|
||||
|
||||
/*!< Parameter valid check for virtual cycles */
|
||||
#define IS_VALID_VIRTUAL_CYCLES(x) \
|
||||
( (QspiVirtualPeriodQsck3 == (x)) || \
|
||||
(QspiVirtualPeriodQsck4 == (x)) || \
|
||||
(QspiVirtualPeriodQsck5 == (x)) || \
|
||||
(QspiVirtualPeriodQsck6 == (x)) || \
|
||||
(QspiVirtualPeriodQsck7 == (x)) || \
|
||||
(QspiVirtualPeriodQsck8 == (x)) || \
|
||||
(QspiVirtualPeriodQsck9 == (x)) || \
|
||||
(QspiVirtualPeriodQsck10 == (x)) || \
|
||||
(QspiVirtualPeriodQsck11 == (x)) || \
|
||||
(QspiVirtualPeriodQsck12 == (x)) || \
|
||||
(QspiVirtualPeriodQsck13 == (x)) || \
|
||||
(QspiVirtualPeriodQsck14 == (x)) || \
|
||||
(QspiVirtualPeriodQsck15 == (x)) || \
|
||||
(QspiVirtualPeriodQsck16 == (x)) || \
|
||||
(QspiVirtualPeriodQsck17 == (x)) || \
|
||||
(QspiVirtualPeriodQsck18 == (x)))
|
||||
|
||||
/*!< Parameter valid check for WP pin output level */
|
||||
#define IS_VALID_WP_OUTPUT_LEVEL(x) \
|
||||
( (QspiWpPinOutputLow == (x)) || \
|
||||
(QspiWpPinOutputHigh == (x)))
|
||||
|
||||
/*!< Parameter valid check for QSSN setup delay time */
|
||||
#define IS_VALID_QSSN_SETUP_DELAY(x) \
|
||||
( (QspiQssnSetupDelayHalfQsck == (x)) || \
|
||||
(QspiQssnSetupDelay1Dot5Qsck == (x)))
|
||||
|
||||
/*!< Parameter valid check for QSSN hold delay time */
|
||||
#define IS_VALID_QSSN_HOLD_TIME(x) \
|
||||
( (QspiQssnHoldDelayHalfQsck == (x)) || \
|
||||
(QspiQssnHoldDelay1Dot5Qsck == (x)))
|
||||
|
||||
/*!< Parameter valid check for interface address width */
|
||||
#define IS_VALID_INTERFACE_ADDR_WIDTH(x) \
|
||||
( (QspiAddressByteOne == (x)) || \
|
||||
(QspiAddressByteTwo == (x)) || \
|
||||
(QspiAddressByteThree == (x)) || \
|
||||
(QspiAddressByteFour == (x)))
|
||||
|
||||
/*!< Parameter valid check for extend address */
|
||||
#define IS_VALID_SET_EXTEND_ADDR(x) ((x) <= 0x3Fu)
|
||||
|
||||
/*!< Parameter valid check for get flag type */
|
||||
#define IS_VALID_GET_FLAG_TYPE(x) \
|
||||
( (QspiFlagBusBusy == (x)) || \
|
||||
(QspiFlagXipMode == (x)) || \
|
||||
(QspiFlagRomAccessError == (x)) || \
|
||||
(QspiFlagPrefetchBufferFull == (x)) || \
|
||||
(QspiFlagPrefetchStop == (x)))
|
||||
|
||||
/*!< Parameter valid check for clear flag type */
|
||||
#define IS_VALID_CLEAR_FLAG_TYPE(x) (QspiFlagRomAccessError == (x))
|
||||
|
||||
/*!< QSPI registers reset value */
|
||||
#define QSPI_REG_CR_RESET_VALUE (0x003F0000ul)
|
||||
#define QSPI_REG_CSCR_RESET_VALUE (0x0000000Ful)
|
||||
#define QSPI_REG_FCR_RESET_VALUE (0x000080B3ul)
|
||||
#define QSPI_REG_SR_RESET_VALUE (0x00008000ul)
|
||||
#define QSPI_REG_CCMD_RESET_VALUE (0x00000000ul)
|
||||
#define QSPI_REG_XCMD_RESET_VALUE (0x000000FFul)
|
||||
#define QSPI_REG_EXAR_RESET_VALUE (0x00000000ul)
|
||||
#define QSPI_REG_SR2_RESET_VALUE (0x00000000ul)
|
||||
#define QSPI_REG_DCOM_RESET_VALUE (0x00000000ul)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-Initialize QSPI unit
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_DeInit(void)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
M4_QSPI->CR = QSPI_REG_CR_RESET_VALUE;
|
||||
if (1u == M4_QSPI->SR_f.RAER)
|
||||
{
|
||||
M4_QSPI->SR2_f.RAERCLR = 1u;
|
||||
}
|
||||
M4_QSPI->CSCR = QSPI_REG_CSCR_RESET_VALUE;
|
||||
M4_QSPI->FCR = QSPI_REG_FCR_RESET_VALUE;
|
||||
M4_QSPI->EXAR = QSPI_REG_EXAR_RESET_VALUE;
|
||||
M4_QSPI->SR = QSPI_REG_SR_RESET_VALUE;
|
||||
M4_QSPI->CCMD = QSPI_REG_CCMD_RESET_VALUE;
|
||||
M4_QSPI->XCMD = QSPI_REG_XCMD_RESET_VALUE;
|
||||
M4_QSPI->DCOM = QSPI_REG_DCOM_RESET_VALUE;
|
||||
M4_QSPI->SR2 = QSPI_REG_SR2_RESET_VALUE;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Initialize QSPI unit
|
||||
**
|
||||
** \param [in] pstcQspiInitCfg Pointer to qspi configuration
|
||||
** \arg See the struct #stc_qspi_init_t
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval Error Parameter error
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_Init(const stc_qspi_init_t *pstcQspiInitCfg)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
if (NULL == pstcQspiInitCfg)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_CLK_DIV(pstcQspiInitCfg->enClkDiv));
|
||||
DDL_ASSERT(IS_VALID_SPI_MODE(pstcQspiInitCfg->enSpiMode));
|
||||
DDL_ASSERT(IS_VALID_BUS_COMM_MODE(pstcQspiInitCfg->enBusCommMode));
|
||||
DDL_ASSERT(IS_VALID_PREFETCH_STOP_LOCATION(pstcQspiInitCfg->enPrefetchMode));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcQspiInitCfg->enPrefetchFuncEn));
|
||||
DDL_ASSERT(IS_VALID_RECE_DATA_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enReceProtocol));
|
||||
DDL_ASSERT(IS_VALID_TRANS_ADDR_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enTransAddrProtocol));
|
||||
DDL_ASSERT(IS_VALID_TRANS_INSTRUCT_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enTransInstrProtocol));
|
||||
DDL_ASSERT(IS_VALID_INTERFACE_READ_MODE(pstcQspiInitCfg->stcCommProtocol.enReadMode));
|
||||
DDL_ASSERT(IS_VALID_QSSN_VALID_EXTEND_TIME(pstcQspiInitCfg->enQssnValidExtendTime));
|
||||
DDL_ASSERT(IS_VALID_QSSN_INTERVAL_TIME(pstcQspiInitCfg->enQssnIntervalTime));
|
||||
DDL_ASSERT(IS_VALID_QSCK_DUTY_CORR(pstcQspiInitCfg->enQsckDutyCorr));
|
||||
DDL_ASSERT(IS_VALID_VIRTUAL_CYCLES(pstcQspiInitCfg->enVirtualPeriod));
|
||||
DDL_ASSERT(IS_VALID_WP_OUTPUT_LEVEL(pstcQspiInitCfg->enWpPinLevel));
|
||||
DDL_ASSERT(IS_VALID_QSSN_SETUP_DELAY(pstcQspiInitCfg->enQssnSetupDelayTime));
|
||||
DDL_ASSERT(IS_VALID_QSSN_HOLD_TIME(pstcQspiInitCfg->enQssnHoldDelayTime));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcQspiInitCfg->enFourByteAddrReadEn));
|
||||
DDL_ASSERT(IS_VALID_INTERFACE_ADDR_WIDTH(pstcQspiInitCfg->enAddrWidth));
|
||||
|
||||
/* Configure control register */
|
||||
M4_QSPI->CR_f.DIV = pstcQspiInitCfg->enClkDiv;
|
||||
M4_QSPI->CR_f.SPIMD3 = pstcQspiInitCfg->enSpiMode;
|
||||
M4_QSPI->CR_f.PFE = pstcQspiInitCfg->enPrefetchFuncEn;
|
||||
M4_QSPI->CR_f.PFSAE = pstcQspiInitCfg->enPrefetchMode;
|
||||
M4_QSPI->CR_f.MDSEL = pstcQspiInitCfg->stcCommProtocol.enReadMode;
|
||||
|
||||
/* Custom read mode */
|
||||
if ((QspiReadModeCustomFast == pstcQspiInitCfg->stcCommProtocol.enReadMode) ||
|
||||
(QspiReadModeCustomStandard == pstcQspiInitCfg->stcCommProtocol.enReadMode))
|
||||
{
|
||||
M4_QSPI->CR_f.IPRSL = pstcQspiInitCfg->stcCommProtocol.enTransInstrProtocol;
|
||||
M4_QSPI->CR_f.APRSL = pstcQspiInitCfg->stcCommProtocol.enTransAddrProtocol;
|
||||
M4_QSPI->CR_f.DPRSL = pstcQspiInitCfg->stcCommProtocol.enReceProtocol;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_QSPI->CR_f.IPRSL = QspiProtocolExtendSpi;
|
||||
M4_QSPI->CR_f.APRSL = QspiProtocolExtendSpi;
|
||||
M4_QSPI->CR_f.DPRSL = QspiProtocolExtendSpi;
|
||||
}
|
||||
|
||||
/* Configure chip select control register */
|
||||
M4_QSPI->CSCR_f.SSNW = pstcQspiInitCfg->enQssnValidExtendTime;
|
||||
M4_QSPI->CSCR_f.SSHW = pstcQspiInitCfg->enQssnIntervalTime;
|
||||
|
||||
/* Configure format control register */
|
||||
if (((pstcQspiInitCfg->enClkDiv % 2) != 0) &&
|
||||
(pstcQspiInitCfg->enQsckDutyCorr != QspiQsckDutyCorrNot))
|
||||
{
|
||||
M4_QSPI->FCR_f.DUTY = QspiQsckDutyCorrNot;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_QSPI->FCR_f.DUTY = pstcQspiInitCfg->enQsckDutyCorr;
|
||||
}
|
||||
M4_QSPI->FCR_f.DMCYCN = pstcQspiInitCfg->enVirtualPeriod;
|
||||
M4_QSPI->FCR_f.WPOL = pstcQspiInitCfg->enWpPinLevel;
|
||||
M4_QSPI->FCR_f.SSNLD = pstcQspiInitCfg->enQssnSetupDelayTime;
|
||||
M4_QSPI->FCR_f.SSNHD = pstcQspiInitCfg->enQssnHoldDelayTime;
|
||||
M4_QSPI->FCR_f.FOUR_BIC = pstcQspiInitCfg->enFourByteAddrReadEn;
|
||||
M4_QSPI->FCR_f.AWSL = pstcQspiInitCfg->enAddrWidth;
|
||||
M4_QSPI->CR_f.DCOME = pstcQspiInitCfg->enBusCommMode;
|
||||
|
||||
/* Configure ROM access instruction */
|
||||
M4_QSPI->CCMD = pstcQspiInitCfg->u8RomAccessInstr;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Config communication protocol structure
|
||||
**
|
||||
** \param [in] pstcCommProtocol Pointer to qspi communication protocol configuration
|
||||
** \arg See the struct #stc_qspi_comm_protocol_t
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval Error Parameter error
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_CommProtocolConfig(const stc_qspi_comm_protocol_t *pstcCommProtocol)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
if (NULL == pstcCommProtocol)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
else
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_RECE_DATA_PROTOCOL(pstcCommProtocol->enReceProtocol));
|
||||
DDL_ASSERT(IS_VALID_TRANS_ADDR_PROTOCOL(pstcCommProtocol->enTransAddrProtocol));
|
||||
DDL_ASSERT(IS_VALID_TRANS_INSTRUCT_PROTOCOL(pstcCommProtocol->enTransInstrProtocol));
|
||||
DDL_ASSERT(IS_VALID_INTERFACE_READ_MODE(pstcCommProtocol->enReadMode));
|
||||
|
||||
M4_QSPI->CR_f.MDSEL = pstcCommProtocol->enReadMode;
|
||||
/* Custom read mode */
|
||||
if ((QspiReadModeCustomFast == pstcCommProtocol->enReadMode) ||
|
||||
(QspiReadModeCustomStandard == pstcCommProtocol->enReadMode))
|
||||
{
|
||||
M4_QSPI->CR_f.IPRSL = pstcCommProtocol->enTransInstrProtocol;
|
||||
M4_QSPI->CR_f.APRSL = pstcCommProtocol->enTransAddrProtocol;
|
||||
M4_QSPI->CR_f.DPRSL = pstcCommProtocol->enReceProtocol;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_QSPI->CR_f.IPRSL = QspiProtocolExtendSpi;
|
||||
M4_QSPI->CR_f.APRSL = QspiProtocolExtendSpi;
|
||||
M4_QSPI->CR_f.DPRSL = QspiProtocolExtendSpi;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable prefetch function
|
||||
**
|
||||
** \param [in] enNewSta The function new state
|
||||
** \arg Disable Disable prefetch function
|
||||
** \arg Enable Enable prefetch function
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_PrefetchCmd(en_functional_state_t enNewSta)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta));
|
||||
|
||||
M4_QSPI->CR_f.PFE = enNewSta;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set clock division
|
||||
**
|
||||
** \param [in] enClkDiv Clock division
|
||||
** \arg QspiHclkDiv2 Clock source: HCLK/2
|
||||
** \arg QspiHclkDiv3 Clock source: HCLK/3
|
||||
** \arg QspiHclkDiv4 Clock source: HCLK/4
|
||||
** \arg QspiHclkDiv5 Clock source: HCLK/5
|
||||
** \arg QspiHclkDiv6 Clock source: HCLK/6
|
||||
** \arg QspiHclkDiv7 Clock source: HCLK/7
|
||||
** \arg QspiHclkDiv8 Clock source: HCLK/8
|
||||
** \arg QspiHclkDiv9 Clock source: HCLK/9
|
||||
** \arg QspiHclkDiv10 Clock source: HCLK/10
|
||||
** \arg QspiHclkDiv11 Clock source: HCLK/11
|
||||
** \arg QspiHclkDiv12 Clock source: HCLK/12
|
||||
** \arg QspiHclkDiv13 Clock source: HCLK/13
|
||||
** \arg QspiHclkDiv14 Clock source: HCLK/14
|
||||
** \arg QspiHclkDiv15 Clock source: HCLK/15
|
||||
** \arg QspiHclkDiv16 Clock source: HCLK/16
|
||||
** \arg QspiHclkDiv17 Clock source: HCLK/17
|
||||
** \arg QspiHclkDiv18 Clock source: HCLK/18
|
||||
** \arg QspiHclkDiv19 Clock source: HCLK/19
|
||||
** \arg QspiHclkDiv20 Clock source: HCLK/20
|
||||
** \arg QspiHclkDiv21 Clock source: HCLK/21
|
||||
** \arg QspiHclkDiv22 Clock source: HCLK/22
|
||||
** \arg QspiHclkDiv23 Clock source: HCLK/23
|
||||
** \arg QspiHclkDiv24 Clock source: HCLK/24
|
||||
** \arg QspiHclkDiv25 Clock source: HCLK/25
|
||||
** \arg QspiHclkDiv26 Clock source: HCLK/26
|
||||
** \arg QspiHclkDiv27 Clock source: HCLK/27
|
||||
** \arg QspiHclkDiv28 Clock source: HCLK/28
|
||||
** \arg QspiHclkDiv29 Clock source: HCLK/29
|
||||
** \arg QspiHclkDiv30 Clock source: HCLK/30
|
||||
** \arg QspiHclkDiv31 Clock source: HCLK/31
|
||||
** \arg QspiHclkDiv32 Clock source: HCLK/32
|
||||
** \arg QspiHclkDiv33 Clock source: HCLK/33
|
||||
** \arg QspiHclkDiv34 Clock source: HCLK/34
|
||||
** \arg QspiHclkDiv35 Clock source: HCLK/35
|
||||
** \arg QspiHclkDiv36 Clock source: HCLK/36
|
||||
** \arg QspiHclkDiv37 Clock source: HCLK/37
|
||||
** \arg QspiHclkDiv38 Clock source: HCLK/38
|
||||
** \arg QspiHclkDiv39 Clock source: HCLK/39
|
||||
** \arg QspiHclkDiv40 Clock source: HCLK/40
|
||||
** \arg QspiHclkDiv41 Clock source: HCLK/41
|
||||
** \arg QspiHclkDiv42 Clock source: HCLK/42
|
||||
** \arg QspiHclkDiv43 Clock source: HCLK/43
|
||||
** \arg QspiHclkDiv44 Clock source: HCLK/44
|
||||
** \arg QspiHclkDiv45 Clock source: HCLK/45
|
||||
** \arg QspiHclkDiv46 Clock source: HCLK/46
|
||||
** \arg QspiHclkDiv47 Clock source: HCLK/47
|
||||
** \arg QspiHclkDiv48 Clock source: HCLK/48
|
||||
** \arg QspiHclkDiv49 Clock source: HCLK/49
|
||||
** \arg QspiHclkDiv50 Clock source: HCLK/50
|
||||
** \arg QspiHclkDiv51 Clock source: HCLK/51
|
||||
** \arg QspiHclkDiv52 Clock source: HCLK/52
|
||||
** \arg QspiHclkDiv53 Clock source: HCLK/53
|
||||
** \arg QspiHclkDiv54 Clock source: HCLK/54
|
||||
** \arg QspiHclkDiv55 Clock source: HCLK/55
|
||||
** \arg QspiHclkDiv56 Clock source: HCLK/56
|
||||
** \arg QspiHclkDiv57 Clock source: HCLK/57
|
||||
** \arg QspiHclkDiv58 Clock source: HCLK/58
|
||||
** \arg QspiHclkDiv59 Clock source: HCLK/59
|
||||
** \arg QspiHclkDiv60 Clock source: HCLK/60
|
||||
** \arg QspiHclkDiv61 Clock source: HCLK/61
|
||||
** \arg QspiHclkDiv62 Clock source: HCLK/62
|
||||
** \arg QspiHclkDiv63 Clock source: HCLK/63
|
||||
** \arg QspiHclkDiv64 Clock source: HCLK/64
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_SetClockDiv(en_qspi_clk_div_t enClkDiv)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
DDL_ASSERT(IS_VALID_CLK_DIV(enClkDiv));
|
||||
|
||||
M4_QSPI->CR_f.DIV = enClkDiv;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set WP Pin level
|
||||
**
|
||||
** \param [in] enWpLevel WP pin level
|
||||
** \arg QspiWpPinOutputLow WP pin(QIO2) output low level
|
||||
** \arg QspiWpPinOutputHigh WP pin(QIO2) output high level
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_SetWPPinLevel(en_qspi_wp_pin_level_t enWpLevel)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
DDL_ASSERT(IS_VALID_WP_OUTPUT_LEVEL(enWpLevel));
|
||||
|
||||
M4_QSPI->FCR_f.WPOL = enWpLevel;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set communication address width
|
||||
**
|
||||
** \param [in] enAddrWidth Communication address width
|
||||
** \arg QspiAddressByteOne One byte address
|
||||
** \arg QspiAddressByteTwo Two byte address
|
||||
** \arg QspiAddressByteThree Three byte address
|
||||
** \arg QspiAddressByteFour Four byte address
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_SetAddrWidth(en_qspi_addr_width_t enAddrWidth)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
DDL_ASSERT(IS_VALID_INTERFACE_ADDR_WIDTH(enAddrWidth));
|
||||
|
||||
M4_QSPI->FCR_f.AWSL = enAddrWidth;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set extend address value
|
||||
**
|
||||
** \param [in] u8Addr Extend address value
|
||||
** \arg 0~0x3F
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_SetExtendAddress(uint8_t u8Addr)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
DDL_ASSERT(IS_VALID_SET_EXTEND_ADDR(u8Addr));
|
||||
|
||||
M4_QSPI->EXAR_f.EXADR = u8Addr;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set rom access instruction
|
||||
**
|
||||
** \param [in] u8Instr Rom access instruction
|
||||
** \arg 0~0xFF
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_SetRomAccessInstruct(uint8_t u8Instr)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
M4_QSPI->CCMD = u8Instr;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Write direct communication value
|
||||
**
|
||||
** \param [in] u8Val Direct communication value
|
||||
** \arg 0~0xFF
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_WriteDirectCommValue(uint8_t u8Val)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
M4_QSPI->DCOM = u8Val;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Read direct communication value
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval uint8_t Direct communication read value
|
||||
**
|
||||
******************************************************************************/
|
||||
uint8_t QSPI_ReadDirectCommValue(void)
|
||||
{
|
||||
return ((uint8_t)M4_QSPI->DCOM);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable xip mode
|
||||
**
|
||||
** \param [in] u8Instr Enable or disable xip mode instruction
|
||||
** \arg 0~0xFF
|
||||
**
|
||||
** \param [in] enNewSta The function new state
|
||||
** \arg Disable Disable xip mode
|
||||
** \arg Enable Enable xip mode
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_XipModeCmd(uint8_t u8Instr, en_functional_state_t enNewSta)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta));
|
||||
|
||||
M4_QSPI->XCMD = u8Instr;
|
||||
if (Enable == enNewSta)
|
||||
{
|
||||
M4_QSPI->CR_f.XIPE = 1u;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_QSPI->CR_f.XIPE = 0u;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enter direct communication mode
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
** \note If you are in XIP mode, you need to exit XIP mode and then start direct communication mode.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_EnterDirectCommMode(void)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
M4_QSPI->CR_f.DCOME = 1u;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Exit direct communication mode
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_ExitDirectCommMode(void)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
M4_QSPI->CR_f.DCOME = 0u;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get prefetch buffer current byte number
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval uint8_t Current buffer byte number
|
||||
**
|
||||
******************************************************************************/
|
||||
uint8_t QSPI_GetPrefetchBufferNum(void)
|
||||
{
|
||||
return ((uint8_t)M4_QSPI->SR_f.PFNUM);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get flag status
|
||||
**
|
||||
** \param [in] enFlag Choose need get status's flag
|
||||
** \arg QspiFlagBusBusy QSPI bus work status flag in direct communication mode
|
||||
** \arg QspiFlagXipMode XIP mode status signal
|
||||
** \arg QspiFlagRomAccessError Trigger rom access error flag in direct communication mode
|
||||
** \arg QspiFlagPrefetchBufferFull Prefetch buffer area status signal
|
||||
** \arg QspiFlagPrefetchStop Prefetch action status signal
|
||||
**
|
||||
** \retval Set Flag is set
|
||||
** \retval Reset Flag is reset
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t QSPI_GetFlag(en_qspi_flag_type_t enFlag)
|
||||
{
|
||||
en_flag_status_t enFlagSta = Reset;
|
||||
|
||||
DDL_ASSERT(IS_VALID_GET_FLAG_TYPE(enFlag));
|
||||
|
||||
switch (enFlag)
|
||||
{
|
||||
case QspiFlagBusBusy:
|
||||
enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.BUSY;
|
||||
break;
|
||||
case QspiFlagXipMode:
|
||||
enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.XIPF;
|
||||
break;
|
||||
case QspiFlagRomAccessError:
|
||||
enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.RAER;
|
||||
break;
|
||||
case QspiFlagPrefetchBufferFull:
|
||||
enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.PFFUL;
|
||||
break;
|
||||
case QspiFlagPrefetchStop:
|
||||
enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.PFAN;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return enFlagSta;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear flag status
|
||||
**
|
||||
** \param [in] enFlag Choose need get status's flag
|
||||
** \arg QspiFlagRomAccessError Trigger rom access error flag in direct communication mode
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval ErrorInvalidParameter Parameter error
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t QSPI_ClearFlag(en_qspi_flag_type_t enFlag)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
if (QspiFlagRomAccessError == enFlag)
|
||||
{
|
||||
M4_QSPI->SR2_f.RAERCLR = 1u;
|
||||
}
|
||||
else
|
||||
{
|
||||
enRet = ErrorInvalidParameter;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
//@} // QspiGroup
|
||||
|
||||
#endif /* DDL_QSPI_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,143 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_rmu.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link RmuGroup RMU description @endlink
|
||||
**
|
||||
** - 2018-10-28 CDT First version for Device Driver Library of RMU.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_rmu.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_RMU_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup RmuGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
#define ENABLE_RMU_REG_WRITE() (M4_SYSREG->PWR_FPRC = 0xa502u)
|
||||
#define DISABLE_RMU_REG_WRITE() (M4_SYSREG->PWR_FPRC = 0xa500u)
|
||||
|
||||
#define RMU_FLAG_TIM ((uint16_t)0x1000u)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the chip reset cause.
|
||||
**
|
||||
** \param [in] pstcData Pointer to return reset cause structure.
|
||||
**
|
||||
** \retval Ok Get successfully.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RMU_GetResetCause(stc_rmu_rstcause_t *pstcData)
|
||||
{
|
||||
uint16_t u16RstCause = 0u;
|
||||
stc_sysreg_rmu_rstf0_field_t *RMU_RSTF0_f = NULL;
|
||||
|
||||
if(NULL == pstcData)
|
||||
{
|
||||
return ErrorInvalidParameter;
|
||||
}
|
||||
|
||||
u16RstCause = M4_SYSREG->RMU_RSTF0;
|
||||
RMU_RSTF0_f = (stc_sysreg_rmu_rstf0_field_t *)(&u16RstCause);
|
||||
|
||||
pstcData->enMultiRst = (en_flag_status_t)(RMU_RSTF0_f->MULTIRF == 1u);
|
||||
pstcData->enXtalErr = (en_flag_status_t)(RMU_RSTF0_f->XTALERF == 1u);
|
||||
pstcData->enClkFreqErr = (en_flag_status_t)(RMU_RSTF0_f->CKFERF == 1u);
|
||||
pstcData->enRamEcc = (en_flag_status_t)(RMU_RSTF0_f->RAECRF == 1u);
|
||||
pstcData->enRamParityErr = (en_flag_status_t)(RMU_RSTF0_f->RAPERF == 1u);
|
||||
pstcData->enMpuErr = (en_flag_status_t)(RMU_RSTF0_f->MPUERF == 1u);
|
||||
pstcData->enSoftware = (en_flag_status_t)(RMU_RSTF0_f->SWRF == 1u);
|
||||
pstcData->enPowerDown = (en_flag_status_t)(RMU_RSTF0_f->PDRF == 1u);
|
||||
pstcData->enSwdt = (en_flag_status_t)(RMU_RSTF0_f->SWDRF == 1u);
|
||||
pstcData->enWdt = (en_flag_status_t)(RMU_RSTF0_f->WDRF == 1u);
|
||||
pstcData->enPvd2 = (en_flag_status_t)(RMU_RSTF0_f->PVD2RF == 1u);
|
||||
pstcData->enPvd1 = (en_flag_status_t)(RMU_RSTF0_f->PVD2RF == 1u);
|
||||
pstcData->enBrownOut = (en_flag_status_t)(RMU_RSTF0_f->BORF == 1u);
|
||||
pstcData->enRstPin = (en_flag_status_t)(RMU_RSTF0_f->PINRF == 1u);
|
||||
pstcData->enPowerOn = (en_flag_status_t)(RMU_RSTF0_f->PORF == 1u);
|
||||
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear the reset flag.
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok Clear successfully.
|
||||
**
|
||||
** \note clear reset flag should be done after read RMU_RSTF0 register.
|
||||
******************************************************************************/
|
||||
en_result_t RMU_ClrResetFlag(void)
|
||||
{
|
||||
uint16_t u16status = 0u;
|
||||
uint32_t u32timeout = 0u;
|
||||
|
||||
ENABLE_RMU_REG_WRITE();
|
||||
|
||||
do
|
||||
{
|
||||
u32timeout++;
|
||||
M4_SYSREG->RMU_RSTF0_f.CLRF = 1u;
|
||||
u16status = M4_SYSREG->RMU_RSTF0;
|
||||
}while((u32timeout != RMU_FLAG_TIM) && u16status);
|
||||
|
||||
DISABLE_RMU_REG_WRITE();
|
||||
|
||||
if(u32timeout >= RMU_FLAG_TIM)
|
||||
{
|
||||
return ErrorTimeout;
|
||||
}
|
||||
|
||||
return Ok;
|
||||
}
|
||||
|
||||
|
||||
//@} // RmuGroup
|
||||
|
||||
#endif /* DDL_RMU_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
||||
@@ -0,0 +1,978 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_rtc.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link RtcGroup Real-Time Clock description @endlink
|
||||
**
|
||||
** - 2018-11-22 CDT First version for Device Driver Library of RTC.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_rtc.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_RTC_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup RtcGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*!< Parameter valid check for clock source type */
|
||||
#define IS_VALID_CLK_SOURCE_TYPE(x) \
|
||||
( (RtcClkXtal32 == (x)) || \
|
||||
(RtcClkLrc == (x)))
|
||||
|
||||
/*!< Parameter valid check for period interrupt condition */
|
||||
#define IS_VALID_PERIOD_INT_CONDITION(x) \
|
||||
( (RtcPeriodIntInvalid == (x)) || \
|
||||
(RtcPeriodIntHalfSec == (x)) || \
|
||||
(RtcPeriodIntOneSec == (x)) || \
|
||||
(RtcPeriodIntOneMin == (x)) || \
|
||||
(RtcPeriodIntOneHour == (x)) || \
|
||||
(RtcPeriodIntOneDay == (x)) || \
|
||||
(RtcPeriodIntOneMon == (x)))
|
||||
|
||||
/*!< Parameter valid check for time format */
|
||||
#define IS_VALID_TIME_FORMAT(x) \
|
||||
( (RtcTimeFormat12Hour == (x)) || \
|
||||
(RtcTimeFormat24Hour == (x)))
|
||||
|
||||
/*!< Parameter valid check for compensation way */
|
||||
#define IS_VALID_COMPEN_WAY(x) \
|
||||
( (RtcOutputCompenDistributed == (x)) || \
|
||||
(RtcOutputCompenUniform == (x)))
|
||||
|
||||
/*!< Parameter valid check for compensation value range */
|
||||
#define IS_VALID_COMPEN_VALUE_RANGE(x) ((x) <= 0x1FFu)
|
||||
|
||||
/*!< Parameter valid check for data format */
|
||||
#define IS_VALID_DATA_FORMAT(x) \
|
||||
( (RtcDataFormatDec == (x)) || \
|
||||
(RtcDataFormatBcd == (x)))
|
||||
|
||||
/*!< Parameter valid check for time second */
|
||||
#define IS_VALID_TIME_SECOND(x) ((x) <= 59u)
|
||||
|
||||
/*!< Parameter valid check for time minute */
|
||||
#define IS_VALID_TIME_MINUTE(x) ((x) <= 59u)
|
||||
|
||||
/*!< Parameter valid check for time hour */
|
||||
#define IS_VALID_TIME_HOUR12(x) (((x) >= 1u) && ((x) <= 12u))
|
||||
#define IS_VALID_TIME_HOUR24(x) ((x) <= 23u)
|
||||
|
||||
/*!< Parameter valid check for date weekday */
|
||||
#define IS_VALID_DATE_WEEKDAY(x) ((x) <= 6u)
|
||||
|
||||
/*!< Parameter valid check for date day */
|
||||
#define IS_VALID_DATE_DAY(x) (((x) >= 1u) && ((x) <= 31u))
|
||||
|
||||
/*!< Parameter valid check for date month */
|
||||
#define IS_VALID_DATE_MONTH(x) (((x) >= 1u) && ((x) <= 12u))
|
||||
|
||||
/*!< Parameter valid check for date year */
|
||||
#define IS_VALID_DATE_YEAR(x) ((x) <= 99u)
|
||||
|
||||
/*!< Parameter valid check for hour12 am/pm */
|
||||
#define IS_VALID_HOUR12_AMPM(x) \
|
||||
( (RtcHour12Am == (x)) || \
|
||||
(RtcHour12Pm == (x)))
|
||||
|
||||
/*!< Parameter valid check for alarm weekday */
|
||||
#define IS_VALID_ALARM_WEEKDAY(x) (((x) >= 1u) && ((x) <= 0x7Fu))
|
||||
|
||||
/*!< Parameter valid check for interrupt request type */
|
||||
#define IS_VALID_IRQ_TYPE(x) \
|
||||
( (RtcIrqPeriod == (x)) || \
|
||||
(RtcIrqAlarm == (x)))
|
||||
|
||||
/*!< 12 hour format am/pm status bit */
|
||||
#define RTC_HOUR12_AMPM_MASK (0x20u)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-Initialize RTC
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval ErrorTimeout De-Initialize timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_DeInit(void)
|
||||
{
|
||||
uint8_t u8RegSta;
|
||||
uint32_t u32Timeout, u32TimeCnt = 0u;
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
M4_RTC->CR0_f.RESET = 0u;
|
||||
/* Waiting for normal count status or end of RTC software reset */
|
||||
u32Timeout = SystemCoreClock >> 8u;
|
||||
do
|
||||
{
|
||||
u8RegSta = (uint8_t)M4_RTC->CR0_f.RESET;
|
||||
u32TimeCnt++;
|
||||
} while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u));
|
||||
|
||||
if (1u == u8RegSta)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialize all RTC registers */
|
||||
M4_RTC->CR0_f.RESET = 1u;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Initialize RTC
|
||||
**
|
||||
** \param [in] pstcRtcInit Pointer to RTC init configuration
|
||||
** \arg See the struct #stc_rtc_init_t
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval Error Parameter error
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
if (NULL == pstcRtcInit)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_CLK_SOURCE_TYPE(pstcRtcInit->enClkSource));
|
||||
DDL_ASSERT(IS_VALID_PERIOD_INT_CONDITION(pstcRtcInit->enPeriodInt));
|
||||
DDL_ASSERT(IS_VALID_TIME_FORMAT(pstcRtcInit->enTimeFormat));
|
||||
DDL_ASSERT(IS_VALID_COMPEN_WAY(pstcRtcInit->enCompenWay));
|
||||
DDL_ASSERT(IS_VALID_COMPEN_VALUE_RANGE(pstcRtcInit->u16CompenVal));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcRtcInit->enCompenEn));
|
||||
|
||||
/* Configure clock */
|
||||
if (RtcClkLrc == pstcRtcInit->enClkSource)
|
||||
{
|
||||
M4_RTC->CR3_f.LRCEN = 1u;
|
||||
}
|
||||
M4_RTC->CR3_f.RCKSEL = pstcRtcInit->enClkSource;
|
||||
|
||||
/* Configure control register */
|
||||
M4_RTC->CR1_f.PRDS = pstcRtcInit->enPeriodInt;
|
||||
M4_RTC->CR1_f.AMPM = pstcRtcInit->enTimeFormat;
|
||||
M4_RTC->CR1_f.ONEHZSEL = pstcRtcInit->enCompenWay;
|
||||
|
||||
/* Configure clock error compensation register */
|
||||
M4_RTC->ERRCRH_f.COMP8 = ((uint32_t)pstcRtcInit->u16CompenVal >> 8u) & 0x01u;
|
||||
M4_RTC->ERRCRL = (uint32_t)pstcRtcInit->u16CompenVal & 0x00FFu;
|
||||
M4_RTC->ERRCRH_f.COMPEN = pstcRtcInit->enCompenEn;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enter RTC read/write mode
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval ErrorTimeout Enter mode timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_EnterRwMode(void)
|
||||
{
|
||||
uint8_t u8RegSta;
|
||||
uint32_t u32Timeout, u32TimeCnt = 0u;
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Mode switch when RTC is running */
|
||||
if (0u != M4_RTC->CR1_f.START)
|
||||
{
|
||||
M4_RTC->CR2_f.RWREQ = 1u;
|
||||
/* Waiting for RWEN bit set */
|
||||
u32Timeout = SystemCoreClock >> 8u;
|
||||
do
|
||||
{
|
||||
u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN;
|
||||
u32TimeCnt++;
|
||||
} while ((u32TimeCnt < u32Timeout) && (u8RegSta == 0u));
|
||||
|
||||
if (0u == u8RegSta)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Exit RTC read/write mode
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval ErrorTimeout Exit mode timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_ExitRwMode(void)
|
||||
{
|
||||
uint8_t u8RegSta;
|
||||
uint32_t u32Timeout, u32TimeCnt = 0u;
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Mode switch when RTC is running */
|
||||
if (0u != M4_RTC->CR1_f.START)
|
||||
{
|
||||
M4_RTC->CR2_f.RWREQ = 0u;
|
||||
/* Waiting for RWEN bit reset */
|
||||
u32Timeout = SystemCoreClock >> 8u;
|
||||
do
|
||||
{
|
||||
u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN;
|
||||
u32TimeCnt++;
|
||||
} while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u));
|
||||
|
||||
if (1u == u8RegSta)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable RTC count
|
||||
**
|
||||
** \param [in] enNewSta The function new state
|
||||
** \arg Disable Disable RTC count
|
||||
** \arg Enable Enable RTC count
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_Cmd(en_functional_state_t enNewSta)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta));
|
||||
|
||||
M4_RTC->CR1_f.START = enNewSta;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC period interrupt config
|
||||
**
|
||||
** \param [in] enIntType Period interrupt request type
|
||||
** \arg RtcPeriodIntInvalid Period interrupt invalid
|
||||
** \arg RtcPeriodIntHalfSec 0.5 second period interrupt
|
||||
** \arg RtcPeriodIntOneSec 1 second period interrupt
|
||||
** \arg RtcPeriodIntOneMin 1 minute period interrupt
|
||||
** \arg RtcPeriodIntOneHour 1 hour period interrupt
|
||||
** \arg RtcPeriodIntOneDay 1 day period interrupt
|
||||
** \arg RtcPeriodIntOneMon 1 month period interrupt
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_PeriodIntConfig(en_rtc_period_int_type_t enIntType)
|
||||
{
|
||||
uint8_t u8RtcSta;
|
||||
uint8_t u8IntSta;
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_PERIOD_INT_CONDITION(enIntType));
|
||||
|
||||
u8RtcSta = (uint8_t)M4_RTC->CR1_f.START;
|
||||
u8IntSta = (uint8_t)M4_RTC->CR2_f.PRDIE;
|
||||
/* Disable period interrupt when START=1 and PRDIE=1 */
|
||||
if ((1u == u8IntSta) && (1u == u8RtcSta))
|
||||
{
|
||||
M4_RTC->CR2_f.PRDIE = 0u;
|
||||
}
|
||||
M4_RTC->CR1_f.PRDS = enIntType;
|
||||
|
||||
if ((1u == u8IntSta) && (1u == u8RtcSta))
|
||||
{
|
||||
M4_RTC->CR2_f.PRDIE = 1u;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief RTC switch to low power mode
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval ErrorInvalidMode RTC count not start
|
||||
** \retval ErrorTimeout Switch timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_LowPowerSwitch(void)
|
||||
{
|
||||
uint8_t u8RegSta;
|
||||
uint32_t u32Timeout, u32TimeCnt = 0u;
|
||||
en_result_t enRet = ErrorInvalidMode;
|
||||
|
||||
/* Check RTC work status */
|
||||
if (0u != M4_RTC->CR1_f.START)
|
||||
{
|
||||
M4_RTC->CR2_f.RWREQ = 1u;
|
||||
/* Waiting for RTC RWEN bit set */
|
||||
u32Timeout = SystemCoreClock / 100u;
|
||||
do
|
||||
{
|
||||
u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN;
|
||||
u32TimeCnt++;
|
||||
} while ((u32TimeCnt < u32Timeout) && (u8RegSta == 0u));
|
||||
|
||||
if (0u == u8RegSta)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_RTC->CR2_f.RWREQ = 0u;
|
||||
/* Waiting for RTC RWEN bit reset */
|
||||
u32TimeCnt = 0u;
|
||||
do
|
||||
{
|
||||
u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN;
|
||||
u32TimeCnt++;
|
||||
} while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u));
|
||||
|
||||
if (1u == u8RegSta)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
}
|
||||
else
|
||||
{
|
||||
enRet = Ok;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set RTC 1hz output compensation value
|
||||
**
|
||||
** \param [in] u16CompenVal Clock compensation value
|
||||
** \arg 0~0x1FF
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_SetClkCompenValue(uint16_t u16CompenVal)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_COMPEN_VALUE_RANGE(u16CompenVal));
|
||||
|
||||
M4_RTC->ERRCRH_f.COMP8 = ((uint32_t)u16CompenVal >> 8u) & 0x01u;
|
||||
M4_RTC->ERRCRL = (uint32_t)u16CompenVal & 0x00FFu;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable clock compensation
|
||||
**
|
||||
** \param [in] enNewSta The function new state
|
||||
** \arg Disable Disable RTC clock compensation
|
||||
** \arg Enable Enable RTC clock compensation
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_ClkCompenCmd(en_functional_state_t enNewSta)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta));
|
||||
|
||||
M4_RTC->ERRCRH_f.COMPEN = enNewSta;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable RTC 1hz output
|
||||
**
|
||||
** \param [in] enNewSta The function new state
|
||||
** \arg Disable Disable RTC 1hz output
|
||||
** \arg Enable Enable RTC 1hz output
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_OneHzOutputCmd(en_functional_state_t enNewSta)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta));
|
||||
|
||||
M4_RTC->CR1_f.ONEHZOE = enNewSta;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set RTC current date and time
|
||||
**
|
||||
** \param [in] enFormat Date and time data format
|
||||
** \arg RtcDataFormatDec Decimal format
|
||||
** \arg RtcDataFormatBcd BCD format
|
||||
**
|
||||
** \param [in] pstcRtcDateTime Pointer to RTC date and time configuration
|
||||
** \arg See the struct #stc_rtc_date_time_t
|
||||
**
|
||||
** \param [in] enUpdateDateEn The function new state(Contain year/month/day/weekday)
|
||||
** \arg Disable Disable update RTC date
|
||||
** \arg Enable Enable update RTC date
|
||||
**
|
||||
** \param [in] enUpdateTimeEn The function new state(Contain hour/minute/second)
|
||||
** \arg Disable Disable update RTC time
|
||||
** \arg Enable Enable update RTC time
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval Error Enter or exit read/write mode failed
|
||||
** \retval ErrorInvalidParameter Parameter enUpdateDateEn or enUpdateTimeEn invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_SetDateTime(en_rtc_data_format_t enFormat, const stc_rtc_date_time_t *pstcRtcDateTime,
|
||||
en_functional_state_t enUpdateDateEn, en_functional_state_t enUpdateTimeEn)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enUpdateDateEn));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enUpdateTimeEn));
|
||||
|
||||
/* Check update status */
|
||||
if (((Disable == enUpdateDateEn) && (Disable == enUpdateTimeEn)) || (NULL == pstcRtcDateTime))
|
||||
{
|
||||
enRet = ErrorInvalidParameter;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the date parameters */
|
||||
if (Enable == enUpdateDateEn)
|
||||
{
|
||||
if (RtcDataFormatDec == enFormat)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_DATE_YEAR(pstcRtcDateTime->u8Year));
|
||||
DDL_ASSERT(IS_VALID_DATE_MONTH(pstcRtcDateTime->u8Month));
|
||||
DDL_ASSERT(IS_VALID_DATE_DAY(pstcRtcDateTime->u8Day));
|
||||
}
|
||||
else
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_DATE_YEAR(BCD2DEC(pstcRtcDateTime->u8Year)));
|
||||
DDL_ASSERT(IS_VALID_DATE_MONTH(BCD2DEC(pstcRtcDateTime->u8Month)));
|
||||
DDL_ASSERT(IS_VALID_DATE_DAY(BCD2DEC(pstcRtcDateTime->u8Day)));
|
||||
}
|
||||
DDL_ASSERT(IS_VALID_DATE_WEEKDAY(pstcRtcDateTime->u8Weekday));
|
||||
}
|
||||
/* Check the time parameters */
|
||||
if (Enable == enUpdateTimeEn)
|
||||
{
|
||||
if (RtcDataFormatDec == enFormat)
|
||||
{
|
||||
if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_TIME_HOUR12(pstcRtcDateTime->u8Hour));
|
||||
DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcDateTime->enAmPm));
|
||||
}
|
||||
else
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_TIME_HOUR24(pstcRtcDateTime->u8Hour));
|
||||
}
|
||||
DDL_ASSERT(IS_VALID_TIME_MINUTE(pstcRtcDateTime->u8Minute));
|
||||
DDL_ASSERT(IS_VALID_TIME_SECOND(pstcRtcDateTime->u8Second));
|
||||
}
|
||||
else
|
||||
{
|
||||
if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_TIME_HOUR12(BCD2DEC(pstcRtcDateTime->u8Hour)));
|
||||
DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcDateTime->enAmPm));
|
||||
}
|
||||
else
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_TIME_HOUR24(BCD2DEC(pstcRtcDateTime->u8Hour)));
|
||||
}
|
||||
DDL_ASSERT(IS_VALID_TIME_MINUTE(BCD2DEC(pstcRtcDateTime->u8Minute)));
|
||||
DDL_ASSERT(IS_VALID_TIME_SECOND(BCD2DEC(pstcRtcDateTime->u8Second)));
|
||||
}
|
||||
}
|
||||
|
||||
/* Enter read/write mode */
|
||||
if (RTC_EnterRwMode() == ErrorTimeout)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update date */
|
||||
if (Enable == enUpdateDateEn)
|
||||
{
|
||||
if (RtcDataFormatDec == enFormat)
|
||||
{
|
||||
M4_RTC->YEAR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Year);
|
||||
M4_RTC->MON = DEC2BCD((uint32_t)pstcRtcDateTime->u8Month);
|
||||
M4_RTC->DAY = DEC2BCD((uint32_t)pstcRtcDateTime->u8Day);
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_RTC->YEAR = pstcRtcDateTime->u8Year;
|
||||
M4_RTC->MON = pstcRtcDateTime->u8Month;
|
||||
M4_RTC->DAY = pstcRtcDateTime->u8Day;
|
||||
}
|
||||
M4_RTC->WEEK = pstcRtcDateTime->u8Weekday;
|
||||
}
|
||||
/* Update time */
|
||||
if (Enable == enUpdateTimeEn)
|
||||
{
|
||||
if (RtcDataFormatDec == enFormat)
|
||||
{
|
||||
if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) &&
|
||||
(RtcHour12Pm == pstcRtcDateTime->enAmPm))
|
||||
{
|
||||
M4_RTC->HOUR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Hour) | RTC_HOUR12_AMPM_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_RTC->HOUR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Hour);
|
||||
}
|
||||
M4_RTC->MIN = DEC2BCD((uint32_t)pstcRtcDateTime->u8Minute);
|
||||
M4_RTC->SEC = DEC2BCD((uint32_t)pstcRtcDateTime->u8Second);
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) &&
|
||||
(RtcHour12Pm == pstcRtcDateTime->enAmPm))
|
||||
{
|
||||
M4_RTC->HOUR = (uint32_t)pstcRtcDateTime->u8Hour | RTC_HOUR12_AMPM_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_RTC->HOUR = (uint32_t)pstcRtcDateTime->u8Hour;
|
||||
}
|
||||
M4_RTC->MIN = pstcRtcDateTime->u8Minute;
|
||||
M4_RTC->SEC = pstcRtcDateTime->u8Second;
|
||||
}
|
||||
}
|
||||
/* Exit read/write mode */
|
||||
if (RTC_ExitRwMode() == ErrorTimeout)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get RTC current date and time
|
||||
**
|
||||
** \param [in] enFormat Date and time data format
|
||||
** \arg RtcDataFormatDec Decimal format
|
||||
** \arg RtcDataFormatBcd BCD format
|
||||
**
|
||||
** \param [out] pstcRtcDateTime Pointer to RTC date and time configuration
|
||||
** \arg See the struct #stc_rtc_date_time_t
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval Error Enter or exit read/write mode failed
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_GetDateTime(en_rtc_data_format_t enFormat, stc_rtc_date_time_t *pstcRtcDateTime)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
if(NULL == pstcRtcDateTime)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat));
|
||||
|
||||
/* Enter read/write mode */
|
||||
if (RTC_EnterRwMode() == ErrorTimeout)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get RTC date and time registers */
|
||||
pstcRtcDateTime->u8Year = (uint8_t)(M4_RTC->YEAR);
|
||||
pstcRtcDateTime->u8Month = (uint8_t)(M4_RTC->MON);
|
||||
pstcRtcDateTime->u8Day = (uint8_t)(M4_RTC->DAY);
|
||||
pstcRtcDateTime->u8Weekday = (uint8_t)(M4_RTC->WEEK);
|
||||
pstcRtcDateTime->u8Hour = (uint8_t)(M4_RTC->HOUR);
|
||||
pstcRtcDateTime->u8Minute = (uint8_t)(M4_RTC->MIN);
|
||||
pstcRtcDateTime->u8Second = (uint8_t)(M4_RTC->SEC);
|
||||
if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM)
|
||||
{
|
||||
if (RTC_HOUR12_AMPM_MASK == (pstcRtcDateTime->u8Hour & RTC_HOUR12_AMPM_MASK))
|
||||
{
|
||||
pstcRtcDateTime->u8Hour &= (uint8_t)(~RTC_HOUR12_AMPM_MASK);
|
||||
pstcRtcDateTime->enAmPm = RtcHour12Pm;
|
||||
}
|
||||
else
|
||||
{
|
||||
pstcRtcDateTime->enAmPm = RtcHour12Am;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check decimal format*/
|
||||
if (RtcDataFormatDec == enFormat)
|
||||
{
|
||||
pstcRtcDateTime->u8Year = BCD2DEC(pstcRtcDateTime->u8Year);
|
||||
pstcRtcDateTime->u8Month = BCD2DEC(pstcRtcDateTime->u8Month);
|
||||
pstcRtcDateTime->u8Day = BCD2DEC(pstcRtcDateTime->u8Day);
|
||||
pstcRtcDateTime->u8Hour = BCD2DEC(pstcRtcDateTime->u8Hour);
|
||||
pstcRtcDateTime->u8Minute = BCD2DEC(pstcRtcDateTime->u8Minute);
|
||||
pstcRtcDateTime->u8Second = BCD2DEC(pstcRtcDateTime->u8Second);
|
||||
}
|
||||
|
||||
/* exit read/write mode */
|
||||
if (RTC_ExitRwMode() == ErrorTimeout)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set RTC alarm time
|
||||
**
|
||||
** \param [in] enFormat Date and time data format
|
||||
** \arg RtcDataFormatDec Decimal format
|
||||
** \arg RtcDataFormatBcd BCD format
|
||||
**
|
||||
** \param [in] pstcRtcAlarmTime Pointer to RTC alarm time configuration
|
||||
** \arg See the struct #stc_rtc_alarm_time_t
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval Error Parameter error
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_SetAlarmTime(en_rtc_data_format_t enFormat, const stc_rtc_alarm_time_t *pstcRtcAlarmTime)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
if (NULL == pstcRtcAlarmTime)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat));
|
||||
|
||||
if (RtcDataFormatDec == enFormat)
|
||||
{
|
||||
if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_TIME_HOUR12(pstcRtcAlarmTime->u8Hour));
|
||||
DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcAlarmTime->enAmPm));
|
||||
}
|
||||
else
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_TIME_HOUR24(pstcRtcAlarmTime->u8Hour));
|
||||
}
|
||||
DDL_ASSERT(IS_VALID_TIME_MINUTE(pstcRtcAlarmTime->u8Minute));
|
||||
}
|
||||
else
|
||||
{
|
||||
if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_TIME_HOUR12(BCD2DEC(pstcRtcAlarmTime->u8Hour)));
|
||||
DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcAlarmTime->enAmPm));
|
||||
}
|
||||
else
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_TIME_HOUR24(BCD2DEC(pstcRtcAlarmTime->u8Hour)));
|
||||
}
|
||||
DDL_ASSERT(IS_VALID_TIME_MINUTE(BCD2DEC(pstcRtcAlarmTime->u8Minute)));
|
||||
}
|
||||
DDL_ASSERT(IS_VALID_ALARM_WEEKDAY(pstcRtcAlarmTime->u8Weekday));
|
||||
|
||||
/* Configure alarm registers */
|
||||
if (RtcDataFormatDec == enFormat)
|
||||
{
|
||||
if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) &&
|
||||
(RtcHour12Pm == pstcRtcAlarmTime->enAmPm))
|
||||
{
|
||||
M4_RTC->ALMHOUR = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Hour) | RTC_HOUR12_AMPM_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_RTC->ALMHOUR = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Hour);
|
||||
}
|
||||
M4_RTC->ALMMIN = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Minute);
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) &&
|
||||
(RtcHour12Pm == pstcRtcAlarmTime->enAmPm))
|
||||
{
|
||||
M4_RTC->ALMHOUR = (uint32_t)pstcRtcAlarmTime->u8Hour | RTC_HOUR12_AMPM_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_RTC->ALMHOUR = (uint32_t)pstcRtcAlarmTime->u8Hour;
|
||||
}
|
||||
M4_RTC->ALMMIN = pstcRtcAlarmTime->u8Minute;
|
||||
}
|
||||
M4_RTC->ALMWEEK = pstcRtcAlarmTime->u8Weekday;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get RTC alarm time
|
||||
**
|
||||
** \param [in] enFormat Date and time data format
|
||||
** \arg RtcDataFormatDec Decimal format
|
||||
** \arg RtcDataFormatBcd BCD format
|
||||
**
|
||||
** \param [out] pstcRtcAlarmTime Pointer to RTC alarm time configuration
|
||||
** \arg See the struct #stc_rtc_alarm_time_t
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
** \retval Error Parameter error
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_GetAlarmTime(en_rtc_data_format_t enFormat, stc_rtc_alarm_time_t *pstcRtcAlarmTime)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
if(NULL == pstcRtcAlarmTime)
|
||||
{
|
||||
enRet = Error;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat));
|
||||
|
||||
/* Get RTC date and time register */
|
||||
pstcRtcAlarmTime->u8Weekday = (uint8_t)M4_RTC->ALMWEEK;
|
||||
pstcRtcAlarmTime->u8Minute = (uint8_t)M4_RTC->ALMMIN;
|
||||
pstcRtcAlarmTime->u8Hour = (uint8_t)M4_RTC->ALMHOUR;
|
||||
if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM)
|
||||
{
|
||||
if ((pstcRtcAlarmTime->u8Hour & RTC_HOUR12_AMPM_MASK) == RTC_HOUR12_AMPM_MASK)
|
||||
{
|
||||
pstcRtcAlarmTime->u8Hour &= (uint8_t)(~RTC_HOUR12_AMPM_MASK);
|
||||
pstcRtcAlarmTime->enAmPm = RtcHour12Pm;
|
||||
}
|
||||
else
|
||||
{
|
||||
pstcRtcAlarmTime->enAmPm = RtcHour12Am;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check decimal format*/
|
||||
if (RtcDataFormatDec == enFormat)
|
||||
{
|
||||
pstcRtcAlarmTime->u8Hour = BCD2DEC(pstcRtcAlarmTime->u8Hour);
|
||||
pstcRtcAlarmTime->u8Minute = BCD2DEC(pstcRtcAlarmTime->u8Minute);
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable RTC alarm function
|
||||
**
|
||||
** \param [in] enNewSta The function new state
|
||||
** \arg Disable Disable RTC alarm function
|
||||
** \arg Enable Enable RTC alarm function
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_AlarmCmd(en_functional_state_t enNewSta)
|
||||
{
|
||||
uint8_t u8RtcSta;
|
||||
uint8_t u8IntSta;
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta));
|
||||
|
||||
u8RtcSta = (uint8_t)M4_RTC->CR1_f.START;
|
||||
u8IntSta = (uint8_t)M4_RTC->CR2_f.ALMIE;
|
||||
/* Disable alarm interrupt and clear alarm flag when START=1 and ALMIE=1 */
|
||||
if ((1u == u8IntSta) && (1u == u8RtcSta))
|
||||
{
|
||||
M4_RTC->CR2_f.ALMIE = 0u;
|
||||
}
|
||||
M4_RTC->CR2_f.ALME = enNewSta;
|
||||
|
||||
if ((1u == u8IntSta) && (1u == u8RtcSta))
|
||||
{
|
||||
M4_RTC->CR1_f.ALMFCLR = 0u;
|
||||
M4_RTC->CR2_f.ALMIE = u8IntSta;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable RTC interrupt request
|
||||
**
|
||||
** \param [in] enIrq RTC interrupt request type
|
||||
** \arg RtcIrqPeriod Period count interrupt request
|
||||
** \arg RtcIrqAlarm Alarm interrupt request
|
||||
**
|
||||
** \param [in] enNewSta The function new state
|
||||
** \arg Disable Disable interrupt request
|
||||
** \arg Enable Enable interrupt request
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_IrqCmd(en_rtc_irq_type_t enIrq, en_functional_state_t enNewSta)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_IRQ_TYPE(enIrq));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta));
|
||||
|
||||
/* enable/disable interrupt */
|
||||
switch (enIrq)
|
||||
{
|
||||
case RtcIrqPeriod:
|
||||
M4_RTC->CR2_f.PRDIE = enNewSta;
|
||||
break;
|
||||
case RtcIrqAlarm:
|
||||
M4_RTC->CR2_f.ALMIE = enNewSta;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get RTC Alarm flag status
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval Set Flag is set
|
||||
** \retval Reset Flag is reset
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t RTC_GetAlarmFlag(void)
|
||||
{
|
||||
return (en_flag_status_t)(M4_RTC->CR2_f.ALMF);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear RTC Alarm flag status
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t RTC_ClearAlarmFlag(void)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
M4_RTC->CR1_f.ALMFCLR = 0u;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
//@} // RtcGroup
|
||||
|
||||
#endif /* DDL_RTC_ENABLE */
|
||||
|
||||
/******************************************************************************
|
||||
* EOF (not truncated)
|
||||
*****************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,286 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_sram.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link SramGroup Internal SRAM module description @endlink
|
||||
**
|
||||
** - 2018-10-17 CDT First version for Device Driver Library of SRAM.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_sram.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_SRAM_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup SramGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*! Parameter validity check for ECC/Parity error handling. */
|
||||
#define IS_VALID_ERR_OP(x) \
|
||||
( ((x) == SramNmi) || \
|
||||
((x) == SramReset))
|
||||
|
||||
/*! Parameter validity check for SRAM ECC mode */
|
||||
#define IS_VALID_ECC_MD(x) \
|
||||
( ((x) == EccMode0) || \
|
||||
((x) == EccMode1) || \
|
||||
((x) == EccMode2) || \
|
||||
((x) == EccMode3))
|
||||
|
||||
/*! Parameter validity check for SRAM Index */
|
||||
#define IS_VALID_INDEX(x) \
|
||||
( ((x) == Sram12Idx) || \
|
||||
((x) == Sram3Idx) || \
|
||||
((x) == SramHsIdx) || \
|
||||
((x) == SramRetIdx))
|
||||
|
||||
/*! Parameter validity check for SRAM R/W wait cycle */
|
||||
#define IS_VALID_WAIT_CYCLE(x) \
|
||||
( ((x) == SramCycle1) || \
|
||||
((x) == SramCycle2) || \
|
||||
((x) == SramCycle3) || \
|
||||
((x) == SramCycle4) || \
|
||||
((x) == SramCycle5) || \
|
||||
((x) == SramCycle6) || \
|
||||
((x) == SramCycle7) || \
|
||||
((x) == SramCycle8))
|
||||
|
||||
/*! Parameter validity check for SRAM error status */
|
||||
#define IS_VALID_ERR(x) \
|
||||
( ((x) == Sram3EccErr1) || \
|
||||
((x) == Sram3EccErr2) || \
|
||||
((x) == Sram12ParityErr) || \
|
||||
((x) == SramHSParityErr) || \
|
||||
((x) == SramRetParityErr))
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SRAM read, write wait cycle register disable function
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok SRAM R/W wait cycle register disabled
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t SRAM_WT_Disable(void)
|
||||
{
|
||||
M4_SRAMC->WTPR = 0x76u;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SRAM read, write wait cycle register enable function
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok SRAM R/W wait cycle register enabled
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t SRAM_WT_Enable(void)
|
||||
{
|
||||
M4_SRAMC->WTPR = 0x77u;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SRAM ECC/Parity check register disable function
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok SRAM ECC/Parity check register disabled
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t SRAM_CK_Disable(void)
|
||||
{
|
||||
M4_SRAMC->CKPR = 0x76u;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SRAM ECC/Parity check register enable function
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok SRAM ECC/Parity check register enabled
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t SRAM_CK_Enable(void)
|
||||
{
|
||||
M4_SRAMC->CKPR = 0x77u;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get SRAM ECC/Parity error status flag
|
||||
**
|
||||
** \param [in] enSramErrStatus SRAM error status, This parameter can be
|
||||
** some values of @ref en_sram_err_status_t
|
||||
**
|
||||
** \retval Set Corresponding error occurs
|
||||
** Reset Corresponding error not occurs
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_ERR(enSramErrStatus));
|
||||
if (true == !!(enSramErrStatus & M4_SRAMC->CKSR))
|
||||
{
|
||||
return Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
return Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear SRAM ECC/Parity error status flag
|
||||
**
|
||||
** \param [in] enSramErrStatus SRAM error status, This parameter can be
|
||||
** some values of @ref en_sram_err_status_t
|
||||
**
|
||||
** \retval Ok Corresponding error flag be cleared
|
||||
** ErrorInvalidParameter Invalid parameter
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_ERR(enSramErrStatus));
|
||||
M4_SRAMC->CKSR |= enSramErrStatus;
|
||||
return Ok;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SRAM initialization
|
||||
**
|
||||
** \param [in] pstcSramConfig SRAM configure structure
|
||||
**
|
||||
** \retval Ok SRAM initialized
|
||||
** ErrorInvalidParameter Invalid parameter
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig)
|
||||
{
|
||||
uint8_t i = 0u;
|
||||
uint8_t u8TmpIdx;
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramRC));
|
||||
DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramWC));
|
||||
DDL_ASSERT(IS_VALID_ECC_MD(pstcSramConfig->enSramEccMode));
|
||||
DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramEccOp));
|
||||
DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramPyOp));
|
||||
|
||||
u8TmpIdx = pstcSramConfig->u8SramIdx;
|
||||
|
||||
if (0u == u8TmpIdx)
|
||||
{
|
||||
enRet = ErrorInvalidParameter;
|
||||
}
|
||||
else
|
||||
{
|
||||
SRAM_WT_Enable();
|
||||
SRAM_CK_Enable();
|
||||
for (i = 0u; i < 4u; i++)
|
||||
{
|
||||
if (true == (u8TmpIdx & 0x01u))
|
||||
{
|
||||
M4_SRAMC->WTCR |= (pstcSramConfig->enSramRC | \
|
||||
(pstcSramConfig->enSramWC << 4ul)) << (i * 8ul);
|
||||
}
|
||||
u8TmpIdx >>= 1u;
|
||||
}
|
||||
/* SRAM3 ECC config */
|
||||
if (pstcSramConfig->u8SramIdx & Sram3Idx)
|
||||
{
|
||||
M4_SRAMC->CKCR_f.ECCMOD = pstcSramConfig->enSramEccMode;
|
||||
M4_SRAMC->CKCR_f.ECCOAD = pstcSramConfig->enSramEccOp;
|
||||
}
|
||||
/* SRAM1/2/HS/Ret parity config */
|
||||
else
|
||||
{
|
||||
M4_SRAMC->CKCR_f.PYOAD = pstcSramConfig->enSramPyOp;
|
||||
}
|
||||
|
||||
SRAM_WT_Disable();
|
||||
SRAM_CK_Disable();
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SRAM de-initialization
|
||||
**
|
||||
** \param None
|
||||
**
|
||||
** \retval Ok SRAM de-initialized
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t SRAM_DeInit(void)
|
||||
{
|
||||
/* SRAM R/W wait register */
|
||||
M4_SRAMC->WTPR = 0x77ul;
|
||||
M4_SRAMC->WTCR = 0ul;
|
||||
M4_SRAMC->WTPR = 0x76ul;
|
||||
|
||||
/* SRAM check register */
|
||||
M4_SRAMC->CKPR = 0x77ul;
|
||||
M4_SRAMC->CKCR = 0ul;
|
||||
M4_SRAMC->CKPR = 0x76ul;
|
||||
|
||||
/* SRAM status register */
|
||||
M4_SRAMC->CKSR = 0x1Ful;
|
||||
|
||||
return Ok;
|
||||
}
|
||||
|
||||
//@} // SramGroup
|
||||
|
||||
#endif /* DDL_SRAM_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,170 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_swdt.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link SwdtGroup Special Watchdog Counter description @endlink
|
||||
**
|
||||
** - 2018-10-16 CDT First version for Device Driver Library of SWDT.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_swdt.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_SWDT_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup SwdtGroup
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*!< Parameter valid check for flag type */
|
||||
#define IS_VALID_FLAG_TYPE(x) \
|
||||
( (SwdtFlagCountUnderflow == (x)) || \
|
||||
(SwdtFlagRefreshError == (x)))
|
||||
|
||||
/*!< SWDT_RR register refresh key */
|
||||
#define SWDT_REFRESH_START_KEY ((uint16_t)0x0123)
|
||||
#define SWDT_REFRESH_END_KEY_ ((uint16_t)0x3210)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief SWDT refresh counter
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t SWDT_RefreshCounter(void)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
M4_SWDT->RR = SWDT_REFRESH_START_KEY;
|
||||
M4_SWDT->RR = SWDT_REFRESH_END_KEY_;
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get SWDT counter current count value
|
||||
**
|
||||
** \param [in] None
|
||||
**
|
||||
** \retval uint16_t SWDT counter current count value
|
||||
**
|
||||
******************************************************************************/
|
||||
uint16_t SWDT_GetCountValue(void)
|
||||
{
|
||||
return ((uint16_t)M4_SWDT->SR_f.CNT);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get SWDT flag status
|
||||
**
|
||||
** \param [in] enFlag SWDT flag type
|
||||
** \arg SwdtFlagCountUnderflow Count underflow flag
|
||||
** \arg SwdtFlagRefreshError Refresh error flag
|
||||
**
|
||||
** \retval Set Flag is set
|
||||
** \retval Reset Flag is reset
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t SWDT_GetFlag(en_swdt_flag_type_t enFlag)
|
||||
{
|
||||
en_flag_status_t enFlagSta = Reset;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag));
|
||||
|
||||
switch (enFlag)
|
||||
{
|
||||
case SwdtFlagCountUnderflow:
|
||||
enFlagSta = (en_flag_status_t)M4_SWDT->SR_f.UDF;
|
||||
break;
|
||||
case SwdtFlagRefreshError:
|
||||
enFlagSta = (en_flag_status_t)M4_SWDT->SR_f.REF;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return enFlagSta;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear SWDT flag status
|
||||
**
|
||||
** \param [in] enFlag SWDT flag type
|
||||
** \arg SwdtFlagCountUnderflow Count underflow flag
|
||||
** \arg SwdtFlagRefreshError Refresh error flag
|
||||
**
|
||||
** \retval Ok Process successfully done
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t SWDT_ClearFlag(en_swdt_flag_type_t enFlag)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag));
|
||||
|
||||
switch (enFlag)
|
||||
{
|
||||
case SwdtFlagCountUnderflow:
|
||||
M4_SWDT->SR_f.UDF = 0u;
|
||||
break;
|
||||
case SwdtFlagRefreshError:
|
||||
M4_SWDT->SR_f.REF = 0u;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
//@} // SwdtGroup
|
||||
|
||||
#endif /* DDL_SWDT_ENABLE */
|
||||
|
||||
/******************************************************************************
|
||||
* EOF (not truncated)
|
||||
*****************************************************************************/
|
||||
@@ -0,0 +1,967 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer0.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer0Group description @endlink
|
||||
**
|
||||
** - 2018-10-11 CDT First version for Device Driver Library of TIMER0.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_timer0.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_TIMER0_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup Timer0Group
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Parameter validity check for unit. */
|
||||
#define IS_VALID_UNIT(x) \
|
||||
( ((x) == M4_TMR01) || \
|
||||
((x) == M4_TMR02))
|
||||
|
||||
/* Parameter validity check for channel. */
|
||||
#define IS_VALID_CHANNEL(x) \
|
||||
( ((x) == Tim0_ChannelA) || \
|
||||
((x) == Tim0_ChannelB))
|
||||
|
||||
/* Parameter validity check for command. */
|
||||
#define IS_VALID_COMMAND(x) \
|
||||
( ((x) == Disable) || \
|
||||
((x) == Enable))
|
||||
|
||||
/* Parameter validity check for timer0 function mode. */
|
||||
#define IS_VALID_FUNCTION(x) \
|
||||
( ((x) == Tim0_OutputCapare) || \
|
||||
((x) == Tim0_InputCaptrue))
|
||||
|
||||
/* Parameter validity check for clock division. */
|
||||
#define IS_VALID_CLK_DIVISION(x) \
|
||||
( ((x) == Tim0_ClkDiv0) || \
|
||||
((x) == Tim0_ClkDiv2) || \
|
||||
((x) == Tim0_ClkDiv4) || \
|
||||
((x) == Tim0_ClkDiv8) || \
|
||||
((x) == Tim0_ClkDiv16) || \
|
||||
((x) == Tim0_ClkDiv32) || \
|
||||
((x) == Tim0_ClkDiv64) || \
|
||||
((x) == Tim0_ClkDiv128) || \
|
||||
((x) == Tim0_ClkDiv256) || \
|
||||
((x) == Tim0_ClkDiv512) || \
|
||||
((x) == Tim0_ClkDiv1024))
|
||||
|
||||
/* Parameter validity check for synchronous clock source. */
|
||||
#define IS_VALID_CLK_SYN_SRC(x) \
|
||||
( ((x) == Tim0_Pclk1) || \
|
||||
((x) == Tim0_InsideHardTrig))
|
||||
|
||||
/* Parameter validity check for asynchronous clock source. */
|
||||
#define IS_VALID_CLK_ASYN_SRC(x) \
|
||||
( ((x) == Tim0_LRC) || \
|
||||
((x) == Tim0_XTAL32))
|
||||
|
||||
/* Parameter validity check for counter clock mode. */
|
||||
#define IS_VALID_CLK_MODE(x) \
|
||||
( ((x) == Tim0_Sync) || \
|
||||
((x) == Tim0_Async))
|
||||
|
||||
/* Parameter validity check for counter clock mode for M4_TMR01. */
|
||||
#define IS_VALID_CLK_MODE_UNIT01(x) \
|
||||
( (x) == Tim0_Async)
|
||||
|
||||
/* Parameter validity check for external trigger event. */
|
||||
#define IS_VALID_TRIG_SRC_EVENT(x) \
|
||||
( ((x) <= EVT_PORT_EIRQ15) || \
|
||||
(((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \
|
||||
(((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \
|
||||
(((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \
|
||||
(((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \
|
||||
(((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \
|
||||
(((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \
|
||||
(((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \
|
||||
(((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \
|
||||
(((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \
|
||||
(((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \
|
||||
(((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \
|
||||
(((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \
|
||||
(((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \
|
||||
(((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \
|
||||
(((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \
|
||||
(((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \
|
||||
(((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \
|
||||
(((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \
|
||||
(((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \
|
||||
(((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \
|
||||
(((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \
|
||||
(((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \
|
||||
(((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \
|
||||
(((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \
|
||||
(((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \
|
||||
((x) == EVT_WDT_REFUDF) || \
|
||||
(((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \
|
||||
(((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \
|
||||
(((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)))
|
||||
|
||||
/* Parameter validity check for common trigger. */
|
||||
#define IS_VALID_TIM0_COM_TRIGGER(x) \
|
||||
( ((x) == Tim0ComTrigger_1) || \
|
||||
((x) == Tim0ComTrigger_2) || \
|
||||
((x) == Tim0ComTrigger_1_2))
|
||||
|
||||
/* Delay count for time out */
|
||||
#define TIMER0_TMOUT (0x5000ul)
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get clock mode
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \retval Tim0_Sync: Synchronous clock
|
||||
** \retval Tim0_Async: Asynchronous clock
|
||||
**
|
||||
******************************************************************************/
|
||||
static en_tim0_counter_mode_t TIMER0_GetClkMode(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh)
|
||||
{
|
||||
en_tim0_counter_mode_t enMode = Tim0_Sync;
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
|
||||
switch(enCh)
|
||||
{
|
||||
case Tim0_ChannelA:
|
||||
enMode = (en_tim0_counter_mode_t)pstcTim0Reg->BCONR_f.SYNSA;
|
||||
break;
|
||||
case Tim0_ChannelB:
|
||||
enMode = (en_tim0_counter_mode_t)pstcTim0Reg->BCONR_f.SYNSB;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return enMode;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Time delay for register write in asynchronous mode
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \param [in] enIsPublicReg Enable for BCONR and STFLR register delay
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
static void AsyncDelay(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,
|
||||
en_functional_state_t enIsPublicReg)
|
||||
{
|
||||
en_functional_state_t enDelayEn = Disable;
|
||||
en_tim0_counter_mode_t enModeA = TIMER0_GetClkMode(pstcTim0Reg, Tim0_ChannelA);
|
||||
en_tim0_counter_mode_t enModeB = TIMER0_GetClkMode(pstcTim0Reg, Tim0_ChannelB);
|
||||
|
||||
if(Enable == enIsPublicReg)
|
||||
{
|
||||
if((Tim0_Async == enModeA) || (Tim0_Async == enModeB))
|
||||
{
|
||||
enDelayEn = Enable;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(Tim0_Async == TIMER0_GetClkMode(pstcTim0Reg, enCh))
|
||||
{
|
||||
enDelayEn = Enable;
|
||||
}
|
||||
}
|
||||
|
||||
if(Enable == enDelayEn)
|
||||
{
|
||||
for(uint32_t i=0ul; i<SystemCoreClock/10000ul; i++)
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer0 status flag
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \retval Set Flag is set
|
||||
** Reset Flag is reset
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t TIMER0_GetFlag(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh)
|
||||
{
|
||||
en_flag_status_t enFlag = Reset;
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
|
||||
switch(enCh)
|
||||
{
|
||||
case Tim0_ChannelA:
|
||||
enFlag = (en_flag_status_t)pstcTim0Reg->STFLR_f.CMAF;
|
||||
break;
|
||||
case Tim0_ChannelB:
|
||||
enFlag = (en_flag_status_t)pstcTim0Reg->STFLR_f.CMBF;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return enFlag;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear Timer0 status flag
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Timer0 channel, Timer0_ChA or Timer0_ChB
|
||||
**
|
||||
** \retval Ok Success
|
||||
** \retval ErrorTimeout Process timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER0_ClearFlag(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
uint32_t u32TimeOut = 0ul;
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
|
||||
if(Tim0_ChannelA == enCh)
|
||||
{
|
||||
pstcTim0Reg->STFLR_f.CMAF =0u;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
while(0u != pstcTim0Reg->STFLR_f.CMAF)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
pstcTim0Reg->STFLR_f.CMBF = 0u;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
while(0u != pstcTim0Reg->STFLR_f.CMBF)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Command the timer0 function
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Timer0 channel, Timer0_ChA or Timer0_ChB
|
||||
**
|
||||
** \param [in] enCmd Disable or Enable the function
|
||||
**
|
||||
** \retval Ok Success
|
||||
** \retval ErrorTimeout Process timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER0_Cmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,
|
||||
en_functional_state_t enCmd)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
uint32_t u32TimeOut = 0ul;
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
DDL_ASSERT(IS_VALID_COMMAND(enCmd));
|
||||
|
||||
switch (enCh)
|
||||
{
|
||||
case Tim0_ChannelA:
|
||||
pstcTim0Reg->BCONR_f.CSTA = enCmd;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
while(enCmd != pstcTim0Reg->BCONR_f.CSTA)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case Tim0_ChannelB:
|
||||
pstcTim0Reg->BCONR_f.CSTB = enCmd;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
while(enCmd != pstcTim0Reg->BCONR_f.CSTB)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Select the timer0 function mode
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \param [in] enFunc Timer0 function,Tim0_OutputCapare or Tim0_InputCapture
|
||||
**
|
||||
** \retval Ok Success
|
||||
** \retval ErrorTimeout Process timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER0_SetFunc(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,
|
||||
en_tim0_function_t enFunc)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
uint32_t u32TimeOut = 0ul;
|
||||
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
DDL_ASSERT(IS_VALID_FUNCTION(enFunc));
|
||||
|
||||
switch (enCh)
|
||||
{
|
||||
case Tim0_ChannelA:
|
||||
pstcTim0Reg->BCONR_f.CAPMDA = enFunc;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
while(enFunc != pstcTim0Reg->BCONR_f.CAPMDA)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case Tim0_ChannelB:
|
||||
pstcTim0Reg->BCONR_f.CAPMDB = enFunc;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
while(enFunc != pstcTim0Reg->BCONR_f.CAPMDB)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 interrupt function command
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \param [in] enCmd Disable or Enable the function
|
||||
**
|
||||
** \retval Ok Success
|
||||
** \retval ErrorTimeout Process timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER0_IntCmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,
|
||||
en_functional_state_t enCmd)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
uint32_t u32TimeOut = 0ul;
|
||||
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
DDL_ASSERT(IS_VALID_COMMAND(enCmd));
|
||||
|
||||
switch (enCh)
|
||||
{
|
||||
case Tim0_ChannelA:
|
||||
pstcTim0Reg->BCONR_f.INTENA = enCmd;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
while(enCmd != pstcTim0Reg->BCONR_f.INTENA)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case Tim0_ChannelB:
|
||||
pstcTim0Reg->BCONR_f.INTENB = enCmd;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
while(enCmd != pstcTim0Reg->BCONR_f.INTENB)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer0 counter register
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \retval uint16_t Count register
|
||||
**
|
||||
******************************************************************************/
|
||||
uint16_t TIMER0_GetCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh)
|
||||
{
|
||||
uint16_t u16Value = 0u;
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
|
||||
if(Tim0_ChannelA == enCh)
|
||||
{
|
||||
u16Value = (uint16_t)((pstcTim0Reg->CNTAR)&0xFFFFu);
|
||||
}
|
||||
else
|
||||
{
|
||||
u16Value = (uint16_t)((pstcTim0Reg->CNTBR)&0xFFFFu);
|
||||
}
|
||||
|
||||
return u16Value;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Write Timer0 counter register
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \param [in] u16Cnt Data to write
|
||||
**
|
||||
** \retval Ok Success
|
||||
** \retval ErrorTimeout Process timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER0_WriteCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh,
|
||||
uint16_t u16Cnt)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
uint32_t u32TimeOut = 0ul;
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
|
||||
if(Tim0_ChannelA == enCh)
|
||||
{
|
||||
pstcTim0Reg->CNTAR = (uint32_t)u16Cnt;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Disable);
|
||||
while(u16Cnt != (uint16_t)pstcTim0Reg->CNTAR)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
pstcTim0Reg->CNTBR = (uint32_t)u16Cnt;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Disable);
|
||||
while(u16Cnt != (uint16_t)pstcTim0Reg->CNTBR)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer0 base compare count register
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \retval uint16_t Base compare count register
|
||||
**
|
||||
******************************************************************************/
|
||||
uint16_t TIMER0_GetCmpReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh)
|
||||
{
|
||||
uint16_t u16Value = 0u;
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
|
||||
if(Tim0_ChannelA == enCh)
|
||||
{
|
||||
u16Value = (uint16_t)((pstcTim0Reg->CMPAR)&0xFFFFu);
|
||||
}
|
||||
else
|
||||
{
|
||||
u16Value = (uint16_t)((pstcTim0Reg->CMPBR)&0xFFFFu);
|
||||
}
|
||||
return u16Value;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Wirte Timer0 base compare count register
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \param [in] u16Cnt Data to write
|
||||
**
|
||||
** \retval Ok Success
|
||||
** \retval ErrorTimeout Process timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER0_WriteCmpReg(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,
|
||||
uint16_t u16Cnt)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
uint32_t u32TimeOut = 0ul;
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
|
||||
if(Tim0_ChannelA == enCh)
|
||||
{
|
||||
pstcTim0Reg->CMPAR = (uint32_t)u16Cnt;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Disable);
|
||||
while(u16Cnt != (uint16_t)pstcTim0Reg->CMPAR)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
pstcTim0Reg->CMPBR = (uint32_t)u16Cnt;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Disable);
|
||||
while(u16Cnt != (uint16_t)pstcTim0Reg->CMPBR)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 peripheral base function initialize
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \param [in] pstcBaseInit Timer0 function base parameter structure
|
||||
**
|
||||
** \retval Ok Process finished.
|
||||
** \retval ErrorInvalidParameter Parameter error.
|
||||
** \retval ErrorTimeout Process timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER0_BaseInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh,
|
||||
const stc_tim0_base_init_t* pstcBaseInit)
|
||||
{
|
||||
stc_tmr0_bconr_field_t stcBconrTmp;
|
||||
en_result_t enRet = Ok;
|
||||
uint32_t u32TimeOut = 0ul;
|
||||
|
||||
if (NULL != pstcBaseInit)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
DDL_ASSERT(IS_VALID_CLK_DIVISION(pstcBaseInit->Tim0_ClockDivision));
|
||||
DDL_ASSERT(IS_VALID_CLK_SYN_SRC(pstcBaseInit->Tim0_SyncClockSource));
|
||||
DDL_ASSERT(IS_VALID_CLK_ASYN_SRC(pstcBaseInit->Tim0_AsyncClockSource));
|
||||
DDL_ASSERT(IS_VALID_CLK_MODE(pstcBaseInit->Tim0_CounterMode));
|
||||
|
||||
if((M4_TMR01 == pstcTim0Reg)&&(Tim0_ChannelA == enCh))
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_CLK_MODE_UNIT01(pstcBaseInit->Tim0_CounterMode));
|
||||
}
|
||||
|
||||
/*Read current BCONR register */
|
||||
stcBconrTmp = pstcTim0Reg->BCONR_f;
|
||||
/* Clear current configurate CH */
|
||||
if(Tim0_ChannelA == enCh)
|
||||
{
|
||||
*(uint32_t *)&stcBconrTmp &= 0xFFFF0000ul;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(uint32_t *)&stcBconrTmp &= 0x0000FFFFul;
|
||||
}
|
||||
pstcTim0Reg->BCONR_f = stcBconrTmp;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
while(*(uint32_t *)&stcBconrTmp != *(uint32_t *)&(pstcTim0Reg->BCONR_f))
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
switch(enCh)
|
||||
{
|
||||
case Tim0_ChannelA:
|
||||
|
||||
switch(pstcBaseInit->Tim0_CounterMode)
|
||||
{
|
||||
case Tim0_Sync:
|
||||
stcBconrTmp.SYNCLKA = pstcBaseInit->Tim0_SyncClockSource;
|
||||
break;
|
||||
case Tim0_Async:
|
||||
stcBconrTmp.ASYNCLKA = pstcBaseInit->Tim0_AsyncClockSource;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
/*set clock division*/
|
||||
stcBconrTmp.CKDIVA = pstcBaseInit->Tim0_ClockDivision;
|
||||
/* Write BCONR register */
|
||||
pstcTim0Reg->BCONR_f = stcBconrTmp;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
|
||||
/*set timer compare value*/
|
||||
pstcTim0Reg->CMPAR = pstcBaseInit->Tim0_CmpValue;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
|
||||
/*set timer counter mode*/
|
||||
pstcTim0Reg->BCONR_f.SYNSA = pstcBaseInit->Tim0_CounterMode;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
u32TimeOut = 0ul;
|
||||
while(pstcBaseInit->Tim0_CounterMode != pstcTim0Reg->BCONR_f.SYNSA)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case Tim0_ChannelB:
|
||||
switch(pstcBaseInit->Tim0_CounterMode)
|
||||
{
|
||||
case Tim0_Sync:
|
||||
stcBconrTmp.SYNCLKB = pstcBaseInit->Tim0_SyncClockSource;
|
||||
break;
|
||||
case Tim0_Async:
|
||||
stcBconrTmp.ASYNCLKB = pstcBaseInit->Tim0_AsyncClockSource;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
/*set clock division*/
|
||||
stcBconrTmp.CKDIVB = pstcBaseInit->Tim0_ClockDivision;
|
||||
/* Write BCONR register */
|
||||
pstcTim0Reg->BCONR_f = stcBconrTmp;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
|
||||
/*set timer compare value*/
|
||||
pstcTim0Reg->CMPBR = pstcBaseInit->Tim0_CmpValue;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
|
||||
/*set timer counter mode*/
|
||||
pstcTim0Reg->BCONR_f.SYNSB = pstcBaseInit->Tim0_CounterMode;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
u32TimeOut = 0ul;
|
||||
while(pstcBaseInit->Tim0_CounterMode != pstcTim0Reg->BCONR_f.SYNSB)
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
enRet = ErrorInvalidParameter;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 peripheral base function initalize
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \retval Ok Process finished.
|
||||
** \retval ErrorTimeout Process timeout
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER0_DeInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
uint32_t u32TimeOut = 0ul;
|
||||
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
|
||||
switch(enCh)
|
||||
{
|
||||
case Tim0_ChannelA:
|
||||
pstcTim0Reg->BCONR &= 0xFFFF0000ul;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
while(0ul != (pstcTim0Reg->BCONR & 0x0000FFFFul))
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pstcTim0Reg->CMPAR = 0x0000FFFFul;
|
||||
pstcTim0Reg->CNTAR = 0x00000000ul;
|
||||
pstcTim0Reg->STFLR_f.CMAF =0u;
|
||||
break;
|
||||
|
||||
case Tim0_ChannelB:
|
||||
pstcTim0Reg->BCONR &= 0x0000FFFFul;
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
while(0ul != (pstcTim0Reg->BCONR & 0xFFFF0000ul))
|
||||
{
|
||||
if(u32TimeOut++ > TIMER0_TMOUT)
|
||||
{
|
||||
enRet = ErrorTimeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pstcTim0Reg->CMPBR = 0x0000FFFFul;
|
||||
pstcTim0Reg->CNTBR = 0x00000000ul;
|
||||
pstcTim0Reg->STFLR_f.CMBF =0u;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set external trigger source for Timer0
|
||||
**
|
||||
** \param [in] enEvent External event source
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
void TIMER0_SetTriggerSrc(en_event_src_t enEvent)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_TRIG_SRC_EVENT(enEvent));
|
||||
|
||||
M4_AOS->TMR0_HTSSR_f.TRGSEL = enEvent;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enable or disable Timer0 common trigger.
|
||||
**
|
||||
** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_tim0_com_trigger_t for details.
|
||||
** \param [in] enState Enable or disable the specified common trigger.
|
||||
**
|
||||
** \retval None
|
||||
**
|
||||
******************************************************************************/
|
||||
void TIMER0_ComTriggerCmd(en_tim0_com_trigger_t enComTrigger, en_functional_state_t enState)
|
||||
{
|
||||
uint32_t u32ComTrig = (uint32_t)enComTrigger;
|
||||
|
||||
DDL_ASSERT(IS_VALID_TIM0_COM_TRIGGER(enComTrigger));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enState));
|
||||
|
||||
if (enState == Enable)
|
||||
{
|
||||
M4_AOS->TMR0_HTSSR |= (u32ComTrig << 30u);
|
||||
}
|
||||
else
|
||||
{
|
||||
M4_AOS->TMR0_HTSSR &= ~(u32ComTrig << 30u);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Timer0 hardware trigger function initalize
|
||||
**
|
||||
** \param [in] pstcTim0Reg Pointer to Timer0 register
|
||||
**
|
||||
** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB
|
||||
**
|
||||
** \param [in] pStcInit Timer0 hareware trigger function structure
|
||||
**
|
||||
** \retval Ok Process finished.
|
||||
** \retval ErrorInvalidParameter Parameter error.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER0_HardTriggerInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh,
|
||||
const stc_tim0_trigger_init_t* pStcInit)
|
||||
{
|
||||
stc_tmr0_bconr_field_t stcBconrTmp;
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
if(NULL != pStcInit)
|
||||
{
|
||||
DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg));
|
||||
DDL_ASSERT(IS_VALID_CHANNEL(enCh));
|
||||
DDL_ASSERT(IS_VALID_FUNCTION(pStcInit->Tim0_OCMode));
|
||||
DDL_ASSERT(IS_VALID_TRIG_SRC_EVENT(pStcInit->Tim0_SelTrigSrc));
|
||||
|
||||
/*Read current BCONR register */
|
||||
stcBconrTmp = pstcTim0Reg->BCONR_f;
|
||||
|
||||
switch(enCh)
|
||||
{
|
||||
case Tim0_ChannelA:
|
||||
/*set work on input captrue or output capare*/
|
||||
stcBconrTmp.CAPMDA = pStcInit->Tim0_OCMode;
|
||||
/*enable input capture*/
|
||||
stcBconrTmp.HICPA = pStcInit->Tim0_InTrigEnable;
|
||||
/*enable trigger clear counter*/
|
||||
stcBconrTmp.HCLEA = pStcInit->Tim0_InTrigClear;
|
||||
/*enable trigger start counter*/
|
||||
stcBconrTmp.HSTAA = pStcInit->Tim0_InTrigStart;
|
||||
/*enable trigger stop counter*/
|
||||
stcBconrTmp.HSTPA = pStcInit->Tim0_InTrigStop;
|
||||
|
||||
/* Write BCONR register */
|
||||
pstcTim0Reg->BCONR_f = stcBconrTmp;
|
||||
break;
|
||||
case Tim0_ChannelB:
|
||||
/*set work on input captrue or output capare*/
|
||||
stcBconrTmp.CAPMDB = pStcInit->Tim0_OCMode;
|
||||
/*enable input capture*/
|
||||
stcBconrTmp.HICPB = pStcInit->Tim0_InTrigEnable;
|
||||
/*enable trigger clear counter*/
|
||||
stcBconrTmp.HCLEB = pStcInit->Tim0_InTrigClear;
|
||||
/*enable trigger start counter*/
|
||||
stcBconrTmp.HSTAB = pStcInit->Tim0_InTrigStart;
|
||||
/*enable trigger stop counter*/
|
||||
stcBconrTmp.HSTPB = pStcInit->Tim0_InTrigStop;
|
||||
|
||||
/* Write BCONR register */
|
||||
pstcTim0Reg->BCONR_f = stcBconrTmp;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
AsyncDelay(pstcTim0Reg, enCh, Enable);
|
||||
|
||||
/* Set trigger source*/
|
||||
M4_AOS->TMR0_HTSSR_f.TRGSEL = pStcInit->Tim0_SelTrigSrc;
|
||||
}
|
||||
else
|
||||
{
|
||||
enRet = ErrorInvalidParameter;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
|
||||
}
|
||||
|
||||
//@} // Timer0Group
|
||||
|
||||
#endif /* DDL_TIMER0_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,842 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer4_cnt.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer4CntGroup Timer4CNT description @endlink
|
||||
**
|
||||
** - 2018-11-02 CDT First version for Device Driver Library of Timer4CNT.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_timer4_cnt.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_TIMER4_CNT_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup Timer4CntGroup
|
||||
******************************************************************************/
|
||||
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*!< Parameter validity check for Timer4 unit */
|
||||
#define IS_VALID_TIMER4(__TMRx__) \
|
||||
( (M4_TMR41 == (__TMRx__)) || \
|
||||
(M4_TMR42 == (__TMRx__)) || \
|
||||
(M4_TMR43 == (__TMRx__)))
|
||||
|
||||
/*!< Parameter validity check for CNT pclk division */
|
||||
#define IS_VALID_CNT_CLK_DIV(x) \
|
||||
( (Timer4CntPclkDiv1 == (x)) || \
|
||||
(Timer4CntPclkDiv2 == (x)) || \
|
||||
(Timer4CntPclkDiv4 == (x)) || \
|
||||
(Timer4CntPclkDiv8 == (x)) || \
|
||||
(Timer4CntPclkDiv16 == (x)) || \
|
||||
(Timer4CntPclkDiv32 == (x)) || \
|
||||
(Timer4CntPclkDiv64 == (x)) || \
|
||||
(Timer4CntPclkDiv128 == (x)) || \
|
||||
(Timer4CntPclkDiv256 == (x)) || \
|
||||
(Timer4CntPclkDiv512 == (x)) || \
|
||||
(Timer4CntPclkDiv1024 == (x)))
|
||||
|
||||
/*!< Parameter validity check for CNT mode */
|
||||
#define IS_VALID_CNT_MODE(x) \
|
||||
( (Timer4CntSawtoothWave == (x)) || \
|
||||
(Timer4CntTriangularWave == (x)))
|
||||
|
||||
/*!< Parameter validity check for CNT interrupt mask */
|
||||
#define IS_VALID_CNT_INT_MSK(x) \
|
||||
( (Timer4CntIntMask0 == (x)) || \
|
||||
(Timer4CntIntMask1 == (x)) || \
|
||||
(Timer4CntIntMask2 == (x)) || \
|
||||
(Timer4CntIntMask3 == (x)) || \
|
||||
(Timer4CntIntMask4 == (x)) || \
|
||||
(Timer4CntIntMask5 == (x)) || \
|
||||
(Timer4CntIntMask6 == (x)) || \
|
||||
(Timer4CntIntMask7 == (x)) || \
|
||||
(Timer4CntIntMask8 == (x)) || \
|
||||
(Timer4CntIntMask9 == (x)) || \
|
||||
(Timer4CntIntMask10 == (x)) || \
|
||||
(Timer4CntIntMask11 == (x)) || \
|
||||
(Timer4CntIntMask12 == (x)) || \
|
||||
(Timer4CntIntMask13 == (x)) || \
|
||||
(Timer4CntIntMask14 == (x)) || \
|
||||
(Timer4CntIntMask15 == (x)))
|
||||
|
||||
/*!< Parameter validity check for CNT match interrupt type */
|
||||
#define IS_VALID_CNT_INT_TYPE(x) \
|
||||
( (Timer4CntZeroMatchInt == (x)) || \
|
||||
(Timer4CntPeakMatchInt == (x)))
|
||||
|
||||
/*!< Parameter validity check for CNT clock source */
|
||||
#define IS_VALID_CNT_CLK(x) \
|
||||
( (Timer4CntPclk == (x)) || \
|
||||
(Timer4CntExtclk == (x)))
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Initialize Timer4 CNT
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] pstcInitCfg Pointer to CNT initialization configuration structure
|
||||
** \arg This parameter detail refer @ref stc_timer4_cnt_init_t
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter If one of following cases matches:
|
||||
** - TMR4x is invalid
|
||||
** - pstcInitCfg == NULL
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_Init(M4_TMR4_TypeDef *TMR4x,
|
||||
const stc_timer4_cnt_init_t *pstcInitCfg)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
stc_tmr4_ccsr_field_t CCSR_f = {0};
|
||||
stc_tmr4_cvpr_field_t CVPR_f = {0};
|
||||
|
||||
/* Check for TMR4x && pstcInitCfg pointer */
|
||||
if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_CNT_CLK(pstcInitCfg->enClk));
|
||||
DDL_ASSERT(IS_VALID_CNT_MODE(pstcInitCfg->enCntMode));
|
||||
DDL_ASSERT(IS_VALID_CNT_CLK_DIV(pstcInitCfg->enClkDiv));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enBufferCmd));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enZeroIntCmd));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enPeakIntCmd));
|
||||
DDL_ASSERT(IS_VALID_CNT_INT_MSK(pstcInitCfg->enZeroIntMsk));
|
||||
DDL_ASSERT(IS_VALID_CNT_INT_MSK(pstcInitCfg->enPeakIntMsk));
|
||||
|
||||
/* Set default value */
|
||||
TMR4x->CCSR = (uint16_t)0x0050u;
|
||||
TMR4x->CNTR = (uint16_t)0x0000u;
|
||||
TMR4x->CPSR = (uint16_t)0xFFFFu;
|
||||
TMR4x->CVPR = (uint16_t)0x0000u;
|
||||
|
||||
/* stop count of CNT */
|
||||
CCSR_f.STOP = 1u;
|
||||
|
||||
/* set count clock div of CNT */
|
||||
CCSR_f.CKDIV = pstcInitCfg->enClkDiv;
|
||||
|
||||
/* set cnt mode */
|
||||
CCSR_f.MODE = pstcInitCfg->enCntMode;
|
||||
|
||||
/* set buffer enable bit */
|
||||
CCSR_f.BUFEN = (uint16_t)(pstcInitCfg->enBufferCmd);
|
||||
|
||||
/* set external clock enable bit */
|
||||
CCSR_f.ECKEN = (Timer4CntExtclk == pstcInitCfg->enClk) ? ((uint16_t)1u) : ((uint16_t)0u);
|
||||
|
||||
/* Set interrupt enable */
|
||||
CCSR_f.IRQZEN = (uint16_t)(pstcInitCfg->enZeroIntCmd);
|
||||
CCSR_f.IRQPEN = (uint16_t)(pstcInitCfg->enPeakIntCmd);
|
||||
|
||||
/* set intterrupt mask times */
|
||||
CVPR_f.ZIM = (uint16_t)(pstcInitCfg->enZeroIntMsk);
|
||||
CVPR_f.PIM = (uint16_t)(pstcInitCfg->enPeakIntMsk);
|
||||
|
||||
/* Set Timer4 register */
|
||||
TMR4x->CVPR_f = CVPR_f;
|
||||
TMR4x->CCSR_f = CCSR_f;
|
||||
TMR4x->CPSR = pstcInitCfg->u16Cycle;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-initialize Timer4 CNT
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval Ok De-Initialize successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_DeInit(M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Set default value */
|
||||
TMR4x->CCSR = (uint16_t)0x0050u;
|
||||
TMR4x->CNTR = (uint16_t)0x0000u;
|
||||
TMR4x->CPSR = (uint16_t)0xFFFFu;
|
||||
TMR4x->CVPR = (uint16_t)0x0000u;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Timer4 CNT clock source
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCntClk Timer4 CNT clock source
|
||||
** \arg Timer4CntPclk Uses the internal clock (PCLK) as CNT's count clock.
|
||||
** \arg Timer4CntExtclk Uses an external input clock (EXCK) as CNT's count clock.
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_SetClock(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_clk_t enCntClk)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_CNT_CLK(enCntClk));
|
||||
/* set external clock enable bit */
|
||||
TMR4x->CCSR_f.ECKEN = (uint16_t)(enCntClk);
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer4 CNT clock source
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval Timer4CntPclk Uses the internal clock (PCLK) as CNT's count clock.
|
||||
** \retval Timer4CntExtclk Uses an external input clock (EXCK) as CNT's count clock.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_timer4_cnt_clk_t TIMER4_CNT_GetClock(M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
|
||||
return (en_timer4_cnt_clk_t)(TMR4x->CCSR_f.ECKEN);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Timer4 CNT clock division
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enClkDiv Timer4 CNT clock division
|
||||
** \arg Timer4CntPclkDiv1 Timer4 CNT clock: PCLK
|
||||
** \arg Timer4CntPclkDiv2 Timer4 CNT clock: PCLK/2
|
||||
** \arg Timer4CntPclkDiv4 Timer4 CNT clock: PCLK/4
|
||||
** \arg Timer4CntPclkDiv8 Timer4 CNT clock: PCLK/8
|
||||
** \arg Timer4CntPclkDiv16 Timer4 CNT clock: PCLK/16
|
||||
** \arg Timer4CntPclkDiv32 Timer4 CNT clock: PCLK/32
|
||||
** \arg Timer4CntPclkDiv64 Timer4 CNT clock: PCLK/64
|
||||
** \arg Timer4CntPclkDiv128 Timer4 CNT clock: PCLK/128
|
||||
** \arg Timer4CntPclkDiv256 Timer4 CNT clock: PCLK/256
|
||||
** \arg Timer4CntPclkDiv512 Timer4 CNT clock: PCLK/512
|
||||
** \arg Timer4CntPclkDiv1024 Timer4 CNT clock: PCLK/1024
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_SetClockDiv(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_clk_div_t enClkDiv)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_CNT_CLK_DIV(enClkDiv));
|
||||
TMR4x->CCSR_f.CKDIV = (uint16_t)enClkDiv;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer4 CNT clock division
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval Timer4CntPclkDiv1 Timer4 CNT clock: PCLK
|
||||
** \retval Timer4CntPclkDiv2 Timer4 CNT clock: PCLK/2
|
||||
** \retval Timer4CntPclkDiv4 Timer4 CNT clock: PCLK/4
|
||||
** \retval Timer4CntPclkDiv8 Timer4 CNT clock: PCLK/8
|
||||
** \retval Timer4CntPclkDiv16 Timer4 CNT clock: PCLK/16
|
||||
** \retval Timer4CntPclkDiv32 Timer4 CNT clock: PCLK/32
|
||||
** \retval Timer4CntPclkDiv64 Timer4 CNT clock: PCLK/64
|
||||
** \retval Timer4CntPclkDiv128 Timer4 CNT clock: PCLK/128
|
||||
** \retval Timer4CntPclkDiv256 Timer4 CNT clock: PCLK/256
|
||||
** \retval Timer4CntPclkDiv512 Timer4 CNT clock: PCLK/512
|
||||
** \retval Timer4CntPclkDiv1024 Timer4 CNT clock: PCLK/1024
|
||||
**
|
||||
******************************************************************************/
|
||||
en_timer4_cnt_clk_div_t TIMER4_CNT_GetClockDiv(M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
|
||||
return (en_timer4_cnt_clk_div_t)(TMR4x->CCSR_f.CKDIV);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Timer4 CNT mode
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enMode Timer4 CNT mode
|
||||
** \arg Timer4CntSawtoothWave Timer4 count mode:sawtooth wave
|
||||
** \arg Timer4CntTriangularWave Timer4 count mode:triangular wave
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_SetMode(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_mode_t enMode)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_CNT_MODE(enMode));
|
||||
TMR4x->CCSR_f.MODE = (uint16_t)enMode;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer4 CNT mode
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval Timer4CntSawtoothWave Timer4 count mode:sawtooth wave
|
||||
** \retval Timer4CntTriangularWave Timer4 count mode:triangular wave
|
||||
**
|
||||
******************************************************************************/
|
||||
en_timer4_cnt_mode_t TIMER4_CNT_GetMode(M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
|
||||
return (en_timer4_cnt_mode_t)(TMR4x->CCSR_f.MODE);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Start Timer4 CNT
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval Ok Start successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_Start(M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
TMR4x->CCSR_f.STOP = (uint16_t)0u;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Stop Timer4 CNT
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval Ok Stop successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_Stop(M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
TMR4x->CCSR_f.STOP = (uint16_t)1u;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Timer4 CNT interrupt
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enIntType The specified type of Timer4 CNT interrupt
|
||||
** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT
|
||||
** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT
|
||||
** \param [in] enCmd DCU interrupt functional state
|
||||
** \arg Enable Enable the specified Timer4 CNT interrupt function
|
||||
** \arg Disable Disable the specified Timer4 CNT interrupt function
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter If one of following cases matches:
|
||||
** - TMR4x is invalid
|
||||
** - enIntType is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_IrqCmd(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_int_t enIntType,
|
||||
en_functional_state_t enCmd)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd));
|
||||
DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType));
|
||||
|
||||
enRet = Ok;
|
||||
switch (enIntType)
|
||||
{
|
||||
case Timer4CntZeroMatchInt:
|
||||
TMR4x->CCSR_f.IRQZEN = (uint16_t)enCmd;
|
||||
break;
|
||||
case Timer4CntPeakMatchInt:
|
||||
TMR4x->CCSR_f.IRQPEN = (uint16_t)enCmd;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer4 CNT interrupt flag
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enIntType Timer4 CNT interrupt type
|
||||
** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT
|
||||
** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT
|
||||
**
|
||||
** \retval Reset None interrupt request on Timer4 CNT
|
||||
** \retval Set Detection interrupt request on Timer4 CNT
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t TIMER4_CNT_GetIrqFlag(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_int_t enIntType)
|
||||
{
|
||||
uint16_t u16Flag = 0u;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType));
|
||||
|
||||
switch (enIntType)
|
||||
{
|
||||
case Timer4CntZeroMatchInt:
|
||||
u16Flag = TMR4x->CCSR_f.IRQZF;
|
||||
break;
|
||||
case Timer4CntPeakMatchInt:
|
||||
u16Flag = TMR4x->CCSR_f.IRQPF;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return (en_flag_status_t)u16Flag;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear Timer4 CNT interrupt flag
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enIntType Timer4 CNT interrupt type
|
||||
** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT
|
||||
** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT
|
||||
**
|
||||
** \retval Ok Clear successfully.
|
||||
** \retval ErrorInvalidParameter If one of following cases matches:
|
||||
** - TMR4x is invalid
|
||||
** - enIntType is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_int_t enIntType)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType));
|
||||
|
||||
enRet = Ok;
|
||||
switch (enIntType)
|
||||
{
|
||||
case Timer4CntZeroMatchInt:
|
||||
TMR4x->CCSR_f.IRQZF = (uint16_t)0u;
|
||||
break;
|
||||
case Timer4CntPeakMatchInt:
|
||||
TMR4x->CCSR_f.IRQPF = (uint16_t)0u;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set the cycle value of the specified Timer4 CNT.
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] u16Cycle The Timer4 CNT cycle value
|
||||
** \arg number of 16bit
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_SetCycleVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Cycle)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
TMR4x->CPSR = u16Cycle;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get the cycle value of the specified Timer4 CNT.
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval The cycle value of the specified Timer4 CNT.
|
||||
**
|
||||
******************************************************************************/
|
||||
uint16_t TIMER4_CNT_GetCycleVal(const M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
|
||||
return TMR4x->CPSR;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear Timer4 CNT register CNTR
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval Ok Clear successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_ClearCountVal(M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
TMR4x->CCSR_f.CLEAR = (uint16_t)1u;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set the current count value of the specified Timer4 CNT.
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] u16Count The Timer4 CNT current count value
|
||||
** \arg number of 16bit
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_SetCountVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Count)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
TMR4x->CNTR = u16Count;
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer4 CNT current count value
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval The current count value of the specified Timer4 CNT.
|
||||
**
|
||||
******************************************************************************/
|
||||
uint16_t TIMER4_CNT_GetCountVal(const M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
|
||||
return TMR4x->CNTR;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Timer4 CNT interrupt mask times
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enIntType Timer4 CNT interrupt type
|
||||
** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT
|
||||
** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT
|
||||
** \param [in] enMaskTimes Timer4 CNT interrupt mask times
|
||||
** \arg Timer4CntIntMask0 CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak.
|
||||
** \arg Timer4CntIntMask1 CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count).
|
||||
** \arg Timer4CntIntMask2 CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count).
|
||||
** \arg Timer4CntIntMask3 CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count).
|
||||
** \arg Timer4CntIntMask4 CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count).
|
||||
** \arg Timer4CntIntMask5 CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count).
|
||||
** \arg Timer4CntIntMask6 CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count).
|
||||
** \arg Timer4CntIntMask7 CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count).
|
||||
** \arg Timer4CntIntMask8 CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count).
|
||||
** \arg Timer4CntIntMask9 CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count).
|
||||
** \arg Timer4CntIntMask10 CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count).
|
||||
** \arg Timer4CntIntMask11 CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count).
|
||||
** \arg Timer4CntIntMask12 CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count).
|
||||
** \arg Timer4CntIntMask13 CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count).
|
||||
** \arg Timer4CntIntMask14 CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count).
|
||||
** \arg Timer4CntIntMask15 CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count).
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_CNT_SetIntMaskTimes(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_int_t enIntType,
|
||||
en_timer4_cnt_int_mask_t enMaskTimes)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType));
|
||||
DDL_ASSERT(IS_VALID_CNT_INT_MSK(enMaskTimes));
|
||||
|
||||
enRet = Ok;
|
||||
switch (enIntType)
|
||||
{
|
||||
case Timer4CntZeroMatchInt:
|
||||
TMR4x->CVPR_f.ZIM = (uint16_t)enMaskTimes;
|
||||
break;
|
||||
case Timer4CntPeakMatchInt:
|
||||
TMR4x->CVPR_f.PIM = (uint16_t)enMaskTimes;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer4 CNT interrupt mask times
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enIntType Timer4 CNT interrupt type
|
||||
** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT
|
||||
** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT
|
||||
**
|
||||
** \retval Timer4CntIntMask0 CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak.
|
||||
** \retval Timer4CntIntMask1 CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count).
|
||||
** \retval Timer4CntIntMask2 CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count).
|
||||
** \retval Timer4CntIntMask3 CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count).
|
||||
** \retval Timer4CntIntMask4 CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count).
|
||||
** \retval Timer4CntIntMask5 CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count).
|
||||
** \retval Timer4CntIntMask6 CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count).
|
||||
** \retval Timer4CntIntMask7 CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count).
|
||||
** \retval Timer4CntIntMask8 CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count).
|
||||
** \retval Timer4CntIntMask9 CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count).
|
||||
** \retval Timer4CntIntMask10 CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count).
|
||||
** \retval Timer4CntIntMask11 CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count).
|
||||
** \retval Timer4CntIntMask12 CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count).
|
||||
** \retval Timer4CntIntMask13 CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count).
|
||||
** \retval Timer4CntIntMask14 CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count).
|
||||
** \retval Timer4CntIntMask15 CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count).
|
||||
**
|
||||
******************************************************************************/
|
||||
en_timer4_cnt_int_mask_t TIMER4_CNT_GetIntMaskTimes(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_cnt_int_t enIntType)
|
||||
{
|
||||
uint16_t u16MaskTimes = 0u;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType));
|
||||
|
||||
switch (enIntType)
|
||||
{
|
||||
case Timer4CntZeroMatchInt:
|
||||
u16MaskTimes = TMR4x->CVPR_f.ZIM;
|
||||
break;
|
||||
case Timer4CntPeakMatchInt:
|
||||
u16MaskTimes = TMR4x->CVPR_f.PIM;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return (en_timer4_cnt_int_mask_t)u16MaskTimes;
|
||||
}
|
||||
|
||||
//@} // Timer4CntGroup
|
||||
|
||||
#endif /* DDL_TIMER4_CNT_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,278 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer4_emb.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer4EmbGroup Timer4EMB description @endlink
|
||||
**
|
||||
** - 2018-11-02 CDT First version for Device Driver Library of Timer4EMB.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_timer4_emb.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_TIMER4_EMB_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup Timer4EmbGroup
|
||||
******************************************************************************/
|
||||
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*!< Parameter validity check for Timer4 unit */
|
||||
#define IS_VALID_TIMER4(__TMRx__) \
|
||||
( (M4_TMR41 == (__TMRx__)) || \
|
||||
(M4_TMR42 == (__TMRx__)) || \
|
||||
(M4_TMR43 == (__TMRx__)))
|
||||
|
||||
/*!< Parameter valid check for EMB HOLD mode. */
|
||||
#define IS_VALID_EMB_HOLD_MODE(x) \
|
||||
( (EmbHoldPwm == (x)) || \
|
||||
(EmbChangePwm == (x)))
|
||||
|
||||
/*!< Parameter valid check for EMB state. */
|
||||
#define IS_VALID_EMB_STATE(x) \
|
||||
( (EmbTrigPwmOutputHiz == (x)) || \
|
||||
(EmbTrigPwmOutputNormal == (x)) || \
|
||||
(EmbTrigPwmOutputLowLevel == (x)) || \
|
||||
(EmbTrigPwmOutputHighLevel == (x)))
|
||||
|
||||
/*!< Timer4x ECER register address. */
|
||||
#define TMR4_ECERx(__TMRx__) \
|
||||
( (M4_TMR41 == (__TMRx__)) ? &M4_TMR4_CR->ECER1 : \
|
||||
((M4_TMR42 == (__TMRx__)) ? &M4_TMR4_CR->ECER2 : &M4_TMR4_CR->ECER3))
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Initialize Timer4 EMB
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] pstcInitCfg The pointer of EMB configure structure
|
||||
** \arg This parameter detail refer @ref stc_timer4_emb_init_t
|
||||
**
|
||||
** \retval Ok Initialize successfully
|
||||
** \retval ErrorInvalidParameter If one of following conditions are met:
|
||||
** - TMR4x is invalid
|
||||
** - pstcInitCfg == NULL
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_EMB_Init(M4_TMR4_TypeDef *TMR4x,
|
||||
const stc_timer4_emb_init_t *pstcInitCfg)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x && pstcInitCfg pointer */
|
||||
if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_EMB_STATE(pstcInitCfg->enEmbState));
|
||||
DDL_ASSERT(IS_VALID_EMB_HOLD_MODE(pstcInitCfg->enPwmHold));
|
||||
|
||||
/* Set EMB HOLD mode */
|
||||
TMR4x->ECSR_f.HOLD = (uint16_t)(pstcInitCfg->enPwmHold);
|
||||
|
||||
/* Set EMB state */
|
||||
*(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)(pstcInitCfg->enEmbState);
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-initialize Timer4 EMB
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval Ok De-Initialize successfully
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_EMB_DeInit(M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Set reset value(0x0000) to register ESCR */
|
||||
TMR4x->ECSR = 0u;
|
||||
|
||||
/* Set reset value(0x0000) to register ECER */
|
||||
*(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)0ul;
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Timer4 EMB HOLD mode
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enHoldMode EMB HOLD mode
|
||||
** \arg EmbChangePwm Don't hold PWM output when EMB signal occurs
|
||||
** \arg EmbHoldPwm Hold PWM output when EMB signal occurs
|
||||
**
|
||||
** \retval Ok Set successfully
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_EMB_SetHoldMode(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_emb_hold_mode_t enHoldMode)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_EMB_HOLD_MODE(enHoldMode));
|
||||
|
||||
/* Set EMB HOLD mode */
|
||||
TMR4x->ECSR_f.HOLD = (uint16_t)enHoldMode;
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer4 EMB HOLD mode
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval EmbChangePwm Don't hold PWM output when EMB signal occurs
|
||||
** \retval EmbHoldPwm Hold PWM output when EMB signal occurs
|
||||
**
|
||||
******************************************************************************/
|
||||
en_timer4_emb_hold_mode_t TIMER4_EMB_GetHoldMode(M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
|
||||
return (en_timer4_emb_hold_mode_t)(TMR4x->ECSR_f.HOLD);
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Timer4 EMB state
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enEmbState EMB state
|
||||
** \arg EmbTrigPwmOutputNormal PWM output signal normally.
|
||||
** \arg EmbTrigPwmOutputHiz PWM output Hiz signal.
|
||||
** \arg EmbTrigPwmOutputLowLevel PWM output low level signal.
|
||||
** \arg EmbTrigPwmOutputHighLevel PWM output high level signal.
|
||||
**
|
||||
** \retval Ok Set successfully
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_EMB_SetState(const M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_emb_state_t enEmbState)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_EMB_STATE(enEmbState));
|
||||
|
||||
/* Set EMB state */
|
||||
*(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)enEmbState;
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer4 EMB state
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
**
|
||||
** \retval EmbTrigPwmOutputNormal PWM output signal normally.
|
||||
** \retval EmbTrigPwmOutputHiz PWM output Hiz signal.
|
||||
** \retval EmbTrigPwmOutputLowLevel PWM output low level signal.
|
||||
** \retval EmbTrigPwmOutputHighLevel PWM output high level signal.
|
||||
**
|
||||
******************************************************************************/
|
||||
en_timer4_emb_state_t TIMER4_EMB_GetState(const M4_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
|
||||
return *(__IO en_timer4_emb_state_t *)TMR4_ECERx(TMR4x);
|
||||
}
|
||||
|
||||
//@} // Timer4EmbGroup
|
||||
|
||||
#endif /* DDL_TIMER4_EMB_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,600 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer4_pwm.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer4PwmGroup Timer4PWM description @endlink
|
||||
**
|
||||
** - 2018-11-02 CDT First version for Device Driver Library of Timer4PWM.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_timer4_pwm.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_TIMER4_PWM_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup Timer4PwmGroup
|
||||
******************************************************************************/
|
||||
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*!< Parameter validity check for Timer4 unit */
|
||||
#define IS_VALID_TIMER4(__TMRx__) \
|
||||
( (M4_TMR41 == (__TMRx__)) || \
|
||||
(M4_TMR42 == (__TMRx__)) || \
|
||||
(M4_TMR43 == (__TMRx__)))
|
||||
|
||||
/*!< Parameter validity check for PWM channel */
|
||||
#define IS_VALID_PWM_CH(x) \
|
||||
( (Timer4PwmU == (x)) || \
|
||||
(Timer4PwmV == (x)) || \
|
||||
(Timer4PwmW == (x)))
|
||||
|
||||
/*!< Parameter validity check for PWM mode */
|
||||
#define IS_VALID_PWM_MODE(x) \
|
||||
( (PwmThroughMode == (x)) || \
|
||||
(PwmDeadTimerMode == (x)) || \
|
||||
(PwmDeadTimerFilterMode == (x)))
|
||||
|
||||
/*!< Parameter valid check for PWM output state. */
|
||||
#define IS_VALID_PWM_OUTPUT_STATE(x) \
|
||||
( (PwmHPwmLHold == (x)) || \
|
||||
(PwmHPwmLReverse == (x)) || \
|
||||
(PwmHReversePwmLHold == (x)) || \
|
||||
(PwmHHoldPwmLReverse == (x)))
|
||||
|
||||
/*!< Parameter valid check for PWM clock division. */
|
||||
#define IS_VALID_PWM_CLK_DIV(x) \
|
||||
( (PwmPlckDiv1 == (x)) || \
|
||||
(PwmPlckDiv2 == (x)) || \
|
||||
(PwmPlckDiv4 == (x)) || \
|
||||
(PwmPlckDiv8 == (x)) || \
|
||||
(PwmPlckDiv16 == (x)) || \
|
||||
(PwmPlckDiv32 == (x)) || \
|
||||
(PwmPlckDiv64 == (x)) || \
|
||||
(PwmPlckDiv128 == (x)))
|
||||
|
||||
/*!< Get the specified register address of the specified Timer4 unit */
|
||||
#define TMR4_RCSRx(__TMR4x__) ((uint32_t)&(__TMR4x__)->RCSR)
|
||||
#define TMR4_POCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->POCRU + ((uint32_t)(__CH__))*4ul)
|
||||
#define TMR4_PDARx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PDARU + ((uint32_t)(__CH__))*8ul)
|
||||
#define TMR4_PDBRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PDBRU + ((uint32_t)(__CH__))*8ul)
|
||||
#define TMR4_PFSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PFSRU + ((uint32_t)(__CH__))*8ul)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Initialize a couple PWM channels
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Channel of PWM
|
||||
** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL
|
||||
** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL
|
||||
** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL
|
||||
** \param [in] pstcInitCfg The pointer of PWM configure structure
|
||||
** \arg This parameter detail refer @ref stc_timer4_pwm_init_t
|
||||
**
|
||||
** \retval Ok Initialize successfully
|
||||
** \retval ErrorInvalidParameter If one of following conditions are met:
|
||||
** - TMR4x is invalid
|
||||
** - pstcInitCfg == NULL
|
||||
** - enCh is invalid
|
||||
** - Other invalid configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_PWM_Init(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh,
|
||||
const stc_timer4_pwm_init_t *pstcInitCfg)
|
||||
{
|
||||
__IO stc_tmr4_pocr_field_t *pstcPOCR_f = NULL;
|
||||
__IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL;
|
||||
en_result_t enRet = Ok;
|
||||
|
||||
/* Check TMR4x && pstcInitCfg pointer */
|
||||
if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_PWM_MODE(pstcInitCfg->enMode));
|
||||
DDL_ASSERT(IS_VALID_PWM_CLK_DIV(pstcInitCfg->enClkDiv));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enRtIntMaskCmd));
|
||||
DDL_ASSERT(IS_VALID_PWM_OUTPUT_STATE(pstcInitCfg->enOutputState));
|
||||
|
||||
/* Get pointer of current channel PWM register address */
|
||||
pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x);
|
||||
pstcPOCR_f = (__IO stc_tmr4_pocr_field_t*)TMR4_POCRx(TMR4x, enCh);
|
||||
|
||||
/* Configure PWM mode */
|
||||
pstcPOCR_f->PWMMD = (uint16_t)(pstcInitCfg->enMode);
|
||||
|
||||
/* Configure PWM mode */
|
||||
pstcPOCR_f->LVLS = (uint16_t)(pstcInitCfg->enOutputState);
|
||||
|
||||
/* Set timer clock division */
|
||||
pstcPOCR_f->DIVCK = (uint16_t)(pstcInitCfg->enClkDiv);
|
||||
|
||||
/* Set interrupt mask */
|
||||
switch (enCh)
|
||||
{
|
||||
case Timer4PwmU:
|
||||
pstcRCSR_f->RTIDU = (uint16_t)(pstcInitCfg->enRtIntMaskCmd);
|
||||
break;
|
||||
case Timer4PwmV:
|
||||
pstcRCSR_f->RTIDV = (uint16_t)(pstcInitCfg->enRtIntMaskCmd);
|
||||
break;
|
||||
case Timer4PwmW:
|
||||
pstcRCSR_f->RTIDW = (uint16_t)(pstcInitCfg->enRtIntMaskCmd);
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
enRet = ErrorInvalidParameter;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-Initialize a couple PWM channels
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Channel of PWM
|
||||
** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL
|
||||
** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL
|
||||
** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL
|
||||
**
|
||||
** \retval Ok De-Initialize successfully.
|
||||
** \retval ErrorInvalidParameter If one of following conditions are met:
|
||||
** - TMR4x is invalid
|
||||
** - enCh out of range
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_PWM_DeInit(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh)
|
||||
{
|
||||
en_result_t enRet = Ok;
|
||||
__IO uint16_t *pu16PDAR = NULL;
|
||||
__IO uint16_t *pu16PDBR = NULL;
|
||||
__IO uint16_t *pu16PFSR = NULL;
|
||||
__IO stc_tmr4_pocr_field_t *pstcPOCR_f = NULL;
|
||||
__IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Get pointer of current channel PWM register address */
|
||||
pu16PDAR = (__IO uint16_t*)TMR4_PDARx(TMR4x, enCh);
|
||||
pu16PDBR = (__IO uint16_t*)TMR4_PDBRx(TMR4x, enCh);
|
||||
pu16PFSR = (__IO uint16_t*)TMR4_PFSRx(TMR4x, enCh);
|
||||
pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x);
|
||||
pstcPOCR_f = (__IO stc_tmr4_pocr_field_t*)TMR4_POCRx(TMR4x, enCh);
|
||||
|
||||
*pu16PDAR = (uint16_t)0u;
|
||||
*pu16PDBR = (uint16_t)0u;
|
||||
*pu16PFSR = (uint16_t)0u;
|
||||
pstcPOCR_f->DIVCK = (uint16_t)0u;
|
||||
pstcPOCR_f->LVLS = (uint16_t)0u;
|
||||
pstcPOCR_f->PWMMD = (uint16_t)0u;
|
||||
|
||||
switch (enCh)
|
||||
{
|
||||
case Timer4PwmU:
|
||||
pstcRCSR_f->RTIDU = (uint16_t)0u;
|
||||
break;
|
||||
case Timer4PwmV:
|
||||
pstcRCSR_f->RTIDV = (uint16_t)0u;
|
||||
break;
|
||||
case Timer4PwmW:
|
||||
pstcRCSR_f->RTIDW = (uint16_t)0u;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
enRet = ErrorInvalidParameter;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Start PWM timer
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Channel of PWM
|
||||
** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL
|
||||
** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL
|
||||
** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL
|
||||
**
|
||||
** \retval Ok Start timer successfully
|
||||
** \retval ErrorInvalidParameter If one of following conditions are met:
|
||||
** - TMR4x is invalid
|
||||
** - enCh out of range
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_PWM_StartTimer(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
__IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
enRet = Ok;
|
||||
/* Get pointer of current channel PWM register address */
|
||||
pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x);
|
||||
|
||||
switch (enCh)
|
||||
{
|
||||
case Timer4PwmU:
|
||||
pstcRCSR_f->RTEU = (uint16_t)1u;
|
||||
break;
|
||||
case Timer4PwmV:
|
||||
pstcRCSR_f->RTEV = (uint16_t)1u;
|
||||
break;
|
||||
case Timer4PwmW:
|
||||
pstcRCSR_f->RTEW = (uint16_t)1u;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Stop PWM timer
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Channel of PWM
|
||||
** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL
|
||||
** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL
|
||||
** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL
|
||||
**
|
||||
** \retval Ok Stop timer successfully
|
||||
** \retval ErrorInvalidParameter If one of following conditions are met:
|
||||
** - TMR4x is invalid
|
||||
** - enCh out of range
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_PWM_StopTimer(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
__IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_PWM_CH(enCh));
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
enRet = Ok;
|
||||
|
||||
/* Get pointer of current channel PWM register address */
|
||||
pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x);
|
||||
switch (enCh)
|
||||
{
|
||||
case Timer4PwmU:
|
||||
pstcRCSR_f->RTSU = (uint16_t)1u;
|
||||
break;
|
||||
case Timer4PwmV:
|
||||
pstcRCSR_f->RTSV = (uint16_t)1u;
|
||||
break;
|
||||
case Timer4PwmW:
|
||||
pstcRCSR_f->RTSW = (uint16_t)1u;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get PWM reload-timer interrupt flag
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Channel of PWM
|
||||
** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL
|
||||
** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL
|
||||
** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL
|
||||
**
|
||||
** \retval Reset None interrupt request on PWM reload-timer
|
||||
** \retval Set Detection interrupt request on PWM reload-timer
|
||||
**
|
||||
******************************************************************************/
|
||||
en_flag_status_t TIMER4_PWM_GetIrqFlag(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh)
|
||||
{
|
||||
uint16_t u16Flag = 0u;
|
||||
__IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_PWM_CH(enCh));
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
|
||||
/* Get pointer of current channel PWM register address */
|
||||
pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x);
|
||||
|
||||
switch (enCh)
|
||||
{
|
||||
case Timer4PwmU:
|
||||
u16Flag = pstcRCSR_f->RTIFU;
|
||||
break;
|
||||
case Timer4PwmV:
|
||||
u16Flag = pstcRCSR_f->RTIFV;
|
||||
break;
|
||||
case Timer4PwmW:
|
||||
u16Flag = pstcRCSR_f->RTIFW;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return (en_flag_status_t)u16Flag;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Clear PWM reload-timer interrupt flag
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Channel of PWM
|
||||
** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL
|
||||
** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL
|
||||
** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL
|
||||
**
|
||||
** \retval Ok PWM reload-timer interrupt flag is clear
|
||||
** \retval ErrorInvalidParameter If one of following conditions are met:
|
||||
** - TMR4x is invalid
|
||||
** - enCh out of range
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_PWM_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
__IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_PWM_CH(enCh));
|
||||
|
||||
enRet = Ok;
|
||||
/* Get pointer of current channel PWM register address */
|
||||
pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x);
|
||||
switch (enCh)
|
||||
{
|
||||
case Timer4PwmU:
|
||||
pstcRCSR_f->RTICU = (uint16_t)1u;
|
||||
break;
|
||||
case Timer4PwmV:
|
||||
pstcRCSR_f->RTICV = (uint16_t)1u;
|
||||
break;
|
||||
case Timer4PwmW:
|
||||
pstcRCSR_f->RTICW = (uint16_t)1u;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Write timer count cycle
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Channel of PWM
|
||||
** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL
|
||||
** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL
|
||||
** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL
|
||||
** \param [in] u16PDAR PDAR value
|
||||
** \arg 0~65535
|
||||
** \param [in] u16PDBR PDBR value
|
||||
** \arg 0~65535
|
||||
**
|
||||
** \retval Ok Timer count cycle is written
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_PWM_WriteDeadRegionValue(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh,
|
||||
uint16_t u16PDAR,
|
||||
uint16_t u16PDBR)
|
||||
{
|
||||
__IO uint16_t *pu16PDAR = NULL;
|
||||
__IO uint16_t *pu16PDBR = NULL;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_PWM_CH(enCh));
|
||||
|
||||
/* Get pointer of current channel PWM register address */
|
||||
pu16PDAR = (__IO uint16_t *)TMR4_PDARx(TMR4x, enCh);
|
||||
pu16PDBR = (__IO uint16_t *)TMR4_PDBRx(TMR4x, enCh);
|
||||
|
||||
/* set the register */
|
||||
*pu16PDAR = u16PDAR;
|
||||
*pu16PDBR = u16PDBR;
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Read dead region count value
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Channel of PWM
|
||||
** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL
|
||||
** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL
|
||||
** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL
|
||||
** \param [out] u16PDAR Pointer of uint16_t type
|
||||
** \arg 0~65535
|
||||
** \param [out] u16PDBR Pointer of uint16_t type
|
||||
** \arg 0~65535
|
||||
**
|
||||
** \retval Ok Read successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_PWM_ReadDeadRegionValue(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh,
|
||||
uint16_t *u16PDAR,
|
||||
uint16_t *u16PDBR)
|
||||
{
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_PWM_CH(enCh));
|
||||
|
||||
/* Get pointer of current channel PWM register address */
|
||||
*u16PDAR = *(__IO uint16_t *)TMR4_PDARx(TMR4x, enCh);
|
||||
*u16PDBR = *(__IO uint16_t *)TMR4_PDBRx(TMR4x, enCh);
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set cycle of PWM timer
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Channel of PWM
|
||||
** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL
|
||||
** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL
|
||||
** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL
|
||||
** \param [in] u16Count PWM pulse counter value
|
||||
** \arg 0~65535
|
||||
**
|
||||
** \retval Ok Cycle of PWM timer is set
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_PWM_SetFilterCountValue(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_pwm_ch_t enCh,
|
||||
uint16_t u16Count)
|
||||
{
|
||||
__IO uint16_t *pu16PFSR = NULL;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_PWM_CH(enCh));
|
||||
|
||||
/* Get pointer of current channel PWM register address */
|
||||
pu16PFSR = (__IO uint16_t*)TMR4_PFSRx(TMR4x, enCh);
|
||||
*pu16PFSR =u16Count;
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
//@} // Timer4PwmGroup
|
||||
|
||||
#endif /* DDL_TIMER4_PWM_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,593 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_timer4_sevt.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Timer4SevtGroup Timer4SEVT description @endlink
|
||||
**
|
||||
** - 2018-11-02 CDT First version for Device Driver Library of Timer4SEVT.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32f460_timer4_sevt.h"
|
||||
#include "hc32f460_utility.h"
|
||||
|
||||
#if (DDL_TIMER4_SEVT_ENABLE == DDL_ON)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup Timer4SevtGroup
|
||||
******************************************************************************/
|
||||
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*!< Parameter validity check for Timer4 unit */
|
||||
#define IS_VALID_TIMER4(__TMRx__) \
|
||||
( (M4_TMR41 == (__TMRx__)) || \
|
||||
(M4_TMR42 == (__TMRx__)) || \
|
||||
(M4_TMR43 == (__TMRx__)))
|
||||
|
||||
/*!< Parameter validity check for SEVT channel */
|
||||
#define IS_VALID_SEVT_CH(x) \
|
||||
( (Timer4SevtCh0 == (x)) || \
|
||||
(Timer4SevtCh1 == (x)) || \
|
||||
(Timer4SevtCh2 == (x)) || \
|
||||
(Timer4SevtCh3 == (x)) || \
|
||||
(Timer4SevtCh4 == (x)) || \
|
||||
(Timer4SevtCh5 == (x)))
|
||||
|
||||
/*!< Parameter validity check for adct buffer mode */
|
||||
#define IS_VALID_SEVT_BUF_MODE(x) \
|
||||
( (SevtBufDisable == (x)) || \
|
||||
(SevtBufCntZero == (x)) || \
|
||||
(SevtBufCntPeak == (x)) || \
|
||||
(SevtBufCntZeroOrCntPeak == (x)) || \
|
||||
(SevtBufCntZeroZicZero == (x)) || \
|
||||
(SevtBufCntPeakPicZero == (x)) || \
|
||||
(SevtBufCntZeroZicZeroOrCntPeakPicZero == (x)))
|
||||
|
||||
/*!< Parameter validity check for SEVT trigger event */
|
||||
#define IS_VALID_SEVT_TRG_EVT(x) \
|
||||
( (SevtTrgEvtSCMUH == (x)) || \
|
||||
(SevtTrgEvtSCMUL == (x)) || \
|
||||
(SevtTrgEvtSCMVH == (x)) || \
|
||||
(SevtTrgEvtSCMVL == (x)) || \
|
||||
(SevtTrgEvtSCMWH == (x)) || \
|
||||
(SevtTrgEvtSCMWL == (x)))
|
||||
|
||||
/*!< Parameter validity check for SEVT OCCR selection */
|
||||
#define IS_VALID_SEVT_OCCR_SEL(x) \
|
||||
( (SevtSelOCCRxh == (x)) || \
|
||||
(SevtSelOCCRxl == (x)))
|
||||
|
||||
/*!< Parameter validity check for SEVT running mode */
|
||||
#define IS_VALID_SEVT_MODE(x) \
|
||||
( (SevtDelayTrigMode == (x)) || \
|
||||
(SevtCompareTrigMode == (x)))
|
||||
|
||||
/*!< Parameter validity check for SEVT mask time */
|
||||
#define IS_VALID_SEVT_MSK(x) \
|
||||
( (Timer4SevtMask0 == (x)) || \
|
||||
(Timer4SevtMask1 == (x)) || \
|
||||
(Timer4SevtMask2 == (x)) || \
|
||||
(Timer4SevtMask3 == (x)) || \
|
||||
(Timer4SevtMask4 == (x)) || \
|
||||
(Timer4SevtMask5 == (x)) || \
|
||||
(Timer4SevtMask6 == (x)) || \
|
||||
(Timer4SevtMask7 == (x)) || \
|
||||
(Timer4SevtMask8 == (x)) || \
|
||||
(Timer4SevtMask9 == (x)) || \
|
||||
(Timer4SevtMask10 == (x)) || \
|
||||
(Timer4SevtMask11 == (x)) || \
|
||||
(Timer4SevtMask12 == (x)) || \
|
||||
(Timer4SevtMask13 == (x)) || \
|
||||
(Timer4SevtMask14 == (x)) || \
|
||||
(Timer4SevtMask15 == (x)))
|
||||
|
||||
/*!< Get the specified register address of the specified Timer4 unit */
|
||||
#define TMR4_SCCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCCRUH + ((uint32_t)(__CH__))*4ul)
|
||||
#define TMR4_SCSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCSRUH + ((uint32_t)(__CH__))*4ul)
|
||||
#define TMR4_SCMRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCMRUH + ((uint32_t)(__CH__))*4ul)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Initialize a Special-Event channel
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Timer4 SEVT channel
|
||||
** \arg Timer4SevtCh0 Timer4 SEVT channel:0
|
||||
** \arg Timer4SevtCh1 Timer4 SEVT channel:1
|
||||
** \arg Timer4SevtCh2 Timer4 SEVT channel:2
|
||||
** \arg Timer4SevtCh3 Timer4 SEVT channel:3
|
||||
** \arg Timer4SevtCh4 Timer4 SEVT channel:4
|
||||
** \arg Timer4SevtCh5 Timer4 SEVT channel:5
|
||||
** \param [in] pstcInitCfg The pointer of SEVT configure structure
|
||||
** \arg This parameter detail refer @ref stc_timer4_sevt_init_t
|
||||
**
|
||||
** \retval Ok Initialize successfully
|
||||
** \retval ErrorInvalidParameter If one of following conditions are met:
|
||||
** - TMR4x is invalid
|
||||
** - pstcInitCfg == NULL
|
||||
** - enCh is invalid
|
||||
** - Other invalid configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_SEVT_Init(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh,
|
||||
const stc_timer4_sevt_init_t *pstcInitCfg)
|
||||
{
|
||||
__IO uint16_t *pu16SCCR = NULL;
|
||||
__IO stc_tmr4_scsr_field_t stcSCSR_f;
|
||||
__IO stc_tmr4_scmr_field_t stcSCMR_f;
|
||||
__IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL;
|
||||
__IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x && pstcInitCfg pointer */
|
||||
if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_SEVT_CH(enCh));
|
||||
DDL_ASSERT(IS_VALID_SEVT_MODE(pstcInitCfg->enMode));
|
||||
DDL_ASSERT(IS_VALID_SEVT_BUF_MODE(pstcInitCfg->enBuf));
|
||||
DDL_ASSERT(IS_VALID_SEVT_MSK(pstcInitCfg->enMaskTimes));
|
||||
DDL_ASSERT(IS_VALID_SEVT_TRG_EVT(pstcInitCfg->enTrigEvt));
|
||||
DDL_ASSERT(IS_VALID_SEVT_OCCR_SEL(pstcInitCfg->enOccrSel));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpAmcZicCmd));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpAmcPicCmd));
|
||||
|
||||
enRet = Ok;
|
||||
/* Get actual address of register list of current channel */
|
||||
pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh);
|
||||
pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh);
|
||||
pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh);
|
||||
|
||||
/* Configure default parameter */
|
||||
*pu16SCCR = (uint16_t)0u;
|
||||
*(__IO uint16_t*)pstcSCSR_f = (uint16_t)0x0000u;
|
||||
*(__IO uint16_t*)pstcSCMR_f = (uint16_t)0xFF00u;
|
||||
|
||||
switch (pstcInitCfg->enBuf)
|
||||
{
|
||||
case SevtBufDisable:
|
||||
stcSCSR_f.BUFEN = (uint16_t)0u;
|
||||
stcSCSR_f.LMC = (uint16_t)0u;
|
||||
break;
|
||||
case SevtBufCntZero:
|
||||
stcSCSR_f.BUFEN = (uint16_t)1u;
|
||||
stcSCSR_f.LMC = (uint16_t)0u;
|
||||
break;
|
||||
case SevtBufCntPeak:
|
||||
stcSCSR_f.BUFEN = (uint16_t)2u;
|
||||
stcSCSR_f.LMC = (uint16_t)0u;
|
||||
break;
|
||||
case SevtBufCntZeroOrCntPeak:
|
||||
stcSCSR_f.BUFEN = (uint16_t)3u;
|
||||
stcSCSR_f.LMC = (uint16_t)0u;
|
||||
break;
|
||||
case SevtBufCntZeroZicZero:
|
||||
stcSCSR_f.BUFEN = (uint16_t)1u;
|
||||
stcSCSR_f.LMC = (uint16_t)1u;
|
||||
break;
|
||||
case SevtBufCntPeakPicZero:
|
||||
stcSCSR_f.BUFEN = (uint16_t)2u;
|
||||
stcSCSR_f.LMC = (uint16_t)1u;
|
||||
break;
|
||||
case SevtBufCntZeroZicZeroOrCntPeakPicZero:
|
||||
stcSCSR_f.BUFEN = (uint16_t)3u;
|
||||
stcSCSR_f.LMC = (uint16_t)1u;
|
||||
break;
|
||||
default:
|
||||
enRet = ErrorInvalidParameter;
|
||||
break;
|
||||
}
|
||||
|
||||
if (Ok == enRet)
|
||||
{
|
||||
/* Configure start trigger output channel number */
|
||||
stcSCSR_f.EVTOS = (uint16_t)(pstcInitCfg->enTrigEvt);
|
||||
|
||||
/* Select SEVT running mode */
|
||||
stcSCSR_f.EVTMS = (uint16_t)(pstcInitCfg->enMode);
|
||||
|
||||
/* select OCO OCCR register: OCCR(x) */
|
||||
stcSCSR_f.EVTDS = (uint16_t)(pstcInitCfg->enOccrSel);
|
||||
|
||||
/* Set the comparison with CNT interrupt mask counter */
|
||||
stcSCMR_f.AMC = (uint16_t)(pstcInitCfg->enMaskTimes);
|
||||
stcSCMR_f.MZCE = (uint16_t)(pstcInitCfg->enCmpAmcZicCmd);
|
||||
stcSCMR_f.MPCE = (uint16_t)(pstcInitCfg->enCmpAmcPicCmd);
|
||||
|
||||
*pstcSCSR_f = stcSCSR_f;
|
||||
*pstcSCMR_f = stcSCMR_f;
|
||||
}
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief De-Initialize a SEVT channel
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Timer4 SEVT channel
|
||||
** \arg Timer4SevtCh0 Timer4 SEVT channel:0
|
||||
** \arg Timer4SevtCh1 Timer4 SEVT channel:1
|
||||
** \arg Timer4SevtCh2 Timer4 SEVT channel:2
|
||||
** \arg Timer4SevtCh3 Timer4 SEVT channel:3
|
||||
** \arg Timer4SevtCh4 Timer4 SEVT channel:4
|
||||
** \arg Timer4SevtCh5 Timer4 SEVT channel:5
|
||||
**
|
||||
** \retval Ok De-Initialize successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_SEVT_DeInit(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh)
|
||||
{
|
||||
__IO uint16_t *pu16SCCR = NULL;
|
||||
__IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL;
|
||||
__IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_SEVT_CH(enCh));
|
||||
|
||||
/* Get actual address of register list of current channel */
|
||||
pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh);
|
||||
pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh);
|
||||
pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh);
|
||||
|
||||
/* Configure default parameter */
|
||||
*pu16SCCR = 0u;
|
||||
*(__IO uint16_t*)pstcSCSR_f = (uint16_t)0x0000u;
|
||||
*(__IO uint16_t*)pstcSCMR_f = (uint16_t)0xFF00u;
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Timer4 SEVT trigger event.
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Timer4 SEVT channel
|
||||
** \arg Timer4SevtCh0 Timer4 SEVT channel:0
|
||||
** \arg Timer4SevtCh1 Timer4 SEVT channel:1
|
||||
** \arg Timer4SevtCh2 Timer4 SEVT channel:2
|
||||
** \arg Timer4SevtCh3 Timer4 SEVT channel:3
|
||||
** \arg Timer4SevtCh4 Timer4 SEVT channel:4
|
||||
** \arg Timer4SevtCh5 Timer4 SEVT channel:5
|
||||
** \param [in] enTrgEvt Timer4 Special-EVT Event
|
||||
** \arg SevtTrgEvtSCMUH Timer4 Special-EVT Event: TMR4_Ux_SCMUH
|
||||
** \arg SevtTrgEvtSCMUL Timer4 Special-EVT Event: TMR4_Ux_SCMUL
|
||||
** \arg SevtTrgEvtSCMVH Timer4 Special-EVT Event: TMR4_Ux_SCMVH
|
||||
** \arg SevtTrgEvtSCMVL Timer4 Special-EVT Event: TMR4_Ux_SCMVL
|
||||
** \arg SevtTrgEvtSCMWH Timer4 Special-EVT Event: TMR4_Ux_SCMWH
|
||||
** \arg SevtTrgEvtSCMWL Timer4 Special-EVT Event: TMR4_Ux_SCMWL
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_SEVT_SetTriggerEvent(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh,
|
||||
en_timer4_sevt_trigger_evt_t enTrgEvt)
|
||||
{
|
||||
__IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_SEVT_CH(enCh));
|
||||
DDL_ASSERT(IS_VALID_SEVT_TRG_EVT(enTrgEvt));
|
||||
|
||||
/* Get actual address of register list of current channel */
|
||||
pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh);
|
||||
pstcSCSR_f->EVTOS = (uint16_t)(enTrgEvt);
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Timer4 SEVT trigger condition.
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Timer4 SEVT channel
|
||||
** \arg Timer4SevtCh0 Timer4 SEVT channel:0
|
||||
** \arg Timer4SevtCh1 Timer4 SEVT channel:1
|
||||
** \arg Timer4SevtCh2 Timer4 SEVT channel:2
|
||||
** \arg Timer4SevtCh3 Timer4 SEVT channel:3
|
||||
** \arg Timer4SevtCh4 Timer4 SEVT channel:4
|
||||
** \arg Timer4SevtCh5 Timer4 SEVT channel:5
|
||||
** \param [in] pstcTrigCond The pointer of SEVT trigger condition structure
|
||||
** \arg This parameter detail refer @ref stc_timer4_sevt_trigger_cond_t
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_SEVT_SetTriggerCond(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh,
|
||||
const stc_timer4_sevt_trigger_cond_t *pstcTrigCond)
|
||||
{
|
||||
__IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_SEVT_CH(enCh));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enUpMatchCmd));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enZeroMatchCmd));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enDownMatchCmd));
|
||||
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enPeakMatchCmd));
|
||||
|
||||
/* Get actual address of register list of current channel */
|
||||
pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh);
|
||||
pstcSCSR_f->PEN = (uint16_t)(pstcTrigCond->enPeakMatchCmd);
|
||||
pstcSCSR_f->ZEN = (uint16_t)(pstcTrigCond->enZeroMatchCmd);
|
||||
pstcSCSR_f->UEN = (uint16_t)(pstcTrigCond->enUpMatchCmd);
|
||||
pstcSCSR_f->DEN = (uint16_t)(pstcTrigCond->enDownMatchCmd);
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Write compare or delay value to Timer4 SEVT
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Timer4 SEVT channel
|
||||
** \arg Timer4SevtCh0 Timer4 SEVT channel:0
|
||||
** \arg Timer4SevtCh1 Timer4 SEVT channel:1
|
||||
** \arg Timer4SevtCh2 Timer4 SEVT channel:2
|
||||
** \arg Timer4SevtCh3 Timer4 SEVT channel:3
|
||||
** \arg Timer4SevtCh4 Timer4 SEVT channel:4
|
||||
** \arg Timer4SevtCh5 Timer4 SEVT channel:5
|
||||
** \param [in] u16SccrVal Timer4 SEVT compare value
|
||||
**
|
||||
** \retval Ok Compare or delay value to Timer4 SEVT is set
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_SEVT_WriteSCCR(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh,
|
||||
uint16_t u16SccrVal)
|
||||
{
|
||||
__IO uint16_t *pu16SCCR = NULL;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* check parameters */
|
||||
DDL_ASSERT(IS_VALID_SEVT_CH(enCh));
|
||||
|
||||
/* Get actual address of register list of current channel */
|
||||
pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh);
|
||||
*pu16SCCR = u16SccrVal;
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Read compare value or delay value of ATVR
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Timer4 SEVT channel
|
||||
** \arg Timer4SevtCh0 Timer4 SEVT channel:0
|
||||
** \arg Timer4SevtCh1 Timer4 SEVT channel:1
|
||||
** \arg Timer4SevtCh2 Timer4 SEVT channel:2
|
||||
** \arg Timer4SevtCh3 Timer4 SEVT channel:3
|
||||
** \arg Timer4SevtCh4 Timer4 SEVT channel:4
|
||||
** \arg Timer4SevtCh5 Timer4 SEVT channel:5
|
||||
**
|
||||
** \retval Value of register SCCR
|
||||
**
|
||||
******************************************************************************/
|
||||
uint16_t TIMER4_SEVT_ReadSCCR(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh)
|
||||
{
|
||||
__IO uint16_t *pu16SCCR = NULL;
|
||||
|
||||
/* check parameters */
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
DDL_ASSERT(IS_VALID_SEVT_CH(enCh));
|
||||
|
||||
/* Get actual address of register list of current channel */
|
||||
pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh);
|
||||
|
||||
return *pu16SCCR;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Set Timer4 SEVT trigger event.
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Timer4 SEVT channel
|
||||
** \arg Timer4SevtCh0 Timer4 SEVT channel:0
|
||||
** \arg Timer4SevtCh1 Timer4 SEVT channel:1
|
||||
** \arg Timer4SevtCh2 Timer4 SEVT channel:2
|
||||
** \arg Timer4SevtCh3 Timer4 SEVT channel:3
|
||||
** \arg Timer4SevtCh4 Timer4 SEVT channel:4
|
||||
** \arg Timer4SevtCh5 Timer4 SEVT channel:5
|
||||
** \param [in] enMaskTimes Timer4 Special-EVT event mask times
|
||||
** \arg Timer4SevtMask0 Mask 0 time.
|
||||
** \arg Timer4SevtMask1 Mask 1 times.
|
||||
** \arg Timer4SevtMask2 Mask 2 times.
|
||||
** \arg Timer4SevtMask3 Mask 3 times.
|
||||
** \arg Timer4SevtMask4 Mask 4 times.
|
||||
** \arg Timer4SevtMask5 Mask 5 times.
|
||||
** \arg Timer4SevtMask6 Mask 6 times.
|
||||
** \arg Timer4SevtMask7 Mask 7 times.
|
||||
** \arg Timer4SevtMask8 Mask 8 times.
|
||||
** \arg Timer4SevtMask9 Mask 9 times.
|
||||
** \arg Timer4SevtMask10 Mask 10 times
|
||||
** \arg Timer4SevtMask11 Mask 11 times
|
||||
** \arg Timer4SevtMask12 Mask 12 times
|
||||
** \arg Timer4SevtMask13 Mask 13 times
|
||||
** \arg Timer4SevtMask14 Mask 14 times
|
||||
** \arg Timer4SevtMask15 Mask 15 times
|
||||
**
|
||||
** \retval Ok Set successfully.
|
||||
** \retval ErrorInvalidParameter TMR4x is invalid
|
||||
**
|
||||
******************************************************************************/
|
||||
en_result_t TIMER4_SEVT_SetMaskTimes(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh,
|
||||
en_timer4_sevt_mask_t enMaskTimes)
|
||||
{
|
||||
__IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL;
|
||||
en_result_t enRet = ErrorInvalidParameter;
|
||||
|
||||
/* Check TMR4x pointer */
|
||||
if (IS_VALID_TIMER4(TMR4x))
|
||||
{
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_SEVT_CH(enCh));
|
||||
DDL_ASSERT(IS_VALID_SEVT_MSK(enMaskTimes));
|
||||
|
||||
/* Get actual address of register list of current channel */
|
||||
pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh);
|
||||
pstcSCMR_f->AMC = (uint16_t)(enMaskTimes);
|
||||
|
||||
enRet = Ok;
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Get Timer4 SEVT mask count.
|
||||
**
|
||||
** \param [in] TMR4x Pointer to Timer4 instance register base
|
||||
** \arg M4_TMR41 Timer4 unit 1 instance register base
|
||||
** \arg M4_TMR42 Timer4 unit 2 instance register base
|
||||
** \arg M4_TMR43 Timer4 unit 3 instance register base
|
||||
** \param [in] enCh Timer4 SEVT channel
|
||||
** \arg Timer4SevtCh0 Timer4 SEVT channel:0
|
||||
** \arg Timer4SevtCh1 Timer4 SEVT channel:1
|
||||
** \arg Timer4SevtCh2 Timer4 SEVT channel:2
|
||||
** \arg Timer4SevtCh3 Timer4 SEVT channel:3
|
||||
** \arg Timer4SevtCh4 Timer4 SEVT channel:4
|
||||
** \arg Timer4SevtCh5 Timer4 SEVT channel:5
|
||||
**
|
||||
** \retval Timer4SevtMask0 Mask 0 time.
|
||||
** \retval Timer4SevtMask1 Mask 1 times.
|
||||
** \retval Timer4SevtMask2 Mask 2 times.
|
||||
** \retval Timer4SevtMask3 Mask 3 times.
|
||||
** \retval Timer4SevtMask4 Mask 4 times.
|
||||
** \retval Timer4SevtMask5 Mask 5 times.
|
||||
** \retval Timer4SevtMask6 Mask 6 times.
|
||||
** \retval Timer4SevtMask7 Mask 7 times.
|
||||
** \retval Timer4SevtMask8 Mask 8 times.
|
||||
** \retval Timer4SevtMask9 Mask 9 times.
|
||||
** \retval Timer4SevtMask10 Mask 10 times
|
||||
** \retval Timer4SevtMask11 Mask 11 times
|
||||
** \retval Timer4SevtMask12 Mask 12 times
|
||||
** \retval Timer4SevtMask13 Mask 13 times
|
||||
** \retval Timer4SevtMask14 Mask 14 times
|
||||
** \retval Timer4SevtMask15 Mask 15 times
|
||||
**
|
||||
******************************************************************************/
|
||||
en_timer4_sevt_mask_t TIMER4_SEVT_GetMaskTimes(M4_TMR4_TypeDef *TMR4x,
|
||||
en_timer4_sevt_ch_t enCh)
|
||||
{
|
||||
__IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL;
|
||||
|
||||
/* Check parameters */
|
||||
DDL_ASSERT(IS_VALID_TIMER4(TMR4x));
|
||||
DDL_ASSERT(IS_VALID_SEVT_CH(enCh));
|
||||
|
||||
/* Get actual address of register list of current channel */
|
||||
pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh);
|
||||
|
||||
return (en_timer4_sevt_mask_t)pstcSCMR_f->AMC;
|
||||
}
|
||||
|
||||
//@} // Timer4SevtGroup
|
||||
|
||||
#endif /* DDL_TIMER4_SEVT_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
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