From 0723faf209efaa7fdfb5c2d65c534d914f0f4292 Mon Sep 17 00:00:00 2001
From: YuanHongbin <975559679@qq.com>
Date: Mon, 22 Jun 2026 09:19:00 +0800
Subject: [PATCH] =?UTF-8?q?=E5=88=9D=E5=A7=8B=E7=89=88=E6=9C=AC?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
---
MDK/BootLoader.uvoptx | 831 +
MDK/BootLoader.uvprojx | 711 +
MDK/EventRecorderStub.scvd | 9 +
MDK/JLinkSettings.ini | 35 +
MDK/RTE/File_System/FS_Config.c | 78 +
MDK/RTE/File_System/FS_Config_MC_0.h | 55 +
MDK/RTE/File_System/FS_Debug.c | 50 +
MDK/RTE/Network/Net_Config.c | 173 +
MDK/RTE/Network/Net_Config_ETH_0.h | 253 +
MDK/RTE/Network/Net_Config_TCP.h | 69 +
MDK/RTE/RTOS/board.c | 90 +
MDK/RTE/RTOS/board.c.base@3.1.5 | 79 +
MDK/RTE/RTOS/rtconfig.h | 139 +
MDK/RTE/RTOS/rtconfig.h.base@3.1.5 | 139 +
MDK/RTE/_Debug/RTE_Components.h | 21 +
MDK/RTE/_Release/RTE_Components.h | 21 +
MDK/RTE/_i2c_24c256_Debug/RTE_Components.h | 21 +
MDK/RTE/_i2c_24c256_Release/RTE_Components.h | 21 +
MDK/RTE/_template_Debug/RTE_Components.h | 21 +
MDK/startup_hc32f460.s | 621 +
Update.exe | Bin 0 -> 1051648 bytes
driver/inc/hc32f460_adc.h | 509 +
driver/inc/hc32f460_aes.h | 81 +
driver/inc/hc32f460_can.h | 518 +
driver/inc/hc32f460_can1.h | 514 +
driver/inc/hc32f460_clk.h | 647 +
driver/inc/hc32f460_cmp.h | 279 +
driver/inc/hc32f460_crc.h | 118 +
driver/inc/hc32f460_dcu.h | 216 +
driver/inc/hc32f460_dmac.h | 363 +
driver/inc/hc32f460_efm.h | 209 +
driver/inc/hc32f460_emb.h | 205 +
driver/inc/hc32f460_event_port.h | 176 +
driver/inc/hc32f460_exint_nmi_swi.h | 257 +
driver/inc/hc32f460_gpio.h | 294 +
driver/inc/hc32f460_hash.h | 72 +
driver/inc/hc32f460_i2c.h | 270 +
driver/inc/hc32f460_i2s.h | 206 +
driver/inc/hc32f460_icg.h | 406 +
driver/inc/hc32f460_interrupts.h | 542 +
driver/inc/hc32f460_keyscan.h | 191 +
driver/inc/hc32f460_mpu.h | 293 +
driver/inc/hc32f460_ots.h | 139 +
driver/inc/hc32f460_pwc.h | 567 +
driver/inc/hc32f460_qspi.h | 402 +
driver/inc/hc32f460_rmu.h | 96 +
driver/inc/hc32f460_rtc.h | 274 +
driver/inc/hc32f460_sdioc.h | 559 +
driver/inc/hc32f460_spi.h | 426 +
driver/inc/hc32f460_sram.h | 190 +
driver/inc/hc32f460_swdt.h | 86 +
driver/inc/hc32f460_timer0.h | 209 +
driver/inc/hc32f460_timer4_cnt.h | 209 +
driver/inc/hc32f460_timer4_emb.h | 115 +
driver/inc/hc32f460_timer4_oco.h | 273 +
driver/inc/hc32f460_timer4_pwm.h | 158 +
driver/inc/hc32f460_timer4_sevt.h | 221 +
driver/inc/hc32f460_timer6.h | 734 +
driver/inc/hc32f460_timera.h | 493 +
driver/inc/hc32f460_trng.h | 100 +
driver/inc/hc32f460_usart.h | 359 +
driver/inc/hc32f460_utility.h | 108 +
driver/inc/hc32f460_wdt.h | 162 +
driver/src/hc32f460_adc.c | 1739 +
driver/src/hc32f460_aes.c | 311 +
driver/src/hc32f460_can.c | 562 +
driver/src/hc32f460_can1.c | 532 +
driver/src/hc32f460_clk.c | 1813 +
driver/src/hc32f460_cmp.c | 1046 +
driver/src/hc32f460_crc.c | 327 +
driver/src/hc32f460_dcu.c | 975 +
driver/src/hc32f460_dmac.c | 1827 +
driver/src/hc32f460_efm.c | 942 +
driver/src/hc32f460_emb.c | 487 +
driver/src/hc32f460_event_port.c | 468 +
driver/src/hc32f460_exint_nmi_swi.c | 337 +
driver/src/hc32f460_gpio.c | 671 +
driver/src/hc32f460_hash.c | 301 +
driver/src/hc32f460_i2c.c | 1318 +
driver/src/hc32f460_i2s.c | 437 +
driver/src/hc32f460_icg.c | 83 +
driver/src/hc32f460_interrupts.c | 3783 ++
driver/src/hc32f460_keyscan.c | 207 +
driver/src/hc32f460_mpu.c | 1057 +
driver/src/hc32f460_ots.c | 386 +
driver/src/hc32f460_pwc.c | 2025 +
driver/src/hc32f460_qspi.c | 756 +
driver/src/hc32f460_rmu.c | 143 +
driver/src/hc32f460_rtc.c | 978 +
driver/src/hc32f460_sdioc.c | 2222 ++
driver/src/hc32f460_spi.c | 1132 +
driver/src/hc32f460_sram.c | 286 +
driver/src/hc32f460_swdt.c | 170 +
driver/src/hc32f460_timer0.c | 967 +
driver/src/hc32f460_timer4_cnt.c | 842 +
driver/src/hc32f460_timer4_emb.c | 278 +
driver/src/hc32f460_timer4_oco.c | 1295 +
driver/src/hc32f460_timer4_pwm.c | 600 +
driver/src/hc32f460_timer4_sevt.c | 593 +
driver/src/hc32f460_timer6.c | 1786 +
driver/src/hc32f460_timera.c | 1972 +
driver/src/hc32f460_trng.c | 263 +
driver/src/hc32f460_usart.c | 1640 +
driver/src/hc32f460_utility.c | 531 +
driver/src/hc32f460_wdt.c | 254 +
mcu/common/hc32_common.h | 219 +
mcu/common/hc32_ddl.h | 267 +
mcu/common/hc32f460.h | 30602 ++++++++++++++++
mcu/common/system_hc32f460.c | 122 +
mcu/common/system_hc32f460.h | 105 +
source/Module/AD7924/ad7924.c | 2 +
source/Module/FatFS/LICENSE.txt | 24 +
source/Module/FatFS/documents/00index_e.html | 149 +
source/Module/FatFS/documents/css_e.css | 73 +
.../Module/FatFS/documents/doc/appnote.html | 339 +
source/Module/FatFS/documents/doc/chdir.html | 88 +
.../Module/FatFS/documents/doc/chdrive.html | 70 +
source/Module/FatFS/documents/doc/chmod.html | 89 +
source/Module/FatFS/documents/doc/close.html | 65 +
.../Module/FatFS/documents/doc/closedir.html | 64 +
source/Module/FatFS/documents/doc/config.html | 304 +
source/Module/FatFS/documents/doc/dinit.html | 46 +
source/Module/FatFS/documents/doc/dioctl.html | 101 +
source/Module/FatFS/documents/doc/dread.html | 73 +
source/Module/FatFS/documents/doc/dstat.html | 48 +
source/Module/FatFS/documents/doc/dwrite.html | 76 +
source/Module/FatFS/documents/doc/eof.html | 62 +
source/Module/FatFS/documents/doc/error.html | 62 +
source/Module/FatFS/documents/doc/expand.html | 117 +
.../Module/FatFS/documents/doc/fattime.html | 80 +
source/Module/FatFS/documents/doc/fdisk.html | 95 +
.../Module/FatFS/documents/doc/filename.html | 94 +
.../Module/FatFS/documents/doc/findfirst.html | 118 +
.../Module/FatFS/documents/doc/findnext.html | 69 +
.../Module/FatFS/documents/doc/forward.html | 139 +
source/Module/FatFS/documents/doc/getcwd.html | 83 +
.../Module/FatFS/documents/doc/getfree.html | 94 +
.../Module/FatFS/documents/doc/getlabel.html | 90 +
source/Module/FatFS/documents/doc/gets.html | 65 +
source/Module/FatFS/documents/doc/lseek.html | 139 +
source/Module/FatFS/documents/doc/mkdir.html | 80 +
source/Module/FatFS/documents/doc/mkfs.html | 127 +
source/Module/FatFS/documents/doc/mount.html | 122 +
source/Module/FatFS/documents/doc/open.html | 185 +
.../Module/FatFS/documents/doc/opendir.html | 75 +
source/Module/FatFS/documents/doc/printf.html | 115 +
source/Module/FatFS/documents/doc/putc.html | 60 +
source/Module/FatFS/documents/doc/puts.html | 61 +
source/Module/FatFS/documents/doc/rc.html | 135 +
source/Module/FatFS/documents/doc/read.html | 80 +
.../Module/FatFS/documents/doc/readdir.html | 139 +
source/Module/FatFS/documents/doc/rename.html | 87 +
source/Module/FatFS/documents/doc/sdir.html | 38 +
source/Module/FatFS/documents/doc/setcp.html | 82 +
.../Module/FatFS/documents/doc/setlabel.html | 92 +
source/Module/FatFS/documents/doc/sfatfs.html | 62 +
source/Module/FatFS/documents/doc/sfile.html | 43 +
.../Module/FatFS/documents/doc/sfileinfo.html | 78 +
source/Module/FatFS/documents/doc/size.html | 62 +
source/Module/FatFS/documents/doc/stat.html | 112 +
source/Module/FatFS/documents/doc/sync.html | 88 +
source/Module/FatFS/documents/doc/tell.html | 62 +
.../Module/FatFS/documents/doc/truncate.html | 66 +
source/Module/FatFS/documents/doc/unlink.html | 74 +
source/Module/FatFS/documents/doc/utime.html | 99 +
source/Module/FatFS/documents/doc/write.html | 80 +
source/Module/FatFS/documents/res/app1.c | 44 +
source/Module/FatFS/documents/res/app2.c | 81 +
source/Module/FatFS/documents/res/app3.c | 109 +
source/Module/FatFS/documents/res/app4.c | 315 +
source/Module/FatFS/documents/res/app5.c | 38 +
source/Module/FatFS/documents/res/app6.c | 61 +
source/Module/FatFS/documents/res/f1.png | Bin 0 -> 1414 bytes
source/Module/FatFS/documents/res/f2.png | Bin 0 -> 1458 bytes
source/Module/FatFS/documents/res/f3.png | Bin 0 -> 1039 bytes
source/Module/FatFS/documents/res/f4.png | Bin 0 -> 1973 bytes
source/Module/FatFS/documents/res/f5.png | Bin 0 -> 2224 bytes
source/Module/FatFS/documents/res/f6.png | Bin 0 -> 1464 bytes
source/Module/FatFS/documents/res/f7.png | Bin 0 -> 25760 bytes
source/Module/FatFS/documents/res/funcs.png | Bin 0 -> 26839 bytes
source/Module/FatFS/documents/res/layers.png | Bin 0 -> 5521 bytes
source/Module/FatFS/documents/res/layers1.png | Bin 0 -> 3843 bytes
source/Module/FatFS/documents/res/layers2.png | Bin 0 -> 4950 bytes
source/Module/FatFS/documents/res/layers3.png | Bin 0 -> 2379 bytes
.../Module/FatFS/documents/res/mkfatimg.zip | Bin 0 -> 778875 bytes
source/Module/FatFS/documents/res/mkfs.xlsx | Bin 0 -> 1491997 bytes
source/Module/FatFS/documents/res/modules.png | Bin 0 -> 15396 bytes
source/Module/FatFS/documents/res/rwtest1.png | Bin 0 -> 69114 bytes
source/Module/FatFS/documents/res/rwtest2.png | Bin 0 -> 8153 bytes
source/Module/FatFS/documents/res/rwtest3.png | Bin 0 -> 3011 bytes
source/Module/FatFS/documents/res/uniconv.zip | Bin 0 -> 4175 bytes
source/Module/FatFS/documents/updates.html | 481 +
source/Module/FatFS/ff15.zip | Bin 0 -> 2379894 bytes
source/Module/FatFS/source/00history.txt | 369 +
source/Module/FatFS/source/00readme.txt | 21 +
source/Module/FatFS/source/diskio.c | 233 +
source/Module/FatFS/source/diskio.h | 77 +
source/Module/FatFS/source/ff.c | 7085 ++++
source/Module/FatFS/source/ff.h | 429 +
source/Module/FatFS/source/ffconf.h | 296 +
source/Module/FatFS/source/ffsystem.c | 223 +
source/Module/FatFS/source/ffunicode.c | 15593 ++++++++
source/Module/FatFS/source/sd_diskio.c | 204 +
source/Module/FatFS/source/sd_diskio.h | 26 +
source/Module/SDCard/sd_card.c | 1319 +
source/Module/SDCard/sd_card.h | 404 +
source/Module/SDCard/sd_card_1.c | 1268 +
source/Module/SDCard/sdmmc_cmd.c | 1641 +
source/Module/SDCard/sdmmc_cmd.h | 311 +
source/Module/SDCard/sdmmc_cmd_1.c | 1641 +
source/Module/SHT20/SHT20.C | 615 +
source/Module/SHT20/SHT20.H | 156 +
source/Module/SX127x/sx127x.c | 654 +
source/Module/SX127x/sx127x.h | 802 +
source/User/Inc/ADS1231.h | 13 +
source/User/Inc/AppTask.h | 0
source/User/Inc/CatOneTask.h | 107 +
source/User/Inc/DebugCmd.h | 7 +
source/User/Inc/Encryption.h | 7 +
source/User/Inc/LoraTask.h | 11 +
source/User/Inc/Public.h | 381 +
source/User/Inc/PublicTypes.h | 14 +
source/User/Inc/RS485Task.h | 69 +
source/User/Inc/bsp.h | 314 +
source/User/Inc/ddl_config.h | 160 +
source/User/Inc/main.h | 74 +
source/User/Inc/spiflash.h | 75 +
source/User/Src/ADS1231.c | 126 +
source/User/Src/AppTask.c | 0
source/User/Src/CatOneTask.c | 709 +
source/User/Src/DebugCmd.c | 1450 +
source/User/Src/Encryption.c | 87 +
source/User/Src/LoraTask.c | 188 +
source/User/Src/Public.c | 905 +
source/User/Src/RS485Task.c | 546 +
source/User/Src/bsp.c | 413 +
source/User/Src/main.c | 338 +
source/User/Src/spiflash.c | 486 +
version.txt | 267 +
串口升级协议.xlsx | Bin 0 -> 12665 bytes
240 files changed, 131805 insertions(+)
create mode 100644 MDK/BootLoader.uvoptx
create mode 100644 MDK/BootLoader.uvprojx
create mode 100644 MDK/EventRecorderStub.scvd
create mode 100644 MDK/JLinkSettings.ini
create mode 100644 MDK/RTE/File_System/FS_Config.c
create mode 100644 MDK/RTE/File_System/FS_Config_MC_0.h
create mode 100644 MDK/RTE/File_System/FS_Debug.c
create mode 100644 MDK/RTE/Network/Net_Config.c
create mode 100644 MDK/RTE/Network/Net_Config_ETH_0.h
create mode 100644 MDK/RTE/Network/Net_Config_TCP.h
create mode 100644 MDK/RTE/RTOS/board.c
create mode 100644 MDK/RTE/RTOS/board.c.base@3.1.5
create mode 100644 MDK/RTE/RTOS/rtconfig.h
create mode 100644 MDK/RTE/RTOS/rtconfig.h.base@3.1.5
create mode 100644 MDK/RTE/_Debug/RTE_Components.h
create mode 100644 MDK/RTE/_Release/RTE_Components.h
create mode 100644 MDK/RTE/_i2c_24c256_Debug/RTE_Components.h
create mode 100644 MDK/RTE/_i2c_24c256_Release/RTE_Components.h
create mode 100644 MDK/RTE/_template_Debug/RTE_Components.h
create mode 100644 MDK/startup_hc32f460.s
create mode 100644 Update.exe
create mode 100644 driver/inc/hc32f460_adc.h
create mode 100644 driver/inc/hc32f460_aes.h
create mode 100644 driver/inc/hc32f460_can.h
create mode 100644 driver/inc/hc32f460_can1.h
create mode 100644 driver/inc/hc32f460_clk.h
create mode 100644 driver/inc/hc32f460_cmp.h
create mode 100644 driver/inc/hc32f460_crc.h
create mode 100644 driver/inc/hc32f460_dcu.h
create mode 100644 driver/inc/hc32f460_dmac.h
create mode 100644 driver/inc/hc32f460_efm.h
create mode 100644 driver/inc/hc32f460_emb.h
create mode 100644 driver/inc/hc32f460_event_port.h
create mode 100644 driver/inc/hc32f460_exint_nmi_swi.h
create mode 100644 driver/inc/hc32f460_gpio.h
create mode 100644 driver/inc/hc32f460_hash.h
create mode 100644 driver/inc/hc32f460_i2c.h
create mode 100644 driver/inc/hc32f460_i2s.h
create mode 100644 driver/inc/hc32f460_icg.h
create mode 100644 driver/inc/hc32f460_interrupts.h
create mode 100644 driver/inc/hc32f460_keyscan.h
create mode 100644 driver/inc/hc32f460_mpu.h
create mode 100644 driver/inc/hc32f460_ots.h
create mode 100644 driver/inc/hc32f460_pwc.h
create mode 100644 driver/inc/hc32f460_qspi.h
create mode 100644 driver/inc/hc32f460_rmu.h
create mode 100644 driver/inc/hc32f460_rtc.h
create mode 100644 driver/inc/hc32f460_sdioc.h
create mode 100644 driver/inc/hc32f460_spi.h
create mode 100644 driver/inc/hc32f460_sram.h
create mode 100644 driver/inc/hc32f460_swdt.h
create mode 100644 driver/inc/hc32f460_timer0.h
create mode 100644 driver/inc/hc32f460_timer4_cnt.h
create mode 100644 driver/inc/hc32f460_timer4_emb.h
create mode 100644 driver/inc/hc32f460_timer4_oco.h
create mode 100644 driver/inc/hc32f460_timer4_pwm.h
create mode 100644 driver/inc/hc32f460_timer4_sevt.h
create mode 100644 driver/inc/hc32f460_timer6.h
create mode 100644 driver/inc/hc32f460_timera.h
create mode 100644 driver/inc/hc32f460_trng.h
create mode 100644 driver/inc/hc32f460_usart.h
create mode 100644 driver/inc/hc32f460_utility.h
create mode 100644 driver/inc/hc32f460_wdt.h
create mode 100644 driver/src/hc32f460_adc.c
create mode 100644 driver/src/hc32f460_aes.c
create mode 100644 driver/src/hc32f460_can.c
create mode 100644 driver/src/hc32f460_can1.c
create mode 100644 driver/src/hc32f460_clk.c
create mode 100644 driver/src/hc32f460_cmp.c
create mode 100644 driver/src/hc32f460_crc.c
create mode 100644 driver/src/hc32f460_dcu.c
create mode 100644 driver/src/hc32f460_dmac.c
create mode 100644 driver/src/hc32f460_efm.c
create mode 100644 driver/src/hc32f460_emb.c
create mode 100644 driver/src/hc32f460_event_port.c
create mode 100644 driver/src/hc32f460_exint_nmi_swi.c
create mode 100644 driver/src/hc32f460_gpio.c
create mode 100644 driver/src/hc32f460_hash.c
create mode 100644 driver/src/hc32f460_i2c.c
create mode 100644 driver/src/hc32f460_i2s.c
create mode 100644 driver/src/hc32f460_icg.c
create mode 100644 driver/src/hc32f460_interrupts.c
create mode 100644 driver/src/hc32f460_keyscan.c
create mode 100644 driver/src/hc32f460_mpu.c
create mode 100644 driver/src/hc32f460_ots.c
create mode 100644 driver/src/hc32f460_pwc.c
create mode 100644 driver/src/hc32f460_qspi.c
create mode 100644 driver/src/hc32f460_rmu.c
create mode 100644 driver/src/hc32f460_rtc.c
create mode 100644 driver/src/hc32f460_sdioc.c
create mode 100644 driver/src/hc32f460_spi.c
create mode 100644 driver/src/hc32f460_sram.c
create mode 100644 driver/src/hc32f460_swdt.c
create mode 100644 driver/src/hc32f460_timer0.c
create mode 100644 driver/src/hc32f460_timer4_cnt.c
create mode 100644 driver/src/hc32f460_timer4_emb.c
create mode 100644 driver/src/hc32f460_timer4_oco.c
create mode 100644 driver/src/hc32f460_timer4_pwm.c
create mode 100644 driver/src/hc32f460_timer4_sevt.c
create mode 100644 driver/src/hc32f460_timer6.c
create mode 100644 driver/src/hc32f460_timera.c
create mode 100644 driver/src/hc32f460_trng.c
create mode 100644 driver/src/hc32f460_usart.c
create mode 100644 driver/src/hc32f460_utility.c
create mode 100644 driver/src/hc32f460_wdt.c
create mode 100644 mcu/common/hc32_common.h
create mode 100644 mcu/common/hc32_ddl.h
create mode 100644 mcu/common/hc32f460.h
create mode 100644 mcu/common/system_hc32f460.c
create mode 100644 mcu/common/system_hc32f460.h
create mode 100644 source/Module/AD7924/ad7924.c
create mode 100644 source/Module/FatFS/LICENSE.txt
create mode 100644 source/Module/FatFS/documents/00index_e.html
create mode 100644 source/Module/FatFS/documents/css_e.css
create mode 100644 source/Module/FatFS/documents/doc/appnote.html
create mode 100644 source/Module/FatFS/documents/doc/chdir.html
create mode 100644 source/Module/FatFS/documents/doc/chdrive.html
create mode 100644 source/Module/FatFS/documents/doc/chmod.html
create mode 100644 source/Module/FatFS/documents/doc/close.html
create mode 100644 source/Module/FatFS/documents/doc/closedir.html
create mode 100644 source/Module/FatFS/documents/doc/config.html
create mode 100644 source/Module/FatFS/documents/doc/dinit.html
create mode 100644 source/Module/FatFS/documents/doc/dioctl.html
create mode 100644 source/Module/FatFS/documents/doc/dread.html
create mode 100644 source/Module/FatFS/documents/doc/dstat.html
create mode 100644 source/Module/FatFS/documents/doc/dwrite.html
create mode 100644 source/Module/FatFS/documents/doc/eof.html
create mode 100644 source/Module/FatFS/documents/doc/error.html
create mode 100644 source/Module/FatFS/documents/doc/expand.html
create mode 100644 source/Module/FatFS/documents/doc/fattime.html
create mode 100644 source/Module/FatFS/documents/doc/fdisk.html
create mode 100644 source/Module/FatFS/documents/doc/filename.html
create mode 100644 source/Module/FatFS/documents/doc/findfirst.html
create mode 100644 source/Module/FatFS/documents/doc/findnext.html
create mode 100644 source/Module/FatFS/documents/doc/forward.html
create mode 100644 source/Module/FatFS/documents/doc/getcwd.html
create mode 100644 source/Module/FatFS/documents/doc/getfree.html
create mode 100644 source/Module/FatFS/documents/doc/getlabel.html
create mode 100644 source/Module/FatFS/documents/doc/gets.html
create mode 100644 source/Module/FatFS/documents/doc/lseek.html
create mode 100644 source/Module/FatFS/documents/doc/mkdir.html
create mode 100644 source/Module/FatFS/documents/doc/mkfs.html
create mode 100644 source/Module/FatFS/documents/doc/mount.html
create mode 100644 source/Module/FatFS/documents/doc/open.html
create mode 100644 source/Module/FatFS/documents/doc/opendir.html
create mode 100644 source/Module/FatFS/documents/doc/printf.html
create mode 100644 source/Module/FatFS/documents/doc/putc.html
create mode 100644 source/Module/FatFS/documents/doc/puts.html
create mode 100644 source/Module/FatFS/documents/doc/rc.html
create mode 100644 source/Module/FatFS/documents/doc/read.html
create mode 100644 source/Module/FatFS/documents/doc/readdir.html
create mode 100644 source/Module/FatFS/documents/doc/rename.html
create mode 100644 source/Module/FatFS/documents/doc/sdir.html
create mode 100644 source/Module/FatFS/documents/doc/setcp.html
create mode 100644 source/Module/FatFS/documents/doc/setlabel.html
create mode 100644 source/Module/FatFS/documents/doc/sfatfs.html
create mode 100644 source/Module/FatFS/documents/doc/sfile.html
create mode 100644 source/Module/FatFS/documents/doc/sfileinfo.html
create mode 100644 source/Module/FatFS/documents/doc/size.html
create mode 100644 source/Module/FatFS/documents/doc/stat.html
create mode 100644 source/Module/FatFS/documents/doc/sync.html
create mode 100644 source/Module/FatFS/documents/doc/tell.html
create mode 100644 source/Module/FatFS/documents/doc/truncate.html
create mode 100644 source/Module/FatFS/documents/doc/unlink.html
create mode 100644 source/Module/FatFS/documents/doc/utime.html
create mode 100644 source/Module/FatFS/documents/doc/write.html
create mode 100644 source/Module/FatFS/documents/res/app1.c
create mode 100644 source/Module/FatFS/documents/res/app2.c
create mode 100644 source/Module/FatFS/documents/res/app3.c
create mode 100644 source/Module/FatFS/documents/res/app4.c
create mode 100644 source/Module/FatFS/documents/res/app5.c
create mode 100644 source/Module/FatFS/documents/res/app6.c
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create mode 100644 source/Module/FatFS/source/sd_diskio.h
create mode 100644 source/Module/SDCard/sd_card.c
create mode 100644 source/Module/SDCard/sd_card.h
create mode 100644 source/Module/SDCard/sd_card_1.c
create mode 100644 source/Module/SDCard/sdmmc_cmd.c
create mode 100644 source/Module/SDCard/sdmmc_cmd.h
create mode 100644 source/Module/SDCard/sdmmc_cmd_1.c
create mode 100644 source/Module/SHT20/SHT20.C
create mode 100644 source/Module/SHT20/SHT20.H
create mode 100644 source/Module/SX127x/sx127x.c
create mode 100644 source/Module/SX127x/sx127x.h
create mode 100644 source/User/Inc/ADS1231.h
create mode 100644 source/User/Inc/AppTask.h
create mode 100644 source/User/Inc/CatOneTask.h
create mode 100644 source/User/Inc/DebugCmd.h
create mode 100644 source/User/Inc/Encryption.h
create mode 100644 source/User/Inc/LoraTask.h
create mode 100644 source/User/Inc/Public.h
create mode 100644 source/User/Inc/PublicTypes.h
create mode 100644 source/User/Inc/RS485Task.h
create mode 100644 source/User/Inc/bsp.h
create mode 100644 source/User/Inc/ddl_config.h
create mode 100644 source/User/Inc/main.h
create mode 100644 source/User/Inc/spiflash.h
create mode 100644 source/User/Src/ADS1231.c
create mode 100644 source/User/Src/AppTask.c
create mode 100644 source/User/Src/CatOneTask.c
create mode 100644 source/User/Src/DebugCmd.c
create mode 100644 source/User/Src/Encryption.c
create mode 100644 source/User/Src/LoraTask.c
create mode 100644 source/User/Src/Public.c
create mode 100644 source/User/Src/RS485Task.c
create mode 100644 source/User/Src/bsp.c
create mode 100644 source/User/Src/main.c
create mode 100644 source/User/Src/spiflash.c
create mode 100644 version.txt
create mode 100644 串口升级协议.xlsx
diff --git a/MDK/BootLoader.uvoptx b/MDK/BootLoader.uvoptx
new file mode 100644
index 0000000..8f1d100
--- /dev/null
+++ b/MDK/BootLoader.uvoptx
@@ -0,0 +1,831 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc; *.md
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ Release
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
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+ 1
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+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
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+ 66
+ 8
+ .\output\debug\
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ CMSIS_AGDI
+ -X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K.FLM -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FF1HC32F460_otp.FLM -FS13000C00 -FL13FC -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN2 -FC1000 -FD1FFF8000 -FF0HC32F460_512K -FF1HC32F460_otp -FL080000 -FL13FC -FS00 -FS13000C00 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM)
+
+
+ 0
+ JL2CM3
+ -U4294967295 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8027 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_256K.FLM -FS00 -FL040000 -FP0($$Device:HC32F460JCTA$FlashARM\HC32F460_256K.FLM) -FF1HC32F460_otp.FLM -FS13000C00 -FL13FC -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM)
+
+
+ 0
+ ARMRTXEVENTFLAGS
+ -L70 -Z18 -C0 -M0 -T1
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+
+
+
+ 0
+ 1
+ BL.RxBuff
+
+
+ 1
+ 1
+ BL.Para,0x10
+
+
+
+
+ 0
+ 2
+ SComm2Para
+
+
+
+
+ 1
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+
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+ system_hc32f460.c
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+ .\startup_hc32f460.s
+ startup_hc32f460.s
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+
+
+ User
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+ main.c
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+
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+ bsp.c
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+
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+ hc32f460_aes.c
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+
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+ hc32f460_timer4_cnt.c
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+
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+
+ 3
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+ ..\driver\src\hc32f460_utility.c
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+ 0
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+
+ 3
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+ ..\driver\src\hc32f460_wdt.c
+ hc32f460_wdt.c
+ 0
+ 0
+
+
+
+
+ Readme
+ 1
+ 0
+ 0
+ 0
+
+
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
+
diff --git a/MDK/BootLoader.uvprojx b/MDK/BootLoader.uvprojx
new file mode 100644
index 0000000..af1973f
--- /dev/null
+++ b/MDK/BootLoader.uvprojx
@@ -0,0 +1,711 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ Release
+ 0x4
+ ARM-ADS
+ 5060960::V5.06 update 7 (build 960)::ARMCC
+ 0
+
+
+ HC32F460PETB
+ HDSC
+ HDSC.HC32F460.1.0.12
+ https://raw.githubusercontent.com/hdscmcu/pack/master/
+ IRAM(0x1FFF8000,0x2F000) IRAM2(0x200F0000,0x1000) IROM(0x00000000,0x80000) IROM2(0x03000C00,0x003FC) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FF1HC32F460_otp -FS13000C00 -FL13FC -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM))
+ 0
+ $$Device:HC32F460PETB$Device\Include\HC32F460PETB.h
+
+
+
+
+
+
+
+
+
+ $$Device:HC32F460PETB$SVD\HC32F460PETB.svd
+ 1
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\output\debug\
+ GateWay
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\output\debug\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 0
+ fromelf --bin -o "$L@L.bin" "#L"
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -MPU
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
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+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 0
+ "Cortex-M4"
+
+ 0
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+ 1
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+ 0
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+
+ 0
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+ 0
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+
+ 0
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+ 0x0
+
+
+ 0
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+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x1fff8000
+ 0x2f000
+
+
+ 1
+ 0x0
+ 0x80000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
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+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x80000
+
+
+ 1
+ 0x3000c00
+ 0x3fc
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
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+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
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+
+ 0
+ 0x1fff8000
+ 0x2f000
+
+
+ 0
+ 0x200f0000
+ 0x1000
+
+
+
+
+
+ 1
+ 1
+ 0
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+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+ --diag_suppress=186,66
+ __DEBUG,HC32F460,USE_DEVICE_DRIVER_LIB,JEUA
+
+ ..\driver\src;..\driver\inc;..\mcu\common;..\source\User\Src;..\source\User\Inc;..\source\Module\Debug;..\source\Module\SDCard;..\source\Module\FatFS\source;..\source\Module\SX127x
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 4
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x1FFF8000
+
+ i2c_24c256.sct
+
+
+ --keep=*Handler
+
+
+
+
+
+
+
+ common
+
+
+ system_hc32f460.c
+ 1
+ ..\mcu\common\system_hc32f460.c
+
+
+ startup_hc32f460.s
+ 2
+ .\startup_hc32f460.s
+
+
+
+
+ User
+
+
+ main.c
+ 1
+ ..\source\User\Src\main.c
+
+
+ bsp.c
+ 1
+ ..\source\User\Src\bsp.c
+
+
+
+
+ driver
+
+
+ hc32f460_adc.c
+ 1
+ ..\driver\src\hc32f460_adc.c
+
+
+ hc32f460_aes.c
+ 1
+ ..\driver\src\hc32f460_aes.c
+
+
+ hc32f460_can.c
+ 1
+ ..\driver\src\hc32f460_can.c
+
+
+ hc32f460_can1.c
+ 1
+ ..\driver\src\hc32f460_can1.c
+
+
+ hc32f460_clk.c
+ 1
+ ..\driver\src\hc32f460_clk.c
+
+
+ hc32f460_cmp.c
+ 1
+ ..\driver\src\hc32f460_cmp.c
+
+
+ hc32f460_crc.c
+ 1
+ ..\driver\src\hc32f460_crc.c
+
+
+ hc32f460_dcu.c
+ 1
+ ..\driver\src\hc32f460_dcu.c
+
+
+ hc32f460_dmac.c
+ 1
+ ..\driver\src\hc32f460_dmac.c
+
+
+ hc32f460_efm.c
+ 1
+ ..\driver\src\hc32f460_efm.c
+
+
+ hc32f460_emb.c
+ 1
+ ..\driver\src\hc32f460_emb.c
+
+
+ hc32f460_event_port.c
+ 1
+ ..\driver\src\hc32f460_event_port.c
+
+
+ hc32f460_exint_nmi_swi.c
+ 1
+ ..\driver\src\hc32f460_exint_nmi_swi.c
+
+
+ hc32f460_gpio.c
+ 1
+ ..\driver\src\hc32f460_gpio.c
+
+
+ hc32f460_hash.c
+ 1
+ ..\driver\src\hc32f460_hash.c
+
+
+ hc32f460_i2c.c
+ 1
+ ..\driver\src\hc32f460_i2c.c
+
+
+ hc32f460_i2s.c
+ 1
+ ..\driver\src\hc32f460_i2s.c
+
+
+ hc32f460_icg.c
+ 1
+ ..\driver\src\hc32f460_icg.c
+
+
+ hc32f460_interrupts.c
+ 1
+ ..\driver\src\hc32f460_interrupts.c
+
+
+ hc32f460_keyscan.c
+ 1
+ ..\driver\src\hc32f460_keyscan.c
+
+
+ hc32f460_mpu.c
+ 1
+ ..\driver\src\hc32f460_mpu.c
+
+
+ hc32f460_ots.c
+ 1
+ ..\driver\src\hc32f460_ots.c
+
+
+ hc32f460_pwc.c
+ 1
+ ..\driver\src\hc32f460_pwc.c
+
+
+ hc32f460_qspi.c
+ 1
+ ..\driver\src\hc32f460_qspi.c
+
+
+ hc32f460_rmu.c
+ 1
+ ..\driver\src\hc32f460_rmu.c
+
+
+ hc32f460_rtc.c
+ 1
+ ..\driver\src\hc32f460_rtc.c
+
+
+ hc32f460_sdioc.c
+ 1
+ ..\driver\src\hc32f460_sdioc.c
+
+
+ hc32f460_spi.c
+ 1
+ ..\driver\src\hc32f460_spi.c
+
+
+ hc32f460_sram.c
+ 1
+ ..\driver\src\hc32f460_sram.c
+
+
+ hc32f460_swdt.c
+ 1
+ ..\driver\src\hc32f460_swdt.c
+
+
+ hc32f460_timer0.c
+ 1
+ ..\driver\src\hc32f460_timer0.c
+
+
+ hc32f460_timer4_cnt.c
+ 1
+ ..\driver\src\hc32f460_timer4_cnt.c
+
+
+ hc32f460_timer4_emb.c
+ 1
+ ..\driver\src\hc32f460_timer4_emb.c
+
+
+ hc32f460_timer4_oco.c
+ 1
+ ..\driver\src\hc32f460_timer4_oco.c
+
+
+ hc32f460_timer4_pwm.c
+ 1
+ ..\driver\src\hc32f460_timer4_pwm.c
+
+
+ hc32f460_timer4_sevt.c
+ 1
+ ..\driver\src\hc32f460_timer4_sevt.c
+
+
+ hc32f460_timer6.c
+ 1
+ ..\driver\src\hc32f460_timer6.c
+
+
+ hc32f460_timera.c
+ 1
+ ..\driver\src\hc32f460_timera.c
+
+
+ hc32f460_trng.c
+ 1
+ ..\driver\src\hc32f460_trng.c
+
+
+ hc32f460_usart.c
+ 1
+ ..\driver\src\hc32f460_usart.c
+
+
+ hc32f460_utility.c
+ 1
+ ..\driver\src\hc32f460_utility.c
+
+
+ hc32f460_wdt.c
+ 1
+ ..\driver\src\hc32f460_wdt.c
+
+
+
+
+ Readme
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ RTE\File_System\FS_Config.c
+
+
+
+
+
+ RTE\File_System\FS_Config_MC_0.h
+
+
+
+
+
+ RTE\File_System\FS_Debug.c
+
+
+
+
+
+ RTE\Network\Net_Config.c
+
+
+
+
+
+ RTE\Network\Net_Config_ETH_0.h
+
+
+
+
+
+ RTE\Network\Net_Config_TCP.h
+
+
+
+
+
+ RTE\RTOS\board.c
+
+
+
+
+
+ RTE\RTOS\rtconfig.h
+
+
+
+
+
+
+
+
+
+
+ GateWay
+ 0
+ 1
+
+
+
+
+
diff --git a/MDK/EventRecorderStub.scvd b/MDK/EventRecorderStub.scvd
new file mode 100644
index 0000000..2956b29
--- /dev/null
+++ b/MDK/EventRecorderStub.scvd
@@ -0,0 +1,9 @@
+
+
+
+
+
+
+
+
+
diff --git a/MDK/JLinkSettings.ini b/MDK/JLinkSettings.ini
new file mode 100644
index 0000000..b06dcf5
--- /dev/null
+++ b/MDK/JLinkSettings.ini
@@ -0,0 +1,35 @@
+[BREAKPOINTS]
+ForceImpTypeAny = 0
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 1
+Device="Cortex-M4"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF
diff --git a/MDK/RTE/File_System/FS_Config.c b/MDK/RTE/File_System/FS_Config.c
new file mode 100644
index 0000000..21f42a7
--- /dev/null
+++ b/MDK/RTE/File_System/FS_Config.c
@@ -0,0 +1,78 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name: FS_Config.c
+ * Purpose: File System Configuration
+ * Rev.: V6.3.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// FAT File System
+// Define FAT File System parameters
+
+// Number of open files <1-16>
+// Define number of files that can be opened at the same time.
+// Default: 4
+#define FAT_MAX_OPEN_FILES 4
+
+//
+
+// Embedded File System
+// Define Embedded File System parameters
+
+// Number of open files <1-16>
+// Define number of files that can be opened at the same time.
+// Default: 4
+#define EFS_MAX_OPEN_FILES 4
+
+//
+
+// Initial Current Drive <0=>F0: <1=>F1:
+// <2=>M0: <3=>M1:
+// <4=>N0: <5=>N1:
+// <6=>R0: <9=>R1:
+// <7=>U0: <8=>U1:
+// Set initial setting for current drive. Current drive is used for File System functions
+// that are invoked with the "" string and can be altered anytime during run-time.
+#define FS_INITIAL_CDRIVE 2
+
+#include "RTE_Components.h"
+
+#ifdef RTE_FileSystem_Drive_RAM_0
+#include "FS_Config_RAM_0.h"
+#endif
+#ifdef RTE_FileSystem_Drive_RAM_1
+#include "FS_Config_RAM_1.h"
+#endif
+
+#ifdef RTE_FileSystem_Drive_NOR_0
+#include "FS_Config_NOR_0.h"
+#endif
+#ifdef RTE_FileSystem_Drive_NOR_1
+#include "FS_Config_NOR_1.h"
+#endif
+
+#ifdef RTE_FileSystem_Drive_NAND_0
+#include "FS_Config_NAND_0.h"
+#endif
+#ifdef RTE_FileSystem_Drive_NAND_1
+#include "FS_Config_NAND_1.h"
+#endif
+
+#ifdef RTE_FileSystem_Drive_MC_0
+#include "FS_Config_MC_0.h"
+#endif
+#ifdef RTE_FileSystem_Drive_MC_1
+#include "FS_Config_MC_1.h"
+#endif
+
+#ifdef RTE_FileSystem_Drive_USB_0
+#include "FS_Config_USB_0.h"
+#endif
+#ifdef RTE_FileSystem_Drive_USB_1
+#include "FS_Config_USB_1.h"
+#endif
+
+#include "fs_config.h"
diff --git a/MDK/RTE/File_System/FS_Config_MC_0.h b/MDK/RTE/File_System/FS_Config_MC_0.h
new file mode 100644
index 0000000..b04116e
--- /dev/null
+++ b/MDK/RTE/File_System/FS_Config_MC_0.h
@@ -0,0 +1,55 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System:Drive
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name: FS_Config_MC_0.h
+ * Purpose: File System Configuration for Memory Card Drive
+ * Rev.: V6.2.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Memory Card Drive 0
+// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
+#define MC0_ENABLE 1
+
+// Connect to hardware via Driver_MCI# <0-255>
+// Select driver control block for hardware interface
+#define MC0_MCI_DRIVER 0
+
+// Connect to hardware via Driver_SPI# <0-255>
+// Select driver control block for hardware interface when in SPI mode
+#define MC0_SPI_DRIVER 0
+
+// Memory Card Interface Mode <0=>Native <1=>SPI
+// Native uses a SD Bus with up to 8 data lines, CLK, and CMD
+// SPI uses 2 data lines (MOSI and MISO), SCLK and CS
+#define MC0_SPI 0
+
+// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+// <8=>8 KB <16=>16 KB <32=>32 KB
+// Drive Cache stores data sectors and may be increased to speed-up
+// file read/write operations on this drive (default: 4 KB)
+#define MC0_CACHE_SIZE 4
+
+// Locate Drive Cache and Drive Buffer
+// Some microcontrollers support DMA only in specific memory areas and
+// require to locate the drive buffers at a fixed address.
+#define MC0_CACHE_RELOC 0
+
+// Base address <0x0000-0xFFFFFE00:0x200>
+// Set buffer base address to RAM areas that support DMA with the drive.
+#define MC0_CACHE_ADDR 0x7FD00000
+
+//
+// Filename Cache Size <0-1000000>
+// Define number of cached file or directory names.
+// 48 bytes of RAM is required for each cached name.
+#define MC0_NAME_CACHE_SIZE 0
+
+// Use FAT Journal
+// Protect File Allocation Table and Directory Entries for
+// fail-safe operation.
+#define MC0_FAT_JOURNAL 0
+
+//
diff --git a/MDK/RTE/File_System/FS_Debug.c b/MDK/RTE/File_System/FS_Debug.c
new file mode 100644
index 0000000..38e37f5
--- /dev/null
+++ b/MDK/RTE/File_System/FS_Debug.c
@@ -0,0 +1,50 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name: FS_Debug.c
+ * Purpose: File System Debug Configuration
+ * Rev.: V1.0.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// File System Debug
+// Enable File System event recording
+#define FS_DEBUG_EVR_ENABLE 0
+
+// Core Management <0=>Off <1=>Errors <2=>Errors + API <3=>All
+// Configure FsCore: Core Management event recording
+#define FS_DEBUG_EVR_CORE 1
+
+// FAT File System <0=>Off <1=>Errors <2=>Errors + API <3=>All
+// Configure FsFAT: FAT File System event recording
+#define FS_DEBUG_EVR_FAT 1
+
+// EFS File System <0=>Off <1=>Errors <2=>Errors + API <3=>All
+// Configure FsEFS: EFS File System event recording
+#define FS_DEBUG_EVR_EFS 1
+
+// I/O Control Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All
+// Configure FsIOC: I/O Control Interface event recording
+#define FS_DEBUG_EVR_IOC 1
+
+// NAND Flash Translation Layer <0=>Off <1=>Errors <2=>Errors + API <3=>All
+// Configure FsNFTL: NAND Flash Translation Layer event recording
+#define FS_DEBUG_EVR_NFTL 1
+
+// NAND Device Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All
+// Configure FsNAND: NAND Device Interface event recording
+#define FS_DEBUG_EVR_NAND 1
+
+// Memory Card MCI <0=>Off <1=>Errors <2=>Errors + API <3=>All
+// Configure FsMcMCI: Memory Card MCI event recording
+#define FS_DEBUG_EVR_MC_MCI 1
+
+// Memory Card SPI <0=>Off <1=>Errors <2=>Errors + API <3=>All
+// Configure FsMcSPI: Memory Card SPI event recording
+#define FS_DEBUG_EVR_MC_SPI 1
+
+//
+
+#include "fs_debug.h"
diff --git a/MDK/RTE/Network/Net_Config.c b/MDK/RTE/Network/Net_Config.c
new file mode 100644
index 0000000..f72bbaf
--- /dev/null
+++ b/MDK/RTE/Network/Net_Config.c
@@ -0,0 +1,173 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name: Net_Config.c
+ * Purpose: Network Configuration
+ * Rev.: V7.1.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Network System Settings
+// Global Network System definitions
+// Local Host Name
+// This is the name under which embedded host can be
+// accessed on a local area network.
+// Default: "my_host"
+#define NET_HOST_NAME "my_host"
+
+// Memory Pool Size <1536-262144:4>
+// This is the size of a memory pool in bytes. Buffers for
+// network packets are allocated from this memory pool.
+// Default: 12000 bytes
+#define NET_MEM_POOL_SIZE 12000
+
+// Start System Services
+// If enabled, the system will automatically start server services
+// (HTTP, FTP, TFTP server, ...) when initializing the network system.
+// Default: Enabled
+#define NET_START_SERVICE 1
+
+// OS Resource Settings
+// These settings are used to optimize usage of OS resources.
+// Core Thread Stack Size <512-65535:4>
+// Default: 1024 bytes
+#define NET_THREAD_STACK_SIZE 1024
+
+// Core Thread Priority
+#define NET_THREAD_PRIORITY osPriorityNormal
+
+//
+//
+
+//------------- <<< end of configuration section >>> ---------------------------
+
+#include "RTE_Components.h"
+
+#ifdef RTE_Network_Interface_ETH_0
+#include "Net_Config_ETH_0.h"
+#endif
+#ifdef RTE_Network_Interface_ETH_1
+#include "Net_Config_ETH_1.h"
+#endif
+
+#ifdef RTE_Network_Interface_WiFi_0
+#include "Net_Config_WiFi_0.h"
+#endif
+
+#ifdef RTE_Network_Interface_WiFi_1
+#include "Net_Config_WiFi_1.h"
+#endif
+
+#ifdef RTE_Network_Interface_PPP
+#include "Net_Config_PPP.h"
+#endif
+
+#ifdef RTE_Network_Interface_SLIP
+#include "Net_Config_SLIP.h"
+#endif
+
+#ifdef RTE_Network_Socket_UDP
+#include "Net_Config_UDP.h"
+#endif
+#ifdef RTE_Network_Socket_TCP
+#include "Net_Config_TCP.h"
+#endif
+#ifdef RTE_Network_Socket_BSD
+#include "Net_Config_BSD.h"
+#endif
+
+#ifdef RTE_Network_Web_Server_RO
+#include "Net_Config_HTTP_Server.h"
+#endif
+#ifdef RTE_Network_Web_Server_FS
+#include "Net_Config_HTTP_Server.h"
+#endif
+
+#ifdef RTE_Network_Telnet_Server
+#include "Net_Config_Telnet_Server.h"
+#endif
+
+#ifdef RTE_Network_TFTP_Server
+#include "Net_Config_TFTP_Server.h"
+#endif
+#ifdef RTE_Network_TFTP_Client
+#include "Net_Config_TFTP_Client.h"
+#endif
+
+#ifdef RTE_Network_FTP_Server
+#include "Net_Config_FTP_Server.h"
+#endif
+#ifdef RTE_Network_FTP_Client
+#include "Net_Config_FTP_Client.h"
+#endif
+
+#ifdef RTE_Network_DNS_Client
+#include "Net_Config_DNS_Client.h"
+#endif
+
+#ifdef RTE_Network_SMTP_Client
+#include "Net_Config_SMTP_Client.h"
+#endif
+
+#ifdef RTE_Network_SNMP_Agent
+#include "Net_Config_SNMP_Agent.h"
+#endif
+
+#ifdef RTE_Network_SNTP_Client
+#include "Net_Config_SNTP_Client.h"
+#endif
+
+#include "net_config.h"
+
+/**
+\addtogroup net_genFunc
+@{
+*/
+/**
+ \fn void net_sys_error (NET_ERROR error)
+ \ingroup net_cores
+ \brief Network system error handler.
+*/
+void net_sys_error (NET_ERROR error) {
+ /* This function is called when a fatal error is encountered. */
+ /* The normal program execution is not possible anymore. */
+
+ switch (error) {
+ case NET_ERROR_MEM_ALLOC:
+ /* Out of memory */
+ break;
+
+ case NET_ERROR_MEM_FREE:
+ /* Trying to release non existing memory block */
+ break;
+
+ case NET_ERROR_MEM_CORRUPT:
+ /* Memory Link pointer corrupted */
+ /* More data written than the size of allocated memory block */
+ break;
+
+ case NET_ERROR_CONFIG:
+ /* Network configuration error detected */
+ break;
+
+ case NET_ERROR_UDP_ALLOC:
+ /* Out of UDP Sockets */
+ break;
+
+ case NET_ERROR_TCP_ALLOC:
+ /* Out of TCP Sockets */
+ break;
+
+ case NET_ERROR_TCP_STATE:
+ /* TCP State machine in undefined state */
+ break;
+ }
+
+ /* End-less loop */
+ while (1);
+}
+/**
+@}
+*/
diff --git a/MDK/RTE/Network/Net_Config_ETH_0.h b/MDK/RTE/Network/Net_Config_ETH_0.h
new file mode 100644
index 0000000..2fac34c
--- /dev/null
+++ b/MDK/RTE/Network/Net_Config_ETH_0.h
@@ -0,0 +1,253 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Interface
+ * Copyright (c) 2004-2020 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name: Net_Config_ETH_0.h
+ * Purpose: Network Configuration for ETH Interface
+ * Rev.: V7.3.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Ethernet Network Interface 0
+#define ETH0_ENABLE 1
+
+// Connect to hardware via Driver_ETH# <0-255>
+// Select driver control block for MAC and PHY interface
+#define ETH0_DRIVER 0
+
+// MAC Address
+// Ethernet MAC Address in text representation
+// Value FF-FF-FF-FF-FF-FF is not allowed,
+// LSB of first byte must be 0 (an ethernet Multicast bit).
+// Default: "1E-30-6C-A2-45-5E"
+#define ETH0_MAC_ADDR "1E-30-6C-A2-45-5E"
+
+// VLAN
+// Enable or disable Virtual LAN
+#define ETH0_VLAN_ENABLE 0
+
+// VLAN Identifier <1-4093>
+// A unique 12-bit numeric value
+// Default: 1
+#define ETH0_VLAN_ID 1
+//
+
+// IPv4
+// Enable IPv4 Protocol for Network Interface
+#define ETH0_IP4_ENABLE 1
+
+// IP Address
+// Static IPv4 Address in text representation
+// Default: "192.168.0.100"
+#define ETH0_IP4_ADDR "192.168.0.100"
+
+// Subnet mask
+// Local Subnet mask in text representation
+// Default: "255.255.255.0"
+#define ETH0_IP4_MASK "255.255.255.0"
+
+// Default Gateway
+// IP Address of Default Gateway in text representation
+// Default: "192.168.0.254"
+#define ETH0_IP4_GATEWAY "192.168.0.254"
+
+// Primary DNS Server
+// IP Address of Primary DNS Server in text representation
+// Default: "8.8.8.8"
+#define ETH0_IP4_PRIMARY_DNS "8.8.8.8"
+
+// Secondary DNS Server
+// IP Address of Secondary DNS Server in text representation
+// Default: "8.8.4.4"
+#define ETH0_IP4_SECONDARY_DNS "8.8.4.4"
+
+// IP Fragmentation
+// This option enables fragmentation of outgoing IP datagrams,
+// and reassembling the fragments of incoming IP datagrams.
+// Default: enabled
+#define ETH0_IP4_FRAG_ENABLE 1
+
+// MTU size <576-1500>
+// Maximum Transmission Unit in bytes
+// Default: 1500
+#define ETH0_IP4_MTU 1500
+//
+
+// ARP Address Resolution
+// ARP cache and node address resolver settings
+// Cache Table size <5-100>
+// Number of cached MAC/IP addresses
+// Default: 10
+#define ETH0_ARP_TAB_SIZE 10
+
+// Cache Timeout in seconds <5-255>
+// A timeout for cached hardware/IP addresses
+// Default: 150
+#define ETH0_ARP_CACHE_TOUT 150
+
+// Number of Retries <0-20>
+// Number of Retries to resolve an IP address
+// before ARP module gives up
+// Default: 4
+#define ETH0_ARP_MAX_RETRY 4
+
+// Resend Timeout in seconds <1-10>
+// A timeout to resend the ARP Request
+// Default: 2
+#define ETH0_ARP_RESEND_TOUT 2
+
+// Send Notification on Address changes
+// When this option is enabled, the embedded host
+// will send a Gratuitous ARP notification at startup,
+// or when the device IP address has changed.
+// Default: Disabled
+#define ETH0_ARP_NOTIFY 0
+//
+
+// IGMP Group Management
+// Enable or disable Internet Group Management Protocol
+#define ETH0_IGMP_ENABLE 0
+
+// Membership Table size <2-50>
+// Number of Groups this host can join
+// Default: 5
+#define ETH0_IGMP_TAB_SIZE 5
+//
+
+// NetBIOS Name Service
+// When this option is enabled, the embedded host can be
+// accessed by its name on local LAN using NBNS protocol.
+#define ETH0_NBNS_ENABLE 1
+
+// Dynamic Host Configuration
+// When this option is enabled, local IP address, Net Mask
+// and Default Gateway are obtained automatically from
+// the DHCP Server on local LAN.
+#define ETH0_DHCP_ENABLE 1
+
+// Vendor Class Identifier
+// This value is optional. If specified, it is added
+// to DHCP request message, identifying vendor type.
+// Default: ""
+#define ETH0_DHCP_VCID ""
+
+// Bootfile Name
+// This value is optional. If enabled, the Bootfile Name
+// (option 67) is also requested from DHCP server.
+// Default: disabled
+#define ETH0_DHCP_BOOTFILE 0
+
+// NTP Servers
+// This value is optional. If enabled, a list of NTP Servers
+// (option 42) is also requested from DHCP server.
+// Default: disabled
+#define ETH0_DHCP_NTP_SERVERS 0
+//
+
+// Disable ICMP Echo response
+#define ETH0_ICMP_NO_ECHO 0
+//
+
+// IPv6
+// Enable IPv6 Protocol for Network Interface
+#define ETH0_IP6_ENABLE 1
+
+// IPv6 Address
+// Static IPv6 Address in text representation
+// Use unspecified address "::" when static
+// IPv6 address is not used.
+// Default: "fec0::2"
+#define ETH0_IP6_ADDR "fec0::2"
+
+// Subnet prefix-length <1-128>
+// Number of bits that define network address
+// Default: 64
+#define ETH0_IP6_PREFIX_LEN 64
+
+// Default Gateway
+// Default Gateway IPv6 Address in text representation
+// Default: "fec0::1"
+#define ETH0_IP6_GATEWAY "fec0::1"
+
+// Primary DNS Server
+// Primary DNS Server IPv6 Address in text representation
+// Default: "2001:4860:4860::8888"
+#define ETH0_IP6_PRIMARY_DNS "2001:4860:4860::8888"
+
+// Secondary DNS Server
+// Secondary DNS Server IPv6 Address in text representation
+// Default: "2001:4860:4860::8844"
+#define ETH0_IP6_SECONDARY_DNS "2001:4860:4860::8844"
+
+// Neighbor Discovery
+// Neighbor cache and node address resolver settings
+// Cache Table size <5-100>
+// Number of cached node addresses
+// Default: 5
+#define ETH0_NDP_TAB_SIZE 5
+
+// Cache Timeout in seconds <5-255>
+// Timeout for cached node addresses
+// Default: 150
+#define ETH0_NDP_CACHE_TOUT 150
+
+// Number of Retries <0-20>
+// Number of retries to resolve an IP address
+// before NDP module gives up
+// Default: 4
+#define ETH0_NDP_MAX_RETRY 4
+
+// Resend Timeout in seconds <1-10>
+// A timeout to resend Neighbor Solicitation
+// Default: 2
+#define ETH0_NDP_RESEND_TOUT 2
+//
+
+// Dynamic Host Configuration
+// When this option is enabled, local IPv6 address is
+// automatically configured.
+#define ETH0_DHCP6_ENABLE 1
+
+// DHCPv6 Client Mode <0=>Stateless Mode <1=>Statefull Mode
+// Stateless DHCPv6 Client uses router advertisements
+// for IPv6 address autoconfiguration (SLAAC).
+// Statefull DHCPv6 Client connects to DHCPv6 server for a
+// leased IPv6 address and DNS server IPv6 addresses.
+#define ETH0_DHCP6_MODE 1
+
+// Vendor Class Option
+// If enabled, Vendor Class option is added to DHCPv6
+// request message, identifying vendor type.
+// Default: disabled
+#define ETH0_DHCP6_VCLASS_ENABLE 0
+
+// Enterprise ID
+// Enterprise-number as registered with IANA.
+// Default: 0 (Reserved)
+#define ETH0_DHCP6_VCLASS_EID 0
+
+// Vendor Class Data
+// This string identifies vendor type.
+// Default: ""
+#define ETH0_DHCP6_VCLASS_DATA ""
+//
+//
+
+// Disable ICMP6 Echo response
+#define ETH0_ICMP6_NO_ECHO 0
+//
+
+// OS Resource Settings
+// These settings are used to optimize usage of OS resources.
+// Interface Thread Stack Size <512-65535:4>
+// Default: 512 bytes
+#define ETH0_THREAD_STACK_SIZE 512
+
+// Interface Thread Priority
+#define ETH0_THREAD_PRIORITY osPriorityAboveNormal
+
+//
+//
+
+//------------- <<< end of configuration section >>> ---------------------------
diff --git a/MDK/RTE/Network/Net_Config_TCP.h b/MDK/RTE/Network/Net_Config_TCP.h
new file mode 100644
index 0000000..79ba88c
--- /dev/null
+++ b/MDK/RTE/Network/Net_Config_TCP.h
@@ -0,0 +1,69 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name: Net_Config_TCP.h
+ * Purpose: Network Configuration for TCP Sockets
+ * Rev.: V7.1.1
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// TCP Sockets
+#define TCP_ENABLE 1
+
+// Number of TCP Sockets <1-20>
+// Number of available TCP sockets
+// Default: 6
+#define TCP_NUM_SOCKS 6
+
+// Number of Retries <0-20>
+// How many times TCP module will try to retransmit data
+// before giving up. Increase this value for high-latency
+// and low throughput networks.
+// Default: 5
+#define TCP_MAX_RETRY 5
+
+// Retry Timeout in seconds <1-10>
+// If data frame not acknowledged within this time frame,
+// TCP module will try to resend the data again.
+// Default: 4
+#define TCP_RETRY_TOUT 4
+
+// Default Connect Timeout in seconds <1-65535>
+// If no TCP data frame has been exchanged during this time,
+// the TCP connection is either closed or a keep-alive frame
+// is sent to verify that the connection still exists.
+// Default: 120
+#define TCP_DEFAULT_TOUT 120
+
+// Maximum Segment Size <536-1440>
+// The Maximum Segment Size specifies the maximum
+// number of bytes in the TCP segment's Data field.
+// Default: 1440
+#define TCP_MAX_SEG_SIZE 1440
+
+// Receive Window Size <536-65535>
+// Receive Window Size specifies the size of data,
+// that the socket is able to buffer in flow-control mode.
+// Default: 4320
+#define TCP_RECEIVE_WIN_SIZE 4320
+
+//
+
+// TCP Initial Retransmit period in seconds
+#define TCP_INITIAL_RETRY_TOUT 1
+
+// TCP SYN frame retransmit period in seconds
+#define TCP_SYN_RETRY_TOUT 2
+
+// Number of retries to establish a connection
+#define TCP_CONNECT_RETRY 7
+
+// Dynamic port start (default 49152)
+#define TCP_DYN_PORT_START 49152
+
+// Dynamic port end (default 65535)
+#define TCP_DYN_PORT_END 65535
+
+//------------- <<< end of configuration section >>> ---------------------------
diff --git a/MDK/RTE/RTOS/board.c b/MDK/RTE/RTOS/board.c
new file mode 100644
index 0000000..7b3b1e8
--- /dev/null
+++ b/MDK/RTE/RTOS/board.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-05-24 the first version
+ */
+
+#include
+#include
+#include "bsp.h"
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+/*
+ * Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP
+ * the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes
+ */
+#define RT_HEAP_SIZE (32*1024)
+static rt_uint8_t rt_heap[RT_HEAP_SIZE];
+
+RT_WEAK void *rt_heap_begin_get(void)
+{
+ return rt_heap;
+}
+
+RT_WEAK void *rt_heap_end_get(void)
+{
+ return rt_heap + RT_HEAP_SIZE;
+}
+#endif
+
+void rt_os_tick_callback(void)
+{
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ rt_interrupt_leave();
+}
+
+void SysTick_IrqHandler(void)
+{
+ rt_os_tick_callback();
+}
+
+/**
+ * This function will initial your board.
+ */
+void rt_hw_board_init(void)
+{
+//#error "TODO 1: OS Tick Configuration."
+ BSP_Init();
+ /*
+ * TODO 1: OS Tick Configuration
+ * Enable the hardware timer and call the rt_os_tick_callback function
+ * periodically with the frequency RT_TICK_PER_SECOND.
+ */
+
+ /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+ rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
+#endif
+}
+
+#ifdef RT_USING_CONSOLE
+
+static int uart_init(void)
+{
+//#error "TODO 2: Enable the hardware uart and config baudrate."
+ DbgUart_Config(500000);
+ return 0;
+}
+INIT_BOARD_EXPORT(uart_init);
+
+void rt_hw_console_output(const char *str)
+{
+//#error "TODO 3: Output the string 'str' through the uart."
+ rt_enter_critical();
+ DebugUartSend((uint8_t *)str, strlen(str));
+ rt_exit_critical();
+}
+
+#endif
+
diff --git a/MDK/RTE/RTOS/board.c.base@3.1.5 b/MDK/RTE/RTOS/board.c.base@3.1.5
new file mode 100644
index 0000000..e45e75f
--- /dev/null
+++ b/MDK/RTE/RTOS/board.c.base@3.1.5
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-05-24 the first version
+ */
+
+#include
+#include
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+/*
+ * Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP
+ * the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes
+ */
+#define RT_HEAP_SIZE (15*1024)
+static rt_uint8_t rt_heap[RT_HEAP_SIZE];
+
+RT_WEAK void *rt_heap_begin_get(void)
+{
+ return rt_heap;
+}
+
+RT_WEAK void *rt_heap_end_get(void)
+{
+ return rt_heap + RT_HEAP_SIZE;
+}
+#endif
+
+void rt_os_tick_callback(void)
+{
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ rt_interrupt_leave();
+}
+
+/**
+ * This function will initial your board.
+ */
+void rt_hw_board_init(void)
+{
+#error "TODO 1: OS Tick Configuration."
+ /*
+ * TODO 1: OS Tick Configuration
+ * Enable the hardware timer and call the rt_os_tick_callback function
+ * periodically with the frequency RT_TICK_PER_SECOND.
+ */
+
+ /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+ rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
+#endif
+}
+
+#ifdef RT_USING_CONSOLE
+
+static int uart_init(void)
+{
+#error "TODO 2: Enable the hardware uart and config baudrate."
+ return 0;
+}
+INIT_BOARD_EXPORT(uart_init);
+
+void rt_hw_console_output(const char *str)
+{
+#error "TODO 3: Output the string 'str' through the uart."
+}
+
+#endif
+
diff --git a/MDK/RTE/RTOS/rtconfig.h b/MDK/RTE/RTOS/rtconfig.h
new file mode 100644
index 0000000..0aa25fe
--- /dev/null
+++ b/MDK/RTE/RTOS/rtconfig.h
@@ -0,0 +1,139 @@
+/* RT-Thread config file */
+
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Basic Configuration
+// Maximal level of thread priority <8-256>
+// Default: 32
+#define RT_THREAD_PRIORITY_MAX 16
+// OS tick per second
+// Default: 1000 (1ms)
+#define RT_TICK_PER_SECOND 1000
+// Alignment size for CPU architecture data access
+// Default: 4
+#define RT_ALIGN_SIZE 4
+// the max length of object name<2-16>
+// Default: 8
+#define RT_NAME_MAX 10
+// Using RT-Thread components initialization
+// Using RT-Thread components initialization
+#define RT_USING_COMPONENTS_INIT
+//
+
+#define RT_USING_USER_MAIN
+
+// the stack size of main thread<1-4086>
+// Default: 512
+#define RT_MAIN_THREAD_STACK_SIZE 512
+
+//
+
+// Debug Configuration
+// enable kernel debug configuration
+// Default: enable kernel debug configuration
+//#define RT_DEBUG
+//
+// enable components initialization debug configuration<0-1>
+// Default: 0
+#define RT_DEBUG_INIT 0
+// thread stack over flow detect
+// Diable Thread stack over flow detect
+//#define RT_USING_OVERFLOW_CHECK
+//
+//
+
+// Hook Configuration
+// using hook
+// using hook
+//#define RT_USING_HOOK
+//
+// using idle hook
+// using idle hook
+//#define RT_USING_IDLE_HOOK
+//
+//
+
+// Software timers Configuration
+// Enables user timers
+#define RT_USING_TIMER_SOFT 0
+#if RT_USING_TIMER_SOFT == 0
+ #undef RT_USING_TIMER_SOFT
+#endif
+// The priority level of timer thread <0-31>
+// Default: 4
+#define RT_TIMER_THREAD_PRIO 4
+// The stack size of timer thread <0-8192>
+// Default: 512
+#define RT_TIMER_THREAD_STACK_SIZE 512
+//
+
+// IPC(Inter-process communication) Configuration
+// Using Semaphore
+// Using Semaphore
+#define RT_USING_SEMAPHORE
+//
+// Using Mutex
+// Using Mutex
+#define RT_USING_MUTEX
+//
+// Using Event
+// Using Event
+//#define RT_USING_EVENT
+//
+// Using MailBox
+// Using MailBox
+#define RT_USING_MAILBOX
+//
+// Using Message Queue
+// Using Message Queue
+#define RT_USING_MESSAGEQUEUE
+//
+//
+
+// Memory Management Configuration
+// Memory Pool Management
+// Memory Pool Management
+//#define RT_USING_MEMPOOL
+//
+// Dynamic Heap Management(Algorithm: small memory )
+// Dynamic Heap Management
+#define RT_USING_HEAP
+#define RT_USING_SMALL_MEM
+//
+// using tiny size of memory
+// using tiny size of memory
+//#define RT_USING_TINY_SIZE
+//
+//
+
+// Console Configuration
+// Using console
+// Using console
+#define RT_USING_CONSOLE
+//
+// the buffer size of console <1-1024>
+// the buffer size of console
+// Default: 128 (128Byte)
+#define RT_CONSOLEBUF_SIZE 512
+//
+
+// FinSH Configuration
+// include finsh config
+// Select this choice if you using FinSH
+//#include "finsh_config.h"
+//
+//
+
+// Device Configuration
+// using device framework
+// using device framework
+//#define RT_USING_DEVICE
+//
+//
+
+// <<< end of configuration section >>>
+
+#endif
diff --git a/MDK/RTE/RTOS/rtconfig.h.base@3.1.5 b/MDK/RTE/RTOS/rtconfig.h.base@3.1.5
new file mode 100644
index 0000000..5b54665
--- /dev/null
+++ b/MDK/RTE/RTOS/rtconfig.h.base@3.1.5
@@ -0,0 +1,139 @@
+/* RT-Thread config file */
+
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Basic Configuration
+// Maximal level of thread priority <8-256>
+// Default: 32
+#define RT_THREAD_PRIORITY_MAX 32
+// OS tick per second
+// Default: 1000 (1ms)
+#define RT_TICK_PER_SECOND 1000
+// Alignment size for CPU architecture data access
+// Default: 4
+#define RT_ALIGN_SIZE 4
+// the max length of object name<2-16>
+// Default: 8
+#define RT_NAME_MAX 8
+// Using RT-Thread components initialization
+// Using RT-Thread components initialization
+#define RT_USING_COMPONENTS_INIT
+//
+
+#define RT_USING_USER_MAIN
+
+// the stack size of main thread<1-4086>
+// Default: 512
+#define RT_MAIN_THREAD_STACK_SIZE 256
+
+//
+
+// Debug Configuration
+// enable kernel debug configuration
+// Default: enable kernel debug configuration
+//#define RT_DEBUG
+//
+// enable components initialization debug configuration<0-1>
+// Default: 0
+#define RT_DEBUG_INIT 0
+// thread stack over flow detect
+// Diable Thread stack over flow detect
+//#define RT_USING_OVERFLOW_CHECK
+//
+//
+
+// Hook Configuration
+// using hook
+// using hook
+//#define RT_USING_HOOK
+//
+// using idle hook
+// using idle hook
+//#define RT_USING_IDLE_HOOK
+//
+//
+
+// Software timers Configuration
+// Enables user timers
+#define RT_USING_TIMER_SOFT 0
+#if RT_USING_TIMER_SOFT == 0
+ #undef RT_USING_TIMER_SOFT
+#endif
+// The priority level of timer thread <0-31>
+// Default: 4
+#define RT_TIMER_THREAD_PRIO 4
+// The stack size of timer thread <0-8192>
+// Default: 512
+#define RT_TIMER_THREAD_STACK_SIZE 512
+//
+
+// IPC(Inter-process communication) Configuration
+// Using Semaphore
+// Using Semaphore
+#define RT_USING_SEMAPHORE
+//
+// Using Mutex
+// Using Mutex
+//#define RT_USING_MUTEX
+//
+// Using Event
+// Using Event
+//#define RT_USING_EVENT
+//
+// Using MailBox
+// Using MailBox
+#define RT_USING_MAILBOX
+//
+// Using Message Queue
+// Using Message Queue
+//#define RT_USING_MESSAGEQUEUE
+//
+//
+
+// Memory Management Configuration
+// Memory Pool Management
+// Memory Pool Management
+//#define RT_USING_MEMPOOL
+//
+// Dynamic Heap Management(Algorithm: small memory )
+// Dynamic Heap Management
+#define RT_USING_HEAP
+#define RT_USING_SMALL_MEM
+//
+// using tiny size of memory
+// using tiny size of memory
+//#define RT_USING_TINY_SIZE
+//
+//
+
+// Console Configuration
+// Using console
+// Using console
+//#define RT_USING_CONSOLE
+//
+// the buffer size of console <1-1024>
+// the buffer size of console
+// Default: 128 (128Byte)
+#define RT_CONSOLEBUF_SIZE 256
+//
+
+// FinSH Configuration
+// include finsh config
+// Select this choice if you using FinSH
+//#include "finsh_config.h"
+//
+//
+
+// Device Configuration
+// using device framework
+// using device framework
+//#define RT_USING_DEVICE
+//
+//
+
+// <<< end of configuration section >>>
+
+#endif
diff --git a/MDK/RTE/_Debug/RTE_Components.h b/MDK/RTE/_Debug/RTE_Components.h
new file mode 100644
index 0000000..e54c9c5
--- /dev/null
+++ b/MDK/RTE/_Debug/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'BootLoader'
+ * Target: 'Debug'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "HC32F460PETB.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/MDK/RTE/_Release/RTE_Components.h b/MDK/RTE/_Release/RTE_Components.h
new file mode 100644
index 0000000..c4ca988
--- /dev/null
+++ b/MDK/RTE/_Release/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'BootLoader'
+ * Target: 'Release'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "HC32F460PETB.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/MDK/RTE/_i2c_24c256_Debug/RTE_Components.h b/MDK/RTE/_i2c_24c256_Debug/RTE_Components.h
new file mode 100644
index 0000000..bf25b8a
--- /dev/null
+++ b/MDK/RTE/_i2c_24c256_Debug/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'DigitalModule_4Ch'
+ * Target: 'i2c_24c256_Debug'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "HC32F460PETB.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/MDK/RTE/_i2c_24c256_Release/RTE_Components.h b/MDK/RTE/_i2c_24c256_Release/RTE_Components.h
new file mode 100644
index 0000000..b3756ae
--- /dev/null
+++ b/MDK/RTE/_i2c_24c256_Release/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'DigitalModule_4Ch'
+ * Target: 'i2c_24c256_Release'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "HC32F460PETB.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/MDK/RTE/_template_Debug/RTE_Components.h b/MDK/RTE/_template_Debug/RTE_Components.h
new file mode 100644
index 0000000..114830a
--- /dev/null
+++ b/MDK/RTE/_template_Debug/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'DigitalModule_4Ch'
+ * Target: 'template_Debug'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "HC32F460PETB.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/MDK/startup_hc32f460.s b/MDK/startup_hc32f460.s
new file mode 100644
index 0000000..52a327d
--- /dev/null
+++ b/MDK/startup_hc32f460.s
@@ -0,0 +1,621 @@
+;/******************************************************************************
+; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+; *
+; * This software component is licensed by HDSC under BSD 3-Clause license
+; * (the "License"); You may not use this file except in compliance with the
+; * License. You may obtain a copy of the License at:
+; * opensource.org/licenses/BSD-3-Clause
+;/*****************************************************************************/
+;/* Startup for ARM */
+;/* Version V1.0 */
+;/* Date 2018-10-13 */
+;/* Target-mcu HC32F460 */
+;/*****************************************************************************/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00008000
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Peripheral Interrupts
+ DCD IRQ000_Handler ; IRQ000_Handler
+ DCD IRQ001_Handler ; IRQ001_Handler
+ DCD IRQ002_Handler ; IRQ002_Handler
+ DCD IRQ003_Handler ; IRQ003_Handler
+ DCD IRQ004_Handler ; IRQ004_Handler
+ DCD IRQ005_Handler ; IRQ005_Handler
+ DCD IRQ006_Handler ; IRQ006_Handler
+ DCD IRQ007_Handler ; IRQ007_Handler
+ DCD IRQ008_Handler ; IRQ008_Handler
+ DCD IRQ009_Handler ; IRQ009_Handler
+ DCD IRQ010_Handler ; IRQ010_Handler
+ DCD IRQ011_Handler ; IRQ011_Handler
+ DCD IRQ012_Handler ; IRQ012_Handler
+ DCD IRQ013_Handler ; IRQ013_Handler
+ DCD IRQ014_Handler ; IRQ014_Handler
+ DCD IRQ015_Handler ; IRQ015_Handler
+ DCD IRQ016_Handler ; IRQ016_Handler
+ DCD IRQ017_Handler ; IRQ017_Handler
+ DCD IRQ018_Handler ; IRQ018_Handler
+ DCD IRQ019_Handler ; IRQ019_Handler
+ DCD IRQ020_Handler ; IRQ020_Handler
+ DCD IRQ021_Handler ; IRQ021_Handler
+ DCD IRQ022_Handler ; IRQ022_Handler
+ DCD IRQ023_Handler ; IRQ023_Handler
+ DCD IRQ024_Handler ; IRQ024_Handler
+ DCD IRQ025_Handler ; IRQ025_Handler
+ DCD IRQ026_Handler ; IRQ026_Handler
+ DCD IRQ027_Handler ; IRQ027_Handler
+ DCD IRQ028_Handler ; IRQ028_Handler
+ DCD IRQ029_Handler ; IRQ029_Handler
+ DCD IRQ030_Handler ; IRQ030_Handler
+ DCD IRQ031_Handler ; IRQ031_Handler
+ DCD IRQ032_Handler ; IRQ032_Handler
+ DCD IRQ033_Handler ; IRQ033_Handler
+ DCD IRQ034_Handler ; IRQ034_Handler
+ DCD IRQ035_Handler ; IRQ035_Handler
+ DCD IRQ036_Handler ; IRQ036_Handler
+ DCD IRQ037_Handler ; IRQ037_Handler
+ DCD IRQ038_Handler ; IRQ038_Handler
+ DCD IRQ039_Handler ; IRQ039_Handler
+ DCD IRQ040_Handler ; IRQ040_Handler
+ DCD IRQ041_Handler ; IRQ041_Handler
+ DCD IRQ042_Handler ; IRQ042_Handler
+ DCD IRQ043_Handler ; IRQ043_Handler
+ DCD IRQ044_Handler ; IRQ044_Handler
+ DCD IRQ045_Handler ; IRQ045_Handler
+ DCD IRQ046_Handler ; IRQ046_Handler
+ DCD IRQ047_Handler ; IRQ047_Handler
+ DCD IRQ048_Handler ; IRQ048_Handler
+ DCD IRQ049_Handler ; IRQ049_Handler
+ DCD IRQ050_Handler ; IRQ050_Handler
+ DCD IRQ051_Handler ; IRQ051_Handler
+ DCD IRQ052_Handler ; IRQ052_Handler
+ DCD IRQ053_Handler ; IRQ053_Handler
+ DCD IRQ054_Handler ; IRQ054_Handler
+ DCD IRQ055_Handler ; IRQ055_Handler
+ DCD IRQ056_Handler ; IRQ056_Handler
+ DCD IRQ057_Handler ; IRQ057_Handler
+ DCD IRQ058_Handler ; IRQ058_Handler
+ DCD IRQ059_Handler ; IRQ059_Handler
+ DCD IRQ060_Handler ; IRQ060_Handler
+ DCD IRQ061_Handler ; IRQ061_Handler
+ DCD IRQ062_Handler ; IRQ062_Handler
+ DCD IRQ063_Handler ; IRQ063_Handler
+ DCD IRQ064_Handler ; IRQ064_Handler
+ DCD IRQ065_Handler ; IRQ065_Handler
+ DCD IRQ066_Handler ; IRQ066_Handler
+ DCD IRQ067_Handler ; IRQ067_Handler
+ DCD IRQ068_Handler ; IRQ068_Handler
+ DCD IRQ069_Handler ; IRQ069_Handler
+ DCD IRQ070_Handler ; IRQ070_Handler
+ DCD IRQ071_Handler ; IRQ071_Handler
+ DCD IRQ072_Handler ; IRQ072_Handler
+ DCD IRQ073_Handler ; IRQ073_Handler
+ DCD IRQ074_Handler ; IRQ074_Handler
+ DCD IRQ075_Handler ; IRQ075_Handler
+ DCD IRQ076_Handler ; IRQ076_Handler
+ DCD IRQ077_Handler ; IRQ077_Handler
+ DCD IRQ078_Handler ; IRQ078_Handler
+ DCD IRQ079_Handler ; IRQ079_Handler
+ DCD IRQ080_Handler ; IRQ080_Handler
+ DCD IRQ081_Handler ; IRQ081_Handler
+ DCD IRQ082_Handler ; IRQ082_Handler
+ DCD IRQ083_Handler ; IRQ083_Handler
+ DCD IRQ084_Handler ; IRQ084_Handler
+ DCD IRQ085_Handler ; IRQ085_Handler
+ DCD IRQ086_Handler ; IRQ086_Handler
+ DCD IRQ087_Handler ; IRQ087_Handler
+ DCD IRQ088_Handler ; IRQ088_Handler
+ DCD IRQ089_Handler ; IRQ089_Handler
+ DCD IRQ090_Handler ; IRQ090_Handler
+ DCD IRQ091_Handler ; IRQ091_Handler
+ DCD IRQ092_Handler ; IRQ092_Handler
+ DCD IRQ093_Handler ; IRQ093_Handler
+ DCD IRQ094_Handler ; IRQ094_Handler
+ DCD IRQ095_Handler ; IRQ095_Handler
+ DCD IRQ096_Handler ; IRQ096_Handler
+ DCD IRQ097_Handler ; IRQ097_Handler
+ DCD IRQ098_Handler ; IRQ098_Handler
+ DCD IRQ099_Handler ; IRQ099_Handler
+ DCD IRQ100_Handler ; IRQ100_Handler
+ DCD IRQ101_Handler ; IRQ101_Handler
+ DCD IRQ102_Handler ; IRQ102_Handler
+ DCD IRQ103_Handler ; IRQ103_Handler
+ DCD IRQ104_Handler ; IRQ104_Handler
+ DCD IRQ105_Handler ; IRQ105_Handler
+ DCD IRQ106_Handler ; IRQ106_Handler
+ DCD IRQ107_Handler ; IRQ107_Handler
+ DCD IRQ108_Handler ; IRQ108_Handler
+ DCD IRQ109_Handler ; IRQ109_Handler
+ DCD IRQ110_Handler ; IRQ110_Handler
+ DCD IRQ111_Handler ; IRQ111_Handler
+ DCD IRQ112_Handler ; IRQ112_Handler
+ DCD IRQ113_Handler ; IRQ113_Handler
+ DCD IRQ114_Handler ; IRQ114_Handler
+ DCD IRQ115_Handler ; IRQ115_Handler
+ DCD IRQ116_Handler ; IRQ116_Handler
+ DCD IRQ117_Handler ; IRQ117_Handler
+ DCD IRQ118_Handler ; IRQ118_Handler
+ DCD IRQ119_Handler ; IRQ119_Handler
+ DCD IRQ120_Handler ; IRQ120_Handler
+ DCD IRQ121_Handler ; IRQ121_Handler
+ DCD IRQ122_Handler ; IRQ122_Handler
+ DCD IRQ123_Handler ; IRQ123_Handler
+ DCD IRQ124_Handler ; IRQ124_Handler
+ DCD IRQ125_Handler ; IRQ125_Handler
+ DCD IRQ126_Handler ; IRQ126_Handler
+ DCD IRQ127_Handler ; IRQ127_Handler
+ DCD IRQ128_Handler ; IRQ128_Handler
+ DCD IRQ129_Handler ; IRQ129_Handler
+ DCD IRQ130_Handler ; IRQ130_Handler
+ DCD IRQ131_Handler ; IRQ131_Handler
+ DCD IRQ132_Handler ; IRQ132_Handler
+ DCD IRQ133_Handler ; IRQ133_Handler
+ DCD IRQ134_Handler ; IRQ134_Handler
+ DCD IRQ135_Handler ; IRQ135_Handler
+ DCD IRQ136_Handler ; IRQ136_Handler
+ DCD IRQ137_Handler ; IRQ137_Handler
+ DCD IRQ138_Handler ; IRQ138_Handler
+ DCD IRQ139_Handler ; IRQ139_Handler
+ DCD IRQ140_Handler ; IRQ140_Handler
+ DCD IRQ141_Handler ; IRQ141_Handler
+ DCD IRQ142_Handler ; IRQ142_Handler
+ DCD IRQ143_Handler ; IRQ143_Handler
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+SET_SRAM3_WAIT
+ LDR R0, =0x40050804
+ MOV R1, #0x77
+ STR R1, [R0]
+
+ LDR R0, =0x4005080C
+ MOV R1, #0x77
+ STR R1, [R0]
+
+ LDR R0, =0x40050800
+ MOV R1, #0x1100
+ STR R1, [R0]
+
+ LDR R0, =0x40050804
+ MOV R1, #0x76
+ STR R1, [R0]
+
+ LDR R0, =0x4005080C
+ MOV R1, #0x76
+ STR R1, [R0]
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT IRQ000_Handler [WEAK]
+ EXPORT IRQ001_Handler [WEAK]
+ EXPORT IRQ002_Handler [WEAK]
+ EXPORT IRQ003_Handler [WEAK]
+ EXPORT IRQ004_Handler [WEAK]
+ EXPORT IRQ005_Handler [WEAK]
+ EXPORT IRQ006_Handler [WEAK]
+ EXPORT IRQ007_Handler [WEAK]
+ EXPORT IRQ008_Handler [WEAK]
+ EXPORT IRQ009_Handler [WEAK]
+ EXPORT IRQ010_Handler [WEAK]
+ EXPORT IRQ011_Handler [WEAK]
+ EXPORT IRQ012_Handler [WEAK]
+ EXPORT IRQ013_Handler [WEAK]
+ EXPORT IRQ014_Handler [WEAK]
+ EXPORT IRQ015_Handler [WEAK]
+ EXPORT IRQ016_Handler [WEAK]
+ EXPORT IRQ017_Handler [WEAK]
+ EXPORT IRQ018_Handler [WEAK]
+ EXPORT IRQ019_Handler [WEAK]
+ EXPORT IRQ020_Handler [WEAK]
+ EXPORT IRQ021_Handler [WEAK]
+ EXPORT IRQ022_Handler [WEAK]
+ EXPORT IRQ023_Handler [WEAK]
+ EXPORT IRQ024_Handler [WEAK]
+ EXPORT IRQ025_Handler [WEAK]
+ EXPORT IRQ026_Handler [WEAK]
+ EXPORT IRQ027_Handler [WEAK]
+ EXPORT IRQ028_Handler [WEAK]
+ EXPORT IRQ029_Handler [WEAK]
+ EXPORT IRQ030_Handler [WEAK]
+ EXPORT IRQ031_Handler [WEAK]
+ EXPORT IRQ032_Handler [WEAK]
+ EXPORT IRQ033_Handler [WEAK]
+ EXPORT IRQ034_Handler [WEAK]
+ EXPORT IRQ035_Handler [WEAK]
+ EXPORT IRQ036_Handler [WEAK]
+ EXPORT IRQ037_Handler [WEAK]
+ EXPORT IRQ038_Handler [WEAK]
+ EXPORT IRQ039_Handler [WEAK]
+ EXPORT IRQ040_Handler [WEAK]
+ EXPORT IRQ041_Handler [WEAK]
+ EXPORT IRQ042_Handler [WEAK]
+ EXPORT IRQ043_Handler [WEAK]
+ EXPORT IRQ044_Handler [WEAK]
+ EXPORT IRQ045_Handler [WEAK]
+ EXPORT IRQ046_Handler [WEAK]
+ EXPORT IRQ047_Handler [WEAK]
+ EXPORT IRQ048_Handler [WEAK]
+ EXPORT IRQ049_Handler [WEAK]
+ EXPORT IRQ050_Handler [WEAK]
+ EXPORT IRQ051_Handler [WEAK]
+ EXPORT IRQ052_Handler [WEAK]
+ EXPORT IRQ053_Handler [WEAK]
+ EXPORT IRQ054_Handler [WEAK]
+ EXPORT IRQ055_Handler [WEAK]
+ EXPORT IRQ056_Handler [WEAK]
+ EXPORT IRQ057_Handler [WEAK]
+ EXPORT IRQ058_Handler [WEAK]
+ EXPORT IRQ059_Handler [WEAK]
+ EXPORT IRQ060_Handler [WEAK]
+ EXPORT IRQ061_Handler [WEAK]
+ EXPORT IRQ062_Handler [WEAK]
+ EXPORT IRQ063_Handler [WEAK]
+ EXPORT IRQ064_Handler [WEAK]
+ EXPORT IRQ065_Handler [WEAK]
+ EXPORT IRQ066_Handler [WEAK]
+ EXPORT IRQ067_Handler [WEAK]
+ EXPORT IRQ068_Handler [WEAK]
+ EXPORT IRQ069_Handler [WEAK]
+ EXPORT IRQ070_Handler [WEAK]
+ EXPORT IRQ071_Handler [WEAK]
+ EXPORT IRQ072_Handler [WEAK]
+ EXPORT IRQ073_Handler [WEAK]
+ EXPORT IRQ074_Handler [WEAK]
+ EXPORT IRQ075_Handler [WEAK]
+ EXPORT IRQ076_Handler [WEAK]
+ EXPORT IRQ077_Handler [WEAK]
+ EXPORT IRQ078_Handler [WEAK]
+ EXPORT IRQ079_Handler [WEAK]
+ EXPORT IRQ080_Handler [WEAK]
+ EXPORT IRQ081_Handler [WEAK]
+ EXPORT IRQ082_Handler [WEAK]
+ EXPORT IRQ083_Handler [WEAK]
+ EXPORT IRQ084_Handler [WEAK]
+ EXPORT IRQ085_Handler [WEAK]
+ EXPORT IRQ086_Handler [WEAK]
+ EXPORT IRQ087_Handler [WEAK]
+ EXPORT IRQ088_Handler [WEAK]
+ EXPORT IRQ089_Handler [WEAK]
+ EXPORT IRQ090_Handler [WEAK]
+ EXPORT IRQ091_Handler [WEAK]
+ EXPORT IRQ092_Handler [WEAK]
+ EXPORT IRQ093_Handler [WEAK]
+ EXPORT IRQ094_Handler [WEAK]
+ EXPORT IRQ095_Handler [WEAK]
+ EXPORT IRQ096_Handler [WEAK]
+ EXPORT IRQ097_Handler [WEAK]
+ EXPORT IRQ098_Handler [WEAK]
+ EXPORT IRQ099_Handler [WEAK]
+ EXPORT IRQ100_Handler [WEAK]
+ EXPORT IRQ101_Handler [WEAK]
+ EXPORT IRQ102_Handler [WEAK]
+ EXPORT IRQ103_Handler [WEAK]
+ EXPORT IRQ104_Handler [WEAK]
+ EXPORT IRQ105_Handler [WEAK]
+ EXPORT IRQ106_Handler [WEAK]
+ EXPORT IRQ107_Handler [WEAK]
+ EXPORT IRQ108_Handler [WEAK]
+ EXPORT IRQ109_Handler [WEAK]
+ EXPORT IRQ110_Handler [WEAK]
+ EXPORT IRQ111_Handler [WEAK]
+ EXPORT IRQ112_Handler [WEAK]
+ EXPORT IRQ113_Handler [WEAK]
+ EXPORT IRQ114_Handler [WEAK]
+ EXPORT IRQ115_Handler [WEAK]
+ EXPORT IRQ116_Handler [WEAK]
+ EXPORT IRQ117_Handler [WEAK]
+ EXPORT IRQ118_Handler [WEAK]
+ EXPORT IRQ119_Handler [WEAK]
+ EXPORT IRQ120_Handler [WEAK]
+ EXPORT IRQ121_Handler [WEAK]
+ EXPORT IRQ122_Handler [WEAK]
+ EXPORT IRQ123_Handler [WEAK]
+ EXPORT IRQ124_Handler [WEAK]
+ EXPORT IRQ125_Handler [WEAK]
+ EXPORT IRQ126_Handler [WEAK]
+ EXPORT IRQ127_Handler [WEAK]
+ EXPORT IRQ128_Handler [WEAK]
+ EXPORT IRQ129_Handler [WEAK]
+ EXPORT IRQ130_Handler [WEAK]
+ EXPORT IRQ131_Handler [WEAK]
+ EXPORT IRQ132_Handler [WEAK]
+ EXPORT IRQ133_Handler [WEAK]
+ EXPORT IRQ134_Handler [WEAK]
+ EXPORT IRQ135_Handler [WEAK]
+ EXPORT IRQ136_Handler [WEAK]
+ EXPORT IRQ137_Handler [WEAK]
+ EXPORT IRQ138_Handler [WEAK]
+ EXPORT IRQ139_Handler [WEAK]
+ EXPORT IRQ140_Handler [WEAK]
+ EXPORT IRQ141_Handler [WEAK]
+ EXPORT IRQ142_Handler [WEAK]
+ EXPORT IRQ143_Handler [WEAK]
+IRQ000_Handler
+IRQ001_Handler
+IRQ002_Handler
+IRQ003_Handler
+IRQ004_Handler
+IRQ005_Handler
+IRQ006_Handler
+IRQ007_Handler
+IRQ008_Handler
+IRQ009_Handler
+IRQ010_Handler
+IRQ011_Handler
+IRQ012_Handler
+IRQ013_Handler
+IRQ014_Handler
+IRQ015_Handler
+IRQ016_Handler
+IRQ017_Handler
+IRQ018_Handler
+IRQ019_Handler
+IRQ020_Handler
+IRQ021_Handler
+IRQ022_Handler
+IRQ023_Handler
+IRQ024_Handler
+IRQ025_Handler
+IRQ026_Handler
+IRQ027_Handler
+IRQ028_Handler
+IRQ029_Handler
+IRQ030_Handler
+IRQ031_Handler
+IRQ032_Handler
+IRQ033_Handler
+IRQ034_Handler
+IRQ035_Handler
+IRQ036_Handler
+IRQ037_Handler
+IRQ038_Handler
+IRQ039_Handler
+IRQ040_Handler
+IRQ041_Handler
+IRQ042_Handler
+IRQ043_Handler
+IRQ044_Handler
+IRQ045_Handler
+IRQ046_Handler
+IRQ047_Handler
+IRQ048_Handler
+IRQ049_Handler
+IRQ050_Handler
+IRQ051_Handler
+IRQ052_Handler
+IRQ053_Handler
+IRQ054_Handler
+IRQ055_Handler
+IRQ056_Handler
+IRQ057_Handler
+IRQ058_Handler
+IRQ059_Handler
+IRQ060_Handler
+IRQ061_Handler
+IRQ062_Handler
+IRQ063_Handler
+IRQ064_Handler
+IRQ065_Handler
+IRQ066_Handler
+IRQ067_Handler
+IRQ068_Handler
+IRQ069_Handler
+IRQ070_Handler
+IRQ071_Handler
+IRQ072_Handler
+IRQ073_Handler
+IRQ074_Handler
+IRQ075_Handler
+IRQ076_Handler
+IRQ077_Handler
+IRQ078_Handler
+IRQ079_Handler
+IRQ080_Handler
+IRQ081_Handler
+IRQ082_Handler
+IRQ083_Handler
+IRQ084_Handler
+IRQ085_Handler
+IRQ086_Handler
+IRQ087_Handler
+IRQ088_Handler
+IRQ089_Handler
+IRQ090_Handler
+IRQ091_Handler
+IRQ092_Handler
+IRQ093_Handler
+IRQ094_Handler
+IRQ095_Handler
+IRQ096_Handler
+IRQ097_Handler
+IRQ098_Handler
+IRQ099_Handler
+IRQ100_Handler
+IRQ101_Handler
+IRQ102_Handler
+IRQ103_Handler
+IRQ104_Handler
+IRQ105_Handler
+IRQ106_Handler
+IRQ107_Handler
+IRQ108_Handler
+IRQ109_Handler
+IRQ110_Handler
+IRQ111_Handler
+IRQ112_Handler
+IRQ113_Handler
+IRQ114_Handler
+IRQ115_Handler
+IRQ116_Handler
+IRQ117_Handler
+IRQ118_Handler
+IRQ119_Handler
+IRQ120_Handler
+IRQ121_Handler
+IRQ122_Handler
+IRQ123_Handler
+IRQ124_Handler
+IRQ125_Handler
+IRQ126_Handler
+IRQ127_Handler
+IRQ128_Handler
+IRQ129_Handler
+IRQ130_Handler
+IRQ131_Handler
+IRQ132_Handler
+IRQ133_Handler
+IRQ134_Handler
+IRQ135_Handler
+IRQ136_Handler
+IRQ137_Handler
+IRQ138_Handler
+IRQ139_Handler
+IRQ140_Handler
+IRQ141_Handler
+IRQ142_Handler
+IRQ143_Handler
+ B .
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/Update.exe b/Update.exe
new file mode 100644
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