1、初始程序
This commit is contained in:
cui635
+199
@@ -0,0 +1,199 @@
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{
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"configurations": [
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{
|
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"name": "Debug",
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"includePath": [
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"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\driver\\inc",
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||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\mcu\\common",
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||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\User\\Inc",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\Module\\Debug",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\Module\\SDCard",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\Module\\FatFS\\source",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\Module\\LIS2HH12",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\Module\\RS485",
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||||
"C:\\Keil_v5\\ARM\\ARMCC\\include",
|
||||
"C:\\Keil_v5\\ARM\\ARMCC\\include\\rw",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\MDK",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\User\\Src",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\driver\\src"
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],
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"defines": [
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"__DEBUG",
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||||
"HC32F460",
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||||
"USE_DEVICE_DRIVER_LIB",
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"JEUA",
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||||
"__CC_ARM",
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||||
"__arm__",
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||||
"__align(x)=",
|
||||
"__ALIGNOF__(x)=",
|
||||
"__alignof__(x)=",
|
||||
"__asm(x)=",
|
||||
"__forceinline=",
|
||||
"__restrict=",
|
||||
"__global_reg(n)=",
|
||||
"__inline=",
|
||||
"__int64=long long",
|
||||
"__INTADDR__(expr)=0",
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||||
"__irq=",
|
||||
"__packed=",
|
||||
"__pure=",
|
||||
"__smc(n)=",
|
||||
"__svc(n)=",
|
||||
"__svc_indirect(n)=",
|
||||
"__svc_indirect_r7(n)=",
|
||||
"__value_in_regs=",
|
||||
"__weak=",
|
||||
"__writeonly=",
|
||||
"__declspec(x)=",
|
||||
"__attribute__(x)=",
|
||||
"__nonnull__(x)=",
|
||||
"__register=",
|
||||
"__breakpoint(x)=",
|
||||
"__cdp(x,y,z)=",
|
||||
"__clrex()=",
|
||||
"__clz(x)=0U",
|
||||
"__current_pc()=0U",
|
||||
"__current_sp()=0U",
|
||||
"__disable_fiq()=",
|
||||
"__disable_irq()=",
|
||||
"__dmb(x)=",
|
||||
"__dsb(x)=",
|
||||
"__enable_fiq()=",
|
||||
"__enable_irq()=",
|
||||
"__fabs(x)=0.0",
|
||||
"__fabsf(x)=0.0f",
|
||||
"__force_loads()=",
|
||||
"__force_stores()=",
|
||||
"__isb(x)=",
|
||||
"__ldrex(x)=0U",
|
||||
"__ldrexd(x)=0U",
|
||||
"__ldrt(x)=0U",
|
||||
"__memory_changed()=",
|
||||
"__nop()=",
|
||||
"__pld(...)=",
|
||||
"__pli(...)=",
|
||||
"__qadd(x,y)=0",
|
||||
"__qdbl(x)=0",
|
||||
"__qsub(x,y)=0",
|
||||
"__rbit(x)=0U",
|
||||
"__rev(x)=0U",
|
||||
"__return_address()=0U",
|
||||
"__ror(x,y)=0U",
|
||||
"__schedule_barrier()=",
|
||||
"__semihost(x,y)=0",
|
||||
"__sev()=",
|
||||
"__sqrt(x)=0.0",
|
||||
"__sqrtf(x)=0.0f",
|
||||
"__ssat(x,y)=0",
|
||||
"__strex(x,y)=0U",
|
||||
"__strexd(x,y)=0",
|
||||
"__strt(x,y)=",
|
||||
"__swp(x,y)=0U",
|
||||
"__usat(x,y)=0U",
|
||||
"__wfe()=",
|
||||
"__wfi()=",
|
||||
"__yield()=",
|
||||
"__vfp_status(x,y)=0"
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||||
],
|
||||
"intelliSenseMode": "${default}"
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||||
},
|
||||
{
|
||||
"name": "Release",
|
||||
"includePath": [
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\mcu\\common",
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||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source",
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||||
"d:\\CUI\\Electronics\\SynologyDrive\\driver\\inc",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\bsp\\ev_hc32f460_lqfp100_v2",
|
||||
"C:\\Keil_v5\\ARM\\ARMCC\\include",
|
||||
"C:\\Keil_v5\\ARM\\ARMCC\\include\\rw",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\MDK",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\mcu\\common",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\User\\Src",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\driver\\src",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\Module\\Debug",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\Module\\SDCard",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\Module\\FatFS\\source",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\Module\\LIS2HH12",
|
||||
"d:\\CUI\\Electronics\\SynologyDrive\\HC32F460PRO\\HC32F460JEUA-SonarSenser_V1.5-2024-04-10\\Project\\SonarSensor\\source\\Module\\RS485"
|
||||
],
|
||||
"defines": [
|
||||
"HC32F460",
|
||||
"USE_DEVICE_DRIVER_LIB",
|
||||
"__CC_ARM",
|
||||
"__arm__",
|
||||
"__align(x)=",
|
||||
"__ALIGNOF__(x)=",
|
||||
"__alignof__(x)=",
|
||||
"__asm(x)=",
|
||||
"__forceinline=",
|
||||
"__restrict=",
|
||||
"__global_reg(n)=",
|
||||
"__inline=",
|
||||
"__int64=long long",
|
||||
"__INTADDR__(expr)=0",
|
||||
"__irq=",
|
||||
"__packed=",
|
||||
"__pure=",
|
||||
"__smc(n)=",
|
||||
"__svc(n)=",
|
||||
"__svc_indirect(n)=",
|
||||
"__svc_indirect_r7(n)=",
|
||||
"__value_in_regs=",
|
||||
"__weak=",
|
||||
"__writeonly=",
|
||||
"__declspec(x)=",
|
||||
"__attribute__(x)=",
|
||||
"__nonnull__(x)=",
|
||||
"__register=",
|
||||
"__breakpoint(x)=",
|
||||
"__cdp(x,y,z)=",
|
||||
"__clrex()=",
|
||||
"__clz(x)=0U",
|
||||
"__current_pc()=0U",
|
||||
"__current_sp()=0U",
|
||||
"__disable_fiq()=",
|
||||
"__disable_irq()=",
|
||||
"__dmb(x)=",
|
||||
"__dsb(x)=",
|
||||
"__enable_fiq()=",
|
||||
"__enable_irq()=",
|
||||
"__fabs(x)=0.0",
|
||||
"__fabsf(x)=0.0f",
|
||||
"__force_loads()=",
|
||||
"__force_stores()=",
|
||||
"__isb(x)=",
|
||||
"__ldrex(x)=0U",
|
||||
"__ldrexd(x)=0U",
|
||||
"__ldrt(x)=0U",
|
||||
"__memory_changed()=",
|
||||
"__nop()=",
|
||||
"__pld(...)=",
|
||||
"__pli(...)=",
|
||||
"__qadd(x,y)=0",
|
||||
"__qdbl(x)=0",
|
||||
"__qsub(x,y)=0",
|
||||
"__rbit(x)=0U",
|
||||
"__rev(x)=0U",
|
||||
"__return_address()=0U",
|
||||
"__ror(x,y)=0U",
|
||||
"__schedule_barrier()=",
|
||||
"__semihost(x,y)=0",
|
||||
"__sev()=",
|
||||
"__sqrt(x)=0.0",
|
||||
"__sqrtf(x)=0.0f",
|
||||
"__ssat(x,y)=0",
|
||||
"__strex(x,y)=0U",
|
||||
"__strexd(x,y)=0",
|
||||
"__strt(x,y)=",
|
||||
"__swp(x,y)=0U",
|
||||
"__usat(x,y)=0U",
|
||||
"__wfe()=",
|
||||
"__wfi()=",
|
||||
"__yield()=",
|
||||
"__vfp_status(x,y)=0"
|
||||
],
|
||||
"intelliSenseMode": "${default}"
|
||||
}
|
||||
],
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||||
"version": 4
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||||
}
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+22
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[info] Log at : 2023/11/16|16:57:03|GMT+0800
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[info] Log at : 2023/11/16|16:57:11|GMT+0800
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[info] Log at : 2023/11/22|13:54:46|GMT+0800
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||||
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||||
[info] Log at : 2023/11/22|13:54:54|GMT+0800
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||||
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||||
[info] Log at : 2024/1/9|15:41:17|GMT+0800
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||||
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||||
[info] Log at : 2024/1/9|15:41:52|GMT+0800
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||||
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||||
[info] Log at : 2024/1/15|09:54:51|GMT+0800
|
||||
|
||||
[info] Log at : 2024/1/15|09:58:16|GMT+0800
|
||||
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||||
[info] Log at : 2024/6/7|13:58:44|GMT+0800
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||||
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||||
[info] Log at : 2024/6/7|14:11:09|GMT+0800
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||||
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||||
[info] Log at : 2024/6/12|17:35:35|GMT+0800
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Vendored
+4
@@ -0,0 +1,4 @@
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*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
|
||||
Build target 'Debug'
|
||||
".\output\debug\BombSensor.axf" - 0 Error(s), 0 Warning(s).
|
||||
Build Time Elapsed: 00:00:00
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+1
@@ -0,0 +1 @@
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2024/1/9 15:43:05
|
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@@ -0,0 +1,16 @@
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; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x1FFF8000 0x0002F000 { ; RW data
|
||||
.ANY (+RW +ZI)
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}
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||||
}
|
||||
|
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@@ -0,0 +1,9 @@
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<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
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@@ -0,0 +1,632 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
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<SchemaVersion>1.0</SchemaVersion>
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<Header>### uVision Project, (C) Keil Software</Header>
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<Extensions>
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<tExt>*.txt; *.h; *.inc</tExt>
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<Target>
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<TargetName>Debug</TargetName>
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<HexSelection>1</HexSelection>
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<FlashByte>65535</FlashByte>
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<tvExp>1</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
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<IsCurrentTarget>1</IsCurrentTarget>
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</OPTFL>
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<CpuCode>0</CpuCode>
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<DebugOpt>
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<uSim>0</uSim>
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<uTrg>1</uTrg>
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<sLdApp>1</sLdApp>
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<sGomain>1</sGomain>
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<sDll></sDll>
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<tIfile></tIfile>
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<pMon>BIN\UL2CM3.DLL</pMon>
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</DebugOpt>
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<TargetDriverDllRegistry>
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<SetRegEntry>
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<Number>0</Number>
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<Key>UL2CM3</Key>
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<Name>UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FF1HC32F460_otp -FS13000C00 -FL13FC -FP0($$Device:HC32F460JEUA$FlashARM\HC32F460_512K.FLM) -FP1($$Device:HC32F460JEUA$FlashARM\HC32F460_otp.FLM))</Name>
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|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\driver\src\hc32f460_sdioc.c</PathWithFileName>
|
||||
<FilenameWithoutPath>hc32f460_sdioc.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>19</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\driver\src\hc32f460_dmac.c</PathWithFileName>
|
||||
<FilenameWithoutPath>hc32f460_dmac.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>20</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\driver\src\hc32f460_rtc.c</PathWithFileName>
|
||||
<FilenameWithoutPath>hc32f460_rtc.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>21</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\driver\src\hc32f460_adc.c</PathWithFileName>
|
||||
<FilenameWithoutPath>hc32f460_adc.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Debug</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>4</GroupNumber>
|
||||
<FileNumber>22</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\source\Module\Debug\Debug.c</PathWithFileName>
|
||||
<FilenameWithoutPath>Debug.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Readme</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,35 @@
|
||||
[BREAKPOINTS]
|
||||
ForceImpTypeAny = 0
|
||||
ShowInfoWin = 1
|
||||
EnableFlashBP = 2
|
||||
BPDuringExecution = 0
|
||||
[CFI]
|
||||
CFISize = 0x00
|
||||
CFIAddr = 0x00
|
||||
[CPU]
|
||||
OverrideMemMap = 0
|
||||
AllowSimulation = 1
|
||||
ScriptFile=""
|
||||
[FLASH]
|
||||
CacheExcludeSize = 0x00
|
||||
CacheExcludeAddr = 0x00
|
||||
MinNumBytesFlashDL = 0
|
||||
SkipProgOnCRCMatch = 1
|
||||
VerifyDownload = 1
|
||||
AllowCaching = 1
|
||||
EnableFlashDL = 2
|
||||
Override = 1
|
||||
Device="Cortex-M4"
|
||||
[GENERAL]
|
||||
WorkRAMSize = 0x00
|
||||
WorkRAMAddr = 0x00
|
||||
RAMUsageLimit = 0x00
|
||||
[SWO]
|
||||
SWOLogFile=""
|
||||
[MEM]
|
||||
RdOverrideOrMask = 0x00
|
||||
RdOverrideAndMask = 0xFFFFFFFF
|
||||
RdOverrideAddr = 0xFFFFFFFF
|
||||
WrOverrideOrMask = 0x00
|
||||
WrOverrideAndMask = 0xFFFFFFFF
|
||||
WrOverrideAddr = 0xFFFFFFFF
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'HC32F460'
|
||||
* Target: 'Debug'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460JEUA.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'BombSensor'
|
||||
* Target: 'Release'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'DigitalModule_4Ch'
|
||||
* Target: 'i2c_24c256_Debug'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'DigitalModule_4Ch'
|
||||
* Target: 'i2c_24c256_Release'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'DigitalModule_4Ch'
|
||||
* Target: 'template_Debug'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,621 @@
|
||||
;/******************************************************************************
|
||||
; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
; *
|
||||
; * This software component is licensed by HDSC under BSD 3-Clause license
|
||||
; * (the "License"); You may not use this file except in compliance with the
|
||||
; * License. You may obtain a copy of the License at:
|
||||
; * opensource.org/licenses/BSD-3-Clause
|
||||
;/*****************************************************************************/
|
||||
;/* Startup for ARM */
|
||||
;/* Version V1.0 */
|
||||
;/* Date 2018-10-13 */
|
||||
;/* Target-mcu HC32F460 */
|
||||
;/*****************************************************************************/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00002000
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00002000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; Peripheral Interrupts
|
||||
DCD IRQ000_Handler ; IRQ000_Handler
|
||||
DCD IRQ001_Handler ; IRQ001_Handler
|
||||
DCD IRQ002_Handler ; IRQ002_Handler
|
||||
DCD IRQ003_Handler ; IRQ003_Handler
|
||||
DCD IRQ004_Handler ; IRQ004_Handler
|
||||
DCD IRQ005_Handler ; IRQ005_Handler
|
||||
DCD IRQ006_Handler ; IRQ006_Handler
|
||||
DCD IRQ007_Handler ; IRQ007_Handler
|
||||
DCD IRQ008_Handler ; IRQ008_Handler
|
||||
DCD IRQ009_Handler ; IRQ009_Handler
|
||||
DCD IRQ010_Handler ; IRQ010_Handler
|
||||
DCD IRQ011_Handler ; IRQ011_Handler
|
||||
DCD IRQ012_Handler ; IRQ012_Handler
|
||||
DCD IRQ013_Handler ; IRQ013_Handler
|
||||
DCD IRQ014_Handler ; IRQ014_Handler
|
||||
DCD IRQ015_Handler ; IRQ015_Handler
|
||||
DCD IRQ016_Handler ; IRQ016_Handler
|
||||
DCD IRQ017_Handler ; IRQ017_Handler
|
||||
DCD IRQ018_Handler ; IRQ018_Handler
|
||||
DCD IRQ019_Handler ; IRQ019_Handler
|
||||
DCD IRQ020_Handler ; IRQ020_Handler
|
||||
DCD IRQ021_Handler ; IRQ021_Handler
|
||||
DCD IRQ022_Handler ; IRQ022_Handler
|
||||
DCD IRQ023_Handler ; IRQ023_Handler
|
||||
DCD IRQ024_Handler ; IRQ024_Handler
|
||||
DCD IRQ025_Handler ; IRQ025_Handler
|
||||
DCD IRQ026_Handler ; IRQ026_Handler
|
||||
DCD IRQ027_Handler ; IRQ027_Handler
|
||||
DCD IRQ028_Handler ; IRQ028_Handler
|
||||
DCD IRQ029_Handler ; IRQ029_Handler
|
||||
DCD IRQ030_Handler ; IRQ030_Handler
|
||||
DCD IRQ031_Handler ; IRQ031_Handler
|
||||
DCD IRQ032_Handler ; IRQ032_Handler
|
||||
DCD IRQ033_Handler ; IRQ033_Handler
|
||||
DCD IRQ034_Handler ; IRQ034_Handler
|
||||
DCD IRQ035_Handler ; IRQ035_Handler
|
||||
DCD IRQ036_Handler ; IRQ036_Handler
|
||||
DCD IRQ037_Handler ; IRQ037_Handler
|
||||
DCD IRQ038_Handler ; IRQ038_Handler
|
||||
DCD IRQ039_Handler ; IRQ039_Handler
|
||||
DCD IRQ040_Handler ; IRQ040_Handler
|
||||
DCD IRQ041_Handler ; IRQ041_Handler
|
||||
DCD IRQ042_Handler ; IRQ042_Handler
|
||||
DCD IRQ043_Handler ; IRQ043_Handler
|
||||
DCD IRQ044_Handler ; IRQ044_Handler
|
||||
DCD IRQ045_Handler ; IRQ045_Handler
|
||||
DCD IRQ046_Handler ; IRQ046_Handler
|
||||
DCD IRQ047_Handler ; IRQ047_Handler
|
||||
DCD IRQ048_Handler ; IRQ048_Handler
|
||||
DCD IRQ049_Handler ; IRQ049_Handler
|
||||
DCD IRQ050_Handler ; IRQ050_Handler
|
||||
DCD IRQ051_Handler ; IRQ051_Handler
|
||||
DCD IRQ052_Handler ; IRQ052_Handler
|
||||
DCD IRQ053_Handler ; IRQ053_Handler
|
||||
DCD IRQ054_Handler ; IRQ054_Handler
|
||||
DCD IRQ055_Handler ; IRQ055_Handler
|
||||
DCD IRQ056_Handler ; IRQ056_Handler
|
||||
DCD IRQ057_Handler ; IRQ057_Handler
|
||||
DCD IRQ058_Handler ; IRQ058_Handler
|
||||
DCD IRQ059_Handler ; IRQ059_Handler
|
||||
DCD IRQ060_Handler ; IRQ060_Handler
|
||||
DCD IRQ061_Handler ; IRQ061_Handler
|
||||
DCD IRQ062_Handler ; IRQ062_Handler
|
||||
DCD IRQ063_Handler ; IRQ063_Handler
|
||||
DCD IRQ064_Handler ; IRQ064_Handler
|
||||
DCD IRQ065_Handler ; IRQ065_Handler
|
||||
DCD IRQ066_Handler ; IRQ066_Handler
|
||||
DCD IRQ067_Handler ; IRQ067_Handler
|
||||
DCD IRQ068_Handler ; IRQ068_Handler
|
||||
DCD IRQ069_Handler ; IRQ069_Handler
|
||||
DCD IRQ070_Handler ; IRQ070_Handler
|
||||
DCD IRQ071_Handler ; IRQ071_Handler
|
||||
DCD IRQ072_Handler ; IRQ072_Handler
|
||||
DCD IRQ073_Handler ; IRQ073_Handler
|
||||
DCD IRQ074_Handler ; IRQ074_Handler
|
||||
DCD IRQ075_Handler ; IRQ075_Handler
|
||||
DCD IRQ076_Handler ; IRQ076_Handler
|
||||
DCD IRQ077_Handler ; IRQ077_Handler
|
||||
DCD IRQ078_Handler ; IRQ078_Handler
|
||||
DCD IRQ079_Handler ; IRQ079_Handler
|
||||
DCD IRQ080_Handler ; IRQ080_Handler
|
||||
DCD IRQ081_Handler ; IRQ081_Handler
|
||||
DCD IRQ082_Handler ; IRQ082_Handler
|
||||
DCD IRQ083_Handler ; IRQ083_Handler
|
||||
DCD IRQ084_Handler ; IRQ084_Handler
|
||||
DCD IRQ085_Handler ; IRQ085_Handler
|
||||
DCD IRQ086_Handler ; IRQ086_Handler
|
||||
DCD IRQ087_Handler ; IRQ087_Handler
|
||||
DCD IRQ088_Handler ; IRQ088_Handler
|
||||
DCD IRQ089_Handler ; IRQ089_Handler
|
||||
DCD IRQ090_Handler ; IRQ090_Handler
|
||||
DCD IRQ091_Handler ; IRQ091_Handler
|
||||
DCD IRQ092_Handler ; IRQ092_Handler
|
||||
DCD IRQ093_Handler ; IRQ093_Handler
|
||||
DCD IRQ094_Handler ; IRQ094_Handler
|
||||
DCD IRQ095_Handler ; IRQ095_Handler
|
||||
DCD IRQ096_Handler ; IRQ096_Handler
|
||||
DCD IRQ097_Handler ; IRQ097_Handler
|
||||
DCD IRQ098_Handler ; IRQ098_Handler
|
||||
DCD IRQ099_Handler ; IRQ099_Handler
|
||||
DCD IRQ100_Handler ; IRQ100_Handler
|
||||
DCD IRQ101_Handler ; IRQ101_Handler
|
||||
DCD IRQ102_Handler ; IRQ102_Handler
|
||||
DCD IRQ103_Handler ; IRQ103_Handler
|
||||
DCD IRQ104_Handler ; IRQ104_Handler
|
||||
DCD IRQ105_Handler ; IRQ105_Handler
|
||||
DCD IRQ106_Handler ; IRQ106_Handler
|
||||
DCD IRQ107_Handler ; IRQ107_Handler
|
||||
DCD IRQ108_Handler ; IRQ108_Handler
|
||||
DCD IRQ109_Handler ; IRQ109_Handler
|
||||
DCD IRQ110_Handler ; IRQ110_Handler
|
||||
DCD IRQ111_Handler ; IRQ111_Handler
|
||||
DCD IRQ112_Handler ; IRQ112_Handler
|
||||
DCD IRQ113_Handler ; IRQ113_Handler
|
||||
DCD IRQ114_Handler ; IRQ114_Handler
|
||||
DCD IRQ115_Handler ; IRQ115_Handler
|
||||
DCD IRQ116_Handler ; IRQ116_Handler
|
||||
DCD IRQ117_Handler ; IRQ117_Handler
|
||||
DCD IRQ118_Handler ; IRQ118_Handler
|
||||
DCD IRQ119_Handler ; IRQ119_Handler
|
||||
DCD IRQ120_Handler ; IRQ120_Handler
|
||||
DCD IRQ121_Handler ; IRQ121_Handler
|
||||
DCD IRQ122_Handler ; IRQ122_Handler
|
||||
DCD IRQ123_Handler ; IRQ123_Handler
|
||||
DCD IRQ124_Handler ; IRQ124_Handler
|
||||
DCD IRQ125_Handler ; IRQ125_Handler
|
||||
DCD IRQ126_Handler ; IRQ126_Handler
|
||||
DCD IRQ127_Handler ; IRQ127_Handler
|
||||
DCD IRQ128_Handler ; IRQ128_Handler
|
||||
DCD IRQ129_Handler ; IRQ129_Handler
|
||||
DCD IRQ130_Handler ; IRQ130_Handler
|
||||
DCD IRQ131_Handler ; IRQ131_Handler
|
||||
DCD IRQ132_Handler ; IRQ132_Handler
|
||||
DCD IRQ133_Handler ; IRQ133_Handler
|
||||
DCD IRQ134_Handler ; IRQ134_Handler
|
||||
DCD IRQ135_Handler ; IRQ135_Handler
|
||||
DCD IRQ136_Handler ; IRQ136_Handler
|
||||
DCD IRQ137_Handler ; IRQ137_Handler
|
||||
DCD IRQ138_Handler ; IRQ138_Handler
|
||||
DCD IRQ139_Handler ; IRQ139_Handler
|
||||
DCD IRQ140_Handler ; IRQ140_Handler
|
||||
DCD IRQ141_Handler ; IRQ141_Handler
|
||||
DCD IRQ142_Handler ; IRQ142_Handler
|
||||
DCD IRQ143_Handler ; IRQ143_Handler
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
SET_SRAM3_WAIT
|
||||
LDR R0, =0x40050804
|
||||
MOV R1, #0x77
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x4005080C
|
||||
MOV R1, #0x77
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x40050800
|
||||
MOV R1, #0x1100
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x40050804
|
||||
MOV R1, #0x76
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x4005080C
|
||||
MOV R1, #0x76
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT IRQ000_Handler [WEAK]
|
||||
EXPORT IRQ001_Handler [WEAK]
|
||||
EXPORT IRQ002_Handler [WEAK]
|
||||
EXPORT IRQ003_Handler [WEAK]
|
||||
EXPORT IRQ004_Handler [WEAK]
|
||||
EXPORT IRQ005_Handler [WEAK]
|
||||
EXPORT IRQ006_Handler [WEAK]
|
||||
EXPORT IRQ007_Handler [WEAK]
|
||||
EXPORT IRQ008_Handler [WEAK]
|
||||
EXPORT IRQ009_Handler [WEAK]
|
||||
EXPORT IRQ010_Handler [WEAK]
|
||||
EXPORT IRQ011_Handler [WEAK]
|
||||
EXPORT IRQ012_Handler [WEAK]
|
||||
EXPORT IRQ013_Handler [WEAK]
|
||||
EXPORT IRQ014_Handler [WEAK]
|
||||
EXPORT IRQ015_Handler [WEAK]
|
||||
EXPORT IRQ016_Handler [WEAK]
|
||||
EXPORT IRQ017_Handler [WEAK]
|
||||
EXPORT IRQ018_Handler [WEAK]
|
||||
EXPORT IRQ019_Handler [WEAK]
|
||||
EXPORT IRQ020_Handler [WEAK]
|
||||
EXPORT IRQ021_Handler [WEAK]
|
||||
EXPORT IRQ022_Handler [WEAK]
|
||||
EXPORT IRQ023_Handler [WEAK]
|
||||
EXPORT IRQ024_Handler [WEAK]
|
||||
EXPORT IRQ025_Handler [WEAK]
|
||||
EXPORT IRQ026_Handler [WEAK]
|
||||
EXPORT IRQ027_Handler [WEAK]
|
||||
EXPORT IRQ028_Handler [WEAK]
|
||||
EXPORT IRQ029_Handler [WEAK]
|
||||
EXPORT IRQ030_Handler [WEAK]
|
||||
EXPORT IRQ031_Handler [WEAK]
|
||||
EXPORT IRQ032_Handler [WEAK]
|
||||
EXPORT IRQ033_Handler [WEAK]
|
||||
EXPORT IRQ034_Handler [WEAK]
|
||||
EXPORT IRQ035_Handler [WEAK]
|
||||
EXPORT IRQ036_Handler [WEAK]
|
||||
EXPORT IRQ037_Handler [WEAK]
|
||||
EXPORT IRQ038_Handler [WEAK]
|
||||
EXPORT IRQ039_Handler [WEAK]
|
||||
EXPORT IRQ040_Handler [WEAK]
|
||||
EXPORT IRQ041_Handler [WEAK]
|
||||
EXPORT IRQ042_Handler [WEAK]
|
||||
EXPORT IRQ043_Handler [WEAK]
|
||||
EXPORT IRQ044_Handler [WEAK]
|
||||
EXPORT IRQ045_Handler [WEAK]
|
||||
EXPORT IRQ046_Handler [WEAK]
|
||||
EXPORT IRQ047_Handler [WEAK]
|
||||
EXPORT IRQ048_Handler [WEAK]
|
||||
EXPORT IRQ049_Handler [WEAK]
|
||||
EXPORT IRQ050_Handler [WEAK]
|
||||
EXPORT IRQ051_Handler [WEAK]
|
||||
EXPORT IRQ052_Handler [WEAK]
|
||||
EXPORT IRQ053_Handler [WEAK]
|
||||
EXPORT IRQ054_Handler [WEAK]
|
||||
EXPORT IRQ055_Handler [WEAK]
|
||||
EXPORT IRQ056_Handler [WEAK]
|
||||
EXPORT IRQ057_Handler [WEAK]
|
||||
EXPORT IRQ058_Handler [WEAK]
|
||||
EXPORT IRQ059_Handler [WEAK]
|
||||
EXPORT IRQ060_Handler [WEAK]
|
||||
EXPORT IRQ061_Handler [WEAK]
|
||||
EXPORT IRQ062_Handler [WEAK]
|
||||
EXPORT IRQ063_Handler [WEAK]
|
||||
EXPORT IRQ064_Handler [WEAK]
|
||||
EXPORT IRQ065_Handler [WEAK]
|
||||
EXPORT IRQ066_Handler [WEAK]
|
||||
EXPORT IRQ067_Handler [WEAK]
|
||||
EXPORT IRQ068_Handler [WEAK]
|
||||
EXPORT IRQ069_Handler [WEAK]
|
||||
EXPORT IRQ070_Handler [WEAK]
|
||||
EXPORT IRQ071_Handler [WEAK]
|
||||
EXPORT IRQ072_Handler [WEAK]
|
||||
EXPORT IRQ073_Handler [WEAK]
|
||||
EXPORT IRQ074_Handler [WEAK]
|
||||
EXPORT IRQ075_Handler [WEAK]
|
||||
EXPORT IRQ076_Handler [WEAK]
|
||||
EXPORT IRQ077_Handler [WEAK]
|
||||
EXPORT IRQ078_Handler [WEAK]
|
||||
EXPORT IRQ079_Handler [WEAK]
|
||||
EXPORT IRQ080_Handler [WEAK]
|
||||
EXPORT IRQ081_Handler [WEAK]
|
||||
EXPORT IRQ082_Handler [WEAK]
|
||||
EXPORT IRQ083_Handler [WEAK]
|
||||
EXPORT IRQ084_Handler [WEAK]
|
||||
EXPORT IRQ085_Handler [WEAK]
|
||||
EXPORT IRQ086_Handler [WEAK]
|
||||
EXPORT IRQ087_Handler [WEAK]
|
||||
EXPORT IRQ088_Handler [WEAK]
|
||||
EXPORT IRQ089_Handler [WEAK]
|
||||
EXPORT IRQ090_Handler [WEAK]
|
||||
EXPORT IRQ091_Handler [WEAK]
|
||||
EXPORT IRQ092_Handler [WEAK]
|
||||
EXPORT IRQ093_Handler [WEAK]
|
||||
EXPORT IRQ094_Handler [WEAK]
|
||||
EXPORT IRQ095_Handler [WEAK]
|
||||
EXPORT IRQ096_Handler [WEAK]
|
||||
EXPORT IRQ097_Handler [WEAK]
|
||||
EXPORT IRQ098_Handler [WEAK]
|
||||
EXPORT IRQ099_Handler [WEAK]
|
||||
EXPORT IRQ100_Handler [WEAK]
|
||||
EXPORT IRQ101_Handler [WEAK]
|
||||
EXPORT IRQ102_Handler [WEAK]
|
||||
EXPORT IRQ103_Handler [WEAK]
|
||||
EXPORT IRQ104_Handler [WEAK]
|
||||
EXPORT IRQ105_Handler [WEAK]
|
||||
EXPORT IRQ106_Handler [WEAK]
|
||||
EXPORT IRQ107_Handler [WEAK]
|
||||
EXPORT IRQ108_Handler [WEAK]
|
||||
EXPORT IRQ109_Handler [WEAK]
|
||||
EXPORT IRQ110_Handler [WEAK]
|
||||
EXPORT IRQ111_Handler [WEAK]
|
||||
EXPORT IRQ112_Handler [WEAK]
|
||||
EXPORT IRQ113_Handler [WEAK]
|
||||
EXPORT IRQ114_Handler [WEAK]
|
||||
EXPORT IRQ115_Handler [WEAK]
|
||||
EXPORT IRQ116_Handler [WEAK]
|
||||
EXPORT IRQ117_Handler [WEAK]
|
||||
EXPORT IRQ118_Handler [WEAK]
|
||||
EXPORT IRQ119_Handler [WEAK]
|
||||
EXPORT IRQ120_Handler [WEAK]
|
||||
EXPORT IRQ121_Handler [WEAK]
|
||||
EXPORT IRQ122_Handler [WEAK]
|
||||
EXPORT IRQ123_Handler [WEAK]
|
||||
EXPORT IRQ124_Handler [WEAK]
|
||||
EXPORT IRQ125_Handler [WEAK]
|
||||
EXPORT IRQ126_Handler [WEAK]
|
||||
EXPORT IRQ127_Handler [WEAK]
|
||||
EXPORT IRQ128_Handler [WEAK]
|
||||
EXPORT IRQ129_Handler [WEAK]
|
||||
EXPORT IRQ130_Handler [WEAK]
|
||||
EXPORT IRQ131_Handler [WEAK]
|
||||
EXPORT IRQ132_Handler [WEAK]
|
||||
EXPORT IRQ133_Handler [WEAK]
|
||||
EXPORT IRQ134_Handler [WEAK]
|
||||
EXPORT IRQ135_Handler [WEAK]
|
||||
EXPORT IRQ136_Handler [WEAK]
|
||||
EXPORT IRQ137_Handler [WEAK]
|
||||
EXPORT IRQ138_Handler [WEAK]
|
||||
EXPORT IRQ139_Handler [WEAK]
|
||||
EXPORT IRQ140_Handler [WEAK]
|
||||
EXPORT IRQ141_Handler [WEAK]
|
||||
EXPORT IRQ142_Handler [WEAK]
|
||||
EXPORT IRQ143_Handler [WEAK]
|
||||
IRQ000_Handler
|
||||
IRQ001_Handler
|
||||
IRQ002_Handler
|
||||
IRQ003_Handler
|
||||
IRQ004_Handler
|
||||
IRQ005_Handler
|
||||
IRQ006_Handler
|
||||
IRQ007_Handler
|
||||
IRQ008_Handler
|
||||
IRQ009_Handler
|
||||
IRQ010_Handler
|
||||
IRQ011_Handler
|
||||
IRQ012_Handler
|
||||
IRQ013_Handler
|
||||
IRQ014_Handler
|
||||
IRQ015_Handler
|
||||
IRQ016_Handler
|
||||
IRQ017_Handler
|
||||
IRQ018_Handler
|
||||
IRQ019_Handler
|
||||
IRQ020_Handler
|
||||
IRQ021_Handler
|
||||
IRQ022_Handler
|
||||
IRQ023_Handler
|
||||
IRQ024_Handler
|
||||
IRQ025_Handler
|
||||
IRQ026_Handler
|
||||
IRQ027_Handler
|
||||
IRQ028_Handler
|
||||
IRQ029_Handler
|
||||
IRQ030_Handler
|
||||
IRQ031_Handler
|
||||
IRQ032_Handler
|
||||
IRQ033_Handler
|
||||
IRQ034_Handler
|
||||
IRQ035_Handler
|
||||
IRQ036_Handler
|
||||
IRQ037_Handler
|
||||
IRQ038_Handler
|
||||
IRQ039_Handler
|
||||
IRQ040_Handler
|
||||
IRQ041_Handler
|
||||
IRQ042_Handler
|
||||
IRQ043_Handler
|
||||
IRQ044_Handler
|
||||
IRQ045_Handler
|
||||
IRQ046_Handler
|
||||
IRQ047_Handler
|
||||
IRQ048_Handler
|
||||
IRQ049_Handler
|
||||
IRQ050_Handler
|
||||
IRQ051_Handler
|
||||
IRQ052_Handler
|
||||
IRQ053_Handler
|
||||
IRQ054_Handler
|
||||
IRQ055_Handler
|
||||
IRQ056_Handler
|
||||
IRQ057_Handler
|
||||
IRQ058_Handler
|
||||
IRQ059_Handler
|
||||
IRQ060_Handler
|
||||
IRQ061_Handler
|
||||
IRQ062_Handler
|
||||
IRQ063_Handler
|
||||
IRQ064_Handler
|
||||
IRQ065_Handler
|
||||
IRQ066_Handler
|
||||
IRQ067_Handler
|
||||
IRQ068_Handler
|
||||
IRQ069_Handler
|
||||
IRQ070_Handler
|
||||
IRQ071_Handler
|
||||
IRQ072_Handler
|
||||
IRQ073_Handler
|
||||
IRQ074_Handler
|
||||
IRQ075_Handler
|
||||
IRQ076_Handler
|
||||
IRQ077_Handler
|
||||
IRQ078_Handler
|
||||
IRQ079_Handler
|
||||
IRQ080_Handler
|
||||
IRQ081_Handler
|
||||
IRQ082_Handler
|
||||
IRQ083_Handler
|
||||
IRQ084_Handler
|
||||
IRQ085_Handler
|
||||
IRQ086_Handler
|
||||
IRQ087_Handler
|
||||
IRQ088_Handler
|
||||
IRQ089_Handler
|
||||
IRQ090_Handler
|
||||
IRQ091_Handler
|
||||
IRQ092_Handler
|
||||
IRQ093_Handler
|
||||
IRQ094_Handler
|
||||
IRQ095_Handler
|
||||
IRQ096_Handler
|
||||
IRQ097_Handler
|
||||
IRQ098_Handler
|
||||
IRQ099_Handler
|
||||
IRQ100_Handler
|
||||
IRQ101_Handler
|
||||
IRQ102_Handler
|
||||
IRQ103_Handler
|
||||
IRQ104_Handler
|
||||
IRQ105_Handler
|
||||
IRQ106_Handler
|
||||
IRQ107_Handler
|
||||
IRQ108_Handler
|
||||
IRQ109_Handler
|
||||
IRQ110_Handler
|
||||
IRQ111_Handler
|
||||
IRQ112_Handler
|
||||
IRQ113_Handler
|
||||
IRQ114_Handler
|
||||
IRQ115_Handler
|
||||
IRQ116_Handler
|
||||
IRQ117_Handler
|
||||
IRQ118_Handler
|
||||
IRQ119_Handler
|
||||
IRQ120_Handler
|
||||
IRQ121_Handler
|
||||
IRQ122_Handler
|
||||
IRQ123_Handler
|
||||
IRQ124_Handler
|
||||
IRQ125_Handler
|
||||
IRQ126_Handler
|
||||
IRQ127_Handler
|
||||
IRQ128_Handler
|
||||
IRQ129_Handler
|
||||
IRQ130_Handler
|
||||
IRQ131_Handler
|
||||
IRQ132_Handler
|
||||
IRQ133_Handler
|
||||
IRQ134_Handler
|
||||
IRQ135_Handler
|
||||
IRQ136_Handler
|
||||
IRQ137_Handler
|
||||
IRQ138_Handler
|
||||
IRQ139_Handler
|
||||
IRQ140_Handler
|
||||
IRQ141_Handler
|
||||
IRQ142_Handler
|
||||
IRQ143_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@@ -0,0 +1,2 @@
|
||||
#include "bps.h"
|
||||
|
||||
@@ -0,0 +1,589 @@
|
||||
#include "sx127x.h"
|
||||
#include "Debug.h"
|
||||
|
||||
#if (LORA_MODULE == SX1278W1)
|
||||
Sx1276Type_t LoRaPara = {
|
||||
.ucChannel = 0,
|
||||
.dwFreqHz = FREQ_CENT,
|
||||
.ucPower = 20,
|
||||
.SignalBw = SX1276_BW_250K,
|
||||
.SpreadFactor = SX1276_SF_512,
|
||||
.ErrorCoding = SX1276_EC_4_6,
|
||||
.RegPreamble = 10,
|
||||
.ucOpModePrev = RFLR_OPMODE_STANDBY,
|
||||
.bAntSwPrev = RF_ANT_RECEIVER,
|
||||
.RegBuff = 0,
|
||||
.State = SX1276_IDLE,
|
||||
.ucRxPacketSize = 0,
|
||||
.ucTxPacketSize = 0,
|
||||
.RxCallBack = NULL,
|
||||
};
|
||||
|
||||
void LoraReset(void)
|
||||
{
|
||||
LORA_RESET_CLR();
|
||||
Ddl_Delay1ms(1);
|
||||
LORA_RESET_SET();
|
||||
}
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
void SX1276SetAntSw(Sx1276AntStatus_m Status)
|
||||
{
|
||||
switch(Status){
|
||||
case RF_ANT_TRANSMITTER:
|
||||
LORA_ANTTXEN();
|
||||
break;
|
||||
case RF_ANT_RECEIVER:
|
||||
LORA_ANTRXEN();
|
||||
break;
|
||||
case RF_ANT_CLOSE:
|
||||
LORA_ANTCLOSE();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void SX1276ReadBuffer(uint8_t ucAddr, uint8_t *pucBuff, uint8_t ucLen)
|
||||
{
|
||||
uint8_t ucCnt;
|
||||
LORA_SPI_NSS_CLR();
|
||||
LORA_SPI_READ_WRITE(ucAddr & 0x7F);
|
||||
for( ucCnt = 0; ucCnt < ucLen; ucCnt++ ){
|
||||
pucBuff[ucCnt] = LORA_SPI_READ_WRITE(0);
|
||||
}
|
||||
LORA_SPI_NSS_SET();
|
||||
}
|
||||
|
||||
void SX1276WriteBuffer(uint8_t ucAddr, uint8_t *pucBuff, uint8_t ucLen)
|
||||
{
|
||||
uint8_t ucCnt;
|
||||
LORA_SPI_NSS_CLR();
|
||||
LORA_SPI_READ_WRITE(ucAddr | 0x80);
|
||||
for( ucCnt = 0; ucCnt < ucLen; ucCnt++ ){
|
||||
LORA_SPI_READ_WRITE(pucBuff[ucCnt]);
|
||||
}
|
||||
LORA_SPI_NSS_SET();
|
||||
}
|
||||
|
||||
void SX1276Write(uint8_t ucAddr, uint8_t ucData)
|
||||
{
|
||||
SX1276WriteBuffer(ucAddr, &ucData, 1);
|
||||
}
|
||||
|
||||
void SX1276Read(uint8_t ucAddr, uint8_t * pucData)
|
||||
{
|
||||
SX1276ReadBuffer(ucAddr, pucData, 1);
|
||||
}
|
||||
|
||||
void SX1276WriteFifo(uint8_t *pucBuff, uint8_t ucLen)
|
||||
{
|
||||
SX1276WriteBuffer(0, pucBuff, ucLen);
|
||||
}
|
||||
|
||||
void SX1276ReadFifo(uint8_t *pucBuff, uint8_t ucLen)
|
||||
{
|
||||
SX1276ReadBuffer(0, pucBuff, ucLen);
|
||||
}
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
void SX1276LoRaSetNbTrigPeaks(uint8_t ucValue)
|
||||
{
|
||||
SX1276Read(0x31, &(LoRaPara.RegBuff.RegTestReserved31));
|
||||
LoRaPara.RegBuff.RegTestReserved31 = (LoRaPara.RegBuff.RegTestReserved31 & 0xF8) | ucValue;
|
||||
SX1276Write(0x31, LoRaPara.RegBuff.RegTestReserved31 );
|
||||
}
|
||||
|
||||
void SX1276LoRaSetSignalBandwidth(Sx1276BwType Bw)
|
||||
{
|
||||
SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1));
|
||||
LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_BW_MASK) | Bw;
|
||||
SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1);
|
||||
LoRaPara.SignalBw = Bw;
|
||||
}
|
||||
|
||||
void SX1276LoRaSetSpreadingFactor(Sx1276SpreadFactorType Factor)
|
||||
{
|
||||
if (Factor > SX1276_SF_4096){
|
||||
Factor = SX1276_SF_4096;
|
||||
}
|
||||
else if (Factor < SX1276_SF_64){
|
||||
Factor = SX1276_SF_64;
|
||||
}
|
||||
if (Factor == SX1276_SF_64){
|
||||
SX1276LoRaSetNbTrigPeaks(5);
|
||||
}
|
||||
else{
|
||||
SX1276LoRaSetNbTrigPeaks(3);
|
||||
}
|
||||
SX1276Read(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2));
|
||||
LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SF_MASK ) | Factor;
|
||||
SX1276Write(REG_LR_MODEMCONFIG2, LoRaPara.RegBuff.RegModemConfig2);
|
||||
LoRaPara.SpreadFactor = Factor;
|
||||
}
|
||||
|
||||
void SX1276LoRaSetErrorCoding(Sx1276ErrorCodingType Value){
|
||||
SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1));
|
||||
LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_CODINGRATE_MASK ) | Value;
|
||||
SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1 );
|
||||
LoRaPara.ErrorCoding = Value;
|
||||
}
|
||||
|
||||
void SX1276LoRaSetFreqHz(uint32_t dwFreqHz)
|
||||
{
|
||||
LoRaPara.dwFreqHz = dwFreqHz;
|
||||
dwFreqHz = ( uint32_t )( ( double )dwFreqHz / ( double )FREQ_STEP );
|
||||
LoRaPara.RegBuff.RegFrfMsb = ( uint8_t )( ( dwFreqHz >> 16 ) & 0xFF );
|
||||
LoRaPara.RegBuff.RegFrfMid = ( uint8_t )( ( dwFreqHz >> 8 ) & 0xFF );
|
||||
LoRaPara.RegBuff.RegFrfLsb = ( uint8_t )( dwFreqHz & 0xFF );
|
||||
SX1276WriteBuffer(REG_LR_FRFMSB, &(LoRaPara.RegBuff.RegFrfMsb), 3);
|
||||
}
|
||||
|
||||
void SX1276LoRaSetSymbTimeout(uint16_t ucValue)
|
||||
{
|
||||
SX1276ReadBuffer(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2), 2);
|
||||
LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK) | (( ucValue >> 8) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK );
|
||||
LoRaPara.RegBuff.RegSymbTimeoutLsb = ucValue & 0xFF;
|
||||
SX1276WriteBuffer(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2), 2);
|
||||
}
|
||||
|
||||
void SX1276LoRaSetLowDatarateOptimize(bool bEnable)
|
||||
{
|
||||
SX1276Read(REG_LR_MODEMCONFIG3, &(LoRaPara.RegBuff.RegModemConfig3));
|
||||
LoRaPara.RegBuff.RegModemConfig3 = (LoRaPara.RegBuff.RegModemConfig3 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) | ( bEnable << 3 );
|
||||
SX1276Write(REG_LR_MODEMCONFIG3, LoRaPara.RegBuff.RegModemConfig3);
|
||||
}
|
||||
|
||||
void SX1276LoRaSetPAOutput(uint8_t ucOutputPin)
|
||||
{
|
||||
SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig));
|
||||
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_MASK ) | ucOutputPin;
|
||||
SX1276Write(REG_LR_PACONFIG, LoRaPara.RegBuff.RegPaConfig );
|
||||
}
|
||||
|
||||
void SX1276LoRaSetPa20dBm(bool bEnable)
|
||||
{
|
||||
SX1276Read(REG_LR_PADAC, &(LoRaPara.RegBuff.RegPaDac));
|
||||
SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig));
|
||||
if ((LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST ) {
|
||||
if( bEnable == true ){
|
||||
LoRaPara.RegBuff.RegPaDac = 0x87;
|
||||
}
|
||||
}
|
||||
else{
|
||||
LoRaPara.RegBuff.RegPaDac = 0x84;
|
||||
}
|
||||
SX1276Write(REG_LR_PADAC, LoRaPara.RegBuff.RegPaDac );
|
||||
}
|
||||
|
||||
void SX1276LoRaSetRfPower(int8_t sbPower)
|
||||
{
|
||||
SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig));
|
||||
SX1276Read(REG_LR_PADAC, &(LoRaPara.RegBuff.RegPaDac));
|
||||
if ((LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST ) {
|
||||
if ((LoRaPara.RegBuff.RegPaDac & 0x87) == 0x87){
|
||||
if( sbPower < 5 ){
|
||||
sbPower = 5;
|
||||
}
|
||||
if( sbPower > 20){
|
||||
sbPower = 20;
|
||||
}
|
||||
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
|
||||
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) |
|
||||
( uint8_t )( ( uint16_t )( sbPower - 5 ) & 0x0F );
|
||||
}
|
||||
else{
|
||||
if( sbPower < 2){
|
||||
sbPower = 2;
|
||||
}
|
||||
if( sbPower > 17){
|
||||
sbPower = 17;
|
||||
}
|
||||
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
|
||||
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) |
|
||||
( uint8_t )( ( uint16_t )( sbPower - 2 ) & 0x0F );
|
||||
}
|
||||
}
|
||||
else{
|
||||
if( sbPower < -1){
|
||||
sbPower = -1;
|
||||
}
|
||||
if( sbPower > 14){
|
||||
sbPower = 14;
|
||||
}
|
||||
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
|
||||
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) |
|
||||
( uint8_t )( ( uint16_t )( sbPower + 1 ) & 0x0F );
|
||||
}
|
||||
SX1276Write(REG_LR_PACONFIG, LoRaPara.RegBuff.RegPaConfig);
|
||||
LoRaPara.ucPower = sbPower;
|
||||
}
|
||||
|
||||
void SX1276LoRaSetOpMode(Sx1276OpModeType ucOpMode)
|
||||
{
|
||||
Sx1276AntStatus_m bAntSwStatus = RF_ANT_RECEIVER;
|
||||
LoRaPara.ucOpModePrev = LoRaPara.RegBuff.RegOpMode & ~RFLR_OPMODE_MASK;
|
||||
if( ucOpMode != LoRaPara.ucOpModePrev){
|
||||
if(ucOpMode == RFLR_OPMODE_TRANSMITTER){
|
||||
bAntSwStatus = RF_ANT_TRANSMITTER;
|
||||
}
|
||||
else if(ucOpMode == RFLR_OPMODE_RECEIVER){
|
||||
bAntSwStatus = RF_ANT_RECEIVER;
|
||||
}
|
||||
else {
|
||||
bAntSwStatus = RF_ANT_CLOSE;
|
||||
}
|
||||
if( bAntSwStatus != LoRaPara.bAntSwPrev ){
|
||||
LoRaPara.bAntSwPrev = bAntSwStatus;
|
||||
SX1276SetAntSw(bAntSwStatus);
|
||||
}
|
||||
LoRaPara.RegBuff.RegOpMode = (LoRaPara.RegBuff.RegOpMode & RFLR_OPMODE_MASK ) | ucOpMode;
|
||||
SX1276Write( REG_LR_OPMODE, LoRaPara.RegBuff.RegOpMode);
|
||||
}
|
||||
}
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
void Sx1276LoRaEnterRx(void)
|
||||
{
|
||||
uint8_t ucCnt;
|
||||
SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);
|
||||
LoRaPara.RegBuff.RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | RFLR_IRQFLAGS_VALIDHEADER | RFLR_IRQFLAGS_TXDONE;
|
||||
SX1276Write(REG_LR_IRQFLAGSMASK, LoRaPara.RegBuff.RegIrqFlagsMask);
|
||||
LoRaPara.RegBuff.RegHopPeriod = 255;
|
||||
SX1276Write(REG_LR_HOPPERIOD, LoRaPara.RegBuff.RegHopPeriod );
|
||||
// RxDone RxTimeout FhssChangeChannel ValidHeader
|
||||
LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_01 | RFLR_DIOMAPPING1_DIO3_01;
|
||||
// CadDetected ModeReady
|
||||
LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00;
|
||||
SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2);
|
||||
LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoRxBaseAddr;
|
||||
SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr);
|
||||
SX1276LoRaSetOpMode(RFLR_OPMODE_RECEIVER);
|
||||
for (ucCnt=0; ucCnt< LORA_BUFF_SIZE; ucCnt++){
|
||||
LoRaPara.RxTxBuff[ucCnt] = 0;
|
||||
}
|
||||
LoRaPara.State = SX1276_IDLE;//COMST_RX
|
||||
uint8_t temp;
|
||||
SX1276Read(REG_LR_IRQFLAGS, &temp);
|
||||
}
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
void Sx1276LoRaInit(void (*RxCallBack)(uint8_t *rBuff, uint8_t rlen))
|
||||
{
|
||||
if(RxCallBack != NULL) {
|
||||
LoRaPara.RxCallBack = RxCallBack;
|
||||
}
|
||||
LoraReset();
|
||||
SX1276LoRaSetOpMode(RFLR_OPMODE_SLEEP);
|
||||
LoRaPara.RegBuff.RegOpMode = (LoRaPara.RegBuff.RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON;
|
||||
SX1276Write(REG_LR_OPMODE, LoRaPara.RegBuff.RegOpMode );
|
||||
SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);
|
||||
// RxDone RxTimeout FhssChangeChannel ValidHeader
|
||||
LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_01;
|
||||
// CadDetected ModeReady
|
||||
LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00;
|
||||
SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2 );
|
||||
SX1276ReadBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS);
|
||||
LoRaPara.State = SX1276_BUSY;
|
||||
SX1276Read(REG_LR_VERSION, &(LoRaPara.RegBuff.RegVersion));
|
||||
SX1276ReadBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS);
|
||||
LoRaPara.RegBuff.RegLna = RFLR_LNA_GAIN_G1;
|
||||
SX1276WriteBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS);
|
||||
// set the RF settings
|
||||
SX1276LoRaSetFreqHz(LoRaPara.dwFreqHz);
|
||||
//REG_LR_MODEMCONFIG1
|
||||
SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1));
|
||||
//SignalBandwidth
|
||||
LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_BW_MASK ) | LoRaPara.SignalBw;
|
||||
//ErrorCoding
|
||||
LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_CODINGRATE_MASK ) | LoRaPara.ErrorCoding;
|
||||
//IMPLICITHEADER
|
||||
LoRaPara.RegBuff.RegModemConfig1 = LoRaPara.RegBuff.RegModemConfig1 | RFLR_MODEMCONFIG1_IMPLICITHEADER_ON;
|
||||
SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1);
|
||||
//REG_LR_MODEMCONFIG2
|
||||
SX1276Read(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2));
|
||||
//SpreadingFactor
|
||||
if( LoRaPara.SpreadFactor == SX1276_SF_64){
|
||||
SX1276LoRaSetNbTrigPeaks(5);
|
||||
SX1276LoRaSetLowDatarateOptimize(true); //低数据速率设置
|
||||
}
|
||||
else{
|
||||
SX1276LoRaSetNbTrigPeaks(3);
|
||||
SX1276LoRaSetLowDatarateOptimize(false); //低数据速率设置
|
||||
}
|
||||
LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SF_MASK ) | LoRaPara.SpreadFactor;
|
||||
//PacketCrcOn
|
||||
LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) | SX1276_CRC_ON; //SX1276_CRC_OFF
|
||||
SX1276Write(REG_LR_MODEMCONFIG2, LoRaPara.RegBuff.RegModemConfig2);
|
||||
LoRaPara.RegBuff.RegModemConfig2 = 0;
|
||||
SX1276Read(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2));
|
||||
|
||||
SX1276LoRaSetSymbTimeout(0x3FF);
|
||||
LoRaPara.RegBuff.RegPreambleMsb= (LoRaPara.RegPreamble >> 8) & 0x00ff;
|
||||
LoRaPara.RegBuff.RegPreambleLsb= LoRaPara.RegPreamble & 0x00ff;
|
||||
SX1276Write(REG_LR_PREAMBLEMSB, LoRaPara.RegBuff.RegPreambleMsb);
|
||||
SX1276Write(REG_LR_PREAMBLELSB, LoRaPara.RegBuff.RegPreambleLsb);
|
||||
SX1276Write(REG_LR_PAYLOADLENGTH, LORA_BUFF_SIZE);
|
||||
SX1276Write(REG_LR_PAYLOADMAXLENGTH, LORA_BUFF_SIZE);
|
||||
LoRaPara.RegBuff.RegPayloadLength = LORA_BUFF_SIZE;
|
||||
|
||||
#ifndef USE_LORA_860_PA
|
||||
if(LoRaPara.dwFreqHz > 860000000 ){
|
||||
SX1276LoRaSetPAOutput(RFLR_PACONFIG_PASELECT_RFO);
|
||||
SX1276LoRaSetPa20dBm(false);
|
||||
LoRaPara.ucPower = 14;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
SX1276LoRaSetPAOutput(RFLR_PACONFIG_PASELECT_PABOOST);
|
||||
SX1276LoRaSetPa20dBm(true);
|
||||
LoRaPara.ucPower = 20;
|
||||
}
|
||||
SX1276LoRaSetRfPower(LoRaPara.ucPower);
|
||||
SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);
|
||||
Sx1276LoRaEnterRx();
|
||||
}
|
||||
|
||||
void IsrSx1276LoRaTxRx(void){
|
||||
switch (LoRaPara.State){
|
||||
case SX1276_IDLE:
|
||||
case SX1276_RX:
|
||||
// Clear Irq
|
||||
SET_LORA_RX_LED();
|
||||
do {
|
||||
SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE);
|
||||
SX1276Read(REG_LR_IRQFLAGS, &(LoRaPara.RegBuff.RegIrqFlags));
|
||||
if((LoRaPara.RegBuff.RegIrqFlags & RFLR_IRQFLAGS_RXDONE) != RFLR_IRQFLAGS_RXDONE)
|
||||
break;
|
||||
}while(1);
|
||||
if((LoRaPara.RegBuff.RegIrqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR ) == RFLR_IRQFLAGS_PAYLOADCRCERROR) {
|
||||
// Clear Irq
|
||||
SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR);
|
||||
LoRaPara.State = SX1276_IDLE;
|
||||
break;
|
||||
}
|
||||
SX1276Read(REG_LR_PKTSNRVALUE, &(LoRaPara.RegBuff.RegPktSnrValue));
|
||||
SX1276Read(REG_LR_RSSIVALUE, &(LoRaPara.RegBuff.RegRssiValue));
|
||||
SX1276Read(REG_LR_PKTRSSIVALUE, &(LoRaPara.RegBuff.RegPktRssiValue));
|
||||
SX1276Read(REG_LR_FIFORXCURRENTADDR, &(LoRaPara.RegBuff.RegFifoRxCurrentAddr));
|
||||
SX1276Read(REG_LR_NBRXBYTES, &(LoRaPara.RegBuff.RegNbRxBytes));
|
||||
LoRaPara.ucRxPacketSize = LoRaPara.RegBuff.RegNbRxBytes;
|
||||
LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoRxCurrentAddr;
|
||||
SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr);
|
||||
SX1276ReadFifo(LoRaPara.RxTxBuff, (LoRaPara.ucRxPacketSize > LORA_BUFF_SIZE) ? LORA_BUFF_SIZE : LoRaPara.ucRxPacketSize);
|
||||
uint8_t ucLen;
|
||||
if(LoRaPara.ucRxPacketSize < LORA_BUFF_SIZE) {
|
||||
ucLen= LoRaPara.ucRxPacketSize;
|
||||
}
|
||||
else {
|
||||
ucLen= LORA_BUFF_SIZE;
|
||||
}
|
||||
LoRaPara.RxTxBuff[ucLen] = 0;
|
||||
if(LoRaPara.RxCallBack != NULL)
|
||||
LoRaPara.RxCallBack(LoRaPara.RxTxBuff, ucLen);
|
||||
|
||||
LoRaPara.ucRxPacketSize = 0;
|
||||
LoRaPara.State = SX1276_IDLE;
|
||||
CLR_LORA_RX_LED();
|
||||
break;
|
||||
case SX1276_TX:
|
||||
// Clear Irq
|
||||
SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE);
|
||||
LORA_TXLED_OFF();
|
||||
Sx1276LoRaEnterRx();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void Sx1276LoRaLoopHandler(void)
|
||||
{
|
||||
if(LORA_GETDIO0() > 0){ // RxDone or TxDone
|
||||
IsrSx1276LoRaTxRx();
|
||||
}
|
||||
}
|
||||
void Sx1276LoRaSendBuffer(uint8_t* pucBuff, uint8_t ucLen)
|
||||
{
|
||||
LoRaPara.State = SX1276_BUSY;
|
||||
if (ucLen > LORA_BUFF_SIZE){
|
||||
ucLen = LORA_BUFF_SIZE;
|
||||
}
|
||||
LoRaPara.ucTxPacketSize = ucLen;
|
||||
while(ucLen--){
|
||||
LoRaPara.RxTxBuff[ucLen] = pucBuff[ucLen];
|
||||
};
|
||||
SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);
|
||||
LoRaPara.RegBuff.RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | RFLR_IRQFLAGS_RXDONE | RFLR_IRQFLAGS_PAYLOADCRCERROR | RFLR_IRQFLAGS_VALIDHEADER;
|
||||
//LoRaPara.RegBuff.RegHopPeriod = 0;
|
||||
//SX1276Write(REG_LR_HOPPERIOD, LoRaPara.RegBuff.RegHopPeriod);
|
||||
SX1276Write(REG_LR_IRQFLAGSMASK, LoRaPara.RegBuff.RegIrqFlagsMask);
|
||||
// Initializes the payload size
|
||||
LoRaPara.RegBuff.RegPayloadLength = LoRaPara.ucTxPacketSize;
|
||||
SX1276Write(REG_LR_PAYLOADLENGTH, LoRaPara.RegBuff.RegPayloadLength);
|
||||
LoRaPara.RegBuff.RegFifoTxBaseAddr = 0x00; // Full buffer used for Tx
|
||||
SX1276Write(REG_LR_FIFOTXBASEADDR, LoRaPara.RegBuff.RegFifoTxBaseAddr);
|
||||
LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoTxBaseAddr;
|
||||
SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr);
|
||||
// Write payload buffer to LORA modem
|
||||
SX1276WriteFifo(LoRaPara.RxTxBuff, LoRaPara.RegBuff.RegPayloadLength);
|
||||
// TxDone RxTimeout FhssChangeChannel ValidHeader
|
||||
LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_01;
|
||||
// PllLock Mode Ready
|
||||
LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_01 | RFLR_DIOMAPPING2_DIO5_00;
|
||||
SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2);
|
||||
SX1276LoRaSetOpMode(RFLR_OPMODE_TRANSMITTER);
|
||||
uint8_t temp;
|
||||
SX1276Read(REG_LR_IRQFLAGS, &temp);
|
||||
LORA_TXLED_ON();
|
||||
LoRaPara.State = SX1276_TX;
|
||||
}
|
||||
|
||||
void Sx1276LoRaSleep(void)
|
||||
{
|
||||
SX1276LoRaSetOpMode(RFLR_OPMODE_SLEEP);//RFLR_OPMODE_STANDBY
|
||||
}
|
||||
|
||||
void Sx1276LoRaWakeup(void)
|
||||
{
|
||||
Sx1276LoRaEnterRx();
|
||||
}
|
||||
|
||||
////////////////////////////////////////
|
||||
//配置本层参数的函数
|
||||
//频道表
|
||||
const uint32_t gdwSx1276ChannelTbl[SX1276_CHANNEL_MAX]={
|
||||
FREQ_CENT-FREQ_DEV*8, FREQ_CENT-FREQ_DEV*7, FREQ_CENT-FREQ_DEV*6, FREQ_CENT-FREQ_DEV*5,
|
||||
FREQ_CENT-FREQ_DEV*4, FREQ_CENT-FREQ_DEV*3, FREQ_CENT-FREQ_DEV*2, FREQ_CENT-FREQ_DEV*1,
|
||||
FREQ_CENT+FREQ_DEV*0, FREQ_CENT+FREQ_DEV*1, FREQ_CENT+FREQ_DEV*2, FREQ_CENT+FREQ_DEV*3,
|
||||
FREQ_CENT+FREQ_DEV*4, FREQ_CENT+FREQ_DEV*5, FREQ_CENT+FREQ_DEV*6, FREQ_CENT+FREQ_DEV*7,
|
||||
FREQ_CENT+FREQ_DEV*8
|
||||
};
|
||||
|
||||
//LORAPT_CHANNEL
|
||||
uint8_t SX1276LoRaReadChannel(void)
|
||||
{
|
||||
return LoRaPara.ucChannel;
|
||||
}
|
||||
|
||||
bool SX1276LoRaWriteChannel(uint8_t Channel)
|
||||
{
|
||||
if(Channel > SX1276_CHANNEL_MAX) {
|
||||
return false;
|
||||
}
|
||||
|
||||
LoRaPara.dwFreqHz = gdwSx1276ChannelTbl[Channel];
|
||||
SX1276LoRaSetFreqHz(LoRaPara.dwFreqHz);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
//LORAPT_FREQ,
|
||||
uint32_t SX1276LoRaReadFreq(void)
|
||||
{
|
||||
return LoRaPara.dwFreqHz;
|
||||
}
|
||||
|
||||
void SX1276LoRaWriteFreq(uint32_t Freq)
|
||||
{
|
||||
SX1276LoRaSetFreqHz(Freq);
|
||||
}
|
||||
|
||||
//LORAPT_BW,
|
||||
uint32_t SX1276LoRaReadBw(void)
|
||||
{
|
||||
return LoRaPara.SignalBw;
|
||||
}
|
||||
|
||||
void SX1276LoRaWriteBw(Sx1276BwType SignalBw)
|
||||
{
|
||||
LoRaPara.SignalBw = SignalBw;
|
||||
SX1276LoRaSetSignalBandwidth(SignalBw);
|
||||
}
|
||||
|
||||
//LORAPT_SF,
|
||||
uint8_t SX1276LoRaReadSf(void)
|
||||
{
|
||||
return LoRaPara.SpreadFactor;
|
||||
}
|
||||
|
||||
void SX1276LoRaWriteSf(Sx1276SpreadFactorType SpreadFactor)
|
||||
{
|
||||
LoRaPara.SpreadFactor = SpreadFactor;
|
||||
SX1276LoRaSetSpreadingFactor(LoRaPara.SpreadFactor);
|
||||
}
|
||||
|
||||
//LORAPT_EC,
|
||||
uint8_t SX1276LoRaReadEc(void)
|
||||
{
|
||||
return LoRaPara.ErrorCoding;
|
||||
}
|
||||
|
||||
void SX1276LoRaWriteEc(Sx1276ErrorCodingType ErrorCoding)
|
||||
{
|
||||
LoRaPara.ErrorCoding = ErrorCoding;
|
||||
SX1276LoRaSetErrorCoding(ErrorCoding);
|
||||
}
|
||||
|
||||
//LORAPT_RSSI,
|
||||
uint32_t SX1276LoRaParaReadRssi(void)
|
||||
{
|
||||
uint32_t rssi;
|
||||
|
||||
SX1276Read(REG_LR_PKTRSSIVALUE, &(LoRaPara.RegBuff.RegPktRssiValue));
|
||||
SX1276Read(REG_LR_RSSIVALUE, &(LoRaPara.RegBuff.RegRssiValue));
|
||||
rssi = (uint16_t)(LoRaPara.RegBuff.RegPktSnrValue)<<16;
|
||||
rssi |= (uint16_t)(LoRaPara.RegBuff.RegRssiValue)<<8;
|
||||
rssi |= LoRaPara.RegBuff.RegPktRssiValue;
|
||||
return rssi;
|
||||
}
|
||||
|
||||
uint8_t SX1276LoRaReadRssiPkt(void)
|
||||
{
|
||||
uint8_t RssiPkt;
|
||||
|
||||
SX1276Read(REG_LR_PKTRSSIVALUE, &LoRaPara.RegBuff.RegPktRssiValue);
|
||||
RssiPkt = LoRaPara.RegBuff.RegPktRssiValue;
|
||||
return RssiPkt;
|
||||
}
|
||||
|
||||
//LORAPT_POWER,
|
||||
void SX1276LoRaWritePwr(int8_t Pwr)
|
||||
{
|
||||
SX1276LoRaSetRfPower(Pwr);
|
||||
}
|
||||
|
||||
//LORAPT_SET_RX,
|
||||
void SX1276LoRaWriteRx(void)
|
||||
{
|
||||
Sx1276LoRaEnterRx();
|
||||
}
|
||||
|
||||
//LORAPT_SET_SLEEP,true-Sleep, false-Wakeup
|
||||
void SX1276LoRaWriteSleep(bool Sleep)
|
||||
{
|
||||
if(Sleep){
|
||||
Sx1276LoRaSleep();
|
||||
}
|
||||
else {
|
||||
Sx1276LoRaWakeup();
|
||||
}
|
||||
}
|
||||
|
||||
Sx1276StateType_t SX1276LoRaReadStatus(void)
|
||||
{
|
||||
return LoRaPara.State;
|
||||
}
|
||||
|
||||
///////////////RSSI Calc///////////////
|
||||
void SX1276LoCalcRssiSnr(int16_t *pswRssi, int8_t *psbSnr)
|
||||
{
|
||||
int8_t sbSnr= LoRaPara.RegBuff.RegPktSnrValue & 0x80 ? (-1)*((int8_t)(((~LoRaPara.RegBuff.RegPktSnrValue+ 1)& 0xFF)/4)): (~LoRaPara.RegBuff.RegPktSnrValue& 0xFF)/4;
|
||||
if (*psbSnr > 0) {
|
||||
*pswRssi= RSSI_OFFSET_LF+ LoRaPara.RegBuff.RegPktRssiValue;
|
||||
}
|
||||
else {
|
||||
*pswRssi= NOISE_ABSOLUTE_ZERO + 10 + SIGNAL_BW_LOG_125KHZ + NOISE_FIGURE_LF + sbSnr;
|
||||
}
|
||||
*psbSnr= sbSnr;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,789 @@
|
||||
#ifndef __SX127X_H
|
||||
#define __SX127X_H
|
||||
|
||||
#include "bsp.h"
|
||||
|
||||
//Constant values need to compute the RSSI value
|
||||
#define RSSI_OFFSET_LF -155
|
||||
#define RSSI_OFFSET_HF -150
|
||||
#define NOISE_ABSOLUTE_ZERO -174
|
||||
#define NOISE_FIGURE_LF 4
|
||||
#define NOISE_FIGURE_HF 6
|
||||
#define SIGNAL_BW_LOG_125KHZ 5
|
||||
|
||||
//SX1276 definitions
|
||||
#define XTAL_FREQ 32000000
|
||||
#define FREQ_STEP 61.03515625
|
||||
|
||||
//SX1276 Internal registers Address
|
||||
#define REG_LR_FIFO 0x00
|
||||
// Common settings
|
||||
#define REG_LR_OPMODE 0x01
|
||||
#define REG_LR_BANDSETTING 0x04
|
||||
#define REG_LR_FRFMSB 0x06
|
||||
#define REG_LR_FRFMID 0x07
|
||||
#define REG_LR_FRFLSB 0x08
|
||||
// Tx settings
|
||||
#define REG_LR_PACONFIG 0x09
|
||||
#define REG_LR_PARAMP 0x0A
|
||||
#define REG_LR_OCP 0x0B
|
||||
// Rx settings
|
||||
#define REG_LR_LNA 0x0C
|
||||
// LoRa registers
|
||||
#define REG_LR_FIFOADDRPTR 0x0D
|
||||
#define REG_LR_FIFOTXBASEADDR 0x0E
|
||||
#define REG_LR_FIFORXBASEADDR 0x0F
|
||||
#define REG_LR_FIFORXCURRENTADDR 0x10
|
||||
#define REG_LR_IRQFLAGSMASK 0x11
|
||||
#define REG_LR_IRQFLAGS 0x12
|
||||
#define REG_LR_NBRXBYTES 0x13
|
||||
#define REG_LR_RXHEADERCNTVALUEMSB 0x14
|
||||
#define REG_LR_RXHEADERCNTVALUELSB 0x15
|
||||
#define REG_LR_RXPACKETCNTVALUEMSB 0x16
|
||||
#define REG_LR_RXPACKETCNTVALUELSB 0x17
|
||||
#define REG_LR_MODEMSTAT 0x18
|
||||
#define REG_LR_PKTSNRVALUE 0x19
|
||||
#define REG_LR_PKTRSSIVALUE 0x1A
|
||||
#define REG_LR_RSSIVALUE 0x1B
|
||||
#define REG_LR_HOPCHANNEL 0x1C
|
||||
#define REG_LR_MODEMCONFIG1 0x1D
|
||||
#define REG_LR_MODEMCONFIG2 0x1E
|
||||
#define REG_LR_SYMBTIMEOUTLSB 0x1F
|
||||
#define REG_LR_PREAMBLEMSB 0x20
|
||||
#define REG_LR_PREAMBLELSB 0x21
|
||||
#define REG_LR_PAYLOADLENGTH 0x22
|
||||
#define REG_LR_PAYLOADMAXLENGTH 0x23
|
||||
#define REG_LR_HOPPERIOD 0x24
|
||||
#define REG_LR_FIFORXBYTEADDR 0x25
|
||||
#define REG_LR_MODEMCONFIG3 0x26
|
||||
// end of documented register in datasheet
|
||||
// I/O settings
|
||||
#define REG_LR_DIOMAPPING1 0x40
|
||||
#define REG_LR_DIOMAPPING2 0x41
|
||||
// Version
|
||||
#define REG_LR_VERSION 0x42
|
||||
// Additional settings
|
||||
#define REG_LR_PLLHOP 0x44
|
||||
#define REG_LR_TCXO 0x4B
|
||||
#define REG_LR_PADAC 0x4D
|
||||
#define REG_LR_FORMERTEMP 0x5B
|
||||
#define REG_LR_BITRATEFRAC 0x5D
|
||||
#define REG_LR_AGCREF 0x61
|
||||
#define REG_LR_AGCTHRESH1 0x62
|
||||
#define REG_LR_AGCTHRESH2 0x63
|
||||
#define REG_LR_AGCTHRESH3 0x64
|
||||
|
||||
//RegOpMode
|
||||
typedef enum{
|
||||
RFLR_OPMODE_LONGRANGEMODE_MASK =0x7F,
|
||||
RFLR_OPMODE_LONGRANGEMODE_OFF =0x00, // Default
|
||||
RFLR_OPMODE_LONGRANGEMODE_ON =0x80,
|
||||
RFLR_OPMODE_ACCESSSHAREDREG_MASK =0xBF,
|
||||
RFLR_OPMODE_ACCESSSHAREDREG_ENABLE =0x40,
|
||||
RFLR_OPMODE_ACCESSSHAREDREG_DISABLE =0x00, // Default
|
||||
RFLR_OPMODE_FREQMODE_ACCESS_MASK =0xF7,
|
||||
RFLR_OPMODE_FREQMODE_ACCESS_LF =0x08, // Default
|
||||
RFLR_OPMODE_FREQMODE_ACCESS_HF =0x00,
|
||||
RFLR_OPMODE_MASK =0xF8,
|
||||
RFLR_OPMODE_SLEEP =0x00,
|
||||
RFLR_OPMODE_STANDBY =0x01, // Default
|
||||
RFLR_OPMODE_SYNTHESIZER_TX =0x02,
|
||||
RFLR_OPMODE_TRANSMITTER =0x03,
|
||||
RFLR_OPMODE_SYNTHESIZER_RX =0x04,
|
||||
RFLR_OPMODE_RECEIVER =0x05,
|
||||
// LoRa specific modes
|
||||
RFLR_OPMODE_RECEIVER_SINGLE =0x06,
|
||||
RFLR_OPMODE_CAD =0x07
|
||||
}Sx1276OpModeType;
|
||||
|
||||
//RegBandSetting
|
||||
#define RFLR_BANDSETTING_MASK 0x3F
|
||||
#define RFLR_BANDSETTING_AUTO 0x00 // Default
|
||||
#define RFLR_BANDSETTING_DIV_BY_1 0x40
|
||||
#define RFLR_BANDSETTING_DIV_BY_2 0x80
|
||||
#define RFLR_BANDSETTING_DIV_BY_6 0xC0
|
||||
|
||||
//RegFrf (MHz)
|
||||
#define RFLR_FRFMSB_434_MHZ 0x6C // Default
|
||||
#define RFLR_FRFMID_434_MHZ 0x80 // Default
|
||||
#define RFLR_FRFLSB_434_MHZ 0x00 // Default
|
||||
#define RFLR_FRFMSB_863_MHZ 0xD7
|
||||
#define RFLR_FRFMID_863_MHZ 0xC0
|
||||
#define RFLR_FRFLSB_863_MHZ 0x00
|
||||
#define RFLR_FRFMSB_864_MHZ 0xD8
|
||||
#define RFLR_FRFMID_864_MHZ 0x00
|
||||
#define RFLR_FRFLSB_864_MHZ 0x00
|
||||
#define RFLR_FRFMSB_865_MHZ 0xD8
|
||||
#define RFLR_FRFMID_865_MHZ 0x40
|
||||
#define RFLR_FRFLSB_865_MHZ 0x00
|
||||
#define RFLR_FRFMSB_866_MHZ 0xD8
|
||||
#define RFLR_FRFMID_866_MHZ 0x80
|
||||
#define RFLR_FRFLSB_866_MHZ 0x00
|
||||
#define RFLR_FRFMSB_867_MHZ 0xD8
|
||||
#define RFLR_FRFMID_867_MHZ 0xC0
|
||||
#define RFLR_FRFLSB_867_MHZ 0x00
|
||||
#define RFLR_FRFMSB_868_MHZ 0xD9
|
||||
#define RFLR_FRFMID_868_MHZ 0x00
|
||||
#define RFLR_FRFLSB_868_MHZ 0x00
|
||||
#define RFLR_FRFMSB_869_MHZ 0xD9
|
||||
#define RFLR_FRFMID_869_MHZ 0x40
|
||||
#define RFLR_FRFLSB_869_MHZ 0x00
|
||||
#define RFLR_FRFMSB_870_MHZ 0xD9
|
||||
#define RFLR_FRFMID_870_MHZ 0x80
|
||||
#define RFLR_FRFLSB_870_MHZ 0x00
|
||||
#define RFLR_FRFMSB_902_MHZ 0xE1
|
||||
#define RFLR_FRFMID_902_MHZ 0x80
|
||||
#define RFLR_FRFLSB_902_MHZ 0x00
|
||||
#define RFLR_FRFMSB_903_MHZ 0xE1
|
||||
#define RFLR_FRFMID_903_MHZ 0xC0
|
||||
#define RFLR_FRFLSB_903_MHZ 0x00
|
||||
#define RFLR_FRFMSB_904_MHZ 0xE2
|
||||
#define RFLR_FRFMID_904_MHZ 0x00
|
||||
#define RFLR_FRFLSB_904_MHZ 0x00
|
||||
#define RFLR_FRFMSB_905_MHZ 0xE2
|
||||
#define RFLR_FRFMID_905_MHZ 0x40
|
||||
#define RFLR_FRFLSB_905_MHZ 0x00
|
||||
#define RFLR_FRFMSB_906_MHZ 0xE2
|
||||
#define RFLR_FRFMID_906_MHZ 0x80
|
||||
#define RFLR_FRFLSB_906_MHZ 0x00
|
||||
#define RFLR_FRFMSB_907_MHZ 0xE2
|
||||
#define RFLR_FRFMID_907_MHZ 0xC0
|
||||
#define RFLR_FRFLSB_907_MHZ 0x00
|
||||
#define RFLR_FRFMSB_908_MHZ 0xE3
|
||||
#define RFLR_FRFMID_908_MHZ 0x00
|
||||
#define RFLR_FRFLSB_908_MHZ 0x00
|
||||
#define RFLR_FRFMSB_909_MHZ 0xE3
|
||||
#define RFLR_FRFMID_909_MHZ 0x40
|
||||
#define RFLR_FRFLSB_909_MHZ 0x00
|
||||
#define RFLR_FRFMSB_910_MHZ 0xE3
|
||||
#define RFLR_FRFMID_910_MHZ 0x80
|
||||
#define RFLR_FRFLSB_910_MHZ 0x00
|
||||
#define RFLR_FRFMSB_911_MHZ 0xE3
|
||||
#define RFLR_FRFMID_911_MHZ 0xC0
|
||||
#define RFLR_FRFLSB_911_MHZ 0x00
|
||||
#define RFLR_FRFMSB_912_MHZ 0xE4
|
||||
#define RFLR_FRFMID_912_MHZ 0x00
|
||||
#define RFLR_FRFLSB_912_MHZ 0x00
|
||||
#define RFLR_FRFMSB_913_MHZ 0xE4
|
||||
#define RFLR_FRFMID_913_MHZ 0x40
|
||||
#define RFLR_FRFLSB_913_MHZ 0x00
|
||||
#define RFLR_FRFMSB_914_MHZ 0xE4
|
||||
#define RFLR_FRFMID_914_MHZ 0x80
|
||||
#define RFLR_FRFLSB_914_MHZ 0x00
|
||||
#define RFLR_FRFMSB_915_MHZ 0xE4 // Default
|
||||
#define RFLR_FRFMID_915_MHZ 0xC0 // Default
|
||||
#define RFLR_FRFLSB_915_MHZ 0x00 // Default
|
||||
#define RFLR_FRFMSB_916_MHZ 0xE5
|
||||
#define RFLR_FRFMID_916_MHZ 0x00
|
||||
#define RFLR_FRFLSB_916_MHZ 0x00
|
||||
#define RFLR_FRFMSB_917_MHZ 0xE5
|
||||
#define RFLR_FRFMID_917_MHZ 0x40
|
||||
#define RFLR_FRFLSB_917_MHZ 0x00
|
||||
#define RFLR_FRFMSB_918_MHZ 0xE5
|
||||
#define RFLR_FRFMID_918_MHZ 0x80
|
||||
#define RFLR_FRFLSB_918_MHZ 0x00
|
||||
#define RFLR_FRFMSB_919_MHZ 0xE5
|
||||
#define RFLR_FRFMID_919_MHZ 0xC0
|
||||
#define RFLR_FRFLSB_919_MHZ 0x00
|
||||
#define RFLR_FRFMSB_920_MHZ 0xE6
|
||||
#define RFLR_FRFMID_920_MHZ 0x00
|
||||
#define RFLR_FRFLSB_920_MHZ 0x00
|
||||
#define RFLR_FRFMSB_921_MHZ 0xE6
|
||||
#define RFLR_FRFMID_921_MHZ 0x40
|
||||
#define RFLR_FRFLSB_921_MHZ 0x00
|
||||
#define RFLR_FRFMSB_922_MHZ 0xE6
|
||||
#define RFLR_FRFMID_922_MHZ 0x80
|
||||
#define RFLR_FRFLSB_922_MHZ 0x00
|
||||
#define RFLR_FRFMSB_923_MHZ 0xE6
|
||||
#define RFLR_FRFMID_923_MHZ 0xC0
|
||||
#define RFLR_FRFLSB_923_MHZ 0x00
|
||||
#define RFLR_FRFMSB_924_MHZ 0xE7
|
||||
#define RFLR_FRFMID_924_MHZ 0x00
|
||||
#define RFLR_FRFLSB_924_MHZ 0x00
|
||||
#define RFLR_FRFMSB_925_MHZ 0xE7
|
||||
#define RFLR_FRFMID_925_MHZ 0x40
|
||||
#define RFLR_FRFLSB_925_MHZ 0x00
|
||||
#define RFLR_FRFMSB_926_MHZ 0xE7
|
||||
#define RFLR_FRFMID_926_MHZ 0x80
|
||||
#define RFLR_FRFLSB_926_MHZ 0x00
|
||||
#define RFLR_FRFMSB_927_MHZ 0xE7
|
||||
#define RFLR_FRFMID_927_MHZ 0xC0
|
||||
#define RFLR_FRFLSB_927_MHZ 0x00
|
||||
#define RFLR_FRFMSB_928_MHZ 0xE8
|
||||
#define RFLR_FRFMID_928_MHZ 0x00
|
||||
#define RFLR_FRFLSB_928_MHZ 0x00
|
||||
|
||||
//RegPaConfig
|
||||
#define RFLR_PACONFIG_PASELECT_MASK 0x7F
|
||||
#define RFLR_PACONFIG_PASELECT_PABOOST 0x80
|
||||
#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default
|
||||
#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F
|
||||
#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0
|
||||
|
||||
//RegPaRamp
|
||||
#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF
|
||||
#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10
|
||||
#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default
|
||||
#define RFLR_PARAMP_MASK 0xF0
|
||||
#define RFLR_PARAMP_3400_US 0x00
|
||||
#define RFLR_PARAMP_2000_US 0x01
|
||||
#define RFLR_PARAMP_1000_US 0x02
|
||||
#define RFLR_PARAMP_0500_US 0x03
|
||||
#define RFLR_PARAMP_0250_US 0x04
|
||||
#define RFLR_PARAMP_0125_US 0x05
|
||||
#define RFLR_PARAMP_0100_US 0x06
|
||||
#define RFLR_PARAMP_0062_US 0x07
|
||||
#define RFLR_PARAMP_0050_US 0x08
|
||||
#define RFLR_PARAMP_0040_US 0x09 // Default
|
||||
#define RFLR_PARAMP_0031_US 0x0A
|
||||
#define RFLR_PARAMP_0025_US 0x0B
|
||||
#define RFLR_PARAMP_0020_US 0x0C
|
||||
#define RFLR_PARAMP_0015_US 0x0D
|
||||
#define RFLR_PARAMP_0012_US 0x0E
|
||||
#define RFLR_PARAMP_0010_US 0x0F
|
||||
|
||||
//RegOcp
|
||||
#define RFLR_OCP_MASK 0xDF
|
||||
#define RFLR_OCP_ON 0x20 // Default
|
||||
#define RFLR_OCP_OFF 0x00
|
||||
#define RFLR_OCP_TRIM_MASK 0xE0
|
||||
#define RFLR_OCP_TRIM_045_MA 0x00
|
||||
#define RFLR_OCP_TRIM_050_MA 0x01
|
||||
#define RFLR_OCP_TRIM_055_MA 0x02
|
||||
#define RFLR_OCP_TRIM_060_MA 0x03
|
||||
#define RFLR_OCP_TRIM_065_MA 0x04
|
||||
#define RFLR_OCP_TRIM_070_MA 0x05
|
||||
#define RFLR_OCP_TRIM_075_MA 0x06
|
||||
#define RFLR_OCP_TRIM_080_MA 0x07
|
||||
#define RFLR_OCP_TRIM_085_MA 0x08
|
||||
#define RFLR_OCP_TRIM_090_MA 0x09
|
||||
#define RFLR_OCP_TRIM_095_MA 0x0A
|
||||
#define RFLR_OCP_TRIM_100_MA 0x0B // Default
|
||||
#define RFLR_OCP_TRIM_105_MA 0x0C
|
||||
#define RFLR_OCP_TRIM_110_MA 0x0D
|
||||
#define RFLR_OCP_TRIM_115_MA 0x0E
|
||||
#define RFLR_OCP_TRIM_120_MA 0x0F
|
||||
#define RFLR_OCP_TRIM_130_MA 0x10
|
||||
#define RFLR_OCP_TRIM_140_MA 0x11
|
||||
#define RFLR_OCP_TRIM_150_MA 0x12
|
||||
#define RFLR_OCP_TRIM_160_MA 0x13
|
||||
#define RFLR_OCP_TRIM_170_MA 0x14
|
||||
#define RFLR_OCP_TRIM_180_MA 0x15
|
||||
#define RFLR_OCP_TRIM_190_MA 0x16
|
||||
#define RFLR_OCP_TRIM_200_MA 0x17
|
||||
#define RFLR_OCP_TRIM_210_MA 0x18
|
||||
#define RFLR_OCP_TRIM_220_MA 0x19
|
||||
#define RFLR_OCP_TRIM_230_MA 0x1A
|
||||
#define RFLR_OCP_TRIM_240_MA 0x1B
|
||||
|
||||
//RegLna
|
||||
#define RFLR_LNA_GAIN_MASK 0x1F
|
||||
#define RFLR_LNA_GAIN_G1 0x20 // Default
|
||||
#define RFLR_LNA_GAIN_G2 0x40
|
||||
#define RFLR_LNA_GAIN_G3 0x60
|
||||
#define RFLR_LNA_GAIN_G4 0x80
|
||||
#define RFLR_LNA_GAIN_G5 0xA0
|
||||
#define RFLR_LNA_GAIN_G6 0xC0
|
||||
#define RFLR_LNA_BOOST_LF_MASK 0xE7
|
||||
#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default
|
||||
#define RFLR_LNA_BOOST_LF_GAIN 0x08
|
||||
#define RFLR_LNA_BOOST_LF_IP3 0x10
|
||||
#define RFLR_LNA_BOOST_LF_BOOST 0x18
|
||||
#define RFLR_LNA_RXBANDFORCE_MASK 0xFB
|
||||
#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04
|
||||
#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default
|
||||
#define RFLR_LNA_BOOST_HF_MASK 0xFC
|
||||
#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default
|
||||
#define RFLR_LNA_BOOST_HF_ON 0x03
|
||||
|
||||
//RegFifoAddrPtr
|
||||
#define RFLR_FIFOADDRPTR 0x00 // Default
|
||||
|
||||
//RegFifoTxBaseAddr
|
||||
#define RFLR_FIFOTXBASEADDR 0x80 // Default
|
||||
|
||||
//RegFifoTxBaseAddr
|
||||
#define RFLR_FIFORXBASEADDR 0x00 // Default
|
||||
|
||||
//RegFifoRxCurrentAddr (Read Only)
|
||||
|
||||
//RegIrqFlagsMask
|
||||
#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80
|
||||
#define RFLR_IRQFLAGS_RXDONE_MASK 0x40
|
||||
#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20
|
||||
#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10
|
||||
#define RFLR_IRQFLAGS_TXDONE_MASK 0x08
|
||||
#define RFLR_IRQFLAGS_CADDONE_MASK 0x04
|
||||
#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02
|
||||
#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01
|
||||
|
||||
//RegIrqFlags
|
||||
#define RFLR_IRQFLAGS_RXTIMEOUT 0x80
|
||||
#define RFLR_IRQFLAGS_RXDONE 0x40
|
||||
#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20
|
||||
#define RFLR_IRQFLAGS_VALIDHEADER 0x10
|
||||
#define RFLR_IRQFLAGS_TXDONE 0x08
|
||||
#define RFLR_IRQFLAGS_CADDONE 0x04
|
||||
#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02
|
||||
#define RFLR_IRQFLAGS_CADDETECTED 0x01
|
||||
|
||||
//RegModemStat (Read Only)
|
||||
#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F
|
||||
#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0
|
||||
|
||||
//RegModemConfig1
|
||||
#define RFLR_MODEMCONFIG1_BW_MASK 0x0F
|
||||
#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00
|
||||
#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10
|
||||
#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20
|
||||
#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30
|
||||
#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40
|
||||
#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50
|
||||
#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60
|
||||
#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default
|
||||
#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80
|
||||
#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90
|
||||
#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1
|
||||
#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02
|
||||
#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default
|
||||
#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06
|
||||
#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08
|
||||
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE
|
||||
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x00
|
||||
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x01 // Default
|
||||
|
||||
//RegModemConfig2
|
||||
#define RFLR_MODEMCONFIG2_SF_MASK 0x0F
|
||||
#define RFLR_MODEMCONFIG2_SF_6 0x60
|
||||
#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default
|
||||
#define RFLR_MODEMCONFIG2_SF_8 0x80
|
||||
#define RFLR_MODEMCONFIG2_SF_9 0x90
|
||||
#define RFLR_MODEMCONFIG2_SF_10 0xA0
|
||||
#define RFLR_MODEMCONFIG2_SF_11 0xB0
|
||||
#define RFLR_MODEMCONFIG2_SF_12 0xC0
|
||||
|
||||
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7
|
||||
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08
|
||||
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00
|
||||
|
||||
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB
|
||||
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04
|
||||
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default
|
||||
|
||||
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC
|
||||
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default
|
||||
|
||||
|
||||
//RegHopChannel (Read Only)
|
||||
#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F
|
||||
#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80
|
||||
#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default
|
||||
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF
|
||||
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40
|
||||
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default
|
||||
#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F
|
||||
|
||||
|
||||
//RegSymbTimeoutLsb
|
||||
#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default
|
||||
|
||||
//RegPreambleLengthMsb
|
||||
#define RFLR_PREAMBLELENGTHMSB 0x00 // Default
|
||||
|
||||
//RegPreambleLengthLsb
|
||||
#define RFLR_PREAMBLELENGTHLSB 0x08 // Default
|
||||
|
||||
//RegPayloadLength
|
||||
#define RFLR_PAYLOADLENGTH 0x0E // Default
|
||||
|
||||
//RegPayloadMaxLength
|
||||
#define RFLR_PAYLOADMAXLENGTH 0xFF // Default
|
||||
|
||||
//RegHopPeriod
|
||||
#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default
|
||||
|
||||
|
||||
//RegDioMapping1
|
||||
//DIO0
|
||||
#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F
|
||||
#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default
|
||||
#define RFLR_DIOMAPPING1_DIO0_01 0x40
|
||||
#define RFLR_DIOMAPPING1_DIO0_10 0x80
|
||||
#define RFLR_DIOMAPPING1_DIO0_11 0xC0
|
||||
//DIO1
|
||||
#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF
|
||||
#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default
|
||||
#define RFLR_DIOMAPPING1_DIO1_01 0x10
|
||||
#define RFLR_DIOMAPPING1_DIO1_10 0x20
|
||||
#define RFLR_DIOMAPPING1_DIO1_11 0x30
|
||||
//DIO2
|
||||
#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3
|
||||
#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default
|
||||
#define RFLR_DIOMAPPING1_DIO2_01 0x04
|
||||
#define RFLR_DIOMAPPING1_DIO2_10 0x08
|
||||
#define RFLR_DIOMAPPING1_DIO2_11 0x0C
|
||||
//DIO3
|
||||
#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC
|
||||
#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default
|
||||
#define RFLR_DIOMAPPING1_DIO3_01 0x01
|
||||
#define RFLR_DIOMAPPING1_DIO3_10 0x02
|
||||
#define RFLR_DIOMAPPING1_DIO3_11 0x03
|
||||
|
||||
//RegDioMapping2
|
||||
//DIO4
|
||||
#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F
|
||||
#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default
|
||||
#define RFLR_DIOMAPPING2_DIO4_01 0x40
|
||||
#define RFLR_DIOMAPPING2_DIO4_10 0x80
|
||||
#define RFLR_DIOMAPPING2_DIO4_11 0xC0
|
||||
//DIO5
|
||||
#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF
|
||||
#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default
|
||||
#define RFLR_DIOMAPPING2_DIO5_01 0x10
|
||||
#define RFLR_DIOMAPPING2_DIO5_10 0x20
|
||||
#define RFLR_DIOMAPPING2_DIO5_11 0x30
|
||||
//MAP
|
||||
#define RFLR_DIOMAPPING2_MAP_MASK 0xFE
|
||||
#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
|
||||
#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default
|
||||
|
||||
// RegPllHop
|
||||
#define RFLR_PLLHOP_FASTHOP_MASK 0x7F
|
||||
#define RFLR_PLLHOP_FASTHOP_ON 0x80
|
||||
#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default
|
||||
|
||||
//RegTcxo
|
||||
#define RFLR_TCXO_TCXOINPUT_MASK 0xEF
|
||||
#define RFLR_TCXO_TCXOINPUT_ON 0x10
|
||||
#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default
|
||||
|
||||
//RegPaDac
|
||||
#define RFLR_PADAC_20DBM_MASK 0xF8
|
||||
#define RFLR_PADAC_20DBM_ON 0x07
|
||||
#define RFLR_PADAC_20DBM_OFF 0x04 // Default
|
||||
|
||||
//RegPll
|
||||
#define RFLR_PLL_BANDWIDTH_MASK 0x3F
|
||||
#define RFLR_PLL_BANDWIDTH_75 0x00
|
||||
#define RFLR_PLL_BANDWIDTH_150 0x40
|
||||
#define RFLR_PLL_BANDWIDTH_225 0x80
|
||||
#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default
|
||||
|
||||
//RegPllLowPn
|
||||
#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F
|
||||
#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00
|
||||
#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40
|
||||
#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80
|
||||
#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default
|
||||
|
||||
//RegModemConfig3
|
||||
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7
|
||||
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08
|
||||
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default
|
||||
#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB
|
||||
#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default
|
||||
#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00
|
||||
|
||||
//REGISTER
|
||||
typedef struct _Sx1276RegType{
|
||||
uint8_t RegFifo; // 0x00
|
||||
// Common settings
|
||||
uint8_t RegOpMode; // 0x01
|
||||
uint8_t RegRes02; // 0x02
|
||||
uint8_t RegRes03; // 0x03
|
||||
uint8_t RegBandSetting; // 0x04
|
||||
uint8_t RegRes05; // 0x05
|
||||
uint8_t RegFrfMsb; // 0x06
|
||||
uint8_t RegFrfMid; // 0x07
|
||||
uint8_t RegFrfLsb; // 0x08
|
||||
// Tx settings
|
||||
uint8_t RegPaConfig; // 0x09
|
||||
uint8_t RegPaRamp; // 0x0A
|
||||
uint8_t RegOcp; // 0x0B
|
||||
// Rx settings
|
||||
uint8_t RegLna; // 0x0C
|
||||
// LoRa registers
|
||||
uint8_t RegFifoAddrPtr; // 0x0D
|
||||
uint8_t RegFifoTxBaseAddr; // 0x0E
|
||||
uint8_t RegFifoRxBaseAddr; // 0x0F
|
||||
uint8_t RegFifoRxCurrentAddr; // 0x10
|
||||
uint8_t RegIrqFlagsMask; // 0x11
|
||||
uint8_t RegIrqFlags; // 0x12
|
||||
uint8_t RegNbRxBytes; // 0x13
|
||||
uint8_t RegRxHeaderCntValueMsb; // 0x14
|
||||
uint8_t RegRxHeaderCntValueLsb; // 0x15
|
||||
uint8_t RegRxPacketCntValueMsb; // 0x16
|
||||
uint8_t RegRxPacketCntValueLsb; // 0x17
|
||||
uint8_t RegModemStat; // 0x18
|
||||
uint8_t RegPktSnrValue; // 0x19
|
||||
uint8_t RegPktRssiValue; // 0x1A
|
||||
uint8_t RegRssiValue; // 0x1B
|
||||
uint8_t RegHopChannel; // 0x1C
|
||||
uint8_t RegModemConfig1; // 0x1D
|
||||
uint8_t RegModemConfig2; // 0x1E
|
||||
uint8_t RegSymbTimeoutLsb; // 0x1F
|
||||
uint8_t RegPreambleMsb; // 0x20
|
||||
uint8_t RegPreambleLsb; // 0x21
|
||||
uint8_t RegPayloadLength; // 0x22
|
||||
uint8_t RegMaxPayloadLength; // 0x23
|
||||
uint8_t RegHopPeriod; // 0x24
|
||||
uint8_t RegFifoRxByteAddr; // 0x25
|
||||
uint8_t RegModemConfig3; // 0x26
|
||||
uint8_t RegTestReserved27[0x30 - 0x27]; // 0x27-0x30
|
||||
uint8_t RegTestReserved31; // 0x31
|
||||
uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x40
|
||||
// I/O settings
|
||||
uint8_t RegDioMapping1; // 0x40
|
||||
uint8_t RegDioMapping2; // 0x41
|
||||
// Version
|
||||
uint8_t RegVersion; // 0x42
|
||||
// Additional settings
|
||||
uint8_t RegAgcRef; // 0x43
|
||||
uint8_t RegAgcThresh1; // 0x44
|
||||
uint8_t RegAgcThresh2; // 0x45
|
||||
uint8_t RegAgcThresh3; // 0x46
|
||||
// Test
|
||||
uint8_t RegTestReserved47[0x4B - 0x47]; // 0x47-0x4A
|
||||
// Additional settings
|
||||
uint8_t RegPllHop; // 0x4B
|
||||
uint8_t RegTestReserved4C; // 0x4C
|
||||
uint8_t RegPaDac; // 0x4D
|
||||
// Test
|
||||
//uint8_t RegTestReserved4E[0x58-0x4E]; // 0x4E-0x57
|
||||
// Additional settings
|
||||
//uint8_t RegTcxo; // 0x58
|
||||
// Test
|
||||
//uint8_t RegTestReserved59; // 0x59
|
||||
// Test
|
||||
//uint8_t RegTestReserved5B; // 0x5B
|
||||
// Additional settings
|
||||
//uint8_t RegPll; // 0x5C
|
||||
// Test
|
||||
//uint8_t RegTestReserved5D; // 0x5D
|
||||
// Additional settings
|
||||
//uint8_t RegPllLowPn; // 0x5E
|
||||
// Test
|
||||
//uint8_t RegTestReserved5F[0x6C - 0x5F]; // 0x5F-0x6B
|
||||
// Additional settings
|
||||
//uint8_t RegFormerTemp; // 0x6C
|
||||
// Test
|
||||
//uint8_t RegTestReserved6D[0x71 - 0x6D]; // 0x6D-0x70
|
||||
}Sx1276RegType;
|
||||
|
||||
#define SIZE_OF_REGISTERS (sizeof(Sx1276RegType))
|
||||
|
||||
//RF state machine
|
||||
typedef enum{
|
||||
RFLR_STATE_IDLE,
|
||||
RFLR_STATE_RX_RUNNING,
|
||||
RFLR_STATE_TX_RUNNING,
|
||||
}LRStateType;
|
||||
|
||||
typedef enum{
|
||||
RADIO_RESET_OFF,
|
||||
RADIO_RESET_ON,
|
||||
}tRadioResetState;
|
||||
|
||||
typedef enum{
|
||||
RF_IDLE,
|
||||
RF_BUSY,
|
||||
RF_RX_DONE,
|
||||
RF_RX_TIMEOUT,
|
||||
RF_TX_DONE,
|
||||
RF_TX_TIMEOUT,
|
||||
RF_LEN_ERROR,
|
||||
RF_CHANNEL_EMPTY,
|
||||
RF_CHANNEL_ACTIVITY_DETECTED,
|
||||
}Sx1276RetType;
|
||||
|
||||
typedef enum{
|
||||
SX1276_BW_7K8= (0),
|
||||
SX1276_BW_10K4= (1<<4),
|
||||
SX1276_BW_15K6= (2<<4),
|
||||
SX1276_BW_20K8= (3<<4),
|
||||
SX1276_BW_31K2= (4<<4),
|
||||
SX1276_BW_41K6= (5<<4),
|
||||
SX1276_BW_62K5= (6<<4),
|
||||
SX1276_BW_125K= (7<<4),
|
||||
SX1276_BW_250K= (8<<4),
|
||||
SX1276_BW_500K= (9<<4)
|
||||
}Sx1276BwType;
|
||||
|
||||
typedef enum{
|
||||
SX1276_SF_64= (6<<4),
|
||||
SX1276_SF_128= (7<<4),
|
||||
SX1276_SF_256= (8<<4),
|
||||
SX1276_SF_512= (9<<4),
|
||||
SX1276_SF_1024= (10<<4),
|
||||
SX1276_SF_2048= (11<<4),
|
||||
SX1276_SF_4096= (12<<4)
|
||||
}Sx1276SpreadFactorType;
|
||||
|
||||
typedef enum{
|
||||
SX1276_EC_4_5= (1<<1),
|
||||
SX1276_EC_4_6= (2<<1),
|
||||
SX1276_EC_4_7= (3<<1),
|
||||
SX1276_EC_4_8= (4<<1)
|
||||
}Sx1276ErrorCodingType;
|
||||
|
||||
typedef enum{
|
||||
SX1276_CRC_OFF= (0),
|
||||
SX1276_CRC_ON= (1<<2)
|
||||
}Sx1276CrcOnType;
|
||||
|
||||
typedef enum{
|
||||
SX1276_IH_OFF= (0),
|
||||
SX1276_IH_ON= (1)
|
||||
}Sx1276ImplicitHeaderOnType;
|
||||
|
||||
//可变速率
|
||||
typedef struct _AutoSfType{
|
||||
Sx1276SpreadFactorType Sf;
|
||||
uint8_t ucRssiMin, ucRssiMax;
|
||||
uint16_t wTimeout;
|
||||
}AutoSfType, *PAutoSf;
|
||||
|
||||
//Parameter
|
||||
typedef enum{
|
||||
LORAPT_STATUS,
|
||||
LORAPT_CHANNEL,
|
||||
LORAPT_FREQ,
|
||||
LORAPT_BW,
|
||||
LORAPT_SF,
|
||||
LORAPT_EC,
|
||||
LORAPT_RSSI,
|
||||
LORAPT_POWER,
|
||||
LORAPT_SET_RX,
|
||||
LORAPT_SET_SLEEP,
|
||||
LORAPT_MAX
|
||||
}Sx1276LoraParaType;
|
||||
|
||||
#define SX1276_CHANNEL_MAX 17
|
||||
|
||||
#define LORA_RESET_SET() SET_LORA_RST()
|
||||
#define LORA_RESET_CLR() CLR_LORA_RST()
|
||||
#define LORA_SPI_NSS_SET() SET_LORA_NSS()
|
||||
#define LORA_SPI_NSS_CLR() CLR_LORA_NSS()
|
||||
#define LORA_SPI_READ_WRITE(x) SpiSendReceive(x)
|
||||
#define LORA_GETDIO0() GET_LORA_DIO0()
|
||||
#define LORA_GETDIO1() GET_LORA_DIO1()
|
||||
|
||||
#define USE_RF_SW 0
|
||||
#define USE_LORA_LED 0
|
||||
#if USE_RF_SW == 1
|
||||
#define LORA_ANTTXEN() { \
|
||||
SET_LORA_TXEN_PIN();\
|
||||
CLR_LORA_RXEN_PIN();\
|
||||
}
|
||||
|
||||
#define LORA_ANTRXEN() { \
|
||||
SET_LORA_RXEN_PIN();\
|
||||
CLR_LORA_TXEN_PIN();\
|
||||
}
|
||||
|
||||
#define LORA_ANTCLOSE() { \
|
||||
CLR_LORA_RXEN_PIN();\
|
||||
CLR_LORA_TXEN_PIN();\
|
||||
}
|
||||
#else
|
||||
#define LORA_ANTTXEN()
|
||||
#define LORA_ANTRXEN()
|
||||
#define LORA_ANTCLOSE()
|
||||
#endif
|
||||
|
||||
#if USE_LORA_LED == 1
|
||||
#define LORA_TXLED_ON() SET_LED_PIN()
|
||||
#define LORA_TXLED_OFF() CLR_LED_PIN()
|
||||
#else
|
||||
#define LORA_TXLED_ON() SET_LORA_TX_LED()
|
||||
#define LORA_TXLED_OFF() CLR_LORA_TX_LED()
|
||||
#endif
|
||||
|
||||
#define LORA_BUFF_SIZE 255
|
||||
|
||||
typedef enum {
|
||||
RF_ANT_TRANSMITTER,
|
||||
RF_ANT_RECEIVER,
|
||||
RF_ANT_CLOSE,
|
||||
}Sx1276AntStatus_m;
|
||||
|
||||
typedef enum {
|
||||
SX1276_SLEEP,
|
||||
SX1276_IDLE,
|
||||
SX1276_RX,
|
||||
SX1276_TX,
|
||||
SX1276_BUSY,
|
||||
SX1276_ERROR,
|
||||
SX1276_MAX
|
||||
}Sx1276StateType_t;
|
||||
|
||||
typedef struct {
|
||||
uint8_t ucChannel;
|
||||
uint32_t dwFreqHz;
|
||||
int8_t ucPower;
|
||||
Sx1276BwType SignalBw;
|
||||
Sx1276SpreadFactorType SpreadFactor;
|
||||
Sx1276ErrorCodingType ErrorCoding;
|
||||
uint8_t RegPreamble;
|
||||
uint8_t ucOpModePrev;
|
||||
Sx1276AntStatus_m bAntSwPrev;
|
||||
Sx1276RegType RegBuff;
|
||||
Sx1276StateType_t State;
|
||||
uint8_t ucRxPacketSize;
|
||||
uint8_t ucTxPacketSize;
|
||||
uint8_t RxTxBuff[LORA_BUFF_SIZE];
|
||||
void (*RxCallBack)(uint8_t *rBuff, uint8_t rlen);
|
||||
}Sx1276Type_t, *pSx1276Type;
|
||||
|
||||
//ISM Freq In China
|
||||
//Up Link:
|
||||
//CH0-5: 470.3-471.3MHz
|
||||
//CH39-44:478.1-479.1MHz
|
||||
//CH78-95:485.9-489.3MHz
|
||||
//Down Link:
|
||||
//CH0-47:500.3-509.7MHz
|
||||
|
||||
#define USE_915MHZ 0//=1使用915 =0使用433
|
||||
|
||||
#if (USE_915MHZ == 1)
|
||||
//中心频率，不定义则默认为449000000Hz
|
||||
#define FREQ_CENT 915000000ul
|
||||
//860MHz-1GHz使用PA功放，不定义则默认不使用
|
||||
//SX127x不定义，HOPERF模块需要定义
|
||||
#define USE_LORA_860_PA
|
||||
#endif
|
||||
|
||||
#if !defined FREQ_CENT
|
||||
#define FREQ_CENT (433100000ul+ 0)//125000
|
||||
//#define FREQ_DEV 250000ul
|
||||
#endif
|
||||
#if !defined FREQ_DEV
|
||||
//#define FREQ_CENT (449000000ul+ 0)//125000
|
||||
#define FREQ_DEV 250000ul
|
||||
#endif
|
||||
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
void Sx1276LoRaLoopHandler(void);
|
||||
void Sx1276LoRaInit(void (*RxCallBack)(uint8_t *rBuff, uint8_t rlen));
|
||||
void Sx1276LoRaSendBuffer(uint8_t* pucBuff, uint8_t ucLen);
|
||||
uint8_t SX1276LoRaReadChannel(void);
|
||||
bool SX1276LoRaWriteChannel(uint8_t Channel);
|
||||
uint32_t SX1276LoRaReadFreq(void);
|
||||
void SX1276LoRaWriteFreq(uint32_t Freq);
|
||||
void SX1276LoRaWriteBw(Sx1276BwType SignalBw);
|
||||
uint32_t SX1276LoRaReadBw(void);
|
||||
uint8_t SX1276LoRaReadSf(void);
|
||||
void SX1276LoRaWriteSf(Sx1276SpreadFactorType SpreadFactor);
|
||||
void SX1276LoRaWriteEc(Sx1276ErrorCodingType ErrorCoding);
|
||||
uint8_t SX1276LoRaReadEc(void);
|
||||
uint32_t SX1276LoRaParaReadRssi(void);
|
||||
uint8_t SX1276LoRaReadRssiPkt(void);
|
||||
void SX1276LoRaWritePwr(int8_t Pwr);
|
||||
void SX1276LoRaWriteRx(void);
|
||||
void SX1276LoRaWriteSleep(bool Sleep);
|
||||
Sx1276StateType_t SX1276LoRaReadStatus(void);
|
||||
void SX1276LoCalcRssiSnr(int16_t *pswRssi, int8_t *psbSnr);
|
||||
void Sx1276LoRaSleep(void);
|
||||
void Sx1276LoRaWakeup(void);
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
#ifndef __ADS1231__
|
||||
#define __ADS1231__
|
||||
|
||||
#include "bsp.h"
|
||||
|
||||
void ADS1231_Open(void);
|
||||
void ADS1231_SpeedSet(void);
|
||||
bool ADS1231_Read(uint32_t *r_data, uint8_t channel);
|
||||
void ADS1231_HighSpeedSet(void);
|
||||
void ADS1231_LowSpeedSet(void);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,7 @@
|
||||
#ifndef __EPT__
|
||||
#define __EPT__
|
||||
|
||||
void Encrypt_Code(unsigned char *data, unsigned char *EPT_data);
|
||||
void Decrypt_Code(unsigned char *EPT_data,unsigned char *DPT_data);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,232 @@
|
||||
#ifndef __BSP_H
|
||||
#define __BSP_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <time.h>
|
||||
#include "hc32_ddl.h"
|
||||
|
||||
|
||||
//#define WATCH_DOG 1
|
||||
|
||||
#define DEBUG 1
|
||||
#define RS485 1
|
||||
|
||||
#define DBGUART_IRQn Int006_IRQn
|
||||
#define DBGUART_EI_IRQn Int007_IRQn
|
||||
#define DBG_RXPIN_IRQn Int002_IRQn
|
||||
|
||||
#define RS485UART_IRQn Int008_IRQn
|
||||
#define RS485UART_EI_IRQn Int009_IRQn
|
||||
#define RS485_RXPIN_IRQn Int005_IRQn
|
||||
|
||||
|
||||
|
||||
#define RTC_IRQn Int001_IRQn
|
||||
|
||||
//DEBUG
|
||||
#define DBG_USART_CH (M4_USART3)
|
||||
//#define DBG_USART_RX_PORT (PortA)
|
||||
//#define DBG_USART_RX_PIN (Pin15)
|
||||
//#define DBG_USART_TX_PORT (PortA)
|
||||
//#define DBG_USART_TX_PIN (Pin12)
|
||||
#define DBG_USART_RX_PORT (PortB)
|
||||
#define DBG_USART_RX_PIN (Pin09)
|
||||
#define DBG_USART_TX_PORT (PortB)
|
||||
#define DBG_USART_TX_PIN (Pin08)
|
||||
#define DBG_USART_RX_FUNC (Func_Usart3_Rx)
|
||||
#define DBG_USART_TX_FUNC (Func_Usart3_Tx)
|
||||
#define DBG_USART_RI_NUM (INT_USART3_RI)
|
||||
#define DBG_USART_EI_NUM (INT_USART3_EI)
|
||||
#define DBG_USART_TI_NUM (INT_USART3_TI)
|
||||
#define DBG_USART_TCI_NUM (INT_USART3_TCI)
|
||||
#define DBG_FCG1_PERIPH (PWC_FCG1_PERIPH_USART3)
|
||||
#define DBG_RXPIN_EXIT_CH (ExtiCh13)
|
||||
#define DBG_RXPIN_EXIT_SRC (INT_PORT_EIRQ13)
|
||||
|
||||
|
||||
//#define DBG_USART_CH (M4_USART1)
|
||||
//#define DBG_USART_RX_PORT (PortC)
|
||||
//#define DBG_USART_RX_PIN (Pin13)
|
||||
//#define DBG_USART_TX_PORT (PortH)
|
||||
//#define DBG_USART_TX_PIN (Pin02)
|
||||
//#define DBG_USART_RX_FUNC (Func_Usart1_Rx)
|
||||
//#define DBG_USART_TX_FUNC (Func_Usart1_Tx)
|
||||
//#define DBG_USART_RI_NUM (INT_USART1_RI)
|
||||
//#define DBG_USART_EI_NUM (INT_USART1_EI)
|
||||
//#define DBG_USART_TI_NUM (INT_USART1_TI)
|
||||
//#define DBG_USART_TCI_NUM (INT_USART1_TCI)
|
||||
//#define DBG_FCG1_PERIPH (PWC_FCG1_PERIPH_USART1)
|
||||
//#define DBG_RXPIN_EXIT_CH (ExtiCh13)
|
||||
//#define DBG_RXPIN_EXIT_SRC (INT_PORT_EIRQ13)
|
||||
|
||||
|
||||
|
||||
//RS485
|
||||
#define RS485_USART_CH (M4_USART1)
|
||||
//#define RS485_USART_RX_PORT (PortB)
|
||||
//#define RS485_USART_RX_PIN (Pin08)
|
||||
//#define RS485_USART_TX_PORT (PortB)
|
||||
//#define RS485_USART_TX_PIN (Pin09)
|
||||
#define RS485_USART_RX_PORT (PortA)
|
||||
#define RS485_USART_RX_PIN (Pin15)
|
||||
#define RS485_USART_TX_PORT (PortA)
|
||||
#define RS485_USART_TX_PIN (Pin12)
|
||||
#define RS485_USART_RX_FUNC (Func_Usart1_Rx)
|
||||
#define RS485_USART_TX_FUNC (Func_Usart1_Tx)
|
||||
#define RS485_USART_RI_NUM (INT_USART1_RI)
|
||||
#define RS485_USART_EI_NUM (INT_USART1_EI)
|
||||
#define RS485_USART_TI_NUM (INT_USART1_TI)
|
||||
#define RS485_USART_TCI_NUM (INT_USART1_TCI)
|
||||
#define RS485_FCG1_PERIPH (PWC_FCG1_PERIPH_USART1)
|
||||
#define RS485_RXPIN_EXIT_CH (ExtiCh14)
|
||||
#define RS485_RXPIN_EXIT_SRC (INT_PORT_EIRQ14)
|
||||
|
||||
#define RS485_CTRL_PORT (PortC)
|
||||
#define RS485_CTRL_PIN (Pin13)
|
||||
#define RS485_TX() PORT_SetBits(RS485_CTRL_PORT, RS485_CTRL_PIN)
|
||||
#define RS485_RX() PORT_ResetBits(RS485_CTRL_PORT, RS485_CTRL_PIN)
|
||||
|
||||
|
||||
|
||||
/* LED */
|
||||
#define LED_Blue_PORT (PortH)
|
||||
#define LED_Blue_PIN (Pin02)
|
||||
|
||||
#define LED_Green_PORT (PortB)
|
||||
#define LED_Green_PIN (Pin01)
|
||||
|
||||
|
||||
/* SPI_SCK Port/Pin definition */
|
||||
#define SPI_SCK_PORT (PortA)
|
||||
#define SPI_SCK_PIN (Pin05)
|
||||
#define SPI_SCK_FUNC (Func_Spi1_Sck)
|
||||
|
||||
/* SPI_MOSI Port/Pin definition */
|
||||
#define SPI_MOSI_PORT (PortA)
|
||||
#define SPI_MOSI_PIN (Pin04)
|
||||
#define SPI_MOSI_FUNC (Func_Spi1_Mosi)
|
||||
|
||||
/* SPI_MISO Port/Pin definition */
|
||||
#define SPI_MISO_PORT (PortA)
|
||||
#define SPI_MISO_PIN (Pin02)
|
||||
#define SPI_MISO_FUNC (Func_Spi1_Miso)
|
||||
|
||||
/* SPI_MOSI Port/Pin definition */
|
||||
#define SPI_NSS_PORT (PortA)
|
||||
#define SPI_NSS_PIN (Pin03)
|
||||
#define SPI_NSS_FUNC (Func_Spi1_Nss0)
|
||||
#define SPI_NSS_SET() PORT_SetBits(SPI_NSS_PORT, SPI_NSS_PIN)
|
||||
#define SPI_NSS_CLR() PORT_ResetBits(SPI_NSS_PORT, SPI_NSS_PIN)
|
||||
|
||||
/* SPI unit and clock definition */
|
||||
#define SPI_UNIT (M4_SPI1)
|
||||
#define SPI_UNIT_CLOCK (PWC_FCG1_PERIPH_SPI1)
|
||||
|
||||
//SPI3
|
||||
/* SPI3_SCK Port/Pin definition */
|
||||
#define SPI3_SCK_PORT (PortB)
|
||||
#define SPI3_SCK_PIN (Pin14)
|
||||
#define SPI3_SCK_FUNC (Func_Spi3_Sck)
|
||||
|
||||
/* SPI3_MOSI Port/Pin definition */
|
||||
#define SPI3_MOSI_PORT (PortB)
|
||||
#define SPI3_MOSI_PIN (Pin10)
|
||||
#define SPI3_MOSI_FUNC (Func_Spi3_Mosi)
|
||||
|
||||
/* SPI3_MISO Port/Pin definition */
|
||||
#define SPI3_MISO_PORT (PortB)
|
||||
#define SPI3_MISO_PIN (Pin12)
|
||||
#define SPI3_MISO_FUNC (Func_Spi3_Miso)
|
||||
|
||||
/* SPI3_MOSI Port/Pin definition */
|
||||
#define SPI3_NSS_PORT (PortB)
|
||||
#define SPI3_NSS_PIN (Pin13)
|
||||
#define SPI3_NSS_FUNC (Func_Spi3_Nss0)
|
||||
#define SPI3_NSS_SET() PORT_SetBits(SPI3_NSS_PORT, SPI3_NSS_PIN)
|
||||
#define SPI3_NSS_CLR() PORT_ResetBits(SPI3_NSS_PORT, SPI3_NSS_PIN)
|
||||
|
||||
/* SPI3 unit and clock definition */
|
||||
#define SPI3_UNIT (M4_SPI3)
|
||||
#define SPI3_UNIT_CLOCK (PWC_FCG1_PERIPH_SPI3)
|
||||
|
||||
|
||||
/* SDIOC Port/Pin definition */
|
||||
#define SDIOC_CD_PORT (PortA)
|
||||
#define SDIOC_CD_PIN (Pin10)
|
||||
|
||||
#define SDIOC_CK_PORT (PortB)
|
||||
#define SDIOC_CK_PIN (Pin15)
|
||||
|
||||
#define SDIOC_CMD_PORT (PortA)
|
||||
#define SDIOC_CMD_PIN (Pin06)
|
||||
|
||||
#define SDIOC_D0_PORT (PortB)
|
||||
#define SDIOC_D0_PIN (Pin04)
|
||||
|
||||
#define SDIOC_D1_PORT (PortA)
|
||||
#define SDIOC_D1_PIN (Pin08)
|
||||
|
||||
#define SDIOC_D2_PORT (PortA)
|
||||
#define SDIOC_D2_PIN (Pin09)
|
||||
|
||||
#define SDIOC_D3_PORT (PortB)
|
||||
#define SDIOC_D3_PIN (Pin05)
|
||||
|
||||
/* SD sector && count */
|
||||
#define SD_SECTOR_START (0u)
|
||||
#define SD_SECTOR_COUNT (4u)
|
||||
|
||||
/* SDIOC unit */
|
||||
#define SDIOC_UNIT (M4_SDIOC1)
|
||||
|
||||
|
||||
|
||||
void BSP_Init(void);
|
||||
uint8_t DbgUartRec(void);
|
||||
void DebugUartSend(uint8_t *sData, uint16_t sLen);
|
||||
void Error_Handler(void);
|
||||
void FeedDog(void);
|
||||
void EnterStop(void);
|
||||
void Wakeup(void);
|
||||
|
||||
uint8_t RS485UartRec(void);
|
||||
void RS485UsartErrIrqCallback(void);
|
||||
void RS485_RxPinIntCallBack(void);
|
||||
void RS485UsartRxIrqCallback(void);
|
||||
void RS485UartSend(uint8_t *sData, uint16_t sLen);
|
||||
|
||||
void RS485_1msRoutine(void);
|
||||
|
||||
|
||||
void DbgUsartRxIrqCallback(void);
|
||||
void DBGUsartErrIrqCallback(void);
|
||||
void DBG_RxPinIntCallBack(void);
|
||||
void SysTick_IrqHandler(void);
|
||||
void RtcPeriod_IrqCallback(void);
|
||||
uint16_t SpiSendReceive(uint16_t sData);
|
||||
|
||||
uint8_t Spi3_RWByte(M4_SPI_TypeDef *SPIx, uint8_t u8Data);
|
||||
|
||||
en_result_t SdioInit(void);
|
||||
|
||||
bool SDCardErase(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr);
|
||||
bool SDCardReadBlocks(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr, uint8_t *ReadBuff);
|
||||
bool SDCardWriteBlocks(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr, uint8_t *WriteBuff);
|
||||
|
||||
void ReadAdcValue(uint16_t *ADValue);
|
||||
void ADC_Start(void) ;
|
||||
void ADC_Stop(void) ;
|
||||
uint16_t *GetADCBuffPoint(void);
|
||||
|
||||
uint8_t exf_getfree(uint8_t *drv,uint32_t *total,uint32_t *free);
|
||||
uint32_t mf_showfree(uint8_t *drv);
|
||||
|
||||
|
||||
void TimeGet(struct tm *cTime);
|
||||
int TimeTs(void);
|
||||
void TimeShow(uint32_t dwStamp);
|
||||
void TimeSync(time_t ts) ;
|
||||
#endif
|
||||
@@ -0,0 +1,160 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file ddl_config.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link DdlConfigGroup Ddl Config description @endlink
|
||||
**
|
||||
** - 2021-04-16 CDT First version for Device Driver Library config.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __DDL_CONFIG_H__
|
||||
#define __DDL_CONFIG_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup DdlConfigGroup Device Driver Library config(DDLCONFIG)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*! Chip module on-off define */
|
||||
#define DDL_ON (1u)
|
||||
#define DDL_OFF (0u)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief This is the list of modules to be used in the device driver library
|
||||
** Select the modules you need to use to DDL_ON.
|
||||
**
|
||||
** \note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
|
||||
** properly.
|
||||
**
|
||||
** \note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
|
||||
** Library.
|
||||
**
|
||||
** \note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
|
||||
******************************************************************************/
|
||||
#define DDL_ICG_ENABLE (DDL_ON)
|
||||
#define DDL_UTILITY_ENABLE (DDL_ON)
|
||||
#define DDL_PRINT_ENABLE (DDL_OFF)
|
||||
|
||||
#define DDL_ADC_ENABLE (DDL_ON)
|
||||
#define DDL_AES_ENABLE (DDL_OFF)
|
||||
#define DDL_CAN_ENABLE (DDL_OFF)
|
||||
#define DDL_CLK_ENABLE (DDL_ON)
|
||||
#define DDL_CMP_ENABLE (DDL_OFF)
|
||||
#define DDL_CRC_ENABLE (DDL_OFF)
|
||||
#define DDL_DCU_ENABLE (DDL_OFF)
|
||||
#define DDL_DMAC_ENABLE (DDL_ON)
|
||||
#define DDL_EFM_ENABLE (DDL_ON)
|
||||
#define DDL_EMB_ENABLE (DDL_OFF)
|
||||
#define DDL_EVENT_PORT_ENABLE (DDL_OFF)
|
||||
#define DDL_EXINT_NMI_SWI_ENABLE (DDL_ON)
|
||||
#define DDL_GPIO_ENABLE (DDL_ON)
|
||||
#define DDL_HASH_ENABLE (DDL_OFF)
|
||||
#define DDL_I2C_ENABLE (DDL_OFF)
|
||||
#define DDL_I2S_ENABLE (DDL_OFF)
|
||||
#define DDL_INTERRUPTS_ENABLE (DDL_ON)
|
||||
#define DDL_INTERRUPTS_SHARE_ENABLE (DDL_OFF)
|
||||
#define DDL_KEYSCAN_ENABLE (DDL_OFF)
|
||||
#define DDL_MPU_ENABLE (DDL_OFF)
|
||||
#define DDL_OTS_ENABLE (DDL_OFF)
|
||||
#define DDL_PWC_ENABLE (DDL_ON)
|
||||
#define DDL_QSPI_ENABLE (DDL_OFF)
|
||||
#define DDL_RMU_ENABLE (DDL_OFF)
|
||||
#define DDL_RTC_ENABLE (DDL_ON)
|
||||
#define DDL_SDIOC_ENABLE (DDL_ON)
|
||||
#define DDL_SPI_ENABLE (DDL_ON)
|
||||
#define DDL_SRAM_ENABLE (DDL_ON)
|
||||
#define DDL_SWDT_ENABLE (DDL_ON)
|
||||
#define DDL_TIMER0_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER4_CNT_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER4_EMB_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER4_OCO_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER4_PWM_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER4_SEVT_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER6_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMERA_ENABLE (DDL_OFF)
|
||||
#define DDL_TRNG_ENABLE (DDL_OFF)
|
||||
#define DDL_USART_ENABLE (DDL_ON)
|
||||
#define DDL_USBFS_ENABLE (DDL_OFF)
|
||||
#define DDL_WDT_ENABLE (DDL_OFF)
|
||||
|
||||
|
||||
/*! Midware module on-off define */
|
||||
#define MW_ON (1u)
|
||||
#define MW_OFF (0u)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief This is the list of Midware modules to use
|
||||
** Select the modules you need to use to MW_ON.
|
||||
******************************************************************************/
|
||||
#define MW_FS_ENABLE (MW_OFF)
|
||||
#define MW_SD_CARD_ENABLE (MW_OFF)
|
||||
#define MW_W25QXX_ENABLE (MW_OFF)
|
||||
#define MW_WM8731_ENABLE (MW_OFF)
|
||||
|
||||
/* BSP on-off define */
|
||||
#define BSP_ON (1u)
|
||||
#define BSP_OFF (0u)
|
||||
|
||||
/**
|
||||
* @brief The following is a list of currently supported BSP boards.
|
||||
*/
|
||||
#define BSP_EV_HC32F460_LQFP100_V1 (1u)
|
||||
#define BSP_EV_HC32F460_LQFP100_V2 (2u)
|
||||
|
||||
/**
|
||||
* @brief The macro BSP_EV_HC32F460 is used to specify the BSP board currently
|
||||
* in use.
|
||||
* The value should be set to one of the list of currently supported BSP boards.
|
||||
* @note If there is no supported BSP board or the BSP function is not used,
|
||||
* the value needs to be set to BSP_EV_HC32F460.
|
||||
*/
|
||||
#define BSP_EV_HC32F460 (BSP_EV_HC32F460_LQFP100_V2)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
//@} // DdlConfigGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DDL_CONFIG_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,24 @@
|
||||
#ifndef __MAIN__H
|
||||
#define __MAIN__H
|
||||
#include "bsp.h"
|
||||
|
||||
|
||||
#define USE_FILE_SYSTEM 1
|
||||
#define SDCARD_BLOCK_MAX (10000)
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint16_t Acc[3];
|
||||
uint16_t SensorValue[4];
|
||||
}SendData_t, *SendData;
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint16_t ADValue[4];
|
||||
uint16_t Index;
|
||||
}SaveData_t, *SaveData;
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,126 @@
|
||||
#include "ADS1231.h"
|
||||
|
||||
extern float Temperature;
|
||||
|
||||
|
||||
void ADS1231_Open(void)
|
||||
{
|
||||
PDWN1_SET();
|
||||
PDWN2_SET();
|
||||
PDWN3_SET();
|
||||
PDWN4_SET();
|
||||
}
|
||||
|
||||
void ADS1231_HighSpeedSet(void)
|
||||
{
|
||||
SPEED1_SET();
|
||||
SPEED2_SET();
|
||||
SPEED3_SET();
|
||||
SPEED4_SET();
|
||||
}
|
||||
|
||||
void ADS1231_LowSpeedSet(void)
|
||||
{
|
||||
SPEED1_RESET();
|
||||
SPEED2_RESET();
|
||||
SPEED3_RESET();
|
||||
SPEED4_RESET();
|
||||
}
|
||||
|
||||
uint32_t GpioAGetDout(en_pin_t enPin)
|
||||
{
|
||||
return *(uint32_t *)((uint32_t)(&M4_PORT->PIDRA)) & (enPin);
|
||||
}
|
||||
|
||||
uint32_t GpioBGetDout(en_pin_t enPin)
|
||||
{
|
||||
return *(uint32_t *)((uint32_t)(&M4_PORT->PIDRB)) & (enPin);
|
||||
}
|
||||
|
||||
bool ADS1231_Read(uint32_t *r_data, uint8_t channel) {
|
||||
uint8_t i;
|
||||
uint32_t data = 0;
|
||||
|
||||
switch(channel) {
|
||||
case 0:
|
||||
if(GpioAGetDout(DRDY_DOUT1_PIN) != 0)
|
||||
return false;
|
||||
|
||||
for(i = 0; i < 24; i++) {
|
||||
SCLK1_SET();
|
||||
data <<= 0x01;
|
||||
__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
|
||||
SCLK1_RESET();
|
||||
|
||||
if(GpioAGetDout(DRDY_DOUT1_PIN) != 0)
|
||||
data |= 0x01;
|
||||
}
|
||||
SCLK1_SET();
|
||||
__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
|
||||
SCLK1_RESET();
|
||||
break;
|
||||
case 1:
|
||||
if(GpioAGetDout(DRDY_DOUT2_PIN) != 0)
|
||||
return false;
|
||||
|
||||
for(i = 0; i < 24; i++) {
|
||||
SCLK2_SET();
|
||||
data <<= 0x01;
|
||||
__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
|
||||
SCLK2_RESET();
|
||||
__NOP(); __NOP();
|
||||
if(GpioAGetDout(DRDY_DOUT2_PIN) != 0)
|
||||
data |= 0x01;
|
||||
}
|
||||
SCLK2_SET();
|
||||
__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
|
||||
SCLK2_RESET();
|
||||
break;
|
||||
case 2:
|
||||
if(GpioBGetDout(DRDY_DOUT3_PIN) != 0)
|
||||
return false;
|
||||
|
||||
for(i = 0; i < 24; i++) {
|
||||
SCLK3_SET();
|
||||
data <<= 0x01;
|
||||
__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
|
||||
SCLK3_RESET();
|
||||
if(GpioBGetDout(DRDY_DOUT3_PIN) != 0 )
|
||||
data |= 0x01;
|
||||
}
|
||||
SCLK3_SET();
|
||||
__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
|
||||
SCLK3_RESET();
|
||||
break;
|
||||
case 3:
|
||||
if(GpioBGetDout(DRDY_DOUT4_PIN) != 0 )
|
||||
return false;
|
||||
|
||||
for(i = 0; i < 24; i++) {
|
||||
SCLK4_SET();
|
||||
data <<= 0x01;
|
||||
__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
|
||||
SCLK4_RESET();
|
||||
if(GpioBGetDout(DRDY_DOUT4_PIN) != 0 )
|
||||
data |= 0x01;
|
||||
}
|
||||
SCLK4_SET();
|
||||
__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
|
||||
SCLK4_RESET();
|
||||
break;
|
||||
default:
|
||||
return false;
|
||||
|
||||
}
|
||||
|
||||
if(data <= 0x00ffffff) {
|
||||
if(data > 0x007fffff)
|
||||
*r_data = data|0xff000000;
|
||||
else
|
||||
*r_data = data;
|
||||
}
|
||||
else
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
@@ -0,0 +1,87 @@
|
||||
#include "encryption.h"
|
||||
|
||||
//从机加密表
|
||||
const unsigned char EPT_Table[32][6] = {
|
||||
{1, 6, 4, 2, 3, 5}, {2, 4, 6, 3, 5, 1}, {3, 5, 6, 2, 1, 4}, {5, 3, 2, 1, 4, 6},
|
||||
{4, 2, 3, 1, 5, 6}, {6, 3, 5, 1, 4, 2}, {3, 5, 2, 6, 4, 1}, {2, 5, 4, 3, 1, 6},
|
||||
{2, 4, 1, 5, 3, 6}, {4, 6, 1, 3, 2, 5}, {4, 2, 1, 5, 6, 3}, {3, 2, 6, 5, 1, 4},
|
||||
{2, 6, 5, 1, 4, 3}, {6, 4, 3, 1, 2, 5}, {1, 6, 3, 2, 4, 5}, {5, 3, 4, 6, 2, 1},
|
||||
{5, 3, 1, 2, 6, 4}, {1, 4, 2, 6, 5, 3}, {3, 5, 2, 1, 4, 6}, {6, 1, 4, 2, 3, 5},
|
||||
{4, 1, 2, 5, 3, 6}, {4, 2, 6, 3, 5, 1}, {2, 6, 1, 4, 3, 5}, {4, 3, 1, 5, 6, 2},
|
||||
{5, 1, 2, 4, 6, 3}, {6, 5, 1, 3, 4, 2}, {2, 1, 6, 3, 5, 4}, {1, 5, 6, 3, 4, 2},
|
||||
{3, 6, 5, 4, 2, 1}, {1, 2, 6, 3, 5, 4}, {4, 6, 5, 3, 2, 1}, {5, 3, 4, 2, 6, 1}
|
||||
};
|
||||
|
||||
//从机解密表：
|
||||
const unsigned char DPT_Table[32][5] ={
|
||||
{1, 4, 2, 3, 5}, {2, 4, 3, 5, 1}, {3, 5, 2, 1, 4}, {5, 3, 2, 1, 4},
|
||||
{4, 2, 3, 1, 5}, {3, 5, 1, 4, 2}, {3, 5, 2, 4, 1}, {2, 5, 4, 3, 1},
|
||||
{2, 4, 1, 5, 3}, {4, 1, 3, 2, 5}, {4, 2, 1, 5, 3}, {3, 2, 5, 1, 4},
|
||||
{2, 5, 1, 4, 3}, {4, 3, 1, 2, 5}, {1, 3, 2, 4, 5}, {5, 3, 4, 2, 1},
|
||||
{5, 3, 1, 2, 4}, {1, 4, 2, 5, 3}, {3, 2, 1, 4, 5}, {1, 4, 5, 2, 3},
|
||||
{4, 1, 2, 5, 3}, {4, 2, 3, 5, 1}, {2, 1, 4, 3, 5}, {4, 3, 1, 5, 2},
|
||||
{5, 1, 2, 4, 3}, {5, 1, 3, 4, 2}, {2, 1, 3, 5, 4}, {1, 5, 3, 4, 2},
|
||||
{3, 5, 4, 2, 1}, {1, 2, 3, 5, 4}, {4, 5, 3, 2, 1}, {5, 3, 4, 2, 1}
|
||||
};
|
||||
|
||||
//数据位加密表：
|
||||
const unsigned char EPT_D[32] = {
|
||||
0x23, 0x4c, 0x92, 0x38, 0x52, 0xa4, 0x9a, 0x61,
|
||||
0x86, 0xc8, 0x70, 0x16, 0x32, 0x58, 0x62, 0x83,
|
||||
0xa5, 0x16, 0x1c, 0x49, 0x48, 0xc1, 0x8c, 0x91,
|
||||
0xd0, 0x2c, 0x49, 0x42, 0xc1, 0x8c, 0x98, 0xd0
|
||||
};
|
||||
|
||||
/****************************************************************/
|
||||
/* 加密函数 */
|
||||
/* */
|
||||
/*函数入口: *data,未加密的普通协议数据 */
|
||||
/* */
|
||||
/*函数出口: *EPT_data，生成的加密协议 */
|
||||
/****************************************************************/
|
||||
void Encrypt_Code(unsigned char *data, unsigned char *EPT_data) {
|
||||
unsigned char Edata[6];
|
||||
unsigned char i = 0;
|
||||
unsigned char check;
|
||||
unsigned char ept_byte;
|
||||
|
||||
check = (data[0]+data[1]+data[2]+data[3]+data[4]+data[5]) % 0xff;
|
||||
ept_byte = check % 32;
|
||||
|
||||
for (i = 0; i < 6; i++) {
|
||||
Edata[i] = ((~(data[i] & EPT_D[ept_byte])) & EPT_D[ept_byte]) | (data[i] & (~EPT_D[ept_byte]));
|
||||
}
|
||||
|
||||
for (i = 0; i < 6; i++) {
|
||||
EPT_data[i] = Edata[EPT_Table[ept_byte][i]-1];
|
||||
}
|
||||
|
||||
EPT_data[6] = ((~(check & 0xaa)) & 0xaa) | (check & 0x55);
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
/* 解密函数 */
|
||||
/* */
|
||||
/*函数入口： *EPT_data，需要解密的加密协议 */
|
||||
/* */
|
||||
/*函数出口： *DPT_data，生成的普通协议 */
|
||||
/****************************************************************/
|
||||
void Decrypt_Code(unsigned char *EPT_data,unsigned char *DPT_data) {
|
||||
unsigned char data[5];
|
||||
unsigned char i = 0;
|
||||
unsigned char check;
|
||||
unsigned char ept_byte;
|
||||
|
||||
check = ((~(EPT_data[5]&0xaa))&0xaa)|(EPT_data[5]&0x55);
|
||||
ept_byte = check % 32;
|
||||
|
||||
for(i=0;i<5;i++) {
|
||||
data[i] = ((~(EPT_data[i]&EPT_D[ept_byte]))&EPT_D[ept_byte])|(EPT_data[i]&(~EPT_D[ept_byte]));
|
||||
}
|
||||
for(i=0;i<5;i++) {
|
||||
DPT_data[DPT_Table[ept_byte][i]-1] = data[i];
|
||||
}
|
||||
DPT_data[5] = check;
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,96 @@
|
||||
#include <stdlib.h>
|
||||
#include <math.h>
|
||||
|
||||
#include "main.h"
|
||||
#include "encryption.h"
|
||||
#include "Debug.h"
|
||||
|
||||
|
||||
#define MAIN_DBG_LOG(...) DBG_LOG(__VA_ARGS__)
|
||||
#define MAIN_DBG_ARRAY(ARRAY, SIZE) DBG_ARRAY(ARRAY,SIZE)
|
||||
|
||||
uint8_t TestData[16 * 512];
|
||||
|
||||
|
||||
|
||||
|
||||
void HexToAscii(uint8_t *HexData, char *ASCData, uint8_t sLen)
|
||||
{
|
||||
uint8_t temp;
|
||||
|
||||
for(int i = 0; i < sLen; i++) {
|
||||
temp = (HexData[i] >> 4) & 0x0f;
|
||||
if(temp < 10)
|
||||
temp += '0';
|
||||
else
|
||||
temp = (temp - 10) + 'A';
|
||||
|
||||
ASCData[i * 2] = temp;
|
||||
|
||||
temp = HexData[i] & 0x0f;
|
||||
if(temp < 10)
|
||||
temp += '0';
|
||||
else
|
||||
temp = (temp - 10) + 'A';
|
||||
|
||||
ASCData[i * 2 + 1] = temp;
|
||||
}
|
||||
ASCData[sLen * 2] = '\r';
|
||||
ASCData[sLen * 2 + 1] = '\n';
|
||||
ASCData[sLen * 2 + 2] = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
void ADC_DMA_CallBack(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
BSP_Init();
|
||||
DBG_LOG("**********************************************\r\n");
|
||||
DBG_LOG("* Ver 1.0 2024-01-15 *\r\n");
|
||||
DBG_LOG("**********************************************\r\n");
|
||||
while(1) {
|
||||
DebugLoopHandler();
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************************
|
||||
* 函数名称: SysTick_IrqHandler
|
||||
* 功能描述: 系统滴答中断
|
||||
* 参 数: 无
|
||||
* 返 回 值: 无
|
||||
*****************************************************************************************/
|
||||
void SysTick_IrqHandler(void)
|
||||
{
|
||||
SysTick_IncTick();
|
||||
Dbg1msRoutine();
|
||||
}
|
||||
|
||||
/*****************************************************************************************
|
||||
* 函数名称: DBG_RxPinIntCallBack
|
||||
* 功能描述: DBG接收中断回调函数
|
||||
* 参 数: 无
|
||||
* 返 回 值: 无
|
||||
*****************************************************************************************/
|
||||
void DBG_RxPinIntCallBack(void)
|
||||
{
|
||||
PORT_Toggle(LED_Blue_PORT, LED_Blue_PIN);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void RtcPeriod_IrqCallback(void)
|
||||
{
|
||||
PORT_Toggle(LED_Green_PORT, LED_Green_PIN);
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user